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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_2_V
`define SKY130_FD_SC_MS__A41OI_2_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_2 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:00:11 03/29/2015
// Design Name:
// Module Name: decoderparam
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decoderparam
# (parameter WIDTH = 4)
( output reg [2**WIDTH-1 : 0] code,
input [WIDTH-1 : 0] a,
input clken
);
localparam STAGE = WIDTH;
integer i, s, r;
reg [(STAGE+1)*(2**STAGE):0] p;
always @(a, p, clken) begin
p[STAGE*(2**STAGE)] <= clken;
for(s=STAGE; s > 0; s = s - 1) begin
for (r = 0; r < 2**(STAGE - s); r = r + 1) begin
p[(s-1)*(2**STAGE) + 2*r] <= !a[s-1] && p[s*(2**STAGE)+r];
p[(s-1)*(2**STAGE) + 2*r+1] <= a[s-1] && p[s*(2**STAGE)+r];
end
end
for (i=0; i < 2**STAGE; i = i + 1) begin
code[i] <= p[i];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4B_BEHAVIORAL_PP_V |
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// 4. For ECC ON case inserts error on LSB bit
// of data from DRAM to FPGA.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "TRUE";
parameter BEGIN_ADDRESS = 32'h00000000;
parameter END_ADDRESS = 32'h00000fff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 1;
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
parameter DM_WIDTH = 2;
// # of DM (data mask)
parameter DQ_WIDTH = 16;
// # of DQ (data)
parameter DQS_WIDTH = 2;
parameter DQS_CNT_WIDTH = 1;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
// # of DQ per DQS
parameter ECC = "OFF";
parameter RANKS = 1;
// # of Ranks.
parameter ODT_WIDTH = 1;
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8";
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 4999;
// Input Clock Period
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "SIM_INIT_CAL_FULL" - Complete
// memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter TCQ = 100;
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0;
// IODELAYCTRL reference clock frequency
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3333;
// memory tCK paramter.
// # = Clock Period in pS.
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
parameter C_S_AXI_ID_WIDTH = 4;
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_ADDR_WIDTH = 32;
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32;
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0;
// Indicates whether to instatiate upsizer
// Range: 0, 1
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DRAM_TYPE = "DDR2";
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00;
// Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00;
// Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00;
// Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00;
// Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00;
// Delay for data signal during Read operation
localparam MEMORY_WIDTH = 16;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam ECC_TEST = "OFF" ;
localparam ERR_INSERT = (ECC_TEST == "ON") ? "OFF" : ECC ;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam RESET_PERIOD = 200000; //in pSec
localparam real SYSCLK_PERIOD = tCK;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
reg sys_clk_i;
reg clk_ref_i;
wire ddr2_reset_n;
wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
wire [ROW_WIDTH-1:0] ddr2_addr_fpga;
wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
wire ddr2_ras_n_fpga;
wire ddr2_cas_n_fpga;
wire ddr2_we_n_fpga;
wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_n_fpga;
wire init_calib_complete;
wire tg_compare_error;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_fpga;
wire [DM_WIDTH-1:0] ddr2_dm_fpga;
wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram_tmp;
reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
reg [ODT_WIDTH-1:0] ddr2_odt_sdram_tmp;
wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
reg [ROW_WIDTH-1:0] ddr2_addr_sdram;
reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
reg ddr2_ras_n_sdram;
reg ddr2_cas_n_sdram;
reg ddr2_we_n_sdram;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram;
wire [ODT_WIDTH-1:0] ddr2_odt_sdram;
reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
wire [DM_WIDTH-1:0] ddr2_dm_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_n_sdram;
//**************************************************************************//
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
always @( * ) begin
ddr2_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_p_fpga;
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
ddr2_addr_sdram <= #(TPROP_PCB_CTRL) ddr2_addr_fpga;
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
end
always @( * )
ddr2_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
assign ddr2_cs_n_sdram = ddr2_cs_n_sdram_tmp;
always @( * )
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
always @( * )
ddr2_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
assign ddr2_odt_sdram = ddr2_odt_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr2_dq_fpga[dqwd]),
.B (ddr2_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
// For ECC ON case error is inserted on LSB bit from DRAM to FPGA
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT (ERR_INSERT)
)
u_delay_dq_0
(
.A (ddr2_dq_fpga[0]),
.B (ddr2_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr2_dqs_p_fpga[dqswd]),
.B (ddr2_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr2_dqs_n_fpga[dqswd]),
.B (ddr2_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
endgenerate
//===========================================================================
// FPGA Memory Controller
//===========================================================================
example_top #
(
.SIMULATION (SIMULATION),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC_TEST (ECC_TEST),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.BURST_MODE (BURST_MODE),
.TCQ (TCQ),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.DEBUG_PORT (DEBUG_PORT)
// .RST_ACT_LOW (RST_ACT_LOW)
)
u_ip_top
(
.ddr2_dq (ddr2_dq_fpga),
.ddr2_dqs_n (ddr2_dqs_n_fpga),
.ddr2_dqs_p (ddr2_dqs_p_fpga),
.ddr2_addr (ddr2_addr_fpga),
.ddr2_ba (ddr2_ba_fpga),
.ddr2_ras_n (ddr2_ras_n_fpga),
.ddr2_cas_n (ddr2_cas_n_fpga),
.ddr2_we_n (ddr2_we_n_fpga),
.ddr2_ck_p (ddr2_ck_p_fpga),
.ddr2_ck_n (ddr2_ck_n_fpga),
.ddr2_cke (ddr2_cke_fpga),
.ddr2_cs_n (ddr2_cs_n_fpga),
.ddr2_dm (ddr2_dm_fpga),
.ddr2_odt (ddr2_odt_fpga),
.sys_clk_i (sys_clk_i),
.device_temp_i (12'b0),
.init_calib_complete (init_calib_complete),
.tg_compare_error (tg_compare_error),
.sys_rst (sys_rst)
);
//**************************************************************************//
// Memory Models instantiations
//**************************************************************************//
genvar r,i;
generate
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
if(DQ_WIDTH/16) begin: mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs (ddr2_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq (ddr2_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr2_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs ({ddr2_dm_sdram[DM_WIDTH-1],ddr2_dm_sdram[DM_WIDTH-1]}),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq ({ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr2_dqs_p_sdram[DQS_WIDTH-1],
ddr2_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr2_dqs_n_sdram[DQS_WIDTH-1],
ddr2_dqs_n_sdram[DQS_WIDTH-1]}),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
// Status reporting logic exists both in simulation test bench (sim_tb_top)
// and sim.do file for ModelSim. Any update in simulation run time or time out
// in this file need to be updated in sim.do file as well.
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (init_calib_complete);
$display("Calibration Done");
#50000000.0;
if (!tg_compare_error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")
#2500000000.0;
else
#1000000000.0;
if (!init_calib_complete) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
/* SRAM Test Bench
*
* Case I:
* Tests the FIFO by writing the FF byte and reading them back.
*
* Created By David Tran
* Version 0.1.0.0
* Last Modified:05-01-2014
*/
`include "sram_fifo.v"
module sram_fifo_tb (
readMode, // Specifies if we want to read to the FIFO
writeMode, // Specifies if we want to write to the FIFO
inputPacket // The input packet
);
parameter bits = 8;
output readMode, writeMode;
reg readMode, writeMode;
reg readModeQ;
output [bits-1:0] inputPacket;
reg [bits-1:0] inputPacket;
reg clk, rst;
wire [bits-1:0] outputPacket;
SRAM_fifo SRAM (readMode, writeMode, inputPacket, outputPacket, clk, rst);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
forever begin
@(posedge clk); begin // Only output on positive edge
$display("time=%04d RW=%b%b I=%h O=%h clk=%b", $time,
readModeQ, writeMode, inputPacket, outputPacket, clk);
readModeQ = readMode;
end
end
end
initial
begin
// Test Case I: Write to capacity and empty
rst = 1;
readMode = 0;
readModeQ = 0;
writeMode = 0;
#5 rst = 0;
#5 inputPacket = {bits{1'b1}}; writeMode = 1;
#80 writeMode = 0; readMode = 1; inputPacket = {bits{1'b0}};
#90 readMode = 0;
if (outputPacket === {bits{1'b1}}) begin
$display("Pass");
end else begin
$display("Fail");
end
$finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:43:26 02/26/2016
// Design Name: signExt
// Module Name: C:/Users/Ranolazine/Desktop/Lab/lab4/test_signExt.v
// Project Name: lab4
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: signExt
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_signExt;
// Inputs
reg [15:0] inst;
// Outputs
wire [31:0] data;
// Instantiate the Unit Under Test (UUT)
signExt uut (
.inst(inst),
.data(data)
);
initial begin
// Initialize Inputs
inst = 0;
// Wait 100 ns for global reset to finish
#100;
inst = 16'b0000000011111010;
#100;
inst = 16'b1111111111111111;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221AI_SYMBOL_V
`define SKY130_FD_SC_LS__O221AI_SYMBOL_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o221ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221AI_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Analog Auxiliary SYSMON Input Output Buffer
// /___/ /\ Filename : IOBUF_ANALOG.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IOBUF_ANALOG #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer DRIVE = 12,
parameter IBUF_LOW_PWR = "TRUE",
parameter IOSTANDARD = "DEFAULT",
parameter SLEW = "SLOW"
)(
output O,
inout IO,
input I,
input T
);
// define constants
localparam MODULE_NAME = "IOBUF_ANALOG";
// Parameter encodings and registers
localparam IBUF_LOW_PWR_FALSE = 1;
localparam IBUF_LOW_PWR_TRUE = 0;
localparam IOSTANDARD_DEFAULT = 0;
localparam SLEW_FAST = 1;
localparam SLEW_SLOW = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "IOBUF_ANALOG_dr.v"
`else
localparam [4:0] DRIVE_REG = DRIVE;
localparam [40:1] IBUF_LOW_PWR_REG = IBUF_LOW_PWR;
localparam [56:1] IOSTANDARD_REG = IOSTANDARD;
localparam [32:1] SLEW_REG = SLEW;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire I_in;
wire T_in;
assign I_in = (I === 1'bz) || I; // rv 1
assign T_in = (T === 1'bz) || T; // rv 1
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((DRIVE_REG < 2) || (DRIVE_REG > 24))) begin
$display("Error: [Unisim %s-101] DRIVE attribute is set to %d. Legal values for this attribute are 2 to 24. Instance: %m", MODULE_NAME, DRIVE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IBUF_LOW_PWR_REG != "TRUE") &&
(IBUF_LOW_PWR_REG != "FALSE"))) begin
$display("Error: [Unisim %s-104] IBUF_LOW_PWR attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, IBUF_LOW_PWR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SLEW_REG != "SLOW") &&
(SLEW_REG != "FAST"))) begin
$display("Error: [Unisim %s-109] SLEW attribute is set to %s. Legal values for this attribute are SLOW or FAST. Instance: %m", MODULE_NAME, SLEW_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
assign O = IO;
assign IO = ~T_in ? I_in : 1'bz;
specify
(I => IO) = (0:0:0, 0:0:0);
(IO => O) = (0:0:0, 0:0:0);
(T => IO) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
// Date : Sat Jan 21 14:32:47 2017
// Host : natu-OMEN-by-HP-Laptop running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -force -mode funcsim
// /media/natu/data/proj/myproj/NPU/fpga_implement/npu8/npu8.srcs/sources_1/ip/mult16_16/mult16_16_sim_netlist.v
// Design : mult16_16
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xcku035-fbva676-3-e
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "mult16_16,mult_gen_v12_0_12,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "mult_gen_v12_0_12,Vivado 2016.4" *)
(* NotValidForBitStream *)
module mult16_16
(CLK,
A,
B,
P);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk_intf CLK" *) input CLK;
(* x_interface_info = "xilinx.com:signal:data:1.0 a_intf DATA" *) input [15:0]A;
(* x_interface_info = "xilinx.com:signal:data:1.0 b_intf DATA" *) input [15:0]B;
(* x_interface_info = "xilinx.com:signal:data:1.0 p_intf DATA" *) output [7:0]P;
wire [15:0]A;
wire [15:0]B;
wire CLK;
wire [7:0]P;
wire [47:0]NLW_U0_PCASC_UNCONNECTED;
wire [1:0]NLW_U0_ZERO_DETECT_UNCONNECTED;
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "24" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mult16_16_mult_gen_v12_0_12 U0
(.A(A),
.B(B),
.CE(1'b1),
.CLK(CLK),
.P(P),
.PCASC(NLW_U0_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_U0_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
(* C_A_TYPE = "1" *) (* C_A_WIDTH = "16" *) (* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *) (* C_B_WIDTH = "16" *) (* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *) (* C_HAS_CE = "0" *) (* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *) (* C_LATENCY = "4" *) (* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *) (* C_OPTIMIZE_GOAL = "1" *) (* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "24" *) (* C_ROUND_OUTPUT = "0" *) (* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *) (* C_XDEVICEFAMILY = "kintexu" *) (* ORIG_REF_NAME = "mult_gen_v12_0_12" *)
(* downgradeipidentifiedwarnings = "yes" *)
module mult16_16_mult_gen_v12_0_12
(CLK,
A,
B,
CE,
SCLR,
ZERO_DETECT,
P,
PCASC);
input CLK;
input [15:0]A;
input [15:0]B;
input CE;
input SCLR;
output [1:0]ZERO_DETECT;
output [7:0]P;
output [47:0]PCASC;
wire \<const0> ;
wire [15:0]A;
wire [15:0]B;
wire CLK;
wire [7:0]P;
wire [47:0]NLW_i_mult_PCASC_UNCONNECTED;
wire [1:0]NLW_i_mult_ZERO_DETECT_UNCONNECTED;
assign PCASC[47] = \<const0> ;
assign PCASC[46] = \<const0> ;
assign PCASC[45] = \<const0> ;
assign PCASC[44] = \<const0> ;
assign PCASC[43] = \<const0> ;
assign PCASC[42] = \<const0> ;
assign PCASC[41] = \<const0> ;
assign PCASC[40] = \<const0> ;
assign PCASC[39] = \<const0> ;
assign PCASC[38] = \<const0> ;
assign PCASC[37] = \<const0> ;
assign PCASC[36] = \<const0> ;
assign PCASC[35] = \<const0> ;
assign PCASC[34] = \<const0> ;
assign PCASC[33] = \<const0> ;
assign PCASC[32] = \<const0> ;
assign PCASC[31] = \<const0> ;
assign PCASC[30] = \<const0> ;
assign PCASC[29] = \<const0> ;
assign PCASC[28] = \<const0> ;
assign PCASC[27] = \<const0> ;
assign PCASC[26] = \<const0> ;
assign PCASC[25] = \<const0> ;
assign PCASC[24] = \<const0> ;
assign PCASC[23] = \<const0> ;
assign PCASC[22] = \<const0> ;
assign PCASC[21] = \<const0> ;
assign PCASC[20] = \<const0> ;
assign PCASC[19] = \<const0> ;
assign PCASC[18] = \<const0> ;
assign PCASC[17] = \<const0> ;
assign PCASC[16] = \<const0> ;
assign PCASC[15] = \<const0> ;
assign PCASC[14] = \<const0> ;
assign PCASC[13] = \<const0> ;
assign PCASC[12] = \<const0> ;
assign PCASC[11] = \<const0> ;
assign PCASC[10] = \<const0> ;
assign PCASC[9] = \<const0> ;
assign PCASC[8] = \<const0> ;
assign PCASC[7] = \<const0> ;
assign PCASC[6] = \<const0> ;
assign PCASC[5] = \<const0> ;
assign PCASC[4] = \<const0> ;
assign PCASC[3] = \<const0> ;
assign PCASC[2] = \<const0> ;
assign PCASC[1] = \<const0> ;
assign PCASC[0] = \<const0> ;
assign ZERO_DETECT[1] = \<const0> ;
assign ZERO_DETECT[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_A_TYPE = "1" *)
(* C_A_WIDTH = "16" *)
(* C_B_TYPE = "1" *)
(* C_B_VALUE = "10000001" *)
(* C_B_WIDTH = "16" *)
(* C_CCM_IMP = "0" *)
(* C_CE_OVERRIDES_SCLR = "0" *)
(* C_HAS_CE = "0" *)
(* C_HAS_SCLR = "0" *)
(* C_HAS_ZERO_DETECT = "0" *)
(* C_LATENCY = "4" *)
(* C_MODEL_TYPE = "0" *)
(* C_MULT_TYPE = "0" *)
(* C_OUT_HIGH = "31" *)
(* C_OUT_LOW = "24" *)
(* C_ROUND_OUTPUT = "0" *)
(* C_ROUND_PT = "0" *)
(* C_VERBOSITY = "0" *)
(* C_XDEVICEFAMILY = "kintexu" *)
(* c_optimize_goal = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
mult16_16_mult_gen_v12_0_12_viv i_mult
(.A(A),
.B(B),
.CE(1'b0),
.CLK(CLK),
.P(P),
.PCASC(NLW_i_mult_PCASC_UNCONNECTED[47:0]),
.SCLR(1'b0),
.ZERO_DETECT(NLW_i_mult_ZERO_DETECT_UNCONNECTED[1:0]));
endmodule
`pragma protect begin_protected
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`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xc0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xc0(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O22AI_M_V
`define SKY130_FD_SC_LP__O22AI_M_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog wrapper for o22ai with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o22ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_m (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o22ai_m (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o22ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O22AI_M_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2BB2OI_FUNCTIONAL_V
`define SKY130_FD_SC_HS__A2BB2OI_FUNCTIONAL_V
/**
* a2bb2oi: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input NOR.
*
* Y = !((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a2bb2oi (
VPWR,
VGND,
Y ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Local signals
wire B2 and0_out ;
wire B2 nor0_out ;
wire nor1_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
nor nor1 (nor1_out_Y , nor0_out, and0_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor1_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2BB2OI_FUNCTIONAL_V |
//--------------------------------------------------------------------------------
// Project : SWITCH
// File : pcie_top.v
// Version : 0.1
// Author : Vipin.K
//
// Description: Instantiates the Xilinx PCIe endpoint and the PCIe interface logic
//
//--------------------------------------------------------------------------------
module pcie_top # (
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width
parameter NUM_PCIE_STRM = 4,
parameter RECONFIG_ENABLE = 1,
parameter RCM_ENABLE = 1
) (
output [3:0] pci_exp_txp,
output [3:0] pci_exp_txn,
input [3:0] pci_exp_rxp,
input [3:0] pci_exp_rxn,
input sys_clk_p,
input sys_clk_n,
input sys_reset_n,
input i_ddr_clk,
output o_ddr_wr_req,
output [255:0] o_ddr_wr_data,
output [31:0] o_ddr_wr_be,
input i_ddr_wr_ack,
output [26:0] o_ddr_addr,
output ddr_rd_req_o,
input ddr_rd_ack_i,
input ddr_rd_valid_i,
input [255:0] ddr_rd_data_i,
output user_clk_o,
output pcie_clk_o,
output user_reset_o,
output [31:0] user_data_o,
output [19:0] user_addr_o,
output user_wr_req_o,
input [31:0] user_data_i,
input user_rd_ack_i,
output user_rd_req_o,
input user_intr_req_i,
output user_intr_ack_o,
//user stream interface
output user_str1_data_valid_o,
input user_str1_ack_i,
output [63:0] user_str1_data_o,
input user_str1_data_valid_i,
output user_str1_ack_o,
input [63:0] user_str1_data_i,
output user_str2_data_valid_o,
input user_str2_ack_i,
output [63:0] user_str2_data_o,
input user_str2_data_valid_i,
output user_str2_ack_o,
input [63:0] user_str2_data_i,
output user_str3_data_valid_o,
input user_str3_ack_i,
output [63:0] user_str3_data_o,
input user_str3_data_valid_i,
output user_str3_ack_o,
input [63:0] user_str3_data_i,
output user_str4_data_valid_o,
input user_str4_ack_i,
output [63:0] user_str4_data_o,
input user_str4_data_valid_i,
output user_str4_ack_o,
input [63:0] user_str4_data_i,
//To user ddr stream controllers
output [31:0] o_ddr_user1_str_addr,
output [31:0] o_ddr_user1_str_len,
output o_ddr_user1_str_en,
input i_ddr_user1_str_done,
output o_ddr_user1_str_done_ack,
output o_user1_ddr_str_en,
input i_user1_ddr_str_done,
output o_user1_ddr_str_done_ack,
output [31:0] o_user1_ddr_str_addr,
output [31:0] o_user1_ddr_str_len,
output [31:0] o_ddr_user2_str_addr,
output [31:0] o_ddr_user2_str_len,
output o_ddr_user2_str_en,
input i_ddr_user2_str_done,
output o_ddr_user2_str_done_ack,
output o_user2_ddr_str_en,
input i_user2_ddr_str_done,
output o_user2_ddr_str_done_ack,
output [31:0] o_user2_ddr_str_addr,
output [31:0] o_user2_ddr_str_len,
output [31:0] o_ddr_user3_str_addr,
output [31:0] o_ddr_user3_str_len,
output o_ddr_user3_str_en,
input i_ddr_user3_str_done,
output o_ddr_user3_str_done_ack,
output o_user3_ddr_str_en,
input i_user3_ddr_str_done,
output o_user3_ddr_str_done_ack,
output [31:0] o_user3_ddr_str_addr,
output [31:0] o_user3_ddr_str_len,
output [31:0] o_ddr_user4_str_addr,
output [31:0] o_ddr_user4_str_len,
output o_ddr_user4_str_en,
input i_ddr_user4_str_done,
output o_ddr_user4_str_done_ack,
output o_user4_ddr_str_en,
input i_user4_ddr_str_done,
output o_user4_ddr_str_done_ack,
output [31:0] o_user4_ddr_str_addr,
output [31:0] o_user4_ddr_str_len,
output pcie_link_status,
input clk_sysmon_i,
input i_ddr_link_stat,
input i_enet_link_stat,
//ethernet
output o_enet_clk,
output o_enet_enable,
output o_enet_loopback,
output [31:0] o_enet_send_data_size,
output [31:0] o_enet_rcv_data_size,
output [31:0] o_enet_ddr_src_addr,
output [31:0] o_enet_ddr_dest_addr,
input [31:0] i_enet_rx_cnt,
input [31:0] i_enet_tx_cnt,
input i_enet_rx_done,
input i_enet_tx_done
);
localparam TCQ = 1;
reg [25:0] user_clk_heartbeat = 'h0;
wire user_clk;
wire user_reset;
wire user_lnk_up;
// Tx
wire [5:0] tx_buf_av;
wire tx_cfg_req;
wire tx_err_drop;
wire tx_cfg_gnt;
wire s_axis_tx_tready;
wire [3:0] s_axis_tx_tuser;
wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
// Rx
wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire rx_np_ok;
wire rx_np_req;
// Flow Control
wire [11:0] fc_cpld;
wire [7:0] fc_cplh;
wire [11:0] fc_npd;
wire [7:0] fc_nph;
wire [11:0] fc_pd;
wire [7:0] fc_ph;
wire [2:0] fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
wire cfg_err_cor;
wire cfg_err_ur;
wire cfg_err_ecrc;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort;
wire cfg_err_cpl_unexpect;
wire cfg_err_posted;
wire cfg_err_locked;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_err_cpl_rdy;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_di;
wire [7:0] cfg_interrupt_do;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire [4:0] cfg_pciecap_interrupt_msgnum;
wire cfg_turnoff_ok;
wire cfg_to_turnoff;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire [15:0] cfg_dcommand2;
wire [2:0] cfg_pcie_link_state;
wire [63:0] cfg_dsn;
wire [127:0] cfg_err_aer_headerlog;
wire [4:0] cfg_aer_interrupt_msgnum;
wire cfg_err_aer_headerlog_set;
wire cfg_aer_ecrc_check_en;
wire cfg_aer_ecrc_gen_en;
wire [31:0] cfg_mgmt_di;
wire [3:0] cfg_mgmt_byte_en;
wire [9:0] cfg_mgmt_dwaddr;
wire cfg_mgmt_wr_en;
wire cfg_mgmt_rd_en;
wire cfg_mgmt_wr_readonly;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
wire [2:0] pl_initial_link_width;
wire [1:0] pl_lane_reversal_mode;
wire pl_link_gen2_cap;
wire pl_link_partner_gen2_supported;
wire pl_link_upcfg_cap;
wire [5:0] pl_ltssm_state;
wire pl_received_hot_rst;
wire pl_sel_lnk_rate;
wire [1:0] pl_sel_lnk_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire sys_rst_n_c;
// Wires used for external clocking connectivity
wire PIPE_PCLK_IN;
wire PIPE_RXUSRCLK_IN;
wire [3:0] PIPE_RXOUTCLK_IN;
wire PIPE_DCLK_IN;
wire PIPE_USERCLK1_IN;
wire PIPE_USERCLK2_IN;
wire PIPE_MMCM_LOCK_IN;
wire PIPE_TXOUTCLK_OUT;
wire [3:0] PIPE_RXOUTCLK_OUT;
wire [3:0] PIPE_PCLK_SEL_OUT;
wire PIPE_GEN3_OUT;
wire PIPE_OOBCLK_IN;
localparam USER_CLK_FREQ = 3;
localparam USER_CLK2_DIV2 = "FALSE";
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ?
(USER_CLK_FREQ == 4) ? 3 :
(USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ :
USER_CLK_FREQ;
//-------------------------------------------------------
//IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_reset_n));
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n));
reg user_reset_q;
reg user_lnk_up_q;
assign pcie_link_status = user_lnk_up;
assign pcie_clk_o = user_lnk_up;
always @(posedge user_clk) begin
user_reset_q <= user_reset;
user_lnk_up_q <= user_lnk_up;
end
// Generate External Clock Module if External Clocking is selected
generate
if (PCIE_EXT_CLK == "TRUE") begin : ext_clk
//---------- PIPE Clock Module -------------------------------------------------
pcie_7x_v1_8_pipe_clock #
(
.PCIE_ASYNC_EN ( "FALSE" ), // PCIe async enable
.PCIE_TXBUF_EN ( "FALSE" ), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE ( 6'h04 ), // PCIe number of lanes
// synthesis translate_off
.PCIE_LINK_SPEED ( 2 ),
// synthesis translate_on
.PCIE_REFCLK_FREQ ( 0 ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency
.PCIE_DEBUG_MODE ( 0 )
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK ( sys_clk ),
.CLK_TXOUTCLK ( PIPE_TXOUTCLK_OUT ), // Reference clock from lane 0
.CLK_RXOUTCLK_IN ( PIPE_RXOUTCLK_OUT ),
.CLK_RST_N ( 1'b1 ),
.CLK_PCLK_SEL ( PIPE_PCLK_SEL_OUT ),
.CLK_GEN3 ( PIPE_GEN3_OUT ),
//---------- Output ------------------------------------
.CLK_PCLK ( PIPE_PCLK_IN ),
.CLK_RXUSRCLK ( PIPE_RXUSRCLK_IN ),
.CLK_RXOUTCLK_OUT ( PIPE_RXOUTCLK_IN ),
.CLK_DCLK ( PIPE_DCLK_IN ),
.CLK_OOBCLK ( PIPE_OOBCLK_IN ),
.CLK_USERCLK1 ( PIPE_USERCLK1_IN ),
.CLK_USERCLK2 ( PIPE_USERCLK2_IN ),
.CLK_MMCM_LOCK ( PIPE_MMCM_LOCK_IN )
);
end
endgenerate
pcie_7x_v1_8 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK )
) pcie_7x_v1_8_i
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
// Rx
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Clocking Interface //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_OOBCLK_IN ( PIPE_OOBCLK_IN ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
// TX
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( 1'b1 ),
// Flow Control
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
.cfg_mgmt_do ( ),
.cfg_mgmt_rd_wr_done ( ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( ),
.cfg_pmcsr_powerstate ( ),
.cfg_pmcsr_pme_status ( ),
.cfg_received_func_lvl_rst ( ),
// Management Interface
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( 1'b0 ),
.cfg_mgmt_rd_en ( 1'b0 ),
.cfg_mgmt_wr_readonly ( 1'b0 ),
// Error Reporting Interface
.cfg_err_ecrc ( 1'b0 ),
.cfg_err_ur ( 1'b0 ),
.cfg_err_cpl_timeout ( 1'b0 ),
.cfg_err_cpl_unexpect ( 1'b0 ),
.cfg_err_cpl_abort ( 1'b0 ),
.cfg_err_posted ( 1'b0 ),
.cfg_err_cor ( 1'b0 ),
.cfg_err_atomic_egress_blocked ( 1'b0 ),
.cfg_err_internal_cor ( 1'b0 ),
.cfg_err_malformed ( 1'b0 ),
.cfg_err_mc_blocked ( 1'b0 ),
.cfg_err_poisoned ( 1'b0 ),
.cfg_err_norecovery ( 1'b0 ),
.cfg_err_tlp_cpl_header ( 48'd00 ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_err_locked ( 1'b0 ),
.cfg_err_acs ( 1'b0 ),
.cfg_err_internal_uncor ( 1'b0 ),
.cfg_trn_pending ( 1'b0 ),
.cfg_pm_halt_aspm_l0s ( 1'b0 ),
.cfg_pm_halt_aspm_l1 ( 1'b0 ),
.cfg_pm_force_state_en ( 1'b0 ),
.cfg_pm_force_state ( 2'b00 ),
.cfg_dsn ( cfg_dsn ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_pm_wake ( cfg_pm_wake ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
.cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ),
.cfg_msg_received ( ),
.cfg_msg_data ( ),
.cfg_bridge_serr_en ( ),
.cfg_slot_control_electromech_il_ctl_pulse ( ),
.cfg_root_control_syserr_corr_err_en ( ),
.cfg_root_control_syserr_non_fatal_err_en ( ),
.cfg_root_control_syserr_fatal_err_en ( ),
.cfg_root_control_pme_int_en ( ),
.cfg_aer_rooterr_corr_err_reporting_en ( ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_corr_err_received ( ),
.cfg_aer_rooterr_non_fatal_err_received ( ),
.cfg_aer_rooterr_fatal_err_received ( ),
.cfg_msg_received_err_cor ( ),
.cfg_msg_received_err_non_fatal ( ),
.cfg_msg_received_err_fatal ( ),
.cfg_msg_received_pm_as_nak ( ),
.cfg_msg_received_pme_to_ack ( ),
.cfg_msg_received_assert_int_a ( ),
.cfg_msg_received_assert_int_b ( ),
.cfg_msg_received_assert_int_c ( ),
.cfg_msg_received_assert_int_d ( ),
.cfg_msg_received_deassert_int_a ( ),
.cfg_msg_received_deassert_int_b ( ),
.cfg_msg_received_deassert_int_c ( ),
.cfg_msg_received_deassert_int_d ( ),
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_phy_lnk_up ( ),
.pl_tx_pm_state ( ),
.pl_rx_pm_state ( ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_directed_change_done ( ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.pl_received_hot_rst ( pl_received_hot_rst ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.pl_transmit_hot_rst ( 1'b0 ),
.pl_downstream_deemph_source ( 1'b0 ),
//----------------------------------------------------------------------------------------------------------------//
// 6. AER Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_vc_tcvc_map ( ),
//----------------------------------------------------------------------------------------------------------------//
// 8. System (SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
.sys_clk ( sys_clk ),
.sys_rst_n ( sys_reset_n )
);
pcie_app #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.NUM_PCIE_STRM(NUM_PCIE_STRM),
.RECONFIG_ENABLE(RECONFIG_ENABLE),
.RCM_ENABLE(RCM_ENABLE)
)app (
//-------------------------------------------------------
// 1. AXI-S Interface
//-------------------------------------------------------
// Common
.pcie_core_clk( user_clk ),
.user_reset( user_reset ),
.user_lnk_up( user_lnk_up ),
// Tx
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.tx_cfg_gnt( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.rx_np_ok( rx_np_ok ),
.fc_sel( fc_sel ),
//-------------------------------------------------------
// 2. Configuration (CFG) Interface
//-------------------------------------------------------
.cfg_di( cfg_di ),
.cfg_byte_en( cfg_byte_en ),
.cfg_dwaddr( cfg_dwaddr ),
.cfg_wr_en( cfg_wr_en ),
.cfg_rd_en( cfg_rd_en ),
.cfg_err_cor( cfg_err_cor ),
.cfg_err_ur( cfg_err_ur ),
.cfg_err_ecrc( cfg_err_ecrc ),
.cfg_err_cpl_timeout( cfg_err_cpl_timeout ),
.cfg_err_cpl_abort( cfg_err_cpl_abort ),
.cfg_err_cpl_unexpect( cfg_err_cpl_unexpect ),
.cfg_err_posted( cfg_err_posted ),
.cfg_err_locked( cfg_err_locked ),
.cfg_err_tlp_cpl_header( cfg_err_tlp_cpl_header ),
.cfg_interrupt( cfg_interrupt ),
.cfg_interrupt_rdy( cfg_interrupt_rdy ),
.cfg_interrupt_assert( cfg_interrupt_assert ),
.cfg_interrupt_di( cfg_interrupt_di ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
.cfg_trn_pending( cfg_trn_pending ),
.cfg_pm_wake( cfg_pm_wake ),
.cfg_bus_number( cfg_bus_number ),
.cfg_device_number( cfg_device_number ),
.cfg_function_number( cfg_function_number ),
.cfg_dsn( cfg_dsn ),
//-------------------------------------------------------
// 3. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
.pl_directed_link_auton( pl_directed_link_auton ),
.pl_directed_link_change( pl_directed_link_change ),
.pl_directed_link_speed( pl_directed_link_speed ),
.pl_directed_link_width( pl_directed_link_width ),
.pl_upstream_prefer_deemph( pl_upstream_prefer_deemph ),
.i_ddr_clk(i_ddr_clk),
.o_ddr_wr_req(o_ddr_wr_req),
.o_ddr_wr_data(o_ddr_wr_data),
.o_ddr_wr_be(o_ddr_wr_be),
.i_ddr_wr_ack(i_ddr_wr_ack),
.o_ddr_addr(o_ddr_addr),
.ddr_rd_req_o(ddr_rd_req_o),
.ddr_rd_ack_i(ddr_rd_ack_i),
.ddr_rd_valid_i(ddr_rd_valid_i),
.ddr_rd_data_i(ddr_rd_data_i),
.user_clk_o(user_clk_o),
.user_reset_o(user_reset_o),
.user_data_o(user_data_o),
.user_addr_o(user_addr_o),
.user_wr_req_o(user_wr_req_o),
.user_data_i(user_data_i),
.user_rd_ack_i(user_rd_ack_i),
.user_rd_req_o(user_rd_req_o),
.user_intr_req_i(user_intr_req_i),
.user_intr_ack_o(user_intr_ack_o),
.user_str1_data_valid_o(user_str1_data_valid_o),
.user_str1_ack_i(user_str1_ack_i),
.user_str1_data_o(user_str1_data_o),
.user_str1_data_valid_i(user_str1_data_valid_i),
.user_str1_ack_o(user_str1_ack_o),
.user_str1_data_i(user_str1_data_i),
.user_str2_data_valid_o(user_str2_data_valid_o),
.user_str2_ack_i(user_str2_ack_i),
.user_str2_data_o(user_str2_data_o),
.user_str2_data_valid_i(user_str2_data_valid_i),
.user_str2_ack_o(user_str2_ack_o),
.user_str2_data_i(user_str2_data_i),
.user_str3_data_valid_o(user_str3_data_valid_o),
.user_str3_ack_i(user_str3_ack_i),
.user_str3_data_o(user_str3_data_o),
.user_str3_data_valid_i(user_str3_data_valid_i),
.user_str3_ack_o(user_str3_ack_o),
.user_str3_data_i(user_str3_data_i),
.user_str4_data_valid_o(user_str4_data_valid_o),
.user_str4_ack_i(user_str4_ack_i),
.user_str4_data_o(user_str4_data_o),
.user_str4_data_valid_i(user_str4_data_valid_i),
.user_str4_ack_o(user_str4_ack_o),
.user_str4_data_i(user_str4_data_i),
.o_ddr_user1_str_en(o_ddr_user1_str_en),
.i_ddr_user1_str_done(i_ddr_user1_str_done),
.o_ddr_user1_str_done_ack(o_ddr_user1_str_done_ack),
.o_ddr_user1_str_addr(o_ddr_user1_str_addr),
.o_ddr_user1_str_len(o_ddr_user1_str_len),
.o_user1_ddr_str_en(o_user1_ddr_str_en),
.i_user1_ddr_str_done(i_user1_ddr_str_done),
.o_user1_ddr_str_done_ack(o_user1_ddr_str_done_ack),
.o_user1_ddr_str_addr(o_user1_ddr_str_addr),
.o_user1_ddr_str_len(o_user1_ddr_str_len),
.o_ddr_user2_str_addr(o_ddr_user2_str_addr),
.o_ddr_user2_str_len(o_ddr_user2_str_len),
.o_ddr_user2_str_en(o_ddr_user2_str_en),
.i_ddr_user2_str_done(i_ddr_user2_str_done),
.o_ddr_user2_str_done_ack(o_ddr_user2_str_done_ack),
.o_user2_ddr_str_en(o_user2_ddr_str_en),
.i_user2_ddr_str_done(i_user2_ddr_str_done),
.o_user2_ddr_str_done_ack(o_user2_ddr_str_done_ack),
.o_user2_ddr_str_addr(o_user2_ddr_str_addr),
.o_user2_ddr_str_len(o_user2_ddr_str_len),
.o_ddr_user3_str_addr(o_ddr_user3_str_addr),
.o_ddr_user3_str_len(o_ddr_user3_str_len),
.o_ddr_user3_str_en(o_ddr_user3_str_en),
.i_ddr_user3_str_done(i_ddr_user3_str_done),
.o_ddr_user3_str_done_ack(o_ddr_user3_str_done_ack),
.o_user3_ddr_str_en(o_user3_ddr_str_en),
.i_user3_ddr_str_done(i_user3_ddr_str_done),
.o_user3_ddr_str_done_ack(o_user3_ddr_str_done_ack),
.o_user3_ddr_str_addr(o_user3_ddr_str_addr),
.o_user3_ddr_str_len(o_user3_ddr_str_len),
.o_ddr_user4_str_addr(o_ddr_user4_str_addr),
.o_ddr_user4_str_len(o_ddr_user4_str_len),
.o_ddr_user4_str_en(o_ddr_user4_str_en),
.i_ddr_user4_str_done(i_ddr_user4_str_done),
.o_ddr_user4_str_done_ack(o_ddr_user4_str_done_ack),
.o_user4_ddr_str_en(o_user4_ddr_str_en),
.i_user4_ddr_str_done(i_user4_ddr_str_done),
.o_user4_ddr_str_done_ack(o_user4_ddr_str_done_ack),
.o_user4_ddr_str_addr(o_user4_ddr_str_addr),
.o_user4_ddr_str_len(o_user4_ddr_str_len),
.clk_sysmon_i(clk_sysmon_i),
.o_enet_enable(o_enet_enable),
.o_enet_loopback(o_enet_loopback),
.o_enet_send_data_size(o_enet_send_data_size),
.o_enet_rcv_data_size(o_enet_rcv_data_size),
.o_enet_ddr_src_addr(o_enet_ddr_src_addr),
.o_enet_ddr_dest_addr(o_enet_ddr_dest_addr),
.i_enet_rx_cnt(i_enet_rx_cnt),
.i_enet_tx_cnt(i_enet_tx_cnt),
.i_enet_rx_done(i_enet_rx_done),
.i_enet_tx_done(i_enet_tx_done)
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:hls:HLS_accel:1.0
// IP Revision: 1605192151
(* X_CORE_INFO = "HLS_accel,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "system_HLS_accel_0_0,HLS_accel,{}" *)
(* CORE_GENERATION_INFO = "system_HLS_accel_0_0,HLS_accel,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=HLS_accel,x_ipVersion=1.0,x_ipCoreRevision=1605192151,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_CONTROL_BUS_ADDR_WIDTH=5,C_S_AXI_CONTROL_BUS_DATA_WIDTH=32}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module system_HLS_accel_0_0 (
s_axi_CONTROL_BUS_AWADDR,
s_axi_CONTROL_BUS_AWVALID,
s_axi_CONTROL_BUS_AWREADY,
s_axi_CONTROL_BUS_WDATA,
s_axi_CONTROL_BUS_WSTRB,
s_axi_CONTROL_BUS_WVALID,
s_axi_CONTROL_BUS_WREADY,
s_axi_CONTROL_BUS_BRESP,
s_axi_CONTROL_BUS_BVALID,
s_axi_CONTROL_BUS_BREADY,
s_axi_CONTROL_BUS_ARADDR,
s_axi_CONTROL_BUS_ARVALID,
s_axi_CONTROL_BUS_ARREADY,
s_axi_CONTROL_BUS_RDATA,
s_axi_CONTROL_BUS_RRESP,
s_axi_CONTROL_BUS_RVALID,
s_axi_CONTROL_BUS_RREADY,
ap_clk,
ap_rst_n,
interrupt,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TDATA,
INPUT_STREAM_TDEST,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TDEST,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID
);
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS AWADDR" *)
input wire [4 : 0] s_axi_CONTROL_BUS_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS AWVALID" *)
input wire s_axi_CONTROL_BUS_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS AWREADY" *)
output wire s_axi_CONTROL_BUS_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS WDATA" *)
input wire [31 : 0] s_axi_CONTROL_BUS_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS WSTRB" *)
input wire [3 : 0] s_axi_CONTROL_BUS_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS WVALID" *)
input wire s_axi_CONTROL_BUS_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS WREADY" *)
output wire s_axi_CONTROL_BUS_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS BRESP" *)
output wire [1 : 0] s_axi_CONTROL_BUS_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS BVALID" *)
output wire s_axi_CONTROL_BUS_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS BREADY" *)
input wire s_axi_CONTROL_BUS_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS ARADDR" *)
input wire [4 : 0] s_axi_CONTROL_BUS_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS ARVALID" *)
input wire s_axi_CONTROL_BUS_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS ARREADY" *)
output wire s_axi_CONTROL_BUS_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS RDATA" *)
output wire [31 : 0] s_axi_CONTROL_BUS_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS RRESP" *)
output wire [1 : 0] s_axi_CONTROL_BUS_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS RVALID" *)
output wire s_axi_CONTROL_BUS_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 s_axi_CONTROL_BUS RREADY" *)
input wire s_axi_CONTROL_BUS_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input wire ap_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 ap_rst_n RST" *)
input wire ap_rst_n;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT" *)
output wire interrupt;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TVALID" *)
input wire INPUT_STREAM_TVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TREADY" *)
output wire INPUT_STREAM_TREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TDATA" *)
input wire [31 : 0] INPUT_STREAM_TDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TDEST" *)
input wire [4 : 0] INPUT_STREAM_TDEST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TKEEP" *)
input wire [3 : 0] INPUT_STREAM_TKEEP;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TSTRB" *)
input wire [3 : 0] INPUT_STREAM_TSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TUSER" *)
input wire [3 : 0] INPUT_STREAM_TUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TLAST" *)
input wire [0 : 0] INPUT_STREAM_TLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 INPUT_STREAM TID" *)
input wire [4 : 0] INPUT_STREAM_TID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TVALID" *)
output wire OUTPUT_STREAM_TVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TREADY" *)
input wire OUTPUT_STREAM_TREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TDATA" *)
output wire [31 : 0] OUTPUT_STREAM_TDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TDEST" *)
output wire [4 : 0] OUTPUT_STREAM_TDEST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TKEEP" *)
output wire [3 : 0] OUTPUT_STREAM_TKEEP;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TSTRB" *)
output wire [3 : 0] OUTPUT_STREAM_TSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TUSER" *)
output wire [3 : 0] OUTPUT_STREAM_TUSER;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TLAST" *)
output wire [0 : 0] OUTPUT_STREAM_TLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:axis:1.0 OUTPUT_STREAM TID" *)
output wire [4 : 0] OUTPUT_STREAM_TID;
HLS_accel #(
.C_S_AXI_CONTROL_BUS_ADDR_WIDTH(5),
.C_S_AXI_CONTROL_BUS_DATA_WIDTH(32)
) inst (
.s_axi_CONTROL_BUS_AWADDR(s_axi_CONTROL_BUS_AWADDR),
.s_axi_CONTROL_BUS_AWVALID(s_axi_CONTROL_BUS_AWVALID),
.s_axi_CONTROL_BUS_AWREADY(s_axi_CONTROL_BUS_AWREADY),
.s_axi_CONTROL_BUS_WDATA(s_axi_CONTROL_BUS_WDATA),
.s_axi_CONTROL_BUS_WSTRB(s_axi_CONTROL_BUS_WSTRB),
.s_axi_CONTROL_BUS_WVALID(s_axi_CONTROL_BUS_WVALID),
.s_axi_CONTROL_BUS_WREADY(s_axi_CONTROL_BUS_WREADY),
.s_axi_CONTROL_BUS_BRESP(s_axi_CONTROL_BUS_BRESP),
.s_axi_CONTROL_BUS_BVALID(s_axi_CONTROL_BUS_BVALID),
.s_axi_CONTROL_BUS_BREADY(s_axi_CONTROL_BUS_BREADY),
.s_axi_CONTROL_BUS_ARADDR(s_axi_CONTROL_BUS_ARADDR),
.s_axi_CONTROL_BUS_ARVALID(s_axi_CONTROL_BUS_ARVALID),
.s_axi_CONTROL_BUS_ARREADY(s_axi_CONTROL_BUS_ARREADY),
.s_axi_CONTROL_BUS_RDATA(s_axi_CONTROL_BUS_RDATA),
.s_axi_CONTROL_BUS_RRESP(s_axi_CONTROL_BUS_RRESP),
.s_axi_CONTROL_BUS_RVALID(s_axi_CONTROL_BUS_RVALID),
.s_axi_CONTROL_BUS_RREADY(s_axi_CONTROL_BUS_RREADY),
.ap_clk(ap_clk),
.ap_rst_n(ap_rst_n),
.interrupt(interrupt),
.INPUT_STREAM_TVALID(INPUT_STREAM_TVALID),
.INPUT_STREAM_TREADY(INPUT_STREAM_TREADY),
.INPUT_STREAM_TDATA(INPUT_STREAM_TDATA),
.INPUT_STREAM_TDEST(INPUT_STREAM_TDEST),
.INPUT_STREAM_TKEEP(INPUT_STREAM_TKEEP),
.INPUT_STREAM_TSTRB(INPUT_STREAM_TSTRB),
.INPUT_STREAM_TUSER(INPUT_STREAM_TUSER),
.INPUT_STREAM_TLAST(INPUT_STREAM_TLAST),
.INPUT_STREAM_TID(INPUT_STREAM_TID),
.OUTPUT_STREAM_TVALID(OUTPUT_STREAM_TVALID),
.OUTPUT_STREAM_TREADY(OUTPUT_STREAM_TREADY),
.OUTPUT_STREAM_TDATA(OUTPUT_STREAM_TDATA),
.OUTPUT_STREAM_TDEST(OUTPUT_STREAM_TDEST),
.OUTPUT_STREAM_TKEEP(OUTPUT_STREAM_TKEEP),
.OUTPUT_STREAM_TSTRB(OUTPUT_STREAM_TSTRB),
.OUTPUT_STREAM_TUSER(OUTPUT_STREAM_TUSER),
.OUTPUT_STREAM_TLAST(OUTPUT_STREAM_TLAST),
.OUTPUT_STREAM_TID(OUTPUT_STREAM_TID)
);
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*/
`include "control.h"
// Behavioral model for the ALU
module arrmul (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// Defining integers: integer [name_of_integer] = value;
// Indicates the number of bits that have been shifted
integer sgn;
/**
* Indicates the number of iterations for adding a multiplier
* so that these additions resemble the multiplication/shift
* operation with this currently enumerated bit of the
* multiplicand
*/
integer cnt;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
/**
* Temporary reg(s) to contain the partial products during
* multiplication
*/
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:7] p_pdt8a3;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
$display("reg_A",reg_A);
$display("reg_B",reg_B);
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8a3=8'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16a3=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
`w8: // aluwmuleu AND `w8
begin
p_pdt8a[8:15]=reg_A[0:7];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[0:7]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[0:15]=p_pdt[0:15]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[16:23];
p_pdt8b[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[16:23]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[16:31]=p_pdt[16:31]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[32:39];
p_pdt8c[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[32:39]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[48:55];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[64:71];
p_pdt8e[0:7]=8'd0;
for(sgn=71; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[80:87];
p_pdt8f[0:7]=8'd0;
for(sgn=87; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[96:103];
p_pdt8g[0:7]=8'd0;
for(sgn=103; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[112:119];
p_pdt8h[0:7]=8'd0;
for(sgn=119; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmuleu AND `w16
begin
p_pdt16a[16:31]=reg_A[0:15];
p_pdt16a[0:15]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[0:15]<<(15-sgn));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[32:47];
p_pdt16b[0:15]=8'd0;
for(sgn=47; sgn>=32; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[32:47]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[64:79];
p_pdt16c[0:15]=8'd0;
for(sgn=79; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[64:79]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[96:111];
p_pdt16d[0:15]=8'd0;
for(sgn=111; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[96:111]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmuleu AND Default
begin
result=128'd0;
end
endcase
end
/**
* ====================================================================
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*/
// ======================================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
(`w8+2'd1): // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
p_pdt8a2[0:15]={{8{1'b0}},reg_B[32:39]};
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
p_pdt[32:47]=p_pdt[32:47]+((p_pdt8a[sgn]==1'd1)?(p_pdt8a2<<(8'd15-sgn)):16'b0);
end
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
for(sgn=31; sgn>=24; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
for(sgn=39; sgn>=33; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
for(sgn=79; sgn>=72; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
for(sgn=95; sgn>=88; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
for(sgn=111; sgn>=104; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
for(sgn=127; sgn>=120; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmulou AND `w16
begin
p_pdt16a[16:31]=reg_A[16:31];
p_pdt16a[0:15]=8'd0;
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[16:31]<<(15-(sgn%16)));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[48:63];
p_pdt16b[0:15]=8'd0;
for(sgn=63; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[48:63]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[80:95];
p_pdt16c[0:15]=8'd0;
for(sgn=95; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[80:95]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[112:127];
p_pdt16d[0:15]=8'd0;
for(sgn=127; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[112:127]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmulou AND Default
begin
result=128'd0;
end
endcase
end
/**
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
*/
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
`w8: // aluwmulos AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[8:15];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[8]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
if(reg_B[8]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
end
else
begin
p_pdt8a[8:15]=reg_A[8:15];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[24:31];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[24]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
if(reg_B[24]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
end
else
begin
p_pdt8b[8:15]=reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]=1+~p_pdt[16:31];
end
else
begin
result[16:31]=p_pdt[16:31];
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[40:47];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[40]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
if(reg_B[40]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
end
else
begin
p_pdt8c[8:15]=reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]=1+~p_pdt[32:47];
end
else
begin
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[56:63];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[56]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
if(reg_B[56]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
end
else
begin
p_pdt8d[8:15]=reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]=1+~p_pdt[48:63];
end
else
begin
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[72:79];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[72]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
if(reg_B[72]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
end
else
begin
p_pdt8e[8:15]=reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]=1+~p_pdt[64:79];
end
else
begin
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[88:95];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[88]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
if(reg_B[88]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
end
else
begin
p_pdt8f[8:15]=reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]=1+~p_pdt[80:95];
end
else
begin
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[104:111];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[104]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
if(reg_B[104]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
end
else
begin
p_pdt8g[8:15]=reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]=1+~p_pdt[96:111];
end
else
begin
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[120:127];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[120]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
if(reg_B[120]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
end
else
begin
p_pdt8h[8:15]=reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]=1+~p_pdt[112:127];
end
else
begin
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
`w16: // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[16:31];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
if(reg_B[16]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
end
else
begin
p_pdt16a[16:31]=reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]=1+~p_pdt[0:31];
end
else
begin
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[48:63];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
if(reg_B[48]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
end
else
begin
p_pdt16b[16:31]=reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]=1+~p_pdt[32:63];
end
else
begin
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[80:95];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
if(reg_B[80]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
end
else
begin
p_pdt16c[16:31]=reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]=1+~p_pdt[64:95];
end
else
begin
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[112:127];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
if(reg_B[112]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
end
else
begin
p_pdt16d[16:31]=reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]=1+~p_pdt[96:127];
end
else
begin
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
`w8: // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
end
if(p_pdt8b[8]==1'd1)
begin
end
else
begin
result[16:31]=p_pdt[16:31];
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]=1+~p_pdt[32:47];
end
else
begin
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]=1+~p_pdt[48:63];
end
else
begin
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]=1+~p_pdt[64:79];
end
else
begin
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]=1+~p_pdt[80:95];
end
else
begin
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]=1+~p_pdt[96:111];
end
else
begin
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]=1+~p_pdt[112:127];
end
else
begin
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
`w16: // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]=1+~p_pdt[0:31];
end
else
begin
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[32:47];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]=1+~p_pdt[32:63];
end
else
begin
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]=1+~p_pdt[64:95];
end
else
begin
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]=1+~p_pdt[96:127];
end
else
begin
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311A_BLACKBOX_V
`define SKY130_FD_SC_HS__O311A_BLACKBOX_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311A_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__probe_p (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__PROBE_P_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31OI_TB_V
`define SKY130_FD_SC_HD__A31OI_TB_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a31oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__a31oi dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31OI_TB_V
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:42:40 06/01/2015
// Design Name:
// Module Name: scancode_to_speccy
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module scancode_to_sam (
input wire clk, // el mismo clk de ps/2
input wire rst,
input wire scan_received,
input wire [7:0] scan,
input wire extended,
input wire released,
input wire kbclean,
//------------------------
input wire [8:0] sam_row,
output wire [7:0] sam_col,
output wire user_reset,
output wire master_reset,
output wire user_nmi,
output wire [1:0] user_toggles,
//------------------------
input wire [7:0] din,
output reg [7:0] dout,
input wire cpuwrite,
input wire cpuread,
input wire rewind
);
// las teclas del SAM. Se inicializan a "no pulsadas".
reg [7:0] row[0:8];
initial begin
row[0] = 8'hFF;
row[1] = 8'hFF;
row[2] = 8'hFF;
row[3] = 8'hFF;
row[4] = 8'hFF;
row[5] = 8'hFF;
row[6] = 8'hFF;
row[7] = 8'hFF;
row[8] = 8'hFF;
end
// El gran mapa de teclado y sus registros de acceso
reg [7:0] keymap[0:16383]; // 16K x 8 bits
reg [13:0] addr = 14'h0000;
reg [13:0] cpuaddr = 14'h0000; // Dirección E/S desde la CPU. Se autoincrementa en cada acceso
initial begin
$readmemh ("keyb_es_hex.txt", keymap);
end
reg [3:0] keyrow1 = 4'h0;
reg [7:0] keycol1 = 8'h00;
reg [3:0] keyrow2 = 4'h0;
reg [7:0] keycol2 = 8'h00;
reg [2:0] keymodifiers = 3'b000;
reg [2:0] signalstate = 3'b000;
reg [1:0] togglestate = 2'b00;
reg rmaster_reset = 1'b0, ruser_reset = 1'b0, ruser_nmi = 1'b0;
reg [1:0] ruser_toggles = 2'b00;
assign master_reset = rmaster_reset;
assign user_reset = ruser_reset;
assign user_nmi = ruser_nmi;
assign user_toggles = ruser_toggles;
// Asi funciona la matriz de teclado cuando se piden semifilas
// desde la CPU.
// Un always @* hubiera quedado más claro en la descripción
// pero por algun motivo, el XST no lo ha admitido en este caso
assign sam_col = ((sam_row[0] == 1'b0)? row[0] : 8'hFF) &
((sam_row[1] == 1'b0)? row[1] : 8'hFF) &
((sam_row[2] == 1'b0)? row[2] : 8'hFF) &
((sam_row[3] == 1'b0)? row[3] : 8'hFF) &
((sam_row[4] == 1'b0)? row[4] : 8'hFF) &
((sam_row[5] == 1'b0)? row[5] : 8'hFF) &
((sam_row[6] == 1'b0)? row[6] : 8'hFF) &
((sam_row[7] == 1'b0)? row[7] : 8'hFF) &
((sam_row[8] == 1'b0)? row[8] : 8'hFF);
reg [2:0] modifiers = 3'b000;
reg [3:0] keycount = 4'b0000;
parameter
CLEANMATRIX = 4'd0,
IDLE = 4'd1,
ADDR0PUT = 4'd2,
ADDR1PUT = 4'd3,
ADDR2PUT = 4'd4,
ADDR3PUT = 4'd5,
TRANSLATE1 = 4'd6,
TRANSLATE2 = 4'd7,
TRANSLATE3 = 4'd8,
CPUTIME = 4'd9,
CPUREAD = 4'd10,
CPUWRITE = 4'd11,
CPUINCADD = 4'd12,
UPDCOUNTERS1= 4'd13,
UPDCOUNTERS2= 4'd14;
reg [3:0] state = CLEANMATRIX;
reg key_is_pending = 1'b0;
always @(posedge clk) begin
if (scan_received == 1'b1)
key_is_pending <= 1'b1;
if (rst == 1'b1 || (kbclean == 1'b1 && state == IDLE && scan_received == 1'b0))
state <= CLEANMATRIX;
else begin
case (state)
CLEANMATRIX: begin
modifiers <= 3'b000;
keycount <= 4'b0000;
row[0] <= 8'hFF;
row[1] <= 8'hFF;
row[2] <= 8'hFF;
row[3] <= 8'hFF;
row[4] <= 8'hFF;
row[5] <= 8'hFF;
row[6] <= 8'hFF;
row[7] <= 8'hFF;
row[8] <= 8'hFF;
state <= IDLE;
end
IDLE: begin
if (key_is_pending == 1'b1) begin
addr <= {modifiers, extended, scan, 2'b00}; // 1 scan tiene 8 bits + 1 bit para indicar scan extendido + 3 bits para el modificador usado
state <= ADDR0PUT;
key_is_pending <= 1'b0;
end
else if (cpuread == 1'b1 || cpuwrite == 1'b1 || rewind == 1'b1)
state <= CPUTIME;
end
ADDR0PUT: begin
{keyrow1,keycol1[7:4]} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b01};
state <= ADDR1PUT;
end
ADDR1PUT: begin
{keycol1[3:0],keyrow2} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b10};
state <= ADDR2PUT;
end
ADDR2PUT: begin
{keycol2} <= keymap[addr];
addr <= {modifiers, extended, scan, 2'b11};
state <= ADDR3PUT;
end
ADDR3PUT: begin
{signalstate,keymodifiers,togglestate} <= keymap[addr];
state <= TRANSLATE1;
end
TRANSLATE1: begin
// Actualiza las 8 semifilas del teclado con la primera tecla
if (~released) begin
if (keyrow1[3] == 1'b1)
row[8] <= row[8] & ~keycol1;
else
row[keyrow1[2:0]] <= row[keyrow1[2:0]] & ~keycol1;
end
else begin
if (keyrow1[3] == 1'b1)
row[8] <= row[8] | keycol1;
else
row[keyrow1[2:0]] <= row[keyrow1[2:0]] | keycol1;
end
state <= TRANSLATE2;
end
TRANSLATE2: begin
// Actualiza las 8 semifilas del teclado con la segunda tecla
if (~released) begin
if (keyrow2[3] == 1'b1)
row[8] <= row[8] & ~keycol2;
else
row[keyrow2[2:0]] <= row[keyrow2[2:0]] & ~keycol2;
end
else begin
if (keyrow2[3] == 1'b1)
row[8] <= row[8] | keycol2;
else
row[keyrow2[2:0]] <= row[keyrow2[2:0]] | keycol2;
end
state <= TRANSLATE3;
end
TRANSLATE3: begin
// Actualiza modificadores
if (~released)
modifiers <= modifiers | keymodifiers;
else
modifiers <= modifiers & ~keymodifiers;
// Y de la misma forma tendria que actualizar resets y los user_toogles
if (~released)
{rmaster_reset,ruser_reset,ruser_nmi} <= {rmaster_reset,ruser_reset,ruser_nmi} | signalstate;
else
{rmaster_reset,ruser_reset,ruser_nmi} <= {rmaster_reset,ruser_reset,ruser_nmi} & ~signalstate;
if (~released)
ruser_toggles <= ruser_toggles | togglestate;
else
ruser_toggles <= ruser_toggles & ~togglestate;
//state <= UPDCOUNTERS1;
state <= IDLE;
end
CPUTIME: begin
if (rewind == 1'b1) begin
cpuaddr <= 14'h0000;
state <= IDLE;
end
else if (cpuread == 1'b1) begin
addr <= cpuaddr;
state <= CPUREAD;
end
else if (cpuwrite == 1'b1) begin
addr <= cpuaddr;
state <= CPUWRITE;
end
else
state <= IDLE;
end
CPUREAD: begin // CPU wants to read from keymap
dout <= keymap[addr];
state <= CPUINCADD;
end
CPUWRITE: begin
keymap[addr] <= din;
state <= CPUINCADD;
end
CPUINCADD: begin
if (cpuread == 1'b0 && cpuwrite == 1'b0) begin
cpuaddr <= cpuaddr + 1;
state <= IDLE;
end
end
default: begin
state <= IDLE;
end
endcase
end
end
endmodule
module keyboard_pressed_status (
input wire clk,
input wire rst,
input wire scan_received,
input wire [7:0] scancode,
input wire extended,
input wire released,
output reg kbclean
);
parameter
RESETTING = 2'd0,
UPDATING = 2'd1,
SCANNING = 2'd2;
reg keybstat_ne[0:255]; // non extended keymap
reg keybstat_ex[0:255]; // extended keymap
reg [7:0] addrscan = 8'h00; // keymap bit address
reg keypressed_ne = 1'b0; // there is at least one key pressed
reg keypressed_ex = 1'b0; // there is at least one extended key pressed
reg [1:0] state = RESETTING;
integer i;
initial begin
kbclean = 1'b1;
for (i=0;i<256;i=i+1) begin
keybstat_ne[i] = 1'b0;
keybstat_ex[i] = 1'b0;
end
end
always @(posedge clk) begin
if (rst == 1'b1) begin
state <= RESETTING;
addrscan <= 8'h00;
end
else begin
case (state)
RESETTING:
begin
if (addrscan == 8'hFF) begin
addrscan <= 8'h00;
state <= SCANNING;
kbclean <= 1'b1;
end
else begin
keybstat_ne[addrscan] <= 1'b0;
keybstat_ex[addrscan] <= 1'b0;
addrscan <= addrscan + 8'd1;
end
end
UPDATING:
begin
state <= SCANNING;
addrscan <= 8'h00;
kbclean <= 1'b0;
keypressed_ne <= 1'b0;
keypressed_ex <= 1'b0;
if (extended == 1'b0)
keybstat_ne[scancode] <= ~released;
else
keybstat_ex[scancode] <= ~released;
end
SCANNING:
begin
if (scan_received == 1'b1)
state <= UPDATING;
addrscan <= addrscan + 8'd1;
if (addrscan == 8'hFF) begin
kbclean <= ~(keypressed_ne | keypressed_ex);
keypressed_ne <= 1'b0;
keypressed_ex <= 1'b0;
end
else begin
keypressed_ne <= keypressed_ne | keybstat_ne[addrscan];
keypressed_ex <= keypressed_ex | keybstat_ex[addrscan];
end
end
endcase
end
end
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Dynamic_Saturation_block1.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Dynamic_Saturation_block1
// Source Path: velocityControlHdl/Control_Velocity/Rotor_Velocity_Control/PI_Sat/Dynamic Saturation
// Hierarchy Level: 7
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Dynamic_Saturation_block1
(
up,
u,
lo,
y,
sat_mode
);
input signed [17:0] up; // sfix18_En15
input signed [35:0] u; // sfix36_En22
input signed [17:0] lo; // sfix18_En15
output signed [35:0] y; // sfix36_En22
output sat_mode;
wire signed [35:0] LowerRelop1_1_cast; // sfix36_En22
wire LowerRelop1_relop1;
wire signed [35:0] UpperRelop_1_cast; // sfix36_En22
wire UpperRelop_relop1;
wire signed [35:0] lo_dtc; // sfix36_En22
wire signed [35:0] Switch_out1; // sfix36_En22
wire signed [35:0] up_dtc; // sfix36_En22
wire signed [35:0] Switch2_out1; // sfix36_En22
wire LowerRelop1_out1;
// <S33>/LowerRelop1
assign LowerRelop1_1_cast = {{11{up[17]}}, {up, 7'b0000000}};
assign LowerRelop1_relop1 = (u > LowerRelop1_1_cast ? 1'b1 :
1'b0);
// <S33>/UpperRelop
assign UpperRelop_1_cast = {{11{lo[17]}}, {lo, 7'b0000000}};
assign UpperRelop_relop1 = (u < UpperRelop_1_cast ? 1'b1 :
1'b0);
assign lo_dtc = {{11{lo[17]}}, {lo, 7'b0000000}};
// <S33>/Switch
assign Switch_out1 = (UpperRelop_relop1 == 1'b0 ? u :
lo_dtc);
assign up_dtc = {{11{up[17]}}, {up, 7'b0000000}};
// <S33>/Switch2
assign Switch2_out1 = (LowerRelop1_relop1 == 1'b0 ? Switch_out1 :
up_dtc);
assign y = Switch2_out1;
// <S33>/Logical Operator
assign LowerRelop1_out1 = LowerRelop1_relop1 | UpperRelop_relop1;
assign sat_mode = LowerRelop1_out1;
endmodule // velocityControlHdl_Dynamic_Saturation_block1
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2009 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file virtex4_pmem.v when simulating
// the core, virtex4_pmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module virtex4_pmem(
clka,
ena,
wea,
addra,
dina,
douta);
input clka;
input ena;
input [1 : 0] wea;
input [11 : 0] addra;
input [15 : 0] dina;
output [15 : 0] douta;
// synthesis translate_off
BLK_MEM_GEN_V3_3 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_BYTE_SIZE(8),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("virtex4"),
.C_HAS_ENA(1),
.C_HAS_ENB(0),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(0),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(16),
.C_READ_WIDTH_B(16),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(1),
.C_USE_BYTE_WEB(1),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_WEA_WIDTH(2),
.C_WEB_WIDTH(2),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(16),
.C_WRITE_WIDTH_B(16),
.C_XDEVICEFAMILY("virtex4"))
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.RSTA(),
.REGCEA(),
.CLKB(),
.RSTB(),
.ENB(),
.REGCEB(),
.WEB(),
.ADDRB(),
.DINB(),
.DOUTB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of virtex4_pmem is "black_box"
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * CNRS-Ecole Polytechnique-INRIA Futurs-Universite Paris Sud *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(*i $Id: Zdiv.v 11477 2008-10-20 15:16:14Z letouzey $ i*)
(* Contribution by Claude Marché and Xavier Urbain *)
(** Euclidean Division
Defines first of function that allows Coq to normalize.
Then only after proves the main required property.
*)
Require Export ZArith_base.
Require Import Zbool.
Require Import Omega.
Require Import ZArithRing.
Require Import Zcomplements.
Require Export Setoid.
Open Local Scope Z_scope.
(** * Definitions of Euclidian operations *)
(** Euclidean division of a positive by a integer
(that is supposed to be positive).
Total function than returns an arbitrary value when
divisor is not positive
*)
Unboxed Fixpoint Zdiv_eucl_POS (a:positive) (b:Z) {struct a} :
Z * Z :=
match a with
| xH => if Zge_bool b 2 then (0, 1) else (1, 0)
| xO a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
| xI a' =>
let (q, r) := Zdiv_eucl_POS a' b in
let r' := 2 * r + 1 in
if Zgt_bool b r' then (2 * q, r') else (2 * q + 1, r' - b)
end.
(** Euclidean division of integers.
Total function than returns (0,0) when dividing by 0.
*)
(**
The pseudo-code is:
if b = 0 : (0,0)
if b <> 0 and a = 0 : (0,0)
if b > 0 and a < 0 : let (q,r) = div_eucl_pos (-a) b in
if r = 0 then (-q,0) else (-(q+1),b-r)
if b < 0 and a < 0 : let (q,r) = div_eucl (-a) (-b) in (q,-r)
if b < 0 and a > 0 : let (q,r) = div_eucl a (-b) in
if r = 0 then (-q,0) else (-(q+1),b+r)
In other word, when b is non-zero, q is chosen to be the greatest integer
smaller or equal to a/b. And sgn(r)=sgn(b) and |r| < |b| (at least when
r is not null).
*)
(* Nota: At least two others conventions also exist for euclidean division.
They all satify the equation a=b*q+r, but differ on the choice of (q,r)
on negative numbers.
* Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
* Another solution is to always pick a non-negative remainder:
a=b*q+r with 0 <= r < |b|
*)
Definition Zdiv_eucl (a b:Z) : Z * Z :=
match a, b with
| Z0, _ => (0, 0)
| _, Z0 => (0, 0)
| Zpos a', Zpos _ => Zdiv_eucl_POS a' b
| Zneg a', Zpos _ =>
let (q, r) := Zdiv_eucl_POS a' b in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b - r)
end
| Zneg a', Zneg b' => let (q, r) := Zdiv_eucl_POS a' (Zpos b') in (q, - r)
| Zpos a', Zneg b' =>
let (q, r) := Zdiv_eucl_POS a' (Zpos b') in
match r with
| Z0 => (- q, 0)
| _ => (- (q + 1), b + r)
end
end.
(** Division and modulo are projections of [Zdiv_eucl] *)
Definition Zdiv (a b:Z) : Z := let (q, _) := Zdiv_eucl a b in q.
Definition Zmod (a b:Z) : Z := let (_, r) := Zdiv_eucl a b in r.
(** Syntax *)
Infix "/" := Zdiv : Z_scope.
Infix "mod" := Zmod (at level 40, no associativity) : Z_scope.
(* Tests:
Eval compute in (Zdiv_eucl 7 3).
Eval compute in (Zdiv_eucl (-7) 3).
Eval compute in (Zdiv_eucl 7 (-3)).
Eval compute in (Zdiv_eucl (-7) (-3)).
*)
(** * Main division theorem *)
(** First a lemma for two positive arguments *)
Lemma Z_div_mod_POS :
forall b:Z,
b > 0 ->
forall a:positive,
let (q, r) := Zdiv_eucl_POS a b in Zpos a = b * q + r /\ 0 <= r < b.
Proof.
simple induction a; cbv beta iota delta [Zdiv_eucl_POS] in |- *;
fold Zdiv_eucl_POS in |- *; cbv zeta.
intro p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r + 1)).
case (Zgt_bool b (2 * r + 1));
(rewrite BinInt.Zpos_xI; rewrite H0; split; [ ring | omega ]).
intros p; case (Zdiv_eucl_POS p b); intros q r [H0 H1].
generalize (Zgt_cases b (2 * r)).
case (Zgt_bool b (2 * r)); rewrite BinInt.Zpos_xO;
change (Zpos (xO p)) with (2 * Zpos p) in |- *; rewrite H0;
(split; [ ring | omega ]).
generalize (Zge_cases b 2).
case (Zge_bool b 2); (intros; split; [ try ring | omega ]).
omega.
Qed.
(** Then the usual situation of a positive [b] and no restriction on [a] *)
Theorem Z_div_mod :
forall a b:Z,
b > 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ 0 <= r < b.
Proof.
intros a b; case a; case b; try (simpl in |- *; intros; omega).
unfold Zdiv_eucl in |- *; intros; apply Z_div_mod_POS; trivial.
intros; discriminate.
intros.
generalize (Z_div_mod_POS (Zpos p) H p0).
unfold Zdiv_eucl in |- *.
case (Zdiv_eucl_POS p0 (Zpos p)).
intros z z0.
case z0.
intros [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zgt_pos_0 p1); omega.
intros p1 [H1 H2].
split; trivial.
change (Zneg p0) with (- Zpos p0); rewrite H1; ring.
generalize (Zorder.Zlt_neg_0 p1); omega.
intros; discriminate.
Qed.
(** For stating the fully general result, let's give a short name
to the condition on the remainder. *)
Definition Remainder r b := 0 <= r < b \/ b < r <= 0.
(** Another equivalent formulation: *)
Definition Remainder_alt r b := Zabs r < Zabs b /\ Zsgn r <> - Zsgn b.
(* In the last formulation, [ Zsgn r <> - Zsgn b ] is less nice than saying
[ Zsgn r = Zsgn b ], but at least it works even when [r] is null. *)
Lemma Remainder_equiv : forall r b, Remainder r b <-> Remainder_alt r b.
Proof.
intros; unfold Remainder, Remainder_alt; omega with *.
Qed.
Hint Unfold Remainder.
(** Now comes the fully general result about Euclidean division. *)
Theorem Z_div_mod_full :
forall a b:Z,
b <> 0 -> let (q, r) := Zdiv_eucl a b in a = b * q + r /\ Remainder r b.
Proof.
destruct b as [|b|b].
(* b = 0 *)
intro H; elim H; auto.
(* b > 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
destruct Zdiv_eucl as (q,r); intuition; simpl; auto.
(* b < 0 *)
intros _.
assert (Zpos b > 0) by auto with zarith.
generalize (Z_div_mod a (Zpos b) H).
unfold Remainder.
destruct a as [|a|a].
(* a = 0 *)
simpl; intuition.
(* a > 0 *)
unfold Zdiv_eucl; destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; [ | | omega with *].
rewrite <- Zmult_opp_comm; simpl Zopp; intuition.
rewrite <- Zmult_opp_comm; simpl Zopp.
rewrite Zmult_plus_distr_r; omega with *.
(* a < 0 *)
unfold Zdiv_eucl.
generalize (Z_div_mod_POS (Zpos b) H a).
destruct Zdiv_eucl_POS as (q,r).
destruct r as [|r|r]; change (Zneg b) with (-Zpos b).
rewrite Zmult_opp_comm; omega with *.
rewrite <- Zmult_opp_comm, Zmult_plus_distr_r;
repeat rewrite Zmult_opp_comm; omega.
rewrite Zmult_opp_comm; omega with *.
Qed.
(** The same results as before, stated separately in terms of Zdiv and Zmod *)
Lemma Z_mod_remainder : forall a b:Z, b<>0 -> Remainder (a mod b) b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb); auto.
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_lt : forall a b:Z, b > 0 -> 0 <= a mod b < b.
Proof.
unfold Zmod; intros a b Hb; generalize (Z_div_mod a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_mod_neg : forall a b:Z, b < 0 -> b < a mod b <= 0.
Proof.
unfold Zmod; intros a b Hb.
assert (Hb' : b<>0) by (auto with zarith).
generalize (Z_div_mod_full a b Hb').
destruct Zdiv_eucl.
unfold Remainder; intuition.
Qed.
Lemma Z_div_mod_eq_full : forall a b:Z, b <> 0 -> a = b*(a/b) + (a mod b).
Proof.
unfold Zdiv, Zmod; intros a b Hb; generalize (Z_div_mod_full a b Hb).
destruct Zdiv_eucl; tauto.
Qed.
Lemma Z_div_mod_eq : forall a b:Z, b > 0 -> a = b*(a/b) + (a mod b).
Proof.
intros; apply Z_div_mod_eq_full; auto with zarith.
Qed.
Lemma Zmod_eq_full : forall a b:Z, b<>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq_full; auto.
Qed.
Lemma Zmod_eq : forall a b:Z, b>0 -> a mod b = a - (a/b)*b.
Proof.
intros.
rewrite <- Zeq_plus_swap, Zplus_comm, Zmult_comm; symmetry.
apply Z_div_mod_eq; auto.
Qed.
(** Existence theorem *)
Theorem Zdiv_eucl_exist : forall (b:Z)(Hb:b>0)(a:Z),
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < b}.
Proof.
intros b Hb a.
exists (Zdiv_eucl a b).
exact (Z_div_mod a b Hb).
Qed.
Implicit Arguments Zdiv_eucl_exist.
(** Uniqueness theorems *)
Theorem Zdiv_mod_unique :
forall b q1 q2 r1 r2:Z,
0 <= r1 < Zabs b -> 0 <= r2 < Zabs b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 H.
destruct (Z_eq_dec q1 q2) as [Hq|Hq].
split; trivial.
rewrite Hq in H; omega.
elim (Zlt_not_le (Zabs (r2 - r1)) (Zabs b)).
omega with *.
replace (r2-r1) with (b*(q1-q2)) by (rewrite Zmult_minus_distr_l; omega).
replace (Zabs b) with ((Zabs b)*1) by ring.
rewrite Zabs_Zmult.
apply Zmult_le_compat_l; auto with *.
omega with *.
Qed.
Theorem Zdiv_mod_unique_2 :
forall b q1 q2 r1 r2:Z,
Remainder r1 b -> Remainder r2 b ->
b*q1+r1 = b*q2+r2 -> q1=q2 /\ r1=r2.
Proof.
unfold Remainder.
intros b q1 q2 r1 r2 Hr1 Hr2 H.
destruct (Z_eq_dec q1 q2) as [Hq|Hq].
split; trivial.
rewrite Hq in H; omega.
elim (Zlt_not_le (Zabs (r2 - r1)) (Zabs b)).
omega with *.
replace (r2-r1) with (b*(q1-q2)) by (rewrite Zmult_minus_distr_l; omega).
replace (Zabs b) with ((Zabs b)*1) by ring.
rewrite Zabs_Zmult.
apply Zmult_le_compat_l; auto with *.
omega with *.
Qed.
Theorem Zdiv_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> q = a/b.
Proof.
intros.
assert (b <> 0) by (unfold Remainder in *; omega with *).
generalize (Z_div_mod_full a b H1).
unfold Zdiv; destruct Zdiv_eucl as (q',r').
intros (H2,H3); rewrite H2 in H0.
destruct (Zdiv_mod_unique_2 b q q' r r'); auto.
Qed.
Theorem Zdiv_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> q = a/b.
Proof.
intros; eapply Zdiv_unique_full; eauto.
Qed.
Theorem Zmod_unique_full:
forall a b q r, Remainder r b ->
a = b*q + r -> r = a mod b.
Proof.
intros.
assert (b <> 0) by (unfold Remainder in *; omega with *).
generalize (Z_div_mod_full a b H1).
unfold Zmod; destruct Zdiv_eucl as (q',r').
intros (H2,H3); rewrite H2 in H0.
destruct (Zdiv_mod_unique_2 b q q' r r'); auto.
Qed.
Theorem Zmod_unique:
forall a b q r, 0 <= r < b ->
a = b*q + r -> r = a mod b.
Proof.
intros; eapply Zmod_unique_full; eauto.
Qed.
(** * Basic values of divisions and modulo. *)
Lemma Zmod_0_l: forall a, 0 mod a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_0_r: forall a, a mod 0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_l: forall a, 0/a = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zdiv_0_r: forall a, a/0 = 0.
Proof.
destruct a; simpl; auto.
Qed.
Lemma Zmod_1_r: forall a, a mod 1 = 0.
Proof.
intros; symmetry; apply Zmod_unique with a; auto with zarith.
Qed.
Lemma Zdiv_1_r: forall a, a/1 = a.
Proof.
intros; symmetry; apply Zdiv_unique with 0; auto with zarith.
Qed.
Hint Resolve Zmod_0_l Zmod_0_r Zdiv_0_l Zdiv_0_r Zdiv_1_r Zmod_1_r
: zarith.
Lemma Zdiv_1_l: forall a, 1 < a -> 1/a = 0.
Proof.
intros; symmetry; apply Zdiv_unique with 1; auto with zarith.
Qed.
Lemma Zmod_1_l: forall a, 1 < a -> 1 mod a = 1.
Proof.
intros; symmetry; apply Zmod_unique with 0; auto with zarith.
Qed.
Lemma Z_div_same_full : forall a:Z, a<>0 -> a/a = 1.
Proof.
intros; symmetry; apply Zdiv_unique_full with 0; auto with *; red; omega.
Qed.
Lemma Z_mod_same_full : forall a, a mod a = 0.
Proof.
destruct a; intros; symmetry.
compute; auto.
apply Zmod_unique with 1; auto with *; omega with *.
apply Zmod_unique_full with 1; auto with *; red; omega with *.
Qed.
Lemma Z_mod_mult : forall a b, (a*b) mod b = 0.
Proof.
intros a b; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; simpl; rewrite Zmod_0_r; auto.
symmetry; apply Zmod_unique_full with a; [ red; omega | ring ].
Qed.
Lemma Z_div_mult_full : forall a b:Z, b <> 0 -> (a*b)/b = a.
Proof.
intros; symmetry; apply Zdiv_unique_full with 0; auto with zarith;
[ red; omega | ring].
Qed.
(** * Order results about Zmod and Zdiv *)
(* Division of positive numbers is positive. *)
Lemma Z_div_pos: forall a b, b > 0 -> 0 <= a -> 0 <= a/b.
Proof.
intros.
rewrite (Z_div_mod_eq a b H) in H0.
assert (H1:=Z_mod_lt a b H).
destruct (Z_lt_le_dec (a/b) 0); auto.
assert (b*(a/b) <= -b).
replace (-b) with (b*-1); [ | ring].
apply Zmult_le_compat_l; auto with zarith.
omega.
Qed.
Lemma Z_div_ge0: forall a b, b > 0 -> a >= 0 -> a/b >=0.
Proof.
intros; generalize (Z_div_pos a b H); auto with zarith.
Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_div_lt : forall a b:Z, b >= 2 -> a > 0 -> a/b < a.
Proof.
intros. cut (b > 0); [ intro Hb | omega ].
generalize (Z_div_mod a b Hb).
cut (a >= 0); [ intro Ha | omega ].
generalize (Z_div_ge0 a b Hb Ha).
unfold Zdiv in |- *; case (Zdiv_eucl a b); intros q r H1 [H2 H3].
cut (a >= 2 * q -> q < a); [ intro h; apply h; clear h | intros; omega ].
apply Zge_trans with (b * q).
omega.
auto with zarith.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem Zdiv_small: forall a b, 0 <= a < b -> a/b = 0.
Proof.
intros a b H; apply sym_equal; apply Zdiv_unique with a; auto with zarith.
Qed.
(** Same situation, in term of modulo: *)
Theorem Zmod_small: forall a n, 0 <= a < n -> a mod n = a.
Proof.
intros a b H; apply sym_equal; apply Zmod_unique with 0; auto with zarith.
Qed.
(** [Zge] is compatible with a positive division. *)
Lemma Z_div_ge : forall a b c:Z, c > 0 -> a >= b -> a/c >= b/c.
Proof.
intros a b c cPos aGeb.
generalize (Z_div_mod_eq a c cPos).
generalize (Z_mod_lt a c cPos).
generalize (Z_div_mod_eq b c cPos).
generalize (Z_mod_lt b c cPos).
intros.
elim (Z_ge_lt_dec (a / c) (b / c)); trivial.
intro.
absurd (b - a >= 1).
omega.
replace (b-a) with (c * (b/c-a/c) + b mod c - a mod c) by
(symmetry; pattern a at 1; rewrite H2; pattern b at 1; rewrite H0; ring).
assert (c * (b / c - a / c) >= c * 1).
apply Zmult_ge_compat_l.
omega.
omega.
assert (c * 1 = c).
ring.
omega.
Qed.
(** Same, with [Zle]. *)
Lemma Z_div_le : forall a b c:Z, c > 0 -> a <= b -> a/c <= b/c.
Proof.
intros a b c H H0.
apply Zge_le.
apply Z_div_ge; auto with *.
Qed.
(** With our choice of division, rounding of (a/b) is always done toward bottom: *)
Lemma Z_mult_div_ge : forall a b:Z, b > 0 -> b*(a/b) <= a.
Proof.
intros a b H; generalize (Z_div_mod_eq a b H) (Z_mod_lt a b H); omega.
Qed.
Lemma Z_mult_div_ge_neg : forall a b:Z, b < 0 -> b*(a/b) >= a.
Proof.
intros a b H.
generalize (Z_div_mod_eq_full a _ (Zlt_not_eq _ _ H)) (Z_mod_neg a _ H); omega.
Qed.
(** The previous inequalities are exact iff the modulo is zero. *)
Lemma Z_div_exact_full_1 : forall a b:Z, a = b*(a/b) -> a mod b = 0.
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst b; simpl in *; subst; auto.
generalize (Z_div_mod_eq_full a b Hb); omega.
Qed.
Lemma Z_div_exact_full_2 : forall a b:Z, b <> 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; generalize (Z_div_mod_eq_full a b H); omega.
Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zmod_le: forall a b, 0 < b -> 0 <= a -> a mod b <= a.
Proof.
intros a b H1 H2; case (Zle_or_lt b a); intros H3.
case (Z_mod_lt a b); auto with zarith.
rewrite Zmod_small; auto with zarith.
Qed.
(** Some additionnal inequalities about Zdiv. *)
Theorem Zdiv_le_upper_bound:
forall a b q, 0 <= a -> 0 < b -> a <= q*b -> a/b <= q.
Proof.
intros a b q H1 H2 H3.
apply Zmult_le_reg_r with b; auto with zarith.
apply Zle_trans with (2 := H3).
pattern a at 2; rewrite (Z_div_mod_eq a b); auto with zarith.
rewrite (Zmult_comm b); case (Z_mod_lt a b); auto with zarith.
Qed.
Theorem Zdiv_lt_upper_bound:
forall a b q, 0 <= a -> 0 < b -> a < q*b -> a/b < q.
Proof.
intros a b q H1 H2 H3.
apply Zmult_lt_reg_r with b; auto with zarith.
apply Zle_lt_trans with (2 := H3).
pattern a at 2; rewrite (Z_div_mod_eq a b); auto with zarith.
rewrite (Zmult_comm b); case (Z_mod_lt a b); auto with zarith.
Qed.
Theorem Zdiv_le_lower_bound:
forall a b q, 0 <= a -> 0 < b -> q*b <= a -> q <= a/b.
Proof.
intros a b q H1 H2 H3.
assert (q < a / b + 1); auto with zarith.
apply Zmult_lt_reg_r with b; auto with zarith.
apply Zle_lt_trans with (1 := H3).
pattern a at 1; rewrite (Z_div_mod_eq a b); auto with zarith.
rewrite Zmult_plus_distr_l; rewrite (Zmult_comm b); case (Z_mod_lt a b);
auto with zarith.
Qed.
(** A division of respect opposite monotonicity for the divisor *)
Lemma Zdiv_le_compat_l: forall p q r, 0 <= p -> 0 < q < r ->
p / r <= p / q.
Proof.
intros p q r H H1.
apply Zdiv_le_lower_bound; auto with zarith.
rewrite Zmult_comm.
pattern p at 2; rewrite (Z_div_mod_eq p r); auto with zarith.
apply Zle_trans with (r * (p / r)); auto with zarith.
apply Zmult_le_compat_r; auto with zarith.
apply Zdiv_le_lower_bound; auto with zarith.
case (Z_mod_lt p r); auto with zarith.
Qed.
Theorem Zdiv_sgn: forall a b,
0 <= Zsgn (a/b) * Zsgn a * Zsgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
generalize (Z_div_pos (Zpos a) (Zpos b)); unfold Zdiv, Zdiv_eucl;
destruct Zdiv_eucl_POS as (q,r); destruct r; omega with *.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
Lemma Z_mod_plus_full : forall a b c:Z, (a + b * c) mod c = a mod c.
Proof.
intros; destruct (Z_eq_dec c 0) as [Hc|Hc].
subst; do 2 rewrite Zmod_0_r; auto.
symmetry; apply Zmod_unique_full with (a/c+b); auto with zarith.
red; generalize (Z_mod_lt a c)(Z_mod_neg a c); omega.
rewrite Zmult_plus_distr_r, Zmult_comm.
generalize (Z_div_mod_eq_full a c Hc); omega.
Qed.
Lemma Z_div_plus_full : forall a b c:Z, c <> 0 -> (a + b * c) / c = a / c + b.
Proof.
intro; symmetry.
apply Zdiv_unique_full with (a mod c); auto with zarith.
red; generalize (Z_mod_lt a c)(Z_mod_neg a c); omega.
rewrite Zmult_plus_distr_r, Zmult_comm.
generalize (Z_div_mod_eq_full a c H); omega.
Qed.
Theorem Z_div_plus_full_l: forall a b c : Z, b <> 0 -> (a * b + c) / b = a + c / b.
Proof.
intros a b c H; rewrite Zplus_comm; rewrite Z_div_plus_full;
try apply Zplus_comm; auto with zarith.
Qed.
(** [Zopp] and [Zdiv], [Zmod].
Due to the choice of convention for our Euclidean division,
some of the relations about [Zopp] and divisions are rather complex. *)
Lemma Zdiv_opp_opp : forall a b:Z, (-a)/(-b) = a/b.
Proof.
intros [|a|a] [|b|b]; try reflexivity; unfold Zdiv; simpl;
destruct (Zdiv_eucl_POS a (Zpos b)); destruct z0; try reflexivity.
Qed.
Lemma Zmod_opp_opp : forall a b:Z, (-a) mod (-b) = - (a mod b).
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
intros; symmetry.
apply Zmod_unique_full with ((-a)/(-b)); auto.
generalize (Z_mod_remainder a b Hb); destruct 1; [right|left]; omega.
rewrite Zdiv_opp_opp.
pattern a at 1; rewrite (Z_div_mod_eq_full a b Hb); ring.
Qed.
Lemma Z_mod_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; rewrite Zmod_0_r; auto.
rewrite Z_div_exact_full_2 with a b; auto.
replace (- (b * (a / b))) with (0 + - (a / b) * b).
rewrite Z_mod_plus_full; auto.
ring.
Qed.
Lemma Z_mod_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a) mod b = b - (a mod b).
Proof.
intros.
assert (b<>0) by (contradict H; subst; rewrite Zmod_0_r; auto).
symmetry; apply Zmod_unique_full with (-1-a/b); auto.
generalize (Z_mod_remainder a b H0); destruct 1; [left|right]; omega.
rewrite Zmult_minus_distr_l.
pattern a at 1; rewrite (Z_div_mod_eq_full a b H0); ring.
Qed.
Lemma Z_mod_zero_opp_r : forall a b:Z, a mod b = 0 -> a mod (-b) = 0.
Proof.
intros.
rewrite <- (Zopp_involutive a).
rewrite Zmod_opp_opp.
rewrite Z_mod_zero_opp_full; auto.
Qed.
Lemma Z_mod_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a mod (-b) = (a mod b) - b.
Proof.
intros.
pattern a at 1; rewrite <- (Zopp_involutive a).
rewrite Zmod_opp_opp.
rewrite Z_mod_nz_opp_full; auto; omega.
Qed.
Lemma Z_div_zero_opp_full : forall a b:Z, a mod b = 0 -> (-a)/b = -(a/b).
Proof.
intros; destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; do 2 rewrite Zdiv_0_r; auto.
symmetry; apply Zdiv_unique_full with 0; auto.
red; omega.
pattern a at 1; rewrite (Z_div_mod_eq_full a b Hb).
rewrite H; ring.
Qed.
Lemma Z_div_nz_opp_full : forall a b:Z, a mod b <> 0 ->
(-a)/b = -(a/b)-1.
Proof.
intros.
assert (b<>0) by (contradict H; subst; rewrite Zmod_0_r; auto).
symmetry; apply Zdiv_unique_full with (b-a mod b); auto.
generalize (Z_mod_remainder a b H0); destruct 1; [left|right]; omega.
pattern a at 1; rewrite (Z_div_mod_eq_full a b H0); ring.
Qed.
Lemma Z_div_zero_opp_r : forall a b:Z, a mod b = 0 -> a/(-b) = -(a/b).
Proof.
intros.
pattern a at 1; rewrite <- (Zopp_involutive a).
rewrite Zdiv_opp_opp.
rewrite Z_div_zero_opp_full; auto.
Qed.
Lemma Z_div_nz_opp_r : forall a b:Z, a mod b <> 0 ->
a/(-b) = -(a/b)-1.
Proof.
intros.
pattern a at 1; rewrite <- (Zopp_involutive a).
rewrite Zdiv_opp_opp.
rewrite Z_div_nz_opp_full; auto; omega.
Qed.
(** Cancellations. *)
Lemma Zdiv_mult_cancel_r : forall a b c:Z,
c <> 0 -> (a*c)/(b*c) = a/b.
Proof.
assert (X: forall a b c, b > 0 -> c > 0 -> (a*c) / (b*c) = a / b).
intros a b c Hb Hc.
symmetry.
apply Zdiv_unique with ((a mod b)*c); auto with zarith.
destruct (Z_mod_lt a b Hb); split.
apply Zmult_le_0_compat; auto with zarith.
apply Zmult_lt_compat_r; auto with zarith.
pattern a at 1; rewrite (Z_div_mod_eq a b Hb); ring.
intros a b c Hc.
destruct (Z_dec b 0) as [Hb|Hb].
destruct Hb as [Hb|Hb]; destruct (not_Zeq_inf _ _ Hc); auto with *.
rewrite <- (Zdiv_opp_opp a), <- (Zmult_opp_opp b), <-(Zmult_opp_opp a);
auto with *.
rewrite <- (Zdiv_opp_opp a), <- Zdiv_opp_opp, Zopp_mult_distr_l,
Zopp_mult_distr_l; auto with *.
rewrite <- Zdiv_opp_opp, Zopp_mult_distr_r, Zopp_mult_distr_r; auto with *.
rewrite Hb; simpl; do 2 rewrite Zdiv_0_r; auto.
Qed.
Lemma Zdiv_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)/(c*b) = a/b.
Proof.
intros.
rewrite (Zmult_comm c a); rewrite (Zmult_comm c b).
apply Zdiv_mult_cancel_r; auto.
Qed.
Lemma Zmult_mod_distr_l: forall a b c,
(c*a) mod (c*b) = c * (a mod b).
Proof.
intros; destruct (Z_eq_dec c 0) as [Hc|Hc].
subst; simpl; rewrite Zmod_0_r; auto.
destruct (Z_eq_dec b 0) as [Hb|Hb].
subst; repeat rewrite Zmult_0_r || rewrite Zmod_0_r; auto.
assert (c*b <> 0).
contradict Hc; eapply Zmult_integral_l; eauto.
rewrite (Zplus_minus_eq _ _ _ (Z_div_mod_eq_full (c*a) (c*b) H)).
rewrite (Zplus_minus_eq _ _ _ (Z_div_mod_eq_full a b Hb)).
rewrite Zdiv_mult_cancel_l; auto with zarith.
ring.
Qed.
Lemma Zmult_mod_distr_r: forall a b c,
(a*c) mod (b*c) = (a mod b) * c.
Proof.
intros; repeat rewrite (fun x => (Zmult_comm x c)).
apply Zmult_mod_distr_l; auto.
Qed.
(** Operations modulo. *)
Theorem Zmod_mod: forall a n, (a mod n) mod n = a mod n.
Proof.
intros; destruct (Z_eq_dec n 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
pattern a at 2; rewrite (Z_div_mod_eq_full a n); auto with zarith.
rewrite Zplus_comm; rewrite Zmult_comm.
apply sym_equal; apply Z_mod_plus_full; auto with zarith.
Qed.
Theorem Zmult_mod: forall a b n,
(a * b) mod n = ((a mod n) * (b mod n)) mod n.
Proof.
intros; destruct (Z_eq_dec n 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
pattern a at 1; rewrite (Z_div_mod_eq_full a n); auto with zarith.
pattern b at 1; rewrite (Z_div_mod_eq_full b n); auto with zarith.
set (A:=a mod n); set (B:=b mod n); set (A':=a/n); set (B':=b/n).
replace ((n*A' + A) * (n*B' + B))
with (A*B + (A'*B+B'*A+n*A'*B')*n) by ring.
apply Z_mod_plus_full; auto with zarith.
Qed.
Theorem Zplus_mod: forall a b n,
(a + b) mod n = (a mod n + b mod n) mod n.
Proof.
intros; destruct (Z_eq_dec n 0) as [Hb|Hb].
subst; do 2 rewrite Zmod_0_r; auto.
pattern a at 1; rewrite (Z_div_mod_eq_full a n); auto with zarith.
pattern b at 1; rewrite (Z_div_mod_eq_full b n); auto with zarith.
replace ((n * (a / n) + a mod n) + (n * (b / n) + b mod n))
with ((a mod n + b mod n) + (a / n + b / n) * n) by ring.
apply Z_mod_plus_full; auto with zarith.
Qed.
Theorem Zminus_mod: forall a b n,
(a - b) mod n = (a mod n - b mod n) mod n.
Proof.
intros.
replace (a - b) with (a + (-1) * b); auto with zarith.
replace (a mod n - b mod n) with (a mod n + (-1) * (b mod n)); auto with zarith.
rewrite Zplus_mod.
rewrite Zmult_mod.
rewrite Zplus_mod with (b:=(-1) * (b mod n)).
rewrite Zmult_mod.
rewrite Zmult_mod with (b:= b mod n).
repeat rewrite Zmod_mod; auto.
Qed.
Lemma Zplus_mod_idemp_l: forall a b n, (a mod n + b) mod n = (a + b) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zplus_mod_idemp_r: forall a b n, (b + a mod n) mod n = (b + a) mod n.
Proof.
intros; rewrite Zplus_mod, Zmod_mod, <- Zplus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_l: forall a b n, (a mod n - b) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zminus_mod_idemp_r: forall a b n, (a - b mod n) mod n = (a - b) mod n.
Proof.
intros; rewrite Zminus_mod, Zmod_mod, <- Zminus_mod; auto.
Qed.
Lemma Zmult_mod_idemp_l: forall a b n, (a mod n * b) mod n = (a * b) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
Lemma Zmult_mod_idemp_r: forall a b n, (b * (a mod n)) mod n = (b * a) mod n.
Proof.
intros; rewrite Zmult_mod, Zmod_mod, <- Zmult_mod; auto.
Qed.
(** For a specific number N, equality modulo N is hence a nice setoid
equivalence, compatible with [+], [-] and [*]. *)
Definition eqm N a b := (a mod N = b mod N).
Lemma eqm_refl N : forall a, (eqm N) a a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_sym N : forall a b, (eqm N) a b -> (eqm N) b a.
Proof. unfold eqm; auto. Qed.
Lemma eqm_trans N : forall a b c,
(eqm N) a b -> (eqm N) b c -> (eqm N) a c.
Proof. unfold eqm; eauto with *. Qed.
Add Parametric Relation N : Z (eqm N)
reflexivity proved by (eqm_refl N)
symmetry proved by (eqm_sym N)
transitivity proved by (eqm_trans N) as eqm_setoid.
Add Parametric Morphism N : Zplus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zplus_eqm.
Proof.
unfold eqm; intros; rewrite Zplus_mod, H, H0, <- Zplus_mod; auto.
Qed.
Add Parametric Morphism N : Zminus
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zminus_eqm.
Proof.
unfold eqm; intros; rewrite Zminus_mod, H, H0, <- Zminus_mod; auto.
Qed.
Add Parametric Morphism N : Zmult
with signature (eqm N) ==> (eqm N) ==> (eqm N) as Zmult_eqm.
Proof.
unfold eqm; intros; rewrite Zmult_mod, H, H0, <- Zmult_mod; auto.
Qed.
Add Parametric Morphism N : Zopp
with signature (eqm N) ==> (eqm N) as Zopp_eqm.
Proof.
intros; change ((eqm N) (-x) (-y)) with ((eqm N) (0-x) (0-y)).
rewrite H; red; auto.
Qed.
Lemma Zmod_eqm N : forall a, (eqm N) (a mod N) a.
Proof.
intros; exact (Zmod_mod a N).
Qed.
(* NB: Zmod and Zdiv are not morphisms with respect to eqm.
For instance, let (==) be (eqm 2). Then we have (3 == 1) but:
~ (3 mod 3 == 1 mod 3)
~ (1 mod 3 == 1 mod 1)
~ (3/3 == 1/3)
~ (1/3 == 1/1)
*)
Lemma Zdiv_Zdiv : forall a b c, 0<=b -> 0<=c -> (a/b)/c = a/(b*c).
Proof.
intros a b c Hb Hc.
destruct (Zle_lt_or_eq _ _ Hb); [ | subst; rewrite Zdiv_0_r, Zdiv_0_r, Zdiv_0_l; auto].
destruct (Zle_lt_or_eq _ _ Hc); [ | subst; rewrite Zmult_0_r, Zdiv_0_r, Zdiv_0_r; auto].
pattern a at 2;rewrite (Z_div_mod_eq_full a b);auto with zarith.
pattern (a/b) at 2;rewrite (Z_div_mod_eq_full (a/b) c);auto with zarith.
replace (b * (c * (a / b / c) + (a / b) mod c) + a mod b) with
((a / b / c)*(b * c) + (b * ((a / b) mod c) + a mod b)) by ring.
rewrite Z_div_plus_full_l; auto with zarith.
rewrite (Zdiv_small (b * ((a / b) mod c) + a mod b)).
ring.
split.
apply Zplus_le_0_compat;auto with zarith.
apply Zmult_le_0_compat;auto with zarith.
destruct (Z_mod_lt (a/b) c);auto with zarith.
destruct (Z_mod_lt a b);auto with zarith.
apply Zle_lt_trans with (b * ((a / b) mod c) + (b-1)).
destruct (Z_mod_lt a b);auto with zarith.
apply Zle_lt_trans with (b * (c-1) + (b - 1)).
apply Zplus_le_compat;auto with zarith.
destruct (Z_mod_lt (a/b) c);auto with zarith.
replace (b * (c - 1) + (b - 1)) with (b*c-1);try ring;auto with zarith.
intro H1;
assert (H2: c <> 0) by auto with zarith;
rewrite (Zmult_integral_l _ _ H2 H1) in H; auto with zarith.
Qed.
(** Unfortunately, the previous result isn't always true on negative numbers.
For instance: 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) *)
(** A last inequality: *)
Theorem Zdiv_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof.
intros a b c H1 H2 H3.
destruct (Zle_lt_or_eq _ _ H2);
[ | subst; rewrite Zdiv_0_r, Zdiv_0_r, Zmult_0_r; auto].
case (Z_mod_lt a b); auto with zarith; intros Hu1 Hu2.
case (Z_mod_lt c b); auto with zarith; intros Hv1 Hv2.
apply Zmult_le_reg_r with b; auto with zarith.
rewrite <- Zmult_assoc.
replace (a / b * b) with (a - a mod b).
replace (c * a / b * b) with (c * a - (c * a) mod b).
rewrite Zmult_minus_distr_l.
unfold Zminus; apply Zplus_le_compat_l.
match goal with |- - ?X <= -?Y => assert (Y <= X); auto with zarith end.
apply Zle_trans with ((c mod b) * (a mod b)); auto with zarith.
rewrite Zmult_mod; auto with zarith.
apply (Zmod_le ((c mod b) * (a mod b)) b); auto with zarith.
apply Zmult_le_compat_r; auto with zarith.
apply (Zmod_le c b); auto.
pattern (c * a) at 1; rewrite (Z_div_mod_eq (c * a) b); try ring;
auto with zarith.
pattern a at 1; rewrite (Z_div_mod_eq a b); try ring; auto with zarith.
Qed.
(** Zmod is related to divisibility (see more in Znumtheory) *)
Lemma Zmod_divides : forall a b, b<>0 ->
(a mod b = 0 <-> exists c, a = b*c).
Proof.
split; intros.
exists (a/b).
pattern a at 1; rewrite (Z_div_mod_eq_full a b); auto with zarith.
destruct H0 as [c Hc].
symmetry.
apply Zmod_unique_full with c; auto with zarith.
red; omega with *.
Qed.
(** * Compatibility *)
(** Weaker results kept only for compatibility *)
Lemma Z_mod_same : forall a, a > 0 -> a mod a = 0.
Proof.
intros; apply Z_mod_same_full.
Qed.
Lemma Z_div_same : forall a, a > 0 -> a/a = 1.
Proof.
intros; apply Z_div_same_full; auto with zarith.
Qed.
Lemma Z_div_plus : forall a b c:Z, c > 0 -> (a + b * c) / c = a / c + b.
Proof.
intros; apply Z_div_plus_full; auto with zarith.
Qed.
Lemma Z_div_mult : forall a b:Z, b > 0 -> (a*b)/b = a.
Proof.
intros; apply Z_div_mult_full; auto with zarith.
Qed.
Lemma Z_mod_plus : forall a b c:Z, c > 0 -> (a + b * c) mod c = a mod c.
Proof.
intros; apply Z_mod_plus_full; auto with zarith.
Qed.
Lemma Z_div_exact_1 : forall a b:Z, b > 0 -> a = b*(a/b) -> a mod b = 0.
Proof.
intros; apply Z_div_exact_full_1; auto with zarith.
Qed.
Lemma Z_div_exact_2 : forall a b:Z, b > 0 -> a mod b = 0 -> a = b*(a/b).
Proof.
intros; apply Z_div_exact_full_2; auto with zarith.
Qed.
Lemma Z_mod_zero_opp : forall a b:Z, b > 0 -> a mod b = 0 -> (-a) mod b = 0.
Proof.
intros; apply Z_mod_zero_opp_full; auto with zarith.
Qed.
(** * A direct way to compute Zmod *)
Fixpoint Zmod_POS (a : positive) (b : Z) {struct a} : Z :=
match a with
| xI a' =>
let r := Zmod_POS a' b in
let r' := (2 * r + 1) in
if Zgt_bool b r' then r' else (r' - b)
| xO a' =>
let r := Zmod_POS a' b in
let r' := (2 * r) in
if Zgt_bool b r' then r' else (r' - b)
| xH => if Zge_bool b 2 then 1 else 0
end.
Definition Zmod' a b :=
match a with
| Z0 => 0
| Zpos a' =>
match b with
| Z0 => 0
| Zpos _ => Zmod_POS a' b
| Zneg b' =>
let r := Zmod_POS a' (Zpos b') in
match r with Z0 => 0 | _ => b + r end
end
| Zneg a' =>
match b with
| Z0 => 0
| Zpos _ =>
let r := Zmod_POS a' b in
match r with Z0 => 0 | _ => b - r end
| Zneg b' => - (Zmod_POS a' (Zpos b'))
end
end.
Theorem Zmod_POS_correct: forall a b, Zmod_POS a b = (snd (Zdiv_eucl_POS a b)).
Proof.
intros a b; elim a; simpl; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
intros p Rec; rewrite Rec.
case (Zdiv_eucl_POS p b); intros z1 z2; simpl; auto.
match goal with |- context [Zgt_bool _ ?X] => case (Zgt_bool b X) end; auto.
case (Zge_bool b 2); auto.
Qed.
Theorem Zmod'_correct: forall a b, Zmod' a b = Zmod a b.
Proof.
intros a b; unfold Zmod; case a; simpl; auto.
intros p; case b; simpl; auto.
intros p1; refine (Zmod_POS_correct _ _); auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p; case b; simpl; auto.
intros p1; rewrite Zmod_POS_correct; auto.
case (Zdiv_eucl_POS p (Zpos p1)); simpl; intros z1 z2; case z2; auto.
intros p1; rewrite Zmod_POS_correct; simpl; auto.
case (Zdiv_eucl_POS p (Zpos p1)); auto.
Qed.
(** Another convention is possible for division by negative numbers:
* quotient is always the biggest integer smaller than or equal to a/b
* remainder is hence always positive or null. *)
Theorem Zdiv_eucl_extended :
forall b:Z,
b <> 0 ->
forall a:Z,
{qr : Z * Z | let (q, r) := qr in a = b * q + r /\ 0 <= r < Zabs b}.
Proof.
intros b Hb a.
elim (Z_le_gt_dec 0 b); intro Hb'.
cut (b > 0); [ intro Hb'' | omega ].
rewrite Zabs_eq; [ apply Zdiv_eucl_exist; assumption | assumption ].
cut (- b > 0); [ intro Hb'' | omega ].
elim (Zdiv_eucl_exist Hb'' a); intros qr.
elim qr; intros q r Hqr.
exists (- q, r).
elim Hqr; intros.
split.
rewrite <- Zmult_opp_comm; assumption.
rewrite Zabs_non_eq; [ assumption | omega ].
Qed.
Implicit Arguments Zdiv_eucl_extended.
(** A third convention: Ocaml.
See files ZOdiv_def.v and ZOdiv.v.
Ocaml uses Round-Toward-Zero division: (-a)/b = a/(-b) = -(a/b).
Hence (-a) mod b = - (a mod b)
a mod (-b) = a mod b
And: |r| < |b| and sgn(r) = sgn(a) (notice the a here instead of b).
*)
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Thu Mar 20 00:59:05 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim /home/keith/Documents/VHDL-lib/top/lab_2/part_4/ip/dds/dds_funcsim.v
// Design : dds
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dds_compiler_v6_0,Vivado 2013.4" *) (* CHECK_LICENSE_TYPE = "dds,dds_compiler_v6_0,{}" *)
(* core_generation_info = "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=42,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=3,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=0,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=8,C_PHASE_ANGLE_WIDTH=8,C_PHASE_INCREMENT=2,C_PHASE_INCREMENT_VALUE=1000000000000000000000000000000000_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=0,C_S_PHASE_TDATA_WIDTH=1,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=8,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}" *)
(* NotValidForBitStream *)
module dds
(aclk,
m_axis_data_tvalid,
m_axis_data_tdata);
input aclk;
output m_axis_data_tvalid;
output [7:0]m_axis_data_tdata;
wire aclk;
wire [7:0]m_axis_data_tdata;
wire m_axis_data_tvalid;
ddsdds_compiler_v6_0__parameterized0 U0
(.aclk(aclk),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tvalid(m_axis_data_tvalid));
endmodule
module ddsaccum
(out,
aclk);
output [7:0]out;
input aclk;
wire aclk;
wire \n_10_i_fabric.i_common.i_phase_acc ;
wire \n_11_i_fabric.i_common.i_phase_acc ;
wire \n_12_i_fabric.i_common.i_phase_acc ;
wire \n_13_i_fabric.i_common.i_phase_acc ;
wire \n_14_i_fabric.i_common.i_phase_acc ;
wire \n_15_i_fabric.i_common.i_phase_acc ;
wire \n_16_i_fabric.i_common.i_phase_acc ;
wire \n_17_i_fabric.i_common.i_phase_acc ;
wire \n_8_i_fabric.i_common.i_phase_acc ;
wire \n_9_i_fabric.i_common.i_phase_acc ;
wire [7:0]out;
wire [42:32]p_0_in;
ddsxbip_pipe_v3_0_viv__parameterized7 \i_fabric.i_common.i_phase_acc
(.L({\n_9_i_fabric.i_common.i_phase_acc ,\n_10_i_fabric.i_common.i_phase_acc ,\n_11_i_fabric.i_common.i_phase_acc ,\n_12_i_fabric.i_common.i_phase_acc ,\n_13_i_fabric.i_common.i_phase_acc ,\n_14_i_fabric.i_common.i_phase_acc ,\n_15_i_fabric.i_common.i_phase_acc ,\n_16_i_fabric.i_common.i_phase_acc ,\n_17_i_fabric.i_common.i_phase_acc }),
.aclk(aclk),
.out({out,\n_8_i_fabric.i_common.i_phase_acc }),
.temp(p_0_in));
ddspipe_add__parameterized0 \i_fabric.i_one_channel.i_accum
(.L({\n_9_i_fabric.i_common.i_phase_acc ,\n_10_i_fabric.i_common.i_phase_acc ,\n_11_i_fabric.i_common.i_phase_acc ,\n_12_i_fabric.i_common.i_phase_acc ,\n_13_i_fabric.i_common.i_phase_acc ,\n_14_i_fabric.i_common.i_phase_acc ,\n_15_i_fabric.i_common.i_phase_acc ,\n_16_i_fabric.i_common.i_phase_acc ,\n_8_i_fabric.i_common.i_phase_acc ,\n_17_i_fabric.i_common.i_phase_acc }),
.temp(p_0_in));
endmodule
(* ORIG_REF_NAME = "dds_compiler_v6_0" *)
module ddsdds_compiler_v6_0__parameterized0
(m_axis_data_tvalid,
m_axis_data_tdata,
aclk);
output m_axis_data_tvalid;
output [7:0]m_axis_data_tdata;
input aclk;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire [7:0]m_axis_data_tdata;
wire m_axis_data_tvalid;
wire NLW_i_synth_debug_axi_resync_in_UNCONNECTED;
wire NLW_i_synth_debug_core_nd_UNCONNECTED;
wire NLW_i_synth_debug_phase_nd_UNCONNECTED;
wire NLW_i_synth_event_phase_in_invalid_UNCONNECTED;
wire NLW_i_synth_event_pinc_invalid_UNCONNECTED;
wire NLW_i_synth_event_poff_invalid_UNCONNECTED;
wire NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED;
wire NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED;
wire NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED;
wire NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED;
wire NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED;
wire NLW_i_synth_m_axis_data_tlast_UNCONNECTED;
wire NLW_i_synth_m_axis_phase_tlast_UNCONNECTED;
wire NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED;
wire NLW_i_synth_s_axis_config_tready_UNCONNECTED;
wire NLW_i_synth_s_axis_phase_tready_UNCONNECTED;
wire [0:0]NLW_i_synth_debug_axi_chan_in_UNCONNECTED;
wire [41:0]NLW_i_synth_debug_axi_pinc_in_UNCONNECTED;
wire [41:0]NLW_i_synth_debug_axi_poff_in_UNCONNECTED;
wire [41:0]NLW_i_synth_debug_phase_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_data_tuser_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_phase_tdata_UNCONNECTED;
wire [0:0]NLW_i_synth_m_axis_phase_tuser_UNCONNECTED;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* C_ACCUMULATOR_WIDTH = "42" *)
(* C_AMPLITUDE = "0" *)
(* C_CHANNELS = "1" *)
(* C_CHAN_WIDTH = "1" *)
(* C_DEBUG_INTERFACE = "0" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_M_DATA = "1" *)
(* C_HAS_M_PHASE = "0" *)
(* C_HAS_PHASEGEN = "1" *)
(* C_HAS_PHASE_OUT = "0" *)
(* C_HAS_SINCOS = "1" *)
(* C_HAS_S_CONFIG = "0" *)
(* C_HAS_S_PHASE = "0" *)
(* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *)
(* C_LATENCY = "3" *)
(* C_MEM_TYPE = "1" *)
(* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "9" *)
(* C_M_DATA_HAS_TUSER = "0" *)
(* C_M_DATA_TDATA_WIDTH = "8" *)
(* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TDATA_WIDTH = "1" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *)
(* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *)
(* C_NOISE_SHAPING = "0" *)
(* C_OPTIMISE_GOAL = "0" *)
(* C_OUTPUTS_REQUIRED = "0" *)
(* C_OUTPUT_FORM = "0" *)
(* C_OUTPUT_WIDTH = "8" *)
(* C_PHASE_ANGLE_WIDTH = "8" *)
(* C_PHASE_INCREMENT = "2" *)
(* C_PHASE_INCREMENT_VALUE = "1000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_PHASE_OFFSET = "0" *)
(* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *)
(* C_POR_MODE = "0" *)
(* C_RESYNC = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *)
(* C_S_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *)
(* C_S_PHASE_TDATA_WIDTH = "1" *)
(* C_S_PHASE_TUSER_WIDTH = "1" *)
(* C_USE_DSP48 = "0" *)
(* C_XDEVICEFAMILY = "zynq" *)
(* downgradeipidentifiedwarnings = "yes" *)
ddsdds_compiler_v6_0_viv__parameterized0 i_synth
(.aclk(aclk),
.aclken(\<const1> ),
.aresetn(\<const1> ),
.debug_axi_chan_in(NLW_i_synth_debug_axi_chan_in_UNCONNECTED[0]),
.debug_axi_pinc_in(NLW_i_synth_debug_axi_pinc_in_UNCONNECTED[41:0]),
.debug_axi_poff_in(NLW_i_synth_debug_axi_poff_in_UNCONNECTED[41:0]),
.debug_axi_resync_in(NLW_i_synth_debug_axi_resync_in_UNCONNECTED),
.debug_core_nd(NLW_i_synth_debug_core_nd_UNCONNECTED),
.debug_phase(NLW_i_synth_debug_phase_UNCONNECTED[41:0]),
.debug_phase_nd(NLW_i_synth_debug_phase_nd_UNCONNECTED),
.event_phase_in_invalid(NLW_i_synth_event_phase_in_invalid_UNCONNECTED),
.event_pinc_invalid(NLW_i_synth_event_pinc_invalid_UNCONNECTED),
.event_poff_invalid(NLW_i_synth_event_poff_invalid_UNCONNECTED),
.event_s_config_tlast_missing(NLW_i_synth_event_s_config_tlast_missing_UNCONNECTED),
.event_s_config_tlast_unexpected(NLW_i_synth_event_s_config_tlast_unexpected_UNCONNECTED),
.event_s_phase_chanid_incorrect(NLW_i_synth_event_s_phase_chanid_incorrect_UNCONNECTED),
.event_s_phase_tlast_missing(NLW_i_synth_event_s_phase_tlast_missing_UNCONNECTED),
.event_s_phase_tlast_unexpected(NLW_i_synth_event_s_phase_tlast_unexpected_UNCONNECTED),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(NLW_i_synth_m_axis_data_tlast_UNCONNECTED),
.m_axis_data_tready(\<const0> ),
.m_axis_data_tuser(NLW_i_synth_m_axis_data_tuser_UNCONNECTED[0]),
.m_axis_data_tvalid(m_axis_data_tvalid),
.m_axis_phase_tdata(NLW_i_synth_m_axis_phase_tdata_UNCONNECTED[0]),
.m_axis_phase_tlast(NLW_i_synth_m_axis_phase_tlast_UNCONNECTED),
.m_axis_phase_tready(\<const0> ),
.m_axis_phase_tuser(NLW_i_synth_m_axis_phase_tuser_UNCONNECTED[0]),
.m_axis_phase_tvalid(NLW_i_synth_m_axis_phase_tvalid_UNCONNECTED),
.s_axis_config_tdata(\<const0> ),
.s_axis_config_tlast(\<const0> ),
.s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED),
.s_axis_config_tvalid(\<const0> ),
.s_axis_phase_tdata(\<const0> ),
.s_axis_phase_tlast(\<const0> ),
.s_axis_phase_tready(NLW_i_synth_s_axis_phase_tready_UNCONNECTED),
.s_axis_phase_tuser(\<const0> ),
.s_axis_phase_tvalid(\<const0> ));
endmodule
module ddsdds_compiler_v6_0_core
(m_axis_data_tdata,
aclk);
output [7:0]m_axis_data_tdata;
input aclk;
wire [41:34]acc_phase_shaped;
wire aclk;
wire [7:0]m_axis_data_tdata;
ddsaccum \I_PHASEGEN.i_conventional_accum.i_accum
(.aclk(aclk),
.out(acc_phase_shaped));
ddssin_cos__parameterized0 \I_SINCOS.i_std_rom.i_rom
(.D(acc_phase_shaped),
.aclk(aclk),
.m_axis_data_tdata(m_axis_data_tdata));
ddsdds_compiler_v6_0_rdy \i_rdy.rdy_logic
(.aclk(aclk));
endmodule
module ddsdds_compiler_v6_0_rdy
(aclk);
input aclk;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire [1:0]mutant_x_op;
wire \n_0_mutant_x_op[0]_i_1 ;
wire \n_0_mutant_x_op[1]_i_1 ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
ddsxbip_pipe_v3_0_viv__parameterized1 \i_single_channel.i_non_trivial_lat.i_rdy
(.aclk(aclk),
.mutant_x_op(mutant_x_op));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h2))
\mutant_x_op[0]_i_1
(.I0(mutant_x_op[1]),
.I1(mutant_x_op[0]),
.O(\n_0_mutant_x_op[0]_i_1 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h8))
\mutant_x_op[1]_i_1
(.I0(mutant_x_op[1]),
.I1(mutant_x_op[0]),
.O(\n_0_mutant_x_op[1]_i_1 ));
FDRE #(
.INIT(1'b0))
\mutant_x_op_reg[0]
(.C(aclk),
.CE(\<const1> ),
.D(\n_0_mutant_x_op[0]_i_1 ),
.Q(mutant_x_op[0]),
.R(\<const0> ));
FDRE #(
.INIT(1'b1))
\mutant_x_op_reg[1]
(.C(aclk),
.CE(\<const1> ),
.D(\n_0_mutant_x_op[1]_i_1 ),
.Q(mutant_x_op[1]),
.R(\<const0> ));
endmodule
(* ORIG_REF_NAME = "dds_compiler_v6_0_viv" *) (* C_XDEVICEFAMILY = "zynq" *) (* C_MODE_OF_OPERATION = "0" *)
(* C_MODULUS = "9" *) (* C_ACCUMULATOR_WIDTH = "42" *) (* C_CHANNELS = "1" *)
(* C_HAS_PHASE_OUT = "0" *) (* C_HAS_PHASEGEN = "1" *) (* C_HAS_SINCOS = "1" *)
(* C_LATENCY = "3" *) (* C_MEM_TYPE = "1" *) (* C_NEGATIVE_COSINE = "0" *)
(* C_NEGATIVE_SINE = "0" *) (* C_NOISE_SHAPING = "0" *) (* C_OUTPUTS_REQUIRED = "0" *)
(* C_OUTPUT_FORM = "0" *) (* C_OUTPUT_WIDTH = "8" *) (* C_PHASE_ANGLE_WIDTH = "8" *)
(* C_PHASE_INCREMENT = "2" *) (* C_PHASE_INCREMENT_VALUE = "1000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_RESYNC = "0" *)
(* C_PHASE_OFFSET = "0" *) (* C_PHASE_OFFSET_VALUE = "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0" *) (* C_OPTIMISE_GOAL = "0" *)
(* C_USE_DSP48 = "0" *) (* C_POR_MODE = "0" *) (* C_AMPLITUDE = "0" *)
(* C_HAS_ACLKEN = "0" *) (* C_HAS_ARESETN = "0" *) (* C_HAS_TLAST = "0" *)
(* C_HAS_TREADY = "0" *) (* C_HAS_S_PHASE = "0" *) (* C_S_PHASE_TDATA_WIDTH = "1" *)
(* C_S_PHASE_HAS_TUSER = "0" *) (* C_S_PHASE_TUSER_WIDTH = "1" *) (* C_HAS_S_CONFIG = "0" *)
(* C_S_CONFIG_SYNC_MODE = "0" *) (* C_S_CONFIG_TDATA_WIDTH = "1" *) (* C_HAS_M_DATA = "1" *)
(* C_M_DATA_TDATA_WIDTH = "8" *) (* C_M_DATA_HAS_TUSER = "0" *) (* C_M_DATA_TUSER_WIDTH = "1" *)
(* C_HAS_M_PHASE = "0" *) (* C_M_PHASE_TDATA_WIDTH = "1" *) (* C_M_PHASE_HAS_TUSER = "0" *)
(* C_M_PHASE_TUSER_WIDTH = "1" *) (* C_DEBUG_INTERFACE = "0" *) (* C_CHAN_WIDTH = "1" *)
(* downgradeipidentifiedwarnings = "yes" *)
module ddsdds_compiler_v6_0_viv__parameterized0
(aclk,
aclken,
aresetn,
s_axis_phase_tvalid,
s_axis_phase_tready,
s_axis_phase_tdata,
s_axis_phase_tlast,
s_axis_phase_tuser,
s_axis_config_tvalid,
s_axis_config_tready,
s_axis_config_tdata,
s_axis_config_tlast,
m_axis_data_tvalid,
m_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tlast,
m_axis_data_tuser,
m_axis_phase_tvalid,
m_axis_phase_tready,
m_axis_phase_tdata,
m_axis_phase_tlast,
m_axis_phase_tuser,
event_pinc_invalid,
event_poff_invalid,
event_phase_in_invalid,
event_s_phase_tlast_missing,
event_s_phase_tlast_unexpected,
event_s_phase_chanid_incorrect,
event_s_config_tlast_missing,
event_s_config_tlast_unexpected,
debug_axi_pinc_in,
debug_axi_poff_in,
debug_axi_resync_in,
debug_axi_chan_in,
debug_core_nd,
debug_phase,
debug_phase_nd);
input aclk;
input aclken;
input aresetn;
input s_axis_phase_tvalid;
output s_axis_phase_tready;
input [0:0]s_axis_phase_tdata;
input s_axis_phase_tlast;
input [0:0]s_axis_phase_tuser;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [0:0]s_axis_config_tdata;
input s_axis_config_tlast;
output m_axis_data_tvalid;
input m_axis_data_tready;
output [7:0]m_axis_data_tdata;
output m_axis_data_tlast;
output [0:0]m_axis_data_tuser;
output m_axis_phase_tvalid;
input m_axis_phase_tready;
output [0:0]m_axis_phase_tdata;
output m_axis_phase_tlast;
output [0:0]m_axis_phase_tuser;
output event_pinc_invalid;
output event_poff_invalid;
output event_phase_in_invalid;
output event_s_phase_tlast_missing;
output event_s_phase_tlast_unexpected;
output event_s_phase_chanid_incorrect;
output event_s_config_tlast_missing;
output event_s_config_tlast_unexpected;
output [41:0]debug_axi_pinc_in;
output [41:0]debug_axi_poff_in;
output debug_axi_resync_in;
output [0:0]debug_axi_chan_in;
output debug_core_nd;
output [41:0]debug_phase;
output debug_phase_nd;
wire \<const0> ;
wire aclk;
wire [7:0]m_axis_data_tdata;
wire m_axis_data_tvalid;
assign debug_axi_chan_in[0] = \<const0> ;
assign debug_axi_pinc_in[41] = \<const0> ;
assign debug_axi_pinc_in[40] = \<const0> ;
assign debug_axi_pinc_in[39] = \<const0> ;
assign debug_axi_pinc_in[38] = \<const0> ;
assign debug_axi_pinc_in[37] = \<const0> ;
assign debug_axi_pinc_in[36] = \<const0> ;
assign debug_axi_pinc_in[35] = \<const0> ;
assign debug_axi_pinc_in[34] = \<const0> ;
assign debug_axi_pinc_in[33] = \<const0> ;
assign debug_axi_pinc_in[32] = \<const0> ;
assign debug_axi_pinc_in[31] = \<const0> ;
assign debug_axi_pinc_in[30] = \<const0> ;
assign debug_axi_pinc_in[29] = \<const0> ;
assign debug_axi_pinc_in[28] = \<const0> ;
assign debug_axi_pinc_in[27] = \<const0> ;
assign debug_axi_pinc_in[26] = \<const0> ;
assign debug_axi_pinc_in[25] = \<const0> ;
assign debug_axi_pinc_in[24] = \<const0> ;
assign debug_axi_pinc_in[23] = \<const0> ;
assign debug_axi_pinc_in[22] = \<const0> ;
assign debug_axi_pinc_in[21] = \<const0> ;
assign debug_axi_pinc_in[20] = \<const0> ;
assign debug_axi_pinc_in[19] = \<const0> ;
assign debug_axi_pinc_in[18] = \<const0> ;
assign debug_axi_pinc_in[17] = \<const0> ;
assign debug_axi_pinc_in[16] = \<const0> ;
assign debug_axi_pinc_in[15] = \<const0> ;
assign debug_axi_pinc_in[14] = \<const0> ;
assign debug_axi_pinc_in[13] = \<const0> ;
assign debug_axi_pinc_in[12] = \<const0> ;
assign debug_axi_pinc_in[11] = \<const0> ;
assign debug_axi_pinc_in[10] = \<const0> ;
assign debug_axi_pinc_in[9] = \<const0> ;
assign debug_axi_pinc_in[8] = \<const0> ;
assign debug_axi_pinc_in[7] = \<const0> ;
assign debug_axi_pinc_in[6] = \<const0> ;
assign debug_axi_pinc_in[5] = \<const0> ;
assign debug_axi_pinc_in[4] = \<const0> ;
assign debug_axi_pinc_in[3] = \<const0> ;
assign debug_axi_pinc_in[2] = \<const0> ;
assign debug_axi_pinc_in[1] = \<const0> ;
assign debug_axi_pinc_in[0] = \<const0> ;
assign debug_axi_poff_in[41] = \<const0> ;
assign debug_axi_poff_in[40] = \<const0> ;
assign debug_axi_poff_in[39] = \<const0> ;
assign debug_axi_poff_in[38] = \<const0> ;
assign debug_axi_poff_in[37] = \<const0> ;
assign debug_axi_poff_in[36] = \<const0> ;
assign debug_axi_poff_in[35] = \<const0> ;
assign debug_axi_poff_in[34] = \<const0> ;
assign debug_axi_poff_in[33] = \<const0> ;
assign debug_axi_poff_in[32] = \<const0> ;
assign debug_axi_poff_in[31] = \<const0> ;
assign debug_axi_poff_in[30] = \<const0> ;
assign debug_axi_poff_in[29] = \<const0> ;
assign debug_axi_poff_in[28] = \<const0> ;
assign debug_axi_poff_in[27] = \<const0> ;
assign debug_axi_poff_in[26] = \<const0> ;
assign debug_axi_poff_in[25] = \<const0> ;
assign debug_axi_poff_in[24] = \<const0> ;
assign debug_axi_poff_in[23] = \<const0> ;
assign debug_axi_poff_in[22] = \<const0> ;
assign debug_axi_poff_in[21] = \<const0> ;
assign debug_axi_poff_in[20] = \<const0> ;
assign debug_axi_poff_in[19] = \<const0> ;
assign debug_axi_poff_in[18] = \<const0> ;
assign debug_axi_poff_in[17] = \<const0> ;
assign debug_axi_poff_in[16] = \<const0> ;
assign debug_axi_poff_in[15] = \<const0> ;
assign debug_axi_poff_in[14] = \<const0> ;
assign debug_axi_poff_in[13] = \<const0> ;
assign debug_axi_poff_in[12] = \<const0> ;
assign debug_axi_poff_in[11] = \<const0> ;
assign debug_axi_poff_in[10] = \<const0> ;
assign debug_axi_poff_in[9] = \<const0> ;
assign debug_axi_poff_in[8] = \<const0> ;
assign debug_axi_poff_in[7] = \<const0> ;
assign debug_axi_poff_in[6] = \<const0> ;
assign debug_axi_poff_in[5] = \<const0> ;
assign debug_axi_poff_in[4] = \<const0> ;
assign debug_axi_poff_in[3] = \<const0> ;
assign debug_axi_poff_in[2] = \<const0> ;
assign debug_axi_poff_in[1] = \<const0> ;
assign debug_axi_poff_in[0] = \<const0> ;
assign debug_axi_resync_in = \<const0> ;
assign debug_core_nd = \<const0> ;
assign debug_phase[41] = \<const0> ;
assign debug_phase[40] = \<const0> ;
assign debug_phase[39] = \<const0> ;
assign debug_phase[38] = \<const0> ;
assign debug_phase[37] = \<const0> ;
assign debug_phase[36] = \<const0> ;
assign debug_phase[35] = \<const0> ;
assign debug_phase[34] = \<const0> ;
assign debug_phase[33] = \<const0> ;
assign debug_phase[32] = \<const0> ;
assign debug_phase[31] = \<const0> ;
assign debug_phase[30] = \<const0> ;
assign debug_phase[29] = \<const0> ;
assign debug_phase[28] = \<const0> ;
assign debug_phase[27] = \<const0> ;
assign debug_phase[26] = \<const0> ;
assign debug_phase[25] = \<const0> ;
assign debug_phase[24] = \<const0> ;
assign debug_phase[23] = \<const0> ;
assign debug_phase[22] = \<const0> ;
assign debug_phase[21] = \<const0> ;
assign debug_phase[20] = \<const0> ;
assign debug_phase[19] = \<const0> ;
assign debug_phase[18] = \<const0> ;
assign debug_phase[17] = \<const0> ;
assign debug_phase[16] = \<const0> ;
assign debug_phase[15] = \<const0> ;
assign debug_phase[14] = \<const0> ;
assign debug_phase[13] = \<const0> ;
assign debug_phase[12] = \<const0> ;
assign debug_phase[11] = \<const0> ;
assign debug_phase[10] = \<const0> ;
assign debug_phase[9] = \<const0> ;
assign debug_phase[8] = \<const0> ;
assign debug_phase[7] = \<const0> ;
assign debug_phase[6] = \<const0> ;
assign debug_phase[5] = \<const0> ;
assign debug_phase[4] = \<const0> ;
assign debug_phase[3] = \<const0> ;
assign debug_phase[2] = \<const0> ;
assign debug_phase[1] = \<const0> ;
assign debug_phase[0] = \<const0> ;
assign debug_phase_nd = \<const0> ;
assign event_phase_in_invalid = \<const0> ;
assign event_pinc_invalid = \<const0> ;
assign event_poff_invalid = \<const0> ;
assign event_s_config_tlast_missing = \<const0> ;
assign event_s_config_tlast_unexpected = \<const0> ;
assign event_s_phase_chanid_incorrect = \<const0> ;
assign event_s_phase_tlast_missing = \<const0> ;
assign event_s_phase_tlast_unexpected = \<const0> ;
assign m_axis_data_tlast = \<const0> ;
assign m_axis_data_tuser[0] = \<const0> ;
assign m_axis_phase_tdata[0] = \<const0> ;
assign m_axis_phase_tlast = \<const0> ;
assign m_axis_phase_tuser[0] = \<const0> ;
assign m_axis_phase_tvalid = \<const0> ;
assign s_axis_config_tready = \<const0> ;
assign s_axis_phase_tready = \<const0> ;
GND GND
(.G(\<const0> ));
ddsdds_compiler_v6_0_core i_dds
(.aclk(aclk),
.m_axis_data_tdata(m_axis_data_tdata));
ddsxbip_pipe_v3_0_viv \i_has_nd_rdy_pipe.channel_pipe
(.aclk(aclk));
ddsxbip_pipe_v3_0_viv_0 \i_has_nd_rdy_pipe.valid_phase_read_del
(.aclk(aclk),
.m_axis_data_tvalid(m_axis_data_tvalid));
endmodule
(* ORIG_REF_NAME = "pipe_add" *)
module ddspipe_add__parameterized0
(temp,
L);
output [10:0]temp;
input [9:0]L;
wire \<const0> ;
wire \<const1> ;
wire [9:0]L;
wire \n_0_opt_has_pipe.first_q[35]_i_4 ;
wire \n_0_opt_has_pipe.first_q_reg[35]_i_1 ;
wire \n_0_opt_has_pipe.first_q_reg[39]_i_1 ;
wire \n_1_opt_has_pipe.first_q_reg[35]_i_1 ;
wire \n_1_opt_has_pipe.first_q_reg[39]_i_1 ;
wire \n_2_opt_has_pipe.first_q_reg[35]_i_1 ;
wire \n_2_opt_has_pipe.first_q_reg[39]_i_1 ;
wire \n_3_opt_has_pipe.first_q_reg[35]_i_1 ;
wire \n_3_opt_has_pipe.first_q_reg[39]_i_1 ;
wire \n_3_opt_has_pipe.first_q_reg[42]_i_1 ;
wire [10:0]temp;
wire [3:1]\NLW_opt_has_pipe.first_q_reg[42]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_opt_has_pipe.first_q_reg[42]_i_1_O_UNCONNECTED ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
LUT1 #(
.INIT(2'h1))
\opt_has_pipe.first_q[35]_i_4
(.I0(L[1]),
.O(\n_0_opt_has_pipe.first_q[35]_i_4 ));
CARRY4 \opt_has_pipe.first_q_reg[35]_i_1
(.CI(\<const0> ),
.CO({\n_0_opt_has_pipe.first_q_reg[35]_i_1 ,\n_1_opt_has_pipe.first_q_reg[35]_i_1 ,\n_2_opt_has_pipe.first_q_reg[35]_i_1 ,\n_3_opt_has_pipe.first_q_reg[35]_i_1 }),
.CYINIT(\<const0> ),
.DI({\<const0> ,\<const0> ,L[1],\<const0> }),
.O(temp[3:0]),
.S({L[3:2],\n_0_opt_has_pipe.first_q[35]_i_4 ,L[0]}));
CARRY4 \opt_has_pipe.first_q_reg[39]_i_1
(.CI(\n_0_opt_has_pipe.first_q_reg[35]_i_1 ),
.CO({\n_0_opt_has_pipe.first_q_reg[39]_i_1 ,\n_1_opt_has_pipe.first_q_reg[39]_i_1 ,\n_2_opt_has_pipe.first_q_reg[39]_i_1 ,\n_3_opt_has_pipe.first_q_reg[39]_i_1 }),
.CYINIT(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.O(temp[7:4]),
.S(L[7:4]));
CARRY4 \opt_has_pipe.first_q_reg[42]_i_1
(.CI(\n_0_opt_has_pipe.first_q_reg[39]_i_1 ),
.CO({\NLW_opt_has_pipe.first_q_reg[42]_i_1_CO_UNCONNECTED [3],temp[10],\NLW_opt_has_pipe.first_q_reg[42]_i_1_CO_UNCONNECTED [1],\n_3_opt_has_pipe.first_q_reg[42]_i_1 }),
.CYINIT(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.O({\NLW_opt_has_pipe.first_q_reg[42]_i_1_O_UNCONNECTED [3:2],temp[9:8]}),
.S({\<const0> ,\<const1> ,L[9:8]}));
endmodule
(* ORIG_REF_NAME = "sin_cos" *)
module ddssin_cos__parameterized0
(m_axis_data_tdata,
aclk,
D);
output [7:0]m_axis_data_tdata;
input aclk;
input [7:0]D;
wire \<const0> ;
wire \<const1> ;
wire [7:0]D;
wire [8:0]Q;
wire aclk;
wire [7:0]m_axis_data_tdata;
wire [15:8]\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOADO_UNCONNECTED ;
wire [15:0]\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOBDO_UNCONNECTED ;
wire [1:0]\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPADOP_UNCONNECTED ;
wire [1:0]\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPBDOP_UNCONNECTED ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
ddsxbip_pipe_v3_0_viv__parameterized11_1 \i_rtl.i_double_table.i_addr_reg_a
(.D(D),
.aclk(aclk),
.out(Q));
ddsxbip_pipe_v3_0_viv__parameterized11 \i_rtl.i_double_table.i_addr_reg_b
(.D(D),
.aclk(aclk));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell inst1}}" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "35" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h002F002C0029002600230020001D001A001700140011000E000B000800050002),
.INIT_01(256'h0058005600530051004F004C004A004700450042003F003D003A003700340032),
.INIT_02(256'h0074007300710070006E006D006B006A00680066006400620060005E005C005A),
.INIT_03(256'h007E007E007E007E007D007D007C007C007B007B007A00790078007700760075),
.INIT_04(256'h00750076007700780079007A007B007B007C007C007D007D007E007E007E007E),
.INIT_05(256'h005A005C005E00600062006400660068006A006B006D006E0070007100730074),
.INIT_06(256'h003200340037003A003D003F004200450047004A004C004F0051005300560058),
.INIT_07(256'h000200050008000B000E001100140017001A001D0020002300260029002C002F),
.INIT_08(256'h00D100D400D700DA00DD00E000E300E600E900EC00EF00F200F500F800FB00FE),
.INIT_09(256'h00A800AA00AD00AF00B100B400B600B900BB00BE00C100C300C600C900CC00CE),
.INIT_0A(256'h008C008D008F009000920093009500960098009A009C009E00A000A200A400A6),
.INIT_0B(256'h00820082008200820083008300840084008500850086008700880089008A008B),
.INIT_0C(256'h008B008A00890088008700860085008500840084008300830082008200820082),
.INIT_0D(256'h00A600A400A200A0009E009C009A009800960095009300920090008F008D008C),
.INIT_0E(256'h00CE00CC00C900C600C300C100BE00BB00B900B600B400B100AF00AD00AA00A8),
.INIT_0F(256'h00FE00FB00F800F500F200EF00EC00E900E600E300E000DD00DA00D700D400D1),
.INIT_10(256'h00750076007700780079007A007B007B007C007C007D007D007E007E007E007E),
.INIT_11(256'h005A005C005E00600062006400660068006A006B006D006E0070007100730074),
.INIT_12(256'h003200340037003A003D003F004200450047004A004C004F0051005300560058),
.INIT_13(256'h000200050008000B000E001100140017001A001D0020002300260029002C002F),
.INIT_14(256'h00D100D400D700DA00DD00E000E300E600E900EC00EF00F200F500F800FB00FE),
.INIT_15(256'h00A800AA00AD00AF00B100B400B600B900BB00BE00C100C300C600C900CC00CE),
.INIT_16(256'h008C008D008F009000920093009500960098009A009C009E00A000A200A400A6),
.INIT_17(256'h00820082008200820083008300840084008500850086008700880089008A008B),
.INIT_18(256'h008B008A00890088008700860085008500840084008300830082008200820082),
.INIT_19(256'h00A600A400A200A0009E009C009A009800960095009300920090008F008D008C),
.INIT_1A(256'h00CE00CC00C900C600C300C100BE00BB00B900B600B400B100AF00AD00AA00A8),
.INIT_1B(256'h00FE00FB00F800F500F200EF00EC00E900E600E300E000DD00DA00D700D400D1),
.INIT_1C(256'h002F002C0029002600230020001D001A001700140011000E000B000800050002),
.INIT_1D(256'h0058005600530051004F004C004A004700450042003F003D003A003700340032),
.INIT_1E(256'h0074007300710070006E006D006B006A00680066006400620060005E005C005A),
.INIT_1F(256'h007E007E007E007E007D007D007C007C007B007B007A00790078007700760075),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
\i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg
(.ADDRARDADDR({\<const0> ,Q,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.ADDRBWRADDR({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }),
.CLKARDCLK(aclk),
.CLKBWRCLK(\<const0> ),
.DIADI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }),
.DIBDI({\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> ,\<const1> }),
.DIPADIP({\<const0> ,\<const0> }),
.DIPBDIP({\<const1> ,\<const1> }),
.DOADO({\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOADO_UNCONNECTED [15:8],m_axis_data_tdata}),
.DOBDO(\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOBDO_UNCONNECTED [15:0]),
.DOPADOP(\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPADOP_UNCONNECTED [1:0]),
.DOPBDOP(\NLW_i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_DOPBDOP_UNCONNECTED [1:0]),
.ENARDEN(\<const1> ),
.ENBWREN(\<const0> ),
.REGCEAREGCE(\<const0> ),
.REGCEB(\<const0> ),
.RSTRAMARSTRAM(\<const0> ),
.RSTRAMB(\<const0> ),
.RSTREGARSTREG(\<const0> ),
.RSTREGB(\<const0> ),
.WEA({\<const0> ,\<const0> }),
.WEBWE({\<const0> ,\<const0> ,\<const0> ,\<const0> }));
endmodule
module ddsxbip_pipe_v3_0_viv
(aclk);
input aclk;
wire \<const0> ;
wire \<const1> ;
wire aclk;
(* RTL_KEEP = "true" *) wire first_q;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[0]
(.C(aclk),
.CE(\<const1> ),
.D(\<const0> ),
.Q(first_q),
.R(\<const0> ));
endmodule
(* ORIG_REF_NAME = "xbip_pipe_v3_0_viv" *)
module ddsxbip_pipe_v3_0_viv_0
(m_axis_data_tvalid,
aclk);
output m_axis_data_tvalid;
input aclk;
wire \<const0> ;
wire \<const1> ;
wire aclk;
(* RTL_KEEP = "true" *) wire first_q;
wire m_axis_data_tvalid;
wire \pipe[2] ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[0]
(.C(aclk),
.CE(\<const1> ),
.D(\<const1> ),
.Q(first_q),
.R(\<const0> ));
FDRE #(
.INIT(1'b0))
\opt_has_pipe.i_pipe[2].pipe_reg[2][0]
(.C(aclk),
.CE(\<const1> ),
.D(first_q),
.Q(\pipe[2] ),
.R(\<const0> ));
FDRE #(
.INIT(1'b0))
\opt_has_pipe.i_pipe[3].pipe_reg[3][0]
(.C(aclk),
.CE(\<const1> ),
.D(\pipe[2] ),
.Q(m_axis_data_tvalid),
.R(\<const0> ));
endmodule
(* ORIG_REF_NAME = "xbip_pipe_v3_0_viv" *)
module ddsxbip_pipe_v3_0_viv__parameterized1
(aclk,
mutant_x_op);
input aclk;
input [1:0]mutant_x_op;
wire \<const0> ;
wire \<const1> ;
wire aclk;
(* RTL_KEEP = "true" *) wire first_q;
wire [1:0]mutant_x_op;
wire pre_rdy;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
LUT2 #(
.INIT(4'h1))
\opt_has_pipe.first_q[0]_i_1
(.I0(mutant_x_op[0]),
.I1(mutant_x_op[1]),
.O(pre_rdy));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[0]
(.C(aclk),
.CE(\<const1> ),
.D(pre_rdy),
.Q(first_q),
.R(\<const0> ));
endmodule
(* ORIG_REF_NAME = "xbip_pipe_v3_0_viv" *)
module ddsxbip_pipe_v3_0_viv__parameterized11
(aclk,
D);
input aclk;
input [7:0]D;
wire \<const0> ;
wire \<const1> ;
wire [7:0]D;
wire aclk;
(* RTL_KEEP = "true" *) wire [8:0]first_q;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[0]
(.C(aclk),
.CE(\<const1> ),
.D(D[0]),
.Q(first_q[0]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[1]
(.C(aclk),
.CE(\<const1> ),
.D(D[1]),
.Q(first_q[1]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[2]
(.C(aclk),
.CE(\<const1> ),
.D(D[2]),
.Q(first_q[2]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[3]
(.C(aclk),
.CE(\<const1> ),
.D(D[3]),
.Q(first_q[3]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[4]
(.C(aclk),
.CE(\<const1> ),
.D(D[4]),
.Q(first_q[4]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[5]
(.C(aclk),
.CE(\<const1> ),
.D(D[5]),
.Q(first_q[5]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[6]
(.C(aclk),
.CE(\<const1> ),
.D(D[6]),
.Q(first_q[6]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[7]
(.C(aclk),
.CE(\<const1> ),
.D(D[7]),
.Q(first_q[7]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[8]
(.C(aclk),
.CE(\<const1> ),
.D(\<const1> ),
.Q(first_q[8]),
.R(\<const0> ));
endmodule
(* ORIG_REF_NAME = "xbip_pipe_v3_0_viv" *)
module ddsxbip_pipe_v3_0_viv__parameterized11_1
(out,
aclk,
D);
output [8:0]out;
input aclk;
input [7:0]D;
wire \<const0> ;
wire \<const1> ;
wire [7:0]D;
wire aclk;
(* RTL_KEEP = "true" *) wire [8:0]first_q;
wire [8:0]out;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(first_q[8]),
.O(out[8]));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(first_q[7]),
.O(out[7]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(first_q[6]),
.O(out[6]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(first_q[5]),
.O(out[5]));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(first_q[4]),
.O(out[4]));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(first_q[3]),
.O(out[3]));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(first_q[2]),
.O(out[2]));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(first_q[1]),
.O(out[1]));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(first_q[0]),
.O(out[0]));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[0]
(.C(aclk),
.CE(\<const1> ),
.D(D[0]),
.Q(first_q[0]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[1]
(.C(aclk),
.CE(\<const1> ),
.D(D[1]),
.Q(first_q[1]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[2]
(.C(aclk),
.CE(\<const1> ),
.D(D[2]),
.Q(first_q[2]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[3]
(.C(aclk),
.CE(\<const1> ),
.D(D[3]),
.Q(first_q[3]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[4]
(.C(aclk),
.CE(\<const1> ),
.D(D[4]),
.Q(first_q[4]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[5]
(.C(aclk),
.CE(\<const1> ),
.D(D[5]),
.Q(first_q[5]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[6]
(.C(aclk),
.CE(\<const1> ),
.D(D[6]),
.Q(first_q[6]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[7]
(.C(aclk),
.CE(\<const1> ),
.D(D[7]),
.Q(first_q[7]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[8]
(.C(aclk),
.CE(\<const1> ),
.D(\<const0> ),
.Q(first_q[8]),
.R(\<const0> ));
endmodule
(* ORIG_REF_NAME = "xbip_pipe_v3_0_viv" *)
module ddsxbip_pipe_v3_0_viv__parameterized7
(out,
L,
temp,
aclk);
output [8:0]out;
output [8:0]L;
input [10:0]temp;
input aclk;
wire \<const0> ;
wire \<const1> ;
wire [8:0]L;
wire aclk;
(* RTL_KEEP = "true" *) wire [42:0]first_q;
wire [8:0]out;
wire [10:0]temp;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(first_q[41]),
.O(out[8]));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(first_q[40]),
.O(out[7]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(first_q[39]),
.O(out[6]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(first_q[38]),
.O(out[5]));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(first_q[37]),
.O(out[4]));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(first_q[36]),
.O(out[3]));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(first_q[35]),
.O(out[2]));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(first_q[34]),
.O(out[1]));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(first_q[33]),
.O(out[0]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[35]_i_2
(.I0(first_q[35]),
.O(L[2]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[35]_i_3
(.I0(first_q[34]),
.O(L[1]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[35]_i_5
(.I0(first_q[32]),
.O(L[0]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[39]_i_2
(.I0(first_q[39]),
.O(L[6]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[39]_i_3
(.I0(first_q[38]),
.O(L[5]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[39]_i_4
(.I0(first_q[37]),
.O(L[4]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[39]_i_5
(.I0(first_q[36]),
.O(L[3]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[42]_i_2
(.I0(first_q[41]),
.O(L[8]));
LUT1 #(
.INIT(2'h2))
\opt_has_pipe.first_q[42]_i_3
(.I0(first_q[40]),
.O(L[7]));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[0]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[0]),
.Q(first_q[0]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[10]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[10]),
.Q(first_q[10]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[11]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[11]),
.Q(first_q[11]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[12]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[12]),
.Q(first_q[12]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[13]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[13]),
.Q(first_q[13]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[14]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[14]),
.Q(first_q[14]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[15]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[15]),
.Q(first_q[15]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[16]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[16]),
.Q(first_q[16]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[17]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[17]),
.Q(first_q[17]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[18]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[18]),
.Q(first_q[18]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[19]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[19]),
.Q(first_q[19]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[1]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[1]),
.Q(first_q[1]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[20]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[20]),
.Q(first_q[20]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[21]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[21]),
.Q(first_q[21]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[22]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[22]),
.Q(first_q[22]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[23]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[23]),
.Q(first_q[23]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[24]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[24]),
.Q(first_q[24]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[25]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[25]),
.Q(first_q[25]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[26]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[26]),
.Q(first_q[26]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[27]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[27]),
.Q(first_q[27]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[28]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[28]),
.Q(first_q[28]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[29]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[29]),
.Q(first_q[29]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[2]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[2]),
.Q(first_q[2]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[30]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[30]),
.Q(first_q[30]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[31]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[31]),
.Q(first_q[31]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[32]
(.C(aclk),
.CE(\<const1> ),
.D(temp[0]),
.Q(first_q[32]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[33]
(.C(aclk),
.CE(\<const1> ),
.D(temp[1]),
.Q(first_q[33]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[34]
(.C(aclk),
.CE(\<const1> ),
.D(temp[2]),
.Q(first_q[34]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[35]
(.C(aclk),
.CE(\<const1> ),
.D(temp[3]),
.Q(first_q[35]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[36]
(.C(aclk),
.CE(\<const1> ),
.D(temp[4]),
.Q(first_q[36]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[37]
(.C(aclk),
.CE(\<const1> ),
.D(temp[5]),
.Q(first_q[37]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[38]
(.C(aclk),
.CE(\<const1> ),
.D(temp[6]),
.Q(first_q[38]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[39]
(.C(aclk),
.CE(\<const1> ),
.D(temp[7]),
.Q(first_q[39]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[3]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[3]),
.Q(first_q[3]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[40]
(.C(aclk),
.CE(\<const1> ),
.D(temp[8]),
.Q(first_q[40]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[41]
(.C(aclk),
.CE(\<const1> ),
.D(temp[9]),
.Q(first_q[41]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[42]
(.C(aclk),
.CE(\<const1> ),
.D(temp[10]),
.Q(first_q[42]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[4]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[4]),
.Q(first_q[4]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[5]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[5]),
.Q(first_q[5]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[6]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[6]),
.Q(first_q[6]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[7]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[7]),
.Q(first_q[7]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[8]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[8]),
.Q(first_q[8]),
.R(\<const0> ));
(* keep = "yes" *)
FDRE #(
.INIT(1'b0))
\opt_has_pipe.first_q_reg[9]
(.C(aclk),
.CE(\<const1> ),
.D(first_q[9]),
.Q(first_q[9]),
.R(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (
input wire CLK,
output reg RESET
);
neg neg (.clk(CLK));
little little (.clk(CLK));
glbl glbl ();
// A vector
logic [2:1] vec [4:3];
integer val = 0;
always @ (posedge CLK) begin
if (RESET) val <= 0;
else val <= val + 1;
vec[3] <= val[1:0];
vec[4] <= val[3:2];
end
initial RESET = 1'b1;
always @ (posedge CLK)
RESET <= glbl.GSR;
endmodule
module glbl();
`ifdef PUB_FUNC
reg GSR;
task setGSR;
/* verilator public */
input value;
GSR = value;
endtask
`else
reg GSR /*verilator public*/;
`endif
endmodule
module neg (
input clk
);
reg [0:-7] i8; initial i8 = '0;
reg [-1:-48] i48; initial i48 = '0;
reg [63:-64] i128; initial i128 = '0;
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
module little (
input clk
);
// verilator lint_off LITENDIAN
reg [0:7] i8; initial i8 = '0;
reg [1:49] i48; initial i48 = '0;
reg [63:190] i128; initial i128 = '0;
// verilator lint_on LITENDIAN
always @ (posedge clk) begin
i8 <= ~i8;
i48 <= ~i48;
i128 <= ~i128;
end
endmodule
|
`timescale 1ns / 1ns
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:28:18 02/06/2014
// Design Name:
// Module Name: test1
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tld_zxuno (
input wire clk50mhz,
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire csync,
output wire stdn,
output wire stdnb
);
assign stdn = 1'b0;
assign stdnb = 1'b1;
// Generación de relojes
reg [1:0] divs = 2'b00;
wire wssclk,sysclk;
wire clk14 = divs[0];
wire clk7 = divs[1];
always @(posedge sysclk)
divs <= divs + 1;
relojes los_relojes_del_sistema (
.CLKIN_IN(clk50mhz),
.CLKDV_OUT(wssclk),
.CLKFX_OUT(sysclk),
.CLKIN_IBUFG_OUT(),
.CLK0_OUT(),
.LOCKED_OUT()
);
// Instanciación del sistema
zxuno la_maquina (
.clk(clk7),
.wssclk(wssclk),
.r(r),
.g(g),
.b(b),
.csync(csync)
);
endmodule
|
//
// Conformal-LEC Version 15.20-d227 ( 10-Mar-2016) ( 64 bit executable)
//
module top ( n0 , n1 , n2 , n3 , n4 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 , n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 );
input n0 , n1 , n2 , n3 , n4 , n6 , n7 , n8 , n9 , n10 , n11 , n12 , n13 , n14 , n15 , n16 , n17 , n18 , n19 , n20 , n21 , n22 , n23 , n24 , n25 , n26 , n27 , n28 , n29 , n30 , n31 , n32 , n33 , n34 , n35 , n36 , n37 , n38 , n39 , n40 , n41 , n42 ;
output n43 , n44 , n45 , n46 , n47 , n48 , n49 , n50 , n51 , n52 , n53 , n54 , n55 , n56 , n57 , n58 ;
wire n118 , n119 , n120 , n121 , n122 , n123 , n124 , n125 , n126 ,
n127 , n128 , n129 , n130 , n131 , n132 , n133 , n134 , n135 , n136 ,
n137 , n138 , n139 , n140 , n141 , n142 , n143 , n144 , n145 , n146 ,
n147 , n148 , n149 , n150 , n151 , n152 , n153 , n154 , n155 , n156 ,
n157 , n158 , n159 , n160 , n161 , n162 , n163 , n164 , n165 , n166 ,
n167 , n168 , n169 , n170 , n171 , n172 , n173 , n174 , n175 , n176 ,
n177 , n178 , n179 , n180 , n181 , n182 , n183 , n184 , n185 , n186 ,
n187 , n188 , n189 , n190 , n191 , n192 , n193 , n194 , n195 , n196 ,
n197 , n198 , n199 , n200 , n201 , n202 , n203 , n204 , n205 , n206 ,
n207 , n208 , n209 , n210 , n211 , n212 , n213 , n214 , n215 , n216 ,
n217 , n218 , n219 , n220 , n221 , n222 , n223 , n224 , n225 , n226 ,
n227 , n228 , n229 , n230 , n231 , n232 , n233 , n234 , n235 , n236 ,
n237 , n238 , n239 , n240 , n241 , n242 , n243 , n244 , n245 , n246 ,
n247 , n248 , n249 , n250 , n251 , n252 , n253 , n254 , n255 , n256 ,
n257 , n258 , n259 , n260 , n261 , n262 , n263 , n264 , n265 , n266 ,
n267 , n268 , n269 , n270 , n271 , n272 , n273 , n274 , n275 , n276 ,
n277 , n278 , n279 , n280 , n281 , n282 , n283 , n284 , n285 , n286 ,
n287 , n288 , n289 , n290 , n291 , n292 , n293 , n294 , n295 , n296 ,
n297 , n298 , n299 , n300 , n301 , n302 , n303 , n304 , n305 , n306 ,
n307 , n308 , n309 , n310 , n311 , n312 , n313 , n314 , n315 , n316 ,
n317 , n318 , n319 , n320 , n321 , n322 , n323 , n324 , n325 , n326 ,
n327 , n328 , n329 , n330 , n331 , n332 , n333 , n334 , n335 , n336 ,
n337 , n338 , n339 , n340 , n341 , n342 , n343 , n344 , n345 , n346 ,
n347 , n348 , n349 , n350 , n351 , n352 , n353 , n354 , n355 , n356 ,
n357 , n358 , n359 , n360 , n361 , n362 , n363 , n364 , n365 , n366 ,
n367 , n368 , n369 , n370 , n371 , n372 , n373 , n374 , n375 , n376 ,
n377 , n378 , n379 , n380 , n381 , n382 , n383 , n384 , n385 , n386 ,
n387 , n388 , n389 , n390 , n391 , n392 , n393 , n394 , n395 , n396 ,
n397 , n398 , n399 , n400 , n401 , n402 , n403 , n404 , n405 , n406 ,
n407 , n408 , n409 , n410 , n411 , n412 , n413 , n414 , n415 , n416 ,
n417 , n418 , n419 , n420 , n421 , n422 , n423 , n424 , n425 , n426 ,
n427 , n428 , n429 , n430 , n431 , n432 , n433 , n434 , n435 , n436 ,
n437 , n438 , n439 , n440 , n441 ;
buf ( n53 , n382 );
buf ( n43 , n386 );
buf ( n58 , n390 );
buf ( n56 , n394 );
buf ( n52 , n398 );
buf ( n51 , n402 );
buf ( n44 , n406 );
buf ( n50 , n410 );
buf ( n45 , n414 );
buf ( n47 , n418 );
buf ( n49 , n422 );
buf ( n55 , n426 );
buf ( n57 , n430 );
buf ( n48 , n434 );
buf ( n54 , n438 );
buf ( n46 , n441 );
buf ( n120 , n4 );
buf ( n121 , n25 );
buf ( n122 , n40 );
buf ( n123 , n24 );
buf ( n124 , n3 );
buf ( n125 , n38 );
buf ( n126 , n9 );
buf ( n127 , n39 );
buf ( n128 , n33 );
buf ( n129 , n14 );
buf ( n130 , n17 );
buf ( n131 , n2 );
buf ( n132 , n15 );
buf ( n133 , n10 );
buf ( n134 , n37 );
buf ( n135 , n32 );
buf ( n136 , n31 );
buf ( n137 , n19 );
buf ( n138 , n8 );
buf ( n139 , n7 );
buf ( n140 , n18 );
buf ( n141 , n21 );
buf ( n142 , n12 );
buf ( n143 , n23 );
buf ( n144 , n34 );
buf ( n145 , n36 );
buf ( n146 , n1 );
buf ( n147 , n42 );
buf ( n148 , n11 );
buf ( n149 , n30 );
buf ( n150 , n20 );
buf ( n151 , n35 );
buf ( n152 , n26 );
buf ( n153 , n13 );
buf ( n154 , n16 );
buf ( n155 , n0 );
buf ( n156 , n41 );
buf ( n157 , n28 );
buf ( n158 , n22 );
buf ( n159 , n27 );
buf ( n160 , n29 );
buf ( n161 , n6 );
buf ( n162 , n120 );
buf ( n163 , n121 );
buf ( n164 , n122 );
buf ( n165 , n123 );
buf ( n166 , n152 );
and ( n167 , n165 , n166 );
buf ( n168 , n124 );
buf ( n169 , n153 );
and ( n170 , n168 , n169 );
buf ( n171 , n125 );
buf ( n172 , n154 );
and ( n173 , n171 , n172 );
buf ( n174 , n126 );
buf ( n175 , n155 );
and ( n176 , n174 , n175 );
buf ( n177 , n127 );
buf ( n178 , n156 );
and ( n179 , n177 , n178 );
buf ( n180 , n128 );
buf ( n181 , n157 );
and ( n182 , n180 , n181 );
buf ( n183 , n129 );
buf ( n184 , n158 );
and ( n185 , n183 , n184 );
buf ( n186 , n130 );
buf ( n187 , n159 );
and ( n188 , n186 , n187 );
buf ( n189 , n131 );
buf ( n190 , n160 );
and ( n191 , n189 , n190 );
buf ( n192 , n132 );
buf ( n193 , n161 );
and ( n194 , n192 , n193 );
buf ( n195 , n133 );
buf ( n196 , n134 );
buf ( n197 , n135 );
or ( n198 , n196 , n197 );
or ( n199 , n195 , n198 );
and ( n200 , n193 , n199 );
and ( n201 , n192 , n199 );
or ( n202 , n194 , n200 , n201 );
and ( n203 , n190 , n202 );
and ( n204 , n189 , n202 );
or ( n205 , n191 , n203 , n204 );
and ( n206 , n187 , n205 );
and ( n207 , n186 , n205 );
or ( n208 , n188 , n206 , n207 );
and ( n209 , n184 , n208 );
and ( n210 , n183 , n208 );
or ( n211 , n185 , n209 , n210 );
and ( n212 , n181 , n211 );
and ( n213 , n180 , n211 );
or ( n214 , n182 , n212 , n213 );
and ( n215 , n178 , n214 );
and ( n216 , n177 , n214 );
or ( n217 , n179 , n215 , n216 );
and ( n218 , n175 , n217 );
and ( n219 , n174 , n217 );
or ( n220 , n176 , n218 , n219 );
and ( n221 , n172 , n220 );
and ( n222 , n171 , n220 );
or ( n223 , n173 , n221 , n222 );
and ( n224 , n169 , n223 );
and ( n225 , n168 , n223 );
or ( n226 , n170 , n224 , n225 );
and ( n227 , n166 , n226 );
and ( n228 , n165 , n226 );
or ( n229 , n167 , n227 , n228 );
and ( n230 , n164 , n229 );
and ( n231 , n163 , n230 );
xor ( n232 , n162 , n231 );
buf ( n233 , n232 );
buf ( n234 , n233 );
buf ( n235 , n136 );
not ( n236 , n235 );
xor ( n237 , n234 , n236 );
xor ( n238 , n163 , n230 );
buf ( n239 , n238 );
buf ( n240 , n239 );
buf ( n241 , n137 );
not ( n242 , n241 );
and ( n243 , n240 , n242 );
xor ( n244 , n164 , n229 );
buf ( n245 , n244 );
buf ( n246 , n245 );
buf ( n247 , n138 );
not ( n248 , n247 );
and ( n249 , n246 , n248 );
xor ( n250 , n165 , n166 );
xor ( n251 , n250 , n226 );
buf ( n252 , n251 );
buf ( n253 , n252 );
buf ( n254 , n139 );
not ( n255 , n254 );
and ( n256 , n253 , n255 );
xor ( n257 , n168 , n169 );
xor ( n258 , n257 , n223 );
buf ( n259 , n258 );
buf ( n260 , n259 );
buf ( n261 , n140 );
not ( n262 , n261 );
and ( n263 , n260 , n262 );
xor ( n264 , n171 , n172 );
xor ( n265 , n264 , n220 );
buf ( n266 , n265 );
buf ( n267 , n266 );
buf ( n268 , n141 );
not ( n269 , n268 );
and ( n270 , n267 , n269 );
xor ( n271 , n174 , n175 );
xor ( n272 , n271 , n217 );
buf ( n273 , n272 );
buf ( n274 , n273 );
buf ( n275 , n142 );
not ( n276 , n275 );
and ( n277 , n274 , n276 );
xor ( n278 , n177 , n178 );
xor ( n279 , n278 , n214 );
buf ( n280 , n279 );
buf ( n281 , n280 );
buf ( n282 , n143 );
not ( n283 , n282 );
and ( n284 , n281 , n283 );
xor ( n285 , n180 , n181 );
xor ( n286 , n285 , n211 );
buf ( n287 , n286 );
buf ( n288 , n287 );
buf ( n289 , n144 );
not ( n290 , n289 );
and ( n291 , n288 , n290 );
xor ( n292 , n183 , n184 );
xor ( n293 , n292 , n208 );
buf ( n294 , n293 );
buf ( n295 , n294 );
buf ( n296 , n145 );
not ( n297 , n296 );
and ( n298 , n295 , n297 );
xor ( n299 , n186 , n187 );
xor ( n300 , n299 , n205 );
buf ( n301 , n300 );
buf ( n302 , n301 );
buf ( n303 , n146 );
not ( n304 , n303 );
and ( n305 , n302 , n304 );
xor ( n306 , n189 , n190 );
xor ( n307 , n306 , n202 );
buf ( n308 , n307 );
buf ( n309 , n308 );
buf ( n310 , n147 );
not ( n311 , n310 );
and ( n312 , n309 , n311 );
xor ( n313 , n192 , n193 );
xor ( n314 , n313 , n199 );
buf ( n315 , n314 );
buf ( n316 , n315 );
buf ( n317 , n148 );
not ( n318 , n317 );
and ( n319 , n316 , n318 );
xnor ( n320 , n195 , n198 );
buf ( n321 , n320 );
buf ( n322 , n321 );
buf ( n323 , n149 );
not ( n324 , n323 );
and ( n325 , n322 , n324 );
xnor ( n326 , n196 , n197 );
buf ( n327 , n326 );
buf ( n328 , n327 );
buf ( n329 , n150 );
not ( n330 , n329 );
and ( n331 , n328 , n330 );
not ( n332 , n197 );
buf ( n333 , n332 );
buf ( n334 , n333 );
buf ( n335 , n151 );
not ( n336 , n335 );
or ( n337 , n334 , n336 );
and ( n338 , n330 , n337 );
and ( n339 , n328 , n337 );
or ( n340 , n331 , n338 , n339 );
and ( n341 , n324 , n340 );
and ( n342 , n322 , n340 );
or ( n343 , n325 , n341 , n342 );
and ( n344 , n318 , n343 );
and ( n345 , n316 , n343 );
or ( n346 , n319 , n344 , n345 );
and ( n347 , n311 , n346 );
and ( n348 , n309 , n346 );
or ( n349 , n312 , n347 , n348 );
and ( n350 , n304 , n349 );
and ( n351 , n302 , n349 );
or ( n352 , n305 , n350 , n351 );
and ( n353 , n297 , n352 );
and ( n354 , n295 , n352 );
or ( n355 , n298 , n353 , n354 );
and ( n356 , n290 , n355 );
and ( n357 , n288 , n355 );
or ( n358 , n291 , n356 , n357 );
and ( n359 , n283 , n358 );
and ( n360 , n281 , n358 );
or ( n361 , n284 , n359 , n360 );
and ( n362 , n276 , n361 );
and ( n363 , n274 , n361 );
or ( n364 , n277 , n362 , n363 );
and ( n365 , n269 , n364 );
and ( n366 , n267 , n364 );
or ( n367 , n270 , n365 , n366 );
and ( n368 , n262 , n367 );
and ( n369 , n260 , n367 );
or ( n370 , n263 , n368 , n369 );
and ( n371 , n255 , n370 );
and ( n372 , n253 , n370 );
or ( n373 , n256 , n371 , n372 );
and ( n374 , n248 , n373 );
and ( n375 , n246 , n373 );
or ( n376 , n249 , n374 , n375 );
and ( n377 , n242 , n376 );
and ( n378 , n240 , n376 );
or ( n379 , n243 , n377 , n378 );
xor ( n380 , n237 , n379 );
buf ( n381 , n380 );
buf ( n382 , n381 );
xor ( n383 , n240 , n242 );
xor ( n384 , n383 , n376 );
buf ( n385 , n384 );
buf ( n386 , n385 );
xor ( n387 , n246 , n248 );
xor ( n388 , n387 , n373 );
buf ( n389 , n388 );
buf ( n390 , n389 );
xor ( n391 , n253 , n255 );
xor ( n392 , n391 , n370 );
buf ( n393 , n392 );
buf ( n394 , n393 );
xor ( n395 , n260 , n262 );
xor ( n396 , n395 , n367 );
buf ( n397 , n396 );
buf ( n398 , n397 );
xor ( n399 , n267 , n269 );
xor ( n400 , n399 , n364 );
buf ( n401 , n400 );
buf ( n402 , n401 );
xor ( n403 , n274 , n276 );
xor ( n404 , n403 , n361 );
buf ( n405 , n404 );
buf ( n406 , n405 );
xor ( n407 , n281 , n283 );
xor ( n408 , n407 , n358 );
buf ( n409 , n408 );
buf ( n410 , n409 );
xor ( n411 , n288 , n290 );
xor ( n412 , n411 , n355 );
buf ( n413 , n412 );
buf ( n414 , n413 );
xor ( n415 , n295 , n297 );
xor ( n416 , n415 , n352 );
buf ( n417 , n416 );
buf ( n418 , n417 );
xor ( n419 , n302 , n304 );
xor ( n420 , n419 , n349 );
buf ( n421 , n420 );
buf ( n422 , n421 );
xor ( n423 , n309 , n311 );
xor ( n424 , n423 , n346 );
buf ( n425 , n424 );
buf ( n426 , n425 );
xor ( n427 , n316 , n318 );
xor ( n428 , n427 , n343 );
buf ( n429 , n428 );
buf ( n430 , n429 );
xor ( n431 , n322 , n324 );
xor ( n432 , n431 , n340 );
buf ( n433 , n432 );
buf ( n434 , n433 );
xor ( n435 , n328 , n330 );
xor ( n436 , n435 , n337 );
buf ( n437 , n436 );
buf ( n438 , n437 );
xor ( n439 , n334 , n335 );
buf ( n440 , n439 );
buf ( n441 , n440 );
endmodule
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs_pma_gige.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs_pma_gige_phyip.v,v $
//
// $Revision: #17 $
// $Date: 2010/10/07 $
// Check in by : $Author: aishak $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level MAC + PCS + PMA module for Triple Speed Ethernet MAC + PCS + PMA
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//Legal Notice: (C)2007 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs_pma_gige_phyip /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
// inputs:
address,
clk,
ff_rx_clk,
ff_rx_rdy,
ff_tx_clk,
ff_tx_crc_fwd,
ff_tx_data,
ff_tx_mod,
ff_tx_eop,
ff_tx_err,
ff_tx_sop,
ff_tx_wren,
magic_sleep_n,
mdio_in,
read,
reconfig_togxb,
ref_clk,
reset,
rxp,
write,
writedata,
xoff_gen,
xon_gen,
// outputs:
ff_rx_a_empty,
ff_rx_a_full,
ff_rx_data,
ff_rx_mod,
ff_rx_dsav,
ff_rx_dval,
ff_rx_eop,
ff_rx_sop,
ff_tx_a_empty,
ff_tx_a_full,
ff_tx_rdy,
ff_tx_septy,
led_an,
led_char_err,
led_col,
led_crs,
led_disp_err,
led_link,
magic_wakeup,
mdc,
mdio_oen,
mdio_out,
readdata,
reconfig_fromgxb,
rx_err,
rx_err_stat,
rx_frm_type,
tx_ff_uflow,
txp,
rx_recovclkout,
waitrequest,
// phy_mgmt_interface
phy_mgmt_address,
phy_mgmt_read,
phy_mgmt_readdata,
phy_mgmt_waitrequest,
phy_mgmt_write,
phy_mgmt_writedata
);
// Parameters to configure the core for different variations
// ---------------------------------------------------------
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hask Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // MorethanIP Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 1; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;// PHY Identifier
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter EXPORT_PWRDN = 1'b0; // Option to export the Alt2gxb powerdown signal
parameter DEVICE_FAMILY = "ARRIAGX"; // The device family the the core is targetted for.
parameter TRANSCEIVER_OPTION = 1'b0; // Option to select transceiver block for MAC PCS PMA Instantiation. Valid Values are 0 and 1: 0 - GXB (GIGE Mode) 1 - LVDS I/O
parameter ENABLE_ALT_RECONFIG = 0; // Option to have the Alt_Reconfig ports exposed
parameter STARTING_CHANNEL_NUMBER = 0; // Starting Channel Number for Reconfig block
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
output ff_rx_a_empty;
output ff_rx_a_full;
output [ENABLE_ENA-1:0] ff_rx_data;
output [1:0] ff_rx_mod;
output ff_rx_dsav;
output ff_rx_dval;
output ff_rx_eop;
output ff_rx_sop;
output ff_tx_a_empty;
output ff_tx_a_full;
output ff_tx_rdy;
output ff_tx_septy;
output led_an;
output led_char_err;
output led_col;
output led_crs;
output led_disp_err;
output led_link;
output magic_wakeup;
output mdc;
output mdio_oen;
output mdio_out;
output [31: 0] readdata;
output [91:0] reconfig_fromgxb;
output [5: 0] rx_err;
output [17: 0] rx_err_stat;
output [3: 0] rx_frm_type;
output tx_ff_uflow;
output txp;
output rx_recovclkout;
output waitrequest;
input [7: 0] address;
input clk;
input ff_rx_clk;
input ff_rx_rdy;
input ff_tx_clk;
input ff_tx_crc_fwd;
input [ENABLE_ENA-1:0] ff_tx_data;
input [1:0] ff_tx_mod;
input ff_tx_eop;
input ff_tx_err;
input ff_tx_sop;
input ff_tx_wren;
input magic_sleep_n;
input mdio_in;
input read;
input [139:0] reconfig_togxb;
input ref_clk;
input reset;
input rxp;
input write;
input [31:0] writedata;
input xoff_gen;
input xon_gen;
input [8:0] phy_mgmt_address;
input phy_mgmt_read;
output [31:0] phy_mgmt_readdata;
output phy_mgmt_waitrequest;
input phy_mgmt_write;
input [31:0]phy_mgmt_writedata;
wire MAC_PCS_reset;
wire ff_rx_a_empty;
wire ff_rx_a_full;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_eop;
wire ff_rx_sop;
wire ff_tx_a_empty;
wire ff_tx_a_full;
wire ff_tx_rdy;
wire ff_tx_septy;
wire gige_pma_reset;
wire led_an;
wire led_char_err;
wire led_char_err_gx;
wire led_col;
wire led_crs;
wire led_disp_err;
wire led_link;
wire link_status;
wire magic_wakeup;
wire mdc;
wire mdio_oen;
wire mdio_out;
wire rx_pcs_clk;
wire tx_pcs_clk;
wire [7:0] pcs_rx_frame;
wire pcs_rx_kchar;
wire pcs_pwrdn_out_sig;
wire gxb_pwrdn_in_sig;
wire gxb_cal_blk_clk_sig;
wire [31:0] readdata;
wire rx_char_err_gx;
wire rx_disp_err;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire [7:0] rx_frame;
wire rx_syncstatus;
wire rx_kchar;
wire sd_loopback;
wire tx_ff_uflow;
wire [7:0] tx_frame;
wire tx_kchar;
wire txp;
wire rx_recovclkout;
wire waitrequest;
wire rx_runlengthviolation;
wire rx_patterndetect;
wire rx_runningdisp;
wire rx_rmfifodatadeleted;
wire rx_rmfifodatainserted;
wire pcs_rx_carrierdetected;
wire pcs_rx_rmfifodatadeleted;
wire pcs_rx_rmfifodatainserted;
wire [91:0] reconfig_fromgxb;
wire reset_ref_clk;
wire reset_rx_pcs_clk_int;
// Assign the character error and link status to top level leds
// ------------------------------------------------------------
assign led_char_err = led_char_err_gx;
assign led_link = link_status;
// Instantiation of the MAC_PCS core that connects to a PMA
// --------------------------------------------------------
altera_tse_mac_pcs_pma_strx_gx_ena altera_tse_mac_pcs_pma_strx_gx_ena_inst
(
.rx_carrierdetected(pcs_rx_carrierdetected),
.rx_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.rx_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.address (address),
.clk (clk),
.ff_rx_a_empty (ff_rx_a_empty),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_clk (ff_rx_clk),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_eop (ff_rx_eop),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_sop (ff_rx_sop),
.ff_tx_a_empty (ff_tx_a_empty),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_clk (ff_tx_clk),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_sop (ff_tx_sop),
.ff_tx_wren (ff_tx_wren),
.led_an (led_an),
.led_char_err (led_char_err_gx),
.led_col (led_col),
.led_crs (led_crs),
.led_link (link_status),
.magic_sleep_n (magic_sleep_n),
.magic_wakeup (magic_wakeup),
.mdc (mdc),
.mdio_in (mdio_in),
.mdio_oen (mdio_oen),
.mdio_out (mdio_out),
.powerdown (pcs_pwrdn_out_sig),
.read (read),
.readdata (readdata),
.reset (reset),
.rx_clkout (rx_pcs_clk),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frame (pcs_rx_frame),
.rx_frm_type (rx_frm_type),
.rx_kchar (pcs_rx_kchar),
.sd_loopback (sd_loopback),
.tx_clkout (tx_pcs_clk),
.tx_ff_uflow (tx_ff_uflow),
.tx_frame (tx_frame),
.tx_kchar (tx_kchar),
.waitrequest (waitrequest),
.write (write),
.writedata (writedata),
.xoff_gen (xoff_gen),
.xon_gen (xon_gen)
);
defparam
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_ENA = ENABLE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.USE_SYNC_RESET = USE_SYNC_RESET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENA_HASH = ENA_HASH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.STAT_CNT_ENA = STAT_CNT_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_FIFO = EG_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.EG_ADDR = EG_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_FIFO = ING_FIFO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ING_ADDR = ING_ADDR,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RESET_LEVEL = RESET_LEVEL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CORE_VERSION = CORE_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CUST_VERSION = CUST_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MDIO = ENABLE_MDIO,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MACLITE = ENABLE_MACLITE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.MACLITE_GIGE = MACLITE_GIGE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32DWIDTH = CRC32DWIDTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.CRC32GENDELAY = CRC32GENDELAY,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.INSERT_TA = INSERT_TA,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.RAM_TYPE = RAM_TYPE,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.DEV_VERSION = DEV_VERSION,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_SGMII = ENABLE_SGMII,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
altera_tse_mac_pcs_pma_strx_gx_ena_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
// Instantiation of the Alt2gxb block as the PMA for Stratix_II_GX and ArriaGX devices
// -----------------------------------------------------------------------------------
altera_tse_reset_synchronizer ch_0_reset_sync_0 (
.clk(rx_pcs_clk),
.reset_in(reset),
.reset_out(reset_rx_pcs_clk_int)
);
// Aligned Rx_sync from gxb
// -------------------------------
altera_tse_gxb_aligned_rxsync the_altera_tse_gxb_aligned_rxsync
(
.clk(rx_pcs_clk),
.reset(reset_rx_pcs_clk_int),
//input (from alt2gxb)
.alt_dataout(rx_frame),
.alt_sync(rx_syncstatus),
.alt_disperr(rx_disp_err),
.alt_ctrldetect(rx_kchar),
.alt_errdetect(rx_char_err_gx),
.alt_rmfifodatadeleted(rx_rmfifodatadeleted),
.alt_rmfifodatainserted(rx_rmfifodatainserted),
.alt_runlengthviolation(rx_runlengthviolation),
.alt_patterndetect(rx_patterndetect),
.alt_runningdisp(rx_runningdisp),
//output (to PCS)
.altpcs_dataout(pcs_rx_frame),
.altpcs_sync(link_status),
.altpcs_disperr(led_disp_err),
.altpcs_ctrldetect(pcs_rx_kchar),
.altpcs_errdetect(led_char_err_gx),
.altpcs_rmfifodatadeleted(pcs_rx_rmfifodatadeleted),
.altpcs_rmfifodatainserted(pcs_rx_rmfifodatainserted),
.altpcs_carrierdetect(pcs_rx_carrierdetected)
) ;
defparam
the_altera_tse_gxb_aligned_rxsync.DEVICE_FAMILY = DEVICE_FAMILY;
// Custom PhyIP
// ------------------------------------------
altera_tse_gxb_gige_phyip_inst the_altera_tse_gxb_gige_phyip_inst(
.phy_mgmt_clk(clk), // phy_mgmt_clk.clk
.phy_mgmt_clk_reset(reset), // phy_mgmt_clk_reset.reset
.phy_mgmt_address(phy_mgmt_address), // phy_mgmt.address
.phy_mgmt_read(phy_mgmt_read), // .read
.phy_mgmt_readdata(phy_mgmt_readdata), // .readdata
.phy_mgmt_waitrequest(phy_mgmt_waitrequest), // .waitrequest
.phy_mgmt_write(phy_mgmt_write), // .write
.phy_mgmt_writedata(phy_mgmt_writedata), // .writedata
.tx_ready(), // tx_ready.export
.rx_ready(), // rx_ready.export
.pll_ref_clk(ref_clk), // pll_ref_clk.clk
.pll_locked(), // pll_locked.export
.tx_serial_data(txp), // tx_serial_data.export
.rx_serial_data(rxp), // rx_serial_data.export
.rx_runningdisp(rx_runningdisp), // rx_runningdisp.export
.rx_disperr(rx_disp_err), // rx_disperr.export
.rx_errdetect(rx_char_err_gx), // rx_errdetect.export
.rx_patterndetect(rx_patterndetect), // rx_patterndetect.export
.rx_syncstatus(rx_syncstatus), // rx_syncstatus.export
.tx_clkout(tx_pcs_clk), // tx_clkout0.clk
.rx_clkout(rx_pcs_clk), // rx_clkout0.clk
.tx_parallel_data(tx_frame), // tx_parallel_data0.data
.tx_datak(tx_kchar), // tx_datak0.data
.rx_parallel_data(rx_frame), // rx_parallel_data0.data
.rx_datak(rx_kchar), // rx_datak0.data
.rx_rlv(rx_runlengthviolation),
.rx_recovclkout(rx_recovclkout),
.rx_rmfifodatadeleted(rx_rmfifodatadeleted),
.rx_rmfifodatainserted(rx_rmfifodatainserted),
.reconfig_togxb(reconfig_togxb),
.reconfig_fromgxb(reconfig_fromgxb)
);
defparam
the_altera_tse_gxb_gige_phyip_inst.ENABLE_ALT_RECONFIG = ENABLE_ALT_RECONFIG,
the_altera_tse_gxb_gige_phyip_inst.DEVICE_FAMILY = DEVICE_FAMILY,
the_altera_tse_gxb_gige_phyip_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfbbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFBBP_PP_SYMBOL_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.3
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 64-Deep by 8-bit Wide Multi Port RAM
// /___/ /\ Filename : RAM64M8.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/02/12 - Initial version, from RAM64M
// 09/17/12 - 678604 - fix compilation errors
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAM64M8 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [63:0] INIT_A = 64'h0000000000000000,
parameter [63:0] INIT_B = 64'h0000000000000000,
parameter [63:0] INIT_C = 64'h0000000000000000,
parameter [63:0] INIT_D = 64'h0000000000000000,
parameter [63:0] INIT_E = 64'h0000000000000000,
parameter [63:0] INIT_F = 64'h0000000000000000,
parameter [63:0] INIT_G = 64'h0000000000000000,
parameter [63:0] INIT_H = 64'h0000000000000000,
parameter [0:0] IS_WCLK_INVERTED = 1'b0
)(
output DOA,
output DOB,
output DOC,
output DOD,
output DOE,
output DOF,
output DOG,
output DOH,
input [5:0] ADDRA,
input [5:0] ADDRB,
input [5:0] ADDRC,
input [5:0] ADDRD,
input [5:0] ADDRE,
input [5:0] ADDRF,
input [5:0] ADDRG,
input [5:0] ADDRH,
input DIA,
input DIB,
input DIC,
input DID,
input DIE,
input DIF,
input DIG,
input DIH,
input WCLK,
input WE
);
// define constants
localparam MODULE_NAME = "RAM64M8";
reg trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire IS_WCLK_INVERTED_BIN;
wire [5:0] ADDRH_in;
wire DIA_in;
wire DIB_in;
wire DIC_in;
wire DID_in;
wire DIE_in;
wire DIF_in;
wire DIG_in;
wire DIH_in;
wire WCLK_in;
wire WE_in;
`ifdef XIL_TIMING
wire [5:0] ADDRH_dly;
wire DIA_dly;
wire DIB_dly;
wire DIC_dly;
wire DID_dly;
wire DIE_dly;
wire DIF_dly;
wire DIG_dly;
wire DIH_dly;
wire WCLK_dly;
wire WE_dly;
reg notifier;
wire sh_clk_en_p;
wire sh_clk_en_n;
wire sh_we_clk_en_p;
wire sh_we_clk_en_n;
assign ADDRH_in = ADDRH_dly;
assign DIA_in = DIA_dly;
assign DIB_in = DIB_dly;
assign DIC_in = DIC_dly;
assign DID_in = DID_dly;
assign DIE_in = DIE_dly;
assign DIF_in = DIF_dly;
assign DIG_in = DIG_dly;
assign DIH_in = DIH_dly;
assign WCLK_in = WCLK_dly ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE_dly; // rv 1
`else
assign ADDRH_in = ADDRH;
assign DIA_in = DIA;
assign DIB_in = DIB;
assign DIC_in = DIC;
assign DID_in = DID;
assign DIE_in = DIE;
assign DIF_in = DIF;
assign DIG_in = DIG;
assign DIH_in = DIH;
assign WCLK_in = WCLK ^ IS_WCLK_INVERTED_BIN;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign IS_WCLK_INVERTED_BIN = IS_WCLK_INVERTED;
reg [63:0] mem_a, mem_b, mem_c, mem_d;
reg [63:0] mem_e, mem_f, mem_g, mem_h;
initial begin
mem_a = INIT_A;
mem_b = INIT_B;
mem_c = INIT_C;
mem_d = INIT_D;
mem_e = INIT_E;
mem_f = INIT_F;
mem_g = INIT_G;
mem_h = INIT_H;
end
always @(posedge WCLK_in)
if (WE_in) begin
mem_a[ADDRH_in] <= #100 DIA_in;
mem_b[ADDRH_in] <= #100 DIB_in;
mem_c[ADDRH_in] <= #100 DIC_in;
mem_d[ADDRH_in] <= #100 DID_in;
mem_e[ADDRH_in] <= #100 DIE_in;
mem_f[ADDRH_in] <= #100 DIF_in;
mem_g[ADDRH_in] <= #100 DIG_in;
mem_h[ADDRH_in] <= #100 DIH_in;
end
assign DOA = mem_a[ADDRA];
assign DOB = mem_b[ADDRB];
assign DOC = mem_c[ADDRC];
assign DOD = mem_d[ADDRD];
assign DOE = mem_e[ADDRE];
assign DOF = mem_f[ADDRF];
assign DOG = mem_g[ADDRG];
assign DOH = mem_h[ADDRH_in];
`ifdef XIL_TIMING
always @(notifier) begin
mem_a[ADDRH_in] <= 1'bx;
mem_b[ADDRH_in] <= 1'bx;
mem_c[ADDRH_in] <= 1'bx;
mem_d[ADDRH_in] <= 1'bx;
mem_e[ADDRH_in] <= 1'bx;
mem_f[ADDRH_in] <= 1'bx;
mem_g[ADDRH_in] <= 1'bx;
mem_h[ADDRH_in] <= 1'bx;
end
assign sh_clk_en_p = ~IS_WCLK_INVERTED_BIN;
assign sh_clk_en_n = IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_p = WE_in && ~IS_WCLK_INVERTED_BIN;
assign sh_we_clk_en_n = WE_in && IS_WCLK_INVERTED_BIN;
specify
(WCLK => DOA) = (0:0:0, 0:0:0);
(WCLK => DOB) = (0:0:0, 0:0:0);
(WCLK => DOC) = (0:0:0, 0:0:0);
(WCLK => DOD) = (0:0:0, 0:0:0);
(WCLK => DOE) = (0:0:0, 0:0:0);
(WCLK => DOF) = (0:0:0, 0:0:0);
(WCLK => DOG) = (0:0:0, 0:0:0);
(WCLK => DOH) = (0:0:0, 0:0:0);
(ADDRA *> DOA) = (0:0:0, 0:0:0);
(ADDRB *> DOB) = (0:0:0, 0:0:0);
(ADDRC *> DOC) = (0:0:0, 0:0:0);
(ADDRD *> DOD) = (0:0:0, 0:0:0);
(ADDRE *> DOE) = (0:0:0, 0:0:0);
(ADDRF *> DOF) = (0:0:0, 0:0:0);
(ADDRG *> DOG) = (0:0:0, 0:0:0);
(ADDRH *> DOH) = (0:0:0, 0:0:0);
$period (negedge WCLK &&& WE, 0:0:0, notifier);
$period (posedge WCLK &&& WE, 0:0:0, notifier);
$setuphold (negedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, negedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[5]);
$setuphold (negedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, negedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly);
$setuphold (negedge WCLK, negedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly);
$setuphold (negedge WCLK, negedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly);
$setuphold (negedge WCLK, negedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly);
$setuphold (negedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (negedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[0]);
$setuphold (negedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[1]);
$setuphold (negedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[2]);
$setuphold (negedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[3]);
$setuphold (negedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[4]);
$setuphold (negedge WCLK, posedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,ADDRH_dly[5]);
$setuphold (negedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIA_dly);
$setuphold (negedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIB_dly);
$setuphold (negedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIC_dly);
$setuphold (negedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DID_dly);
$setuphold (negedge WCLK, posedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIE_dly);
$setuphold (negedge WCLK, posedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIF_dly);
$setuphold (negedge WCLK, posedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIG_dly);
$setuphold (negedge WCLK, posedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_n,sh_we_clk_en_n,WCLK_dly,DIH_dly);
$setuphold (negedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_n,sh_clk_en_n,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, negedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, negedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, negedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, negedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, negedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, negedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[5]);
$setuphold (posedge WCLK, negedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, negedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, negedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, negedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, negedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly);
$setuphold (posedge WCLK, negedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly);
$setuphold (posedge WCLK, negedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly);
$setuphold (posedge WCLK, negedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly);
$setuphold (posedge WCLK, negedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
$setuphold (posedge WCLK, posedge ADDRH[0], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[0]);
$setuphold (posedge WCLK, posedge ADDRH[1], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[1]);
$setuphold (posedge WCLK, posedge ADDRH[2], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[2]);
$setuphold (posedge WCLK, posedge ADDRH[3], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[3]);
$setuphold (posedge WCLK, posedge ADDRH[4], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[4]);
$setuphold (posedge WCLK, posedge ADDRH[5], 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,ADDRH_dly[5]);
$setuphold (posedge WCLK, posedge DIA, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIA_dly);
$setuphold (posedge WCLK, posedge DIB, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIB_dly);
$setuphold (posedge WCLK, posedge DIC, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIC_dly);
$setuphold (posedge WCLK, posedge DID, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DID_dly);
$setuphold (posedge WCLK, posedge DIE, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIE_dly);
$setuphold (posedge WCLK, posedge DIF, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIF_dly);
$setuphold (posedge WCLK, posedge DIG, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIG_dly);
$setuphold (posedge WCLK, posedge DIH, 0:0:0, 0:0:0, notifier,sh_we_clk_en_p,sh_we_clk_en_p,WCLK_dly,DIH_dly);
$setuphold (posedge WCLK, posedge WE, 0:0:0, 0:0:0, notifier,sh_clk_en_p,sh_clk_en_p,WCLK_dly,WE_dly);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// nios_system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 186 at 2016.05.04.10:35:24
`timescale 1 ps / 1 ps
module nios_system_mm_interconnect_0 (
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire nios2_qsys_0_reset_reset_bridge_in_reset_reset, // nios2_qsys_0_reset_reset_bridge_in_reset.reset
input wire [18:0] nios2_qsys_0_data_master_address, // nios2_qsys_0_data_master.address
output wire nios2_qsys_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_qsys_0_data_master_byteenable, // .byteenable
input wire nios2_qsys_0_data_master_read, // .read
output wire [31:0] nios2_qsys_0_data_master_readdata, // .readdata
input wire nios2_qsys_0_data_master_write, // .write
input wire [31:0] nios2_qsys_0_data_master_writedata, // .writedata
input wire nios2_qsys_0_data_master_debugaccess, // .debugaccess
input wire [18:0] nios2_qsys_0_instruction_master_address, // nios2_qsys_0_instruction_master.address
output wire nios2_qsys_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_qsys_0_instruction_master_read, // .read
output wire [31:0] nios2_qsys_0_instruction_master_readdata, // .readdata
output wire [1:0] alu_a_s1_address, // alu_a_s1.address
output wire alu_a_s1_write, // .write
input wire [31:0] alu_a_s1_readdata, // .readdata
output wire [31:0] alu_a_s1_writedata, // .writedata
output wire alu_a_s1_chipselect, // .chipselect
output wire [1:0] alu_b_s1_address, // alu_b_s1.address
output wire alu_b_s1_write, // .write
input wire [31:0] alu_b_s1_readdata, // .readdata
output wire [31:0] alu_b_s1_writedata, // .writedata
output wire alu_b_s1_chipselect, // .chipselect
output wire [1:0] alu_carry_out_s1_address, // alu_carry_out_s1.address
input wire [31:0] alu_carry_out_s1_readdata, // .readdata
output wire [1:0] alu_control_s1_address, // alu_control_s1.address
output wire alu_control_s1_write, // .write
input wire [31:0] alu_control_s1_readdata, // .readdata
output wire [31:0] alu_control_s1_writedata, // .writedata
output wire alu_control_s1_chipselect, // .chipselect
output wire [1:0] alu_negative_s1_address, // alu_negative_s1.address
input wire [31:0] alu_negative_s1_readdata, // .readdata
output wire [1:0] alu_out_s1_address, // alu_out_s1.address
input wire [31:0] alu_out_s1_readdata, // .readdata
output wire [1:0] alu_overflow_s1_address, // alu_overflow_s1.address
input wire [31:0] alu_overflow_s1_readdata, // .readdata
output wire [1:0] alu_zero_s1_address, // alu_zero_s1.address
input wire [31:0] alu_zero_s1_readdata, // .readdata
output wire [1:0] hex_0_s1_address, // hex_0_s1.address
output wire hex_0_s1_write, // .write
input wire [31:0] hex_0_s1_readdata, // .readdata
output wire [31:0] hex_0_s1_writedata, // .writedata
output wire hex_0_s1_chipselect, // .chipselect
output wire [1:0] hex_1_s1_address, // hex_1_s1.address
output wire hex_1_s1_write, // .write
input wire [31:0] hex_1_s1_readdata, // .readdata
output wire [31:0] hex_1_s1_writedata, // .writedata
output wire hex_1_s1_chipselect, // .chipselect
output wire [1:0] hex_2_s1_address, // hex_2_s1.address
output wire hex_2_s1_write, // .write
input wire [31:0] hex_2_s1_readdata, // .readdata
output wire [31:0] hex_2_s1_writedata, // .writedata
output wire hex_2_s1_chipselect, // .chipselect
output wire [1:0] hex_3_s1_address, // hex_3_s1.address
output wire hex_3_s1_write, // .write
input wire [31:0] hex_3_s1_readdata, // .readdata
output wire [31:0] hex_3_s1_writedata, // .writedata
output wire hex_3_s1_chipselect, // .chipselect
output wire [1:0] hex_4_s1_address, // hex_4_s1.address
output wire hex_4_s1_write, // .write
input wire [31:0] hex_4_s1_readdata, // .readdata
output wire [31:0] hex_4_s1_writedata, // .writedata
output wire hex_4_s1_chipselect, // .chipselect
output wire [1:0] hex_5_s1_address, // hex_5_s1.address
output wire hex_5_s1_write, // .write
input wire [31:0] hex_5_s1_readdata, // .readdata
output wire [31:0] hex_5_s1_writedata, // .writedata
output wire hex_5_s1_chipselect, // .chipselect
output wire [0:0] jtag_uart_0_avalon_jtag_slave_address, // jtag_uart_0_avalon_jtag_slave.address
output wire jtag_uart_0_avalon_jtag_slave_write, // .write
output wire jtag_uart_0_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_0_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_0_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_0_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_0_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] keys_s1_address, // keys_s1.address
input wire [31:0] keys_s1_readdata, // .readdata
output wire [1:0] LEDs_s1_address, // LEDs_s1.address
output wire LEDs_s1_write, // .write
input wire [31:0] LEDs_s1_readdata, // .readdata
output wire [31:0] LEDs_s1_writedata, // .writedata
output wire LEDs_s1_chipselect, // .chipselect
output wire [8:0] nios2_qsys_0_debug_mem_slave_address, // nios2_qsys_0_debug_mem_slave.address
output wire nios2_qsys_0_debug_mem_slave_write, // .write
output wire nios2_qsys_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_qsys_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_qsys_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_qsys_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_qsys_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_qsys_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [14:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [1:0] regfile_data_s1_address, // regfile_data_s1.address
output wire regfile_data_s1_write, // .write
input wire [31:0] regfile_data_s1_readdata, // .readdata
output wire [31:0] regfile_data_s1_writedata, // .writedata
output wire regfile_data_s1_chipselect, // .chipselect
output wire [1:0] regfile_r1sel_s1_address, // regfile_r1sel_s1.address
output wire regfile_r1sel_s1_write, // .write
input wire [31:0] regfile_r1sel_s1_readdata, // .readdata
output wire [31:0] regfile_r1sel_s1_writedata, // .writedata
output wire regfile_r1sel_s1_chipselect, // .chipselect
output wire [1:0] regfile_r2sel_s1_address, // regfile_r2sel_s1.address
output wire regfile_r2sel_s1_write, // .write
input wire [31:0] regfile_r2sel_s1_readdata, // .readdata
output wire [31:0] regfile_r2sel_s1_writedata, // .writedata
output wire regfile_r2sel_s1_chipselect, // .chipselect
output wire [1:0] regfile_reg1_s1_address, // regfile_reg1_s1.address
input wire [31:0] regfile_reg1_s1_readdata, // .readdata
output wire [1:0] regfile_reg2_s1_address, // regfile_reg2_s1.address
input wire [31:0] regfile_reg2_s1_readdata, // .readdata
output wire [1:0] regfile_we_s1_address, // regfile_we_s1.address
output wire regfile_we_s1_write, // .write
input wire [31:0] regfile_we_s1_readdata, // .readdata
output wire [31:0] regfile_we_s1_writedata, // .writedata
output wire regfile_we_s1_chipselect, // .chipselect
output wire [1:0] regfile_wsel_s1_address, // regfile_wsel_s1.address
output wire regfile_wsel_s1_write, // .write
input wire [31:0] regfile_wsel_s1_readdata, // .readdata
output wire [31:0] regfile_wsel_s1_writedata, // .writedata
output wire regfile_wsel_s1_chipselect, // .chipselect
output wire [1:0] sram_addr_s1_address, // sram_addr_s1.address
output wire sram_addr_s1_write, // .write
input wire [31:0] sram_addr_s1_readdata, // .readdata
output wire [31:0] sram_addr_s1_writedata, // .writedata
output wire sram_addr_s1_chipselect, // .chipselect
output wire [1:0] sram_cs_s1_address, // sram_cs_s1.address
output wire sram_cs_s1_write, // .write
input wire [31:0] sram_cs_s1_readdata, // .readdata
output wire [31:0] sram_cs_s1_writedata, // .writedata
output wire sram_cs_s1_chipselect, // .chipselect
output wire [1:0] sram_data_s1_address, // sram_data_s1.address
output wire sram_data_s1_write, // .write
input wire [31:0] sram_data_s1_readdata, // .readdata
output wire [31:0] sram_data_s1_writedata, // .writedata
output wire sram_data_s1_chipselect, // .chipselect
output wire [1:0] sram_oe_s1_address, // sram_oe_s1.address
output wire sram_oe_s1_write, // .write
input wire [31:0] sram_oe_s1_readdata, // .readdata
output wire [31:0] sram_oe_s1_writedata, // .writedata
output wire sram_oe_s1_chipselect, // .chipselect
output wire [1:0] sram_read_write_s1_address, // sram_read_write_s1.address
output wire sram_read_write_s1_write, // .write
input wire [31:0] sram_read_write_s1_readdata, // .readdata
output wire [31:0] sram_read_write_s1_writedata, // .writedata
output wire sram_read_write_s1_chipselect, // .chipselect
output wire [1:0] switches_s1_address, // switches_s1.address
input wire [31:0] switches_s1_readdata // .readdata
);
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_data_master_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_data_master_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_agent:av_debugaccess
wire [18:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_agent:av_address
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_agent:av_read
wire [3:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_agent:av_byteenable
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_data_master_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_agent:av_lock
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_agent:av_write
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_agent:av_writedata
wire [2:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_qsys_0_data_master_agent:rp_valid
wire [98:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_qsys_0_data_master_agent:rp_data
wire rsp_mux_src_ready; // nios2_qsys_0_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [31:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_qsys_0_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_qsys_0_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_qsys_0_data_master_agent:rp_endofpacket
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_instruction_master_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_instruction_master_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_agent:av_debugaccess
wire [18:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_agent:av_address
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_agent:av_read
wire [3:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_agent:av_byteenable
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_instruction_master_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_agent:av_lock
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_agent:av_write
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_agent:av_writedata
wire [2:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_qsys_0_instruction_master_agent:rp_valid
wire [98:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_qsys_0_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_qsys_0_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [31:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_qsys_0_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_qsys_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_qsys_0_instruction_master_agent:rp_endofpacket
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_agent:m0_waitrequest
wire jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [18:0] jtag_uart_0_avalon_jtag_slave_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire [3:0] jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire [31:0] jtag_uart_0_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire jtag_uart_0_avalon_jtag_slave_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire [2:0] jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire [99:0] jtag_uart_0_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_valid
wire [99:0] jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_src_valid; // cmd_mux:src_valid -> jtag_uart_0_avalon_jtag_slave_agent:cp_valid
wire [98:0] cmd_mux_src_data; // cmd_mux:src_data -> jtag_uart_0_avalon_jtag_slave_agent:cp_data
wire cmd_mux_src_ready; // jtag_uart_0_avalon_jtag_slave_agent:cp_ready -> cmd_mux:src_ready
wire [31:0] cmd_mux_src_channel; // cmd_mux:src_channel -> jtag_uart_0_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> jtag_uart_0_avalon_jtag_slave_agent:cp_endofpacket
wire [31:0] nios2_qsys_0_debug_mem_slave_agent_m0_readdata; // nios2_qsys_0_debug_mem_slave_translator:uav_readdata -> nios2_qsys_0_debug_mem_slave_agent:m0_readdata
wire nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest; // nios2_qsys_0_debug_mem_slave_translator:uav_waitrequest -> nios2_qsys_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess; // nios2_qsys_0_debug_mem_slave_agent:m0_debugaccess -> nios2_qsys_0_debug_mem_slave_translator:uav_debugaccess
wire [18:0] nios2_qsys_0_debug_mem_slave_agent_m0_address; // nios2_qsys_0_debug_mem_slave_agent:m0_address -> nios2_qsys_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_qsys_0_debug_mem_slave_agent_m0_byteenable; // nios2_qsys_0_debug_mem_slave_agent:m0_byteenable -> nios2_qsys_0_debug_mem_slave_translator:uav_byteenable
wire nios2_qsys_0_debug_mem_slave_agent_m0_read; // nios2_qsys_0_debug_mem_slave_agent:m0_read -> nios2_qsys_0_debug_mem_slave_translator:uav_read
wire nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_qsys_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_qsys_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_qsys_0_debug_mem_slave_agent_m0_lock; // nios2_qsys_0_debug_mem_slave_agent:m0_lock -> nios2_qsys_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_qsys_0_debug_mem_slave_agent_m0_writedata; // nios2_qsys_0_debug_mem_slave_agent:m0_writedata -> nios2_qsys_0_debug_mem_slave_translator:uav_writedata
wire nios2_qsys_0_debug_mem_slave_agent_m0_write; // nios2_qsys_0_debug_mem_slave_agent:m0_write -> nios2_qsys_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_qsys_0_debug_mem_slave_agent_m0_burstcount; // nios2_qsys_0_debug_mem_slave_agent:m0_burstcount -> nios2_qsys_0_debug_mem_slave_translator:uav_burstcount
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_valid; // nios2_qsys_0_debug_mem_slave_agent:rf_source_valid -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [99:0] nios2_qsys_0_debug_mem_slave_agent_rf_source_data; // nios2_qsys_0_debug_mem_slave_agent:rf_source_data -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_ready; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_qsys_0_debug_mem_slave_agent:rf_source_ready
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_qsys_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_qsys_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_valid
wire [99:0] nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_qsys_0_debug_mem_slave_agent:rf_sink_ready -> nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_qsys_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_debug_mem_slave_agent:rf_sink_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_valid -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_data -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready; // nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> nios2_qsys_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> nios2_qsys_0_debug_mem_slave_agent:cp_valid
wire [98:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> nios2_qsys_0_debug_mem_slave_agent:cp_data
wire cmd_mux_001_src_ready; // nios2_qsys_0_debug_mem_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [31:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> nios2_qsys_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> nios2_qsys_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> nios2_qsys_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [18:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [99:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [99:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [98:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_002_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_002:src_ready
wire [31:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] leds_s1_agent_m0_readdata; // LEDs_s1_translator:uav_readdata -> LEDs_s1_agent:m0_readdata
wire leds_s1_agent_m0_waitrequest; // LEDs_s1_translator:uav_waitrequest -> LEDs_s1_agent:m0_waitrequest
wire leds_s1_agent_m0_debugaccess; // LEDs_s1_agent:m0_debugaccess -> LEDs_s1_translator:uav_debugaccess
wire [18:0] leds_s1_agent_m0_address; // LEDs_s1_agent:m0_address -> LEDs_s1_translator:uav_address
wire [3:0] leds_s1_agent_m0_byteenable; // LEDs_s1_agent:m0_byteenable -> LEDs_s1_translator:uav_byteenable
wire leds_s1_agent_m0_read; // LEDs_s1_agent:m0_read -> LEDs_s1_translator:uav_read
wire leds_s1_agent_m0_readdatavalid; // LEDs_s1_translator:uav_readdatavalid -> LEDs_s1_agent:m0_readdatavalid
wire leds_s1_agent_m0_lock; // LEDs_s1_agent:m0_lock -> LEDs_s1_translator:uav_lock
wire [31:0] leds_s1_agent_m0_writedata; // LEDs_s1_agent:m0_writedata -> LEDs_s1_translator:uav_writedata
wire leds_s1_agent_m0_write; // LEDs_s1_agent:m0_write -> LEDs_s1_translator:uav_write
wire [2:0] leds_s1_agent_m0_burstcount; // LEDs_s1_agent:m0_burstcount -> LEDs_s1_translator:uav_burstcount
wire leds_s1_agent_rf_source_valid; // LEDs_s1_agent:rf_source_valid -> LEDs_s1_agent_rsp_fifo:in_valid
wire [99:0] leds_s1_agent_rf_source_data; // LEDs_s1_agent:rf_source_data -> LEDs_s1_agent_rsp_fifo:in_data
wire leds_s1_agent_rf_source_ready; // LEDs_s1_agent_rsp_fifo:in_ready -> LEDs_s1_agent:rf_source_ready
wire leds_s1_agent_rf_source_startofpacket; // LEDs_s1_agent:rf_source_startofpacket -> LEDs_s1_agent_rsp_fifo:in_startofpacket
wire leds_s1_agent_rf_source_endofpacket; // LEDs_s1_agent:rf_source_endofpacket -> LEDs_s1_agent_rsp_fifo:in_endofpacket
wire leds_s1_agent_rsp_fifo_out_valid; // LEDs_s1_agent_rsp_fifo:out_valid -> LEDs_s1_agent:rf_sink_valid
wire [99:0] leds_s1_agent_rsp_fifo_out_data; // LEDs_s1_agent_rsp_fifo:out_data -> LEDs_s1_agent:rf_sink_data
wire leds_s1_agent_rsp_fifo_out_ready; // LEDs_s1_agent:rf_sink_ready -> LEDs_s1_agent_rsp_fifo:out_ready
wire leds_s1_agent_rsp_fifo_out_startofpacket; // LEDs_s1_agent_rsp_fifo:out_startofpacket -> LEDs_s1_agent:rf_sink_startofpacket
wire leds_s1_agent_rsp_fifo_out_endofpacket; // LEDs_s1_agent_rsp_fifo:out_endofpacket -> LEDs_s1_agent:rf_sink_endofpacket
wire leds_s1_agent_rdata_fifo_src_valid; // LEDs_s1_agent:rdata_fifo_src_valid -> LEDs_s1_agent:rdata_fifo_sink_valid
wire [33:0] leds_s1_agent_rdata_fifo_src_data; // LEDs_s1_agent:rdata_fifo_src_data -> LEDs_s1_agent:rdata_fifo_sink_data
wire leds_s1_agent_rdata_fifo_src_ready; // LEDs_s1_agent:rdata_fifo_sink_ready -> LEDs_s1_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> LEDs_s1_agent:cp_valid
wire [98:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> LEDs_s1_agent:cp_data
wire cmd_mux_003_src_ready; // LEDs_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [31:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> LEDs_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> LEDs_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> LEDs_s1_agent:cp_endofpacket
wire [31:0] switches_s1_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_agent:m0_readdata
wire switches_s1_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_agent:m0_waitrequest
wire switches_s1_agent_m0_debugaccess; // switches_s1_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
wire [18:0] switches_s1_agent_m0_address; // switches_s1_agent:m0_address -> switches_s1_translator:uav_address
wire [3:0] switches_s1_agent_m0_byteenable; // switches_s1_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
wire switches_s1_agent_m0_read; // switches_s1_agent:m0_read -> switches_s1_translator:uav_read
wire switches_s1_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_agent:m0_readdatavalid
wire switches_s1_agent_m0_lock; // switches_s1_agent:m0_lock -> switches_s1_translator:uav_lock
wire [31:0] switches_s1_agent_m0_writedata; // switches_s1_agent:m0_writedata -> switches_s1_translator:uav_writedata
wire switches_s1_agent_m0_write; // switches_s1_agent:m0_write -> switches_s1_translator:uav_write
wire [2:0] switches_s1_agent_m0_burstcount; // switches_s1_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
wire switches_s1_agent_rf_source_valid; // switches_s1_agent:rf_source_valid -> switches_s1_agent_rsp_fifo:in_valid
wire [99:0] switches_s1_agent_rf_source_data; // switches_s1_agent:rf_source_data -> switches_s1_agent_rsp_fifo:in_data
wire switches_s1_agent_rf_source_ready; // switches_s1_agent_rsp_fifo:in_ready -> switches_s1_agent:rf_source_ready
wire switches_s1_agent_rf_source_startofpacket; // switches_s1_agent:rf_source_startofpacket -> switches_s1_agent_rsp_fifo:in_startofpacket
wire switches_s1_agent_rf_source_endofpacket; // switches_s1_agent:rf_source_endofpacket -> switches_s1_agent_rsp_fifo:in_endofpacket
wire switches_s1_agent_rsp_fifo_out_valid; // switches_s1_agent_rsp_fifo:out_valid -> switches_s1_agent:rf_sink_valid
wire [99:0] switches_s1_agent_rsp_fifo_out_data; // switches_s1_agent_rsp_fifo:out_data -> switches_s1_agent:rf_sink_data
wire switches_s1_agent_rsp_fifo_out_ready; // switches_s1_agent:rf_sink_ready -> switches_s1_agent_rsp_fifo:out_ready
wire switches_s1_agent_rsp_fifo_out_startofpacket; // switches_s1_agent_rsp_fifo:out_startofpacket -> switches_s1_agent:rf_sink_startofpacket
wire switches_s1_agent_rsp_fifo_out_endofpacket; // switches_s1_agent_rsp_fifo:out_endofpacket -> switches_s1_agent:rf_sink_endofpacket
wire switches_s1_agent_rdata_fifo_src_valid; // switches_s1_agent:rdata_fifo_src_valid -> switches_s1_agent:rdata_fifo_sink_valid
wire [33:0] switches_s1_agent_rdata_fifo_src_data; // switches_s1_agent:rdata_fifo_src_data -> switches_s1_agent:rdata_fifo_sink_data
wire switches_s1_agent_rdata_fifo_src_ready; // switches_s1_agent:rdata_fifo_sink_ready -> switches_s1_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> switches_s1_agent:cp_valid
wire [98:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> switches_s1_agent:cp_data
wire cmd_mux_004_src_ready; // switches_s1_agent:cp_ready -> cmd_mux_004:src_ready
wire [31:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> switches_s1_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> switches_s1_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> switches_s1_agent:cp_endofpacket
wire [31:0] sram_data_s1_agent_m0_readdata; // sram_data_s1_translator:uav_readdata -> sram_data_s1_agent:m0_readdata
wire sram_data_s1_agent_m0_waitrequest; // sram_data_s1_translator:uav_waitrequest -> sram_data_s1_agent:m0_waitrequest
wire sram_data_s1_agent_m0_debugaccess; // sram_data_s1_agent:m0_debugaccess -> sram_data_s1_translator:uav_debugaccess
wire [18:0] sram_data_s1_agent_m0_address; // sram_data_s1_agent:m0_address -> sram_data_s1_translator:uav_address
wire [3:0] sram_data_s1_agent_m0_byteenable; // sram_data_s1_agent:m0_byteenable -> sram_data_s1_translator:uav_byteenable
wire sram_data_s1_agent_m0_read; // sram_data_s1_agent:m0_read -> sram_data_s1_translator:uav_read
wire sram_data_s1_agent_m0_readdatavalid; // sram_data_s1_translator:uav_readdatavalid -> sram_data_s1_agent:m0_readdatavalid
wire sram_data_s1_agent_m0_lock; // sram_data_s1_agent:m0_lock -> sram_data_s1_translator:uav_lock
wire [31:0] sram_data_s1_agent_m0_writedata; // sram_data_s1_agent:m0_writedata -> sram_data_s1_translator:uav_writedata
wire sram_data_s1_agent_m0_write; // sram_data_s1_agent:m0_write -> sram_data_s1_translator:uav_write
wire [2:0] sram_data_s1_agent_m0_burstcount; // sram_data_s1_agent:m0_burstcount -> sram_data_s1_translator:uav_burstcount
wire sram_data_s1_agent_rf_source_valid; // sram_data_s1_agent:rf_source_valid -> sram_data_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_data_s1_agent_rf_source_data; // sram_data_s1_agent:rf_source_data -> sram_data_s1_agent_rsp_fifo:in_data
wire sram_data_s1_agent_rf_source_ready; // sram_data_s1_agent_rsp_fifo:in_ready -> sram_data_s1_agent:rf_source_ready
wire sram_data_s1_agent_rf_source_startofpacket; // sram_data_s1_agent:rf_source_startofpacket -> sram_data_s1_agent_rsp_fifo:in_startofpacket
wire sram_data_s1_agent_rf_source_endofpacket; // sram_data_s1_agent:rf_source_endofpacket -> sram_data_s1_agent_rsp_fifo:in_endofpacket
wire sram_data_s1_agent_rsp_fifo_out_valid; // sram_data_s1_agent_rsp_fifo:out_valid -> sram_data_s1_agent:rf_sink_valid
wire [99:0] sram_data_s1_agent_rsp_fifo_out_data; // sram_data_s1_agent_rsp_fifo:out_data -> sram_data_s1_agent:rf_sink_data
wire sram_data_s1_agent_rsp_fifo_out_ready; // sram_data_s1_agent:rf_sink_ready -> sram_data_s1_agent_rsp_fifo:out_ready
wire sram_data_s1_agent_rsp_fifo_out_startofpacket; // sram_data_s1_agent_rsp_fifo:out_startofpacket -> sram_data_s1_agent:rf_sink_startofpacket
wire sram_data_s1_agent_rsp_fifo_out_endofpacket; // sram_data_s1_agent_rsp_fifo:out_endofpacket -> sram_data_s1_agent:rf_sink_endofpacket
wire sram_data_s1_agent_rdata_fifo_src_valid; // sram_data_s1_agent:rdata_fifo_src_valid -> sram_data_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_data_s1_agent_rdata_fifo_src_data; // sram_data_s1_agent:rdata_fifo_src_data -> sram_data_s1_agent:rdata_fifo_sink_data
wire sram_data_s1_agent_rdata_fifo_src_ready; // sram_data_s1_agent:rdata_fifo_sink_ready -> sram_data_s1_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sram_data_s1_agent:cp_valid
wire [98:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sram_data_s1_agent:cp_data
wire cmd_mux_005_src_ready; // sram_data_s1_agent:cp_ready -> cmd_mux_005:src_ready
wire [31:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sram_data_s1_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sram_data_s1_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sram_data_s1_agent:cp_endofpacket
wire [31:0] sram_addr_s1_agent_m0_readdata; // sram_addr_s1_translator:uav_readdata -> sram_addr_s1_agent:m0_readdata
wire sram_addr_s1_agent_m0_waitrequest; // sram_addr_s1_translator:uav_waitrequest -> sram_addr_s1_agent:m0_waitrequest
wire sram_addr_s1_agent_m0_debugaccess; // sram_addr_s1_agent:m0_debugaccess -> sram_addr_s1_translator:uav_debugaccess
wire [18:0] sram_addr_s1_agent_m0_address; // sram_addr_s1_agent:m0_address -> sram_addr_s1_translator:uav_address
wire [3:0] sram_addr_s1_agent_m0_byteenable; // sram_addr_s1_agent:m0_byteenable -> sram_addr_s1_translator:uav_byteenable
wire sram_addr_s1_agent_m0_read; // sram_addr_s1_agent:m0_read -> sram_addr_s1_translator:uav_read
wire sram_addr_s1_agent_m0_readdatavalid; // sram_addr_s1_translator:uav_readdatavalid -> sram_addr_s1_agent:m0_readdatavalid
wire sram_addr_s1_agent_m0_lock; // sram_addr_s1_agent:m0_lock -> sram_addr_s1_translator:uav_lock
wire [31:0] sram_addr_s1_agent_m0_writedata; // sram_addr_s1_agent:m0_writedata -> sram_addr_s1_translator:uav_writedata
wire sram_addr_s1_agent_m0_write; // sram_addr_s1_agent:m0_write -> sram_addr_s1_translator:uav_write
wire [2:0] sram_addr_s1_agent_m0_burstcount; // sram_addr_s1_agent:m0_burstcount -> sram_addr_s1_translator:uav_burstcount
wire sram_addr_s1_agent_rf_source_valid; // sram_addr_s1_agent:rf_source_valid -> sram_addr_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_addr_s1_agent_rf_source_data; // sram_addr_s1_agent:rf_source_data -> sram_addr_s1_agent_rsp_fifo:in_data
wire sram_addr_s1_agent_rf_source_ready; // sram_addr_s1_agent_rsp_fifo:in_ready -> sram_addr_s1_agent:rf_source_ready
wire sram_addr_s1_agent_rf_source_startofpacket; // sram_addr_s1_agent:rf_source_startofpacket -> sram_addr_s1_agent_rsp_fifo:in_startofpacket
wire sram_addr_s1_agent_rf_source_endofpacket; // sram_addr_s1_agent:rf_source_endofpacket -> sram_addr_s1_agent_rsp_fifo:in_endofpacket
wire sram_addr_s1_agent_rsp_fifo_out_valid; // sram_addr_s1_agent_rsp_fifo:out_valid -> sram_addr_s1_agent:rf_sink_valid
wire [99:0] sram_addr_s1_agent_rsp_fifo_out_data; // sram_addr_s1_agent_rsp_fifo:out_data -> sram_addr_s1_agent:rf_sink_data
wire sram_addr_s1_agent_rsp_fifo_out_ready; // sram_addr_s1_agent:rf_sink_ready -> sram_addr_s1_agent_rsp_fifo:out_ready
wire sram_addr_s1_agent_rsp_fifo_out_startofpacket; // sram_addr_s1_agent_rsp_fifo:out_startofpacket -> sram_addr_s1_agent:rf_sink_startofpacket
wire sram_addr_s1_agent_rsp_fifo_out_endofpacket; // sram_addr_s1_agent_rsp_fifo:out_endofpacket -> sram_addr_s1_agent:rf_sink_endofpacket
wire sram_addr_s1_agent_rdata_fifo_src_valid; // sram_addr_s1_agent:rdata_fifo_src_valid -> sram_addr_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_addr_s1_agent_rdata_fifo_src_data; // sram_addr_s1_agent:rdata_fifo_src_data -> sram_addr_s1_agent:rdata_fifo_sink_data
wire sram_addr_s1_agent_rdata_fifo_src_ready; // sram_addr_s1_agent:rdata_fifo_sink_ready -> sram_addr_s1_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> sram_addr_s1_agent:cp_valid
wire [98:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> sram_addr_s1_agent:cp_data
wire cmd_mux_006_src_ready; // sram_addr_s1_agent:cp_ready -> cmd_mux_006:src_ready
wire [31:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> sram_addr_s1_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> sram_addr_s1_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> sram_addr_s1_agent:cp_endofpacket
wire [31:0] sram_read_write_s1_agent_m0_readdata; // sram_read_write_s1_translator:uav_readdata -> sram_read_write_s1_agent:m0_readdata
wire sram_read_write_s1_agent_m0_waitrequest; // sram_read_write_s1_translator:uav_waitrequest -> sram_read_write_s1_agent:m0_waitrequest
wire sram_read_write_s1_agent_m0_debugaccess; // sram_read_write_s1_agent:m0_debugaccess -> sram_read_write_s1_translator:uav_debugaccess
wire [18:0] sram_read_write_s1_agent_m0_address; // sram_read_write_s1_agent:m0_address -> sram_read_write_s1_translator:uav_address
wire [3:0] sram_read_write_s1_agent_m0_byteenable; // sram_read_write_s1_agent:m0_byteenable -> sram_read_write_s1_translator:uav_byteenable
wire sram_read_write_s1_agent_m0_read; // sram_read_write_s1_agent:m0_read -> sram_read_write_s1_translator:uav_read
wire sram_read_write_s1_agent_m0_readdatavalid; // sram_read_write_s1_translator:uav_readdatavalid -> sram_read_write_s1_agent:m0_readdatavalid
wire sram_read_write_s1_agent_m0_lock; // sram_read_write_s1_agent:m0_lock -> sram_read_write_s1_translator:uav_lock
wire [31:0] sram_read_write_s1_agent_m0_writedata; // sram_read_write_s1_agent:m0_writedata -> sram_read_write_s1_translator:uav_writedata
wire sram_read_write_s1_agent_m0_write; // sram_read_write_s1_agent:m0_write -> sram_read_write_s1_translator:uav_write
wire [2:0] sram_read_write_s1_agent_m0_burstcount; // sram_read_write_s1_agent:m0_burstcount -> sram_read_write_s1_translator:uav_burstcount
wire sram_read_write_s1_agent_rf_source_valid; // sram_read_write_s1_agent:rf_source_valid -> sram_read_write_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_read_write_s1_agent_rf_source_data; // sram_read_write_s1_agent:rf_source_data -> sram_read_write_s1_agent_rsp_fifo:in_data
wire sram_read_write_s1_agent_rf_source_ready; // sram_read_write_s1_agent_rsp_fifo:in_ready -> sram_read_write_s1_agent:rf_source_ready
wire sram_read_write_s1_agent_rf_source_startofpacket; // sram_read_write_s1_agent:rf_source_startofpacket -> sram_read_write_s1_agent_rsp_fifo:in_startofpacket
wire sram_read_write_s1_agent_rf_source_endofpacket; // sram_read_write_s1_agent:rf_source_endofpacket -> sram_read_write_s1_agent_rsp_fifo:in_endofpacket
wire sram_read_write_s1_agent_rsp_fifo_out_valid; // sram_read_write_s1_agent_rsp_fifo:out_valid -> sram_read_write_s1_agent:rf_sink_valid
wire [99:0] sram_read_write_s1_agent_rsp_fifo_out_data; // sram_read_write_s1_agent_rsp_fifo:out_data -> sram_read_write_s1_agent:rf_sink_data
wire sram_read_write_s1_agent_rsp_fifo_out_ready; // sram_read_write_s1_agent:rf_sink_ready -> sram_read_write_s1_agent_rsp_fifo:out_ready
wire sram_read_write_s1_agent_rsp_fifo_out_startofpacket; // sram_read_write_s1_agent_rsp_fifo:out_startofpacket -> sram_read_write_s1_agent:rf_sink_startofpacket
wire sram_read_write_s1_agent_rsp_fifo_out_endofpacket; // sram_read_write_s1_agent_rsp_fifo:out_endofpacket -> sram_read_write_s1_agent:rf_sink_endofpacket
wire sram_read_write_s1_agent_rdata_fifo_src_valid; // sram_read_write_s1_agent:rdata_fifo_src_valid -> sram_read_write_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_read_write_s1_agent_rdata_fifo_src_data; // sram_read_write_s1_agent:rdata_fifo_src_data -> sram_read_write_s1_agent:rdata_fifo_sink_data
wire sram_read_write_s1_agent_rdata_fifo_src_ready; // sram_read_write_s1_agent:rdata_fifo_sink_ready -> sram_read_write_s1_agent:rdata_fifo_src_ready
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> sram_read_write_s1_agent:cp_valid
wire [98:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> sram_read_write_s1_agent:cp_data
wire cmd_mux_007_src_ready; // sram_read_write_s1_agent:cp_ready -> cmd_mux_007:src_ready
wire [31:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> sram_read_write_s1_agent:cp_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> sram_read_write_s1_agent:cp_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> sram_read_write_s1_agent:cp_endofpacket
wire [31:0] sram_cs_s1_agent_m0_readdata; // sram_cs_s1_translator:uav_readdata -> sram_cs_s1_agent:m0_readdata
wire sram_cs_s1_agent_m0_waitrequest; // sram_cs_s1_translator:uav_waitrequest -> sram_cs_s1_agent:m0_waitrequest
wire sram_cs_s1_agent_m0_debugaccess; // sram_cs_s1_agent:m0_debugaccess -> sram_cs_s1_translator:uav_debugaccess
wire [18:0] sram_cs_s1_agent_m0_address; // sram_cs_s1_agent:m0_address -> sram_cs_s1_translator:uav_address
wire [3:0] sram_cs_s1_agent_m0_byteenable; // sram_cs_s1_agent:m0_byteenable -> sram_cs_s1_translator:uav_byteenable
wire sram_cs_s1_agent_m0_read; // sram_cs_s1_agent:m0_read -> sram_cs_s1_translator:uav_read
wire sram_cs_s1_agent_m0_readdatavalid; // sram_cs_s1_translator:uav_readdatavalid -> sram_cs_s1_agent:m0_readdatavalid
wire sram_cs_s1_agent_m0_lock; // sram_cs_s1_agent:m0_lock -> sram_cs_s1_translator:uav_lock
wire [31:0] sram_cs_s1_agent_m0_writedata; // sram_cs_s1_agent:m0_writedata -> sram_cs_s1_translator:uav_writedata
wire sram_cs_s1_agent_m0_write; // sram_cs_s1_agent:m0_write -> sram_cs_s1_translator:uav_write
wire [2:0] sram_cs_s1_agent_m0_burstcount; // sram_cs_s1_agent:m0_burstcount -> sram_cs_s1_translator:uav_burstcount
wire sram_cs_s1_agent_rf_source_valid; // sram_cs_s1_agent:rf_source_valid -> sram_cs_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_cs_s1_agent_rf_source_data; // sram_cs_s1_agent:rf_source_data -> sram_cs_s1_agent_rsp_fifo:in_data
wire sram_cs_s1_agent_rf_source_ready; // sram_cs_s1_agent_rsp_fifo:in_ready -> sram_cs_s1_agent:rf_source_ready
wire sram_cs_s1_agent_rf_source_startofpacket; // sram_cs_s1_agent:rf_source_startofpacket -> sram_cs_s1_agent_rsp_fifo:in_startofpacket
wire sram_cs_s1_agent_rf_source_endofpacket; // sram_cs_s1_agent:rf_source_endofpacket -> sram_cs_s1_agent_rsp_fifo:in_endofpacket
wire sram_cs_s1_agent_rsp_fifo_out_valid; // sram_cs_s1_agent_rsp_fifo:out_valid -> sram_cs_s1_agent:rf_sink_valid
wire [99:0] sram_cs_s1_agent_rsp_fifo_out_data; // sram_cs_s1_agent_rsp_fifo:out_data -> sram_cs_s1_agent:rf_sink_data
wire sram_cs_s1_agent_rsp_fifo_out_ready; // sram_cs_s1_agent:rf_sink_ready -> sram_cs_s1_agent_rsp_fifo:out_ready
wire sram_cs_s1_agent_rsp_fifo_out_startofpacket; // sram_cs_s1_agent_rsp_fifo:out_startofpacket -> sram_cs_s1_agent:rf_sink_startofpacket
wire sram_cs_s1_agent_rsp_fifo_out_endofpacket; // sram_cs_s1_agent_rsp_fifo:out_endofpacket -> sram_cs_s1_agent:rf_sink_endofpacket
wire sram_cs_s1_agent_rdata_fifo_src_valid; // sram_cs_s1_agent:rdata_fifo_src_valid -> sram_cs_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_cs_s1_agent_rdata_fifo_src_data; // sram_cs_s1_agent:rdata_fifo_src_data -> sram_cs_s1_agent:rdata_fifo_sink_data
wire sram_cs_s1_agent_rdata_fifo_src_ready; // sram_cs_s1_agent:rdata_fifo_sink_ready -> sram_cs_s1_agent:rdata_fifo_src_ready
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> sram_cs_s1_agent:cp_valid
wire [98:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> sram_cs_s1_agent:cp_data
wire cmd_mux_008_src_ready; // sram_cs_s1_agent:cp_ready -> cmd_mux_008:src_ready
wire [31:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> sram_cs_s1_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> sram_cs_s1_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> sram_cs_s1_agent:cp_endofpacket
wire [31:0] sram_oe_s1_agent_m0_readdata; // sram_oe_s1_translator:uav_readdata -> sram_oe_s1_agent:m0_readdata
wire sram_oe_s1_agent_m0_waitrequest; // sram_oe_s1_translator:uav_waitrequest -> sram_oe_s1_agent:m0_waitrequest
wire sram_oe_s1_agent_m0_debugaccess; // sram_oe_s1_agent:m0_debugaccess -> sram_oe_s1_translator:uav_debugaccess
wire [18:0] sram_oe_s1_agent_m0_address; // sram_oe_s1_agent:m0_address -> sram_oe_s1_translator:uav_address
wire [3:0] sram_oe_s1_agent_m0_byteenable; // sram_oe_s1_agent:m0_byteenable -> sram_oe_s1_translator:uav_byteenable
wire sram_oe_s1_agent_m0_read; // sram_oe_s1_agent:m0_read -> sram_oe_s1_translator:uav_read
wire sram_oe_s1_agent_m0_readdatavalid; // sram_oe_s1_translator:uav_readdatavalid -> sram_oe_s1_agent:m0_readdatavalid
wire sram_oe_s1_agent_m0_lock; // sram_oe_s1_agent:m0_lock -> sram_oe_s1_translator:uav_lock
wire [31:0] sram_oe_s1_agent_m0_writedata; // sram_oe_s1_agent:m0_writedata -> sram_oe_s1_translator:uav_writedata
wire sram_oe_s1_agent_m0_write; // sram_oe_s1_agent:m0_write -> sram_oe_s1_translator:uav_write
wire [2:0] sram_oe_s1_agent_m0_burstcount; // sram_oe_s1_agent:m0_burstcount -> sram_oe_s1_translator:uav_burstcount
wire sram_oe_s1_agent_rf_source_valid; // sram_oe_s1_agent:rf_source_valid -> sram_oe_s1_agent_rsp_fifo:in_valid
wire [99:0] sram_oe_s1_agent_rf_source_data; // sram_oe_s1_agent:rf_source_data -> sram_oe_s1_agent_rsp_fifo:in_data
wire sram_oe_s1_agent_rf_source_ready; // sram_oe_s1_agent_rsp_fifo:in_ready -> sram_oe_s1_agent:rf_source_ready
wire sram_oe_s1_agent_rf_source_startofpacket; // sram_oe_s1_agent:rf_source_startofpacket -> sram_oe_s1_agent_rsp_fifo:in_startofpacket
wire sram_oe_s1_agent_rf_source_endofpacket; // sram_oe_s1_agent:rf_source_endofpacket -> sram_oe_s1_agent_rsp_fifo:in_endofpacket
wire sram_oe_s1_agent_rsp_fifo_out_valid; // sram_oe_s1_agent_rsp_fifo:out_valid -> sram_oe_s1_agent:rf_sink_valid
wire [99:0] sram_oe_s1_agent_rsp_fifo_out_data; // sram_oe_s1_agent_rsp_fifo:out_data -> sram_oe_s1_agent:rf_sink_data
wire sram_oe_s1_agent_rsp_fifo_out_ready; // sram_oe_s1_agent:rf_sink_ready -> sram_oe_s1_agent_rsp_fifo:out_ready
wire sram_oe_s1_agent_rsp_fifo_out_startofpacket; // sram_oe_s1_agent_rsp_fifo:out_startofpacket -> sram_oe_s1_agent:rf_sink_startofpacket
wire sram_oe_s1_agent_rsp_fifo_out_endofpacket; // sram_oe_s1_agent_rsp_fifo:out_endofpacket -> sram_oe_s1_agent:rf_sink_endofpacket
wire sram_oe_s1_agent_rdata_fifo_src_valid; // sram_oe_s1_agent:rdata_fifo_src_valid -> sram_oe_s1_agent:rdata_fifo_sink_valid
wire [33:0] sram_oe_s1_agent_rdata_fifo_src_data; // sram_oe_s1_agent:rdata_fifo_src_data -> sram_oe_s1_agent:rdata_fifo_sink_data
wire sram_oe_s1_agent_rdata_fifo_src_ready; // sram_oe_s1_agent:rdata_fifo_sink_ready -> sram_oe_s1_agent:rdata_fifo_src_ready
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> sram_oe_s1_agent:cp_valid
wire [98:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> sram_oe_s1_agent:cp_data
wire cmd_mux_009_src_ready; // sram_oe_s1_agent:cp_ready -> cmd_mux_009:src_ready
wire [31:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> sram_oe_s1_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> sram_oe_s1_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> sram_oe_s1_agent:cp_endofpacket
wire [31:0] regfile_data_s1_agent_m0_readdata; // regfile_data_s1_translator:uav_readdata -> regfile_data_s1_agent:m0_readdata
wire regfile_data_s1_agent_m0_waitrequest; // regfile_data_s1_translator:uav_waitrequest -> regfile_data_s1_agent:m0_waitrequest
wire regfile_data_s1_agent_m0_debugaccess; // regfile_data_s1_agent:m0_debugaccess -> regfile_data_s1_translator:uav_debugaccess
wire [18:0] regfile_data_s1_agent_m0_address; // regfile_data_s1_agent:m0_address -> regfile_data_s1_translator:uav_address
wire [3:0] regfile_data_s1_agent_m0_byteenable; // regfile_data_s1_agent:m0_byteenable -> regfile_data_s1_translator:uav_byteenable
wire regfile_data_s1_agent_m0_read; // regfile_data_s1_agent:m0_read -> regfile_data_s1_translator:uav_read
wire regfile_data_s1_agent_m0_readdatavalid; // regfile_data_s1_translator:uav_readdatavalid -> regfile_data_s1_agent:m0_readdatavalid
wire regfile_data_s1_agent_m0_lock; // regfile_data_s1_agent:m0_lock -> regfile_data_s1_translator:uav_lock
wire [31:0] regfile_data_s1_agent_m0_writedata; // regfile_data_s1_agent:m0_writedata -> regfile_data_s1_translator:uav_writedata
wire regfile_data_s1_agent_m0_write; // regfile_data_s1_agent:m0_write -> regfile_data_s1_translator:uav_write
wire [2:0] regfile_data_s1_agent_m0_burstcount; // regfile_data_s1_agent:m0_burstcount -> regfile_data_s1_translator:uav_burstcount
wire regfile_data_s1_agent_rf_source_valid; // regfile_data_s1_agent:rf_source_valid -> regfile_data_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_data_s1_agent_rf_source_data; // regfile_data_s1_agent:rf_source_data -> regfile_data_s1_agent_rsp_fifo:in_data
wire regfile_data_s1_agent_rf_source_ready; // regfile_data_s1_agent_rsp_fifo:in_ready -> regfile_data_s1_agent:rf_source_ready
wire regfile_data_s1_agent_rf_source_startofpacket; // regfile_data_s1_agent:rf_source_startofpacket -> regfile_data_s1_agent_rsp_fifo:in_startofpacket
wire regfile_data_s1_agent_rf_source_endofpacket; // regfile_data_s1_agent:rf_source_endofpacket -> regfile_data_s1_agent_rsp_fifo:in_endofpacket
wire regfile_data_s1_agent_rsp_fifo_out_valid; // regfile_data_s1_agent_rsp_fifo:out_valid -> regfile_data_s1_agent:rf_sink_valid
wire [99:0] regfile_data_s1_agent_rsp_fifo_out_data; // regfile_data_s1_agent_rsp_fifo:out_data -> regfile_data_s1_agent:rf_sink_data
wire regfile_data_s1_agent_rsp_fifo_out_ready; // regfile_data_s1_agent:rf_sink_ready -> regfile_data_s1_agent_rsp_fifo:out_ready
wire regfile_data_s1_agent_rsp_fifo_out_startofpacket; // regfile_data_s1_agent_rsp_fifo:out_startofpacket -> regfile_data_s1_agent:rf_sink_startofpacket
wire regfile_data_s1_agent_rsp_fifo_out_endofpacket; // regfile_data_s1_agent_rsp_fifo:out_endofpacket -> regfile_data_s1_agent:rf_sink_endofpacket
wire regfile_data_s1_agent_rdata_fifo_src_valid; // regfile_data_s1_agent:rdata_fifo_src_valid -> regfile_data_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_data_s1_agent_rdata_fifo_src_data; // regfile_data_s1_agent:rdata_fifo_src_data -> regfile_data_s1_agent:rdata_fifo_sink_data
wire regfile_data_s1_agent_rdata_fifo_src_ready; // regfile_data_s1_agent:rdata_fifo_sink_ready -> regfile_data_s1_agent:rdata_fifo_src_ready
wire cmd_mux_010_src_valid; // cmd_mux_010:src_valid -> regfile_data_s1_agent:cp_valid
wire [98:0] cmd_mux_010_src_data; // cmd_mux_010:src_data -> regfile_data_s1_agent:cp_data
wire cmd_mux_010_src_ready; // regfile_data_s1_agent:cp_ready -> cmd_mux_010:src_ready
wire [31:0] cmd_mux_010_src_channel; // cmd_mux_010:src_channel -> regfile_data_s1_agent:cp_channel
wire cmd_mux_010_src_startofpacket; // cmd_mux_010:src_startofpacket -> regfile_data_s1_agent:cp_startofpacket
wire cmd_mux_010_src_endofpacket; // cmd_mux_010:src_endofpacket -> regfile_data_s1_agent:cp_endofpacket
wire [31:0] regfile_reg1_s1_agent_m0_readdata; // regfile_reg1_s1_translator:uav_readdata -> regfile_reg1_s1_agent:m0_readdata
wire regfile_reg1_s1_agent_m0_waitrequest; // regfile_reg1_s1_translator:uav_waitrequest -> regfile_reg1_s1_agent:m0_waitrequest
wire regfile_reg1_s1_agent_m0_debugaccess; // regfile_reg1_s1_agent:m0_debugaccess -> regfile_reg1_s1_translator:uav_debugaccess
wire [18:0] regfile_reg1_s1_agent_m0_address; // regfile_reg1_s1_agent:m0_address -> regfile_reg1_s1_translator:uav_address
wire [3:0] regfile_reg1_s1_agent_m0_byteenable; // regfile_reg1_s1_agent:m0_byteenable -> regfile_reg1_s1_translator:uav_byteenable
wire regfile_reg1_s1_agent_m0_read; // regfile_reg1_s1_agent:m0_read -> regfile_reg1_s1_translator:uav_read
wire regfile_reg1_s1_agent_m0_readdatavalid; // regfile_reg1_s1_translator:uav_readdatavalid -> regfile_reg1_s1_agent:m0_readdatavalid
wire regfile_reg1_s1_agent_m0_lock; // regfile_reg1_s1_agent:m0_lock -> regfile_reg1_s1_translator:uav_lock
wire [31:0] regfile_reg1_s1_agent_m0_writedata; // regfile_reg1_s1_agent:m0_writedata -> regfile_reg1_s1_translator:uav_writedata
wire regfile_reg1_s1_agent_m0_write; // regfile_reg1_s1_agent:m0_write -> regfile_reg1_s1_translator:uav_write
wire [2:0] regfile_reg1_s1_agent_m0_burstcount; // regfile_reg1_s1_agent:m0_burstcount -> regfile_reg1_s1_translator:uav_burstcount
wire regfile_reg1_s1_agent_rf_source_valid; // regfile_reg1_s1_agent:rf_source_valid -> regfile_reg1_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_reg1_s1_agent_rf_source_data; // regfile_reg1_s1_agent:rf_source_data -> regfile_reg1_s1_agent_rsp_fifo:in_data
wire regfile_reg1_s1_agent_rf_source_ready; // regfile_reg1_s1_agent_rsp_fifo:in_ready -> regfile_reg1_s1_agent:rf_source_ready
wire regfile_reg1_s1_agent_rf_source_startofpacket; // regfile_reg1_s1_agent:rf_source_startofpacket -> regfile_reg1_s1_agent_rsp_fifo:in_startofpacket
wire regfile_reg1_s1_agent_rf_source_endofpacket; // regfile_reg1_s1_agent:rf_source_endofpacket -> regfile_reg1_s1_agent_rsp_fifo:in_endofpacket
wire regfile_reg1_s1_agent_rsp_fifo_out_valid; // regfile_reg1_s1_agent_rsp_fifo:out_valid -> regfile_reg1_s1_agent:rf_sink_valid
wire [99:0] regfile_reg1_s1_agent_rsp_fifo_out_data; // regfile_reg1_s1_agent_rsp_fifo:out_data -> regfile_reg1_s1_agent:rf_sink_data
wire regfile_reg1_s1_agent_rsp_fifo_out_ready; // regfile_reg1_s1_agent:rf_sink_ready -> regfile_reg1_s1_agent_rsp_fifo:out_ready
wire regfile_reg1_s1_agent_rsp_fifo_out_startofpacket; // regfile_reg1_s1_agent_rsp_fifo:out_startofpacket -> regfile_reg1_s1_agent:rf_sink_startofpacket
wire regfile_reg1_s1_agent_rsp_fifo_out_endofpacket; // regfile_reg1_s1_agent_rsp_fifo:out_endofpacket -> regfile_reg1_s1_agent:rf_sink_endofpacket
wire regfile_reg1_s1_agent_rdata_fifo_src_valid; // regfile_reg1_s1_agent:rdata_fifo_src_valid -> regfile_reg1_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_reg1_s1_agent_rdata_fifo_src_data; // regfile_reg1_s1_agent:rdata_fifo_src_data -> regfile_reg1_s1_agent:rdata_fifo_sink_data
wire regfile_reg1_s1_agent_rdata_fifo_src_ready; // regfile_reg1_s1_agent:rdata_fifo_sink_ready -> regfile_reg1_s1_agent:rdata_fifo_src_ready
wire cmd_mux_011_src_valid; // cmd_mux_011:src_valid -> regfile_reg1_s1_agent:cp_valid
wire [98:0] cmd_mux_011_src_data; // cmd_mux_011:src_data -> regfile_reg1_s1_agent:cp_data
wire cmd_mux_011_src_ready; // regfile_reg1_s1_agent:cp_ready -> cmd_mux_011:src_ready
wire [31:0] cmd_mux_011_src_channel; // cmd_mux_011:src_channel -> regfile_reg1_s1_agent:cp_channel
wire cmd_mux_011_src_startofpacket; // cmd_mux_011:src_startofpacket -> regfile_reg1_s1_agent:cp_startofpacket
wire cmd_mux_011_src_endofpacket; // cmd_mux_011:src_endofpacket -> regfile_reg1_s1_agent:cp_endofpacket
wire [31:0] regfile_reg2_s1_agent_m0_readdata; // regfile_reg2_s1_translator:uav_readdata -> regfile_reg2_s1_agent:m0_readdata
wire regfile_reg2_s1_agent_m0_waitrequest; // regfile_reg2_s1_translator:uav_waitrequest -> regfile_reg2_s1_agent:m0_waitrequest
wire regfile_reg2_s1_agent_m0_debugaccess; // regfile_reg2_s1_agent:m0_debugaccess -> regfile_reg2_s1_translator:uav_debugaccess
wire [18:0] regfile_reg2_s1_agent_m0_address; // regfile_reg2_s1_agent:m0_address -> regfile_reg2_s1_translator:uav_address
wire [3:0] regfile_reg2_s1_agent_m0_byteenable; // regfile_reg2_s1_agent:m0_byteenable -> regfile_reg2_s1_translator:uav_byteenable
wire regfile_reg2_s1_agent_m0_read; // regfile_reg2_s1_agent:m0_read -> regfile_reg2_s1_translator:uav_read
wire regfile_reg2_s1_agent_m0_readdatavalid; // regfile_reg2_s1_translator:uav_readdatavalid -> regfile_reg2_s1_agent:m0_readdatavalid
wire regfile_reg2_s1_agent_m0_lock; // regfile_reg2_s1_agent:m0_lock -> regfile_reg2_s1_translator:uav_lock
wire [31:0] regfile_reg2_s1_agent_m0_writedata; // regfile_reg2_s1_agent:m0_writedata -> regfile_reg2_s1_translator:uav_writedata
wire regfile_reg2_s1_agent_m0_write; // regfile_reg2_s1_agent:m0_write -> regfile_reg2_s1_translator:uav_write
wire [2:0] regfile_reg2_s1_agent_m0_burstcount; // regfile_reg2_s1_agent:m0_burstcount -> regfile_reg2_s1_translator:uav_burstcount
wire regfile_reg2_s1_agent_rf_source_valid; // regfile_reg2_s1_agent:rf_source_valid -> regfile_reg2_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_reg2_s1_agent_rf_source_data; // regfile_reg2_s1_agent:rf_source_data -> regfile_reg2_s1_agent_rsp_fifo:in_data
wire regfile_reg2_s1_agent_rf_source_ready; // regfile_reg2_s1_agent_rsp_fifo:in_ready -> regfile_reg2_s1_agent:rf_source_ready
wire regfile_reg2_s1_agent_rf_source_startofpacket; // regfile_reg2_s1_agent:rf_source_startofpacket -> regfile_reg2_s1_agent_rsp_fifo:in_startofpacket
wire regfile_reg2_s1_agent_rf_source_endofpacket; // regfile_reg2_s1_agent:rf_source_endofpacket -> regfile_reg2_s1_agent_rsp_fifo:in_endofpacket
wire regfile_reg2_s1_agent_rsp_fifo_out_valid; // regfile_reg2_s1_agent_rsp_fifo:out_valid -> regfile_reg2_s1_agent:rf_sink_valid
wire [99:0] regfile_reg2_s1_agent_rsp_fifo_out_data; // regfile_reg2_s1_agent_rsp_fifo:out_data -> regfile_reg2_s1_agent:rf_sink_data
wire regfile_reg2_s1_agent_rsp_fifo_out_ready; // regfile_reg2_s1_agent:rf_sink_ready -> regfile_reg2_s1_agent_rsp_fifo:out_ready
wire regfile_reg2_s1_agent_rsp_fifo_out_startofpacket; // regfile_reg2_s1_agent_rsp_fifo:out_startofpacket -> regfile_reg2_s1_agent:rf_sink_startofpacket
wire regfile_reg2_s1_agent_rsp_fifo_out_endofpacket; // regfile_reg2_s1_agent_rsp_fifo:out_endofpacket -> regfile_reg2_s1_agent:rf_sink_endofpacket
wire regfile_reg2_s1_agent_rdata_fifo_src_valid; // regfile_reg2_s1_agent:rdata_fifo_src_valid -> regfile_reg2_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_reg2_s1_agent_rdata_fifo_src_data; // regfile_reg2_s1_agent:rdata_fifo_src_data -> regfile_reg2_s1_agent:rdata_fifo_sink_data
wire regfile_reg2_s1_agent_rdata_fifo_src_ready; // regfile_reg2_s1_agent:rdata_fifo_sink_ready -> regfile_reg2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_012_src_valid; // cmd_mux_012:src_valid -> regfile_reg2_s1_agent:cp_valid
wire [98:0] cmd_mux_012_src_data; // cmd_mux_012:src_data -> regfile_reg2_s1_agent:cp_data
wire cmd_mux_012_src_ready; // regfile_reg2_s1_agent:cp_ready -> cmd_mux_012:src_ready
wire [31:0] cmd_mux_012_src_channel; // cmd_mux_012:src_channel -> regfile_reg2_s1_agent:cp_channel
wire cmd_mux_012_src_startofpacket; // cmd_mux_012:src_startofpacket -> regfile_reg2_s1_agent:cp_startofpacket
wire cmd_mux_012_src_endofpacket; // cmd_mux_012:src_endofpacket -> regfile_reg2_s1_agent:cp_endofpacket
wire [31:0] regfile_r1sel_s1_agent_m0_readdata; // regfile_r1sel_s1_translator:uav_readdata -> regfile_r1sel_s1_agent:m0_readdata
wire regfile_r1sel_s1_agent_m0_waitrequest; // regfile_r1sel_s1_translator:uav_waitrequest -> regfile_r1sel_s1_agent:m0_waitrequest
wire regfile_r1sel_s1_agent_m0_debugaccess; // regfile_r1sel_s1_agent:m0_debugaccess -> regfile_r1sel_s1_translator:uav_debugaccess
wire [18:0] regfile_r1sel_s1_agent_m0_address; // regfile_r1sel_s1_agent:m0_address -> regfile_r1sel_s1_translator:uav_address
wire [3:0] regfile_r1sel_s1_agent_m0_byteenable; // regfile_r1sel_s1_agent:m0_byteenable -> regfile_r1sel_s1_translator:uav_byteenable
wire regfile_r1sel_s1_agent_m0_read; // regfile_r1sel_s1_agent:m0_read -> regfile_r1sel_s1_translator:uav_read
wire regfile_r1sel_s1_agent_m0_readdatavalid; // regfile_r1sel_s1_translator:uav_readdatavalid -> regfile_r1sel_s1_agent:m0_readdatavalid
wire regfile_r1sel_s1_agent_m0_lock; // regfile_r1sel_s1_agent:m0_lock -> regfile_r1sel_s1_translator:uav_lock
wire [31:0] regfile_r1sel_s1_agent_m0_writedata; // regfile_r1sel_s1_agent:m0_writedata -> regfile_r1sel_s1_translator:uav_writedata
wire regfile_r1sel_s1_agent_m0_write; // regfile_r1sel_s1_agent:m0_write -> regfile_r1sel_s1_translator:uav_write
wire [2:0] regfile_r1sel_s1_agent_m0_burstcount; // regfile_r1sel_s1_agent:m0_burstcount -> regfile_r1sel_s1_translator:uav_burstcount
wire regfile_r1sel_s1_agent_rf_source_valid; // regfile_r1sel_s1_agent:rf_source_valid -> regfile_r1sel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_r1sel_s1_agent_rf_source_data; // regfile_r1sel_s1_agent:rf_source_data -> regfile_r1sel_s1_agent_rsp_fifo:in_data
wire regfile_r1sel_s1_agent_rf_source_ready; // regfile_r1sel_s1_agent_rsp_fifo:in_ready -> regfile_r1sel_s1_agent:rf_source_ready
wire regfile_r1sel_s1_agent_rf_source_startofpacket; // regfile_r1sel_s1_agent:rf_source_startofpacket -> regfile_r1sel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_r1sel_s1_agent_rf_source_endofpacket; // regfile_r1sel_s1_agent:rf_source_endofpacket -> regfile_r1sel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_r1sel_s1_agent_rsp_fifo_out_valid; // regfile_r1sel_s1_agent_rsp_fifo:out_valid -> regfile_r1sel_s1_agent:rf_sink_valid
wire [99:0] regfile_r1sel_s1_agent_rsp_fifo_out_data; // regfile_r1sel_s1_agent_rsp_fifo:out_data -> regfile_r1sel_s1_agent:rf_sink_data
wire regfile_r1sel_s1_agent_rsp_fifo_out_ready; // regfile_r1sel_s1_agent:rf_sink_ready -> regfile_r1sel_s1_agent_rsp_fifo:out_ready
wire regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket; // regfile_r1sel_s1_agent_rsp_fifo:out_startofpacket -> regfile_r1sel_s1_agent:rf_sink_startofpacket
wire regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket; // regfile_r1sel_s1_agent_rsp_fifo:out_endofpacket -> regfile_r1sel_s1_agent:rf_sink_endofpacket
wire regfile_r1sel_s1_agent_rdata_fifo_src_valid; // regfile_r1sel_s1_agent:rdata_fifo_src_valid -> regfile_r1sel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_r1sel_s1_agent_rdata_fifo_src_data; // regfile_r1sel_s1_agent:rdata_fifo_src_data -> regfile_r1sel_s1_agent:rdata_fifo_sink_data
wire regfile_r1sel_s1_agent_rdata_fifo_src_ready; // regfile_r1sel_s1_agent:rdata_fifo_sink_ready -> regfile_r1sel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_013_src_valid; // cmd_mux_013:src_valid -> regfile_r1sel_s1_agent:cp_valid
wire [98:0] cmd_mux_013_src_data; // cmd_mux_013:src_data -> regfile_r1sel_s1_agent:cp_data
wire cmd_mux_013_src_ready; // regfile_r1sel_s1_agent:cp_ready -> cmd_mux_013:src_ready
wire [31:0] cmd_mux_013_src_channel; // cmd_mux_013:src_channel -> regfile_r1sel_s1_agent:cp_channel
wire cmd_mux_013_src_startofpacket; // cmd_mux_013:src_startofpacket -> regfile_r1sel_s1_agent:cp_startofpacket
wire cmd_mux_013_src_endofpacket; // cmd_mux_013:src_endofpacket -> regfile_r1sel_s1_agent:cp_endofpacket
wire [31:0] regfile_r2sel_s1_agent_m0_readdata; // regfile_r2sel_s1_translator:uav_readdata -> regfile_r2sel_s1_agent:m0_readdata
wire regfile_r2sel_s1_agent_m0_waitrequest; // regfile_r2sel_s1_translator:uav_waitrequest -> regfile_r2sel_s1_agent:m0_waitrequest
wire regfile_r2sel_s1_agent_m0_debugaccess; // regfile_r2sel_s1_agent:m0_debugaccess -> regfile_r2sel_s1_translator:uav_debugaccess
wire [18:0] regfile_r2sel_s1_agent_m0_address; // regfile_r2sel_s1_agent:m0_address -> regfile_r2sel_s1_translator:uav_address
wire [3:0] regfile_r2sel_s1_agent_m0_byteenable; // regfile_r2sel_s1_agent:m0_byteenable -> regfile_r2sel_s1_translator:uav_byteenable
wire regfile_r2sel_s1_agent_m0_read; // regfile_r2sel_s1_agent:m0_read -> regfile_r2sel_s1_translator:uav_read
wire regfile_r2sel_s1_agent_m0_readdatavalid; // regfile_r2sel_s1_translator:uav_readdatavalid -> regfile_r2sel_s1_agent:m0_readdatavalid
wire regfile_r2sel_s1_agent_m0_lock; // regfile_r2sel_s1_agent:m0_lock -> regfile_r2sel_s1_translator:uav_lock
wire [31:0] regfile_r2sel_s1_agent_m0_writedata; // regfile_r2sel_s1_agent:m0_writedata -> regfile_r2sel_s1_translator:uav_writedata
wire regfile_r2sel_s1_agent_m0_write; // regfile_r2sel_s1_agent:m0_write -> regfile_r2sel_s1_translator:uav_write
wire [2:0] regfile_r2sel_s1_agent_m0_burstcount; // regfile_r2sel_s1_agent:m0_burstcount -> regfile_r2sel_s1_translator:uav_burstcount
wire regfile_r2sel_s1_agent_rf_source_valid; // regfile_r2sel_s1_agent:rf_source_valid -> regfile_r2sel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_r2sel_s1_agent_rf_source_data; // regfile_r2sel_s1_agent:rf_source_data -> regfile_r2sel_s1_agent_rsp_fifo:in_data
wire regfile_r2sel_s1_agent_rf_source_ready; // regfile_r2sel_s1_agent_rsp_fifo:in_ready -> regfile_r2sel_s1_agent:rf_source_ready
wire regfile_r2sel_s1_agent_rf_source_startofpacket; // regfile_r2sel_s1_agent:rf_source_startofpacket -> regfile_r2sel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_r2sel_s1_agent_rf_source_endofpacket; // regfile_r2sel_s1_agent:rf_source_endofpacket -> regfile_r2sel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_r2sel_s1_agent_rsp_fifo_out_valid; // regfile_r2sel_s1_agent_rsp_fifo:out_valid -> regfile_r2sel_s1_agent:rf_sink_valid
wire [99:0] regfile_r2sel_s1_agent_rsp_fifo_out_data; // regfile_r2sel_s1_agent_rsp_fifo:out_data -> regfile_r2sel_s1_agent:rf_sink_data
wire regfile_r2sel_s1_agent_rsp_fifo_out_ready; // regfile_r2sel_s1_agent:rf_sink_ready -> regfile_r2sel_s1_agent_rsp_fifo:out_ready
wire regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket; // regfile_r2sel_s1_agent_rsp_fifo:out_startofpacket -> regfile_r2sel_s1_agent:rf_sink_startofpacket
wire regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket; // regfile_r2sel_s1_agent_rsp_fifo:out_endofpacket -> regfile_r2sel_s1_agent:rf_sink_endofpacket
wire regfile_r2sel_s1_agent_rdata_fifo_src_valid; // regfile_r2sel_s1_agent:rdata_fifo_src_valid -> regfile_r2sel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_r2sel_s1_agent_rdata_fifo_src_data; // regfile_r2sel_s1_agent:rdata_fifo_src_data -> regfile_r2sel_s1_agent:rdata_fifo_sink_data
wire regfile_r2sel_s1_agent_rdata_fifo_src_ready; // regfile_r2sel_s1_agent:rdata_fifo_sink_ready -> regfile_r2sel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_014_src_valid; // cmd_mux_014:src_valid -> regfile_r2sel_s1_agent:cp_valid
wire [98:0] cmd_mux_014_src_data; // cmd_mux_014:src_data -> regfile_r2sel_s1_agent:cp_data
wire cmd_mux_014_src_ready; // regfile_r2sel_s1_agent:cp_ready -> cmd_mux_014:src_ready
wire [31:0] cmd_mux_014_src_channel; // cmd_mux_014:src_channel -> regfile_r2sel_s1_agent:cp_channel
wire cmd_mux_014_src_startofpacket; // cmd_mux_014:src_startofpacket -> regfile_r2sel_s1_agent:cp_startofpacket
wire cmd_mux_014_src_endofpacket; // cmd_mux_014:src_endofpacket -> regfile_r2sel_s1_agent:cp_endofpacket
wire [31:0] regfile_wsel_s1_agent_m0_readdata; // regfile_wsel_s1_translator:uav_readdata -> regfile_wsel_s1_agent:m0_readdata
wire regfile_wsel_s1_agent_m0_waitrequest; // regfile_wsel_s1_translator:uav_waitrequest -> regfile_wsel_s1_agent:m0_waitrequest
wire regfile_wsel_s1_agent_m0_debugaccess; // regfile_wsel_s1_agent:m0_debugaccess -> regfile_wsel_s1_translator:uav_debugaccess
wire [18:0] regfile_wsel_s1_agent_m0_address; // regfile_wsel_s1_agent:m0_address -> regfile_wsel_s1_translator:uav_address
wire [3:0] regfile_wsel_s1_agent_m0_byteenable; // regfile_wsel_s1_agent:m0_byteenable -> regfile_wsel_s1_translator:uav_byteenable
wire regfile_wsel_s1_agent_m0_read; // regfile_wsel_s1_agent:m0_read -> regfile_wsel_s1_translator:uav_read
wire regfile_wsel_s1_agent_m0_readdatavalid; // regfile_wsel_s1_translator:uav_readdatavalid -> regfile_wsel_s1_agent:m0_readdatavalid
wire regfile_wsel_s1_agent_m0_lock; // regfile_wsel_s1_agent:m0_lock -> regfile_wsel_s1_translator:uav_lock
wire [31:0] regfile_wsel_s1_agent_m0_writedata; // regfile_wsel_s1_agent:m0_writedata -> regfile_wsel_s1_translator:uav_writedata
wire regfile_wsel_s1_agent_m0_write; // regfile_wsel_s1_agent:m0_write -> regfile_wsel_s1_translator:uav_write
wire [2:0] regfile_wsel_s1_agent_m0_burstcount; // regfile_wsel_s1_agent:m0_burstcount -> regfile_wsel_s1_translator:uav_burstcount
wire regfile_wsel_s1_agent_rf_source_valid; // regfile_wsel_s1_agent:rf_source_valid -> regfile_wsel_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_wsel_s1_agent_rf_source_data; // regfile_wsel_s1_agent:rf_source_data -> regfile_wsel_s1_agent_rsp_fifo:in_data
wire regfile_wsel_s1_agent_rf_source_ready; // regfile_wsel_s1_agent_rsp_fifo:in_ready -> regfile_wsel_s1_agent:rf_source_ready
wire regfile_wsel_s1_agent_rf_source_startofpacket; // regfile_wsel_s1_agent:rf_source_startofpacket -> regfile_wsel_s1_agent_rsp_fifo:in_startofpacket
wire regfile_wsel_s1_agent_rf_source_endofpacket; // regfile_wsel_s1_agent:rf_source_endofpacket -> regfile_wsel_s1_agent_rsp_fifo:in_endofpacket
wire regfile_wsel_s1_agent_rsp_fifo_out_valid; // regfile_wsel_s1_agent_rsp_fifo:out_valid -> regfile_wsel_s1_agent:rf_sink_valid
wire [99:0] regfile_wsel_s1_agent_rsp_fifo_out_data; // regfile_wsel_s1_agent_rsp_fifo:out_data -> regfile_wsel_s1_agent:rf_sink_data
wire regfile_wsel_s1_agent_rsp_fifo_out_ready; // regfile_wsel_s1_agent:rf_sink_ready -> regfile_wsel_s1_agent_rsp_fifo:out_ready
wire regfile_wsel_s1_agent_rsp_fifo_out_startofpacket; // regfile_wsel_s1_agent_rsp_fifo:out_startofpacket -> regfile_wsel_s1_agent:rf_sink_startofpacket
wire regfile_wsel_s1_agent_rsp_fifo_out_endofpacket; // regfile_wsel_s1_agent_rsp_fifo:out_endofpacket -> regfile_wsel_s1_agent:rf_sink_endofpacket
wire regfile_wsel_s1_agent_rdata_fifo_src_valid; // regfile_wsel_s1_agent:rdata_fifo_src_valid -> regfile_wsel_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_wsel_s1_agent_rdata_fifo_src_data; // regfile_wsel_s1_agent:rdata_fifo_src_data -> regfile_wsel_s1_agent:rdata_fifo_sink_data
wire regfile_wsel_s1_agent_rdata_fifo_src_ready; // regfile_wsel_s1_agent:rdata_fifo_sink_ready -> regfile_wsel_s1_agent:rdata_fifo_src_ready
wire cmd_mux_015_src_valid; // cmd_mux_015:src_valid -> regfile_wsel_s1_agent:cp_valid
wire [98:0] cmd_mux_015_src_data; // cmd_mux_015:src_data -> regfile_wsel_s1_agent:cp_data
wire cmd_mux_015_src_ready; // regfile_wsel_s1_agent:cp_ready -> cmd_mux_015:src_ready
wire [31:0] cmd_mux_015_src_channel; // cmd_mux_015:src_channel -> regfile_wsel_s1_agent:cp_channel
wire cmd_mux_015_src_startofpacket; // cmd_mux_015:src_startofpacket -> regfile_wsel_s1_agent:cp_startofpacket
wire cmd_mux_015_src_endofpacket; // cmd_mux_015:src_endofpacket -> regfile_wsel_s1_agent:cp_endofpacket
wire [31:0] regfile_we_s1_agent_m0_readdata; // regfile_we_s1_translator:uav_readdata -> regfile_we_s1_agent:m0_readdata
wire regfile_we_s1_agent_m0_waitrequest; // regfile_we_s1_translator:uav_waitrequest -> regfile_we_s1_agent:m0_waitrequest
wire regfile_we_s1_agent_m0_debugaccess; // regfile_we_s1_agent:m0_debugaccess -> regfile_we_s1_translator:uav_debugaccess
wire [18:0] regfile_we_s1_agent_m0_address; // regfile_we_s1_agent:m0_address -> regfile_we_s1_translator:uav_address
wire [3:0] regfile_we_s1_agent_m0_byteenable; // regfile_we_s1_agent:m0_byteenable -> regfile_we_s1_translator:uav_byteenable
wire regfile_we_s1_agent_m0_read; // regfile_we_s1_agent:m0_read -> regfile_we_s1_translator:uav_read
wire regfile_we_s1_agent_m0_readdatavalid; // regfile_we_s1_translator:uav_readdatavalid -> regfile_we_s1_agent:m0_readdatavalid
wire regfile_we_s1_agent_m0_lock; // regfile_we_s1_agent:m0_lock -> regfile_we_s1_translator:uav_lock
wire [31:0] regfile_we_s1_agent_m0_writedata; // regfile_we_s1_agent:m0_writedata -> regfile_we_s1_translator:uav_writedata
wire regfile_we_s1_agent_m0_write; // regfile_we_s1_agent:m0_write -> regfile_we_s1_translator:uav_write
wire [2:0] regfile_we_s1_agent_m0_burstcount; // regfile_we_s1_agent:m0_burstcount -> regfile_we_s1_translator:uav_burstcount
wire regfile_we_s1_agent_rf_source_valid; // regfile_we_s1_agent:rf_source_valid -> regfile_we_s1_agent_rsp_fifo:in_valid
wire [99:0] regfile_we_s1_agent_rf_source_data; // regfile_we_s1_agent:rf_source_data -> regfile_we_s1_agent_rsp_fifo:in_data
wire regfile_we_s1_agent_rf_source_ready; // regfile_we_s1_agent_rsp_fifo:in_ready -> regfile_we_s1_agent:rf_source_ready
wire regfile_we_s1_agent_rf_source_startofpacket; // regfile_we_s1_agent:rf_source_startofpacket -> regfile_we_s1_agent_rsp_fifo:in_startofpacket
wire regfile_we_s1_agent_rf_source_endofpacket; // regfile_we_s1_agent:rf_source_endofpacket -> regfile_we_s1_agent_rsp_fifo:in_endofpacket
wire regfile_we_s1_agent_rsp_fifo_out_valid; // regfile_we_s1_agent_rsp_fifo:out_valid -> regfile_we_s1_agent:rf_sink_valid
wire [99:0] regfile_we_s1_agent_rsp_fifo_out_data; // regfile_we_s1_agent_rsp_fifo:out_data -> regfile_we_s1_agent:rf_sink_data
wire regfile_we_s1_agent_rsp_fifo_out_ready; // regfile_we_s1_agent:rf_sink_ready -> regfile_we_s1_agent_rsp_fifo:out_ready
wire regfile_we_s1_agent_rsp_fifo_out_startofpacket; // regfile_we_s1_agent_rsp_fifo:out_startofpacket -> regfile_we_s1_agent:rf_sink_startofpacket
wire regfile_we_s1_agent_rsp_fifo_out_endofpacket; // regfile_we_s1_agent_rsp_fifo:out_endofpacket -> regfile_we_s1_agent:rf_sink_endofpacket
wire regfile_we_s1_agent_rdata_fifo_src_valid; // regfile_we_s1_agent:rdata_fifo_src_valid -> regfile_we_s1_agent:rdata_fifo_sink_valid
wire [33:0] regfile_we_s1_agent_rdata_fifo_src_data; // regfile_we_s1_agent:rdata_fifo_src_data -> regfile_we_s1_agent:rdata_fifo_sink_data
wire regfile_we_s1_agent_rdata_fifo_src_ready; // regfile_we_s1_agent:rdata_fifo_sink_ready -> regfile_we_s1_agent:rdata_fifo_src_ready
wire cmd_mux_016_src_valid; // cmd_mux_016:src_valid -> regfile_we_s1_agent:cp_valid
wire [98:0] cmd_mux_016_src_data; // cmd_mux_016:src_data -> regfile_we_s1_agent:cp_data
wire cmd_mux_016_src_ready; // regfile_we_s1_agent:cp_ready -> cmd_mux_016:src_ready
wire [31:0] cmd_mux_016_src_channel; // cmd_mux_016:src_channel -> regfile_we_s1_agent:cp_channel
wire cmd_mux_016_src_startofpacket; // cmd_mux_016:src_startofpacket -> regfile_we_s1_agent:cp_startofpacket
wire cmd_mux_016_src_endofpacket; // cmd_mux_016:src_endofpacket -> regfile_we_s1_agent:cp_endofpacket
wire [31:0] hex_0_s1_agent_m0_readdata; // hex_0_s1_translator:uav_readdata -> hex_0_s1_agent:m0_readdata
wire hex_0_s1_agent_m0_waitrequest; // hex_0_s1_translator:uav_waitrequest -> hex_0_s1_agent:m0_waitrequest
wire hex_0_s1_agent_m0_debugaccess; // hex_0_s1_agent:m0_debugaccess -> hex_0_s1_translator:uav_debugaccess
wire [18:0] hex_0_s1_agent_m0_address; // hex_0_s1_agent:m0_address -> hex_0_s1_translator:uav_address
wire [3:0] hex_0_s1_agent_m0_byteenable; // hex_0_s1_agent:m0_byteenable -> hex_0_s1_translator:uav_byteenable
wire hex_0_s1_agent_m0_read; // hex_0_s1_agent:m0_read -> hex_0_s1_translator:uav_read
wire hex_0_s1_agent_m0_readdatavalid; // hex_0_s1_translator:uav_readdatavalid -> hex_0_s1_agent:m0_readdatavalid
wire hex_0_s1_agent_m0_lock; // hex_0_s1_agent:m0_lock -> hex_0_s1_translator:uav_lock
wire [31:0] hex_0_s1_agent_m0_writedata; // hex_0_s1_agent:m0_writedata -> hex_0_s1_translator:uav_writedata
wire hex_0_s1_agent_m0_write; // hex_0_s1_agent:m0_write -> hex_0_s1_translator:uav_write
wire [2:0] hex_0_s1_agent_m0_burstcount; // hex_0_s1_agent:m0_burstcount -> hex_0_s1_translator:uav_burstcount
wire hex_0_s1_agent_rf_source_valid; // hex_0_s1_agent:rf_source_valid -> hex_0_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_0_s1_agent_rf_source_data; // hex_0_s1_agent:rf_source_data -> hex_0_s1_agent_rsp_fifo:in_data
wire hex_0_s1_agent_rf_source_ready; // hex_0_s1_agent_rsp_fifo:in_ready -> hex_0_s1_agent:rf_source_ready
wire hex_0_s1_agent_rf_source_startofpacket; // hex_0_s1_agent:rf_source_startofpacket -> hex_0_s1_agent_rsp_fifo:in_startofpacket
wire hex_0_s1_agent_rf_source_endofpacket; // hex_0_s1_agent:rf_source_endofpacket -> hex_0_s1_agent_rsp_fifo:in_endofpacket
wire hex_0_s1_agent_rsp_fifo_out_valid; // hex_0_s1_agent_rsp_fifo:out_valid -> hex_0_s1_agent:rf_sink_valid
wire [99:0] hex_0_s1_agent_rsp_fifo_out_data; // hex_0_s1_agent_rsp_fifo:out_data -> hex_0_s1_agent:rf_sink_data
wire hex_0_s1_agent_rsp_fifo_out_ready; // hex_0_s1_agent:rf_sink_ready -> hex_0_s1_agent_rsp_fifo:out_ready
wire hex_0_s1_agent_rsp_fifo_out_startofpacket; // hex_0_s1_agent_rsp_fifo:out_startofpacket -> hex_0_s1_agent:rf_sink_startofpacket
wire hex_0_s1_agent_rsp_fifo_out_endofpacket; // hex_0_s1_agent_rsp_fifo:out_endofpacket -> hex_0_s1_agent:rf_sink_endofpacket
wire hex_0_s1_agent_rdata_fifo_src_valid; // hex_0_s1_agent:rdata_fifo_src_valid -> hex_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_0_s1_agent_rdata_fifo_src_data; // hex_0_s1_agent:rdata_fifo_src_data -> hex_0_s1_agent:rdata_fifo_sink_data
wire hex_0_s1_agent_rdata_fifo_src_ready; // hex_0_s1_agent:rdata_fifo_sink_ready -> hex_0_s1_agent:rdata_fifo_src_ready
wire cmd_mux_017_src_valid; // cmd_mux_017:src_valid -> hex_0_s1_agent:cp_valid
wire [98:0] cmd_mux_017_src_data; // cmd_mux_017:src_data -> hex_0_s1_agent:cp_data
wire cmd_mux_017_src_ready; // hex_0_s1_agent:cp_ready -> cmd_mux_017:src_ready
wire [31:0] cmd_mux_017_src_channel; // cmd_mux_017:src_channel -> hex_0_s1_agent:cp_channel
wire cmd_mux_017_src_startofpacket; // cmd_mux_017:src_startofpacket -> hex_0_s1_agent:cp_startofpacket
wire cmd_mux_017_src_endofpacket; // cmd_mux_017:src_endofpacket -> hex_0_s1_agent:cp_endofpacket
wire [31:0] hex_1_s1_agent_m0_readdata; // hex_1_s1_translator:uav_readdata -> hex_1_s1_agent:m0_readdata
wire hex_1_s1_agent_m0_waitrequest; // hex_1_s1_translator:uav_waitrequest -> hex_1_s1_agent:m0_waitrequest
wire hex_1_s1_agent_m0_debugaccess; // hex_1_s1_agent:m0_debugaccess -> hex_1_s1_translator:uav_debugaccess
wire [18:0] hex_1_s1_agent_m0_address; // hex_1_s1_agent:m0_address -> hex_1_s1_translator:uav_address
wire [3:0] hex_1_s1_agent_m0_byteenable; // hex_1_s1_agent:m0_byteenable -> hex_1_s1_translator:uav_byteenable
wire hex_1_s1_agent_m0_read; // hex_1_s1_agent:m0_read -> hex_1_s1_translator:uav_read
wire hex_1_s1_agent_m0_readdatavalid; // hex_1_s1_translator:uav_readdatavalid -> hex_1_s1_agent:m0_readdatavalid
wire hex_1_s1_agent_m0_lock; // hex_1_s1_agent:m0_lock -> hex_1_s1_translator:uav_lock
wire [31:0] hex_1_s1_agent_m0_writedata; // hex_1_s1_agent:m0_writedata -> hex_1_s1_translator:uav_writedata
wire hex_1_s1_agent_m0_write; // hex_1_s1_agent:m0_write -> hex_1_s1_translator:uav_write
wire [2:0] hex_1_s1_agent_m0_burstcount; // hex_1_s1_agent:m0_burstcount -> hex_1_s1_translator:uav_burstcount
wire hex_1_s1_agent_rf_source_valid; // hex_1_s1_agent:rf_source_valid -> hex_1_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_1_s1_agent_rf_source_data; // hex_1_s1_agent:rf_source_data -> hex_1_s1_agent_rsp_fifo:in_data
wire hex_1_s1_agent_rf_source_ready; // hex_1_s1_agent_rsp_fifo:in_ready -> hex_1_s1_agent:rf_source_ready
wire hex_1_s1_agent_rf_source_startofpacket; // hex_1_s1_agent:rf_source_startofpacket -> hex_1_s1_agent_rsp_fifo:in_startofpacket
wire hex_1_s1_agent_rf_source_endofpacket; // hex_1_s1_agent:rf_source_endofpacket -> hex_1_s1_agent_rsp_fifo:in_endofpacket
wire hex_1_s1_agent_rsp_fifo_out_valid; // hex_1_s1_agent_rsp_fifo:out_valid -> hex_1_s1_agent:rf_sink_valid
wire [99:0] hex_1_s1_agent_rsp_fifo_out_data; // hex_1_s1_agent_rsp_fifo:out_data -> hex_1_s1_agent:rf_sink_data
wire hex_1_s1_agent_rsp_fifo_out_ready; // hex_1_s1_agent:rf_sink_ready -> hex_1_s1_agent_rsp_fifo:out_ready
wire hex_1_s1_agent_rsp_fifo_out_startofpacket; // hex_1_s1_agent_rsp_fifo:out_startofpacket -> hex_1_s1_agent:rf_sink_startofpacket
wire hex_1_s1_agent_rsp_fifo_out_endofpacket; // hex_1_s1_agent_rsp_fifo:out_endofpacket -> hex_1_s1_agent:rf_sink_endofpacket
wire hex_1_s1_agent_rdata_fifo_src_valid; // hex_1_s1_agent:rdata_fifo_src_valid -> hex_1_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_1_s1_agent_rdata_fifo_src_data; // hex_1_s1_agent:rdata_fifo_src_data -> hex_1_s1_agent:rdata_fifo_sink_data
wire hex_1_s1_agent_rdata_fifo_src_ready; // hex_1_s1_agent:rdata_fifo_sink_ready -> hex_1_s1_agent:rdata_fifo_src_ready
wire cmd_mux_018_src_valid; // cmd_mux_018:src_valid -> hex_1_s1_agent:cp_valid
wire [98:0] cmd_mux_018_src_data; // cmd_mux_018:src_data -> hex_1_s1_agent:cp_data
wire cmd_mux_018_src_ready; // hex_1_s1_agent:cp_ready -> cmd_mux_018:src_ready
wire [31:0] cmd_mux_018_src_channel; // cmd_mux_018:src_channel -> hex_1_s1_agent:cp_channel
wire cmd_mux_018_src_startofpacket; // cmd_mux_018:src_startofpacket -> hex_1_s1_agent:cp_startofpacket
wire cmd_mux_018_src_endofpacket; // cmd_mux_018:src_endofpacket -> hex_1_s1_agent:cp_endofpacket
wire [31:0] hex_2_s1_agent_m0_readdata; // hex_2_s1_translator:uav_readdata -> hex_2_s1_agent:m0_readdata
wire hex_2_s1_agent_m0_waitrequest; // hex_2_s1_translator:uav_waitrequest -> hex_2_s1_agent:m0_waitrequest
wire hex_2_s1_agent_m0_debugaccess; // hex_2_s1_agent:m0_debugaccess -> hex_2_s1_translator:uav_debugaccess
wire [18:0] hex_2_s1_agent_m0_address; // hex_2_s1_agent:m0_address -> hex_2_s1_translator:uav_address
wire [3:0] hex_2_s1_agent_m0_byteenable; // hex_2_s1_agent:m0_byteenable -> hex_2_s1_translator:uav_byteenable
wire hex_2_s1_agent_m0_read; // hex_2_s1_agent:m0_read -> hex_2_s1_translator:uav_read
wire hex_2_s1_agent_m0_readdatavalid; // hex_2_s1_translator:uav_readdatavalid -> hex_2_s1_agent:m0_readdatavalid
wire hex_2_s1_agent_m0_lock; // hex_2_s1_agent:m0_lock -> hex_2_s1_translator:uav_lock
wire [31:0] hex_2_s1_agent_m0_writedata; // hex_2_s1_agent:m0_writedata -> hex_2_s1_translator:uav_writedata
wire hex_2_s1_agent_m0_write; // hex_2_s1_agent:m0_write -> hex_2_s1_translator:uav_write
wire [2:0] hex_2_s1_agent_m0_burstcount; // hex_2_s1_agent:m0_burstcount -> hex_2_s1_translator:uav_burstcount
wire hex_2_s1_agent_rf_source_valid; // hex_2_s1_agent:rf_source_valid -> hex_2_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_2_s1_agent_rf_source_data; // hex_2_s1_agent:rf_source_data -> hex_2_s1_agent_rsp_fifo:in_data
wire hex_2_s1_agent_rf_source_ready; // hex_2_s1_agent_rsp_fifo:in_ready -> hex_2_s1_agent:rf_source_ready
wire hex_2_s1_agent_rf_source_startofpacket; // hex_2_s1_agent:rf_source_startofpacket -> hex_2_s1_agent_rsp_fifo:in_startofpacket
wire hex_2_s1_agent_rf_source_endofpacket; // hex_2_s1_agent:rf_source_endofpacket -> hex_2_s1_agent_rsp_fifo:in_endofpacket
wire hex_2_s1_agent_rsp_fifo_out_valid; // hex_2_s1_agent_rsp_fifo:out_valid -> hex_2_s1_agent:rf_sink_valid
wire [99:0] hex_2_s1_agent_rsp_fifo_out_data; // hex_2_s1_agent_rsp_fifo:out_data -> hex_2_s1_agent:rf_sink_data
wire hex_2_s1_agent_rsp_fifo_out_ready; // hex_2_s1_agent:rf_sink_ready -> hex_2_s1_agent_rsp_fifo:out_ready
wire hex_2_s1_agent_rsp_fifo_out_startofpacket; // hex_2_s1_agent_rsp_fifo:out_startofpacket -> hex_2_s1_agent:rf_sink_startofpacket
wire hex_2_s1_agent_rsp_fifo_out_endofpacket; // hex_2_s1_agent_rsp_fifo:out_endofpacket -> hex_2_s1_agent:rf_sink_endofpacket
wire hex_2_s1_agent_rdata_fifo_src_valid; // hex_2_s1_agent:rdata_fifo_src_valid -> hex_2_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_2_s1_agent_rdata_fifo_src_data; // hex_2_s1_agent:rdata_fifo_src_data -> hex_2_s1_agent:rdata_fifo_sink_data
wire hex_2_s1_agent_rdata_fifo_src_ready; // hex_2_s1_agent:rdata_fifo_sink_ready -> hex_2_s1_agent:rdata_fifo_src_ready
wire cmd_mux_019_src_valid; // cmd_mux_019:src_valid -> hex_2_s1_agent:cp_valid
wire [98:0] cmd_mux_019_src_data; // cmd_mux_019:src_data -> hex_2_s1_agent:cp_data
wire cmd_mux_019_src_ready; // hex_2_s1_agent:cp_ready -> cmd_mux_019:src_ready
wire [31:0] cmd_mux_019_src_channel; // cmd_mux_019:src_channel -> hex_2_s1_agent:cp_channel
wire cmd_mux_019_src_startofpacket; // cmd_mux_019:src_startofpacket -> hex_2_s1_agent:cp_startofpacket
wire cmd_mux_019_src_endofpacket; // cmd_mux_019:src_endofpacket -> hex_2_s1_agent:cp_endofpacket
wire [31:0] hex_3_s1_agent_m0_readdata; // hex_3_s1_translator:uav_readdata -> hex_3_s1_agent:m0_readdata
wire hex_3_s1_agent_m0_waitrequest; // hex_3_s1_translator:uav_waitrequest -> hex_3_s1_agent:m0_waitrequest
wire hex_3_s1_agent_m0_debugaccess; // hex_3_s1_agent:m0_debugaccess -> hex_3_s1_translator:uav_debugaccess
wire [18:0] hex_3_s1_agent_m0_address; // hex_3_s1_agent:m0_address -> hex_3_s1_translator:uav_address
wire [3:0] hex_3_s1_agent_m0_byteenable; // hex_3_s1_agent:m0_byteenable -> hex_3_s1_translator:uav_byteenable
wire hex_3_s1_agent_m0_read; // hex_3_s1_agent:m0_read -> hex_3_s1_translator:uav_read
wire hex_3_s1_agent_m0_readdatavalid; // hex_3_s1_translator:uav_readdatavalid -> hex_3_s1_agent:m0_readdatavalid
wire hex_3_s1_agent_m0_lock; // hex_3_s1_agent:m0_lock -> hex_3_s1_translator:uav_lock
wire [31:0] hex_3_s1_agent_m0_writedata; // hex_3_s1_agent:m0_writedata -> hex_3_s1_translator:uav_writedata
wire hex_3_s1_agent_m0_write; // hex_3_s1_agent:m0_write -> hex_3_s1_translator:uav_write
wire [2:0] hex_3_s1_agent_m0_burstcount; // hex_3_s1_agent:m0_burstcount -> hex_3_s1_translator:uav_burstcount
wire hex_3_s1_agent_rf_source_valid; // hex_3_s1_agent:rf_source_valid -> hex_3_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_3_s1_agent_rf_source_data; // hex_3_s1_agent:rf_source_data -> hex_3_s1_agent_rsp_fifo:in_data
wire hex_3_s1_agent_rf_source_ready; // hex_3_s1_agent_rsp_fifo:in_ready -> hex_3_s1_agent:rf_source_ready
wire hex_3_s1_agent_rf_source_startofpacket; // hex_3_s1_agent:rf_source_startofpacket -> hex_3_s1_agent_rsp_fifo:in_startofpacket
wire hex_3_s1_agent_rf_source_endofpacket; // hex_3_s1_agent:rf_source_endofpacket -> hex_3_s1_agent_rsp_fifo:in_endofpacket
wire hex_3_s1_agent_rsp_fifo_out_valid; // hex_3_s1_agent_rsp_fifo:out_valid -> hex_3_s1_agent:rf_sink_valid
wire [99:0] hex_3_s1_agent_rsp_fifo_out_data; // hex_3_s1_agent_rsp_fifo:out_data -> hex_3_s1_agent:rf_sink_data
wire hex_3_s1_agent_rsp_fifo_out_ready; // hex_3_s1_agent:rf_sink_ready -> hex_3_s1_agent_rsp_fifo:out_ready
wire hex_3_s1_agent_rsp_fifo_out_startofpacket; // hex_3_s1_agent_rsp_fifo:out_startofpacket -> hex_3_s1_agent:rf_sink_startofpacket
wire hex_3_s1_agent_rsp_fifo_out_endofpacket; // hex_3_s1_agent_rsp_fifo:out_endofpacket -> hex_3_s1_agent:rf_sink_endofpacket
wire hex_3_s1_agent_rdata_fifo_src_valid; // hex_3_s1_agent:rdata_fifo_src_valid -> hex_3_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_3_s1_agent_rdata_fifo_src_data; // hex_3_s1_agent:rdata_fifo_src_data -> hex_3_s1_agent:rdata_fifo_sink_data
wire hex_3_s1_agent_rdata_fifo_src_ready; // hex_3_s1_agent:rdata_fifo_sink_ready -> hex_3_s1_agent:rdata_fifo_src_ready
wire cmd_mux_020_src_valid; // cmd_mux_020:src_valid -> hex_3_s1_agent:cp_valid
wire [98:0] cmd_mux_020_src_data; // cmd_mux_020:src_data -> hex_3_s1_agent:cp_data
wire cmd_mux_020_src_ready; // hex_3_s1_agent:cp_ready -> cmd_mux_020:src_ready
wire [31:0] cmd_mux_020_src_channel; // cmd_mux_020:src_channel -> hex_3_s1_agent:cp_channel
wire cmd_mux_020_src_startofpacket; // cmd_mux_020:src_startofpacket -> hex_3_s1_agent:cp_startofpacket
wire cmd_mux_020_src_endofpacket; // cmd_mux_020:src_endofpacket -> hex_3_s1_agent:cp_endofpacket
wire [31:0] hex_4_s1_agent_m0_readdata; // hex_4_s1_translator:uav_readdata -> hex_4_s1_agent:m0_readdata
wire hex_4_s1_agent_m0_waitrequest; // hex_4_s1_translator:uav_waitrequest -> hex_4_s1_agent:m0_waitrequest
wire hex_4_s1_agent_m0_debugaccess; // hex_4_s1_agent:m0_debugaccess -> hex_4_s1_translator:uav_debugaccess
wire [18:0] hex_4_s1_agent_m0_address; // hex_4_s1_agent:m0_address -> hex_4_s1_translator:uav_address
wire [3:0] hex_4_s1_agent_m0_byteenable; // hex_4_s1_agent:m0_byteenable -> hex_4_s1_translator:uav_byteenable
wire hex_4_s1_agent_m0_read; // hex_4_s1_agent:m0_read -> hex_4_s1_translator:uav_read
wire hex_4_s1_agent_m0_readdatavalid; // hex_4_s1_translator:uav_readdatavalid -> hex_4_s1_agent:m0_readdatavalid
wire hex_4_s1_agent_m0_lock; // hex_4_s1_agent:m0_lock -> hex_4_s1_translator:uav_lock
wire [31:0] hex_4_s1_agent_m0_writedata; // hex_4_s1_agent:m0_writedata -> hex_4_s1_translator:uav_writedata
wire hex_4_s1_agent_m0_write; // hex_4_s1_agent:m0_write -> hex_4_s1_translator:uav_write
wire [2:0] hex_4_s1_agent_m0_burstcount; // hex_4_s1_agent:m0_burstcount -> hex_4_s1_translator:uav_burstcount
wire hex_4_s1_agent_rf_source_valid; // hex_4_s1_agent:rf_source_valid -> hex_4_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_4_s1_agent_rf_source_data; // hex_4_s1_agent:rf_source_data -> hex_4_s1_agent_rsp_fifo:in_data
wire hex_4_s1_agent_rf_source_ready; // hex_4_s1_agent_rsp_fifo:in_ready -> hex_4_s1_agent:rf_source_ready
wire hex_4_s1_agent_rf_source_startofpacket; // hex_4_s1_agent:rf_source_startofpacket -> hex_4_s1_agent_rsp_fifo:in_startofpacket
wire hex_4_s1_agent_rf_source_endofpacket; // hex_4_s1_agent:rf_source_endofpacket -> hex_4_s1_agent_rsp_fifo:in_endofpacket
wire hex_4_s1_agent_rsp_fifo_out_valid; // hex_4_s1_agent_rsp_fifo:out_valid -> hex_4_s1_agent:rf_sink_valid
wire [99:0] hex_4_s1_agent_rsp_fifo_out_data; // hex_4_s1_agent_rsp_fifo:out_data -> hex_4_s1_agent:rf_sink_data
wire hex_4_s1_agent_rsp_fifo_out_ready; // hex_4_s1_agent:rf_sink_ready -> hex_4_s1_agent_rsp_fifo:out_ready
wire hex_4_s1_agent_rsp_fifo_out_startofpacket; // hex_4_s1_agent_rsp_fifo:out_startofpacket -> hex_4_s1_agent:rf_sink_startofpacket
wire hex_4_s1_agent_rsp_fifo_out_endofpacket; // hex_4_s1_agent_rsp_fifo:out_endofpacket -> hex_4_s1_agent:rf_sink_endofpacket
wire hex_4_s1_agent_rdata_fifo_src_valid; // hex_4_s1_agent:rdata_fifo_src_valid -> hex_4_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_4_s1_agent_rdata_fifo_src_data; // hex_4_s1_agent:rdata_fifo_src_data -> hex_4_s1_agent:rdata_fifo_sink_data
wire hex_4_s1_agent_rdata_fifo_src_ready; // hex_4_s1_agent:rdata_fifo_sink_ready -> hex_4_s1_agent:rdata_fifo_src_ready
wire cmd_mux_021_src_valid; // cmd_mux_021:src_valid -> hex_4_s1_agent:cp_valid
wire [98:0] cmd_mux_021_src_data; // cmd_mux_021:src_data -> hex_4_s1_agent:cp_data
wire cmd_mux_021_src_ready; // hex_4_s1_agent:cp_ready -> cmd_mux_021:src_ready
wire [31:0] cmd_mux_021_src_channel; // cmd_mux_021:src_channel -> hex_4_s1_agent:cp_channel
wire cmd_mux_021_src_startofpacket; // cmd_mux_021:src_startofpacket -> hex_4_s1_agent:cp_startofpacket
wire cmd_mux_021_src_endofpacket; // cmd_mux_021:src_endofpacket -> hex_4_s1_agent:cp_endofpacket
wire [31:0] hex_5_s1_agent_m0_readdata; // hex_5_s1_translator:uav_readdata -> hex_5_s1_agent:m0_readdata
wire hex_5_s1_agent_m0_waitrequest; // hex_5_s1_translator:uav_waitrequest -> hex_5_s1_agent:m0_waitrequest
wire hex_5_s1_agent_m0_debugaccess; // hex_5_s1_agent:m0_debugaccess -> hex_5_s1_translator:uav_debugaccess
wire [18:0] hex_5_s1_agent_m0_address; // hex_5_s1_agent:m0_address -> hex_5_s1_translator:uav_address
wire [3:0] hex_5_s1_agent_m0_byteenable; // hex_5_s1_agent:m0_byteenable -> hex_5_s1_translator:uav_byteenable
wire hex_5_s1_agent_m0_read; // hex_5_s1_agent:m0_read -> hex_5_s1_translator:uav_read
wire hex_5_s1_agent_m0_readdatavalid; // hex_5_s1_translator:uav_readdatavalid -> hex_5_s1_agent:m0_readdatavalid
wire hex_5_s1_agent_m0_lock; // hex_5_s1_agent:m0_lock -> hex_5_s1_translator:uav_lock
wire [31:0] hex_5_s1_agent_m0_writedata; // hex_5_s1_agent:m0_writedata -> hex_5_s1_translator:uav_writedata
wire hex_5_s1_agent_m0_write; // hex_5_s1_agent:m0_write -> hex_5_s1_translator:uav_write
wire [2:0] hex_5_s1_agent_m0_burstcount; // hex_5_s1_agent:m0_burstcount -> hex_5_s1_translator:uav_burstcount
wire hex_5_s1_agent_rf_source_valid; // hex_5_s1_agent:rf_source_valid -> hex_5_s1_agent_rsp_fifo:in_valid
wire [99:0] hex_5_s1_agent_rf_source_data; // hex_5_s1_agent:rf_source_data -> hex_5_s1_agent_rsp_fifo:in_data
wire hex_5_s1_agent_rf_source_ready; // hex_5_s1_agent_rsp_fifo:in_ready -> hex_5_s1_agent:rf_source_ready
wire hex_5_s1_agent_rf_source_startofpacket; // hex_5_s1_agent:rf_source_startofpacket -> hex_5_s1_agent_rsp_fifo:in_startofpacket
wire hex_5_s1_agent_rf_source_endofpacket; // hex_5_s1_agent:rf_source_endofpacket -> hex_5_s1_agent_rsp_fifo:in_endofpacket
wire hex_5_s1_agent_rsp_fifo_out_valid; // hex_5_s1_agent_rsp_fifo:out_valid -> hex_5_s1_agent:rf_sink_valid
wire [99:0] hex_5_s1_agent_rsp_fifo_out_data; // hex_5_s1_agent_rsp_fifo:out_data -> hex_5_s1_agent:rf_sink_data
wire hex_5_s1_agent_rsp_fifo_out_ready; // hex_5_s1_agent:rf_sink_ready -> hex_5_s1_agent_rsp_fifo:out_ready
wire hex_5_s1_agent_rsp_fifo_out_startofpacket; // hex_5_s1_agent_rsp_fifo:out_startofpacket -> hex_5_s1_agent:rf_sink_startofpacket
wire hex_5_s1_agent_rsp_fifo_out_endofpacket; // hex_5_s1_agent_rsp_fifo:out_endofpacket -> hex_5_s1_agent:rf_sink_endofpacket
wire hex_5_s1_agent_rdata_fifo_src_valid; // hex_5_s1_agent:rdata_fifo_src_valid -> hex_5_s1_agent:rdata_fifo_sink_valid
wire [33:0] hex_5_s1_agent_rdata_fifo_src_data; // hex_5_s1_agent:rdata_fifo_src_data -> hex_5_s1_agent:rdata_fifo_sink_data
wire hex_5_s1_agent_rdata_fifo_src_ready; // hex_5_s1_agent:rdata_fifo_sink_ready -> hex_5_s1_agent:rdata_fifo_src_ready
wire cmd_mux_022_src_valid; // cmd_mux_022:src_valid -> hex_5_s1_agent:cp_valid
wire [98:0] cmd_mux_022_src_data; // cmd_mux_022:src_data -> hex_5_s1_agent:cp_data
wire cmd_mux_022_src_ready; // hex_5_s1_agent:cp_ready -> cmd_mux_022:src_ready
wire [31:0] cmd_mux_022_src_channel; // cmd_mux_022:src_channel -> hex_5_s1_agent:cp_channel
wire cmd_mux_022_src_startofpacket; // cmd_mux_022:src_startofpacket -> hex_5_s1_agent:cp_startofpacket
wire cmd_mux_022_src_endofpacket; // cmd_mux_022:src_endofpacket -> hex_5_s1_agent:cp_endofpacket
wire [31:0] alu_a_s1_agent_m0_readdata; // alu_a_s1_translator:uav_readdata -> alu_a_s1_agent:m0_readdata
wire alu_a_s1_agent_m0_waitrequest; // alu_a_s1_translator:uav_waitrequest -> alu_a_s1_agent:m0_waitrequest
wire alu_a_s1_agent_m0_debugaccess; // alu_a_s1_agent:m0_debugaccess -> alu_a_s1_translator:uav_debugaccess
wire [18:0] alu_a_s1_agent_m0_address; // alu_a_s1_agent:m0_address -> alu_a_s1_translator:uav_address
wire [3:0] alu_a_s1_agent_m0_byteenable; // alu_a_s1_agent:m0_byteenable -> alu_a_s1_translator:uav_byteenable
wire alu_a_s1_agent_m0_read; // alu_a_s1_agent:m0_read -> alu_a_s1_translator:uav_read
wire alu_a_s1_agent_m0_readdatavalid; // alu_a_s1_translator:uav_readdatavalid -> alu_a_s1_agent:m0_readdatavalid
wire alu_a_s1_agent_m0_lock; // alu_a_s1_agent:m0_lock -> alu_a_s1_translator:uav_lock
wire [31:0] alu_a_s1_agent_m0_writedata; // alu_a_s1_agent:m0_writedata -> alu_a_s1_translator:uav_writedata
wire alu_a_s1_agent_m0_write; // alu_a_s1_agent:m0_write -> alu_a_s1_translator:uav_write
wire [2:0] alu_a_s1_agent_m0_burstcount; // alu_a_s1_agent:m0_burstcount -> alu_a_s1_translator:uav_burstcount
wire alu_a_s1_agent_rf_source_valid; // alu_a_s1_agent:rf_source_valid -> alu_a_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_a_s1_agent_rf_source_data; // alu_a_s1_agent:rf_source_data -> alu_a_s1_agent_rsp_fifo:in_data
wire alu_a_s1_agent_rf_source_ready; // alu_a_s1_agent_rsp_fifo:in_ready -> alu_a_s1_agent:rf_source_ready
wire alu_a_s1_agent_rf_source_startofpacket; // alu_a_s1_agent:rf_source_startofpacket -> alu_a_s1_agent_rsp_fifo:in_startofpacket
wire alu_a_s1_agent_rf_source_endofpacket; // alu_a_s1_agent:rf_source_endofpacket -> alu_a_s1_agent_rsp_fifo:in_endofpacket
wire alu_a_s1_agent_rsp_fifo_out_valid; // alu_a_s1_agent_rsp_fifo:out_valid -> alu_a_s1_agent:rf_sink_valid
wire [99:0] alu_a_s1_agent_rsp_fifo_out_data; // alu_a_s1_agent_rsp_fifo:out_data -> alu_a_s1_agent:rf_sink_data
wire alu_a_s1_agent_rsp_fifo_out_ready; // alu_a_s1_agent:rf_sink_ready -> alu_a_s1_agent_rsp_fifo:out_ready
wire alu_a_s1_agent_rsp_fifo_out_startofpacket; // alu_a_s1_agent_rsp_fifo:out_startofpacket -> alu_a_s1_agent:rf_sink_startofpacket
wire alu_a_s1_agent_rsp_fifo_out_endofpacket; // alu_a_s1_agent_rsp_fifo:out_endofpacket -> alu_a_s1_agent:rf_sink_endofpacket
wire alu_a_s1_agent_rdata_fifo_src_valid; // alu_a_s1_agent:rdata_fifo_src_valid -> alu_a_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_a_s1_agent_rdata_fifo_src_data; // alu_a_s1_agent:rdata_fifo_src_data -> alu_a_s1_agent:rdata_fifo_sink_data
wire alu_a_s1_agent_rdata_fifo_src_ready; // alu_a_s1_agent:rdata_fifo_sink_ready -> alu_a_s1_agent:rdata_fifo_src_ready
wire cmd_mux_023_src_valid; // cmd_mux_023:src_valid -> alu_a_s1_agent:cp_valid
wire [98:0] cmd_mux_023_src_data; // cmd_mux_023:src_data -> alu_a_s1_agent:cp_data
wire cmd_mux_023_src_ready; // alu_a_s1_agent:cp_ready -> cmd_mux_023:src_ready
wire [31:0] cmd_mux_023_src_channel; // cmd_mux_023:src_channel -> alu_a_s1_agent:cp_channel
wire cmd_mux_023_src_startofpacket; // cmd_mux_023:src_startofpacket -> alu_a_s1_agent:cp_startofpacket
wire cmd_mux_023_src_endofpacket; // cmd_mux_023:src_endofpacket -> alu_a_s1_agent:cp_endofpacket
wire [31:0] alu_b_s1_agent_m0_readdata; // alu_b_s1_translator:uav_readdata -> alu_b_s1_agent:m0_readdata
wire alu_b_s1_agent_m0_waitrequest; // alu_b_s1_translator:uav_waitrequest -> alu_b_s1_agent:m0_waitrequest
wire alu_b_s1_agent_m0_debugaccess; // alu_b_s1_agent:m0_debugaccess -> alu_b_s1_translator:uav_debugaccess
wire [18:0] alu_b_s1_agent_m0_address; // alu_b_s1_agent:m0_address -> alu_b_s1_translator:uav_address
wire [3:0] alu_b_s1_agent_m0_byteenable; // alu_b_s1_agent:m0_byteenable -> alu_b_s1_translator:uav_byteenable
wire alu_b_s1_agent_m0_read; // alu_b_s1_agent:m0_read -> alu_b_s1_translator:uav_read
wire alu_b_s1_agent_m0_readdatavalid; // alu_b_s1_translator:uav_readdatavalid -> alu_b_s1_agent:m0_readdatavalid
wire alu_b_s1_agent_m0_lock; // alu_b_s1_agent:m0_lock -> alu_b_s1_translator:uav_lock
wire [31:0] alu_b_s1_agent_m0_writedata; // alu_b_s1_agent:m0_writedata -> alu_b_s1_translator:uav_writedata
wire alu_b_s1_agent_m0_write; // alu_b_s1_agent:m0_write -> alu_b_s1_translator:uav_write
wire [2:0] alu_b_s1_agent_m0_burstcount; // alu_b_s1_agent:m0_burstcount -> alu_b_s1_translator:uav_burstcount
wire alu_b_s1_agent_rf_source_valid; // alu_b_s1_agent:rf_source_valid -> alu_b_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_b_s1_agent_rf_source_data; // alu_b_s1_agent:rf_source_data -> alu_b_s1_agent_rsp_fifo:in_data
wire alu_b_s1_agent_rf_source_ready; // alu_b_s1_agent_rsp_fifo:in_ready -> alu_b_s1_agent:rf_source_ready
wire alu_b_s1_agent_rf_source_startofpacket; // alu_b_s1_agent:rf_source_startofpacket -> alu_b_s1_agent_rsp_fifo:in_startofpacket
wire alu_b_s1_agent_rf_source_endofpacket; // alu_b_s1_agent:rf_source_endofpacket -> alu_b_s1_agent_rsp_fifo:in_endofpacket
wire alu_b_s1_agent_rsp_fifo_out_valid; // alu_b_s1_agent_rsp_fifo:out_valid -> alu_b_s1_agent:rf_sink_valid
wire [99:0] alu_b_s1_agent_rsp_fifo_out_data; // alu_b_s1_agent_rsp_fifo:out_data -> alu_b_s1_agent:rf_sink_data
wire alu_b_s1_agent_rsp_fifo_out_ready; // alu_b_s1_agent:rf_sink_ready -> alu_b_s1_agent_rsp_fifo:out_ready
wire alu_b_s1_agent_rsp_fifo_out_startofpacket; // alu_b_s1_agent_rsp_fifo:out_startofpacket -> alu_b_s1_agent:rf_sink_startofpacket
wire alu_b_s1_agent_rsp_fifo_out_endofpacket; // alu_b_s1_agent_rsp_fifo:out_endofpacket -> alu_b_s1_agent:rf_sink_endofpacket
wire alu_b_s1_agent_rdata_fifo_src_valid; // alu_b_s1_agent:rdata_fifo_src_valid -> alu_b_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_b_s1_agent_rdata_fifo_src_data; // alu_b_s1_agent:rdata_fifo_src_data -> alu_b_s1_agent:rdata_fifo_sink_data
wire alu_b_s1_agent_rdata_fifo_src_ready; // alu_b_s1_agent:rdata_fifo_sink_ready -> alu_b_s1_agent:rdata_fifo_src_ready
wire cmd_mux_024_src_valid; // cmd_mux_024:src_valid -> alu_b_s1_agent:cp_valid
wire [98:0] cmd_mux_024_src_data; // cmd_mux_024:src_data -> alu_b_s1_agent:cp_data
wire cmd_mux_024_src_ready; // alu_b_s1_agent:cp_ready -> cmd_mux_024:src_ready
wire [31:0] cmd_mux_024_src_channel; // cmd_mux_024:src_channel -> alu_b_s1_agent:cp_channel
wire cmd_mux_024_src_startofpacket; // cmd_mux_024:src_startofpacket -> alu_b_s1_agent:cp_startofpacket
wire cmd_mux_024_src_endofpacket; // cmd_mux_024:src_endofpacket -> alu_b_s1_agent:cp_endofpacket
wire [31:0] alu_control_s1_agent_m0_readdata; // alu_control_s1_translator:uav_readdata -> alu_control_s1_agent:m0_readdata
wire alu_control_s1_agent_m0_waitrequest; // alu_control_s1_translator:uav_waitrequest -> alu_control_s1_agent:m0_waitrequest
wire alu_control_s1_agent_m0_debugaccess; // alu_control_s1_agent:m0_debugaccess -> alu_control_s1_translator:uav_debugaccess
wire [18:0] alu_control_s1_agent_m0_address; // alu_control_s1_agent:m0_address -> alu_control_s1_translator:uav_address
wire [3:0] alu_control_s1_agent_m0_byteenable; // alu_control_s1_agent:m0_byteenable -> alu_control_s1_translator:uav_byteenable
wire alu_control_s1_agent_m0_read; // alu_control_s1_agent:m0_read -> alu_control_s1_translator:uav_read
wire alu_control_s1_agent_m0_readdatavalid; // alu_control_s1_translator:uav_readdatavalid -> alu_control_s1_agent:m0_readdatavalid
wire alu_control_s1_agent_m0_lock; // alu_control_s1_agent:m0_lock -> alu_control_s1_translator:uav_lock
wire [31:0] alu_control_s1_agent_m0_writedata; // alu_control_s1_agent:m0_writedata -> alu_control_s1_translator:uav_writedata
wire alu_control_s1_agent_m0_write; // alu_control_s1_agent:m0_write -> alu_control_s1_translator:uav_write
wire [2:0] alu_control_s1_agent_m0_burstcount; // alu_control_s1_agent:m0_burstcount -> alu_control_s1_translator:uav_burstcount
wire alu_control_s1_agent_rf_source_valid; // alu_control_s1_agent:rf_source_valid -> alu_control_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_control_s1_agent_rf_source_data; // alu_control_s1_agent:rf_source_data -> alu_control_s1_agent_rsp_fifo:in_data
wire alu_control_s1_agent_rf_source_ready; // alu_control_s1_agent_rsp_fifo:in_ready -> alu_control_s1_agent:rf_source_ready
wire alu_control_s1_agent_rf_source_startofpacket; // alu_control_s1_agent:rf_source_startofpacket -> alu_control_s1_agent_rsp_fifo:in_startofpacket
wire alu_control_s1_agent_rf_source_endofpacket; // alu_control_s1_agent:rf_source_endofpacket -> alu_control_s1_agent_rsp_fifo:in_endofpacket
wire alu_control_s1_agent_rsp_fifo_out_valid; // alu_control_s1_agent_rsp_fifo:out_valid -> alu_control_s1_agent:rf_sink_valid
wire [99:0] alu_control_s1_agent_rsp_fifo_out_data; // alu_control_s1_agent_rsp_fifo:out_data -> alu_control_s1_agent:rf_sink_data
wire alu_control_s1_agent_rsp_fifo_out_ready; // alu_control_s1_agent:rf_sink_ready -> alu_control_s1_agent_rsp_fifo:out_ready
wire alu_control_s1_agent_rsp_fifo_out_startofpacket; // alu_control_s1_agent_rsp_fifo:out_startofpacket -> alu_control_s1_agent:rf_sink_startofpacket
wire alu_control_s1_agent_rsp_fifo_out_endofpacket; // alu_control_s1_agent_rsp_fifo:out_endofpacket -> alu_control_s1_agent:rf_sink_endofpacket
wire alu_control_s1_agent_rdata_fifo_src_valid; // alu_control_s1_agent:rdata_fifo_src_valid -> alu_control_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_control_s1_agent_rdata_fifo_src_data; // alu_control_s1_agent:rdata_fifo_src_data -> alu_control_s1_agent:rdata_fifo_sink_data
wire alu_control_s1_agent_rdata_fifo_src_ready; // alu_control_s1_agent:rdata_fifo_sink_ready -> alu_control_s1_agent:rdata_fifo_src_ready
wire cmd_mux_025_src_valid; // cmd_mux_025:src_valid -> alu_control_s1_agent:cp_valid
wire [98:0] cmd_mux_025_src_data; // cmd_mux_025:src_data -> alu_control_s1_agent:cp_data
wire cmd_mux_025_src_ready; // alu_control_s1_agent:cp_ready -> cmd_mux_025:src_ready
wire [31:0] cmd_mux_025_src_channel; // cmd_mux_025:src_channel -> alu_control_s1_agent:cp_channel
wire cmd_mux_025_src_startofpacket; // cmd_mux_025:src_startofpacket -> alu_control_s1_agent:cp_startofpacket
wire cmd_mux_025_src_endofpacket; // cmd_mux_025:src_endofpacket -> alu_control_s1_agent:cp_endofpacket
wire [31:0] alu_out_s1_agent_m0_readdata; // alu_out_s1_translator:uav_readdata -> alu_out_s1_agent:m0_readdata
wire alu_out_s1_agent_m0_waitrequest; // alu_out_s1_translator:uav_waitrequest -> alu_out_s1_agent:m0_waitrequest
wire alu_out_s1_agent_m0_debugaccess; // alu_out_s1_agent:m0_debugaccess -> alu_out_s1_translator:uav_debugaccess
wire [18:0] alu_out_s1_agent_m0_address; // alu_out_s1_agent:m0_address -> alu_out_s1_translator:uav_address
wire [3:0] alu_out_s1_agent_m0_byteenable; // alu_out_s1_agent:m0_byteenable -> alu_out_s1_translator:uav_byteenable
wire alu_out_s1_agent_m0_read; // alu_out_s1_agent:m0_read -> alu_out_s1_translator:uav_read
wire alu_out_s1_agent_m0_readdatavalid; // alu_out_s1_translator:uav_readdatavalid -> alu_out_s1_agent:m0_readdatavalid
wire alu_out_s1_agent_m0_lock; // alu_out_s1_agent:m0_lock -> alu_out_s1_translator:uav_lock
wire [31:0] alu_out_s1_agent_m0_writedata; // alu_out_s1_agent:m0_writedata -> alu_out_s1_translator:uav_writedata
wire alu_out_s1_agent_m0_write; // alu_out_s1_agent:m0_write -> alu_out_s1_translator:uav_write
wire [2:0] alu_out_s1_agent_m0_burstcount; // alu_out_s1_agent:m0_burstcount -> alu_out_s1_translator:uav_burstcount
wire alu_out_s1_agent_rf_source_valid; // alu_out_s1_agent:rf_source_valid -> alu_out_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_out_s1_agent_rf_source_data; // alu_out_s1_agent:rf_source_data -> alu_out_s1_agent_rsp_fifo:in_data
wire alu_out_s1_agent_rf_source_ready; // alu_out_s1_agent_rsp_fifo:in_ready -> alu_out_s1_agent:rf_source_ready
wire alu_out_s1_agent_rf_source_startofpacket; // alu_out_s1_agent:rf_source_startofpacket -> alu_out_s1_agent_rsp_fifo:in_startofpacket
wire alu_out_s1_agent_rf_source_endofpacket; // alu_out_s1_agent:rf_source_endofpacket -> alu_out_s1_agent_rsp_fifo:in_endofpacket
wire alu_out_s1_agent_rsp_fifo_out_valid; // alu_out_s1_agent_rsp_fifo:out_valid -> alu_out_s1_agent:rf_sink_valid
wire [99:0] alu_out_s1_agent_rsp_fifo_out_data; // alu_out_s1_agent_rsp_fifo:out_data -> alu_out_s1_agent:rf_sink_data
wire alu_out_s1_agent_rsp_fifo_out_ready; // alu_out_s1_agent:rf_sink_ready -> alu_out_s1_agent_rsp_fifo:out_ready
wire alu_out_s1_agent_rsp_fifo_out_startofpacket; // alu_out_s1_agent_rsp_fifo:out_startofpacket -> alu_out_s1_agent:rf_sink_startofpacket
wire alu_out_s1_agent_rsp_fifo_out_endofpacket; // alu_out_s1_agent_rsp_fifo:out_endofpacket -> alu_out_s1_agent:rf_sink_endofpacket
wire alu_out_s1_agent_rdata_fifo_src_valid; // alu_out_s1_agent:rdata_fifo_src_valid -> alu_out_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_out_s1_agent_rdata_fifo_src_data; // alu_out_s1_agent:rdata_fifo_src_data -> alu_out_s1_agent:rdata_fifo_sink_data
wire alu_out_s1_agent_rdata_fifo_src_ready; // alu_out_s1_agent:rdata_fifo_sink_ready -> alu_out_s1_agent:rdata_fifo_src_ready
wire cmd_mux_026_src_valid; // cmd_mux_026:src_valid -> alu_out_s1_agent:cp_valid
wire [98:0] cmd_mux_026_src_data; // cmd_mux_026:src_data -> alu_out_s1_agent:cp_data
wire cmd_mux_026_src_ready; // alu_out_s1_agent:cp_ready -> cmd_mux_026:src_ready
wire [31:0] cmd_mux_026_src_channel; // cmd_mux_026:src_channel -> alu_out_s1_agent:cp_channel
wire cmd_mux_026_src_startofpacket; // cmd_mux_026:src_startofpacket -> alu_out_s1_agent:cp_startofpacket
wire cmd_mux_026_src_endofpacket; // cmd_mux_026:src_endofpacket -> alu_out_s1_agent:cp_endofpacket
wire [31:0] alu_zero_s1_agent_m0_readdata; // alu_zero_s1_translator:uav_readdata -> alu_zero_s1_agent:m0_readdata
wire alu_zero_s1_agent_m0_waitrequest; // alu_zero_s1_translator:uav_waitrequest -> alu_zero_s1_agent:m0_waitrequest
wire alu_zero_s1_agent_m0_debugaccess; // alu_zero_s1_agent:m0_debugaccess -> alu_zero_s1_translator:uav_debugaccess
wire [18:0] alu_zero_s1_agent_m0_address; // alu_zero_s1_agent:m0_address -> alu_zero_s1_translator:uav_address
wire [3:0] alu_zero_s1_agent_m0_byteenable; // alu_zero_s1_agent:m0_byteenable -> alu_zero_s1_translator:uav_byteenable
wire alu_zero_s1_agent_m0_read; // alu_zero_s1_agent:m0_read -> alu_zero_s1_translator:uav_read
wire alu_zero_s1_agent_m0_readdatavalid; // alu_zero_s1_translator:uav_readdatavalid -> alu_zero_s1_agent:m0_readdatavalid
wire alu_zero_s1_agent_m0_lock; // alu_zero_s1_agent:m0_lock -> alu_zero_s1_translator:uav_lock
wire [31:0] alu_zero_s1_agent_m0_writedata; // alu_zero_s1_agent:m0_writedata -> alu_zero_s1_translator:uav_writedata
wire alu_zero_s1_agent_m0_write; // alu_zero_s1_agent:m0_write -> alu_zero_s1_translator:uav_write
wire [2:0] alu_zero_s1_agent_m0_burstcount; // alu_zero_s1_agent:m0_burstcount -> alu_zero_s1_translator:uav_burstcount
wire alu_zero_s1_agent_rf_source_valid; // alu_zero_s1_agent:rf_source_valid -> alu_zero_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_zero_s1_agent_rf_source_data; // alu_zero_s1_agent:rf_source_data -> alu_zero_s1_agent_rsp_fifo:in_data
wire alu_zero_s1_agent_rf_source_ready; // alu_zero_s1_agent_rsp_fifo:in_ready -> alu_zero_s1_agent:rf_source_ready
wire alu_zero_s1_agent_rf_source_startofpacket; // alu_zero_s1_agent:rf_source_startofpacket -> alu_zero_s1_agent_rsp_fifo:in_startofpacket
wire alu_zero_s1_agent_rf_source_endofpacket; // alu_zero_s1_agent:rf_source_endofpacket -> alu_zero_s1_agent_rsp_fifo:in_endofpacket
wire alu_zero_s1_agent_rsp_fifo_out_valid; // alu_zero_s1_agent_rsp_fifo:out_valid -> alu_zero_s1_agent:rf_sink_valid
wire [99:0] alu_zero_s1_agent_rsp_fifo_out_data; // alu_zero_s1_agent_rsp_fifo:out_data -> alu_zero_s1_agent:rf_sink_data
wire alu_zero_s1_agent_rsp_fifo_out_ready; // alu_zero_s1_agent:rf_sink_ready -> alu_zero_s1_agent_rsp_fifo:out_ready
wire alu_zero_s1_agent_rsp_fifo_out_startofpacket; // alu_zero_s1_agent_rsp_fifo:out_startofpacket -> alu_zero_s1_agent:rf_sink_startofpacket
wire alu_zero_s1_agent_rsp_fifo_out_endofpacket; // alu_zero_s1_agent_rsp_fifo:out_endofpacket -> alu_zero_s1_agent:rf_sink_endofpacket
wire alu_zero_s1_agent_rdata_fifo_src_valid; // alu_zero_s1_agent:rdata_fifo_src_valid -> alu_zero_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_zero_s1_agent_rdata_fifo_src_data; // alu_zero_s1_agent:rdata_fifo_src_data -> alu_zero_s1_agent:rdata_fifo_sink_data
wire alu_zero_s1_agent_rdata_fifo_src_ready; // alu_zero_s1_agent:rdata_fifo_sink_ready -> alu_zero_s1_agent:rdata_fifo_src_ready
wire cmd_mux_027_src_valid; // cmd_mux_027:src_valid -> alu_zero_s1_agent:cp_valid
wire [98:0] cmd_mux_027_src_data; // cmd_mux_027:src_data -> alu_zero_s1_agent:cp_data
wire cmd_mux_027_src_ready; // alu_zero_s1_agent:cp_ready -> cmd_mux_027:src_ready
wire [31:0] cmd_mux_027_src_channel; // cmd_mux_027:src_channel -> alu_zero_s1_agent:cp_channel
wire cmd_mux_027_src_startofpacket; // cmd_mux_027:src_startofpacket -> alu_zero_s1_agent:cp_startofpacket
wire cmd_mux_027_src_endofpacket; // cmd_mux_027:src_endofpacket -> alu_zero_s1_agent:cp_endofpacket
wire [31:0] alu_overflow_s1_agent_m0_readdata; // alu_overflow_s1_translator:uav_readdata -> alu_overflow_s1_agent:m0_readdata
wire alu_overflow_s1_agent_m0_waitrequest; // alu_overflow_s1_translator:uav_waitrequest -> alu_overflow_s1_agent:m0_waitrequest
wire alu_overflow_s1_agent_m0_debugaccess; // alu_overflow_s1_agent:m0_debugaccess -> alu_overflow_s1_translator:uav_debugaccess
wire [18:0] alu_overflow_s1_agent_m0_address; // alu_overflow_s1_agent:m0_address -> alu_overflow_s1_translator:uav_address
wire [3:0] alu_overflow_s1_agent_m0_byteenable; // alu_overflow_s1_agent:m0_byteenable -> alu_overflow_s1_translator:uav_byteenable
wire alu_overflow_s1_agent_m0_read; // alu_overflow_s1_agent:m0_read -> alu_overflow_s1_translator:uav_read
wire alu_overflow_s1_agent_m0_readdatavalid; // alu_overflow_s1_translator:uav_readdatavalid -> alu_overflow_s1_agent:m0_readdatavalid
wire alu_overflow_s1_agent_m0_lock; // alu_overflow_s1_agent:m0_lock -> alu_overflow_s1_translator:uav_lock
wire [31:0] alu_overflow_s1_agent_m0_writedata; // alu_overflow_s1_agent:m0_writedata -> alu_overflow_s1_translator:uav_writedata
wire alu_overflow_s1_agent_m0_write; // alu_overflow_s1_agent:m0_write -> alu_overflow_s1_translator:uav_write
wire [2:0] alu_overflow_s1_agent_m0_burstcount; // alu_overflow_s1_agent:m0_burstcount -> alu_overflow_s1_translator:uav_burstcount
wire alu_overflow_s1_agent_rf_source_valid; // alu_overflow_s1_agent:rf_source_valid -> alu_overflow_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_overflow_s1_agent_rf_source_data; // alu_overflow_s1_agent:rf_source_data -> alu_overflow_s1_agent_rsp_fifo:in_data
wire alu_overflow_s1_agent_rf_source_ready; // alu_overflow_s1_agent_rsp_fifo:in_ready -> alu_overflow_s1_agent:rf_source_ready
wire alu_overflow_s1_agent_rf_source_startofpacket; // alu_overflow_s1_agent:rf_source_startofpacket -> alu_overflow_s1_agent_rsp_fifo:in_startofpacket
wire alu_overflow_s1_agent_rf_source_endofpacket; // alu_overflow_s1_agent:rf_source_endofpacket -> alu_overflow_s1_agent_rsp_fifo:in_endofpacket
wire alu_overflow_s1_agent_rsp_fifo_out_valid; // alu_overflow_s1_agent_rsp_fifo:out_valid -> alu_overflow_s1_agent:rf_sink_valid
wire [99:0] alu_overflow_s1_agent_rsp_fifo_out_data; // alu_overflow_s1_agent_rsp_fifo:out_data -> alu_overflow_s1_agent:rf_sink_data
wire alu_overflow_s1_agent_rsp_fifo_out_ready; // alu_overflow_s1_agent:rf_sink_ready -> alu_overflow_s1_agent_rsp_fifo:out_ready
wire alu_overflow_s1_agent_rsp_fifo_out_startofpacket; // alu_overflow_s1_agent_rsp_fifo:out_startofpacket -> alu_overflow_s1_agent:rf_sink_startofpacket
wire alu_overflow_s1_agent_rsp_fifo_out_endofpacket; // alu_overflow_s1_agent_rsp_fifo:out_endofpacket -> alu_overflow_s1_agent:rf_sink_endofpacket
wire alu_overflow_s1_agent_rdata_fifo_src_valid; // alu_overflow_s1_agent:rdata_fifo_src_valid -> alu_overflow_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_overflow_s1_agent_rdata_fifo_src_data; // alu_overflow_s1_agent:rdata_fifo_src_data -> alu_overflow_s1_agent:rdata_fifo_sink_data
wire alu_overflow_s1_agent_rdata_fifo_src_ready; // alu_overflow_s1_agent:rdata_fifo_sink_ready -> alu_overflow_s1_agent:rdata_fifo_src_ready
wire cmd_mux_028_src_valid; // cmd_mux_028:src_valid -> alu_overflow_s1_agent:cp_valid
wire [98:0] cmd_mux_028_src_data; // cmd_mux_028:src_data -> alu_overflow_s1_agent:cp_data
wire cmd_mux_028_src_ready; // alu_overflow_s1_agent:cp_ready -> cmd_mux_028:src_ready
wire [31:0] cmd_mux_028_src_channel; // cmd_mux_028:src_channel -> alu_overflow_s1_agent:cp_channel
wire cmd_mux_028_src_startofpacket; // cmd_mux_028:src_startofpacket -> alu_overflow_s1_agent:cp_startofpacket
wire cmd_mux_028_src_endofpacket; // cmd_mux_028:src_endofpacket -> alu_overflow_s1_agent:cp_endofpacket
wire [31:0] alu_carry_out_s1_agent_m0_readdata; // alu_carry_out_s1_translator:uav_readdata -> alu_carry_out_s1_agent:m0_readdata
wire alu_carry_out_s1_agent_m0_waitrequest; // alu_carry_out_s1_translator:uav_waitrequest -> alu_carry_out_s1_agent:m0_waitrequest
wire alu_carry_out_s1_agent_m0_debugaccess; // alu_carry_out_s1_agent:m0_debugaccess -> alu_carry_out_s1_translator:uav_debugaccess
wire [18:0] alu_carry_out_s1_agent_m0_address; // alu_carry_out_s1_agent:m0_address -> alu_carry_out_s1_translator:uav_address
wire [3:0] alu_carry_out_s1_agent_m0_byteenable; // alu_carry_out_s1_agent:m0_byteenable -> alu_carry_out_s1_translator:uav_byteenable
wire alu_carry_out_s1_agent_m0_read; // alu_carry_out_s1_agent:m0_read -> alu_carry_out_s1_translator:uav_read
wire alu_carry_out_s1_agent_m0_readdatavalid; // alu_carry_out_s1_translator:uav_readdatavalid -> alu_carry_out_s1_agent:m0_readdatavalid
wire alu_carry_out_s1_agent_m0_lock; // alu_carry_out_s1_agent:m0_lock -> alu_carry_out_s1_translator:uav_lock
wire [31:0] alu_carry_out_s1_agent_m0_writedata; // alu_carry_out_s1_agent:m0_writedata -> alu_carry_out_s1_translator:uav_writedata
wire alu_carry_out_s1_agent_m0_write; // alu_carry_out_s1_agent:m0_write -> alu_carry_out_s1_translator:uav_write
wire [2:0] alu_carry_out_s1_agent_m0_burstcount; // alu_carry_out_s1_agent:m0_burstcount -> alu_carry_out_s1_translator:uav_burstcount
wire alu_carry_out_s1_agent_rf_source_valid; // alu_carry_out_s1_agent:rf_source_valid -> alu_carry_out_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_carry_out_s1_agent_rf_source_data; // alu_carry_out_s1_agent:rf_source_data -> alu_carry_out_s1_agent_rsp_fifo:in_data
wire alu_carry_out_s1_agent_rf_source_ready; // alu_carry_out_s1_agent_rsp_fifo:in_ready -> alu_carry_out_s1_agent:rf_source_ready
wire alu_carry_out_s1_agent_rf_source_startofpacket; // alu_carry_out_s1_agent:rf_source_startofpacket -> alu_carry_out_s1_agent_rsp_fifo:in_startofpacket
wire alu_carry_out_s1_agent_rf_source_endofpacket; // alu_carry_out_s1_agent:rf_source_endofpacket -> alu_carry_out_s1_agent_rsp_fifo:in_endofpacket
wire alu_carry_out_s1_agent_rsp_fifo_out_valid; // alu_carry_out_s1_agent_rsp_fifo:out_valid -> alu_carry_out_s1_agent:rf_sink_valid
wire [99:0] alu_carry_out_s1_agent_rsp_fifo_out_data; // alu_carry_out_s1_agent_rsp_fifo:out_data -> alu_carry_out_s1_agent:rf_sink_data
wire alu_carry_out_s1_agent_rsp_fifo_out_ready; // alu_carry_out_s1_agent:rf_sink_ready -> alu_carry_out_s1_agent_rsp_fifo:out_ready
wire alu_carry_out_s1_agent_rsp_fifo_out_startofpacket; // alu_carry_out_s1_agent_rsp_fifo:out_startofpacket -> alu_carry_out_s1_agent:rf_sink_startofpacket
wire alu_carry_out_s1_agent_rsp_fifo_out_endofpacket; // alu_carry_out_s1_agent_rsp_fifo:out_endofpacket -> alu_carry_out_s1_agent:rf_sink_endofpacket
wire alu_carry_out_s1_agent_rdata_fifo_src_valid; // alu_carry_out_s1_agent:rdata_fifo_src_valid -> alu_carry_out_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_carry_out_s1_agent_rdata_fifo_src_data; // alu_carry_out_s1_agent:rdata_fifo_src_data -> alu_carry_out_s1_agent:rdata_fifo_sink_data
wire alu_carry_out_s1_agent_rdata_fifo_src_ready; // alu_carry_out_s1_agent:rdata_fifo_sink_ready -> alu_carry_out_s1_agent:rdata_fifo_src_ready
wire cmd_mux_029_src_valid; // cmd_mux_029:src_valid -> alu_carry_out_s1_agent:cp_valid
wire [98:0] cmd_mux_029_src_data; // cmd_mux_029:src_data -> alu_carry_out_s1_agent:cp_data
wire cmd_mux_029_src_ready; // alu_carry_out_s1_agent:cp_ready -> cmd_mux_029:src_ready
wire [31:0] cmd_mux_029_src_channel; // cmd_mux_029:src_channel -> alu_carry_out_s1_agent:cp_channel
wire cmd_mux_029_src_startofpacket; // cmd_mux_029:src_startofpacket -> alu_carry_out_s1_agent:cp_startofpacket
wire cmd_mux_029_src_endofpacket; // cmd_mux_029:src_endofpacket -> alu_carry_out_s1_agent:cp_endofpacket
wire [31:0] alu_negative_s1_agent_m0_readdata; // alu_negative_s1_translator:uav_readdata -> alu_negative_s1_agent:m0_readdata
wire alu_negative_s1_agent_m0_waitrequest; // alu_negative_s1_translator:uav_waitrequest -> alu_negative_s1_agent:m0_waitrequest
wire alu_negative_s1_agent_m0_debugaccess; // alu_negative_s1_agent:m0_debugaccess -> alu_negative_s1_translator:uav_debugaccess
wire [18:0] alu_negative_s1_agent_m0_address; // alu_negative_s1_agent:m0_address -> alu_negative_s1_translator:uav_address
wire [3:0] alu_negative_s1_agent_m0_byteenable; // alu_negative_s1_agent:m0_byteenable -> alu_negative_s1_translator:uav_byteenable
wire alu_negative_s1_agent_m0_read; // alu_negative_s1_agent:m0_read -> alu_negative_s1_translator:uav_read
wire alu_negative_s1_agent_m0_readdatavalid; // alu_negative_s1_translator:uav_readdatavalid -> alu_negative_s1_agent:m0_readdatavalid
wire alu_negative_s1_agent_m0_lock; // alu_negative_s1_agent:m0_lock -> alu_negative_s1_translator:uav_lock
wire [31:0] alu_negative_s1_agent_m0_writedata; // alu_negative_s1_agent:m0_writedata -> alu_negative_s1_translator:uav_writedata
wire alu_negative_s1_agent_m0_write; // alu_negative_s1_agent:m0_write -> alu_negative_s1_translator:uav_write
wire [2:0] alu_negative_s1_agent_m0_burstcount; // alu_negative_s1_agent:m0_burstcount -> alu_negative_s1_translator:uav_burstcount
wire alu_negative_s1_agent_rf_source_valid; // alu_negative_s1_agent:rf_source_valid -> alu_negative_s1_agent_rsp_fifo:in_valid
wire [99:0] alu_negative_s1_agent_rf_source_data; // alu_negative_s1_agent:rf_source_data -> alu_negative_s1_agent_rsp_fifo:in_data
wire alu_negative_s1_agent_rf_source_ready; // alu_negative_s1_agent_rsp_fifo:in_ready -> alu_negative_s1_agent:rf_source_ready
wire alu_negative_s1_agent_rf_source_startofpacket; // alu_negative_s1_agent:rf_source_startofpacket -> alu_negative_s1_agent_rsp_fifo:in_startofpacket
wire alu_negative_s1_agent_rf_source_endofpacket; // alu_negative_s1_agent:rf_source_endofpacket -> alu_negative_s1_agent_rsp_fifo:in_endofpacket
wire alu_negative_s1_agent_rsp_fifo_out_valid; // alu_negative_s1_agent_rsp_fifo:out_valid -> alu_negative_s1_agent:rf_sink_valid
wire [99:0] alu_negative_s1_agent_rsp_fifo_out_data; // alu_negative_s1_agent_rsp_fifo:out_data -> alu_negative_s1_agent:rf_sink_data
wire alu_negative_s1_agent_rsp_fifo_out_ready; // alu_negative_s1_agent:rf_sink_ready -> alu_negative_s1_agent_rsp_fifo:out_ready
wire alu_negative_s1_agent_rsp_fifo_out_startofpacket; // alu_negative_s1_agent_rsp_fifo:out_startofpacket -> alu_negative_s1_agent:rf_sink_startofpacket
wire alu_negative_s1_agent_rsp_fifo_out_endofpacket; // alu_negative_s1_agent_rsp_fifo:out_endofpacket -> alu_negative_s1_agent:rf_sink_endofpacket
wire alu_negative_s1_agent_rdata_fifo_src_valid; // alu_negative_s1_agent:rdata_fifo_src_valid -> alu_negative_s1_agent:rdata_fifo_sink_valid
wire [33:0] alu_negative_s1_agent_rdata_fifo_src_data; // alu_negative_s1_agent:rdata_fifo_src_data -> alu_negative_s1_agent:rdata_fifo_sink_data
wire alu_negative_s1_agent_rdata_fifo_src_ready; // alu_negative_s1_agent:rdata_fifo_sink_ready -> alu_negative_s1_agent:rdata_fifo_src_ready
wire cmd_mux_030_src_valid; // cmd_mux_030:src_valid -> alu_negative_s1_agent:cp_valid
wire [98:0] cmd_mux_030_src_data; // cmd_mux_030:src_data -> alu_negative_s1_agent:cp_data
wire cmd_mux_030_src_ready; // alu_negative_s1_agent:cp_ready -> cmd_mux_030:src_ready
wire [31:0] cmd_mux_030_src_channel; // cmd_mux_030:src_channel -> alu_negative_s1_agent:cp_channel
wire cmd_mux_030_src_startofpacket; // cmd_mux_030:src_startofpacket -> alu_negative_s1_agent:cp_startofpacket
wire cmd_mux_030_src_endofpacket; // cmd_mux_030:src_endofpacket -> alu_negative_s1_agent:cp_endofpacket
wire [31:0] keys_s1_agent_m0_readdata; // keys_s1_translator:uav_readdata -> keys_s1_agent:m0_readdata
wire keys_s1_agent_m0_waitrequest; // keys_s1_translator:uav_waitrequest -> keys_s1_agent:m0_waitrequest
wire keys_s1_agent_m0_debugaccess; // keys_s1_agent:m0_debugaccess -> keys_s1_translator:uav_debugaccess
wire [18:0] keys_s1_agent_m0_address; // keys_s1_agent:m0_address -> keys_s1_translator:uav_address
wire [3:0] keys_s1_agent_m0_byteenable; // keys_s1_agent:m0_byteenable -> keys_s1_translator:uav_byteenable
wire keys_s1_agent_m0_read; // keys_s1_agent:m0_read -> keys_s1_translator:uav_read
wire keys_s1_agent_m0_readdatavalid; // keys_s1_translator:uav_readdatavalid -> keys_s1_agent:m0_readdatavalid
wire keys_s1_agent_m0_lock; // keys_s1_agent:m0_lock -> keys_s1_translator:uav_lock
wire [31:0] keys_s1_agent_m0_writedata; // keys_s1_agent:m0_writedata -> keys_s1_translator:uav_writedata
wire keys_s1_agent_m0_write; // keys_s1_agent:m0_write -> keys_s1_translator:uav_write
wire [2:0] keys_s1_agent_m0_burstcount; // keys_s1_agent:m0_burstcount -> keys_s1_translator:uav_burstcount
wire keys_s1_agent_rf_source_valid; // keys_s1_agent:rf_source_valid -> keys_s1_agent_rsp_fifo:in_valid
wire [99:0] keys_s1_agent_rf_source_data; // keys_s1_agent:rf_source_data -> keys_s1_agent_rsp_fifo:in_data
wire keys_s1_agent_rf_source_ready; // keys_s1_agent_rsp_fifo:in_ready -> keys_s1_agent:rf_source_ready
wire keys_s1_agent_rf_source_startofpacket; // keys_s1_agent:rf_source_startofpacket -> keys_s1_agent_rsp_fifo:in_startofpacket
wire keys_s1_agent_rf_source_endofpacket; // keys_s1_agent:rf_source_endofpacket -> keys_s1_agent_rsp_fifo:in_endofpacket
wire keys_s1_agent_rsp_fifo_out_valid; // keys_s1_agent_rsp_fifo:out_valid -> keys_s1_agent:rf_sink_valid
wire [99:0] keys_s1_agent_rsp_fifo_out_data; // keys_s1_agent_rsp_fifo:out_data -> keys_s1_agent:rf_sink_data
wire keys_s1_agent_rsp_fifo_out_ready; // keys_s1_agent:rf_sink_ready -> keys_s1_agent_rsp_fifo:out_ready
wire keys_s1_agent_rsp_fifo_out_startofpacket; // keys_s1_agent_rsp_fifo:out_startofpacket -> keys_s1_agent:rf_sink_startofpacket
wire keys_s1_agent_rsp_fifo_out_endofpacket; // keys_s1_agent_rsp_fifo:out_endofpacket -> keys_s1_agent:rf_sink_endofpacket
wire keys_s1_agent_rdata_fifo_src_valid; // keys_s1_agent:rdata_fifo_src_valid -> keys_s1_agent:rdata_fifo_sink_valid
wire [33:0] keys_s1_agent_rdata_fifo_src_data; // keys_s1_agent:rdata_fifo_src_data -> keys_s1_agent:rdata_fifo_sink_data
wire keys_s1_agent_rdata_fifo_src_ready; // keys_s1_agent:rdata_fifo_sink_ready -> keys_s1_agent:rdata_fifo_src_ready
wire cmd_mux_031_src_valid; // cmd_mux_031:src_valid -> keys_s1_agent:cp_valid
wire [98:0] cmd_mux_031_src_data; // cmd_mux_031:src_data -> keys_s1_agent:cp_data
wire cmd_mux_031_src_ready; // keys_s1_agent:cp_ready -> cmd_mux_031:src_ready
wire [31:0] cmd_mux_031_src_channel; // cmd_mux_031:src_channel -> keys_s1_agent:cp_channel
wire cmd_mux_031_src_startofpacket; // cmd_mux_031:src_startofpacket -> keys_s1_agent:cp_startofpacket
wire cmd_mux_031_src_endofpacket; // cmd_mux_031:src_endofpacket -> keys_s1_agent:cp_endofpacket
wire nios2_qsys_0_data_master_agent_cp_valid; // nios2_qsys_0_data_master_agent:cp_valid -> router:sink_valid
wire [98:0] nios2_qsys_0_data_master_agent_cp_data; // nios2_qsys_0_data_master_agent:cp_data -> router:sink_data
wire nios2_qsys_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_qsys_0_data_master_agent:cp_ready
wire nios2_qsys_0_data_master_agent_cp_startofpacket; // nios2_qsys_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_qsys_0_data_master_agent_cp_endofpacket; // nios2_qsys_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [98:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [31:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_qsys_0_instruction_master_agent_cp_valid; // nios2_qsys_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [98:0] nios2_qsys_0_instruction_master_agent_cp_data; // nios2_qsys_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_qsys_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_qsys_0_instruction_master_agent:cp_ready
wire nios2_qsys_0_instruction_master_agent_cp_startofpacket; // nios2_qsys_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_qsys_0_instruction_master_agent_cp_endofpacket; // nios2_qsys_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [98:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [31:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_agent:rp_valid -> router_002:sink_valid
wire [98:0] jtag_uart_0_avalon_jtag_slave_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_agent:rp_data -> router_002:sink_data
wire jtag_uart_0_avalon_jtag_slave_agent_rp_ready; // router_002:sink_ready -> jtag_uart_0_avalon_jtag_slave_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_startofpacket -> router_002:sink_startofpacket
wire jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [98:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [31:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rp_valid; // nios2_qsys_0_debug_mem_slave_agent:rp_valid -> router_003:sink_valid
wire [98:0] nios2_qsys_0_debug_mem_slave_agent_rp_data; // nios2_qsys_0_debug_mem_slave_agent:rp_data -> router_003:sink_data
wire nios2_qsys_0_debug_mem_slave_agent_rp_ready; // router_003:sink_ready -> nios2_qsys_0_debug_mem_slave_agent:rp_ready
wire nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket; // nios2_qsys_0_debug_mem_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket; // nios2_qsys_0_debug_mem_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [98:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [31:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_004:sink_valid
wire [98:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_004:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_004:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [98:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [31:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire leds_s1_agent_rp_valid; // LEDs_s1_agent:rp_valid -> router_005:sink_valid
wire [98:0] leds_s1_agent_rp_data; // LEDs_s1_agent:rp_data -> router_005:sink_data
wire leds_s1_agent_rp_ready; // router_005:sink_ready -> LEDs_s1_agent:rp_ready
wire leds_s1_agent_rp_startofpacket; // LEDs_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire leds_s1_agent_rp_endofpacket; // LEDs_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [98:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [31:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire switches_s1_agent_rp_valid; // switches_s1_agent:rp_valid -> router_006:sink_valid
wire [98:0] switches_s1_agent_rp_data; // switches_s1_agent:rp_data -> router_006:sink_data
wire switches_s1_agent_rp_ready; // router_006:sink_ready -> switches_s1_agent:rp_ready
wire switches_s1_agent_rp_startofpacket; // switches_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire switches_s1_agent_rp_endofpacket; // switches_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire [98:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire [31:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sram_data_s1_agent_rp_valid; // sram_data_s1_agent:rp_valid -> router_007:sink_valid
wire [98:0] sram_data_s1_agent_rp_data; // sram_data_s1_agent:rp_data -> router_007:sink_data
wire sram_data_s1_agent_rp_ready; // router_007:sink_ready -> sram_data_s1_agent:rp_ready
wire sram_data_s1_agent_rp_startofpacket; // sram_data_s1_agent:rp_startofpacket -> router_007:sink_startofpacket
wire sram_data_s1_agent_rp_endofpacket; // sram_data_s1_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [98:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [31:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire sram_addr_s1_agent_rp_valid; // sram_addr_s1_agent:rp_valid -> router_008:sink_valid
wire [98:0] sram_addr_s1_agent_rp_data; // sram_addr_s1_agent:rp_data -> router_008:sink_data
wire sram_addr_s1_agent_rp_ready; // router_008:sink_ready -> sram_addr_s1_agent:rp_ready
wire sram_addr_s1_agent_rp_startofpacket; // sram_addr_s1_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sram_addr_s1_agent_rp_endofpacket; // sram_addr_s1_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [98:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [31:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire sram_read_write_s1_agent_rp_valid; // sram_read_write_s1_agent:rp_valid -> router_009:sink_valid
wire [98:0] sram_read_write_s1_agent_rp_data; // sram_read_write_s1_agent:rp_data -> router_009:sink_data
wire sram_read_write_s1_agent_rp_ready; // router_009:sink_ready -> sram_read_write_s1_agent:rp_ready
wire sram_read_write_s1_agent_rp_startofpacket; // sram_read_write_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire sram_read_write_s1_agent_rp_endofpacket; // sram_read_write_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_007:sink_valid
wire [98:0] router_009_src_data; // router_009:src_data -> rsp_demux_007:sink_data
wire router_009_src_ready; // rsp_demux_007:sink_ready -> router_009:src_ready
wire [31:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_007:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire sram_cs_s1_agent_rp_valid; // sram_cs_s1_agent:rp_valid -> router_010:sink_valid
wire [98:0] sram_cs_s1_agent_rp_data; // sram_cs_s1_agent:rp_data -> router_010:sink_data
wire sram_cs_s1_agent_rp_ready; // router_010:sink_ready -> sram_cs_s1_agent:rp_ready
wire sram_cs_s1_agent_rp_startofpacket; // sram_cs_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire sram_cs_s1_agent_rp_endofpacket; // sram_cs_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_008:sink_valid
wire [98:0] router_010_src_data; // router_010:src_data -> rsp_demux_008:sink_data
wire router_010_src_ready; // rsp_demux_008:sink_ready -> router_010:src_ready
wire [31:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_008:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire sram_oe_s1_agent_rp_valid; // sram_oe_s1_agent:rp_valid -> router_011:sink_valid
wire [98:0] sram_oe_s1_agent_rp_data; // sram_oe_s1_agent:rp_data -> router_011:sink_data
wire sram_oe_s1_agent_rp_ready; // router_011:sink_ready -> sram_oe_s1_agent:rp_ready
wire sram_oe_s1_agent_rp_startofpacket; // sram_oe_s1_agent:rp_startofpacket -> router_011:sink_startofpacket
wire sram_oe_s1_agent_rp_endofpacket; // sram_oe_s1_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_009:sink_valid
wire [98:0] router_011_src_data; // router_011:src_data -> rsp_demux_009:sink_data
wire router_011_src_ready; // rsp_demux_009:sink_ready -> router_011:src_ready
wire [31:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_009:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire regfile_data_s1_agent_rp_valid; // regfile_data_s1_agent:rp_valid -> router_012:sink_valid
wire [98:0] regfile_data_s1_agent_rp_data; // regfile_data_s1_agent:rp_data -> router_012:sink_data
wire regfile_data_s1_agent_rp_ready; // router_012:sink_ready -> regfile_data_s1_agent:rp_ready
wire regfile_data_s1_agent_rp_startofpacket; // regfile_data_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
wire regfile_data_s1_agent_rp_endofpacket; // regfile_data_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
wire router_012_src_valid; // router_012:src_valid -> rsp_demux_010:sink_valid
wire [98:0] router_012_src_data; // router_012:src_data -> rsp_demux_010:sink_data
wire router_012_src_ready; // rsp_demux_010:sink_ready -> router_012:src_ready
wire [31:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_010:sink_channel
wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_010:sink_startofpacket
wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_010:sink_endofpacket
wire regfile_reg1_s1_agent_rp_valid; // regfile_reg1_s1_agent:rp_valid -> router_013:sink_valid
wire [98:0] regfile_reg1_s1_agent_rp_data; // regfile_reg1_s1_agent:rp_data -> router_013:sink_data
wire regfile_reg1_s1_agent_rp_ready; // router_013:sink_ready -> regfile_reg1_s1_agent:rp_ready
wire regfile_reg1_s1_agent_rp_startofpacket; // regfile_reg1_s1_agent:rp_startofpacket -> router_013:sink_startofpacket
wire regfile_reg1_s1_agent_rp_endofpacket; // regfile_reg1_s1_agent:rp_endofpacket -> router_013:sink_endofpacket
wire router_013_src_valid; // router_013:src_valid -> rsp_demux_011:sink_valid
wire [98:0] router_013_src_data; // router_013:src_data -> rsp_demux_011:sink_data
wire router_013_src_ready; // rsp_demux_011:sink_ready -> router_013:src_ready
wire [31:0] router_013_src_channel; // router_013:src_channel -> rsp_demux_011:sink_channel
wire router_013_src_startofpacket; // router_013:src_startofpacket -> rsp_demux_011:sink_startofpacket
wire router_013_src_endofpacket; // router_013:src_endofpacket -> rsp_demux_011:sink_endofpacket
wire regfile_reg2_s1_agent_rp_valid; // regfile_reg2_s1_agent:rp_valid -> router_014:sink_valid
wire [98:0] regfile_reg2_s1_agent_rp_data; // regfile_reg2_s1_agent:rp_data -> router_014:sink_data
wire regfile_reg2_s1_agent_rp_ready; // router_014:sink_ready -> regfile_reg2_s1_agent:rp_ready
wire regfile_reg2_s1_agent_rp_startofpacket; // regfile_reg2_s1_agent:rp_startofpacket -> router_014:sink_startofpacket
wire regfile_reg2_s1_agent_rp_endofpacket; // regfile_reg2_s1_agent:rp_endofpacket -> router_014:sink_endofpacket
wire router_014_src_valid; // router_014:src_valid -> rsp_demux_012:sink_valid
wire [98:0] router_014_src_data; // router_014:src_data -> rsp_demux_012:sink_data
wire router_014_src_ready; // rsp_demux_012:sink_ready -> router_014:src_ready
wire [31:0] router_014_src_channel; // router_014:src_channel -> rsp_demux_012:sink_channel
wire router_014_src_startofpacket; // router_014:src_startofpacket -> rsp_demux_012:sink_startofpacket
wire router_014_src_endofpacket; // router_014:src_endofpacket -> rsp_demux_012:sink_endofpacket
wire regfile_r1sel_s1_agent_rp_valid; // regfile_r1sel_s1_agent:rp_valid -> router_015:sink_valid
wire [98:0] regfile_r1sel_s1_agent_rp_data; // regfile_r1sel_s1_agent:rp_data -> router_015:sink_data
wire regfile_r1sel_s1_agent_rp_ready; // router_015:sink_ready -> regfile_r1sel_s1_agent:rp_ready
wire regfile_r1sel_s1_agent_rp_startofpacket; // regfile_r1sel_s1_agent:rp_startofpacket -> router_015:sink_startofpacket
wire regfile_r1sel_s1_agent_rp_endofpacket; // regfile_r1sel_s1_agent:rp_endofpacket -> router_015:sink_endofpacket
wire router_015_src_valid; // router_015:src_valid -> rsp_demux_013:sink_valid
wire [98:0] router_015_src_data; // router_015:src_data -> rsp_demux_013:sink_data
wire router_015_src_ready; // rsp_demux_013:sink_ready -> router_015:src_ready
wire [31:0] router_015_src_channel; // router_015:src_channel -> rsp_demux_013:sink_channel
wire router_015_src_startofpacket; // router_015:src_startofpacket -> rsp_demux_013:sink_startofpacket
wire router_015_src_endofpacket; // router_015:src_endofpacket -> rsp_demux_013:sink_endofpacket
wire regfile_r2sel_s1_agent_rp_valid; // regfile_r2sel_s1_agent:rp_valid -> router_016:sink_valid
wire [98:0] regfile_r2sel_s1_agent_rp_data; // regfile_r2sel_s1_agent:rp_data -> router_016:sink_data
wire regfile_r2sel_s1_agent_rp_ready; // router_016:sink_ready -> regfile_r2sel_s1_agent:rp_ready
wire regfile_r2sel_s1_agent_rp_startofpacket; // regfile_r2sel_s1_agent:rp_startofpacket -> router_016:sink_startofpacket
wire regfile_r2sel_s1_agent_rp_endofpacket; // regfile_r2sel_s1_agent:rp_endofpacket -> router_016:sink_endofpacket
wire router_016_src_valid; // router_016:src_valid -> rsp_demux_014:sink_valid
wire [98:0] router_016_src_data; // router_016:src_data -> rsp_demux_014:sink_data
wire router_016_src_ready; // rsp_demux_014:sink_ready -> router_016:src_ready
wire [31:0] router_016_src_channel; // router_016:src_channel -> rsp_demux_014:sink_channel
wire router_016_src_startofpacket; // router_016:src_startofpacket -> rsp_demux_014:sink_startofpacket
wire router_016_src_endofpacket; // router_016:src_endofpacket -> rsp_demux_014:sink_endofpacket
wire regfile_wsel_s1_agent_rp_valid; // regfile_wsel_s1_agent:rp_valid -> router_017:sink_valid
wire [98:0] regfile_wsel_s1_agent_rp_data; // regfile_wsel_s1_agent:rp_data -> router_017:sink_data
wire regfile_wsel_s1_agent_rp_ready; // router_017:sink_ready -> regfile_wsel_s1_agent:rp_ready
wire regfile_wsel_s1_agent_rp_startofpacket; // regfile_wsel_s1_agent:rp_startofpacket -> router_017:sink_startofpacket
wire regfile_wsel_s1_agent_rp_endofpacket; // regfile_wsel_s1_agent:rp_endofpacket -> router_017:sink_endofpacket
wire router_017_src_valid; // router_017:src_valid -> rsp_demux_015:sink_valid
wire [98:0] router_017_src_data; // router_017:src_data -> rsp_demux_015:sink_data
wire router_017_src_ready; // rsp_demux_015:sink_ready -> router_017:src_ready
wire [31:0] router_017_src_channel; // router_017:src_channel -> rsp_demux_015:sink_channel
wire router_017_src_startofpacket; // router_017:src_startofpacket -> rsp_demux_015:sink_startofpacket
wire router_017_src_endofpacket; // router_017:src_endofpacket -> rsp_demux_015:sink_endofpacket
wire regfile_we_s1_agent_rp_valid; // regfile_we_s1_agent:rp_valid -> router_018:sink_valid
wire [98:0] regfile_we_s1_agent_rp_data; // regfile_we_s1_agent:rp_data -> router_018:sink_data
wire regfile_we_s1_agent_rp_ready; // router_018:sink_ready -> regfile_we_s1_agent:rp_ready
wire regfile_we_s1_agent_rp_startofpacket; // regfile_we_s1_agent:rp_startofpacket -> router_018:sink_startofpacket
wire regfile_we_s1_agent_rp_endofpacket; // regfile_we_s1_agent:rp_endofpacket -> router_018:sink_endofpacket
wire router_018_src_valid; // router_018:src_valid -> rsp_demux_016:sink_valid
wire [98:0] router_018_src_data; // router_018:src_data -> rsp_demux_016:sink_data
wire router_018_src_ready; // rsp_demux_016:sink_ready -> router_018:src_ready
wire [31:0] router_018_src_channel; // router_018:src_channel -> rsp_demux_016:sink_channel
wire router_018_src_startofpacket; // router_018:src_startofpacket -> rsp_demux_016:sink_startofpacket
wire router_018_src_endofpacket; // router_018:src_endofpacket -> rsp_demux_016:sink_endofpacket
wire hex_0_s1_agent_rp_valid; // hex_0_s1_agent:rp_valid -> router_019:sink_valid
wire [98:0] hex_0_s1_agent_rp_data; // hex_0_s1_agent:rp_data -> router_019:sink_data
wire hex_0_s1_agent_rp_ready; // router_019:sink_ready -> hex_0_s1_agent:rp_ready
wire hex_0_s1_agent_rp_startofpacket; // hex_0_s1_agent:rp_startofpacket -> router_019:sink_startofpacket
wire hex_0_s1_agent_rp_endofpacket; // hex_0_s1_agent:rp_endofpacket -> router_019:sink_endofpacket
wire router_019_src_valid; // router_019:src_valid -> rsp_demux_017:sink_valid
wire [98:0] router_019_src_data; // router_019:src_data -> rsp_demux_017:sink_data
wire router_019_src_ready; // rsp_demux_017:sink_ready -> router_019:src_ready
wire [31:0] router_019_src_channel; // router_019:src_channel -> rsp_demux_017:sink_channel
wire router_019_src_startofpacket; // router_019:src_startofpacket -> rsp_demux_017:sink_startofpacket
wire router_019_src_endofpacket; // router_019:src_endofpacket -> rsp_demux_017:sink_endofpacket
wire hex_1_s1_agent_rp_valid; // hex_1_s1_agent:rp_valid -> router_020:sink_valid
wire [98:0] hex_1_s1_agent_rp_data; // hex_1_s1_agent:rp_data -> router_020:sink_data
wire hex_1_s1_agent_rp_ready; // router_020:sink_ready -> hex_1_s1_agent:rp_ready
wire hex_1_s1_agent_rp_startofpacket; // hex_1_s1_agent:rp_startofpacket -> router_020:sink_startofpacket
wire hex_1_s1_agent_rp_endofpacket; // hex_1_s1_agent:rp_endofpacket -> router_020:sink_endofpacket
wire router_020_src_valid; // router_020:src_valid -> rsp_demux_018:sink_valid
wire [98:0] router_020_src_data; // router_020:src_data -> rsp_demux_018:sink_data
wire router_020_src_ready; // rsp_demux_018:sink_ready -> router_020:src_ready
wire [31:0] router_020_src_channel; // router_020:src_channel -> rsp_demux_018:sink_channel
wire router_020_src_startofpacket; // router_020:src_startofpacket -> rsp_demux_018:sink_startofpacket
wire router_020_src_endofpacket; // router_020:src_endofpacket -> rsp_demux_018:sink_endofpacket
wire hex_2_s1_agent_rp_valid; // hex_2_s1_agent:rp_valid -> router_021:sink_valid
wire [98:0] hex_2_s1_agent_rp_data; // hex_2_s1_agent:rp_data -> router_021:sink_data
wire hex_2_s1_agent_rp_ready; // router_021:sink_ready -> hex_2_s1_agent:rp_ready
wire hex_2_s1_agent_rp_startofpacket; // hex_2_s1_agent:rp_startofpacket -> router_021:sink_startofpacket
wire hex_2_s1_agent_rp_endofpacket; // hex_2_s1_agent:rp_endofpacket -> router_021:sink_endofpacket
wire router_021_src_valid; // router_021:src_valid -> rsp_demux_019:sink_valid
wire [98:0] router_021_src_data; // router_021:src_data -> rsp_demux_019:sink_data
wire router_021_src_ready; // rsp_demux_019:sink_ready -> router_021:src_ready
wire [31:0] router_021_src_channel; // router_021:src_channel -> rsp_demux_019:sink_channel
wire router_021_src_startofpacket; // router_021:src_startofpacket -> rsp_demux_019:sink_startofpacket
wire router_021_src_endofpacket; // router_021:src_endofpacket -> rsp_demux_019:sink_endofpacket
wire hex_3_s1_agent_rp_valid; // hex_3_s1_agent:rp_valid -> router_022:sink_valid
wire [98:0] hex_3_s1_agent_rp_data; // hex_3_s1_agent:rp_data -> router_022:sink_data
wire hex_3_s1_agent_rp_ready; // router_022:sink_ready -> hex_3_s1_agent:rp_ready
wire hex_3_s1_agent_rp_startofpacket; // hex_3_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
wire hex_3_s1_agent_rp_endofpacket; // hex_3_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
wire router_022_src_valid; // router_022:src_valid -> rsp_demux_020:sink_valid
wire [98:0] router_022_src_data; // router_022:src_data -> rsp_demux_020:sink_data
wire router_022_src_ready; // rsp_demux_020:sink_ready -> router_022:src_ready
wire [31:0] router_022_src_channel; // router_022:src_channel -> rsp_demux_020:sink_channel
wire router_022_src_startofpacket; // router_022:src_startofpacket -> rsp_demux_020:sink_startofpacket
wire router_022_src_endofpacket; // router_022:src_endofpacket -> rsp_demux_020:sink_endofpacket
wire hex_4_s1_agent_rp_valid; // hex_4_s1_agent:rp_valid -> router_023:sink_valid
wire [98:0] hex_4_s1_agent_rp_data; // hex_4_s1_agent:rp_data -> router_023:sink_data
wire hex_4_s1_agent_rp_ready; // router_023:sink_ready -> hex_4_s1_agent:rp_ready
wire hex_4_s1_agent_rp_startofpacket; // hex_4_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
wire hex_4_s1_agent_rp_endofpacket; // hex_4_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
wire router_023_src_valid; // router_023:src_valid -> rsp_demux_021:sink_valid
wire [98:0] router_023_src_data; // router_023:src_data -> rsp_demux_021:sink_data
wire router_023_src_ready; // rsp_demux_021:sink_ready -> router_023:src_ready
wire [31:0] router_023_src_channel; // router_023:src_channel -> rsp_demux_021:sink_channel
wire router_023_src_startofpacket; // router_023:src_startofpacket -> rsp_demux_021:sink_startofpacket
wire router_023_src_endofpacket; // router_023:src_endofpacket -> rsp_demux_021:sink_endofpacket
wire hex_5_s1_agent_rp_valid; // hex_5_s1_agent:rp_valid -> router_024:sink_valid
wire [98:0] hex_5_s1_agent_rp_data; // hex_5_s1_agent:rp_data -> router_024:sink_data
wire hex_5_s1_agent_rp_ready; // router_024:sink_ready -> hex_5_s1_agent:rp_ready
wire hex_5_s1_agent_rp_startofpacket; // hex_5_s1_agent:rp_startofpacket -> router_024:sink_startofpacket
wire hex_5_s1_agent_rp_endofpacket; // hex_5_s1_agent:rp_endofpacket -> router_024:sink_endofpacket
wire router_024_src_valid; // router_024:src_valid -> rsp_demux_022:sink_valid
wire [98:0] router_024_src_data; // router_024:src_data -> rsp_demux_022:sink_data
wire router_024_src_ready; // rsp_demux_022:sink_ready -> router_024:src_ready
wire [31:0] router_024_src_channel; // router_024:src_channel -> rsp_demux_022:sink_channel
wire router_024_src_startofpacket; // router_024:src_startofpacket -> rsp_demux_022:sink_startofpacket
wire router_024_src_endofpacket; // router_024:src_endofpacket -> rsp_demux_022:sink_endofpacket
wire alu_a_s1_agent_rp_valid; // alu_a_s1_agent:rp_valid -> router_025:sink_valid
wire [98:0] alu_a_s1_agent_rp_data; // alu_a_s1_agent:rp_data -> router_025:sink_data
wire alu_a_s1_agent_rp_ready; // router_025:sink_ready -> alu_a_s1_agent:rp_ready
wire alu_a_s1_agent_rp_startofpacket; // alu_a_s1_agent:rp_startofpacket -> router_025:sink_startofpacket
wire alu_a_s1_agent_rp_endofpacket; // alu_a_s1_agent:rp_endofpacket -> router_025:sink_endofpacket
wire router_025_src_valid; // router_025:src_valid -> rsp_demux_023:sink_valid
wire [98:0] router_025_src_data; // router_025:src_data -> rsp_demux_023:sink_data
wire router_025_src_ready; // rsp_demux_023:sink_ready -> router_025:src_ready
wire [31:0] router_025_src_channel; // router_025:src_channel -> rsp_demux_023:sink_channel
wire router_025_src_startofpacket; // router_025:src_startofpacket -> rsp_demux_023:sink_startofpacket
wire router_025_src_endofpacket; // router_025:src_endofpacket -> rsp_demux_023:sink_endofpacket
wire alu_b_s1_agent_rp_valid; // alu_b_s1_agent:rp_valid -> router_026:sink_valid
wire [98:0] alu_b_s1_agent_rp_data; // alu_b_s1_agent:rp_data -> router_026:sink_data
wire alu_b_s1_agent_rp_ready; // router_026:sink_ready -> alu_b_s1_agent:rp_ready
wire alu_b_s1_agent_rp_startofpacket; // alu_b_s1_agent:rp_startofpacket -> router_026:sink_startofpacket
wire alu_b_s1_agent_rp_endofpacket; // alu_b_s1_agent:rp_endofpacket -> router_026:sink_endofpacket
wire router_026_src_valid; // router_026:src_valid -> rsp_demux_024:sink_valid
wire [98:0] router_026_src_data; // router_026:src_data -> rsp_demux_024:sink_data
wire router_026_src_ready; // rsp_demux_024:sink_ready -> router_026:src_ready
wire [31:0] router_026_src_channel; // router_026:src_channel -> rsp_demux_024:sink_channel
wire router_026_src_startofpacket; // router_026:src_startofpacket -> rsp_demux_024:sink_startofpacket
wire router_026_src_endofpacket; // router_026:src_endofpacket -> rsp_demux_024:sink_endofpacket
wire alu_control_s1_agent_rp_valid; // alu_control_s1_agent:rp_valid -> router_027:sink_valid
wire [98:0] alu_control_s1_agent_rp_data; // alu_control_s1_agent:rp_data -> router_027:sink_data
wire alu_control_s1_agent_rp_ready; // router_027:sink_ready -> alu_control_s1_agent:rp_ready
wire alu_control_s1_agent_rp_startofpacket; // alu_control_s1_agent:rp_startofpacket -> router_027:sink_startofpacket
wire alu_control_s1_agent_rp_endofpacket; // alu_control_s1_agent:rp_endofpacket -> router_027:sink_endofpacket
wire router_027_src_valid; // router_027:src_valid -> rsp_demux_025:sink_valid
wire [98:0] router_027_src_data; // router_027:src_data -> rsp_demux_025:sink_data
wire router_027_src_ready; // rsp_demux_025:sink_ready -> router_027:src_ready
wire [31:0] router_027_src_channel; // router_027:src_channel -> rsp_demux_025:sink_channel
wire router_027_src_startofpacket; // router_027:src_startofpacket -> rsp_demux_025:sink_startofpacket
wire router_027_src_endofpacket; // router_027:src_endofpacket -> rsp_demux_025:sink_endofpacket
wire alu_out_s1_agent_rp_valid; // alu_out_s1_agent:rp_valid -> router_028:sink_valid
wire [98:0] alu_out_s1_agent_rp_data; // alu_out_s1_agent:rp_data -> router_028:sink_data
wire alu_out_s1_agent_rp_ready; // router_028:sink_ready -> alu_out_s1_agent:rp_ready
wire alu_out_s1_agent_rp_startofpacket; // alu_out_s1_agent:rp_startofpacket -> router_028:sink_startofpacket
wire alu_out_s1_agent_rp_endofpacket; // alu_out_s1_agent:rp_endofpacket -> router_028:sink_endofpacket
wire router_028_src_valid; // router_028:src_valid -> rsp_demux_026:sink_valid
wire [98:0] router_028_src_data; // router_028:src_data -> rsp_demux_026:sink_data
wire router_028_src_ready; // rsp_demux_026:sink_ready -> router_028:src_ready
wire [31:0] router_028_src_channel; // router_028:src_channel -> rsp_demux_026:sink_channel
wire router_028_src_startofpacket; // router_028:src_startofpacket -> rsp_demux_026:sink_startofpacket
wire router_028_src_endofpacket; // router_028:src_endofpacket -> rsp_demux_026:sink_endofpacket
wire alu_zero_s1_agent_rp_valid; // alu_zero_s1_agent:rp_valid -> router_029:sink_valid
wire [98:0] alu_zero_s1_agent_rp_data; // alu_zero_s1_agent:rp_data -> router_029:sink_data
wire alu_zero_s1_agent_rp_ready; // router_029:sink_ready -> alu_zero_s1_agent:rp_ready
wire alu_zero_s1_agent_rp_startofpacket; // alu_zero_s1_agent:rp_startofpacket -> router_029:sink_startofpacket
wire alu_zero_s1_agent_rp_endofpacket; // alu_zero_s1_agent:rp_endofpacket -> router_029:sink_endofpacket
wire router_029_src_valid; // router_029:src_valid -> rsp_demux_027:sink_valid
wire [98:0] router_029_src_data; // router_029:src_data -> rsp_demux_027:sink_data
wire router_029_src_ready; // rsp_demux_027:sink_ready -> router_029:src_ready
wire [31:0] router_029_src_channel; // router_029:src_channel -> rsp_demux_027:sink_channel
wire router_029_src_startofpacket; // router_029:src_startofpacket -> rsp_demux_027:sink_startofpacket
wire router_029_src_endofpacket; // router_029:src_endofpacket -> rsp_demux_027:sink_endofpacket
wire alu_overflow_s1_agent_rp_valid; // alu_overflow_s1_agent:rp_valid -> router_030:sink_valid
wire [98:0] alu_overflow_s1_agent_rp_data; // alu_overflow_s1_agent:rp_data -> router_030:sink_data
wire alu_overflow_s1_agent_rp_ready; // router_030:sink_ready -> alu_overflow_s1_agent:rp_ready
wire alu_overflow_s1_agent_rp_startofpacket; // alu_overflow_s1_agent:rp_startofpacket -> router_030:sink_startofpacket
wire alu_overflow_s1_agent_rp_endofpacket; // alu_overflow_s1_agent:rp_endofpacket -> router_030:sink_endofpacket
wire router_030_src_valid; // router_030:src_valid -> rsp_demux_028:sink_valid
wire [98:0] router_030_src_data; // router_030:src_data -> rsp_demux_028:sink_data
wire router_030_src_ready; // rsp_demux_028:sink_ready -> router_030:src_ready
wire [31:0] router_030_src_channel; // router_030:src_channel -> rsp_demux_028:sink_channel
wire router_030_src_startofpacket; // router_030:src_startofpacket -> rsp_demux_028:sink_startofpacket
wire router_030_src_endofpacket; // router_030:src_endofpacket -> rsp_demux_028:sink_endofpacket
wire alu_carry_out_s1_agent_rp_valid; // alu_carry_out_s1_agent:rp_valid -> router_031:sink_valid
wire [98:0] alu_carry_out_s1_agent_rp_data; // alu_carry_out_s1_agent:rp_data -> router_031:sink_data
wire alu_carry_out_s1_agent_rp_ready; // router_031:sink_ready -> alu_carry_out_s1_agent:rp_ready
wire alu_carry_out_s1_agent_rp_startofpacket; // alu_carry_out_s1_agent:rp_startofpacket -> router_031:sink_startofpacket
wire alu_carry_out_s1_agent_rp_endofpacket; // alu_carry_out_s1_agent:rp_endofpacket -> router_031:sink_endofpacket
wire router_031_src_valid; // router_031:src_valid -> rsp_demux_029:sink_valid
wire [98:0] router_031_src_data; // router_031:src_data -> rsp_demux_029:sink_data
wire router_031_src_ready; // rsp_demux_029:sink_ready -> router_031:src_ready
wire [31:0] router_031_src_channel; // router_031:src_channel -> rsp_demux_029:sink_channel
wire router_031_src_startofpacket; // router_031:src_startofpacket -> rsp_demux_029:sink_startofpacket
wire router_031_src_endofpacket; // router_031:src_endofpacket -> rsp_demux_029:sink_endofpacket
wire alu_negative_s1_agent_rp_valid; // alu_negative_s1_agent:rp_valid -> router_032:sink_valid
wire [98:0] alu_negative_s1_agent_rp_data; // alu_negative_s1_agent:rp_data -> router_032:sink_data
wire alu_negative_s1_agent_rp_ready; // router_032:sink_ready -> alu_negative_s1_agent:rp_ready
wire alu_negative_s1_agent_rp_startofpacket; // alu_negative_s1_agent:rp_startofpacket -> router_032:sink_startofpacket
wire alu_negative_s1_agent_rp_endofpacket; // alu_negative_s1_agent:rp_endofpacket -> router_032:sink_endofpacket
wire router_032_src_valid; // router_032:src_valid -> rsp_demux_030:sink_valid
wire [98:0] router_032_src_data; // router_032:src_data -> rsp_demux_030:sink_data
wire router_032_src_ready; // rsp_demux_030:sink_ready -> router_032:src_ready
wire [31:0] router_032_src_channel; // router_032:src_channel -> rsp_demux_030:sink_channel
wire router_032_src_startofpacket; // router_032:src_startofpacket -> rsp_demux_030:sink_startofpacket
wire router_032_src_endofpacket; // router_032:src_endofpacket -> rsp_demux_030:sink_endofpacket
wire keys_s1_agent_rp_valid; // keys_s1_agent:rp_valid -> router_033:sink_valid
wire [98:0] keys_s1_agent_rp_data; // keys_s1_agent:rp_data -> router_033:sink_data
wire keys_s1_agent_rp_ready; // router_033:sink_ready -> keys_s1_agent:rp_ready
wire keys_s1_agent_rp_startofpacket; // keys_s1_agent:rp_startofpacket -> router_033:sink_startofpacket
wire keys_s1_agent_rp_endofpacket; // keys_s1_agent:rp_endofpacket -> router_033:sink_endofpacket
wire router_033_src_valid; // router_033:src_valid -> rsp_demux_031:sink_valid
wire [98:0] router_033_src_data; // router_033:src_data -> rsp_demux_031:sink_data
wire router_033_src_ready; // rsp_demux_031:sink_ready -> router_033:src_ready
wire [31:0] router_033_src_channel; // router_033:src_channel -> rsp_demux_031:sink_channel
wire router_033_src_startofpacket; // router_033:src_startofpacket -> rsp_demux_031:sink_startofpacket
wire router_033_src_endofpacket; // router_033:src_endofpacket -> rsp_demux_031:sink_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [98:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [31:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [98:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [31:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [98:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [31:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [98:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [31:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [98:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [31:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [98:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [31:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire [98:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire [31:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [98:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [31:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
wire [98:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
wire [31:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_src9_valid; // cmd_demux:src9_valid -> cmd_mux_009:sink0_valid
wire [98:0] cmd_demux_src9_data; // cmd_demux:src9_data -> cmd_mux_009:sink0_data
wire cmd_demux_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux:src9_ready
wire [31:0] cmd_demux_src9_channel; // cmd_demux:src9_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_src9_startofpacket; // cmd_demux:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_src9_endofpacket; // cmd_demux:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
wire cmd_demux_src10_valid; // cmd_demux:src10_valid -> cmd_mux_010:sink0_valid
wire [98:0] cmd_demux_src10_data; // cmd_demux:src10_data -> cmd_mux_010:sink0_data
wire cmd_demux_src10_ready; // cmd_mux_010:sink0_ready -> cmd_demux:src10_ready
wire [31:0] cmd_demux_src10_channel; // cmd_demux:src10_channel -> cmd_mux_010:sink0_channel
wire cmd_demux_src10_startofpacket; // cmd_demux:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
wire cmd_demux_src10_endofpacket; // cmd_demux:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
wire cmd_demux_src11_valid; // cmd_demux:src11_valid -> cmd_mux_011:sink0_valid
wire [98:0] cmd_demux_src11_data; // cmd_demux:src11_data -> cmd_mux_011:sink0_data
wire cmd_demux_src11_ready; // cmd_mux_011:sink0_ready -> cmd_demux:src11_ready
wire [31:0] cmd_demux_src11_channel; // cmd_demux:src11_channel -> cmd_mux_011:sink0_channel
wire cmd_demux_src11_startofpacket; // cmd_demux:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
wire cmd_demux_src11_endofpacket; // cmd_demux:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
wire cmd_demux_src12_valid; // cmd_demux:src12_valid -> cmd_mux_012:sink0_valid
wire [98:0] cmd_demux_src12_data; // cmd_demux:src12_data -> cmd_mux_012:sink0_data
wire cmd_demux_src12_ready; // cmd_mux_012:sink0_ready -> cmd_demux:src12_ready
wire [31:0] cmd_demux_src12_channel; // cmd_demux:src12_channel -> cmd_mux_012:sink0_channel
wire cmd_demux_src12_startofpacket; // cmd_demux:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
wire cmd_demux_src12_endofpacket; // cmd_demux:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
wire cmd_demux_src13_valid; // cmd_demux:src13_valid -> cmd_mux_013:sink0_valid
wire [98:0] cmd_demux_src13_data; // cmd_demux:src13_data -> cmd_mux_013:sink0_data
wire cmd_demux_src13_ready; // cmd_mux_013:sink0_ready -> cmd_demux:src13_ready
wire [31:0] cmd_demux_src13_channel; // cmd_demux:src13_channel -> cmd_mux_013:sink0_channel
wire cmd_demux_src13_startofpacket; // cmd_demux:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
wire cmd_demux_src13_endofpacket; // cmd_demux:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
wire cmd_demux_src14_valid; // cmd_demux:src14_valid -> cmd_mux_014:sink0_valid
wire [98:0] cmd_demux_src14_data; // cmd_demux:src14_data -> cmd_mux_014:sink0_data
wire cmd_demux_src14_ready; // cmd_mux_014:sink0_ready -> cmd_demux:src14_ready
wire [31:0] cmd_demux_src14_channel; // cmd_demux:src14_channel -> cmd_mux_014:sink0_channel
wire cmd_demux_src14_startofpacket; // cmd_demux:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
wire cmd_demux_src14_endofpacket; // cmd_demux:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
wire cmd_demux_src15_valid; // cmd_demux:src15_valid -> cmd_mux_015:sink0_valid
wire [98:0] cmd_demux_src15_data; // cmd_demux:src15_data -> cmd_mux_015:sink0_data
wire cmd_demux_src15_ready; // cmd_mux_015:sink0_ready -> cmd_demux:src15_ready
wire [31:0] cmd_demux_src15_channel; // cmd_demux:src15_channel -> cmd_mux_015:sink0_channel
wire cmd_demux_src15_startofpacket; // cmd_demux:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
wire cmd_demux_src15_endofpacket; // cmd_demux:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
wire cmd_demux_src16_valid; // cmd_demux:src16_valid -> cmd_mux_016:sink0_valid
wire [98:0] cmd_demux_src16_data; // cmd_demux:src16_data -> cmd_mux_016:sink0_data
wire cmd_demux_src16_ready; // cmd_mux_016:sink0_ready -> cmd_demux:src16_ready
wire [31:0] cmd_demux_src16_channel; // cmd_demux:src16_channel -> cmd_mux_016:sink0_channel
wire cmd_demux_src16_startofpacket; // cmd_demux:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
wire cmd_demux_src16_endofpacket; // cmd_demux:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
wire cmd_demux_src17_valid; // cmd_demux:src17_valid -> cmd_mux_017:sink0_valid
wire [98:0] cmd_demux_src17_data; // cmd_demux:src17_data -> cmd_mux_017:sink0_data
wire cmd_demux_src17_ready; // cmd_mux_017:sink0_ready -> cmd_demux:src17_ready
wire [31:0] cmd_demux_src17_channel; // cmd_demux:src17_channel -> cmd_mux_017:sink0_channel
wire cmd_demux_src17_startofpacket; // cmd_demux:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
wire cmd_demux_src17_endofpacket; // cmd_demux:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
wire cmd_demux_src18_valid; // cmd_demux:src18_valid -> cmd_mux_018:sink0_valid
wire [98:0] cmd_demux_src18_data; // cmd_demux:src18_data -> cmd_mux_018:sink0_data
wire cmd_demux_src18_ready; // cmd_mux_018:sink0_ready -> cmd_demux:src18_ready
wire [31:0] cmd_demux_src18_channel; // cmd_demux:src18_channel -> cmd_mux_018:sink0_channel
wire cmd_demux_src18_startofpacket; // cmd_demux:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
wire cmd_demux_src18_endofpacket; // cmd_demux:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
wire cmd_demux_src19_valid; // cmd_demux:src19_valid -> cmd_mux_019:sink0_valid
wire [98:0] cmd_demux_src19_data; // cmd_demux:src19_data -> cmd_mux_019:sink0_data
wire cmd_demux_src19_ready; // cmd_mux_019:sink0_ready -> cmd_demux:src19_ready
wire [31:0] cmd_demux_src19_channel; // cmd_demux:src19_channel -> cmd_mux_019:sink0_channel
wire cmd_demux_src19_startofpacket; // cmd_demux:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
wire cmd_demux_src19_endofpacket; // cmd_demux:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
wire cmd_demux_src20_valid; // cmd_demux:src20_valid -> cmd_mux_020:sink0_valid
wire [98:0] cmd_demux_src20_data; // cmd_demux:src20_data -> cmd_mux_020:sink0_data
wire cmd_demux_src20_ready; // cmd_mux_020:sink0_ready -> cmd_demux:src20_ready
wire [31:0] cmd_demux_src20_channel; // cmd_demux:src20_channel -> cmd_mux_020:sink0_channel
wire cmd_demux_src20_startofpacket; // cmd_demux:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
wire cmd_demux_src20_endofpacket; // cmd_demux:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
wire cmd_demux_src21_valid; // cmd_demux:src21_valid -> cmd_mux_021:sink0_valid
wire [98:0] cmd_demux_src21_data; // cmd_demux:src21_data -> cmd_mux_021:sink0_data
wire cmd_demux_src21_ready; // cmd_mux_021:sink0_ready -> cmd_demux:src21_ready
wire [31:0] cmd_demux_src21_channel; // cmd_demux:src21_channel -> cmd_mux_021:sink0_channel
wire cmd_demux_src21_startofpacket; // cmd_demux:src21_startofpacket -> cmd_mux_021:sink0_startofpacket
wire cmd_demux_src21_endofpacket; // cmd_demux:src21_endofpacket -> cmd_mux_021:sink0_endofpacket
wire cmd_demux_src22_valid; // cmd_demux:src22_valid -> cmd_mux_022:sink0_valid
wire [98:0] cmd_demux_src22_data; // cmd_demux:src22_data -> cmd_mux_022:sink0_data
wire cmd_demux_src22_ready; // cmd_mux_022:sink0_ready -> cmd_demux:src22_ready
wire [31:0] cmd_demux_src22_channel; // cmd_demux:src22_channel -> cmd_mux_022:sink0_channel
wire cmd_demux_src22_startofpacket; // cmd_demux:src22_startofpacket -> cmd_mux_022:sink0_startofpacket
wire cmd_demux_src22_endofpacket; // cmd_demux:src22_endofpacket -> cmd_mux_022:sink0_endofpacket
wire cmd_demux_src23_valid; // cmd_demux:src23_valid -> cmd_mux_023:sink0_valid
wire [98:0] cmd_demux_src23_data; // cmd_demux:src23_data -> cmd_mux_023:sink0_data
wire cmd_demux_src23_ready; // cmd_mux_023:sink0_ready -> cmd_demux:src23_ready
wire [31:0] cmd_demux_src23_channel; // cmd_demux:src23_channel -> cmd_mux_023:sink0_channel
wire cmd_demux_src23_startofpacket; // cmd_demux:src23_startofpacket -> cmd_mux_023:sink0_startofpacket
wire cmd_demux_src23_endofpacket; // cmd_demux:src23_endofpacket -> cmd_mux_023:sink0_endofpacket
wire cmd_demux_src24_valid; // cmd_demux:src24_valid -> cmd_mux_024:sink0_valid
wire [98:0] cmd_demux_src24_data; // cmd_demux:src24_data -> cmd_mux_024:sink0_data
wire cmd_demux_src24_ready; // cmd_mux_024:sink0_ready -> cmd_demux:src24_ready
wire [31:0] cmd_demux_src24_channel; // cmd_demux:src24_channel -> cmd_mux_024:sink0_channel
wire cmd_demux_src24_startofpacket; // cmd_demux:src24_startofpacket -> cmd_mux_024:sink0_startofpacket
wire cmd_demux_src24_endofpacket; // cmd_demux:src24_endofpacket -> cmd_mux_024:sink0_endofpacket
wire cmd_demux_src25_valid; // cmd_demux:src25_valid -> cmd_mux_025:sink0_valid
wire [98:0] cmd_demux_src25_data; // cmd_demux:src25_data -> cmd_mux_025:sink0_data
wire cmd_demux_src25_ready; // cmd_mux_025:sink0_ready -> cmd_demux:src25_ready
wire [31:0] cmd_demux_src25_channel; // cmd_demux:src25_channel -> cmd_mux_025:sink0_channel
wire cmd_demux_src25_startofpacket; // cmd_demux:src25_startofpacket -> cmd_mux_025:sink0_startofpacket
wire cmd_demux_src25_endofpacket; // cmd_demux:src25_endofpacket -> cmd_mux_025:sink0_endofpacket
wire cmd_demux_src26_valid; // cmd_demux:src26_valid -> cmd_mux_026:sink0_valid
wire [98:0] cmd_demux_src26_data; // cmd_demux:src26_data -> cmd_mux_026:sink0_data
wire cmd_demux_src26_ready; // cmd_mux_026:sink0_ready -> cmd_demux:src26_ready
wire [31:0] cmd_demux_src26_channel; // cmd_demux:src26_channel -> cmd_mux_026:sink0_channel
wire cmd_demux_src26_startofpacket; // cmd_demux:src26_startofpacket -> cmd_mux_026:sink0_startofpacket
wire cmd_demux_src26_endofpacket; // cmd_demux:src26_endofpacket -> cmd_mux_026:sink0_endofpacket
wire cmd_demux_src27_valid; // cmd_demux:src27_valid -> cmd_mux_027:sink0_valid
wire [98:0] cmd_demux_src27_data; // cmd_demux:src27_data -> cmd_mux_027:sink0_data
wire cmd_demux_src27_ready; // cmd_mux_027:sink0_ready -> cmd_demux:src27_ready
wire [31:0] cmd_demux_src27_channel; // cmd_demux:src27_channel -> cmd_mux_027:sink0_channel
wire cmd_demux_src27_startofpacket; // cmd_demux:src27_startofpacket -> cmd_mux_027:sink0_startofpacket
wire cmd_demux_src27_endofpacket; // cmd_demux:src27_endofpacket -> cmd_mux_027:sink0_endofpacket
wire cmd_demux_src28_valid; // cmd_demux:src28_valid -> cmd_mux_028:sink0_valid
wire [98:0] cmd_demux_src28_data; // cmd_demux:src28_data -> cmd_mux_028:sink0_data
wire cmd_demux_src28_ready; // cmd_mux_028:sink0_ready -> cmd_demux:src28_ready
wire [31:0] cmd_demux_src28_channel; // cmd_demux:src28_channel -> cmd_mux_028:sink0_channel
wire cmd_demux_src28_startofpacket; // cmd_demux:src28_startofpacket -> cmd_mux_028:sink0_startofpacket
wire cmd_demux_src28_endofpacket; // cmd_demux:src28_endofpacket -> cmd_mux_028:sink0_endofpacket
wire cmd_demux_src29_valid; // cmd_demux:src29_valid -> cmd_mux_029:sink0_valid
wire [98:0] cmd_demux_src29_data; // cmd_demux:src29_data -> cmd_mux_029:sink0_data
wire cmd_demux_src29_ready; // cmd_mux_029:sink0_ready -> cmd_demux:src29_ready
wire [31:0] cmd_demux_src29_channel; // cmd_demux:src29_channel -> cmd_mux_029:sink0_channel
wire cmd_demux_src29_startofpacket; // cmd_demux:src29_startofpacket -> cmd_mux_029:sink0_startofpacket
wire cmd_demux_src29_endofpacket; // cmd_demux:src29_endofpacket -> cmd_mux_029:sink0_endofpacket
wire cmd_demux_src30_valid; // cmd_demux:src30_valid -> cmd_mux_030:sink0_valid
wire [98:0] cmd_demux_src30_data; // cmd_demux:src30_data -> cmd_mux_030:sink0_data
wire cmd_demux_src30_ready; // cmd_mux_030:sink0_ready -> cmd_demux:src30_ready
wire [31:0] cmd_demux_src30_channel; // cmd_demux:src30_channel -> cmd_mux_030:sink0_channel
wire cmd_demux_src30_startofpacket; // cmd_demux:src30_startofpacket -> cmd_mux_030:sink0_startofpacket
wire cmd_demux_src30_endofpacket; // cmd_demux:src30_endofpacket -> cmd_mux_030:sink0_endofpacket
wire cmd_demux_src31_valid; // cmd_demux:src31_valid -> cmd_mux_031:sink0_valid
wire [98:0] cmd_demux_src31_data; // cmd_demux:src31_data -> cmd_mux_031:sink0_data
wire cmd_demux_src31_ready; // cmd_mux_031:sink0_ready -> cmd_demux:src31_ready
wire [31:0] cmd_demux_src31_channel; // cmd_demux:src31_channel -> cmd_mux_031:sink0_channel
wire cmd_demux_src31_startofpacket; // cmd_demux:src31_startofpacket -> cmd_mux_031:sink0_startofpacket
wire cmd_demux_src31_endofpacket; // cmd_demux:src31_endofpacket -> cmd_mux_031:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_001:sink1_valid
wire [98:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src0_ready
wire [31:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_002:sink1_valid
wire [98:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src1_ready
wire [31:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [98:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [31:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [98:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [31:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink0_valid
wire [98:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_001:src1_ready
wire [31:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [98:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [31:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink1_valid
wire [98:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_002:src1_ready
wire [31:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [98:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [31:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [98:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [31:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [98:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [31:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire [98:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire [31:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [98:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [31:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
wire [98:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
wire [31:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux:sink9_valid
wire [98:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux:sink9_data
wire rsp_demux_009_src0_ready; // rsp_mux:sink9_ready -> rsp_demux_009:src0_ready
wire [31:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux:sink9_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux:sink9_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux:sink9_endofpacket
wire rsp_demux_010_src0_valid; // rsp_demux_010:src0_valid -> rsp_mux:sink10_valid
wire [98:0] rsp_demux_010_src0_data; // rsp_demux_010:src0_data -> rsp_mux:sink10_data
wire rsp_demux_010_src0_ready; // rsp_mux:sink10_ready -> rsp_demux_010:src0_ready
wire [31:0] rsp_demux_010_src0_channel; // rsp_demux_010:src0_channel -> rsp_mux:sink10_channel
wire rsp_demux_010_src0_startofpacket; // rsp_demux_010:src0_startofpacket -> rsp_mux:sink10_startofpacket
wire rsp_demux_010_src0_endofpacket; // rsp_demux_010:src0_endofpacket -> rsp_mux:sink10_endofpacket
wire rsp_demux_011_src0_valid; // rsp_demux_011:src0_valid -> rsp_mux:sink11_valid
wire [98:0] rsp_demux_011_src0_data; // rsp_demux_011:src0_data -> rsp_mux:sink11_data
wire rsp_demux_011_src0_ready; // rsp_mux:sink11_ready -> rsp_demux_011:src0_ready
wire [31:0] rsp_demux_011_src0_channel; // rsp_demux_011:src0_channel -> rsp_mux:sink11_channel
wire rsp_demux_011_src0_startofpacket; // rsp_demux_011:src0_startofpacket -> rsp_mux:sink11_startofpacket
wire rsp_demux_011_src0_endofpacket; // rsp_demux_011:src0_endofpacket -> rsp_mux:sink11_endofpacket
wire rsp_demux_012_src0_valid; // rsp_demux_012:src0_valid -> rsp_mux:sink12_valid
wire [98:0] rsp_demux_012_src0_data; // rsp_demux_012:src0_data -> rsp_mux:sink12_data
wire rsp_demux_012_src0_ready; // rsp_mux:sink12_ready -> rsp_demux_012:src0_ready
wire [31:0] rsp_demux_012_src0_channel; // rsp_demux_012:src0_channel -> rsp_mux:sink12_channel
wire rsp_demux_012_src0_startofpacket; // rsp_demux_012:src0_startofpacket -> rsp_mux:sink12_startofpacket
wire rsp_demux_012_src0_endofpacket; // rsp_demux_012:src0_endofpacket -> rsp_mux:sink12_endofpacket
wire rsp_demux_013_src0_valid; // rsp_demux_013:src0_valid -> rsp_mux:sink13_valid
wire [98:0] rsp_demux_013_src0_data; // rsp_demux_013:src0_data -> rsp_mux:sink13_data
wire rsp_demux_013_src0_ready; // rsp_mux:sink13_ready -> rsp_demux_013:src0_ready
wire [31:0] rsp_demux_013_src0_channel; // rsp_demux_013:src0_channel -> rsp_mux:sink13_channel
wire rsp_demux_013_src0_startofpacket; // rsp_demux_013:src0_startofpacket -> rsp_mux:sink13_startofpacket
wire rsp_demux_013_src0_endofpacket; // rsp_demux_013:src0_endofpacket -> rsp_mux:sink13_endofpacket
wire rsp_demux_014_src0_valid; // rsp_demux_014:src0_valid -> rsp_mux:sink14_valid
wire [98:0] rsp_demux_014_src0_data; // rsp_demux_014:src0_data -> rsp_mux:sink14_data
wire rsp_demux_014_src0_ready; // rsp_mux:sink14_ready -> rsp_demux_014:src0_ready
wire [31:0] rsp_demux_014_src0_channel; // rsp_demux_014:src0_channel -> rsp_mux:sink14_channel
wire rsp_demux_014_src0_startofpacket; // rsp_demux_014:src0_startofpacket -> rsp_mux:sink14_startofpacket
wire rsp_demux_014_src0_endofpacket; // rsp_demux_014:src0_endofpacket -> rsp_mux:sink14_endofpacket
wire rsp_demux_015_src0_valid; // rsp_demux_015:src0_valid -> rsp_mux:sink15_valid
wire [98:0] rsp_demux_015_src0_data; // rsp_demux_015:src0_data -> rsp_mux:sink15_data
wire rsp_demux_015_src0_ready; // rsp_mux:sink15_ready -> rsp_demux_015:src0_ready
wire [31:0] rsp_demux_015_src0_channel; // rsp_demux_015:src0_channel -> rsp_mux:sink15_channel
wire rsp_demux_015_src0_startofpacket; // rsp_demux_015:src0_startofpacket -> rsp_mux:sink15_startofpacket
wire rsp_demux_015_src0_endofpacket; // rsp_demux_015:src0_endofpacket -> rsp_mux:sink15_endofpacket
wire rsp_demux_016_src0_valid; // rsp_demux_016:src0_valid -> rsp_mux:sink16_valid
wire [98:0] rsp_demux_016_src0_data; // rsp_demux_016:src0_data -> rsp_mux:sink16_data
wire rsp_demux_016_src0_ready; // rsp_mux:sink16_ready -> rsp_demux_016:src0_ready
wire [31:0] rsp_demux_016_src0_channel; // rsp_demux_016:src0_channel -> rsp_mux:sink16_channel
wire rsp_demux_016_src0_startofpacket; // rsp_demux_016:src0_startofpacket -> rsp_mux:sink16_startofpacket
wire rsp_demux_016_src0_endofpacket; // rsp_demux_016:src0_endofpacket -> rsp_mux:sink16_endofpacket
wire rsp_demux_017_src0_valid; // rsp_demux_017:src0_valid -> rsp_mux:sink17_valid
wire [98:0] rsp_demux_017_src0_data; // rsp_demux_017:src0_data -> rsp_mux:sink17_data
wire rsp_demux_017_src0_ready; // rsp_mux:sink17_ready -> rsp_demux_017:src0_ready
wire [31:0] rsp_demux_017_src0_channel; // rsp_demux_017:src0_channel -> rsp_mux:sink17_channel
wire rsp_demux_017_src0_startofpacket; // rsp_demux_017:src0_startofpacket -> rsp_mux:sink17_startofpacket
wire rsp_demux_017_src0_endofpacket; // rsp_demux_017:src0_endofpacket -> rsp_mux:sink17_endofpacket
wire rsp_demux_018_src0_valid; // rsp_demux_018:src0_valid -> rsp_mux:sink18_valid
wire [98:0] rsp_demux_018_src0_data; // rsp_demux_018:src0_data -> rsp_mux:sink18_data
wire rsp_demux_018_src0_ready; // rsp_mux:sink18_ready -> rsp_demux_018:src0_ready
wire [31:0] rsp_demux_018_src0_channel; // rsp_demux_018:src0_channel -> rsp_mux:sink18_channel
wire rsp_demux_018_src0_startofpacket; // rsp_demux_018:src0_startofpacket -> rsp_mux:sink18_startofpacket
wire rsp_demux_018_src0_endofpacket; // rsp_demux_018:src0_endofpacket -> rsp_mux:sink18_endofpacket
wire rsp_demux_019_src0_valid; // rsp_demux_019:src0_valid -> rsp_mux:sink19_valid
wire [98:0] rsp_demux_019_src0_data; // rsp_demux_019:src0_data -> rsp_mux:sink19_data
wire rsp_demux_019_src0_ready; // rsp_mux:sink19_ready -> rsp_demux_019:src0_ready
wire [31:0] rsp_demux_019_src0_channel; // rsp_demux_019:src0_channel -> rsp_mux:sink19_channel
wire rsp_demux_019_src0_startofpacket; // rsp_demux_019:src0_startofpacket -> rsp_mux:sink19_startofpacket
wire rsp_demux_019_src0_endofpacket; // rsp_demux_019:src0_endofpacket -> rsp_mux:sink19_endofpacket
wire rsp_demux_020_src0_valid; // rsp_demux_020:src0_valid -> rsp_mux:sink20_valid
wire [98:0] rsp_demux_020_src0_data; // rsp_demux_020:src0_data -> rsp_mux:sink20_data
wire rsp_demux_020_src0_ready; // rsp_mux:sink20_ready -> rsp_demux_020:src0_ready
wire [31:0] rsp_demux_020_src0_channel; // rsp_demux_020:src0_channel -> rsp_mux:sink20_channel
wire rsp_demux_020_src0_startofpacket; // rsp_demux_020:src0_startofpacket -> rsp_mux:sink20_startofpacket
wire rsp_demux_020_src0_endofpacket; // rsp_demux_020:src0_endofpacket -> rsp_mux:sink20_endofpacket
wire rsp_demux_021_src0_valid; // rsp_demux_021:src0_valid -> rsp_mux:sink21_valid
wire [98:0] rsp_demux_021_src0_data; // rsp_demux_021:src0_data -> rsp_mux:sink21_data
wire rsp_demux_021_src0_ready; // rsp_mux:sink21_ready -> rsp_demux_021:src0_ready
wire [31:0] rsp_demux_021_src0_channel; // rsp_demux_021:src0_channel -> rsp_mux:sink21_channel
wire rsp_demux_021_src0_startofpacket; // rsp_demux_021:src0_startofpacket -> rsp_mux:sink21_startofpacket
wire rsp_demux_021_src0_endofpacket; // rsp_demux_021:src0_endofpacket -> rsp_mux:sink21_endofpacket
wire rsp_demux_022_src0_valid; // rsp_demux_022:src0_valid -> rsp_mux:sink22_valid
wire [98:0] rsp_demux_022_src0_data; // rsp_demux_022:src0_data -> rsp_mux:sink22_data
wire rsp_demux_022_src0_ready; // rsp_mux:sink22_ready -> rsp_demux_022:src0_ready
wire [31:0] rsp_demux_022_src0_channel; // rsp_demux_022:src0_channel -> rsp_mux:sink22_channel
wire rsp_demux_022_src0_startofpacket; // rsp_demux_022:src0_startofpacket -> rsp_mux:sink22_startofpacket
wire rsp_demux_022_src0_endofpacket; // rsp_demux_022:src0_endofpacket -> rsp_mux:sink22_endofpacket
wire rsp_demux_023_src0_valid; // rsp_demux_023:src0_valid -> rsp_mux:sink23_valid
wire [98:0] rsp_demux_023_src0_data; // rsp_demux_023:src0_data -> rsp_mux:sink23_data
wire rsp_demux_023_src0_ready; // rsp_mux:sink23_ready -> rsp_demux_023:src0_ready
wire [31:0] rsp_demux_023_src0_channel; // rsp_demux_023:src0_channel -> rsp_mux:sink23_channel
wire rsp_demux_023_src0_startofpacket; // rsp_demux_023:src0_startofpacket -> rsp_mux:sink23_startofpacket
wire rsp_demux_023_src0_endofpacket; // rsp_demux_023:src0_endofpacket -> rsp_mux:sink23_endofpacket
wire rsp_demux_024_src0_valid; // rsp_demux_024:src0_valid -> rsp_mux:sink24_valid
wire [98:0] rsp_demux_024_src0_data; // rsp_demux_024:src0_data -> rsp_mux:sink24_data
wire rsp_demux_024_src0_ready; // rsp_mux:sink24_ready -> rsp_demux_024:src0_ready
wire [31:0] rsp_demux_024_src0_channel; // rsp_demux_024:src0_channel -> rsp_mux:sink24_channel
wire rsp_demux_024_src0_startofpacket; // rsp_demux_024:src0_startofpacket -> rsp_mux:sink24_startofpacket
wire rsp_demux_024_src0_endofpacket; // rsp_demux_024:src0_endofpacket -> rsp_mux:sink24_endofpacket
wire rsp_demux_025_src0_valid; // rsp_demux_025:src0_valid -> rsp_mux:sink25_valid
wire [98:0] rsp_demux_025_src0_data; // rsp_demux_025:src0_data -> rsp_mux:sink25_data
wire rsp_demux_025_src0_ready; // rsp_mux:sink25_ready -> rsp_demux_025:src0_ready
wire [31:0] rsp_demux_025_src0_channel; // rsp_demux_025:src0_channel -> rsp_mux:sink25_channel
wire rsp_demux_025_src0_startofpacket; // rsp_demux_025:src0_startofpacket -> rsp_mux:sink25_startofpacket
wire rsp_demux_025_src0_endofpacket; // rsp_demux_025:src0_endofpacket -> rsp_mux:sink25_endofpacket
wire rsp_demux_026_src0_valid; // rsp_demux_026:src0_valid -> rsp_mux:sink26_valid
wire [98:0] rsp_demux_026_src0_data; // rsp_demux_026:src0_data -> rsp_mux:sink26_data
wire rsp_demux_026_src0_ready; // rsp_mux:sink26_ready -> rsp_demux_026:src0_ready
wire [31:0] rsp_demux_026_src0_channel; // rsp_demux_026:src0_channel -> rsp_mux:sink26_channel
wire rsp_demux_026_src0_startofpacket; // rsp_demux_026:src0_startofpacket -> rsp_mux:sink26_startofpacket
wire rsp_demux_026_src0_endofpacket; // rsp_demux_026:src0_endofpacket -> rsp_mux:sink26_endofpacket
wire rsp_demux_027_src0_valid; // rsp_demux_027:src0_valid -> rsp_mux:sink27_valid
wire [98:0] rsp_demux_027_src0_data; // rsp_demux_027:src0_data -> rsp_mux:sink27_data
wire rsp_demux_027_src0_ready; // rsp_mux:sink27_ready -> rsp_demux_027:src0_ready
wire [31:0] rsp_demux_027_src0_channel; // rsp_demux_027:src0_channel -> rsp_mux:sink27_channel
wire rsp_demux_027_src0_startofpacket; // rsp_demux_027:src0_startofpacket -> rsp_mux:sink27_startofpacket
wire rsp_demux_027_src0_endofpacket; // rsp_demux_027:src0_endofpacket -> rsp_mux:sink27_endofpacket
wire rsp_demux_028_src0_valid; // rsp_demux_028:src0_valid -> rsp_mux:sink28_valid
wire [98:0] rsp_demux_028_src0_data; // rsp_demux_028:src0_data -> rsp_mux:sink28_data
wire rsp_demux_028_src0_ready; // rsp_mux:sink28_ready -> rsp_demux_028:src0_ready
wire [31:0] rsp_demux_028_src0_channel; // rsp_demux_028:src0_channel -> rsp_mux:sink28_channel
wire rsp_demux_028_src0_startofpacket; // rsp_demux_028:src0_startofpacket -> rsp_mux:sink28_startofpacket
wire rsp_demux_028_src0_endofpacket; // rsp_demux_028:src0_endofpacket -> rsp_mux:sink28_endofpacket
wire rsp_demux_029_src0_valid; // rsp_demux_029:src0_valid -> rsp_mux:sink29_valid
wire [98:0] rsp_demux_029_src0_data; // rsp_demux_029:src0_data -> rsp_mux:sink29_data
wire rsp_demux_029_src0_ready; // rsp_mux:sink29_ready -> rsp_demux_029:src0_ready
wire [31:0] rsp_demux_029_src0_channel; // rsp_demux_029:src0_channel -> rsp_mux:sink29_channel
wire rsp_demux_029_src0_startofpacket; // rsp_demux_029:src0_startofpacket -> rsp_mux:sink29_startofpacket
wire rsp_demux_029_src0_endofpacket; // rsp_demux_029:src0_endofpacket -> rsp_mux:sink29_endofpacket
wire rsp_demux_030_src0_valid; // rsp_demux_030:src0_valid -> rsp_mux:sink30_valid
wire [98:0] rsp_demux_030_src0_data; // rsp_demux_030:src0_data -> rsp_mux:sink30_data
wire rsp_demux_030_src0_ready; // rsp_mux:sink30_ready -> rsp_demux_030:src0_ready
wire [31:0] rsp_demux_030_src0_channel; // rsp_demux_030:src0_channel -> rsp_mux:sink30_channel
wire rsp_demux_030_src0_startofpacket; // rsp_demux_030:src0_startofpacket -> rsp_mux:sink30_startofpacket
wire rsp_demux_030_src0_endofpacket; // rsp_demux_030:src0_endofpacket -> rsp_mux:sink30_endofpacket
wire rsp_demux_031_src0_valid; // rsp_demux_031:src0_valid -> rsp_mux:sink31_valid
wire [98:0] rsp_demux_031_src0_data; // rsp_demux_031:src0_data -> rsp_mux:sink31_data
wire rsp_demux_031_src0_ready; // rsp_mux:sink31_ready -> rsp_demux_031:src0_ready
wire [31:0] rsp_demux_031_src0_channel; // rsp_demux_031:src0_channel -> rsp_mux:sink31_channel
wire rsp_demux_031_src0_startofpacket; // rsp_demux_031:src0_startofpacket -> rsp_mux:sink31_startofpacket
wire rsp_demux_031_src0_endofpacket; // rsp_demux_031:src0_endofpacket -> rsp_mux:sink31_endofpacket
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_qsys_0_data_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_0_data_master_read), // .read
.av_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.av_write (nios2_qsys_0_data_master_write), // .write
.av_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_0_instruction_master_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_0_instruction_master_read), // .read
.av_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_0_debug_mem_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_qsys_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_qsys_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_0_debug_mem_slave_write), // .write
.av_read (nios2_qsys_0_debug_mem_slave_read), // .read
.av_readdata (nios2_qsys_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_qsys_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_qsys_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_qsys_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_qsys_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (15),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) leds_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (leds_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.uav_read (leds_s1_agent_m0_read), // .read
.uav_write (leds_s1_agent_m0_write), // .write
.uav_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (leds_s1_agent_m0_readdata), // .readdata
.uav_writedata (leds_s1_agent_m0_writedata), // .writedata
.uav_lock (leds_s1_agent_m0_lock), // .lock
.uav_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.av_address (LEDs_s1_address), // avalon_anti_slave_0.address
.av_write (LEDs_s1_write), // .write
.av_readdata (LEDs_s1_readdata), // .readdata
.av_writedata (LEDs_s1_writedata), // .writedata
.av_chipselect (LEDs_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switches_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (switches_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.uav_read (switches_s1_agent_m0_read), // .read
.uav_write (switches_s1_agent_m0_write), // .write
.uav_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (switches_s1_agent_m0_readdata), // .readdata
.uav_writedata (switches_s1_agent_m0_writedata), // .writedata
.uav_lock (switches_s1_agent_m0_lock), // .lock
.uav_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.av_address (switches_s1_address), // avalon_anti_slave_0.address
.av_readdata (switches_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_data_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_data_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_data_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_data_s1_agent_m0_read), // .read
.uav_write (sram_data_s1_agent_m0_write), // .write
.uav_waitrequest (sram_data_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_data_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_data_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_data_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_data_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_data_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_data_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_data_s1_address), // avalon_anti_slave_0.address
.av_write (sram_data_s1_write), // .write
.av_readdata (sram_data_s1_readdata), // .readdata
.av_writedata (sram_data_s1_writedata), // .writedata
.av_chipselect (sram_data_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_addr_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_addr_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_addr_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_addr_s1_agent_m0_read), // .read
.uav_write (sram_addr_s1_agent_m0_write), // .write
.uav_waitrequest (sram_addr_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_addr_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_addr_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_addr_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_addr_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_addr_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_addr_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_addr_s1_address), // avalon_anti_slave_0.address
.av_write (sram_addr_s1_write), // .write
.av_readdata (sram_addr_s1_readdata), // .readdata
.av_writedata (sram_addr_s1_writedata), // .writedata
.av_chipselect (sram_addr_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_read_write_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_read_write_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_read_write_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_read_write_s1_agent_m0_read), // .read
.uav_write (sram_read_write_s1_agent_m0_write), // .write
.uav_waitrequest (sram_read_write_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_read_write_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_read_write_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_read_write_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_read_write_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_read_write_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_read_write_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_read_write_s1_address), // avalon_anti_slave_0.address
.av_write (sram_read_write_s1_write), // .write
.av_readdata (sram_read_write_s1_readdata), // .readdata
.av_writedata (sram_read_write_s1_writedata), // .writedata
.av_chipselect (sram_read_write_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_cs_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_cs_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_cs_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_cs_s1_agent_m0_read), // .read
.uav_write (sram_cs_s1_agent_m0_write), // .write
.uav_waitrequest (sram_cs_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_cs_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_cs_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_cs_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_cs_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_cs_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_cs_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_cs_s1_address), // avalon_anti_slave_0.address
.av_write (sram_cs_s1_write), // .write
.av_readdata (sram_cs_s1_readdata), // .readdata
.av_writedata (sram_cs_s1_writedata), // .writedata
.av_chipselect (sram_cs_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_oe_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sram_oe_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_oe_s1_agent_m0_burstcount), // .burstcount
.uav_read (sram_oe_s1_agent_m0_read), // .read
.uav_write (sram_oe_s1_agent_m0_write), // .write
.uav_waitrequest (sram_oe_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_oe_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_oe_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_oe_s1_agent_m0_readdata), // .readdata
.uav_writedata (sram_oe_s1_agent_m0_writedata), // .writedata
.uav_lock (sram_oe_s1_agent_m0_lock), // .lock
.uav_debugaccess (sram_oe_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sram_oe_s1_address), // avalon_anti_slave_0.address
.av_write (sram_oe_s1_write), // .write
.av_readdata (sram_oe_s1_readdata), // .readdata
.av_writedata (sram_oe_s1_writedata), // .writedata
.av_chipselect (sram_oe_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_data_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_data_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_data_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_data_s1_agent_m0_read), // .read
.uav_write (regfile_data_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_data_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_data_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_data_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_data_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_data_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_data_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_data_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_data_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_data_s1_write), // .write
.av_readdata (regfile_data_s1_readdata), // .readdata
.av_writedata (regfile_data_s1_writedata), // .writedata
.av_chipselect (regfile_data_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_reg1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_reg1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_reg1_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_reg1_s1_agent_m0_read), // .read
.uav_write (regfile_reg1_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_reg1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_reg1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_reg1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_reg1_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_reg1_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_reg1_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_reg1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_reg1_s1_address), // avalon_anti_slave_0.address
.av_readdata (regfile_reg1_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_reg2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_reg2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_reg2_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_reg2_s1_agent_m0_read), // .read
.uav_write (regfile_reg2_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_reg2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_reg2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_reg2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_reg2_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_reg2_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_reg2_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_reg2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_reg2_s1_address), // avalon_anti_slave_0.address
.av_readdata (regfile_reg2_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_r1sel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_r1sel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_r1sel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_r1sel_s1_agent_m0_read), // .read
.uav_write (regfile_r1sel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_r1sel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_r1sel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_r1sel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_r1sel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_r1sel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_r1sel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_r1sel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_r1sel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_r1sel_s1_write), // .write
.av_readdata (regfile_r1sel_s1_readdata), // .readdata
.av_writedata (regfile_r1sel_s1_writedata), // .writedata
.av_chipselect (regfile_r1sel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_r2sel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_r2sel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_r2sel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_r2sel_s1_agent_m0_read), // .read
.uav_write (regfile_r2sel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_r2sel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_r2sel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_r2sel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_r2sel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_r2sel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_r2sel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_r2sel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_r2sel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_r2sel_s1_write), // .write
.av_readdata (regfile_r2sel_s1_readdata), // .readdata
.av_writedata (regfile_r2sel_s1_writedata), // .writedata
.av_chipselect (regfile_r2sel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_wsel_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_wsel_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_wsel_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_wsel_s1_agent_m0_read), // .read
.uav_write (regfile_wsel_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_wsel_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_wsel_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_wsel_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_wsel_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_wsel_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_wsel_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_wsel_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_wsel_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_wsel_s1_write), // .write
.av_readdata (regfile_wsel_s1_readdata), // .readdata
.av_writedata (regfile_wsel_s1_writedata), // .writedata
.av_chipselect (regfile_wsel_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) regfile_we_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (regfile_we_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (regfile_we_s1_agent_m0_burstcount), // .burstcount
.uav_read (regfile_we_s1_agent_m0_read), // .read
.uav_write (regfile_we_s1_agent_m0_write), // .write
.uav_waitrequest (regfile_we_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (regfile_we_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (regfile_we_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (regfile_we_s1_agent_m0_readdata), // .readdata
.uav_writedata (regfile_we_s1_agent_m0_writedata), // .writedata
.uav_lock (regfile_we_s1_agent_m0_lock), // .lock
.uav_debugaccess (regfile_we_s1_agent_m0_debugaccess), // .debugaccess
.av_address (regfile_we_s1_address), // avalon_anti_slave_0.address
.av_write (regfile_we_s1_write), // .write
.av_readdata (regfile_we_s1_readdata), // .readdata
.av_writedata (regfile_we_s1_writedata), // .writedata
.av_chipselect (regfile_we_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_0_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_0_s1_agent_m0_read), // .read
.uav_write (hex_0_s1_agent_m0_write), // .write
.uav_waitrequest (hex_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_0_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_0_s1_address), // avalon_anti_slave_0.address
.av_write (hex_0_s1_write), // .write
.av_readdata (hex_0_s1_readdata), // .readdata
.av_writedata (hex_0_s1_writedata), // .writedata
.av_chipselect (hex_0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_1_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_1_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_1_s1_agent_m0_read), // .read
.uav_write (hex_1_s1_agent_m0_write), // .write
.uav_waitrequest (hex_1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_1_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_1_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_1_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_1_s1_address), // avalon_anti_slave_0.address
.av_write (hex_1_s1_write), // .write
.av_readdata (hex_1_s1_readdata), // .readdata
.av_writedata (hex_1_s1_writedata), // .writedata
.av_chipselect (hex_1_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_2_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_2_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_2_s1_agent_m0_read), // .read
.uav_write (hex_2_s1_agent_m0_write), // .write
.uav_waitrequest (hex_2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_2_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_2_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_2_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_2_s1_address), // avalon_anti_slave_0.address
.av_write (hex_2_s1_write), // .write
.av_readdata (hex_2_s1_readdata), // .readdata
.av_writedata (hex_2_s1_writedata), // .writedata
.av_chipselect (hex_2_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_3_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_3_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_3_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_3_s1_agent_m0_read), // .read
.uav_write (hex_3_s1_agent_m0_write), // .write
.uav_waitrequest (hex_3_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_3_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_3_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_3_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_3_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_3_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_3_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_3_s1_address), // avalon_anti_slave_0.address
.av_write (hex_3_s1_write), // .write
.av_readdata (hex_3_s1_readdata), // .readdata
.av_writedata (hex_3_s1_writedata), // .writedata
.av_chipselect (hex_3_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_4_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_4_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_4_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_4_s1_agent_m0_read), // .read
.uav_write (hex_4_s1_agent_m0_write), // .write
.uav_waitrequest (hex_4_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_4_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_4_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_4_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_4_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_4_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_4_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_4_s1_address), // avalon_anti_slave_0.address
.av_write (hex_4_s1_write), // .write
.av_readdata (hex_4_s1_readdata), // .readdata
.av_writedata (hex_4_s1_writedata), // .writedata
.av_chipselect (hex_4_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex_5_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex_5_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex_5_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex_5_s1_agent_m0_read), // .read
.uav_write (hex_5_s1_agent_m0_write), // .write
.uav_waitrequest (hex_5_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex_5_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex_5_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex_5_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex_5_s1_agent_m0_writedata), // .writedata
.uav_lock (hex_5_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex_5_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex_5_s1_address), // avalon_anti_slave_0.address
.av_write (hex_5_s1_write), // .write
.av_readdata (hex_5_s1_readdata), // .readdata
.av_writedata (hex_5_s1_writedata), // .writedata
.av_chipselect (hex_5_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_a_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_a_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_a_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_a_s1_agent_m0_read), // .read
.uav_write (alu_a_s1_agent_m0_write), // .write
.uav_waitrequest (alu_a_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_a_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_a_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_a_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_a_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_a_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_a_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_a_s1_address), // avalon_anti_slave_0.address
.av_write (alu_a_s1_write), // .write
.av_readdata (alu_a_s1_readdata), // .readdata
.av_writedata (alu_a_s1_writedata), // .writedata
.av_chipselect (alu_a_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_b_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_b_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_b_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_b_s1_agent_m0_read), // .read
.uav_write (alu_b_s1_agent_m0_write), // .write
.uav_waitrequest (alu_b_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_b_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_b_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_b_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_b_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_b_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_b_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_b_s1_address), // avalon_anti_slave_0.address
.av_write (alu_b_s1_write), // .write
.av_readdata (alu_b_s1_readdata), // .readdata
.av_writedata (alu_b_s1_writedata), // .writedata
.av_chipselect (alu_b_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_control_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_control_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_control_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_control_s1_agent_m0_read), // .read
.uav_write (alu_control_s1_agent_m0_write), // .write
.uav_waitrequest (alu_control_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_control_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_control_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_control_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_control_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_control_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_control_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_control_s1_address), // avalon_anti_slave_0.address
.av_write (alu_control_s1_write), // .write
.av_readdata (alu_control_s1_readdata), // .readdata
.av_writedata (alu_control_s1_writedata), // .writedata
.av_chipselect (alu_control_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_out_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_out_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_out_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_out_s1_agent_m0_read), // .read
.uav_write (alu_out_s1_agent_m0_write), // .write
.uav_waitrequest (alu_out_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_out_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_out_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_out_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_out_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_out_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_out_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_out_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_out_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_zero_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_zero_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_zero_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_zero_s1_agent_m0_read), // .read
.uav_write (alu_zero_s1_agent_m0_write), // .write
.uav_waitrequest (alu_zero_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_zero_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_zero_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_zero_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_zero_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_zero_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_zero_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_zero_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_zero_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_overflow_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_overflow_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_overflow_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_overflow_s1_agent_m0_read), // .read
.uav_write (alu_overflow_s1_agent_m0_write), // .write
.uav_waitrequest (alu_overflow_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_overflow_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_overflow_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_overflow_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_overflow_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_overflow_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_overflow_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_overflow_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_overflow_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_carry_out_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_carry_out_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_carry_out_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_carry_out_s1_agent_m0_read), // .read
.uav_write (alu_carry_out_s1_agent_m0_write), // .write
.uav_waitrequest (alu_carry_out_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_carry_out_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_carry_out_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_carry_out_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_carry_out_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_carry_out_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_carry_out_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_carry_out_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_carry_out_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) alu_negative_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (alu_negative_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (alu_negative_s1_agent_m0_burstcount), // .burstcount
.uav_read (alu_negative_s1_agent_m0_read), // .read
.uav_write (alu_negative_s1_agent_m0_write), // .write
.uav_waitrequest (alu_negative_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (alu_negative_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (alu_negative_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (alu_negative_s1_agent_m0_readdata), // .readdata
.uav_writedata (alu_negative_s1_agent_m0_writedata), // .writedata
.uav_lock (alu_negative_s1_agent_m0_lock), // .lock
.uav_debugaccess (alu_negative_s1_agent_m0_debugaccess), // .debugaccess
.av_address (alu_negative_s1_address), // avalon_anti_slave_0.address
.av_readdata (alu_negative_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (19),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) keys_s1_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (keys_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (keys_s1_agent_m0_burstcount), // .burstcount
.uav_read (keys_s1_agent_m0_read), // .read
.uav_write (keys_s1_agent_m0_write), // .write
.uav_waitrequest (keys_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (keys_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (keys_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (keys_s1_agent_m0_readdata), // .readdata
.uav_writedata (keys_s1_agent_m0_writedata), // .writedata
.uav_lock (keys_s1_agent_m0_lock), // .lock
.uav_debugaccess (keys_s1_agent_m0_debugaccess), // .debugaccess
.av_address (keys_s1_address), // avalon_anti_slave_0.address
.av_readdata (keys_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_CACHE_H (93),
.PKT_CACHE_L (90),
.PKT_THREAD_ID_H (86),
.PKT_THREAD_ID_L (86),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.ST_DATA_W (99),
.ST_CHANNEL_W (32),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_data_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_QOS_H (75),
.PKT_QOS_L (75),
.PKT_DATA_SIDEBAND_H (73),
.PKT_DATA_SIDEBAND_L (73),
.PKT_ADDR_SIDEBAND_H (72),
.PKT_ADDR_SIDEBAND_L (72),
.PKT_BURST_TYPE_H (71),
.PKT_BURST_TYPE_L (70),
.PKT_CACHE_H (93),
.PKT_CACHE_L (90),
.PKT_THREAD_ID_H (86),
.PKT_THREAD_ID_L (86),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_EXCLUSIVE (60),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.ST_DATA_W (99),
.ST_CHANNEL_W (32),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_instruction_master_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_0_avalon_jtag_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_debug_mem_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_qsys_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_qsys_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_0_debug_mem_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_qsys_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) onchip_memory2_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) leds_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (leds_s1_agent_m0_address), // m0.address
.m0_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (leds_s1_agent_m0_lock), // .lock
.m0_readdata (leds_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (leds_s1_agent_m0_read), // .read
.m0_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (leds_s1_agent_m0_writedata), // .writedata
.m0_write (leds_s1_agent_m0_write), // .write
.rp_endofpacket (leds_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (leds_s1_agent_rp_ready), // .ready
.rp_valid (leds_s1_agent_rp_valid), // .valid
.rp_data (leds_s1_agent_rp_data), // .data
.rp_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (leds_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (leds_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (leds_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (leds_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (leds_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (leds_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (leds_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) leds_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (leds_s1_agent_rf_source_data), // in.data
.in_valid (leds_s1_agent_rf_source_valid), // .valid
.in_ready (leds_s1_agent_rf_source_ready), // .ready
.in_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (leds_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (leds_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) switches_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (switches_s1_agent_m0_address), // m0.address
.m0_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (switches_s1_agent_m0_lock), // .lock
.m0_readdata (switches_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switches_s1_agent_m0_read), // .read
.m0_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switches_s1_agent_m0_writedata), // .writedata
.m0_write (switches_s1_agent_m0_write), // .write
.rp_endofpacket (switches_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switches_s1_agent_rp_ready), // .ready
.rp_valid (switches_s1_agent_rp_valid), // .valid
.rp_data (switches_s1_agent_rp_data), // .data
.rp_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (switches_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switches_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switches_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switches_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switches_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (switches_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switches_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switches_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (switches_s1_agent_rf_source_data), // in.data
.in_valid (switches_s1_agent_rf_source_valid), // .valid
.in_ready (switches_s1_agent_rf_source_ready), // .ready
.in_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (switches_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (switches_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_data_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_data_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_data_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_data_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_data_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_data_s1_agent_m0_lock), // .lock
.m0_readdata (sram_data_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_data_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_data_s1_agent_m0_read), // .read
.m0_waitrequest (sram_data_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_data_s1_agent_m0_writedata), // .writedata
.m0_write (sram_data_s1_agent_m0_write), // .write
.rp_endofpacket (sram_data_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_data_s1_agent_rp_ready), // .ready
.rp_valid (sram_data_s1_agent_rp_valid), // .valid
.rp_data (sram_data_s1_agent_rp_data), // .data
.rp_startofpacket (sram_data_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (sram_data_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_data_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_data_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_data_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_data_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_data_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_data_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_data_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_data_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_data_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_data_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_data_s1_agent_rf_source_data), // in.data
.in_valid (sram_data_s1_agent_rf_source_valid), // .valid
.in_ready (sram_data_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_data_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_data_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_data_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_data_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_data_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_addr_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_addr_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_addr_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_addr_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_addr_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_addr_s1_agent_m0_lock), // .lock
.m0_readdata (sram_addr_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_addr_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_addr_s1_agent_m0_read), // .read
.m0_waitrequest (sram_addr_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_addr_s1_agent_m0_writedata), // .writedata
.m0_write (sram_addr_s1_agent_m0_write), // .write
.rp_endofpacket (sram_addr_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_addr_s1_agent_rp_ready), // .ready
.rp_valid (sram_addr_s1_agent_rp_valid), // .valid
.rp_data (sram_addr_s1_agent_rp_data), // .data
.rp_startofpacket (sram_addr_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (sram_addr_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_addr_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_addr_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_addr_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_addr_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_addr_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_addr_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_addr_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_addr_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_addr_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_addr_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_addr_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_addr_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_addr_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_addr_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_addr_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_addr_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_addr_s1_agent_rf_source_data), // in.data
.in_valid (sram_addr_s1_agent_rf_source_valid), // .valid
.in_ready (sram_addr_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_addr_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_addr_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_addr_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_addr_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_addr_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_addr_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_addr_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_read_write_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_read_write_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_read_write_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_read_write_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_read_write_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_read_write_s1_agent_m0_lock), // .lock
.m0_readdata (sram_read_write_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_read_write_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_read_write_s1_agent_m0_read), // .read
.m0_waitrequest (sram_read_write_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_read_write_s1_agent_m0_writedata), // .writedata
.m0_write (sram_read_write_s1_agent_m0_write), // .write
.rp_endofpacket (sram_read_write_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_read_write_s1_agent_rp_ready), // .ready
.rp_valid (sram_read_write_s1_agent_rp_valid), // .valid
.rp_data (sram_read_write_s1_agent_rp_data), // .data
.rp_startofpacket (sram_read_write_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_007_src_ready), // cp.ready
.cp_valid (cmd_mux_007_src_valid), // .valid
.cp_data (cmd_mux_007_src_data), // .data
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_007_src_channel), // .channel
.rf_sink_ready (sram_read_write_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_read_write_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_read_write_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_read_write_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_read_write_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_read_write_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_read_write_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_read_write_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_read_write_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_read_write_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_read_write_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_read_write_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_read_write_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_read_write_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_read_write_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_read_write_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_read_write_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_read_write_s1_agent_rf_source_data), // in.data
.in_valid (sram_read_write_s1_agent_rf_source_valid), // .valid
.in_ready (sram_read_write_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_read_write_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_read_write_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_read_write_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_read_write_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_read_write_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_read_write_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_read_write_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_cs_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_cs_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_cs_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_cs_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_cs_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_cs_s1_agent_m0_lock), // .lock
.m0_readdata (sram_cs_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_cs_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_cs_s1_agent_m0_read), // .read
.m0_waitrequest (sram_cs_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_cs_s1_agent_m0_writedata), // .writedata
.m0_write (sram_cs_s1_agent_m0_write), // .write
.rp_endofpacket (sram_cs_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_cs_s1_agent_rp_ready), // .ready
.rp_valid (sram_cs_s1_agent_rp_valid), // .valid
.rp_data (sram_cs_s1_agent_rp_data), // .data
.rp_startofpacket (sram_cs_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (sram_cs_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_cs_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_cs_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_cs_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_cs_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_cs_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_cs_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_cs_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_cs_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_cs_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_cs_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_cs_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_cs_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_cs_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_cs_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_cs_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_cs_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_cs_s1_agent_rf_source_data), // in.data
.in_valid (sram_cs_s1_agent_rf_source_valid), // .valid
.in_ready (sram_cs_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_cs_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_cs_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_cs_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_cs_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_cs_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_cs_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_cs_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_oe_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sram_oe_s1_agent_m0_address), // m0.address
.m0_burstcount (sram_oe_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_oe_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_oe_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_oe_s1_agent_m0_lock), // .lock
.m0_readdata (sram_oe_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_oe_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_oe_s1_agent_m0_read), // .read
.m0_waitrequest (sram_oe_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_oe_s1_agent_m0_writedata), // .writedata
.m0_write (sram_oe_s1_agent_m0_write), // .write
.rp_endofpacket (sram_oe_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_oe_s1_agent_rp_ready), // .ready
.rp_valid (sram_oe_s1_agent_rp_valid), // .valid
.rp_data (sram_oe_s1_agent_rp_data), // .data
.rp_startofpacket (sram_oe_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (sram_oe_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_oe_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_oe_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_oe_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_oe_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_oe_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_oe_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_oe_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_oe_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_oe_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_oe_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_oe_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sram_oe_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sram_oe_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_oe_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_oe_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_oe_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sram_oe_s1_agent_rf_source_data), // in.data
.in_valid (sram_oe_s1_agent_rf_source_valid), // .valid
.in_ready (sram_oe_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sram_oe_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_oe_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_oe_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_oe_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_oe_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_oe_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_oe_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_data_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_data_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_data_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_data_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_data_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_data_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_data_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_data_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_data_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_data_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_data_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_data_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_data_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_data_s1_agent_rp_ready), // .ready
.rp_valid (regfile_data_s1_agent_rp_valid), // .valid
.rp_data (regfile_data_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_data_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_010_src_ready), // cp.ready
.cp_valid (cmd_mux_010_src_valid), // .valid
.cp_data (cmd_mux_010_src_data), // .data
.cp_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_010_src_channel), // .channel
.rf_sink_ready (regfile_data_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_data_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_data_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_data_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_data_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_data_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_data_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_data_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_data_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_data_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_data_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_data_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_data_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_data_s1_agent_rf_source_data), // in.data
.in_valid (regfile_data_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_data_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_data_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_data_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_data_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_data_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_data_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_data_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_data_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_reg1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_reg1_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_reg1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_reg1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_reg1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_reg1_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_reg1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_reg1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_reg1_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_reg1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_reg1_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_reg1_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_reg1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_reg1_s1_agent_rp_ready), // .ready
.rp_valid (regfile_reg1_s1_agent_rp_valid), // .valid
.rp_data (regfile_reg1_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_reg1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_011_src_ready), // cp.ready
.cp_valid (cmd_mux_011_src_valid), // .valid
.cp_data (cmd_mux_011_src_data), // .data
.cp_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_011_src_channel), // .channel
.rf_sink_ready (regfile_reg1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_reg1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_reg1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_reg1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_reg1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_reg1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_reg1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_reg1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_reg1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_reg1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_reg1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_reg1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_reg1_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_reg1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_reg1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_reg1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_reg1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_reg1_s1_agent_rf_source_data), // in.data
.in_valid (regfile_reg1_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_reg1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_reg1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_reg1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_reg1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_reg1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_reg1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_reg1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_reg1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_reg2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_reg2_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_reg2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_reg2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_reg2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_reg2_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_reg2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_reg2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_reg2_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_reg2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_reg2_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_reg2_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_reg2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_reg2_s1_agent_rp_ready), // .ready
.rp_valid (regfile_reg2_s1_agent_rp_valid), // .valid
.rp_data (regfile_reg2_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_reg2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_012_src_ready), // cp.ready
.cp_valid (cmd_mux_012_src_valid), // .valid
.cp_data (cmd_mux_012_src_data), // .data
.cp_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_012_src_channel), // .channel
.rf_sink_ready (regfile_reg2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_reg2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_reg2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_reg2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_reg2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_reg2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_reg2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_reg2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_reg2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_reg2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_reg2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_reg2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_reg2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_reg2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_reg2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_reg2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_reg2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_reg2_s1_agent_rf_source_data), // in.data
.in_valid (regfile_reg2_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_reg2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_reg2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_reg2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_reg2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_reg2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_reg2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_reg2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_reg2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_r1sel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_r1sel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_r1sel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_r1sel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_r1sel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_r1sel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_r1sel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_r1sel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_r1sel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_r1sel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_r1sel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_r1sel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_r1sel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_r1sel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_r1sel_s1_agent_rp_valid), // .valid
.rp_data (regfile_r1sel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_r1sel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_013_src_ready), // cp.ready
.cp_valid (cmd_mux_013_src_valid), // .valid
.cp_data (cmd_mux_013_src_data), // .data
.cp_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_013_src_channel), // .channel
.rf_sink_ready (regfile_r1sel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_r1sel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_r1sel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_r1sel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_r1sel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_r1sel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_r1sel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_r1sel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_r1sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_r1sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_r1sel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_r1sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_r1sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_r1sel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_r1sel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_r1sel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_r1sel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_r1sel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_r1sel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_r1sel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_r1sel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_r1sel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_r1sel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_r1sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_r2sel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_r2sel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_r2sel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_r2sel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_r2sel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_r2sel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_r2sel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_r2sel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_r2sel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_r2sel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_r2sel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_r2sel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_r2sel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_r2sel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_r2sel_s1_agent_rp_valid), // .valid
.rp_data (regfile_r2sel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_r2sel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_014_src_ready), // cp.ready
.cp_valid (cmd_mux_014_src_valid), // .valid
.cp_data (cmd_mux_014_src_data), // .data
.cp_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_014_src_channel), // .channel
.rf_sink_ready (regfile_r2sel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_r2sel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_r2sel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_r2sel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_r2sel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_r2sel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_r2sel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_r2sel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_r2sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_r2sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_r2sel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_r2sel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_r2sel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_r2sel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_r2sel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_r2sel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_r2sel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_r2sel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_r2sel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_r2sel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_r2sel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_r2sel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_r2sel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_r2sel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_wsel_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_wsel_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_wsel_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_wsel_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_wsel_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_wsel_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_wsel_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_wsel_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_wsel_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_wsel_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_wsel_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_wsel_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_wsel_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_wsel_s1_agent_rp_ready), // .ready
.rp_valid (regfile_wsel_s1_agent_rp_valid), // .valid
.rp_data (regfile_wsel_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_wsel_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_015_src_ready), // cp.ready
.cp_valid (cmd_mux_015_src_valid), // .valid
.cp_data (cmd_mux_015_src_data), // .data
.cp_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_015_src_channel), // .channel
.rf_sink_ready (regfile_wsel_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_wsel_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_wsel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_wsel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_wsel_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_wsel_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_wsel_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_wsel_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_wsel_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_wsel_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_wsel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_wsel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_wsel_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_wsel_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_wsel_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_wsel_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_wsel_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_wsel_s1_agent_rf_source_data), // in.data
.in_valid (regfile_wsel_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_wsel_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_wsel_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_wsel_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_wsel_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_wsel_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_wsel_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_wsel_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_wsel_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) regfile_we_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (regfile_we_s1_agent_m0_address), // m0.address
.m0_burstcount (regfile_we_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (regfile_we_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (regfile_we_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (regfile_we_s1_agent_m0_lock), // .lock
.m0_readdata (regfile_we_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (regfile_we_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (regfile_we_s1_agent_m0_read), // .read
.m0_waitrequest (regfile_we_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (regfile_we_s1_agent_m0_writedata), // .writedata
.m0_write (regfile_we_s1_agent_m0_write), // .write
.rp_endofpacket (regfile_we_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (regfile_we_s1_agent_rp_ready), // .ready
.rp_valid (regfile_we_s1_agent_rp_valid), // .valid
.rp_data (regfile_we_s1_agent_rp_data), // .data
.rp_startofpacket (regfile_we_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_016_src_ready), // cp.ready
.cp_valid (cmd_mux_016_src_valid), // .valid
.cp_data (cmd_mux_016_src_data), // .data
.cp_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_016_src_channel), // .channel
.rf_sink_ready (regfile_we_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (regfile_we_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (regfile_we_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (regfile_we_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (regfile_we_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (regfile_we_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (regfile_we_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (regfile_we_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (regfile_we_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (regfile_we_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (regfile_we_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (regfile_we_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (regfile_we_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (regfile_we_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (regfile_we_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (regfile_we_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) regfile_we_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (regfile_we_s1_agent_rf_source_data), // in.data
.in_valid (regfile_we_s1_agent_rf_source_valid), // .valid
.in_ready (regfile_we_s1_agent_rf_source_ready), // .ready
.in_startofpacket (regfile_we_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (regfile_we_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (regfile_we_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (regfile_we_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (regfile_we_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (regfile_we_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (regfile_we_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_0_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_0_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_0_s1_agent_m0_lock), // .lock
.m0_readdata (hex_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_0_s1_agent_m0_read), // .read
.m0_waitrequest (hex_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_0_s1_agent_m0_writedata), // .writedata
.m0_write (hex_0_s1_agent_m0_write), // .write
.rp_endofpacket (hex_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_0_s1_agent_rp_ready), // .ready
.rp_valid (hex_0_s1_agent_rp_valid), // .valid
.rp_data (hex_0_s1_agent_rp_data), // .data
.rp_startofpacket (hex_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_017_src_ready), // cp.ready
.cp_valid (cmd_mux_017_src_valid), // .valid
.cp_data (cmd_mux_017_src_data), // .data
.cp_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_017_src_channel), // .channel
.rf_sink_ready (hex_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_0_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_0_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_0_s1_agent_rf_source_data), // in.data
.in_valid (hex_0_s1_agent_rf_source_valid), // .valid
.in_ready (hex_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_1_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_1_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_1_s1_agent_m0_lock), // .lock
.m0_readdata (hex_1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_1_s1_agent_m0_read), // .read
.m0_waitrequest (hex_1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_1_s1_agent_m0_writedata), // .writedata
.m0_write (hex_1_s1_agent_m0_write), // .write
.rp_endofpacket (hex_1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_1_s1_agent_rp_ready), // .ready
.rp_valid (hex_1_s1_agent_rp_valid), // .valid
.rp_data (hex_1_s1_agent_rp_data), // .data
.rp_startofpacket (hex_1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_018_src_ready), // cp.ready
.cp_valid (cmd_mux_018_src_valid), // .valid
.cp_data (cmd_mux_018_src_data), // .data
.cp_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_018_src_channel), // .channel
.rf_sink_ready (hex_1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_1_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_1_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_1_s1_agent_rf_source_data), // in.data
.in_valid (hex_1_s1_agent_rf_source_valid), // .valid
.in_ready (hex_1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_2_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_2_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_2_s1_agent_m0_lock), // .lock
.m0_readdata (hex_2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_2_s1_agent_m0_read), // .read
.m0_waitrequest (hex_2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_2_s1_agent_m0_writedata), // .writedata
.m0_write (hex_2_s1_agent_m0_write), // .write
.rp_endofpacket (hex_2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_2_s1_agent_rp_ready), // .ready
.rp_valid (hex_2_s1_agent_rp_valid), // .valid
.rp_data (hex_2_s1_agent_rp_data), // .data
.rp_startofpacket (hex_2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_019_src_ready), // cp.ready
.cp_valid (cmd_mux_019_src_valid), // .valid
.cp_data (cmd_mux_019_src_data), // .data
.cp_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_019_src_channel), // .channel
.rf_sink_ready (hex_2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_2_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_2_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_2_s1_agent_rf_source_data), // in.data
.in_valid (hex_2_s1_agent_rf_source_valid), // .valid
.in_ready (hex_2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_3_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_3_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_3_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_3_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_3_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_3_s1_agent_m0_lock), // .lock
.m0_readdata (hex_3_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_3_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_3_s1_agent_m0_read), // .read
.m0_waitrequest (hex_3_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_3_s1_agent_m0_writedata), // .writedata
.m0_write (hex_3_s1_agent_m0_write), // .write
.rp_endofpacket (hex_3_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_3_s1_agent_rp_ready), // .ready
.rp_valid (hex_3_s1_agent_rp_valid), // .valid
.rp_data (hex_3_s1_agent_rp_data), // .data
.rp_startofpacket (hex_3_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_020_src_ready), // cp.ready
.cp_valid (cmd_mux_020_src_valid), // .valid
.cp_data (cmd_mux_020_src_data), // .data
.cp_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_020_src_channel), // .channel
.rf_sink_ready (hex_3_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_3_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_3_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_3_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_3_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_3_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_3_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_3_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_3_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_3_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_3_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_3_s1_agent_rf_source_data), // in.data
.in_valid (hex_3_s1_agent_rf_source_valid), // .valid
.in_ready (hex_3_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_3_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_3_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_3_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_3_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_3_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_4_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_4_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_4_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_4_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_4_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_4_s1_agent_m0_lock), // .lock
.m0_readdata (hex_4_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_4_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_4_s1_agent_m0_read), // .read
.m0_waitrequest (hex_4_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_4_s1_agent_m0_writedata), // .writedata
.m0_write (hex_4_s1_agent_m0_write), // .write
.rp_endofpacket (hex_4_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_4_s1_agent_rp_ready), // .ready
.rp_valid (hex_4_s1_agent_rp_valid), // .valid
.rp_data (hex_4_s1_agent_rp_data), // .data
.rp_startofpacket (hex_4_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_021_src_ready), // cp.ready
.cp_valid (cmd_mux_021_src_valid), // .valid
.cp_data (cmd_mux_021_src_data), // .data
.cp_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_021_src_channel), // .channel
.rf_sink_ready (hex_4_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_4_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_4_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_4_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_4_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_4_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_4_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_4_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_4_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_4_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_4_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_4_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_4_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_4_s1_agent_rf_source_data), // in.data
.in_valid (hex_4_s1_agent_rf_source_valid), // .valid
.in_ready (hex_4_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_4_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_4_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_4_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_4_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_4_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) hex_5_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex_5_s1_agent_m0_address), // m0.address
.m0_burstcount (hex_5_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex_5_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex_5_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex_5_s1_agent_m0_lock), // .lock
.m0_readdata (hex_5_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex_5_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex_5_s1_agent_m0_read), // .read
.m0_waitrequest (hex_5_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex_5_s1_agent_m0_writedata), // .writedata
.m0_write (hex_5_s1_agent_m0_write), // .write
.rp_endofpacket (hex_5_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex_5_s1_agent_rp_ready), // .ready
.rp_valid (hex_5_s1_agent_rp_valid), // .valid
.rp_data (hex_5_s1_agent_rp_data), // .data
.rp_startofpacket (hex_5_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_022_src_ready), // cp.ready
.cp_valid (cmd_mux_022_src_valid), // .valid
.cp_data (cmd_mux_022_src_data), // .data
.cp_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_022_src_channel), // .channel
.rf_sink_ready (hex_5_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex_5_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex_5_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex_5_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex_5_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex_5_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex_5_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex_5_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (hex_5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (hex_5_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (hex_5_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (hex_5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex_5_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex_5_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex_5_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex_5_s1_agent_rf_source_data), // in.data
.in_valid (hex_5_s1_agent_rf_source_valid), // .valid
.in_ready (hex_5_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex_5_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex_5_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex_5_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex_5_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex_5_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex_5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex_5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_a_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_a_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_a_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_a_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_a_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_a_s1_agent_m0_lock), // .lock
.m0_readdata (alu_a_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_a_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_a_s1_agent_m0_read), // .read
.m0_waitrequest (alu_a_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_a_s1_agent_m0_writedata), // .writedata
.m0_write (alu_a_s1_agent_m0_write), // .write
.rp_endofpacket (alu_a_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_a_s1_agent_rp_ready), // .ready
.rp_valid (alu_a_s1_agent_rp_valid), // .valid
.rp_data (alu_a_s1_agent_rp_data), // .data
.rp_startofpacket (alu_a_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_023_src_ready), // cp.ready
.cp_valid (cmd_mux_023_src_valid), // .valid
.cp_data (cmd_mux_023_src_data), // .data
.cp_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_023_src_channel), // .channel
.rf_sink_ready (alu_a_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_a_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_a_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_a_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_a_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_a_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_a_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_a_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_a_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_a_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_a_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_a_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_a_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_a_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_a_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_a_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_a_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_a_s1_agent_rf_source_data), // in.data
.in_valid (alu_a_s1_agent_rf_source_valid), // .valid
.in_ready (alu_a_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_a_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_a_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_a_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_a_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_a_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_a_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_a_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_b_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_b_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_b_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_b_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_b_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_b_s1_agent_m0_lock), // .lock
.m0_readdata (alu_b_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_b_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_b_s1_agent_m0_read), // .read
.m0_waitrequest (alu_b_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_b_s1_agent_m0_writedata), // .writedata
.m0_write (alu_b_s1_agent_m0_write), // .write
.rp_endofpacket (alu_b_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_b_s1_agent_rp_ready), // .ready
.rp_valid (alu_b_s1_agent_rp_valid), // .valid
.rp_data (alu_b_s1_agent_rp_data), // .data
.rp_startofpacket (alu_b_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_024_src_ready), // cp.ready
.cp_valid (cmd_mux_024_src_valid), // .valid
.cp_data (cmd_mux_024_src_data), // .data
.cp_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_024_src_channel), // .channel
.rf_sink_ready (alu_b_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_b_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_b_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_b_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_b_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_b_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_b_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_b_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_b_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_b_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_b_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_b_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_b_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_b_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_b_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_b_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_b_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_b_s1_agent_rf_source_data), // in.data
.in_valid (alu_b_s1_agent_rf_source_valid), // .valid
.in_ready (alu_b_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_b_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_b_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_b_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_b_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_b_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_b_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_b_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_control_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_control_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_control_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_control_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_control_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_control_s1_agent_m0_lock), // .lock
.m0_readdata (alu_control_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_control_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_control_s1_agent_m0_read), // .read
.m0_waitrequest (alu_control_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_control_s1_agent_m0_writedata), // .writedata
.m0_write (alu_control_s1_agent_m0_write), // .write
.rp_endofpacket (alu_control_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_control_s1_agent_rp_ready), // .ready
.rp_valid (alu_control_s1_agent_rp_valid), // .valid
.rp_data (alu_control_s1_agent_rp_data), // .data
.rp_startofpacket (alu_control_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_025_src_ready), // cp.ready
.cp_valid (cmd_mux_025_src_valid), // .valid
.cp_data (cmd_mux_025_src_data), // .data
.cp_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_025_src_channel), // .channel
.rf_sink_ready (alu_control_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_control_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_control_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_control_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_control_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_control_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_control_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_control_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_control_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_control_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_control_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_control_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_control_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_control_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_control_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_control_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_control_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_control_s1_agent_rf_source_data), // in.data
.in_valid (alu_control_s1_agent_rf_source_valid), // .valid
.in_ready (alu_control_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_control_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_control_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_control_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_control_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_control_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_control_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_control_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_out_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_out_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_out_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_out_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_out_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_out_s1_agent_m0_lock), // .lock
.m0_readdata (alu_out_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_out_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_out_s1_agent_m0_read), // .read
.m0_waitrequest (alu_out_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_out_s1_agent_m0_writedata), // .writedata
.m0_write (alu_out_s1_agent_m0_write), // .write
.rp_endofpacket (alu_out_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_out_s1_agent_rp_ready), // .ready
.rp_valid (alu_out_s1_agent_rp_valid), // .valid
.rp_data (alu_out_s1_agent_rp_data), // .data
.rp_startofpacket (alu_out_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_026_src_ready), // cp.ready
.cp_valid (cmd_mux_026_src_valid), // .valid
.cp_data (cmd_mux_026_src_data), // .data
.cp_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_026_src_channel), // .channel
.rf_sink_ready (alu_out_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_out_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_out_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_out_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_out_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_out_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_out_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_out_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_out_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_out_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_out_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_out_s1_agent_rf_source_data), // in.data
.in_valid (alu_out_s1_agent_rf_source_valid), // .valid
.in_ready (alu_out_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_out_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_out_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_out_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_out_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_out_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_zero_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_zero_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_zero_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_zero_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_zero_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_zero_s1_agent_m0_lock), // .lock
.m0_readdata (alu_zero_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_zero_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_zero_s1_agent_m0_read), // .read
.m0_waitrequest (alu_zero_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_zero_s1_agent_m0_writedata), // .writedata
.m0_write (alu_zero_s1_agent_m0_write), // .write
.rp_endofpacket (alu_zero_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_zero_s1_agent_rp_ready), // .ready
.rp_valid (alu_zero_s1_agent_rp_valid), // .valid
.rp_data (alu_zero_s1_agent_rp_data), // .data
.rp_startofpacket (alu_zero_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_027_src_ready), // cp.ready
.cp_valid (cmd_mux_027_src_valid), // .valid
.cp_data (cmd_mux_027_src_data), // .data
.cp_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_027_src_channel), // .channel
.rf_sink_ready (alu_zero_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_zero_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_zero_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_zero_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_zero_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_zero_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_zero_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_zero_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_zero_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_zero_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_zero_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_zero_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_zero_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_zero_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_zero_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_zero_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_zero_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_zero_s1_agent_rf_source_data), // in.data
.in_valid (alu_zero_s1_agent_rf_source_valid), // .valid
.in_ready (alu_zero_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_zero_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_zero_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_zero_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_zero_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_zero_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_zero_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_zero_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_overflow_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_overflow_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_overflow_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_overflow_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_overflow_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_overflow_s1_agent_m0_lock), // .lock
.m0_readdata (alu_overflow_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_overflow_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_overflow_s1_agent_m0_read), // .read
.m0_waitrequest (alu_overflow_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_overflow_s1_agent_m0_writedata), // .writedata
.m0_write (alu_overflow_s1_agent_m0_write), // .write
.rp_endofpacket (alu_overflow_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_overflow_s1_agent_rp_ready), // .ready
.rp_valid (alu_overflow_s1_agent_rp_valid), // .valid
.rp_data (alu_overflow_s1_agent_rp_data), // .data
.rp_startofpacket (alu_overflow_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_028_src_ready), // cp.ready
.cp_valid (cmd_mux_028_src_valid), // .valid
.cp_data (cmd_mux_028_src_data), // .data
.cp_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_028_src_channel), // .channel
.rf_sink_ready (alu_overflow_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_overflow_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_overflow_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_overflow_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_overflow_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_overflow_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_overflow_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_overflow_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_overflow_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_overflow_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_overflow_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_overflow_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_overflow_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_overflow_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_overflow_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_overflow_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_overflow_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_overflow_s1_agent_rf_source_data), // in.data
.in_valid (alu_overflow_s1_agent_rf_source_valid), // .valid
.in_ready (alu_overflow_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_overflow_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_overflow_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_overflow_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_overflow_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_overflow_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_overflow_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_overflow_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_carry_out_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_carry_out_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_carry_out_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_carry_out_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_carry_out_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_carry_out_s1_agent_m0_lock), // .lock
.m0_readdata (alu_carry_out_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_carry_out_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_carry_out_s1_agent_m0_read), // .read
.m0_waitrequest (alu_carry_out_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_carry_out_s1_agent_m0_writedata), // .writedata
.m0_write (alu_carry_out_s1_agent_m0_write), // .write
.rp_endofpacket (alu_carry_out_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_carry_out_s1_agent_rp_ready), // .ready
.rp_valid (alu_carry_out_s1_agent_rp_valid), // .valid
.rp_data (alu_carry_out_s1_agent_rp_data), // .data
.rp_startofpacket (alu_carry_out_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_029_src_ready), // cp.ready
.cp_valid (cmd_mux_029_src_valid), // .valid
.cp_data (cmd_mux_029_src_data), // .data
.cp_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_029_src_channel), // .channel
.rf_sink_ready (alu_carry_out_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_carry_out_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_carry_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_carry_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_carry_out_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_carry_out_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_carry_out_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_carry_out_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_carry_out_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_carry_out_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_carry_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_carry_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_carry_out_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_carry_out_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_carry_out_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_carry_out_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_carry_out_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_carry_out_s1_agent_rf_source_data), // in.data
.in_valid (alu_carry_out_s1_agent_rf_source_valid), // .valid
.in_ready (alu_carry_out_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_carry_out_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_carry_out_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_carry_out_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_carry_out_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_carry_out_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_carry_out_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_carry_out_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) alu_negative_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (alu_negative_s1_agent_m0_address), // m0.address
.m0_burstcount (alu_negative_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (alu_negative_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (alu_negative_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (alu_negative_s1_agent_m0_lock), // .lock
.m0_readdata (alu_negative_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (alu_negative_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (alu_negative_s1_agent_m0_read), // .read
.m0_waitrequest (alu_negative_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (alu_negative_s1_agent_m0_writedata), // .writedata
.m0_write (alu_negative_s1_agent_m0_write), // .write
.rp_endofpacket (alu_negative_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (alu_negative_s1_agent_rp_ready), // .ready
.rp_valid (alu_negative_s1_agent_rp_valid), // .valid
.rp_data (alu_negative_s1_agent_rp_data), // .data
.rp_startofpacket (alu_negative_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_030_src_ready), // cp.ready
.cp_valid (cmd_mux_030_src_valid), // .valid
.cp_data (cmd_mux_030_src_data), // .data
.cp_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_030_src_channel), // .channel
.rf_sink_ready (alu_negative_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (alu_negative_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (alu_negative_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (alu_negative_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (alu_negative_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (alu_negative_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (alu_negative_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (alu_negative_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (alu_negative_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (alu_negative_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (alu_negative_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (alu_negative_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (alu_negative_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (alu_negative_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (alu_negative_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (alu_negative_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) alu_negative_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (alu_negative_s1_agent_rf_source_data), // in.data
.in_valid (alu_negative_s1_agent_rf_source_valid), // .valid
.in_ready (alu_negative_s1_agent_rf_source_ready), // .ready
.in_startofpacket (alu_negative_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (alu_negative_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (alu_negative_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (alu_negative_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (alu_negative_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (alu_negative_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (alu_negative_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (98),
.PKT_ORI_BURST_SIZE_L (96),
.PKT_RESPONSE_STATUS_H (95),
.PKT_RESPONSE_STATUS_L (94),
.PKT_BURST_SIZE_H (69),
.PKT_BURST_SIZE_L (67),
.PKT_TRANS_LOCK (59),
.PKT_BEGIN_BURST (74),
.PKT_PROTECTION_H (89),
.PKT_PROTECTION_L (87),
.PKT_BURSTWRAP_H (66),
.PKT_BURSTWRAP_L (64),
.PKT_BYTE_CNT_H (63),
.PKT_BYTE_CNT_L (61),
.PKT_ADDR_H (54),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (55),
.PKT_TRANS_POSTED (56),
.PKT_TRANS_WRITE (57),
.PKT_TRANS_READ (58),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (80),
.PKT_SRC_ID_L (76),
.PKT_DEST_ID_H (85),
.PKT_DEST_ID_L (81),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (32),
.ST_DATA_W (99),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) keys_s1_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (keys_s1_agent_m0_address), // m0.address
.m0_burstcount (keys_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (keys_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (keys_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (keys_s1_agent_m0_lock), // .lock
.m0_readdata (keys_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (keys_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (keys_s1_agent_m0_read), // .read
.m0_waitrequest (keys_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (keys_s1_agent_m0_writedata), // .writedata
.m0_write (keys_s1_agent_m0_write), // .write
.rp_endofpacket (keys_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (keys_s1_agent_rp_ready), // .ready
.rp_valid (keys_s1_agent_rp_valid), // .valid
.rp_data (keys_s1_agent_rp_data), // .data
.rp_startofpacket (keys_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_031_src_ready), // cp.ready
.cp_valid (cmd_mux_031_src_valid), // .valid
.cp_data (cmd_mux_031_src_data), // .data
.cp_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_031_src_channel), // .channel
.rf_sink_ready (keys_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (keys_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (keys_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (keys_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (keys_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (keys_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (keys_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (keys_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (keys_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (keys_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (keys_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (keys_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (keys_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (keys_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (100),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) keys_s1_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (keys_s1_agent_rf_source_data), // in.data
.in_valid (keys_s1_agent_rf_source_valid), // .valid
.in_ready (keys_s1_agent_rf_source_ready), // .ready
.in_startofpacket (keys_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (keys_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (keys_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (keys_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (keys_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (keys_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (keys_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
nios_system_mm_interconnect_0_router router (
.sink_ready (nios2_qsys_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_qsys_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_003 router_003 (
.sink_ready (nios2_qsys_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_qsys_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_003 router_004 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_005 (
.sink_ready (leds_s1_agent_rp_ready), // sink.ready
.sink_valid (leds_s1_agent_rp_valid), // .valid
.sink_data (leds_s1_agent_rp_data), // .data
.sink_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (leds_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_006 (
.sink_ready (switches_s1_agent_rp_ready), // sink.ready
.sink_valid (switches_s1_agent_rp_valid), // .valid
.sink_data (switches_s1_agent_rp_data), // .data
.sink_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switches_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_007 (
.sink_ready (sram_data_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_data_s1_agent_rp_valid), // .valid
.sink_data (sram_data_s1_agent_rp_data), // .data
.sink_startofpacket (sram_data_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_data_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_008 (
.sink_ready (sram_addr_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_addr_s1_agent_rp_valid), // .valid
.sink_data (sram_addr_s1_agent_rp_data), // .data
.sink_startofpacket (sram_addr_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_addr_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_009 (
.sink_ready (sram_read_write_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_read_write_s1_agent_rp_valid), // .valid
.sink_data (sram_read_write_s1_agent_rp_data), // .data
.sink_startofpacket (sram_read_write_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_read_write_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_010 (
.sink_ready (sram_cs_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_cs_s1_agent_rp_valid), // .valid
.sink_data (sram_cs_s1_agent_rp_data), // .data
.sink_startofpacket (sram_cs_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_cs_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_011 (
.sink_ready (sram_oe_s1_agent_rp_ready), // sink.ready
.sink_valid (sram_oe_s1_agent_rp_valid), // .valid
.sink_data (sram_oe_s1_agent_rp_data), // .data
.sink_startofpacket (sram_oe_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_oe_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_012 (
.sink_ready (regfile_data_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_data_s1_agent_rp_valid), // .valid
.sink_data (regfile_data_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_data_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_data_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_012_src_ready), // src.ready
.src_valid (router_012_src_valid), // .valid
.src_data (router_012_src_data), // .data
.src_channel (router_012_src_channel), // .channel
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_013 (
.sink_ready (regfile_reg1_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_reg1_s1_agent_rp_valid), // .valid
.sink_data (regfile_reg1_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_reg1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_reg1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_013_src_ready), // src.ready
.src_valid (router_013_src_valid), // .valid
.src_data (router_013_src_data), // .data
.src_channel (router_013_src_channel), // .channel
.src_startofpacket (router_013_src_startofpacket), // .startofpacket
.src_endofpacket (router_013_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_014 (
.sink_ready (regfile_reg2_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_reg2_s1_agent_rp_valid), // .valid
.sink_data (regfile_reg2_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_reg2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_reg2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_014_src_ready), // src.ready
.src_valid (router_014_src_valid), // .valid
.src_data (router_014_src_data), // .data
.src_channel (router_014_src_channel), // .channel
.src_startofpacket (router_014_src_startofpacket), // .startofpacket
.src_endofpacket (router_014_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_015 (
.sink_ready (regfile_r1sel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_r1sel_s1_agent_rp_valid), // .valid
.sink_data (regfile_r1sel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_r1sel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_r1sel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_015_src_ready), // src.ready
.src_valid (router_015_src_valid), // .valid
.src_data (router_015_src_data), // .data
.src_channel (router_015_src_channel), // .channel
.src_startofpacket (router_015_src_startofpacket), // .startofpacket
.src_endofpacket (router_015_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_016 (
.sink_ready (regfile_r2sel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_r2sel_s1_agent_rp_valid), // .valid
.sink_data (regfile_r2sel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_r2sel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_r2sel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_016_src_ready), // src.ready
.src_valid (router_016_src_valid), // .valid
.src_data (router_016_src_data), // .data
.src_channel (router_016_src_channel), // .channel
.src_startofpacket (router_016_src_startofpacket), // .startofpacket
.src_endofpacket (router_016_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_017 (
.sink_ready (regfile_wsel_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_wsel_s1_agent_rp_valid), // .valid
.sink_data (regfile_wsel_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_wsel_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_wsel_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_017_src_ready), // src.ready
.src_valid (router_017_src_valid), // .valid
.src_data (router_017_src_data), // .data
.src_channel (router_017_src_channel), // .channel
.src_startofpacket (router_017_src_startofpacket), // .startofpacket
.src_endofpacket (router_017_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_018 (
.sink_ready (regfile_we_s1_agent_rp_ready), // sink.ready
.sink_valid (regfile_we_s1_agent_rp_valid), // .valid
.sink_data (regfile_we_s1_agent_rp_data), // .data
.sink_startofpacket (regfile_we_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (regfile_we_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_018_src_ready), // src.ready
.src_valid (router_018_src_valid), // .valid
.src_data (router_018_src_data), // .data
.src_channel (router_018_src_channel), // .channel
.src_startofpacket (router_018_src_startofpacket), // .startofpacket
.src_endofpacket (router_018_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_019 (
.sink_ready (hex_0_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_0_s1_agent_rp_valid), // .valid
.sink_data (hex_0_s1_agent_rp_data), // .data
.sink_startofpacket (hex_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_019_src_ready), // src.ready
.src_valid (router_019_src_valid), // .valid
.src_data (router_019_src_data), // .data
.src_channel (router_019_src_channel), // .channel
.src_startofpacket (router_019_src_startofpacket), // .startofpacket
.src_endofpacket (router_019_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_020 (
.sink_ready (hex_1_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_1_s1_agent_rp_valid), // .valid
.sink_data (hex_1_s1_agent_rp_data), // .data
.sink_startofpacket (hex_1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_1_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_020_src_ready), // src.ready
.src_valid (router_020_src_valid), // .valid
.src_data (router_020_src_data), // .data
.src_channel (router_020_src_channel), // .channel
.src_startofpacket (router_020_src_startofpacket), // .startofpacket
.src_endofpacket (router_020_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_021 (
.sink_ready (hex_2_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_2_s1_agent_rp_valid), // .valid
.sink_data (hex_2_s1_agent_rp_data), // .data
.sink_startofpacket (hex_2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_2_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_021_src_ready), // src.ready
.src_valid (router_021_src_valid), // .valid
.src_data (router_021_src_data), // .data
.src_channel (router_021_src_channel), // .channel
.src_startofpacket (router_021_src_startofpacket), // .startofpacket
.src_endofpacket (router_021_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_022 (
.sink_ready (hex_3_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_3_s1_agent_rp_valid), // .valid
.sink_data (hex_3_s1_agent_rp_data), // .data
.sink_startofpacket (hex_3_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_3_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_022_src_ready), // src.ready
.src_valid (router_022_src_valid), // .valid
.src_data (router_022_src_data), // .data
.src_channel (router_022_src_channel), // .channel
.src_startofpacket (router_022_src_startofpacket), // .startofpacket
.src_endofpacket (router_022_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_023 (
.sink_ready (hex_4_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_4_s1_agent_rp_valid), // .valid
.sink_data (hex_4_s1_agent_rp_data), // .data
.sink_startofpacket (hex_4_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_4_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_023_src_ready), // src.ready
.src_valid (router_023_src_valid), // .valid
.src_data (router_023_src_data), // .data
.src_channel (router_023_src_channel), // .channel
.src_startofpacket (router_023_src_startofpacket), // .startofpacket
.src_endofpacket (router_023_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_024 (
.sink_ready (hex_5_s1_agent_rp_ready), // sink.ready
.sink_valid (hex_5_s1_agent_rp_valid), // .valid
.sink_data (hex_5_s1_agent_rp_data), // .data
.sink_startofpacket (hex_5_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex_5_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_024_src_ready), // src.ready
.src_valid (router_024_src_valid), // .valid
.src_data (router_024_src_data), // .data
.src_channel (router_024_src_channel), // .channel
.src_startofpacket (router_024_src_startofpacket), // .startofpacket
.src_endofpacket (router_024_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_025 (
.sink_ready (alu_a_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_a_s1_agent_rp_valid), // .valid
.sink_data (alu_a_s1_agent_rp_data), // .data
.sink_startofpacket (alu_a_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_a_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_025_src_ready), // src.ready
.src_valid (router_025_src_valid), // .valid
.src_data (router_025_src_data), // .data
.src_channel (router_025_src_channel), // .channel
.src_startofpacket (router_025_src_startofpacket), // .startofpacket
.src_endofpacket (router_025_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_026 (
.sink_ready (alu_b_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_b_s1_agent_rp_valid), // .valid
.sink_data (alu_b_s1_agent_rp_data), // .data
.sink_startofpacket (alu_b_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_b_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_026_src_ready), // src.ready
.src_valid (router_026_src_valid), // .valid
.src_data (router_026_src_data), // .data
.src_channel (router_026_src_channel), // .channel
.src_startofpacket (router_026_src_startofpacket), // .startofpacket
.src_endofpacket (router_026_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_027 (
.sink_ready (alu_control_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_control_s1_agent_rp_valid), // .valid
.sink_data (alu_control_s1_agent_rp_data), // .data
.sink_startofpacket (alu_control_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_control_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_027_src_ready), // src.ready
.src_valid (router_027_src_valid), // .valid
.src_data (router_027_src_data), // .data
.src_channel (router_027_src_channel), // .channel
.src_startofpacket (router_027_src_startofpacket), // .startofpacket
.src_endofpacket (router_027_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_028 (
.sink_ready (alu_out_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_out_s1_agent_rp_valid), // .valid
.sink_data (alu_out_s1_agent_rp_data), // .data
.sink_startofpacket (alu_out_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_out_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_028_src_ready), // src.ready
.src_valid (router_028_src_valid), // .valid
.src_data (router_028_src_data), // .data
.src_channel (router_028_src_channel), // .channel
.src_startofpacket (router_028_src_startofpacket), // .startofpacket
.src_endofpacket (router_028_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_029 (
.sink_ready (alu_zero_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_zero_s1_agent_rp_valid), // .valid
.sink_data (alu_zero_s1_agent_rp_data), // .data
.sink_startofpacket (alu_zero_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_zero_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_029_src_ready), // src.ready
.src_valid (router_029_src_valid), // .valid
.src_data (router_029_src_data), // .data
.src_channel (router_029_src_channel), // .channel
.src_startofpacket (router_029_src_startofpacket), // .startofpacket
.src_endofpacket (router_029_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_030 (
.sink_ready (alu_overflow_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_overflow_s1_agent_rp_valid), // .valid
.sink_data (alu_overflow_s1_agent_rp_data), // .data
.sink_startofpacket (alu_overflow_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_overflow_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_030_src_ready), // src.ready
.src_valid (router_030_src_valid), // .valid
.src_data (router_030_src_data), // .data
.src_channel (router_030_src_channel), // .channel
.src_startofpacket (router_030_src_startofpacket), // .startofpacket
.src_endofpacket (router_030_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_031 (
.sink_ready (alu_carry_out_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_carry_out_s1_agent_rp_valid), // .valid
.sink_data (alu_carry_out_s1_agent_rp_data), // .data
.sink_startofpacket (alu_carry_out_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_carry_out_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_031_src_ready), // src.ready
.src_valid (router_031_src_valid), // .valid
.src_data (router_031_src_data), // .data
.src_channel (router_031_src_channel), // .channel
.src_startofpacket (router_031_src_startofpacket), // .startofpacket
.src_endofpacket (router_031_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_032 (
.sink_ready (alu_negative_s1_agent_rp_ready), // sink.ready
.sink_valid (alu_negative_s1_agent_rp_valid), // .valid
.sink_data (alu_negative_s1_agent_rp_data), // .data
.sink_startofpacket (alu_negative_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (alu_negative_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_032_src_ready), // src.ready
.src_valid (router_032_src_valid), // .valid
.src_data (router_032_src_data), // .data
.src_channel (router_032_src_channel), // .channel
.src_startofpacket (router_032_src_startofpacket), // .startofpacket
.src_endofpacket (router_032_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_router_002 router_033 (
.sink_ready (keys_s1_agent_rp_ready), // sink.ready
.sink_valid (keys_s1_agent_rp_valid), // .valid
.sink_data (keys_s1_agent_rp_data), // .data
.sink_startofpacket (keys_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (keys_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_033_src_ready), // src.ready
.src_valid (router_033_src_valid), // .valid
.src_data (router_033_src_data), // .data
.src_channel (router_033_src_channel), // .channel
.src_startofpacket (router_033_src_startofpacket), // .startofpacket
.src_endofpacket (router_033_src_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_src8_ready), // src8.ready
.src8_valid (cmd_demux_src8_valid), // .valid
.src8_data (cmd_demux_src8_data), // .data
.src8_channel (cmd_demux_src8_channel), // .channel
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_src9_ready), // src9.ready
.src9_valid (cmd_demux_src9_valid), // .valid
.src9_data (cmd_demux_src9_data), // .data
.src9_channel (cmd_demux_src9_channel), // .channel
.src9_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_src10_ready), // src10.ready
.src10_valid (cmd_demux_src10_valid), // .valid
.src10_data (cmd_demux_src10_data), // .data
.src10_channel (cmd_demux_src10_channel), // .channel
.src10_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_src10_endofpacket), // .endofpacket
.src11_ready (cmd_demux_src11_ready), // src11.ready
.src11_valid (cmd_demux_src11_valid), // .valid
.src11_data (cmd_demux_src11_data), // .data
.src11_channel (cmd_demux_src11_channel), // .channel
.src11_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
.src11_endofpacket (cmd_demux_src11_endofpacket), // .endofpacket
.src12_ready (cmd_demux_src12_ready), // src12.ready
.src12_valid (cmd_demux_src12_valid), // .valid
.src12_data (cmd_demux_src12_data), // .data
.src12_channel (cmd_demux_src12_channel), // .channel
.src12_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
.src12_endofpacket (cmd_demux_src12_endofpacket), // .endofpacket
.src13_ready (cmd_demux_src13_ready), // src13.ready
.src13_valid (cmd_demux_src13_valid), // .valid
.src13_data (cmd_demux_src13_data), // .data
.src13_channel (cmd_demux_src13_channel), // .channel
.src13_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
.src13_endofpacket (cmd_demux_src13_endofpacket), // .endofpacket
.src14_ready (cmd_demux_src14_ready), // src14.ready
.src14_valid (cmd_demux_src14_valid), // .valid
.src14_data (cmd_demux_src14_data), // .data
.src14_channel (cmd_demux_src14_channel), // .channel
.src14_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
.src14_endofpacket (cmd_demux_src14_endofpacket), // .endofpacket
.src15_ready (cmd_demux_src15_ready), // src15.ready
.src15_valid (cmd_demux_src15_valid), // .valid
.src15_data (cmd_demux_src15_data), // .data
.src15_channel (cmd_demux_src15_channel), // .channel
.src15_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
.src15_endofpacket (cmd_demux_src15_endofpacket), // .endofpacket
.src16_ready (cmd_demux_src16_ready), // src16.ready
.src16_valid (cmd_demux_src16_valid), // .valid
.src16_data (cmd_demux_src16_data), // .data
.src16_channel (cmd_demux_src16_channel), // .channel
.src16_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
.src16_endofpacket (cmd_demux_src16_endofpacket), // .endofpacket
.src17_ready (cmd_demux_src17_ready), // src17.ready
.src17_valid (cmd_demux_src17_valid), // .valid
.src17_data (cmd_demux_src17_data), // .data
.src17_channel (cmd_demux_src17_channel), // .channel
.src17_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
.src17_endofpacket (cmd_demux_src17_endofpacket), // .endofpacket
.src18_ready (cmd_demux_src18_ready), // src18.ready
.src18_valid (cmd_demux_src18_valid), // .valid
.src18_data (cmd_demux_src18_data), // .data
.src18_channel (cmd_demux_src18_channel), // .channel
.src18_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
.src18_endofpacket (cmd_demux_src18_endofpacket), // .endofpacket
.src19_ready (cmd_demux_src19_ready), // src19.ready
.src19_valid (cmd_demux_src19_valid), // .valid
.src19_data (cmd_demux_src19_data), // .data
.src19_channel (cmd_demux_src19_channel), // .channel
.src19_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
.src19_endofpacket (cmd_demux_src19_endofpacket), // .endofpacket
.src20_ready (cmd_demux_src20_ready), // src20.ready
.src20_valid (cmd_demux_src20_valid), // .valid
.src20_data (cmd_demux_src20_data), // .data
.src20_channel (cmd_demux_src20_channel), // .channel
.src20_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
.src20_endofpacket (cmd_demux_src20_endofpacket), // .endofpacket
.src21_ready (cmd_demux_src21_ready), // src21.ready
.src21_valid (cmd_demux_src21_valid), // .valid
.src21_data (cmd_demux_src21_data), // .data
.src21_channel (cmd_demux_src21_channel), // .channel
.src21_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
.src21_endofpacket (cmd_demux_src21_endofpacket), // .endofpacket
.src22_ready (cmd_demux_src22_ready), // src22.ready
.src22_valid (cmd_demux_src22_valid), // .valid
.src22_data (cmd_demux_src22_data), // .data
.src22_channel (cmd_demux_src22_channel), // .channel
.src22_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
.src22_endofpacket (cmd_demux_src22_endofpacket), // .endofpacket
.src23_ready (cmd_demux_src23_ready), // src23.ready
.src23_valid (cmd_demux_src23_valid), // .valid
.src23_data (cmd_demux_src23_data), // .data
.src23_channel (cmd_demux_src23_channel), // .channel
.src23_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
.src23_endofpacket (cmd_demux_src23_endofpacket), // .endofpacket
.src24_ready (cmd_demux_src24_ready), // src24.ready
.src24_valid (cmd_demux_src24_valid), // .valid
.src24_data (cmd_demux_src24_data), // .data
.src24_channel (cmd_demux_src24_channel), // .channel
.src24_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
.src24_endofpacket (cmd_demux_src24_endofpacket), // .endofpacket
.src25_ready (cmd_demux_src25_ready), // src25.ready
.src25_valid (cmd_demux_src25_valid), // .valid
.src25_data (cmd_demux_src25_data), // .data
.src25_channel (cmd_demux_src25_channel), // .channel
.src25_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
.src25_endofpacket (cmd_demux_src25_endofpacket), // .endofpacket
.src26_ready (cmd_demux_src26_ready), // src26.ready
.src26_valid (cmd_demux_src26_valid), // .valid
.src26_data (cmd_demux_src26_data), // .data
.src26_channel (cmd_demux_src26_channel), // .channel
.src26_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
.src26_endofpacket (cmd_demux_src26_endofpacket), // .endofpacket
.src27_ready (cmd_demux_src27_ready), // src27.ready
.src27_valid (cmd_demux_src27_valid), // .valid
.src27_data (cmd_demux_src27_data), // .data
.src27_channel (cmd_demux_src27_channel), // .channel
.src27_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
.src27_endofpacket (cmd_demux_src27_endofpacket), // .endofpacket
.src28_ready (cmd_demux_src28_ready), // src28.ready
.src28_valid (cmd_demux_src28_valid), // .valid
.src28_data (cmd_demux_src28_data), // .data
.src28_channel (cmd_demux_src28_channel), // .channel
.src28_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
.src28_endofpacket (cmd_demux_src28_endofpacket), // .endofpacket
.src29_ready (cmd_demux_src29_ready), // src29.ready
.src29_valid (cmd_demux_src29_valid), // .valid
.src29_data (cmd_demux_src29_data), // .data
.src29_channel (cmd_demux_src29_channel), // .channel
.src29_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
.src29_endofpacket (cmd_demux_src29_endofpacket), // .endofpacket
.src30_ready (cmd_demux_src30_ready), // src30.ready
.src30_valid (cmd_demux_src30_valid), // .valid
.src30_data (cmd_demux_src30_data), // .data
.src30_channel (cmd_demux_src30_channel), // .channel
.src30_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
.src30_endofpacket (cmd_demux_src30_endofpacket), // .endofpacket
.src31_ready (cmd_demux_src31_ready), // src31.ready
.src31_valid (cmd_demux_src31_valid), // .valid
.src31_data (cmd_demux_src31_data), // .data
.src31_channel (cmd_demux_src31_channel), // .channel
.src31_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
.src31_endofpacket (cmd_demux_src31_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_src8_valid), // .valid
.sink0_channel (cmd_demux_src8_channel), // .channel
.sink0_data (cmd_demux_src8_data), // .data
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src8_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src9_ready), // sink0.ready
.sink0_valid (cmd_demux_src9_valid), // .valid
.sink0_channel (cmd_demux_src9_channel), // .channel
.sink0_data (cmd_demux_src9_data), // .data
.sink0_startofpacket (cmd_demux_src9_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src9_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_010_src_ready), // src.ready
.src_valid (cmd_mux_010_src_valid), // .valid
.src_data (cmd_mux_010_src_data), // .data
.src_channel (cmd_mux_010_src_channel), // .channel
.src_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src10_ready), // sink0.ready
.sink0_valid (cmd_demux_src10_valid), // .valid
.sink0_channel (cmd_demux_src10_channel), // .channel
.sink0_data (cmd_demux_src10_data), // .data
.sink0_startofpacket (cmd_demux_src10_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src10_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_011 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_011_src_ready), // src.ready
.src_valid (cmd_mux_011_src_valid), // .valid
.src_data (cmd_mux_011_src_data), // .data
.src_channel (cmd_mux_011_src_channel), // .channel
.src_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src11_ready), // sink0.ready
.sink0_valid (cmd_demux_src11_valid), // .valid
.sink0_channel (cmd_demux_src11_channel), // .channel
.sink0_data (cmd_demux_src11_data), // .data
.sink0_startofpacket (cmd_demux_src11_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src11_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_012 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_012_src_ready), // src.ready
.src_valid (cmd_mux_012_src_valid), // .valid
.src_data (cmd_mux_012_src_data), // .data
.src_channel (cmd_mux_012_src_channel), // .channel
.src_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src12_ready), // sink0.ready
.sink0_valid (cmd_demux_src12_valid), // .valid
.sink0_channel (cmd_demux_src12_channel), // .channel
.sink0_data (cmd_demux_src12_data), // .data
.sink0_startofpacket (cmd_demux_src12_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src12_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_013 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_013_src_ready), // src.ready
.src_valid (cmd_mux_013_src_valid), // .valid
.src_data (cmd_mux_013_src_data), // .data
.src_channel (cmd_mux_013_src_channel), // .channel
.src_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src13_ready), // sink0.ready
.sink0_valid (cmd_demux_src13_valid), // .valid
.sink0_channel (cmd_demux_src13_channel), // .channel
.sink0_data (cmd_demux_src13_data), // .data
.sink0_startofpacket (cmd_demux_src13_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src13_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_014 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_014_src_ready), // src.ready
.src_valid (cmd_mux_014_src_valid), // .valid
.src_data (cmd_mux_014_src_data), // .data
.src_channel (cmd_mux_014_src_channel), // .channel
.src_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src14_ready), // sink0.ready
.sink0_valid (cmd_demux_src14_valid), // .valid
.sink0_channel (cmd_demux_src14_channel), // .channel
.sink0_data (cmd_demux_src14_data), // .data
.sink0_startofpacket (cmd_demux_src14_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src14_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_015 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_015_src_ready), // src.ready
.src_valid (cmd_mux_015_src_valid), // .valid
.src_data (cmd_mux_015_src_data), // .data
.src_channel (cmd_mux_015_src_channel), // .channel
.src_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src15_ready), // sink0.ready
.sink0_valid (cmd_demux_src15_valid), // .valid
.sink0_channel (cmd_demux_src15_channel), // .channel
.sink0_data (cmd_demux_src15_data), // .data
.sink0_startofpacket (cmd_demux_src15_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src15_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_016 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_016_src_ready), // src.ready
.src_valid (cmd_mux_016_src_valid), // .valid
.src_data (cmd_mux_016_src_data), // .data
.src_channel (cmd_mux_016_src_channel), // .channel
.src_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src16_ready), // sink0.ready
.sink0_valid (cmd_demux_src16_valid), // .valid
.sink0_channel (cmd_demux_src16_channel), // .channel
.sink0_data (cmd_demux_src16_data), // .data
.sink0_startofpacket (cmd_demux_src16_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src16_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_017 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_017_src_ready), // src.ready
.src_valid (cmd_mux_017_src_valid), // .valid
.src_data (cmd_mux_017_src_data), // .data
.src_channel (cmd_mux_017_src_channel), // .channel
.src_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src17_ready), // sink0.ready
.sink0_valid (cmd_demux_src17_valid), // .valid
.sink0_channel (cmd_demux_src17_channel), // .channel
.sink0_data (cmd_demux_src17_data), // .data
.sink0_startofpacket (cmd_demux_src17_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src17_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_018 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_018_src_ready), // src.ready
.src_valid (cmd_mux_018_src_valid), // .valid
.src_data (cmd_mux_018_src_data), // .data
.src_channel (cmd_mux_018_src_channel), // .channel
.src_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src18_ready), // sink0.ready
.sink0_valid (cmd_demux_src18_valid), // .valid
.sink0_channel (cmd_demux_src18_channel), // .channel
.sink0_data (cmd_demux_src18_data), // .data
.sink0_startofpacket (cmd_demux_src18_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src18_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_019 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_019_src_ready), // src.ready
.src_valid (cmd_mux_019_src_valid), // .valid
.src_data (cmd_mux_019_src_data), // .data
.src_channel (cmd_mux_019_src_channel), // .channel
.src_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src19_ready), // sink0.ready
.sink0_valid (cmd_demux_src19_valid), // .valid
.sink0_channel (cmd_demux_src19_channel), // .channel
.sink0_data (cmd_demux_src19_data), // .data
.sink0_startofpacket (cmd_demux_src19_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src19_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_020 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_020_src_ready), // src.ready
.src_valid (cmd_mux_020_src_valid), // .valid
.src_data (cmd_mux_020_src_data), // .data
.src_channel (cmd_mux_020_src_channel), // .channel
.src_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src20_ready), // sink0.ready
.sink0_valid (cmd_demux_src20_valid), // .valid
.sink0_channel (cmd_demux_src20_channel), // .channel
.sink0_data (cmd_demux_src20_data), // .data
.sink0_startofpacket (cmd_demux_src20_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src20_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_021 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_021_src_ready), // src.ready
.src_valid (cmd_mux_021_src_valid), // .valid
.src_data (cmd_mux_021_src_data), // .data
.src_channel (cmd_mux_021_src_channel), // .channel
.src_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src21_ready), // sink0.ready
.sink0_valid (cmd_demux_src21_valid), // .valid
.sink0_channel (cmd_demux_src21_channel), // .channel
.sink0_data (cmd_demux_src21_data), // .data
.sink0_startofpacket (cmd_demux_src21_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src21_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_022 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_022_src_ready), // src.ready
.src_valid (cmd_mux_022_src_valid), // .valid
.src_data (cmd_mux_022_src_data), // .data
.src_channel (cmd_mux_022_src_channel), // .channel
.src_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src22_ready), // sink0.ready
.sink0_valid (cmd_demux_src22_valid), // .valid
.sink0_channel (cmd_demux_src22_channel), // .channel
.sink0_data (cmd_demux_src22_data), // .data
.sink0_startofpacket (cmd_demux_src22_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src22_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_023 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_023_src_ready), // src.ready
.src_valid (cmd_mux_023_src_valid), // .valid
.src_data (cmd_mux_023_src_data), // .data
.src_channel (cmd_mux_023_src_channel), // .channel
.src_startofpacket (cmd_mux_023_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_023_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src23_ready), // sink0.ready
.sink0_valid (cmd_demux_src23_valid), // .valid
.sink0_channel (cmd_demux_src23_channel), // .channel
.sink0_data (cmd_demux_src23_data), // .data
.sink0_startofpacket (cmd_demux_src23_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src23_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_024 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_024_src_ready), // src.ready
.src_valid (cmd_mux_024_src_valid), // .valid
.src_data (cmd_mux_024_src_data), // .data
.src_channel (cmd_mux_024_src_channel), // .channel
.src_startofpacket (cmd_mux_024_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_024_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src24_ready), // sink0.ready
.sink0_valid (cmd_demux_src24_valid), // .valid
.sink0_channel (cmd_demux_src24_channel), // .channel
.sink0_data (cmd_demux_src24_data), // .data
.sink0_startofpacket (cmd_demux_src24_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src24_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_025 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_025_src_ready), // src.ready
.src_valid (cmd_mux_025_src_valid), // .valid
.src_data (cmd_mux_025_src_data), // .data
.src_channel (cmd_mux_025_src_channel), // .channel
.src_startofpacket (cmd_mux_025_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_025_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src25_ready), // sink0.ready
.sink0_valid (cmd_demux_src25_valid), // .valid
.sink0_channel (cmd_demux_src25_channel), // .channel
.sink0_data (cmd_demux_src25_data), // .data
.sink0_startofpacket (cmd_demux_src25_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src25_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_026 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_026_src_ready), // src.ready
.src_valid (cmd_mux_026_src_valid), // .valid
.src_data (cmd_mux_026_src_data), // .data
.src_channel (cmd_mux_026_src_channel), // .channel
.src_startofpacket (cmd_mux_026_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_026_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src26_ready), // sink0.ready
.sink0_valid (cmd_demux_src26_valid), // .valid
.sink0_channel (cmd_demux_src26_channel), // .channel
.sink0_data (cmd_demux_src26_data), // .data
.sink0_startofpacket (cmd_demux_src26_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src26_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_027 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_027_src_ready), // src.ready
.src_valid (cmd_mux_027_src_valid), // .valid
.src_data (cmd_mux_027_src_data), // .data
.src_channel (cmd_mux_027_src_channel), // .channel
.src_startofpacket (cmd_mux_027_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_027_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src27_ready), // sink0.ready
.sink0_valid (cmd_demux_src27_valid), // .valid
.sink0_channel (cmd_demux_src27_channel), // .channel
.sink0_data (cmd_demux_src27_data), // .data
.sink0_startofpacket (cmd_demux_src27_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src27_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_028 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_028_src_ready), // src.ready
.src_valid (cmd_mux_028_src_valid), // .valid
.src_data (cmd_mux_028_src_data), // .data
.src_channel (cmd_mux_028_src_channel), // .channel
.src_startofpacket (cmd_mux_028_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_028_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src28_ready), // sink0.ready
.sink0_valid (cmd_demux_src28_valid), // .valid
.sink0_channel (cmd_demux_src28_channel), // .channel
.sink0_data (cmd_demux_src28_data), // .data
.sink0_startofpacket (cmd_demux_src28_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src28_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_029 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_029_src_ready), // src.ready
.src_valid (cmd_mux_029_src_valid), // .valid
.src_data (cmd_mux_029_src_data), // .data
.src_channel (cmd_mux_029_src_channel), // .channel
.src_startofpacket (cmd_mux_029_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_029_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src29_ready), // sink0.ready
.sink0_valid (cmd_demux_src29_valid), // .valid
.sink0_channel (cmd_demux_src29_channel), // .channel
.sink0_data (cmd_demux_src29_data), // .data
.sink0_startofpacket (cmd_demux_src29_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src29_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_030 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_030_src_ready), // src.ready
.src_valid (cmd_mux_030_src_valid), // .valid
.src_data (cmd_mux_030_src_data), // .data
.src_channel (cmd_mux_030_src_channel), // .channel
.src_startofpacket (cmd_mux_030_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_030_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src30_ready), // sink0.ready
.sink0_valid (cmd_demux_src30_valid), // .valid
.sink0_channel (cmd_demux_src30_channel), // .channel
.sink0_data (cmd_demux_src30_data), // .data
.sink0_startofpacket (cmd_demux_src30_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src30_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_mux cmd_mux_031 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_031_src_ready), // src.ready
.src_valid (cmd_mux_031_src_valid), // .valid
.src_data (cmd_mux_031_src_data), // .data
.src_channel (cmd_mux_031_src_channel), // .channel
.src_startofpacket (cmd_mux_031_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_031_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src31_ready), // sink0.ready
.sink0_valid (cmd_demux_src31_valid), // .valid
.sink0_channel (cmd_demux_src31_channel), // .channel
.sink0_data (cmd_demux_src31_data), // .data
.sink0_startofpacket (cmd_demux_src31_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src31_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 rsp_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_cmd_demux_001 rsp_demux_002 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_005 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_007 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_009 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_010 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_012_src_ready), // sink.ready
.sink_channel (router_012_src_channel), // .channel
.sink_data (router_012_src_data), // .data
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
.sink_valid (router_012_src_valid), // .valid
.src0_ready (rsp_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_demux_010_src0_valid), // .valid
.src0_data (rsp_demux_010_src0_data), // .data
.src0_channel (rsp_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_010_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_011 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_013_src_ready), // sink.ready
.sink_channel (router_013_src_channel), // .channel
.sink_data (router_013_src_data), // .data
.sink_startofpacket (router_013_src_startofpacket), // .startofpacket
.sink_endofpacket (router_013_src_endofpacket), // .endofpacket
.sink_valid (router_013_src_valid), // .valid
.src0_ready (rsp_demux_011_src0_ready), // src0.ready
.src0_valid (rsp_demux_011_src0_valid), // .valid
.src0_data (rsp_demux_011_src0_data), // .data
.src0_channel (rsp_demux_011_src0_channel), // .channel
.src0_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_011_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_012 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_014_src_ready), // sink.ready
.sink_channel (router_014_src_channel), // .channel
.sink_data (router_014_src_data), // .data
.sink_startofpacket (router_014_src_startofpacket), // .startofpacket
.sink_endofpacket (router_014_src_endofpacket), // .endofpacket
.sink_valid (router_014_src_valid), // .valid
.src0_ready (rsp_demux_012_src0_ready), // src0.ready
.src0_valid (rsp_demux_012_src0_valid), // .valid
.src0_data (rsp_demux_012_src0_data), // .data
.src0_channel (rsp_demux_012_src0_channel), // .channel
.src0_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_012_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_013 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_015_src_ready), // sink.ready
.sink_channel (router_015_src_channel), // .channel
.sink_data (router_015_src_data), // .data
.sink_startofpacket (router_015_src_startofpacket), // .startofpacket
.sink_endofpacket (router_015_src_endofpacket), // .endofpacket
.sink_valid (router_015_src_valid), // .valid
.src0_ready (rsp_demux_013_src0_ready), // src0.ready
.src0_valid (rsp_demux_013_src0_valid), // .valid
.src0_data (rsp_demux_013_src0_data), // .data
.src0_channel (rsp_demux_013_src0_channel), // .channel
.src0_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_013_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_014 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_016_src_ready), // sink.ready
.sink_channel (router_016_src_channel), // .channel
.sink_data (router_016_src_data), // .data
.sink_startofpacket (router_016_src_startofpacket), // .startofpacket
.sink_endofpacket (router_016_src_endofpacket), // .endofpacket
.sink_valid (router_016_src_valid), // .valid
.src0_ready (rsp_demux_014_src0_ready), // src0.ready
.src0_valid (rsp_demux_014_src0_valid), // .valid
.src0_data (rsp_demux_014_src0_data), // .data
.src0_channel (rsp_demux_014_src0_channel), // .channel
.src0_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_014_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_015 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_017_src_ready), // sink.ready
.sink_channel (router_017_src_channel), // .channel
.sink_data (router_017_src_data), // .data
.sink_startofpacket (router_017_src_startofpacket), // .startofpacket
.sink_endofpacket (router_017_src_endofpacket), // .endofpacket
.sink_valid (router_017_src_valid), // .valid
.src0_ready (rsp_demux_015_src0_ready), // src0.ready
.src0_valid (rsp_demux_015_src0_valid), // .valid
.src0_data (rsp_demux_015_src0_data), // .data
.src0_channel (rsp_demux_015_src0_channel), // .channel
.src0_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_015_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_016 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_018_src_ready), // sink.ready
.sink_channel (router_018_src_channel), // .channel
.sink_data (router_018_src_data), // .data
.sink_startofpacket (router_018_src_startofpacket), // .startofpacket
.sink_endofpacket (router_018_src_endofpacket), // .endofpacket
.sink_valid (router_018_src_valid), // .valid
.src0_ready (rsp_demux_016_src0_ready), // src0.ready
.src0_valid (rsp_demux_016_src0_valid), // .valid
.src0_data (rsp_demux_016_src0_data), // .data
.src0_channel (rsp_demux_016_src0_channel), // .channel
.src0_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_016_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_017 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_019_src_ready), // sink.ready
.sink_channel (router_019_src_channel), // .channel
.sink_data (router_019_src_data), // .data
.sink_startofpacket (router_019_src_startofpacket), // .startofpacket
.sink_endofpacket (router_019_src_endofpacket), // .endofpacket
.sink_valid (router_019_src_valid), // .valid
.src0_ready (rsp_demux_017_src0_ready), // src0.ready
.src0_valid (rsp_demux_017_src0_valid), // .valid
.src0_data (rsp_demux_017_src0_data), // .data
.src0_channel (rsp_demux_017_src0_channel), // .channel
.src0_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_017_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_018 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_020_src_ready), // sink.ready
.sink_channel (router_020_src_channel), // .channel
.sink_data (router_020_src_data), // .data
.sink_startofpacket (router_020_src_startofpacket), // .startofpacket
.sink_endofpacket (router_020_src_endofpacket), // .endofpacket
.sink_valid (router_020_src_valid), // .valid
.src0_ready (rsp_demux_018_src0_ready), // src0.ready
.src0_valid (rsp_demux_018_src0_valid), // .valid
.src0_data (rsp_demux_018_src0_data), // .data
.src0_channel (rsp_demux_018_src0_channel), // .channel
.src0_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_018_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_019 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_021_src_ready), // sink.ready
.sink_channel (router_021_src_channel), // .channel
.sink_data (router_021_src_data), // .data
.sink_startofpacket (router_021_src_startofpacket), // .startofpacket
.sink_endofpacket (router_021_src_endofpacket), // .endofpacket
.sink_valid (router_021_src_valid), // .valid
.src0_ready (rsp_demux_019_src0_ready), // src0.ready
.src0_valid (rsp_demux_019_src0_valid), // .valid
.src0_data (rsp_demux_019_src0_data), // .data
.src0_channel (rsp_demux_019_src0_channel), // .channel
.src0_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_019_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_020 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_022_src_ready), // sink.ready
.sink_channel (router_022_src_channel), // .channel
.sink_data (router_022_src_data), // .data
.sink_startofpacket (router_022_src_startofpacket), // .startofpacket
.sink_endofpacket (router_022_src_endofpacket), // .endofpacket
.sink_valid (router_022_src_valid), // .valid
.src0_ready (rsp_demux_020_src0_ready), // src0.ready
.src0_valid (rsp_demux_020_src0_valid), // .valid
.src0_data (rsp_demux_020_src0_data), // .data
.src0_channel (rsp_demux_020_src0_channel), // .channel
.src0_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_020_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_021 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_023_src_ready), // sink.ready
.sink_channel (router_023_src_channel), // .channel
.sink_data (router_023_src_data), // .data
.sink_startofpacket (router_023_src_startofpacket), // .startofpacket
.sink_endofpacket (router_023_src_endofpacket), // .endofpacket
.sink_valid (router_023_src_valid), // .valid
.src0_ready (rsp_demux_021_src0_ready), // src0.ready
.src0_valid (rsp_demux_021_src0_valid), // .valid
.src0_data (rsp_demux_021_src0_data), // .data
.src0_channel (rsp_demux_021_src0_channel), // .channel
.src0_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_021_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_022 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_024_src_ready), // sink.ready
.sink_channel (router_024_src_channel), // .channel
.sink_data (router_024_src_data), // .data
.sink_startofpacket (router_024_src_startofpacket), // .startofpacket
.sink_endofpacket (router_024_src_endofpacket), // .endofpacket
.sink_valid (router_024_src_valid), // .valid
.src0_ready (rsp_demux_022_src0_ready), // src0.ready
.src0_valid (rsp_demux_022_src0_valid), // .valid
.src0_data (rsp_demux_022_src0_data), // .data
.src0_channel (rsp_demux_022_src0_channel), // .channel
.src0_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_022_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_023 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_025_src_ready), // sink.ready
.sink_channel (router_025_src_channel), // .channel
.sink_data (router_025_src_data), // .data
.sink_startofpacket (router_025_src_startofpacket), // .startofpacket
.sink_endofpacket (router_025_src_endofpacket), // .endofpacket
.sink_valid (router_025_src_valid), // .valid
.src0_ready (rsp_demux_023_src0_ready), // src0.ready
.src0_valid (rsp_demux_023_src0_valid), // .valid
.src0_data (rsp_demux_023_src0_data), // .data
.src0_channel (rsp_demux_023_src0_channel), // .channel
.src0_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_023_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_024 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_026_src_ready), // sink.ready
.sink_channel (router_026_src_channel), // .channel
.sink_data (router_026_src_data), // .data
.sink_startofpacket (router_026_src_startofpacket), // .startofpacket
.sink_endofpacket (router_026_src_endofpacket), // .endofpacket
.sink_valid (router_026_src_valid), // .valid
.src0_ready (rsp_demux_024_src0_ready), // src0.ready
.src0_valid (rsp_demux_024_src0_valid), // .valid
.src0_data (rsp_demux_024_src0_data), // .data
.src0_channel (rsp_demux_024_src0_channel), // .channel
.src0_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_024_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_025 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_027_src_ready), // sink.ready
.sink_channel (router_027_src_channel), // .channel
.sink_data (router_027_src_data), // .data
.sink_startofpacket (router_027_src_startofpacket), // .startofpacket
.sink_endofpacket (router_027_src_endofpacket), // .endofpacket
.sink_valid (router_027_src_valid), // .valid
.src0_ready (rsp_demux_025_src0_ready), // src0.ready
.src0_valid (rsp_demux_025_src0_valid), // .valid
.src0_data (rsp_demux_025_src0_data), // .data
.src0_channel (rsp_demux_025_src0_channel), // .channel
.src0_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_025_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_026 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_028_src_ready), // sink.ready
.sink_channel (router_028_src_channel), // .channel
.sink_data (router_028_src_data), // .data
.sink_startofpacket (router_028_src_startofpacket), // .startofpacket
.sink_endofpacket (router_028_src_endofpacket), // .endofpacket
.sink_valid (router_028_src_valid), // .valid
.src0_ready (rsp_demux_026_src0_ready), // src0.ready
.src0_valid (rsp_demux_026_src0_valid), // .valid
.src0_data (rsp_demux_026_src0_data), // .data
.src0_channel (rsp_demux_026_src0_channel), // .channel
.src0_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_026_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_027 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_029_src_ready), // sink.ready
.sink_channel (router_029_src_channel), // .channel
.sink_data (router_029_src_data), // .data
.sink_startofpacket (router_029_src_startofpacket), // .startofpacket
.sink_endofpacket (router_029_src_endofpacket), // .endofpacket
.sink_valid (router_029_src_valid), // .valid
.src0_ready (rsp_demux_027_src0_ready), // src0.ready
.src0_valid (rsp_demux_027_src0_valid), // .valid
.src0_data (rsp_demux_027_src0_data), // .data
.src0_channel (rsp_demux_027_src0_channel), // .channel
.src0_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_027_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_028 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_030_src_ready), // sink.ready
.sink_channel (router_030_src_channel), // .channel
.sink_data (router_030_src_data), // .data
.sink_startofpacket (router_030_src_startofpacket), // .startofpacket
.sink_endofpacket (router_030_src_endofpacket), // .endofpacket
.sink_valid (router_030_src_valid), // .valid
.src0_ready (rsp_demux_028_src0_ready), // src0.ready
.src0_valid (rsp_demux_028_src0_valid), // .valid
.src0_data (rsp_demux_028_src0_data), // .data
.src0_channel (rsp_demux_028_src0_channel), // .channel
.src0_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_028_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_029 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_031_src_ready), // sink.ready
.sink_channel (router_031_src_channel), // .channel
.sink_data (router_031_src_data), // .data
.sink_startofpacket (router_031_src_startofpacket), // .startofpacket
.sink_endofpacket (router_031_src_endofpacket), // .endofpacket
.sink_valid (router_031_src_valid), // .valid
.src0_ready (rsp_demux_029_src0_ready), // src0.ready
.src0_valid (rsp_demux_029_src0_valid), // .valid
.src0_data (rsp_demux_029_src0_data), // .data
.src0_channel (rsp_demux_029_src0_channel), // .channel
.src0_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_029_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_030 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_032_src_ready), // sink.ready
.sink_channel (router_032_src_channel), // .channel
.sink_data (router_032_src_data), // .data
.sink_startofpacket (router_032_src_startofpacket), // .startofpacket
.sink_endofpacket (router_032_src_endofpacket), // .endofpacket
.sink_valid (router_032_src_valid), // .valid
.src0_ready (rsp_demux_030_src0_ready), // src0.ready
.src0_valid (rsp_demux_030_src0_valid), // .valid
.src0_data (rsp_demux_030_src0_data), // .data
.src0_channel (rsp_demux_030_src0_channel), // .channel
.src0_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_030_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_demux rsp_demux_031 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_033_src_ready), // sink.ready
.sink_channel (router_033_src_channel), // .channel
.sink_data (router_033_src_data), // .data
.sink_startofpacket (router_033_src_startofpacket), // .startofpacket
.sink_endofpacket (router_033_src_endofpacket), // .endofpacket
.sink_valid (router_033_src_valid), // .valid
.src0_ready (rsp_demux_031_src0_ready), // src0.ready
.src0_valid (rsp_demux_031_src0_valid), // .valid
.src0_data (rsp_demux_031_src0_data), // .data
.src0_channel (rsp_demux_031_src0_channel), // .channel
.src0_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_031_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src0_valid), // .valid
.sink9_channel (rsp_demux_009_src0_channel), // .channel
.sink9_data (rsp_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src0_valid), // .valid
.sink10_channel (rsp_demux_010_src0_channel), // .channel
.sink10_data (rsp_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src0_endofpacket), // .endofpacket
.sink11_ready (rsp_demux_011_src0_ready), // sink11.ready
.sink11_valid (rsp_demux_011_src0_valid), // .valid
.sink11_channel (rsp_demux_011_src0_channel), // .channel
.sink11_data (rsp_demux_011_src0_data), // .data
.sink11_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.sink11_endofpacket (rsp_demux_011_src0_endofpacket), // .endofpacket
.sink12_ready (rsp_demux_012_src0_ready), // sink12.ready
.sink12_valid (rsp_demux_012_src0_valid), // .valid
.sink12_channel (rsp_demux_012_src0_channel), // .channel
.sink12_data (rsp_demux_012_src0_data), // .data
.sink12_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.sink12_endofpacket (rsp_demux_012_src0_endofpacket), // .endofpacket
.sink13_ready (rsp_demux_013_src0_ready), // sink13.ready
.sink13_valid (rsp_demux_013_src0_valid), // .valid
.sink13_channel (rsp_demux_013_src0_channel), // .channel
.sink13_data (rsp_demux_013_src0_data), // .data
.sink13_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.sink13_endofpacket (rsp_demux_013_src0_endofpacket), // .endofpacket
.sink14_ready (rsp_demux_014_src0_ready), // sink14.ready
.sink14_valid (rsp_demux_014_src0_valid), // .valid
.sink14_channel (rsp_demux_014_src0_channel), // .channel
.sink14_data (rsp_demux_014_src0_data), // .data
.sink14_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.sink14_endofpacket (rsp_demux_014_src0_endofpacket), // .endofpacket
.sink15_ready (rsp_demux_015_src0_ready), // sink15.ready
.sink15_valid (rsp_demux_015_src0_valid), // .valid
.sink15_channel (rsp_demux_015_src0_channel), // .channel
.sink15_data (rsp_demux_015_src0_data), // .data
.sink15_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.sink15_endofpacket (rsp_demux_015_src0_endofpacket), // .endofpacket
.sink16_ready (rsp_demux_016_src0_ready), // sink16.ready
.sink16_valid (rsp_demux_016_src0_valid), // .valid
.sink16_channel (rsp_demux_016_src0_channel), // .channel
.sink16_data (rsp_demux_016_src0_data), // .data
.sink16_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.sink16_endofpacket (rsp_demux_016_src0_endofpacket), // .endofpacket
.sink17_ready (rsp_demux_017_src0_ready), // sink17.ready
.sink17_valid (rsp_demux_017_src0_valid), // .valid
.sink17_channel (rsp_demux_017_src0_channel), // .channel
.sink17_data (rsp_demux_017_src0_data), // .data
.sink17_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.sink17_endofpacket (rsp_demux_017_src0_endofpacket), // .endofpacket
.sink18_ready (rsp_demux_018_src0_ready), // sink18.ready
.sink18_valid (rsp_demux_018_src0_valid), // .valid
.sink18_channel (rsp_demux_018_src0_channel), // .channel
.sink18_data (rsp_demux_018_src0_data), // .data
.sink18_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.sink18_endofpacket (rsp_demux_018_src0_endofpacket), // .endofpacket
.sink19_ready (rsp_demux_019_src0_ready), // sink19.ready
.sink19_valid (rsp_demux_019_src0_valid), // .valid
.sink19_channel (rsp_demux_019_src0_channel), // .channel
.sink19_data (rsp_demux_019_src0_data), // .data
.sink19_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.sink19_endofpacket (rsp_demux_019_src0_endofpacket), // .endofpacket
.sink20_ready (rsp_demux_020_src0_ready), // sink20.ready
.sink20_valid (rsp_demux_020_src0_valid), // .valid
.sink20_channel (rsp_demux_020_src0_channel), // .channel
.sink20_data (rsp_demux_020_src0_data), // .data
.sink20_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.sink20_endofpacket (rsp_demux_020_src0_endofpacket), // .endofpacket
.sink21_ready (rsp_demux_021_src0_ready), // sink21.ready
.sink21_valid (rsp_demux_021_src0_valid), // .valid
.sink21_channel (rsp_demux_021_src0_channel), // .channel
.sink21_data (rsp_demux_021_src0_data), // .data
.sink21_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.sink21_endofpacket (rsp_demux_021_src0_endofpacket), // .endofpacket
.sink22_ready (rsp_demux_022_src0_ready), // sink22.ready
.sink22_valid (rsp_demux_022_src0_valid), // .valid
.sink22_channel (rsp_demux_022_src0_channel), // .channel
.sink22_data (rsp_demux_022_src0_data), // .data
.sink22_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.sink22_endofpacket (rsp_demux_022_src0_endofpacket), // .endofpacket
.sink23_ready (rsp_demux_023_src0_ready), // sink23.ready
.sink23_valid (rsp_demux_023_src0_valid), // .valid
.sink23_channel (rsp_demux_023_src0_channel), // .channel
.sink23_data (rsp_demux_023_src0_data), // .data
.sink23_startofpacket (rsp_demux_023_src0_startofpacket), // .startofpacket
.sink23_endofpacket (rsp_demux_023_src0_endofpacket), // .endofpacket
.sink24_ready (rsp_demux_024_src0_ready), // sink24.ready
.sink24_valid (rsp_demux_024_src0_valid), // .valid
.sink24_channel (rsp_demux_024_src0_channel), // .channel
.sink24_data (rsp_demux_024_src0_data), // .data
.sink24_startofpacket (rsp_demux_024_src0_startofpacket), // .startofpacket
.sink24_endofpacket (rsp_demux_024_src0_endofpacket), // .endofpacket
.sink25_ready (rsp_demux_025_src0_ready), // sink25.ready
.sink25_valid (rsp_demux_025_src0_valid), // .valid
.sink25_channel (rsp_demux_025_src0_channel), // .channel
.sink25_data (rsp_demux_025_src0_data), // .data
.sink25_startofpacket (rsp_demux_025_src0_startofpacket), // .startofpacket
.sink25_endofpacket (rsp_demux_025_src0_endofpacket), // .endofpacket
.sink26_ready (rsp_demux_026_src0_ready), // sink26.ready
.sink26_valid (rsp_demux_026_src0_valid), // .valid
.sink26_channel (rsp_demux_026_src0_channel), // .channel
.sink26_data (rsp_demux_026_src0_data), // .data
.sink26_startofpacket (rsp_demux_026_src0_startofpacket), // .startofpacket
.sink26_endofpacket (rsp_demux_026_src0_endofpacket), // .endofpacket
.sink27_ready (rsp_demux_027_src0_ready), // sink27.ready
.sink27_valid (rsp_demux_027_src0_valid), // .valid
.sink27_channel (rsp_demux_027_src0_channel), // .channel
.sink27_data (rsp_demux_027_src0_data), // .data
.sink27_startofpacket (rsp_demux_027_src0_startofpacket), // .startofpacket
.sink27_endofpacket (rsp_demux_027_src0_endofpacket), // .endofpacket
.sink28_ready (rsp_demux_028_src0_ready), // sink28.ready
.sink28_valid (rsp_demux_028_src0_valid), // .valid
.sink28_channel (rsp_demux_028_src0_channel), // .channel
.sink28_data (rsp_demux_028_src0_data), // .data
.sink28_startofpacket (rsp_demux_028_src0_startofpacket), // .startofpacket
.sink28_endofpacket (rsp_demux_028_src0_endofpacket), // .endofpacket
.sink29_ready (rsp_demux_029_src0_ready), // sink29.ready
.sink29_valid (rsp_demux_029_src0_valid), // .valid
.sink29_channel (rsp_demux_029_src0_channel), // .channel
.sink29_data (rsp_demux_029_src0_data), // .data
.sink29_startofpacket (rsp_demux_029_src0_startofpacket), // .startofpacket
.sink29_endofpacket (rsp_demux_029_src0_endofpacket), // .endofpacket
.sink30_ready (rsp_demux_030_src0_ready), // sink30.ready
.sink30_valid (rsp_demux_030_src0_valid), // .valid
.sink30_channel (rsp_demux_030_src0_channel), // .channel
.sink30_data (rsp_demux_030_src0_data), // .data
.sink30_startofpacket (rsp_demux_030_src0_startofpacket), // .startofpacket
.sink30_endofpacket (rsp_demux_030_src0_endofpacket), // .endofpacket
.sink31_ready (rsp_demux_031_src0_ready), // sink31.ready
.sink31_valid (rsp_demux_031_src0_valid), // .valid
.sink31_channel (rsp_demux_031_src0_channel), // .channel
.sink31_data (rsp_demux_031_src0_data), // .data
.sink31_startofpacket (rsp_demux_031_src0_startofpacket), // .startofpacket
.sink31_endofpacket (rsp_demux_031_src0_endofpacket) // .endofpacket
);
nios_system_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (nios2_qsys_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src1_valid), // .valid
.sink0_channel (rsp_demux_001_src1_channel), // .channel
.sink0_data (rsp_demux_001_src1_data), // .data
.sink0_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_002_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_002_src1_valid), // .valid
.sink1_channel (rsp_demux_002_src1_channel), // .channel
.sink1_data (rsp_demux_002_src1_data), // .data
.sink1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
endmodule
|
module peripherals (
input clk,
input nrst,
output reg[31:0] data_out,
input wire[31:0] data_in,
input wire[5:0] addr,
input cs,
input oe,
input[3:0] wstrb,
// PORTA
inout[7:0] porta,
// PORTB
inout[7:0] portb,
// SDCARD
input sdcard_sck,
input sdcard_mosi,
output sdcard_miso,
// UART related
input rxd,
output wire txd,
// TIMER0
output timer0_comp_irq
);
wire [7:0] porta_pinx;
reg [7:0] porta_portx;
reg [7:0] porta_ddrx;
wire [7:0] portb_pinx;
reg [7:0] portb_portx;
reg [7:0] portb_ddrx;
reg [10:0] ser_out = ~0;
reg [8:0] ser_in = ~0;
reg [15:0] ser_tx_cnt = 0;
reg [15:0] ser_rx_cnt = 0;
reg [7:0] ser_rx_data;
reg [15:0] ser_brr;
reg ser_rxc;
reg ser_fe;
reg ser_dor;
reg rxd_s;
assign txd = ser_out[0];
reg ocie0, ocf0;
reg [23:0] tcnt0, ocr0;
assign timer0_comp_irq = ocie0 && ocf0;
tri_buf tri_buf_porta_inst[7:0](.out(porta_portx), .in(porta_pinx),
.en(porta_ddrx), .pin(porta));
tri_buf tri_buf_portb_inst[7:0](
.out ({portb_portx[7:3],
{sdcard_mosi, sdcard_sck},
portb_portx[0]}),
.in (portb_pinx),
.en ({portb_ddrx[7:4], 1'b0, portb_ddrx[2:0]}),
.pin (portb));
assign sdcard_miso = portb_pinx[3];
always @(posedge clk)
if (~nrst) begin
porta_portx <= 8'h00;
porta_ddrx <= 8'h00;
portb_portx <= 8'h00;
portb_ddrx <= 8'h00;
ser_out <= ~0;
ser_in <= ~0;
ser_tx_cnt <= 0;
ser_rx_cnt <= 0;
ser_brr <= 0;
ser_rx_data <= 8'h00;
ser_rxc <= 1'b0;
ser_fe <= 1'b0;
ser_dor <= 1'b0;
rxd_s <= 1'b1;
ocie0 <= 1'b0;
ocf0 <= 1'b0;
tcnt0 <= 0;
ocr0 <= 0;
end else begin
if (ser_tx_cnt == 0) begin
ser_out <= {1'b1,ser_out[10:1]};
ser_tx_cnt <= ser_brr;
end else
ser_tx_cnt <= ser_tx_cnt - 1;
if (ser_rx_cnt == 0) begin
ser_rx_cnt <= ser_brr;
if (!ser_in[0]) begin
ser_rx_data <= ser_in[8:1];
ser_fe <= ~rxd_s;
ser_dor <= ser_rxc;
ser_rxc <= 1'b1;
ser_in <= ~0;
end else
ser_in <= { rxd_s, ser_in[8:1] };
end else if (&ser_in && rxd_s) // if (ser_rx_cnt == 0)
ser_rx_cnt <= ser_brr >> 1;
else
ser_rx_cnt <= ser_rx_cnt - 1;
rxd_s <= rxd;
if(cs && oe && addr == 6'h08) begin
/* UDR0 is read, clear RXC0, FE0, and DOR0 */
ser_rxc <= 1'b0;
ser_fe <= 1'b0;
ser_dor <= 1'b0;
end
if (tcnt0 == ocr0) begin
tcnt0 <= 0;
ocf0 <= 1'b1;
end else
tcnt0 <= tcnt0 + 1;
if(cs && wstrb[0])
case(addr)
6'h00: porta_portx <= data_in[7:0];
6'h02: porta_ddrx <= data_in[7:0];
6'h04: portb_portx <= data_in[7:0];
6'h06: portb_ddrx <= data_in[7:0];
6'h08: ser_out <= {1'b1, data_in[7:0], 1'b0, 1'b1};
6'h0a: ser_brr[7:0] <= data_in[7:0];
6'h0c: tcnt0[7:0] <= data_in[7:0];
6'h0d: ocr0[7:0] <= data_in[7:0];
6'h0e: if (data_in[0]) ocf0 <= 1'b0;
6'h0f: ocie0 <= data_in[0];
endcase; // case (addr)
if(cs && wstrb[1])
case(addr)
6'h0a: ser_brr[15:8] <= data_in[15:8];
6'h0c: tcnt0[15:8] <= data_in[15:8];
6'h0d: ocr0[15:8] <= data_in[15:8];
endcase; // case (addr)
if(cs && wstrb[2])
case(addr)
6'h0c: tcnt0[23:16] <= data_in[23:16];
6'h0d: ocr0[23:16] <= data_in[23:16];
endcase; // case (addr)
end // else: !if(~nrst)
always @(*) begin
data_out = 32'h00000000;
if (nrst && cs && oe)
case(addr)
6'h00: data_out[7:0] = porta_portx;
6'h01: data_out[7:0] = porta_pinx;
6'h02: data_out[7:0] = porta_ddrx;
6'h04: data_out[7:0] = portb_portx;
6'h05: data_out[7:0] = portb_pinx;
6'h06: data_out[7:0] = portb_ddrx;
6'h08: data_out[7:0] = ser_rx_data;
6'h09: data_out[7:0] = {ser_rxc, &ser_out, &ser_out, ser_fe, ser_dor, 3'b000};
6'h0a: data_out[15:0] = ser_brr;
6'h0c: data_out[23:0] = tcnt0;
6'h0d: data_out[23:0] = ocr0;
6'h0e: data_out[0] = ocf0;
6'h0f: data_out[0] = ocie0;
endcase // case (addr)
end
endmodule // peripherals
|
/*
* These source files contain a hardware description of a network
* automatically generated by CONNECT (CONfigurable NEtwork Creation Tool).
*
* This product includes a hardware design developed by Carnegie Mellon
* University.
*
* Copyright (c) 2012 by Michael K. Papamichael, Carnegie Mellon University
*
* For more information, see the CONNECT project website at:
* http://www.ece.cmu.edu/~mpapamic/connect
*
* This design is provided for internal, non-commercial research use only,
* cannot be used for, or in support of, goods or services, and is not for
* redistribution, with or without modifications.
*
* You may not use the name "Carnegie Mellon University" or derivations
* thereof to endorse or promote products derived from this software.
*
* THE SOFTWARE IS PROVIDED "AS-IS" WITHOUT ANY WARRANTY OF ANY KIND, EITHER
* EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO ANY WARRANTY
* THAT THE SOFTWARE WILL CONFORM TO SPECIFICATIONS OR BE ERROR-FREE AND ANY
* IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE,
* TITLE, OR NON-INFRINGEMENT. IN NO EVENT SHALL CARNEGIE MELLON UNIVERSITY
* BE LIABLE FOR ANY DAMAGES, INCLUDING BUT NOT LIMITED TO DIRECT, INDIRECT,
* SPECIAL OR CONSEQUENTIAL DAMAGES, ARISING OUT OF, RESULTING FROM, OR IN
* ANY WAY CONNECTED WITH THIS SOFTWARE (WHETHER OR NOT BASED UPON WARRANTY,
* CONTRACT, TORT OR OTHERWISE).
*
*/
/* =========================================================================
*
* Filename: testbench_sample.v
* Date created: 05-28-2012
* Last modified: 06-09-2012
* Authors: Michael Papamichael <papamixATcs.cmu.edu>
*
* Description:
* Minimal testbench sample for CONNECT networks
*
* =========================================================================
*/
`ifndef XST_SYNTH
`timescale 1ns / 1ps
`include "connect_parameters.v"
module CONNECT_testbench_sample();
parameter HalfClkPeriod = 5;
localparam ClkPeriod = 2*HalfClkPeriod;
// non-VC routers still reeserve 1 dummy bit for VC.
localparam vc_bits = (`NUM_VCS > 1) ? $clog2(`NUM_VCS) : 1;
localparam dest_bits = $clog2(`NUM_USER_RECV_PORTS);
localparam flit_port_width = 2 /*valid and tail bits*/+ `FLIT_DATA_WIDTH + dest_bits + vc_bits;
localparam credit_port_width = 1 + vc_bits; // 1 valid bit
localparam test_cycles = 20;
reg Clk;
reg Rst_n;
// input regs
reg send_flit [0:`NUM_USER_SEND_PORTS-1]; // enable sending flits
reg [flit_port_width-1:0] flit_in [0:`NUM_USER_SEND_PORTS-1]; // send port inputs
reg send_credit [0:`NUM_USER_RECV_PORTS-1]; // enable sending credits
reg [credit_port_width-1:0] credit_in [0:`NUM_USER_RECV_PORTS-1]; //recv port credits
// output wires
wire [credit_port_width-1:0] credit_out [0:`NUM_USER_SEND_PORTS-1];
wire [flit_port_width-1:0] flit_out [0:`NUM_USER_RECV_PORTS-1];
reg [31:0] cycle;
integer i;
// packet fields
reg is_valid;
reg is_tail;
reg [dest_bits-1:0] dest;
reg [vc_bits-1:0] vc;
reg [`FLIT_DATA_WIDTH-1:0] data;
// Generate Clock
initial Clk = 0;
always #(HalfClkPeriod) Clk = ~Clk;
// Run simulation
initial begin
cycle = 0;
for(i = 0; i < `NUM_USER_SEND_PORTS; i = i + 1) begin flit_in[i] = 0; send_flit[i] = 0; end
for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin credit_in[i] = 0; send_credit[i] = 0; end
$display("---- Performing Reset ----");
Rst_n = 0; // perform reset (active low)
#(5*ClkPeriod+HalfClkPeriod);
Rst_n = 1;
#(HalfClkPeriod);
// send a 2-flit packet from send port 0 to receive port 1
send_flit[0] = 1'b1;
dest = 1;
vc = 0;
data = 'ha;
flit_in[0] = {1'b1 /*valid*/, 1'b0 /*tail*/, dest, vc, data};
$display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);
#(ClkPeriod);
// send 2nd flit of packet
send_flit[0] = 1'b1;
data = 'hb;
flit_in[0] = {1'b1 /*valid*/, 1'b1 /*tail*/, dest, vc, data};
$display("@%3d: Injecting flit %x into send port %0d", cycle, flit_in[0], 0);
#(ClkPeriod);
// stop sending flits
send_flit[0] = 1'b0;
flit_in[0] = 'b0; // valid bit
end
// Monitor arriving flits
always @ (posedge Clk) begin
cycle <= cycle + 1;
for(i = 0; i < `NUM_USER_RECV_PORTS; i = i + 1) begin
if(flit_out[i][flit_port_width-1]) begin // valid flit
$display("@%3d: Ejecting flit %x at receive port %0d", cycle, flit_out[i], i);
end
end
// terminate simulation
if (cycle > test_cycles) begin
$finish();
end
end
// Add your code to handle flow control here (sending receiving credits)
// Instantiate CONNECT network
mkNetwork dut
(.CLK(Clk)
,.RST_N(Rst_n)
,.send_ports_0_putFlit_flit_in(flit_in[0])
,.EN_send_ports_0_putFlit(send_flit[0])
,.EN_send_ports_0_getCredits(1'b1) // drain credits
,.send_ports_0_getCredits(credit_out[0])
,.send_ports_1_putFlit_flit_in(flit_in[1])
,.EN_send_ports_1_putFlit(send_flit[1])
,.EN_send_ports_1_getCredits(1'b1) // drain credits
,.send_ports_1_getCredits(credit_out[1])
// add rest of send ports here
//
,.EN_recv_ports_0_getFlit(1'b1) // drain flits
,.recv_ports_0_getFlit(flit_out[0])
,.recv_ports_0_putCredits_cr_in(credit_in[0])
,.EN_recv_ports_0_putCredits(send_credit[0])
,.EN_recv_ports_1_getFlit(1'b1) // drain flits
,.recv_ports_1_getFlit(flit_out[1])
,.recv_ports_1_putCredits_cr_in(credit_in[1])
,.EN_recv_ports_1_putCredits(send_credit[1])
// add rest of receive ports here
//
);
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4_4_V
`define SKY130_FD_SC_MS__OR4_4_V
/**
* or4: 4-input OR.
*
* Verilog wrapper for or4 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4_4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or4_4 (
X,
A,
B,
C,
D
);
output X;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or4 base (
.X(X),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4_4_V
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire clk90,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T RGMII
*/
input wire phy_rx_clk,
input wire [3:0] phy_rxd,
input wire phy_rx_ctl,
output wire phy_tx_clk,
output wire [3:0] phy_txd,
output wire phy_tx_ctl,
output wire phy_reset_n,
input wire phy_int_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
output wire uart_rts,
input wire uart_cts
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
assign uart_rts = 0;
eth_mac_1g_rgmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR"),
.CLOCK_INPUT_STYLE("BUFR"),
.USE_CLK90("TRUE"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_clk90(clk90),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.rgmii_rx_clk(phy_rx_clk),
.rgmii_rxd(phy_rxd),
.rgmii_rx_ctl(phy_rx_ctl),
.rgmii_tx_clk(phy_tx_clk),
.rgmii_txd(phy_txd),
.rgmii_tx_ctl(phy_tx_ctl),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
module counter (clk,sig,f);
/*This module takes an input signal and implements a period counter,
taking the reciprocal to deliver the frequency in kHz.
USAGE:
counter c(clk,sig,f);
clk and sig are 1-bit inputs representing the clock and RF signal whose frequency
is to be measured.
f is a 4-bit output corresponding to the frequency of sig, IN UNITS OF HUNDREDS
OF Hz. This is because hundreds of Hz is the highest requeired frequency
resolution, and we want to use integer arithmetic.
Reference: Agilent Technologies. "Fundamentals of the Electronic Counters".
Application Note 200, Electronic Counter Series.
Design notes:
In a period counter, pulses of the clock are counted in a register, with the
totaling (counting) action gated by pulses from the RF input whose frequency
is being measured. Averaging over multiple RF cycles reduces error.
The total time elapsed between RF edges will be
n_clk*tau_c+err = m/f
=>f= m/(n_clk*tau_c+err)
where tau_c is the clock period, n_clk is the number of clock cycles actually counted
by the register, err is the error in the time estimate, m is the number of RF
positive edges, and f is the RF frequency.
Contributions to error include the +-1 count error, timebase deviations, etc.
The +-1 count error, or quantization error, arises because time is only measured
in discrete steps, and a measurement of four clock time units may be produced by
RF pulses which are acutally separated by 3+delta or 5-delta clock units.
The nominal frequency estimate
f_nominal=m/(n_clk*tau_c)
converges with the value that would arise from an average after many cycles
if n_clk is very large.
With just the +-1 count error, the spread in maximum and minimum possible
frequency estimates
fmax-fmin=m/tau_c*(1/(n_clk-1)-1/(n_clk+1))=2*m/tau_c * 1/(n_clk^2-1) ~= 2*f_nom^2*tau_c/m
=2*f_nom^2/(f_clk*m)
The error increases with frequency for a fixed number of RF pulses, but decreases
as the clock frequency increases and as the number of RF pulses averaged over
increases.
We require about 3 kHz resolution at the highest frequencies (around 300 kHz)
and about 500 Hz resolution at the lowest frequencies - these values are about
half the frequency interval between adjacent bins in these sub-bands. With
a clock speed of 4 MHz,
m=2*f_high^2/(f_clk*Delta_f_high)=2*(3E5^2)/(4E6*3E3)=18E10/(12E9)=15
with m=15, at the lower frequencies,
fmax-fmin=2*5E4^2/(4E6*15) = Delta_f_high/36 ~= 83 Hz
while m/5E4=15/5E4=3.0E-4=300 us is the maximum time elapsed per measurement.
At high frequency, Delta_t = m/300E3=50 us.
Since we are willing to accept a reaction time on the order of 1 ms, we can
actually improve accuracy by increasing m such that Delta_t_max = 1 ms = m/5E4
=>m=50.
So choose m=50, which gives fmax-fmin~=900 Hz at f_rf=300 kHz.
f_nom = m*f_clk/n_clk => n_clk = m*f_clk/f_nom,
n_clk_max=50*4E6/5E4=80E2=4000
=>n_clk needs to be at least 12 bits. Make 13.
13 Jan 2012
In general, the phase of clk edges relative sig edges will change. Some phases produce floor(M*tau_s/tau_c) clock counts, while others produce floor(M*tau_s/tau_c)+1 clock counts. This results in a jitter in n_clk. By itself, this might not be so bad, but when many bits are changing (since we are not using a Gray code), this can be problematic. Further, in practice, the spread in clock counts seems to reach +0+2, instead of +0+1.
The fix implemented is to compare the value of n_clk at the 50th sig interval to the value of n_clk used in the last frequency calculation. If the absolute value of the difference is larger than MIN_CHANGE=2, then the frequency is re-computed. Otherwise, the frequency is not changed. This seems to take care of the jitter.
//Error (10239): Verilog HDL Always Construct error at counter.v(102): event control cannot test for both positive and negative edges of variable "clk"
*/
`define CLK_COUNTER_SIZE 14 //Number of bits in clock edge counter.
`define SIG_COUNTER_SIZE 7 //Number of bits in signal edge counter.
input clk,sig;
output reg [13:0] f; //Output frequency in hundreds of Hz.
reg [13:0] n_clk; //Register to hold number of clock counts between RF signal.
reg [13:0] n_clk_last; //Holds value of n_clk used in the last frequency computation. Compared with current value to determine whether frequency should be recomputed.
reg [6:0] n_sig; //Register to count the number of RF cycles.
reg cnt_flg; //Counter flag.
reg reset; //Internal flag to reset clock counter.
//Clock frequency in hundreds of Hz.
//parameter F_CLK=40000;
parameter F_CLK=35795; //This clock was used to test whether incorrect firing of state happens at different frequencies depending on clock frequency and precession of this with sync signal freq.
//Number of cycles of RF signal over which to average period.
parameter M=50;
//Define macros to set counter sizes for convenience (so that don't have to make multiple changes if counter size needs to be adjusted).
parameter MIN_CHANGE=`CLK_COUNTER_SIZE'b10; //n_clk must change by at least this ambout (up or down) from last n_clk in order for a change in computed frequency to be allowed.
initial begin
#0
n_clk=`CLK_COUNTER_SIZE'b0; //Initialize clock edge counter.
n_sig=`SIG_COUNTER_SIZE'b0; //RF Cycle counter.
reset=1'b1; //Initialize reset flag to block clock counter until signal counter gate opens.
end
//Clock loop
//always @(posedge clk) begin //Triggering on reset was there in case there were two sig edges before the next clk edge, in which case the reset call would get skipped. But maybe false triggers are causing clock count to drift or flicker. Remove this edge detector and see what happens. Result - no, that didn't fix the problem.
always @(posedge clk or posedge reset) begin
if (reset) begin
n_clk=`CLK_COUNTER_SIZE'b0; //Reset clk counter.
end else begin
n_clk=n_clk+`CLK_COUNTER_SIZE'b1; //Increment clk counter.
end
end
//Gate on positive edges of signal
always @(posedge sig) begin
//Initially, the gate is closed and n_sig=0.
//When the gate is opened, n_sig is incremented, so n_sig=1.
//The gate is closed again at the (M+1)th positive edge on n_sig, but before n_sig is incremented,
//so n_sig=M still.
//As such, the gate is open between the 1st and (M+1)th positive edges of n_sig, corresponding to M sig intervals.
//The gate is closed between the (M+1)th=0th and 1st signal edges.
//THEN dt = (M)*tau_sig = (M)/f_sig = (n_clk-1+[-0+2])/f_clk
//It is n_clk-1 because this is the number of clock time intervals in n_clk positive edges.
// [-0+2]=error on time measurement - time is at least (n_clk-1)*tau_c, but could be as much as
// (n_clk-1+2-delta)*tau_c, so on average, elapsed time is actually (n_clk-1 - (average error = (0+2)/2=1))*tau_c
// => f_sig = f_clk * (M)/(n_clk-1-(0+2)/2) = f_clk * (M)/n_clk
if (n_sig==M) begin //This is actually the M+1th edge, and the Mth interval
//After M sig edges and n_clk clock edges,
//Handle case where n_clk=0 by saturating frequency at f=M*F_CLK.
if(n_clk==`CLK_COUNTER_SIZE'b0) f=(M)*F_CLK; //Case where no counts on clock are registered.
//Disallow jitter from changes in n_clk by +-2; only update frequency
//when clock counter is different by a number other than +-MIN_CHANGE.
else if ((n_clk>n_clk_last && n_clk-n_clk_last>MIN_CHANGE) || ( n_clk_last>n_clk && n_clk_last-n_clk>MIN_CHANGE) ) begin
n_clk_last=n_clk; //Store clock counter at last frequency change.
f=(M*F_CLK)/n_clk; //Re-compute RF frequency.
end
n_sig=`SIG_COUNTER_SIZE'b0; //Zero out rf cycle counter.
reset=1'b1; //Set reset flag high to restart clock counter.
end else begin //Start incrementing signal positive edge counter.
reset=1'b0; //Set reset low and start counting clock cycles again.
n_sig=n_sig+`SIG_COUNTER_SIZE'b1; //Increment RF cycle counter.
end
end
endmodule
|
/**
* A module for fetching the next instruction for
* the processor to execute.
*
* @author Robert Fotino, 2016
*/
`include "definitions.vh"
module instr_cache
(
input clk,
input boot_done,
// Requests for instructions
input [`ADDR_BITS-1:0] instr_ptr,
output valid,
output reg [`INSTR_BITS-1:0] instr,
// Main memory controls
output reg mem_cmd_en,
output [2:0] mem_cmd_instr,
output [5:0] mem_cmd_bl,
output reg [29:0] mem_cmd_byte_addr,
input mem_cmd_empty,
input mem_cmd_full,
output reg mem_rd_en,
input [31:0] mem_rd_data,
input mem_rd_full,
input mem_rd_empty,
input [6:0] mem_rd_count,
input mem_rd_overflow,
input mem_rd_error
);
initial begin
instr = 0;
mem_cmd_en = 0;
mem_cmd_byte_addr = 0;
mem_rd_en = 0;
end
// Always read
assign mem_cmd_instr = 3'b001;
// Burst length is always one word (for now)
assign mem_cmd_bl = 6'b000000;
// State machine logic for talking to RAM
`define STATE_PRE_BOOT 0
`define STATE_CMD 1
`define STATE_WAIT 2
`define STATE_READ 3
reg [1:0] state = `STATE_PRE_BOOT;
wire [29:0] prefixed_instr_ptr = { `MAIN_MEM_PREFIX, instr_ptr };
assign valid = (`STATE_CMD == state) && (mem_cmd_byte_addr == prefixed_instr_ptr);
always @ (posedge clk) begin
mem_cmd_en <= 0;
mem_rd_en <= 0;
case (state)
`STATE_PRE_BOOT: begin
if (boot_done) begin
send_cmd();
end
end
`STATE_CMD: begin
if (mem_cmd_byte_addr != prefixed_instr_ptr) begin
send_cmd();
end
end
`STATE_WAIT: begin
if (!mem_rd_empty) begin
mem_rd_en <= 1;
state <= `STATE_READ;
end
end
`STATE_READ: begin
instr <= mem_rd_data;
state <= `STATE_CMD;
end
endcase
end
task send_cmd;
begin
mem_cmd_en <= 1;
mem_cmd_byte_addr <= prefixed_instr_ptr;
state <= `STATE_WAIT;
end
endtask
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
(* altera_attribute = "-name GLOBAL_SIGNAL OFF" *)
module ddr3_s4_uniphy_example_if0_p0_reset(
seq_reset_mem_stable,
pll_afi_clk,
pll_addr_cmd_clk,
pll_dqs_ena_clk,
seq_clk,
scc_clk,
pll_avl_clk,
reset_n_scc_clk,
reset_n_avl_clk,
read_capture_clk,
pll_locked,
global_reset_n,
soft_reset_n,
csr_soft_reset_req,
reset_request_n,
ctl_reset_n,
reset_n_afi_clk,
reset_n_addr_cmd_clk,
reset_n_resync_clk,
reset_n_seq_clk,
reset_n_read_capture_clk
);
parameter MEM_READ_DQS_WIDTH = "";
parameter NUM_AFI_RESET = 1;
input seq_reset_mem_stable;
input pll_afi_clk;
input pll_addr_cmd_clk;
input pll_dqs_ena_clk;
input seq_clk;
input scc_clk;
input pll_avl_clk;
output reset_n_scc_clk;
output reset_n_avl_clk;
input [MEM_READ_DQS_WIDTH-1:0] read_capture_clk;
input pll_locked;
input global_reset_n;
input soft_reset_n;
input csr_soft_reset_req;
output reset_request_n;
output ctl_reset_n;
output [NUM_AFI_RESET-1:0] reset_n_afi_clk;
output reset_n_addr_cmd_clk;
output reset_n_resync_clk;
output reset_n_seq_clk;
output [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture_clk;
// Apply the synthesis keep attribute on the synchronized reset wires
// so that these names can be constrained using QSF settings to keep
// the resets on local routing.
wire phy_reset_n /* synthesis keep = 1 */;
wire phy_reset_mem_stable_n /* synthesis keep = 1*/;
wire [MEM_READ_DQS_WIDTH-1:0] reset_n_read_capture;
assign reset_request_n = pll_locked;
assign phy_reset_mem_stable_n = phy_reset_n & seq_reset_mem_stable;
assign reset_n_read_capture_clk = reset_n_read_capture;
assign phy_reset_n = pll_locked & global_reset_n & soft_reset_n & (!csr_soft_reset_req);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_afi_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (reset_n_afi_clk)
);
defparam ureset_afi_clk.RESET_SYNC_STAGES = 5;
defparam ureset_afi_clk.NUM_RESET_OUTPUT = NUM_AFI_RESET;
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_ctl_reset_clk(
.reset_n (phy_reset_n),
.clk (pll_afi_clk),
.reset_n_sync (ctl_reset_n)
);
defparam ureset_ctl_reset_clk.RESET_SYNC_STAGES = 5;
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_addr_cmd_clk(
.reset_n (phy_reset_n),
.clk (pll_addr_cmd_clk),
.reset_n_sync (reset_n_addr_cmd_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_resync_clk(
.reset_n (phy_reset_n),
.clk (pll_dqs_ena_clk),
.reset_n_sync (reset_n_resync_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_seq_clk(
.reset_n (phy_reset_n),
.clk (seq_clk),
.reset_n_sync (reset_n_seq_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_scc_clk(
.reset_n (phy_reset_n),
.clk (scc_clk),
.reset_n_sync (reset_n_scc_clk)
);
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_avl_clk(
.reset_n (phy_reset_n),
.clk (pll_avl_clk),
.reset_n_sync (reset_n_avl_clk)
);
generate
genvar i;
for (i=0; i<MEM_READ_DQS_WIDTH; i=i+1)
begin: read_capture_reset
ddr3_s4_uniphy_example_if0_p0_reset_sync ureset_read_capture_clk(
.reset_n (phy_reset_mem_stable_n),
.clk (read_capture_clk[i]),
.reset_n_sync (reset_n_read_capture[i])
);
end
endgenerate
endmodule
|
module top;
reg passed = 1'b1;
wire out, cout0, cout1;
reg sel, in_1, in_0;
reg pout;
assign cout0 = sel ? 1'bz : in_0;
assign cout1 = sel ? in_1: 1'bz;
assign out = sel ? in_1: in_0;
task automatic check;
input bit, in_1, in_0;
input [63:0] comment;
begin
if (sel === 1'b1) begin
if (bit !== in_1) begin
$display("FAILED: %0s sel = 1'b1, expected %b, got %b",
comment, in_1, bit);
passed = 1'b0;
end
end else if (sel === 1'b0) begin
if (bit !== in_0) begin
$display("FAILED: %0s sel = 1'b0, expected %b, got %b",
comment, in_0, bit);
passed = 1'b0;
end
end else begin
// This is technically incorrect for 1'bz inputs. The standard
// states that we should produce 1'bx for that case (idiotic)!
if (in_0 === in_1 && in_0 !== bit) begin
$display("FAILED: %0s sel = 1'bx/z & ins = %b, expected 1'b%b, got %b",
comment, in_0, in_0, bit);
passed = 1'b0;
end else if (in_0 !== in_1 && bit !== 1'bx) begin
$display("FAILED: %0s sel = 1'bx/z & %b %b, expected 1'bx, got %b",
comment, in_1, in_0, bit);
passed = 1'b0;
end
end
end
endtask
// Check the 1 case as a constant Z
always @(cout0) begin
check(cout0, 1'bz, in_0, "CZ 1");
end
// Check the 0 case as a constant Z
always @(cout1) begin
check(cout1, in_1, 1'bz, "CZ 0");
end
// Check the continuous assign
always @(out) begin
check(out, in_1, in_0, "CA");
end
// Check procedural assign.
always @(sel, in_1, in_0) begin
check(sel ? in_1 : in_0, in_1, in_0, "PR");
end
initial begin
#1 sel = 1'b1;
#1 in_1 = 1'b0;
#1 in_1 = 1'b1;
#1 in_1 = 1'bz;
#1 in_1 = 1'bx;
#1 sel = 1'b0;
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bx;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 sel = 1'bz;
#1 in_1 = 1'b0; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'b1; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bz; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 in_1 = 1'bx; //
#1 in_0 = 1'b0;
#1 in_0 = 1'b1;
#1 in_0 = 1'bz;
#1 in_0 = 1'bx;
#1 if (passed) $display("PASSED");
end
endmodule
|
module RAMDP(clock,reset,we,addr0,addr1,data_i,data_o0,data_o1);
parameter AddrSize = 8;
parameter DataSize = 8;
input wire clock;
input wire reset;
input wire we;
input wire [AddrSize-1:0] addr0;
input wire [AddrSize-1:0] addr1;
input wire [DataSize-1:0] data_i;
`ifdef SIM
output reg [DataSize-1:0] data_o0;
output reg [DataSize-1:0] data_o1;
reg [DataSize-1:0] s_Data[2**AddrSize-1:0];
reg [AddrSize:0] k;
initial begin
for (k = 0; k < 2**AddrSize; k = k + 1) begin
s_Data[k] = 0;
end
end
always @ (posedge clock) begin
if (reset) begin
data_o0 <= 0;
data_o1 <= 0;
end
else begin
if (we) begin
s_Data[addr0] <= data_i;
end
data_o0 <= s_Data[addr0];
data_o1 <= s_Data[addr1];
end
end // always @ (posedge clock)
`endif // `ifdef SIM
`ifdef FPGA
output wire [DataSize-1:0] data_o0;
output wire [DataSize-1:0] data_o1;
RAMB16_S1_S1
ramse (.CLKA(clock),
.CLKB(clock),
.SSRA(reset),
.SSRB(reset),
.ENA(~reset),
.WEA(we),
.ADDRA(addr0),
.DIA(data_i),
.DOA(data_o0),
.ENB(~reset),
.WEB(0),
.ADDRB(addr1),
.DIB(1'b0),
.DOB(data_o1));
`endif
endmodule // RAMDP
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O221AI_PP_BLACKBOX_V
/**
* o221ai: 2-input OR into first two inputs of 3-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o221ai (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221AI_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A2111OI_PP_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a2111oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
input D1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_BLACKBOX_V
`define SKY130_FD_SC_MS__O21A_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o21a (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb4to1 (
//# {{data|Data Signals}}
input [3:0] D,
output Z,
//# {{control|Control Signals}}
input [3:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 07/07/2016 09:24:55 AM
// Design Name:
// Module Name: Deslinealizador
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module DESLINEALIZADOR#(parameter P = 32)(
input wire CLK, //system clock
input wire [P-1:0] T, //VALOR DEL ARGUMENTO DEL EXPONENCIAL QUE SE DESEA CALCULAR
input wire RST_EX, //system reset
input wire Begin_FSM_EX, //INICIAL EL CALCULO
output wire ACK_EX, //INDICA QUE EL CALCULO FUE REALIZADO
output wire ACK_SUMX,
output wire ACK_SUMY,
output wire ACK_SUMZ,
output wire ACK_MULT,
output wire O_FX, //BANDERA DE OVER FLOW X
output wire O_FY, //BANDERA DE OVER FLOW Y
output wire O_FZ, //BANDERA DE OVER FLOW Z
output wire O_Fmult, //BANDERA DE OVER FLOW MULT
output wire U_FX, //BANDERA DE UNDER FLOW X
output wire U_FY, //BANDERA DE UNDER FLOW Y
output wire U_FZ, //BANDERA DE UNDER FLOW Z
output wire U_Fmult, //BANDERA DE UNDER FLOW MULT
output wire [P-1:0] RESULT //RESULTADO FINAL
);
wire [4:0] CONT_ITERA;
wire RST;
wire MS_1;
wire [1:0] MS_M;
wire EN_REG3;
wire EN_REG4;
wire ADD_SUBT;
wire Begin_SUMX;
wire Begin_SUMY;
wire Begin_SUMZ;
wire Begin_MULT;
wire EN_REG1X;
wire EN_REG1Y;
wire EN_REG1Z;
wire [1:0] MS_2;
wire EN_REG2;
wire CLK_CDIR;
wire EN_REG2XYZ;
// wire ACK_SUMX;
// wire ACK_SUMY;
// wire ACK_SUMZ;
wire EN_MS1;
wire EN_MS2;
wire EN_MS_M;
wire EN_ADDSUBT;
wire [1:0] MS_M_reg;
wire MS_1_reg;
wire [1:0] MS_2_reg;
wire ADD_SUBT_reg;
assign BeginSUMX = Begin_SUMX;
assign BeginSUMY = Begin_SUMY;
assign BeginSUMZ = Begin_SUMZ;
assign BeginMULT = Begin_MULT;
//assign MS_Mreg = MS_M_reg;
//assign MS_1reg = MS_1_reg;
//assign MS_2reg = MS_2_reg;
Coprocesador_CORDIC C_CORDIC_EX (
.T(T),
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST),
.MS_M(MS_M_reg),
.MS_1(MS_1_reg),
.EN_REG3(EN_REG3),
.EN_REG4(EN_REG4),
.ADD_SUBT(ADD_SUBT_reg),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.Begin_MULT(Begin_MULT),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2_reg),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_SUMX(ACK_SUMX),
.ACK_SUMY(ACK_SUMY),
.ACK_SUMZ(ACK_SUMZ),
.ACK_MULT(ACK_MULT),
.O_FX(O_FX),
.U_FX(U_FX),
.O_FY(O_FY),
.U_FY(U_FY),
.O_FZ(O_FZ),
.U_FZ(U_FZ),
.O_Fmult(O_Fmult),
.U_Fmult(U_Fmult),
.RESULT(RESULT),
.CONT_ITERA(CONT_ITERA)
);
FF_D #(.P(1)) REG_ADDSUBTL( //#(.P(1))
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_ADDSUBT), //ENABLE
.D(ADD_SUBT), //ENTRADA
.Q(ADD_SUBT_reg) //SALIDA
);
FF_D #(.P(2)) REG_MS_M(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS_M), //ENABLE
.D(MS_M), //ENTRADA
.Q(MS_M_reg) //SALIDA
);
FF_D #(.P(1)) REG_MS_1(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS1), //ENABLE
.D(MS_1), //ENTRADA
.Q(MS_1_reg) //SALIDA
);
FF_D #(.P(2)) REG_MS_2(
.CLK(CLK), //RELOJ DEL SISTEMA
.RST(RST), //RESET
.EN(EN_MS2), //ENABLE
.D(MS_2), //ENTRADA
.Q(MS_2_reg) //SALIDA
);
FSM_C_CORDIC M_E_EX (
.CLK(CLK), //RELOJ DEL SISTEMA
.RST_EX(RST_EX), //system reset
.ACK_ADD_SUBTX(ACK_SUMX),
.ACK_ADD_SUBTY(ACK_SUMY),
.ACK_ADD_SUBTZ(ACK_SUMZ),
.ACK_MULT(ACK_MULT),
.Begin_FSM_EX(Begin_FSM_EX),
.CONT_ITER(CONT_ITERA),
.RST(RST),
.MS_M(MS_M),
.MS_1(MS_1),
.EN_REG3(EN_REG3),
.EN_REG4(EN_REG4),
.ADD_SUBT(ADD_SUBT),
.Begin_SUMX(Begin_SUMX),
.Begin_SUMY(Begin_SUMY),
.Begin_SUMZ(Begin_SUMZ),
.Begin_MULT(Begin_MULT),
.EN_REG1X(EN_REG1X),
.EN_REG1Y(EN_REG1Y),
.EN_REG1Z(EN_REG1Z),
.MS_2(MS_2),
.EN_REG2(EN_REG2),
.CLK_CDIR(CLK_CDIR),
.EN_REG2XYZ(EN_REG2XYZ),
.ACK_EX(ACK_EX),
.EN_ADDSUBT(EN_ADDSUBT),
.EN_MS_M(EN_MS_M),
.EN_MS1(EN_MS1),
.EN_MS2(EN_MS2)
);
endmodule
|
//======================================================================
//
// tb_hc.v
// --------
// Testbench for the hc top level wrapper.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
//------------------------------------------------------------------
// Test module.
//------------------------------------------------------------------
module tb_hc();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
// The DUT address map.
parameter ADDR_NAME0 = 8'h00;
parameter ADDR_NAME1 = 8'h01;
parameter ADDR_VERSION = 8'h02;
parameter ADDR_CTRL = 8'h08;
parameter CTRL_INIT_BIT = 0;
parameter CTRL_NEXT_BIT = 1;
parameter CTRL_ENCDEC_BIT = 2;
parameter CTRL_KEYLEN_BIT = 3;
parameter ADDR_STATUS = 8'h09;
parameter STATUS_READY_BIT = 0;
parameter STATUS_VALID_BIT = 1;
parameter ADDR_CONFIG = 8'h0a;
parameter ADDR_KEY0 = 8'h10;
parameter ADDR_KEY1 = 8'h11;
parameter ADDR_KEY2 = 8'h12;
parameter ADDR_KEY3 = 8'h13;
parameter ADDR_KEY4 = 8'h14;
parameter ADDR_KEY5 = 8'h15;
parameter ADDR_KEY6 = 8'h16;
parameter ADDR_KEY7 = 8'h17;
parameter ADDR_BLOCK0 = 8'h20;
parameter ADDR_BLOCK1 = 8'h21;
parameter ADDR_BLOCK2 = 8'h22;
parameter ADDR_BLOCK3 = 8'h23;
parameter ADDR_RESULT0 = 8'h30;
parameter ADDR_RESULT1 = 8'h31;
parameter ADDR_RESULT2 = 8'h32;
parameter ADDR_RESULT3 = 8'h33;
parameter HC_128_BIT_KEY = 0;
parameter HC_256_BIT_KEY = 1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg [31 : 0] read_data;
reg [127 : 0] result_data;
reg tb_clk;
reg tb_reset_n;
reg tb_cs;
reg tb_we;
reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
hc dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.cs(tb_cs),
.we(tb_we),
.address(tb_address),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("cycle: 0x%016x", cycle_ctr);
$display("State of DUT");
$display("------------");
// $display("ctrl_reg: init = 0x%01x, next = 0x%01x", dut.init_reg, dut.next_reg);
// $display("config_reg: encdec = 0x%01x, length = 0x%01x ", dut.encdec_reg, dut.keylen_reg);
// $display("");
//
// $display("block: 0x%08x, 0x%08x, 0x%08x, 0x%08x",
// dut.block_reg[0], dut.block_reg[1], dut.block_reg[2], dut.block_reg[3]);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
$display("");
end
endtask // reset_dut
//----------------------------------------------------------------
// display_test_results()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_results;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_results
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_cs = 0;
tb_we = 0;
tb_address = 8'h0;
tb_write_data = 32'h0;
end
endtask // init_sim
//----------------------------------------------------------------
// write_word()
//
// Write the given word to the DUT using the DUT interface.
//----------------------------------------------------------------
task write_word(input [11 : 0] address,
input [31 : 0] word);
begin
if (DEBUG)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
end
tb_address = address;
tb_write_data = word;
tb_cs = 1;
tb_we = 1;
#(2 * CLK_PERIOD);
tb_cs = 0;
tb_we = 0;
end
endtask // write_word
//----------------------------------------------------------------
// write_block()
//
// Write the given block to the dut.
//----------------------------------------------------------------
task write_block(input [127 : 0] block);
begin
write_word(ADDR_BLOCK0, block[127 : 96]);
write_word(ADDR_BLOCK1, block[95 : 64]);
write_word(ADDR_BLOCK2, block[63 : 32]);
write_word(ADDR_BLOCK3, block[31 : 0]);
end
endtask // write_block
//----------------------------------------------------------------
// read_word()
//
// Read a data word from the given address in the DUT.
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
task read_word(input [11 : 0] address);
begin
tb_address = address;
tb_cs = 1;
tb_we = 0;
#(CLK_PERIOD);
read_data = tb_read_data;
tb_cs = 0;
if (DEBUG)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
end
end
endtask // read_word
//----------------------------------------------------------------
// read_result()
//
// Read the result block in the dut.
//----------------------------------------------------------------
task read_result;
begin
read_word(ADDR_RESULT0);
result_data[127 : 096] = read_data;
read_word(ADDR_RESULT1);
result_data[095 : 064] = read_data;
read_word(ADDR_RESULT2);
result_data[063 : 032] = read_data;
read_word(ADDR_RESULT3);
result_data[031 : 000] = read_data;
end
endtask // read_result
//----------------------------------------------------------------
// init_key()
//
// init the key in the dut by writing the given key and
// key length and then trigger init processing.
//----------------------------------------------------------------
task init_key(input [255 : 0] key, input key_length);
begin
if (DEBUG)
begin
$display("key length: 0x%01x", key_length);
$display("Initializing key expansion for key: 0x%016x", key);
end
write_word(ADDR_KEY0, key[255 : 224]);
write_word(ADDR_KEY1, key[223 : 192]);
write_word(ADDR_KEY2, key[191 : 160]);
write_word(ADDR_KEY3, key[159 : 128]);
write_word(ADDR_KEY4, key[127 : 96]);
write_word(ADDR_KEY5, key[95 : 64]);
write_word(ADDR_KEY6, key[63 : 32]);
write_word(ADDR_KEY7, key[31 : 0]);
if (key_length)
begin
write_word(ADDR_CONFIG, 8'h02);
end
else
begin
write_word(ADDR_CONFIG, 8'h00);
end
write_word(ADDR_CTRL, 8'h01);
#(100 * CLK_PERIOD);
end
endtask // init_key
//----------------------------------------------------------------
// hc_test()
//
// Main test task will perform complete NIST test of HC.
//----------------------------------------------------------------
task hc_test;
begin
$display("HC 128 bit key tests");
$display("---------------------");
$display("");
$display("HC 256 bit key tests");
$display("---------------------");
$display("");
end
endtask // hc_test
//----------------------------------------------------------------
// main
//
// The main test functionality.
//----------------------------------------------------------------
initial
begin : main
$display(" -= Testbench for HC started =-");
$display(" =============================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
hc_test();
display_test_results();
$display("");
$display("*** HC simulation done. ***");
$finish;
end // main
endmodule // tb_hc
//======================================================================
// EOF tb_hc.v
//======================================================================
|
// Cache Memory (default : 8way 4word) //
// cache configuration can be changed by change and cache_config port //
// i_ means input port //
// o_ means output port //
// _p_ means data exchange with processor //
// _m_ means data exchange with memory //
// Replacement policy is pseudo LRU (7bit) //
`default_nettype none
module cache(clk,
rst,
i_p_addr,
i_p_byte_en,
i_p_writedata,
i_p_read,
i_p_write,
o_p_readdata,
o_p_readdata_valid,
o_p_waitrequest,
o_m_addr,
o_m_byte_en,
o_m_writedata,
o_m_read,
o_m_write,
i_m_readdata,
i_m_readdata_valid,
i_m_waitrequest,
cnt_r,
cnt_w,
cnt_hit_r,
cnt_hit_w,
cnt_wb_r,
cnt_wb_w,
cache_config,
change);
parameter cache_entry = 9;
input wire clk, rst;
input wire [24:0] i_p_addr;
input wire [3:0] i_p_byte_en;
input wire [31:0] i_p_writedata;
input wire i_p_read, i_p_write;
output reg [31:0] o_p_readdata;
output reg o_p_readdata_valid;
output wire o_p_waitrequest;
output reg [25:0] o_m_addr;
output wire [3:0] o_m_byte_en;
output reg [127:0] o_m_writedata;
output reg o_m_read, o_m_write;
input wire [127:0] i_m_readdata;
input wire i_m_readdata_valid;
input wire i_m_waitrequest;
output reg [31:0] cnt_r;
output reg [31:0] cnt_w;
output reg [31:0] cnt_hit_r;
output reg [31:0] cnt_hit_w;
output reg [31:0] cnt_wb_r;
output reg [31:0] cnt_wb_w;
input wire [3:0] cache_config;
input wire change;
wire [7:0] hit;
wire [7:0] modify;
wire [7:0] miss;
wire [7:0] valid;
wire [127:0] readdata0, readdata1, readdata2, readdata3;
wire [127:0] readdata4, readdata5, readdata6, readdata7;
wire [127:0] writedata;
wire write0, write1, write2, write3;
wire write4, write5, write6, write7;
wire [3:0] word_en;
wire [3:0] byte_en;
wire [22:0] addr;
wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
wire [7:0] r_cm_data;
wire [3:0] hit_num;
wire [3:0] invalid_num;
reg [3:0] state;
reg [127:0] writedata_buf;
reg [24:0] write_addr_buf;
reg [3:0] byte_en_buf;
reg write_buf, read_buf;
reg [7:0] write_set;
reg [7:0] fetch_write;
reg [7:0] w_cm_data;
reg w_cm;
wire [2:0] replace;
reg [1:0] flash;
reg [3:0] phase;
reg [cache_entry:0] flash_cnt;
wire [7:0] dirty;
reg [3:0] current_config;
localparam IDLE = 0;
localparam COMP = 1;
localparam HIT = 2;
localparam FETCH1 = 3;
localparam FETCH2 = 4;
localparam FETCH3 = 5;
localparam WB1 = 6;
localparam WB2 = 7;
localparam FLASH = 8;
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_hot.mem[i] = 0;
end
end
`endif
simple_ram #(.width(8), .widthad(cache_entry)) ram_hot(clk, addr[cache_entry-1:0], w_cm, w_cm_data, addr[cache_entry-1:0], r_cm_data);
config_ctrl #(.cache_entry(cache_entry))
config_ctrl(.clk(clk),
.rst(rst),
.entry(addr[cache_entry-1:0]),
.o_tag(addr[22:cache_entry]),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en),
.write({write7, write6, write5, write4, write3, write2, write1, write0}),
.readdata0(readdata0),
.readdata1(readdata1),
.readdata2(readdata2),
.readdata3(readdata3),
.readdata4(readdata4),
.readdata5(readdata5),
.readdata6(readdata6),
.readdata7(readdata7),
.wb_addr0(wb_addr0),
.wb_addr1(wb_addr1),
.wb_addr2(wb_addr2),
.wb_addr3(wb_addr3),
.wb_addr4(wb_addr4),
.wb_addr5(wb_addr5),
.wb_addr6(wb_addr6),
.wb_addr7(wb_addr7),
.hit(hit),
.miss(miss),
.dirty(dirty),
.valid(valid),
.read_miss(read_buf),
.flash(flash),
.c_fig(current_config)
);
assign writedata = (|fetch_write) ? i_m_readdata : writedata_buf; //128bit
assign write0 = (fetch_write[0]) ? i_m_readdata_valid : write_set[0];
assign write1 = (fetch_write[1]) ? i_m_readdata_valid : write_set[1];
assign write2 = (fetch_write[2]) ? i_m_readdata_valid : write_set[2];
assign write3 = (fetch_write[3]) ? i_m_readdata_valid : write_set[3];
assign write4 = (fetch_write[4]) ? i_m_readdata_valid : write_set[4];
assign write5 = (fetch_write[5]) ? i_m_readdata_valid : write_set[5];
assign write6 = (fetch_write[6]) ? i_m_readdata_valid : write_set[6];
assign write7 = (fetch_write[7]) ? i_m_readdata_valid : write_set[7];
assign addr = (state == FLASH) ? {write_addr_buf[24:cache_entry+2], flash_cnt[cache_entry-1:0]} :
(o_p_waitrequest) ? write_addr_buf[24:2] : i_p_addr[24:2]; // set module input addr is 23bit
assign byte_en = (|fetch_write) ? 4'b1111 : byte_en_buf;
assign o_p_waitrequest = (state != IDLE);
assign o_m_byte_en = 4'b1111;
assign hit_num = (hit[0]) ? 0 :
(hit[1]) ? 1 :
(hit[2]) ? 2 :
(hit[3]) ? 3 :
(hit[4]) ? 4 :
(hit[5]) ? 5 :
(hit[6]) ? 6 : 7;
assign invalid_num = (!valid[0]) ? 0 :
(!valid[1]) ? 1 :
(!valid[2]) ? 2 :
(!valid[3]) ? 3 :
(!valid[4]) ? 4 :
(!valid[5]) ? 5 :
(!valid[6]) ? 6 : 7;
assign word_en = (|fetch_write) ? 4'b1111 :
(write_addr_buf[1:0] == 2'b00) ? 4'b0001 :
(write_addr_buf[1:0] == 2'b01) ? 4'b0010 :
(write_addr_buf[1:0] == 2'b10) ? 4'b0100 : 4'b1000;
assign replace = (current_config) ? {1'b0, r_cm_data[1:0]} :
(r_cm_data[6]) ? ((r_cm_data[4]) ? ((r_cm_data[0]) ? 7 : 6) : ((r_cm_data[1]) ? 5 : 4)) :
((r_cm_data[5]) ? ((r_cm_data[2]) ? 3 : 2) : ((r_cm_data[3]) ? 1 : 0));
always @(posedge clk) begin
if(current_config == 4'b0000) begin
if(hit) begin
case(hit_num)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else if(!(&valid)) begin
case(invalid_num)
// 0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
0: w_cm_data <= 8'b01101000;
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end else begin
case(replace)
0: w_cm_data <= {3'b011, r_cm_data[4], 1'b1, r_cm_data[2:0]};
1: w_cm_data <= {3'b011, r_cm_data[4], 1'b0, r_cm_data[2:0]};
2: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b1, r_cm_data[1:0]};
3: w_cm_data <= {3'b010, r_cm_data[4:3], 1'b0, r_cm_data[1:0]};
4: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b1, r_cm_data[0]};
5: w_cm_data <= {2'b00, r_cm_data[5], 1'b1, r_cm_data[3:2], 1'b0, r_cm_data[0]};
6: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b1};
7: w_cm_data <= {2'b00, r_cm_data[5], 1'b0, r_cm_data[3:1], 1'b0};
endcase
end
end else if(current_config == 4'b0001) begin
if(hit) begin
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == hit_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == hit_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
end else if(!(&valid)) begin
if(!valid[0]) w_cm_data <= 8'b00111001;
else begin
w_cm_data <= (r_cm_data[1:0] == invalid_num) ? {r_cm_data[1:0], r_cm_data[7:2]} :
(r_cm_data[3:2] == invalid_num) ? {r_cm_data[3:2], r_cm_data[7:4], r_cm_data[1:0]} :
(r_cm_data[5:4] == invalid_num) ? {r_cm_data[5:4], r_cm_data[7:6], r_cm_data[3:0]} : r_cm_data;
end
end else begin
w_cm_data <= {r_cm_data[1:0], r_cm_data[7:2]};
end
end else if(current_config == 4'b0010) begin
if(hit) begin
w_cm_data <= (r_cm_data[1:0] == hit_num) ? {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]} : r_cm_data;
end else if(!(&valid)) begin
if(!valid[0]) w_cm_data <= 8'b11100001;
else begin
w_cm_data <= (r_cm_data[1:0] == invalid_num) ? {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]} : r_cm_data;
end
end else begin
w_cm_data <= {r_cm_data[7:4], r_cm_data[1:0], r_cm_data[3:2]};
end
end
end
always @(posedge clk) begin
if(rst) begin
o_p_readdata_valid <= 0;
{o_m_read, o_m_write} <= 0;
o_m_addr <= 0;
write_addr_buf <= 0;
byte_en_buf <= 0;
writedata_buf <= 0;
{write_buf, read_buf} <= 0;
write_set <= 0;
fetch_write <= 0;
flash <= 0;
phase <= 0;
flash_cnt <= 0;
current_config <= 0; // default cache config is 4way
w_cm <= 0;
{cnt_r, cnt_w} <= 0;
{cnt_hit_r, cnt_hit_w} <= 0;
{cnt_wb_r, cnt_wb_w} <= 0;
state <= IDLE;
end
else begin
case (state)
IDLE: begin
write_set <= 0;
o_p_readdata_valid <= 0;
writedata_buf <= {i_p_writedata, i_p_writedata, i_p_writedata, i_p_writedata};
write_addr_buf <= i_p_addr;
byte_en_buf <= i_p_byte_en;
write_buf <= i_p_write;
read_buf <= i_p_read;
if(i_p_read) begin
state <= COMP;
cnt_r <= cnt_r + 1;
end else if(i_p_write) begin
state <= COMP;
cnt_w <= cnt_w + 1;
end else if(change) begin
state <= FLASH;
flash <= 2'b10;
phase <= 0;
end
end
COMP: begin
if((|hit) && write_buf) begin
state <= HIT;
w_cm <= 1;
write_set <= hit;
cnt_hit_w <= cnt_hit_w + 1;
end else if((|hit) && read_buf) begin
state <= IDLE;
w_cm <= 1;
o_p_readdata_valid <= 1;
cnt_hit_r <= cnt_hit_r + 1;
case(write_addr_buf[1:0])
2'b00: begin
o_p_readdata <= (hit[0]) ? readdata0[31:0] :
(hit[1]) ? readdata1[31:0] :
(hit[2]) ? readdata2[31:0] :
(hit[3]) ? readdata3[31:0] :
(hit[4]) ? readdata4[31:0] :
(hit[5]) ? readdata5[31:0] :
(hit[6]) ? readdata6[31:0] : readdata7[31:0];
end
2'b01: begin
o_p_readdata <= (hit[0]) ? readdata0[63:32] :
(hit[1]) ? readdata1[63:32] :
(hit[2]) ? readdata2[63:32] :
(hit[3]) ? readdata3[63:32] :
(hit[4]) ? readdata4[63:32] :
(hit[5]) ? readdata5[63:32] :
(hit[6]) ? readdata6[63:32] : readdata7[63:32];
end
2'b10: begin
o_p_readdata <= (hit[0]) ? readdata0[95:64] :
(hit[1]) ? readdata1[95:64] :
(hit[2]) ? readdata2[95:64] :
(hit[3]) ? readdata3[95:64] :
(hit[4]) ? readdata4[95:64] :
(hit[5]) ? readdata5[95:64] :
(hit[6]) ? readdata6[95:64] : readdata7[95:64];
end
2'b11: begin
o_p_readdata <= (hit[0]) ? readdata0[127:96] :
(hit[1]) ? readdata1[127:96] :
(hit[2]) ? readdata2[127:96] :
(hit[3]) ? readdata3[127:96] :
(hit[4]) ? readdata4[127:96] :
(hit[5]) ? readdata5[127:96] :
(hit[6]) ? readdata6[127:96] : readdata7[127:96];
end
endcase
end else if(!(&valid)) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(invalid_num)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else if(miss[replace]) begin
state <= FETCH1;
w_cm <= 1;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
end else begin
state <= WB1;
w_cm <= 1;
case(replace)
0: fetch_write <= 8'b00000001;
1: fetch_write <= 8'b00000010;
2: fetch_write <= 8'b00000100;
3: fetch_write <= 8'b00001000;
4: fetch_write <= 8'b00010000;
5: fetch_write <= 8'b00100000;
6: fetch_write <= 8'b01000000;
7: fetch_write <= 8'b10000000;
endcase
if(read_buf) cnt_wb_r <= cnt_wb_r + 1;
else if(write_buf) cnt_wb_w <= cnt_wb_w + 1;
end
end
HIT: begin
w_cm <= 0;
write_set <= 0;
state <= IDLE;
end
FETCH1: begin
w_cm <= 0;
if(!i_m_waitrequest) begin
o_m_read <= 0;
state <= FETCH2;
end
end
FETCH2: begin
if(i_m_readdata_valid) begin
fetch_write <= 0; //add 3/9
if(write_buf) begin
state <= FETCH3;
write_set <= fetch_write;
end else if(read_buf) begin
state <= IDLE;
o_p_readdata_valid <= 1;
case(write_addr_buf[1:0])
2'b00: o_p_readdata <= i_m_readdata[ 31: 0];
2'b01: o_p_readdata <= i_m_readdata[ 63:32];
2'b10: o_p_readdata <= i_m_readdata[ 95:64];
2'b11: o_p_readdata <= i_m_readdata[127:96];
endcase
end
end
end
FETCH3: begin
state <= IDLE;
write_set <= 0;
end
WB1: begin
w_cm <= 0;
o_m_addr <= (fetch_write[0]) ? {wb_addr0, 3'b000} :
(fetch_write[1]) ? {wb_addr1, 3'b000} :
(fetch_write[2]) ? {wb_addr2, 3'b000} :
(fetch_write[3]) ? {wb_addr3, 3'b000} :
(fetch_write[4]) ? {wb_addr4, 3'b000} :
(fetch_write[5]) ? {wb_addr5, 3'b000} :
(fetch_write[6]) ? {wb_addr6, 3'b000} : {wb_addr7, 3'b000};
o_m_writedata <= (fetch_write[0]) ? readdata0 :
(fetch_write[1]) ? readdata1 :
(fetch_write[2]) ? readdata2 :
(fetch_write[3]) ? readdata3 :
(fetch_write[4]) ? readdata4 :
(fetch_write[5]) ? readdata5 :
(fetch_write[6]) ? readdata6 : readdata7;
o_m_write <= 1;
state <= WB2;
end
WB2: begin
if(!i_m_waitrequest) begin
o_m_write <= 0;
o_m_addr <= {write_addr_buf[24:2], 3'b000};
o_m_read <= 1;
state <= FETCH1;
end
end
FLASH: begin
if(!i_m_waitrequest) begin
if(flash_cnt[cache_entry] && !change) begin
state <= IDLE;
flash <= 0;
o_m_write <= 0;
flash_cnt <= 0;
current_config <= cache_config;
end else if(flash_cnt[cache_entry]) begin
flash <= 0;
o_m_write <= 0;
end else begin
phase <= (phase == 10) ? 0 : phase + 1;
case(phase)
0: o_m_write <= 0;
1: begin
if(dirty[0]) begin
o_m_addr <= {wb_addr0, 3'b000};
o_m_writedata <= readdata0;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
2: begin
if(dirty[1]) begin
o_m_addr <= {wb_addr1, 3'b000};
o_m_writedata <= readdata1;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
3: begin
if(dirty[2]) begin
o_m_addr <= {wb_addr2, 3'b000};
o_m_writedata <= readdata2;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
4: begin
if(dirty[3]) begin
o_m_addr <= {wb_addr3, 3'b000};
o_m_writedata <= readdata3;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
5: begin
if(dirty[4]) begin
o_m_addr <= {wb_addr4, 3'b000};
o_m_writedata <= readdata0;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
6: begin
if(dirty[5]) begin
o_m_addr <= {wb_addr5, 3'b000};
o_m_writedata <= readdata1;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
7: begin
if(dirty[6]) begin
o_m_addr <= {wb_addr6, 3'b000};
o_m_writedata <= readdata2;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
8: begin
if(dirty[7]) begin
o_m_addr <= {wb_addr7, 3'b000};
o_m_writedata <= readdata3;
o_m_write <= 1;
end else begin
o_m_write <= 0;
end
end
9: begin
o_m_write <= 0;
flash <= 2'b11;
end
10: begin
flash <= 2'b10;
flash_cnt <= flash_cnt + 1;
end
endcase
end
end
end
endcase // case (state)
end
end
endmodule // cache
module config_ctrl(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
word_en,
write,
readdata0,
readdata1,
readdata2,
readdata3,
readdata4,
readdata5,
readdata6,
readdata7,
wb_addr0,
wb_addr1,
wb_addr2,
wb_addr3,
wb_addr4,
wb_addr5,
wb_addr6,
wb_addr7,
hit,
miss,
dirty,
valid,
read_miss,
flash,
c_fig);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire [3:0] word_en;
input wire [7:0] write;
input wire read_miss;
input wire [1:0] flash;
input wire [3:0] c_fig;
output wire [127:0] readdata0, readdata1, readdata2, readdata3;
output wire [127:0] readdata4, readdata5, readdata6, readdata7;
output wire [22:0] wb_addr0, wb_addr1, wb_addr2, wb_addr3;
output wire [22:0] wb_addr4, wb_addr5, wb_addr6, wb_addr7;
output wire [7:0] hit, miss, dirty, valid;
wire [7:0] s_hit;
wire [7:0] s_miss;
wire [7:0] s_dirty;
wire [7:0] s_valid;
wire [127:0] s_readdata0, s_readdata1, s_readdata2, s_readdata3;
wire [127:0] s_readdata4, s_readdata5, s_readdata6, s_readdata7;
wire [22:0] s_wb_addr0, s_wb_addr1, s_wb_addr2, s_wb_addr3;
wire [22:0] s_wb_addr4, s_wb_addr5, s_wb_addr6, s_wb_addr7;
assign hit = (c_fig == 0) ? s_hit :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b0000, s_hit[7], s_hit[5], s_hit[3], s_hit[1]} :
{4'b0000, s_hit[6], s_hit[4], s_hit[2], s_hit[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b000000, s_hit[4], s_hit[0]} :
(o_tag[1:0] == 2'b01) ? {6'b000000, s_hit[5], s_hit[1]} :
(o_tag[1:0] == 2'b10) ? {6'b000000, s_hit[6], s_hit[2]} :
{6'b000000, s_hit[7], s_hit[3]}) : 8'b00000000;
assign miss = (c_fig == 0) ? s_miss :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b0000, s_miss[7], s_miss[5], s_miss[3], s_miss[1]} :
{4'b0000, s_miss[6], s_miss[4], s_miss[2], s_miss[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b000000, s_miss[4], s_miss[0]} :
(o_tag[1:0] == 2'b01) ? {6'b000000, s_miss[5], s_miss[1]} :
(o_tag[1:0] == 2'b10) ? {6'b000000, s_miss[6], s_miss[2]} :
{6'b000000, s_miss[7], s_miss[3]}) : 8'b00000000;
assign dirty = s_dirty;
assign valid = (c_fig == 0) ? s_valid :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {4'b1111, s_valid[7], s_valid[5], s_valid[3], s_valid[1]} :
{4'b1111, s_valid[6], s_valid[4], s_valid[2], s_valid[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {6'b111111, s_valid[4], s_valid[0]} :
(o_tag[1:0] == 2'b01) ? {6'b111111, s_valid[5], s_valid[1]} :
(o_tag[1:0] == 2'b10) ? {6'b111111, s_valid[6], s_valid[2]} :
{6'b111111, s_valid[7], s_valid[3]}) : 8'b00000000;
assign readdata0 = ((c_fig == 0) || flash[1]) ? s_readdata0 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata1 : s_readdata0) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_readdata0 :
(o_tag[1:0] == 2'b01) ? s_readdata1 :
(o_tag[1:0] == 2'b10) ? s_readdata2 : s_readdata3) : s_readdata0;
assign readdata1 = ((c_fig == 0) || flash[1]) ? s_readdata1 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata3 : s_readdata2) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_readdata4 :
(o_tag[1:0] == 2'b01) ? s_readdata5 :
(o_tag[1:0] == 2'b10) ? s_readdata6 : s_readdata7) : s_readdata1;
assign readdata2 = ((c_fig == 0) || flash[1]) ? s_readdata2 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata5 : s_readdata4) : readdata2;
assign readdata3 = ((c_fig == 0) || flash[1]) ? s_readdata3 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_readdata7 : s_readdata6) : readdata3;
assign readdata4 = s_readdata4;
assign readdata5 = s_readdata5;
assign readdata6 = s_readdata6;
assign readdata7 = s_readdata7;
assign wb_addr0 = ((c_fig == 0) || flash[1]) ? s_wb_addr0 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr1 : s_wb_addr0) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_wb_addr0 :
(o_tag[1:0] == 2'b01) ? s_wb_addr1 :
(o_tag[1:0] == 2'b10) ? s_wb_addr2 : s_wb_addr3) : s_wb_addr0;
assign wb_addr1 = ((c_fig == 0) || flash[1]) ? s_wb_addr1 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr3 : s_wb_addr2) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? s_wb_addr4 :
(o_tag[1:0] == 2'b01) ? s_wb_addr5 :
(o_tag[1:0] == 2'b10) ? s_wb_addr6 : s_wb_addr7) : s_wb_addr1;
assign wb_addr2 = ((c_fig == 0) || flash[1]) ? s_wb_addr2 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr5 : s_wb_addr4) : wb_addr2;
assign wb_addr3 = ((c_fig == 0) || flash[1]) ? s_wb_addr3 :
(c_fig == 4'b0001) ? ((o_tag[0]) ? s_wb_addr7 : s_wb_addr6) : wb_addr3;
assign wb_addr4 = s_wb_addr4;
assign wb_addr5 = s_wb_addr5;
assign wb_addr6 = s_wb_addr6;
assign wb_addr7 = s_wb_addr7;
wire [7:0] s_write;
assign s_write = (c_fig == 0) ? write :
(c_fig == 4'b0001) ? ((o_tag[0]) ? {write[3], 1'b0, write[2], 1'b0, write[1], 1'b0, write[0], 1'b0} :
{1'b0, write[3], 1'b0, write[2], 1'b0, write[1], 1'b0, write[0]}) :
(c_fig == 4'b0010) ? ((o_tag[1:0] == 2'b00) ? {3'b000, write[1], 3'b000, write[0]} :
(o_tag[1:0] == 2'b01) ? {2'b00, write[1], 3'b000, write[0], 1'b0} :
(o_tag[1:0] == 2'b10) ? {1'b0, write[1], 3'b000, write[0], 2'b00} : {write[1], 3'b000, write[0], 3'b000}) : 8'b00000000;
set #(.cache_entry(cache_entry))
set0(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[0]),
.readdata(s_readdata0),
.wb_addr(s_wb_addr0),
.hit(s_hit[0]),
.miss(s_miss[0]),
.dirty(s_dirty[0]),
.valid(s_valid[0]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set1(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[1]),
.readdata(s_readdata1),
.wb_addr(s_wb_addr1),
.hit(s_hit[1]),
.miss(s_miss[1]),
.dirty(s_dirty[1]),
.valid(s_valid[1]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set2(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[2]),
.readdata(s_readdata2),
.wb_addr(s_wb_addr2),
.hit(s_hit[2]),
.miss(s_miss[2]),
.dirty(s_dirty[2]),
.valid(s_valid[2]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set3(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[3]),
.readdata(s_readdata3),
.wb_addr(s_wb_addr3),
.hit(s_hit[3]),
.miss(s_miss[3]),
.dirty(s_dirty[3]),
.valid(s_valid[3]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set4(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[4]),
.readdata(s_readdata4),
.wb_addr(s_wb_addr4),
.hit(s_hit[4]),
.miss(s_miss[4]),
.dirty(s_dirty[4]),
.valid(s_valid[4]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set5(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[5]),
.readdata(s_readdata5),
.wb_addr(s_wb_addr5),
.hit(s_hit[5]),
.miss(s_miss[5]),
.dirty(s_dirty[5]),
.valid(s_valid[5]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set6(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[6]),
.readdata(s_readdata6),
.wb_addr(s_wb_addr6),
.hit(s_hit[6]),
.miss(s_miss[6]),
.dirty(s_dirty[6]),
.valid(s_valid[6]),
.read_miss(read_miss),
.flash(flash[0]));
set #(.cache_entry(cache_entry))
set7(.clk(clk),
.rst(rst),
.entry(entry),
.o_tag(o_tag),
.writedata(writedata),
.byte_en(byte_en),
.word_en(word_en), // 4word r/w change
.write(s_write[7]),
.readdata(s_readdata7),
.wb_addr(s_wb_addr7),
.hit(s_hit[7]),
.miss(s_miss[7]),
.dirty(s_dirty[7]),
.valid(s_valid[7]),
.read_miss(read_miss),
.flash(flash[0]));
endmodule // config_ctrl
module set(clk,
rst,
entry,
o_tag,
writedata,
byte_en,
write,
word_en,
readdata,
wb_addr,
hit,
miss,
dirty,
valid,
read_miss,
flash);
parameter cache_entry = 14;
input wire clk, rst;
input wire [cache_entry-1:0] entry;
input wire [22-cache_entry:0] o_tag;
input wire [127:0] writedata;
input wire [3:0] byte_en;
input wire write;
input wire [3:0] word_en;
input wire read_miss;
input wire flash;
output wire [127:0] readdata;
output wire [22:0] wb_addr;
output wire hit, miss, dirty, valid;
wire [22-cache_entry:0] i_tag;
wire modify;
wire [24-cache_entry:0] write_tag_data;
assign hit = valid && (o_tag == i_tag);
assign modify = valid && (o_tag != i_tag) && dirty;
assign miss = !valid || ((o_tag != i_tag) && !dirty);
assign wb_addr = {i_tag, entry};
//write -> [3:0] write, writedata/readdata 32bit -> 128bit
simple_ram #(.width(8), .widthad(cache_entry)) ram11_3(clk, entry, write && word_en[3] && byte_en[3], writedata[127:120], entry, readdata[127:120]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_2(clk, entry, write && word_en[3] && byte_en[2], writedata[119:112], entry, readdata[119:112]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_1(clk, entry, write && word_en[3] && byte_en[1], writedata[111:104], entry, readdata[111:104]);
simple_ram #(.width(8), .widthad(cache_entry)) ram11_0(clk, entry, write && word_en[3] && byte_en[0], writedata[103:96], entry, readdata[103:96]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_3(clk, entry, write && word_en[2] && byte_en[3], writedata[95:88], entry, readdata[95:88]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_2(clk, entry, write && word_en[2] && byte_en[2], writedata[87:80], entry, readdata[87:80]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_1(clk, entry, write && word_en[2] && byte_en[1], writedata[79:72], entry, readdata[79:72]);
simple_ram #(.width(8), .widthad(cache_entry)) ram10_0(clk, entry, write && word_en[2] && byte_en[0], writedata[71:64], entry, readdata[71:64]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_3(clk, entry, write && word_en[1] && byte_en[3], writedata[63:56], entry, readdata[63:56]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_2(clk, entry, write && word_en[1] && byte_en[2], writedata[55:48], entry, readdata[55:48]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_1(clk, entry, write && word_en[1] && byte_en[1], writedata[47:40], entry, readdata[47:40]);
simple_ram #(.width(8), .widthad(cache_entry)) ram01_0(clk, entry, write && word_en[1] && byte_en[0], writedata[39:32], entry, readdata[39:32]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_3(clk, entry, write && word_en[0] && byte_en[3], writedata[31:24], entry, readdata[31:24]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_2(clk, entry, write && word_en[0] && byte_en[2], writedata[23:16], entry, readdata[23:16]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_1(clk, entry, write && word_en[0] && byte_en[1], writedata[15: 8], entry, readdata[15:8]);
simple_ram #(.width(8), .widthad(cache_entry)) ram00_0(clk, entry, write && word_en[0] && byte_en[0], writedata[ 7: 0], entry, readdata[ 7:0]);
assign write_tag_data = (flash) ? {1'b0, 1'b0, i_tag} :
(read_miss) ? {1'b0, 1'b1, o_tag} :
(modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
// assign write_tag_data = (read_miss) ? {1'b0, 1'b1, o_tag} : (modify || miss ) ? {1'b1, 1'b1, o_tag} : {1'b1, 1'b1, i_tag};
simple_ram #(.width(25-cache_entry), .widthad(cache_entry)) ram_tag(clk, entry, (write || flash), write_tag_data, entry, {dirty, valid, i_tag});
`ifdef SIM
integer i;
initial begin
for(i = 0; i <=(2**cache_entry-1); i=i+1) begin
ram_tag.mem[i] = 0;
end
end
`endif
endmodule
|
// ledtest_mm_interconnect_0_avalon_st_adapter.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 17.0 595
`timescale 1 ps / 1 ps
module ledtest_mm_interconnect_0_avalon_st_adapter #(
parameter inBitsPerSymbol = 34,
parameter inUsePackets = 0,
parameter inDataWidth = 34,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 34,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [33:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [33:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 34)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
ledtest_mm_interconnect_0_avalon_st_adapter_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__NAND4B_FUNCTIONAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4B_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_BLACKBOX_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1
* UDP_OUT :=UDP_IN when VPWR==1
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood_pp$P (
UDP_OUT,
UDP_IN ,
VPWR
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_PP_P_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:07:30 07/02/2014
// Design Name: FONT5_base
// Module Name: H:/Firmware/FONT5_base/ISE13/FONT5_base/font5_base_TB.v
// Project Name: FONT5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: FONT5_base
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module RebeccaTB;
//`include "H:\Firmware\FONT5_base\sources\verilog\definitions.vh"
parameter CH1_BITFLIP = (13'b1011010000101 ^ -13'sd4096);
parameter CH2_BITFLIP = (13'b0101110001000 ^ -13'sd4096);
parameter CH4_BITFLIP = (13'b0111100000000 ^ -13'sd4096);
parameter CH5_BITFLIP = (13'b0100110011010 ^ -13'sd4096);
//assign ch3_bitflip = 13'b0001011110100;
// Inputs
reg clk357;
reg clk40;
reg clk40_ibufg;
reg signed [12:0] ch1_data_in_del;
reg signed [12:0] ch2_data_in_del;
reg [12:0] ch3_data_in_del;
reg [12:0] ch4_data_in_del;
reg [12:0] ch5_data_in_del;
reg [12:0] ch6_data_in_del;
reg [12:0] ch7_data_in_del;
reg [12:0] ch8_data_in_del;
reg [12:0] ch9_data_in_del;
reg signed [12:0] ch1_data_in_del1 [0:8199];
reg signed [12:0] ch2_data_in_del1 [0:8199];
reg [12:0] ch3_data_in_del1 [0:8199];
reg [12:0] ch4_data_in_del1 [0:8199];
reg [12:0] ch5_data_in_del1 [0:8199];
reg [12:0] ch6_data_in_del1 [0:8199];
reg [12:0] ch7_data_in_del1 [0:8199];
reg [12:0] ch8_data_in_del1 [0:8199];
reg [12:0] ch9_data_in_del1 [0:8199];
reg rs232_in;
reg diginput1;
reg diginput2;
reg dcm200_locked;
reg idelayctrl_rdy;
reg pll_clk357_locked;
reg dcm360_locked;
reg IDDR1_Q1;
reg IDDR1_Q2;
reg IDDR2_Q1;
reg IDDR2_Q2;
reg IDDR3_Q1;
reg IDDR3_Q2;
// Outputs
wire adc_powerdown;
wire iddr_ce;
wire [12:0] dac1_out;
wire dac1_clk;
wire [12:0] dac2_out;
wire dac2_clk;
wire rs232_out;
wire led0_out;
wire led1_out;
wire led2_out;
wire trim_cs_ld;
wire trim_sck;
wire trim_sdi;
wire diginput1A;
wire diginput1B;
wire diginput2A;
wire diginput2B;
wire auxOutA;
wire auxOutB;
wire dcm200_rst;
wire clk_blk;
wire clk357_idelay_ce;
wire clk357_idelay_rst;
wire idelay_rst;
wire fastClk_sel;
wire clkPLL_sel;
wire run;
wire delay_calc_strb1;
wire delay_calc_strb2;
wire delay_calc_strb3;
wire delay_trig1;
wire delay_trig2;
wire delay_trig3;
wire adc1_drdy_delay_ce;
wire adc2_drdy_delay_ce;
wire adc3_drdy_delay_ce;
wire adc1_clk_delay_ce;
wire adc2_clk_delay_ce;
wire adc3_clk_delay_ce;
wire adc1_data_delay_ce;
wire adc2_data_delay_ce;
wire adc3_data_delay_ce;
// Instantiate the Unit Under Test (UUT)
FONT5_base uut (
.clk357(clk357),
.clk40(clk40),
.clk40_ibufg(clk40_ibufg),
.ch1_data_in_del(ch1_data_in_del ^ CH1_BITFLIP),
.ch2_data_in_del(ch2_data_in_del ^ CH2_BITFLIP),
.ch3_data_in_del(ch3_data_in_del),
.ch4_data_in_del(ch4_data_in_del ^ CH4_BITFLIP),
.ch5_data_in_del(ch5_data_in_del ^ CH5_BITFLIP),
.ch6_data_in_del(ch6_data_in_del),
.ch7_data_in_del(ch7_data_in_del),
.ch8_data_in_del(ch8_data_in_del),
.ch9_data_in_del(ch9_data_in_del),
.rs232_in(rs232_in),
.adc_powerdown(adc_powerdown),
.iddr_ce(iddr_ce),
.dac1_out(dac1_out),
.dac1_clk(dac1_clk),
.dac2_out(dac2_out),
.dac2_clk(dac2_clk),
.rs232_out(rs232_out),
.led0_out(led0_out),
.led1_out(led1_out),
.led2_out(led2_out),
.trim_cs_ld(trim_cs_ld),
.trim_sck(trim_sck),
.trim_sdi(trim_sdi),
.diginput1A(diginput1A),
.diginput1B(diginput1B),
.diginput1(diginput1),
.diginput2A(diginput2A),
.diginput2B(diginput2B),
.diginput2(diginput2),
.auxOutA(auxOutA),
.auxOutB(auxOutB),
//.dcm200_rst(dcm200_rst),
.dcm200_locked(dcm200_locked),
.clk_blk(clk_blk),
.idelayctrl_rdy(idelayctrl_rdy),
//.pll_clk357_locked(pll_clk357_locked),
.clk357_idelay_ce(clk357_idelay_ce),
.clk357_idelay_rst(clk357_idelay_rst),
.idelay_rst(idelay_rst),
//.dcm360_locked(dcm360_locked),
//.fastClk_sel(fastClk_sel),
//.clkPLL_sel_a(clkPLL_sel),
.run(run),
.delay_calc_strb1(delay_calc_strb1),
.delay_calc_strb2(delay_calc_strb2),
.delay_calc_strb3(delay_calc_strb3),
.delay_trig1(delay_trig1),
.delay_trig2(delay_trig2),
.delay_trig3(delay_trig3),
.adc1_drdy_delay_ce(adc1_drdy_delay_ce),
.adc2_drdy_delay_ce(adc2_drdy_delay_ce),
.adc3_drdy_delay_ce(adc3_drdy_delay_ce),
.adc1_clk_delay_ce(adc1_clk_delay_ce),
.adc2_clk_delay_ce(adc2_clk_delay_ce),
.adc3_clk_delay_ce(adc3_clk_delay_ce),
.adc1_data_delay_ce(adc1_data_delay_ce),
.adc2_data_delay_ce(adc2_data_delay_ce),
.adc3_data_delay_ce(adc3_data_delay_ce),
.IDDR1_Q1(IDDR1_Q1),
.IDDR1_Q2(IDDR1_Q2),
.IDDR2_Q1(IDDR2_Q1),
.IDDR2_Q2(IDDR2_Q2),
.IDDR3_Q1(IDDR3_Q1),
.IDDR3_Q2(IDDR3_Q2),
.store_strb(store_strb)
);
/*integer fid;
reg [12:0] k = 13'd0;
reg [12:0] Mem[0:499], Mem2[0:499];*/
integer i;
integer trigger_counter;
initial begin
// $readmemh("diodeAD.dat", Mem);
// $readmemh("mixer_ad.dat", Mem2);
// fid = $fopen("simOut.dat");
// Initialize Inputs
clk357 = 0;
clk40 = 0;
clk40_ibufg = 0;
ch1_data_in_del = 13'sd0;
ch2_data_in_del = 13'sd0;
ch3_data_in_del = 0;
ch4_data_in_del = 13'sd0;
ch5_data_in_del = 13'sd0;
ch6_data_in_del = 0;
ch7_data_in_del = 0;
ch8_data_in_del = 0;
ch9_data_in_del = 0;
rs232_in = 0;
diginput1 = 0;
diginput2 = 0;
dcm200_locked = 0;
idelayctrl_rdy = 0;
pll_clk357_locked = 0;
dcm360_locked = 0;
IDDR1_Q1 = 0;
IDDR1_Q2 = 0;
IDDR2_Q1 = 0;
IDDR2_Q2 = 0;
IDDR3_Q1 = 0;
IDDR3_Q2 = 0;
// i=0;
trigger_counter=0;
end
// // Wait 100 ns for global reset to finish
// #100;
//
// // Add stimulus here
//
// #28;
// //ch1_data_in_del = 13'sd1000;
// //ch2_data_in_del = -13'sd4000;
// ch2_data_in_del = 13'sd2048;
// ch1_data_in_del = -13'sd256;
// ch4_data_in_del = 13'sd500;
// ch5_data_in_del = 13'sd0;
//
// #280; ch2_data_in_del = 13'sd1024;
// #280; ch2_data_in_del = 13'sd512;
// #280; ch2_data_in_del = -13'sd512;
// #280; ch2_data_in_del = 13'sd0;
//
//
// //ch1_data_in_del = 13'sd1250;
// //ch2_data_in_del = -13'sd250;
//// #1120;
//// ch1_data_in_del = 13'sd0;
//// ch2_data_in_del = 13'sd0;
//// ch4_data_in_del = 13'sd0;
//// ch5_data_in_del = 13'sd0;
//
//
// end
initial forever #1.4 clk357 = ~clk357;
initial forever #12.5 clk40 = ~clk40;
initial begin
$readmemb("tempai.txt",ch4_data_in_del1);
$readmemb("tempaq.txt",ch5_data_in_del1);
$readmemb("tempbi.txt",ch1_data_in_del1);
$readmemb("tempbq.txt",ch2_data_in_del1);
$readmemb("tempci.txt",ch7_data_in_del1);
$readmemb("tempcq.txt",ch8_data_in_del1);
$readmemb("tempq.txt",ch9_data_in_del1);
end
always @ (negedge clk357)
begin
if (store_strb==0) begin
// ai_in <= 0;
// bi_in<=0;
// ci_in<=0;
// aq_in <=0;
// bq_in<=0;
// cq_in<=0;
// sel[1] <=1;
// sel[0] <=0;
ch1_data_in_del <= 13'sd0;
ch2_data_in_del <= 13'sd0;
ch3_data_in_del <= 0;
ch4_data_in_del <= 13'sd0;
ch5_data_in_del <= 13'sd0;
ch6_data_in_del <= 0;
ch7_data_in_del <= 0;
ch8_data_in_del <= 0;
ch9_data_in_del <= 0;
i<=(4*trigger_counter+2)*164;
end else begin
ch1_data_in_del = ch1_data_in_del1[i];
ch2_data_in_del = ch2_data_in_del1[i];
// ch3_data_in_del = ch3_data_in_del1[i];
ch4_data_in_del = ch4_data_in_del1[i];
ch5_data_in_del = ch5_data_in_del1[i];
// ch6_data_in_del = ch6_data_in_del1[i];
ch7_data_in_del = ch7_data_in_del1[i+5];
ch8_data_in_del = ch8_data_in_del1[i+5];
ch9_data_in_del = ch9_data_in_del1[i+10];
//ai_in<=ai_in1[i];
//aq_in<=aq_in1[i];
//bi_in<=bi_in1[i];
//bq_in<=bq_in1[i];
//ci_in<=ci_in1[i+5];
//cq_in<=cq_in1[i+5];
//q_signal<=q_signal1[i+10];
i<=i+1;
end
end
always @ (posedge store_strb) begin
#1 trigger_counter=trigger_counter+1;
end
/*always @(posedge clk357) begin
ch1_data_in_del <= Mem[k];
ch2_data_in_del <= Mem2[k];
k <= k + 1'b1;
$fwrite(fid,"%h\n", dac1_out);
if (k==13'd499) begin
$fclose(fid);
$finish;
end
end */
endmodule
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666666} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={0} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS18} bidis={4} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={CAN} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={23.809523} usageRate={0.5} /><IO interface={I2C} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={25.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=49.5, PCW_UIPARAM_DDR_T_RAS_MIN=36.0, PCW_UIPARAM_DDR_T_FAW=30.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=0.217, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=0.133, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.089, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.248, PCW_UIPARAM_DDR_BOARD_DELAY0=0.537, PCW_UIPARAM_DDR_BOARD_DELAY1=0.442, PCW_UIPARAM_DDR_BOARD_DELAY2=0.464, PCW_UIPARAM_DDR_BOARD_DELAY3=0.521, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=0, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=0, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=0, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=68.4725, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=71.086, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=66.794, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=108.7385, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=64.1705, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=63.686, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=68.46, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=105.4895, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=61.0905, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=666.666666, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=23.8095, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=50, PCW_FPGA2_PERIPHERAL_FREQMHZ=50, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=100, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 1.8V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41J256M8 HX-15E, PCW_UIPARAM_DDR_DRAM_WIDTH=8 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=1, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=1, PCW_ENET0_RESET_IO=MIO 11, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 0, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 15, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=1, PCW_CAN0_CAN0_IO=MIO 46 .. 47, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 7, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=MIO 50 .. 51, PCW_I2C0_GRP_INT_ENABLE=0, PCW_I2C0_RESET_ENABLE=1, PCW_I2C0_RESET_IO=MIO 13, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=0, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=100 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11, PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0,
// Enable and disable AFI Secure transaction
parameter C_USE_AXI_NONSECURE = 0,
//parameters for HP enable ports
parameter C_USE_S_AXI_HP0 = 0,
parameter C_USE_S_AXI_HP1 = 0,
parameter C_USE_S_AXI_HP2 = 0,
parameter C_USE_S_AXI_HP3 = 0,
//parameters for GP and ACP enable ports */
parameter C_USE_M_AXI_GP0 = 0,
parameter C_USE_M_AXI_GP1 = 0,
parameter C_USE_S_AXI_GP0 = 0,
parameter C_USE_S_AXI_GP1 = 0,
parameter C_USE_S_AXI_ACP = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN = 'b0,
output reg ENET0_GMII_TX_ER = 'b0,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN = 'b0,
output reg ENET1_GMII_TX_ER = 'b0,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
// Wires for connecting to the PS7
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
wire FCLK_CLK0_temp;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire S_AXI_HP0_ACLK_temp;
wire S_AXI_HP1_ACLK_temp;
wire S_AXI_HP2_ACLK_temp;
wire S_AXI_HP3_ACLK_temp;
wire M_AXI_GP0_ACLK_temp;
wire M_AXI_GP1_ACLK_temp;
wire S_AXI_GP0_ACLK_temp;
wire S_AXI_GP1_ACLK_temp;
wire S_AXI_ACP_ACLK_temp;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
(* keep = "true" *) reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
(* keep = "true" *) reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
else
begin
always @*
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= 1'b0;
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= 1'b0;
TRACE_DATA_PIPE[j-1] <= 1'b0;
end
TRACE_CLK_OUT <= 1'b0;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
else
always@*
begin
ENET0_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= 'b0;
ENET0_GMII_CRS_i <= 'b0;
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET0_GMII_RXD_i <= 0;
ENET0_GMII_RX_DV_i <= 0;
ENET0_GMII_RX_ER_i <= 0;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
else
begin
always@*
begin
ENET1_GMII_TXD <= 'b0;//ENET0_GMII_TXD_i;
ENET1_GMII_TX_EN <= 'b0;//ENET0_GMII_TX_EN_i; //1'b0; //ENET0_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= 'b0;//ENET0_GMII_TX_ER_i; //1'b0;//ENET0_GMII_TX_ER_i;
ENET1_GMII_COL_i <= 0;
ENET1_GMII_CRS_i <= 0;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
else
begin
always @*
begin
ENET1_GMII_RXD_i <= 'b0;
ENET1_GMII_RX_DV_i <= 'b0;
ENET1_GMII_RX_ER_i <= 'b0;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
else
begin
assign FTMD_TRACEIN_DATA_i = 1'b0;
assign FTMD_TRACEIN_VALID_i = 1'b0;
assign FTMD_TRACEIN_ATID_i = 1'b0;
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
else
begin
assign PJTAG_TDO = 1'b0;
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0_temp = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
assign FCLK_CLK0 = FCLK_CLK0_temp;
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
// Connect FCLK in case of disable the AXI port for non Secure Transaction
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP0 == 0) begin
assign S_AXI_HP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP0_ACLK_temp = S_AXI_HP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP1 == 0) begin
assign S_AXI_HP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP1_ACLK_temp = S_AXI_HP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP2 == 0) begin
assign S_AXI_HP2_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP2_ACLK_temp = S_AXI_HP2_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_HP3 == 0) begin
assign S_AXI_HP3_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_HP3_ACLK_temp = S_AXI_HP3_ACLK;
end
endgenerate
//Start
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP0 == 0) begin
assign M_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP0_ACLK_temp = M_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_M_AXI_GP1 == 0) begin
assign M_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign M_AXI_GP1_ACLK_temp = M_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP0 == 0) begin
assign S_AXI_GP0_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP0_ACLK_temp = S_AXI_GP0_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_GP1 == 0) begin
assign S_AXI_GP1_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_GP1_ACLK_temp = S_AXI_GP1_ACLK;
end
endgenerate
generate
if ( C_USE_AXI_NONSECURE == 1 && C_USE_S_AXI_ACP == 0) begin
assign S_AXI_ACP_ACLK_temp = FCLK_CLK0_temp;
end
else begin
assign S_AXI_ACP_ACLK_temp = S_AXI_ACP_ACLK;
end
endgenerate
//END
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), //(ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i), // (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i), // (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i), // (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i), // (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i), // (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i), // (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK_temp),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK_temp ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK_temp),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK_temp ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK_temp ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK_temp ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK_temp),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK_temp),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK_temp),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK_temp),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFXTP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFXTP_SYMBOL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFXTP_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_axis_dma_rx (
// adc interface
adc_clk,
adc_rst,
// dma interface
dma_clk,
dma_rst,
dma_start,
dma_stream,
dma_count,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00050063;
parameter ID = 0;
// adc interface
input adc_clk;
output adc_rst;
// dma interface
input dma_clk;
output dma_rst;
output dma_start;
output dma_stream;
output [31:0] dma_count;
input dma_ovf;
input dma_unf;
input dma_status;
input [31:0] dma_bw;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_preset = 'd0;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_dma_stream = 'd0;
reg up_dma_start = 'd0;
reg [31:0] up_dma_count = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
reg dma_start_d = 'd0;
reg dma_start_2d = 'd0;
reg dma_start = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_dma_ovf_s;
wire up_dma_unf_s;
wire up_dma_status_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == 6'h00) ? up_wreq : 1'b0;
assign up_rreq_s = (up_waddr[13:8] == 6'h00) ? up_rreq : 1'b0;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_preset <= 1'd1;
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_dma_stream <= 'd0;
up_dma_start <= 'd0;
up_dma_count <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
end else begin
up_preset <= 1'd0;
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_dma_stream <= up_wdata[1];
up_dma_start <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h21)) begin
up_dma_count <= up_wdata;
end
if (up_dma_ovf_s == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
end
if (up_dma_unf_s == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[1];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {31'd0, up_resetn};
8'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
8'h21: up_rdata <= up_dma_count;
8'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status_s};
8'h23: up_rdata <= dma_bw;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_adc_rst_reg (.preset(up_preset), .clk(adc_clk), .rst(adc_rst));
ad_rst i_dma_rst_reg (.preset(up_preset), .clk(dma_clk), .rst(dma_rst));
// dma control & status
up_xfer_cntrl #(.DATA_WIDTH(34)) i_dma_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_dma_start,
up_dma_stream,
up_dma_count}),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_cntrl ({ dma_start_s,
dma_stream,
dma_count}));
up_xfer_status #(.DATA_WIDTH(3)) i_dma_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_dma_ovf_s,
up_dma_unf_s,
up_dma_status_s}),
.d_rst (dma_rst),
.d_clk (dma_clk),
.d_data_status ({ dma_ovf,
dma_unf,
dma_status}));
// start needs to be a pulse
always @(posedge dma_clk) begin
dma_start_d <= dma_start_s;
dma_start_2d <= dma_start_d;
dma_start <= dma_start_d & ~dma_start_2d;
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : ram_2p.v
// Author : Yibo FAN
// Created : 2012-04-01
// Description : Dual Port Ram Model
//
// $Id$
//-------------------------------------------------------------------
module ram_lcu_row_32x64 (
clka ,
cena_i ,
oena_i ,
wena_i ,
addra_i ,
dataa_o ,
dataa_i ,
clkb ,
cenb_i ,
oenb_i ,
wenb_i ,
addrb_i ,
datab_o ,
datab_i
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
parameter Word_Width=32;
parameter Addr_Width=6;
// ********************************************
//
// Input/Output DECLARATION
//
// ********************************************
// A port
input clka; // clock input
input cena_i; // chip enable, low active
input oena_i; // data output enable, low active
input wena_i; // write enable, low active
input [Addr_Width-1:0] addra_i; // address input
input [Word_Width-1:0] dataa_i; // data input
output [Word_Width-1:0] dataa_o; // data output
// B Port
input clkb; // clock input
input cenb_i; // chip enable, low active
input oenb_i; // data output enable, low active
input wenb_i; // write enable, low active
input [Addr_Width-1:0] addrb_i; // address input
input [Word_Width-1:0] datab_i; // data input
output [Word_Width-1:0] datab_o; // data output
// ********************************************
//
// Register DECLARATION
//
// ********************************************
reg [Word_Width-1:0] mem_array[(1<<Addr_Width)-1:0];
// ********************************************
//
// Wire DECLARATION
//
// ********************************************
reg [Word_Width-1:0] dataa_r;
reg [Word_Width-1:0] datab_r;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// -- A Port --//
always @(posedge clka) begin
if(!cena_i && !wena_i)
mem_array[addra_i] <= dataa_i;
end
always @(posedge clka) begin
if (!cena_i && wena_i)
dataa_r <= mem_array[addra_i];
else
dataa_r <= 'bx;
end
assign dataa_o = oena_i ? 'bz : dataa_r;
// -- B Port --//
always @(posedge clkb) begin
if(!cenb_i && !wenb_i)
mem_array[addrb_i] <= datab_i;
end
always @(posedge clkb) begin
if (!cenb_i && wenb_i)
datab_r <= mem_array[addrb_i];
else
datab_r <= 'bx;
end
assign datab_o = oenb_i ? 'bz : datab_r;
endmodule |
/////////////////////////////////////////////////////////////////
// MODULE Sobel_system
/////////////////////////////////////////////////////////////////
module Sobel_system
(
input logic clock,
input logic clock2x,
input logic resetn,
// AVS avs_sobel_cra
input logic avs_sobel_cra_read,
input logic avs_sobel_cra_write,
input logic [3:0] avs_sobel_cra_address,
input logic [63:0] avs_sobel_cra_writedata,
input logic [7:0] avs_sobel_cra_byteenable,
output logic avs_sobel_cra_waitrequest,
output logic [63:0] avs_sobel_cra_readdata,
output logic avs_sobel_cra_readdatavalid,
output logic kernel_irq,
// AVM avm_memgmem0_port_0_0_rw
output logic avm_memgmem0_port_0_0_rw_read,
output logic avm_memgmem0_port_0_0_rw_write,
output logic [4:0] avm_memgmem0_port_0_0_rw_burstcount,
output logic [29:0] avm_memgmem0_port_0_0_rw_address,
output logic [255:0] avm_memgmem0_port_0_0_rw_writedata,
output logic [31:0] avm_memgmem0_port_0_0_rw_byteenable,
input logic avm_memgmem0_port_0_0_rw_waitrequest,
input logic [255:0] avm_memgmem0_port_0_0_rw_readdata,
input logic avm_memgmem0_port_0_0_rw_readdatavalid,
input logic avm_memgmem0_port_0_0_rw_writeack
);
genvar i;
logic kernel_irqs;
logic gmem0_global_avm_read [2];
logic gmem0_global_avm_write [2];
logic [4:0] gmem0_global_avm_burstcount [2];
logic [29:0] gmem0_global_avm_address [2];
logic [255:0] gmem0_global_avm_writedata [2];
logic [31:0] gmem0_global_avm_byteenable [2];
logic gmem0_global_avm_waitrequest [2];
logic [255:0] gmem0_global_avm_readdata [2];
logic gmem0_global_avm_readdatavalid [2];
logic gmem0_global_avm_writeack [2];
// INST sobel of sobel_top_wrapper
sobel_top_wrapper sobel
(
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.cra_irq(kernel_irqs),
// AVS avs_cra
.avs_cra_read(avs_sobel_cra_read),
.avs_cra_write(avs_sobel_cra_write),
.avs_cra_address(avs_sobel_cra_address),
.avs_cra_writedata(avs_sobel_cra_writedata),
.avs_cra_byteenable(avs_sobel_cra_byteenable),
.avs_cra_waitrequest(avs_sobel_cra_waitrequest),
.avs_cra_readdata(avs_sobel_cra_readdata),
.avs_cra_readdatavalid(avs_sobel_cra_readdatavalid),
// AVM avm_local_bb1_ld__inst0
.avm_local_bb1_ld__inst0_read(gmem0_global_avm_read[0]),
.avm_local_bb1_ld__inst0_write(gmem0_global_avm_write[0]),
.avm_local_bb1_ld__inst0_burstcount(gmem0_global_avm_burstcount[0]),
.avm_local_bb1_ld__inst0_address(gmem0_global_avm_address[0]),
.avm_local_bb1_ld__inst0_writedata(gmem0_global_avm_writedata[0]),
.avm_local_bb1_ld__inst0_byteenable(gmem0_global_avm_byteenable[0]),
.avm_local_bb1_ld__inst0_waitrequest(gmem0_global_avm_waitrequest[0]),
.avm_local_bb1_ld__inst0_readdata(gmem0_global_avm_readdata[0]),
.avm_local_bb1_ld__inst0_readdatavalid(gmem0_global_avm_readdatavalid[0]),
.avm_local_bb1_ld__inst0_writeack(gmem0_global_avm_writeack[0]),
// AVM avm_local_bb1_st_add43_lobit_inst0
.avm_local_bb1_st_add43_lobit_inst0_read(gmem0_global_avm_read[1]),
.avm_local_bb1_st_add43_lobit_inst0_write(gmem0_global_avm_write[1]),
.avm_local_bb1_st_add43_lobit_inst0_burstcount(gmem0_global_avm_burstcount[1]),
.avm_local_bb1_st_add43_lobit_inst0_address(gmem0_global_avm_address[1]),
.avm_local_bb1_st_add43_lobit_inst0_writedata(gmem0_global_avm_writedata[1]),
.avm_local_bb1_st_add43_lobit_inst0_byteenable(gmem0_global_avm_byteenable[1]),
.avm_local_bb1_st_add43_lobit_inst0_waitrequest(gmem0_global_avm_waitrequest[1]),
.avm_local_bb1_st_add43_lobit_inst0_readdata(gmem0_global_avm_readdata[1]),
.avm_local_bb1_st_add43_lobit_inst0_readdatavalid(gmem0_global_avm_readdatavalid[1]),
.avm_local_bb1_st_add43_lobit_inst0_writeack(gmem0_global_avm_writeack[1])
);
assign kernel_irq = |kernel_irqs;
generate
begin:gmem0_
logic gmem0_icm_in_arb_request [2];
logic gmem0_icm_in_arb_read [2];
logic gmem0_icm_in_arb_write [2];
logic [4:0] gmem0_icm_in_arb_burstcount [2];
logic [24:0] gmem0_icm_in_arb_address [2];
logic [255:0] gmem0_icm_in_arb_writedata [2];
logic [31:0] gmem0_icm_in_arb_byteenable [2];
logic gmem0_icm_in_arb_stall [2];
logic gmem0_icm_in_wrp_ack [2];
logic gmem0_icm_in_rrp_datavalid [2];
logic [255:0] gmem0_icm_in_rrp_data [2];
logic gmem0_icm_preroute_arb_request [2];
logic gmem0_icm_preroute_arb_read [2];
logic gmem0_icm_preroute_arb_write [2];
logic [4:0] gmem0_icm_preroute_arb_burstcount [2];
logic [24:0] gmem0_icm_preroute_arb_address [2];
logic [255:0] gmem0_icm_preroute_arb_writedata [2];
logic [31:0] gmem0_icm_preroute_arb_byteenable [2];
logic gmem0_icm_preroute_arb_stall [2];
logic gmem0_icm_preroute_wrp_ack [2];
logic gmem0_icm_preroute_rrp_datavalid [2];
logic [255:0] gmem0_icm_preroute_rrp_data [2];
logic icm_groupgmem0_router_0_arb_request [1];
logic icm_groupgmem0_router_0_arb_read [1];
logic icm_groupgmem0_router_0_arb_write [1];
logic [4:0] icm_groupgmem0_router_0_arb_burstcount [1];
logic [24:0] icm_groupgmem0_router_0_arb_address [1];
logic [255:0] icm_groupgmem0_router_0_arb_writedata [1];
logic [31:0] icm_groupgmem0_router_0_arb_byteenable [1];
logic icm_groupgmem0_router_0_arb_stall [1];
logic icm_groupgmem0_router_0_wrp_ack [1];
logic icm_groupgmem0_router_0_rrp_datavalid [1];
logic [255:0] icm_groupgmem0_router_0_rrp_data [1];
logic icm_groupgmem0_router_1_arb_request [1];
logic icm_groupgmem0_router_1_arb_read [1];
logic icm_groupgmem0_router_1_arb_write [1];
logic [4:0] icm_groupgmem0_router_1_arb_burstcount [1];
logic [24:0] icm_groupgmem0_router_1_arb_address [1];
logic [255:0] icm_groupgmem0_router_1_arb_writedata [1];
logic [31:0] icm_groupgmem0_router_1_arb_byteenable [1];
logic icm_groupgmem0_router_1_arb_stall [1];
logic icm_groupgmem0_router_1_wrp_ack [1];
logic icm_groupgmem0_router_1_rrp_datavalid [1];
logic [255:0] icm_groupgmem0_router_1_rrp_data [1];
logic icm_out_0_rw_arb_request [1];
logic icm_out_0_rw_arb_read [1];
logic icm_out_0_rw_arb_write [1];
logic [4:0] icm_out_0_rw_arb_burstcount [1];
logic [24:0] icm_out_0_rw_arb_address [1];
logic [255:0] icm_out_0_rw_arb_writedata [1];
logic [31:0] icm_out_0_rw_arb_byteenable [1];
logic icm_out_0_rw_arb_id [1];
logic icm_out_0_rw_arb_stall [1];
logic icm_out_0_rw_wrp_ack [1];
logic icm_out_0_rw_rrp_datavalid [1];
logic [255:0] icm_out_0_rw_rrp_data [1];
logic icm_routedgmem0_port_0_0_rw_arb_request [2];
logic icm_routedgmem0_port_0_0_rw_arb_read [2];
logic icm_routedgmem0_port_0_0_rw_arb_write [2];
logic [4:0] icm_routedgmem0_port_0_0_rw_arb_burstcount [2];
logic [24:0] icm_routedgmem0_port_0_0_rw_arb_address [2];
logic [255:0] icm_routedgmem0_port_0_0_rw_arb_writedata [2];
logic [31:0] icm_routedgmem0_port_0_0_rw_arb_byteenable [2];
logic icm_routedgmem0_port_0_0_rw_arb_stall [2];
logic icm_routedgmem0_port_0_0_rw_wrp_ack [2];
logic icm_routedgmem0_port_0_0_rw_rrp_datavalid [2];
logic [255:0] icm_routedgmem0_port_0_0_rw_rrp_data [2];
for( i = 0; i < 2; i = i + 1 )
begin:t
// INST gmem0_avm_to_ic of acl_avm_to_ic
acl_avm_to_ic
#(
.DATA_W(256),
.WRITEDATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(30),
.BYTEENA_W(32)
)
gmem0_avm_to_ic
(
// AVM avm
.avm_read(gmem0_global_avm_read[i]),
.avm_write(gmem0_global_avm_write[i]),
.avm_burstcount(gmem0_global_avm_burstcount[i]),
.avm_address(gmem0_global_avm_address[i]),
.avm_writedata(gmem0_global_avm_writedata[i]),
.avm_byteenable(gmem0_global_avm_byteenable[i]),
.avm_waitrequest(gmem0_global_avm_waitrequest[i]),
.avm_readdata(gmem0_global_avm_readdata[i]),
.avm_readdatavalid(gmem0_global_avm_readdatavalid[i]),
.avm_writeack(gmem0_global_avm_writeack[i]),
// ICM ic
.ic_arb_request(gmem0_icm_in_arb_request[i]),
.ic_arb_read(gmem0_icm_in_arb_read[i]),
.ic_arb_write(gmem0_icm_in_arb_write[i]),
.ic_arb_burstcount(gmem0_icm_in_arb_burstcount[i]),
.ic_arb_address(gmem0_icm_in_arb_address[i]),
.ic_arb_writedata(gmem0_icm_in_arb_writedata[i]),
.ic_arb_byteenable(gmem0_icm_in_arb_byteenable[i]),
.ic_arb_stall(gmem0_icm_in_arb_stall[i]),
.ic_wrp_ack(gmem0_icm_in_wrp_ack[i]),
.ic_rrp_datavalid(gmem0_icm_in_rrp_datavalid[i]),
.ic_rrp_data(gmem0_icm_in_rrp_data[i])
);
end
assign icm_groupgmem0_router_0_arb_request[0] = gmem0_icm_in_arb_request[1];
assign icm_groupgmem0_router_0_arb_read[0] = gmem0_icm_in_arb_read[1];
assign icm_groupgmem0_router_0_arb_write[0] = gmem0_icm_in_arb_write[1];
assign icm_groupgmem0_router_0_arb_burstcount[0] = gmem0_icm_in_arb_burstcount[1];
assign icm_groupgmem0_router_0_arb_address[0] = gmem0_icm_in_arb_address[1];
assign icm_groupgmem0_router_0_arb_writedata[0] = gmem0_icm_in_arb_writedata[1];
assign icm_groupgmem0_router_0_arb_byteenable[0] = gmem0_icm_in_arb_byteenable[1];
assign gmem0_icm_in_arb_stall[1] = icm_groupgmem0_router_0_arb_stall[0];
assign gmem0_icm_in_wrp_ack[1] = icm_groupgmem0_router_0_wrp_ack[0];
assign gmem0_icm_in_rrp_datavalid[1] = icm_groupgmem0_router_0_rrp_datavalid[0];
assign gmem0_icm_in_rrp_data[1] = icm_groupgmem0_router_0_rrp_data[0];
// INST global_ic_preroutegmem0_router_0 of interconnect_0
interconnect_0 global_ic_preroutegmem0_router_0
(
.clock(clock),
.resetn(resetn),
// ICM m
.m_arb_request(icm_groupgmem0_router_0_arb_request),
.m_arb_read(icm_groupgmem0_router_0_arb_read),
.m_arb_write(icm_groupgmem0_router_0_arb_write),
.m_arb_burstcount(icm_groupgmem0_router_0_arb_burstcount),
.m_arb_address(icm_groupgmem0_router_0_arb_address),
.m_arb_writedata(icm_groupgmem0_router_0_arb_writedata),
.m_arb_byteenable(icm_groupgmem0_router_0_arb_byteenable),
.m_arb_stall(icm_groupgmem0_router_0_arb_stall),
.m_wrp_ack(icm_groupgmem0_router_0_wrp_ack),
.m_rrp_datavalid(icm_groupgmem0_router_0_rrp_datavalid),
.m_rrp_data(icm_groupgmem0_router_0_rrp_data),
// ICM mout
.mout_arb_request(gmem0_icm_preroute_arb_request[0]),
.mout_arb_read(gmem0_icm_preroute_arb_read[0]),
.mout_arb_write(gmem0_icm_preroute_arb_write[0]),
.mout_arb_burstcount(gmem0_icm_preroute_arb_burstcount[0]),
.mout_arb_address(gmem0_icm_preroute_arb_address[0]),
.mout_arb_writedata(gmem0_icm_preroute_arb_writedata[0]),
.mout_arb_byteenable(gmem0_icm_preroute_arb_byteenable[0]),
.mout_arb_id(),
.mout_arb_stall(gmem0_icm_preroute_arb_stall[0]),
.mout_wrp_ack(gmem0_icm_preroute_wrp_ack[0]),
.mout_rrp_datavalid(gmem0_icm_preroute_rrp_datavalid[0]),
.mout_rrp_data(gmem0_icm_preroute_rrp_data[0])
);
assign icm_groupgmem0_router_1_arb_request[0] = gmem0_icm_in_arb_request[0];
assign icm_groupgmem0_router_1_arb_read[0] = gmem0_icm_in_arb_read[0];
assign icm_groupgmem0_router_1_arb_write[0] = gmem0_icm_in_arb_write[0];
assign icm_groupgmem0_router_1_arb_burstcount[0] = gmem0_icm_in_arb_burstcount[0];
assign icm_groupgmem0_router_1_arb_address[0] = gmem0_icm_in_arb_address[0];
assign icm_groupgmem0_router_1_arb_writedata[0] = gmem0_icm_in_arb_writedata[0];
assign icm_groupgmem0_router_1_arb_byteenable[0] = gmem0_icm_in_arb_byteenable[0];
assign gmem0_icm_in_arb_stall[0] = icm_groupgmem0_router_1_arb_stall[0];
assign gmem0_icm_in_wrp_ack[0] = icm_groupgmem0_router_1_wrp_ack[0];
assign gmem0_icm_in_rrp_datavalid[0] = icm_groupgmem0_router_1_rrp_datavalid[0];
assign gmem0_icm_in_rrp_data[0] = icm_groupgmem0_router_1_rrp_data[0];
// INST global_ic_preroutegmem0_router_1 of interconnect_1
interconnect_1 global_ic_preroutegmem0_router_1
(
.clock(clock),
.resetn(resetn),
// ICM m
.m_arb_request(icm_groupgmem0_router_1_arb_request),
.m_arb_read(icm_groupgmem0_router_1_arb_read),
.m_arb_write(icm_groupgmem0_router_1_arb_write),
.m_arb_burstcount(icm_groupgmem0_router_1_arb_burstcount),
.m_arb_address(icm_groupgmem0_router_1_arb_address),
.m_arb_writedata(icm_groupgmem0_router_1_arb_writedata),
.m_arb_byteenable(icm_groupgmem0_router_1_arb_byteenable),
.m_arb_stall(icm_groupgmem0_router_1_arb_stall),
.m_wrp_ack(icm_groupgmem0_router_1_wrp_ack),
.m_rrp_datavalid(icm_groupgmem0_router_1_rrp_datavalid),
.m_rrp_data(icm_groupgmem0_router_1_rrp_data),
// ICM mout
.mout_arb_request(gmem0_icm_preroute_arb_request[1]),
.mout_arb_read(gmem0_icm_preroute_arb_read[1]),
.mout_arb_write(gmem0_icm_preroute_arb_write[1]),
.mout_arb_burstcount(gmem0_icm_preroute_arb_burstcount[1]),
.mout_arb_address(gmem0_icm_preroute_arb_address[1]),
.mout_arb_writedata(gmem0_icm_preroute_arb_writedata[1]),
.mout_arb_byteenable(gmem0_icm_preroute_arb_byteenable[1]),
.mout_arb_id(),
.mout_arb_stall(gmem0_icm_preroute_arb_stall[1]),
.mout_wrp_ack(gmem0_icm_preroute_wrp_ack[1]),
.mout_rrp_datavalid(gmem0_icm_preroute_rrp_datavalid[1]),
.mout_rrp_data(gmem0_icm_preroute_rrp_data[1])
);
for( i = 0; i < 2; i = i + 1 )
begin:router
logic b_arb_request [1];
logic b_arb_read [1];
logic b_arb_write [1];
logic [4:0] b_arb_burstcount [1];
logic [24:0] b_arb_address [1];
logic [255:0] b_arb_writedata [1];
logic [31:0] b_arb_byteenable [1];
logic b_arb_stall [1];
logic b_wrp_ack [1];
logic b_rrp_datavalid [1];
logic [255:0] b_rrp_data [1];
logic bank_select;
// INST router of acl_ic_mem_router
acl_ic_mem_router
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.NUM_BANKS(1)
)
router
(
.clock(clock),
.resetn(resetn),
.bank_select(bank_select),
// ICM m
.m_arb_request(gmem0_icm_preroute_arb_request[i]),
.m_arb_read(gmem0_icm_preroute_arb_read[i]),
.m_arb_write(gmem0_icm_preroute_arb_write[i]),
.m_arb_burstcount(gmem0_icm_preroute_arb_burstcount[i]),
.m_arb_address(gmem0_icm_preroute_arb_address[i]),
.m_arb_writedata(gmem0_icm_preroute_arb_writedata[i]),
.m_arb_byteenable(gmem0_icm_preroute_arb_byteenable[i]),
.m_arb_stall(gmem0_icm_preroute_arb_stall[i]),
.m_wrp_ack(gmem0_icm_preroute_wrp_ack[i]),
.m_rrp_datavalid(gmem0_icm_preroute_rrp_datavalid[i]),
.m_rrp_data(gmem0_icm_preroute_rrp_data[i]),
// ICM b
.b_arb_request(b_arb_request),
.b_arb_read(b_arb_read),
.b_arb_write(b_arb_write),
.b_arb_burstcount(b_arb_burstcount),
.b_arb_address(b_arb_address),
.b_arb_writedata(b_arb_writedata),
.b_arb_byteenable(b_arb_byteenable),
.b_arb_stall(b_arb_stall),
.b_wrp_ack(b_wrp_ack),
.b_rrp_datavalid(b_rrp_datavalid),
.b_rrp_data(b_rrp_data)
);
assign bank_select = 1'b1;
end
// INST global_icgmem0_port_0_0_rw of interconnect_2
interconnect_2 global_icgmem0_port_0_0_rw
(
.clock(clock),
.resetn(resetn),
// ICM m
.m_arb_request(icm_routedgmem0_port_0_0_rw_arb_request),
.m_arb_read(icm_routedgmem0_port_0_0_rw_arb_read),
.m_arb_write(icm_routedgmem0_port_0_0_rw_arb_write),
.m_arb_burstcount(icm_routedgmem0_port_0_0_rw_arb_burstcount),
.m_arb_address(icm_routedgmem0_port_0_0_rw_arb_address),
.m_arb_writedata(icm_routedgmem0_port_0_0_rw_arb_writedata),
.m_arb_byteenable(icm_routedgmem0_port_0_0_rw_arb_byteenable),
.m_arb_stall(icm_routedgmem0_port_0_0_rw_arb_stall),
.m_wrp_ack(icm_routedgmem0_port_0_0_rw_wrp_ack),
.m_rrp_datavalid(icm_routedgmem0_port_0_0_rw_rrp_datavalid),
.m_rrp_data(icm_routedgmem0_port_0_0_rw_rrp_data),
// ICM mout
.mout_arb_request(icm_out_0_rw_arb_request[0]),
.mout_arb_read(icm_out_0_rw_arb_read[0]),
.mout_arb_write(icm_out_0_rw_arb_write[0]),
.mout_arb_burstcount(icm_out_0_rw_arb_burstcount[0]),
.mout_arb_address(icm_out_0_rw_arb_address[0]),
.mout_arb_writedata(icm_out_0_rw_arb_writedata[0]),
.mout_arb_byteenable(icm_out_0_rw_arb_byteenable[0]),
.mout_arb_id(icm_out_0_rw_arb_id[0]),
.mout_arb_stall(icm_out_0_rw_arb_stall[0]),
.mout_wrp_ack(icm_out_0_rw_wrp_ack[0]),
.mout_rrp_datavalid(icm_out_0_rw_rrp_datavalid[0]),
.mout_rrp_data(icm_out_0_rw_rrp_data[0])
);
for( i = 0; i < 2; i = i + 1 )
begin:mgmem0_port_0_0_rw
assign icm_routedgmem0_port_0_0_rw_arb_request[i] = router[i].b_arb_request[0];
assign icm_routedgmem0_port_0_0_rw_arb_read[i] = router[i].b_arb_read[0];
assign icm_routedgmem0_port_0_0_rw_arb_write[i] = router[i].b_arb_write[0];
assign icm_routedgmem0_port_0_0_rw_arb_burstcount[i] = router[i].b_arb_burstcount[0];
assign icm_routedgmem0_port_0_0_rw_arb_address[i] = router[i].b_arb_address[0];
assign icm_routedgmem0_port_0_0_rw_arb_writedata[i] = router[i].b_arb_writedata[0];
assign icm_routedgmem0_port_0_0_rw_arb_byteenable[i] = router[i].b_arb_byteenable[0];
assign router[i].b_arb_stall[0] = icm_routedgmem0_port_0_0_rw_arb_stall[i];
assign router[i].b_wrp_ack[0] = icm_routedgmem0_port_0_0_rw_wrp_ack[i];
assign router[i].b_rrp_datavalid[0] = icm_routedgmem0_port_0_0_rw_rrp_datavalid[i];
assign router[i].b_rrp_data[0] = icm_routedgmem0_port_0_0_rw_rrp_data[i];
end
// INST global_out_ic_to_avmgmem0_port_0_0_rw of acl_ic_to_avm
acl_ic_to_avm
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(30),
.BYTEENA_W(32),
.ID_W(1)
)
global_out_ic_to_avmgmem0_port_0_0_rw
(
// ICM ic
.ic_arb_request(icm_out_0_rw_arb_request[0]),
.ic_arb_read(icm_out_0_rw_arb_read[0]),
.ic_arb_write(icm_out_0_rw_arb_write[0]),
.ic_arb_burstcount(icm_out_0_rw_arb_burstcount[0]),
.ic_arb_address(icm_out_0_rw_arb_address[0]),
.ic_arb_writedata(icm_out_0_rw_arb_writedata[0]),
.ic_arb_byteenable(icm_out_0_rw_arb_byteenable[0]),
.ic_arb_id(icm_out_0_rw_arb_id[0]),
.ic_arb_stall(icm_out_0_rw_arb_stall[0]),
.ic_wrp_ack(icm_out_0_rw_wrp_ack[0]),
.ic_rrp_datavalid(icm_out_0_rw_rrp_datavalid[0]),
.ic_rrp_data(icm_out_0_rw_rrp_data[0]),
// AVM avm
.avm_read(avm_memgmem0_port_0_0_rw_read),
.avm_write(avm_memgmem0_port_0_0_rw_write),
.avm_burstcount(avm_memgmem0_port_0_0_rw_burstcount),
.avm_address(avm_memgmem0_port_0_0_rw_address),
.avm_writedata(avm_memgmem0_port_0_0_rw_writedata),
.avm_byteenable(avm_memgmem0_port_0_0_rw_byteenable),
.avm_waitrequest(avm_memgmem0_port_0_0_rw_waitrequest),
.avm_readdata(avm_memgmem0_port_0_0_rw_readdata),
.avm_readdatavalid(avm_memgmem0_port_0_0_rw_readdatavalid),
.avm_writeack(avm_memgmem0_port_0_0_rw_writeack)
);
end
endgenerate
endmodule
/////////////////////////////////////////////////////////////////
// MODULE sobel_top_wrapper
/////////////////////////////////////////////////////////////////
module sobel_top_wrapper
(
input logic clock,
input logic clock2x,
input logic resetn,
output logic cra_irq,
// AVS avs_cra
input logic avs_cra_read,
input logic avs_cra_write,
input logic [3:0] avs_cra_address,
input logic [63:0] avs_cra_writedata,
input logic [7:0] avs_cra_byteenable,
output logic avs_cra_waitrequest,
output logic [63:0] avs_cra_readdata,
output logic avs_cra_readdatavalid,
// AVM avm_local_bb1_ld__inst0
output logic avm_local_bb1_ld__inst0_read,
output logic avm_local_bb1_ld__inst0_write,
output logic [4:0] avm_local_bb1_ld__inst0_burstcount,
output logic [29:0] avm_local_bb1_ld__inst0_address,
output logic [255:0] avm_local_bb1_ld__inst0_writedata,
output logic [31:0] avm_local_bb1_ld__inst0_byteenable,
input logic avm_local_bb1_ld__inst0_waitrequest,
input logic [255:0] avm_local_bb1_ld__inst0_readdata,
input logic avm_local_bb1_ld__inst0_readdatavalid,
input logic avm_local_bb1_ld__inst0_writeack,
// AVM avm_local_bb1_st_add43_lobit_inst0
output logic avm_local_bb1_st_add43_lobit_inst0_read,
output logic avm_local_bb1_st_add43_lobit_inst0_write,
output logic [4:0] avm_local_bb1_st_add43_lobit_inst0_burstcount,
output logic [29:0] avm_local_bb1_st_add43_lobit_inst0_address,
output logic [255:0] avm_local_bb1_st_add43_lobit_inst0_writedata,
output logic [31:0] avm_local_bb1_st_add43_lobit_inst0_byteenable,
input logic avm_local_bb1_st_add43_lobit_inst0_waitrequest,
input logic [255:0] avm_local_bb1_st_add43_lobit_inst0_readdata,
input logic avm_local_bb1_st_add43_lobit_inst0_readdatavalid,
input logic avm_local_bb1_st_add43_lobit_inst0_writeack
);
logic lmem_invalid_single_bit;
// INST kernel of sobel_function_wrapper
sobel_function_wrapper kernel
(
.local_router_hang(lmem_invalid_single_bit),
.clock(clock),
.clock2x(clock2x),
.resetn(resetn),
.cra_irq(cra_irq),
// AVS avs_cra
.avs_cra_read(avs_cra_read),
.avs_cra_write(avs_cra_write),
.avs_cra_address(avs_cra_address),
.avs_cra_writedata(avs_cra_writedata),
.avs_cra_byteenable(avs_cra_byteenable),
.avs_cra_waitrequest(avs_cra_waitrequest),
.avs_cra_readdata(avs_cra_readdata),
.avs_cra_readdatavalid(avs_cra_readdatavalid),
// AVM avm_local_bb1_ld__inst0
.avm_local_bb1_ld__inst0_read(avm_local_bb1_ld__inst0_read),
.avm_local_bb1_ld__inst0_write(avm_local_bb1_ld__inst0_write),
.avm_local_bb1_ld__inst0_burstcount(avm_local_bb1_ld__inst0_burstcount),
.avm_local_bb1_ld__inst0_address(avm_local_bb1_ld__inst0_address),
.avm_local_bb1_ld__inst0_writedata(avm_local_bb1_ld__inst0_writedata),
.avm_local_bb1_ld__inst0_byteenable(avm_local_bb1_ld__inst0_byteenable),
.avm_local_bb1_ld__inst0_waitrequest(avm_local_bb1_ld__inst0_waitrequest),
.avm_local_bb1_ld__inst0_readdata(avm_local_bb1_ld__inst0_readdata),
.avm_local_bb1_ld__inst0_readdatavalid(avm_local_bb1_ld__inst0_readdatavalid),
.avm_local_bb1_ld__inst0_writeack(avm_local_bb1_ld__inst0_writeack),
// AVM avm_local_bb1_st_add43_lobit_inst0
.avm_local_bb1_st_add43_lobit_inst0_read(avm_local_bb1_st_add43_lobit_inst0_read),
.avm_local_bb1_st_add43_lobit_inst0_write(avm_local_bb1_st_add43_lobit_inst0_write),
.avm_local_bb1_st_add43_lobit_inst0_burstcount(avm_local_bb1_st_add43_lobit_inst0_burstcount),
.avm_local_bb1_st_add43_lobit_inst0_address(avm_local_bb1_st_add43_lobit_inst0_address),
.avm_local_bb1_st_add43_lobit_inst0_writedata(avm_local_bb1_st_add43_lobit_inst0_writedata),
.avm_local_bb1_st_add43_lobit_inst0_byteenable(avm_local_bb1_st_add43_lobit_inst0_byteenable),
.avm_local_bb1_st_add43_lobit_inst0_waitrequest(avm_local_bb1_st_add43_lobit_inst0_waitrequest),
.avm_local_bb1_st_add43_lobit_inst0_readdata(avm_local_bb1_st_add43_lobit_inst0_readdata),
.avm_local_bb1_st_add43_lobit_inst0_readdatavalid(avm_local_bb1_st_add43_lobit_inst0_readdatavalid),
.avm_local_bb1_st_add43_lobit_inst0_writeack(avm_local_bb1_st_add43_lobit_inst0_writeack)
);
assign lmem_invalid_single_bit = 'b0;
endmodule
/////////////////////////////////////////////////////////////////
// MODULE interconnect_0
/////////////////////////////////////////////////////////////////
module interconnect_0
(
input logic clock,
input logic resetn,
// ICM m
input logic m_arb_request [1],
input logic m_arb_read [1],
input logic m_arb_write [1],
input logic [4:0] m_arb_burstcount [1],
input logic [24:0] m_arb_address [1],
input logic [255:0] m_arb_writedata [1],
input logic [31:0] m_arb_byteenable [1],
output logic m_arb_stall [1],
output logic m_wrp_ack [1],
output logic m_rrp_datavalid [1],
output logic [255:0] m_rrp_data [1],
// ICM mout
output logic mout_arb_request,
output logic mout_arb_read,
output logic mout_arb_write,
output logic [4:0] mout_arb_burstcount,
output logic [24:0] mout_arb_address,
output logic [255:0] mout_arb_writedata,
output logic [31:0] mout_arb_byteenable,
output logic mout_arb_id,
input logic mout_arb_stall,
input logic mout_wrp_ack,
input logic mout_rrp_datavalid,
input logic [255:0] mout_rrp_data
);
genvar i;
generate
for( i = 0; i < 1; i = i + 1 )
begin:m
logic id;
acl_ic_master_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
assign id = i;
// INST m_endp of acl_ic_master_endpoint
acl_ic_master_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.TOTAL_NUM_MASTERS(1),
.ID(i)
)
m_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(m_intf),
.arb_intf(arb_intf),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
assign m_intf.arb.req.request = m_arb_request[i];
assign m_intf.arb.req.read = m_arb_read[i];
assign m_intf.arb.req.write = m_arb_write[i];
assign m_intf.arb.req.burstcount = m_arb_burstcount[i];
assign m_intf.arb.req.address = m_arb_address[i];
assign m_intf.arb.req.writedata = m_arb_writedata[i];
assign m_intf.arb.req.byteenable = m_arb_byteenable[i];
assign m_arb_stall[i] = m_intf.arb.stall;
assign m_wrp_ack[i] = m_intf.wrp.ack;
assign m_rrp_datavalid[i] = m_intf.rrp.datavalid;
assign m_rrp_data[i] = m_intf.rrp.data;
assign m_intf.arb.req.id = id;
end
endgenerate
generate
begin:s
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) in_arb_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) out_arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
// INST s_endp of acl_ic_slave_endpoint
acl_ic_slave_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.NUM_MASTERS(1),
.PIPELINE_RETURN_PATHS(1),
.WRP_FIFO_DEPTH(64),
.RRP_FIFO_DEPTH(64),
.RRP_USE_LL_FIFO(1),
.SLAVE_FIXED_LATENCY(0),
.SEPARATE_READ_WRITE_STALLS(0)
)
s_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(in_arb_intf),
.s_intf(out_arb_intf),
.s_readdatavalid(mout_rrp_datavalid),
.s_readdata(mout_rrp_data),
.s_writeack(mout_wrp_ack),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
end
endgenerate
generate
begin:wrp
assign m[0].wrp_intf.ack = s.wrp_intf.ack;
assign m[0].wrp_intf.id = s.wrp_intf.id;
end
endgenerate
generate
begin:rrp
end
endgenerate
assign mout_arb_request = s.out_arb_intf.req.request;
assign mout_arb_read = s.out_arb_intf.req.read;
assign mout_arb_write = s.out_arb_intf.req.write;
assign mout_arb_burstcount = s.out_arb_intf.req.burstcount;
assign mout_arb_address = s.out_arb_intf.req.address;
assign mout_arb_writedata = s.out_arb_intf.req.writedata;
assign mout_arb_byteenable = s.out_arb_intf.req.byteenable;
assign mout_arb_id = s.out_arb_intf.req.id;
assign s.out_arb_intf.stall = mout_arb_stall;
assign s.in_arb_intf.req = m[0].arb_intf.req;
assign m[0].arb_intf.stall = s.in_arb_intf.stall;
endmodule
/////////////////////////////////////////////////////////////////
// MODULE interconnect_1
/////////////////////////////////////////////////////////////////
module interconnect_1
(
input logic clock,
input logic resetn,
// ICM m
input logic m_arb_request [1],
input logic m_arb_read [1],
input logic m_arb_write [1],
input logic [4:0] m_arb_burstcount [1],
input logic [24:0] m_arb_address [1],
input logic [255:0] m_arb_writedata [1],
input logic [31:0] m_arb_byteenable [1],
output logic m_arb_stall [1],
output logic m_wrp_ack [1],
output logic m_rrp_datavalid [1],
output logic [255:0] m_rrp_data [1],
// ICM mout
output logic mout_arb_request,
output logic mout_arb_read,
output logic mout_arb_write,
output logic [4:0] mout_arb_burstcount,
output logic [24:0] mout_arb_address,
output logic [255:0] mout_arb_writedata,
output logic [31:0] mout_arb_byteenable,
output logic mout_arb_id,
input logic mout_arb_stall,
input logic mout_wrp_ack,
input logic mout_rrp_datavalid,
input logic [255:0] mout_rrp_data
);
genvar i;
generate
for( i = 0; i < 1; i = i + 1 )
begin:m
logic id;
acl_ic_master_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
assign id = i;
// INST m_endp of acl_ic_master_endpoint
acl_ic_master_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.TOTAL_NUM_MASTERS(1),
.ID(i)
)
m_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(m_intf),
.arb_intf(arb_intf),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
assign m_intf.arb.req.request = m_arb_request[i];
assign m_intf.arb.req.read = m_arb_read[i];
assign m_intf.arb.req.write = m_arb_write[i];
assign m_intf.arb.req.burstcount = m_arb_burstcount[i];
assign m_intf.arb.req.address = m_arb_address[i];
assign m_intf.arb.req.writedata = m_arb_writedata[i];
assign m_intf.arb.req.byteenable = m_arb_byteenable[i];
assign m_arb_stall[i] = m_intf.arb.stall;
assign m_wrp_ack[i] = m_intf.wrp.ack;
assign m_rrp_datavalid[i] = m_intf.rrp.datavalid;
assign m_rrp_data[i] = m_intf.rrp.data;
assign m_intf.arb.req.id = id;
end
endgenerate
generate
begin:s
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) in_arb_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) out_arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
// INST s_endp of acl_ic_slave_endpoint
acl_ic_slave_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.NUM_MASTERS(1),
.PIPELINE_RETURN_PATHS(1),
.WRP_FIFO_DEPTH(64),
.RRP_FIFO_DEPTH(64),
.RRP_USE_LL_FIFO(1),
.SLAVE_FIXED_LATENCY(0),
.SEPARATE_READ_WRITE_STALLS(0)
)
s_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(in_arb_intf),
.s_intf(out_arb_intf),
.s_readdatavalid(mout_rrp_datavalid),
.s_readdata(mout_rrp_data),
.s_writeack(mout_wrp_ack),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
end
endgenerate
generate
begin:wrp
end
endgenerate
generate
begin:rrp
assign m[0].rrp_intf.datavalid = s.rrp_intf.datavalid;
assign m[0].rrp_intf.data = s.rrp_intf.data;
assign m[0].rrp_intf.id = s.rrp_intf.id;
end
endgenerate
assign mout_arb_request = s.out_arb_intf.req.request;
assign mout_arb_read = s.out_arb_intf.req.read;
assign mout_arb_write = s.out_arb_intf.req.write;
assign mout_arb_burstcount = s.out_arb_intf.req.burstcount;
assign mout_arb_address = s.out_arb_intf.req.address;
assign mout_arb_writedata = s.out_arb_intf.req.writedata;
assign mout_arb_byteenable = s.out_arb_intf.req.byteenable;
assign mout_arb_id = s.out_arb_intf.req.id;
assign s.out_arb_intf.stall = mout_arb_stall;
assign s.in_arb_intf.req = m[0].arb_intf.req;
assign m[0].arb_intf.stall = s.in_arb_intf.stall;
endmodule
/////////////////////////////////////////////////////////////////
// MODULE interconnect_2
/////////////////////////////////////////////////////////////////
module interconnect_2
(
input logic clock,
input logic resetn,
// ICM m
input logic m_arb_request [2],
input logic m_arb_read [2],
input logic m_arb_write [2],
input logic [4:0] m_arb_burstcount [2],
input logic [24:0] m_arb_address [2],
input logic [255:0] m_arb_writedata [2],
input logic [31:0] m_arb_byteenable [2],
output logic m_arb_stall [2],
output logic m_wrp_ack [2],
output logic m_rrp_datavalid [2],
output logic [255:0] m_rrp_data [2],
// ICM mout
output logic mout_arb_request,
output logic mout_arb_read,
output logic mout_arb_write,
output logic [4:0] mout_arb_burstcount,
output logic [24:0] mout_arb_address,
output logic [255:0] mout_arb_writedata,
output logic [31:0] mout_arb_byteenable,
output logic mout_arb_id,
input logic mout_arb_stall,
input logic mout_wrp_ack,
input logic mout_rrp_datavalid,
input logic [255:0] mout_rrp_data
);
genvar i;
generate
for( i = 0; i < 2; i = i + 1 )
begin:m
logic id;
acl_ic_master_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
assign id = i;
// INST m_endp of acl_ic_master_endpoint
acl_ic_master_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.TOTAL_NUM_MASTERS(2),
.ID(i)
)
m_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(m_intf),
.arb_intf(arb_intf),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
assign m_intf.arb.req.request = m_arb_request[i];
assign m_intf.arb.req.read = m_arb_read[i];
assign m_intf.arb.req.write = m_arb_write[i];
assign m_intf.arb.req.burstcount = m_arb_burstcount[i];
assign m_intf.arb.req.address = m_arb_address[i];
assign m_intf.arb.req.writedata = m_arb_writedata[i];
assign m_intf.arb.req.byteenable = m_arb_byteenable[i];
assign m_arb_stall[i] = m_intf.arb.stall;
assign m_wrp_ack[i] = m_intf.wrp.ack;
assign m_rrp_datavalid[i] = m_intf.rrp.datavalid;
assign m_rrp_data[i] = m_intf.rrp.data;
assign m_intf.arb.req.id = id;
end
endgenerate
generate
begin:s
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) in_arb_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) out_arb_intf();
acl_ic_wrp_intf
#(
.ID_W(1)
) wrp_intf();
acl_ic_rrp_intf
#(
.DATA_W(256),
.ID_W(1)
) rrp_intf();
// INST s_endp of acl_ic_slave_endpoint
acl_ic_slave_endpoint
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.NUM_MASTERS(2),
.PIPELINE_RETURN_PATHS(1),
.WRP_FIFO_DEPTH(0),
.RRP_FIFO_DEPTH(64),
.RRP_USE_LL_FIFO(1),
.SLAVE_FIXED_LATENCY(0),
.SEPARATE_READ_WRITE_STALLS(0)
)
s_endp
(
.clock(clock),
.resetn(resetn),
.m_intf(in_arb_intf),
.s_intf(out_arb_intf),
.s_readdatavalid(mout_rrp_datavalid),
.s_readdata(mout_rrp_data),
.s_writeack(mout_wrp_ack),
.wrp_intf(wrp_intf),
.rrp_intf(rrp_intf)
);
end
endgenerate
generate
begin:wrp
assign m[0].wrp_intf.ack = s.wrp_intf.ack;
assign m[0].wrp_intf.id = s.wrp_intf.id;
assign m[1].wrp_intf.ack = s.wrp_intf.ack;
assign m[1].wrp_intf.id = s.wrp_intf.id;
end
endgenerate
generate
begin:rrp
assign m[0].rrp_intf.datavalid = s.rrp_intf.datavalid;
assign m[0].rrp_intf.data = s.rrp_intf.data;
assign m[0].rrp_intf.id = s.rrp_intf.id;
assign m[1].rrp_intf.datavalid = s.rrp_intf.datavalid;
assign m[1].rrp_intf.data = s.rrp_intf.data;
assign m[1].rrp_intf.id = s.rrp_intf.id;
end
endgenerate
generate
for( i = 0; i < 1; i = i + 1 )
begin:a
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m0_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) m1_intf();
acl_arb_intf
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1)
) mout_intf();
// INST a of acl_arb2
acl_arb2
#(
.DATA_W(256),
.BURSTCOUNT_W(5),
.ADDRESS_W(25),
.BYTEENA_W(32),
.ID_W(1),
.PIPELINE("none"),
.KEEP_LAST_GRANT(1),
.NO_STALL_NETWORK(0)
)
a
(
.clock(clock),
.resetn(resetn),
.m0_intf(m0_intf),
.m1_intf(m1_intf),
.mout_intf(mout_intf)
);
end
endgenerate
assign mout_arb_request = s.out_arb_intf.req.request;
assign mout_arb_read = s.out_arb_intf.req.read;
assign mout_arb_write = s.out_arb_intf.req.write;
assign mout_arb_burstcount = s.out_arb_intf.req.burstcount;
assign mout_arb_address = s.out_arb_intf.req.address;
assign mout_arb_writedata = s.out_arb_intf.req.writedata;
assign mout_arb_byteenable = s.out_arb_intf.req.byteenable;
assign mout_arb_id = s.out_arb_intf.req.id;
assign s.out_arb_intf.stall = mout_arb_stall;
assign s.in_arb_intf.req = a[0].mout_intf.req;
assign a[0].mout_intf.stall = s.in_arb_intf.stall;
assign a[0].m0_intf.req = m[0].arb_intf.req;
assign m[0].arb_intf.stall = a[0].m0_intf.stall;
assign a[0].m1_intf.req = m[1].arb_intf.req;
assign m[1].arb_intf.stall = a[0].m1_intf.stall;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:39:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_overlay_0_0 -prefix
// system_vga_overlay_0_0_ system_vga_overlay_0_0_sim_netlist.v
// Design : system_vga_overlay_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_overlay_0_0,vga_overlay,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_overlay,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_overlay_0_0
(clk,
rgb_0,
rgb_1,
rgb);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
wire clk;
wire [23:0]rgb;
wire [23:0]rgb_0;
wire [23:0]rgb_1;
system_vga_overlay_0_0_vga_overlay U0
(.clk(clk),
.rgb(rgb),
.rgb_0({rgb_0[23:17],rgb_0[15:9],rgb_0[7:1]}),
.rgb_1({rgb_1[23:17],rgb_1[15:9],rgb_1[7:1]}));
endmodule
module system_vga_overlay_0_0_vga_overlay
(rgb,
rgb_1,
clk,
rgb_0);
output [23:0]rgb;
input [20:0]rgb_1;
input clk;
input [20:0]rgb_0;
wire [6:0]b_0;
wire [6:0]b_1;
wire clk;
wire [6:0]g_0;
wire [6:0]g_1;
wire [6:0]r_0;
wire [6:0]r_1;
wire [23:0]rgb;
wire [7:0]rgb0;
wire [7:0]rgb00_out;
wire [7:0]rgb01_out;
wire \rgb[11]_i_2_n_0 ;
wire \rgb[11]_i_3_n_0 ;
wire \rgb[11]_i_4_n_0 ;
wire \rgb[11]_i_5_n_0 ;
wire \rgb[15]_i_2_n_0 ;
wire \rgb[15]_i_3_n_0 ;
wire \rgb[15]_i_4_n_0 ;
wire \rgb[19]_i_2_n_0 ;
wire \rgb[19]_i_3_n_0 ;
wire \rgb[19]_i_4_n_0 ;
wire \rgb[19]_i_5_n_0 ;
wire \rgb[23]_i_2_n_0 ;
wire \rgb[23]_i_3_n_0 ;
wire \rgb[23]_i_4_n_0 ;
wire \rgb[3]_i_2_n_0 ;
wire \rgb[3]_i_3_n_0 ;
wire \rgb[3]_i_4_n_0 ;
wire \rgb[3]_i_5_n_0 ;
wire \rgb[7]_i_2_n_0 ;
wire \rgb[7]_i_3_n_0 ;
wire \rgb[7]_i_4_n_0 ;
wire [20:0]rgb_0;
wire [20:0]rgb_1;
wire \rgb_reg[11]_i_1_n_0 ;
wire \rgb_reg[11]_i_1_n_1 ;
wire \rgb_reg[11]_i_1_n_2 ;
wire \rgb_reg[11]_i_1_n_3 ;
wire \rgb_reg[15]_i_1_n_2 ;
wire \rgb_reg[15]_i_1_n_3 ;
wire \rgb_reg[19]_i_1_n_0 ;
wire \rgb_reg[19]_i_1_n_1 ;
wire \rgb_reg[19]_i_1_n_2 ;
wire \rgb_reg[19]_i_1_n_3 ;
wire \rgb_reg[23]_i_1_n_2 ;
wire \rgb_reg[23]_i_1_n_3 ;
wire \rgb_reg[3]_i_1_n_0 ;
wire \rgb_reg[3]_i_1_n_1 ;
wire \rgb_reg[3]_i_1_n_2 ;
wire \rgb_reg[3]_i_1_n_3 ;
wire \rgb_reg[7]_i_1_n_2 ;
wire \rgb_reg[7]_i_1_n_3 ;
wire [2:2]\NLW_rgb_reg[15]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_reg[15]_i_1_O_UNCONNECTED ;
wire [2:2]\NLW_rgb_reg[23]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_reg[23]_i_1_O_UNCONNECTED ;
wire [2:2]\NLW_rgb_reg[7]_i_1_CO_UNCONNECTED ;
wire [3:3]\NLW_rgb_reg[7]_i_1_O_UNCONNECTED ;
FDRE \b_0_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_0[0]),
.Q(b_0[0]),
.R(1'b0));
FDRE \b_0_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_0[1]),
.Q(b_0[1]),
.R(1'b0));
FDRE \b_0_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_0[2]),
.Q(b_0[2]),
.R(1'b0));
FDRE \b_0_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_0[3]),
.Q(b_0[3]),
.R(1'b0));
FDRE \b_0_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_0[4]),
.Q(b_0[4]),
.R(1'b0));
FDRE \b_0_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_0[5]),
.Q(b_0[5]),
.R(1'b0));
FDRE \b_0_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_0[6]),
.Q(b_0[6]),
.R(1'b0));
FDRE \b_1_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_1[0]),
.Q(b_1[0]),
.R(1'b0));
FDRE \b_1_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_1[1]),
.Q(b_1[1]),
.R(1'b0));
FDRE \b_1_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_1[2]),
.Q(b_1[2]),
.R(1'b0));
FDRE \b_1_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_1[3]),
.Q(b_1[3]),
.R(1'b0));
FDRE \b_1_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_1[4]),
.Q(b_1[4]),
.R(1'b0));
FDRE \b_1_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_1[5]),
.Q(b_1[5]),
.R(1'b0));
FDRE \b_1_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_1[6]),
.Q(b_1[6]),
.R(1'b0));
FDRE \g_0_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_0[7]),
.Q(g_0[0]),
.R(1'b0));
FDRE \g_0_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_0[8]),
.Q(g_0[1]),
.R(1'b0));
FDRE \g_0_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_0[9]),
.Q(g_0[2]),
.R(1'b0));
FDRE \g_0_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_0[10]),
.Q(g_0[3]),
.R(1'b0));
FDRE \g_0_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_0[11]),
.Q(g_0[4]),
.R(1'b0));
FDRE \g_0_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_0[12]),
.Q(g_0[5]),
.R(1'b0));
FDRE \g_0_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_0[13]),
.Q(g_0[6]),
.R(1'b0));
FDRE \g_1_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_1[7]),
.Q(g_1[0]),
.R(1'b0));
FDRE \g_1_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_1[8]),
.Q(g_1[1]),
.R(1'b0));
FDRE \g_1_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_1[9]),
.Q(g_1[2]),
.R(1'b0));
FDRE \g_1_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_1[10]),
.Q(g_1[3]),
.R(1'b0));
FDRE \g_1_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_1[11]),
.Q(g_1[4]),
.R(1'b0));
FDRE \g_1_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_1[12]),
.Q(g_1[5]),
.R(1'b0));
FDRE \g_1_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_1[13]),
.Q(g_1[6]),
.R(1'b0));
FDRE \r_0_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_0[14]),
.Q(r_0[0]),
.R(1'b0));
FDRE \r_0_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_0[15]),
.Q(r_0[1]),
.R(1'b0));
FDRE \r_0_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_0[16]),
.Q(r_0[2]),
.R(1'b0));
FDRE \r_0_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_0[17]),
.Q(r_0[3]),
.R(1'b0));
FDRE \r_0_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_0[18]),
.Q(r_0[4]),
.R(1'b0));
FDRE \r_0_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_0[19]),
.Q(r_0[5]),
.R(1'b0));
FDRE \r_0_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_0[20]),
.Q(r_0[6]),
.R(1'b0));
FDRE \r_1_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb_1[14]),
.Q(r_1[0]),
.R(1'b0));
FDRE \r_1_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb_1[15]),
.Q(r_1[1]),
.R(1'b0));
FDRE \r_1_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb_1[16]),
.Q(r_1[2]),
.R(1'b0));
FDRE \r_1_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb_1[17]),
.Q(r_1[3]),
.R(1'b0));
FDRE \r_1_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb_1[18]),
.Q(r_1[4]),
.R(1'b0));
FDRE \r_1_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb_1[19]),
.Q(r_1[5]),
.R(1'b0));
FDRE \r_1_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb_1[20]),
.Q(r_1[6]),
.R(1'b0));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_2
(.I0(g_0[3]),
.I1(g_1[3]),
.O(\rgb[11]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_3
(.I0(g_0[2]),
.I1(g_1[2]),
.O(\rgb[11]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_4
(.I0(g_0[1]),
.I1(g_1[1]),
.O(\rgb[11]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[11]_i_5
(.I0(g_0[0]),
.I1(g_1[0]),
.O(\rgb[11]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[15]_i_2
(.I0(g_0[6]),
.I1(g_1[6]),
.O(\rgb[15]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[15]_i_3
(.I0(g_0[5]),
.I1(g_1[5]),
.O(\rgb[15]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[15]_i_4
(.I0(g_0[4]),
.I1(g_1[4]),
.O(\rgb[15]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_2
(.I0(r_0[3]),
.I1(r_1[3]),
.O(\rgb[19]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_3
(.I0(r_0[2]),
.I1(r_1[2]),
.O(\rgb[19]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_4
(.I0(r_0[1]),
.I1(r_1[1]),
.O(\rgb[19]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[19]_i_5
(.I0(r_0[0]),
.I1(r_1[0]),
.O(\rgb[19]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[23]_i_2
(.I0(r_0[6]),
.I1(r_1[6]),
.O(\rgb[23]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[23]_i_3
(.I0(r_0[5]),
.I1(r_1[5]),
.O(\rgb[23]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[23]_i_4
(.I0(r_0[4]),
.I1(r_1[4]),
.O(\rgb[23]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_2
(.I0(b_0[3]),
.I1(b_1[3]),
.O(\rgb[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_3
(.I0(b_0[2]),
.I1(b_1[2]),
.O(\rgb[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_4
(.I0(b_0[1]),
.I1(b_1[1]),
.O(\rgb[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[3]_i_5
(.I0(b_0[0]),
.I1(b_1[0]),
.O(\rgb[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[7]_i_2
(.I0(b_0[6]),
.I1(b_1[6]),
.O(\rgb[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[7]_i_3
(.I0(b_0[5]),
.I1(b_1[5]),
.O(\rgb[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h6))
\rgb[7]_i_4
(.I0(b_0[4]),
.I1(b_1[4]),
.O(\rgb[7]_i_4_n_0 ));
FDRE \rgb_reg[0]
(.C(clk),
.CE(1'b1),
.D(rgb0[0]),
.Q(rgb[0]),
.R(1'b0));
FDRE \rgb_reg[10]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[2]),
.Q(rgb[10]),
.R(1'b0));
FDRE \rgb_reg[11]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[3]),
.Q(rgb[11]),
.R(1'b0));
CARRY4 \rgb_reg[11]_i_1
(.CI(1'b0),
.CO({\rgb_reg[11]_i_1_n_0 ,\rgb_reg[11]_i_1_n_1 ,\rgb_reg[11]_i_1_n_2 ,\rgb_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(g_0[3:0]),
.O(rgb00_out[3:0]),
.S({\rgb[11]_i_2_n_0 ,\rgb[11]_i_3_n_0 ,\rgb[11]_i_4_n_0 ,\rgb[11]_i_5_n_0 }));
FDRE \rgb_reg[12]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[4]),
.Q(rgb[12]),
.R(1'b0));
FDRE \rgb_reg[13]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[5]),
.Q(rgb[13]),
.R(1'b0));
FDRE \rgb_reg[14]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[6]),
.Q(rgb[14]),
.R(1'b0));
FDRE \rgb_reg[15]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[7]),
.Q(rgb[15]),
.R(1'b0));
CARRY4 \rgb_reg[15]_i_1
(.CI(\rgb_reg[11]_i_1_n_0 ),
.CO({rgb00_out[7],\NLW_rgb_reg[15]_i_1_CO_UNCONNECTED [2],\rgb_reg[15]_i_1_n_2 ,\rgb_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,g_0[6:4]}),
.O({\NLW_rgb_reg[15]_i_1_O_UNCONNECTED [3],rgb00_out[6:4]}),
.S({1'b1,\rgb[15]_i_2_n_0 ,\rgb[15]_i_3_n_0 ,\rgb[15]_i_4_n_0 }));
FDRE \rgb_reg[16]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[0]),
.Q(rgb[16]),
.R(1'b0));
FDRE \rgb_reg[17]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[1]),
.Q(rgb[17]),
.R(1'b0));
FDRE \rgb_reg[18]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[2]),
.Q(rgb[18]),
.R(1'b0));
FDRE \rgb_reg[19]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[3]),
.Q(rgb[19]),
.R(1'b0));
CARRY4 \rgb_reg[19]_i_1
(.CI(1'b0),
.CO({\rgb_reg[19]_i_1_n_0 ,\rgb_reg[19]_i_1_n_1 ,\rgb_reg[19]_i_1_n_2 ,\rgb_reg[19]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(r_0[3:0]),
.O(rgb01_out[3:0]),
.S({\rgb[19]_i_2_n_0 ,\rgb[19]_i_3_n_0 ,\rgb[19]_i_4_n_0 ,\rgb[19]_i_5_n_0 }));
FDRE \rgb_reg[1]
(.C(clk),
.CE(1'b1),
.D(rgb0[1]),
.Q(rgb[1]),
.R(1'b0));
FDRE \rgb_reg[20]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[4]),
.Q(rgb[20]),
.R(1'b0));
FDRE \rgb_reg[21]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[5]),
.Q(rgb[21]),
.R(1'b0));
FDRE \rgb_reg[22]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[6]),
.Q(rgb[22]),
.R(1'b0));
FDRE \rgb_reg[23]
(.C(clk),
.CE(1'b1),
.D(rgb01_out[7]),
.Q(rgb[23]),
.R(1'b0));
CARRY4 \rgb_reg[23]_i_1
(.CI(\rgb_reg[19]_i_1_n_0 ),
.CO({rgb01_out[7],\NLW_rgb_reg[23]_i_1_CO_UNCONNECTED [2],\rgb_reg[23]_i_1_n_2 ,\rgb_reg[23]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,r_0[6:4]}),
.O({\NLW_rgb_reg[23]_i_1_O_UNCONNECTED [3],rgb01_out[6:4]}),
.S({1'b1,\rgb[23]_i_2_n_0 ,\rgb[23]_i_3_n_0 ,\rgb[23]_i_4_n_0 }));
FDRE \rgb_reg[2]
(.C(clk),
.CE(1'b1),
.D(rgb0[2]),
.Q(rgb[2]),
.R(1'b0));
FDRE \rgb_reg[3]
(.C(clk),
.CE(1'b1),
.D(rgb0[3]),
.Q(rgb[3]),
.R(1'b0));
CARRY4 \rgb_reg[3]_i_1
(.CI(1'b0),
.CO({\rgb_reg[3]_i_1_n_0 ,\rgb_reg[3]_i_1_n_1 ,\rgb_reg[3]_i_1_n_2 ,\rgb_reg[3]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(b_0[3:0]),
.O(rgb0[3:0]),
.S({\rgb[3]_i_2_n_0 ,\rgb[3]_i_3_n_0 ,\rgb[3]_i_4_n_0 ,\rgb[3]_i_5_n_0 }));
FDRE \rgb_reg[4]
(.C(clk),
.CE(1'b1),
.D(rgb0[4]),
.Q(rgb[4]),
.R(1'b0));
FDRE \rgb_reg[5]
(.C(clk),
.CE(1'b1),
.D(rgb0[5]),
.Q(rgb[5]),
.R(1'b0));
FDRE \rgb_reg[6]
(.C(clk),
.CE(1'b1),
.D(rgb0[6]),
.Q(rgb[6]),
.R(1'b0));
FDRE \rgb_reg[7]
(.C(clk),
.CE(1'b1),
.D(rgb0[7]),
.Q(rgb[7]),
.R(1'b0));
CARRY4 \rgb_reg[7]_i_1
(.CI(\rgb_reg[3]_i_1_n_0 ),
.CO({rgb0[7],\NLW_rgb_reg[7]_i_1_CO_UNCONNECTED [2],\rgb_reg[7]_i_1_n_2 ,\rgb_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,b_0[6:4]}),
.O({\NLW_rgb_reg[7]_i_1_O_UNCONNECTED [3],rgb0[6:4]}),
.S({1'b1,\rgb[7]_i_2_n_0 ,\rgb[7]_i_3_n_0 ,\rgb[7]_i_4_n_0 }));
FDRE \rgb_reg[8]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[0]),
.Q(rgb[8]),
.R(1'b0));
FDRE \rgb_reg[9]
(.C(clk),
.CE(1'b1),
.D(rgb00_out[1]),
.Q(rgb[9]),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_BLACKBOX_V
`define SKY130_FD_SC_HS__A211OI_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a211oi (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_BLACKBOX_V
|
// system_acl_iface_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_0 (
input wire [11:0] hps_h2f_lw_axi_master_awid, // hps_h2f_lw_axi_master.awid
input wire [20:0] hps_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_h2f_lw_axi_master_awprot, // .awprot
input wire hps_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_h2f_lw_axi_master_wlast, // .wlast
input wire hps_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_h2f_lw_axi_master_bresp, // .bresp
output wire hps_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_h2f_lw_axi_master_arprot, // .arprot
input wire hps_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_h2f_lw_axi_master_rresp, // .rresp
output wire hps_h2f_lw_axi_master_rlast, // .rlast
output wire hps_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_h2f_lw_axi_master_rready, // .rready
input wire config_clk_out_clk_clk, // config_clk_out_clk.clk
input wire hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
input wire version_id_clk_reset_reset_bridge_in_reset_reset, // version_id_clk_reset_reset_bridge_in_reset.reset
output wire [10:0] acl_kernel_clk_ctrl_address, // acl_kernel_clk_ctrl.address
output wire acl_kernel_clk_ctrl_write, // .write
output wire acl_kernel_clk_ctrl_read, // .read
input wire [31:0] acl_kernel_clk_ctrl_readdata, // .readdata
output wire [31:0] acl_kernel_clk_ctrl_writedata, // .writedata
output wire [0:0] acl_kernel_clk_ctrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_clk_ctrl_byteenable, // .byteenable
input wire acl_kernel_clk_ctrl_readdatavalid, // .readdatavalid
input wire acl_kernel_clk_ctrl_waitrequest, // .waitrequest
output wire acl_kernel_clk_ctrl_debugaccess, // .debugaccess
output wire [13:0] acl_kernel_interface_kernel_cntrl_address, // acl_kernel_interface_kernel_cntrl.address
output wire acl_kernel_interface_kernel_cntrl_write, // .write
output wire acl_kernel_interface_kernel_cntrl_read, // .read
input wire [31:0] acl_kernel_interface_kernel_cntrl_readdata, // .readdata
output wire [31:0] acl_kernel_interface_kernel_cntrl_writedata, // .writedata
output wire [0:0] acl_kernel_interface_kernel_cntrl_burstcount, // .burstcount
output wire [3:0] acl_kernel_interface_kernel_cntrl_byteenable, // .byteenable
input wire acl_kernel_interface_kernel_cntrl_readdatavalid, // .readdatavalid
input wire acl_kernel_interface_kernel_cntrl_waitrequest, // .waitrequest
output wire acl_kernel_interface_kernel_cntrl_debugaccess, // .debugaccess
output wire version_id_s_read, // version_id_s.read
input wire [31:0] version_id_s_readdata // .readdata
);
wire [31:0] version_id_s_agent_m0_readdata; // version_id_s_translator:uav_readdata -> version_id_s_agent:m0_readdata
wire version_id_s_agent_m0_waitrequest; // version_id_s_translator:uav_waitrequest -> version_id_s_agent:m0_waitrequest
wire version_id_s_agent_m0_debugaccess; // version_id_s_agent:m0_debugaccess -> version_id_s_translator:uav_debugaccess
wire [20:0] version_id_s_agent_m0_address; // version_id_s_agent:m0_address -> version_id_s_translator:uav_address
wire [3:0] version_id_s_agent_m0_byteenable; // version_id_s_agent:m0_byteenable -> version_id_s_translator:uav_byteenable
wire version_id_s_agent_m0_read; // version_id_s_agent:m0_read -> version_id_s_translator:uav_read
wire version_id_s_agent_m0_readdatavalid; // version_id_s_translator:uav_readdatavalid -> version_id_s_agent:m0_readdatavalid
wire version_id_s_agent_m0_lock; // version_id_s_agent:m0_lock -> version_id_s_translator:uav_lock
wire [31:0] version_id_s_agent_m0_writedata; // version_id_s_agent:m0_writedata -> version_id_s_translator:uav_writedata
wire version_id_s_agent_m0_write; // version_id_s_agent:m0_write -> version_id_s_translator:uav_write
wire [2:0] version_id_s_agent_m0_burstcount; // version_id_s_agent:m0_burstcount -> version_id_s_translator:uav_burstcount
wire version_id_s_agent_rf_source_valid; // version_id_s_agent:rf_source_valid -> version_id_s_agent_rsp_fifo:in_valid
wire [114:0] version_id_s_agent_rf_source_data; // version_id_s_agent:rf_source_data -> version_id_s_agent_rsp_fifo:in_data
wire version_id_s_agent_rf_source_ready; // version_id_s_agent_rsp_fifo:in_ready -> version_id_s_agent:rf_source_ready
wire version_id_s_agent_rf_source_startofpacket; // version_id_s_agent:rf_source_startofpacket -> version_id_s_agent_rsp_fifo:in_startofpacket
wire version_id_s_agent_rf_source_endofpacket; // version_id_s_agent:rf_source_endofpacket -> version_id_s_agent_rsp_fifo:in_endofpacket
wire version_id_s_agent_rsp_fifo_out_valid; // version_id_s_agent_rsp_fifo:out_valid -> version_id_s_agent:rf_sink_valid
wire [114:0] version_id_s_agent_rsp_fifo_out_data; // version_id_s_agent_rsp_fifo:out_data -> version_id_s_agent:rf_sink_data
wire version_id_s_agent_rsp_fifo_out_ready; // version_id_s_agent:rf_sink_ready -> version_id_s_agent_rsp_fifo:out_ready
wire version_id_s_agent_rsp_fifo_out_startofpacket; // version_id_s_agent_rsp_fifo:out_startofpacket -> version_id_s_agent:rf_sink_startofpacket
wire version_id_s_agent_rsp_fifo_out_endofpacket; // version_id_s_agent_rsp_fifo:out_endofpacket -> version_id_s_agent:rf_sink_endofpacket
wire version_id_s_agent_rdata_fifo_src_valid; // version_id_s_agent:rdata_fifo_src_valid -> version_id_s_agent_rdata_fifo:in_valid
wire [33:0] version_id_s_agent_rdata_fifo_src_data; // version_id_s_agent:rdata_fifo_src_data -> version_id_s_agent_rdata_fifo:in_data
wire version_id_s_agent_rdata_fifo_src_ready; // version_id_s_agent_rdata_fifo:in_ready -> version_id_s_agent:rdata_fifo_src_ready
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_readdata; // acl_kernel_interface_kernel_cntrl_translator:uav_readdata -> acl_kernel_interface_kernel_cntrl_agent:m0_readdata
wire acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest; // acl_kernel_interface_kernel_cntrl_translator:uav_waitrequest -> acl_kernel_interface_kernel_cntrl_agent:m0_waitrequest
wire acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess; // acl_kernel_interface_kernel_cntrl_agent:m0_debugaccess -> acl_kernel_interface_kernel_cntrl_translator:uav_debugaccess
wire [20:0] acl_kernel_interface_kernel_cntrl_agent_m0_address; // acl_kernel_interface_kernel_cntrl_agent:m0_address -> acl_kernel_interface_kernel_cntrl_translator:uav_address
wire [3:0] acl_kernel_interface_kernel_cntrl_agent_m0_byteenable; // acl_kernel_interface_kernel_cntrl_agent:m0_byteenable -> acl_kernel_interface_kernel_cntrl_translator:uav_byteenable
wire acl_kernel_interface_kernel_cntrl_agent_m0_read; // acl_kernel_interface_kernel_cntrl_agent:m0_read -> acl_kernel_interface_kernel_cntrl_translator:uav_read
wire acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid; // acl_kernel_interface_kernel_cntrl_translator:uav_readdatavalid -> acl_kernel_interface_kernel_cntrl_agent:m0_readdatavalid
wire acl_kernel_interface_kernel_cntrl_agent_m0_lock; // acl_kernel_interface_kernel_cntrl_agent:m0_lock -> acl_kernel_interface_kernel_cntrl_translator:uav_lock
wire [31:0] acl_kernel_interface_kernel_cntrl_agent_m0_writedata; // acl_kernel_interface_kernel_cntrl_agent:m0_writedata -> acl_kernel_interface_kernel_cntrl_translator:uav_writedata
wire acl_kernel_interface_kernel_cntrl_agent_m0_write; // acl_kernel_interface_kernel_cntrl_agent:m0_write -> acl_kernel_interface_kernel_cntrl_translator:uav_write
wire [2:0] acl_kernel_interface_kernel_cntrl_agent_m0_burstcount; // acl_kernel_interface_kernel_cntrl_agent:m0_burstcount -> acl_kernel_interface_kernel_cntrl_translator:uav_burstcount
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_valid; // acl_kernel_interface_kernel_cntrl_agent:rf_source_valid -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_valid
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rf_source_data; // acl_kernel_interface_kernel_cntrl_agent:rf_source_data -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_ready; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rf_source_ready
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_startofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_startofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rf_source_endofpacket -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_valid -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_valid
wire [114:0] acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_data -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready; // acl_kernel_interface_kernel_cntrl_agent:rf_sink_ready -> acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_ready
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_startofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_interface_kernel_cntrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:rf_sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_valid -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_data -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:in_ready -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_src_ready
wire [31:0] acl_kernel_clk_ctrl_agent_m0_readdata; // acl_kernel_clk_ctrl_translator:uav_readdata -> acl_kernel_clk_ctrl_agent:m0_readdata
wire acl_kernel_clk_ctrl_agent_m0_waitrequest; // acl_kernel_clk_ctrl_translator:uav_waitrequest -> acl_kernel_clk_ctrl_agent:m0_waitrequest
wire acl_kernel_clk_ctrl_agent_m0_debugaccess; // acl_kernel_clk_ctrl_agent:m0_debugaccess -> acl_kernel_clk_ctrl_translator:uav_debugaccess
wire [20:0] acl_kernel_clk_ctrl_agent_m0_address; // acl_kernel_clk_ctrl_agent:m0_address -> acl_kernel_clk_ctrl_translator:uav_address
wire [3:0] acl_kernel_clk_ctrl_agent_m0_byteenable; // acl_kernel_clk_ctrl_agent:m0_byteenable -> acl_kernel_clk_ctrl_translator:uav_byteenable
wire acl_kernel_clk_ctrl_agent_m0_read; // acl_kernel_clk_ctrl_agent:m0_read -> acl_kernel_clk_ctrl_translator:uav_read
wire acl_kernel_clk_ctrl_agent_m0_readdatavalid; // acl_kernel_clk_ctrl_translator:uav_readdatavalid -> acl_kernel_clk_ctrl_agent:m0_readdatavalid
wire acl_kernel_clk_ctrl_agent_m0_lock; // acl_kernel_clk_ctrl_agent:m0_lock -> acl_kernel_clk_ctrl_translator:uav_lock
wire [31:0] acl_kernel_clk_ctrl_agent_m0_writedata; // acl_kernel_clk_ctrl_agent:m0_writedata -> acl_kernel_clk_ctrl_translator:uav_writedata
wire acl_kernel_clk_ctrl_agent_m0_write; // acl_kernel_clk_ctrl_agent:m0_write -> acl_kernel_clk_ctrl_translator:uav_write
wire [2:0] acl_kernel_clk_ctrl_agent_m0_burstcount; // acl_kernel_clk_ctrl_agent:m0_burstcount -> acl_kernel_clk_ctrl_translator:uav_burstcount
wire acl_kernel_clk_ctrl_agent_rf_source_valid; // acl_kernel_clk_ctrl_agent:rf_source_valid -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_valid
wire [114:0] acl_kernel_clk_ctrl_agent_rf_source_data; // acl_kernel_clk_ctrl_agent:rf_source_data -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rf_source_ready; // acl_kernel_clk_ctrl_agent_rsp_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rf_source_ready
wire acl_kernel_clk_ctrl_agent_rf_source_startofpacket; // acl_kernel_clk_ctrl_agent:rf_source_startofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_startofpacket
wire acl_kernel_clk_ctrl_agent_rf_source_endofpacket; // acl_kernel_clk_ctrl_agent:rf_source_endofpacket -> acl_kernel_clk_ctrl_agent_rsp_fifo:in_endofpacket
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_valid -> acl_kernel_clk_ctrl_agent:rf_sink_valid
wire [114:0] acl_kernel_clk_ctrl_agent_rsp_fifo_out_data; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_data -> acl_kernel_clk_ctrl_agent:rf_sink_data
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready; // acl_kernel_clk_ctrl_agent:rf_sink_ready -> acl_kernel_clk_ctrl_agent_rsp_fifo:out_ready
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_startofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_startofpacket
wire acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket; // acl_kernel_clk_ctrl_agent_rsp_fifo:out_endofpacket -> acl_kernel_clk_ctrl_agent:rf_sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_valid -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_src_data; // acl_kernel_clk_ctrl_agent:rdata_fifo_src_data -> acl_kernel_clk_ctrl_agent_rdata_fifo:in_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready; // acl_kernel_clk_ctrl_agent_rdata_fifo:in_ready -> acl_kernel_clk_ctrl_agent:rdata_fifo_src_ready
wire hps_h2f_lw_axi_master_agent_write_cp_valid; // hps_h2f_lw_axi_master_agent:write_cp_valid -> router:sink_valid
wire [113:0] hps_h2f_lw_axi_master_agent_write_cp_data; // hps_h2f_lw_axi_master_agent:write_cp_data -> router:sink_data
wire hps_h2f_lw_axi_master_agent_write_cp_ready; // router:sink_ready -> hps_h2f_lw_axi_master_agent:write_cp_ready
wire hps_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_h2f_lw_axi_master_agent:write_cp_startofpacket -> router:sink_startofpacket
wire hps_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_h2f_lw_axi_master_agent:write_cp_endofpacket -> router:sink_endofpacket
wire hps_h2f_lw_axi_master_agent_read_cp_valid; // hps_h2f_lw_axi_master_agent:read_cp_valid -> router_001:sink_valid
wire [113:0] hps_h2f_lw_axi_master_agent_read_cp_data; // hps_h2f_lw_axi_master_agent:read_cp_data -> router_001:sink_data
wire hps_h2f_lw_axi_master_agent_read_cp_ready; // router_001:sink_ready -> hps_h2f_lw_axi_master_agent:read_cp_ready
wire hps_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_h2f_lw_axi_master_agent:read_cp_startofpacket -> router_001:sink_startofpacket
wire hps_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_h2f_lw_axi_master_agent:read_cp_endofpacket -> router_001:sink_endofpacket
wire version_id_s_agent_rp_valid; // version_id_s_agent:rp_valid -> router_002:sink_valid
wire [113:0] version_id_s_agent_rp_data; // version_id_s_agent:rp_data -> router_002:sink_data
wire version_id_s_agent_rp_ready; // router_002:sink_ready -> version_id_s_agent:rp_ready
wire version_id_s_agent_rp_startofpacket; // version_id_s_agent:rp_startofpacket -> router_002:sink_startofpacket
wire version_id_s_agent_rp_endofpacket; // version_id_s_agent:rp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire [113:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire [2:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rp_valid; // acl_kernel_interface_kernel_cntrl_agent:rp_valid -> router_003:sink_valid
wire [113:0] acl_kernel_interface_kernel_cntrl_agent_rp_data; // acl_kernel_interface_kernel_cntrl_agent:rp_data -> router_003:sink_data
wire acl_kernel_interface_kernel_cntrl_agent_rp_ready; // router_003:sink_ready -> acl_kernel_interface_kernel_cntrl_agent:rp_ready
wire acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_startofpacket -> router_003:sink_startofpacket
wire acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket; // acl_kernel_interface_kernel_cntrl_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [113:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [2:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire acl_kernel_clk_ctrl_agent_rp_valid; // acl_kernel_clk_ctrl_agent:rp_valid -> router_004:sink_valid
wire [113:0] acl_kernel_clk_ctrl_agent_rp_data; // acl_kernel_clk_ctrl_agent:rp_data -> router_004:sink_data
wire acl_kernel_clk_ctrl_agent_rp_ready; // router_004:sink_ready -> acl_kernel_clk_ctrl_agent:rp_ready
wire acl_kernel_clk_ctrl_agent_rp_startofpacket; // acl_kernel_clk_ctrl_agent:rp_startofpacket -> router_004:sink_startofpacket
wire acl_kernel_clk_ctrl_agent_rp_endofpacket; // acl_kernel_clk_ctrl_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire [113:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire [2:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_src_valid; // router:src_valid -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_valid
wire [113:0] router_src_data; // router:src_data -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_data
wire router_src_ready; // hps_h2f_lw_axi_master_wr_limiter:cmd_sink_ready -> router:src_ready
wire [2:0] router_src_channel; // router:src_channel -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:cmd_sink_endofpacket
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_data -> cmd_demux:sink_data
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready; // cmd_demux:sink_ready -> hps_h2f_lw_axi_master_wr_limiter:cmd_src_ready
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_valid
wire [113:0] rsp_mux_src_data; // rsp_mux:src_data -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_data
wire rsp_mux_src_ready; // hps_h2f_lw_axi_master_wr_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [2:0] rsp_mux_src_channel; // rsp_mux:src_channel -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> hps_h2f_lw_axi_master_wr_limiter:rsp_sink_endofpacket
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:write_rp_valid
wire [113:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_data; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:write_rp_data
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:write_rp_ready -> hps_h2f_lw_axi_master_wr_limiter:rsp_src_ready
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:write_rp_channel
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:write_rp_startofpacket
wire hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_wr_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:write_rp_endofpacket
wire router_001_src_valid; // router_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_valid
wire [113:0] router_001_src_data; // router_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_data
wire router_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:cmd_sink_ready -> router_001:src_ready
wire [2:0] router_001_src_channel; // router_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:cmd_sink_endofpacket
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_data -> cmd_demux_001:sink_data
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready; // cmd_demux_001:sink_ready -> hps_h2f_lw_axi_master_rd_limiter:cmd_src_ready
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_channel -> cmd_demux_001:sink_channel
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_startofpacket -> cmd_demux_001:sink_startofpacket
wire hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_endofpacket -> cmd_demux_001:sink_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_valid
wire [113:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_data
wire rsp_mux_001_src_ready; // hps_h2f_lw_axi_master_rd_limiter:rsp_sink_ready -> rsp_mux_001:src_ready
wire [2:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> hps_h2f_lw_axi_master_rd_limiter:rsp_sink_endofpacket
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_valid -> hps_h2f_lw_axi_master_agent:read_rp_valid
wire [113:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_data; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_data -> hps_h2f_lw_axi_master_agent:read_rp_data
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready; // hps_h2f_lw_axi_master_agent:read_rp_ready -> hps_h2f_lw_axi_master_rd_limiter:rsp_src_ready
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_channel -> hps_h2f_lw_axi_master_agent:read_rp_channel
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_startofpacket -> hps_h2f_lw_axi_master_agent:read_rp_startofpacket
wire hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket; // hps_h2f_lw_axi_master_rd_limiter:rsp_src_endofpacket -> hps_h2f_lw_axi_master_agent:read_rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> version_id_s_burst_adapter:sink0_valid
wire [113:0] cmd_mux_src_data; // cmd_mux:src_data -> version_id_s_burst_adapter:sink0_data
wire cmd_mux_src_ready; // version_id_s_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [2:0] cmd_mux_src_channel; // cmd_mux:src_channel -> version_id_s_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> version_id_s_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> version_id_s_burst_adapter:sink0_endofpacket
wire version_id_s_burst_adapter_source0_valid; // version_id_s_burst_adapter:source0_valid -> version_id_s_agent:cp_valid
wire [113:0] version_id_s_burst_adapter_source0_data; // version_id_s_burst_adapter:source0_data -> version_id_s_agent:cp_data
wire version_id_s_burst_adapter_source0_ready; // version_id_s_agent:cp_ready -> version_id_s_burst_adapter:source0_ready
wire [2:0] version_id_s_burst_adapter_source0_channel; // version_id_s_burst_adapter:source0_channel -> version_id_s_agent:cp_channel
wire version_id_s_burst_adapter_source0_startofpacket; // version_id_s_burst_adapter:source0_startofpacket -> version_id_s_agent:cp_startofpacket
wire version_id_s_burst_adapter_source0_endofpacket; // version_id_s_burst_adapter:source0_endofpacket -> version_id_s_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_valid
wire [113:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_data
wire cmd_mux_001_src_ready; // acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_ready -> cmd_mux_001:src_ready
wire [2:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> acl_kernel_interface_kernel_cntrl_burst_adapter:sink0_endofpacket
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_valid -> acl_kernel_interface_kernel_cntrl_agent:cp_valid
wire [113:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_data -> acl_kernel_interface_kernel_cntrl_agent:cp_data
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready; // acl_kernel_interface_kernel_cntrl_agent:cp_ready -> acl_kernel_interface_kernel_cntrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_channel -> acl_kernel_interface_kernel_cntrl_agent:cp_channel
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_startofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_startofpacket
wire acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket; // acl_kernel_interface_kernel_cntrl_burst_adapter:source0_endofpacket -> acl_kernel_interface_kernel_cntrl_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> acl_kernel_clk_ctrl_burst_adapter:sink0_valid
wire [113:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> acl_kernel_clk_ctrl_burst_adapter:sink0_data
wire cmd_mux_002_src_ready; // acl_kernel_clk_ctrl_burst_adapter:sink0_ready -> cmd_mux_002:src_ready
wire [2:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> acl_kernel_clk_ctrl_burst_adapter:sink0_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> acl_kernel_clk_ctrl_burst_adapter:sink0_endofpacket
wire acl_kernel_clk_ctrl_burst_adapter_source0_valid; // acl_kernel_clk_ctrl_burst_adapter:source0_valid -> acl_kernel_clk_ctrl_agent:cp_valid
wire [113:0] acl_kernel_clk_ctrl_burst_adapter_source0_data; // acl_kernel_clk_ctrl_burst_adapter:source0_data -> acl_kernel_clk_ctrl_agent:cp_data
wire acl_kernel_clk_ctrl_burst_adapter_source0_ready; // acl_kernel_clk_ctrl_agent:cp_ready -> acl_kernel_clk_ctrl_burst_adapter:source0_ready
wire [2:0] acl_kernel_clk_ctrl_burst_adapter_source0_channel; // acl_kernel_clk_ctrl_burst_adapter:source0_channel -> acl_kernel_clk_ctrl_agent:cp_channel
wire acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_startofpacket -> acl_kernel_clk_ctrl_agent:cp_startofpacket
wire acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket; // acl_kernel_clk_ctrl_burst_adapter:source0_endofpacket -> acl_kernel_clk_ctrl_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [113:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [2:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [113:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [2:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [113:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [2:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire [113:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire [2:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire [113:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire [2:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire [113:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire [2:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [113:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [2:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire [113:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire [2:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [113:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [2:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire [113:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire [2:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [113:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [2:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire [113:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire [2:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire [2:0] hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_wr_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire [2:0] hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data; // hps_h2f_lw_axi_master_rd_limiter:cmd_src_valid -> cmd_demux_001:sink_valid
wire version_id_s_agent_rdata_fifo_out_valid; // version_id_s_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [33:0] version_id_s_agent_rdata_fifo_out_data; // version_id_s_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire version_id_s_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> version_id_s_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> version_id_s_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> version_id_s_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // version_id_s_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> version_id_s_agent:rdata_fifo_sink_error
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data; // acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_data -> avalon_st_adapter_001:in_0_data
wire acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready; // avalon_st_adapter_001:in_0_ready -> acl_kernel_interface_kernel_cntrl_agent_rdata_fifo:out_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> acl_kernel_interface_kernel_cntrl_agent:rdata_fifo_sink_error
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] acl_kernel_clk_ctrl_agent_rdata_fifo_out_data; // acl_kernel_clk_ctrl_agent_rdata_fifo:out_data -> avalon_st_adapter_002:in_0_data
wire acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready; // avalon_st_adapter_002:in_0_ready -> acl_kernel_clk_ctrl_agent_rdata_fifo:out_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // acl_kernel_clk_ctrl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> acl_kernel_clk_ctrl_agent:rdata_fifo_sink_error
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_s_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_s_agent_m0_read), // .read
.uav_write (version_id_s_agent_m0_write), // .write
.uav_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_interface_kernel_cntrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.uav_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_interface_kernel_cntrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_interface_kernel_cntrl_write), // .write
.av_read (acl_kernel_interface_kernel_cntrl_read), // .read
.av_readdata (acl_kernel_interface_kernel_cntrl_readdata), // .readdata
.av_writedata (acl_kernel_interface_kernel_cntrl_writedata), // .writedata
.av_burstcount (acl_kernel_interface_kernel_cntrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_interface_kernel_cntrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_interface_kernel_cntrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_interface_kernel_cntrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_interface_kernel_cntrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (11),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) acl_kernel_clk_ctrl_translator (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (acl_kernel_clk_ctrl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.uav_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.uav_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.uav_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.uav_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.uav_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.uav_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.uav_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.av_address (acl_kernel_clk_ctrl_address), // avalon_anti_slave_0.address
.av_write (acl_kernel_clk_ctrl_write), // .write
.av_read (acl_kernel_clk_ctrl_read), // .read
.av_readdata (acl_kernel_clk_ctrl_readdata), // .readdata
.av_writedata (acl_kernel_clk_ctrl_writedata), // .writedata
.av_burstcount (acl_kernel_clk_ctrl_burstcount), // .burstcount
.av_byteenable (acl_kernel_clk_ctrl_byteenable), // .byteenable
.av_readdatavalid (acl_kernel_clk_ctrl_readdatavalid), // .readdatavalid
.av_waitrequest (acl_kernel_clk_ctrl_waitrequest), // .waitrequest
.av_debugaccess (acl_kernel_clk_ctrl_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (108),
.PKT_CACHE_L (105),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (109),
.PKT_RESPONSE_STATUS_H (110),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_THREAD_ID_H (101),
.PKT_THREAD_ID_L (90),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_ORI_BURST_SIZE_H (113),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.ID (0)
) hps_h2f_lw_axi_master_agent (
.aclk (config_clk_out_clk_clk), // clk.clk
.aresetn (~hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.write_rp_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // read_rp.valid
.read_rp_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.read_rp_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.read_rp_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // .ready
.awid (hps_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_h2f_lw_axi_master_awready), // .awready
.wid (hps_h2f_lw_axi_master_wid), // .wid
.wdata (hps_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_h2f_lw_axi_master_wready), // .wready
.bid (hps_h2f_lw_axi_master_bid), // .bid
.bresp (hps_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_h2f_lw_axi_master_bready), // .bready
.arid (hps_h2f_lw_axi_master_arid), // .arid
.araddr (hps_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_h2f_lw_axi_master_arready), // .arready
.rid (hps_h2f_lw_axi_master_rid), // .rid
.rdata (hps_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (1'b0), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (61),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) version_id_s_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_s_agent_m0_lock), // .lock
.m0_readdata (version_id_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_s_agent_m0_read), // .read
.m0_waitrequest (version_id_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_s_agent_m0_writedata), // .writedata
.m0_write (version_id_s_agent_m0_write), // .write
.rp_endofpacket (version_id_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_s_agent_rp_ready), // .ready
.rp_valid (version_id_s_agent_rp_valid), // .valid
.rp_data (version_id_s_agent_rp_data), // .data
.rp_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (version_id_s_burst_adapter_source0_ready), // cp.ready
.cp_valid (version_id_s_burst_adapter_source0_valid), // .valid
.cp_data (version_id_s_burst_adapter_source0_data), // .data
.cp_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (version_id_s_burst_adapter_source0_channel), // .channel
.rf_sink_ready (version_id_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (version_id_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rf_source_data), // in.data
.in_valid (version_id_s_agent_rf_source_valid), // .valid
.in_ready (version_id_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_s_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_s_agent_rdata_fifo_src_data), // in.data
.in_valid (version_id_s_agent_rdata_fifo_src_valid), // .valid
.in_ready (version_id_s_agent_rdata_fifo_src_ready), // .ready
.out_data (version_id_s_agent_rdata_fifo_out_data), // out.data
.out_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.out_ready (version_id_s_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (61),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) acl_kernel_interface_kernel_cntrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_interface_kernel_cntrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_interface_kernel_cntrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_interface_kernel_cntrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_interface_kernel_cntrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_interface_kernel_cntrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_interface_kernel_cntrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_interface_kernel_cntrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_interface_kernel_cntrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_interface_kernel_cntrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_interface_kernel_cntrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_interface_kernel_cntrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_interface_kernel_cntrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (113),
.PKT_ORI_BURST_SIZE_L (111),
.PKT_RESPONSE_STATUS_H (110),
.PKT_RESPONSE_STATUS_L (109),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_TRANS_LOCK (61),
.PKT_BEGIN_BURST (84),
.PKT_PROTECTION_H (104),
.PKT_PROTECTION_L (102),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (3),
.ST_DATA_W (114),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) acl_kernel_clk_ctrl_agent (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (acl_kernel_clk_ctrl_agent_m0_address), // m0.address
.m0_burstcount (acl_kernel_clk_ctrl_agent_m0_burstcount), // .burstcount
.m0_byteenable (acl_kernel_clk_ctrl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (acl_kernel_clk_ctrl_agent_m0_debugaccess), // .debugaccess
.m0_lock (acl_kernel_clk_ctrl_agent_m0_lock), // .lock
.m0_readdata (acl_kernel_clk_ctrl_agent_m0_readdata), // .readdata
.m0_readdatavalid (acl_kernel_clk_ctrl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (acl_kernel_clk_ctrl_agent_m0_read), // .read
.m0_waitrequest (acl_kernel_clk_ctrl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (acl_kernel_clk_ctrl_agent_m0_writedata), // .writedata
.m0_write (acl_kernel_clk_ctrl_agent_m0_write), // .write
.rp_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (acl_kernel_clk_ctrl_agent_rp_ready), // .ready
.rp_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.rp_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.rp_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.cp_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready), // cp.ready
.cp_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // .valid
.cp_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.cp_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.rf_sink_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (acl_kernel_clk_ctrl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (115),
.FIFO_DEPTH (5),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rsp_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rf_source_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rf_source_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rf_source_ready), // .ready
.in_startofpacket (acl_kernel_clk_ctrl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (acl_kernel_clk_ctrl_agent_rf_source_endofpacket), // .endofpacket
.out_data (acl_kernel_clk_ctrl_agent_rsp_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rsp_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (acl_kernel_clk_ctrl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) acl_kernel_clk_ctrl_agent_rdata_fifo (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (acl_kernel_clk_ctrl_agent_rdata_fifo_src_data), // in.data
.in_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_src_valid), // .valid
.in_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_src_ready), // .ready
.out_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // out.data
.out_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.out_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_mm_interconnect_0_router router (
.sink_ready (hps_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router router_001 (
.sink_ready (hps_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_002 (
.sink_ready (version_id_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_s_agent_rp_valid), // .valid
.sink_data (version_id_s_agent_rp_data), // .data
.sink_startofpacket (version_id_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_s_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_003 (
.sink_ready (acl_kernel_interface_kernel_cntrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_interface_kernel_cntrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_interface_kernel_cntrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_interface_kernel_cntrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_router_002 router_004 (
.sink_ready (acl_kernel_clk_ctrl_agent_rp_ready), // sink.ready
.sink_valid (acl_kernel_clk_ctrl_agent_rp_valid), // .valid
.sink_data (acl_kernel_clk_ctrl_agent_rp_data), // .data
.sink_startofpacket (acl_kernel_clk_ctrl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (acl_kernel_clk_ctrl_agent_rp_endofpacket), // .endofpacket
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) hps_h2f_lw_axi_master_wr_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_wr_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_wr_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_wr_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_wr_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_wr_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (88),
.PKT_SRC_ID_H (87),
.PKT_SRC_ID_L (86),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (6),
.PIPELINED (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.VALID_WIDTH (3),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) hps_h2f_lw_axi_master_rd_limiter (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_001_src_valid), // .valid
.cmd_sink_data (router_001_src_data), // .data
.cmd_sink_channel (router_001_src_channel), // .channel
.cmd_sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.cmd_src_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (hps_h2f_lw_axi_master_rd_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (hps_h2f_lw_axi_master_rd_limiter_rsp_src_valid), // .valid
.rsp_src_data (hps_h2f_lw_axi_master_rd_limiter_rsp_src_data), // .data
.rsp_src_channel (hps_h2f_lw_axi_master_rd_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (hps_h2f_lw_axi_master_rd_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) version_id_s_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (version_id_s_burst_adapter_source0_valid), // source0.valid
.source0_data (version_id_s_burst_adapter_source0_data), // .data
.source0_channel (version_id_s_burst_adapter_source0_channel), // .channel
.source0_startofpacket (version_id_s_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (version_id_s_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (version_id_s_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_interface_kernel_cntrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_mux_001_src_data), // .data
.sink0_channel (cmd_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_001_src_ready), // .ready
.source0_valid (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_interface_kernel_cntrl_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (114),
.ST_CHANNEL_W (3),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0),
.ADAPTER_VERSION ("13.1")
) acl_kernel_clk_ctrl_burst_adapter (
.clk (config_clk_out_clk_clk), // cr0.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_002_src_valid), // sink0.valid
.sink0_data (cmd_mux_002_src_data), // .data
.sink0_channel (cmd_mux_002_src_channel), // .channel
.sink0_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_002_src_ready), // .ready
.source0_valid (acl_kernel_clk_ctrl_burst_adapter_source0_valid), // source0.valid
.source0_data (acl_kernel_clk_ctrl_burst_adapter_source0_data), // .data
.source0_channel (acl_kernel_clk_ctrl_burst_adapter_source0_channel), // .channel
.source0_startofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (acl_kernel_clk_ctrl_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (acl_kernel_clk_ctrl_burst_adapter_source0_ready) // .ready
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_wr_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_wr_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_wr_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_wr_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_wr_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_demux cmd_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (hps_h2f_lw_axi_master_rd_limiter_cmd_src_ready), // sink.ready
.sink_channel (hps_h2f_lw_axi_master_rd_limiter_cmd_src_channel), // .channel
.sink_data (hps_h2f_lw_axi_master_rd_limiter_cmd_src_data), // .data
.sink_startofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (hps_h2f_lw_axi_master_rd_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (hps_h2f_lw_axi_master_rd_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (version_id_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_rsp_mux rsp_mux_001 (
.clk (config_clk_out_clk_clk), // clk.clk
.reset (hps_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (config_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (version_id_clk_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (version_id_s_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (version_id_s_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (version_id_s_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (config_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (version_id_clk_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (acl_kernel_interface_kernel_cntrl_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
system_acl_iface_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (config_clk_out_clk_clk), // in_clk_0.clk
.in_rst_0_reset (version_id_clk_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (acl_kernel_clk_ctrl_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (acl_kernel_clk_ctrl_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (acl_kernel_clk_ctrl_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O221A_SYMBOL_V
`define SKY130_FD_SC_HS__O221A_SYMBOL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o221a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O221A_SYMBOL_V
|
//
// my_fpga_test_count_up_1k.v
//
`timescale 1ns/1ps
`define ms(t) (t * 1e6)
`define ns(t) (t)
module my_fpga_test_count_up_1k;
reg clk = 0, n_rst = 0;
reg up = 0, dn = 0;
wire [31:0] cnt;
wire [3:0] cnt_1k;
reg in1 = 0, in2 = 0;
wire out1, out2;
time t, u;
my_fpga uut(clk, n_rst, up, dn, cnt, cnt_1k, in1, in2, out1, out2);
tbmsgs msgs();
always
#5 clk = ~clk;
initial
begin
msgs.testcase("my_fpga count up 1k", 1);
#1000
n_rst = 1;
#1000
@(negedge clk);
up <= 1;
// wait until cnt_1k output is 0x1
begin : break1
while (1) begin
@(negedge clk);
if (cnt_1k == 4'h1) begin
t = $time;
disable break1;
end
end
end
// wait until cnt_1k output is 0xb
begin : break2
while (1) begin
@(negedge clk);
if (cnt_1k == 4'hb) begin
t = $time - t;
disable break2;
end
end
end
msgs.check(t > `ms(10) - `ns(100) && t < `ms(10) + `ns(100),
"cnt_1k output should count at 1KHz");
msgs.tested("count 1k output");
msgs.testcase_complete();
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DIODE_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DIODE_PP_BLACKBOX_V
/**
* diode: Antenna tie-down diode.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__diode (
DIODE,
VPWR ,
VGND ,
VPB ,
VNB
);
input DIODE;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DIODE_PP_BLACKBOX_V
|
/*
* Copyright (C) 2011 Kiel Friedt
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
//authors Kiel Friedt, Kevin McIntosh,Cody DeHaan
module add4_LA(a, b, c_in, sum, c_out, P, G);
input [3:0] a, b;
input c_in;
output [3:0] sum;
output c_out;
output P, G;
wire [2:0] c;
wire [3:0] p, g;
fulladder_LA f0(a[0], b[0], c_in, sum[0], p[0], g[0]);
fulladder_LA f1(a[1], b[1], c[0], sum[1], p[1], g[1]);
fulladder_LA f2(a[2], b[2], c[1], sum[2], p[2], g[2]);
fulladder_LA f3(a[3], b[3], c[2], sum[3], p[3], g[3]);
lookahead l1(c_in, c_out, c, p, g, P, G);
endmodule
|
module serial (rxd, txd, clk);
input rxd;
input clk;
output txd;
parameter [3:0] send1 = 3'b001, send2 = 3'b011, send3 = 3'b101, send4 = 3'b111,
s1 = 3'b000, s2 = 3'b010, s3 = 3'b100, s4 = 3'b110;
reg [3:0] present_state = s1;
reg [3:0] next_state = s1;
/* sender ports */
reg [7:0] snd_data;
reg snd_start;
wire snd_busy;
/* set senders port */
async_transmitter snd(clk, snd_start, snd_data, txd, snd_busy);
always @(posedge clk) begin
present_state = next_state;
end
always @(present_state, snd_busy) begin
case (present_state)
0: begin
/* start send @ */
snd_data = 8'b0100_0000;
snd_start = 1'b1;
next_state = send1;
end
1: begin
snd_start <= 1'b0;
if (snd_busy == 1'b0)
next_state = s2;
end
2: begin
/* start send 0 */
snd_data = 8'b0011_0000;
snd_start = 1'b1;
next_state = send2;
end
3: begin
snd_start <= 1'b0;
if (snd_busy == 1'b0)
next_state = s3;
end
4: begin
/* start send / */
snd_data = 8'b0010_1111;
snd_start = 1'b1;
next_state = send3;
end
5: begin
snd_start <= 1'b0;
if (snd_busy == 1'b0)
next_state = s4;
end
6: begin
/* start send \n */
snd_data = 8'b0000_1010;
snd_start = 1'b1;
next_state = send4;
end
7: begin
snd_start <= 1'b0;
if (snd_busy == 1'b0)
next_state = s1;
end
endcase
end
endmodule
|
`include "enc_defines.v"
module q_iq(
clk,
rst,
type_i,
qp_i,
tq_en_i,
inverse,
i_valid,
tq_size_i,
i_0 ,
i_1 ,
i_2 ,
i_3 ,
i_4 ,
i_5 ,
i_6 ,
i_7 ,
i_8 ,
i_9 ,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
cef_data_i,
cef_wen_o,
cef_widx_o,
cef_data_o,
cef_ren_o,
cef_ridx_o,
o_valid,
o_0 ,
o_1 ,
o_2 ,
o_3 ,
o_4 ,
o_5 ,
o_6 ,
o_7 ,
o_8 ,
o_9 ,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input type_i;
input tq_en_i;
input inverse;
input i_valid;
input [5:0] qp_i;
input [1:0] tq_size_i;
input signed [15:0] i_0 ;
input signed [15:0] i_1 ;
input signed [15:0] i_2 ;
input signed [15:0] i_3 ;
input signed [15:0] i_4 ;
input signed [15:0] i_5 ;
input signed [15:0] i_6 ;
input signed [15:0] i_7 ;
input signed [15:0] i_8 ;
input signed [15:0] i_9 ;
input signed [15:0] i_10;
input signed [15:0] i_11;
input signed [15:0] i_12;
input signed [15:0] i_13;
input signed [15:0] i_14;
input signed [15:0] i_15;
input signed [15:0] i_16;
input signed [15:0] i_17;
input signed [15:0] i_18;
input signed [15:0] i_19;
input signed [15:0] i_20;
input signed [15:0] i_21;
input signed [15:0] i_22;
input signed [15:0] i_23;
input signed [15:0] i_24;
input signed [15:0] i_25;
input signed [15:0] i_26;
input signed [15:0] i_27;
input signed [15:0] i_28;
input signed [15:0] i_29;
input signed [15:0] i_30;
input signed [15:0] i_31;
input [511:0] cef_data_i;
output cef_wen_o;
output [4:0] cef_widx_o;
output [511:0] cef_data_o;
output cef_ren_o;
output [4:0] cef_ridx_o;
output o_valid;
output signed [15:0] o_0 ;
output signed [15:0] o_1 ;
output signed [15:0] o_2 ;
output signed [15:0] o_3 ;
output signed [15:0] o_4 ;
output signed [15:0] o_5 ;
output signed [15:0] o_6 ;
output signed [15:0] o_7 ;
output signed [15:0] o_8 ;
output signed [15:0] o_9 ;
output signed [15:0] o_10;
output signed [15:0] o_11;
output signed [15:0] o_12;
output signed [15:0] o_13;
output signed [15:0] o_14;
output signed [15:0] o_15;
output signed [15:0] o_16;
output signed [15:0] o_17;
output signed [15:0] o_18;
output signed [15:0] o_19;
output signed [15:0] o_20;
output signed [15:0] o_21;
output signed [15:0] o_22;
output signed [15:0] o_23;
output signed [15:0] o_24;
output signed [15:0] o_25;
output signed [15:0] o_26;
output signed [15:0] o_27;
output signed [15:0] o_28;
output signed [15:0] o_29;
output signed [15:0] o_30;
output signed [15:0] o_31;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire i_q_valid;
wire i_q_valid_0;
wire i_q_valid_4;
wire signed [15:0] i_q_0 ;
wire signed [15:0] i_q_1 ;
wire signed [15:0] i_q_2 ;
wire signed [15:0] i_q_3 ;
wire signed [15:0] i_q_4 ;
wire signed [15:0] i_q_5 ;
wire signed [15:0] i_q_6 ;
wire signed [15:0] i_q_7 ;
wire signed [15:0] i_q_8 ;
wire signed [15:0] i_q_9 ;
wire signed [15:0] i_q_10;
wire signed [15:0] i_q_11;
wire signed [15:0] i_q_12;
wire signed [15:0] i_q_13;
wire signed [15:0] i_q_14;
wire signed [15:0] i_q_15;
wire signed [15:0] i_q_16;
wire signed [15:0] i_q_17;
wire signed [15:0] i_q_18;
wire signed [15:0] i_q_19;
wire signed [15:0] i_q_20;
wire signed [15:0] i_q_21;
wire signed [15:0] i_q_22;
wire signed [15:0] i_q_23;
wire signed [15:0] i_q_24;
wire signed [15:0] i_q_25;
wire signed [15:0] i_q_26;
wire signed [15:0] i_q_27;
wire signed [15:0] i_q_28;
wire signed [15:0] i_q_29;
wire signed [15:0] i_q_30;
wire signed [15:0] i_q_31;
wire signed [15:0] i4_0 ;
wire signed [15:0] i4_1 ;
wire signed [15:0] i4_2 ;
wire signed [15:0] i4_3 ;
wire signed [15:0] i4_4 ;
wire signed [15:0] i4_5 ;
wire signed [15:0] i4_6 ;
wire signed [15:0] i4_7 ;
wire signed [15:0] i4_8 ;
wire signed [15:0] i4_9 ;
wire signed [15:0] i4_10;
wire signed [15:0] i4_11;
wire signed [15:0] i4_12;
wire signed [15:0] i4_13;
wire signed [15:0] i4_14;
wire signed [15:0] i4_15;
wire signed [15:0] i4_16;
wire signed [15:0] i4_17;
wire signed [15:0] i4_18;
wire signed [15:0] i4_19;
wire signed [15:0] i4_20;
wire signed [15:0] i4_21;
wire signed [15:0] i4_22;
wire signed [15:0] i4_23;
wire signed [15:0] i4_24;
wire signed [15:0] i4_25;
wire signed [15:0] i4_26;
wire signed [15:0] i4_27;
wire signed [15:0] i4_28;
wire signed [15:0] i4_29;
wire signed [15:0] i4_30;
wire signed [15:0] i4_31;
wire signed [15:0] in_0 ;
wire signed [15:0] in_1 ;
wire signed [15:0] in_2 ;
wire signed [15:0] in_3 ;
wire signed [15:0] in_4 ;
wire signed [15:0] in_5 ;
wire signed [15:0] in_6 ;
wire signed [15:0] in_7 ;
wire signed [15:0] in_8 ;
wire signed [15:0] in_9 ;
wire signed [15:0] in_10;
wire signed [15:0] in_11;
wire signed [15:0] in_12;
wire signed [15:0] in_13;
wire signed [15:0] in_14;
wire signed [15:0] in_15;
wire signed [15:0] in_16;
wire signed [15:0] in_17;
wire signed [15:0] in_18;
wire signed [15:0] in_19;
wire signed [15:0] in_20;
wire signed [15:0] in_21;
wire signed [15:0] in_22;
wire signed [15:0] in_23;
wire signed [15:0] in_24;
wire signed [15:0] in_25;
wire signed [15:0] in_26;
wire signed [15:0] in_27;
wire signed [15:0] in_28;
wire signed [15:0] in_29;
wire signed [15:0] in_30;
wire signed [15:0] in_31;
wire o_q_valid;
wire signed [15:0] o_q_0 ;
wire signed [15:0] o_q_1 ;
wire signed [15:0] o_q_2 ;
wire signed [15:0] o_q_3 ;
wire signed [15:0] o_q_4 ;
wire signed [15:0] o_q_5 ;
wire signed [15:0] o_q_6 ;
wire signed [15:0] o_q_7 ;
wire signed [15:0] o_q_8 ;
wire signed [15:0] o_q_9 ;
wire signed [15:0] o_q_10;
wire signed [15:0] o_q_11;
wire signed [15:0] o_q_12;
wire signed [15:0] o_q_13;
wire signed [15:0] o_q_14;
wire signed [15:0] o_q_15;
wire signed [15:0] o_q_16;
wire signed [15:0] o_q_17;
wire signed [15:0] o_q_18;
wire signed [15:0] o_q_19;
wire signed [15:0] o_q_20;
wire signed [15:0] o_q_21;
wire signed [15:0] o_q_22;
wire signed [15:0] o_q_23;
wire signed [15:0] o_q_24;
wire signed [15:0] o_q_25;
wire signed [15:0] o_q_26;
wire signed [15:0] o_q_27;
wire signed [15:0] o_q_28;
wire signed [15:0] o_q_29;
wire signed [15:0] o_q_30;
wire signed [15:0] o_q_31;
wire signed [15:0] i_coeff_0 ;
wire signed [15:0] i_coeff_1 ;
wire signed [15:0] i_coeff_2 ;
wire signed [15:0] i_coeff_3 ;
wire signed [15:0] i_coeff_4 ;
wire signed [15:0] i_coeff_5 ;
wire signed [15:0] i_coeff_6 ;
wire signed [15:0] i_coeff_7 ;
wire signed [15:0] i_coeff_8 ;
wire signed [15:0] i_coeff_9 ;
wire signed [15:0] i_coeff_10;
wire signed [15:0] i_coeff_11;
wire signed [15:0] i_coeff_12;
wire signed [15:0] i_coeff_13;
wire signed [15:0] i_coeff_14;
wire signed [15:0] i_coeff_15;
wire signed [15:0] i_coeff_16;
wire signed [15:0] i_coeff_17;
wire signed [15:0] i_coeff_18;
wire signed [15:0] i_coeff_19;
wire signed [15:0] i_coeff_20;
wire signed [15:0] i_coeff_21;
wire signed [15:0] i_coeff_22;
wire signed [15:0] i_coeff_23;
wire signed [15:0] i_coeff_24;
wire signed [15:0] i_coeff_25;
wire signed [15:0] i_coeff_26;
wire signed [15:0] i_coeff_27;
wire signed [15:0] i_coeff_28;
wire signed [15:0] i_coeff_29;
wire signed [15:0] i_coeff_30;
wire signed [15:0] i_coeff_31;
wire signed [15:0] o_coeff_0 ;
wire signed [15:0] o_coeff_1 ;
wire signed [15:0] o_coeff_2 ;
wire signed [15:0] o_coeff_3 ;
wire signed [15:0] o_coeff_4 ;
wire signed [15:0] o_coeff_5 ;
wire signed [15:0] o_coeff_6 ;
wire signed [15:0] o_coeff_7 ;
wire signed [15:0] o_coeff_8 ;
wire signed [15:0] o_coeff_9 ;
wire signed [15:0] o_coeff_10;
wire signed [15:0] o_coeff_11;
wire signed [15:0] o_coeff_12;
wire signed [15:0] o_coeff_13;
wire signed [15:0] o_coeff_14;
wire signed [15:0] o_coeff_15;
wire signed [15:0] o_coeff_16;
wire signed [15:0] o_coeff_17;
wire signed [15:0] o_coeff_18;
wire signed [15:0] o_coeff_19;
wire signed [15:0] o_coeff_20;
wire signed [15:0] o_coeff_21;
wire signed [15:0] o_coeff_22;
wire signed [15:0] o_coeff_23;
wire signed [15:0] o_coeff_24;
wire signed [15:0] o_coeff_25;
wire signed [15:0] o_coeff_26;
wire signed [15:0] o_coeff_27;
wire signed [15:0] o_coeff_28;
wire signed [15:0] o_coeff_29;
wire signed [15:0] o_coeff_30;
wire signed [15:0] o_coeff_31;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
reg cef_val_i;
reg cef_ren_o;
reg [4:0] cef_ridx_o;
reg [4:0] cef_widx_o;
reg [4:0] counter_1;
reg [4:0] counter_2;
// **********************************************
//
// Combinational Logic
//
// **********************************************
assign i_q_valid_0=inverse?cef_val_i:i_valid;
assign i_q_valid_4=inverse?1'b0:(i_valid||o_q_valid);
assign i_q_valid=(tq_size_i==2'b00)?i_q_valid_4:i_q_valid_0;
assign i_q_0 =inverse?o_coeff_0 :in_0 ;
assign i_q_1 =inverse?o_coeff_1 :in_1 ;
assign i_q_2 =inverse?o_coeff_2 :in_2 ;
assign i_q_3 =inverse?o_coeff_3 :in_3 ;
assign i_q_4 =inverse?o_coeff_4 :in_4 ;
assign i_q_5 =inverse?o_coeff_5 :in_5 ;
assign i_q_6 =inverse?o_coeff_6 :in_6 ;
assign i_q_7 =inverse?o_coeff_7 :in_7 ;
assign i_q_8 =inverse?o_coeff_8 :in_8 ;
assign i_q_9 =inverse?o_coeff_9 :in_9 ;
assign i_q_10=inverse?o_coeff_10:in_10;
assign i_q_11=inverse?o_coeff_11:in_11;
assign i_q_12=inverse?o_coeff_12:in_12;
assign i_q_13=inverse?o_coeff_13:in_13;
assign i_q_14=inverse?o_coeff_14:in_14;
assign i_q_15=inverse?o_coeff_15:in_15;
assign i_q_16=inverse?o_coeff_16:in_16;
assign i_q_17=inverse?o_coeff_17:in_17;
assign i_q_18=inverse?o_coeff_18:in_18;
assign i_q_19=inverse?o_coeff_19:in_19;
assign i_q_20=inverse?o_coeff_20:in_20;
assign i_q_21=inverse?o_coeff_21:in_21;
assign i_q_22=inverse?o_coeff_22:in_22;
assign i_q_23=inverse?o_coeff_23:in_23;
assign i_q_24=inverse?o_coeff_24:in_24;
assign i_q_25=inverse?o_coeff_25:in_25;
assign i_q_26=inverse?o_coeff_26:in_26;
assign i_q_27=inverse?o_coeff_27:in_27;
assign i_q_28=inverse?o_coeff_28:in_28;
assign i_q_29=inverse?o_coeff_29:in_29;
assign i_q_30=inverse?o_coeff_30:in_30;
assign i_q_31=inverse?o_coeff_31:in_31;
assign i4_0 =i_valid?i_0 :o_q_0 ;
assign i4_1 =i_valid?i_1 :o_q_1 ;
assign i4_2 =i_valid?i_2 :o_q_2 ;
assign i4_3 =i_valid?i_3 :o_q_3 ;
assign i4_4 =i_valid?i_4 :o_q_4 ;
assign i4_5 =i_valid?i_5 :o_q_5 ;
assign i4_6 =i_valid?i_6 :o_q_6 ;
assign i4_7 =i_valid?i_7 :o_q_7 ;
assign i4_8 =i_valid?i_8 :o_q_8 ;
assign i4_9 =i_valid?i_9 :o_q_9 ;
assign i4_10=i_valid?i_10:o_q_10;
assign i4_11=i_valid?i_11:o_q_11;
assign i4_12=i_valid?i_12:o_q_12;
assign i4_13=i_valid?i_13:o_q_13;
assign i4_14=i_valid?i_14:o_q_14;
assign i4_15=i_valid?i_15:o_q_15;
assign i4_16=i_valid?i_16:o_q_16;
assign i4_17=i_valid?i_17:o_q_17;
assign i4_18=i_valid?i_18:o_q_18;
assign i4_19=i_valid?i_19:o_q_19;
assign i4_20=i_valid?i_20:o_q_20;
assign i4_21=i_valid?i_21:o_q_21;
assign i4_22=i_valid?i_22:o_q_22;
assign i4_23=i_valid?i_23:o_q_23;
assign i4_24=i_valid?i_24:o_q_24;
assign i4_25=i_valid?i_25:o_q_25;
assign i4_26=i_valid?i_26:o_q_26;
assign i4_27=i_valid?i_27:o_q_27;
assign i4_28=i_valid?i_28:o_q_28;
assign i4_29=i_valid?i_29:o_q_29;
assign i4_30=i_valid?i_30:o_q_30;
assign i4_31=i_valid?i_31:o_q_31;
assign in_0 =(tq_size_i==2'b00)?i4_0 :i_0 ;
assign in_1 =(tq_size_i==2'b00)?i4_1 :i_1 ;
assign in_2 =(tq_size_i==2'b00)?i4_2 :i_2 ;
assign in_3 =(tq_size_i==2'b00)?i4_3 :i_3 ;
assign in_4 =(tq_size_i==2'b00)?i4_4 :i_4 ;
assign in_5 =(tq_size_i==2'b00)?i4_5 :i_5 ;
assign in_6 =(tq_size_i==2'b00)?i4_6 :i_6 ;
assign in_7 =(tq_size_i==2'b00)?i4_7 :i_7 ;
assign in_8 =(tq_size_i==2'b00)?i4_8 :i_8 ;
assign in_9 =(tq_size_i==2'b00)?i4_9 :i_9 ;
assign in_10=(tq_size_i==2'b00)?i4_10:i_10;
assign in_11=(tq_size_i==2'b00)?i4_11:i_11;
assign in_12=(tq_size_i==2'b00)?i4_12:i_12;
assign in_13=(tq_size_i==2'b00)?i4_13:i_13;
assign in_14=(tq_size_i==2'b00)?i4_14:i_14;
assign in_15=(tq_size_i==2'b00)?i4_15:i_15;
assign in_16=(tq_size_i==2'b00)?i4_16:i_16;
assign in_17=(tq_size_i==2'b00)?i4_17:i_17;
assign in_18=(tq_size_i==2'b00)?i4_18:i_18;
assign in_19=(tq_size_i==2'b00)?i4_19:i_19;
assign in_20=(tq_size_i==2'b00)?i4_20:i_20;
assign in_21=(tq_size_i==2'b00)?i4_21:i_21;
assign in_22=(tq_size_i==2'b00)?i4_22:i_22;
assign in_23=(tq_size_i==2'b00)?i4_23:i_23;
assign in_24=(tq_size_i==2'b00)?i4_24:i_24;
assign in_25=(tq_size_i==2'b00)?i4_25:i_25;
assign in_26=(tq_size_i==2'b00)?i4_26:i_26;
assign in_27=(tq_size_i==2'b00)?i4_27:i_27;
assign in_28=(tq_size_i==2'b00)?i4_28:i_28;
assign in_29=(tq_size_i==2'b00)?i4_29:i_29;
assign in_30=(tq_size_i==2'b00)?i4_30:i_30;
assign in_31=(tq_size_i==2'b00)?i4_31:i_31;
assign cef_wen_o =inverse?1'b0:o_q_valid;
assign i_coeff_0 =inverse?16'b0:o_q_0 ;
assign i_coeff_1 =inverse?16'b0:o_q_1 ;
assign i_coeff_2 =inverse?16'b0:o_q_2 ;
assign i_coeff_3 =inverse?16'b0:o_q_3 ;
assign i_coeff_4 =inverse?16'b0:o_q_4 ;
assign i_coeff_5 =inverse?16'b0:o_q_5 ;
assign i_coeff_6 =inverse?16'b0:o_q_6 ;
assign i_coeff_7 =inverse?16'b0:o_q_7 ;
assign i_coeff_8 =inverse?16'b0:o_q_8 ;
assign i_coeff_9 =inverse?16'b0:o_q_9 ;
assign i_coeff_10=inverse?16'b0:o_q_10;
assign i_coeff_11=inverse?16'b0:o_q_11;
assign i_coeff_12=inverse?16'b0:o_q_12;
assign i_coeff_13=inverse?16'b0:o_q_13;
assign i_coeff_14=inverse?16'b0:o_q_14;
assign i_coeff_15=inverse?16'b0:o_q_15;
assign i_coeff_16=inverse?16'b0:o_q_16;
assign i_coeff_17=inverse?16'b0:o_q_17;
assign i_coeff_18=inverse?16'b0:o_q_18;
assign i_coeff_19=inverse?16'b0:o_q_19;
assign i_coeff_20=inverse?16'b0:o_q_20;
assign i_coeff_21=inverse?16'b0:o_q_21;
assign i_coeff_22=inverse?16'b0:o_q_22;
assign i_coeff_23=inverse?16'b0:o_q_23;
assign i_coeff_24=inverse?16'b0:o_q_24;
assign i_coeff_25=inverse?16'b0:o_q_25;
assign i_coeff_26=inverse?16'b0:o_q_26;
assign i_coeff_27=inverse?16'b0:o_q_27;
assign i_coeff_28=inverse?16'b0:o_q_28;
assign i_coeff_29=inverse?16'b0:o_q_29;
assign i_coeff_30=inverse?16'b0:o_q_30;
assign i_coeff_31=inverse?16'b0:o_q_31;
assign cef_data_o={i_coeff_31,i_coeff_30,i_coeff_29,i_coeff_28,
i_coeff_27,i_coeff_26,i_coeff_25,i_coeff_24,
i_coeff_23,i_coeff_22,i_coeff_21,i_coeff_20,
i_coeff_19,i_coeff_18,i_coeff_17,i_coeff_16,
i_coeff_15,i_coeff_14,i_coeff_13,i_coeff_12,
i_coeff_11,i_coeff_10,i_coeff_9,i_coeff_8,
i_coeff_7,i_coeff_6,i_coeff_5,i_coeff_4,
i_coeff_3,i_coeff_2,i_coeff_1,i_coeff_0
};
assign o_coeff_0 =cef_data_i[15 :0 ];
assign o_coeff_1 =cef_data_i[31 :16 ];
assign o_coeff_2 =cef_data_i[47 :32 ];
assign o_coeff_3 =cef_data_i[63 :48 ];
assign o_coeff_4 =cef_data_i[79 :64 ];
assign o_coeff_5 =cef_data_i[95 :80 ];
assign o_coeff_6 =cef_data_i[111:96 ];
assign o_coeff_7 =cef_data_i[127:112];
assign o_coeff_8 =cef_data_i[143:128];
assign o_coeff_9 =cef_data_i[159:144];
assign o_coeff_10=cef_data_i[175:160];
assign o_coeff_11=cef_data_i[191:176];
assign o_coeff_12=cef_data_i[207:192];
assign o_coeff_13=cef_data_i[223:208];
assign o_coeff_14=cef_data_i[239:224];
assign o_coeff_15=cef_data_i[255:240];
assign o_coeff_16=cef_data_i[271:256];
assign o_coeff_17=cef_data_i[287:272];
assign o_coeff_18=cef_data_i[303:288];
assign o_coeff_19=cef_data_i[319:304];
assign o_coeff_20=cef_data_i[335:320];
assign o_coeff_21=cef_data_i[351:336];
assign o_coeff_22=cef_data_i[367:352];
assign o_coeff_23=cef_data_i[383:368];
assign o_coeff_24=cef_data_i[399:384];
assign o_coeff_25=cef_data_i[415:400];
assign o_coeff_26=cef_data_i[431:416];
assign o_coeff_27=cef_data_i[447:432];
assign o_coeff_28=cef_data_i[463:448];
assign o_coeff_29=cef_data_i[479:464];
assign o_coeff_30=cef_data_i[495:480];
assign o_coeff_31=cef_data_i[511:496];
assign o_valid=inverse?o_q_valid:1'b0;
assign o_0 =inverse?o_q_0 :16'd0;
assign o_1 =inverse?o_q_1 :16'd0;
assign o_2 =inverse?o_q_2 :16'd0;
assign o_3 =inverse?o_q_3 :16'd0;
assign o_4 =inverse?o_q_4 :16'd0;
assign o_5 =inverse?o_q_5 :16'd0;
assign o_6 =inverse?o_q_6 :16'd0;
assign o_7 =inverse?o_q_7 :16'd0;
assign o_8 =inverse?o_q_8 :16'd0;
assign o_9 =inverse?o_q_9 :16'd0;
assign o_10=inverse?o_q_10:16'd0;
assign o_11=inverse?o_q_11:16'd0;
assign o_12=inverse?o_q_12:16'd0;
assign o_13=inverse?o_q_13:16'd0;
assign o_14=inverse?o_q_14:16'd0;
assign o_15=inverse?o_q_15:16'd0;
assign o_16=inverse?o_q_16:16'd0;
assign o_17=inverse?o_q_17:16'd0;
assign o_18=inverse?o_q_18:16'd0;
assign o_19=inverse?o_q_19:16'd0;
assign o_20=inverse?o_q_20:16'd0;
assign o_21=inverse?o_q_21:16'd0;
assign o_22=inverse?o_q_22:16'd0;
assign o_23=inverse?o_q_23:16'd0;
assign o_24=inverse?o_q_24:16'd0;
assign o_25=inverse?o_q_25:16'd0;
assign o_26=inverse?o_q_26:16'd0;
assign o_27=inverse?o_q_27:16'd0;
assign o_28=inverse?o_q_28:16'd0;
assign o_29=inverse?o_q_29:16'd0;
assign o_30=inverse?o_q_30:16'd0;
assign o_31=inverse?o_q_31:16'd0;
always@(*)
case(tq_size_i)
2'b00:begin
cef_widx_o=5'd0;
cef_ridx_o=5'd0;
end
2'b01:begin
cef_widx_o=(counter_1<<2);
cef_ridx_o=(counter_2<<2);
end
2'b10:begin
cef_widx_o=(counter_1<<1);
cef_ridx_o=(counter_2<<1);
end
2'b11:begin
cef_widx_o=counter_1;
cef_ridx_o=counter_2;
end
endcase
// ***************************************************
//
// Sequential Logic
//
// ***************************************************
always@(posedge clk or negedge rst)
if(!rst)
counter_1<=5'd0;
else
if(cef_wen_o)
counter_1<=counter_1+1'b1;
else
counter_1<=5'd0;
always@(posedge clk or negedge rst)
if(!rst)
counter_2<=5'd0;
else
if(cef_ren_o)
counter_2<=counter_2+1'b1;
else
counter_2<=5'd0;
always@(posedge clk or negedge rst)
if(!rst)
cef_ren_o<=1'b0;
else
if(cef_wen_o)
case(tq_size_i)
2'b00:cef_ren_o<=1'b0;
2'b01:if(counter_1==5'd1)
cef_ren_o<=1'b1;
else
cef_ren_o<=1'b0;
2'b10:if(counter_1==5'd7)
cef_ren_o<=1'b1;
else
cef_ren_o<=1'b0;
2'b11:if(counter_1==5'd31)
cef_ren_o<=1'b1;
else
cef_ren_o<=1'b0;
endcase
else
case(tq_size_i)
2'b00:cef_ren_o<=1'b0;
2'b01:if(counter_2==5'd1)
cef_ren_o<=1'b0;
2'b10:if(counter_2==5'd7)
cef_ren_o<=1'b0;
2'b11:if(counter_2==5'd31)
cef_ren_o<=1'b0;
endcase
always@(posedge clk or negedge rst)
if(!rst)
cef_val_i<=1'b0;
else
cef_val_i<=cef_ren_o;
//*************************************************
//
// SUB MODULE
//
//**************************************************
quan quan_0(
.clk(clk),
.rst(rst),
.type(type_i),
. qp(qp_i),
.i_valid(tq_en_i),
.i_2d_valid(i_q_valid),
.i_transize(tq_size_i),
.i_0(i_q_0),
.i_1(i_q_1),
.i_2(i_q_2),
.i_3(i_q_3),
.i_4(i_q_4),
.i_5(i_q_5),
.i_6(i_q_6),
.i_7(i_q_7),
.i_8(i_q_8),
.i_9(i_q_9),
.i_10(i_q_10),
.i_11(i_q_11),
.i_12(i_q_12),
.i_13(i_q_13),
.i_14(i_q_14),
.i_15(i_q_15),
.i_16(i_q_16),
.i_17(i_q_17),
.i_18(i_q_18),
.i_19(i_q_19),
.i_20(i_q_20),
.i_21(i_q_21),
.i_22(i_q_22),
.i_23(i_q_23),
.i_24(i_q_24),
.i_25(i_q_25),
.i_26(i_q_26),
.i_27(i_q_27),
.i_28(i_q_28),
.i_29(i_q_29),
.i_30(i_q_30),
.i_31(i_q_31),
.o_valid(o_q_valid),
.o_0(o_q_0),
.o_1(o_q_1),
.o_2(o_q_2),
.o_3(o_q_3),
.o_4(o_q_4),
.o_5(o_q_5),
.o_6(o_q_6),
.o_7(o_q_7),
.o_8(o_q_8),
.o_9(o_q_9),
.o_10(o_q_10),
.o_11(o_q_11),
.o_12(o_q_12),
.o_13(o_q_13),
.o_14(o_q_14),
.o_15(o_q_15),
.o_16(o_q_16),
.o_17(o_q_17),
.o_18(o_q_18),
.o_19(o_q_19),
.o_20(o_q_20),
.o_21(o_q_21),
.o_22(o_q_22),
.o_23(o_q_23),
.o_24(o_q_24),
.o_25(o_q_25),
.o_26(o_q_26),
.o_27(o_q_27),
.o_28(o_q_28),
.o_29(o_q_29),
.o_30(o_q_30),
.o_31(o_q_31)
);
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p/sky130_fd_sc_lp__udp_dlatch_p.v"
`celldefine
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
// Delay Name Output Other arguments
not not0 (clkn , CLK );
sky130_fd_sc_lp__udp_dlatch$P `UNIT_DELAY dlatch0 (m0 , GATE, clkn );
and and0 (GCLK , m0, CLK );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_FUNCTIONAL_V |
//altpll bandwidth_type="AUTO" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" clk0_divide_by=25 clk0_duty_cycle=50 clk0_multiply_by=1 clk0_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone IV E" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" lpm_hint="CBX_MODULE_PREFIX=dac_pll" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
//VERSION_BEGIN 16.0 cbx_altclkbuf 2016:04:27:18:05:34:SJ cbx_altiobuf_bidir 2016:04:27:18:05:34:SJ cbx_altiobuf_in 2016:04:27:18:05:34:SJ cbx_altiobuf_out 2016:04:27:18:05:34:SJ cbx_altpll 2016:04:27:18:05:34:SJ cbx_cycloneii 2016:04:27:18:05:34:SJ cbx_lpm_add_sub 2016:04:27:18:05:34:SJ cbx_lpm_compare 2016:04:27:18:05:34:SJ cbx_lpm_counter 2016:04:27:18:05:34:SJ cbx_lpm_decode 2016:04:27:18:05:34:SJ cbx_lpm_mux 2016:04:27:18:05:34:SJ cbx_mgl 2016:04:27:18:06:48:SJ cbx_nadder 2016:04:27:18:05:34:SJ cbx_stratix 2016:04:27:18:05:34:SJ cbx_stratixii 2016:04:27:18:05:34:SJ cbx_stratixiii 2016:04:27:18:05:34:SJ cbx_stratixv 2016:04:27:18:05:34:SJ cbx_util_mgl 2016:04:27:18:05:34:SJ VERSION_END
//CBXI_INSTANCE_NAME="DE0_myfirstfpga_dac_pll_inst_altpll_altpll_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = cycloneive_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module dac_pll_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneive_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 25,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 1,
pll1.clk0_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 20000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneive_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //dac_pll_altpll
//VALID FILE
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CPU OPERATING MODES */
/*---------------------------------------------------------------------------*/
/* Test the CPU Operating modes: */
/* - CPUOFF (<=> R2[4]): turn off CPU. */
/* - OSCOFF (<=> R2[5]): turn off LFXT_CLK. */
/* - SCG0 (<=> R2[6]): turn off DCO. */
/* - SCG1 (<=> R2[7]): turn off SMCLK. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
integer dco_clk_cnt;
always @(negedge dco_clk)
dco_clk_cnt <= dco_clk_cnt+1;
integer mclk_cnt;
always @(negedge mclk)
mclk_cnt <= mclk_cnt+1;
integer smclk_cnt;
always @(negedge smclk)
smclk_cnt <= smclk_cnt+1;
integer aclk_cnt;
always @(negedge aclk)
aclk_cnt <= aclk_cnt+1;
integer inst_cnt;
always @(inst_number)
inst_cnt = inst_cnt+1;
// Wakeup synchronizer to generate IRQ
reg [1:0] wkup2_sync;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) wkup2_sync <= 2'b00;
else wkup2_sync <= {wkup2_sync[0], wkup[2]};
always @(wkup2_sync)
irq[`IRQ_NR-14] = wkup2_sync[1]; // IRQ-2
// Wakeup synchronizer to generate IRQ
reg [1:0] wkup3_sync;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) wkup3_sync <= 2'b00;
else wkup3_sync <= {wkup3_sync[0], wkup[3]};
always @(wkup3_sync)
irq[`IRQ_NR-13] = wkup3_sync[1]; // IRQ-3
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
irq[`IRQ_NR-14] = 0; // IRQ-2
wkup[2] = 0;
irq[`IRQ_NR-13] = 0; // IRQ-3
wkup[3] = 0;
`ifdef ASIC_CLOCKING
// SCG1 (<=> R2[7]): turn off SMCLK
//--------------------------------------------------------
@(r15==16'h1001);
repeat (10) @(posedge mclk);
smclk_cnt = 0;
repeat (100) @(posedge mclk);
if (smclk_cnt !== 100) tb_error("====== SCG1 TEST 1: SMCLK IS NOT RUNNING =====");
smclk_cnt = 0;
@(r15==16'h1002);
repeat (10) @(posedge mclk);
smclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef SCG1_EN
if (smclk_cnt !== 0) tb_error("====== SCG1 TEST 2: SMCLK IS NOT STOPPED =====");
`else
if (smclk_cnt !== 100) tb_error("====== SCG1 TEST 2: SMCLK IS STOPPED =====");
`endif
smclk_cnt = 0;
@(r15==16'h1003); //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
wkup[3] = 1'b1;
@(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
aclk_cnt = 0;
repeat (10) @(posedge mclk);
smclk_cnt = 0;
repeat (50) @(posedge mclk);
if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 3: SMCLK IS NOT RUNNING DURING IRQ =====");
smclk_cnt = 0;
@(r13==16'hbbbb);
wkup[3] = 1'b0;
@(r15==16'h1004);
smclk_cnt = 0;
repeat (50) @(posedge mclk);
if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 4: SMCLK IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
smclk_cnt = 0;
@(r15==16'h1005);
repeat (10) @(posedge mclk);
smclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef SCG1_EN
if (smclk_cnt !== 0) tb_error("====== SCG1 TEST 5: SMCLK IS NOT STOPPED =====");
`else
if (smclk_cnt !== 100) tb_error("====== SCG1 TEST 5: SMCLK IS STOPPED =====");
`endif
smclk_cnt = 0;
@(r15==16'h1006); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
wkup[2] = 1'b1;
@(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
repeat (10) @(posedge mclk);
smclk_cnt = 0;
repeat (50) @(posedge mclk);
if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 6: SMCLK IS NOT RUNNING DURING IRQ =====");
smclk_cnt = 0;
@(r13==16'haaaa);
wkup[2] = 1'b0;
@(r15==16'h1007);
repeat (10) @(posedge mclk);
smclk_cnt = 0;
repeat (50) @(posedge mclk);
`ifdef SCG1_EN
if (smclk_cnt !== 0) tb_error("====== SCG1 TEST 7: SMCLK IS NOT STOPPED WHEN RETURNING FROM IRQ =====");
`else
if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 7: SMCLK IS STOPPED WHEN RETURNING FROM IRQ =====");
`endif
smclk_cnt = 0;
@(r15==16'h1008);
repeat (10) @(posedge mclk);
smclk_cnt = 0;
repeat (50) @(posedge mclk);
if (smclk_cnt !== 50) tb_error("====== SCG1 TEST 8: SMCLK IS NOT RUNNING =====");
smclk_cnt = 0;
// OSCOFF (<=> R2[5]): turn off LFXT1CLK
//--------------------------------------------------------
@(r15==16'h2001);
repeat (10) @(posedge mclk);
aclk_cnt = 0;
repeat (200) @(posedge mclk);
`ifdef LFXT_DOMAIN
if (aclk_cnt !== 7) tb_error("====== OSCOFF TEST 1: ACLK IS NOT RUNNING =====");
`else
if (aclk_cnt !== 200) tb_error("====== OSCOFF TEST 1: ACLK IS NOT RUNNING =====");
`endif
aclk_cnt = 0;
@(r15==16'h2002);
repeat (100) @(posedge mclk);
aclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef OSCOFF_EN
if (aclk_cnt !== 0) tb_error("====== OSCOFF TEST 2: ACLK IS NOT STOPPED =====");
`else
if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 2: ACLK IS STOPPED =====");
`endif
aclk_cnt = 0;
@(r15==16'h2003); //---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
wkup[3] = 1'b1;
@(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
repeat (100) @(posedge mclk);
aclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef LFXT_DOMAIN
if (aclk_cnt !== 3) tb_error("====== OSCOFF TEST 3: ACLK IS NOT RUNNING DURING IRQ =====");
`else
if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 3: ACLK IS NOT RUNNING DURING IRQ =====");
`endif
aclk_cnt = 0;
@(r13==16'hbbbb);
wkup[3] = 1'b0;
@(r15==16'h2004);
repeat (100) @(posedge mclk);
aclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef LFXT_DOMAIN
if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 4: ACLK IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
`else
if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 4: ACLK IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
`endif
aclk_cnt = 0;
@(r15==16'h2005);
repeat (100) @(posedge mclk);
aclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef OSCOFF_EN
if (aclk_cnt !== 0) tb_error("====== OSCOFF TEST 5: ACLK IS NOT STOPPED =====");
`else
if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 5: ACLK IS STOPPED =====");
`endif
aclk_cnt = 0;
@(r15==16'h2006); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
wkup[2] = 1'b1;
@(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
repeat (100) @(posedge mclk);
aclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef LFXT_DOMAIN
if (aclk_cnt !== 3) tb_error("====== OSCOFF TEST 6: ACLK IS NOT RUNNING DURING IRQ =====");
`else
if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 6: ACLK IS NOT RUNNING DURING IRQ =====");
`endif
aclk_cnt = 0;
@(r13==16'haaaa);
wkup[2] = 1'b0;
@(r15==16'h2007);
repeat (100) @(posedge mclk);
aclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef OSCOFF_EN
if (aclk_cnt !== 0) tb_error("====== OSCOFF TEST 7: ACLK IS NOT STOPPED WHEN RETURNING FROM IRQ =====");
`else
if (aclk_cnt < 3) tb_error("====== OSCOFF TEST 7: ACLK IS STOPPED WHEN RETURNING FROM IRQ =====");
`endif
aclk_cnt = 0;
@(r15==16'h2008);
repeat (100) @(posedge mclk);
aclk_cnt = 0;
repeat (100) @(posedge mclk);
`ifdef LFXT_DOMAIN
if (aclk_cnt !== 3) tb_error("====== OSCOFF TEST 8: ACLK IS NOT RUNNING =====");
`else
if (aclk_cnt !== 100) tb_error("====== OSCOFF TEST 8: ACLK IS NOT RUNNING =====");
`endif
aclk_cnt = 0;
// CPUOFF (<=> R2[4]): turn off CPU
//--------------------------------------------------------
@(r15==16'h3001);
repeat (10) @(negedge dco_clk);
mclk_cnt = 0;
repeat (80) @(negedge dco_clk);
if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 1: CPU IS NOT RUNNING =====");
@(r15==16'h3002);
repeat (10) @(negedge dco_clk);
mclk_cnt = 0;
repeat (80) @(negedge dco_clk);
if (mclk_cnt !== 0) tb_error("====== CPUOFF TEST 2: CPU IS NOT STOPPED =====");
@(posedge dco_clk); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
wkup[2] = 1'b1;
@(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
repeat(10) @(negedge dco_clk);
mclk_cnt = 0;
repeat (80) @(negedge dco_clk);
if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
mclk_cnt = 0;
@(r13==16'haaaa);
wkup[2] = 1'b0;
@(r1==(`PER_SIZE+16'h0050));
repeat (10) @(negedge dco_clk);
mclk_cnt = 0;
repeat (80) @(negedge dco_clk);
if (mclk_cnt !== 0) tb_error("====== CPUOFF TEST 4: CPU IS NOT STOPPED AFTER IRQ =====");
//---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
wkup[3] = 1'b1;
@(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
repeat (10) @(posedge dco_clk);
mclk_cnt = 0;
repeat (80) @(posedge dco_clk);
if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ =====");
mclk_cnt = 0;
@(r13==16'hbbbb);
wkup[3] = 1'b0;
@(r1==(`PER_SIZE+16'h0050));
repeat (10) @(negedge dco_clk);
mclk_cnt = 0;
repeat (80) @(negedge dco_clk);
if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING AFTER IRQ =====");
@(r15==16'h3003);
repeat (10) @(posedge dco_clk);
mclk_cnt = 0;
repeat (80) @(posedge dco_clk);
if (mclk_cnt !== 80) tb_error("====== CPUOFF TEST 7: CPU IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
mclk_cnt = 0;
// SCG0 (<=> R2[6]): turn off DCO oscillator
//--------------------------------------------------------
@(r15==16'h4001);
#(10*50);
dco_clk_cnt = 0;
#(80*50);
if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 1: DCO IS NOT RUNNING =====");
@(r15==16'h4002);
#(10*50);
dco_clk_cnt = 0;
#(80*50);
if (dco_clk_cnt !== 0) tb_error("====== SCG0 TEST 2: DCO IS NOT STOPPED =====");
#(1*50); //---------- PORT1 IRQ TRIAL (STAYING IN POWER MODE) -------------//
wkup[2] = 1'b1;
@(posedge irq_acc[`IRQ_NR-14]); // IRQ_ACC-2
#(10*50);
dco_clk_cnt = 0;
#(80*50);
if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 3: DCO IS NOT RUNNING DURING IRQ (PORT 1) =====");
dco_clk_cnt = 0;
@(r13==16'haaaa);
wkup[2] = 1'b0;
#(10*50);
dco_clk_cnt = 0;
#(80*50);
if (dco_clk_cnt !== 0) tb_error("====== SCG0 TEST 4: DCO IS NOT STOPPED AFTER IRQ =====");
//---------- PORT2 IRQ TRIAL (EXITING POWER MODE) -------------//
wkup[3] = 1'b1;
@(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
#(10*50);
dco_clk_cnt = 0;
#(80*50);
if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 5: DCO IS NOT RUNNING DURING IRQ =====");
dco_clk_cnt = 0;
@(r13==16'hbbbb);
wkup[3] = 1'b0;
#(10*50);
dco_clk_cnt = 0;
#(80*50);
if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 6: DCO IS NOT RUNNING AFTER IRQ =====");
@(r15==16'h4003);
#(10*50);
dco_clk_cnt = 0;
#(80*50);
if (dco_clk_cnt !== 80) tb_error("====== SCG0 TEST 7: DCO IS STILL NOT RUNNING WHEN RETURNING FROM IRQ =====");
dco_clk_cnt = 0;
`else
tb_skip_finish("| (this test is not supported in FPGA mode) |");
`endif
stimulus_done = 1;
end
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DFXBP_BEHAVIORAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_lp__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXBP_BEHAVIORAL_PP_V |
(** * StlcProp: Properties of STLC *)
Require Export Stlc.
Module STLCProp.
Import STLC.
(** In this chapter, we develop the fundamental theory of the Simply
Typed Lambda Calculus -- in particular, the type safety
theorem. *)
(* ###################################################################### *)
(** * Canonical Forms *)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
(* ###################################################################### *)
(** * Progress *)
(** As before, the _progress_ theorem tells us that closed, well-typed
terms are not stuck: either a well-typed term is a value, or it
can take an evaluation step. The proof is a relatively
straightforward extension of the progress proof we saw in the
[Types] chapter. *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
(** _Proof_: by induction on the derivation of [|- t \in T].
- The last rule of the derivation cannot be [T_Var], since a
variable is never well typed in an empty context.
- The [T_True], [T_False], and [T_Abs] cases are trivial, since in
each of these cases we know immediately that [t] is a value.
- If the last rule of the derivation was [T_App], then [t = t1
t2], and we know that [t1] and [t2] are also well typed in the
empty context; in particular, there exists a type [T2] such that
[|- t1 \in T2 -> T] and [|- t2 \in T2]. By the induction
hypothesis, either [t1] is a value or it can take an evaluation
step.
- If [t1] is a value, we now consider [t2], which by the other
induction hypothesis must also either be a value or take an
evaluation step.
- Suppose [t2] is a value. Since [t1] is a value with an
arrow type, it must be a lambda abstraction; hence [t1
t2] can take a step by [ST_AppAbs].
- Otherwise, [t2] can take a step, and hence so can [t1
t2] by [ST_App2].
- If [t1] can take a step, then so can [t1 t2] by [ST_App1].
- If the last rule of the derivation was [T_If], then [t = if t1
then t2 else t3], where [t1] has type [Bool]. By the IH, [t1]
either is a value or takes a step.
- If [t1] is a value, then since it has type [Bool] it must be
either [true] or [false]. If it is [true], then [t] steps
to [t2]; otherwise it steps to [t3].
- Otherwise, [t1] takes a step, and therefore so does [t] (by
[ST_If]).
*)
Proof with eauto.
intros t T Ht.
remember (empty) as Gamma.
(* remember (@empty ty) as Gamma. *)
has_type_cases (induction Ht) Case; subst Gamma...
Case "T_Var".
(* contradictory: variables cannot be typed in an
empty context *)
inversion H.
Case "T_App".
(* [t] = [t1 t2]. Proceed by cases on whether [t1] is a
value or steps... *)
right. destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is also a value".
assert (exists x0 t0, t1 = tabs x0 T11 t0).
eapply canonical_forms_fun; eauto.
destruct H1 as [x0 [t0 Heq]]. subst.
exists ([x0:=t2]t0)...
SSCase "t2 steps".
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_If".
right. destruct IHHt1...
SCase "t1 is a value".
destruct (canonical_forms_bool t1); subst; eauto.
SCase "t1 also steps".
inversion H as [t1' Hstp]. exists (tif t1' t2 t3)...
Qed.
(** **** Exercise: 3 stars, optional (progress_from_term_ind) *)
(** Show that progress can also be proved by induction on terms
instead of induction on typing derivations. *)
Theorem progress' : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
intros t.
t_cases (induction t) Case; intros T Ht; auto.
inv Ht. inversion H1.
inv Ht.
generalize H2; intro H1.
generalize H4; intro H3.
apply IHt1 in H2.
apply IHt2 in H4.
right.
inv H4. inv H2.
inv H1; inv H0.
eexists. (*using it to early, right after right, will make next line not work *)
apply ST_AppAbs...
inv H0. eexists. apply ST_App1...
inv H2. inv H. eexists. apply ST_App2...
inv H. inv H0. eexists. apply ST_App1...
inv Ht.
generalize H3; intro T1.
generalize H5; intro T2.
generalize H6; intro T3.
apply IHt1 in H3.
apply IHt2 in H5.
apply IHt3 in H6.
right.
inv H3. inv H. inv T1. eexists; constructor. eexists; constructor.
inv H. eexists; constructor...
Qed.
(** [] *)
(* ###################################################################### *)
(** * Preservation *)
(** The other half of the type soundness property is the preservation
of types during reduction. For this, we need to develop some
technical machinery for reasoning about variables and
substitution. Working from top to bottom (the high-level property
we are actually interested in to the lowest-level technical lemmas
that are needed by various cases of the more interesting proofs),
the story goes like this:
- The _preservation theorem_ is proved by induction on a typing
derivation, pretty much as we did in the [Types] chapter. The
one case that is significantly different is the one for the
[ST_AppAbs] rule, which is defined using the substitution
operation. To see that this step preserves typing, we need to
know that the substitution itself does. So we prove a...
- _substitution lemma_, stating that substituting a (closed)
term [s] for a variable [x] in a term [t] preserves the type
of [t]. The proof goes by induction on the form of [t] and
requires looking at all the different cases in the definition
of substitition. This time, the tricky cases are the ones for
variables and for function abstractions. In both cases, we
discover that we need to take a term [s] that has been shown
to be well-typed in some context [Gamma] and consider the same
term [s] in a slightly different context [Gamma']. For this
we prove a...
- _context invariance_ lemma, showing that typing is preserved
under "inessential changes" to the context [Gamma] -- in
particular, changes that do not affect any of the free
variables of the term. For this, we need a careful definition
of
- the _free variables_ of a term -- i.e., the variables occuring
in the term that are not in the scope of a function
abstraction that binds them.
*)
(* ###################################################################### *)
(** ** Free Occurrences *)
(** A variable [x] _appears free in_ a term _t_ if [t] contains some
occurrence of [x] that is not under an abstraction labeled [x]. For example:
- [y] appears free, but [x] does not, in [\x:T->U. x y]
- both [x] and [y] appear free in [(\x:T->U. x y) x]
- no variables appear free in [\x:T->U. \y:T. x y] *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2"
| Case_aux c "afi_abs"
| Case_aux c "afi_if1" | Case_aux c "afi_if2"
| Case_aux c "afi_if3" ].
Hint Constructors appears_free_in.
(** A term in which no variables appear free is said to be _closed_. *)
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
(* ###################################################################### *)
(** ** Substitution *)
(** We first need a technical lemma connecting free variables and
typing contexts. If a variable [x] appears free in a term [t],
and if we know [t] is well typed in context [Gamma], then it must
be the case that [Gamma] assigns a type to [x]. *)
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
(** _Proof_: We show, by induction on the proof that [x] appears free
in [t], that, for all contexts [Gamma], if [t] is well typed
under [Gamma], then [Gamma] assigns some type to [x].
- If the last rule used was [afi_var], then [t = x], and from
the assumption that [t] is well typed under [Gamma] we have
immediately that [Gamma] assigns a type to [x].
- If the last rule used was [afi_app1], then [t = t1 t2] and [x]
appears free in [t1]. Since [t] is well typed under [Gamma],
we can see from the typing rules that [t1] must also be, and
the IH then tells us that [Gamma] assigns [x] a type.
- Almost all the other cases are similar: [x] appears free in a
subterm of [t], and since [t] is well typed under [Gamma], we
know the subterm of [t] in which [x] appears is well typed
under [Gamma] as well, and the IH gives us exactly the
conclusion we want.
- The only remaining case is [afi_abs]. In this case [t =
\y:T11.t12], and [x] appears free in [t12]; we also know that
[x] is different from [y]. The difference from the previous
cases is that whereas [t] is well typed under [Gamma], its
body [t12] is well typed under [(Gamma, y:T11)], so the IH
allows us to conclude that [x] is assigned some type by the
extended context [(Gamma, y:T11)]. To conclude that [Gamma]
assigns a type to [x], we appeal to lemma [extend_neq], noting
that [x] and [y] are different variables. *)
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
(** Next, we'll need the fact that any term [t] which is well typed in
the empty context is closed -- that is, it has no free variables. *)
(** **** Exercise: 2 stars, optional (typable_empty__closed) *)
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Proof.
unfold closed, not.
intros.
apply free_in_context with (Gamma:=empty) (T:=T) in H0.
inv H0. inv H1. assumption.
Qed.
(** Sometimes, when we have a proof [Gamma |- t : T], we will need to
replace [Gamma] by a different context [Gamma']. When is it safe
to do this? Intuitively, it must at least be the case that
[Gamma'] assigns the same types as [Gamma] to all the variables
that appear free in [t]. In fact, this is the only condition that
is needed. *)
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
(** _Proof_: By induction on the derivation of [Gamma |- t \in T].
- If the last rule in the derivation was [T_Var], then [t = x]
and [Gamma x = T]. By assumption, [Gamma' x = T] as well, and
hence [Gamma' |- t \in T] by [T_Var].
- If the last rule was [T_Abs], then [t = \y:T11. t12], with [T
= T11 -> T12] and [Gamma, y:T11 |- t12 \in T12]. The induction
hypothesis is that for any context [Gamma''], if [Gamma,
y:T11] and [Gamma''] assign the same types to all the free
variables in [t12], then [t12] has type [T12] under [Gamma''].
Let [Gamma'] be a context which agrees with [Gamma] on the
free variables in [t]; we must show [Gamma' |- \y:T11. t12 \in
T11 -> T12].
By [T_Abs], it suffices to show that [Gamma', y:T11 |- t12 \in
T12]. By the IH (setting [Gamma'' = Gamma', y:T11]), it
suffices to show that [Gamma, y:T11] and [Gamma', y:T11] agree
on all the variables that appear free in [t12].
Any variable occurring free in [t12] must either be [y], or
some other variable. [Gamma, y:T11] and [Gamma', y:T11]
clearly agree on [y]. Otherwise, we note that any variable
other than [y] which occurs free in [t12] also occurs free in
[t = \y:T11. t12], and by assumption [Gamma] and [Gamma']
agree on all such variables, and hence so do [Gamma, y:T11]
and [Gamma', y:T11].
- If the last rule was [T_App], then [t = t1 t2], with [Gamma |-
t1 \in T2 -> T] and [Gamma |- t2 \in T2]. One induction
hypothesis states that for all contexts [Gamma'], if [Gamma']
agrees with [Gamma] on the free variables in [t1], then [t1]
has type [T2 -> T] under [Gamma']; there is a similar IH for
[t2]. We must show that [t1 t2] also has type [T] under
[Gamma'], given the assumption that [Gamma'] agrees with
[Gamma] on all the free variables in [t1 t2]. By [T_App], it
suffices to show that [t1] and [t2] each have the same type
under [Gamma'] as under [Gamma]. However, we note that all
free variables in [t1] are also free in [t1 t2], and similarly
for free variables in [t2]; hence the desired result follows
by the two IHs.
*)
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros; auto.
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
(** Now we come to the conceptual heart of the proof that reduction
preserves types -- namely, the observation that _substitution_
preserves types.
Formally, the so-called _Substitution Lemma_ says this: suppose we
have a term [t] with a free variable [x], and suppose we've been
able to assign a type [T] to [t] under the assumption that [x] has
some type [U]. Also, suppose that we have some other term [v] and
that we've shown that [v] has type [U]. Then, since [v] satisfies
the assumption we made about [x] when typing [t], we should be
able to substitute [v] for each of the occurrences of [x] in [t]
and obtain a new term that still has type [T]. *)
(** _Lemma_: If [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T]. *)
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
(** One technical subtlety in the statement of the lemma is that we
assign [v] the type [U] in the _empty_ context -- in other words,
we assume [v] is closed. This assumption considerably simplifies
the [T_Abs] case of the proof (compared to assuming [Gamma |- v \in
U], which would be the other reasonable assumption at this point)
because the context invariance lemma then tells us that [v] has
type [U] in any context at all -- we don't have to worry about
free variables in [v] clashing with the variable being introduced
into the context by [T_Abs].
_Proof_: We prove, by induction on [t], that, for all [T] and
[Gamma], if [Gamma,x:U |- t \in T] and [|- v \in U], then [Gamma |-
[x:=v]t \in T].
- If [t] is a variable, there are two cases to consider, depending
on whether [t] is [x] or some other variable.
- If [t = x], then from the fact that [Gamma, x:U |- x \in T] we
conclude that [U = T]. We must show that [[x:=v]x = v] has
type [T] under [Gamma], given the assumption that [v] has
type [U = T] under the empty context. This follows from
context invariance: if a closed term has type [T] in the
empty context, it has that type in any context.
- If [t] is some variable [y] that is not equal to [x], then
we need only note that [y] has the same type under [Gamma,
x:U] as under [Gamma].
- If [t] is an abstraction [\y:T11. t12], then the IH tells us,
for all [Gamma'] and [T'], that if [Gamma',x:U |- t12 \in T']
and [|- v \in U], then [Gamma' |- [x:=v]t12 \in T'].
The substitution in the conclusion behaves differently,
depending on whether [x] and [y] are the same variable name.
First, suppose [x = y]. Then, by the definition of
substitution, [[x:=v]t = t], so we just need to show [Gamma |-
t \in T]. But we know [Gamma,x:U |- t : T], and since the
variable [y] does not appear free in [\y:T11. t12], the
context invariance lemma yields [Gamma |- t \in T].
Second, suppose [x <> y]. We know [Gamma,x:U,y:T11 |- t12 \in
T12] by inversion of the typing relation, and [Gamma,y:T11,x:U
|- t12 \in T12] follows from this by the context invariance
lemma, so the IH applies, giving us [Gamma,y:T11 |- [x:=v]t12 \in
T12]. By [T_Abs], [Gamma |- \y:T11. [x:=v]t12 \in T11->T12], and
by the definition of substitution (noting that [x <> y]),
[Gamma |- \y:T11. [x:=v]t12 \in T11->T12] as required.
- If [t] is an application [t1 t2], the result follows
straightforwardly from the definition of substitution and the
induction hypotheses.
- The remaining cases are similar to the application case.
Another technical note: This proof is a rare case where an
induction on terms, rather than typing derivations, yields a
simpler argument. The reason for this is that the assumption
[extend Gamma x U |- t \in T] is not completely generic, in
the sense that one of the "slots" in the typing relation -- namely
the context -- is not just a variable, and this means that Coq's
native induction tactic does not give us the induction hypothesis
that we want. It is possible to work around this, but the needed
generalization is a little tricky. The term [t], on the other
hand, _is_ completely generic. *)
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
(** The substitution lemma can be viewed as a kind of "commutation"
property. Intuitively, it says that substitution and typing can
be done in either order: we can either assign types to the terms
[t] and [v] separately (under suitable contexts) and then combine
them using substitution, or we can substitute first and then
assign a type to [ [x:=v] t ] -- the result is the same either
way. *)
(* ###################################################################### *)
(** ** Main Theorem *)
(** We now have the tools we need to prove preservation: if a closed
term [t] has type [T], and takes an evaluation step to [t'], then [t']
is also a closed term with type [T]. In other words, the small-step
evaluation relation preserves types.
*)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
(** _Proof_: by induction on the derivation of [|- t \in T].
- We can immediately rule out [T_Var], [T_Abs], [T_True], and
[T_False] as the final rules in the derivation, since in each of
these cases [t] cannot take a step.
- If the last rule in the derivation was [T_App], then [t = t1
t2]. There are three cases to consider, one for each rule that
could have been used to show that [t1 t2] takes a step to [t'].
- If [t1 t2] takes a step by [ST_App1], with [t1] stepping to
[t1'], then by the IH [t1'] has the same type as [t1], and
hence [t1' t2] has the same type as [t1 t2].
- The [ST_App2] case is similar.
- If [t1 t2] takes a step by [ST_AppAbs], then [t1 =
\x:T11.t12] and [t1 t2] steps to [[x:=t2]t12]; the
desired result now follows from the fact that substitution
preserves types.
- If the last rule in the derivation was [T_If], then [t = if t1
then t2 else t3], and there are again three cases depending on
how [t] steps.
- If [t] steps to [t2] or [t3], the result is immediate, since
[t2] and [t3] have the same type as [t].
- Otherwise, [t] steps by [ST_If], and the desired conclusion
follows directly from the induction hypothesis.
*)
Proof with eauto.
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
Qed.
(** **** Exercise: 2 stars (subject_expansion_stlc) *)
(** An exercise in the [Types] chapter asked about the subject
expansion property for the simple language of arithmetic and
boolean expressions. Does this property hold for STLC? That is,
is it always the case that, if [t ==> t'] and [has_type t' T],
then [empty |- t \in T]? If so, prove it. If not, give a
counter-example not involving conditionals.
(* FILL IN HERE *)
[]
*)
(* ###################################################################### *)
(** * Type Soundness *)
(** **** Exercise: 2 stars, optional (type_soundness) *)
(** Put progress and preservation together and show that a well-typed
term can _never_ reach a stuck state. *)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
unfold not in Hnf.
unfold not in Hnot_val.
apply progress in Hhas_type.
inv Hhas_type. apply Hnot_val in H. inv H.
apply Hnf in H. inv H.
generalize (preservation x0 y0 T Hhas_type H); intro.
apply IHHmulti in H0. inv H0.
assumption.
assumption.
(*
unfold not in Hnf.
generalize (progress x0 T Hhas_type); intro.
inv H0.
inv H.
inv Hhas_type.
*)
(*
destruct T.
apply canonical_forms_bool in Hhas_type.
inv Hhas_type.
apply Hnot_val. auto.
apply Hnot_val. auto.
destruct x0 eqn:eq.
inv Hhas_type. inv H1.
inv Hhas_type.
apply Hnf. eexists. constructor.
*)
Qed.
(*
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Corollary typable_empty__closed : forall t T,
empty |- t \in T ->
closed t.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
*)
(* ###################################################################### *)
(** * Uniqueness of Types *)
(** **** Exercise: 3 stars (types_unique) *)
(** Another pleasant property of the STLC is that types are
unique: a given term (in a given context) has at most one
type. *)
(** Formalize this statement and prove it. *)
Lemma neq_type_arrow : forall Ta Tb Tc,
TArrow Ta Tb <> TArrow Ta Tc ->
Tb <> Tc.
Proof with eauto.
intros.
unfold not.
intro.
subst.
contradiction H.
reflexivity.
Qed.
(*
Lemma lem : forall Gamma i t t' T,
extend Gamma i t |- t' \in T ->
Gamma |- t' \in T -> False.
*)
Theorem types_unique : forall Gamma t T T',
T <> T' ->
Gamma |- t \in T ->
Gamma |- t \in T' ->
False.
Proof with auto.
(*
intros.
generalize dependent T'.
induction H0; intros.
inv H1. rewrite H in H4. inversion H4. auto.
inv H1. unfold not in H. apply neq_type_arrow in H. apply (IHhas_type T1 H H7).
inv H1.
inv H1. inv H4; inv H0_.
rewrite H0 in H3. inversion H3...
eapply IHhas_type.
*)
intros Gamma t.
induction t; intros; inv H0; inv H1.
rewrite H4 in H3. inversion H3...
generalize (IHt1 (TArrow T11 T) (TArrow T0 T')); intro H9;
exploit H9... unfold not; intros; inversion H0; auto.
apply neq_type_arrow in H.
admit.
(*
apply IHt in H...
destruct t0; inv H7; inv H6. rewrite H2 in H3. inversion H3. contradiction H.
inv H7; inv H6.
rewrite H0 in H3. inversion H3. contradiction H.
*)
auto. auto.
eapply IHt2. eauto. auto. auto.
(*
generalize (substitution_preserves_typing Gamma i t t0 (tvar i) T12); intro T.
exploit T...
apply substitution_preserves_typing with (v:=t0) in H7.
apply IHt in H...
apply IHt1 with (T:=(TArrow T11 T)) in H5. inv H5.
intros.
generalize dependent T'.
induction H0; intros.
: forall (Gamma : partial_map ty) (x : id) (U : ty) (t v : tm) (T : ty),
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T
Lemma substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
empty |- v \in U ->
Gamma |- [x:=v]t \in T.
T_Abs:
forall (Gamma : partial_map ty) (x : id) (T11 T12 : ty) (t12 : tm),
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
*)
Qed.
(* ####################
peeked
https://github.com/panx/SF/blob/master/StlcProp.v
I don't see why only this method works...
########!!!!!!!!!!!!!!!!!! ***********)
Theorem types_unique' : forall Gamma t T,
Gamma |- t \in T ->
forall T', Gamma |- t \in T' ->
T = T'.
Proof with eauto.
intros.
generalize dependent T'.
induction H; intros...; inv H0.
inv H0. rewrite H in H3. inversion H3...
inv H0. apply IHhas_type in H6. subst...
inv H1. apply IHhas_type1 in H5. inversion H5...
inv H0...
inv H0...
inv H2. apply IHhas_type2 in H9...
(*
intros.
generalize dependent T'.
induction H; intros.
inv H0. admit.
apply IHhas_type in H.
induction t; intros;
inv H; inv H0.
admit.
apply IHt1 with (T:=TArrow T0 T') in H4... inversion H4...
*)
Qed.
Theorem types_unique'' : forall Gamma t T,
Gamma |- t \in T ->
forall T', Gamma |- t \in T' ->
T = T'.
Proof with eauto.
intros Gamma t. generalize dependent Gamma.
induction t; intros; inv H; inv H0...
rewrite H3 in H2. inversion H2...
generalize (IHt1 Gamma (TArrow T11 T) H4 (TArrow T0 T') H3); intro. inversion H...
generalize (IHt (extend Gamma i t) T12 H6 T0 H5); intro. inversion H...
Qed.
Theorem types_unique''' : forall Gamma t T T',
T <> T' ->
Gamma |- t \in T ->
Gamma |- t \in T' ->
False.
Proof with eauto.
(* intros. apply (types_unique'' Gamma t T') in H0. auto. auto. *)
intros Gamma t. generalize dependent Gamma.
induction t; intros; inv H0; inv H1...
rewrite H4 in H3. inversion H3...
generalize (IHt1 Gamma (TArrow T11 T) (TArrow T0 T')); intro G; exploit G...
unfold not; intro. inversion H0. rewrite H3 in H...
generalize (IHt (extend Gamma i t) T12 T0); intro G; exploit G...
unfold not; intros. rewrite H0 in H...
Qed.
(* ###################################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 1 star (progress_preservation_statement) *)
(** Without peeking, write down the progress and preservation
theorems for the simply typed lambda-calculus. *)
(*
progress : if some "tm" "has_type", then it is "value" or "step"s to another "tm".
preservation : if some "tm" has "step"ed to another "tm", the latter one has same "ty" with former one.
*)
(*
Ans :
: forall (t : tm) (T : ty),
\empty |- t \in T -> value t \/ (exists t' : tm, t ==> t')
: forall (t t' : tm) (T : ty),
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T
*)
(* above theorems were defiend in only "empty" gamma? *)
(** **** Exercise: 2 stars (stlc_variation1) *)
(** Suppose we add a new term [zap] with the following reduction rule:
--------- (ST_Zap)
t ==> zap
and the following typing rule:
---------------- (T_Zap)
Gamma |- zap : T
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
Module stlc_variation1.
Inductive tm : Type :=
tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| zap : tm.
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
| zap => zap
end
where "'[' x ':=' s ']' t" := (subst x s t).
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Zap : forall t,
t ==> zap
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
| T_Zap : forall Gamma T,
Gamma |- zap \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
Theorem not_step_deterministic:
~(deterministic step).
Proof with eauto.
unfold deterministic, not; intro.
generalize (H (tif ttrue tfalse tfalse) tfalse zap); intro T; exploit T...
intro. inv H0.
Qed.
Theorem progress :
forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t').
Proof with eauto.
induction t; intros...
Qed.
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
(* has_type_cases (induction H) Case; intros; auto. *)
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
Theorem substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T.
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* t_cases (induction t) Case; intros T Gamma H; *)
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T.
Proof with eauto.
(*******!!!!!!!##################
HERE, (remember (empty) as Gamma.) acts as crucial key...
WHY?????????????
*)
intros. generalize dependent t'.
remember (empty) as Gamma.
(* remember (@empty ty) as Gamma. *)
induction H; intros; (* inv H0...; *)
subst Gamma; subst;
(* inv HeqGamma; *)
try solve [inv H0].
inv H0...
inv H0...
inv H1; subst...
(*
: forall (Gamma : partial_map ty) (x : id) (U : ty)
(t v : STLC.tm) (T : ty),
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T
*)
eapply substitution_preserves_typing... inv H...
inv H0...
inv H0...
inv H2...
inv H0...
(*
intros. generalize dependent t'.
induction H; intros...; (* inv H0...; *)
try solve [inv H0...].
inv H0...
inv H0...
admit.
inv H0...
inv H0...
inv H2...
inv H0...
*)
Qed.
(*
remember (@empty ty) as Gamma.
intros t t' T HT. generalize dependent t'.
has_type_cases (induction HT) Case;
intros t' HE; subst Gamma; subst;
try solve [inversion HE; subst; auto].
Case "T_App".
inversion HE; subst...
(* Most of the cases are immediate by induction,
and [eauto] takes care of them *)
SCase "ST_AppAbs".
apply substitution_preserves_typing with T11...
inversion HT1...
*)
(*
Theorem not_preservation :
~(forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T).
Proof with eauto.
unfold not; intro.
generalize (H (tapp (tabs x TBool (tvar x)) ttrue) (*[x := ttrue](tvar x)*)
zap
(* (subst x ttrue (tvar x)) *)
TBool
);
intro T; exploit T.
eapply T_App...
constructor...
intro.
inv H0.
apply T_App with (T11:=TBool).
constructor. constructor. rewrite extend_eq.
generalize (H (tapp (tif ttrue tfalse tfalse) ttrue) (tapp tfalse ttrue)
);
intro T; exploit T.
intro. inv H0.
Qed.
| T_Abs : forall (Gamma : partial_map ty) (x : id)
(T11 T12 : ty) (t12 : tm),
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
value v2 -> tapp (tabs x T t12) v2 ==> [x := v2]t12
*)
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
unfold not in Hnf.
unfold not in Hnot_val.
apply progress in Hhas_type.
inv Hhas_type. apply Hnot_val in H. inv H.
apply Hnf in H. inv H.
generalize (preservation x0 y0 T Hhas_type H); intro.
apply IHHmulti in H0. inv H0.
assumption.
assumption.
Qed.
End stlc_variation1.
(** **** Exercise: 2 stars (stlc_variation2) *)
(** Suppose instead that we add a new term [foo] with the following reduction rules:
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
Module stlc_variation2.
Inductive tm : Type :=
tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm
| foo : tm.
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
| zap => zap
end
where "'[' x ':=' s ']' t" := (subst x s t).
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_Foo1 : forall x A,
(tabs x A (tvar x)) ==> foo
| ST_Foo2 :
foo ==> ttrue
where "t1 '==>' t2" := (step t1 t2).
(*
----------------- (ST_Foo1)
(\x:A. x) ==> foo
------------ (ST_Foo2)
foo ==> true
*)
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
Theorem not_step_deterministic:
~(deterministic step).
Proof with eauto.
unfold deterministic, not; intro.
generalize (H (tapp (tabs x TBool (tvar x)) ttrue) (subst x ttrue (tvar x))); intro T; exploit T...
intro. inv H0.
Qed.
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Theorem progress :
forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t').
Proof with eauto.
induction t; intros; inv H...
inv H2.
generalize H3; intro.
generalize H5; intro.
apply IHt1 in H3.
apply IHt2 in H5.
right.
inv H3; inv H5.
inv H0; inv H...
inv H2. eexists...
inv H. eexists...
inv H. eexists...
right.
generalize H4; intro.
generalize H6; intro.
generalize H7; intro.
apply IHt1 in H4.
apply IHt2 in H6.
apply IHt3 in H7.
inv H4.
apply canonical_forms_bool in H...
inv H; eexists...
inv H; eexists...
Qed.
Theorem not_preservation : ~(forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T).
Proof with eauto.
unfold not; intro.
generalize (H (tabs x TBool (tvar x)) foo); intro T; exploit T.
repeat constructor...
constructor.
intro.
inv H0.
Qed.
End stlc_variation2.
(** **** Exercise: 2 stars (stlc_variation3) *)
(** Suppose instead that we remove the rule [ST_App1] from the [step]
relation. Which of the following properties of the STLC remain
true in the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
Module stlc_variation3.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Theorem step_deterministic :
deterministic step.
Proof with auto.
unfold deterministic.
intros.
generalize dependent y2.
induction H; intros...; inv H0...
inv H0. auto. inv H3. inv H... inv H5... inv H5. inv H5.
inv H1... inv H... inv H5...
inv H0... inv H0. inv H0. apply IHstep in H6. subst...
inv H0... inv H4.
inv H0... inv H4.
inv H0... inv H. inv H. apply IHstep in H5. subst...
Qed.
Theorem not_progress :
~(forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t')).
Proof with eauto.
unfold not; intros.
generalize (H (tapp (tif ttrue (tabs x TBool (tvar x))
(tabs x TBool (tvar x)))
ttrue) TBool); intro T; exploit T...
eapply T_App... constructor...
intro. inv H0. inv H1. inv H1. inv H0. inv H5.
Qed.
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
(* has_type_cases (induction H) Case; intros; auto. *)
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
Theorem substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T.
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* t_cases (induction t) Case; intros T Gamma H; *)
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T.
Proof with eauto.
intros. generalize dependent t'.
remember (empty) as Gamma.
(* remember (@empty ty) as Gamma. *)
induction H; intros; (* inv H0...; *)
subst Gamma; subst;
(* inv HeqGamma; *)
try solve [inv H0].
inv H1...
eapply substitution_preserves_typing... inv H...
inv H2...
Qed.
End stlc_variation3.
(** **** Exercise: 2 stars, optional (stlc_variation4) *)
(** Suppose instead that we add the following new rule to the reduction relation:
---------------------------------- (ST_FunnyIfTrue)
(if true then t1 else t2) ==> true
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
Module stlc_variation4.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
| ST_FunnyIfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> ttrue
(* (if true then t1 else t2) ==> true *)
where "t1 '==>' t2" := (step t1 t2).
Hint Constructors step.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Theorem not_step_deterministic :
not (deterministic step).
Proof with eauto.
unfold deterministic, not; intros.
generalize (H (tif ttrue tfalse tfalse) tfalse ttrue); intro T; exploit T...
intro. inv H0.
Qed.
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Theorem progress :
forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t').
Proof with eauto.
induction t; intros; inv H...
inv H2.
generalize H3; intro.
generalize H5; intro.
apply IHt1 in H3.
apply IHt2 in H5.
right.
inv H3; inv H5.
inv H0; inv H...
inv H2. eexists...
inv H. eexists...
inv H. eexists...
right.
generalize H4; intro.
generalize H6; intro.
generalize H7; intro.
apply IHt1 in H4.
apply IHt2 in H6.
apply IHt3 in H7.
inv H4.
apply canonical_forms_bool in H...
inv H; eexists...
inv H; eexists...
Qed.
Theorem not_preservation : ~(forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T).
Proof with eauto.
unfold not; intro.
generalize (H (tif ttrue
(tabs x TBool (tvar x))
(tabs x TBool (tvar x)))
ttrue
(TArrow TBool TBool)); intro T; exploit T.
repeat constructor. apply ST_FunnyIfTrue.
intro. inv H0.
Qed.
End stlc_variation4.
(** **** Exercise: 2 stars, optional (stlc_variation5) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
Module stlc_variation5.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
| T_FunnyApp : forall Gamma t1 t2,
Gamma |- t1 \in (TArrow (TArrow TBool TBool) TBool) ->
Gamma |- t2 \in TBool ->
Gamma |- (tapp t1 t2) \in TBool
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
(*
Gamma |- t1 \in Bool->Bool->Bool
Gamma |- t2 \in Bool
------------------------------ (T_FunnyApp)
Gamma |- t1 t2 \in Bool
*)
Hint Constructors has_type.
(* determinstic step : not changed *)
(*
Theorem not_progress :
~(forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t')).
Proof with eauto.
unfold not; intros.
generalize (H
(tapp (tabs x (TArrow TBool TBool) (ttrue))
(* (tapp (tvar x) idB) *)
(* ttrue *)
(tif ttrue tfalse tfalse)
)
TBool);
intro T; exploit T.
apply T_FunnyApp...
intro.
inv H0.
inv H1...
inv H1...
inv H0...
inv H6. inv H4. inv H3. inv H5.
ST_AppAbs : forall (x : id) (T : ty) (t12 v2 : tm),
value v2 -> tapp (tabs x T t12) v2 ==> [x := v2]t12
| ST_App1 : forall t1 t1' t2 : tm, t1 ==> t1' -> tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2' : tm,
value v1 -> t2 ==> t2' -> tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2 : tm, tif ttrue t1 t2 ==> t1
Qed.
Gamma |- t1 \in (TArrow (TArrow TBool TBool) TBool) ->
Gamma |- t2 \in TBool ->
Gamma |- (tapp t1 t2) \in TBool
*)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
Theorem progress :
forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t').
Proof with eauto.
induction t; intros; inv H...
inv H2.
generalize H3; intro.
generalize H5; intro.
apply IHt1 in H3.
apply IHt2 in H5.
right.
inv H3; inv H5.
inv H0; inv H...
inv H2. eexists...
inv H. eexists...
inv H. eexists...
right.
generalize H3; intro; apply IHt1 in H3.
generalize H5; intro; apply IHt2 in H5.
inv H3; inv H5.
apply (canonical_forms_fun t1 (TArrow TBool TBool) TBool) in H...
inv H. inv H3.
eexists...
inv H2; eexists...
inv H; eexists...
inv H; eexists...
right.
generalize H4; intro.
generalize H6; intro.
generalize H7; intro.
apply IHt1 in H4.
apply IHt2 in H6.
apply IHt3 in H7.
inv H4.
apply canonical_forms_bool in H...
inv H; eexists...
inv H; eexists...
Qed.
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
(* has_type_cases (induction H) Case; intros; auto. *)
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
Theorem substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T.
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* t_cases (induction t) Case; intros T Gamma H; *)
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Example tmp :
exists t', (tapp (tabs x (TArrow TBool TBool) ((tif ttrue ttrue ttrue)))
(ttrue)) ==> t'.
Proof.
eexists... info_eauto.
Qed.
Example tmp2 :
(tapp (tabs x (TArrow TBool TBool) ((tif ttrue ttrue ttrue)))
(ttrue)) ==> [x := ttrue] (tif ttrue ttrue ttrue).
Proof. info_auto. Qed.
Inductive not_appears_in : id -> tm -> Prop :=
| nai_var : forall x y,
x <> y ->
not_appears_in x (tvar y)
| nai_app : forall x t1 t2,
not_appears_in x t1 ->
not_appears_in x t2 ->
not_appears_in x (tapp t1 t2)
| nai_abs : forall x y T t,
x <> y ->
not_appears_in x t ->
not_appears_in x (tabs y T t)
| nai_if : forall x t1 t2 t3,
not_appears_in x t1 ->
not_appears_in x t2 ->
not_appears_in x t3 ->
not_appears_in x (tif t1 t2 t3).
Hint Constructors not_appears_in.
(*
Ltac neq_eq_id_dec a b H := destruct (eq_id_dec a b); subst. contradiction H.
*)
(*
Ltac find_if_inside :=
match goal with
| [ |- context[if ?X then _ else _] ] => destruct X
end.
*)
(*
Ltac find_neq :=
match goal with
H1: ?E = true |- _ => simpl.
end.
*)
Lemma not_appears_in_subst : forall x s t Gamma T,
not_appears_in x t ->
(Gamma |- [x := s]t \in T <->
Gamma |- t \in T).
Proof with eauto.
induction t; split; intros...
inv H; inv H0...
destruct (eq_id_dec x0 i); subst... contradiction H3... rewrite <- H...
destruct (eq_id_dec x0 i); subst... contradiction H3... rewrite <- H...
destruct (eq_id_dec x0 i); subst... contradiction H3... rewrite <- H...
destruct (eq_id_dec x0 i); subst... contradiction H3... rewrite <- H2...
destruct (eq_id_dec x0 i); subst... contradiction H3... rewrite <- H2...
destruct (eq_id_dec x0 i); subst... contradiction H3... rewrite <- H...
destruct (eq_id_dec x0 i); subst... contradiction H3... rewrite <- H...
inv H; inv H0... unfold subst.
destruct (eq_id_dec x0 i); subst... contradiction H3...
inv H; inv H0...
eapply IHt1 in H4. eapply IHt2 in H5.
apply H4 in H3. apply H5 in H7.
eapply T_App...
eapply IHt1 in H4. eapply IHt2 in H5.
apply H4 in H3. apply H5 in H7.
eapply T_FunnyApp...
inv H; inv H0...
eapply IHt1 in H4. eapply IHt2 in H5.
apply H4 in H3. apply H5 in H7.
simpl. eapply T_App...
eapply IHt1 in H4. eapply IHt2 in H5.
apply H4 in H3. apply H5 in H7.
simpl. eapply T_FunnyApp...
inv H0; inv H.
eapply T_Abs.
destruct (eq_id_dec x0 i); subst...
eapply IHt in H5. apply H5 in H6...
inv H; inv H0...
eapply IHt in H6.
simpl. destruct (eq_id_dec x0 i); subst. contradiction H4...
constructor. apply H6 in H7...
inv H; inv H0... eapply IHt1 in H5. eapply IHt2 in H6. eapply IHt3 in H7.
apply H5 in H4. apply H6 in H9. apply H7 in H10.
constructor...
inv H; inv H0...
eapply IHt1 in H5. apply H5 in H4.
eapply IHt2 in H6. apply H6 in H9.
eapply IHt3 in H7. apply H7 in H10.
simpl. constructor...
Qed.
(*
Lemma not_congruent_implies_not_appears_in : forall t Gamma x s,
Gamma |- s \in TBool ->
Gamma |- tabs x (TArrow TBool TBool) t
\in TArrow (TArrow TBool TBool) TBool ->
not_appears_in x t.
Proof with eauto.
induction t; simpl; intros.
destruct (eq_id_dec x0 i); subst... inv H0. inv H3. rewrite extend_eq in H2. inversion H2.
inv H0; inv H3.
constructor. eapply IHt1... apply T_Abs in H4.
Qed.
*)
Lemma not_congruent_implies_not_appears_in : forall t Gamma x s,
Gamma |- s \in TBool ->
value s ->
tapp (tabs x (TArrow TBool TBool) t) s ==> [x := s] t ->
Gamma |- tabs x (TArrow TBool TBool) t \in TArrow (TArrow TBool TBool) TBool ->
not_appears_in x t.
Proof with eauto.
induction t; simpl; intros.
destruct (eq_id_dec x0 i); subst... inv H2. inv H5. rewrite extend_eq in H4. inversion H4.
constructor. eapply IHt1... inv H2.
Admitted.
(*
t2 : tm
H0 : \empty |- t2 \in TBool
IHhas_type2 : \empty = \empty ->
forall t' : tm, t2 ==> t' -> \empty |- t' \in TBool
x0 : id
t12 : tm
H5 : extend \empty x0 (TArrow TBool TBool) |- t12 \in TBool
IHhas_type1 : \empty = \empty ->
forall t' : tm,
tabs x0 (TArrow TBool TBool) t12 ==> t' ->
\empty |- t' \in TArrow (TArrow TBool TBool) TBool
M : \empty |- tabs x0 (TArrow TBool TBool) t12 \in
TArrow (TArrow TBool TBool) TBool
H7 : value t2
M1 : tapp (tabs x0 (TArrow TBool TBool) t12) t2 ==> [x0 := t2]t12
============================
\empty |- [x0 := t2]t12 \in TBool
*)
(*
t1 : tm
t2 : tm
t' : tm
H1 : tapp t1 t2 ==> t'
H : \empty |- t1 \in TArrow (TArrow TBool TBool) TBool
H0 : \empty |- t2 \in TBool
IHhas_type1 : \empty = \empty ->
forall t'0 : tm,
t1 ==> t'0 ->
\empty |- t'0 \in TArrow (TArrow TBool TBool) TBool
IHhas_type2 : \empty = \empty ->
forall t'0 : tm, t2 ==> t'0 -> \empty |- t'0 \in TBool
M : \empty |- t1 \in TArrow (TArrow TBool TBool) TBool
M1 : tapp t1 t2 ==> t'
============================
\empty |- t' \in TBool
*)
(*
t2 : tm
H0 : \empty |- t2 \in TBool
IHhas_type2 : \empty = \empty ->
forall t' : tm, t2 ==> t' -> \empty |- t' \in TBool
x0 : id
T : ty
t12 : tm
H5 : value t2
H : \empty |- tabs x0 T t12 \in TArrow (TArrow TBool TBool) TBool
IHhas_type1 : \empty = \empty ->
forall t' : tm,
tabs x0 T t12 ==> t' ->
\empty |- t' \in TArrow (TArrow TBool TBool) TBool
============================
\empty |- [x0 := t2]t12 \in TBool
*)
(*
Lemma abnea : forall t1 t2 x Gamma,
Gamma |- t2 \in TBool ->
value t2 ->
Gamma |- tabs x (TArrow TBool TBool) t1 \in TArrow (TArrow TBool TBool) TBool ->
not_appears_in x t1.
Proof with eauto.
induction t1; simpl; intros.
admit.
constructor. eapply IHt1_1... inv H1. inv H4.
Qed.
*)
Theorem preservation : forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T.
Proof with eauto.
intros. generalize dependent t'.
remember (empty) as Gamma.
(* remember (@empty ty) as Gamma. *)
induction H; intros; (* inv H0...; *)
subst Gamma; subst;
(* inv HeqGamma; *)
try solve [inv H0].
inv H1...
eapply substitution_preserves_typing... inv H...
inv H2...
generalize H; intro M.
generalize H1; intro M1.
inv H; inv H1...
assert(G : not_appears_in x0 t12).
apply not_congruent_implies_not_appears_in with (Gamma:=empty) (s:=t2)...
apply not_appears_in_subst...
apply substitution_preserves_typing with (v:=idB) in H5.
apply not_appears_in_subst in H5...
constructor...
(* inv H1... *)
(*
generalize H; intro M.
generalize H1; intro M1.
inv H1... inv H...
apply substitution_preserves_typing with (TBool)...
eapply substitution_preserves_typing...
apply substitution_preserves_typing with (TBool)...
eapply context_invariance. apply H3.
intros. eapply free_in_context in H... inv H.
destruct (eq_id_dec x0 x1); subst. rewrite extend_eq in H1. inv H1.
rewrite extend_eq. rewrite extend_eq.
appears_free_in x t ->
Gamma |- t \in T -> exists T' : ty, Gamma x = Some T'
apply context_invariance with (empty).
eapply substitution_preserves_typing. apply H3.
apply context_invariance with (empty).
inv H1... inv H... eapply substitution_preserves_typing...
generalize (T_FunnyApp empty t1 t2); intro T; exploit T...
intro; clear T.
inv H2... inv H6; inv H... inversion H5.
inv H1... eapply substitution_preserves_typing...
inv H1... inv H1...
(*
inv H1...
| T_FunnyApp : forall (Gamma : context) (t1 t2 : tm),
Gamma |- t1 \in TArrow (TArrow TBool TBool) TBool ->
Gamma |- t2 \in TBool -> Gamma |- tapp t1 t2 \in TBool
eapply T_FunnyApp.
inv H1; inv H; inv H0...
inv H.
eapply substitution_preserves_typing... inv H5.
eapply substitution_preserves_typing...
inv H1... eapply substitution_preserves_typing...
*)
Abort.
*)
Qed.
(*
Theorem not_preservation : ~(forall T t t',
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T).
Proof with eauto.
unfold not; intro.
remember (tapp (tabs x (TArrow TBool TBool) (ttrue))
(tapp (tvar x) ttrue)
) as t.
generalize (H TBool t); intro T; exploit T.
subst. apply T_FunnyApp.
constructor. constructor. constructor. constructor.
constructor.
unfold not; intro.
remember (tapp (tabs x (TArrow TBool TBool) (ttrue))
ttrue
) as t.
generalize (H TBool t); intro T; exploit T.
subst. apply T_FunnyApp...
subst. apply ST_AppAbs...
intro. inv H0.
generalize (H
(tapp (tabs x (TArrow TBool TBool) ((tif ttrue ttrue ttrue)))
(ttrue))
);
intro T; exploit T...
value v2 -> tapp (tabs x T t12) v2 ==> [x := v2]t12
intro. inv H0.
apply T_FunnyApp...
Qed.
*)
End stlc_variation5.
(** **** Exercise: 2 stars, optional (stlc_variation6) *)
(** Suppose instead that we add the following new rule to the typing relation:
Gamma |- t1 \in Bool
Gamma |- t2 \in Bool
--------------------- (T_FunnyApp')
Gamma |- t1 t2 \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
*)
Module stlc_variation6.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
| T_FunnyApp' : forall Gamma t1 t2,
Gamma |- t1 \in TBool->
Gamma |- t2 \in TBool ->
Gamma |- (tapp t1 t2) \in TBool
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* step : same *)
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
Theorem not_progress :
~(forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t')).
Proof.
unfold not; intros.
generalize (H (tapp ttrue ttrue) TBool); intro T; exploit T; auto.
intro. inv H0. inv H1. inv H1. inv H0. inv H4. inv H5.
Qed.
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
(* has_type_cases (induction H) Case; intros; auto. *)
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
Theorem substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T.
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* t_cases (induction t) Case; intros T Gamma H; *)
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T.
Proof with eauto.
intros. generalize dependent t'.
remember (empty) as Gamma.
induction H; intros; subst Gamma; subst;
try solve [inv H0].
inv H1...
eapply substitution_preserves_typing... inv H...
inv H2...
generalize H; intro M.
generalize H1; intro M1.
inv H; inv H1...
Qed.
End stlc_variation6.
(** **** Exercise: 2 stars, optional (stlc_variation7) *)
(** Suppose we add the following new rule to the typing
relation of the STLC:
------------------- (T_FunnyAbs)
|- \x:Bool.t \in Bool
Which of the following properties of the STLC remain true in
the presence of this rule? For each one, write either
"remains true" or else "becomes false." If a property becomes
false, give a counterexample.
- Determinism of [step]
- Progress
- Preservation
[]
*)
Module stlc_variation7.
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
| T_FunnyAbs : forall Gamma x t,
Gamma |- (tabs x TBool t) \in TBool
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
(* step : same *)
(*
Lemma canonical_forms_bool : forall t,
empty |- t \in TBool ->
value t ->
(t = ttrue) \/ (t = tfalse).
Proof.
intros t HT HVal.
inversion HVal; intros; subst; try inversion HT; auto.
Qed.
*)
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
exists x0. exists t0. auto.
Qed.
Theorem progress :
~(forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t')).
Proof.
unfold not; intro.
generalize (H (tif (tabs x TBool ttrue) tfalse tfalse) TBool); intro T; exploit T; auto.
intro. inv H0. inv H1. inv H1. inv H0. inv H5.
Qed.
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif t1 t2 t3)
| afi_if2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif t1 t2 t3)
| afi_if3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif t1 t2 t3).
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
(* has_type_cases (induction H) Case; intros; auto. *)
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x0 x1)...
Case "T_App".
apply T_App with T11...
Qed.
(*
Theorem not_preservation : ~(forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T).
Proof with eauto.
unfold not; intro.
generalize (H
(tif (tif ttrue (tabs x TBool ttrue) tfalse) ttrue ttrue)
(tif (tabs x TBool ttrue) ttrue ttrue)
TBool
);
intro T; exploit T.
apply T_If. apply T_If... constructor. constructor.
repeat constructor.
intro. inv H0. inv H5.
Qed.
Gamma |- tabs x TBool t \in TBool
*)
Lemma free_in_context :
~(forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T').
Proof.
unfold not; intros.
generalize (H y (tabs x TBool (tvar y))
TBool
(extend empty y TBool)
); intro T; exploit T.
constructor. unfold not; intro; inv H0. constructor.
constructor. intro.
inv H0. inv H1.
Abort.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
afi_cases (induction H) Case;
intros; try solve [inversion H0; eauto].
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Abort.
Theorem substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T.
Proof with eauto.
Admitted.
Theorem preservation : forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T.
Proof with eauto.
intros. generalize dependent t'.
remember (empty) as Gamma.
induction H; intros; subst Gamma; subst;
try solve [inv H0].
inv H1...
eapply substitution_preserves_typing... inv H...
inv H2...
Qed.
End stlc_variation7.
End STLCProp.
(* ###################################################################### *)
(* ###################################################################### *)
(** ** Exercise: STLC with Arithmetic *)
(** To see how the STLC might function as the core of a real
programming language, let's extend it with a concrete base
type of numbers and some constants and primitive
operators. *)
Module STLCArith.
(** To types, we add a base type of natural numbers (and remove
booleans, for brevity) *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty.
(** To terms, we add natural number constants, along with
successor, predecessor, multiplication, and zero-testing... *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tnat"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0" ].
(** **** Exercise: 4 stars (stlc_arith) *)
(** Finish formalizing the definition and properties of the STLC extended
with arithmetic. Specifically:
- Copy the whole development of STLC that we went through above (from
the definition of values through the Progress theorem), and
paste it into the file at this point.
- Extend the definitions of the [subst] operation and the [step]
relation to include appropriate clauses for the arithmetic operators.
- Extend the proofs of all the properties (up to [soundness]) of
the original STLC to deal with the new syntactic forms. Make
sure Coq accepts the whole file. *)
(* FILL IN HERE *)
(** [] *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| tnat n =>
tnat n
| tsucc t =>
tsucc ([x:=s] t)
| tpred t =>
tpred ([x:=s] t)
| tmult t1 t2 =>
tmult ([x:=s] t1) ([x:=s] t2)
| tif0 t1 t2 t3 =>
tif0 ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_nat : forall n,
value (tnat n).
(*
nv_zero : nvalue tzero
| nv_succ : forall t : Types.tm, nvalue t -> nvalue (Types.tsucc t)
*)
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif0 (tnat 0) t1 t2) ==> t1
| ST_IfFalse : forall t1 t2 n,
(tif0 (tnat (S n)) t1 t2) ==> t1
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif0 t1 t2 t3) ==> (tif0 t1' t2 t3)
| ST_Succ : forall t t',
t ==> t' ->
tsucc t ==> tsucc t'
| ST_Pred : forall t t',
t ==> t' ->
tpred t ==> tpred t'
| ST_Mult1 : forall t1 t1' t2,
t1 ==> t1' ->
tmult t1 t2 ==> tmult t1' t2
| ST_Mult2 : forall t1 t2 t2',
value t1 ->
t2 ==> t2' ->
tmult t1 t2 ==> tmult t1 t2'
| ST_NatSucc : forall n,
tsucc (tnat n) ==> (tnat (S n))
| ST_NatPredZero :
tpred (tnat 0) ==> (tnat 0)
| ST_NatPred : forall n,
tpred (tnat (S n)) ==> (tnat n)
| ST_NatMult : forall n m,
tmult (tnat n) (tnat m) ==> (tnat (mult n m))
(*
| ST_NatPredSucc : forall n,
tpred (tsucc (tnat n)) ==> (tnat n)
*)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2"
| Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse"
| Case_aux c "ST_If"
| Case_aux c "ST_Succ"
| Case_aux c "ST_Pred"
| Case_aux c "ST_Mult1"
| Case_aux c "ST_Mult2"
| Case_aux c "ST_NatSucc"
| Case_aux c "ST_NatPredZero"
| Case_aux c "ST_NatPred"
| Case_aux c "ST_NatMult"
(* | Case_aux c "ST_NatPredSucc" *)
].
Hint Constructors step.
Theorem step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
intros.
generalize dependent y2.
step_cases (induction H) Case; intros...; inv H0...
(* induction H; intros...; inv H0... *)
Case "ST_AppAbs".
inv H0... inv H4... inv H3.
inv H; inv H5...
Case "ST_App1".
inv H0... inv H... apply IHstep in H4; subst...
inv H; inv H3...
Case "ST_App2".
inv H1... inv H5; inv H... inv H0. inv H0. inv H; inv H5...
apply IHstep in H6; subst...
Case "ST_IfTrue".
inv H0... inv H4...
Case "ST_IfFalse".
inv H0... inv H4...
Case "ST_If".
inv H0... inv H... inv H. apply IHstep in H5; subst...
Case "ST_Succ".
inv H0... apply IHstep in H2; subst... inv H.
Case "ST_Pred".
inv H0... apply IHstep in H2; subst...
inv H. inv H.
Case "ST_Mult1".
inv H0... apply IHstep in H4; subst... inv H3; inv H...
inv H...
Case "ST_Mult2".
inv H1... inv H; inv H5. apply IHstep in H6; subst...
inv H0...
Case "ST_NatSucc".
inv H0... inv H1. inv H0... inv H1.
Case "ST_NatPred".
inv H0... inv H1...
Case "ST_NatMult".
inv H0... inv H3. inv H4.
Qed.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Definition context := partial_map ty.
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_Nat : forall Gamma n,
Gamma |- (tnat n) \in TNat
| T_If0 : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif0 t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_If0"
| Case_aux c "T_Nat"
].
Hint Constructors has_type.
Lemma canonical_forms_nat : forall t,
empty |- t \in TNat ->
value t ->
exists n, t = tnat n.
Proof with eauto.
intros t HT HVal.
inv HVal. inv HT. eexists...
Qed.
Lemma canonical_forms_fun : forall t T1 T2,
empty |- t \in (TArrow T1 T2) ->
value t ->
exists x u, t = tabs x T1 u.
Proof.
intros t T1 T2 HT HVal.
inversion HVal; intros; subst; try inversion HT; subst; auto.
inv HT...
exists x. exists t0. auto.
Qed.
Theorem progress :
forall t T,
\empty |- t \in T ->
value t \/ (exists t', t ==> t').
Proof with eauto.
intros t.
t_cases (induction t) Case; intros T Ht; auto.
inv Ht. inversion H1.
inv Ht.
generalize H2; intro H1.
generalize H4; intro H3.
apply IHt1 in H2.
apply IHt2 in H4.
right.
inv H4. inv H2.
inv H1; inv H0.
eexists. (*using it to early, right after right, will make next line not work *)
apply ST_AppAbs...
inv H0. eexists. apply ST_App1...
inv H2. inv H. eexists. apply ST_App2...
inv H. inv H0. eexists. apply ST_App1...
inv Ht.
inv Ht.
inv Ht.
inv Ht. generalize H3; intro T1. apply IHt1 in H3. right. inv H3.
apply canonical_forms_nat in T1. inv T1. eexists... destruct x...
assumption. inv H. eexists...
Qed.
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_if0_1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_tsucc : forall x t,
appears_free_in x t ->
appears_free_in x (tsucc t)
| afi_tpred : forall x t,
appears_free_in x t ->
appears_free_in x (tpred t)
| afi_tmult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_tmult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t T,
Gamma |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros; auto.
(* has_type_cases (induction H) Case; intros; auto. *)
Case "T_Var".
apply T_Var. rewrite <- H0...
Case "T_Abs".
apply T_Abs.
apply IHhas_type. intros x1 Hafi.
(* the only tricky step... the [Gamma'] we use to
instantiate is [extend Gamma x T11] *)
unfold extend. destruct (eq_id_dec x x1)...
Case "T_App".
apply T_App with T11...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof.
intros x t T Gamma H H0. generalize dependent Gamma.
generalize dependent T.
induction H;
intros; try solve [inversion H0; eauto].
inversion H1; subst.
apply IHappears_free_in in H7.
rewrite extend_neq in H7; assumption.
Qed.
Theorem substitution_preserves_typing : forall Gamma x U t v T,
extend Gamma x U |- t \in T ->
\empty |- v \in U -> Gamma |- [x := v]t \in T.
Proof with eauto.
intros Gamma x U t v T Ht Ht'.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
(* t_cases (induction t) Case; intros T Gamma H; *)
(* in each case, we'll want to get at the derivation of H *)
inversion H; subst; simpl...
Case "tvar".
rename i into y. destruct (eq_id_dec x y).
SCase "x=y".
subst.
rewrite extend_eq in H2.
inversion H2; subst. clear H2.
eapply context_invariance... intros x Hcontra.
destruct (free_in_context _ _ T empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
apply T_Var. rewrite extend_neq in H2...
Case "tabs".
rename i into y. apply T_Abs.
destruct (eq_id_dec x y).
SCase "x=y".
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
\empty |- t \in T -> t ==> t' -> \empty |- t' \in T.
Proof with eauto.
intros; generalize dependent t'.
remember empty as Gamma.
induction H; intros; subst; try solve [inv H0].
inv H1... eapply substitution_preserves_typing. inv H...
inv H...
inv H2...
Qed.
Definition stuck (t:tm) : Prop :=
(normal_form step) t /\ ~ value t.
Corollary soundness : forall t t' T,
empty |- t \in T ->
t ==>* t' ->
~(stuck t').
Proof.
intros t t' T Hhas_type Hmulti. unfold stuck.
intros [Hnf Hnot_val]. unfold normal_form in Hnf.
induction Hmulti.
unfold not in Hnf.
unfold not in Hnot_val.
apply progress in Hhas_type.
inv Hhas_type. apply Hnot_val in H. inv H.
apply Hnf in H. inv H.
generalize (preservation x y T Hhas_type H); intro.
apply IHHmulti in H0. inv H0.
assumption.
assumption.
Qed.
End STLCArith.
(* $Date: 2014-04-23 09:37:37 -0400 (Wed, 23 Apr 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_2_V
`define SKY130_FD_SC_MS__A221OI_2_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a221oi_2 (
Y ,
A1,
A2,
B1,
B2,
C1
);
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a221oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_12_V
`define SKY130_FD_SC_HD__BUF_12_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 12 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_12 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_12 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_12_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_SYMBOL_V
`define SKY130_FD_SC_LS__AND2_SYMBOL_V
/**
* and2: 2-input AND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV5SD3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV5SD3_FUNCTIONAL_PP_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV5SD3_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__INV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__INV_FUNCTIONAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__INV_FUNCTIONAL_PP_V |
`define CONTROL_SIGNAL {RegDst, RegWrite, ALUSrc, MemRead, MemWrite, MemtoReg, Jump, Branch, Equal, JumpLink}
module Single_Cycle_CPU(
input clk_in,
input btn_t,
input [7:0]sw,
output [6:0]seg,
output [3:0]an
);
wire [31:0]pc_now, inst, read_data_1, read_data_2, debug_output, alu_output, pc_t1, pc_t2, imm, memory_out;
wire [31:0]mux_out_2, mux_out_3, mux_out_5, mux_out_6, mux_out_7;
wire [4:0] mux_out_1;
wire [1:0] RegDst, Jump;
wire btn, clk_100M, RegWrite, ALUSrc, MemRead, MemtoReg, MemWrite, JumpReg, Branch, Equal, JumpLink, zero, mux_out_4;
wire [3:0]ALUCtrl;
reg clk_50M;
wire clk_25M;
reg [15:0] disp_num;
reg [31:0] display_num, counter;
always @(posedge clk_in) counter = counter + 1'b1;
assign clk_100M = clk_in;
initial begin
// clk_50M <= 0;
// clk_25M <= 0;
end
//always @(posedge clk_in) begin
// clk_50M <= ~clk_50M;
//end
// always @(posedge clk_50M) begin
// clk_25M <= ~clk_25M;
// end
assign clk_25M = counter[25];
program_counter M0(
.clk(clk_25M),
.pc_next(mux_out_6),
.pc_now(pc_now)
);
ROM_A M1(
.addr({2'b00, pc_now[31:2]}),
.inst(inst)
);
control M2(
.op(inst[31:26]),
.funct(inst[5:0]),
.RegDst(RegDst),
.RegWrite(RegWrite),
.ALUSrc(ALUSrc),
.MemRead(MemRead),
.MemWrite(MemWrite),
.MemtoReg(MemtoReg),
.Jump(Jump),
.Branch(Branch),
.Equal(Equal),
.JumpLink(JumpLink),
.ALUCtrl(ALUCtrl)
);
register_file M3(
.clk(clk_25M),
.read_register_1(inst[25:21]),
.read_register_2(inst[20:16]),
.write_register(mux_out_1),
.debug_input(sw[4:0]),
.write_data(mux_out_7),
.RegWrite(RegWrite),
.read_data_1(read_data_1),
.read_data_2(read_data_2),
.debug_output(debug_output)
);
alu M4(
.alu_ctl(ALUCtrl),
.A(read_data_1),
.B(mux_out_2),
.zero(zero),
.result(alu_output)
);
adder M5(
.A(pc_now),
.B(32'd4),
.result(pc_t1)
);
adder M6(
.A(pc_t1),
.B({imm[29:0], 2'b00}),
.result(pc_t2)
);
sign_extend M7(
.imm_number(inst[15:0]),
.extended_number(imm)
);
RAM_A M8(
.clk(clk_100M),
.a({2'b00, alu_output[31:2]}),
.d(read_data_2),
.we(MemWrite),
.spo(memory_out)
);
always @(*) begin
case (sw[7:6])
2'b01: display_num <= pc_now;
2'b10: display_num <= inst;
2'b11: display_num <= 32'hFFFFFFFF;
default: display_num <= debug_output;
endcase
end
always @(*) begin
if (sw[5]) begin
disp_num <= display_num[31:16];
end else begin
disp_num <= display_num[15:0];
end
end
display M9(
.clk(clk_100M),
.disp_num(disp_num),
.seg(seg),
.anode(an)
);
mux_4_to_1_5 U1(
.A(inst[20:16]),
.B(inst[15:11]),
.C(5'd31),
.D(5'b0),
.enable(RegDst),
.O(mux_out_1)
);
mux_2_to_1_32 U2(
.A(read_data_2),
.B(imm),
.enable(ALUSrc),
.O(mux_out_2)
);
mux_2_to_1_32 U3(
.A(alu_output),
.B(memory_out),
.enable(MemtoReg),
.O(mux_out_3)
);
mux_2_to_1_1 U4(
.A(zero),
.B(~zero),
.enable(Equal),
.O(mux_out_4)
);
mux_2_to_1_32 U5(
.A(pc_t1),
.B(pc_t2),
.enable(Branch & mux_out_4),
.O(mux_out_5)
);
mux_4_to_1_32 U6(
.A(mux_out_5),
.B({pc_t1[31:28],inst[25:0], 2'b00}),
.C(read_data_1),
.D(32'b0),
.enable(Jump),
.O(mux_out_6)
);
mux_2_to_1_32 U7(
.A(mux_out_3),
.B(pc_t1),
.enable(JumpLink),
.O(mux_out_7)
);
glitch_filter U8(
.clk(clk_100M),
.key_in(btn_t),
.key_out(btn)
);
endmodule
module glitch_filter(
input clk, key_in,
output key_out
);
reg [21:0] count_low;
reg [21:0] count_high;
reg key_out_reg;
always @(posedge clk)
if(key_in ==1'b0)
count_low <= count_low + 1;
else
count_low <= 0;
always @(posedge clk)
if(key_in ==1'b1)
count_high <= count_high + 1;
else
count_high <= 0;
always @(posedge clk)
if(count_high == 4)
key_out_reg <= 1;
else if(count_low == 4)
key_out_reg <= 0;
assign key_out = key_out_reg;
endmodule
module mux_2_to_1_1(
input A,B,
input enable,
output reg O
);
always @* begin
if (enable) O <= B;
else O <= A;
end
endmodule
module mux_2_to_1_5(
input [4:0] A,B,
input enable,
output reg[4:0] O
);
always @* begin
if (enable) O <= B;
else O <= A;
end
endmodule
module mux_4_to_1_5(
input [4:0] A,B,C,D,
input [1:0] enable,
output reg[4:0] O
);
always @* begin
case (enable)
2'b00 : begin
O <= A;
end
2'b01 : begin
O <= B;
end
2'b10 : begin
O <= C;
end
2'b11 : begin
O <= D;
end
endcase
end
endmodule
module mux_2_to_1_32(
input [31:0] A,B,
input enable,
output reg[31:0] O
);
always @* begin
if (enable) O <= B;
else O <= A;
end
endmodule
module mux_4_to_1_32(
input [31:0] A,B,C,D,
input [1:0] enable,
output reg[31:0] O
);
always @* begin
case (enable)
2'b00 : begin
O <= A;
end
2'b01 : begin
O <= B;
end
2'b10 : begin
O <= C;
end
2'b11 : begin
O <= D;
end
endcase
end
endmodule
module ROM_A(
input [31:0] addr,
output [31:0] inst
);
reg [31:0]instructions[128:0];
initial begin
instructions[0] = 32'h00000026;
instructions[1] = 32'h00210826;
instructions[2] = 32'h00421026;
instructions[3] = 32'h00631826;
instructions[4] = 32'h00842026;
instructions[5] = 32'h00a52826;
instructions[6] = 32'h00c63026;
instructions[7] = 32'h00e73826;
instructions[8] = 32'h01084026;
instructions[9] = 32'h01294826;
instructions[10] = 32'h014a5026;
instructions[11] = 32'h016b5826;
instructions[12] = 32'h018c6026;
instructions[13] = 32'h01ad6826;
instructions[14] = 32'h01ce7026;
instructions[15] = 32'h01ef7826;
instructions[16] = 32'h02108026;
instructions[17] = 32'h02318826;
instructions[18] = 32'h02529026;
instructions[19] = 32'h02739826;
instructions[20] = 32'h0294a026;
instructions[21] = 32'h02b5a826;
instructions[22] = 32'h02d6b026;
instructions[23] = 32'h02f7b826;
instructions[24] = 32'h0318c026;
instructions[25] = 32'h0339c826;
instructions[26] = 32'h035ad026;
instructions[27] = 32'h037bd826;
instructions[28] = 32'h039ce026;
instructions[29] = 32'h03bde826;
instructions[30] = 32'h03def026;
instructions[31] = 32'h03fff826;
instructions[32] = 32'h2108000a;
instructions[33] = 32'h21290001;
instructions[34] = 32'h214a0002;
instructions[35] = 32'h216b0003;
instructions[36] = 32'h218c0004;
instructions[37] = 32'h21ad000a;
instructions[38] = 32'h21ce000a;
instructions[39] = 32'h21ef000a;
instructions[40] = 32'h00892020;
instructions[41] = 32'h00aa2820;
instructions[42] = 32'h00cb3020;
instructions[43] = 32'h00ec3820;
instructions[44] = 32'h1488fffb;
instructions[45] = 32'h22100001;
instructions[46] = 32'h3c088000;
instructions[47] = 32'h00008827;
instructions[48] = 32'h00084042;
instructions[49] = 32'h02119024;
instructions[50] = 32'h01119825;
instructions[51] = 32'h0111a026;
instructions[52] = 32'h1408fffb;
instructions[53] = 32'h3c1500ff;
instructions[54] = 32'h22b500ff;
instructions[55] = 32'hac150320;
instructions[56] = 32'h8c160320;
instructions[57] = 32'h12b60000;
instructions[58] = 32'h00892022;
instructions[59] = 32'h00aa2822;
instructions[60] = 32'h00cb3022;
instructions[61] = 32'h00ec3822;
instructions[62] = 32'h00c0402a;
instructions[63] = 32'h1008fffa;
instructions[64] = 32'h0c000042;
instructions[65] = 32'h08000000;
instructions[66] = 32'h03e00008;
end
assign inst = instructions[addr];
endmodule
module register_file(
input clk,
input [4:0]read_register_1,
input [4:0]read_register_2,
input [4:0]write_register,
input [4:0]debug_input,
input [31:0]write_data,
input RegWrite,
output [31:0]read_data_1,
output [31:0]read_data_2,
output [31:0]debug_output
);
reg [31:0]registers[31:0];
initial begin
registers[0] = 32'h0;
registers[1] = 32'h0;
registers[2] = 32'h0;
registers[3] = 32'h0;
registers[4] = 32'h0;
registers[5] = 32'h0;
registers[6] = 32'h0;
registers[7] = 32'h0;
registers[8] = 32'h0;
registers[9] = 32'h0;
registers[10] = 32'h0;
registers[11] = 32'h0;
registers[12] = 32'h0;
registers[13] = 32'h0;
registers[14] = 32'h0;
registers[15] = 32'h0;
registers[16] = 32'h0;
registers[17] = 32'h0;
registers[18] = 32'h0;
registers[19] = 32'h0;
registers[20] = 32'h0;
registers[21] = 32'h0;
registers[22] = 32'h0;
registers[23] = 32'h0;
registers[24] = 32'h0;
registers[25] = 32'h0;
registers[26] = 32'h0;
registers[27] = 32'h0;
registers[28] = 32'h0;
registers[29] = 32'h0;
registers[30] = 32'h0;
registers[31] = 32'h0;
end
assign debug_output = registers[debug_input];
assign read_data_1 = registers[read_register_1];
assign read_data_2 = registers[read_register_2];
always @(posedge clk) begin
if (RegWrite) begin
registers[write_register] = write_data;
end
end
endmodule
module sign_extend(
input [15:0]imm_number,
output [31:0]extended_number
);
assign extended_number = {{16{imm_number[15]}}, imm_number};
endmodule
module adder(
input [31:0]A, B,
output [31:0]result
);
assign result = A + B;
endmodule
module alu(
input [3:0]alu_ctl,
input signed [31:0]A, B,
output zero,
output reg [31:0]result
);
assign zero = (result == 0);
always @* begin
case (alu_ctl)
4'b0001 : result <= A + B;
4'b0010 : result <= A - B;
4'b0011 : result <= A & B;
4'b0100 : result <= A | B;
4'b0101 : result <= A ^ B;
4'b0110 : result <= ~(A | B);
4'b0111 : result <= B >> 1;
4'b1000 : result <= {B[15:0], 16'b0};
4'b1001 : result <= (A < B);
default : result <= 0;
endcase
end
endmodule
module program_counter(
input clk,
input [31:0]pc_next,
output reg [31:0]pc_now
);
initial begin
pc_now <= 0;
end
always @(posedge clk) begin
pc_now <= pc_next;
end
endmodule
module control(
input [5:0]op,
input [5:0]funct,
output reg [1:0]RegDst,
output reg RegWrite,
output reg ALUSrc,
output reg MemRead,
output reg MemWrite,
output reg MemtoReg,
output reg [1:0]Jump,
output reg Branch,
output reg Equal,
output reg JumpLink,
output reg [3:0]ALUCtrl
);
// RegDst 0 : select from rt, 1 : select from rd
// RegWrite 0 : None, 1 : Write data into register file
// ALUSrc 0 : the second operand of ALU come from register file, 1 : come
// from immediate number.
// MemRead read data out from memory.
// MemWrite write data into memory
// MemtoReg output of memory write into registe file
always @* begin
case(op)
6'h08 : begin //addi
`CONTROL_SIGNAL <= 12'b0011000000X0;
ALUCtrl <= 4'b0001; // add
end
6'h0C : begin //andi
`CONTROL_SIGNAL <= 12'b0011000000X0;
ALUCtrl <= 4'b0011; // and
end
6'h0D : begin //ori
`CONTROL_SIGNAL <= 12'b0011000000X0;
ALUCtrl <= 4'b0100; // or
end
6'h0E : begin //xori
`CONTROL_SIGNAL <= 12'b0011000000X0;
ALUCtrl <= 4'b0101; // xor
end
6'h0F : begin //lui
`CONTROL_SIGNAL <= 12'b0011000000X0;
ALUCtrl <= 4'b1000; // lui
end
6'h23 : begin //lw
`CONTROL_SIGNAL <= 12'b0011101000X0;
ALUCtrl <= 4'b0001; // add
end
6'h2B : begin //sw
`CONTROL_SIGNAL <= 12'bXX01011000X0;
ALUCtrl <= 4'b0001; // add
end
6'h04 : begin //beq
`CONTROL_SIGNAL <= 12'b000000000100;
ALUCtrl <= 4'b0010; // sub
end
6'h05 : begin //bne
`CONTROL_SIGNAL <= 12'b000000000110;
ALUCtrl <= 4'b0010; // sub
end
6'h0A : begin //slti
`CONTROL_SIGNAL <= 12'b0011000000X0;
ALUCtrl <= 4'b1001; // slt
end
6'h02 : begin //j
`CONTROL_SIGNAL <= 12'bXX0X000010X0;
ALUCtrl <= 4'b0000;
end
6'h03 : begin //jal
`CONTROL_SIGNAL <= 12'b101X000010X1;
ALUCtrl <= 4'b0000;
end
6'h00 : //R-Type
case(funct)
6'd32 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b0001; // add
end
6'd34 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b0010; // sub
end
6'd36 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b0011; // and
end
6'd37 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b0100; // or
end
6'd38 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b0101; // xor
end
6'd39 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b0110; // nor
end
6'd42 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b1001; // slt
end
6'd02 : begin
`CONTROL_SIGNAL <= 12'b0110000000X0;
ALUCtrl <= 4'b0111; // srl
end
6'd08 : begin // jr
`CONTROL_SIGNAL <= 12'b000000010XX0;
ALUCtrl <= 4'b0000;
end
6'd09 : begin // jalr
`CONTROL_SIGNAL <= 12'b011000010XX1;
ALUCtrl <= 4'b0000;
end
default : begin
`CONTROL_SIGNAL <= 12'b0;
ALUCtrl <= 4'b0; // xor
end
endcase
default : begin
`CONTROL_SIGNAL <= 12'b0;
ALUCtrl <= 4'b0; // xor
end
endcase
end
endmodule
module display(
input clk,
input [15:0]disp_num,
output reg [6:0]seg,
output reg [3:0]anode
);
reg [26:0]tick;
reg [1:0]an;
reg [3:0]num;
reg t;
initial begin
an <= 2'b00;
tick <= 0;
end
always @(posedge clk)
tick = tick+1;
always @(posedge tick[16])
an = an + 1;
always @(an) begin
anode <= ~(4'b1<<an);
case(an)
2'b00: num = disp_num[3:0];
2'b01: num = disp_num[7:4];
2'b10: num = disp_num[11:8];
2'b11: num = disp_num[15:12];
default:;
endcase
end
always @(anode or num) begin
case(num)
4'h0 : seg[6:0] = 7'b1000000;
4'h1 : seg[6:0] = 7'b1111001;
4'h2 : seg[6:0] = 7'b0100100;
4'h3 : seg[6:0] = 7'b0110000;
4'h4 : seg[6:0] = 7'b0011001;
4'h5 : seg[6:0] = 7'b0010010;
4'h6 : seg[6:0] = 7'b0000010;
4'h7 : seg[6:0] = 7'b1111000;
4'h8 : seg[6:0] = 7'b0000000;
4'h9 : seg[6:0] = 7'b0010000;
4'hA : seg[6:0] = 7'b0001000;
4'hB : seg[6:0] = 7'b0000011;
4'hC : seg[6:0] = 7'b1000110;
4'hD : seg[6:0] = 7'b0100001;
4'hE : seg[6:0] = 7'b0000110;
default : seg[6:0] = 7'b0001110;
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Oct 18 10:48:44 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ srio_gen2_0_stub.v
// Design : srio_gen2_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "srio_gen2_v4_0_5,Vivado 2015.1.0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(sys_clkp, sys_clkn, sys_rst, log_clk_out,
phy_clk_out, gt_clk_out, gt_pcs_clk_out, drpclk_out, refclk_out, clk_lock_out, cfg_rst_out,
log_rst_out, buf_rst_out, phy_rst_out, gt_pcs_rst_out, gt0_qpll_clk_out,
gt0_qpll_out_refclk_out, srio_rxn0, srio_rxp0, srio_rxn1, srio_rxp1, srio_txn0, srio_txp0,
srio_txn1, srio_txp1, s_axis_iotx_tvalid, s_axis_iotx_tready, s_axis_iotx_tlast,
s_axis_iotx_tdata, s_axis_iotx_tkeep, s_axis_iotx_tuser, m_axis_iorx_tvalid,
m_axis_iorx_tready, m_axis_iorx_tlast, m_axis_iorx_tdata, m_axis_iorx_tkeep,
m_axis_iorx_tuser, s_axi_maintr_rst, s_axi_maintr_awvalid, s_axi_maintr_awready,
s_axi_maintr_awaddr, s_axi_maintr_wvalid, s_axi_maintr_wready, s_axi_maintr_wdata,
s_axi_maintr_bvalid, s_axi_maintr_bready, s_axi_maintr_bresp, s_axi_maintr_arvalid,
s_axi_maintr_arready, s_axi_maintr_araddr, s_axi_maintr_rvalid, s_axi_maintr_rready,
s_axi_maintr_rdata, s_axi_maintr_rresp, sim_train_en, force_reinit, phy_mce,
phy_link_reset, phy_rcvd_mce, phy_rcvd_link_reset, phy_debug, gtrx_disperr_or,
gtrx_notintable_or, port_error, port_timeout, srio_host, port_decode_error, deviceid,
idle2_selected, phy_lcl_master_enable_out, buf_lcl_response_only_out,
buf_lcl_tx_flow_control_out, buf_lcl_phy_buf_stat_out, phy_lcl_phy_next_fm_out,
phy_lcl_phy_last_ack_out, phy_lcl_phy_rewind_out, phy_lcl_phy_rcvd_buf_stat_out,
phy_lcl_maint_only_out, port_initialized, link_initialized, idle_selected, mode_1x)
/* synthesis syn_black_box black_box_pad_pin="sys_clkp,sys_clkn,sys_rst,log_clk_out,phy_clk_out,gt_clk_out,gt_pcs_clk_out,drpclk_out,refclk_out,clk_lock_out,cfg_rst_out,log_rst_out,buf_rst_out,phy_rst_out,gt_pcs_rst_out,gt0_qpll_clk_out,gt0_qpll_out_refclk_out,srio_rxn0,srio_rxp0,srio_rxn1,srio_rxp1,srio_txn0,srio_txp0,srio_txn1,srio_txp1,s_axis_iotx_tvalid,s_axis_iotx_tready,s_axis_iotx_tlast,s_axis_iotx_tdata[63:0],s_axis_iotx_tkeep[7:0],s_axis_iotx_tuser[31:0],m_axis_iorx_tvalid,m_axis_iorx_tready,m_axis_iorx_tlast,m_axis_iorx_tdata[63:0],m_axis_iorx_tkeep[7:0],m_axis_iorx_tuser[31:0],s_axi_maintr_rst,s_axi_maintr_awvalid,s_axi_maintr_awready,s_axi_maintr_awaddr[31:0],s_axi_maintr_wvalid,s_axi_maintr_wready,s_axi_maintr_wdata[31:0],s_axi_maintr_bvalid,s_axi_maintr_bready,s_axi_maintr_bresp[1:0],s_axi_maintr_arvalid,s_axi_maintr_arready,s_axi_maintr_araddr[31:0],s_axi_maintr_rvalid,s_axi_maintr_rready,s_axi_maintr_rdata[31:0],s_axi_maintr_rresp[1:0],sim_train_en,force_reinit,phy_mce,phy_link_reset,phy_rcvd_mce,phy_rcvd_link_reset,phy_debug[223:0],gtrx_disperr_or,gtrx_notintable_or,port_error,port_timeout[23:0],srio_host,port_decode_error,deviceid[15:0],idle2_selected,phy_lcl_master_enable_out,buf_lcl_response_only_out,buf_lcl_tx_flow_control_out,buf_lcl_phy_buf_stat_out[5:0],phy_lcl_phy_next_fm_out[5:0],phy_lcl_phy_last_ack_out[5:0],phy_lcl_phy_rewind_out,phy_lcl_phy_rcvd_buf_stat_out[5:0],phy_lcl_maint_only_out,port_initialized,link_initialized,idle_selected,mode_1x" */;
input sys_clkp;
input sys_clkn;
input sys_rst;
output log_clk_out;
output phy_clk_out;
output gt_clk_out;
output gt_pcs_clk_out;
output drpclk_out;
output refclk_out;
output clk_lock_out;
output cfg_rst_out;
output log_rst_out;
output buf_rst_out;
output phy_rst_out;
output gt_pcs_rst_out;
output gt0_qpll_clk_out;
output gt0_qpll_out_refclk_out;
input srio_rxn0;
input srio_rxp0;
input srio_rxn1;
input srio_rxp1;
output srio_txn0;
output srio_txp0;
output srio_txn1;
output srio_txp1;
input s_axis_iotx_tvalid;
output s_axis_iotx_tready;
input s_axis_iotx_tlast;
input [63:0]s_axis_iotx_tdata;
input [7:0]s_axis_iotx_tkeep;
input [31:0]s_axis_iotx_tuser;
output m_axis_iorx_tvalid;
input m_axis_iorx_tready;
output m_axis_iorx_tlast;
output [63:0]m_axis_iorx_tdata;
output [7:0]m_axis_iorx_tkeep;
output [31:0]m_axis_iorx_tuser;
input s_axi_maintr_rst;
input s_axi_maintr_awvalid;
output s_axi_maintr_awready;
input [31:0]s_axi_maintr_awaddr;
input s_axi_maintr_wvalid;
output s_axi_maintr_wready;
input [31:0]s_axi_maintr_wdata;
output s_axi_maintr_bvalid;
input s_axi_maintr_bready;
output [1:0]s_axi_maintr_bresp;
input s_axi_maintr_arvalid;
output s_axi_maintr_arready;
input [31:0]s_axi_maintr_araddr;
output s_axi_maintr_rvalid;
input s_axi_maintr_rready;
output [31:0]s_axi_maintr_rdata;
output [1:0]s_axi_maintr_rresp;
input sim_train_en;
input force_reinit;
input phy_mce;
input phy_link_reset;
output phy_rcvd_mce;
output phy_rcvd_link_reset;
output [223:0]phy_debug;
output gtrx_disperr_or;
output gtrx_notintable_or;
output port_error;
output [23:0]port_timeout;
output srio_host;
output port_decode_error;
output [15:0]deviceid;
output idle2_selected;
output phy_lcl_master_enable_out;
output buf_lcl_response_only_out;
output buf_lcl_tx_flow_control_out;
output [5:0]buf_lcl_phy_buf_stat_out;
output [5:0]phy_lcl_phy_next_fm_out;
output [5:0]phy_lcl_phy_last_ack_out;
output phy_lcl_phy_rewind_out;
output [5:0]phy_lcl_phy_rcvd_buf_stat_out;
output phy_lcl_maint_only_out;
output port_initialized;
output link_initialized;
output idle_selected;
output mode_1x;
endmodule
|
module afifo(
din,
wr_en,
wr_clk,
rd_en,
rd_clk,
ainit,
dout,
full,
almost_full,
empty,
wr_count,
rd_count,
rd_ack,
wr_ack);
//////////////////////////////////////////////////////
parameter DATA_WIDTH =16;
parameter ADDR_WIDTH =8;
parameter COUNT_DATA_WIDTH =8;
parameter ALMOST_FULL_DEPTH =8;
//////////////////////////////////////////////////////
input [DATA_WIDTH-1:0] din;
input wr_en;
input wr_clk;
input rd_en;
input rd_clk;
input ainit;
output [DATA_WIDTH-1:0] dout;
output full;
output almost_full;
output empty;
output [COUNT_DATA_WIDTH-1:0] wr_count /* synthesis syn_keep=1 */;
output [COUNT_DATA_WIDTH-1:0] rd_count /* synthesis syn_keep=1 */;
output rd_ack;
output wr_ack;
//////////////////////////////////////////////////////
//local signals
//////////////////////////////////////////////////////
reg [ADDR_WIDTH-1:0] Add_wr;
reg [ADDR_WIDTH-1:0] Add_wr_ungray;
reg [ADDR_WIDTH-1:0] Add_wr_gray;
reg [ADDR_WIDTH-1:0] Add_wr_gray_dl1;
reg [ADDR_WIDTH-1:0] Add_rd;
wire [ADDR_WIDTH-1:0] Add_rd_pluse;
reg [ADDR_WIDTH-1:0] Add_rd_gray;
reg [ADDR_WIDTH-1:0] Add_rd_gray_dl1;
reg [ADDR_WIDTH-1:0] Add_rd_ungray;
wire [ADDR_WIDTH-1:0] Add_wr_pluse;
integer i;
reg full /* synthesis syn_keep=1 */;
reg empty;
wire [ADDR_WIDTH-1:0] ff_used_wr;
wire [ADDR_WIDTH-1:0] ff_used_rd;
reg rd_ack;
reg rd_ack_tmp;
reg almost_full;
wire [DATA_WIDTH-1:0] dout_tmp;
//////////////////////////////////////////////////////
//Write clock domain
//////////////////////////////////////////////////////
assign wr_ack =0;
assign ff_used_wr =Add_wr-Add_rd_ungray;
assign wr_count =ff_used_wr[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
always @ (posedge ainit or posedge wr_clk)
if (ainit)
Add_wr_gray <=0;
else
begin
Add_wr_gray[ADDR_WIDTH-1] <=Add_wr[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_wr_gray[i] <=Add_wr[i+1]^Add_wr[i];
end
//¶ÁµØÖ·½øÐз´gray±àÂë.
always @ (posedge wr_clk or posedge ainit)
if (ainit)
Add_rd_gray_dl1 <=0;
else
Add_rd_gray_dl1 <=Add_rd_gray;
always @ (posedge wr_clk or posedge ainit)
if (ainit)
Add_rd_ungray =0;
else
begin
Add_rd_ungray[ADDR_WIDTH-1] =Add_rd_gray_dl1[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_rd_ungray[i] =Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
end
assign Add_wr_pluse=Add_wr+1;
/*
always @ (Add_wr_pluse or Add_rd_ungray)
if (Add_wr_pluse==Add_rd_ungray)
full =1;
else
full =0;
*/
always @ (posedge wr_clk or posedge ainit)
if (ainit)
full <=0;
else if(Add_wr_pluse==Add_rd_ungray&&wr_en)
full <=1;
else if(Add_wr!=Add_rd_ungray)
full <=0;
always @ (posedge wr_clk or posedge ainit)
if (ainit)
almost_full <=0;
else if (wr_count>=ALMOST_FULL_DEPTH)
almost_full <=1;
else
almost_full <=0;
always @ (posedge wr_clk or posedge ainit)
if (ainit)
Add_wr <=0;
else if (wr_en&&!full)
Add_wr <=Add_wr +1;
//******************************************************************************
//read clock domain
//******************************************************************************
always @ (posedge rd_clk or posedge ainit)
if (ainit)
rd_ack <=0;
else if (rd_en&&!empty)
rd_ack <=1;
else
rd_ack <=0;
assign ff_used_rd =Add_wr_ungray-Add_rd;
assign rd_count =ff_used_rd[ADDR_WIDTH-1:ADDR_WIDTH-COUNT_DATA_WIDTH];
assign Add_rd_pluse =Add_rd+1;
always @ (posedge rd_clk or posedge ainit)
if (ainit)
Add_rd <=0;
else if (rd_en&&!empty) //³öEOPºó¾Í²»¶ÁÁË¡£
Add_rd <=Add_rd + 1;
//¶ÁµØÖ·½øÐÐgrayÂë±ä»».
always @ (posedge ainit or posedge rd_clk)
if (ainit)
Add_rd_gray <=0;
else
begin
Add_rd_gray[ADDR_WIDTH-1] <=Add_rd[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_rd_gray[i] <=Add_rd[i+1]^Add_rd[i];
end
/* Add_rd_gray <={ Add_rd[8],
Add_rd[8]^Add_rd[7],
Add_rd[7]^Add_rd[6],
Add_rd[6]^Add_rd[5],
Add_rd[5]^Add_rd[4],
Add_rd[4]^Add_rd[3],
Add_rd[3]^Add_rd[2],
Add_rd[2]^Add_rd[1],
Add_rd[1]^Add_rd[0]};
*/
//дµØÖ·½øÐз´gray±àÂë.
always @ (posedge rd_clk or posedge ainit)
if (ainit)
Add_wr_gray_dl1 <=0;
else
Add_wr_gray_dl1 <=Add_wr_gray;
always @ (posedge rd_clk or posedge ainit)
if (ainit)
Add_wr_ungray =0;
else
begin
Add_wr_ungray[ADDR_WIDTH-1] =Add_wr_gray_dl1[ADDR_WIDTH-1];
for (i=ADDR_WIDTH-2;i>=0;i=i-1)
Add_wr_ungray[i] =Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];
end
/* Add_wr_ungray <={
Add_wr_gray_dl1[8],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1],
Add_wr_gray_dl1[8]^Add_wr_gray_dl1[7]^Add_wr_gray_dl1[6]^Add_wr_gray_dl1[5]^Add_wr_gray_dl1[4]^Add_wr_gray_dl1[3]^Add_wr_gray_dl1[2]^Add_wr_gray_dl1[1]^Add_wr_gray_dl1[0] };
*/
//emptyÐźŲúÉú
/*
always @ (Add_rd or Add_wr_ungray)
if (Add_rd==Add_wr_ungray)
empty =1;
else
empty =0;
*/
always @ (posedge rd_clk or posedge ainit)
if (ainit)
empty <=1;
else if (Add_rd_pluse==Add_wr_ungray&&rd_en)
empty <=1;
else if (Add_rd!=Add_wr_ungray)
empty <=0;
//////////////////////////////////////////////////////
//instant need change for your own dpram
//////////////////////////////////////////////////////
duram #(
DATA_WIDTH,
ADDR_WIDTH
)
U_duram (
.data_a (din ),
.wren_a (wr_en ),
.address_a (Add_wr ),
.address_b (Add_rd ),
.clock_a (wr_clk ),
.clock_b (rd_clk ),
.q_b (dout ));
endmodule |
//======================================================================
//
// aes_decipher_block.v
// --------------------
// The AES decipher round. A pure combinational module that implements
// the initial round, main round and final round logic for
// decciper operations.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2013, 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module aes_decipher_block(
input wire clk,
input wire reset_n,
input wire next,
input wire keylen,
output wire [3 : 0] round,
input wire [127 : 0] round_key,
input wire [127 : 0] block,
output wire [127 : 0] new_block,
output wire ready
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
localparam AES_128_BIT_KEY = 1'h0;
localparam AES_256_BIT_KEY = 1'h1;
localparam AES128_ROUNDS = 4'ha;
localparam AES256_ROUNDS = 4'he;
localparam NO_UPDATE = 3'h0;
localparam INIT_UPDATE = 3'h1;
localparam SBOX_UPDATE = 3'h2;
localparam MAIN_UPDATE = 3'h3;
localparam FINAL_UPDATE = 3'h4;
localparam CTRL_IDLE = 2'h0;
localparam CTRL_INIT = 2'h1;
localparam CTRL_SBOX = 2'h2;
localparam CTRL_MAIN = 2'h3;
//----------------------------------------------------------------
// Gaolis multiplication functions for Inverse MixColumn.
//----------------------------------------------------------------
function [7 : 0] gm2(input [7 : 0] op);
begin
gm2 = {op[6 : 0], 1'b0} ^ (8'h1b & {8{op[7]}});
end
endfunction // gm2
function [7 : 0] gm3(input [7 : 0] op);
begin
gm3 = gm2(op) ^ op;
end
endfunction // gm3
function [7 : 0] gm4(input [7 : 0] op);
begin
gm4 = gm2(gm2(op));
end
endfunction // gm4
function [7 : 0] gm8(input [7 : 0] op);
begin
gm8 = gm2(gm4(op));
end
endfunction // gm8
function [7 : 0] gm09(input [7 : 0] op);
begin
gm09 = gm8(op) ^ op;
end
endfunction // gm09
function [7 : 0] gm11(input [7 : 0] op);
begin
gm11 = gm8(op) ^ gm2(op) ^ op;
end
endfunction // gm11
function [7 : 0] gm13(input [7 : 0] op);
begin
gm13 = gm8(op) ^ gm4(op) ^ op;
end
endfunction // gm13
function [7 : 0] gm14(input [7 : 0] op);
begin
gm14 = gm8(op) ^ gm4(op) ^ gm2(op);
end
endfunction // gm14
function [31 : 0] inv_mixw(input [31 : 0] w);
reg [7 : 0] b0, b1, b2, b3;
reg [7 : 0] mb0, mb1, mb2, mb3;
begin
b0 = w[31 : 24];
b1 = w[23 : 16];
b2 = w[15 : 08];
b3 = w[07 : 00];
mb0 = gm14(b0) ^ gm11(b1) ^ gm13(b2) ^ gm09(b3);
mb1 = gm09(b0) ^ gm14(b1) ^ gm11(b2) ^ gm13(b3);
mb2 = gm13(b0) ^ gm09(b1) ^ gm14(b2) ^ gm11(b3);
mb3 = gm11(b0) ^ gm13(b1) ^ gm09(b2) ^ gm14(b3);
inv_mixw = {mb0, mb1, mb2, mb3};
end
endfunction // mixw
function [127 : 0] inv_mixcolumns(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = inv_mixw(w0);
ws1 = inv_mixw(w1);
ws2 = inv_mixw(w2);
ws3 = inv_mixw(w3);
inv_mixcolumns = {ws0, ws1, ws2, ws3};
end
endfunction // inv_mixcolumns
function [127 : 0] inv_shiftrows(input [127 : 0] data);
reg [31 : 0] w0, w1, w2, w3;
reg [31 : 0] ws0, ws1, ws2, ws3;
begin
w0 = data[127 : 096];
w1 = data[095 : 064];
w2 = data[063 : 032];
w3 = data[031 : 000];
ws0 = {w0[31 : 24], w3[23 : 16], w2[15 : 08], w1[07 : 00]};
ws1 = {w1[31 : 24], w0[23 : 16], w3[15 : 08], w2[07 : 00]};
ws2 = {w2[31 : 24], w1[23 : 16], w0[15 : 08], w3[07 : 00]};
ws3 = {w3[31 : 24], w2[23 : 16], w1[15 : 08], w0[07 : 00]};
inv_shiftrows = {ws0, ws1, ws2, ws3};
end
endfunction // inv_shiftrows
function [127 : 0] addroundkey(input [127 : 0] data, input [127 : 0] rkey);
begin
addroundkey = data ^ rkey;
end
endfunction // addroundkey
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg [1 : 0] sword_ctr_reg;
reg [1 : 0] sword_ctr_new;
reg sword_ctr_we;
reg sword_ctr_inc;
reg sword_ctr_rst;
reg [3 : 0] round_ctr_reg;
reg [3 : 0] round_ctr_new;
reg round_ctr_we;
reg round_ctr_set;
reg round_ctr_dec;
reg [127 : 0] block_new;
reg [31 : 0] block_w0_reg;
reg [31 : 0] block_w1_reg;
reg [31 : 0] block_w2_reg;
reg [31 : 0] block_w3_reg;
reg block_w0_we;
reg block_w1_we;
reg block_w2_we;
reg block_w3_we;
reg ready_reg;
reg ready_new;
reg ready_we;
reg [1 : 0] dec_ctrl_reg;
reg [1 : 0] dec_ctrl_new;
reg dec_ctrl_we;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [31 : 0] tmp_sboxw;
wire [31 : 0] new_sboxw;
reg [2 : 0] update_type;
//----------------------------------------------------------------
// Instantiations.
//----------------------------------------------------------------
aes_inv_sbox inv_sbox_inst(.sboxw(tmp_sboxw), .new_sboxw(new_sboxw));
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign round = round_ctr_reg;
assign new_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
assign ready = ready_reg;
//----------------------------------------------------------------
// reg_update
//
// Update functionality for all registers in the core.
// All registers are positive edge triggered with synchronous
// active low reset. All registers have write enable.
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin: reg_update
if (!reset_n)
begin
block_w0_reg <= 32'h0;
block_w1_reg <= 32'h0;
block_w2_reg <= 32'h0;
block_w3_reg <= 32'h0;
sword_ctr_reg <= 2'h0;
round_ctr_reg <= 4'h0;
ready_reg <= 1'b1;
dec_ctrl_reg <= CTRL_IDLE;
end
else
begin
if (block_w0_we)
block_w0_reg <= block_new[127 : 096];
if (block_w1_we)
block_w1_reg <= block_new[095 : 064];
if (block_w2_we)
block_w2_reg <= block_new[063 : 032];
if (block_w3_we)
block_w3_reg <= block_new[031 : 000];
if (sword_ctr_we)
sword_ctr_reg <= sword_ctr_new;
if (round_ctr_we)
round_ctr_reg <= round_ctr_new;
if (ready_we)
ready_reg <= ready_new;
if (dec_ctrl_we)
dec_ctrl_reg <= dec_ctrl_new;
end
end // reg_update
//----------------------------------------------------------------
// round_logic
//
// The logic needed to implement init, main and final rounds.
//----------------------------------------------------------------
always @*
begin : round_logic
reg [127 : 0] old_block, inv_shiftrows_block, inv_mixcolumns_block;
reg [127 : 0] addkey_block;
inv_shiftrows_block = 128'h0;
inv_mixcolumns_block = 128'h0;
addkey_block = 128'h0;
block_new = 128'h0;
tmp_sboxw = 32'h0;
block_w0_we = 1'b0;
block_w1_we = 1'b0;
block_w2_we = 1'b0;
block_w3_we = 1'b0;
old_block = {block_w0_reg, block_w1_reg, block_w2_reg, block_w3_reg};
// Update based on update type.
case (update_type)
// InitRound
INIT_UPDATE:
begin
old_block = block;
addkey_block = addroundkey(old_block, round_key);
inv_shiftrows_block = inv_shiftrows(addkey_block);
block_new = inv_shiftrows_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
SBOX_UPDATE:
begin
block_new = {new_sboxw, new_sboxw, new_sboxw, new_sboxw};
case (sword_ctr_reg)
2'h0:
begin
tmp_sboxw = block_w0_reg;
block_w0_we = 1'b1;
end
2'h1:
begin
tmp_sboxw = block_w1_reg;
block_w1_we = 1'b1;
end
2'h2:
begin
tmp_sboxw = block_w2_reg;
block_w2_we = 1'b1;
end
2'h3:
begin
tmp_sboxw = block_w3_reg;
block_w3_we = 1'b1;
end
endcase // case (sbox_mux_ctrl_reg)
end
MAIN_UPDATE:
begin
addkey_block = addroundkey(old_block, round_key);
inv_mixcolumns_block = inv_mixcolumns(addkey_block);
inv_shiftrows_block = inv_shiftrows(inv_mixcolumns_block);
block_new = inv_shiftrows_block;
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
FINAL_UPDATE:
begin
block_new = addroundkey(old_block, round_key);
block_w0_we = 1'b1;
block_w1_we = 1'b1;
block_w2_we = 1'b1;
block_w3_we = 1'b1;
end
default:
begin
end
endcase // case (update_type)
end // round_logic
//----------------------------------------------------------------
// sword_ctr
//
// The subbytes word counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : sword_ctr
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b0;
if (sword_ctr_rst)
begin
sword_ctr_new = 2'h0;
sword_ctr_we = 1'b1;
end
else if (sword_ctr_inc)
begin
sword_ctr_new = sword_ctr_reg + 1'b1;
sword_ctr_we = 1'b1;
end
end // sword_ctr
//----------------------------------------------------------------
// round_ctr
//
// The round counter with reset and increase logic.
//----------------------------------------------------------------
always @*
begin : round_ctr
round_ctr_new = 4'h0;
round_ctr_we = 1'b0;
if (round_ctr_set)
begin
if (keylen == AES_256_BIT_KEY)
begin
round_ctr_new = AES256_ROUNDS;
end
else
begin
round_ctr_new = AES128_ROUNDS;
end
round_ctr_we = 1'b1;
end
else if (round_ctr_dec)
begin
round_ctr_new = round_ctr_reg - 1'b1;
round_ctr_we = 1'b1;
end
end // round_ctr
//----------------------------------------------------------------
// decipher_ctrl
//
// The FSM that controls the decipher operations.
//----------------------------------------------------------------
always @*
begin: decipher_ctrl
sword_ctr_inc = 1'b0;
sword_ctr_rst = 1'b0;
round_ctr_dec = 1'b0;
round_ctr_set = 1'b0;
ready_new = 1'b0;
ready_we = 1'b0;
update_type = NO_UPDATE;
dec_ctrl_new = CTRL_IDLE;
dec_ctrl_we = 1'b0;
case(dec_ctrl_reg)
CTRL_IDLE:
begin
if (next)
begin
round_ctr_set = 1'b1;
ready_new = 1'b0;
ready_we = 1'b1;
dec_ctrl_new = CTRL_INIT;
dec_ctrl_we = 1'b1;
end
end
CTRL_INIT:
begin
sword_ctr_rst = 1'b1;
update_type = INIT_UPDATE;
dec_ctrl_new = CTRL_SBOX;
dec_ctrl_we = 1'b1;
end
CTRL_SBOX:
begin
sword_ctr_inc = 1'b1;
update_type = SBOX_UPDATE;
if (sword_ctr_reg == 2'h3)
begin
round_ctr_dec = 1'b1;
dec_ctrl_new = CTRL_MAIN;
dec_ctrl_we = 1'b1;
end
end
CTRL_MAIN:
begin
sword_ctr_rst = 1'b1;
if (round_ctr_reg > 0)
begin
update_type = MAIN_UPDATE;
dec_ctrl_new = CTRL_SBOX;
dec_ctrl_we = 1'b1;
end
else
begin
update_type = FINAL_UPDATE;
ready_new = 1'b1;
ready_we = 1'b1;
dec_ctrl_new = CTRL_IDLE;
dec_ctrl_we = 1'b1;
end
end
default:
begin
// Empty. Just here to make the synthesis tool happy.
end
endcase // case (dec_ctrl_reg)
end // decipher_ctrl
endmodule // aes_decipher_block
//======================================================================
// EOF aes_decipher_block.v
//======================================================================
|
/**
* @module alu_flags
* @author sabertazimi
* @email [email protected]
* @brief get flags after alu calculation
* @param DATA_WIDTH data width
* @input srcA A port data
* @input srcB B port data
* @input aluop operation code
* @output zero equal flag
* @output of signed overflow flag
* @output uof unsigned overflow flag
*/
module alu_flags
#(parameter DATA_WIDTH = 32)
(
input [DATA_WIDTH-1:0] srcA,
input [DATA_WIDTH-1:0] srcB,
input [3:0] aluop,
output zero,
output of,
output uof
);
wire [DATA_WIDTH-1:0] sum, diff;
wire carry1, carry2;
assign {carry1, sum} = srcA + srcB; // awesome tip
assign {carry2, diff} = srcA - srcB; // awesome tip
assign zero = (srcA == srcB);
assign of = (aluop == 4'd5) ? ((srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & ~sum[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & sum[DATA_WIDTH-1]))
: (aluop == 4'd6) ? ((srcA[DATA_WIDTH-1] & ~srcB[DATA_WIDTH-1] & ~diff[DATA_WIDTH-1]) | (~srcA[DATA_WIDTH-1] & srcB[DATA_WIDTH-1] & diff[DATA_WIDTH-1]))
: 0;
assign uof = (aluop == 4'd5) ? (carry1)
: (aluop == 4'd6) ? (carry2)
: 0;
endmodule // alu_flags
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_4_V
`define SKY130_FD_SC_HDLL__CLKINV_4_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_4 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_4 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_4_V
|
// -*- Mode: Verilog -*-
// Filename : testbench.v
// Description : Basic Picoblaze TB
// Author : Philip Tracton
// Created On : Thu May 21 22:35:48 2015
// Last Modified By: Philip Tracton
// Last Modified On: Thu May 21 22:35:48 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
module testbench (/*AUTOARG*/) ;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
/*AUTOREG*/
//
// Free Running 100 MHz clock
//
reg CLK_IN = 0;
initial begin
forever begin
#5 CLK_IN <= ~CLK_IN;
end
end
//
// Reset
//
reg RESET_IN = 0;
initial begin
#100 RESET_IN <= 1;
#1000 RESET_IN <= 0;
end
wire [7:0] LEDS; // From dut of basic.v
reg [7:0] SWITCHES_reg = 8'h00; // From dut of basic.v
wire [7:0] SWITCHES;
assign SWITCHES = SWITCHES_reg;
basic dut(/*AUTOINST*/
// Outputs
.LEDS (LEDS[7:0]),
// Inputs
.CLK_IN (CLK_IN),
.RESET_IN (RESET_IN),
.SWITCHES (SWITCHES[7:0]));
//
// Test XCase
//
initial begin
@(posedge RESET_IN);
$display("RESET: Asserted @ %d", $time);
@(negedge RESET_IN);
$display("RESET: De-Asserted @ %d", $time);
// @(posedge testbench.dut.syscon.LOCKED);
// $display("DCM LOCKED @ %d", $time);
@(posedge LEDS[7]);
$display("LEDS ON @ %d", $time);
repeat(100) @(posedge CLK_IN);
SWITCHES_reg <= 8'hFF;
$display("SWITCHES ASSERTED @ %d", $time);
@(posedge (LEDS == 8'hFF));
$display("SWITCHES to LEDS FF @ %d", $time);
repeat(100) @(posedge CLK_IN);
SWITCHES_reg <= 8'h00;
@(posedge (LEDS == 8'h00));
$display("SWITCHES to LEDS 00 @ %d", $time);
repeat(100) @(posedge CLK_IN);
SWITCHES_reg <= 8'hFF;
@(posedge (LEDS == 8'hFF));
$display("SWITCHES to LEDS FF @ %d", $time);
repeat(100) @(posedge CLK_IN);
$stop;
end
endmodule // Basic
|
`timescale 1 ns / 1 ps
module mac(
input clk,
input reset,
input [9:0] row,
input [63:0] value0,
input [63:0] value1,
input wr,
output push,
output [63:0] dout,
input done);
//multiplier
reg multiplier_shift [14:0];
reg [9:0] multiplier_row_shift [14:0];
reg adder_shift [11:0];
reg [9:0] adder_row_shift [11:0];
wire [63:0] multy_result;
wire [63:0] sum;
wire inter_add;
wire [63:0] inter_add0, inter_add1;
wire [9:0] inter_add_row;
integer i;
multiplier multy(
.clk(clk),
.result(multy_result),
.a(value0),
.b(value1));
always @(posedge clk) begin
multiplier_shift[0] <= wr;
multiplier_row_shift[0] <= row;
for(i = 0; i < 14; i = i + 1) begin
multiplier_shift[i + 1] <= multiplier_shift[i];
multiplier_row_shift[i + 1] <= multiplier_row_shift[i];
end
end
//TODO: add done signal
reg [7:0] flush_counter;
wire flush;
always @(posedge clk) begin
if(reset)
flush_counter <= 0;
else if(done)
flush_counter <= flush_counter + 1;
else
flush_counter <= 0;
end
assign flush = flush_counter[7];
intermediator inter(
.reset(reset),
.clk(clk),
.valid0(multiplier_shift[14]),
.value0(multy_result),
.row0(multiplier_row_shift[14]),
.valid1(adder_shift[11]),
.value1(sum),
.row1(adder_row_shift[11]),
.store(push),
.store_value(dout),
.add(inter_add),
.add0(inter_add0),
.add1(inter_add1),
.add_row(inter_add_row),
.flush(flush));
adder addy(
.clk(clk),
.result(sum),
.a(inter_add0),
.b(inter_add1));
always @(posedge clk) begin
adder_shift[0] <= inter_add;
adder_row_shift[0] <= inter_add_row;
for(i = 0; i < 11; i = i + 1) begin
adder_shift[i + 1] <= adder_shift[i];
adder_row_shift[i + 1] <= adder_row_shift[i];
end
end
endmodule
|
module Sec6_Top(
input [7:0] ADCData,
input reset_n,
output [2:0] sel,
output [6:0] segments,
output digit,
output CS_n,
output RD_n,
output WR_n
);
wire clk;
wire clk_slow;
wire [3:0] dispNum;
wire [8:0] voltage;
//This is an instance of a special, built in module that accesses our chip's oscillator
OSCH #("2.08") osc_int ( //"2.03" specifies the operating frequency, 2.03 MHz. Other clock frequencies can be found in the MachX02's documentation
.STDBY(1'b0), //Specifies active state
.OSC(clk), //Outputs clock signal to 'clk' net
.SEDSTDBY()); //Leaves SEDSTDBY pin unconnected
clock_counter counter_1(
.clk_i(clk),
.reset_n(reset_n),
.clk_o(clk_slow)
);
ADCinterface int(
.reset_n(reset_n),
.clk(clk),
.CS_n(CS_n),
.RD_n(RD_n),
.WR_n(WR_n)
);
Sec6_SM FSM_1(
.clk_i(clk_slow),
.reset_n(reset_n),
.sel(sel),
.digit(digit)
);
interpretADC interp(
.ADCData(ADCData),
.voltage(voltage)
);
determineNum det(
.sel(sel),
.ADCData(voltage),
// .reset_n(reset_n),
.dispNum(dispNum)
);
sevenSeg segDecoder(
.data(dispNum),
.segments(segments)
);
endmodule |
// --------------------------------------------------------------------
// ng_INT Central register Module
// --------------------------------------------------------------------
`include "ControlPulses.h"
// --------------------------------------------------------------------
module ng_INT(
input CPO4, // Clock Pulse Interrupt1
input CPO5, // Clock Pulse Interrupt3
input KB_STR, // Keyboard Interrupt4
input CLK2, // Clock Pulse 2
input [100:0] CP, // Control Pulse
input [ 15:0] WRITE_BUS, // Control Pulse
output [ 15:0] INT_BUS, // INT Register output
output IRQ // Interrupt request
);
// --------------------------------------------------------------------
// JTAG Debugging Probes
// --------------------------------------------------------------------
//JTAG_Probe INT_OUT16(.probe(INT_BUS));
// 3 3 3 3 1 1 1 1
//JTAG_Probe INT_TST16(.probe({RPCELL,pri_level,pri_out, rst_RUPT, KRPT, CLRP, pri_EO,IT_SEL}));
// 15 14 13 12 11 10 9 8 7, 6, 5, 4, 3, 2, 1, 0
JTAG_Probe INT_TST2(.probe({IRQ,rgINH,rgINH1,KB_STR,RPT,INH,CLINH,CLINH1,WOVI,rgRUPT1,rgRUPT3,rgRUPT4,WRITE_BUS[15],WRITE_BUS[14],KRPT,CLRP }));
// --------------------------------------------------------------------
// Output Assignments
// --------------------------------------------------------------------
assign IRQ = !(IT_INH & IT_INH1 & pri_EO & IT_SEL);
// --------------------------------------------------------------------
// Control Signal Assignments
// --------------------------------------------------------------------
wire GENRST = CP[`CPX(`GENRST)]; // General reset signal
wire RPT = CP[`CPX(`RPT)]; // Read RUPT opcode
wire CLRP = CP[`CPX(`CLRP)]; // Clear RPCELL
wire INH = CP[`CPX(`INH)]; // Set INHINT
wire CLINH = CP[`CPX(`CLINH)]; // Clear INHINT
wire CLINH1 = CP[`CPX(`CLINH1)]; // Clear INHINT1
wire WOVI = CP[`CPX(`WOVI)]; // Write overflow RUPT inhibit
wire KRPT = CP[`CPX(`KRPT)]; // Knock down Rupt priority
// --------------------------------------------------------------------
// Register Storage
// --------------------------------------------------------------------
reg rgINH; // Inhibit Interrupt register
reg rgINH1; // Inhibit 1 Interrupt register
reg rgRUPT1; // Interrupt register 1
reg rgRUPT3; // Interrupt register 3
reg rgRUPT4; // Interrupt register 4
reg [2:0] RPCELL; // RP Register
// --------------------------------------------------------------------
// Interrupt Inhibit Logic
//
// NOTE: A JK FF can be instantiated using this code:
// always@(negedge CLK or negedge CLN or negedge PRN)
// if (!CLN) Q <= 0;
// else if(!PRN) Q <= 1;
// else Q <= ~Q & J | Q & ~K;
// --------------------------------------------------------------------
reg rgINH_i; // internal Inhibit Interrupt register
always@(posedge CLK2)
rgINH_i <= (~rgINH_i & !(INH & GENRST)) | (rgINH_i & CLINH);
always@(negedge CLK2) rgINH <= rgINH_i; // Transfer to outputs on negative edge
reg rgINH1_i; // internal Inhibit Interrupt register
wire IT_INH1_J = (WRITE_BUS[15] ^ WRITE_BUS[14]) & ~WOVI;
always@(posedge CLK2)
if(!GENRST) rgINH1_i <= 1'b0;
else rgINH1_i <= (~rgINH1_i & IT_INH1_J) | (rgINH1_i & CLINH1);
always@(negedge CLK2) rgINH1 <= rgINH1_i; // Transfer to outputs on negative edge
wire IT_INH = !rgINH;
wire IT_INH1 = !rgINH1;
// --------------------------------------------------------------------
// Interrupt Latches
// --------------------------------------------------------------------
wire IT_RST = !(CLK2 & !GENRST); // Reset Signal sync with clock
wire rst_RUPT1 = rst_RUPT[0] & IT_RST; // Rupt reset wires
reg rgRUPT1_i; // Interrupt register 1
always@(posedge CPO4 or negedge rst_RUPT1) // Interrupt latch 1
if(!rst_RUPT1) rgRUPT1_i <= 1'b0; // Release latch
else rgRUPT1_i <= 1'b1; // Set latch
always@(negedge CPO4 or negedge rst_RUPT1) rgRUPT1 <= rgRUPT1_i;
wire rst_RUPT3 = rst_RUPT[1] & IT_RST; // Rupt reset wires
reg rgRUPT3_i; // Interrupt register 3
always@(posedge CPO5 or negedge rst_RUPT3) // Interrupt latch 3
if(!rst_RUPT3) rgRUPT3_i <= 1'b0; // Release latch
else rgRUPT3_i <= 1'b1; // Set latch
always@(negedge CPO5 or negedge rst_RUPT3) rgRUPT3 <= rgRUPT3_i;
reg rgRUPT4_i;
always@(posedge KB_STR or negedge rst_RUPT4) // Interrupt latch 4
if(!rst_RUPT4) rgRUPT4_i <= 1'b0; // Release latch
else if(KB_STR) rgRUPT4_i <= 1'b1; // Set latch
always@(negedge KB_STR or negedge rst_RUPT4) rgRUPT4 <= rgRUPT4_i;
wire rst_RUPT4 = IT_RST & rst_RUPT[2]; // Rupt reset wires
// --------------------------------------------------------------------
// Prioritize the interrupts
// --------------------------------------------------------------------
wire [2:0] pri_level = {rgRUPT1, rgRUPT3, rgRUPT4}; // Priority level
reg [2:0] pri_out; // seected priority
always @(pri_level) begin
casex(pri_level)
3'b1XX : pri_out <= 3'b001; // priority 6, pri_out = 1
3'b01X : pri_out <= 3'b011; // priority 4, pri_out = 3
3'b001 : pri_out <= 3'b100; // priority 3, pri_out = 4
default : pri_out <= 3'b111; // priority X, pri_out = 7
endcase
end
wire pri_EO = |pri_level; // =1 if were any activated
// --------------------------------------------------------------------
// Instantiate Register RPCELL at address
// 2004 = RUPT 1 (TIME3)(octal RUPT addr)
// 2014 = RUPT 3 (TIME4)
// 2020 = RUPT 4 (KBD)
// --------------------------------------------------------------------
always @(posedge CLK2) begin
if(!GENRST) RPCELL <= 3'h0;
else if(!CLRP) RPCELL <= 3'h0;
else if(!RPT) RPCELL <= pri_out;
end
wire IT_SEL = !(|RPCELL);
assign INT_BUS = {11'b0000_0100_000,RPCELL,2'b00};
// --------------------------------------------------------------------
// Interrupt Reset Logic
// --------------------------------------------------------------------
reg [2:0] rst_RUPT; // Rupt reset
always @(posedge CLK2) begin
if(!KRPT) begin
case(pri_out)
3'b001 : rst_RUPT <= 3'b110; // Priority 1
3'b011 : rst_RUPT <= 3'b101; // Priority 3
3'b100 : rst_RUPT <= 3'b011; // Priority 4
default: rst_RUPT <= 3'b111; // Priority 7
endcase
end
else rst_RUPT <= 3'b111;
end
// --------------------------------------------------------------------
endmodule
// --------------------------------------------------------------------
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2018 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [15:0] m_din;
// We expect none of these blocks to split.
// Blocks that can split should go in t_alw_split.v instead.
reg [15:0] b_split_1, b_split_2;
always @ (/*AS*/m_din) begin
b_split_1 = m_din;
b_split_2 = b_split_1;
end
reg [15:0] c_split_1, c_split_2;
always @ (/*AS*/m_din) begin
c_split_1 = m_din;
c_split_2 = c_split_1;
c_split_1 = ~m_din;
end
always @ (posedge clk) begin
$write(" foo %x", m_din);
$write(" bar %x\n", m_din);
end
reg [15:0] e_split_1, e_split_2;
always @ (posedge clk) begin
e_split_1 = m_din;
e_split_2 = e_split_1;
end
reg [15:0] f_split_1, f_split_2;
always @ (posedge clk) begin
f_split_2 = f_split_1;
f_split_1 = m_din;
end
reg [15:0] l_split_1, l_split_2;
always @ (posedge clk) begin
l_split_2 <= l_split_1;
l_split_1 <= l_split_2 | m_din;
end
reg [15:0] z_split_1, z_split_2;
always @ (posedge clk) begin
z_split_1 <= 0;
z_split_1 <= ~m_din;
end
always @ (posedge clk) begin
z_split_2 <= 0;
z_split_2 <= z_split_1;
end
reg [15:0] h_split_1;
reg [15:0] h_split_2;
reg [15:0] h_foo;
always @ (posedge clk) begin
// $write(" cyc = %x m_din = %x\n", cyc, m_din);
h_foo = m_din;
if (cyc > 2) begin
// This conditional depends on non-primary-input foo.
// Its dependency on foo should not be pruned. As a result,
// the dependencies of h_split_1 and h_split_2 on this
// conditional will also not be pruned, making them all
// weakly connected such that they'll end up in the same graph
// and we can't split.
if (h_foo == 16'h0) begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
else begin
h_split_1 <= m_din;
h_split_2 <= ~m_din;
end
end
else begin
h_split_1 <= 16'h0;
h_split_2 <= 16'h0;
end
end // always @ (posedge clk)
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
end
if (cyc==1) begin
m_din <= 16'hfeed;
end
if (cyc==4) begin
m_din <= 16'he11e;
if (!(b_split_1==16'hfeed && b_split_2==16'hfeed)) $stop;
if (!(c_split_1==16'h0112 && c_split_2==16'hfeed)) $stop;
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
end
if (cyc==5) begin
m_din <= 16'he22e;
if (!(b_split_1==16'he11e && b_split_2==16'he11e)) $stop;
if (!(c_split_1==16'h1ee1 && c_split_2==16'he11e)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'hfeed && e_split_2==16'hfeed) && !(e_split_1==16'he11e && e_split_2==16'he11e)) $stop;
if (!(f_split_1==16'hfeed && f_split_2==16'hfeed) && !(f_split_1==16'he11e && f_split_2==16'hfeed)) $stop;
if (!(z_split_1==16'h0112 && z_split_2==16'h0112)) $stop;
end
if (cyc==6) begin
m_din <= 16'he33e;
if (!(b_split_1==16'he22e && b_split_2==16'he22e)) $stop;
if (!(c_split_1==16'h1dd1 && c_split_2==16'he22e)) $stop;
// Two valid orderings, as we don't know which posedge clk gets evaled first
if (!(e_split_1==16'he11e && e_split_2==16'he11e) && !(e_split_1==16'he22e && e_split_2==16'he22e)) $stop;
if (!(f_split_1==16'he11e && f_split_2==16'hfeed) && !(f_split_1==16'he22e && f_split_2==16'he11e)) $stop;
if (!(z_split_1==16'h1ee1 && z_split_2==16'h0112)) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__O21BA_PP_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_PP_BLACKBOX_V
|
(*|
.. raw:: html
<link rel="stylesheet" href="tutorial.css" type="text/css" />
.. coq:: none
|*)
(****************************************************************************)
(* Copyright 2021 The Project Oak Authors *)
(* *)
(* Licensed under the Apache License, Version 2.0 (the "License") *)
(* you may not use this file except in compliance with the License. *)
(* You may obtain a copy of the License at *)
(* *)
(* http://www.apache.org/licenses/LICENSE-2.0 *)
(* *)
(* Unless required by applicable law or agreed to in writing, software *)
(* distributed under the License is distributed on an "AS IS" BASIS, *)
(* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. *)
(* See the License for the specific language governing permissions and *)
(* limitations under the License. *)
(****************************************************************************)
Require Import Cava.Cava.
Require Import Cava.CavaProperties.
Import Circuit.Notations.
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
==================
Advanced Cava Demo
==================
This set of examples goes a bit further than Cava's tutorial_ and showcases some
advanced features. For a more gentle introduction or setup instructions, the
tutorial is the best place to start.
Here's the high-level overview of what we'll cover:
1. We'll write one circuit template to capture the logical structure of an
algorithm, and then show how to *instantiate it with different subcircuits
in order to perform different computations*.
2. We'll construct a circuit that efficiently multiplies by any fixed "compile
time" constant by *constructing the circuit dynamically according to the
constant*.
3. We'll prove everything correct *in full generality*, meaning the proofs
apply to any choice of subcircuits/constants/other parameters!
Some pieces of boilerplate code have been omitted for readability of this
page. You can view the source_ on our GitHub repo to see it, or to step through
the code locally.
In this demo, we'll define a circuit that executes a classic arithmetic
algorithm, exponentiation by squaring (wikipedia_). The pseudocode looks like::
exp(x,e):
if e = 0:
return 1
r = exp (x, e // 2)
if e is even:
return r^2
else:
return r^2 * x
Essentially, you can compute ``x^e`` quickly by looking at the bitwise
representation of ``e`` and either multiplying by ``x`` or squaring. This saves
operations in comparison to the naive approach, especially for large numbers. To
compute ``x^19``, for instance, you would need only 8 multiplications instead of
the 18 you would need with a naive approach::
exp(x,19) = exp(x,9) ^ 2 * x
exp(x,9) = exp(x,4) ^ 2 * x
exp(x,4) = exp(x,2) ^ 2
exp(x,2) = exp(x,1) ^ 2
exp(x,1) = exp(x,0) ^ 2 * x
exp(x,0) = 1
If you substitute addition and doubling for multiplication and squaring in this
algorithm, and return 0 instead of 1 in the base case, it will compute
multiplication instead of exponentiation ("multiplication by doubling"). In this
case, you would compute ``x*19`` as::
exp(x,19) = exp(x,9) * 2 + x
exp(x,9) = exp(x,4) * 2 + x
exp(x,4) = exp(x,2) * 2
exp(x,2) = exp(x,1) * 2
exp(x,1) = exp(x,0) * 2 + x
exp(x,0) = 1
For our hardware implementation, we'll assume that ``x`` is a fixed constant
known before we build the circuit, and that we get the exponent as a stream of
bits (most significant bit first). As a circuit diagram, it looks like:
.. image:: expbysquaring.png
:width: 90%
:alt: Diagram of the exponentiation-by-squaring circuit.
In Cava, this circuit would be defined as follows:
|*)
Definition exp_by_squaring {A} (identity : combType A)
(square : Circuit (signal A) (signal A))
(multiply : Circuit (signal A) (signal A))
: Circuit (signal Bit) (signal A) :=
LoopInit identity
((* start: exp[i], r *)
Second (square >==> (* r^2 *)
Comb fork2 >==> (* r^2, r^2 *)
Second multiply (* r^2, r^2*x *))
>==> (* exp[i], (r^2, r^2*x) *)
Comb (uncurry mux2 >=> fork2) (* r', r' *)).
(*|
In order to support both multiplication and exponentiation with the same
definition, we haven't specified yet what exactly our "square" and "multiply"
procedures are. In Cava, you can take subcircuits as *arguments* to your circuit
definition, much like in some programming languages you can pass functions as
arguments to other functions. In pseudocode, this template would be analogous
to::
exp(identity, square, multiply, e):
if e = 0:
return identity
r = exp(identity, square, multiply, e // 2)
r2 = square(r)
if e is even:
return r2
else:
return multiply(r2)
Note that ``multiply`` has only one operand here; since we assume ``x`` is a
fixed constant, the ``multiply`` is already specialized to multiply the input by
``x``.
This circuit is so general that it can actually be adapted for even more
purposes than exponentiation and multiplication. By plugging in a no-op for
``square`` and an incrementer for ``multiply``, we can simply count the high
bits of the input stream:
|*)
(* count the number of high bits in the input stream *)
Definition count_ones {n}
: Circuit (signal Bit) (signal (Vec Bit n)) :=
exp_by_squaring
(Vec.of_N 0) (Comb ret) (Comb incrN).
(*|
We can simulate the circuit to check that it has the desired behavior:
.. coq:: none
|*)
End WithCava.
(*||*)
Compute map Bv2N (simulate (count_ones (n:=8))
[true;true;true;false;false;true]).
(*|
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
The ``incrN`` subcircuit adds 1 to the input bitvector without growing the size
of the vector. This component is part of Cava's core library; check out the
reference_ to browse the various verified circuit components that are included.
``Vec.of_N`` is also part of this library; it converts a number of Coq's ``N``
(binary natural numbers) type into a constant Cava bit-vector.
Next, let's try to define multiplication-by-doubling. We'll need to have
subcircuits for addition of a constant and for doubling. For addition, we can
use the ``addN`` circuit that's included in Cava's standard library. Doubling,
however, can be treated as a bitwise operation; we can shift left by one. So
let's define a specific ``double`` circuit separately:
|*)
(* double a bitvector by adding 0 and truncating *)
Definition double {n}
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
Comb (Vec.cons zero >=> Vec.shiftout).
(*|
Now, we can write a circuit that, given a constant ``x``, computes ``x`` times
the input stream:
|*)
(* multiply x by the input stream *)
Definition stream_multiply {n} (x : N)
: Circuit (signal Bit) (signal (Vec Bit n)) :=
(* Circuit that adds x to the input bitvector *)
let addx := Comb (fun i => addN (i, Vec.of_N x)) in
exp_by_squaring (Vec.of_N 0) double addx.
(*|
.. coq:: none
|*)
End WithCava.
(*|
Let's simulate it to see if it works. ``[true;false;false;true]`` is an input
stream that represents the number 9, so this simulation computes ``3*9``.
|*)
(* 3 * 9 = 27 *)
Compute map Bv2N (simulate (stream_multiply (n:=8) 3)
[true;false;false;true]).
(*|
The test becomes more readable if we write a quick helper function to convert
numbers into streams:
|*)
(* Helper for simulation: convert a number into a list of bits with the most
significant bit first *)
Definition to_stream (x : N) : list bool :=
(* reverse because N2Bv puts the least significant bit first *)
rev (Vector.to_list (N2Bv x)).
(* 3 * 9 = 27 *)
Compute map Bv2N (simulate (stream_multiply (n:=8) 3)
(to_stream 9)).
(* 5 * 6 = 30 *)
Compute map Bv2N (simulate (stream_multiply (n:=8) 5)
(to_stream 6)).
(* 5 * 60 = 300 (bit vector size increased to 16) *)
Compute map Bv2N (simulate (stream_multiply (n:=16) 5)
(to_stream 60)).
(*|
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
So far, so good. But how about exponentiation by squaring? Now, we need one
subcircuit to multiply by a constant and one subcircuit to square the
input. Cava's core library already includes ``squareN``, which squares an input
bit-vector and truncates to the input size, so squaring is taken care of.
However, for multiplication, since one of the operands is a constant, it might
be efficient to construct our circuit in a way that takes advantage of that
fact. In Cava, we can actually write circuits that change structure based on
constant arguments. This circuit multiplies its input by the number ``x``, which
is expressed as Coq's strictly-positive bitvector type, ``positive``.
|*)
(* construct a circuit to multiply the input by a compile-time
constant (expressed as a strictly positive Coq bitvector) *)
Fixpoint mul_const_pos {n} (x : positive)
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
(match x with
| 1 => Comb ret
| y~0 =>
(* x * i = 2 * y * i *)
(mul_const_pos y) >==> double
| y~1 =>
(* x * i = (2 * y + 1) * i = 2 * y * i + i *)
Comb fork2 >==> (* i, i *)
First (mul_const_pos y >==> double) >==> (* 2*y*i, i *)
Comb addN (* 2*y*i + i *)
end)%positive.
(*|
In case the syntax here is unfamiliar: the ``match`` here separates three cases,
which correspond to the three constructors of ``positive``. In the first case,
``x = 1``, in which case multiplying by ``x`` is just the identity (``Comb ret``
can be read as "a wire"). In the second case, ``x`` is constructed from another
positive ``y`` with a ``0`` appended to the end, so ``x = 2*y``). In the third
case, ``x`` is constructed from another positive ``y``, but this time with a
``1`` appended to the end, so ``x = 2*y + 1``.
We want to handle the case where ``x = 0`` too, so we can define another wrapper
function on top where ``x`` has the type of Coq's *nonnegative* bit-vectors,
``N``. ``N`` has two constructors; either ``x`` is a zero, or ``x`` is a
positive. So to define our circuit in terms of ``N``, we just produce a circuit
that always returns 0 if ``x`` is zero and call ``mul_const_pos`` to construct
the positive case.
|*)
(* construct a circuit to multiply the input by a compile-time
constant (expressed as a nonnegative Coq bitvector) *)
Definition mul_constN {n} (x : N)
: Circuit (signal (Vec Bit n)) (signal (Vec Bit n)) :=
match x with
| 0%N => Comb (fun _ => ret (Vec.of_N 0))
| Npos p => mul_const_pos p
end.
(*|
.. coq:: none
|*)
End WithCava.
(*|
We can try out constructing this circuit for different values of ``x`` to see
how it behaves.
|*)
Eval cbv [mul_constN mul_const_pos] in mul_constN 1.
Eval cbv [mul_constN mul_const_pos] in mul_constN 4.
Eval cbv [mul_constN mul_const_pos] in mul_constN 5.
Eval cbv [mul_constN mul_const_pos] in mul_constN 16.
Eval cbv [mul_constN mul_const_pos] in mul_constN 20.
Eval cbv [mul_constN mul_const_pos] in mul_constN 2048.
Eval cbv [mul_constN mul_const_pos] in mul_constN 100000.
(*|
Here are the circuit diagrams for some of the smaller ones:
.. figure:: mul1.png
:width: 90%
:alt: Diagram of a circuit that multiplies by 1
:align: center
Above: circuit diagram for ``mul_constN 1``.
.. figure:: mul4.png
:width: 90%
:alt: Diagram of a circuit that multiplies by 4.
:align: center
Above: circuit diagram for ``mul_constN 4``.
.. figure:: mul5.png
:width: 90%
:alt: Diagram of a circuit that multiplies by 5.
:align: center
Above: circuit diagram for ``mul_constN 5``.
.. figure:: mul20.png
:width: 90%
:alt: Diagram of a circuit that multiplies by 20.
:align: center
Above: circuit diagram for ``mul_constN 20``. Note that this is the same as
composing ``mul_constN 5`` and ``mul_constN 4``.
.. coq:: none
|*)
Section WithCava.
Context {signal} {semantics : Cava signal}.
(*|
Now that we can multiply by constants efficiently, we can build a circuit that
implements exponentiation by squaring:
|*)
(* raise x to the power of the input stream *)
Definition stream_exponentiate {n} (x : N)
: Circuit (signal Bit) (signal (Vec Bit n)) :=
exp_by_squaring (Vec.of_N 1) (Comb squareN) (mul_constN x).
(*|
.. coq:: none
|*)
End WithCava.
(*|
It works!
|*)
(* Compute 3 ^ 5 = 243 *)
Compute map Bv2N
(simulate (stream_exponentiate (n:=8) 3)
(to_stream 5)).
(* Compute 5 ^ 6 = 15625 *)
Compute map Bv2N
(simulate (stream_exponentiate (n:=16) 5)
(to_stream 6)).
(* Compute 3 ^ 123
= 48519278097689642681155855396759336072749841943521979872827 *)
Compute map Bv2N
(simulate (stream_exponentiate (n:=200) 3)
(to_stream 123)).
(*|
Now that we've defined all our circuits and tested them a little bit to make
sure they work for some inputs, it's time to prove them correct more
rigorously. The really cool thing about defining these circuits in Coq is that
now we can prove that they behave as expected for *all possible inputs*. We can
even prove that they work for all *constant parameters*, such as the bit-vector
size ``n`` for ``stream_exponentiate`` and the constant ``x`` for
``mul_constN``. In a sense, we're not just proving that our one single circuit
is correct; we're proving that the strategy we use to construct it is *always*
correct. This kind of reasoning is an extremely powerful tool.
First, we'll want to prove that ``exp_by_squaring`` is correct. We'll define a
specification for it in Coq's specification language that captures the crux of
the algorithm.
|*)
Definition exp_by_squaring_spec
{A} (mulx square : A -> A)
(id : A) (exponent : list bool) : A :=
fold_left
(fun r (bit : bool) => if bit then mulx (square r) else square r)
exponent id.
(*|
This specification takes a stream of input and produces the output value we
expect from the circuit after that stream of input has been processed. But this
doesn't quite match our circuit's behavior; we'll get intermediate values as
well. We can define a helper function to apply our specification to each prefix
of the input:
|*)
Definition map_stream {A B} (f : list A -> B) (input : list A) : list B
:= map (fun n => f (firstn (S n) input)) (seq 0 (length input)).
(*|
And now, the proof! It more or less comes down to applying a loop-invariant
lemma, using the preconditions about ``square`` and ``multiply`` to rewrite
those expressions, and doing some list manipulations. Just like in the tutorial,
it's our suggestion to focus more on the proof *statements* (the part between
``Lemma`` and ``Proof``) than the proof *bodies* (the part between ``Proof`` and
``Qed``). The former is intended for humans to read and reason about; the latter
is an argument to Coq that the statement is true, and if the Coq typechecker
accepts it then the argument must be valid (unless there's a bug in Coq itself).
|*)
Lemma exp_by_squaring_correct {A}
(mul_spec square_spec : combType A -> combType A)
(identity : combType A)
(square multiply : Circuit (combType A) (combType A))
(square_correct :
forall st i, step square st i = (st, square_spec i))
(multiply_correct :
forall st i, step multiply st i = (st, mul_spec i))
(input : list bool) :
simulate (exp_by_squaring identity square multiply) input
= map_stream (exp_by_squaring_spec mul_spec square_spec identity)
input.
Proof.
cbv [exp_by_squaring map_stream].
autorewrite with push_simulate.
(* apply loop invariant lemma *)
eapply fold_left_accumulate_invariant_seq
with (I:=fun i st out =>
out = map (fun n => exp_by_squaring_spec
mul_spec square_spec
identity (firstn (S n) input))
(seq 0 i)
/\ snd st = exp_by_squaring_spec
mul_spec square_spec identity (firstn i input)).
{ (* invariant holds in reset state *)
split; reflexivity. }
{ (* invariant holds through one timestep *)
cbv zeta; intros. logical_simplify; subst.
destruct_products. cbn [fst snd] in *. subst.
cbv [mcompose uncurry]. simpl_ident.
(* simplify step, rewrite with square/multiply correctness lemmas *)
repeat first [ progress cbn [fst snd step]
| rewrite square_correct
| rewrite multiply_correct
| destruct_pair_let
| progress simpl_ident ].
(* separate the most recent step from previous steps *)
autorewrite with pull_snoc natsimpl.
rewrite (firstn_succ_snoc input _ ltac:(eassumption))
by (cbn [combType] in *; lia).
cbv [exp_by_squaring_spec].
autorewrite with push_list_fold.
split; reflexivity. }
{ (* invariant implies postcondition *)
intros; logical_simplify; subst. reflexivity. }
Qed.
(*|
From here, we no longer have to reason about the exponentiation-by-squaring
circuit; we can use this lemma to prove all our other circuits are
correct. Instead, we can reason about ``exp_by_squaring_spec``, with no
circuit-related reasoning. For example, to prove the ``count_ones`` circuit
correct, we first prove that our specification (which is based on the Coq
standard library definition ``count_occ``) matches ``exp_by_squaring_spec``.
|*)
(* helper lemma proving that count_occ is a specialization of
exp_by_squaring_spec *)
Lemma count_occ_is_exp_by_squaring n l start :
exp_by_squaring_spec
(A:=combType (Vec Bit n))
(fun v => N2Bv_sized n (Bv2N v + 1)) (fun v => v)
(N2Bv_sized n start) l
= N2Bv_sized n (N.of_nat (count_occ bool_dec l true) + start).
Proof.
cbv [exp_by_squaring_spec]. revert start.
induction l as [|bit l]; [ reflexivity | ].
intros; cbn [count_occ fold_left].
destruct bit; destruct_one_match; try congruence; [ ].
rewrite N2Bv_sized_add_idemp_l.
rewrite IHl. f_equal. lia.
Qed.
(*|
We can use this lemma to prove that, no matter how many timesteps we run or how
big our bit-vector is, the nth output of ``count_ones`` will be the number of
``true`` values that appear in the first n bits of input, truncated to fit the
bit-vector size. Because we're doing all of this with inductive reasoning, it's
not at all computationally intensive to write such a proof.
|*)
Lemma count_ones_correct n (input : list bool) :
simulate (count_ones (n:=n)) input
= map_stream
(fun l => let count := count_occ bool_dec l true in
N2Bv_sized n (N.of_nat count))
input.
Proof.
intros; cbv [count_ones].
rewrite exp_by_squaring_correct
with (mul_spec:=fun v => N2Bv_sized n (Bv2N v + 1))
(square_spec := fun v : combType (Vec Bit n) => v)
by (cbn [circuit_state step]; intros;
lazymatch goal with x : unit |- _ => destruct x end;
simpl_ident; reflexivity).
apply map_ext; intros. simpl_ident.
rewrite count_occ_is_exp_by_squaring.
f_equal; lia.
Qed.
(*|
To prove that ``stream_multiply`` is correct, we'll first have to prove the
single-step behavior of ``double`` (to satisfy the ``square_correct``
precondition of ``exp_by_squaring_correct``). That proof is pretty quick:
|*)
Lemma double_step n st i :
step double st i = (st, N2Bv_sized n (Bv2N i + Bv2N i)).
Proof.
cbv [double step mcompose].
simpl_ident. rewrite shiftout_cons0.
apply f_equal2; [ destruct st; reflexivity | ].
f_equal. lia.
Qed.
(*|
It's useful to write the inverse operation of ``to_stream`` so that
we can talk about the numeric value that the input represents:
|*)
Definition from_stream (l : list bool) : N :=
Bv2N (Vector.of_list (rev l)).
Lemma from_stream_cons bit l :
from_stream (bit :: l)
= ((if bit then 2 ^ (N.of_nat (length l)) else 0)
+ from_stream l)%N.
Proof.
cbv [from_stream]. cbn [rev].
rewrite of_list_snoc.
rewrite app_length; cbn [length].
rewrite resize_default_id.
rewrite Bv2N_snoc.
f_equal.
autorewrite with push_length;
reflexivity.
Qed.
(*|
Now, just like for ``count_ones``, we prove that ``exp_by_squaring_spec``
corresponds to multiplication when given the right parameters. We do it in two
steps, because for the inductive logic to work out we have to reason about the
behavior of ``exp_by_squaring_spec`` for *any* starting value, not just 0.
|*)
Lemma multiply_is_exp_by_squaring' n x l start :
exp_by_squaring_spec
(A:=combType (Vec Bit n))
(fun v => N2Bv_sized n (Bv2N v + x))
(fun v => N2Bv_sized n (Bv2N v + Bv2N v))
start l
= N2Bv_sized n (Bv2N start * 2 ^ N.of_nat (length l)
+ x * from_stream l).
Proof.
cbv [exp_by_squaring_spec].
revert start; induction l.
{ intros; cbn.
rewrite N.mul_0_r, N.add_0_r, N.mul_1_r.
rewrite N2Bv_sized_Bv2N; reflexivity. }
{ intros. cbn [fold_left]. rewrite IHl.
rewrite from_stream_cons.
cbn [length]. rewrite Nat2N.inj_succ, N.pow_succ_r'.
destruct_one_match;
autorewrite with pull_N2Bv_sized;
lazymatch goal with
| |- context [N2Bv_sized n (Bv2N (N2Bv_sized n ?x) * ?y + ?z)] =>
rewrite <-(N2Bv_sized_add_idemp_l _ _ z);
autorewrite with pull_N2Bv_sized
end;
apply f_equal; lia. }
Qed.
Lemma multiply_is_exp_by_squaring n x l :
exp_by_squaring_spec
(A:=combType (Vec Bit n))
(fun v => N2Bv_sized n (Bv2N v + x))
(fun v => N2Bv_sized n (Bv2N v + Bv2N v))
(N2Bv_sized n 0) l
= N2Bv_sized n (x * from_stream l).
Proof.
rewrite multiply_is_exp_by_squaring'.
rewrite Bv2N_N2Bv_sized_modulo, N.mod_0_l
by (apply N.pow_nonzero; lia).
f_equal; lia.
Qed.
(*|
With that, we have all we need to prove ``stream_multiply`` is always correct!
|*)
Lemma stream_multiply_correct n x (input : list bool) :
simulate (stream_multiply (n:=n) x) input
= map_stream
(fun i => N2Bv_sized n (x * (from_stream i)))
input.
Proof.
intros; cbv [stream_multiply].
rewrite @exp_by_squaring_correct
with (A:=Vec Bit n)
(mul_spec:=fun v => N2Bv_sized n (Bv2N v + x))
(square_spec := fun v => N2Bv_sized n (Bv2N v + Bv2N v))
by first [ solve [apply double_step]
| cbn [circuit_state step]; intros; simpl_ident;
lazymatch goal with x : unit |- _ => destruct x end;
rewrite N2Bv_sized_add_idemp_r; reflexivity ].
apply map_ext; intros. simpl_ident.
apply multiply_is_exp_by_squaring.
Qed.
(*|
Now, let's move on to ``stream_exponentiate``. We'll need to prove that
``mul_constN`` is correct first, and to prove that we'll need a proof for
``mul_const_pos``. This proof goes by induction on ``x``:
|*)
Lemma mul_const_pos_step n x st i :
step (mul_const_pos x) st i = (st, N2Bv_sized n (Bv2N i * Npos x)).
Proof.
revert st i.
induction x; cbn [mul_const_pos circuit_state];
intros; destruct_products;
repeat lazymatch goal with x : unit |- _ => destruct x end.
{ (* x = y~1 *)
cbn [step]. repeat (destruct_pair_let; cbn [fst snd]).
simpl_ident. rewrite double_step, IHx. cbn [fst snd].
f_equal; [ ].
autorewrite with pull_N2Bv_sized.
repeat lazymatch goal with
| |- context
[N2Bv_sized n (Bv2N (N2Bv_sized n ?x) + ?y + ?z)] =>
replace (Bv2N (N2Bv_sized n x) + y + z)%N
with (y + z + Bv2N (N2Bv_sized n x))%N by lia;
autorewrite with pull_N2Bv_sized
end.
f_equal; lia. }
{ (* x = y~0 *)
cbn [step]. repeat (destruct_pair_let; cbn [fst snd]).
simpl_ident. rewrite double_step, IHx. cbn [fst snd].
f_equal; [ ].
autorewrite with pull_N2Bv_sized.
f_equal; lia. }
{ (* x = 1 *)
cbn [step]. simpl_ident.
rewrite N.mul_1_r, N2Bv_sized_Bv2N.
reflexivity. }
Qed.
Lemma mul_constN_step n x st i :
step (mul_constN x) st i = (st, N2Bv_sized n (Bv2N i * x)).
Proof.
cbv [mul_constN].
destruct x; [ | apply mul_const_pos_step ].
(* remaining case : x = 0 *)
cbn [step]. destruct st. simpl_ident.
rewrite N.mul_0_r. reflexivity.
Qed.
(*|
Just like we did for ``stream_multiply``, we prove that exponentiation matches
``exp_by_squaring_spec`` - first for any start value, and then for a start value
of 1.
|*)
Lemma exponentiate_is_exp_by_squaring' n x l start :
exp_by_squaring_spec
(A:=combType (Vec Bit n))
(fun v => N2Bv_sized n (Bv2N v * x))
(fun v => N2Bv_sized n (Bv2N v * Bv2N v))
start l
= N2Bv_sized n (Bv2N start ^ (2 ^ N.of_nat (length l))
* x ^ from_stream l).
Proof.
cbv [exp_by_squaring_spec].
revert start; induction l.
{ intros; cbn - [N.pow].
rewrite !N.pow_0_r, N.pow_1_r, N.mul_1_r.
rewrite N2Bv_sized_Bv2N; reflexivity. }
{ intros. cbn [fold_left]. rewrite IHl.
rewrite from_stream_cons.
cbn [length]. rewrite Nat2N.inj_succ, N.pow_succ_r'.
destruct_one_match;
rewrite ?N.add_0_l;
autorewrite with pull_N2Bv_sized;
rewrite ?N.pow_mul_r, ?N.pow_add_r;
lazymatch goal with
| |- context [N2Bv_sized n (Bv2N (N2Bv_sized n ?x) ^ ?y * ?z)] =>
rewrite <-(N2Bv_sized_mul_idemp_l _ _ z);
autorewrite with pull_N2Bv_sized
end;
rewrite ?N.pow_2_r, ?N.pow_mul_l;
apply f_equal; lia. }
Qed.
Lemma exponentiation_is_exp_by_squaring n x l :
exp_by_squaring_spec
(A:=combType (Vec Bit n))
(fun v => N2Bv_sized n (Bv2N v * x))
(fun v => N2Bv_sized n (Bv2N v * Bv2N v))
(N2Bv_sized n 1) l
= N2Bv_sized n (x ^ from_stream l).
Proof.
rewrite exponentiate_is_exp_by_squaring'.
assert (2 ^ N.of_nat (length l) <> 0)%N
by (apply N.pow_nonzero; lia).
rewrite Bv2N_N2Bv_sized_modulo by lia.
destruct n; [ apply nil_eq | ].
rewrite N.mod_1_l by (apply N.pow_gt_1; lia).
rewrite N.pow_1_l.
f_equal; lia.
Qed.
(*|
And now we can prove ``stream_exponentiate`` is always correct!
|*)
Lemma stream_exponentiate_correct n x (input : list bool) :
simulate (stream_exponentiate (n:=n) x) input
= map_stream
(fun i => N2Bv_sized n (x ^ (from_stream i)))
input.
Proof.
intros; cbv [stream_exponentiate].
rewrite @exp_by_squaring_correct
with (A:=Vec Bit n)
(mul_spec:=fun v => N2Bv_sized n (Bv2N v * x))
(square_spec := fun v => N2Bv_sized n (Bv2N v * Bv2N v))
by first [ solve [apply mul_constN_step]
| cbn [circuit_state step]; intros; simpl_ident;
lazymatch goal with x : unit |- _ => destruct x end;
reflexivity ].
apply map_ext; intros. simpl_ident.
apply exponentiation_is_exp_by_squaring.
Qed.
(*|
Thanks for bearing with us through the end! For questions, comments, and
contributions, contact us on our GitHub repo_.
.. _reference: ../reference
.. _repo: https://github.com/project-oak/silveroak
.. _tutorial: tutorial
.. _source: https://github.com/project-oak/silveroak/blob/main/demos/ExpBySquaring.v
.. _wikipedia: https://en.wikipedia.org/wiki/Exponentiation_by_squaring
|*)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR4_BEHAVIORAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_BEHAVIORAL_V |
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_seq_wrapper (
// dss ports
phy_clk_1x,
reset_phy_clk_1x_n,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
ctl_cal_req,
int_RANK_HAS_ADDR_SWAP,
ctl_cal_byte_lane_sel_n,
seq_pll_inc_dec_n,
seq_pll_start_reconfig,
seq_pll_select,
phs_shft_busy,
pll_resync_clk_index,
pll_measure_clk_index,
sc_clk_dp,
scan_enable_dqs_config,
scan_update,
scan_din,
scan_enable_ck,
scan_enable_dqs,
scan_enable_dqsn,
scan_enable_dq,
scan_enable_dm,
hr_rsc_clk,
seq_ac_addr,
seq_ac_ba,
seq_ac_cas_n,
seq_ac_ras_n,
seq_ac_we_n,
seq_ac_cke,
seq_ac_cs_n,
seq_ac_odt,
seq_ac_rst_n,
seq_ac_sel,
seq_mem_clk_disable,
ctl_add_1t_ac_lat_internal,
ctl_add_1t_odt_lat_internal,
ctl_add_intermediate_regs_internal,
seq_rdv_doing_rd,
seq_rdp_reset_req_n,
seq_rdp_inc_read_lat_1x,
seq_rdp_dec_read_lat_1x,
ctl_rdata,
int_rdata_valid_1t,
seq_rdata_valid_lat_inc,
seq_rdata_valid_lat_dec,
ctl_rlat,
seq_poa_lat_dec_1x,
seq_poa_lat_inc_1x,
seq_poa_protection_override_1x,
seq_oct_oct_delay,
seq_oct_oct_extend,
seq_oct_val,
seq_wdp_dqs_burst,
seq_wdp_wdata_valid,
seq_wdp_wdata,
seq_wdp_dm,
seq_wdp_dqs,
seq_wdp_ovride,
seq_dqs_add_2t_delay,
ctl_wlat,
seq_mmc_start,
mmc_seq_done,
mmc_seq_value,
mem_err_out_n,
parity_error_n,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
//Inserted Generics
localparam SPEED_GRADE = "C5";
localparam MEM_IF_DQS_WIDTH = 4;
localparam MEM_IF_DWIDTH = 32;
localparam MEM_IF_DM_WIDTH = 4;
localparam MEM_IF_DQ_PER_DQS = 8;
localparam DWIDTH_RATIO = 4;
localparam CLOCK_INDEX_WIDTH = 3;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_ADDR_WIDTH = 14;
localparam MEM_IF_BANKADDR_WIDTH = 3;
localparam MEM_IF_CS_WIDTH = 1;
localparam RESYNCHRONISE_AVALON_DBG = 0;
localparam DBG_A_WIDTH = 13;
localparam DQS_PHASE_SETTING = 2;
localparam SCAN_CLK_DIVIDE_BY = 2;
localparam PLL_STEPS_PER_CYCLE = 32;
localparam MEM_IF_CLK_PS = 3333;
localparam DQS_DELAY_CTL_WIDTH = 6;
localparam MEM_IF_MEMTYPE = "DDR3";
localparam RANK_HAS_ADDR_SWAP = 0;
localparam MEM_IF_MR_0 = 4673;
localparam MEM_IF_MR_1 = 70;
localparam MEM_IF_MR_2 = 8;
localparam MEM_IF_MR_3 = 0;
localparam MEM_IF_OCT_EN = 0;
localparam IP_BUILDNUM = 0;
localparam FAMILY = "Arria II GX";
localparam FAMILYGROUP_ID = 4;
localparam MEM_IF_ADDR_CMD_PHASE = 90;
localparam CAPABILITIES = 0;
localparam WRITE_DESKEW_T10 = 0;
localparam WRITE_DESKEW_HC_T10 = 6;
localparam WRITE_DESKEW_T9NI = 0;
localparam WRITE_DESKEW_HC_T9NI = 6;
localparam WRITE_DESKEW_T9I = 0;
localparam WRITE_DESKEW_HC_T9I = 0;
localparam WRITE_DESKEW_RANGE = 0;
localparam IOE_PHASES_PER_TCK = 10;
localparam ADV_LAT_WIDTH = 5;
localparam RDP_ADDR_WIDTH = 4;
localparam IOE_DELAYS_PER_PHS = 5;
localparam SINGLE_DQS_DELAY_CONTROL_CODE = 0;
localparam PRESET_RLAT = 0;
localparam FORCE_HC = 0;
localparam MEM_IF_DQS_CAPTURE_EN = 1;
localparam REDUCE_SIM_TIME = 0;
localparam TINIT_TCK = 75008;
localparam TINIT_RST = 30004;
localparam GENERATE_ADDITIONAL_DBG_RTL = 0;
localparam MEM_IF_CS_PER_RANK = 1;
localparam MEM_IF_RANKS_PER_SLOT = 1;
localparam CHIP_OR_DIMM = "Discrete Device";
localparam RDIMM_CONFIG_BITS = "0000000000000000000000000000000000000000000000000000000000000000";
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
localparam GENERATE_TRACKING_PHASE_STORE = 0;
// note that num_ranks if the number of discrete chip select signals output from the sequencer
// cs_width is the total number of chip selects which go from the phy to the memory (there can
// be more than one chip select per rank).
localparam MEM_IF_NUM_RANKS = MEM_IF_CS_WIDTH/MEM_IF_CS_PER_RANK;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
input wire ctl_cal_req;
input wire [MEM_IF_NUM_RANKS - 1 : 0] int_RANK_HAS_ADDR_SWAP;
input wire [MEM_IF_NUM_RANKS * MEM_IF_DQS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
output wire seq_pll_inc_dec_n;
output wire seq_pll_start_reconfig;
output wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
input wire phs_shft_busy;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
input wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
output [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs_config;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_update;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_din;
output wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] scan_enable_ck;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqs;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] scan_enable_dqsn;
output wire [MEM_IF_DWIDTH - 1 : 0] scan_enable_dq;
output wire [MEM_IF_DM_WIDTH - 1 : 0] scan_enable_dm;
input wire hr_rsc_clk;
output wire [(DWIDTH_RATIO/2) * MEM_IF_ADDR_WIDTH - 1 : 0] seq_ac_addr;
output wire [(DWIDTH_RATIO/2) * MEM_IF_BANKADDR_WIDTH - 1 : 0] seq_ac_ba;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_cas_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_ras_n;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_we_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_cke;
output wire [(DWIDTH_RATIO/2) * MEM_IF_CS_WIDTH - 1 : 0] seq_ac_cs_n;
output wire [(DWIDTH_RATIO/2) * MEM_IF_NUM_RANKS - 1 : 0] seq_ac_odt;
output wire [(DWIDTH_RATIO/2) - 1 : 0] seq_ac_rst_n;
output wire seq_ac_sel;
output wire seq_mem_clk_disable;
output wire ctl_add_1t_ac_lat_internal;
output wire ctl_add_1t_odt_lat_internal;
output wire ctl_add_intermediate_regs_internal;
output wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_rdv_doing_rd;
output wire seq_rdp_reset_req_n;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_inc_read_lat_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_rdp_dec_read_lat_1x;
input wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] ctl_rdata;
input wire [DWIDTH_RATIO/2 - 1 : 0] int_rdata_valid_1t;
output wire seq_rdata_valid_lat_inc;
output wire seq_rdata_valid_lat_dec;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_rlat;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_dec_1x;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_poa_lat_inc_1x;
output wire seq_poa_protection_override_1x;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay;
output wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend;
output wire seq_oct_val;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_dqs_burst;
output wire [(DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH - 1 : 0] seq_wdp_wdata_valid;
output wire [DWIDTH_RATIO * MEM_IF_DWIDTH - 1 : 0] seq_wdp_wdata;
output wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0] seq_wdp_dm;
output wire [DWIDTH_RATIO - 1 : 0] seq_wdp_dqs;
output wire seq_wdp_ovride;
output wire [MEM_IF_DQS_WIDTH - 1 : 0] seq_dqs_add_2t_delay;
output wire [ADV_LAT_WIDTH - 1 : 0] ctl_wlat;
output wire seq_mmc_start;
input wire mmc_seq_done;
input wire mmc_seq_value;
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH - 1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [ 31 : 0] dbg_wr_data;
output wire [ 31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
input wire mem_err_out_n;
output wire parity_error_n;
(* altera_attribute = "-name global_signal off" *) wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// instantiate the deskew (DDR3) or non-deskew (DDR/DDR2/DDR3) sequencer:
//
ddr3_int_phy_alt_mem_phy_seq #(
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.DWIDTH_RATIO (DWIDTH_RATIO),
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_ADDR_WIDTH (MEM_IF_ADDR_WIDTH),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_NUM_RANKS (MEM_IF_NUM_RANKS),
.MEM_IF_RANKS_PER_SLOT (MEM_IF_RANKS_PER_SLOT),
.ADV_LAT_WIDTH (ADV_LAT_WIDTH),
.RESYNCHRONISE_AVALON_DBG (RESYNCHRONISE_AVALON_DBG),
.AV_IF_ADDR_WIDTH (DBG_A_WIDTH),
.NOM_DQS_PHASE_SETTING (DQS_PHASE_SETTING),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.RDP_ADDR_WIDTH (RDP_ADDR_WIDTH),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE),
.IOE_PHASES_PER_TCK (IOE_PHASES_PER_TCK),
.IOE_DELAYS_PER_PHS (IOE_DELAYS_PER_PHS),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.PHY_DEF_MR_1ST (MEM_IF_MR_0),
.PHY_DEF_MR_2ND (MEM_IF_MR_1),
.PHY_DEF_MR_3RD (MEM_IF_MR_2),
.PHY_DEF_MR_4TH (MEM_IF_MR_3),
.MEM_IF_DQSN_EN (0),
.MEM_IF_DQS_CAPTURE_EN (MEM_IF_DQS_CAPTURE_EN),
.FAMILY (FAMILY),
.FAMILYGROUP_ID (FAMILYGROUP_ID),
.SPEED_GRADE (SPEED_GRADE),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.WRITE_DESKEW_T10 (WRITE_DESKEW_T10),
.WRITE_DESKEW_HC_T10 (WRITE_DESKEW_HC_T10),
.WRITE_DESKEW_T9NI (WRITE_DESKEW_T9NI),
.WRITE_DESKEW_HC_T9NI (WRITE_DESKEW_HC_T9NI),
.WRITE_DESKEW_T9I (WRITE_DESKEW_T9I),
.WRITE_DESKEW_HC_T9I (WRITE_DESKEW_HC_T9I),
.WRITE_DESKEW_RANGE (WRITE_DESKEW_RANGE),
.SINGLE_DQS_DELAY_CONTROL_CODE (SINGLE_DQS_DELAY_CONTROL_CODE),
.PRESET_RLAT (PRESET_RLAT),
.EN_OCT (MEM_IF_OCT_EN),
.SIM_TIME_REDUCTIONS (REDUCE_SIM_TIME),
.FORCE_HC (FORCE_HC),
.CAPABILITIES (CAPABILITIES),
.GENERATE_ADDITIONAL_DBG_RTL (GENERATE_ADDITIONAL_DBG_RTL),
.TINIT_TCK (TINIT_TCK),
.TINIT_RST (TINIT_RST),
.GENERATE_TRACKING_PHASE_STORE (0),
.OCT_LAT_WIDTH (OCT_LAT_WIDTH),
.IP_BUILDNUM (IP_BUILDNUM),
.CHIP_OR_DIMM (CHIP_OR_DIMM),
.RDIMM_CONFIG_BITS (RDIMM_CONFIG_BITS)
) seq_inst (
.clk (phy_clk_1x),
.rst_n (reset_phy_clk_1x_n),
.ctl_init_success (ctl_cal_success),
.ctl_init_fail (ctl_cal_fail),
.ctl_init_warning (ctl_cal_warning),
.ctl_recalibrate_req (ctl_cal_req),
.MEM_AC_SWAPPED_RANKS (int_RANK_HAS_ADDR_SWAP),
.ctl_cal_byte_lanes (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.seq_pll_phs_shift_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.seq_scan_clk (sc_clk_dp),
.seq_scan_enable_dqs_config (scan_enable_dqs_config),
.seq_scan_update (scan_update),
.seq_scan_din (scan_din),
.seq_scan_enable_ck (scan_enable_ck),
.seq_scan_enable_dqs (scan_enable_dqs),
.seq_scan_enable_dqsn (scan_enable_dqsn),
.seq_scan_enable_dq (scan_enable_dq),
.seq_scan_enable_dm (scan_enable_dm),
.hr_rsc_clk (hr_rsc_clk),
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.seq_ac_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.seq_ac_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.seq_ac_add_2t (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_rdv_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.rdata (ctl_rdata),
.rdata_valid (int_rdata_valid_1t),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_value (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.seq_ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (mem_err_out_n),
.parity_error_n (parity_error_n),
.dbg_seq_clk (dbg_clk),
.dbg_seq_rst_n (dbg_reset_n),
.dbg_seq_addr (dbg_addr),
.dbg_seq_wr (dbg_wr),
.dbg_seq_rd (dbg_rd),
.dbg_seq_cs (dbg_cs),
.dbg_seq_wr_data (dbg_wr_data),
.seq_dbg_rd_data (dbg_rd_data),
.seq_dbg_waitrequest (dbg_waitrequest)
);
endmodule
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : spi_interface
// Author : Caleb Fangmeier
// Description : Implementation of a generic SPI interface.
// Interfacing HDL must supply the exact data to be written
// over the interface (including write/read bit and address)
// properly formatted for the device being spoken to.
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module spi_interface (
input wire clk, // 150 MHz
input wire reset,
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//--------------------------------------------------------------------------
input wire [31:0] data_out,
output reg [31:0] data_in,
input wire [7:0] read_bits,
input wire [7:0] write_bits,
input wire request_action,
output wire busy,
//--------------------------------------------------------------------------
//-----------HARDWARE INTERFACE---------------------------------------------
//--------------------------------------------------------------------------
output wire sclk,
inout wire sdio,
output reg cs
);
//----------------------------------------------------------------------------
// Parameters
//----------------------------------------------------------------------------
localparam IDLE = 3'd0,
DATA_WRITE_0 = 3'd1,
DATA_WRITE = 3'd2,
DATA_READ_0 = 3'd3,
DATA_READ = 3'd4;
localparam CLK_DIV = 3;
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire update_in; // Read-in on positive edge of clock
wire update_out; // Write-out on negative edge of clk
wire sdo;
//----------------------------------------------------------------------------
// Registers
//----------------------------------------------------------------------------
reg [CLK_DIV:0] clk_div1;
reg [CLK_DIV:0] clk_div2;
reg [31:0] input_shifter;
reg [31:0] output_shifter;
reg [7:0] read_bits_reg;
reg [7:0] write_bits_reg;
reg [8:0] bit_counter;
reg is_writing;
reg busy_int;
reg [2:0] state;
//----------------------------------------------------------------------------
// Assignments
//----------------------------------------------------------------------------
assign update_in = clk_div1[CLK_DIV] & ~clk_div2[CLK_DIV]; // posedge serial clock
assign update_out = ~clk_div1[CLK_DIV] & clk_div2[CLK_DIV]; // negedge serial clock
assign sdo = output_shifter[31];
assign sclk = clk_div2[CLK_DIV] & cs;
assign sdio = is_writing ? sdo : 1'bz;
assign busy = busy_int | request_action;
//----------------------------------------------------------------------------
// Clock Division
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
clk_div2 <= 0;
clk_div1 <= 0;
end
else begin
clk_div2 <= clk_div1;
clk_div1 <= clk_div1 + 1;
end
end
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
always @( posedge clk ) begin
if ( reset ) begin
state <= IDLE;
data_in <= 32'd0;
busy_int <= 1;
is_writing <= 0;
cs <= 0;
end
else begin
case ( state )
IDLE: begin
data_in <= 32'd0;
if ( request_action ) begin
state <= DATA_WRITE_0;
busy_int <= 1;
output_shifter <= data_out;
input_shifter <= 32'd0;
write_bits_reg <= write_bits;
read_bits_reg <= read_bits;
end
else begin
busy_int <= 1'd0;
end
end
DATA_WRITE_0: begin
if ( update_out ) begin
state <= DATA_WRITE;
is_writing <= 1'd1;
cs <= 1'd1;
bit_counter <= 9'd1;
end
end
DATA_WRITE: begin
if ( update_out ) begin
if ( bit_counter == write_bits_reg ) begin
state <= DATA_READ;
bit_counter <= 9'd0;
is_writing <= 1'd0;
end
else begin
bit_counter <= bit_counter + 9'd1;
output_shifter <= {output_shifter[30:0], 1'd0};
end
end
end
DATA_READ: begin
if ( update_in ) begin
if ( bit_counter == read_bits_reg ) begin
state <= IDLE;
busy_int <= 1'd0;
cs <= 1'd0;
data_in <= input_shifter;
end
else begin
bit_counter <= bit_counter + 9'd1;
input_shifter <= {input_shifter[30:0], sdio};
end
end
end
endcase
end
end
endmodule
|
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
module hi_iso14443a(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
reg ssp_clk;
reg ssp_frame;
reg fc_div_2;
always @(posedge ck_1356meg)
fc_div_2 = ~fc_div_2;
wire adc_clk;
assign adc_clk = ck_1356meg;
reg after_hysteresis, after_hysteresis_prev1, after_hysteresis_prev2, after_hysteresis_prev3;
reg [11:0] has_been_low_for;
reg [8:0] saw_deep_modulation;
reg [2:0] deep_counter;
reg deep_modulation;
always @(negedge adc_clk)
begin
if(& adc_d[7:6]) after_hysteresis <= 1'b1; // if adc_d >= 196
else if(~(| adc_d[7:4])) after_hysteresis <= 1'b0; // if adc_d <= 15
if(~(| adc_d[7:0]))
begin
if(deep_counter == 3'd7)
begin
deep_modulation <= 1'b1;
saw_deep_modulation <= 8'd0;
end
else
deep_counter <= deep_counter + 1;
end
else
begin
deep_counter <= 3'd0;
if(saw_deep_modulation == 8'd255)
deep_modulation <= 1'b0;
else
saw_deep_modulation <= saw_deep_modulation + 1;
end
if(after_hysteresis)
begin
has_been_low_for <= 7'b0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
has_been_low_for <= has_been_low_for + 1;
end
end
// Report every 4 subcarrier cycles
// 64 periods of carrier frequency => 6-bit counter [negedge_cnt]
reg [5:0] negedge_cnt;
reg bit1, bit2, bit3;
reg [3:0] count_ones;
reg [3:0] count_zeros;
// wire [7:0] avg;
// reg [7:0] lavg;
// reg signed [12:0] step1;
// reg signed [12:0] step2;
// reg [7:0] stepsize;
reg [7:0] rx_mod_edge_threshold;
reg curbit;
// reg [12:0] average;
// wire signed [9:0] dif;
// storage for two previous samples:
reg [7:0] adc_d_1;
reg [7:0] adc_d_2;
reg [7:0] adc_d_3;
reg [7:0] adc_d_4;
// the filtered signal (filter performs noise reduction and edge detection)
// (gaussian derivative)
wire signed [10:0] adc_d_filtered;
assign adc_d_filtered = (adc_d_4 << 1) + adc_d_3 - adc_d_1 - (adc_d << 1);
// Registers to store steepest edges detected:
reg [7:0] rx_mod_falling_edge_max;
reg [7:0] rx_mod_rising_edge_max;
// A register to send the results to the arm
reg signed [7:0] to_arm;
reg bit_to_arm;
reg fdt_indicator, fdt_elapsed;
reg [10:0] fdt_counter;
reg [47:0] mod_sig_buf;
wire mod_sig_buf_empty;
reg [5:0] mod_sig_ptr;
reg [3:0] mod_sig_flip;
reg mod_sig, mod_sig_coil;
reg temp_buffer_reset;
reg sendbit;
assign mod_sig_buf_empty = ~(|mod_sig_buf[47:0]);
reg [2:0] ssp_frame_counter;
// ADC data appears on the rising edge, so sample it on the falling edge
always @(negedge adc_clk)
begin
// ------------------------------------------------------------------------------------------------------------------------------------------------------------------
// relevant for TAGSIM_MOD only. Timing of Tag's answer to a command received from a reader
// ISO14443-3 specifies:
// fdt = 1172, if last bit was 0.
// fdt = 1236, if last bit was 1.
// the FPGA takes care for the 1172 delay. To achieve the additional 1236-1172=64 ticks delay, the ARM must send an additional correction bit (before the start bit).
// The correction bit will be coded as 00010000, i.e. it adds 4 bits to the transmission stream, causing the required delay.
if(fdt_counter == 11'd740) fdt_indicator = 1'b1; // fdt_indicator is true for 740 <= fdt_counter <= 1148. Ready to buffer data. (?)
// Shouldn' this be 1236 - 720 = 516? (The mod_sig_buf can buffer 46 data bits,
// i.e. a maximum delay of 46 * 16 = 720 adc_clk ticks)
if(fdt_counter == 11'd1148) // additional 16 (+ eventual n*128) adc_clk_ticks delay will be added by the mod_sig_buf below
// the remaining 8 ticks delay comes from the 8 ticks timing difference between reseting fdt_counter and the mod_sig_buf clock.
begin
if(fdt_elapsed)
begin
if(negedge_cnt[3:0] == mod_sig_flip[3:0]) mod_sig_coil <= mod_sig; // start modulating (if mod_sig is already set)
end
else
begin
mod_sig_flip[3:0] <= negedge_cnt[3:0]; // exact timing of modulation
mod_sig_coil <= mod_sig; // modulate (if mod_sig is already set)
fdt_elapsed = 1'b1;
fdt_indicator = 1'b0;
if(~(| mod_sig_ptr[5:0])) mod_sig_ptr <= 6'b001001; // didn't receive a 1 yet. Delay next 1 by n*128 ticks.
else temp_buffer_reset = 1'b1; // else fix the buffer size at current position
end
end
else
begin
fdt_counter <= fdt_counter + 1; // Count until 1148
end
//-------------------------------------------------------------------------------------------------------------------------------------------
// Relevant for READER_LISTEN only
// look for steepest falling and rising edges:
if (adc_d_filtered > 0)
begin
if (adc_d_filtered > rx_mod_falling_edge_max)
rx_mod_falling_edge_max <= adc_d_filtered;
end
else
begin
if (-adc_d_filtered > rx_mod_rising_edge_max)
rx_mod_rising_edge_max <= -adc_d_filtered;
end
// store previous samples for filtering and edge detection:
adc_d_4 <= adc_d_3;
adc_d_3 <= adc_d_2;
adc_d_2 <= adc_d_1;
adc_d_1 <= adc_d;
if(& negedge_cnt[3:0]) // == 0xf == 15
begin
// Relevant for TAGSIM_MOD only (timing Tag's answer. See above)
// When there is a dip in the signal and not in (READER_MOD, READER_LISTEN, TAGSIM_MOD)
if(~after_hysteresis && mod_sig_buf_empty && ~((mod_type == 3'b100) || (mod_type == 3'b011) || (mod_type == 3'b010))) // last condition to prevent reset
begin
fdt_counter <= 11'd0;
fdt_elapsed = 1'b0;
fdt_indicator = 1'b0;
temp_buffer_reset = 1'b0;
mod_sig_ptr <= 6'b000000;
end
// Relevant for READER_LISTEN only
// detect modulation signal: if modulating, there must be a falling and a rising edge ... and vice versa
if (rx_mod_falling_edge_max > 6 && rx_mod_rising_edge_max > 6)
curbit = 1'b1; // modulation
else
curbit = 1'b0; // no modulation
// prepare next edge detection:
rx_mod_rising_edge_max <= 0;
rx_mod_falling_edge_max <= 0;
// What do we communicate to the ARM
if(mod_type == 3'b001) sendbit = after_hysteresis; // TAGSIM_LISTEN
else if(mod_type == 3'b010) // TAGSIM_MOD
begin
if(fdt_counter > 11'd772) sendbit = mod_sig_coil;
else sendbit = fdt_indicator;
end
else if(mod_type == 3'b011) sendbit = curbit; // READER_LISTEN
else sendbit = 1'b0; // READER_MOD, SNIFFER
end
//------------------------------------------------------------------------------------------------------------------------------------------
// Relevant for SNIFFER mode only. Prepare communication to ARM.
if(negedge_cnt == 7'd63)
begin
if(deep_modulation)
begin
to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis,1'b0,1'b0,1'b0,1'b0};
end
else
begin
to_arm <= {after_hysteresis_prev1,after_hysteresis_prev2,after_hysteresis_prev3,after_hysteresis,bit1,bit2,bit3,curbit};
end
negedge_cnt <= 0;
end
else
begin
negedge_cnt <= negedge_cnt + 1;
end
if(negedge_cnt == 6'd15)
begin
after_hysteresis_prev1 <= after_hysteresis;
bit1 <= curbit;
end
if(negedge_cnt == 6'd31)
begin
after_hysteresis_prev2 <= after_hysteresis;
bit2 <= curbit;
end
if(negedge_cnt == 6'd47)
begin
after_hysteresis_prev3 <= after_hysteresis;
bit3 <= curbit;
end
//--------------------------------------------------------------------------------------------------------------------------------------------------------------
// Relevant in TAGSIM_MOD only. Delay-Line to buffer data and send it at the correct time
// Note: Data in READER_MOD is fed through this delay line as well.
if(mod_type != 3'b000) // != SNIFFER
begin
if(negedge_cnt[3:0] == 4'b1000) // == 0x8
begin
// The modulation signal of the tag. The delay line is only relevant for TAGSIM_MOD, but used in other modes as well.
// Note: this means that even in READER_MOD, there will be an arbitrary delay depending on the time of a previous reset of fdt_counter and the time and
// content of the next bit to be transmitted.
mod_sig_buf[47:0] <= {mod_sig_buf[46:1], ssp_dout, 1'b0}; // shift in new data starting at mod_sig_buf[1]. mod_sig_buf[0] = 0 always.
if((ssp_dout || (| mod_sig_ptr[5:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt_counter = 1148 adc_clk ticks.
if(mod_sig_ptr == 6'b101110) // buffer overflow at 46 - this would mean data loss
begin
mod_sig_ptr <= 6'b000000;
end
else mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). ptr always points to first 1.
else if(fdt_elapsed && ~temp_buffer_reset)
// fdt_elapsed. If we didn't receive a 1 yet, ptr will be at 9 and not yet fixed. Otherwise temp_buffer_reset will be 1 already.
begin
// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
// at intervals of 8 * 16 = 128 adc_clk ticks intervals (as defined in ISO14443-3)
if(ssp_dout) temp_buffer_reset = 1'b1;
if(mod_sig_ptr == 6'b000010) mod_sig_ptr <= 6'b001001; // still nothing received, need to go for the next interval
else mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
end
else
// mod_sig_ptr and therefore the delay is now fixed until fdt_counter is reset (this can happen in SNIFFER and TAGSIM_LISTEN mode only. Note that SNIFFER
// mode (3'b000) is the default and is active in FPGA_MAJOR_MODE_OFF if no other minor mode is explicitly requested.
begin
// don't modulate with the correction bit (which is sent as 00010000, all other bits will come with at least 2 consecutive 1s)
// side effect: when ptr = 1 it will cancel the first 1 of every block of ones. Note: this would only be the case if we received a 1 just before fdt_elapsed.
if(~mod_sig_buf[mod_sig_ptr-1] && ~mod_sig_buf[mod_sig_ptr+1]) mod_sig = 1'b0;
// finally, do the modulation:
else mod_sig = mod_sig_buf[mod_sig_ptr] & fdt_elapsed;
end
end
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
// Communication to ARM (SSP Clock and data)
// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
if(mod_type == 3'b000)
begin
if(negedge_cnt[2:0] == 3'b100)
ssp_clk <= 1'b0;
if(negedge_cnt[2:0] == 3'b000)
begin
ssp_clk <= 1'b1;
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt != 7'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
if(negedge_cnt[5:4] == 2'b00)
ssp_frame = 1'b1;
else
ssp_frame = 1'b0;
bit_to_arm = to_arm[7];
end
else
//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------
// Communication to ARM (SSP Clock and data)
// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
begin
if(negedge_cnt[3:0] == 4'b1000) ssp_clk <= 1'b0;
if(negedge_cnt[3:0] == 4'b0111)
begin
if(ssp_frame_counter == 3'd7) ssp_frame_counter <= 3'd0;
else ssp_frame_counter <= ssp_frame_counter + 1;
end
if(negedge_cnt[3:0] == 4'b0000)
begin
ssp_clk <= 1'b1;
end
ssp_frame = (ssp_frame_counter == 3'd7);
bit_to_arm = sendbit;
end
end
assign ssp_din = bit_to_arm;
// Modulating carrier (adc_clk/16, for TAGSIM_MOD only). Will be 0 for other modes.
wire modulating_carrier;
assign modulating_carrier = (mod_sig_coil & negedge_cnt[3] & (mod_type == 3'b010)); // in TAGSIM_MOD only. Otherwise always 0.
// for READER_MOD only: drop carrier for mod_sig_coil==1 (pause), READER_LISTEN: carrier always on, others: carrier always off
assign pwr_hi = (ck_1356megb & (((mod_type == 3'b100) & ~mod_sig_coil) || (mod_type == 3'b011)));
// Enable HF antenna drivers:
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by modulating_carrier)
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
assign pwr_oe4 = modulating_carrier;
// This is all LF, so doesn't matter.
assign pwr_oe2 = 1'b0;
assign pwr_lo = 1'b0;
assign dbg = negedge_cnt[3];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a22oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22OI_PP_SYMBOL_V
|
module ADT7310P16LS16L (
(* intersynth_port="Reset_n_i" *)
input Reset_n_i,
(* intersynth_port="Clk_i" *)
input Clk_i,
(* intersynth_port="ReconfModuleIn_s", intersynth_conntype="Bit" *)
input Enable_i,
(* intersynth_port="ReconfModuleIRQs_s", intersynth_conntype="Bit" *)
output CpuIntr_o,
(* intersynth_port="Outputs_o", intersynth_conntype="Bit" *)
output ADT7310CS_n_o,
(* intersynth_port="SPI_DataOut", intersynth_conntype="Byte" *)
input[7:0] SPI_Data_i,
(* intersynth_port="SPI_Write", intersynth_conntype="Bit" *)
output SPI_Write_o,
(* intersynth_port="SPI_ReadNext", intersynth_conntype="Bit" *)
output SPI_ReadNext_o,
(* intersynth_port="SPI_DataIn", intersynth_conntype="Byte" *)
output[7:0] SPI_Data_o,
(* intersynth_port="SPI_FIFOFull", intersynth_conntype="Bit" *)
input SPI_FIFOFull_i,
(* intersynth_port="SPI_FIFOEmpty", intersynth_conntype="Bit" *)
input SPI_FIFOEmpty_i,
(* intersynth_port="SPI_Transmission", intersynth_conntype="Bit" *)
input SPI_Transmission_i,
(* intersynth_param="SPICounterPreset_i", intersynth_conntype="Word" *)
input[15:0] SPICounterPreset_i,
(* intersynth_param="Threshold_i", intersynth_conntype="Word" *)
input[15:0] Threshold_i,
(* intersynth_param="PeriodCounterPreset_i", intersynth_conntype="Word" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_param="SensorValue_o", intersynth_conntype="Word" *)
output[15:0] SensorValue_o,
(* intersynth_port="SPI_CPOL", intersynth_conntype="Bit" *)
output SPI_CPOL_o,
(* intersynth_port="SPI_CPHA", intersynth_conntype="Bit" *)
output SPI_CPHA_o,
(* intersynth_port="SPI_LSBFE", intersynth_conntype="Bit" *)
output SPI_LSBFE_o
);
/* constant value for dynamic signal */
assign SPI_CPOL_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_CPHA_o = 1'b1;
/* constant value for dynamic signal */
assign SPI_LSBFE_o = 1'b0;
(* keep *)
wire SPIFSM_Start_s;
(* keep *)
wire SPIFSM_Done_s;
(* keep *)
wire [7:0] SPIFSM_Byte0_s;
(* keep *)
wire [7:0] SPIFSM_Byte1_s;
SPIFSM #(
.SPPRWidth (4),
.SPRWidth (4),
.DataWidth (8)
) SPIFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
// FSM control
.Start_i (SPIFSM_Start_s),
.Done_o (SPIFSM_Done_s),
.Byte0_o (SPIFSM_Byte0_s),
.Byte1_o (SPIFSM_Byte1_s),
// to/from SPI_Master
.SPI_Transmission_i (SPI_Transmission_i),
.SPI_Write_o (SPI_Write_o),
.SPI_ReadNext_o (SPI_ReadNext_o),
.SPI_Data_o (SPI_Data_o),
.SPI_Data_i (SPI_Data_i),
.SPI_FIFOFull_i (SPI_FIFOFull_i),
.SPI_FIFOEmpty_i (SPI_FIFOEmpty_i),
// to ADT7310
.ADT7310CS_n_o (ADT7310CS_n_o),
// parameters
.ParamCounterPreset_i(SPICounterPreset_i)
);
SensorFSM #(
.DataWidth (8)
) SensorFSM_1 (
.Reset_n_i (Reset_n_i),
.Clk_i (Clk_i),
.Enable_i (Enable_i),
.CpuIntr_o (CpuIntr_o),
.SensorValue_o (SensorValue_o),
.MeasureFSM_Start_o (SPIFSM_Start_s),
.MeasureFSM_Done_i (SPIFSM_Done_s),
.MeasureFSM_Byte0_i (SPIFSM_Byte0_s),
.MeasureFSM_Byte1_i (SPIFSM_Byte1_s),
// parameters
.ParamThreshold_i (Threshold_i),
.ParamCounterPreset_i(PeriodCounterPreset_i)
);
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 208 07/03/2011 SP 1.10 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy (
areset,
inclk0,
c0,
c1,
c2,
c3,
c4,
c5,
c6,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output c3;
output c4;
output c5;
output c6;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [9:0] sub_wire0;
wire sub_wire8;
wire [0:0] sub_wire11 = 1'h0;
wire [3:3] sub_wire7 = sub_wire0[3:3];
wire [6:6] sub_wire6 = sub_wire0[6:6];
wire [4:4] sub_wire5 = sub_wire0[4:4];
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [5:5] sub_wire2 = sub_wire0[5:5];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c5 = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire c4 = sub_wire5;
wire c6 = sub_wire6;
wire c3 = sub_wire7;
wire locked = sub_wire8;
wire sub_wire9 = inclk0;
wire [1:0] sub_wire10 = {sub_wire11, sub_wire9};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire10),
.clk (sub_wire0),
.locked (sub_wire8),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 80,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 213,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 40,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 213,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 40,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 213,
altpll_component.clk2_phase_shift = "235",
altpll_component.clk3_divide_by = 80,
altpll_component.clk3_duty_cycle = 50,
altpll_component.clk3_multiply_by = 213,
altpll_component.clk3_phase_shift = "2817",
altpll_component.clk4_divide_by = 160,
altpll_component.clk4_duty_cycle = 50,
altpll_component.clk4_multiply_by = 213,
altpll_component.clk4_phase_shift = "0",
altpll_component.clk5_divide_by = 80,
altpll_component.clk5_duty_cycle = 50,
altpll_component.clk5_multiply_by = 71,
altpll_component.clk5_phase_shift = "0",
altpll_component.clk6_divide_by = 320,
altpll_component.clk6_duty_cycle = 50,
altpll_component.clk6_multiply_by = 71,
altpll_component.clk6_phase_shift = "0",
altpll_component.inclk0_input_frequency = 10000,
altpll_component.intended_device_family = "Stratix IV",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NO_COMPENSATION",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_fbout = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_USED",
altpll_component.port_clk4 = "PORT_USED",
altpll_component.port_clk5 = "PORT_USED",
altpll_component.port_clk6 = "PORT_USED",
altpll_component.port_clk7 = "PORT_UNUSED",
altpll_component.port_clk8 = "PORT_UNUSED",
altpll_component.port_clk9 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.using_fbmimicbidir_port = "OFF",
altpll_component.width_clock = 10;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "1"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "40"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "40"
// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR4 NUMERIC "160"
// Retrieval info: PRIVATE: DIV_FACTOR5 NUMERIC "80"
// Retrieval info: PRIVATE: DIV_FACTOR6 NUMERIC "320"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE4 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE5 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE6 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "266.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "532.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "532.500000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "266.250000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE4 STRING "133.125000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE5 STRING "88.750000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE6 STRING "22.187500"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "10000.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "ps"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR4 NUMERIC "213"
// Retrieval info: PRIVATE: MULT_FACTOR5 NUMERIC "71"
// Retrieval info: PRIVATE: MULT_FACTOR6 NUMERIC "71"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ4 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ5 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ6 STRING "100.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE4 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE5 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE6 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT4 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT5 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT6 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "235.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "2817.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT4 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT5 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT6 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT4 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT5 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT6 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK5 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK6 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLK3 STRING "1"
// Retrieval info: PRIVATE: USE_CLK4 STRING "1"
// Retrieval info: PRIVATE: USE_CLK5 STRING "1"
// Retrieval info: PRIVATE: USE_CLK6 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "40"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "235"
// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "2817"
// Retrieval info: CONSTANT: CLK4_DIVIDE_BY NUMERIC "160"
// Retrieval info: CONSTANT: CLK4_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK4_MULTIPLY_BY NUMERIC "213"
// Retrieval info: CONSTANT: CLK4_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK5_DIVIDE_BY NUMERIC "80"
// Retrieval info: CONSTANT: CLK5_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK5_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK5_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK6_DIVIDE_BY NUMERIC "320"
// Retrieval info: CONSTANT: CLK6_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK6_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK6_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NO_COMPENSATION"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
// Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
// Retrieval info: USED_PORT: c5 0 0 0 0 OUTPUT_CLK_EXT VCC "c5"
// Retrieval info: USED_PORT: c6 0 0 0 0 OUTPUT_CLK_EXT VCC "c6"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
// Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
// Retrieval info: CONNECT: c5 0 0 0 0 @clk 0 0 1 5
// Retrieval info: CONNECT: c6 0 0 0 0 @clk 0 0 1 6
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ddr3_s4_uniphy_example_sim_ddr3_s4_uniphy_example_sim_e0_if0_p0_pll_memphy_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
// Stupid first CPU.
module SimpleCPU(clk, rst, cur_ins);
// Definitions.
parameter REG_SET_SIZE = 16;
parameter WORD_SIZE = 32;
// Instruction opcodes.
parameter OP_NOP = 32'b00000000000000000000000000000000;
parameter OP_INC = 32'b00000000000000000000000000000001;
parameter OP_DEC = 32'b00000000000000000000000000000010;
// Input ports.
input clk;
input rst;
input [WORD_SIZE-1:0] cur_ins;
// Define the set of registers.
reg [WORD_SIZE-1:0] regs [0:REG_SET_SIZE];
reg [WORD_SIZE-1:0] CPSR;
// Define aliases for the CPU registers.
`define REG_SP regs[13] // Stack pointer.
`define REG_LR regs[14] // Link register.
`define REG_PC regs[15] // Program counter.
// Define aliases for the CPU flags.
`define CPSR_V CPSR[28] // Overflow flag.
`define CPSR_C CPSR[29] // Carry flag.
`define CPSR_Z CPSR[30] // Zero flag.
`define CPSR_N CPSR[31] // Negative/less than flag.
// Local variables.
integer i;
// Advance on each 'clk' tick and reset on each 'rst' tick.
always @(posedge clk or posedge rst) begin
if (rst) begin
$display("Resetting the CPU.");
// Reset the flags register.
CPSR = 0;
// Reset the general purpose registers.
for (i = 0; i < REG_SET_SIZE; i = i + 1)
begin
regs[i] = 0;
end
end
// Increment the program counter.
`REG_PC = `REG_PC + 1;
// Debug: dump the state.
$display("Current state:");
$display(" r0:%8x r1:%8x r2:%8x r3:%8x r4:%8x r5:%8x r6:%8x r7:%8x", regs[0], regs[1], regs[2], regs[3], regs[4], regs[5], regs[6], regs[7]);
$display(" r8:%8x r9:%8x r10:%8x r11:%8x r12:%8x SP:%8x LR:%8x PC:%8x", regs[8], regs[9], regs[10], regs[11], regs[12], regs[13], regs[14], regs[15]);
$display(" cur_ins:%8x", cur_ins);
// Main instruction dispatcher.
case (cur_ins)
// No operation.
OP_NOP:
begin
$display("OP_NOP");
end
// Increment r0.
OP_INC:
begin
$display("OP_INC");
regs[0] = regs[0] + 1;
end
// Decrement r0.
OP_DEC:
begin
$display("OP_DEC");
regs[0] = regs[0] - 1;
end
// Handle unknown opcodes.
default:
begin
$display("Unknown opcode %8x", cur_ins);
end
endcase
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11.06.2017 19:09:50
// Design Name:
// Module Name: ss_a_7seg
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Dec_4b_seg(
input [3:0] NUM,
output reg [7:0] CATODOS
);
always @(*) begin
case(NUM)
4'd0: CATODOS=8'b00000011;
4'd1: CATODOS=8'b10011111;
4'd2: CATODOS=8'b00100101;
4'd3: CATODOS=8'b00001101;
4'd4: CATODOS=8'b10011001;
4'd5: CATODOS=8'b01001001;
4'd6: CATODOS=8'b01000001;
4'd7: CATODOS=8'b00011111;
4'd8: CATODOS=8'b00000001;
4'd9: CATODOS=8'b00011001;
4'd10: CATODOS=8'b00010001;
4'd11: CATODOS=8'b11000001;
4'd12: CATODOS=8'b01100011;
4'd13: CATODOS=8'b10000101;
4'd14: CATODOS=8'b01100001;
4'd15: CATODOS=8'b01110001;
default CATODOS=8'b11111101;
endcase
end
endmodule
|
// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3
// Component : VexRiscv
// Git hash : 665470729d63ff293f82037047a4ab71bed16398
`define Input2Kind_binary_sequential_type [0:0]
`define Input2Kind_binary_sequential_RS 1'b0
`define Input2Kind_binary_sequential_IMM_I 1'b1
`define EnvCtrlEnum_binary_sequential_type [1:0]
`define EnvCtrlEnum_binary_sequential_NONE 2'b00
`define EnvCtrlEnum_binary_sequential_XRET 2'b01
`define EnvCtrlEnum_binary_sequential_ECALL 2'b10
`define BranchCtrlEnum_binary_sequential_type [1:0]
`define BranchCtrlEnum_binary_sequential_INC 2'b00
`define BranchCtrlEnum_binary_sequential_B 2'b01
`define BranchCtrlEnum_binary_sequential_JAL 2'b10
`define BranchCtrlEnum_binary_sequential_JALR 2'b11
`define ShiftCtrlEnum_binary_sequential_type [1:0]
`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00
`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01
`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10
`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11
`define AluBitwiseCtrlEnum_binary_sequential_type [1:0]
`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00
`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01
`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10
`define Src2CtrlEnum_binary_sequential_type [1:0]
`define Src2CtrlEnum_binary_sequential_RS 2'b00
`define Src2CtrlEnum_binary_sequential_IMI 2'b01
`define Src2CtrlEnum_binary_sequential_IMS 2'b10
`define Src2CtrlEnum_binary_sequential_PC 2'b11
`define AluCtrlEnum_binary_sequential_type [1:0]
`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00
`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01
`define AluCtrlEnum_binary_sequential_BITWISE 2'b10
`define Src1CtrlEnum_binary_sequential_type [1:0]
`define Src1CtrlEnum_binary_sequential_RS 2'b00
`define Src1CtrlEnum_binary_sequential_IMU 2'b01
`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10
`define Src1CtrlEnum_binary_sequential_URS1 2'b11
module VexRiscv (
input [31:0] externalResetVector,
input timerInterrupt,
input softwareInterrupt,
input [31:0] externalInterruptArray,
output CfuPlugin_bus_cmd_valid,
input CfuPlugin_bus_cmd_ready,
output [9:0] CfuPlugin_bus_cmd_payload_function_id,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_0,
output [31:0] CfuPlugin_bus_cmd_payload_inputs_1,
input CfuPlugin_bus_rsp_valid,
output CfuPlugin_bus_rsp_ready,
input [31:0] CfuPlugin_bus_rsp_payload_outputs_0,
output reg iBusWishbone_CYC,
output reg iBusWishbone_STB,
input iBusWishbone_ACK,
output iBusWishbone_WE,
output [29:0] iBusWishbone_ADR,
input [31:0] iBusWishbone_DAT_MISO,
output [31:0] iBusWishbone_DAT_MOSI,
output [3:0] iBusWishbone_SEL,
input iBusWishbone_ERR,
output [2:0] iBusWishbone_CTI,
output [1:0] iBusWishbone_BTE,
output dBusWishbone_CYC,
output dBusWishbone_STB,
input dBusWishbone_ACK,
output dBusWishbone_WE,
output [29:0] dBusWishbone_ADR,
input [31:0] dBusWishbone_DAT_MISO,
output [31:0] dBusWishbone_DAT_MOSI,
output [3:0] dBusWishbone_SEL,
input dBusWishbone_ERR,
output [2:0] dBusWishbone_CTI,
output [1:0] dBusWishbone_BTE,
input clk,
input reset
);
wire IBusCachedPlugin_cache_io_flush;
wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isValid;
wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck;
wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved;
wire IBusCachedPlugin_cache_io_cpu_decode_isValid;
wire IBusCachedPlugin_cache_io_cpu_decode_isStuck;
wire IBusCachedPlugin_cache_io_cpu_decode_isUser;
reg IBusCachedPlugin_cache_io_cpu_fill_valid;
wire dataCache_1_io_cpu_execute_isValid;
wire [31:0] dataCache_1_io_cpu_execute_address;
wire dataCache_1_io_cpu_memory_isValid;
wire [31:0] dataCache_1_io_cpu_memory_address;
reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess;
reg dataCache_1_io_cpu_writeBack_isValid;
wire dataCache_1_io_cpu_writeBack_isUser;
wire [31:0] dataCache_1_io_cpu_writeBack_storeData;
wire [31:0] dataCache_1_io_cpu_writeBack_address;
wire dataCache_1_io_cpu_writeBack_fence_SW;
wire dataCache_1_io_cpu_writeBack_fence_SR;
wire dataCache_1_io_cpu_writeBack_fence_SO;
wire dataCache_1_io_cpu_writeBack_fence_SI;
wire dataCache_1_io_cpu_writeBack_fence_PW;
wire dataCache_1_io_cpu_writeBack_fence_PR;
wire dataCache_1_io_cpu_writeBack_fence_PO;
wire dataCache_1_io_cpu_writeBack_fence_PI;
wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM;
wire dataCache_1_io_cpu_flush_valid;
wire dataCache_1_io_mem_cmd_ready;
reg [31:0] _zz_RegFilePlugin_regFile_port0;
reg [31:0] _zz_RegFilePlugin_regFile_port1;
wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data;
wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress;
wire IBusCachedPlugin_cache_io_cpu_decode_error;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling;
wire IBusCachedPlugin_cache_io_cpu_decode_mmuException;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data;
wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss;
wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress;
wire IBusCachedPlugin_cache_io_mem_cmd_valid;
wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address;
wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size;
wire dataCache_1_io_cpu_execute_haltIt;
wire dataCache_1_io_cpu_execute_refilling;
wire dataCache_1_io_cpu_memory_isWrite;
wire dataCache_1_io_cpu_writeBack_haltIt;
wire [31:0] dataCache_1_io_cpu_writeBack_data;
wire dataCache_1_io_cpu_writeBack_mmuException;
wire dataCache_1_io_cpu_writeBack_unalignedAccess;
wire dataCache_1_io_cpu_writeBack_accessError;
wire dataCache_1_io_cpu_writeBack_isWrite;
wire dataCache_1_io_cpu_writeBack_keepMemRspData;
wire dataCache_1_io_cpu_writeBack_exclusiveOk;
wire dataCache_1_io_cpu_flush_ready;
wire dataCache_1_io_cpu_redo;
wire dataCache_1_io_mem_cmd_valid;
wire dataCache_1_io_mem_cmd_payload_wr;
wire dataCache_1_io_mem_cmd_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_payload_size;
wire dataCache_1_io_mem_cmd_payload_last;
wire [51:0] _zz_memory_MUL_LOW;
wire [51:0] _zz_memory_MUL_LOW_1;
wire [51:0] _zz_memory_MUL_LOW_2;
wire [51:0] _zz_memory_MUL_LOW_3;
wire [32:0] _zz_memory_MUL_LOW_4;
wire [51:0] _zz_memory_MUL_LOW_5;
wire [49:0] _zz_memory_MUL_LOW_6;
wire [51:0] _zz_memory_MUL_LOW_7;
wire [49:0] _zz_memory_MUL_LOW_8;
wire [31:0] _zz_execute_SHIFT_RIGHT;
wire [32:0] _zz_execute_SHIFT_RIGHT_1;
wire [32:0] _zz_execute_SHIFT_RIGHT_2;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2;
wire _zz_decode_LEGAL_INSTRUCTION_3;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4;
wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8;
wire _zz_decode_LEGAL_INSTRUCTION_9;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10;
wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13;
wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14;
wire _zz_decode_LEGAL_INSTRUCTION_15;
wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16;
wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17;
wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1;
reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6;
wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc;
wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1;
wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2;
wire [19:0] _zz__zz_2;
wire [11:0] _zz__zz_4;
wire [31:0] _zz__zz_6;
wire [31:0] _zz__zz_6_1;
wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload;
wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code;
wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted;
wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1;
reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2;
wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6;
wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18;
wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33;
wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45;
wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62;
wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94;
wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119;
wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128;
wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132;
wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141;
wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143;
wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156;
wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158;
wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159;
wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160;
wire _zz_RegFilePlugin_regFile_port;
wire _zz_decode_RegFilePlugin_rs1Data;
wire _zz_RegFilePlugin_regFile_port_1;
wire _zz_decode_RegFilePlugin_rs2Data;
wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA;
wire [2:0] _zz__zz_execute_SRC1;
wire [4:0] _zz__zz_execute_SRC1_1;
wire [11:0] _zz__zz_execute_SRC2_3;
wire [31:0] _zz_execute_SrcPlugin_addSub;
wire [31:0] _zz_execute_SrcPlugin_addSub_1;
wire [31:0] _zz_execute_SrcPlugin_addSub_2;
wire [31:0] _zz_execute_SrcPlugin_addSub_3;
wire [31:0] _zz_execute_SrcPlugin_addSub_4;
wire [31:0] _zz_execute_SrcPlugin_addSub_5;
wire [31:0] _zz_execute_SrcPlugin_addSub_6;
wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2;
wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1;
wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2;
wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2;
wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4;
wire _zz_execute_BranchPlugin_branch_src2_6;
wire _zz_execute_BranchPlugin_branch_src2_7;
wire _zz_execute_BranchPlugin_branch_src2_8;
wire [2:0] _zz_execute_BranchPlugin_branch_src2_9;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1;
wire _zz_when;
wire _zz_when_1;
wire [65:0] _zz_writeBack_MulPlugin_result;
wire [65:0] _zz_writeBack_MulPlugin_result_1;
wire [31:0] _zz__zz_decode_RS2_2;
wire [31:0] _zz__zz_decode_RS2_2_1;
wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext;
wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1;
wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator;
wire [32:0] _zz_memory_DivPlugin_div_result_1;
wire [32:0] _zz_memory_DivPlugin_div_result_2;
wire [32:0] _zz_memory_DivPlugin_div_result_3;
wire [32:0] _zz_memory_DivPlugin_div_result_4;
wire [0:0] _zz_memory_DivPlugin_div_result_5;
wire [32:0] _zz_memory_DivPlugin_rs1_2;
wire [0:0] _zz_memory_DivPlugin_rs1_3;
wire [31:0] _zz_memory_DivPlugin_rs2_1;
wire [0:0] _zz_memory_DivPlugin_rs2_2;
wire [9:0] _zz_execute_CfuPlugin_functionsIds_0;
wire [26:0] _zz_iBusWishbone_ADR_1;
wire [51:0] memory_MUL_LOW;
wire writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire execute_CfuPlugin_CFU_IN_FLIGHT;
wire [33:0] memory_MUL_HH;
wire [33:0] execute_MUL_HH;
wire [33:0] execute_MUL_HL;
wire [33:0] execute_MUL_LH;
wire [31:0] execute_MUL_LL;
wire [31:0] execute_SHIFT_RIGHT;
wire [31:0] execute_REGFILE_WRITE_DATA;
wire [31:0] memory_MEMORY_STORE_DATA_RF;
wire [31:0] execute_MEMORY_STORE_DATA_RF;
wire decode_CSR_READ_OPCODE;
wire decode_CSR_WRITE_OPCODE;
wire decode_PREDICTION_HAD_BRANCHED2;
wire decode_SRC2_FORCE_ZERO;
wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
wire decode_CfuPlugin_CFU_ENABLE;
wire decode_IS_RS2_SIGNED;
wire decode_IS_RS1_SIGNED;
wire decode_IS_DIV;
wire memory_IS_MUL;
wire execute_IS_MUL;
wire decode_IS_MUL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1;
wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1;
wire decode_IS_CSR;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1;
wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
wire decode_SRC_LESS_UNSIGNED;
wire decode_MEMORY_MANAGMENT;
wire memory_MEMORY_WR;
wire decode_MEMORY_WR;
wire execute_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_MEMORY_STAGE;
wire decode_BYPASSABLE_EXECUTE_STAGE;
wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1;
wire decode_MEMORY_FORCE_CONSTISTENCY;
wire [31:0] writeBack_FORMAL_PC_NEXT;
wire [31:0] memory_FORMAL_PC_NEXT;
wire [31:0] execute_FORMAL_PC_NEXT;
wire [31:0] decode_FORMAL_PC_NEXT;
wire [31:0] memory_PC;
reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire memory_CfuPlugin_CFU_IN_FLIGHT;
wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND;
wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire execute_CfuPlugin_CFU_ENABLE;
wire execute_IS_RS1_SIGNED;
wire execute_IS_DIV;
wire execute_IS_RS2_SIGNED;
wire memory_IS_DIV;
wire writeBack_IS_MUL;
wire [33:0] writeBack_MUL_HH;
wire [51:0] writeBack_MUL_LOW;
wire [33:0] memory_MUL_HL;
wire [33:0] memory_MUL_LH;
wire [31:0] memory_MUL_LL;
wire execute_CSR_READ_OPCODE;
wire execute_CSR_WRITE_OPCODE;
wire execute_IS_CSR;
wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL;
wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL;
wire [31:0] execute_BRANCH_CALC;
wire execute_BRANCH_DO;
wire [31:0] execute_PC;
wire execute_PREDICTION_HAD_BRANCHED2;
(* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ;
wire execute_BRANCH_COND_RESULT;
wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL;
wire decode_RS2_USE;
wire decode_RS1_USE;
reg [31:0] _zz_decode_RS2;
wire execute_REGFILE_WRITE_VALID;
wire execute_BYPASSABLE_EXECUTE_STAGE;
wire memory_REGFILE_WRITE_VALID;
wire [31:0] memory_INSTRUCTION;
wire memory_BYPASSABLE_MEMORY_STAGE;
wire writeBack_REGFILE_WRITE_VALID;
reg [31:0] decode_RS2;
reg [31:0] decode_RS1;
wire [31:0] memory_SHIFT_RIGHT;
reg [31:0] _zz_decode_RS2_1;
wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL;
wire execute_SRC_LESS_UNSIGNED;
wire execute_SRC2_FORCE_ZERO;
wire execute_SRC_USE_SUB_LESS;
wire [31:0] _zz_execute_SRC2;
wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL;
wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL;
wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL;
wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL;
wire decode_SRC_USE_SUB_LESS;
wire decode_SRC_ADD_ZERO;
wire [31:0] execute_SRC_ADD_SUB;
wire execute_SRC_LESS;
wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL;
wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL;
wire [31:0] execute_SRC2;
wire [31:0] execute_SRC1;
wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL;
wire [31:0] _zz_lastStageRegFileWrite_payload_address;
wire _zz_lastStageRegFileWrite_valid;
reg _zz_1;
wire [31:0] decode_INSTRUCTION_ANTICIPATED;
reg decode_REGFILE_WRITE_VALID;
wire decode_LEGAL_INSTRUCTION;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1;
reg [31:0] _zz_decode_RS2_2;
wire writeBack_MEMORY_WR;
wire [31:0] writeBack_MEMORY_STORE_DATA_RF;
wire [31:0] writeBack_REGFILE_WRITE_DATA;
wire writeBack_MEMORY_ENABLE;
wire [31:0] memory_REGFILE_WRITE_DATA;
wire memory_MEMORY_ENABLE;
wire execute_MEMORY_FORCE_CONSTISTENCY;
wire execute_MEMORY_MANAGMENT;
(* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ;
wire execute_MEMORY_WR;
wire [31:0] execute_SRC_ADD;
wire execute_MEMORY_ENABLE;
wire [31:0] execute_INSTRUCTION;
wire decode_MEMORY_ENABLE;
wire decode_FLUSH_ALL;
reg IBusCachedPlugin_rsp_issueDetected_4;
reg IBusCachedPlugin_rsp_issueDetected_3;
reg IBusCachedPlugin_rsp_issueDetected_2;
reg IBusCachedPlugin_rsp_issueDetected_1;
wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1;
wire [31:0] decode_INSTRUCTION;
reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT;
reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT;
wire [31:0] decode_PC;
wire [31:0] writeBack_PC;
wire [31:0] writeBack_INSTRUCTION;
reg decode_arbitration_haltItself;
reg decode_arbitration_haltByOther;
reg decode_arbitration_removeIt;
wire decode_arbitration_flushIt;
reg decode_arbitration_flushNext;
wire decode_arbitration_isValid;
wire decode_arbitration_isStuck;
wire decode_arbitration_isStuckByOthers;
wire decode_arbitration_isFlushed;
wire decode_arbitration_isMoving;
wire decode_arbitration_isFiring;
reg execute_arbitration_haltItself;
reg execute_arbitration_haltByOther;
reg execute_arbitration_removeIt;
wire execute_arbitration_flushIt;
reg execute_arbitration_flushNext;
reg execute_arbitration_isValid;
wire execute_arbitration_isStuck;
wire execute_arbitration_isStuckByOthers;
wire execute_arbitration_isFlushed;
wire execute_arbitration_isMoving;
wire execute_arbitration_isFiring;
reg memory_arbitration_haltItself;
wire memory_arbitration_haltByOther;
reg memory_arbitration_removeIt;
wire memory_arbitration_flushIt;
wire memory_arbitration_flushNext;
reg memory_arbitration_isValid;
wire memory_arbitration_isStuck;
wire memory_arbitration_isStuckByOthers;
wire memory_arbitration_isFlushed;
wire memory_arbitration_isMoving;
wire memory_arbitration_isFiring;
reg writeBack_arbitration_haltItself;
wire writeBack_arbitration_haltByOther;
reg writeBack_arbitration_removeIt;
reg writeBack_arbitration_flushIt;
reg writeBack_arbitration_flushNext;
reg writeBack_arbitration_isValid;
wire writeBack_arbitration_isStuck;
wire writeBack_arbitration_isStuckByOthers;
wire writeBack_arbitration_isFlushed;
wire writeBack_arbitration_isMoving;
wire writeBack_arbitration_isFiring;
wire [31:0] lastStageInstruction /* verilator public */ ;
wire [31:0] lastStagePc /* verilator public */ ;
wire lastStageIsValid /* verilator public */ ;
wire lastStageIsFiring /* verilator public */ ;
reg IBusCachedPlugin_fetcherHalt;
reg IBusCachedPlugin_incomingInstruction;
wire IBusCachedPlugin_predictionJumpInterface_valid;
(* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ;
reg IBusCachedPlugin_decodePrediction_cmd_hadBranch;
wire IBusCachedPlugin_decodePrediction_rsp_wasWrong;
wire IBusCachedPlugin_pcValids_0;
wire IBusCachedPlugin_pcValids_1;
wire IBusCachedPlugin_pcValids_2;
wire IBusCachedPlugin_pcValids_3;
reg IBusCachedPlugin_decodeExceptionPort_valid;
reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code;
wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr;
wire IBusCachedPlugin_mmuBus_cmd_0_isValid;
wire IBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire IBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire IBusCachedPlugin_mmuBus_rsp_isPaging;
wire IBusCachedPlugin_mmuBus_rsp_allowRead;
wire IBusCachedPlugin_mmuBus_rsp_allowWrite;
wire IBusCachedPlugin_mmuBus_rsp_allowExecute;
wire IBusCachedPlugin_mmuBus_rsp_exception;
wire IBusCachedPlugin_mmuBus_rsp_refilling;
wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire IBusCachedPlugin_mmuBus_end;
wire IBusCachedPlugin_mmuBus_busy;
wire dBus_cmd_valid;
wire dBus_cmd_ready;
wire dBus_cmd_payload_wr;
wire dBus_cmd_payload_uncached;
wire [31:0] dBus_cmd_payload_address;
wire [31:0] dBus_cmd_payload_data;
wire [3:0] dBus_cmd_payload_mask;
wire [2:0] dBus_cmd_payload_size;
wire dBus_cmd_payload_last;
wire dBus_rsp_valid;
wire dBus_rsp_payload_last;
wire [31:0] dBus_rsp_payload_data;
wire dBus_rsp_payload_error;
wire DBusCachedPlugin_mmuBus_cmd_0_isValid;
wire DBusCachedPlugin_mmuBus_cmd_0_isStuck;
wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation;
wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress;
wire DBusCachedPlugin_mmuBus_rsp_isIoAccess;
wire DBusCachedPlugin_mmuBus_rsp_isPaging;
wire DBusCachedPlugin_mmuBus_rsp_allowRead;
wire DBusCachedPlugin_mmuBus_rsp_allowWrite;
wire DBusCachedPlugin_mmuBus_rsp_allowExecute;
wire DBusCachedPlugin_mmuBus_rsp_exception;
wire DBusCachedPlugin_mmuBus_rsp_refilling;
wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation;
wire DBusCachedPlugin_mmuBus_end;
wire DBusCachedPlugin_mmuBus_busy;
reg DBusCachedPlugin_redoBranch_valid;
wire [31:0] DBusCachedPlugin_redoBranch_payload;
reg DBusCachedPlugin_exceptionBus_valid;
reg [3:0] DBusCachedPlugin_exceptionBus_payload_code;
wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr;
wire decodeExceptionPort_valid;
wire [3:0] decodeExceptionPort_payload_code;
wire [31:0] decodeExceptionPort_payload_badAddr;
wire BranchPlugin_jumpInterface_valid;
wire [31:0] BranchPlugin_jumpInterface_payload;
reg BranchPlugin_branchExceptionPort_valid;
wire [3:0] BranchPlugin_branchExceptionPort_payload_code;
wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr;
wire [31:0] CsrPlugin_csrMapping_readDataSignal;
wire [31:0] CsrPlugin_csrMapping_readDataInit;
wire [31:0] CsrPlugin_csrMapping_writeDataSignal;
wire CsrPlugin_csrMapping_allowCsrSignal;
wire CsrPlugin_csrMapping_hazardFree;
wire CsrPlugin_inWfi /* verilator public */ ;
wire CsrPlugin_thirdPartyWake;
reg CsrPlugin_jumpInterface_valid;
reg [31:0] CsrPlugin_jumpInterface_payload;
wire CsrPlugin_exceptionPendings_0;
wire CsrPlugin_exceptionPendings_1;
wire CsrPlugin_exceptionPendings_2;
wire CsrPlugin_exceptionPendings_3;
wire externalInterrupt;
wire contextSwitching;
reg [1:0] CsrPlugin_privilege;
wire CsrPlugin_forceMachineWire;
reg CsrPlugin_selfException_valid;
reg [3:0] CsrPlugin_selfException_payload_code;
wire [31:0] CsrPlugin_selfException_payload_badAddr;
wire CsrPlugin_allowInterrupts;
wire CsrPlugin_allowException;
wire CsrPlugin_allowEbreakException;
wire IBusCachedPlugin_externalFlush;
wire IBusCachedPlugin_jump_pcLoad_valid;
wire [31:0] IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload;
wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3;
wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4;
wire IBusCachedPlugin_fetchPc_output_valid;
wire IBusCachedPlugin_fetchPc_output_ready;
wire [31:0] IBusCachedPlugin_fetchPc_output_payload;
reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ;
reg IBusCachedPlugin_fetchPc_correction;
reg IBusCachedPlugin_fetchPc_correctionReg;
wire IBusCachedPlugin_fetchPc_output_fire;
wire IBusCachedPlugin_fetchPc_corrected;
reg IBusCachedPlugin_fetchPc_pcRegPropagate;
reg IBusCachedPlugin_fetchPc_booted;
reg IBusCachedPlugin_fetchPc_inc;
wire when_Fetcher_l131;
wire IBusCachedPlugin_fetchPc_output_fire_1;
wire when_Fetcher_l131_1;
reg [31:0] IBusCachedPlugin_fetchPc_pc;
wire IBusCachedPlugin_fetchPc_redo_valid;
wire [31:0] IBusCachedPlugin_fetchPc_redo_payload;
reg IBusCachedPlugin_fetchPc_flushed;
wire when_Fetcher_l158;
reg IBusCachedPlugin_iBusRsp_redoFetch;
wire IBusCachedPlugin_iBusRsp_stages_0_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_0_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_0_halt;
wire IBusCachedPlugin_iBusRsp_stages_1_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_1_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_1_halt;
wire IBusCachedPlugin_iBusRsp_stages_2_input_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload;
wire IBusCachedPlugin_iBusRsp_stages_2_output_valid;
wire IBusCachedPlugin_iBusRsp_stages_2_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload;
reg IBusCachedPlugin_iBusRsp_stages_2_halt;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready;
wire IBusCachedPlugin_iBusRsp_flush;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
reg IBusCachedPlugin_iBusRsp_readyForError;
wire IBusCachedPlugin_iBusRsp_output_valid;
wire IBusCachedPlugin_iBusRsp_output_ready;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc;
wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error;
wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
wire IBusCachedPlugin_iBusRsp_output_payload_isRvc;
wire when_Fetcher_l240;
wire when_Fetcher_l320;
reg IBusCachedPlugin_injector_nextPcCalc_valids_0;
wire when_Fetcher_l329;
reg IBusCachedPlugin_injector_nextPcCalc_valids_1;
wire when_Fetcher_l329_1;
reg IBusCachedPlugin_injector_nextPcCalc_valids_2;
wire when_Fetcher_l329_2;
reg IBusCachedPlugin_injector_nextPcCalc_valids_3;
wire when_Fetcher_l329_3;
reg IBusCachedPlugin_injector_nextPcCalc_valids_4;
wire when_Fetcher_l329_4;
wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1;
wire _zz_2;
reg [10:0] _zz_3;
wire _zz_4;
reg [18:0] _zz_5;
reg _zz_6;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload;
reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1;
wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3;
wire iBus_cmd_valid;
wire iBus_cmd_ready;
reg [31:0] iBus_cmd_payload_address;
wire [2:0] iBus_cmd_payload_size;
wire iBus_rsp_valid;
wire [31:0] iBus_rsp_payload_data;
wire iBus_rsp_payload_error;
wire [31:0] _zz_IBusCachedPlugin_rspCounter;
reg [31:0] IBusCachedPlugin_rspCounter;
wire IBusCachedPlugin_s0_tightlyCoupledHit;
reg IBusCachedPlugin_s1_tightlyCoupledHit;
reg IBusCachedPlugin_s2_tightlyCoupledHit;
wire IBusCachedPlugin_rsp_iBusRspOutputHalt;
wire IBusCachedPlugin_rsp_issueDetected;
reg IBusCachedPlugin_rsp_redoFetch;
wire when_IBusCachedPlugin_l239;
wire when_IBusCachedPlugin_l244;
wire when_IBusCachedPlugin_l250;
wire when_IBusCachedPlugin_l256;
wire when_IBusCachedPlugin_l267;
wire dataCache_1_io_mem_cmd_s2mPipe_valid;
reg dataCache_1_io_mem_cmd_s2mPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_payload_last;
reg dataCache_1_io_mem_cmd_rValid;
reg dataCache_1_io_mem_cmd_rData_wr;
reg dataCache_1_io_mem_cmd_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_rData_size;
reg dataCache_1_io_mem_cmd_rData_last;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
reg dataCache_1_io_mem_cmd_s2mPipe_rValid;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address;
reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data;
reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size;
reg dataCache_1_io_mem_cmd_s2mPipe_rData_last;
wire when_Stream_l342;
wire [31:0] _zz_DBusCachedPlugin_rspCounter;
reg [31:0] DBusCachedPlugin_rspCounter;
wire when_DBusCachedPlugin_l303;
wire [1:0] execute_DBusCachedPlugin_size;
reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF;
wire dataCache_1_io_cpu_flush_isStall;
wire when_DBusCachedPlugin_l343;
wire when_DBusCachedPlugin_l359;
wire when_DBusCachedPlugin_l386;
wire when_DBusCachedPlugin_l438;
wire when_DBusCachedPlugin_l458;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2;
wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3;
reg [31:0] writeBack_DBusCachedPlugin_rspShifted;
wire [31:0] writeBack_DBusCachedPlugin_rspRf;
wire [1:0] switch_Misc_l200;
wire _zz_writeBack_DBusCachedPlugin_rspFormated;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1;
wire _zz_writeBack_DBusCachedPlugin_rspFormated_2;
reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3;
reg [31:0] writeBack_DBusCachedPlugin_rspFormated;
wire when_DBusCachedPlugin_l484;
wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6;
wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7;
wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2;
wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2;
wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2;
wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2;
wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2;
wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2;
wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2;
wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
wire when_RegFilePlugin_l63;
wire [4:0] decode_RegFilePlugin_regFileReadAddress1;
wire [4:0] decode_RegFilePlugin_regFileReadAddress2;
wire [31:0] decode_RegFilePlugin_rs1Data;
wire [31:0] decode_RegFilePlugin_rs2Data;
reg lastStageRegFileWrite_valid /* verilator public */ ;
reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ;
reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ;
reg _zz_7;
reg [31:0] execute_IntAluPlugin_bitwise;
reg [31:0] _zz_execute_REGFILE_WRITE_DATA;
reg [31:0] _zz_execute_SRC1;
wire _zz_execute_SRC2_1;
reg [19:0] _zz_execute_SRC2_2;
wire _zz_execute_SRC2_3;
reg [19:0] _zz_execute_SRC2_4;
reg [31:0] _zz_execute_SRC2_5;
reg [31:0] execute_SrcPlugin_addSub;
wire execute_SrcPlugin_less;
wire [4:0] execute_FullBarrelShifterPlugin_amplitude;
reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed;
wire [31:0] execute_FullBarrelShifterPlugin_reversed;
reg [31:0] _zz_decode_RS2_3;
reg HazardSimplePlugin_src0Hazard;
reg HazardSimplePlugin_src1Hazard;
wire HazardSimplePlugin_writeBackWrites_valid;
wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address;
wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data;
reg HazardSimplePlugin_writeBackBuffer_valid;
reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address;
reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data;
wire HazardSimplePlugin_addr0Match;
wire HazardSimplePlugin_addr1Match;
wire when_HazardSimplePlugin_l47;
wire when_HazardSimplePlugin_l48;
wire when_HazardSimplePlugin_l51;
wire when_HazardSimplePlugin_l45;
wire when_HazardSimplePlugin_l57;
wire when_HazardSimplePlugin_l58;
wire when_HazardSimplePlugin_l48_1;
wire when_HazardSimplePlugin_l51_1;
wire when_HazardSimplePlugin_l45_1;
wire when_HazardSimplePlugin_l57_1;
wire when_HazardSimplePlugin_l58_1;
wire when_HazardSimplePlugin_l48_2;
wire when_HazardSimplePlugin_l51_2;
wire when_HazardSimplePlugin_l45_2;
wire when_HazardSimplePlugin_l57_2;
wire when_HazardSimplePlugin_l58_2;
wire when_HazardSimplePlugin_l105;
wire when_HazardSimplePlugin_l108;
wire when_HazardSimplePlugin_l113;
wire execute_BranchPlugin_eq;
wire [2:0] switch_Misc_l200_1;
reg _zz_execute_BRANCH_COND_RESULT;
reg _zz_execute_BRANCH_COND_RESULT_1;
wire _zz_execute_BranchPlugin_missAlignedTarget;
reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1;
wire _zz_execute_BranchPlugin_missAlignedTarget_2;
reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3;
wire _zz_execute_BranchPlugin_missAlignedTarget_4;
reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5;
reg _zz_execute_BranchPlugin_missAlignedTarget_6;
wire execute_BranchPlugin_missAlignedTarget;
reg [31:0] execute_BranchPlugin_branch_src1;
reg [31:0] execute_BranchPlugin_branch_src2;
wire _zz_execute_BranchPlugin_branch_src2;
reg [19:0] _zz_execute_BranchPlugin_branch_src2_1;
wire _zz_execute_BranchPlugin_branch_src2_2;
reg [10:0] _zz_execute_BranchPlugin_branch_src2_3;
wire _zz_execute_BranchPlugin_branch_src2_4;
reg [18:0] _zz_execute_BranchPlugin_branch_src2_5;
wire [31:0] execute_BranchPlugin_branchAdder;
wire when_BranchPlugin_l296;
wire [1:0] CsrPlugin_misa_base;
wire [25:0] CsrPlugin_misa_extensions;
reg [1:0] CsrPlugin_mtvec_mode;
reg [29:0] CsrPlugin_mtvec_base;
reg [31:0] CsrPlugin_mepc;
reg CsrPlugin_mstatus_MIE;
reg CsrPlugin_mstatus_MPIE;
reg [1:0] CsrPlugin_mstatus_MPP;
reg CsrPlugin_mip_MEIP;
reg CsrPlugin_mip_MTIP;
reg CsrPlugin_mip_MSIP;
reg CsrPlugin_mie_MEIE;
reg CsrPlugin_mie_MTIE;
reg CsrPlugin_mie_MSIE;
reg CsrPlugin_mcause_interrupt;
reg [3:0] CsrPlugin_mcause_exceptionCode;
reg [31:0] CsrPlugin_mtval;
reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000;
reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000;
wire _zz_when_CsrPlugin_l952;
wire _zz_when_CsrPlugin_l952_1;
wire _zz_when_CsrPlugin_l952_2;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code;
reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped;
wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1;
wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2;
wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3;
wire when_CsrPlugin_l909;
wire when_CsrPlugin_l909_1;
wire when_CsrPlugin_l909_2;
wire when_CsrPlugin_l909_3;
wire when_CsrPlugin_l922;
reg CsrPlugin_interrupt_valid;
reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ;
reg [1:0] CsrPlugin_interrupt_targetPrivilege;
wire when_CsrPlugin_l946;
wire when_CsrPlugin_l952;
wire when_CsrPlugin_l952_1;
wire when_CsrPlugin_l952_2;
wire CsrPlugin_exception;
wire CsrPlugin_lastStageWasWfi;
reg CsrPlugin_pipelineLiberator_pcValids_0;
reg CsrPlugin_pipelineLiberator_pcValids_1;
reg CsrPlugin_pipelineLiberator_pcValids_2;
wire CsrPlugin_pipelineLiberator_active;
wire when_CsrPlugin_l980;
wire when_CsrPlugin_l980_1;
wire when_CsrPlugin_l980_2;
wire when_CsrPlugin_l985;
reg CsrPlugin_pipelineLiberator_done;
wire when_CsrPlugin_l991;
wire CsrPlugin_interruptJump /* verilator public */ ;
reg CsrPlugin_hadException /* verilator public */ ;
reg [1:0] CsrPlugin_targetPrivilege;
reg [3:0] CsrPlugin_trapCause;
reg [1:0] CsrPlugin_xtvec_mode;
reg [29:0] CsrPlugin_xtvec_base;
wire when_CsrPlugin_l1019;
wire when_CsrPlugin_l1064;
wire [1:0] switch_CsrPlugin_l1068;
reg execute_CsrPlugin_wfiWake;
wire when_CsrPlugin_l1116;
wire execute_CsrPlugin_blockedBySideEffects;
reg execute_CsrPlugin_illegalAccess;
reg execute_CsrPlugin_illegalInstruction;
wire when_CsrPlugin_l1136;
wire when_CsrPlugin_l1137;
wire when_CsrPlugin_l1144;
reg execute_CsrPlugin_writeInstruction;
reg execute_CsrPlugin_readInstruction;
wire execute_CsrPlugin_writeEnable;
wire execute_CsrPlugin_readEnable;
wire [31:0] execute_CsrPlugin_readToWriteData;
wire switch_Misc_l200_2;
reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal;
wire when_CsrPlugin_l1176;
wire when_CsrPlugin_l1180;
wire [11:0] execute_CsrPlugin_csrAddress;
reg execute_MulPlugin_aSigned;
reg execute_MulPlugin_bSigned;
wire [31:0] execute_MulPlugin_a;
wire [31:0] execute_MulPlugin_b;
wire [1:0] switch_MulPlugin_l87;
wire [15:0] execute_MulPlugin_aULow;
wire [15:0] execute_MulPlugin_bULow;
wire [16:0] execute_MulPlugin_aSLow;
wire [16:0] execute_MulPlugin_bSLow;
wire [16:0] execute_MulPlugin_aHigh;
wire [16:0] execute_MulPlugin_bHigh;
wire [65:0] writeBack_MulPlugin_result;
wire when_MulPlugin_l147;
wire [1:0] switch_MulPlugin_l148;
reg [32:0] memory_DivPlugin_rs1;
reg [31:0] memory_DivPlugin_rs2;
reg [64:0] memory_DivPlugin_accumulator;
wire memory_DivPlugin_frontendOk;
reg memory_DivPlugin_div_needRevert;
reg memory_DivPlugin_div_counter_willIncrement;
reg memory_DivPlugin_div_counter_willClear;
reg [5:0] memory_DivPlugin_div_counter_valueNext;
reg [5:0] memory_DivPlugin_div_counter_value;
wire memory_DivPlugin_div_counter_willOverflowIfInc;
wire memory_DivPlugin_div_counter_willOverflow;
reg memory_DivPlugin_div_done;
wire when_MulDivIterativePlugin_l126;
wire when_MulDivIterativePlugin_l126_1;
reg [31:0] memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l128;
wire when_MulDivIterativePlugin_l129;
wire when_MulDivIterativePlugin_l132;
wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted;
wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator;
wire [31:0] memory_DivPlugin_div_stage_0_outRemainder;
wire [31:0] memory_DivPlugin_div_stage_0_outNumerator;
wire when_MulDivIterativePlugin_l151;
wire [31:0] _zz_memory_DivPlugin_div_result;
wire when_MulDivIterativePlugin_l162;
wire _zz_memory_DivPlugin_rs2;
wire _zz_memory_DivPlugin_rs1;
reg [32:0] _zz_memory_DivPlugin_rs1_1;
reg [31:0] externalInterruptArray_regNext;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit;
wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1;
wire execute_CfuPlugin_schedule;
reg execute_CfuPlugin_hold;
reg execute_CfuPlugin_fired;
wire CfuPlugin_bus_cmd_fire;
wire when_CfuPlugin_l171;
wire when_CfuPlugin_l175;
wire [9:0] execute_CfuPlugin_functionsIds_0;
wire _zz_CfuPlugin_bus_cmd_payload_inputs_1;
reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1;
reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
wire CfuPlugin_bus_rsp_rsp_valid;
reg CfuPlugin_bus_rsp_rsp_ready;
wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0;
reg CfuPlugin_bus_rsp_rValid;
reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0;
wire when_CfuPlugin_l208;
wire when_Pipeline_l124;
reg [31:0] decode_to_execute_PC;
wire when_Pipeline_l124_1;
reg [31:0] execute_to_memory_PC;
wire when_Pipeline_l124_2;
reg [31:0] memory_to_writeBack_PC;
wire when_Pipeline_l124_3;
reg [31:0] decode_to_execute_INSTRUCTION;
wire when_Pipeline_l124_4;
reg [31:0] execute_to_memory_INSTRUCTION;
wire when_Pipeline_l124_5;
reg [31:0] memory_to_writeBack_INSTRUCTION;
wire when_Pipeline_l124_6;
reg [31:0] decode_to_execute_FORMAL_PC_NEXT;
wire when_Pipeline_l124_7;
reg [31:0] execute_to_memory_FORMAL_PC_NEXT;
wire when_Pipeline_l124_8;
reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT;
wire when_Pipeline_l124_9;
reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
wire when_Pipeline_l124_10;
reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL;
wire when_Pipeline_l124_11;
reg decode_to_execute_SRC_USE_SUB_LESS;
wire when_Pipeline_l124_12;
reg decode_to_execute_MEMORY_ENABLE;
wire when_Pipeline_l124_13;
reg execute_to_memory_MEMORY_ENABLE;
wire when_Pipeline_l124_14;
reg memory_to_writeBack_MEMORY_ENABLE;
wire when_Pipeline_l124_15;
reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL;
wire when_Pipeline_l124_16;
reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL;
wire when_Pipeline_l124_17;
reg decode_to_execute_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_18;
reg execute_to_memory_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_19;
reg memory_to_writeBack_REGFILE_WRITE_VALID;
wire when_Pipeline_l124_20;
reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
wire when_Pipeline_l124_21;
reg decode_to_execute_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_22;
reg execute_to_memory_BYPASSABLE_MEMORY_STAGE;
wire when_Pipeline_l124_23;
reg decode_to_execute_MEMORY_WR;
wire when_Pipeline_l124_24;
reg execute_to_memory_MEMORY_WR;
wire when_Pipeline_l124_25;
reg memory_to_writeBack_MEMORY_WR;
wire when_Pipeline_l124_26;
reg decode_to_execute_MEMORY_MANAGMENT;
wire when_Pipeline_l124_27;
reg decode_to_execute_SRC_LESS_UNSIGNED;
wire when_Pipeline_l124_28;
reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL;
wire when_Pipeline_l124_29;
reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL;
wire when_Pipeline_l124_30;
reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL;
wire when_Pipeline_l124_31;
reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL;
wire when_Pipeline_l124_32;
reg decode_to_execute_IS_CSR;
wire when_Pipeline_l124_33;
reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL;
wire when_Pipeline_l124_34;
reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL;
wire when_Pipeline_l124_35;
reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL;
wire when_Pipeline_l124_36;
reg decode_to_execute_IS_MUL;
wire when_Pipeline_l124_37;
reg execute_to_memory_IS_MUL;
wire when_Pipeline_l124_38;
reg memory_to_writeBack_IS_MUL;
wire when_Pipeline_l124_39;
reg decode_to_execute_IS_DIV;
wire when_Pipeline_l124_40;
reg execute_to_memory_IS_DIV;
wire when_Pipeline_l124_41;
reg decode_to_execute_IS_RS1_SIGNED;
wire when_Pipeline_l124_42;
reg decode_to_execute_IS_RS2_SIGNED;
wire when_Pipeline_l124_43;
reg decode_to_execute_CfuPlugin_CFU_ENABLE;
wire when_Pipeline_l124_44;
reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
wire when_Pipeline_l124_45;
reg [31:0] decode_to_execute_RS1;
wire when_Pipeline_l124_46;
reg [31:0] decode_to_execute_RS2;
wire when_Pipeline_l124_47;
reg decode_to_execute_SRC2_FORCE_ZERO;
wire when_Pipeline_l124_48;
reg decode_to_execute_PREDICTION_HAD_BRANCHED2;
wire when_Pipeline_l124_49;
reg decode_to_execute_CSR_WRITE_OPCODE;
wire when_Pipeline_l124_50;
reg decode_to_execute_CSR_READ_OPCODE;
wire when_Pipeline_l124_51;
reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_52;
reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF;
wire when_Pipeline_l124_53;
reg [31:0] execute_to_memory_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_54;
reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA;
wire when_Pipeline_l124_55;
reg [31:0] execute_to_memory_SHIFT_RIGHT;
wire when_Pipeline_l124_56;
reg [31:0] execute_to_memory_MUL_LL;
wire when_Pipeline_l124_57;
reg [33:0] execute_to_memory_MUL_LH;
wire when_Pipeline_l124_58;
reg [33:0] execute_to_memory_MUL_HL;
wire when_Pipeline_l124_59;
reg [33:0] execute_to_memory_MUL_HH;
wire when_Pipeline_l124_60;
reg [33:0] memory_to_writeBack_MUL_HH;
wire when_Pipeline_l124_61;
reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_62;
reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
wire when_Pipeline_l124_63;
reg [51:0] memory_to_writeBack_MUL_LOW;
wire when_Pipeline_l151;
wire when_Pipeline_l154;
wire when_Pipeline_l151_1;
wire when_Pipeline_l154_1;
wire when_Pipeline_l151_2;
wire when_Pipeline_l154_2;
wire when_CsrPlugin_l1264;
reg execute_CsrPlugin_csr_3264;
wire when_CsrPlugin_l1264_1;
reg execute_CsrPlugin_csr_768;
wire when_CsrPlugin_l1264_2;
reg execute_CsrPlugin_csr_836;
wire when_CsrPlugin_l1264_3;
reg execute_CsrPlugin_csr_772;
wire when_CsrPlugin_l1264_4;
reg execute_CsrPlugin_csr_773;
wire when_CsrPlugin_l1264_5;
reg execute_CsrPlugin_csr_833;
wire when_CsrPlugin_l1264_6;
reg execute_CsrPlugin_csr_834;
wire when_CsrPlugin_l1264_7;
reg execute_CsrPlugin_csr_835;
wire when_CsrPlugin_l1264_8;
reg execute_CsrPlugin_csr_2816;
wire when_CsrPlugin_l1264_9;
reg execute_CsrPlugin_csr_2944;
wire when_CsrPlugin_l1264_10;
reg execute_CsrPlugin_csr_3008;
wire when_CsrPlugin_l1264_11;
reg execute_CsrPlugin_csr_4032;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11;
reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12;
wire when_CsrPlugin_l1297;
wire when_CsrPlugin_l1302;
reg [2:0] _zz_iBusWishbone_ADR;
wire when_InstructionCache_l239;
reg _zz_iBus_rsp_valid;
reg [31:0] iBusWishbone_DAT_MISO_regNext;
reg [2:0] _zz_dBus_cmd_ready;
wire _zz_dBus_cmd_ready_1;
wire _zz_dBus_cmd_ready_2;
wire _zz_dBus_cmd_ready_3;
wire _zz_dBus_cmd_ready_4;
wire _zz_dBus_cmd_ready_5;
reg _zz_dBus_rsp_valid;
reg [31:0] dBusWishbone_DAT_MISO_regNext;
`ifndef SYNTHESIS
reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string;
reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_string;
reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string;
reg [39:0] decode_ENV_CTRL_string;
reg [39:0] _zz_decode_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_string;
reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string;
reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string;
reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string;
reg [71:0] decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string;
reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string;
reg [39:0] decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string;
reg [23:0] decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string;
reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string;
reg [63:0] decode_ALU_CTRL_string;
reg [63:0] _zz_decode_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_string;
reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string;
reg [95:0] decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string;
reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string;
reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
reg [39:0] memory_ENV_CTRL_string;
reg [39:0] _zz_memory_ENV_CTRL_string;
reg [39:0] execute_ENV_CTRL_string;
reg [39:0] _zz_execute_ENV_CTRL_string;
reg [39:0] writeBack_ENV_CTRL_string;
reg [39:0] _zz_writeBack_ENV_CTRL_string;
reg [31:0] execute_BRANCH_CTRL_string;
reg [31:0] _zz_execute_BRANCH_CTRL_string;
reg [71:0] memory_SHIFT_CTRL_string;
reg [71:0] _zz_memory_SHIFT_CTRL_string;
reg [71:0] execute_SHIFT_CTRL_string;
reg [71:0] _zz_execute_SHIFT_CTRL_string;
reg [23:0] execute_SRC2_CTRL_string;
reg [23:0] _zz_execute_SRC2_CTRL_string;
reg [95:0] execute_SRC1_CTRL_string;
reg [95:0] _zz_execute_SRC1_CTRL_string;
reg [63:0] execute_ALU_CTRL_string;
reg [63:0] _zz_execute_ALU_CTRL_string;
reg [39:0] execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string;
reg [39:0] _zz_decode_ENV_CTRL_1_string;
reg [31:0] _zz_decode_BRANCH_CTRL_string;
reg [71:0] _zz_decode_SHIFT_CTRL_1_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string;
reg [23:0] _zz_decode_SRC2_CTRL_1_string;
reg [63:0] _zz_decode_ALU_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_1_string;
reg [31:0] decode_BRANCH_CTRL_string;
reg [31:0] _zz_decode_BRANCH_CTRL_1_string;
reg [95:0] _zz_decode_SRC1_CTRL_2_string;
reg [63:0] _zz_decode_ALU_CTRL_2_string;
reg [23:0] _zz_decode_SRC2_CTRL_2_string;
reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string;
reg [71:0] _zz_decode_SHIFT_CTRL_2_string;
reg [31:0] _zz_decode_BRANCH_CTRL_2_string;
reg [39:0] _zz_decode_ENV_CTRL_2_string;
reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string;
reg [95:0] decode_to_execute_SRC1_CTRL_string;
reg [63:0] decode_to_execute_ALU_CTRL_string;
reg [23:0] decode_to_execute_SRC2_CTRL_string;
reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string;
reg [71:0] decode_to_execute_SHIFT_CTRL_string;
reg [71:0] execute_to_memory_SHIFT_CTRL_string;
reg [31:0] decode_to_execute_BRANCH_CTRL_string;
reg [39:0] decode_to_execute_ENV_CTRL_string;
reg [39:0] execute_to_memory_ENV_CTRL_string;
reg [39:0] memory_to_writeBack_ENV_CTRL_string;
reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string;
`endif
(* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ;
assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00);
assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00);
assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5));
assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3));
assign _zz_memory_MUL_LOW_2 = 52'h0;
assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL};
assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4};
assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16);
assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6};
assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16);
assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8};
assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude);
assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0];
assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed};
assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001);
assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00};
assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1};
assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]};
assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]};
assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101);
assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100);
assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS;
assign _zz__zz_execute_SRC1 = 3'b100;
assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15];
assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]};
assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4));
assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3));
assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1;
assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2);
assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6);
assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001;
assign _zz_execute_SrcPlugin_addSub_6 = 32'h0;
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0};
assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0};
assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]};
assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]};
assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100;
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01);
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1));
assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01);
assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW};
assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32);
assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0];
assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32];
assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement;
assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1};
assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2};
assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0];
assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])};
assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2;
assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3;
assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4);
assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert;
assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5};
assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1;
assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3};
assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2;
assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2};
assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]};
assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5);
assign _zz_decode_RegFilePlugin_rs1Data = 1'b1;
assign _zz_decode_RegFilePlugin_rs2Data = 1'b1;
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3};
assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0];
assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1];
assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f;
assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f);
assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073;
assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073);
assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063);
assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f;
assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f);
assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003;
assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063);
assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f);
assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}};
assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f;
assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f);
assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013;
assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033);
assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033);
assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}};
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31];
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7];
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h10003050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73}} != 6'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84} != 5'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120}}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00000050;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00000038);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00403040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69) == 32'h00000008);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = 6'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = 32'h00000008;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = (decode_INSTRUCTION & 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 32'h00000040;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != 1'b0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = (decode_INSTRUCTION & 32'h00004020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = 32'h00004020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79) == 32'h00000010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = 32'h00002030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = (decode_INSTRUCTION & 32'h00001030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00000020);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = (decode_INSTRUCTION & 32'h00001010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = 32'h00001010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = (decode_INSTRUCTION & 32'h00000070);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123) == 32'h00004010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133} != 4'b0000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = 32'h00000030;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = 32'h02000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h02002060;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h02003020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00000050);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00000010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = 32'h00000020;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = 32'h00004014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = (decode_INSTRUCTION & 32'h00006014);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 32'h00002010;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147}} != 3'b000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152} != 2'b00);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160)};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = 32'h00000044;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00000018);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000058;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h00002010);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h40000030);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151) == 32'h00000004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3};
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 2'b00;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00001004);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = 1'b0;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00002014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h40000034;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = 32'h00000014;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = (decode_INSTRUCTION & 32'h00000044);
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h00000004;
assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00005054;
assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31];
assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7];
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs1Data) begin
_zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1];
end
end
always @(posedge clk) begin
if(_zz_decode_RegFilePlugin_rs2Data) begin
_zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2];
end
end
always @(posedge clk) begin
if(_zz_1) begin
RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data;
end
end
InstructionCache IBusCachedPlugin_cache (
.io_flush (IBusCachedPlugin_cache_io_flush ), //i
.io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i
.io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o
.io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i
.io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i
.io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i
.io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i
.io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i
.io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o
.io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i
.io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o
.io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i
.io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i
.io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i
.io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o
.io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o
.io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o
.io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o
.io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o
.io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o
.io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i
.io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i
.io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i
.io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (iBus_cmd_ready ), //i
.io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o
.io_mem_rsp_valid (iBus_rsp_valid ), //i
.io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
DataCache dataCache_1 (
.io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i
.io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i
.io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o
.io_cpu_execute_args_wr (execute_MEMORY_WR ), //i
.io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i
.io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i
.io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o
.io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i
.io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i
.io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o
.io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i
.io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i
.io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i
.io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i
.io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i
.io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i
.io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i
.io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i
.io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i
.io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i
.io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i
.io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i
.io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i
.io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o
.io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o
.io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i
.io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o
.io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i
.io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o
.io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o
.io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o
.io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o
.io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i
.io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i
.io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i
.io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i
.io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i
.io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i
.io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i
.io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i
.io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i
.io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o
.io_cpu_redo (dataCache_1_io_cpu_redo ), //o
.io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i
.io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o
.io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o
.io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i
.io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o
.io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o
.io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o
.io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o
.io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o
.io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o
.io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o
.io_mem_rsp_valid (dBus_rsp_valid ), //i
.io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i
.io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i
.io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i
.clk (clk ), //i
.reset (reset ) //i
);
always @(*) begin
case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6)
2'b00 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload;
end
2'b01 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload;
end
2'b10 : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload;
end
default : begin
_zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_1)
2'b00 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0;
end
2'b01 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1;
end
2'b10 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
always @(*) begin
case(_zz_writeBack_DBusCachedPlugin_rspShifted_3)
1'b0 : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1;
end
default : begin
_zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3;
end
endcase
end
`ifndef SYNTHESIS
always @(*) begin
case(decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_to_writeBack_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL";
default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL";
default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL";
default : decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL";
default : _zz_decode_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_to_memory_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 ";
default : decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC ";
default : decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC ";
default : _zz_decode_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE ";
default : decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 ";
default : decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_to_execute_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
always @(*) begin
case(memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL";
default : memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL";
default : _zz_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL";
default : execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL";
default : _zz_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL";
default : writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL";
default : _zz_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR";
default : execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR";
default : _zz_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 ";
default : memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 ";
default : execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(_zz_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 ";
default : _zz_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC ";
default : execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(_zz_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC ";
default : _zz_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 ";
default : execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(_zz_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 ";
default : _zz_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE ";
default : execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE ";
default : _zz_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1";
default : execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : _zz_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_1)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL";
default : _zz_decode_ENV_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR";
default : _zz_decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_1)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_1_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_1)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_1)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC ";
default : _zz_decode_SRC2_CTRL_1_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_1)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_1_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_1)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_1_string = "????????????";
endcase
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR";
default : decode_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_1)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR";
default : _zz_decode_BRANCH_CTRL_1_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_SRC1_CTRL_2)
`Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 ";
default : _zz_decode_SRC1_CTRL_2_string = "????????????";
endcase
end
always @(*) begin
case(_zz_decode_ALU_CTRL_2)
`AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE ";
default : _zz_decode_ALU_CTRL_2_string = "????????";
endcase
end
always @(*) begin
case(_zz_decode_SRC2_CTRL_2)
`Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC ";
default : _zz_decode_SRC2_CTRL_2_string = "???";
endcase
end
always @(*) begin
case(_zz_decode_ALU_BITWISE_CTRL_2)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1";
default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_SHIFT_CTRL_2)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 ";
default : _zz_decode_SHIFT_CTRL_2_string = "?????????";
endcase
end
always @(*) begin
case(_zz_decode_BRANCH_CTRL_2)
`BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR";
default : _zz_decode_BRANCH_CTRL_2_string = "????";
endcase
end
always @(*) begin
case(_zz_decode_ENV_CTRL_2)
`EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL";
default : _zz_decode_ENV_CTRL_2_string = "?????";
endcase
end
always @(*) begin
case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8)
`Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I";
default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS ";
`Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU ";
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT";
`Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 ";
default : decode_to_execute_SRC1_CTRL_string = "????????????";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB ";
`AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU";
`AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE ";
default : decode_to_execute_ALU_CTRL_string = "????????";
endcase
end
always @(*) begin
case(decode_to_execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS ";
`Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI";
`Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS";
`Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC ";
default : decode_to_execute_SRC2_CTRL_string = "???";
endcase
end
always @(*) begin
case(decode_to_execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1";
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 ";
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1";
default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 ";
default : decode_to_execute_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(execute_to_memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1";
`ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 ";
`ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 ";
`ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 ";
default : execute_to_memory_SHIFT_CTRL_string = "?????????";
endcase
end
always @(*) begin
case(decode_to_execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC ";
`BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B ";
`BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL ";
`BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR";
default : decode_to_execute_BRANCH_CTRL_string = "????";
endcase
end
always @(*) begin
case(decode_to_execute_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL";
default : decode_to_execute_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(execute_to_memory_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL";
default : execute_to_memory_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(memory_to_writeBack_ENV_CTRL)
`EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE ";
`EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET ";
`EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL";
default : memory_to_writeBack_ENV_CTRL_string = "?????";
endcase
end
always @(*) begin
case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS ";
`Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I";
default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????";
endcase
end
`endif
assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7));
assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired);
assign memory_MUL_HH = execute_to_memory_MUL_HH;
assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow));
assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh));
assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow);
assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT;
assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA;
assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF;
assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF;
assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20);
assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0))));
assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch;
assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS));
assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1;
assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32];
assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31];
assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30];
assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29];
assign memory_IS_MUL = execute_to_memory_IS_MUL;
assign execute_IS_MUL = decode_to_execute_IS_MUL;
assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28];
assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1;
assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1;
assign decode_ENV_CTRL = _zz_decode_ENV_CTRL;
assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1;
assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25];
assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1;
assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1;
assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1;
assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1;
assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17];
assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16];
assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR;
assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13];
assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE;
assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12];
assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11];
assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1;
assign decode_ALU_CTRL = _zz_decode_ALU_CTRL;
assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1;
assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL;
assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1;
assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0;
assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT;
assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT;
assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT;
assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004);
assign memory_PC = execute_to_memory_PC;
always @(*) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT;
if(memory_arbitration_isStuck) begin
_zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
always @(*) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT;
if(execute_arbitration_isStuck) begin
_zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0;
end
end
assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE;
assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED;
assign execute_IS_DIV = decode_to_execute_IS_DIV;
assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED;
assign memory_IS_DIV = execute_to_memory_IS_DIV;
assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL;
assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH;
assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW;
assign memory_MUL_HL = execute_to_memory_MUL_HL;
assign memory_MUL_LH = execute_to_memory_MUL_LH;
assign memory_MUL_LL = execute_to_memory_MUL_LL;
assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE;
assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE;
assign execute_IS_CSR = decode_to_execute_IS_CSR;
assign memory_ENV_CTRL = _zz_memory_ENV_CTRL;
assign execute_ENV_CTRL = _zz_execute_ENV_CTRL;
assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL;
assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0};
assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget);
assign execute_PC = decode_to_execute_PC;
assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2;
assign execute_RS1 = decode_to_execute_RS1;
assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1;
assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL;
assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15];
assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5];
always @(*) begin
_zz_decode_RS2 = execute_REGFILE_WRITE_DATA;
if(when_CsrPlugin_l1176) begin
_zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal;
end
end
assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID;
assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE;
assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID;
assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION;
assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE;
assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID;
always @(*) begin
decode_RS2 = decode_RegFilePlugin_rs2Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr1Match) begin
decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l51) begin
decode_RS2 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l51_1) begin
decode_RS2 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l51_2) begin
decode_RS2 = _zz_decode_RS2;
end
end
end
end
always @(*) begin
decode_RS1 = decode_RegFilePlugin_rs1Data;
if(HazardSimplePlugin_writeBackBuffer_valid) begin
if(HazardSimplePlugin_addr0Match) begin
decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data;
end
end
if(when_HazardSimplePlugin_l45) begin
if(when_HazardSimplePlugin_l47) begin
if(when_HazardSimplePlugin_l48) begin
decode_RS1 = _zz_decode_RS2_2;
end
end
end
if(when_HazardSimplePlugin_l45_1) begin
if(memory_BYPASSABLE_MEMORY_STAGE) begin
if(when_HazardSimplePlugin_l48_1) begin
decode_RS1 = _zz_decode_RS2_1;
end
end
end
if(when_HazardSimplePlugin_l45_2) begin
if(execute_BYPASSABLE_EXECUTE_STAGE) begin
if(when_HazardSimplePlugin_l48_2) begin
decode_RS1 = _zz_decode_RS2;
end
end
end
end
assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT;
always @(*) begin
_zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA;
if(memory_arbitration_isValid) begin
case(memory_SHIFT_CTRL)
`ShiftCtrlEnum_binary_sequential_SLL_1 : begin
_zz_decode_RS2_1 = _zz_decode_RS2_3;
end
`ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin
_zz_decode_RS2_1 = memory_SHIFT_RIGHT;
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l128) begin
_zz_decode_RS2_1 = memory_DivPlugin_div_result;
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
_zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0;
end
end
assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL;
assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL;
assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED;
assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO;
assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS;
assign _zz_execute_SRC2 = execute_PC;
assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL;
assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL;
assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3];
assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20];
assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub;
assign execute_SRC_LESS = execute_SrcPlugin_less;
assign execute_ALU_CTRL = _zz_execute_ALU_CTRL;
assign execute_SRC2 = _zz_execute_SRC2_5;
assign execute_SRC1 = _zz_execute_SRC1;
assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL;
assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION;
assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID;
always @(*) begin
_zz_1 = 1'b0;
if(lastStageRegFileWrite_valid) begin
_zz_1 = 1'b1;
end
end
assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data);
always @(*) begin
decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10];
if(when_RegFilePlugin_l63) begin
decode_REGFILE_WRITE_VALID = 1'b0;
end
end
assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0);
always @(*) begin
_zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA;
if(when_DBusCachedPlugin_l484) begin
_zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated;
end
if(when_MulPlugin_l147) begin
case(switch_MulPlugin_l148)
2'b00 : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2;
end
default : begin
_zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1;
end
endcase
end
end
assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR;
assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF;
assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA;
assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE;
assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA;
assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE;
assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY;
assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT;
assign execute_RS2 = decode_to_execute_RS2;
assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR;
assign execute_SRC_ADD = execute_SrcPlugin_addSub;
assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE;
assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION;
assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4];
assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0];
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3;
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_rsp_issueDetected_4 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2;
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_issueDetected_3 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_rsp_issueDetected_2 = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_issueDetected_1 = 1'b1;
end
end
assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1;
assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst;
always @(*) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT;
if(BranchPlugin_jumpInterface_valid) begin
_zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload;
end
end
always @(*) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
_zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload;
end
end
assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc;
assign writeBack_PC = memory_to_writeBack_PC;
assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION;
always @(*) begin
decode_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l303) begin
decode_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
decode_arbitration_haltByOther = 1'b0;
if(when_HazardSimplePlugin_l113) begin
decode_arbitration_haltByOther = 1'b1;
end
if(CsrPlugin_pipelineLiberator_active) begin
decode_arbitration_haltByOther = 1'b1;
end
if(when_CsrPlugin_l1116) begin
decode_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
decode_arbitration_removeIt = 1'b0;
if(_zz_when) begin
decode_arbitration_removeIt = 1'b1;
end
if(decode_arbitration_isFlushed) begin
decode_arbitration_removeIt = 1'b1;
end
end
assign decode_arbitration_flushIt = 1'b0;
always @(*) begin
decode_arbitration_flushNext = 1'b0;
if(IBusCachedPlugin_predictionJumpInterface_valid) begin
decode_arbitration_flushNext = 1'b1;
end
if(_zz_when) begin
decode_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l343) begin
execute_arbitration_haltItself = 1'b1;
end
if(when_CsrPlugin_l1180) begin
if(execute_CsrPlugin_blockedBySideEffects) begin
execute_arbitration_haltItself = 1'b1;
end
end
if(when_CfuPlugin_l175) begin
execute_arbitration_haltItself = 1'b1;
end
end
always @(*) begin
execute_arbitration_haltByOther = 1'b0;
if(when_DBusCachedPlugin_l359) begin
execute_arbitration_haltByOther = 1'b1;
end
end
always @(*) begin
execute_arbitration_removeIt = 1'b0;
if(_zz_when_1) begin
execute_arbitration_removeIt = 1'b1;
end
if(execute_arbitration_isFlushed) begin
execute_arbitration_removeIt = 1'b1;
end
end
assign execute_arbitration_flushIt = 1'b0;
always @(*) begin
execute_arbitration_flushNext = 1'b0;
if(BranchPlugin_jumpInterface_valid) begin
execute_arbitration_flushNext = 1'b1;
end
if(_zz_when_1) begin
execute_arbitration_flushNext = 1'b1;
end
end
always @(*) begin
memory_arbitration_haltItself = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l129) begin
memory_arbitration_haltItself = 1'b1;
end
end
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
if(when_CfuPlugin_l208) begin
memory_arbitration_haltItself = 1'b1;
end
end
end
assign memory_arbitration_haltByOther = 1'b0;
always @(*) begin
memory_arbitration_removeIt = 1'b0;
if(memory_arbitration_isFlushed) begin
memory_arbitration_removeIt = 1'b1;
end
end
assign memory_arbitration_flushIt = 1'b0;
assign memory_arbitration_flushNext = 1'b0;
always @(*) begin
writeBack_arbitration_haltItself = 1'b0;
if(when_DBusCachedPlugin_l458) begin
writeBack_arbitration_haltItself = 1'b1;
end
end
assign writeBack_arbitration_haltByOther = 1'b0;
always @(*) begin
writeBack_arbitration_removeIt = 1'b0;
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_removeIt = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
writeBack_arbitration_removeIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushIt = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushIt = 1'b1;
end
end
always @(*) begin
writeBack_arbitration_flushNext = 1'b0;
if(DBusCachedPlugin_redoBranch_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(DBusCachedPlugin_exceptionBus_valid) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1019) begin
writeBack_arbitration_flushNext = 1'b1;
end
if(when_CsrPlugin_l1064) begin
writeBack_arbitration_flushNext = 1'b1;
end
end
assign lastStageInstruction = writeBack_INSTRUCTION;
assign lastStagePc = writeBack_PC;
assign lastStageIsValid = writeBack_arbitration_isValid;
assign lastStageIsFiring = writeBack_arbitration_isFiring;
always @(*) begin
IBusCachedPlugin_fetcherHalt = 1'b0;
if(when_CsrPlugin_l922) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1019) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
if(when_CsrPlugin_l1064) begin
IBusCachedPlugin_fetcherHalt = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_incomingInstruction = 1'b0;
if(when_Fetcher_l240) begin
IBusCachedPlugin_incomingInstruction = 1'b1;
end
end
assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0;
assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit;
assign CsrPlugin_inWfi = 1'b0;
assign CsrPlugin_thirdPartyWake = 1'b0;
always @(*) begin
CsrPlugin_jumpInterface_valid = 1'b0;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
if(when_CsrPlugin_l1064) begin
CsrPlugin_jumpInterface_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(when_CsrPlugin_l1019) begin
CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00};
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_jumpInterface_payload = CsrPlugin_mepc;
end
default : begin
end
endcase
end
end
assign CsrPlugin_forceMachineWire = 1'b0;
assign CsrPlugin_allowInterrupts = 1'b1;
assign CsrPlugin_allowException = 1'b1;
assign CsrPlugin_allowEbreakException = 1'b1;
assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000);
assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}};
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1));
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3];
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2);
assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5;
always @(*) begin
IBusCachedPlugin_fetchPc_correction = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_correction = 1'b1;
end
end
assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg);
always @(*) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0;
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1;
end
end
assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate);
assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready);
assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready);
always @(*) begin
IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc);
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload;
end
IBusCachedPlugin_fetchPc_pc[0] = 1'b0;
IBusCachedPlugin_fetchPc_pc[1] = 1'b0;
end
always @(*) begin
IBusCachedPlugin_fetchPc_flushed = 1'b0;
if(IBusCachedPlugin_fetchPc_redo_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
if(IBusCachedPlugin_jump_pcLoad_valid) begin
IBusCachedPlugin_fetchPc_flushed = 1'b1;
end
end
assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate));
assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted);
assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc;
always @(*) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b0;
if(IBusCachedPlugin_rsp_redoFetch) begin
IBusCachedPlugin_iBusRsp_redoFetch = 1'b1;
end
end
assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid;
assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0;
if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin
IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt);
assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0;
if(IBusCachedPlugin_mmuBus_busy) begin
IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt);
assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0;
if(when_IBusCachedPlugin_l267) begin
IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1;
end
end
assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt);
assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch;
assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload;
assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch);
assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready;
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2;
assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1;
assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg;
assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready);
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid;
assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready;
assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload;
always @(*) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b1;
if(when_Fetcher_l320) begin
IBusCachedPlugin_iBusRsp_readyForError = 1'b0;
end
end
assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid);
assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0);
assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready));
assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready));
assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck);
assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck);
assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck);
assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1;
assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2;
assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3;
assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4;
assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck);
assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid;
assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11];
always @(*) begin
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch;
end
always @(*) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31]));
if(_zz_6) begin
IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0;
end
end
assign _zz_2 = _zz__zz_2[19];
always @(*) begin
_zz_3[10] = _zz_2;
_zz_3[9] = _zz_2;
_zz_3[8] = _zz_2;
_zz_3[7] = _zz_2;
_zz_3[6] = _zz_2;
_zz_3[5] = _zz_2;
_zz_3[4] = _zz_2;
_zz_3[3] = _zz_2;
_zz_3[2] = _zz_2;
_zz_3[1] = _zz_2;
_zz_3[0] = _zz_2;
end
assign _zz_4 = _zz__zz_4[11];
always @(*) begin
_zz_5[18] = _zz_4;
_zz_5[17] = _zz_4;
_zz_5[16] = _zz_4;
_zz_5[15] = _zz_4;
_zz_5[14] = _zz_4;
_zz_5[13] = _zz_4;
_zz_5[12] = _zz_4;
_zz_5[11] = _zz_4;
_zz_5[10] = _zz_4;
_zz_5[9] = _zz_4;
_zz_5[8] = _zz_4;
_zz_5[7] = _zz_4;
_zz_5[6] = _zz_4;
_zz_5[5] = _zz_4;
_zz_5[4] = _zz_4;
_zz_5[3] = _zz_4;
_zz_5[2] = _zz_4;
_zz_5[1] = _zz_4;
_zz_5[0] = _zz_4;
end
always @(*) begin
case(decode_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_6 = _zz__zz_6[1];
end
default : begin
_zz_6 = _zz__zz_6_1[1];
end
endcase
end
assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch);
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload;
end
assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11];
always @(*) begin
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
_zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2;
end
assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}));
assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid;
always @(*) begin
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address;
end
assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size;
assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0;
assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid;
assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready);
assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload;
assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush);
assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit));
assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready);
assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00);
assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0;
assign IBusCachedPlugin_rsp_issueDetected = 1'b0;
always @(*) begin
IBusCachedPlugin_rsp_redoFetch = 1'b0;
if(when_IBusCachedPlugin_l239) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_rsp_redoFetch = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling));
if(when_IBusCachedPlugin_l250) begin
IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_valid = 1'b0;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError;
end
end
always @(*) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx;
if(when_IBusCachedPlugin_l244) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100;
end
if(when_IBusCachedPlugin_l256) begin
IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001;
end
end
assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00};
assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected));
assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1));
assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2));
assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3));
assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt);
assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid;
assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready;
assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data;
assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload;
assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL);
assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size);
assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last);
always @(*) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready;
if(when_Stream_l342) begin
dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1;
end
end
assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid);
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last;
assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid;
assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready;
assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr;
assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached;
assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address;
assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data;
assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask;
assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size;
assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last;
assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE);
assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12];
assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE);
assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD;
always @(*) begin
case(execute_DBusCachedPlugin_size)
2'b00 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]};
end
2'b01 : begin
_zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]};
end
default : begin
_zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0];
end
endcase
end
assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT);
assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready));
assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt);
assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid);
assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE);
assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA;
assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid;
assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck;
assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address;
assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0;
assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
always @(*) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess;
if(when_DBusCachedPlugin_l386) begin
dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1;
end
end
assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite));
always @(*) begin
dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
if(writeBack_arbitration_haltByOther) begin
dataCache_1_io_cpu_writeBack_isValid = 1'b0;
end
end
assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00);
assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA;
assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF;
always @(*) begin
DBusCachedPlugin_redoBranch_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_redoBranch_valid = 1'b1;
end
end
end
assign DBusCachedPlugin_redoBranch_payload = writeBack_PC;
always @(*) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_valid = 1'b1;
end
if(dataCache_1_io_cpu_redo) begin
DBusCachedPlugin_exceptionBus_valid = 1'b0;
end
end
end
assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA;
always @(*) begin
DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx;
if(when_DBusCachedPlugin_l438) begin
if(dataCache_1_io_cpu_writeBack_accessError) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code};
end
if(dataCache_1_io_cpu_writeBack_mmuException) begin
DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101);
end
if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin
DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1};
end
end
end
assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt);
assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0];
assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8];
assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16];
assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24];
always @(*) begin
writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted;
writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2;
writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2;
writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3;
end
assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0];
assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12];
assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated;
_zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0];
end
assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14]));
always @(*) begin
_zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2;
_zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0];
end
always @(*) begin
case(switch_Misc_l200)
2'b00 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1;
end
2'b01 : begin
writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3;
end
default : begin
writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf;
end
endcase
end
assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE);
assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign IBusCachedPlugin_mmuBus_busy = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress;
assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1;
assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31];
assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0;
assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0;
assign DBusCachedPlugin_mmuBus_busy = 1'b0;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0);
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}};
assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1];
assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2;
assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6];
assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2;
assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8];
assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2;
assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18];
assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2;
assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21];
assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2;
assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23];
assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2;
assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26];
assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33];
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8;
assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION));
assign decodeExceptionPort_payload_code = 4'b0010;
assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION;
assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0);
assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15];
assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20];
assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0;
assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1;
always @(*) begin
lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
if(_zz_7) begin
lastStageRegFileWrite_valid = 1'b1;
end
end
always @(*) begin
lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
if(_zz_7) begin
lastStageRegFileWrite_payload_address = 5'h0;
end
end
always @(*) begin
lastStageRegFileWrite_payload_data = _zz_decode_RS2_2;
if(_zz_7) begin
lastStageRegFileWrite_payload_data = 32'h0;
end
end
always @(*) begin
case(execute_ALU_BITWISE_CTRL)
`AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2);
end
`AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2);
end
default : begin
execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2);
end
endcase
end
always @(*) begin
case(execute_ALU_CTRL)
`AluCtrlEnum_binary_sequential_BITWISE : begin
_zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise;
end
`AluCtrlEnum_binary_sequential_SLT_SLTU : begin
_zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA};
end
default : begin
_zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB;
end
endcase
end
always @(*) begin
case(execute_SRC1_CTRL)
`Src1CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC1 = execute_RS1;
end
`Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin
_zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1};
end
`Src1CtrlEnum_binary_sequential_IMU : begin
_zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0};
end
default : begin
_zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1};
end
endcase
end
assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_SRC2_2[19] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[18] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[17] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[16] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[15] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[14] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[13] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[12] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[11] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[10] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[9] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[8] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[7] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[6] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[5] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[4] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[3] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[2] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[1] = _zz_execute_SRC2_1;
_zz_execute_SRC2_2[0] = _zz_execute_SRC2_1;
end
assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11];
always @(*) begin
_zz_execute_SRC2_4[19] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[18] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[17] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[16] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[15] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[14] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[13] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[12] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[11] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[10] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[9] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[8] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[7] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[6] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[5] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[4] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[3] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[2] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[1] = _zz_execute_SRC2_3;
_zz_execute_SRC2_4[0] = _zz_execute_SRC2_3;
end
always @(*) begin
case(execute_SRC2_CTRL)
`Src2CtrlEnum_binary_sequential_RS : begin
_zz_execute_SRC2_5 = execute_RS2;
end
`Src2CtrlEnum_binary_sequential_IMI : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]};
end
`Src2CtrlEnum_binary_sequential_IMS : begin
_zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}};
end
default : begin
_zz_execute_SRC2_5 = _zz_execute_SRC2;
end
endcase
end
always @(*) begin
execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub;
if(execute_SRC2_FORCE_ZERO) begin
execute_SrcPlugin_addSub = execute_SRC1;
end
end
assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31]));
assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0];
always @(*) begin
_zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31];
_zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30];
_zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29];
_zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28];
_zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27];
_zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26];
_zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25];
_zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24];
_zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23];
_zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22];
_zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21];
_zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20];
_zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19];
_zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18];
_zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17];
_zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16];
_zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15];
_zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14];
_zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13];
_zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12];
_zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11];
_zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10];
_zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9];
_zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8];
_zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7];
_zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6];
_zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5];
_zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4];
_zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3];
_zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2];
_zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1];
_zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0];
end
assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1);
always @(*) begin
_zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31];
_zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30];
_zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29];
_zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28];
_zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27];
_zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26];
_zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25];
_zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24];
_zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23];
_zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22];
_zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21];
_zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20];
_zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19];
_zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18];
_zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17];
_zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16];
_zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15];
_zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14];
_zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13];
_zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12];
_zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11];
_zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10];
_zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9];
_zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8];
_zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7];
_zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6];
_zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5];
_zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4];
_zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3];
_zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2];
_zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1];
_zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0];
end
always @(*) begin
HazardSimplePlugin_src0Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l48) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l48_1) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l48_2) begin
HazardSimplePlugin_src0Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l105) begin
HazardSimplePlugin_src0Hazard = 1'b0;
end
end
always @(*) begin
HazardSimplePlugin_src1Hazard = 1'b0;
if(when_HazardSimplePlugin_l57) begin
if(when_HazardSimplePlugin_l58) begin
if(when_HazardSimplePlugin_l51) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_1) begin
if(when_HazardSimplePlugin_l58_1) begin
if(when_HazardSimplePlugin_l51_1) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l57_2) begin
if(when_HazardSimplePlugin_l58_2) begin
if(when_HazardSimplePlugin_l51_2) begin
HazardSimplePlugin_src1Hazard = 1'b1;
end
end
end
if(when_HazardSimplePlugin_l108) begin
HazardSimplePlugin_src1Hazard = 1'b0;
end
end
assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring);
assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7];
assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2;
assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]);
assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l47 = 1'b1;
assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47));
assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE));
assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]);
assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]);
assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID);
assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE));
assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE);
assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE);
assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard));
assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2);
assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12];
always @(*) begin
casez(switch_Misc_l200_1)
3'b000 : begin
_zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq;
end
3'b001 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq);
end
3'b1?1 : begin
_zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS);
end
default : begin
_zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS;
end
endcase
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_INC : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b0;
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BRANCH_COND_RESULT_1 = 1'b1;
end
default : begin
_zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT;
end
endcase
end
assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget;
_zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2;
_zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2;
end
assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11];
always @(*) begin
_zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4;
_zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]);
end
`BranchCtrlEnum_binary_sequential_JAL : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1];
end
default : begin
_zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1];
end
endcase
end
assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6);
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src1 = execute_RS1;
end
default : begin
execute_BranchPlugin_branch_src1 = execute_PC;
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2;
_zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2;
end
always @(*) begin
case(execute_BRANCH_CTRL)
`BranchCtrlEnum_binary_sequential_JALR : begin
execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]};
end
default : begin
execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0});
if(execute_PREDICTION_HAD_BRANCHED2) begin
execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9};
end
end
endcase
end
assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2;
_zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2;
end
assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11];
always @(*) begin
_zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4;
_zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4;
end
assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2);
assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0));
assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC;
always @(*) begin
BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1]));
if(when_BranchPlugin_l296) begin
BranchPlugin_branchExceptionPort_valid = 1'b0;
end
end
assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000;
assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC;
assign when_BranchPlugin_l296 = 1'b0;
assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid;
always @(*) begin
CsrPlugin_privilege = 2'b11;
if(CsrPlugin_forceMachineWire) begin
CsrPlugin_privilege = 2'b11;
end
end
assign CsrPlugin_misa_base = 2'b01;
assign CsrPlugin_misa_extensions = 26'h0000042;
assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE);
assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE);
assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE);
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11;
assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege);
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0];
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid};
assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0];
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1;
end
if(decode_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1;
end
if(execute_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
if(memory_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0;
end
end
always @(*) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1;
end
if(writeBack_arbitration_isFlushed) begin
CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0;
end
end
assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck);
assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000);
assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode;
assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute;
assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory;
assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack;
assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11));
assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0));
assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0));
assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException);
assign CsrPlugin_lastStageWasWfi = 1'b0;
assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid);
assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck);
assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck);
assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt);
always @(*) begin
CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2;
if(when_CsrPlugin_l991) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
if(CsrPlugin_hadException) begin
CsrPlugin_pipelineLiberator_done = 1'b0;
end
end
assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000);
assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts);
always @(*) begin
CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege;
if(CsrPlugin_hadException) begin
CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege;
end
end
always @(*) begin
CsrPlugin_trapCause = CsrPlugin_interrupt_code;
if(CsrPlugin_hadException) begin
CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code;
end
end
always @(*) begin
CsrPlugin_xtvec_mode = 2'bxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode;
end
default : begin
end
endcase
end
always @(*) begin
CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_xtvec_base = CsrPlugin_mtvec_base;
end
default : begin
end
endcase
end
assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump);
assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28];
assign contextSwitching = CsrPlugin_jumpInterface_valid;
assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000);
assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0);
always @(*) begin
execute_CsrPlugin_illegalAccess = 1'b1;
if(execute_CsrPlugin_csr_3264) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_768) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_836) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_772) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CSR_WRITE_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_833) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_834) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_835) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2816) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_2944) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(execute_CsrPlugin_csr_3008) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(execute_CsrPlugin_csr_4032) begin
if(execute_CSR_READ_OPCODE) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
if(CsrPlugin_csrMapping_allowCsrSignal) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_illegalAccess = 1'b1;
end
if(when_CsrPlugin_l1302) begin
execute_CsrPlugin_illegalAccess = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_illegalInstruction = 1'b0;
if(when_CsrPlugin_l1136) begin
if(when_CsrPlugin_l1137) begin
execute_CsrPlugin_illegalInstruction = 1'b1;
end
end
end
always @(*) begin
CsrPlugin_selfException_valid = 1'b0;
if(when_CsrPlugin_l1144) begin
CsrPlugin_selfException_valid = 1'b1;
end
end
always @(*) begin
CsrPlugin_selfException_payload_code = 4'bxxxx;
if(when_CsrPlugin_l1144) begin
case(CsrPlugin_privilege)
2'b00 : begin
CsrPlugin_selfException_payload_code = 4'b1000;
end
default : begin
CsrPlugin_selfException_payload_code = 4'b1011;
end
endcase
end
end
assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION;
assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET));
assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]);
assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL));
always @(*) begin
execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_writeInstruction = 1'b0;
end
end
always @(*) begin
execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE);
if(when_CsrPlugin_l1297) begin
execute_CsrPlugin_readInstruction = 1'b0;
end
end
assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck));
assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck));
assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects);
assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal;
assign switch_Misc_l200_2 = execute_INSTRUCTION[13];
always @(*) begin
case(switch_Misc_l200_2)
1'b0 : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1;
end
default : begin
_zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1));
end
endcase
end
assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal;
assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR);
assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0));
assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20];
assign execute_MulPlugin_a = execute_RS1;
assign execute_MulPlugin_b = execute_RS2;
assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12];
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_aSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_aSigned = 1'b1;
end
default : begin
execute_MulPlugin_aSigned = 1'b0;
end
endcase
end
always @(*) begin
case(switch_MulPlugin_l87)
2'b01 : begin
execute_MulPlugin_bSigned = 1'b1;
end
2'b10 : begin
execute_MulPlugin_bSigned = 1'b0;
end
default : begin
execute_MulPlugin_bSigned = 1'b0;
end
endcase
end
assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0];
assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0];
assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]};
assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]};
assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]};
assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]};
assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1));
assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL);
assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12];
assign memory_DivPlugin_frontendOk = 1'b1;
always @(*) begin
memory_DivPlugin_div_counter_willIncrement = 1'b0;
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_div_counter_willIncrement = 1'b1;
end
end
end
always @(*) begin
memory_DivPlugin_div_counter_willClear = 1'b0;
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_div_counter_willClear = 1'b1;
end
end
assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21);
assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement);
always @(*) begin
if(memory_DivPlugin_div_counter_willOverflow) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end else begin
memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext);
end
if(memory_DivPlugin_div_counter_willClear) begin
memory_DivPlugin_div_counter_valueNext = 6'h0;
end
end
assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20);
assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck);
assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV);
assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done));
assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done));
assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0];
assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]};
assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator);
assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1);
assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0];
assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20);
assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]);
assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck);
assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED);
assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED));
always @(*) begin
_zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]);
_zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1;
end
assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext);
assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0);
assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE);
assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready);
assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers);
assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired));
assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready));
assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0;
assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1;
assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31];
always @(*) begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
_zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1;
end
always @(*) begin
case(execute_CfuPlugin_CFU_INPUT_2_KIND)
`Input2Kind_binary_sequential_RS : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2;
end
default : begin
_zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]};
end
endcase
end
assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2;
assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid);
assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0);
always @(*) begin
CfuPlugin_bus_rsp_rsp_ready = 1'b0;
if(memory_CfuPlugin_CFU_IN_FLIGHT) begin
CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers);
end
end
assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid);
assign when_Pipeline_l124 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack));
assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL;
assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1;
assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL;
assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL;
assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1;
assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL;
assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL;
assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1;
assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck);
assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL;
assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL;
assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1;
assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck);
assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL;
assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL;
assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL;
assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1;
assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck);
assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL;
assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck);
assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL;
assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL;
assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL;
assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck);
assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL;
assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL;
assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL;
assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL;
assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1;
assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck);
assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL;
assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck);
assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL;
assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck);
assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL;
assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck);
assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND;
assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1;
assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck);
assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck);
assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck);
assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck);
assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck);
assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000));
assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000));
assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00));
assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0));
assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers);
assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt));
assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck));
assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers);
assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt));
assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck));
assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers);
assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt));
assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0);
assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers);
assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt));
assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt));
assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt);
assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt));
assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt);
assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt));
assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt);
assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt));
assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck);
assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck);
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0;
if(execute_CsrPlugin_csr_3264) begin
_zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000;
_zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0;
if(execute_CsrPlugin_csr_768) begin
_zz_CsrPlugin_csrMapping_readDataInit_3[12 : 11] = CsrPlugin_mstatus_MPP;
_zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mstatus_MPIE;
_zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mstatus_MIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0;
if(execute_CsrPlugin_csr_836) begin
_zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mip_MEIP;
_zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mip_MTIP;
_zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mip_MSIP;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0;
if(execute_CsrPlugin_csr_772) begin
_zz_CsrPlugin_csrMapping_readDataInit_5[11 : 11] = CsrPlugin_mie_MEIE;
_zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mie_MTIE;
_zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mie_MSIE;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0;
if(execute_CsrPlugin_csr_833) begin
_zz_CsrPlugin_csrMapping_readDataInit_6[31 : 0] = CsrPlugin_mepc;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0;
if(execute_CsrPlugin_csr_834) begin
_zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = CsrPlugin_mcause_interrupt;
_zz_CsrPlugin_csrMapping_readDataInit_7[3 : 0] = CsrPlugin_mcause_exceptionCode;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0;
if(execute_CsrPlugin_csr_835) begin
_zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mtval;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0;
if(execute_CsrPlugin_csr_2816) begin
_zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = CsrPlugin_mcycle[31 : 0];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0;
if(execute_CsrPlugin_csr_2944) begin
_zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = CsrPlugin_mcycle[63 : 32];
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0;
if(execute_CsrPlugin_csr_3008) begin
_zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit;
end
end
always @(*) begin
_zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0;
if(execute_CsrPlugin_csr_4032) begin
_zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1;
end
end
assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))) | ((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | _zz_CsrPlugin_csrMapping_readDataInit_12));
assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]);
assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR));
assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR};
assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010);
assign iBusWishbone_BTE = 2'b00;
assign iBusWishbone_SEL = 4'b1111;
assign iBusWishbone_WE = 1'b0;
assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
always @(*) begin
iBusWishbone_CYC = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_CYC = 1'b1;
end
end
always @(*) begin
iBusWishbone_STB = 1'b0;
if(when_InstructionCache_l239) begin
iBusWishbone_STB = 1'b1;
end
end
assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000));
assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK);
assign iBus_rsp_valid = _zz_iBus_rsp_valid;
assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext;
assign iBus_rsp_payload_error = 1'b0;
assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101);
assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid;
assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr;
assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111));
assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4));
assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2);
assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000);
assign dBusWishbone_BTE = 2'b00;
assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111);
assign dBusWishbone_WE = _zz_dBus_cmd_ready_3;
assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data;
assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK);
assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1;
assign dBusWishbone_STB = _zz_dBus_cmd_ready_1;
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
assign dBus_rsp_payload_error = 1'b0;
always @(posedge clk) begin
if(reset) begin
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
IBusCachedPlugin_fetchPc_booted <= 1'b0;
IBusCachedPlugin_fetchPc_inc <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter;
IBusCachedPlugin_rspCounter <= 32'h0;
dataCache_1_io_mem_cmd_rValid <= 1'b0;
dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0;
DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter;
DBusCachedPlugin_rspCounter <= 32'h0;
_zz_7 <= 1'b1;
HazardSimplePlugin_writeBackBuffer_valid <= 1'b0;
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= 1'b0;
CsrPlugin_mstatus_MPP <= 2'b11;
CsrPlugin_mie_MEIE <= 1'b0;
CsrPlugin_mie_MTIE <= 1'b0;
CsrPlugin_mie_MSIE <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0;
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
CsrPlugin_interrupt_valid <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
CsrPlugin_hadException <= 1'b0;
execute_CsrPlugin_wfiWake <= 1'b0;
memory_DivPlugin_div_counter_value <= 6'h0;
_zz_CsrPlugin_csrMapping_readDataInit <= 32'h0;
execute_CfuPlugin_hold <= 1'b0;
execute_CfuPlugin_fired <= 1'b0;
CfuPlugin_bus_rsp_rValid <= 1'b0;
execute_arbitration_isValid <= 1'b0;
memory_arbitration_isValid <= 1'b0;
writeBack_arbitration_isValid <= 1'b0;
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0;
_zz_iBusWishbone_ADR <= 3'b000;
_zz_iBus_rsp_valid <= 1'b0;
_zz_dBus_cmd_ready <= 3'b000;
_zz_dBus_rsp_valid <= 1'b0;
end else begin
if(IBusCachedPlugin_fetchPc_correction) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_output_fire) begin
IBusCachedPlugin_fetchPc_correctionReg <= 1'b0;
end
IBusCachedPlugin_fetchPc_booted <= 1'b1;
if(when_Fetcher_l131) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_output_fire_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b1;
end
if(when_Fetcher_l131_1) begin
IBusCachedPlugin_fetchPc_inc <= 1'b0;
end
if(when_Fetcher_l158) begin
IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc;
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0;
end
if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0));
end
if(IBusCachedPlugin_iBusRsp_flush) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0;
end
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush));
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0;
end
if(when_Fetcher_l329) begin
IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(when_Fetcher_l329_1) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(when_Fetcher_l329_2) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(when_Fetcher_l329_3) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(when_Fetcher_l329_4) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3;
end
if(IBusCachedPlugin_fetchPc_flushed) begin
IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0;
end
if(iBus_rsp_valid) begin
IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001);
end
if(dataCache_1_io_mem_cmd_valid) begin
dataCache_1_io_mem_cmd_rValid <= 1'b1;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_rValid <= 1'b0;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid;
end
if(dBus_rsp_valid) begin
DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001);
end
_zz_7 <= 1'b0;
HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid;
if(when_CsrPlugin_l909) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0;
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode;
end
if(when_CsrPlugin_l909_1) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute;
end
if(when_CsrPlugin_l909_2) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory;
end
if(when_CsrPlugin_l909_3) begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck));
end else begin
CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0;
end
CsrPlugin_interrupt_valid <= 1'b0;
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_valid <= 1'b1;
end
end
if(CsrPlugin_pipelineLiberator_active) begin
if(when_CsrPlugin_l980) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1;
end
if(when_CsrPlugin_l980_1) begin
CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0;
end
if(when_CsrPlugin_l980_2) begin
CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1;
end
end
if(when_CsrPlugin_l985) begin
CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0;
CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0;
end
if(CsrPlugin_interruptJump) begin
CsrPlugin_interrupt_valid <= 1'b0;
end
CsrPlugin_hadException <= CsrPlugin_exception;
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mstatus_MIE <= 1'b0;
CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE;
CsrPlugin_mstatus_MPP <= CsrPlugin_privilege;
end
default : begin
end
endcase
end
if(when_CsrPlugin_l1064) begin
case(switch_CsrPlugin_l1068)
2'b11 : begin
CsrPlugin_mstatus_MPP <= 2'b00;
CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE;
CsrPlugin_mstatus_MPIE <= 1'b1;
end
default : begin
end
endcase
end
execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake);
memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext;
if(execute_CfuPlugin_schedule) begin
execute_CfuPlugin_hold <= 1'b1;
end
if(CfuPlugin_bus_cmd_ready) begin
execute_CfuPlugin_hold <= 1'b0;
end
if(CfuPlugin_bus_cmd_fire) begin
execute_CfuPlugin_fired <= 1'b1;
end
if(when_CfuPlugin_l171) begin
execute_CfuPlugin_fired <= 1'b0;
end
if(CfuPlugin_bus_rsp_valid) begin
CfuPlugin_bus_rsp_rValid <= 1'b1;
end
if(CfuPlugin_bus_rsp_rsp_ready) begin
CfuPlugin_bus_rsp_rValid <= 1'b0;
end
if(when_Pipeline_l124_61) begin
execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l151) begin
execute_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154) begin
execute_arbitration_isValid <= decode_arbitration_isValid;
end
if(when_Pipeline_l151_1) begin
memory_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_1) begin
memory_arbitration_isValid <= execute_arbitration_isValid;
end
if(when_Pipeline_l151_2) begin
writeBack_arbitration_isValid <= 1'b0;
end
if(when_Pipeline_l154_2) begin
writeBack_arbitration_isValid <= memory_arbitration_isValid;
end
if(execute_CsrPlugin_csr_768) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11];
CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_772) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11];
CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7];
CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_3008) begin
if(execute_CsrPlugin_writeEnable) begin
_zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
if(when_InstructionCache_l239) begin
if(iBusWishbone_ACK) begin
_zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001);
end
end
_zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK);
if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin
_zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001);
if(_zz_dBus_cmd_ready_4) begin
_zz_dBus_cmd_ready <= 3'b000;
end
end
_zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK);
end
end
always @(posedge clk) begin
if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin
_zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload;
end
if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin
IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit;
end
if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin
IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit;
end
if(dataCache_1_io_mem_cmd_ready) begin
dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr;
dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached;
dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address;
dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data;
dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask;
dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size;
dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last;
end
if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin
dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr;
dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached;
dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address;
dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data;
dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask;
dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size;
dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last;
end
HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address;
HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data;
CsrPlugin_mip_MEIP <= externalInterrupt;
CsrPlugin_mip_MTIP <= timerInterrupt;
CsrPlugin_mip_MSIP <= softwareInterrupt;
CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001);
if(writeBack_arbitration_isFiring) begin
CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001);
end
if(_zz_when) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr);
end
if(_zz_when_1) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code);
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr);
end
if(DBusCachedPlugin_exceptionBus_valid) begin
CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code;
CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr;
end
if(when_CsrPlugin_l946) begin
if(when_CsrPlugin_l952) begin
CsrPlugin_interrupt_code <= 4'b0111;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_1) begin
CsrPlugin_interrupt_code <= 4'b0011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
if(when_CsrPlugin_l952_2) begin
CsrPlugin_interrupt_code <= 4'b1011;
CsrPlugin_interrupt_targetPrivilege <= 2'b11;
end
end
if(when_CsrPlugin_l1019) begin
case(CsrPlugin_targetPrivilege)
2'b11 : begin
CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException);
CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause;
CsrPlugin_mepc <= writeBack_PC;
if(CsrPlugin_hadException) begin
CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr;
end
end
default : begin
end
endcase
end
if(when_MulDivIterativePlugin_l126) begin
memory_DivPlugin_div_done <= 1'b1;
end
if(when_MulDivIterativePlugin_l126_1) begin
memory_DivPlugin_div_done <= 1'b0;
end
if(when_MulDivIterativePlugin_l128) begin
if(when_MulDivIterativePlugin_l132) begin
memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator;
memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder;
if(when_MulDivIterativePlugin_l151) begin
memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0];
end
end
end
if(when_MulDivIterativePlugin_l162) begin
memory_DivPlugin_accumulator <= 65'h0;
memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2);
memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1);
memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13]))));
end
externalInterruptArray_regNext <= externalInterruptArray;
if(CfuPlugin_bus_rsp_ready) begin
CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0;
end
if(when_Pipeline_l124) begin
decode_to_execute_PC <= decode_PC;
end
if(when_Pipeline_l124_1) begin
execute_to_memory_PC <= _zz_execute_SRC2;
end
if(when_Pipeline_l124_2) begin
memory_to_writeBack_PC <= memory_PC;
end
if(when_Pipeline_l124_3) begin
decode_to_execute_INSTRUCTION <= decode_INSTRUCTION;
end
if(when_Pipeline_l124_4) begin
execute_to_memory_INSTRUCTION <= execute_INSTRUCTION;
end
if(when_Pipeline_l124_5) begin
memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION;
end
if(when_Pipeline_l124_6) begin
decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_7) begin
execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_8) begin
memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT;
end
if(when_Pipeline_l124_9) begin
decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY;
end
if(when_Pipeline_l124_10) begin
decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL;
end
if(when_Pipeline_l124_11) begin
decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS;
end
if(when_Pipeline_l124_12) begin
decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE;
end
if(when_Pipeline_l124_13) begin
execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE;
end
if(when_Pipeline_l124_14) begin
memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE;
end
if(when_Pipeline_l124_15) begin
decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL;
end
if(when_Pipeline_l124_16) begin
decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL;
end
if(when_Pipeline_l124_17) begin
decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_18) begin
execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_19) begin
memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID;
end
if(when_Pipeline_l124_20) begin
decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE;
end
if(when_Pipeline_l124_21) begin
decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_22) begin
execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE;
end
if(when_Pipeline_l124_23) begin
decode_to_execute_MEMORY_WR <= decode_MEMORY_WR;
end
if(when_Pipeline_l124_24) begin
execute_to_memory_MEMORY_WR <= execute_MEMORY_WR;
end
if(when_Pipeline_l124_25) begin
memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR;
end
if(when_Pipeline_l124_26) begin
decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT;
end
if(when_Pipeline_l124_27) begin
decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED;
end
if(when_Pipeline_l124_28) begin
decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL;
end
if(when_Pipeline_l124_29) begin
decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL;
end
if(when_Pipeline_l124_30) begin
execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL;
end
if(when_Pipeline_l124_31) begin
decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL;
end
if(when_Pipeline_l124_32) begin
decode_to_execute_IS_CSR <= decode_IS_CSR;
end
if(when_Pipeline_l124_33) begin
decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL;
end
if(when_Pipeline_l124_34) begin
execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL;
end
if(when_Pipeline_l124_35) begin
memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL;
end
if(when_Pipeline_l124_36) begin
decode_to_execute_IS_MUL <= decode_IS_MUL;
end
if(when_Pipeline_l124_37) begin
execute_to_memory_IS_MUL <= execute_IS_MUL;
end
if(when_Pipeline_l124_38) begin
memory_to_writeBack_IS_MUL <= memory_IS_MUL;
end
if(when_Pipeline_l124_39) begin
decode_to_execute_IS_DIV <= decode_IS_DIV;
end
if(when_Pipeline_l124_40) begin
execute_to_memory_IS_DIV <= execute_IS_DIV;
end
if(when_Pipeline_l124_41) begin
decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED;
end
if(when_Pipeline_l124_42) begin
decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED;
end
if(when_Pipeline_l124_43) begin
decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE;
end
if(when_Pipeline_l124_44) begin
decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND;
end
if(when_Pipeline_l124_45) begin
decode_to_execute_RS1 <= decode_RS1;
end
if(when_Pipeline_l124_46) begin
decode_to_execute_RS2 <= decode_RS2;
end
if(when_Pipeline_l124_47) begin
decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO;
end
if(when_Pipeline_l124_48) begin
decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2;
end
if(when_Pipeline_l124_49) begin
decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE;
end
if(when_Pipeline_l124_50) begin
decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE;
end
if(when_Pipeline_l124_51) begin
execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_52) begin
memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF;
end
if(when_Pipeline_l124_53) begin
execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2;
end
if(when_Pipeline_l124_54) begin
memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1;
end
if(when_Pipeline_l124_55) begin
execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT;
end
if(when_Pipeline_l124_56) begin
execute_to_memory_MUL_LL <= execute_MUL_LL;
end
if(when_Pipeline_l124_57) begin
execute_to_memory_MUL_LH <= execute_MUL_LH;
end
if(when_Pipeline_l124_58) begin
execute_to_memory_MUL_HL <= execute_MUL_HL;
end
if(when_Pipeline_l124_59) begin
execute_to_memory_MUL_HH <= execute_MUL_HH;
end
if(when_Pipeline_l124_60) begin
memory_to_writeBack_MUL_HH <= memory_MUL_HH;
end
if(when_Pipeline_l124_62) begin
memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT;
end
if(when_Pipeline_l124_63) begin
memory_to_writeBack_MUL_LOW <= memory_MUL_LOW;
end
if(when_CsrPlugin_l1264) begin
execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0);
end
if(when_CsrPlugin_l1264_1) begin
execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300);
end
if(when_CsrPlugin_l1264_2) begin
execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344);
end
if(when_CsrPlugin_l1264_3) begin
execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304);
end
if(when_CsrPlugin_l1264_4) begin
execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305);
end
if(when_CsrPlugin_l1264_5) begin
execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341);
end
if(when_CsrPlugin_l1264_6) begin
execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342);
end
if(when_CsrPlugin_l1264_7) begin
execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343);
end
if(when_CsrPlugin_l1264_8) begin
execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00);
end
if(when_CsrPlugin_l1264_9) begin
execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80);
end
if(when_CsrPlugin_l1264_10) begin
execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0);
end
if(when_CsrPlugin_l1264_11) begin
execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0);
end
if(execute_CsrPlugin_csr_836) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3];
end
end
if(execute_CsrPlugin_csr_773) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2];
CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0];
end
end
if(execute_CsrPlugin_csr_833) begin
if(execute_CsrPlugin_writeEnable) begin
CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0];
end
end
iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO;
dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO;
end
endmodule
module DataCache (
input io_cpu_execute_isValid,
input [31:0] io_cpu_execute_address,
output reg io_cpu_execute_haltIt,
input io_cpu_execute_args_wr,
input [1:0] io_cpu_execute_args_size,
input io_cpu_execute_args_totalyConsistent,
output io_cpu_execute_refilling,
input io_cpu_memory_isValid,
input io_cpu_memory_isStuck,
output io_cpu_memory_isWrite,
input [31:0] io_cpu_memory_address,
input [31:0] io_cpu_memory_mmuRsp_physicalAddress,
input io_cpu_memory_mmuRsp_isIoAccess,
input io_cpu_memory_mmuRsp_isPaging,
input io_cpu_memory_mmuRsp_allowRead,
input io_cpu_memory_mmuRsp_allowWrite,
input io_cpu_memory_mmuRsp_allowExecute,
input io_cpu_memory_mmuRsp_exception,
input io_cpu_memory_mmuRsp_refilling,
input io_cpu_memory_mmuRsp_bypassTranslation,
input io_cpu_writeBack_isValid,
input io_cpu_writeBack_isStuck,
input io_cpu_writeBack_isUser,
output reg io_cpu_writeBack_haltIt,
output io_cpu_writeBack_isWrite,
input [31:0] io_cpu_writeBack_storeData,
output reg [31:0] io_cpu_writeBack_data,
input [31:0] io_cpu_writeBack_address,
output io_cpu_writeBack_mmuException,
output io_cpu_writeBack_unalignedAccess,
output reg io_cpu_writeBack_accessError,
output io_cpu_writeBack_keepMemRspData,
input io_cpu_writeBack_fence_SW,
input io_cpu_writeBack_fence_SR,
input io_cpu_writeBack_fence_SO,
input io_cpu_writeBack_fence_SI,
input io_cpu_writeBack_fence_PW,
input io_cpu_writeBack_fence_PR,
input io_cpu_writeBack_fence_PO,
input io_cpu_writeBack_fence_PI,
input [3:0] io_cpu_writeBack_fence_FM,
output io_cpu_writeBack_exclusiveOk,
output reg io_cpu_redo,
input io_cpu_flush_valid,
output io_cpu_flush_ready,
output reg io_mem_cmd_valid,
input io_mem_cmd_ready,
output reg io_mem_cmd_payload_wr,
output io_mem_cmd_payload_uncached,
output reg [31:0] io_mem_cmd_payload_address,
output [31:0] io_mem_cmd_payload_data,
output [3:0] io_mem_cmd_payload_mask,
output reg [2:0] io_mem_cmd_payload_size,
output io_mem_cmd_payload_last,
input io_mem_rsp_valid,
input io_mem_rsp_payload_last,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [21:0] _zz_ways_0_tags_port0;
reg [31:0] _zz_ways_0_data_port0;
wire [21:0] _zz_ways_0_tags_port;
wire [9:0] _zz_stage0_dataColisions;
wire [9:0] _zz__zz_stageA_dataColisions;
wire [0:0] _zz_when;
wire [2:0] _zz_loader_counter_valueNext;
wire [0:0] _zz_loader_counter_valueNext_1;
wire [1:0] _zz_loader_waysAllocator;
reg _zz_1;
reg _zz_2;
wire haltCpu;
reg tagsReadCmd_valid;
reg [6:0] tagsReadCmd_payload;
reg tagsWriteCmd_valid;
reg [0:0] tagsWriteCmd_payload_way;
reg [6:0] tagsWriteCmd_payload_address;
reg tagsWriteCmd_payload_data_valid;
reg tagsWriteCmd_payload_data_error;
reg [19:0] tagsWriteCmd_payload_data_address;
reg tagsWriteLastCmd_valid;
reg [0:0] tagsWriteLastCmd_payload_way;
reg [6:0] tagsWriteLastCmd_payload_address;
reg tagsWriteLastCmd_payload_data_valid;
reg tagsWriteLastCmd_payload_data_error;
reg [19:0] tagsWriteLastCmd_payload_data_address;
reg dataReadCmd_valid;
reg [9:0] dataReadCmd_payload;
reg dataWriteCmd_valid;
reg [0:0] dataWriteCmd_payload_way;
reg [9:0] dataWriteCmd_payload_address;
reg [31:0] dataWriteCmd_payload_data;
reg [3:0] dataWriteCmd_payload_mask;
wire _zz_ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_valid;
wire ways_0_tagsReadRsp_error;
wire [19:0] ways_0_tagsReadRsp_address;
wire [21:0] _zz_ways_0_tagsReadRsp_valid_1;
wire _zz_ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRspMem;
wire [31:0] ways_0_dataReadRsp;
wire when_DataCache_l634;
wire when_DataCache_l637;
wire when_DataCache_l656;
wire rspSync;
wire rspLast;
reg memCmdSent;
wire io_mem_cmd_fire;
wire when_DataCache_l678;
reg [3:0] _zz_stage0_mask;
wire [3:0] stage0_mask;
wire [0:0] stage0_dataColisions;
wire [0:0] stage0_wayInvalidate;
wire stage0_isAmo;
wire when_DataCache_l763;
reg stageA_request_wr;
reg [1:0] stageA_request_size;
reg stageA_request_totalyConsistent;
wire when_DataCache_l763_1;
reg [3:0] stageA_mask;
wire stageA_isAmo;
wire stageA_isLrsc;
wire [0:0] stageA_wayHits;
wire when_DataCache_l763_2;
reg [0:0] stageA_wayInvalidate;
wire when_DataCache_l763_3;
reg [0:0] stage0_dataColisions_regNextWhen;
wire [0:0] _zz_stageA_dataColisions;
wire [0:0] stageA_dataColisions;
wire when_DataCache_l814;
reg stageB_request_wr;
reg [1:0] stageB_request_size;
reg stageB_request_totalyConsistent;
reg stageB_mmuRspFreeze;
wire when_DataCache_l816;
reg [31:0] stageB_mmuRsp_physicalAddress;
reg stageB_mmuRsp_isIoAccess;
reg stageB_mmuRsp_isPaging;
reg stageB_mmuRsp_allowRead;
reg stageB_mmuRsp_allowWrite;
reg stageB_mmuRsp_allowExecute;
reg stageB_mmuRsp_exception;
reg stageB_mmuRsp_refilling;
reg stageB_mmuRsp_bypassTranslation;
wire when_DataCache_l813;
reg stageB_tagsReadRsp_0_valid;
reg stageB_tagsReadRsp_0_error;
reg [19:0] stageB_tagsReadRsp_0_address;
wire when_DataCache_l813_1;
reg [31:0] stageB_dataReadRsp_0;
wire when_DataCache_l812;
reg [0:0] stageB_wayInvalidate;
wire stageB_consistancyHazard;
wire when_DataCache_l812_1;
reg [0:0] stageB_dataColisions;
wire when_DataCache_l812_2;
reg stageB_unaligned;
wire when_DataCache_l812_3;
reg [0:0] stageB_waysHitsBeforeInvalidate;
wire [0:0] stageB_waysHits;
wire stageB_waysHit;
wire [31:0] stageB_dataMux;
wire when_DataCache_l812_4;
reg [3:0] stageB_mask;
reg stageB_loaderValid;
wire [31:0] stageB_ioMemRspMuxed;
reg stageB_flusher_waitDone;
wire stageB_flusher_hold;
reg [7:0] stageB_flusher_counter;
wire when_DataCache_l842;
wire when_DataCache_l848;
reg stageB_flusher_start;
wire stageB_isAmo;
wire stageB_isAmoCached;
wire stageB_isExternalLsrc;
wire stageB_isExternalAmo;
wire [31:0] stageB_requestDataBypass;
reg stageB_cpuWriteToCache;
wire when_DataCache_l911;
wire stageB_badPermissions;
wire stageB_loadStoreFault;
wire stageB_bypassCache;
wire when_DataCache_l980;
wire when_DataCache_l989;
wire when_DataCache_l994;
wire when_DataCache_l1005;
wire when_DataCache_l1017;
wire when_DataCache_l976;
wire when_DataCache_l1051;
wire when_DataCache_l1060;
reg loader_valid;
reg loader_counter_willIncrement;
wire loader_counter_willClear;
reg [2:0] loader_counter_valueNext;
reg [2:0] loader_counter_value;
wire loader_counter_willOverflowIfInc;
wire loader_counter_willOverflow;
reg [0:0] loader_waysAllocator;
reg loader_error;
wire loader_kill;
reg loader_killReg;
wire when_DataCache_l1075;
wire loader_done;
wire when_DataCache_l1103;
reg loader_valid_regNext;
wire when_DataCache_l1107;
wire when_DataCache_l1110;
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023];
(* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023];
reg [7:0] _zz_ways_0_datasymbol_read;
reg [7:0] _zz_ways_0_datasymbol_read_1;
reg [7:0] _zz_ways_0_datasymbol_read_2;
reg [7:0] _zz_ways_0_datasymbol_read_3;
assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0);
assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0);
assign _zz_when = 1'b1;
assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement;
assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1};
assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]};
assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}};
always @(posedge clk) begin
if(_zz_ways_0_tagsReadRsp_valid) begin
_zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(*) begin
_zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read};
end
always @(posedge clk) begin
if(_zz_ways_0_dataReadRspMem) begin
_zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload];
_zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload];
end
end
always @(posedge clk) begin
if(dataWriteCmd_payload_mask[0] && _zz_1) begin
ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0];
end
if(dataWriteCmd_payload_mask[1] && _zz_1) begin
ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8];
end
if(dataWriteCmd_payload_mask[2] && _zz_1) begin
ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16];
end
if(dataWriteCmd_payload_mask[3] && _zz_1) begin
ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(when_DataCache_l637) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(when_DataCache_l634) begin
_zz_2 = 1'b1;
end
end
assign haltCpu = 1'b0;
assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck));
assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0;
assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0];
assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1];
assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2];
assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck));
assign ways_0_dataReadRspMem = _zz_ways_0_data_port0;
assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0];
assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]);
assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]);
always @(*) begin
tagsReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
tagsReadCmd_valid = 1'b1;
end
end
always @(*) begin
tagsReadCmd_payload = 7'bxxxxxxx;
if(when_DataCache_l656) begin
tagsReadCmd_payload = io_cpu_execute_address[11 : 5];
end
end
always @(*) begin
dataReadCmd_valid = 1'b0;
if(when_DataCache_l656) begin
dataReadCmd_valid = 1'b1;
end
end
always @(*) begin
dataReadCmd_payload = 10'bxxxxxxxxxx;
if(when_DataCache_l656) begin
dataReadCmd_payload = io_cpu_execute_address[11 : 2];
end
end
always @(*) begin
tagsWriteCmd_valid = 1'b0;
if(when_DataCache_l842) begin
tagsWriteCmd_valid = 1'b1;
end
if(when_DataCache_l1051) begin
tagsWriteCmd_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_valid = 1'b1;
end
end
always @(*) begin
tagsWriteCmd_payload_way = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_way = 1'b1;
end
if(loader_done) begin
tagsWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
tagsWriteCmd_payload_address = 7'bxxxxxxx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_address = stageB_flusher_counter[6:0];
end
if(loader_done) begin
tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5];
end
end
always @(*) begin
tagsWriteCmd_payload_data_valid = 1'bx;
if(when_DataCache_l842) begin
tagsWriteCmd_payload_data_valid = 1'b0;
end
if(loader_done) begin
tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg));
end
end
always @(*) begin
tagsWriteCmd_payload_data_error = 1'bx;
if(loader_done) begin
tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error));
end
end
always @(*) begin
tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx;
if(loader_done) begin
tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12];
end
end
always @(*) begin
dataWriteCmd_valid = 1'b0;
if(stageB_cpuWriteToCache) begin
if(when_DataCache_l911) begin
dataWriteCmd_valid = 1'b1;
end
end
if(when_DataCache_l1051) begin
dataWriteCmd_valid = 1'b0;
end
if(when_DataCache_l1075) begin
dataWriteCmd_valid = 1'b1;
end
end
always @(*) begin
dataWriteCmd_payload_way = 1'bx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_way = stageB_waysHits;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_way = loader_waysAllocator;
end
end
always @(*) begin
dataWriteCmd_payload_address = 10'bxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2];
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value};
end
end
always @(*) begin
dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass;
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_data = io_mem_rsp_payload_data;
end
end
always @(*) begin
dataWriteCmd_payload_mask = 4'bxxxx;
if(stageB_cpuWriteToCache) begin
dataWriteCmd_payload_mask = 4'b0000;
if(_zz_when[0]) begin
dataWriteCmd_payload_mask[3 : 0] = stageB_mask;
end
end
if(when_DataCache_l1075) begin
dataWriteCmd_payload_mask = 4'b1111;
end
end
assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck));
always @(*) begin
io_cpu_execute_haltIt = 1'b0;
if(when_DataCache_l842) begin
io_cpu_execute_haltIt = 1'b1;
end
end
assign rspSync = 1'b1;
assign rspLast = 1'b1;
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck);
always @(*) begin
_zz_stage0_mask = 4'bxxxx;
case(io_cpu_execute_args_size)
2'b00 : begin
_zz_stage0_mask = 4'b0001;
end
2'b01 : begin
_zz_stage0_mask = 4'b0011;
end
2'b10 : begin
_zz_stage0_mask = 4'b1111;
end
default : begin
end
endcase
end
assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]);
assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stage0_wayInvalidate = 1'b0;
assign stage0_isAmo = 1'b0;
assign when_DataCache_l763 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck);
assign io_cpu_memory_isWrite = stageA_request_wr;
assign stageA_isAmo = 1'b0;
assign stageA_isLrsc = 1'b0;
assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid);
assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck);
assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck);
assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000));
assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions);
assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_mmuRspFreeze = 1'b0;
if(when_DataCache_l1110) begin
stageB_mmuRspFreeze = 1'b1;
end
end
assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze));
assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck);
assign stageB_consistancyHazard = 1'b0;
assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck);
assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck);
assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate));
assign stageB_waysHit = (stageB_waysHits != 1'b0);
assign stageB_dataMux = stageB_dataReadRsp_0;
assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck);
always @(*) begin
stageB_loaderValid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
if(io_mem_cmd_ready) begin
stageB_loaderValid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
stageB_loaderValid = 1'b0;
end
end
assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0];
always @(*) begin
io_cpu_writeBack_haltIt = 1'b1;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
if(when_DataCache_l980) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end else begin
if(when_DataCache_l989) begin
if(when_DataCache_l994) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_cpu_writeBack_haltIt = 1'b0;
end
end
assign stageB_flusher_hold = 1'b0;
assign when_DataCache_l842 = (! stageB_flusher_counter[7]);
assign when_DataCache_l848 = (! stageB_flusher_hold);
assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]);
assign stageB_isAmo = 1'b0;
assign stageB_isAmoCached = 1'b0;
assign stageB_isExternalLsrc = 1'b0;
assign stageB_isExternalAmo = 1'b0;
assign stageB_requestDataBypass = io_cpu_writeBack_storeData;
always @(*) begin
stageB_cpuWriteToCache = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
stageB_cpuWriteToCache = 1'b1;
end
end
end
end
end
assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit);
assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)));
assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions));
always @(*) begin
io_cpu_redo = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(when_DataCache_l989) begin
if(when_DataCache_l1005) begin
io_cpu_redo = 1'b1;
end
end
end
end
end
if(when_DataCache_l1060) begin
io_cpu_redo = 1'b1;
end
if(when_DataCache_l1107) begin
io_cpu_redo = 1'b1;
end
end
always @(*) begin
io_cpu_writeBack_accessError = 1'b0;
if(stageB_bypassCache) begin
io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error);
end else begin
io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging)));
end
end
assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging);
assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned);
assign io_cpu_writeBack_isWrite = stageB_request_wr;
always @(*) begin
io_mem_cmd_valid = 1'b0;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(when_DataCache_l976) begin
io_mem_cmd_valid = (! memCmdSent);
end else begin
if(when_DataCache_l989) begin
if(stageB_request_wr) begin
io_mem_cmd_valid = 1'b1;
end
end else begin
if(when_DataCache_l1017) begin
io_mem_cmd_valid = 1'b1;
end
end
end
end
end
if(when_DataCache_l1051) begin
io_mem_cmd_valid = 1'b0;
end
end
always @(*) begin
io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_address[4 : 0] = 5'h0;
end
end
end
end
end
assign io_mem_cmd_payload_last = 1'b1;
always @(*) begin
io_mem_cmd_payload_wr = stageB_request_wr;
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_wr = 1'b0;
end
end
end
end
end
assign io_mem_cmd_payload_mask = stageB_mask;
assign io_mem_cmd_payload_data = stageB_requestDataBypass;
assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess;
always @(*) begin
io_mem_cmd_payload_size = {1'd0, stageB_request_size};
if(io_cpu_writeBack_isValid) begin
if(!stageB_isExternalAmo) begin
if(!when_DataCache_l976) begin
if(!when_DataCache_l989) begin
io_mem_cmd_payload_size = 3'b101;
end
end
end
end
end
assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo);
assign io_cpu_writeBack_keepMemRspData = 1'b0;
assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready);
assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached)));
assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready);
assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0));
assign when_DataCache_l1017 = (! memCmdSent);
assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc);
always @(*) begin
if(stageB_bypassCache) begin
io_cpu_writeBack_data = stageB_ioMemRspMuxed;
end else begin
io_cpu_writeBack_data = stageB_dataMux;
end
end
assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess);
assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard));
always @(*) begin
loader_counter_willIncrement = 1'b0;
if(when_DataCache_l1075) begin
loader_counter_willIncrement = 1'b1;
end
end
assign loader_counter_willClear = 1'b0;
assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111);
assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement);
always @(*) begin
loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext);
if(loader_counter_willClear) begin
loader_counter_valueNext = 3'b000;
end
end
assign loader_kill = 1'b0;
assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast);
assign loader_done = loader_counter_willOverflow;
assign when_DataCache_l1103 = (! loader_valid);
assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext));
assign io_cpu_execute_refilling = loader_valid;
assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid);
always @(posedge clk) begin
tagsWriteLastCmd_valid <= tagsWriteCmd_valid;
tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way;
tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address;
tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid;
tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error;
tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address;
if(when_DataCache_l763) begin
stageA_request_wr <= io_cpu_execute_args_wr;
stageA_request_size <= io_cpu_execute_args_size;
stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent;
end
if(when_DataCache_l763_1) begin
stageA_mask <= stage0_mask;
end
if(when_DataCache_l763_2) begin
stageA_wayInvalidate <= stage0_wayInvalidate;
end
if(when_DataCache_l763_3) begin
stage0_dataColisions_regNextWhen <= stage0_dataColisions;
end
if(when_DataCache_l814) begin
stageB_request_wr <= stageA_request_wr;
stageB_request_size <= stageA_request_size;
stageB_request_totalyConsistent <= stageA_request_totalyConsistent;
end
if(when_DataCache_l816) begin
stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress;
stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess;
stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging;
stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead;
stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite;
stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute;
stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception;
stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling;
stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation;
end
if(when_DataCache_l813) begin
stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid;
stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error;
stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address;
end
if(when_DataCache_l813_1) begin
stageB_dataReadRsp_0 <= ways_0_dataReadRsp;
end
if(when_DataCache_l812) begin
stageB_wayInvalidate <= stageA_wayInvalidate;
end
if(when_DataCache_l812_1) begin
stageB_dataColisions <= stageA_dataColisions;
end
if(when_DataCache_l812_2) begin
stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00);
end
if(when_DataCache_l812_3) begin
stageB_waysHitsBeforeInvalidate <= stageA_wayHits;
end
if(when_DataCache_l812_4) begin
stageB_mask <= stageA_mask;
end
loader_valid_regNext <= loader_valid;
end
always @(posedge clk) begin
if(reset) begin
memCmdSent <= 1'b0;
stageB_flusher_waitDone <= 1'b0;
stageB_flusher_counter <= 8'h0;
stageB_flusher_start <= 1'b1;
loader_valid <= 1'b0;
loader_counter_value <= 3'b000;
loader_waysAllocator <= 1'b1;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end else begin
if(io_mem_cmd_fire) begin
memCmdSent <= 1'b1;
end
if(when_DataCache_l678) begin
memCmdSent <= 1'b0;
end
if(io_cpu_flush_ready) begin
stageB_flusher_waitDone <= 1'b0;
end
if(when_DataCache_l842) begin
if(when_DataCache_l848) begin
stageB_flusher_counter <= (stageB_flusher_counter + 8'h01);
end
end
stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo));
if(stageB_flusher_start) begin
stageB_flusher_waitDone <= 1'b1;
stageB_flusher_counter <= 8'h0;
end
`ifndef SYNTHESIS
`ifdef FORMAL
assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck)));
`else
if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin
$display("ERROR writeBack stuck by another plugin is not allowed");
end
`endif
`endif
if(stageB_loaderValid) begin
loader_valid <= 1'b1;
end
loader_counter_value <= loader_counter_valueNext;
if(loader_kill) begin
loader_killReg <= 1'b1;
end
if(when_DataCache_l1075) begin
loader_error <= (loader_error || io_mem_rsp_payload_error);
end
if(loader_done) begin
loader_valid <= 1'b0;
loader_error <= 1'b0;
loader_killReg <= 1'b0;
end
if(when_DataCache_l1103) begin
loader_waysAllocator <= _zz_loader_waysAllocator[0:0];
end
end
end
endmodule
module InstructionCache (
input io_flush,
input io_cpu_prefetch_isValid,
output reg io_cpu_prefetch_haltIt,
input [31:0] io_cpu_prefetch_pc,
input io_cpu_fetch_isValid,
input io_cpu_fetch_isStuck,
input io_cpu_fetch_isRemoved,
input [31:0] io_cpu_fetch_pc,
output [31:0] io_cpu_fetch_data,
input [31:0] io_cpu_fetch_mmuRsp_physicalAddress,
input io_cpu_fetch_mmuRsp_isIoAccess,
input io_cpu_fetch_mmuRsp_isPaging,
input io_cpu_fetch_mmuRsp_allowRead,
input io_cpu_fetch_mmuRsp_allowWrite,
input io_cpu_fetch_mmuRsp_allowExecute,
input io_cpu_fetch_mmuRsp_exception,
input io_cpu_fetch_mmuRsp_refilling,
input io_cpu_fetch_mmuRsp_bypassTranslation,
output [31:0] io_cpu_fetch_physicalAddress,
input io_cpu_decode_isValid,
input io_cpu_decode_isStuck,
input [31:0] io_cpu_decode_pc,
output [31:0] io_cpu_decode_physicalAddress,
output [31:0] io_cpu_decode_data,
output io_cpu_decode_cacheMiss,
output io_cpu_decode_error,
output io_cpu_decode_mmuRefilling,
output io_cpu_decode_mmuException,
input io_cpu_decode_isUser,
input io_cpu_fill_valid,
input [31:0] io_cpu_fill_payload,
output io_mem_cmd_valid,
input io_mem_cmd_ready,
output [31:0] io_mem_cmd_payload_address,
output [2:0] io_mem_cmd_payload_size,
input io_mem_rsp_valid,
input [31:0] io_mem_rsp_payload_data,
input io_mem_rsp_payload_error,
input clk,
input reset
);
reg [31:0] _zz_banks_0_port1;
reg [21:0] _zz_ways_0_tags_port1;
wire [21:0] _zz_ways_0_tags_port;
reg _zz_1;
reg _zz_2;
reg lineLoader_fire;
reg lineLoader_valid;
(* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ;
reg lineLoader_hadError;
reg lineLoader_flushPending;
reg [7:0] lineLoader_flushCounter;
wire when_InstructionCache_l338;
reg _zz_when_InstructionCache_l342;
wire when_InstructionCache_l342;
wire when_InstructionCache_l351;
reg lineLoader_cmdSent;
wire io_mem_cmd_fire;
wire when_Utils_l357;
reg lineLoader_wayToAllocate_willIncrement;
wire lineLoader_wayToAllocate_willClear;
wire lineLoader_wayToAllocate_willOverflowIfInc;
wire lineLoader_wayToAllocate_willOverflow;
(* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ;
wire lineLoader_write_tag_0_valid;
wire [6:0] lineLoader_write_tag_0_payload_address;
wire lineLoader_write_tag_0_payload_data_valid;
wire lineLoader_write_tag_0_payload_data_error;
wire [19:0] lineLoader_write_tag_0_payload_data_address;
wire lineLoader_write_data_0_valid;
wire [9:0] lineLoader_write_data_0_payload_address;
wire [31:0] lineLoader_write_data_0_payload_data;
wire when_InstructionCache_l401;
wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem;
wire _zz_fetchStage_read_banksValue_0_dataMem_1;
wire [31:0] fetchStage_read_banksValue_0_dataMem;
wire [31:0] fetchStage_read_banksValue_0_data;
wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid;
wire _zz_fetchStage_read_waysValues_0_tag_valid_1;
wire fetchStage_read_waysValues_0_tag_valid;
wire fetchStage_read_waysValues_0_tag_error;
wire [19:0] fetchStage_read_waysValues_0_tag_address;
wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2;
wire fetchStage_hit_hits_0;
wire fetchStage_hit_valid;
wire fetchStage_hit_error;
wire [31:0] fetchStage_hit_data;
wire [31:0] fetchStage_hit_word;
wire when_InstructionCache_l435;
reg [31:0] io_cpu_fetch_data_regNextWhen;
wire when_InstructionCache_l459;
reg [31:0] decodeStage_mmuRsp_physicalAddress;
reg decodeStage_mmuRsp_isIoAccess;
reg decodeStage_mmuRsp_isPaging;
reg decodeStage_mmuRsp_allowRead;
reg decodeStage_mmuRsp_allowWrite;
reg decodeStage_mmuRsp_allowExecute;
reg decodeStage_mmuRsp_exception;
reg decodeStage_mmuRsp_refilling;
reg decodeStage_mmuRsp_bypassTranslation;
wire when_InstructionCache_l459_1;
reg decodeStage_hit_valid;
wire when_InstructionCache_l459_2;
reg decodeStage_hit_error;
(* ram_style = "block" *) reg [31:0] banks_0 [0:1023];
(* ram_style = "block" *) reg [21:0] ways_0_tags [0:127];
assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}};
always @(posedge clk) begin
if(_zz_1) begin
banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin
_zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem];
end
end
always @(posedge clk) begin
if(_zz_2) begin
ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port;
end
end
always @(posedge clk) begin
if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin
_zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid];
end
end
always @(*) begin
_zz_1 = 1'b0;
if(lineLoader_write_data_0_valid) begin
_zz_1 = 1'b1;
end
end
always @(*) begin
_zz_2 = 1'b0;
if(lineLoader_write_tag_0_valid) begin
_zz_2 = 1'b1;
end
end
always @(*) begin
lineLoader_fire = 1'b0;
if(io_mem_rsp_valid) begin
if(when_InstructionCache_l401) begin
lineLoader_fire = 1'b1;
end
end
end
always @(*) begin
io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending);
if(when_InstructionCache_l338) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(when_InstructionCache_l342) begin
io_cpu_prefetch_haltIt = 1'b1;
end
if(io_flush) begin
io_cpu_prefetch_haltIt = 1'b1;
end
end
assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]);
assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342);
assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid)));
assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready);
assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent));
assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0};
assign io_mem_cmd_payload_size = 3'b101;
assign when_Utils_l357 = (! lineLoader_valid);
always @(*) begin
lineLoader_wayToAllocate_willIncrement = 1'b0;
if(when_Utils_l357) begin
lineLoader_wayToAllocate_willIncrement = 1'b1;
end
end
assign lineLoader_wayToAllocate_willClear = 1'b0;
assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1;
assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement);
assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7]));
assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]);
assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7];
assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error);
assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12];
assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1);
assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex};
assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data;
assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111);
assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2];
assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck);
assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1;
assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0];
assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5];
assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck);
assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1;
assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0];
assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1];
assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2];
assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12]));
assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0);
assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error;
assign fetchStage_hit_data = fetchStage_read_banksValue_0_data;
assign fetchStage_hit_word = fetchStage_hit_data;
assign io_cpu_fetch_data = fetchStage_hit_word;
assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen;
assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress;
assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck);
assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck);
assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid);
assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))));
assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling;
assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)));
assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress;
always @(posedge clk) begin
if(reset) begin
lineLoader_valid <= 1'b0;
lineLoader_hadError <= 1'b0;
lineLoader_flushPending <= 1'b1;
lineLoader_cmdSent <= 1'b0;
lineLoader_wordIndex <= 3'b000;
end else begin
if(lineLoader_fire) begin
lineLoader_valid <= 1'b0;
end
if(lineLoader_fire) begin
lineLoader_hadError <= 1'b0;
end
if(io_cpu_fill_valid) begin
lineLoader_valid <= 1'b1;
end
if(io_flush) begin
lineLoader_flushPending <= 1'b1;
end
if(when_InstructionCache_l351) begin
lineLoader_flushPending <= 1'b0;
end
if(io_mem_cmd_fire) begin
lineLoader_cmdSent <= 1'b1;
end
if(lineLoader_fire) begin
lineLoader_cmdSent <= 1'b0;
end
if(io_mem_rsp_valid) begin
lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001);
if(io_mem_rsp_payload_error) begin
lineLoader_hadError <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if(io_cpu_fill_valid) begin
lineLoader_address <= io_cpu_fill_payload;
end
if(when_InstructionCache_l338) begin
lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01);
end
_zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7];
if(when_InstructionCache_l351) begin
lineLoader_flushCounter <= 8'h0;
end
if(when_InstructionCache_l435) begin
io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data;
end
if(when_InstructionCache_l459) begin
decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress;
decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess;
decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging;
decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead;
decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite;
decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute;
decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception;
decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling;
decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation;
end
if(when_InstructionCache_l459_1) begin
decodeStage_hit_valid <= fetchStage_hit_valid;
end
if(when_InstructionCache_l459_2) begin
decodeStage_hit_error <= fetchStage_hit_error;
end
end
endmodule
|
/*******************************************************************************
* Module: sata_device
* Date: 2015-07-11
* Author: Alexey
* Description: sata device emul top level
*
* Copyright (c) 2015 Elphel, Inc.
* sata_device.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* sata_device.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
//`include "sata_phy_dev.v"
module sata_device(
input wire rst,
input wire RXN,
input wire RXP,
output wire TXN,
output wire TXP,
input wire EXTCLK_P,
input wire EXTCLK_N
);
`include "includes/fis_types.vh"
//`ifdef SIMULATION
reg [639:0] DEV_TITLE = 'bz; // to show human-readable state in the GTKWave
// reg [31:0] DEV_DATA;
integer DEV_DATA;
//`endif
//`define TERMINATE_DMA_H2D
//`undef TERMINATE_DMA_H2D
wire phy_ready;
wire [31:0] phy2dev_data;
wire [3:0] phy2dev_charisk;
wire [3:0] phy2dev_err;
wire clk;
wire dev_rst;
reg [31:0] dev2phy_data = 32'hB5B5957C; // SYNCP
reg [3:0] dev2phy_isk = 4'h1;
reg [2:0] phy_ready_syncp_r; // allow device to send 3 SYNCp before getting ready
reg [4:0] serial_delay = 7; // delay output to check host alignment
localparam DEV_ALIGN_PERIOD = 32; // make it more frequent than 250
//integer align_cntr = DEV_ALIGN_PERIOD;
reg [7:0] align_cntr = DEV_ALIGN_PERIOD;
initial forever @ (posedge clk) begin
if (align_cntr > 0) align_cntr = align_cntr - 1;
end
task send_align_pair_if_needed;
if (align_cntr ==0) begin
dev2phy_data <= PRIM_ALIGNP;
dev2phy_isk <= 4'h1;
align_cntr = DEV_ALIGN_PERIOD;
@ (posedge clk);
@ (posedge clk);
end
endtask
sata_phy_dev phy(
// pll reset
.extrst (rst),
// top-level ifaces
// ref clk from an external source, shall be connected to pads
.extclk_p (EXTCLK_P),
.extclk_n (EXTCLK_N),
// sata link data pins
.txp_out (TXP),
.txn_out (TXN),
.rxp_in (RXP),
.rxn_in (RXN),
.clk (clk),
.rst (dev_rst),
.phy_ready (phy_ready),
.ll_data_out (phy2dev_data),
.ll_charisk_out (phy2dev_charisk),
.ll_err_out (phy2dev_err),
.ll_data_in (dev2phy_data),
.ll_charisk_in (dev2phy_isk),
.serial_delay (serial_delay) // delay output to check host alignment
);
localparam [31:0] PRIM_SYNCP = {3'd5, 5'd21, 3'd5, 5'd21, 3'd4, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_ALIGNP = {3'd3, 5'd27, 3'd2, 5'd10, 3'd2, 5'd10, 3'd5, 5'd28};
localparam [31:0] PRIM_XRDYP = {3'd2, 5'd23, 3'd2, 5'd23, 3'd5, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_SOFP = {3'd1, 5'd23, 3'd1, 5'd23, 3'd5, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_HOLDAP = {3'd4, 5'd21, 3'd4, 5'd21, 3'd5, 5'd10, 3'd3, 5'd28};
localparam [31:0] PRIM_HOLDP = {3'd6, 5'd21, 3'd6, 5'd21, 3'd5, 5'd10, 3'd3, 5'd28};
localparam [31:0] PRIM_EOFP = {3'd6, 5'd21, 3'd6, 5'd21, 3'd5, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_WTRMP = {3'd2, 5'd24, 3'd2, 5'd24, 3'd5, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_RRDYP = {3'd2, 5'd10, 3'd2, 5'd10, 3'd4, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_IPP = {3'd2, 5'd21, 3'd2, 5'd21, 3'd5, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_DMATP = {3'd1, 5'd22, 3'd1, 5'd22, 3'd5, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_OKP = {3'd1, 5'd21, 3'd1, 5'd21, 3'd5, 5'd21, 3'd3, 5'd28};
localparam [31:0] PRIM_ERRP = {3'd2, 5'd22, 3'd2, 5'd22, 3'd5, 5'd21, 3'd3, 5'd28};
initial begin
$display("LIST OF PRIMITIVES:");
$display("SYNC = %x", PRIM_SYNCP );
$display("ALIGN = %x", PRIM_ALIGNP);
$display("XRDY = %x", PRIM_XRDYP );
$display("SOF = %x", PRIM_SOFP );
$display("HOLDA = %x", PRIM_HOLDAP);
$display("HOLD = %x", PRIM_HOLDP );
$display("EOF = %x", PRIM_EOFP );
$display("WTRM = %x", PRIM_WTRMP );
$display("RRDY = %x", PRIM_RRDYP );
$display("IP = %x", PRIM_IPP );
$display("DMAT = %x", PRIM_DMATP );
$display("OK = %x", PRIM_OKP );
$display("ERR = %x", PRIM_ERRP );
end
integer transmit_lock = 0;
integer receive_lock = 0;
integer suppress_receive = 0;
reg [31:0] receive_data [2047:0];
reg [31:0] receive_data_pause [2047:0];
integer received_size; // number of data FIS payload dwords received (minus head and CRC)
reg [31:0] receive_wait_fifo;
reg [31:0] receive_crc;
integer receive_id = 0;
integer receive_status = 0;
/*
* Monitor incoming primitives every clock cycle
* if there is a data transfer request, start a receive sequence
*/
initial forever @ (posedge clk) begin
if (~transmit_lock) begin
// transmitting sequence is not started
if (~receive_lock) begin
// if for the current xrdy stream we haven't aready started a receiving sequence
if (~suppress_receive) begin
// if we do not intentionally ignore host's transmissions
if (linkGetPrim(0) == "XRDY") begin
linkMonitorFIS(receive_id, 2049, receive_status);
receive_id = receive_id + 1;
end
end
end
end
end
function [31:0] scrambleFunc; //SuppressThisWarning VEditor: VDT bug? it is used
input [31:0] context;
reg [31:0] next;
reg [15:0] now;
begin
now = context[15:0];
next[31] = now[12] ^ now[10] ^ now[7] ^ now[3] ^ now[1] ^ now[0];
next[30] = now[15] ^ now[14] ^ now[12] ^ now[11] ^ now[9] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
next[29] = now[15] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[8] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
next[28] = now[14] ^ now[12] ^ now[11] ^ now[10] ^ now[9] ^ now[7] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
next[27] = now[15] ^ now[14] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[9] ^ now[8] ^ now[6] ^ now[1] ^ now[0];
next[26] = now[15] ^ now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[8] ^ now[7] ^ now[5] ^ now[3] ^ now[0];
next[25] = now[15] ^ now[10] ^ now[9] ^ now[8] ^ now[7] ^ now[6] ^ now[4] ^ now[3] ^ now[2];
next[24] = now[14] ^ now[9] ^ now[8] ^ now[7] ^ now[6] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
next[23] = now[13] ^ now[8] ^ now[7] ^ now[6] ^ now[5] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
next[22] = now[15] ^ now[14] ^ now[7] ^ now[6] ^ now[5] ^ now[4] ^ now[1] ^ now[0];
next[21] = now[15] ^ now[13] ^ now[12] ^ now[6] ^ now[5] ^ now[4] ^ now[0];
next[20] = now[15] ^ now[11] ^ now[5] ^ now[4];
next[19] = now[14] ^ now[10] ^ now[4] ^ now[3];
next[18] = now[13] ^ now[9] ^ now[3] ^ now[2];
next[17] = now[12] ^ now[8] ^ now[2] ^ now[1];
next[16] = now[11] ^ now[7] ^ now[1] ^ now[0];
next[15] = now[15] ^ now[14] ^ now[12] ^ now[10] ^ now[6] ^ now[3] ^ now[0];
next[14] = now[15] ^ now[13] ^ now[12] ^ now[11] ^ now[9] ^ now[5] ^ now[3] ^ now[2];
next[13] = now[14] ^ now[12] ^ now[11] ^ now[10] ^ now[8] ^ now[4] ^ now[2] ^ now[1];
next[12] = now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[7] ^ now[3] ^ now[1] ^ now[0];
next[11] = now[15] ^ now[14] ^ now[10] ^ now[9] ^ now[8] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
next[10] = now[15] ^ now[13] ^ now[12] ^ now[9] ^ now[8] ^ now[7] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
next[9] = now[14] ^ now[12] ^ now[11] ^ now[8] ^ now[7] ^ now[6] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
next[8] = now[15] ^ now[14] ^ now[13] ^ now[12] ^ now[11] ^ now[10] ^ now[7] ^ now[6] ^ now[5] ^ now[1] ^ now[0];
next[7] = now[15] ^ now[13] ^ now[11] ^ now[10] ^ now[9] ^ now[6] ^ now[5] ^ now[4] ^ now[3] ^ now[0];
next[6] = now[15] ^ now[10] ^ now[9] ^ now[8] ^ now[5] ^ now[4] ^ now[2];
next[5] = now[14] ^ now[9] ^ now[8] ^ now[7] ^ now[4] ^ now[3] ^ now[1];
next[4] = now[13] ^ now[8] ^ now[7] ^ now[6] ^ now[3] ^ now[2] ^ now[0];
next[3] = now[15] ^ now[14] ^ now[7] ^ now[6] ^ now[5] ^ now[3] ^ now[2] ^ now[1];
next[2] = now[14] ^ now[13] ^ now[6] ^ now[5] ^ now[4] ^ now[2] ^ now[1] ^ now[0];
next[1] = now[15] ^ now[14] ^ now[13] ^ now[5] ^ now[4] ^ now[1] ^ now[0];
next[0] = now[15] ^ now[13] ^ now[4] ^ now[0];
scrambleFunc = next;
end
endfunction
function [31:0] calculateCRC; //SuppressThisWarning VEditor VDT bug, it is used
input [31:0] seed;
input [31:0] data;
reg [31:0] crc_bit;
reg [31:0] new_bit;
begin
crc_bit = seed ^ data;
new_bit[31] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[24] ^
crc_bit[23] ^ crc_bit[15] ^ crc_bit[11] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[5];
new_bit[30] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^
crc_bit[22] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[4];
new_bit[29] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[23] ^
crc_bit[22] ^ crc_bit[21] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[3];
new_bit[28] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[22] ^
crc_bit[21] ^ crc_bit[20] ^ crc_bit[12] ^ crc_bit[8] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[2];
new_bit[27] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[21] ^
crc_bit[20] ^ crc_bit[19] ^ crc_bit[11] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[1];
new_bit[26] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[22] ^
crc_bit[20] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[10] ^ crc_bit[6] ^ crc_bit[4] ^ crc_bit[3] ^
crc_bit[0];
new_bit[25] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[19] ^ crc_bit[18] ^
crc_bit[17] ^ crc_bit[15] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[3] ^ crc_bit[2];
new_bit[24] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^ crc_bit[17] ^
crc_bit[16] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[2] ^ crc_bit[1];
new_bit[23] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[17] ^
crc_bit[16] ^ crc_bit[15] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[1] ^ crc_bit[0];
new_bit[22] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[19] ^
crc_bit[18] ^ crc_bit[16] ^ crc_bit[14] ^ crc_bit[12] ^ crc_bit[11] ^ crc_bit[9] ^ crc_bit[0];
new_bit[21] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[18] ^
crc_bit[17] ^ crc_bit[13] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[5];
new_bit[20] = crc_bit[30] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[23] ^ crc_bit[21] ^ crc_bit[17] ^
crc_bit[16] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[4];
new_bit[19] = crc_bit[29] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[20] ^ crc_bit[16] ^
crc_bit[15] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[3];
new_bit[18] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[21] ^ crc_bit[19] ^
crc_bit[15] ^ crc_bit[14] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[2];
new_bit[17] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[20] ^
crc_bit[18] ^ crc_bit[14] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[1];
new_bit[16] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[19] ^
crc_bit[17] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[8] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[0];
new_bit[15] = crc_bit[30] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[18] ^ crc_bit[16] ^
crc_bit[15] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[4] ^
crc_bit[3];
new_bit[14] = crc_bit[29] ^ crc_bit[26] ^ crc_bit[23] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[17] ^ crc_bit[15] ^
crc_bit[14] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[4] ^ crc_bit[3] ^
crc_bit[2];
new_bit[13] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[25] ^ crc_bit[22] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[16] ^
crc_bit[14] ^ crc_bit[13] ^ crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[3] ^
crc_bit[2] ^ crc_bit[1];
new_bit[12] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[18] ^ crc_bit[17] ^
crc_bit[15] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^
crc_bit[2] ^ crc_bit[1] ^ crc_bit[0];
new_bit[11] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[27] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[20] ^
crc_bit[17] ^ crc_bit[16] ^ crc_bit[15] ^ crc_bit[14] ^ crc_bit[12] ^ crc_bit[9] ^ crc_bit[4] ^
crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
new_bit[10] = crc_bit[31] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[19] ^ crc_bit[16] ^ crc_bit[14] ^
crc_bit[13] ^ crc_bit[9] ^ crc_bit[5] ^ crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
new_bit[9] = crc_bit[29] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[18] ^ crc_bit[13] ^ crc_bit[12] ^ crc_bit[11] ^
crc_bit[9] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[2] ^ crc_bit[1];
new_bit[8] = crc_bit[31] ^ crc_bit[28] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[17] ^ crc_bit[12] ^ crc_bit[11] ^
crc_bit[10] ^ crc_bit[8] ^ crc_bit[4] ^ crc_bit[3] ^ crc_bit[1] ^ crc_bit[0];
new_bit[7] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[23] ^ crc_bit[22] ^ crc_bit[21] ^
crc_bit[16] ^ crc_bit[15] ^ crc_bit[10] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[5] ^ crc_bit[3] ^
crc_bit[2] ^ crc_bit[0];
new_bit[6] = crc_bit[30] ^ crc_bit[29] ^ crc_bit[25] ^ crc_bit[22] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[14] ^
crc_bit[11] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[2] ^
crc_bit[1];
new_bit[5] = crc_bit[29] ^ crc_bit[28] ^ crc_bit[24] ^ crc_bit[21] ^ crc_bit[20] ^ crc_bit[19] ^ crc_bit[13] ^
crc_bit[10] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[5] ^ crc_bit[4] ^ crc_bit[3] ^ crc_bit[1] ^
crc_bit[0];
new_bit[4] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[25] ^ crc_bit[24] ^ crc_bit[20] ^ crc_bit[19] ^
crc_bit[18] ^ crc_bit[15] ^ crc_bit[12] ^ crc_bit[11] ^ crc_bit[8] ^ crc_bit[6] ^ crc_bit[4] ^
crc_bit[3] ^ crc_bit[2] ^ crc_bit[0];
new_bit[3] = crc_bit[31] ^ crc_bit[27] ^ crc_bit[25] ^ crc_bit[19] ^ crc_bit[18] ^ crc_bit[17] ^ crc_bit[15] ^
crc_bit[14] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[3] ^ crc_bit[2] ^
crc_bit[1];
new_bit[2] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[26] ^ crc_bit[24] ^ crc_bit[18] ^ crc_bit[17] ^ crc_bit[16] ^
crc_bit[14] ^ crc_bit[13] ^ crc_bit[9] ^ crc_bit[8] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[2] ^
crc_bit[1] ^ crc_bit[0];
new_bit[1] = crc_bit[28] ^ crc_bit[27] ^ crc_bit[24] ^ crc_bit[17] ^ crc_bit[16] ^ crc_bit[13] ^ crc_bit[12] ^
crc_bit[11] ^ crc_bit[9] ^ crc_bit[7] ^ crc_bit[6] ^ crc_bit[1] ^ crc_bit[0];
new_bit[0] = crc_bit[31] ^ crc_bit[30] ^ crc_bit[29] ^ crc_bit[28] ^ crc_bit[26] ^ crc_bit[25] ^ crc_bit[24] ^
crc_bit[16] ^ crc_bit[12] ^ crc_bit[10] ^ crc_bit[9] ^ crc_bit[6] ^ crc_bit[0];
calculateCRC = new_bit;
end
endfunction
// stub TODO
function tranCheckFIS; //SuppressThisWarning VEditor: VDT bug - the function is used in conditional expression
input count;
begin
// $display("[Device] TRANSPORT: Says the FIS is valid");
DEV_TITLE = "Says the FIS is valid";
$display("[Device] TRANSPORT: %s @%t", DEV_TITLE, $time);
tranCheckFIS = 0; // always tell LL the FIS os OK
end
endfunction
// TODO align every 256 dwords!
/*
* Receives data from a host. ~Link Receive FSM
* Correct execution, as it shall be w/o errors from a device side.
*
* Received data is stored in receive_data memory.
* Data is received by a dword // TODO make support for uneven words (16bit each) count
*
* Each data bundle has corresponding "pause" register, stored in a memory 'receive_data_pause'
* It represents a time (in clock cycles), for which the device shall send HOLD primitives after
* current data bundle reception. If after HOLD request data is still coming, consequetive 'pause's are summed up.
* Could be used to test timeout watchdogs of the host.
*
* receive_wait_fifo shows how many clock cycles receiver shall spent before it allows the host to transmit data
*
* Parameters:
* id - reception id, shown in logs
* dmat_index - after this count of received data dwords DMAT primitive would be sent to the line
* status - returns 0 when the host acknowledges the transaction with OK code,
* 1 when with ERR code
* if it's 1, there are 3 options:
* a) Generated CRC is invalid
* b) Scrambler messed up
* c) There is an error in the host
*/
task linkMonitorFIS;
input integer id;
input integer dmat_index;
output integer status;
reg [111:0] rprim;
integer pause;
integer rcv_stop;
integer rcv_ignore;
integer cnt;
reg [31:0] descrambled_data;
reg [31:0] scrambler_value;
reg [31:0] crc;
reg crc_match;
begin
pause = receive_wait_fifo;
status = 0;
rcv_ignore = 0;
rcv_stop = 0;
crc = 32'h52325032;// crc seed
scrambler_value = {16'hf0f6, 16'h0000}; // scrambler seed
cnt = 0;
// current rprim = XRDY
rprim = "XRDY";
DEV_TITLE = "Detected incoming transmission";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
DEV_TITLE = "Waiting to empty input buffer";
DEV_DATA = pause;
// $display("[Device] LINK: Waiting %h cycles to empty input buffer", pause);
$display("[Device] LINK: %s, pause = %d @%t", DEV_TITLE, DEV_DATA, $time);
while (pause > 0) begin
// L_RcvWaitFifo
if (~phy_ready) begin
DEV_TITLE = "Unexpected line disconnect #1";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim != "XRDY") begin
// $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
@ (posedge clk)
rprim = linkGetPrim(0);
end
// L_RcvChkRdy
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #2";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim != "XRDY") begin
// $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
linkSendPrim("RRDY");
// $display("[Device] LINK: Starting the reception");
DEV_TITLE = "Starting the reception";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk)
rprim = linkGetPrim(0);
while (rprim != "SOF") begin
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #3";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "ALIGN") begin // ALIGNp in pairs can be inserted anywhere (TODO: check they are paired?)
// $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Got ALIGNp";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
@ (posedge clk)
rprim = linkGetPrim(0);
if (rprim != "ALIGN") begin // ALIGNp in pairs can be inserted anywhere (TODO: check they are paired?)
DEV_TITLE = "Was expecting another ALIGNp";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d got primitive = %s @%t", DEV_TITLE, DEV_DATA, rprim, $time);
#100;
$finish;
end else begin
DEV_TITLE = "Got second ALIGNp";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
end
end
if ((rprim != "XRDY") && (rprim != "ALIGN")) begin // ALIGNp in pairs can be inserted anywhere (TODO: check they are paired?)
DEV_TITLE = "Reception terminated by the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d, rprim = %s @%t", DEV_TITLE, DEV_DATA, rprim, $time);
// #100;
// $finish;
end
@ (posedge clk)
rprim = linkGetPrim(0);
end
// L_RcvData
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #4";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
// $display("[Device] LINK: Detected Start of FIS");
DEV_TITLE = "Detected Start of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("IP");
@ (posedge clk)
rprim = linkGetPrim(0);
pause = 0;
while (rcv_stop == 0) begin
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #5";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
// $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if (rprim == "SCRAP") begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
if (rprim == "EOF") begin
// $display("[Device] LINK: Detected End of FIS");
DEV_TITLE = "Detected End of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_stop = 1;
end
else
if (pause > 0) begin
pause = pause - 1;
linkSendPrim("HOLD");
if (rprim == "HOLDA") begin
// $display("[Device] LINK: The pause is acknowledged by the host, chilling out");
DEV_TITLE = "The pause is acknowledged by the host, chilling out";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_ignore = 1;
end
else begin
// $display("[Device] LINK: Asked for a pause");
DEV_TITLE = "Asked for a pause";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_ignore = 0;
end
end
else
if (rprim == "HOLD") begin
// $display("[Device] LINK: the host asked for a pause, acknowledging");
DEV_TITLE = "the host asked for a pause, acknowledging";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLDA");
rcv_ignore = 1;
end
else begin
linkSendPrim("IP");
rcv_ignore = 0;
end
if (rprim == "WTRM") begin
// $display("[Device] LINK: Host invalidated the reception, reception id = %d", id);
DEV_TITLE = "Host invalidated the reception";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
rcv_stop = 2;
end
if ((rcv_stop == 0) && (rcv_ignore == 0)) begin
if (rprim == "ALIGN") begin
DEV_TITLE = "ALIGN got";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d, cnt = %d @%t", DEV_TITLE, DEV_DATA, cnt, $time);
end else begin
if (cnt > 2048) begin
// $display("[Device] LINK: Wrong data dwords count received, reception id = %d", id);
DEV_TITLE = "Wrong data dwords count received";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if (cnt >= dmat_index) begin
linkSendPrim("DMAT");
end
scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
/// receive_data[cnt] = linkGetData(0) ^ scrambler_value;
descrambled_data = linkGetData(0) ^ scrambler_value;
receive_data[cnt] = descrambled_data;
DEV_TITLE = "Got data";
DEV_DATA = receive_data[cnt];
$display("[Device] LINK: %s = %h (#%d) @%t", DEV_TITLE, DEV_DATA, cnt, $time);
pause = pause + receive_data_pause[cnt];
crc_match = (crc == descrambled_data);
crc = calculateCRC(crc, descrambled_data); // running crc. shall be 0
// crc_match = (crc == receive_data[cnt]);
cnt = cnt + 1;
if (cnt <= 2048)
pause = pause + receive_data_pause[cnt];
`ifdef TERMINATE_DMA_H2D
linkSendPrim("DMAT");
`endif
end
end
@ (posedge clk)
rprim = linkGetPrim(0);
end
if (cnt < 2) begin
// $display("[Device] LINK: Incorrect number of received words");
DEV_TITLE = "Incorrect number of received words";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
// $display("[Device] LINK: Running CRC after all data was received = %h", crc);
DEV_TITLE = "Running CRC after all data was received";
DEV_DATA = crc;
$display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time);
received_size = cnt - 2; // data payload size in DWORDs
// if (crc != 32'h88c21025) begin // running disparity when data crc matches actual received crc
if (!crc_match) begin // running disparity when data crc matches actual received crc
// $display("[Device] LINK: Running CRC check failed");
DEV_TITLE = "Running CRC check failed";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rcv_stop = 2;
end
else begin
// $display("[Device] LINK: Running CRC OK");
DEV_TITLE = "Running CRC OK";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
end
if (rcv_stop == 1) begin // ordinary path
// L_RcvEOF
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #6";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
// $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
@ (posedge clk)
rprim = linkGetPrim(0);
// L_GoodCRC
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #7";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
// $display("[Device] LINK: Reception terminated by the host, reception id = %d", id);
DEV_TITLE = "Reception terminated by the host #6";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
if (tranCheckFIS(cnt - 1)) begin
rcv_stop = 2;
end
end
if (rcv_stop == 2) begin
// L_BadEnd
status = 1;
linkSendPrim("ERR");
// $display("[Device] LINK: Found an error");
DEV_TITLE = "Found an error";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
end
else begin
// L_GoodEnd
status = 0;
linkSendPrim("OK");
end
@ (posedge clk)
rprim = linkGetPrim(0);
while (rprim != "SYNC") begin
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #8";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, reception id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
@ (posedge clk)
rprim = linkGetPrim(0);
end
// L_IDLE
linkSendPrim("SYNC");
if (status == 1) begin
// $display("[Device] LINK: Reception done, errors detected, reception id = %d", id);
DEV_TITLE = "Reception done, errors detected";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
end
else
if (status == 0) begin
// $display("[Device] LINK: Reception done OK, reception id = %d", id);
DEV_TITLE = "Reception done OK";
DEV_DATA = id;
$display("[Device] LINK: %s, reception id = %d @%t", DEV_TITLE, DEV_DATA, $time);
end
end
endtask
reg [31:0] transmit_data [2047:0]; // @SuppressThisWarning VEditor - Assigned in testbench
reg [31:0] transmit_data_pause [2047:0];
reg [31:0] transmit_crc; // never assigned // @SuppressThisWarning VEditor - Assigned in testbench
task clear_transmit_pause; // @SuppressThisWarning VEditor - Used in testbench
input [31:0] pause_val;
integer i;
begin
for (i = 0; i < 2048; i = i + 1) begin
transmit_data_pause[i] = pause_val;
end
end
endtask
// Wait for device phy ready (full COMRESET/COMINIT sequence) and wait to send several SYNCp primitives so host knows it is done
task wait_ready; // @SuppressThisWarning VEditor - Used in testbench
input integer num_syncp;
begin
wait (phy_ready);
repeat(num_syncp + 1) @(posedge clk);
end
endtask
/*
task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input [2:0] dev_specific_status_bits;
input irq;
output integer status;
begin
transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (dev_specific_status_bits << 20) | 'h1000000;
transmit_data[1] = 1;
transmit_data[2] = 0;
transmit_data[3] = 1;
transmit_data[4] = 0;
linkTransmitFIS(id, 5, 0, status);
end
endtask
*/
task send_good_status; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input [2:0] dev_specific_status_bits;
input irq;
output integer status;
begin
send_D2HR(id,
irq,
{1'b0,dev_specific_status_bits,4'b0}, // status
1, // error
0, // device
1, // lba_low
0, // lba_high
1, // count
status); // output: result status
// transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (dev_specific_status_bits << 20) | 'h1000000;
// transmit_data[1] = 1;
// transmit_data[2] = 0;
// transmit_data[3] = 1;
// transmit_data[4] = 0;
// linkTransmitFIS(id, 5, 0, status);
end
endtask
task send_D2HR; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input irq;
input [7:0] sts;
input [7:0] error;
input [7:0] device;
input [23:0] lba_low;
input [23:0] lba_high;
input [15:0] count;
output integer status;
begin
transmit_data[0] = FIS_D2HR | (irq? 'h4000:0) | (sts << 16) | (error << 24);
transmit_data[1] = {device,lba_low};
transmit_data[2] = {8'b0, lba_high};
transmit_data[3] = {16'b0,count};
transmit_data[4] = 0;
linkTransmitFIS(id, 5, 0, status);
end
endtask
task send_pio_setup; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input d2h; // 'D' bit: 1 - Data will be D2H, 0 - H2D
input irq; // Set I bit
input [7:0] xmit_status;
input [7:0] xmit_error;
input [7:0] xmit_e_status;
input [15:0] xfer_count;
input [ 7:0] dev;
input [23:0] lba_low; // LBA_low dword
input [23:0] lba_high; // LBA high dword
input [15:0] count; //
output integer status;
begin
transmit_data[0] = FIS_PIOS |
(d2h? 'h2000:0) |
(irq? 'h4000:0) |
(xmit_status << 16) |
(xmit_error << 24);
transmit_data[1] = {dev, lba_low};
transmit_data[2] = {8'b0,lba_high};
transmit_data[3] = {xmit_e_status, 8'b0,count};
transmit_data[4] = {16'b0, xfer_count};
linkTransmitFIS(id, 5, 0, status);
end
endtask
task send_dma_activate; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
output integer status;
begin
transmit_data[0] = FIS_DMAA;
linkTransmitFIS(id, 1, 0, status);
end
endtask
task send_identify_data; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
output integer status;
reg [15:0] identify_data[0:255]; // SuppressThisWarning VEditor : assigned in $readmem() system task
integer i;
begin
clear_transmit_pause(0);
// $readmemh("input_data/identify.dat",identify_data);
$readmemh("input_data/test512.dat",identify_data);
transmit_data[0] = FIS_DATA;
for (i=0;i<128;i=i+1) begin
transmit_data[i+1] = {identify_data[2 * i+1], identify_data[2 * i]};
end
linkTransmitFIS(id, 129, 0, status);
end
endtask
task send_incrementing_data; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input integer len;
output integer status;
integer i;
begin
clear_transmit_pause(0);
transmit_data[0] = FIS_DATA;
for (i=0;i<len;i=i+1) begin
transmit_data[i+1] = i;
end
linkTransmitFIS(id, 129, 0, status);
end
endtask
task send_incrementing_data_pause; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input integer len;
output integer status;
integer i;
begin
clear_transmit_pause(0);
for (i=0;i<len;i=i+8) begin
transmit_data_pause[i+1] = i / 8; // each 8-th have increainsg pause 1,2,3...
end
transmit_data[0] = FIS_DATA;
for (i=0;i<len;i=i+1) begin
transmit_data[i+1] = i;
end
linkTransmitFIS(id, 129, 0, status);
end
endtask
/*
* Transmits data to a host. ~Link Transmit FSM
* Correct execution, as it shall be w/o errors from a device side. (except timeouts and data consistency, see below)
*
* Data to transmit is stored in transmit_data memory.
* Data is transmitted by dwords // TODO make support for uneven words (16bit each) count
*
* It is possible to send incorrect CRC by setting up an input transmit_custom_crc into 1 and desired crc value to transmit_crc
*
* Each data bundle has corresponding "pause" register, stored in a memory 'transmit_data_pause'
* It represents a time (in clock cycles), for which the device shall "wait" for a new portion of data
* Could be used to test timeout watchdogs of the host.
*
* Parameters:
* id - transmission id, shown in logs
* size - how much data to transmit in a FIS
* transmit_custom_crc - see upper
* status - returns 0 when the host acknowledges the transaction with OK code,
* 1 when with ERR code
* if it's 1, there are 3 options:
* a) Generated CRC is invalid
* b) Scrambler messed up
* c) There is an error in the host
*/
task linkTransmitFIS; // @SuppressThisWarning VEditor - Used in testbench
input integer id;
input integer size; // dwords count
input integer transmit_custom_crc;
output integer status;
integer xpause;
integer cnt;
integer crc;
reg [111:0] rprim;
reg [31:0] scrambler_value;
begin
crc = 32'h52325032;// crc seed
scrambler_value = {16'hf0f6, 16'h0000}; // scrambler seed
// tell everyone we need a bus to transmit data
transmit_lock = 1;
// DL_SendChkRdy
linkSendPrim("XRDY");
// $display("[Device] LINK: Started outcoming transmission");
DEV_TITLE = "Started outcoming transmission";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
rprim = linkGetPrim(0);
// $display("[Device] LINK: Waiting for acknowledgement");
DEV_TITLE = "Waiting for acknowledgement";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
while (rprim != "RRDY") begin
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #9";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
@ (posedge clk)
rprim = linkGetPrim(0);
end
// L_SendSOF
linkSendPrim("SOF");
// $display("[Device] LINK: Sending Start of FIS");
DEV_TITLE = "Sending Start of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk)
rprim = linkGetPrim(0);
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #10";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
// $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #1";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
// L_SendData + L_RcvrHold + L_SendHold
cnt = 0;
xpause = transmit_data_pause[0];
while (cnt < size) begin
if (xpause > 0) begin
DEV_TITLE = "Transmission is paused";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLD");
// xpause = xpause - 1;
end else begin
scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
linkSendData(transmit_data[cnt] ^ scrambler_value);
crc = calculateCRC(crc, transmit_data[cnt]);
DEV_TITLE = "Sent data";
DEV_DATA = transmit_data[cnt];
$display("[Device] LINK: %s = %h (#%d) @%t", DEV_TITLE, DEV_DATA, cnt, $time);
end
@ (posedge clk)
rprim = linkGetPrim(0);
if (rprim == "SYNC") begin
// $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #2";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end else if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #6";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end else if (rprim == "DMAT") begin
// $display("[Device] LINK: Transmission terminated by the host via DMAT, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host via DMAT";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end else if (xpause > 0) begin
// DEV_TITLE = "Transmission is paused";
// $display("[Device] LINK: %s @%t", DEV_TITLE, $time);
// linkSendPrim("HOLD");
xpause = xpause - 1;
end else if (rprim == "HOLD") begin
DEV_TITLE = "The host asked for a pause, acknowledging transmission paused";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
linkSendPrim("HOLDA");
end else begin
cnt = cnt + 1;
if (cnt < size)
xpause = transmit_data_pause[cnt];
end
end
// L_SendCRC
// scrambler_value = scrambleFunc(scrambler_value[31:16]);
scrambler_value = scrambleFunc({16'b0,scrambler_value[31:16]});
if (transmit_custom_crc != 0) begin
crc = transmit_crc;
end
linkSendData(crc ^ scrambler_value);
// $display("[Device] LINK: Sent crc = %h", crc);
DEV_TITLE = "Sent crc";
DEV_DATA = crc;
$display("[Device] LINK: %s = %h @%t", DEV_TITLE, DEV_DATA, $time);
@ (posedge clk)
rprim = linkGetPrim(0);
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #11";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
// $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #3";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #7";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
// L_SendEOF
linkSendPrim("EOF");
// $display("[Device] LINK: Sent End of FIS");
DEV_TITLE = "Sent End of FIS";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk)
rprim = linkGetPrim(0);
if (~phy_ready) begin
// $display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #12";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
// $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #4";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #8";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
// L_Wait
linkSendPrim("WTRM");
// $display("[Device] LINK: Waiting for a response from the host");
DEV_TITLE = "Waiting for a response from the host";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
@ (posedge clk)
rprim = linkGetPrim(0);
status = 0;
while ((rprim != "OK") && (status == 0)) begin
if (~phy_ready) begin
//$display("[Device] LINK: Unexpected line disconnect");
DEV_TITLE = "Unexpected line disconnect #13";
$display("[Device] LINK: %s @%t", DEV_TITLE, $time);
#100;
$finish;
end
if (rprim == "SYNC") begin
// $display("[Device] LINK: Transmission terminated by the host, transmission id = %d", id);
DEV_TITLE = "Transmission terminated by the host #5";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
#100;
$finish;
end
if ((rprim == "SCRAP") || (rprim == "DATA")) begin
// $display("[Device] LINK: Bad primitives from the host, is data = %h, data = %h, transmission id = %d", linkIsData(0), linkGetData(0), id);
DEV_TITLE = "Bad primitives from the host #9";
DEV_DATA = id;
$display("[Device] LINK: %s, is data = %h, data = %h, reception id = %d @%t", DEV_TITLE, linkIsData(0), linkGetData(0), DEV_DATA, $time);
#100;
$finish;
end
if (rprim == "ERR") begin
// $display("[Device] LINK: Host invalidated the transmission, transmission id = %d", id);
DEV_TITLE = "Host invalidated the transmission";
DEV_DATA = id;
$display("[Device] LINK: %s, transmission id = %d @%t", DEV_TITLE, DEV_DATA, $time);
status = 1;
end
@ (posedge clk)
rprim = linkGetPrim(0);
end
if (status == 0)
// $display("[Device] LINK: Transmission done OK, id = %d", id);
DEV_TITLE = "Transmission done OK";
DEV_DATA = id;
$display("[Device] LINK: %s, id = %d @%t", DEV_TITLE, DEV_DATA, $time);
if (status == 1)
// $display("[Device] LINK: Transmission done with ERRORs, id = %d", id);
DEV_TITLE = "Transmission done with ERRORS";
DEV_DATA = id;
$display("[Device] LINK: %s, id = %d @%t", DEV_TITLE, DEV_DATA, $time);
// L_IDLE
linkSendPrim("SYNC");
@ (posedge clk);
end
endtask
// checks, if it is data coming from the host
function [0:0] linkIsData;
input dummy; // @SuppressThisWarning VEditor - unused (is it for some simulator?)
begin
if (|phy2dev_charisk)
linkIsData = 1;
else
linkIsData = 0;
end
endfunction
// obvious
function [31:0] linkGetData;
// TODO non-even word count
input dummy; // @SuppressThisWarning VEditor - unused (is it for some simulator?)
begin
linkGetData = phy2dev_data;
end
endfunction
/*
* Returns current primitive at the outputs of phy level
* Return value is a string containing its name!
*/
function [111:0] linkGetPrim;
input integer dummy; // @SuppressThisWarning VEditor - unused (is it for some simulator?)
reg [111:0] type;
begin
if (~|phy2dev_charisk) begin
type = "DATA";
end
else
if (phy2dev_charisk == 4'h1) begin
case (phy2dev_data)
PRIM_SYNCP:
type = "SYNC";
PRIM_ALIGNP:
type = "ALIGN";
PRIM_XRDYP:
type = "XRDY";
PRIM_SOFP:
type = "SOF";
PRIM_HOLDAP:
type = "HOLDA";
PRIM_HOLDP:
type = "HOLD";
PRIM_EOFP:
type = "EOF";
PRIM_WTRMP:
type = "WTRM";
PRIM_RRDYP:
type = "RRDY";
PRIM_IPP:
type = "IP";
PRIM_DMATP:
type = "DMAT";
PRIM_OKP:
type = "OK";
PRIM_ERRP:
type = "ERR";
default:
type = "SCRAP";
endcase
end
else begin
type = "SCRAP";
end
linkGetPrim = type;
end
endfunction
/*
* Sets some data to phy inputs
* input is a data dword
*/
task linkSendData;
input [31:0] data;
begin
send_align_pair_if_needed;
dev2phy_data <= data;
dev2phy_isk <= 4'h0;
end
endtask
/*
* Set a desired primitive to phy inputs
* input is a string containing its name!
*/
task linkSendPrim;
input [111:0] type;
begin
// send_align_pair_if_needed;
case (type)
"SYNC":
begin
send_align_pair_if_needed;
dev2phy_data <= PRIM_SYNCP;
dev2phy_isk <= 4'h1;
end
"ALIGN":
begin
dev2phy_data <= PRIM_ALIGNP;
dev2phy_isk <= 4'h1;
end
"XRDY":
begin
dev2phy_data <= PRIM_XRDYP;
dev2phy_isk <= 4'h1;
end
"SOF":
begin
dev2phy_data <= PRIM_SOFP;
dev2phy_isk <= 4'h1;
end
"HOLDA":
begin
dev2phy_data <= PRIM_HOLDAP;
dev2phy_isk <= 4'h1;
end
"HOLD":
begin
dev2phy_data <= PRIM_HOLDP;
dev2phy_isk <= 4'h1;
end
"EOF":
begin
dev2phy_data <= PRIM_EOFP;
dev2phy_isk <= 4'h1;
end
"WTRM":
begin
dev2phy_data <= PRIM_WTRMP;
dev2phy_isk <= 4'h1;
end
"RRDY":
begin
dev2phy_data <= PRIM_RRDYP;
dev2phy_isk <= 4'h1;
end
"IP":
begin
dev2phy_data <= PRIM_IPP;
dev2phy_isk <= 4'h1;
end
"DMAT":
begin
dev2phy_data <= PRIM_DMATP;
dev2phy_isk <= 4'h1;
end
"OK":
begin
dev2phy_data <= PRIM_OKP;
dev2phy_isk <= 4'h1;
end
"ERR":
begin
dev2phy_data <= PRIM_ERRP;
dev2phy_isk <= 4'h1;
end
default:
begin
dev2phy_data <= PRIM_SYNCP;
dev2phy_isk <= 4'h1;
end
endcase
end
endtask
endmodule
|
//#############################################################################
//# Function: Low power data gate #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
//
module oh_datagate #(parameter DW = 32, // width of data inputs
parameter N = 3 // min quiet time before shutdown
)
(
input clk, // clock
input en, // data valid
input [DW-1:0] din, // data input
output [DW-1:0] dout // data output
);
reg [N-1:0] enable_pipe;
wire enable;
always @ (posedge clk)
enable_pipe[N-1:0] <= {enable_pipe[N-2:0],en};
//Mask to 0 if no valid for last N cycles
assign enable = en | (|enable_pipe[N-1:0]);
assign dout[DW-1:0] = {(DW){enable}} & din[DW-1:0];
endmodule // oh_datagate
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
module SLEEP_CONTROLv4
(
output reg MBC_ISOLATE,
output MBC_ISOLATE_B,
output reg MBC_RESET,
output MBC_RESET_B,
output MBC_SLEEP,
output MBC_SLEEP_B,
output SYSTEM_ACTIVE,
output WAKEUP_REQ_ORED,
input CLK,
input MBUS_DIN,
input RESETn,
input SLEEP_REQ,
input WAKEUP_REQ0,
input WAKEUP_REQ1,
input WAKEUP_REQ2
);
reg set_tran_to_wake;
reg rst_tran_to_wake; // act as tran to "sleep"
assign MBC_ISOLATE_B = ~MBC_ISOLATE;
assign MBC_RESET_B = ~MBC_RESET;
reg MBC_SLEEP_int;
assign MBC_SLEEP_B = ~MBC_SLEEP;
reg tran_to_wake;
assign SYSTEM_ACTIVE = MBC_SLEEP_B | MBC_ISOLATE_B;
assign WAKEUP_REQ_ORED = WAKEUP_REQ0 | WAKEUP_REQ1 | WAKEUP_REQ2;
// set_tran_to_wake
always @ *
begin
if (RESETn & ( WAKEUP_REQ_ORED | ( MBC_SLEEP_int & ~MBUS_DIN ))) // Wake up if there is internal req or DIN pulled down
set_tran_to_wake = 1'b1;
else
set_tran_to_wake = 1'b0;
end
// rst_tran_to_wake
always @ *
begin
if ((~RESETn) | ( WAKEUP_REQ_ORED | (MBC_SLEEP_int & ~MBUS_DIN) | ~SLEEP_REQ ))
rst_tran_to_wake <= 1'b1; // reverse the edge, @ Ye-sheng
else
rst_tran_to_wake <= 1'b0;
end
/*
// tran_to_wake
always @ ( posedge rst_tran_to_wake or posedge set_tran_to_wake )
begin
if( rst_tran_to_wake )
tran_to_wake <= 1'b0;
else if ( set_tran_to_wake )
tran_to_wake <= 1'b1;
else
tran_to_wake <= tran_to_wake;
end
*/
wire tran_to_wake_r = RESETn & rst_tran_to_wake;
always @ (negedge tran_to_wake_r or posedge set_tran_to_wake)
begin
if (~tran_to_wake_r)
tran_to_wake <= 1'b0;
else
tran_to_wake <= 1'b1;
end
// MBC_ISOLATE
always @ ( negedge RESETn or posedge CLK )
begin
if( ~RESETn )
MBC_ISOLATE <= 1'b1;
else
MBC_ISOLATE <= (MBC_SLEEP_int | (~tran_to_wake));
end
// MBC_SLEEP
always @ ( negedge RESETn or posedge CLK )
begin
if( ~RESETn )
MBC_SLEEP_int <= 1'b1;
else
MBC_SLEEP_int <= (MBC_ISOLATE & (~tran_to_wake));
end
assign MBC_SLEEP = MBC_SLEEP_int & ~ (WAKEUP_REQ_ORED | (MBC_SLEEP_int & ~MBUS_DIN) );
// MBC_RESET
always @ ( negedge RESETn or posedge CLK )
begin
if( ~RESETn )
MBC_RESET <= 1'b1;
else
MBC_RESET <= MBC_ISOLATE;
end
endmodule // SLEEP_CONTROLv4
|
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