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// Library - static, Cell - thxor0n, View - schematic
// LAST TIME SAVED: May 23 18:28:33 2014
// NETLIST TIME: May 23 18:28:54 2014
`timescale 1ns / 1ns
module thxor0n ( y, a, b, c, d, rsb );
output y;
input a, b, c, d, rsb;
specify
specparam CDS_LIBNAME = "static";
specparam CDS_CELLNAME = "thxor0n";
specparam CDS_VIEWNAME = "schematic";
endspecify
nfet_b N13 ( .d(net037), .g(c), .s(net44), .b(cds_globals.gnd_));
nfet_b N14 ( .d(net037), .g(b), .s(net44), .b(cds_globals.gnd_));
nfet_b N6 ( .d(net45), .g(d), .s(net030), .b(cds_globals.gnd_));
nfet_b N5 ( .d(net037), .g(a), .s(net44), .b(cds_globals.gnd_));
nfet_b N4 ( .d(net037), .g(c), .s(net45), .b(cds_globals.gnd_));
nfet_b N15 ( .d(net030), .g(rsb), .s(cds_globals.gnd_),
.b(cds_globals.gnd_));
nfet_b N10 ( .d(net037), .g(d), .s(net44), .b(cds_globals.gnd_));
nfet_b N3 ( .d(net44), .g(y), .s(net030), .b(cds_globals.gnd_));
nfet_b N2 ( .d(net040), .g(b), .s(net030), .b(cds_globals.gnd_));
nfet_b N1 ( .d(net037), .g(a), .s(net040), .b(cds_globals.gnd_));
pfet_b P12 ( .b(cds_globals.vdd_), .g(rsb), .s(cds_globals.vdd_),
.d(net037));
pfet_b P11 ( .b(cds_globals.vdd_), .g(c), .s(net036), .d(net045));
pfet_b P7 ( .b(cds_globals.vdd_), .g(d), .s(net036), .d(net045));
pfet_b P10 ( .b(cds_globals.vdd_), .g(y), .s(net045), .d(net037));
pfet_b P5 ( .b(cds_globals.vdd_), .g(b), .s(cds_globals.vdd_),
.d(net036));
pfet_b P4 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net036));
pfet_b P3 ( .b(cds_globals.vdd_), .g(c), .s(net47), .d(net037));
pfet_b P2 ( .b(cds_globals.vdd_), .g(d), .s(net34), .d(net47));
pfet_b P1 ( .b(cds_globals.vdd_), .g(b), .s(net49), .d(net34));
pfet_b P0 ( .b(cds_globals.vdd_), .g(a), .s(cds_globals.vdd_),
.d(net49));
inv I2 ( y, net037);
endmodule
|
`default_nettype none
module pulse_control(
input clk,
input RS232_Rx,
output RS232_Tx,
output [31:0] per,
output [15:0] p1wid,
output [15:0] del,
output [15:0] p2wid,
output [7:0] nut_w,
output [15:0] nut_d,
// output [6:0] pr_att,
// output [6:0] po_att,
output [7:0] cp,
output [7:0] p_bl,
output [15:0] p_bl_off,
output bl,
output rxd
);
// Control the pulses
// Running at a 201-MHz clock, our time step is ~5 (4.975) ns.
// All the times are thus divided by 4.975 ns to get cycles.
// 32-bit allows times up to 21 seconds
parameter stperiod = 15; // 1 ms period
parameter stp1width = 30; // 150 ns
parameter stp2width = 30;
parameter stdelay = 200; // 1 us delay
parameter stblock = 100; // 500 ns block open
parameter stcpmg = 3;
parameter stnutdel = 100;
parameter stnutwid = 100;
reg [31:0] period = stperiod << 16;
reg [15:0] p1width = stp1width;
reg [15:0] delay = stdelay;
reg [15:0] p2width = stp2width;
reg [7:0] pulse_block = 8'd50;
reg [15:0] pulse_block_off = stblock;
reg [7:0] cpmg = stcpmg;
reg block = 1;
reg rx_done = 0;
reg [15:0] nut_del = stnutdel;
reg [7:0] nut_wid = stnutdel;
// Control the attenuators
// parameter att_pre_val = 7'd1;
// parameter att_post_val = 7'd0;
// reg [6:0] pre_att = att_pre_val;
// reg [6:0] post_att = att_post_val;
assign per = period;
assign p1wid = p1width;
assign p2wid = p2width;
assign del = delay;
// assign pr_att = pre_att;
// assign po_att = post_att;
assign cp = cpmg;
assign p_bl = pulse_block;
assign p_bl_off = pulse_block_off;
assign bl = block;
assign rxd = rx_done;
assign nut_d = nut_del;
assign nut_w = nut_wid;
// Setup necessary for UART
wire reset = 0;
reg transmit;
reg [7:0] tx_byte;
wire received;
wire [7:0] rx_byte;
wire is_receiving;
wire is_transmitting;
wire recv_error;
// UART module, from https://github.com/cyrozap/osdvu
uart uart0( //testing with 115200 baud and 50 MHz clock from sim_tb
.clk(clk), // The master clock for this module
.rst(reset), // Synchronous reset
.rx(RS232_Rx), // Incoming serial line
.tx(RS232_Tx), // Outgoing serial line
.transmit(transmit), // Signal to transmit
.tx_byte(tx_byte), // Byte to transmit
.received(received), // Indicated that a byte has been received
.rx_byte(rx_byte), // Byte received
.is_receiving(is_receiving), // Low when receive line is idle
.is_transmitting(is_transmitting),// Low when transmit line is idle
.recv_error(recv_error) // Indicates error in receiving packet.
);
// input and output to be communicated
reg [31:0] vinput; // input and output are reserved keywords
reg [7:0] vcontrol; // Control byte, the MSB (most significant byte) of the transmission
reg [7:0] voutput;
reg [7:0] vcheck; // Checksum byte; the input bytes are summed and sent back as output
// We need to receive multiple bytes sequentially, so this sets up both
// reading and writing. Adapted from the uart-adder from
// https://github.com/cyrozap/iCEstick-UART-Demo/pull/3/files
parameter read_A = 1'd0;
parameter read_wait = 1'd1;
parameter write_A = 1'd0;
parameter write_done = 1'd1;
reg writestate = write_A;
reg [5:0] writecount = 0;
reg [1:0] readstate = read_A;
reg [5:0] readcount = 0;
parameter STATE_RECEIVING = 2'd0;
parameter STATE_CALCULATING = 2'd1;
parameter STATE_SENDING = 2'd2;
// These set the behavior based on the control byte
parameter CONT_SET_DELAY = 8'd0;
parameter CONT_SET_PERIOD = 8'd1;
parameter CONT_SET_PULSE1 = 8'd2;
parameter CONT_SET_PULSE2 = 8'd3;
parameter CONT_TOGGLE_PULSE1 = 8'd4;
parameter CONT_SET_CPMG = 8'd5;
parameter CONT_SET_ATT = 8'd6;
parameter CONT_SET_NUTW = 8'd7;
parameter CONT_SET_NUTD = 8'd8;
reg [2:0] state = STATE_RECEIVING;
// The communication runs at the 12 MHz clock rather than the 200 MHz clock.
always @(posedge clk) begin
case (state)
STATE_RECEIVING: begin
transmit <= 0;
case (readstate)
read_A: begin
if(received) begin
if(readcount == 6'd32) begin // Last byte in the transmission
vcontrol <= rx_byte;
state<=STATE_CALCULATING;
readcount <= 0;
readstate <= read_A;
end
else begin // Read the first bytes into vinput
vinput[readcount +: 8]=rx_byte;
readcount <= readcount + 8;
readstate <= read_wait;
end
end
end // case: read_A
read_wait: begin // Wait for the next byte to arrive
if(~received) begin
readstate <= read_A;
end
end
endcase // case (readstate)
end // case: STATE_RECEIVING
// Based on the control byte, assign a new value to the desired pulse parameter
STATE_CALCULATING: begin
writestate <= write_A;
voutput = vinput[31:24] + vinput[23:16] + vinput[15:8] + vinput[7:0];
case (vcontrol)
CONT_SET_DELAY: begin
delay <= vinput[15:0];
end
CONT_SET_PERIOD: begin
period <= vinput;
end
CONT_SET_PULSE1: begin
p1width <= vinput[15:0];
end
CONT_SET_PULSE2: begin
p2width <= vinput[15:0];
end
CONT_TOGGLE_PULSE1: begin
block <= vinput[1];
pulse_block <= vinput[15:8];
// pulse_block_off <= vinput[31:16];
end
CONT_SET_CPMG: begin
cpmg <= vinput[7:0];
end
CONT_SET_NUTD: begin
nut_del <= vinput[15:0];
end
CONT_SET_NUTW: begin
nut_wid <= vinput[7:0];
end
// CONT_SET_ATT: begin
// pre_att <= vinput[7:0];
// post_att <= vinput[15:8];
// end
endcase // case (vcontrol)
state <= STATE_SENDING;
end
STATE_SENDING: begin
case (writestate)
write_A: begin
rx_done = 1;
if (~ is_transmitting) begin
transmit <= 1;
writestate <= write_done;
tx_byte <= voutput;
state <= STATE_SENDING;
end
end
write_done: begin
rx_done = 0;
if (~ is_transmitting) begin
writestate <= write_A;
state <= STATE_RECEIVING;
transmit <= 0;
end
end
endcase
end
default: begin
// should not be reached
state <= STATE_RECEIVING;
readcount <= read_A;
end
endcase // case (state)
end // always @ (posedge iCE_CLK)
endmodule // pulse_control
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:26:00 05/02/2015
// Design Name: pc_param_behav
// Module Name: D:/Projects/Xilinx/ProgramCounter/test_pc_param_behav.v
// Project Name: ProgramCounter
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: pc_param_behav
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_pc_param_behav;
// Inputs
reg [7:0] disp;
reg [3:0] ra;
reg [3:0] rw;
reg jmp;
reg branch;
reg wren;
reg clk;
reg rst;
reg clken;
// Outputs
wire [15:0] PC_cont;
wire [15:0] PC_cont2;
// Instantiate the Unit Under Test (UUT)
pc_param_behav #(.BITSIZE(16) , .ADDSIZE(4)) uut (
.PC_cont(PC_cont),
.disp(disp),
.ra(ra),
.rw(rw),
.jmp(jmp),
.branch(branch),
.wren(wren),
.clk(clk),
.rst(rst),
.clken(clken)
);
always begin
clk = 1;
#5;
clk = 0;
$display($time,,,"Current PC = %d", PC_cont);
#5;
end
initial begin
// Initialize Inputs
$display($time,,,"Simulation is started.");
disp = 0;
ra = 0;
rw = 0;
jmp = 0;
branch = 0;
wren = 0;
rst = 0;
clken = 1;
#15 rst = 1;
$display($time,,,"Reset is Asserted");
#10;
// Wait 100 ns for global reset to finish
#100;
// Test Positive Branch
#20 branch = 1; disp = 8'b0000_1111;
$display($time,,,"Testing branching with positive value (15).");
#10 branch = 0;
// Test Negative Branch
#120 branch = 1; disp = 8'b1111_0011;
$display($time,,,"Testing branching with negative value.(-13)");
#10 branch = 0;
// Test Jump
// First Fill the Register with the Jump Location which is the current PC value.
#20 wren = 1; rw = 4'b0110;
$display($time,,,"Filling Register 0110 with value %d + 1.", PC_cont);
#10 wren = 0;
// Wait some time. Don't need to but to see the effect, we wait.
#40 jmp = 1; ra = 4'b0110;
$display($time,,,"Testing jumping to value at Register 0110.");
#10 jmp = 0;
// Test Jump and Link. Read from 0110, write to 0100
#80 jmp = 1; ra = 4'b0110; rw = 4'b0100; wren = 1;
$display($time,,,"Filling Register 0100 with value %d + 1.", PC_cont);
$display($time,,,"Testing Jumping to value at Register 0110 at the same time. (JAL OP)");
#10 jmp = 0; wren = 0;
// Check that the link is working by jumping back to link address.
#40 jmp = 1; ra = 4'b0100;
$display($time,,,"Testing jumping to value at Register 0100 which should be previous PC value + 1.");
#10 jmp = 0;
#100;
$display($time,,,"End of Simulation.");
end
endmodule
|
`define WIDTH_P 4
`define ELS_P 3
`include "bsg_defines.v"
/********************************** TEST RATIONALE *************************
1. STATE SPACE
Since the values of data inputs have little influence on the functioning
of DUT, they are kept constant and not varied. The select input should be
a one hot code and is varied from 00..1 to 10..0.
2. PARAMETERIZATION
The parameter WIDTH_P is the width of the data input and ELS_P is the
number of inputs to the mux which in this case is equal to the width of the
select input. Since the DUT deals with the data inputs of different widths
similarly, an arbitrary set of tests that include edge cases would suffice.
So a minimum set of tests might be WIDTH_P = 1,2,3,4 and ELS_P = 2,3,4.
***************************************************************************/
module test_bsg
#(
parameter cycle_time_p = 20,
parameter width_p = `WIDTH_P, // width of test input
parameter els_p = `ELS_P,
parameter reset_cycles_lo_p=0,
parameter reset_cycles_hi_p=5
);
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
initial
begin
$display("\n\n\n");
$display("===========================================================");
$display("testing with ...");
$display("WIDTH_P: %d", width_p);
$display("ELS_P : %d\n", els_p);
end
logic [els_p-1:0][width_p-1:0] test_input_data;
logic [els_p-1:0] test_input_sel;
logic [width_p-1:0] test_output;
logic [`BSG_SAFE_CLOG2(els_p)-1:0] addr;
genvar i;
for(i=0; i<=els_p; ++i)
assign test_input_data[i] = width_p'(i);
always_ff @(posedge clk)
begin
if(reset)
test_input_sel <= els_p'(1);
else
begin
test_input_sel <= (test_input_sel << 1);
if(~|test_input_sel)
begin
$display("=============================================================\n");
$finish;
end
assert (test_output==width_p'(addr))
else $error("mismatch on input %x", test_input_sel);
end
/*$display("test_input_sel: %b, test_output: %b\n"
, test_input_sel, test_output);*/
end
bsg_encode_one_hot #( .width_p(els_p)
) encode_one_hot
( .i (test_input_sel)
, .addr_o(addr)
, .v_o ()
);
bsg_mux_one_hot #( .width_p (width_p)
, .els_p (els_p)
, .harden_p()
) DUT
( .data_i (test_input_data)
, .sel_one_hot_i(test_input_sel)
, .data_o (test_output)
);
/*bsg_nonsynth_ascii_writer #( .width_p (width_p)
, .values_p (2)
, .filename_p ("output.log")
, .fopen_param_p("a+")
, .format_p ("w")
) ascii_writer
( .clk (clk)
, .reset_i(reset)
, .valid_i(1'b1)
, .data_i ({test_output,
width_p'(addr)}
)
);*/
endmodule |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="sparse_mm,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7vx690tffg1761-2,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.280000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=12,HLS_SYN_FF=462,HLS_SYN_LUT=355}" *)
module sparse_mm (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
a_address0,
a_ce0,
a_q0,
a_y,
a_x,
b_address0,
b_ce0,
b_q0,
b_y,
b_x,
c_address0,
c_ce0,
c_we0,
c_d0
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 18'b1;
parameter ap_ST_st2_fsm_1 = 18'b10;
parameter ap_ST_st3_fsm_2 = 18'b100;
parameter ap_ST_st4_fsm_3 = 18'b1000;
parameter ap_ST_st5_fsm_4 = 18'b10000;
parameter ap_ST_st6_fsm_5 = 18'b100000;
parameter ap_ST_st7_fsm_6 = 18'b1000000;
parameter ap_ST_st8_fsm_7 = 18'b10000000;
parameter ap_ST_st9_fsm_8 = 18'b100000000;
parameter ap_ST_st10_fsm_9 = 18'b1000000000;
parameter ap_ST_st11_fsm_10 = 18'b10000000000;
parameter ap_ST_st12_fsm_11 = 18'b100000000000;
parameter ap_ST_st13_fsm_12 = 18'b1000000000000;
parameter ap_ST_st14_fsm_13 = 18'b10000000000000;
parameter ap_ST_st15_fsm_14 = 18'b100000000000000;
parameter ap_ST_st16_fsm_15 = 18'b1000000000000000;
parameter ap_ST_st17_fsm_16 = 18'b10000000000000000;
parameter ap_ST_st18_fsm_17 = 18'b100000000000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_9 = 32'b1001;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv32_D = 32'b1101;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv31_0 = 31'b0000000000000000000000000000000;
parameter ap_const_lv32_11 = 32'b10001;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv31_1 = 31'b1;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_20 = 32'b100000;
parameter ap_const_lv32_3F = 32'b111111;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
output [21:0] a_address0;
output a_ce0;
input [63:0] a_q0;
input [31:0] a_y;
input [31:0] a_x;
output [10:0] b_address0;
output b_ce0;
input [31:0] b_q0;
input [31:0] b_y;
input [31:0] b_x;
output [10:0] c_address0;
output c_ce0;
output c_we0;
output [31:0] c_d0;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg a_ce0;
reg b_ce0;
reg c_ce0;
reg c_we0;
(* fsm_encoding = "none" *) reg [17:0] ap_CS_fsm = 18'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_34;
wire [31:0] ibx_cast_fu_145_p1;
reg [31:0] ibx_cast_reg_258;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_78;
wire [30:0] ibx_1_fu_154_p2;
reg [30:0] ibx_1_reg_267;
wire [31:0] a_i_1_fu_165_p2;
reg [31:0] a_i_1_reg_275;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_89;
wire [0:0] tmp_1_fu_160_p2;
wire [31:0] column_cast_fu_190_p1;
reg [31:0] column_cast_reg_289;
reg ap_sig_cseq_ST_st6_fsm_5;
reg ap_sig_bdd_105;
reg signed [31:0] value_reg_294;
wire [31:0] iay_1_fu_204_p2;
reg [31:0] iay_1_reg_299;
wire [0:0] tmp_6_fu_176_p1;
wire [31:0] grp_fu_215_p2;
reg [31:0] tmp_8_reg_304;
reg ap_sig_cseq_ST_st9_fsm_8;
reg ap_sig_bdd_122;
reg ap_sig_cseq_ST_st10_fsm_9;
reg ap_sig_bdd_131;
reg signed [31:0] b_load_reg_314;
reg ap_sig_cseq_ST_st11_fsm_10;
reg ap_sig_bdd_139;
wire [31:0] grp_fu_228_p2;
reg [31:0] tmp_7_reg_319;
reg ap_sig_cseq_ST_st14_fsm_13;
reg ap_sig_bdd_148;
wire [31:0] sum_1_fu_232_p2;
reg ap_sig_cseq_ST_st15_fsm_14;
reg ap_sig_bdd_157;
wire [31:0] grp_fu_210_p2;
reg [31:0] tmp_3_reg_329;
reg ap_sig_cseq_ST_st17_fsm_16;
reg ap_sig_bdd_166;
reg [30:0] ibx_reg_90;
reg [31:0] a_i_reg_101;
wire [0:0] tmp_fu_149_p2;
reg ap_sig_cseq_ST_st18_fsm_17;
reg ap_sig_bdd_183;
reg signed [31:0] iay_reg_114;
reg [31:0] sum_reg_129;
wire signed [63:0] tmp_2_fu_171_p1;
wire [63:0] tmp_s_fu_223_p1;
wire signed [63:0] tmp_4_fu_241_p1;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_200;
reg ap_sig_cseq_ST_st5_fsm_4;
reg ap_sig_bdd_208;
wire signed [31:0] tmp_fu_149_p1;
wire [30:0] column_fu_180_p4;
wire [30:0] grp_fu_215_p0;
reg ap_sig_cseq_ST_st7_fsm_6;
reg ap_sig_bdd_247;
wire [31:0] tmp_9_fu_219_p2;
wire [31:0] tmp_5_fu_237_p2;
wire grp_fu_210_ce;
wire grp_fu_215_ce;
wire grp_fu_228_ce;
reg [17:0] ap_NS_fsm;
sparse_mm_mul_32s_32s_32_3 #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
sparse_mm_mul_32s_32s_32_3_U1(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( iay_reg_114 ),
.din1( b_x ),
.ce( grp_fu_210_ce ),
.dout( grp_fu_210_p2 )
);
sparse_mm_mul_31ns_32s_32_3 #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 31 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
sparse_mm_mul_31ns_32s_32_3_U2(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( grp_fu_215_p0 ),
.din1( b_x ),
.ce( grp_fu_215_ce ),
.dout( grp_fu_215_p2 )
);
sparse_mm_mul_32s_32s_32_3 #(
.ID( 1 ),
.NUM_STAGE( 3 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
sparse_mm_mul_32s_32s_32_3_U3(
.clk( ap_clk ),
.reset( ap_rst ),
.din0( b_load_reg_314 ),
.din1( value_reg_294 ),
.ce( grp_fu_228_ce ),
.dout( grp_fu_228_p2 )
);
always @ (posedge ap_clk) begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14) | (ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17))) begin
a_i_reg_101 <= a_i_1_reg_275;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == tmp_fu_149_p2))) begin
a_i_reg_101 <= ap_const_lv32_0;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) begin
iay_reg_114 <= iay_reg_114;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) begin
iay_reg_114 <= iay_1_reg_299;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == tmp_fu_149_p2))) begin
iay_reg_114 <= ap_const_lv32_0;
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (tmp_1_fu_160_p2 == ap_const_lv1_0))) begin
ibx_reg_90 <= ibx_1_reg_267;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
ibx_reg_90 <= ap_const_lv31_0;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) begin
sum_reg_129 <= sum_1_fu_232_p2;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_lv1_0 == tmp_fu_149_p2)) | (ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17))) begin
sum_reg_129 <= ap_const_lv32_0;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
a_i_1_reg_275 <= a_i_1_fu_165_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) begin
b_load_reg_314 <= b_q0;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) begin
column_cast_reg_289[30 : 0] <= column_cast_fu_190_p1[30 : 0];
value_reg_294 <= {{a_q0[ap_const_lv32_3F : ap_const_lv32_20]}};
end
end
always @ (posedge ap_clk) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) & ~(ap_const_lv1_0 == tmp_6_fu_176_p1))) begin
iay_1_reg_299 <= iay_1_fu_204_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
ibx_1_reg_267 <= ibx_1_fu_154_p2;
ibx_cast_reg_258[30 : 0] <= ibx_cast_fu_145_p1[30 : 0];
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16)) begin
tmp_3_reg_329 <= grp_fu_210_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) begin
tmp_7_reg_319 <= grp_fu_228_p2;
end
end
always @ (posedge ap_clk) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) begin
tmp_8_reg_304 <= grp_fu_215_p2;
end
end
always @ (ap_sig_cseq_ST_st3_fsm_2 or ap_sig_cseq_ST_st6_fsm_5 or ap_sig_cseq_ST_st4_fsm_3 or ap_sig_cseq_ST_st5_fsm_4) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) | (ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5) | (ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3) | (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_fu_149_p2) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == tmp_fu_149_p2))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0) begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st2_fsm_1 or tmp_fu_149_p2) begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == tmp_fu_149_p2))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_131) begin
if (ap_sig_bdd_131) begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_139) begin
if (ap_sig_bdd_139) begin
ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_148) begin
if (ap_sig_bdd_148) begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_157) begin
if (ap_sig_bdd_157) begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_166) begin
if (ap_sig_bdd_166) begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_183) begin
if (ap_sig_bdd_183) begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_34) begin
if (ap_sig_bdd_34) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_78) begin
if (ap_sig_bdd_78) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_89) begin
if (ap_sig_bdd_89) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_200) begin
if (ap_sig_bdd_200) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_208) begin
if (ap_sig_bdd_208) begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_105) begin
if (ap_sig_bdd_105) begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_247) begin
if (ap_sig_bdd_247) begin
ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_0;
end
end
always @ (ap_sig_bdd_122) begin
if (ap_sig_bdd_122) begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st10_fsm_9) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st18_fsm_17) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) begin
c_ce0 = ap_const_logic_1;
end else begin
c_ce0 = ap_const_logic_0;
end
end
always @ (ap_sig_cseq_ST_st18_fsm_17) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) begin
c_we0 = ap_const_logic_1;
end else begin
c_we0 = ap_const_logic_0;
end
end
always @ (ap_start or ap_CS_fsm or tmp_1_fu_160_p2 or tmp_6_fu_176_p1 or tmp_fu_149_p2) begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if ((ap_const_lv1_0 == tmp_fu_149_p2)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st3_fsm_2 :
begin
if (~(tmp_1_fu_160_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st4_fsm_3 :
begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
ap_ST_st5_fsm_4 :
begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end
ap_ST_st6_fsm_5 :
begin
if (~(ap_const_lv1_0 == tmp_6_fu_176_p1)) begin
ap_NS_fsm = ap_ST_st16_fsm_15;
end else begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end
end
ap_ST_st7_fsm_6 :
begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end
ap_ST_st8_fsm_7 :
begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end
ap_ST_st9_fsm_8 :
begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end
ap_ST_st10_fsm_9 :
begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end
ap_ST_st11_fsm_10 :
begin
ap_NS_fsm = ap_ST_st12_fsm_11;
end
ap_ST_st12_fsm_11 :
begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
ap_ST_st13_fsm_12 :
begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end
ap_ST_st14_fsm_13 :
begin
ap_NS_fsm = ap_ST_st15_fsm_14;
end
ap_ST_st15_fsm_14 :
begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
ap_ST_st16_fsm_15 :
begin
ap_NS_fsm = ap_ST_st17_fsm_16;
end
ap_ST_st17_fsm_16 :
begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end
ap_ST_st18_fsm_17 :
begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign a_address0 = tmp_2_fu_171_p1;
assign a_i_1_fu_165_p2 = (a_i_reg_101 + ap_const_lv32_1);
always @ (ap_CS_fsm) begin
ap_sig_bdd_105 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_122 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_131 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_139 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_148 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_157 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_166 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_183 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_200 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_208 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_247 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_34 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_78 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
always @ (ap_CS_fsm) begin
ap_sig_bdd_89 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
assign b_address0 = tmp_s_fu_223_p1;
assign c_address0 = tmp_4_fu_241_p1;
assign c_d0 = sum_reg_129;
assign column_cast_fu_190_p1 = column_fu_180_p4;
assign column_fu_180_p4 = {{a_q0[ap_const_lv32_1F : ap_const_lv32_1]}};
assign grp_fu_210_ce = ap_const_logic_1;
assign grp_fu_215_ce = ap_const_logic_1;
assign grp_fu_215_p0 = column_cast_reg_289;
assign grp_fu_228_ce = ap_const_logic_1;
assign iay_1_fu_204_p2 = ($signed(iay_reg_114) + $signed(ap_const_lv32_1));
assign ibx_1_fu_154_p2 = (ibx_reg_90 + ap_const_lv31_1);
assign ibx_cast_fu_145_p1 = ibx_reg_90;
assign sum_1_fu_232_p2 = (tmp_7_reg_319 + sum_reg_129);
assign tmp_1_fu_160_p2 = (iay_reg_114 < a_y? 1'b1: 1'b0);
assign tmp_2_fu_171_p1 = $signed(a_i_reg_101);
assign tmp_4_fu_241_p1 = $signed(tmp_5_fu_237_p2);
assign tmp_5_fu_237_p2 = (tmp_3_reg_329 + ibx_cast_reg_258);
assign tmp_6_fu_176_p1 = a_q0[0:0];
assign tmp_9_fu_219_p2 = (tmp_8_reg_304 + ibx_cast_reg_258);
assign tmp_fu_149_p1 = b_x;
assign tmp_fu_149_p2 = ($signed(ibx_cast_fu_145_p1) < $signed(tmp_fu_149_p1)? 1'b1: 1'b0);
assign tmp_s_fu_223_p1 = tmp_9_fu_219_p2;
always @ (posedge ap_clk) begin
ibx_cast_reg_258[31] <= 1'b0;
column_cast_reg_289[31] <= 1'b0;
end
endmodule //sparse_mm
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SEDFXTP_BEHAVIORAL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXTP_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// PN monitors
`timescale 1ns/100ps
module axi_ad9361_rx_pnmon (
// adc interface
adc_clk,
adc_valid,
adc_data_i,
adc_data_q,
// pn out of sync and error
adc_pnseq_sel,
adc_pn_oos,
adc_pn_err);
// parameters
parameter IQSEL = 0;
parameter PRBS_SEL = 0;
localparam PRBS_P09 = 0;
localparam PRBS_P11 = 1;
localparam PRBS_P15 = 2;
localparam PRBS_P20 = 3;
// adc interface
input adc_clk;
input adc_valid;
input [11:0] adc_data_i;
input [11:0] adc_data_q;
// pn out of sync and error
input [ 3:0] adc_pnseq_sel;
output adc_pn_oos;
output adc_pn_err;
// internal registers
reg adc_pn0_valid = 'd0;
reg [15:0] adc_pn0_data = 'd0;
reg adc_pn0_valid_in = 'd0;
reg [15:0] adc_pn0_data_in = 'd0;
reg [15:0] adc_pn0_data_pn = 'd0;
reg adc_pn1_valid_t = 'd0;
reg [11:0] adc_pn1_data_d = 'd0;
reg adc_pn1_valid_in = 'd0;
reg [23:0] adc_pn1_data_in = 'd0;
reg [23:0] adc_pn1_data_pn = 'd0;
reg adc_pn_valid_in = 'd0;
reg [23:0] adc_pn_data_in = 'd0;
reg [23:0] adc_pn_data_pn = 'd0;
// internal signals
wire [11:0] adc_pn0_data_i_s;
wire [11:0] adc_pn0_data_q_s;
wire [11:0] adc_pn0_data_q_rev_s;
wire [15:0] adc_pn0_data_s;
wire adc_pn0_iq_match_s;
wire [15:0] adc_pn0_data_pn_s;
wire adc_pn1_valid_s;
wire [23:0] adc_pn1_data_pn_s;
// bit reversal function
function [11:0] brfn;
input [11:0] din;
reg [11:0] dout;
begin
dout[11] = din[ 0];
dout[10] = din[ 1];
dout[ 9] = din[ 2];
dout[ 8] = din[ 3];
dout[ 7] = din[ 4];
dout[ 6] = din[ 5];
dout[ 5] = din[ 6];
dout[ 4] = din[ 7];
dout[ 3] = din[ 8];
dout[ 2] = din[ 9];
dout[ 1] = din[10];
dout[ 0] = din[11];
brfn = dout;
end
endfunction
// device-specific prbs function
function [15:0] pn0fn;
input [15:0] din;
reg [15:0] dout;
begin
dout = {din[14:0], ((^din[15:4]) ^ (^din[2:1]))};
pn0fn = dout;
end
endfunction
// standard prbs functions
function [23:0] pn1fn;
input [23:0] din;
reg [23:0] dout;
begin
case (PRBS_SEL)
PRBS_P09: begin
dout[23] = din[ 8] ^ din[ 4];
dout[22] = din[ 7] ^ din[ 3];
dout[21] = din[ 6] ^ din[ 2];
dout[20] = din[ 5] ^ din[ 1];
dout[19] = din[ 4] ^ din[ 0];
dout[18] = din[ 3] ^ din[ 8] ^ din[ 4];
dout[17] = din[ 2] ^ din[ 7] ^ din[ 3];
dout[16] = din[ 1] ^ din[ 6] ^ din[ 2];
dout[15] = din[ 0] ^ din[ 5] ^ din[ 1];
dout[14] = din[ 8] ^ din[ 0];
dout[13] = din[ 7] ^ din[ 8] ^ din[ 4];
dout[12] = din[ 6] ^ din[ 7] ^ din[ 3];
dout[11] = din[ 5] ^ din[ 6] ^ din[ 2];
dout[10] = din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 9] = din[ 3] ^ din[ 4] ^ din[ 0];
dout[ 8] = din[ 2] ^ din[ 3] ^ din[ 8] ^ din[ 4];
dout[ 7] = din[ 1] ^ din[ 2] ^ din[ 7] ^ din[ 3];
dout[ 6] = din[ 0] ^ din[ 1] ^ din[ 6] ^ din[ 2];
dout[ 5] = din[ 8] ^ din[ 0] ^ din[ 4] ^ din[ 5] ^ din[ 1];
dout[ 4] = din[ 7] ^ din[ 8] ^ din[ 3] ^ din[ 0];
dout[ 3] = din[ 6] ^ din[ 7] ^ din[ 2] ^ din[ 8] ^ din[ 4];
dout[ 2] = din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 7] ^ din[ 3];
dout[ 1] = din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 6] ^ din[ 2];
dout[ 0] = din[ 3] ^ din[ 8] ^ din[ 5] ^ din[ 1];
end
PRBS_P11: begin
dout[23] = din[10] ^ din[ 8];
dout[22] = din[ 9] ^ din[ 7];
dout[21] = din[ 8] ^ din[ 6];
dout[20] = din[ 7] ^ din[ 5];
dout[19] = din[ 6] ^ din[ 4];
dout[18] = din[ 5] ^ din[ 3];
dout[17] = din[ 4] ^ din[ 2];
dout[16] = din[ 3] ^ din[ 1];
dout[15] = din[ 2] ^ din[ 0];
dout[14] = din[ 1] ^ din[10] ^ din[ 8];
dout[13] = din[ 0] ^ din[ 9] ^ din[ 7];
dout[12] = din[10] ^ din[ 6];
dout[11] = din[ 9] ^ din[ 5];
dout[10] = din[ 8] ^ din[ 4];
dout[ 9] = din[ 7] ^ din[ 3];
dout[ 8] = din[ 6] ^ din[ 2];
dout[ 7] = din[ 5] ^ din[ 1];
dout[ 6] = din[ 4] ^ din[ 0];
dout[ 5] = din[ 3] ^ din[10] ^ din[ 8];
dout[ 4] = din[ 2] ^ din[ 9] ^ din[ 7];
dout[ 3] = din[ 1] ^ din[ 8] ^ din[ 6];
dout[ 2] = din[ 0] ^ din[ 7] ^ din[ 5];
dout[ 1] = din[10] ^ din[ 6] ^ din[ 8] ^ din[ 4];
dout[ 0] = din[ 9] ^ din[ 5] ^ din[ 7] ^ din[ 3];
end
PRBS_P15: begin
dout[23] = din[14] ^ din[13];
dout[22] = din[13] ^ din[12];
dout[21] = din[12] ^ din[11];
dout[20] = din[11] ^ din[10];
dout[19] = din[10] ^ din[ 9];
dout[18] = din[ 9] ^ din[ 8];
dout[17] = din[ 8] ^ din[ 7];
dout[16] = din[ 7] ^ din[ 6];
dout[15] = din[ 6] ^ din[ 5];
dout[14] = din[ 5] ^ din[ 4];
dout[13] = din[ 4] ^ din[ 3];
dout[12] = din[ 3] ^ din[ 2];
dout[11] = din[ 2] ^ din[ 1];
dout[10] = din[ 1] ^ din[ 0];
dout[ 9] = din[ 0] ^ din[14] ^ din[13];
dout[ 8] = din[14] ^ din[12];
dout[ 7] = din[13] ^ din[11];
dout[ 6] = din[12] ^ din[10];
dout[ 5] = din[11] ^ din[ 9];
dout[ 4] = din[10] ^ din[ 8];
dout[ 3] = din[ 9] ^ din[ 7];
dout[ 2] = din[ 8] ^ din[ 6];
dout[ 1] = din[ 7] ^ din[ 5];
dout[ 0] = din[ 6] ^ din[ 4];
end
PRBS_P20: begin
dout[23] = din[19] ^ din[ 2];
dout[22] = din[18] ^ din[ 1];
dout[21] = din[17] ^ din[ 0];
dout[20] = din[16] ^ din[19] ^ din[ 2];
dout[19] = din[15] ^ din[18] ^ din[ 1];
dout[18] = din[14] ^ din[17] ^ din[ 0];
dout[17] = din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[16] = din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[15] = din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[14] = din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[13] = din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[12] = din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[11] = din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[10] = din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 9] = din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 8] = din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 7] = din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 6] = din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 5] = din[ 1] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 4] = din[ 0] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 3] = din[19] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
dout[ 2] = din[18] ^ din[ 4] ^ din[ 7] ^ din[10] ^ din[13] ^ din[16] ^ din[19] ^ din[ 2];
dout[ 1] = din[17] ^ din[ 3] ^ din[ 6] ^ din[ 9] ^ din[12] ^ din[15] ^ din[18] ^ din[ 1];
dout[ 0] = din[16] ^ din[ 2] ^ din[ 5] ^ din[ 8] ^ din[11] ^ din[14] ^ din[17] ^ din[ 0];
end
endcase
pn1fn = dout;
end
endfunction
// device specific, assuming lower nibble is lost-
assign adc_pn0_data_i_s = (IQSEL == 1) ? adc_data_q : adc_data_i;
assign adc_pn0_data_q_s = (IQSEL == 1) ? adc_data_i : adc_data_q;
assign adc_pn0_data_q_rev_s = brfn(adc_pn0_data_q_s);
assign adc_pn0_data_s = {adc_pn0_data_i_s, adc_pn0_data_q_rev_s[3:0]};
assign adc_pn0_iq_match_s = (adc_pn0_data_i_s[7:0] == adc_pn0_data_q_rev_s[11:4]) ? 1'b1 : 1'b0;
assign adc_pn0_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn0_data_in : adc_pn0_data_pn;
always @(posedge adc_clk) begin
adc_pn0_valid <= adc_valid;
adc_pn0_data <= (adc_pn0_iq_match_s == 1'b0) ? 16'hdead : adc_pn0_data_s;
adc_pn0_valid_in <= adc_pn0_valid;
if (adc_pn0_valid == 1'b1) begin
adc_pn0_data_in <= adc_pn0_data;
adc_pn0_data_pn <= pn0fn(adc_pn0_data_pn_s);
end
end
// standard, runs on 24bit
assign adc_pn1_valid_s = adc_pn1_valid_t & adc_valid;
assign adc_pn1_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn1_data_in : adc_pn1_data_pn;
always @(posedge adc_clk) begin
if (adc_valid == 1'b1) begin
adc_pn1_valid_t <= ~adc_pn1_valid_t;
adc_pn1_data_d <= adc_data_i;
end
adc_pn1_valid_in <= adc_pn1_valid_s;
if (adc_pn1_valid_s == 1'b1) begin
adc_pn1_data_in <= {adc_pn1_data_d, adc_data_i};
adc_pn1_data_pn <= pn1fn(adc_pn1_data_pn_s);
end
end
// pn mux
always @(posedge adc_clk) begin
if (adc_pnseq_sel == 4'h9) begin
adc_pn_valid_in <= adc_pn1_valid_in;
adc_pn_data_in <= adc_pn1_data_in;
adc_pn_data_pn <= adc_pn1_data_pn;
end else begin
adc_pn_valid_in <= adc_pn0_valid_in;
adc_pn_data_in <= {adc_pn0_data_in[7:0], adc_pn0_data_in};
adc_pn_data_pn <= {adc_pn0_data_pn[7:0], adc_pn0_data_pn};
end
end
// pn oos & pn err
ad_pnmon #(.DATA_WIDTH(24)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (adc_pn_valid_in),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_hdmi_tx_16b (
// hdmi interface
hdmi_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
// vdma interface
vdma_clk,
vdma_fs,
vdma_fs_ret,
vdma_valid,
vdma_be,
vdma_data,
vdma_last,
vdma_ready,
// processor interface
up_rstn,
up_clk,
up_sel,
up_rwn,
up_addr,
up_wdata,
up_rdata,
up_ack,
up_status,
// debug interface (chipscope)
debug_data,
debug_trigger);
// hdmi interface
input hdmi_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_fs_ret;
input vdma_valid;
input [ 7:0] vdma_be;
input [63:0] vdma_data;
input vdma_last;
output vdma_ready;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_rwn;
input [ 4:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
output [ 7:0] up_status;
// debug interface (chipscope)
output [63:0] debug_data;
output [ 7:0] debug_trigger;
reg up_crcb_init = 'd0;
reg up_tpg_enable = 'd0;
reg up_csc_bypass = 'd0;
reg up_enable = 'd0;
reg [15:0] up_hs_width = 'd0;
reg [15:0] up_hs_count = 'd0;
reg [15:0] up_hs_de_min = 'd0;
reg [15:0] up_hs_de_max = 'd0;
reg [15:0] up_vs_width = 'd0;
reg [15:0] up_vs_count = 'd0;
reg [15:0] up_vs_de_min = 'd0;
reg [15:0] up_vs_de_max = 'd0;
reg up_hdmi_tpm_oos_hold = 'd0;
reg up_vdma_tpm_oos_hold = 'd0;
reg up_vdma_be_error_hold = 'd0;
reg up_vdma_ovf_hold = 'd0;
reg up_vdma_unf_hold = 'd0;
reg up_cp_en = 'd0;
reg [23:0] up_cp = 'd0;
reg [ 7:0] up_status = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_sel_d = 'd0;
reg up_sel_2d = 'd0;
reg up_ack = 'd0;
reg up_hdmi_tpm_oos_m1 = 'd0;
reg up_vdma_tpm_oos_m1 = 'd0;
reg up_vdma_be_error_m1 = 'd0;
reg up_vdma_ovf_m1 = 'd0;
reg up_vdma_unf_m1 = 'd0;
reg up_hdmi_tpm_oos = 'd0;
reg up_vdma_tpm_oos = 'd0;
reg up_vdma_be_error = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf = 'd0;
wire up_wr_s;
wire up_rd_s;
wire up_ack_s;
wire vdma_wr_s;
wire [ 8:0] vdma_waddr_s;
wire [47:0] vdma_wdata_s;
wire vdma_fs_ret_toggle_s;
wire [ 8:0] vdma_fs_waddr_s;
wire vdma_tpm_oos_s;
wire vdma_be_error_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [63:0] vdma_debug_data_s;
wire [ 7:0] vdma_debug_trigger_s;
wire hdmi_fs_toggle_s;
wire [ 8:0] hdmi_raddr_g_s;
wire hdmi_tpm_oos_s;
wire [63:0] hdmi_debug_data_s;
wire [ 7:0] hdmi_debug_trigger_s;
assign debug_data = vdma_debug_data_s;
assign debug_trigger = vdma_debug_trigger_s;
// processor write interface (see regmap.txt for details)
assign up_wr_s = up_sel & ~up_rwn;
assign up_rd_s = up_sel & up_rwn;
assign up_ack_s = up_sel_d & ~up_sel_2d;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_crcb_init <= 'd0;
up_tpg_enable <= 'd0;
up_csc_bypass <= 'd0;
up_enable <= 'd0;
up_hs_width <= 'd0;
up_hs_count <= 'd0;
up_hs_de_min <= 'd0;
up_hs_de_max <= 'd0;
up_vs_width <= 'd0;
up_vs_count <= 'd0;
up_vs_de_min <= 'd0;
up_vs_de_max <= 'd0;
up_hdmi_tpm_oos_hold <= 'd0;
up_vdma_tpm_oos_hold <= 'd0;
up_vdma_be_error_hold <= 'd0;
up_vdma_ovf_hold <= 'd0;
up_vdma_unf_hold <= 'd0;
up_cp_en <= 'd0;
up_cp <= 'd0;
up_status <= 'd0;
end else begin
if ((up_addr == 5'h01) && (up_wr_s == 1'b1)) begin
up_crcb_init <= up_wdata[3];
up_tpg_enable <= up_wdata[2];
up_csc_bypass <= up_wdata[1];
up_enable <= up_wdata[0];
end
if ((up_addr == 5'h02) && (up_wr_s == 1'b1)) begin
up_hs_width <= up_wdata[31:16];
up_hs_count <= up_wdata[15:0];
end
if ((up_addr == 5'h03) && (up_wr_s == 1'b1)) begin
up_hs_de_min <= up_wdata[31:16];
up_hs_de_max <= up_wdata[15:0];
end
if ((up_addr == 5'h04) && (up_wr_s == 1'b1)) begin
up_vs_width <= up_wdata[31:16];
up_vs_count <= up_wdata[15:0];
end
if ((up_addr == 5'h05) && (up_wr_s == 1'b1)) begin
up_vs_de_min <= up_wdata[31:16];
up_vs_de_max <= up_wdata[15:0];
end
if (up_hdmi_tpm_oos == 1'b1) begin
up_hdmi_tpm_oos_hold <= 1'b1;
end else if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_hdmi_tpm_oos_hold <= up_hdmi_tpm_oos_hold & (~up_wdata[4]);
end
if (up_vdma_tpm_oos == 1'b1) begin
up_vdma_tpm_oos_hold <= 1'b1;
end else if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_vdma_tpm_oos_hold <= up_vdma_tpm_oos_hold & (~up_wdata[3]);
end
if (up_vdma_be_error == 1'b1) begin
up_vdma_be_error_hold <= 1'b1;
end else if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_vdma_be_error_hold <= up_vdma_be_error_hold & (~up_wdata[2]);
end
if (up_vdma_ovf == 1'b1) begin
up_vdma_ovf_hold <= 1'b1;
end else if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_vdma_ovf_hold <= up_vdma_ovf_hold & (~up_wdata[1]);
end
if (up_vdma_unf == 1'b1) begin
up_vdma_unf_hold <= 1'b1;
end else if ((up_addr == 5'h06) && (up_wr_s == 1'b1)) begin
up_vdma_unf_hold <= up_vdma_unf_hold & (~up_wdata[0]);
end
if ((up_addr == 5'h07) && (up_wr_s == 1'b1)) begin
up_cp_en <= up_wdata[24];
up_cp <= up_wdata[23:0];
end
up_status <= {up_enable, up_tpg_enable, up_csc_bypass, up_vdma_be_error_hold,
up_hdmi_tpm_oos_hold, up_vdma_tpm_oos_hold, up_vdma_ovf_hold, up_vdma_unf_hold};
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_sel_d <= 'd0;
up_sel_2d <= 'd0;
up_ack <= 'd0;
end else begin
case (up_addr)
5'h00: up_rdata <= 32'h00010061;
5'h01: up_rdata <= {28'd0, up_crcb_init, up_tpg_enable, up_csc_bypass, up_enable};
5'h02: up_rdata <= {up_hs_width, up_hs_count};
5'h03: up_rdata <= {up_hs_de_min, up_hs_de_max};
5'h04: up_rdata <= {up_vs_width, up_vs_count};
5'h05: up_rdata <= {up_vs_de_min, up_vs_de_max};
5'h06: up_rdata <= {28'd0, up_hdmi_tpm_oos_hold, up_vdma_tpm_oos_hold,
up_vdma_be_error_hold, up_vdma_ovf_hold, up_vdma_unf_hold};
5'h07: up_rdata <= {7'd0, up_cp_en, up_cp};
default: up_rdata <= 0;
endcase
up_sel_d <= up_sel;
up_sel_2d <= up_sel_d;
up_ack <= up_ack_s;
end
end
// the hdmi status signals transferred to the processor clock domain
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_hdmi_tpm_oos_m1 <= 'd0;
up_vdma_tpm_oos_m1 <= 'd0;
up_vdma_be_error_m1 <= 'd0;
up_vdma_ovf_m1 <= 'd0;
up_vdma_unf_m1 <= 'd0;
up_hdmi_tpm_oos <= 'd0;
up_vdma_tpm_oos <= 'd0;
up_vdma_be_error <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf <= 'd0;
end else begin
up_hdmi_tpm_oos_m1 <= hdmi_tpm_oos_s;
up_vdma_tpm_oos_m1 <= vdma_tpm_oos_s;
up_vdma_be_error_m1 <= vdma_be_error_s;
up_vdma_ovf_m1 <= vdma_ovf_s;
up_vdma_unf_m1 <= vdma_unf_s;
up_hdmi_tpm_oos <= up_hdmi_tpm_oos_m1;
up_vdma_tpm_oos <= up_vdma_tpm_oos_m1;
up_vdma_be_error <= up_vdma_be_error_m1;
up_vdma_ovf <= up_vdma_ovf_m1;
up_vdma_unf <= up_vdma_unf_m1;
end
end
// vdma interface
cf_vdma i_vdma (
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.vdma_clk (vdma_clk),
.vdma_fs (vdma_fs),
.vdma_fs_ret (vdma_fs_ret),
.vdma_valid (vdma_valid),
.vdma_be (vdma_be),
.vdma_data (vdma_data),
.vdma_last (vdma_last),
.vdma_ready (vdma_ready),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.vdma_tpm_oos (vdma_tpm_oos_s),
.vdma_be_error (vdma_be_error_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.debug_data (vdma_debug_data_s),
.debug_trigger (vdma_debug_trigger_s));
// hdmi interface
cf_hdmi i_hdmi (
.hdmi_clk (hdmi_clk),
.hdmi_vsync (hdmi_vsync),
.hdmi_hsync (hdmi_hsync),
.hdmi_data_e (hdmi_data_e),
.hdmi_data (hdmi_data),
.hdmi_fs_toggle (hdmi_fs_toggle_s),
.hdmi_raddr_g (hdmi_raddr_g_s),
.hdmi_tpm_oos (hdmi_tpm_oos_s),
.vdma_clk (vdma_clk),
.vdma_wr (vdma_wr_s),
.vdma_waddr (vdma_waddr_s),
.vdma_wdata (vdma_wdata_s),
.vdma_fs_ret_toggle (vdma_fs_ret_toggle_s),
.vdma_fs_waddr (vdma_fs_waddr_s),
.up_enable (up_enable),
.up_crcb_init (up_crcb_init),
.up_tpg_enable (up_tpg_enable),
.up_csc_bypass (up_csc_bypass),
.up_hs_width (up_hs_width),
.up_hs_count (up_hs_count),
.up_hs_de_min (up_hs_de_min),
.up_hs_de_max (up_hs_de_max),
.up_vs_width (up_vs_width),
.up_vs_count (up_vs_count),
.up_vs_de_min (up_vs_de_min),
.up_vs_de_max (up_vs_de_max),
.up_cp_en (up_cp_en),
.up_cp (up_cp),
.debug_data (hdmi_debug_data_s),
.debug_trigger (hdmi_debug_trigger_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 14:40:00 10/31/2016
// Module Name: MEM_WB
// Project Name: MIPS
// Description: The MIPS MEM/WB register (latch) of the MEMORY (MEM) stage.
//
// Dependencies: None.
//
////////////////////////////////////////////////////////////////////////////////
module MEM_WB(
input clk,
input [1:0] control_wb_in,
input [31:0] Read_data_in,
input [31:0] ALU_result_in,
input [4:0] Write_reg_in,
output reg [1:0] mem_control_wb,
output reg [31:0] Read_data,
output reg [31:0] mem_ALU_result,
output reg [4:0] mem_Write_reg);
// Initialize outputs to defaults.
initial
begin
mem_control_wb <= 0;
Read_data <= 0;
mem_ALU_result <= 0;
mem_Write_reg <= 0;
end
// Update outputs.
always @ (posedge clk)
begin
mem_control_wb <= control_wb_in;
Read_data <= Read_data_in;
mem_ALU_result <= ALU_result_in;
mem_Write_reg <= Write_reg_in;
end
endmodule
|
// *******************************************************************************************************
// ** **
// ** 25LC256.v - 25LC256 256K-BIT SPI SERIAL EEPROM (VCC = +2.5V TO +5.5V) **
// ** **
// *******************************************************************************************************
// ** **
// ** This information is distributed under license from Young Engineering. **
// ** COPYRIGHT (c) 2006 YOUNG ENGINEERING **
// ** ALL RIGHTS RESERVED **
// ** **
// ** **
// ** Young Engineering provides design expertise for the digital world **
// ** Started in 1990, Young Engineering offers products and services for your electronic design **
// ** project. We have the expertise in PCB, FPGA, ASIC, firmware, and software design. **
// ** From concept to prototype to production, we can help you. **
// ** **
// ** http://www.young-engineering.com/ **
// ** **
// *******************************************************************************************************
// ** **
// ** This information is provided to you for your convenience and use with Microchip products only. **
// ** Microchip disclaims all liability arising from this information and its use. **
// ** **
// ** THIS INFORMATION IS PROVIDED "AS IS." MICROCHIP MAKES NO REPRESENTATION OR WARRANTIES OF **
// ** ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO **
// ** THE INFORMATION PROVIDED TO YOU, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, **
// ** PERFORMANCE, MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR PURPOSE. **
// ** MICROCHIP IS NOT LIABLE, UNDER ANY CIRCUMSTANCES, FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL **
// ** DAMAGES, FOR ANY REASON WHATSOEVER. **
// ** **
// ** It is your responsibility to ensure that your application meets with your specifications. **
// ** **
// *******************************************************************************************************
// ** **
// ** Revision : 1.2 **
// ** Modified Date : 06/05/2006 **
// ** Revision History: **
// ** **
// ** 02/01/2006: Initial design **
// ** 03/10/2006: Modified the write logic to update at the end of the write cycle. **
// ** 06/05/2006: Converted instruction value parameters to macro definitions. **
// ** Modified output data shifter to allow for continuous status register reads. **
// ** Corrected timing checks to reference proper clock edges. **
// ** Added tCLD & tCLE timing checks. **
// ** Changed the legal information in the header. **
// ** **
// *******************************************************************************************************
// ** TABLE OF CONTENTS **
// *******************************************************************************************************
// **---------------------------------------------------------------------------------------------------**
// ** DECLARATIONS **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** INITIALIZATION **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** CORE LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 1.01: Internal Reset Logic **
// ** 1.02: Input Data Shifter **
// ** 1.03: Bit Clock Counter **
// ** 1.04: Instruction Register **
// ** 1.05: Address Register **
// ** 1.06: Block Protect Bits **
// ** 1.07: Write Protect Enable **
// ** 1.08: Write Data Buffer **
// ** 1.09: Write Enable Bit **
// ** 1.10: Write Cycle Processor **
// ** 1.11: Output Data Shifter **
// ** 1.12: Output Data Buffer **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** DEBUG LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 2.01: Memory Data Bytes **
// ** 2.02: Page Buffer Bytes **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** TIMING CHECKS **
// **---------------------------------------------------------------------------------------------------**
// ** **
// *******************************************************************************************************
`timescale 1ns/10ps
module M25LC256 (SI, SO, SCK, CS_N, WP_N, HOLD_N, RESET);
input SI; // serial data input
input SCK; // serial data clock
input CS_N; // chip select - active low
input WP_N; // write protect pin - active low
input HOLD_N; // interface suspend - active low
input RESET; // model reset/power-on reset
output SO; // serial data output
// *******************************************************************************************************
// ** DECLARATIONS **
// *******************************************************************************************************
reg [15:00] DataShifterI; // serial input data shifter
reg [07:00] DataShifterO; // serial output data shifter
reg [31:00] BitCounter; // serial input bit counter
reg [07:00] InstRegister; // instruction register
reg [15:00] AddrRegister; // address register
wire InstructionREAD; // decoded instruction byte
wire InstructionRDSR; // decoded instruction byte
wire InstructionWRSR; // decoded instruction byte
wire InstructionWRDI; // decoded instruction byte
wire InstructionWREN; // decoded instruction byte
wire InstructionWRITE; // decoded instruction byte
reg [07:00] WriteBuffer [0:63]; // 64-byte page write buffer
reg [05:00] WritePointer; // page buffer pointer
reg [06:00] WriteCounter; // byte write counter
reg WriteEnable; // memory write enable bit
wire RstWriteEnable; // asynchronous reset
wire SetWriteEnable; // register set
wire ClrWriteEnable; // register clear
reg WriteActive; // write operation in progress
reg BlockProtect0; // memory block write protect
reg BlockProtect1; // memory block write protect
reg BlockProtect0_New; // memory data to be written
reg BlockProtect1_New; // memory data to be written
reg WP_Enable; // write protect pin enable
reg WP_Enable_New; // memory data to be written
wire StatusWriteProtected; // status register write protected
reg [05:00] PageAddress; // page buffer address
reg [14:00] BaseAddress; // memory write base address
reg [14:00] MemWrAddress; // memory write address
reg [14:00] MemRdAddress; // memory read address
reg [07:00] MemoryBlock [0:32767]; // EEPROM data memory array (32768x8)
reg SO_DO; // serial output data - data
wire SO_OE; // serial output data - output enable
reg SO_Enable; // serial data output enable
wire OutputEnable1; // timing accurate output enable
wire OutputEnable2; // timing accurate output enable
wire OutputEnable3; // timing accurate output enable
integer LoopIndex; // iterative loop index
integer tWC; // timing parameter
integer tV; // timing parameter
integer tHZ; // timing parameter
integer tHV; // timing parameter
integer tDIS; // timing parameter
`define PAGE_SIZE 64 // 64-byte page size
`define WREN 8'b0000_0110 // Write Enable instruction
`define READ 8'b0000_0011 // Read instruction
`define WRDI 8'b0000_0100 // Write Disable instruction
`define WRSR 8'b0000_0001 // Write Status Register instruction
`define WRITE 8'b0000_0010 // Write instruction
`define RDSR 8'b0000_0101 // Read Status Register instruction
// *******************************************************************************************************
// ** INITIALIZATION **
// *******************************************************************************************************
initial begin
`ifdef VCC_2_5V_TO_4_5V
tWC = 5000000; // memory write cycle time
tV = 100; // output valid from SCK low
tHZ = 60; // HOLD_N low to output high-Z
tHV = 60; // HOLD_N high to output valid
tDIS = 80; // CS_N high to output disable
`else
`ifdef VCC_4_5V_TO_5_5V
tWC = 5000000; // memory write cycle time
tV = 50; // output valid from SCK low
tHZ = 30; // HOLD_N low to output high-Z
tHV = 30; // HOLD_N high to output valid
tDIS = 40; // CS_N high to output disable
`else
tWC = 5000000; // memory write cycle time
tV = 50; // output valid from SCK low
tHZ = 30; // HOLD_N low to output high-Z
tHV = 30; // HOLD_N high to output valid
tDIS = 40; // CS_N high to output disable
`endif
`endif
end
initial begin
BlockProtect0 = 0;
BlockProtect1 = 0;
WP_Enable = 0;
WriteActive = 0;
WriteEnable = 0;
end
// *******************************************************************************************************
// ** CORE LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 1.01: Internal Reset Logic
// -------------------------------------------------------------------------------------------------------
always @(negedge CS_N) BitCounter <= 0;
always @(negedge CS_N) SO_Enable <= 0;
always @(negedge CS_N) if (!WriteActive) WritePointer <= 0;
always @(negedge CS_N) if (!WriteActive) WriteCounter <= 0;
// -------------------------------------------------------------------------------------------------------
// 1.02: Input Data Shifter
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (HOLD_N == 1) begin
if (CS_N == 0) DataShifterI <= {DataShifterI[14:00],SI};
end
end
// -------------------------------------------------------------------------------------------------------
// 1.03: Bit Clock Counter
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (HOLD_N == 1) begin
if (CS_N == 0) BitCounter <= BitCounter + 1;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.04: Instruction Register
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (HOLD_N == 1) begin
if (BitCounter == 7) InstRegister <= {DataShifterI[06:00],SI};
end
end
assign InstructionREAD = (InstRegister[7:0] == `READ);
assign InstructionRDSR = (InstRegister[7:0] == `RDSR);
assign InstructionWRSR = (InstRegister[7:0] == `WRSR);
assign InstructionWRDI = (InstRegister[7:0] == `WRDI);
assign InstructionWREN = (InstRegister[7:0] == `WREN);
assign InstructionWRITE = (InstRegister[7:0] == `WRITE);
// -------------------------------------------------------------------------------------------------------
// 1.05: Address Register
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (HOLD_N == 1) begin
if ((BitCounter == 23) & !WriteActive) AddrRegister <= {DataShifterI[14:00],SI};
end
end
// -------------------------------------------------------------------------------------------------------
// 1.06: Block Protect Bits
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (HOLD_N == 1) begin
if ((BitCounter == 15) & InstructionWRSR & WriteEnable & !WriteActive & !StatusWriteProtected) begin
BlockProtect1_New <= DataShifterI[02];
BlockProtect0_New <= DataShifterI[01];
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.07: Write Protect Enable
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (HOLD_N == 1) begin
if ((BitCounter == 15) & InstructionWRSR & WriteEnable & !WriteActive & !StatusWriteProtected) begin
WP_Enable_New <= DataShifterI[06];
end
end
end
assign StatusWriteProtected = WP_Enable & (WP_N == 0);
// -------------------------------------------------------------------------------------------------------
// 1.08: Write Data Buffer
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (HOLD_N == 1) begin
if ((BitCounter >= 31) & (BitCounter[2:0] == 7) & InstructionWRITE & WriteEnable & !WriteActive) begin
WriteBuffer[WritePointer] <= {DataShifterI[06:00],SI};
WritePointer <= WritePointer + 1;
if (WriteCounter < `PAGE_SIZE) WriteCounter <= WriteCounter + 1;
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.09: Write Enable Bit
// -------------------------------------------------------------------------------------------------------
always @(posedge CS_N or posedge RstWriteEnable) begin
if (RstWriteEnable) WriteEnable <= 0;
else if (SetWriteEnable) WriteEnable <= 1;
else if (ClrWriteEnable) WriteEnable <= 0;
end
assign RstWriteEnable = RESET;
assign SetWriteEnable = (BitCounter == 8) & InstructionWREN & !WriteActive;
assign ClrWriteEnable = (BitCounter == 8) & InstructionWRDI & !WriteActive;
// -------------------------------------------------------------------------------------------------------
// 1.10: Write Cycle Processor
// -------------------------------------------------------------------------------------------------------
always @(posedge CS_N) begin
if ((BitCounter == 16) & (BitCounter[2:0] == 0) & InstructionWRSR & WriteEnable & !WriteActive) begin
if (!StatusWriteProtected) begin
WriteActive = 1;
#(tWC);
BlockProtect1 = BlockProtect1_New;
BlockProtect0 = BlockProtect0_New;
WP_Enable = WP_Enable_New;
end
WriteActive = 0;
WriteEnable = 0;
end
if ((BitCounter >= 32) & (BitCounter[2:0] == 0) & InstructionWRITE & WriteEnable & !WriteActive) begin
for (LoopIndex = 0; LoopIndex < WriteCounter; LoopIndex = LoopIndex + 1) begin
BaseAddress = {AddrRegister[14:06],6'h00};
PageAddress = (AddrRegister[05:00] + LoopIndex);
MemWrAddress = {BaseAddress[14:06],PageAddress[05:00]};
if ({BlockProtect1,BlockProtect0} == 2'b00) begin
WriteActive = 1;
end
if ({BlockProtect1,BlockProtect0} == 2'b01) begin
if ((MemWrAddress >= 15'h6000) && (MemWrAddress <= 15'h7FFF)) begin
// write protected region
end
else begin
WriteActive = 1;
end
end
if ({BlockProtect1,BlockProtect0} == 2'b10) begin
if ((MemWrAddress >= 15'h4000) && (MemWrAddress <= 15'h7FFF)) begin
// write protected region
end
else begin
WriteActive = 1;
end
end
if ({BlockProtect1,BlockProtect0} == 2'b11) begin
if ((MemWrAddress >= 15'h0000) && (MemWrAddress <= 15'h7FFF)) begin
// write protected region
end
else begin
WriteActive = 1;
end
end
end
if (WriteActive) begin
#(tWC);
for (LoopIndex = 0; LoopIndex < WriteCounter; LoopIndex = LoopIndex + 1) begin
BaseAddress = {AddrRegister[14:06],6'h00};
PageAddress = (AddrRegister[05:00] + LoopIndex);
MemWrAddress = {BaseAddress[14:06],PageAddress[05:00]};
if ({BlockProtect1,BlockProtect0} == 2'b00) begin
MemoryBlock[MemWrAddress] = WriteBuffer[LoopIndex];
end
if ({BlockProtect1,BlockProtect0} == 2'b01) begin
if ((MemWrAddress >= 15'h6000) && (MemWrAddress <= 15'h7FFF)) begin
// write protected region
end
else begin
MemoryBlock[MemWrAddress] = WriteBuffer[LoopIndex];
end
end
if ({BlockProtect1,BlockProtect0} == 2'b10) begin
if ((MemWrAddress >= 15'h4000) && (MemWrAddress <= 15'h7FFF)) begin
// write protected region
end
else begin
MemoryBlock[MemWrAddress] = WriteBuffer[LoopIndex];
end
end
if ({BlockProtect1,BlockProtect0} == 2'b11) begin
if ((MemWrAddress >= 15'h0000) && (MemWrAddress <= 15'h7FFF)) begin
// write protected region
end
else begin
MemoryBlock[MemWrAddress] = WriteBuffer[LoopIndex];
end
end
end
end
WriteActive = 0;
WriteEnable = 0;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.11: Output Data Shifter
// -------------------------------------------------------------------------------------------------------
always @(negedge SCK) begin
if (HOLD_N == 1) begin
if ((BitCounter >= 24) & (BitCounter[2:0] == 0) & InstructionREAD & !WriteActive) begin
if (BitCounter == 24) begin
DataShifterO <= MemoryBlock[AddrRegister[14:00]];
MemRdAddress <= AddrRegister + 1;
SO_Enable <= 1;
end
else begin
DataShifterO <= MemoryBlock[MemRdAddress[14:00]];
MemRdAddress <= MemRdAddress + 1;
end
end
else if ((BitCounter > 7) & (BitCounter[2:0] == 3'b000) & InstructionRDSR) begin
DataShifterO <= {WP_Enable,3'b000,BlockProtect1,BlockProtect0,WriteEnable,WriteActive};
SO_Enable <= 1;
end
else begin
DataShifterO <= DataShifterO << 1;
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.12: Output Data Buffer
// -------------------------------------------------------------------------------------------------------
bufif1 (SO, SO_DO, SO_OE);
always @(DataShifterO) SO_DO <= #(tV) DataShifterO[07];
bufif1 #(tV,0) (OutputEnable1, SO_Enable, 1);
notif1 #(tDIS) (OutputEnable2, CS_N, 1);
bufif1 #(tHV,tHZ) (OutputEnable3, HOLD_N, 1);
assign SO_OE = OutputEnable1 & OutputEnable2 & OutputEnable3;
// *******************************************************************************************************
// ** DEBUG LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 2.01: Memory Data Bytes
// -------------------------------------------------------------------------------------------------------
wire [07:00] MemoryByte0000 = MemoryBlock[00000];
wire [07:00] MemoryByte0001 = MemoryBlock[00001];
wire [07:00] MemoryByte0002 = MemoryBlock[00002];
wire [07:00] MemoryByte0003 = MemoryBlock[00003];
wire [07:00] MemoryByte0004 = MemoryBlock[00004];
wire [07:00] MemoryByte0005 = MemoryBlock[00005];
wire [07:00] MemoryByte0006 = MemoryBlock[00006];
wire [07:00] MemoryByte0007 = MemoryBlock[00007];
wire [07:00] MemoryByte0008 = MemoryBlock[00008];
wire [07:00] MemoryByte0009 = MemoryBlock[00009];
wire [07:00] MemoryByte000A = MemoryBlock[00010];
wire [07:00] MemoryByte000B = MemoryBlock[00011];
wire [07:00] MemoryByte000C = MemoryBlock[00012];
wire [07:00] MemoryByte000D = MemoryBlock[00013];
wire [07:00] MemoryByte000E = MemoryBlock[00014];
wire [07:00] MemoryByte000F = MemoryBlock[00015];
wire [07:00] MemoryByte7FF0 = MemoryBlock[32752];
wire [07:00] MemoryByte7FF1 = MemoryBlock[32753];
wire [07:00] MemoryByte7FF2 = MemoryBlock[32754];
wire [07:00] MemoryByte7FF3 = MemoryBlock[32755];
wire [07:00] MemoryByte7FF4 = MemoryBlock[32756];
wire [07:00] MemoryByte7FF5 = MemoryBlock[32757];
wire [07:00] MemoryByte7FF6 = MemoryBlock[32758];
wire [07:00] MemoryByte7FF7 = MemoryBlock[32759];
wire [07:00] MemoryByte7FF8 = MemoryBlock[32760];
wire [07:00] MemoryByte7FF9 = MemoryBlock[32761];
wire [07:00] MemoryByte7FFA = MemoryBlock[32762];
wire [07:00] MemoryByte7FFB = MemoryBlock[32763];
wire [07:00] MemoryByte7FFC = MemoryBlock[32764];
wire [07:00] MemoryByte7FFD = MemoryBlock[32765];
wire [07:00] MemoryByte7FFE = MemoryBlock[32766];
wire [07:00] MemoryByte7FFF = MemoryBlock[32767];
// -------------------------------------------------------------------------------------------------------
// 2.02: Page Buffer Bytes
// -------------------------------------------------------------------------------------------------------
wire [07:00] PageBuffer00 = WriteBuffer[00];
wire [07:00] PageBuffer01 = WriteBuffer[01];
wire [07:00] PageBuffer02 = WriteBuffer[02];
wire [07:00] PageBuffer03 = WriteBuffer[03];
wire [07:00] PageBuffer04 = WriteBuffer[04];
wire [07:00] PageBuffer05 = WriteBuffer[05];
wire [07:00] PageBuffer06 = WriteBuffer[06];
wire [07:00] PageBuffer07 = WriteBuffer[07];
wire [07:00] PageBuffer08 = WriteBuffer[08];
wire [07:00] PageBuffer09 = WriteBuffer[09];
wire [07:00] PageBuffer0A = WriteBuffer[10];
wire [07:00] PageBuffer0B = WriteBuffer[11];
wire [07:00] PageBuffer0C = WriteBuffer[12];
wire [07:00] PageBuffer0D = WriteBuffer[13];
wire [07:00] PageBuffer0E = WriteBuffer[14];
wire [07:00] PageBuffer0F = WriteBuffer[15];
wire [07:00] PageBuffer10 = WriteBuffer[16];
wire [07:00] PageBuffer11 = WriteBuffer[17];
wire [07:00] PageBuffer12 = WriteBuffer[18];
wire [07:00] PageBuffer13 = WriteBuffer[19];
wire [07:00] PageBuffer14 = WriteBuffer[20];
wire [07:00] PageBuffer15 = WriteBuffer[21];
wire [07:00] PageBuffer16 = WriteBuffer[22];
wire [07:00] PageBuffer17 = WriteBuffer[23];
wire [07:00] PageBuffer18 = WriteBuffer[24];
wire [07:00] PageBuffer19 = WriteBuffer[25];
wire [07:00] PageBuffer1A = WriteBuffer[26];
wire [07:00] PageBuffer1B = WriteBuffer[27];
wire [07:00] PageBuffer1C = WriteBuffer[28];
wire [07:00] PageBuffer1D = WriteBuffer[29];
wire [07:00] PageBuffer1E = WriteBuffer[30];
wire [07:00] PageBuffer1F = WriteBuffer[31];
wire [07:00] PageBuffer20 = WriteBuffer[32];
wire [07:00] PageBuffer21 = WriteBuffer[33];
wire [07:00] PageBuffer22 = WriteBuffer[34];
wire [07:00] PageBuffer23 = WriteBuffer[35];
wire [07:00] PageBuffer24 = WriteBuffer[36];
wire [07:00] PageBuffer25 = WriteBuffer[37];
wire [07:00] PageBuffer26 = WriteBuffer[38];
wire [07:00] PageBuffer27 = WriteBuffer[39];
wire [07:00] PageBuffer28 = WriteBuffer[40];
wire [07:00] PageBuffer29 = WriteBuffer[41];
wire [07:00] PageBuffer2A = WriteBuffer[42];
wire [07:00] PageBuffer2B = WriteBuffer[43];
wire [07:00] PageBuffer2C = WriteBuffer[44];
wire [07:00] PageBuffer2D = WriteBuffer[45];
wire [07:00] PageBuffer2E = WriteBuffer[46];
wire [07:00] PageBuffer2F = WriteBuffer[47];
wire [07:00] PageBuffer30 = WriteBuffer[48];
wire [07:00] PageBuffer31 = WriteBuffer[49];
wire [07:00] PageBuffer32 = WriteBuffer[50];
wire [07:00] PageBuffer33 = WriteBuffer[51];
wire [07:00] PageBuffer34 = WriteBuffer[52];
wire [07:00] PageBuffer35 = WriteBuffer[53];
wire [07:00] PageBuffer36 = WriteBuffer[54];
wire [07:00] PageBuffer37 = WriteBuffer[55];
wire [07:00] PageBuffer38 = WriteBuffer[56];
wire [07:00] PageBuffer39 = WriteBuffer[57];
wire [07:00] PageBuffer3A = WriteBuffer[58];
wire [07:00] PageBuffer3B = WriteBuffer[59];
wire [07:00] PageBuffer3C = WriteBuffer[60];
wire [07:00] PageBuffer3D = WriteBuffer[61];
wire [07:00] PageBuffer3E = WriteBuffer[62];
wire [07:00] PageBuffer3F = WriteBuffer[63];
// *******************************************************************************************************
// ** TIMING CHECKS **
// *******************************************************************************************************
wire TimingCheckEnable = (RESET == 0) & (CS_N == 0);
specify
`ifdef VCC_2_5V_TO_4_5V
specparam
tHI = 100, // Clock high time
tLO = 100, // Clock low time
tSU = 20, // Data setup time
tHD = 40, // Data hold time
tHS = 40, // HOLD_N setup time
tHH = 40, // HOLD_N hold time
tCSD = 50, // CS_N disable time
tCSS = 100, // CS_N setup time
tCSH = 200, // CS_N hold time
tCLD = 50, // Clock delay time
tCLE = 50; // Clock enable time
`else
`ifdef VCC_4_5V_TO_5_5V
specparam
tHI = 50, // Clock high time
tLO = 50, // Clock low time
tSU = 10, // Data setup time
tHD = 20, // Data hold time
tHS = 20, // HOLD_N setup time
tHH = 20, // HOLD_N hold time
tCSD = 50, // CS_N disable time
tCSS = 50, // CS_N setup time
tCSH = 100, // CS_N hold time
tCLD = 50, // Clock delay time
tCLE = 50; // Clock enable time
`else
specparam
tHI = 50, // Clock high time
tLO = 50, // Clock low time
tSU = 10, // Data setup time
tHD = 20, // Data hold time
tHS = 20, // HOLD_N setup time
tHH = 20, // HOLD_N hold time
tCSD = 50, // CS_N disable time
tCSS = 50, // CS_N setup time
tCSH = 100, // CS_N hold time
tCLD = 50, // Clock delay time
tCLE = 50; // Clock enable time
`endif
`endif
$width (posedge SCK, tHI);
$width (negedge SCK, tLO);
$width (posedge CS_N, tCSD);
$setup (SI, posedge SCK &&& TimingCheckEnable, tSU);
$setup (negedge CS_N, posedge SCK &&& TimingCheckEnable, tCSS);
$setup (negedge SCK, negedge HOLD_N &&& TimingCheckEnable, tHS);
$setup (posedge CS_N, posedge SCK &&& TimingCheckEnable, tCLD);
$hold (posedge SCK &&& TimingCheckEnable, SI, tHD);
$hold (posedge SCK &&& TimingCheckEnable, posedge CS_N, tCSH);
$hold (posedge HOLD_N &&& TimingCheckEnable, posedge SCK, tHH);
$hold (posedge SCK &&& TimingCheckEnable, negedge CS_N, tCLE);
endspecify
endmodule
|
module inicial ( botao, aberto, fechado, motor, sentido, ledVerde, ledVermelho, display, clock );
input botao, aberto, fechado, motor, sentido, clock;
output ledVerde, ledVermelho;
output [6:0] display;
reg [1:0] estado;
reg [4:0] entrada;
reg [6:0] tmpDisplay;
reg tmpLedVerde, tmpLedVermelho;
parameter Fechado = 2'b00, Abrindo = 2'b01, Aberto = 2'b10, Fechando = 2'b11;
initial estado = Fechado;
always @(posedge clock)begin
entrada[4] = botao;
entrada[3] = aberto;
entrada[2] = fechado;
entrada[1] = motor;
entrada[0] = sentido;
case( estado )
Fechado: begin
tmpDisplay = 7'b0001110;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b10110 ) // botao = 1 & aberto = 0 & fechado = 1 & motor = 1 & sentido = 0
estado = Abrindo;
end
Abrindo: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 1;
tmpLedVermelho = 0;
if( entrada == 5'b10010 ) // botao = 1 & aberto = 0 & fechado = 0 && motor = 1 & sentido = 0
estado = Aberto;
if( entrada == 5'b00010 ) // botao = 0 & aberto = 0 & fechado = 0 & motor = 1 & sentido == 0
estado = Fechando;
end
Aberto: begin
tmpDisplay = 7'b0001000;
tmpLedVerde = 0;
tmpLedVermelho = 0;
if( entrada == 5'b01011 ) // botao = 0 & aberto = 1 & fechado = 0 & motor = 1 & sentido = 1
estado = Fechando;
end
Fechando: begin
tmpDisplay = 7'b1000000;
tmpLedVerde = 0;
tmpLedVermelho = 1;
if( entrada == 5'b10011 ) // botao = 1 & aberto = 0 & fechado = 0 & motor = 1 & sentido = 1
estado = Abrindo;
if( entrada == 5'b00011 ) // botao = 0 & aberto = 0 & fechado = 0 & motor = 1 & sentido = 1
estado = Fechado;
end
default: estado = Fechado;
endcase
end
assign display= tmpDisplay;
assign ledVerde = tmpLedVerde;
assign ledVermelho = tmpLedVermelho;
endmodule
module maquina( SW, LEDG, LEDR, HEX0, CLK );
input [4:0] SW;
input CLK;
output [0:0] LEDG, LEDR;
output [6:0] HEX0;
inicial a( SW[4], SW[3], SW[2], SW[1], SW[0], LEDG[0], LEDR[0], HEX0, CLK);
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_256bit_16word.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_256bit_16word (
byteena_a,
clock,
data,
rdaddress,
wraddress,
wren,
q);
input [31:0] byteena_a;
input clock;
input [255:0] data;
input [3:0] rdaddress;
input [3:0] wraddress;
input wren;
output [255:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [31:0] byteena_a;
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [255:0] sub_wire0;
wire [255:0] q = sub_wire0[255:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.byteena_a (byteena_a),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({256{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV GX",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 16,
altsyncram_component.numwords_b = 16,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 4,
altsyncram_component.widthad_b = 4,
altsyncram_component.width_a = 256,
altsyncram_component.width_b = 256,
altsyncram_component.width_byteena_a = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "256"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "256"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "256"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "256"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "256"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "256"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "32"
// Retrieval info: USED_PORT: byteena_a 0 0 32 0 INPUT VCC "byteena_a[31..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL "data[255..0]"
// Retrieval info: USED_PORT: q 0 0 256 0 OUTPUT NODEFVAL "q[255..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL "rdaddress[3..0]"
// Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL "wraddress[3..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 4 0 wraddress 0 0 4 0
// Retrieval info: CONNECT: @address_b 0 0 4 0 rdaddress 0 0 4 0
// Retrieval info: CONNECT: @byteena_a 0 0 32 0 byteena_a 0 0 32 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 256 0 data 0 0 256 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 256 0 @q_b 0 0 256 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256bit_16word.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256bit_16word.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256bit_16word.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256bit_16word.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256bit_16word_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256bit_16word_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module BET_FSM (
clk_50,
rst,
// ram (BET) ports
ram_addr,
ram_r,
ram_w,
ram_w_en,
// garbage collection ports
garbage_en,
garbage_state,
garbage_addr
);
parameter T = 100;
parameter BET_size = 8192;
parameter cmp_ratio = 3'd0,
cmp_flag_count = 3'd1,
rst_bet = 3'd2,
read_bet = 3'd3,
check_flag = 3'd4,
errase_start = 3'd5,
errase_done = 3'd6;
input clk_50, rst;
input ram_r, garbage_state;
output ram_w, ram_w_en, garbage_en;
output [11:0] garbage_addr, ram_addr;
reg ram_w, ram_w_en, flag, garbage_en;
reg [2:0] NS,S;
reg [11:0] f_index,f_index_next, ram_addr, garbage_addr, count;
reg [31:0] e_cnt, f_cnt,ratio;
always @(posedge clk_50 or negedge rst) begin
if (rst == 1'b0) begin
S <= cmp_ratio;
NS <= cmp_ratio;
end else begin
S <= NS;
case (S)
cmp_ratio:
begin
if (ratio < T)
NS <= cmp_ratio;
else
NS <= cmp_flag_count;
end
cmp_flag_count:
begin
if (f_cnt < BET_size)
NS <= read_bet;
else
NS <= rst_bet;
end
rst_bet:
begin
if (count <= BET_size) begin
count <= count + 1'b1;
ram_w_en <= 1'b1;
ram_w <= 1'b0;
ram_addr <= count;
end else begin
f_cnt <= 32'd0;
count <= 12'd0;
NS <= cmp_ratio;
end
end
read_bet:
begin
flag <= ram_r;
ram_addr <= f_index_next;
end
check_flag:
begin
if( flag == 1'b1) begin
NS <= read_bet;
f_index <= f_index_next;
f_index_next <= f_index_next + 1'b1;
end else begin
NS <= errase_start;
end
end
errase_start:
begin
garbage_addr <= f_index;
if (garbage_state == 1'b0) begin
garbage_en <= 1'b1;
NS <= errase_done;
end else begin
garbage_en <= 1'b0;
NS <= errase_start;
end
end
errase_done:
begin
if (garbage_state == 1'b1) begin
NS <= errase_done;
end else begin
NS <= cmp_ratio;
end
end
default:
begin
NS <= cmp_ratio;
end
endcase
end
end
always @ (posedge clk_50 or negedge rst) begin
if (rst == 1'b0) begin
ratio <= 32'd0;
end else begin
ratio <= e_cnt / f_cnt;
end
end
endmodule |
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module linebuffer(
//input TEST_MODE,
//input [7:0] GBD,
input CK,
input WE,
input LOAD,
input CLEARING,
input [3:0] COLOR_INDEX,
input PCK2,
input [7:0] SPR_PAL,
input [7:0] ADDR_LOAD,
output [11:0] DATA_OUT
);
// 192 pixels * 12 bits
reg [11:0] LB_RAM[0:255]; // TODO: Add a check, should never go over 191
reg [7:0] PAL_REG;
reg [7:0] ADDR_COUNTER;
reg [7:0] ADDR_LATCH;
wire [7:0] ADDR_MUX;
wire [11:0] DATA_IN;
wire [3:0] COLOR_GATED;
assign RAM_WE = ~WE;
assign RAM_RE = ~RAM_WE;
// Switch between color index or backdrop clear
// BL: NUDE NOSY...
// BR: NEGA NACO...
// TL: MOZA MAKO...
// TR: NUDE NOSY...
assign COLOR_GATED = COLOR_INDEX | {4{CLEARING}};
// Select color index or test data (unused)
// BL: NODO NUJA...
// BR: NOFA NYKO...
// TL: MAPE MUCA...
// TR: LANO LODO...
assign DATA_IN[3:0] = COLOR_GATED; // TEST_MODE ? GBD : COLOR_GATED;
// Latch sprite palette from P bus
// BL: MANA NAKA...
// BR: MESY NEPA...
// TL: JETU JUMA...
// TR: GENA HARU...
always @(posedge PCK2)
PAL_REG <= SPR_PAL;
// Switch between sprite palette or backdrop clear
// BL: MORA NOKU...
// BR: MECY NUXA...
// TL: JEZA JODE...
// TR: GUSU HYKU...
assign DATA_IN[11:4] = PAL_REG | {8{CLEARING}};
// Switch between address inc or address reload
// BL: RUFY QAZU...
// BR: PECU QUNY...
// TL: BAME CUNU...
// TR: EGED DUGA...
assign ADDR_MUX = LOAD ? (ADDR_COUNTER + 1'b1) : ADDR_LOAD;
// Address counter update
// BL: REVA QEVU...
// BR: PAJE QATA...
// TL: BEWA CENA...
// TR: EPAQ DAFU...
always @(posedge CK)
ADDR_COUNTER <= ADDR_MUX;
// Address counter latch
// BL: NACY OKYS...
// BR: PEXU QUVU...
// TL: ERYV ENOG...
// TR: EDYZ ASYX...
always @(*)
if (WE) ADDR_LATCH <= ADDR_COUNTER;
// RAM read
assign #10 DATA_OUT = RAM_RE ? LB_RAM[ADDR_LATCH] : 12'bzzzzzzzzzzzz;
// RAM write
always @(posedge RAM_WE)
LB_RAM[ADDR_LATCH] <= DATA_IN; // #10
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_pc_2,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_pc_2,axi_protocol_converter_v2_1_14_axi_protocol_converter,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_\
WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_pc_2 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_14_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__OR3B_PP_BLACKBOX_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_PP_BLACKBOX_V
|
//
// Copyright (C) 2017 Markus Hiienkari <[email protected]>
//
// This file is part of Open Source Scan Converter project.
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
`define LT_STATE_IDLE 2'h0
`define LT_STATE_LAT_MEAS 2'h1
`define LT_STATE_STB_MEAS 2'h2
`define LT_STATE_FINISHED 2'h3
module lat_tester (
input clk27,
input pclk,
input active,
input armed,
input sensor,
input trigger,
input VSYNC_in,
input [1:0] mode_in,
output reg [2:0] mode_synced,
output reg [15:0] lat_result,
output reg [11:0] stb_result,
output trig_waiting,
output reg finished
);
reg VSYNC_in_L, VSYNC_in_LL, trigger_L, trigger_LL;
reg [8:0] clk27_ctr;
reg [1:0] state;
assign trig_waiting = (state == `LT_STATE_LAT_MEAS);
always @(posedge pclk) begin
VSYNC_in_L <= VSYNC_in;
VSYNC_in_LL <= VSYNC_in_L;
end
always @(posedge pclk) begin
if (VSYNC_in_LL && !VSYNC_in_L)
mode_synced <= mode_in;
end
always @(posedge clk27) begin
trigger_L <= trigger;
trigger_LL <= trigger_L;
end
always @(posedge clk27) begin
if (!active) begin
state <= `LT_STATE_IDLE;
end else begin
case (state)
default: begin //STATE_IDLE
finished <= 1'b0;
lat_result <= 0;
stb_result <= 0;
clk27_ctr <= 0;
if (armed && trigger_LL)
state <= `LT_STATE_LAT_MEAS;
end
`LT_STATE_LAT_MEAS: begin
if (sensor==0) begin
state <= `LT_STATE_STB_MEAS;
clk27_ctr <= 0;
end else if (lat_result==16'hffff) begin
state <= `LT_STATE_FINISHED;
end else begin
if (clk27_ctr == 270-1) begin
clk27_ctr <= 0;
lat_result <= lat_result + 1'b1;
end else begin
clk27_ctr <= clk27_ctr + 1'b1;
end
end
end
`LT_STATE_STB_MEAS: begin
if (((sensor==1) && (stb_result >= 12'd100)) || (stb_result == 12'hfff)) begin
state <= `LT_STATE_FINISHED;
end else begin
if (clk27_ctr == 270-1) begin
clk27_ctr <= 0;
stb_result <= stb_result + 1'b1;
end else begin
clk27_ctr <= clk27_ctr + 1'b1;
end
end
end
`LT_STATE_FINISHED: begin
finished <= 1'b1;
if (!armed)
state <= `LT_STATE_IDLE;
end
endcase
end
end
endmodule
|
// Filename: sevensegmentdecoder_assign.v
// Author: Danny Dutton
// Date: 03/03/15
// Version: 1
// Description: Decode 4-bit input and drive a seven segment using assignment
module sevensegdecoder_always(digit, drivers);
input [3:0] digit;
output [6:0] drivers; // Take a to be the MSB of the vector.
reg [6:0] drivers;
always @(digit) begin
if(digit == 4'h0)
begin
drivers = 7'b0000001;
end
if(digit == 4'h1)
begin
drivers = 7'b1001111;
end
if(digit == 4'h2)
begin
drivers = 7'b0010010;
end
if(digit == 4'h3)
begin
drivers = 7'b0000110;
end
if(digit == 4'h4)
begin
drivers = 7'b1001100;
end
if(digit == 4'h5)
begin
drivers = 7'b0100100;
end
if(digit == 4'h6)
begin
drivers = 7'b0100000;
end
if(digit == 4'h7)
begin
drivers = 7'b0001101;
end
if(digit == 4'h8)
begin
drivers = 7'b0000000;
end
if(digit == 4'h9)
begin
drivers = 7'b0000100;
end
if(digit == 4'hA)
begin
drivers = 7'b0001000;
end
if(digit == 4'hB)
begin
drivers = 7'b1100000;
end
if(digit == 4'hC)
begin
drivers = 7'b0110001;
end
if(digit == 4'hD)
begin
drivers = 7'b1000010;
end
if(digit == 4'hE)
begin
drivers = 7'b0110000;
end
if(digit == 4'hF)
begin
drivers = 7'b0111000;
end
end
endmodule |
/*
* Copyright (c) 2002 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
module main;
test tt();
defparam tt.foo = 4;
endmodule // main
module test;
parameter foo = 10;
reg [foo-1:0] bar;
initial begin
if ($bits(bar) != 4) begin
$display("FAILED -- $bits(bar) = %d", $bits(bar));
$finish;
end
$display("PASSED");
end
endmodule // test
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.1 (win64) Build 1538259 Fri Apr 8 15:45:27 MDT 2016
// Date : Fri May 27 10:44:27 2016
// Host : Wojciech-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// C:/Users/Wojciech/Documents/Xilinx/Projects/DOS_Mario/DOS_Mario.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_0_sim_netlist.v
// Design : dist_mem_gen_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "dist_mem_gen_0,dist_mem_gen_v8_0_10,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "dist_mem_gen_v8_0_10,Vivado 2016.1" *)
(* NotValidForBitStream *)
module dist_mem_gen_0
(a,
spo);
input [10:0]a;
output [23:0]spo;
wire [10:0]a;
wire [23:0]spo;
wire [23:0]NLW_U0_dpo_UNCONNECTED;
wire [23:0]NLW_U0_qdpo_UNCONNECTED;
wire [23:0]NLW_U0_qspo_UNCONNECTED;
(* C_FAMILY = "artix7" *)
(* C_HAS_D = "0" *)
(* C_HAS_DPO = "0" *)
(* C_HAS_DPRA = "0" *)
(* C_HAS_I_CE = "0" *)
(* C_HAS_QDPO = "0" *)
(* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *)
(* C_HAS_QDPO_RST = "0" *)
(* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_WE = "0" *)
(* C_MEM_TYPE = "0" *)
(* C_PIPELINE_STAGES = "0" *)
(* C_QCE_JOINED = "0" *)
(* C_QUALIFY_WE = "0" *)
(* C_REG_DPRA_INPUT = "0" *)
(* KEEP_HIERARCHY = "true" *)
(* c_addr_width = "11" *)
(* c_default_data = "0" *)
(* c_depth = "1600" *)
(* c_elaboration_dir = "./" *)
(* c_has_clk = "0" *)
(* c_has_qspo = "0" *)
(* c_has_qspo_ce = "0" *)
(* c_has_qspo_rst = "0" *)
(* c_has_qspo_srst = "0" *)
(* c_has_spo = "1" *)
(* c_mem_init_file = "dist_mem_gen_0.mif" *)
(* c_parser_type = "1" *)
(* c_read_mif = "1" *)
(* c_reg_a_d_inputs = "0" *)
(* c_sync_enable = "1" *)
(* c_width = "24" *)
dist_mem_gen_0_dist_mem_gen_v8_0_10 U0
(.a(a),
.clk(1'b0),
.d({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dpo(NLW_U0_dpo_UNCONNECTED[23:0]),
.dpra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.i_ce(1'b1),
.qdpo(NLW_U0_qdpo_UNCONNECTED[23:0]),
.qdpo_ce(1'b1),
.qdpo_clk(1'b0),
.qdpo_rst(1'b0),
.qdpo_srst(1'b0),
.qspo(NLW_U0_qspo_UNCONNECTED[23:0]),
.qspo_ce(1'b1),
.qspo_rst(1'b0),
.qspo_srst(1'b0),
.spo(spo),
.we(1'b0));
endmodule
(* C_ADDR_WIDTH = "11" *) (* C_DEFAULT_DATA = "0" *) (* C_DEPTH = "1600" *)
(* C_ELABORATION_DIR = "./" *) (* C_FAMILY = "artix7" *) (* C_HAS_CLK = "0" *)
(* C_HAS_D = "0" *) (* C_HAS_DPO = "0" *) (* C_HAS_DPRA = "0" *)
(* C_HAS_I_CE = "0" *) (* C_HAS_QDPO = "0" *) (* C_HAS_QDPO_CE = "0" *)
(* C_HAS_QDPO_CLK = "0" *) (* C_HAS_QDPO_RST = "0" *) (* C_HAS_QDPO_SRST = "0" *)
(* C_HAS_QSPO = "0" *) (* C_HAS_QSPO_CE = "0" *) (* C_HAS_QSPO_RST = "0" *)
(* C_HAS_QSPO_SRST = "0" *) (* C_HAS_SPO = "1" *) (* C_HAS_WE = "0" *)
(* C_MEM_INIT_FILE = "dist_mem_gen_0.mif" *) (* C_MEM_TYPE = "0" *) (* C_PARSER_TYPE = "1" *)
(* C_PIPELINE_STAGES = "0" *) (* C_QCE_JOINED = "0" *) (* C_QUALIFY_WE = "0" *)
(* C_READ_MIF = "1" *) (* C_REG_A_D_INPUTS = "0" *) (* C_REG_DPRA_INPUT = "0" *)
(* C_SYNC_ENABLE = "1" *) (* C_WIDTH = "24" *) (* ORIG_REF_NAME = "dist_mem_gen_v8_0_10" *)
module dist_mem_gen_0_dist_mem_gen_v8_0_10
(a,
d,
dpra,
clk,
we,
i_ce,
qspo_ce,
qdpo_ce,
qdpo_clk,
qspo_rst,
qdpo_rst,
qspo_srst,
qdpo_srst,
spo,
dpo,
qspo,
qdpo);
input [10:0]a;
input [23:0]d;
input [10:0]dpra;
input clk;
input we;
input i_ce;
input qspo_ce;
input qdpo_ce;
input qdpo_clk;
input qspo_rst;
input qdpo_rst;
input qspo_srst;
input qdpo_srst;
output [23:0]spo;
output [23:0]dpo;
output [23:0]qspo;
output [23:0]qdpo;
wire \<const0> ;
wire [10:0]a;
wire g0_b1_n_0;
wire g0_b20_n_0;
wire g0_b21_n_0;
wire g0_b23_n_0;
wire g0_b8_n_0;
wire g10_b0_n_0;
wire g10_b10_n_0;
wire g10_b11_n_0;
wire g10_b12_n_0;
wire g10_b13_n_0;
wire g10_b14_n_0;
wire g10_b15_n_0;
wire g10_b16_n_0;
wire g10_b17_n_0;
wire g10_b18_n_0;
wire g10_b19_n_0;
wire g10_b1_n_0;
wire g10_b20_n_0;
wire g10_b21_n_0;
wire g10_b22_n_0;
wire g10_b23_n_0;
wire g10_b2_n_0;
wire g10_b3_n_0;
wire g10_b4_n_0;
wire g10_b5_n_0;
wire g10_b6_n_0;
wire g10_b7_n_0;
wire g10_b8_n_0;
wire g10_b9_n_0;
wire g11_b0_n_0;
wire g11_b10_n_0;
wire g11_b11_n_0;
wire g11_b12_n_0;
wire g11_b13_n_0;
wire g11_b14_n_0;
wire g11_b15_n_0;
wire g11_b16_n_0;
wire g11_b17_n_0;
wire g11_b18_n_0;
wire g11_b19_n_0;
wire g11_b1_n_0;
wire g11_b20_n_0;
wire g11_b21_n_0;
wire g11_b22_n_0;
wire g11_b23_n_0;
wire g11_b2_n_0;
wire g11_b3_n_0;
wire g11_b4_n_0;
wire g11_b5_n_0;
wire g11_b6_n_0;
wire g11_b7_n_0;
wire g11_b8_n_0;
wire g11_b9_n_0;
wire g12_b0_n_0;
wire g12_b10_n_0;
wire g12_b11_n_0;
wire g12_b12_n_0;
wire g12_b13_n_0;
wire g12_b14_n_0;
wire g12_b15_n_0;
wire g12_b16_n_0;
wire g12_b17_n_0;
wire g12_b18_n_0;
wire g12_b19_n_0;
wire g12_b1_n_0;
wire g12_b20_n_0;
wire g12_b21_n_0;
wire g12_b22_n_0;
wire g12_b23_n_0;
wire g12_b2_n_0;
wire g12_b3_n_0;
wire g12_b4_n_0;
wire g12_b5_n_0;
wire g12_b6_n_0;
wire g12_b7_n_0;
wire g12_b8_n_0;
wire g12_b9_n_0;
wire g13_b0_n_0;
wire g13_b10_n_0;
wire g13_b11_n_0;
wire g13_b12_n_0;
wire g13_b13_n_0;
wire g13_b14_n_0;
wire g13_b16_n_0;
wire g13_b17_n_0;
wire g13_b18_n_0;
wire g13_b19_n_0;
wire g13_b1_n_0;
wire g13_b20_n_0;
wire g13_b21_n_0;
wire g13_b22_n_0;
wire g13_b23_n_0;
wire g13_b2_n_0;
wire g13_b3_n_0;
wire g13_b4_n_0;
wire g13_b5_n_0;
wire g13_b6_n_0;
wire g13_b7_n_0;
wire g13_b8_n_0;
wire g13_b9_n_0;
wire g14_b0_n_0;
wire g14_b10_n_0;
wire g14_b11_n_0;
wire g14_b13_n_0;
wire g14_b14_n_0;
wire g14_b16_n_0;
wire g14_b17_n_0;
wire g14_b18_n_0;
wire g14_b19_n_0;
wire g14_b20_n_0;
wire g14_b21_n_0;
wire g14_b22_n_0;
wire g14_b23_n_0;
wire g14_b2_n_0;
wire g14_b3_n_0;
wire g14_b4_n_0;
wire g14_b5_n_0;
wire g14_b6_n_0;
wire g14_b7_n_0;
wire g14_b8_n_0;
wire g14_b9_n_0;
wire g15_b0_n_0;
wire g15_b10_n_0;
wire g15_b11_n_0;
wire g15_b12_n_0;
wire g15_b13_n_0;
wire g15_b14_n_0;
wire g15_b16_n_0;
wire g15_b17_n_0;
wire g15_b18_n_0;
wire g15_b19_n_0;
wire g15_b1_n_0;
wire g15_b20_n_0;
wire g15_b21_n_0;
wire g15_b22_n_0;
wire g15_b23_n_0;
wire g15_b2_n_0;
wire g15_b3_n_0;
wire g15_b4_n_0;
wire g15_b5_n_0;
wire g15_b6_n_0;
wire g15_b7_n_0;
wire g15_b8_n_0;
wire g15_b9_n_0;
wire g16_b0_n_0;
wire g16_b10_n_0;
wire g16_b11_n_0;
wire g16_b12_n_0;
wire g16_b13_n_0;
wire g16_b14_n_0;
wire g16_b15_n_0;
wire g16_b16_n_0;
wire g16_b17_n_0;
wire g16_b18_n_0;
wire g16_b19_n_0;
wire g16_b1_n_0;
wire g16_b20_n_0;
wire g16_b21_n_0;
wire g16_b22_n_0;
wire g16_b23_n_0;
wire g16_b2_n_0;
wire g16_b3_n_0;
wire g16_b4_n_0;
wire g16_b5_n_0;
wire g16_b6_n_0;
wire g16_b7_n_0;
wire g16_b8_n_0;
wire g16_b9_n_0;
wire g17_b0_n_0;
wire g17_b10_n_0;
wire g17_b11_n_0;
wire g17_b12_n_0;
wire g17_b13_n_0;
wire g17_b14_n_0;
wire g17_b15_n_0;
wire g17_b16_n_0;
wire g17_b17_n_0;
wire g17_b18_n_0;
wire g17_b19_n_0;
wire g17_b1_n_0;
wire g17_b20_n_0;
wire g17_b21_n_0;
wire g17_b22_n_0;
wire g17_b23_n_0;
wire g17_b2_n_0;
wire g17_b3_n_0;
wire g17_b4_n_0;
wire g17_b5_n_0;
wire g17_b6_n_0;
wire g17_b7_n_0;
wire g17_b8_n_0;
wire g17_b9_n_0;
wire g18_b0_n_0;
wire g18_b10_n_0;
wire g18_b11_n_0;
wire g18_b12_n_0;
wire g18_b13_n_0;
wire g18_b14_n_0;
wire g18_b15_n_0;
wire g18_b16_n_0;
wire g18_b17_n_0;
wire g18_b18_n_0;
wire g18_b19_n_0;
wire g18_b1_n_0;
wire g18_b20_n_0;
wire g18_b21_n_0;
wire g18_b22_n_0;
wire g18_b23_n_0;
wire g18_b2_n_0;
wire g18_b3_n_0;
wire g18_b4_n_0;
wire g18_b5_n_0;
wire g18_b6_n_0;
wire g18_b7_n_0;
wire g18_b8_n_0;
wire g18_b9_n_0;
wire g19_b0_n_0;
wire g19_b10_n_0;
wire g19_b11_n_0;
wire g19_b12_n_0;
wire g19_b13_n_0;
wire g19_b14_n_0;
wire g19_b15_n_0;
wire g19_b16_n_0;
wire g19_b17_n_0;
wire g19_b18_n_0;
wire g19_b19_n_0;
wire g19_b1_n_0;
wire g19_b20_n_0;
wire g19_b21_n_0;
wire g19_b22_n_0;
wire g19_b23_n_0;
wire g19_b2_n_0;
wire g19_b3_n_0;
wire g19_b4_n_0;
wire g19_b6_n_0;
wire g19_b7_n_0;
wire g19_b8_n_0;
wire g19_b9_n_0;
wire g1_b0_n_0;
wire g1_b10_n_0;
wire g1_b11_n_0;
wire g1_b12_n_0;
wire g1_b13_n_0;
wire g1_b14_n_0;
wire g1_b15_n_0;
wire g1_b16_n_0;
wire g1_b17_n_0;
wire g1_b18_n_0;
wire g1_b19_n_0;
wire g1_b1_n_0;
wire g1_b20_n_0;
wire g1_b21_n_0;
wire g1_b22_n_0;
wire g1_b23_n_0;
wire g1_b2_n_0;
wire g1_b3_n_0;
wire g1_b4_n_0;
wire g1_b5_n_0;
wire g1_b7_n_0;
wire g1_b8_n_0;
wire g1_b9_n_0;
wire g20_b11_n_0;
wire g20_b12_n_0;
wire g20_b14_n_0;
wire g20_b16_n_0;
wire g20_b17_n_0;
wire g20_b18_n_0;
wire g20_b19_n_0;
wire g20_b1_n_0;
wire g20_b20_n_0;
wire g20_b21_n_0;
wire g20_b22_n_0;
wire g20_b23_n_0;
wire g20_b2_n_0;
wire g20_b3_n_0;
wire g20_b5_n_0;
wire g20_b6_n_0;
wire g20_b7_n_0;
wire g20_b8_n_0;
wire g20_b9_n_0;
wire g21_b0_n_0;
wire g21_b10_n_0;
wire g21_b11_n_0;
wire g21_b12_n_0;
wire g21_b13_n_0;
wire g21_b14_n_0;
wire g21_b16_n_0;
wire g21_b17_n_0;
wire g21_b18_n_0;
wire g21_b19_n_0;
wire g21_b1_n_0;
wire g21_b20_n_0;
wire g21_b21_n_0;
wire g21_b22_n_0;
wire g21_b23_n_0;
wire g21_b2_n_0;
wire g21_b3_n_0;
wire g21_b4_n_0;
wire g21_b5_n_0;
wire g21_b6_n_0;
wire g21_b7_n_0;
wire g21_b8_n_0;
wire g21_b9_n_0;
wire g22_b0_n_0;
wire g22_b10_n_0;
wire g22_b11_n_0;
wire g22_b12_n_0;
wire g22_b13_n_0;
wire g22_b14_n_0;
wire g22_b15_n_0;
wire g22_b16_n_0;
wire g22_b17_n_0;
wire g22_b18_n_0;
wire g22_b19_n_0;
wire g22_b1_n_0;
wire g22_b20_n_0;
wire g22_b21_n_0;
wire g22_b22_n_0;
wire g22_b23_n_0;
wire g22_b2_n_0;
wire g22_b3_n_0;
wire g22_b4_n_0;
wire g22_b5_n_0;
wire g22_b6_n_0;
wire g22_b7_n_0;
wire g22_b8_n_0;
wire g22_b9_n_0;
wire g23_b0_n_0;
wire g23_b10_n_0;
wire g23_b11_n_0;
wire g23_b12_n_0;
wire g23_b13_n_0;
wire g23_b14_n_0;
wire g23_b16_n_0;
wire g23_b17_n_0;
wire g23_b18_n_0;
wire g23_b19_n_0;
wire g23_b1_n_0;
wire g23_b20_n_0;
wire g23_b21_n_0;
wire g23_b22_n_0;
wire g23_b23_n_0;
wire g23_b2_n_0;
wire g23_b3_n_0;
wire g23_b4_n_0;
wire g23_b5_n_0;
wire g23_b6_n_0;
wire g23_b7_n_0;
wire g23_b8_n_0;
wire g23_b9_n_0;
wire g24_b10_n_0;
wire g24_b12_n_0;
wire g24_b16_n_0;
wire g24_b18_n_0;
wire g24_b1_n_0;
wire g24_b20_n_0;
wire g24_b21_n_0;
wire g24_b23_n_0;
wire g24_b2_n_0;
wire g2_b0_n_0;
wire g2_b10_n_0;
wire g2_b11_n_0;
wire g2_b12_n_0;
wire g2_b13_n_0;
wire g2_b14_n_0;
wire g2_b15_n_0;
wire g2_b16_n_0;
wire g2_b17_n_0;
wire g2_b18_n_0;
wire g2_b19_n_0;
wire g2_b1_n_0;
wire g2_b20_n_0;
wire g2_b21_n_0;
wire g2_b22_n_0;
wire g2_b23_n_0;
wire g2_b2_n_0;
wire g2_b3_n_0;
wire g2_b4_n_0;
wire g2_b5_n_0;
wire g2_b6_n_0;
wire g2_b7_n_0;
wire g2_b8_n_0;
wire g2_b9_n_0;
wire g3_b0_n_0;
wire g3_b10_n_0;
wire g3_b11_n_0;
wire g3_b12_n_0;
wire g3_b13_n_0;
wire g3_b14_n_0;
wire g3_b15_n_0;
wire g3_b16_n_0;
wire g3_b17_n_0;
wire g3_b18_n_0;
wire g3_b19_n_0;
wire g3_b1_n_0;
wire g3_b20_n_0;
wire g3_b21_n_0;
wire g3_b22_n_0;
wire g3_b23_n_0;
wire g3_b2_n_0;
wire g3_b3_n_0;
wire g3_b4_n_0;
wire g3_b5_n_0;
wire g3_b6_n_0;
wire g3_b7_n_0;
wire g3_b8_n_0;
wire g3_b9_n_0;
wire g4_b0_n_0;
wire g4_b10_n_0;
wire g4_b11_n_0;
wire g4_b12_n_0;
wire g4_b14_n_0;
wire g4_b16_n_0;
wire g4_b17_n_0;
wire g4_b18_n_0;
wire g4_b19_n_0;
wire g4_b1_n_0;
wire g4_b20_n_0;
wire g4_b21_n_0;
wire g4_b22_n_0;
wire g4_b23_n_0;
wire g4_b2_n_0;
wire g4_b3_n_0;
wire g4_b4_n_0;
wire g4_b8_n_0;
wire g4_b9_n_0;
wire g5_b0_n_0;
wire g5_b10_n_0;
wire g5_b11_n_0;
wire g5_b12_n_0;
wire g5_b14_n_0;
wire g5_b16_n_0;
wire g5_b17_n_0;
wire g5_b18_n_0;
wire g5_b19_n_0;
wire g5_b1_n_0;
wire g5_b20_n_0;
wire g5_b21_n_0;
wire g5_b22_n_0;
wire g5_b23_n_0;
wire g5_b2_n_0;
wire g5_b3_n_0;
wire g5_b8_n_0;
wire g5_b9_n_0;
wire g6_b0_n_0;
wire g6_b10_n_0;
wire g6_b11_n_0;
wire g6_b12_n_0;
wire g6_b13_n_0;
wire g6_b14_n_0;
wire g6_b16_n_0;
wire g6_b17_n_0;
wire g6_b18_n_0;
wire g6_b19_n_0;
wire g6_b1_n_0;
wire g6_b20_n_0;
wire g6_b21_n_0;
wire g6_b22_n_0;
wire g6_b23_n_0;
wire g6_b2_n_0;
wire g6_b3_n_0;
wire g6_b4_n_0;
wire g6_b5_n_0;
wire g6_b6_n_0;
wire g6_b7_n_0;
wire g6_b8_n_0;
wire g6_b9_n_0;
wire g7_b0_n_0;
wire g7_b10_n_0;
wire g7_b11_n_0;
wire g7_b12_n_0;
wire g7_b13_n_0;
wire g7_b14_n_0;
wire g7_b15_n_0;
wire g7_b16_n_0;
wire g7_b17_n_0;
wire g7_b18_n_0;
wire g7_b19_n_0;
wire g7_b1_n_0;
wire g7_b20_n_0;
wire g7_b21_n_0;
wire g7_b22_n_0;
wire g7_b23_n_0;
wire g7_b2_n_0;
wire g7_b3_n_0;
wire g7_b4_n_0;
wire g7_b5_n_0;
wire g7_b6_n_0;
wire g7_b7_n_0;
wire g7_b8_n_0;
wire g7_b9_n_0;
wire g8_b0_n_0;
wire g8_b10_n_0;
wire g8_b11_n_0;
wire g8_b12_n_0;
wire g8_b13_n_0;
wire g8_b14_n_0;
wire g8_b15_n_0;
wire g8_b16_n_0;
wire g8_b17_n_0;
wire g8_b18_n_0;
wire g8_b19_n_0;
wire g8_b1_n_0;
wire g8_b20_n_0;
wire g8_b21_n_0;
wire g8_b22_n_0;
wire g8_b23_n_0;
wire g8_b2_n_0;
wire g8_b3_n_0;
wire g8_b4_n_0;
wire g8_b5_n_0;
wire g8_b6_n_0;
wire g8_b7_n_0;
wire g8_b8_n_0;
wire g8_b9_n_0;
wire g9_b0_n_0;
wire g9_b10_n_0;
wire g9_b11_n_0;
wire g9_b12_n_0;
wire g9_b13_n_0;
wire g9_b14_n_0;
wire g9_b15_n_0;
wire g9_b16_n_0;
wire g9_b17_n_0;
wire g9_b18_n_0;
wire g9_b19_n_0;
wire g9_b1_n_0;
wire g9_b20_n_0;
wire g9_b21_n_0;
wire g9_b22_n_0;
wire g9_b23_n_0;
wire g9_b2_n_0;
wire g9_b3_n_0;
wire g9_b4_n_0;
wire g9_b5_n_0;
wire g9_b6_n_0;
wire g9_b7_n_0;
wire g9_b8_n_0;
wire g9_b9_n_0;
wire [23:0]spo;
wire \spo[0]_INST_0_i_10_n_0 ;
wire \spo[0]_INST_0_i_11_n_0 ;
wire \spo[0]_INST_0_i_1_n_0 ;
wire \spo[0]_INST_0_i_2_n_0 ;
wire \spo[0]_INST_0_i_3_n_0 ;
wire \spo[0]_INST_0_i_4_n_0 ;
wire \spo[0]_INST_0_i_5_n_0 ;
wire \spo[0]_INST_0_i_6_n_0 ;
wire \spo[0]_INST_0_i_7_n_0 ;
wire \spo[0]_INST_0_i_8_n_0 ;
wire \spo[0]_INST_0_i_9_n_0 ;
wire \spo[10]_INST_0_i_10_n_0 ;
wire \spo[10]_INST_0_i_11_n_0 ;
wire \spo[10]_INST_0_i_12_n_0 ;
wire \spo[10]_INST_0_i_1_n_0 ;
wire \spo[10]_INST_0_i_2_n_0 ;
wire \spo[10]_INST_0_i_3_n_0 ;
wire \spo[10]_INST_0_i_4_n_0 ;
wire \spo[10]_INST_0_i_5_n_0 ;
wire \spo[10]_INST_0_i_6_n_0 ;
wire \spo[10]_INST_0_i_7_n_0 ;
wire \spo[10]_INST_0_i_8_n_0 ;
wire \spo[10]_INST_0_i_9_n_0 ;
wire \spo[11]_INST_0_i_10_n_0 ;
wire \spo[11]_INST_0_i_11_n_0 ;
wire \spo[11]_INST_0_i_12_n_0 ;
wire \spo[11]_INST_0_i_13_n_0 ;
wire \spo[11]_INST_0_i_1_n_0 ;
wire \spo[11]_INST_0_i_2_n_0 ;
wire \spo[11]_INST_0_i_3_n_0 ;
wire \spo[11]_INST_0_i_4_n_0 ;
wire \spo[11]_INST_0_i_5_n_0 ;
wire \spo[11]_INST_0_i_6_n_0 ;
wire \spo[11]_INST_0_i_7_n_0 ;
wire \spo[11]_INST_0_i_8_n_0 ;
wire \spo[11]_INST_0_i_9_n_0 ;
wire \spo[12]_INST_0_i_10_n_0 ;
wire \spo[12]_INST_0_i_11_n_0 ;
wire \spo[12]_INST_0_i_12_n_0 ;
wire \spo[12]_INST_0_i_1_n_0 ;
wire \spo[12]_INST_0_i_2_n_0 ;
wire \spo[12]_INST_0_i_3_n_0 ;
wire \spo[12]_INST_0_i_4_n_0 ;
wire \spo[12]_INST_0_i_5_n_0 ;
wire \spo[12]_INST_0_i_6_n_0 ;
wire \spo[12]_INST_0_i_7_n_0 ;
wire \spo[12]_INST_0_i_8_n_0 ;
wire \spo[12]_INST_0_i_9_n_0 ;
wire \spo[13]_INST_0_i_10_n_0 ;
wire \spo[13]_INST_0_i_11_n_0 ;
wire \spo[13]_INST_0_i_1_n_0 ;
wire \spo[13]_INST_0_i_2_n_0 ;
wire \spo[13]_INST_0_i_3_n_0 ;
wire \spo[13]_INST_0_i_4_n_0 ;
wire \spo[13]_INST_0_i_5_n_0 ;
wire \spo[13]_INST_0_i_6_n_0 ;
wire \spo[13]_INST_0_i_7_n_0 ;
wire \spo[13]_INST_0_i_8_n_0 ;
wire \spo[13]_INST_0_i_9_n_0 ;
wire \spo[14]_INST_0_i_10_n_0 ;
wire \spo[14]_INST_0_i_11_n_0 ;
wire \spo[14]_INST_0_i_12_n_0 ;
wire \spo[14]_INST_0_i_13_n_0 ;
wire \spo[14]_INST_0_i_1_n_0 ;
wire \spo[14]_INST_0_i_2_n_0 ;
wire \spo[14]_INST_0_i_3_n_0 ;
wire \spo[14]_INST_0_i_4_n_0 ;
wire \spo[14]_INST_0_i_5_n_0 ;
wire \spo[14]_INST_0_i_6_n_0 ;
wire \spo[14]_INST_0_i_7_n_0 ;
wire \spo[14]_INST_0_i_8_n_0 ;
wire \spo[14]_INST_0_i_9_n_0 ;
wire \spo[15]_INST_0_i_1_n_0 ;
wire \spo[15]_INST_0_i_2_n_0 ;
wire \spo[15]_INST_0_i_3_n_0 ;
wire \spo[15]_INST_0_i_4_n_0 ;
wire \spo[15]_INST_0_i_5_n_0 ;
wire \spo[15]_INST_0_i_6_n_0 ;
wire \spo[15]_INST_0_i_7_n_0 ;
wire \spo[15]_INST_0_i_8_n_0 ;
wire \spo[16]_INST_0_i_10_n_0 ;
wire \spo[16]_INST_0_i_11_n_0 ;
wire \spo[16]_INST_0_i_12_n_0 ;
wire \spo[16]_INST_0_i_13_n_0 ;
wire \spo[16]_INST_0_i_14_n_0 ;
wire \spo[16]_INST_0_i_1_n_0 ;
wire \spo[16]_INST_0_i_2_n_0 ;
wire \spo[16]_INST_0_i_3_n_0 ;
wire \spo[16]_INST_0_i_4_n_0 ;
wire \spo[16]_INST_0_i_5_n_0 ;
wire \spo[16]_INST_0_i_6_n_0 ;
wire \spo[16]_INST_0_i_7_n_0 ;
wire \spo[16]_INST_0_i_8_n_0 ;
wire \spo[16]_INST_0_i_9_n_0 ;
wire \spo[17]_INST_0_i_10_n_0 ;
wire \spo[17]_INST_0_i_11_n_0 ;
wire \spo[17]_INST_0_i_12_n_0 ;
wire \spo[17]_INST_0_i_13_n_0 ;
wire \spo[17]_INST_0_i_14_n_0 ;
wire \spo[17]_INST_0_i_1_n_0 ;
wire \spo[17]_INST_0_i_2_n_0 ;
wire \spo[17]_INST_0_i_3_n_0 ;
wire \spo[17]_INST_0_i_4_n_0 ;
wire \spo[17]_INST_0_i_5_n_0 ;
wire \spo[17]_INST_0_i_6_n_0 ;
wire \spo[17]_INST_0_i_7_n_0 ;
wire \spo[17]_INST_0_i_8_n_0 ;
wire \spo[17]_INST_0_i_9_n_0 ;
wire \spo[18]_INST_0_i_10_n_0 ;
wire \spo[18]_INST_0_i_11_n_0 ;
wire \spo[18]_INST_0_i_12_n_0 ;
wire \spo[18]_INST_0_i_1_n_0 ;
wire \spo[18]_INST_0_i_2_n_0 ;
wire \spo[18]_INST_0_i_3_n_0 ;
wire \spo[18]_INST_0_i_4_n_0 ;
wire \spo[18]_INST_0_i_5_n_0 ;
wire \spo[18]_INST_0_i_6_n_0 ;
wire \spo[18]_INST_0_i_7_n_0 ;
wire \spo[18]_INST_0_i_8_n_0 ;
wire \spo[18]_INST_0_i_9_n_0 ;
wire \spo[19]_INST_0_i_10_n_0 ;
wire \spo[19]_INST_0_i_11_n_0 ;
wire \spo[19]_INST_0_i_1_n_0 ;
wire \spo[19]_INST_0_i_2_n_0 ;
wire \spo[19]_INST_0_i_3_n_0 ;
wire \spo[19]_INST_0_i_4_n_0 ;
wire \spo[19]_INST_0_i_5_n_0 ;
wire \spo[19]_INST_0_i_6_n_0 ;
wire \spo[19]_INST_0_i_7_n_0 ;
wire \spo[19]_INST_0_i_8_n_0 ;
wire \spo[19]_INST_0_i_9_n_0 ;
wire \spo[1]_INST_0_i_10_n_0 ;
wire \spo[1]_INST_0_i_11_n_0 ;
wire \spo[1]_INST_0_i_12_n_0 ;
wire \spo[1]_INST_0_i_1_n_0 ;
wire \spo[1]_INST_0_i_2_n_0 ;
wire \spo[1]_INST_0_i_3_n_0 ;
wire \spo[1]_INST_0_i_4_n_0 ;
wire \spo[1]_INST_0_i_5_n_0 ;
wire \spo[1]_INST_0_i_6_n_0 ;
wire \spo[1]_INST_0_i_7_n_0 ;
wire \spo[1]_INST_0_i_8_n_0 ;
wire \spo[1]_INST_0_i_9_n_0 ;
wire \spo[20]_INST_0_i_10_n_0 ;
wire \spo[20]_INST_0_i_11_n_0 ;
wire \spo[20]_INST_0_i_12_n_0 ;
wire \spo[20]_INST_0_i_13_n_0 ;
wire \spo[20]_INST_0_i_14_n_0 ;
wire \spo[20]_INST_0_i_1_n_0 ;
wire \spo[20]_INST_0_i_2_n_0 ;
wire \spo[20]_INST_0_i_3_n_0 ;
wire \spo[20]_INST_0_i_4_n_0 ;
wire \spo[20]_INST_0_i_5_n_0 ;
wire \spo[20]_INST_0_i_6_n_0 ;
wire \spo[20]_INST_0_i_7_n_0 ;
wire \spo[20]_INST_0_i_8_n_0 ;
wire \spo[20]_INST_0_i_9_n_0 ;
wire \spo[21]_INST_0_i_10_n_0 ;
wire \spo[21]_INST_0_i_11_n_0 ;
wire \spo[21]_INST_0_i_12_n_0 ;
wire \spo[21]_INST_0_i_13_n_0 ;
wire \spo[21]_INST_0_i_14_n_0 ;
wire \spo[21]_INST_0_i_1_n_0 ;
wire \spo[21]_INST_0_i_2_n_0 ;
wire \spo[21]_INST_0_i_3_n_0 ;
wire \spo[21]_INST_0_i_4_n_0 ;
wire \spo[21]_INST_0_i_5_n_0 ;
wire \spo[21]_INST_0_i_6_n_0 ;
wire \spo[21]_INST_0_i_7_n_0 ;
wire \spo[21]_INST_0_i_8_n_0 ;
wire \spo[21]_INST_0_i_9_n_0 ;
wire \spo[22]_INST_0_i_10_n_0 ;
wire \spo[22]_INST_0_i_11_n_0 ;
wire \spo[22]_INST_0_i_1_n_0 ;
wire \spo[22]_INST_0_i_2_n_0 ;
wire \spo[22]_INST_0_i_3_n_0 ;
wire \spo[22]_INST_0_i_4_n_0 ;
wire \spo[22]_INST_0_i_5_n_0 ;
wire \spo[22]_INST_0_i_6_n_0 ;
wire \spo[22]_INST_0_i_7_n_0 ;
wire \spo[22]_INST_0_i_8_n_0 ;
wire \spo[22]_INST_0_i_9_n_0 ;
wire \spo[23]_INST_0_i_10_n_0 ;
wire \spo[23]_INST_0_i_11_n_0 ;
wire \spo[23]_INST_0_i_12_n_0 ;
wire \spo[23]_INST_0_i_13_n_0 ;
wire \spo[23]_INST_0_i_14_n_0 ;
wire \spo[23]_INST_0_i_1_n_0 ;
wire \spo[23]_INST_0_i_2_n_0 ;
wire \spo[23]_INST_0_i_3_n_0 ;
wire \spo[23]_INST_0_i_4_n_0 ;
wire \spo[23]_INST_0_i_5_n_0 ;
wire \spo[23]_INST_0_i_6_n_0 ;
wire \spo[23]_INST_0_i_7_n_0 ;
wire \spo[23]_INST_0_i_8_n_0 ;
wire \spo[23]_INST_0_i_9_n_0 ;
wire \spo[2]_INST_0_i_10_n_0 ;
wire \spo[2]_INST_0_i_11_n_0 ;
wire \spo[2]_INST_0_i_12_n_0 ;
wire \spo[2]_INST_0_i_13_n_0 ;
wire \spo[2]_INST_0_i_14_n_0 ;
wire \spo[2]_INST_0_i_1_n_0 ;
wire \spo[2]_INST_0_i_2_n_0 ;
wire \spo[2]_INST_0_i_3_n_0 ;
wire \spo[2]_INST_0_i_4_n_0 ;
wire \spo[2]_INST_0_i_5_n_0 ;
wire \spo[2]_INST_0_i_6_n_0 ;
wire \spo[2]_INST_0_i_7_n_0 ;
wire \spo[2]_INST_0_i_8_n_0 ;
wire \spo[2]_INST_0_i_9_n_0 ;
wire \spo[3]_INST_0_i_10_n_0 ;
wire \spo[3]_INST_0_i_11_n_0 ;
wire \spo[3]_INST_0_i_1_n_0 ;
wire \spo[3]_INST_0_i_2_n_0 ;
wire \spo[3]_INST_0_i_3_n_0 ;
wire \spo[3]_INST_0_i_4_n_0 ;
wire \spo[3]_INST_0_i_5_n_0 ;
wire \spo[3]_INST_0_i_6_n_0 ;
wire \spo[3]_INST_0_i_7_n_0 ;
wire \spo[3]_INST_0_i_8_n_0 ;
wire \spo[3]_INST_0_i_9_n_0 ;
wire \spo[4]_INST_0_i_10_n_0 ;
wire \spo[4]_INST_0_i_11_n_0 ;
wire \spo[4]_INST_0_i_1_n_0 ;
wire \spo[4]_INST_0_i_2_n_0 ;
wire \spo[4]_INST_0_i_3_n_0 ;
wire \spo[4]_INST_0_i_4_n_0 ;
wire \spo[4]_INST_0_i_5_n_0 ;
wire \spo[4]_INST_0_i_6_n_0 ;
wire \spo[4]_INST_0_i_7_n_0 ;
wire \spo[4]_INST_0_i_8_n_0 ;
wire \spo[4]_INST_0_i_9_n_0 ;
wire \spo[5]_INST_0_i_10_n_0 ;
wire \spo[5]_INST_0_i_11_n_0 ;
wire \spo[5]_INST_0_i_1_n_0 ;
wire \spo[5]_INST_0_i_2_n_0 ;
wire \spo[5]_INST_0_i_3_n_0 ;
wire \spo[5]_INST_0_i_4_n_0 ;
wire \spo[5]_INST_0_i_5_n_0 ;
wire \spo[5]_INST_0_i_6_n_0 ;
wire \spo[5]_INST_0_i_7_n_0 ;
wire \spo[5]_INST_0_i_8_n_0 ;
wire \spo[5]_INST_0_i_9_n_0 ;
wire \spo[6]_INST_0_i_10_n_0 ;
wire \spo[6]_INST_0_i_11_n_0 ;
wire \spo[6]_INST_0_i_12_n_0 ;
wire \spo[6]_INST_0_i_1_n_0 ;
wire \spo[6]_INST_0_i_2_n_0 ;
wire \spo[6]_INST_0_i_3_n_0 ;
wire \spo[6]_INST_0_i_4_n_0 ;
wire \spo[6]_INST_0_i_5_n_0 ;
wire \spo[6]_INST_0_i_6_n_0 ;
wire \spo[6]_INST_0_i_7_n_0 ;
wire \spo[6]_INST_0_i_8_n_0 ;
wire \spo[6]_INST_0_i_9_n_0 ;
wire \spo[7]_INST_0_i_10_n_0 ;
wire \spo[7]_INST_0_i_11_n_0 ;
wire \spo[7]_INST_0_i_12_n_0 ;
wire \spo[7]_INST_0_i_13_n_0 ;
wire \spo[7]_INST_0_i_1_n_0 ;
wire \spo[7]_INST_0_i_2_n_0 ;
wire \spo[7]_INST_0_i_3_n_0 ;
wire \spo[7]_INST_0_i_4_n_0 ;
wire \spo[7]_INST_0_i_5_n_0 ;
wire \spo[7]_INST_0_i_6_n_0 ;
wire \spo[7]_INST_0_i_7_n_0 ;
wire \spo[7]_INST_0_i_8_n_0 ;
wire \spo[7]_INST_0_i_9_n_0 ;
wire \spo[8]_INST_0_i_10_n_0 ;
wire \spo[8]_INST_0_i_11_n_0 ;
wire \spo[8]_INST_0_i_12_n_0 ;
wire \spo[8]_INST_0_i_13_n_0 ;
wire \spo[8]_INST_0_i_1_n_0 ;
wire \spo[8]_INST_0_i_2_n_0 ;
wire \spo[8]_INST_0_i_3_n_0 ;
wire \spo[8]_INST_0_i_4_n_0 ;
wire \spo[8]_INST_0_i_5_n_0 ;
wire \spo[8]_INST_0_i_6_n_0 ;
wire \spo[8]_INST_0_i_7_n_0 ;
wire \spo[8]_INST_0_i_8_n_0 ;
wire \spo[8]_INST_0_i_9_n_0 ;
wire \spo[9]_INST_0_i_10_n_0 ;
wire \spo[9]_INST_0_i_11_n_0 ;
wire \spo[9]_INST_0_i_12_n_0 ;
wire \spo[9]_INST_0_i_13_n_0 ;
wire \spo[9]_INST_0_i_1_n_0 ;
wire \spo[9]_INST_0_i_2_n_0 ;
wire \spo[9]_INST_0_i_3_n_0 ;
wire \spo[9]_INST_0_i_4_n_0 ;
wire \spo[9]_INST_0_i_5_n_0 ;
wire \spo[9]_INST_0_i_6_n_0 ;
wire \spo[9]_INST_0_i_7_n_0 ;
wire \spo[9]_INST_0_i_8_n_0 ;
wire \spo[9]_INST_0_i_9_n_0 ;
assign dpo[23] = \<const0> ;
assign dpo[22] = \<const0> ;
assign dpo[21] = \<const0> ;
assign dpo[20] = \<const0> ;
assign dpo[19] = \<const0> ;
assign dpo[18] = \<const0> ;
assign dpo[17] = \<const0> ;
assign dpo[16] = \<const0> ;
assign dpo[15] = \<const0> ;
assign dpo[14] = \<const0> ;
assign dpo[13] = \<const0> ;
assign dpo[12] = \<const0> ;
assign dpo[11] = \<const0> ;
assign dpo[10] = \<const0> ;
assign dpo[9] = \<const0> ;
assign dpo[8] = \<const0> ;
assign dpo[7] = \<const0> ;
assign dpo[6] = \<const0> ;
assign dpo[5] = \<const0> ;
assign dpo[4] = \<const0> ;
assign dpo[3] = \<const0> ;
assign dpo[2] = \<const0> ;
assign dpo[1] = \<const0> ;
assign dpo[0] = \<const0> ;
assign qdpo[23] = \<const0> ;
assign qdpo[22] = \<const0> ;
assign qdpo[21] = \<const0> ;
assign qdpo[20] = \<const0> ;
assign qdpo[19] = \<const0> ;
assign qdpo[18] = \<const0> ;
assign qdpo[17] = \<const0> ;
assign qdpo[16] = \<const0> ;
assign qdpo[15] = \<const0> ;
assign qdpo[14] = \<const0> ;
assign qdpo[13] = \<const0> ;
assign qdpo[12] = \<const0> ;
assign qdpo[11] = \<const0> ;
assign qdpo[10] = \<const0> ;
assign qdpo[9] = \<const0> ;
assign qdpo[8] = \<const0> ;
assign qdpo[7] = \<const0> ;
assign qdpo[6] = \<const0> ;
assign qdpo[5] = \<const0> ;
assign qdpo[4] = \<const0> ;
assign qdpo[3] = \<const0> ;
assign qdpo[2] = \<const0> ;
assign qdpo[1] = \<const0> ;
assign qdpo[0] = \<const0> ;
assign qspo[23] = \<const0> ;
assign qspo[22] = \<const0> ;
assign qspo[21] = \<const0> ;
assign qspo[20] = \<const0> ;
assign qspo[19] = \<const0> ;
assign qspo[18] = \<const0> ;
assign qspo[17] = \<const0> ;
assign qspo[16] = \<const0> ;
assign qspo[15] = \<const0> ;
assign qspo[14] = \<const0> ;
assign qspo[13] = \<const0> ;
assign qspo[12] = \<const0> ;
assign qspo[11] = \<const0> ;
assign qspo[10] = \<const0> ;
assign qspo[9] = \<const0> ;
assign qspo[8] = \<const0> ;
assign qspo[7] = \<const0> ;
assign qspo[6] = \<const0> ;
assign qspo[5] = \<const0> ;
assign qspo[4] = \<const0> ;
assign qspo[3] = \<const0> ;
assign qspo[2] = \<const0> ;
assign qspo[1] = \<const0> ;
assign qspo[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h80000800))
g0_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g0_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'hC0B0))
g0_b20
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g0_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT4 #(
.INIT(16'h3F4F))
g0_b21
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g0_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT3 #(
.INIT(8'h73))
g0_b23
(.I0(a[3]),
.I1(a[4]),
.I2(a[5]),
.O(g0_b23_n_0));
LUT5 #(
.INIT(32'h8FFF38FF))
g0_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g0_b8_n_0));
LUT5 #(
.INIT(32'hFCC7FFCC))
g10_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT5 #(
.INIT(32'h88D6388D))
g10_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b1_n_0));
LUT5 #(
.INIT(32'hC9660C96))
g10_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b10_n_0));
LUT5 #(
.INIT(32'hF7C9FF7C))
g10_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT5 #(
.INIT(32'hB1540B15))
g10_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b12_n_0));
LUT5 #(
.INIT(32'h7383F738))
g10_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b13_n_0));
LUT5 #(
.INIT(32'hB5EFFB5E))
g10_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT5 #(
.INIT(32'h08000080))
g10_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b15_n_0));
LUT5 #(
.INIT(32'h7C8A37C8))
g10_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b16_n_0));
LUT5 #(
.INIT(32'h7B6C07B6))
g10_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b17_n_0));
LUT5 #(
.INIT(32'hF6D00F6D))
g10_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b18_n_0));
LUT5 #(
.INIT(32'h4421F442))
g10_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b19_n_0));
LUT5 #(
.INIT(32'h3E1DE3E1))
g10_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b2_n_0));
LUT5 #(
.INIT(32'h0167F016))
g10_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b20_n_0));
LUT5 #(
.INIT(32'h887BF887))
g10_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b21_n_0));
LUT5 #(
.INIT(32'h7BA007BA))
g10_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b22_n_0));
LUT5 #(
.INIT(32'hBDCFFBDC))
g10_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b23_n_0));
LUT5 #(
.INIT(32'h0F97F0F9))
g10_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b3_n_0));
LUT5 #(
.INIT(32'h3B2403B2))
g10_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b4_n_0));
LUT5 #(
.INIT(32'h442C0442))
g10_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b5_n_0));
LUT5 #(
.INIT(32'hB9C3FB9C))
g10_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b6_n_0));
LUT5 #(
.INIT(32'h00080000))
g10_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b7_n_0));
LUT5 #(
.INIT(32'h405A2405))
g10_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b8_n_0));
LUT5 #(
.INIT(32'h0853E085))
g10_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g10_b9_n_0));
LUT5 #(
.INIT(32'h0303B07F))
g11_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT5 #(
.INIT(32'h2207E263))
g11_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b1_n_0));
LUT5 #(
.INIT(32'hC1F8DC60))
g11_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b10_n_0));
LUT5 #(
.INIT(32'hFDFF7F9F))
g11_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT5 #(
.INIT(32'h82001840))
g11_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b12_n_0));
LUT5 #(
.INIT(32'h0003103F))
g11_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b13_n_0));
LUT5 #(
.INIT(32'h1C0011FF))
g11_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT5 #(
.INIT(32'h0000E000))
g11_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b15_n_0));
LUT5 #(
.INIT(32'h5FFB85A3))
g11_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b16_n_0));
LUT5 #(
.INIT(32'hFDFFAFC0))
g11_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b17_n_0));
LUT5 #(
.INIT(32'h42F82400))
g11_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b18_n_0));
LUT5 #(
.INIT(32'h0303301F))
g11_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b19_n_0));
LUT5 #(
.INIT(32'hBC078BDE))
g11_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b2_n_0));
LUT5 #(
.INIT(32'hE3FC5E7F))
g11_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b20_n_0));
LUT5 #(
.INIT(32'h9C00E9BF))
g11_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b21_n_0));
LUT4 #(
.INIT(16'h01C0))
g11_b22
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g11_b22_n_0));
LUT5 #(
.INIT(32'h1C00F1FF))
g11_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b23_n_0));
LUT5 #(
.INIT(32'h43FB947F))
g11_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b3_n_0));
LUT5 #(
.INIT(32'h80039840))
g11_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b4_n_0));
LUT5 #(
.INIT(32'h1C0061C0))
g11_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b5_n_0));
LUT4 #(
.INIT(16'h00C7))
g11_b6
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g11_b6_n_0));
LUT5 #(
.INIT(32'h1C000180))
g11_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b7_n_0));
LUT5 #(
.INIT(32'h1D0301A2))
g11_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b8_n_0));
LUT5 #(
.INIT(32'h0003B03E))
g11_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g11_b9_n_0));
LUT5 #(
.INIT(32'hD3CC303B))
g12_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'h30B0207E))
g12_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b1_n_0));
LUT5 #(
.INIT(32'h33801F8D))
g12_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b10_n_0));
LUT5 #(
.INIT(32'h33FBDFF7))
g12_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT5 #(
.INIT(32'h0B302001))
g12_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b12_n_0));
LUT5 #(
.INIT(32'h00D00031))
g12_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b13_n_0));
LUT5 #(
.INIT(32'h07E3C001))
g12_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT5 #(
.INIT(32'h0000000E))
g12_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b15_n_0));
LUT5 #(
.INIT(32'hE06FFFB8))
g12_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b16_n_0));
LUT5 #(
.INIT(32'hC3DFDFFA))
g12_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b17_n_0));
LUT5 #(
.INIT(32'h28E82F82))
g12_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b18_n_0));
LUT5 #(
.INIT(32'h0B103033))
g12_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b19_n_0));
LUT5 #(
.INIT(32'h3B5BC078))
g12_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b2_n_0));
LUT5 #(
.INIT(32'h03403FC5))
g12_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b20_n_0));
LUT5 #(
.INIT(32'h043BC00E))
g12_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b21_n_0));
LUT5 #(
.INIT(32'h04E0003F))
g12_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b22_n_0));
LUT4 #(
.INIT(16'h1D83))
g12_b23
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g12_b23_n_0));
LUT5 #(
.INIT(32'h37403FB9))
g12_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b3_n_0));
LUT5 #(
.INIT(32'h0C800039))
g12_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b4_n_0));
LUT5 #(
.INIT(32'h0413C006))
g12_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b5_n_0));
LUT5 #(
.INIT(32'h03E0000F))
g12_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b6_n_0));
LUT4 #(
.INIT(16'h0180))
g12_b7
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g12_b7_n_0));
LUT5 #(
.INIT(32'h0F53D030))
g12_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b8_n_0));
LUT5 #(
.INIT(32'hCB94003B))
g12_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g12_b9_n_0));
LUT5 #(
.INIT(32'hD00D3CC0))
g13_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT5 #(
.INIT(32'h00030B00))
g13_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b1_n_0));
LUT5 #(
.INIT(32'h30033800))
g13_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b10_n_0));
LUT5 #(
.INIT(32'hA7F33FBF))
g13_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'h0000B300))
g13_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b12_n_0));
LUT5 #(
.INIT(32'h80000D00))
g13_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b13_n_0));
LUT5 #(
.INIT(32'hC7F07E3F))
g13_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b14_n_0));
LUT5 #(
.INIT(32'h2FFE06FF))
g13_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b16_n_0));
LUT5 #(
.INIT(32'h5FFC3DFF))
g13_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b17_n_0));
LUT5 #(
.INIT(32'hB0028E80))
g13_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b18_n_0));
LUT5 #(
.INIT(32'h5800B100))
g13_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b19_n_0));
LUT5 #(
.INIT(32'h67F3B5BF))
g13_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b2_n_0));
LUT5 #(
.INIT(32'h10003400))
g13_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b20_n_0));
LUT5 #(
.INIT(32'hDFF043BF))
g13_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b21_n_0));
LUT5 #(
.INIT(32'hA0004E00))
g13_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b22_n_0));
LUT5 #(
.INIT(32'h7FF03F3F))
g13_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b23_n_0));
LUT5 #(
.INIT(32'h60037400))
g13_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b3_n_0));
LUT5 #(
.INIT(32'hC000C800))
g13_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b4_n_0));
LUT5 #(
.INIT(32'hC7F0413F))
g13_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b5_n_0));
LUT5 #(
.INIT(32'h80003E00))
g13_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b6_n_0));
LUT5 #(
.INIT(32'h07F0003F))
g13_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b7_n_0));
LUT5 #(
.INIT(32'h27F0F53F))
g13_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b8_n_0));
LUT5 #(
.INIT(32'hA00CB940))
g13_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g13_b9_n_0));
LUT5 #(
.INIT(32'h020D0020))
g14_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b0_n_0));
LUT5 #(
.INIT(32'h00730007))
g14_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b10_n_0));
LUT5 #(
.INIT(32'hFFFA7FFF))
g14_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b11_n_0));
LUT5 #(
.INIT(32'h03F8003F))
g14_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b13_n_0));
LUT5 #(
.INIT(32'hFFFC7FFF))
g14_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b14_n_0));
LUT5 #(
.INIT(32'hFD82FFD8))
g14_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b16_n_0));
LUT5 #(
.INIT(32'hFDC5FFDC))
g14_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b17_n_0));
LUT5 #(
.INIT(32'h024B0024))
g14_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b18_n_0));
LUT5 #(
.INIT(32'h00758007))
g14_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b19_n_0));
LUT5 #(
.INIT(32'hFF867FF8))
g14_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b2_n_0));
LUT5 #(
.INIT(32'h03C1003C))
g14_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b20_n_0));
LUT5 #(
.INIT(32'hFE3DFFE3))
g14_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b21_n_0));
LUT4 #(
.INIT(16'h0200))
g14_b22
(.I0(a[1]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g14_b22_n_0));
LUT5 #(
.INIT(32'hFC07FFC0))
g14_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b23_n_0));
LUT5 #(
.INIT(32'h01860018))
g14_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b3_n_0));
LUT5 #(
.INIT(32'h038C0038))
g14_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b4_n_0));
LUT5 #(
.INIT(32'hFF8C7FF8))
g14_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b5_n_0));
LUT5 #(
.INIT(32'h03880038))
g14_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b6_n_0));
LUT5 #(
.INIT(32'hFC707FC7))
g14_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b7_n_0));
LUT5 #(
.INIT(32'hFE027FE0))
g14_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b8_n_0));
LUT5 #(
.INIT(32'h01FA001F))
g14_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g14_b9_n_0));
LUT5 #(
.INIT(32'h43405434))
g15_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'h8E8068E8))
g15_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b1_n_0));
LUT5 #(
.INIT(32'hBB800BB8))
g15_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b10_n_0));
LUT5 #(
.INIT(32'h4DFFD4DF))
g15_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT5 #(
.INIT(32'h35802358))
g15_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b12_n_0));
LUT5 #(
.INIT(32'hBA005BA0))
g15_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b13_n_0));
LUT5 #(
.INIT(32'h3C7FC3C7))
g15_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b14_n_0));
LUT5 #(
.INIT(32'hB7FFFB7F))
g15_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b16_n_0));
LUT5 #(
.INIT(32'h017F9017))
g15_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b17_n_0));
LUT5 #(
.INIT(32'h84806848))
g15_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b18_n_0));
LUT5 #(
.INIT(32'h8B8048B8))
g15_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b19_n_0));
LUT5 #(
.INIT(32'h37FFF37F))
g15_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b2_n_0));
LUT5 #(
.INIT(32'hB0C02B0C))
g15_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b20_n_0));
LUT5 #(
.INIT(32'h4CFFF4CF))
g15_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b21_n_0));
LUT5 #(
.INIT(32'h03400034))
g15_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b22_n_0));
LUT5 #(
.INIT(32'h07BF807B))
g15_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b23_n_0));
LUT5 #(
.INIT(32'hB5807B58))
g15_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b3_n_0));
LUT5 #(
.INIT(32'h85803858))
g15_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b4_n_0));
LUT5 #(
.INIT(32'hC23FDC23))
g15_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b5_n_0));
LUT5 #(
.INIT(32'h04404044))
g15_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b6_n_0));
LUT5 #(
.INIT(32'hF83FBF83))
g15_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b7_n_0));
LUT5 #(
.INIT(32'h303F8303))
g15_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b8_n_0));
LUT5 #(
.INIT(32'hCEC01CEC))
g15_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g15_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT5 #(
.INIT(32'h806F7805))
g16_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b0_n_0));
LUT5 #(
.INIT(32'hC0B05C06))
g16_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h40E08400))
g16_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b10_n_0));
LUT5 #(
.INIT(32'h7F7C17FD))
g16_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b11_n_0));
LUT5 #(
.INIT(32'h40E0B402))
g16_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT5 #(
.INIT(32'h8068C805))
g16_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b13_n_0));
LUT5 #(
.INIT(32'h7F50B7FC))
g16_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h803F7803))
g16_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b15_n_0));
LUT5 #(
.INIT(32'h7F1897FF))
g16_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b16_n_0));
LUT5 #(
.INIT(32'h7F2B37F9))
g16_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'h80130806))
g16_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h80A32804))
g16_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b19_n_0));
LUT5 #(
.INIT(32'hBFA8EBFF))
g16_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b2_n_0));
LUT5 #(
.INIT(32'h40731402))
g16_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b20_n_0));
LUT5 #(
.INIT(32'h7F7CF7FF))
g16_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT4 #(
.INIT(16'h8060))
g16_b22
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g16_b22_n_0));
LUT5 #(
.INIT(32'hBF007BF8))
g16_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT5 #(
.INIT(32'h407B9407))
g16_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT5 #(
.INIT(32'h409B3403))
g16_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'hBF0C4BFD))
g16_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b5_n_0));
LUT5 #(
.INIT(32'h40303404))
g16_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b6_n_0));
LUT5 #(
.INIT(32'hBF7FFBFB))
g16_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h3F40A3F8))
g16_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b8_n_0));
LUT5 #(
.INIT(32'hC02FAC01))
g16_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g16_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h57AC06F7))
g17_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b0_n_0));
LUT5 #(
.INIT(32'h13380B05))
g17_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT5 #(
.INIT(32'h1F900E08))
g17_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b10_n_0));
LUT5 #(
.INIT(32'h307BF7C1))
g17_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b11_n_0));
LUT5 #(
.INIT(32'hDF680E0B))
g17_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT5 #(
.INIT(32'h77FC068C))
g17_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b13_n_0));
LUT5 #(
.INIT(32'h4797F50B))
g17_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT5 #(
.INIT(32'h383803F7))
g17_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b15_n_0));
LUT5 #(
.INIT(32'hACF3F189))
g17_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b16_n_0));
LUT5 #(
.INIT(32'hC473F2B3))
g17_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT5 #(
.INIT(32'h8C900130))
g17_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'h4CF00A32))
g17_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b19_n_0));
LUT5 #(
.INIT(32'hF46FFA8E))
g17_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b2_n_0));
LUT5 #(
.INIT(32'h33240731))
g17_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b20_n_0));
LUT5 #(
.INIT(32'h7077F7CF))
g17_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'h001C0003))
g17_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b22_n_0));
LUT5 #(
.INIT(32'h003BF007))
g17_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h7FEC07B9))
g17_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'hE0FC09B3))
g17_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h68FBF0C4))
g17_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b5_n_0));
LUT5 #(
.INIT(32'h50940303))
g17_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b6_n_0));
LUT5 #(
.INIT(32'h3F3BF7FF))
g17_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h6C13F40A))
g17_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b8_n_0));
LUT5 #(
.INIT(32'h843C02FA))
g17_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g17_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'h18057AC0))
g18_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b0_n_0));
LUT5 #(
.INIT(32'hA4013380))
g18_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT5 #(
.INIT(32'hB401F900))
g18_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b10_n_0));
LUT5 #(
.INIT(32'h2FF307BF))
g18_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b11_n_0));
LUT5 #(
.INIT(32'h9C0DF680))
g18_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT5 #(
.INIT(32'h50077FC0))
g18_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b13_n_0));
LUT5 #(
.INIT(32'h87F4797F))
g18_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT5 #(
.INIT(32'h38038380))
g18_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b15_n_0));
LUT5 #(
.INIT(32'hEFFACF3F))
g18_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b16_n_0));
LUT5 #(
.INIT(32'h07FC473F))
g18_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'h7008C900))
g18_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'hE804CF00))
g18_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b19_n_0));
LUT5 #(
.INIT(32'h8BFF46FF))
g18_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b2_n_0));
LUT5 #(
.INIT(32'h64033240))
g18_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b20_n_0));
LUT5 #(
.INIT(32'h0FF7077F))
g18_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT5 #(
.INIT(32'h140001C0))
g18_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b22_n_0));
LUT5 #(
.INIT(32'h3BF003BF))
g18_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'h1C07FEC0))
g18_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'h3C0E0FC0))
g18_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'hD3F68FBF))
g18_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b5_n_0));
LUT5 #(
.INIT(32'h84050940))
g18_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b6_n_0));
LUT5 #(
.INIT(32'h3BF3F3BF))
g18_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT5 #(
.INIT(32'hD3F6C13F))
g18_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b8_n_0));
LUT5 #(
.INIT(32'h2C0843C0))
g18_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g18_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT5 #(
.INIT(32'h03F1803F))
g19_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b0_n_0));
LUT5 #(
.INIT(32'h010A4010))
g19_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h070B4070))
g19_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b10_n_0));
LUT5 #(
.INIT(32'hFE02FFE0))
g19_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b11_n_0));
LUT5 #(
.INIT(32'h0709C070))
g19_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'h01F5001F))
g19_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b13_n_0));
LUT5 #(
.INIT(32'hFBF87FBF))
g19_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'h00038000))
g19_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b15_n_0));
LUT5 #(
.INIT(32'hF8FEFF8F))
g19_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b16_n_0));
LUT5 #(
.INIT(32'hFA007FA0))
g19_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'h02070020))
g19_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'h06FE806F))
g19_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b19_n_0));
LUT5 #(
.INIT(32'hFCF8BFCF))
g19_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b2_n_0));
LUT5 #(
.INIT(32'h01064010))
g19_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b20_n_0));
LUT5 #(
.INIT(32'hF800FF80))
g19_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT5 #(
.INIT(32'h00014000))
g19_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b22_n_0));
LUT5 #(
.INIT(32'hF803BF80))
g19_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h0101C010))
g19_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h02F3C02F))
g19_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b4_n_0));
LUT5 #(
.INIT(32'h02F8402F))
g19_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b6_n_0));
LUT5 #(
.INIT(32'hF903BF90))
g19_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'hFEFD3FEF))
g19_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b8_n_0));
LUT5 #(
.INIT(32'h0602C060))
g19_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g19_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00980000))
g1_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00D00000))
g1_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00280003))
g1_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'hFF701FF0))
g1_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'h0401))
g1_b12
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g1_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h00480000))
g1_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b13_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'hFE001FF0))
g1_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'h0400))
g1_b15
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g1_b15_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'hFFC49FF0))
g1_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT3 #(
.INIT(8'hEF))
g1_b17
(.I0(a[2]),
.I1(a[4]),
.I2(a[5]),
.O(g1_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h017F600C))
g1_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h01B7600C))
g1_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b19_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hFE001FF3))
g1_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h0034E00C))
g1_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hFF879FF3))
g1_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'h00780000))
g1_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b22_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hFEFF1FF0))
g1_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h01200000))
g1_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'h0001))
g1_b4
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g1_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hFE481FF0))
g1_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b5_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hFE301FF0))
g1_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b7_n_0));
LUT5 #(
.INIT(32'hFEB81FF3))
g1_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b8_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h00B80003))
g1_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g1_b9_n_0));
LUT5 #(
.INIT(32'h7C8037C8))
g20_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b1_n_0));
LUT3 #(
.INIT(8'hBD))
g20_b11
(.I0(a[3]),
.I1(a[4]),
.I2(a[5]),
.O(g20_b11_n_0));
LUT4 #(
.INIT(16'hD074))
g20_b12
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g20_b12_n_0));
LUT5 #(
.INIT(32'h07FFC07F))
g20_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b14_n_0));
LUT5 #(
.INIT(32'h0CFFD0CF))
g20_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b16_n_0));
LUT5 #(
.INIT(32'h047FD047))
g20_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'hE078))
g20_b18
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g20_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT5 #(
.INIT(32'h77802778))
g20_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b19_n_0));
LUT5 #(
.INIT(32'h7C7FE7C7))
g20_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b2_n_0));
LUT5 #(
.INIT(32'hF0803F08))
g20_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b20_n_0));
LUT4 #(
.INIT(16'h2F8B))
g20_b21
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g20_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT5 #(
.INIT(32'h04800048))
g20_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b22_n_0));
LUT5 #(
.INIT(32'h037FC037))
g20_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT5 #(
.INIT(32'hFB003FB0))
g20_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT5 #(
.INIT(32'h047FC047))
g20_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b5_n_0));
LUT5 #(
.INIT(32'h03800038))
g20_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b6_n_0));
LUT5 #(
.INIT(32'h007FC007))
g20_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT5 #(
.INIT(32'hFB7FFFB7))
g20_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b8_n_0));
LUT5 #(
.INIT(32'h73803738))
g20_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g20_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT5 #(
.INIT(32'h00072003))
g21_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b0_n_0));
LUT5 #(
.INIT(32'h006F8003))
g21_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT5 #(
.INIT(32'h00585002))
g21_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b10_n_0));
LUT5 #(
.INIT(32'h7F9007FF))
g21_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b11_n_0));
LUT5 #(
.INIT(32'h80700803))
g21_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT5 #(
.INIT(32'h0020E000))
g21_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b13_n_0));
LUT5 #(
.INIT(32'h7FB8F7FC))
g21_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b14_n_0));
LUT5 #(
.INIT(32'hFFF7CFFD))
g21_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b16_n_0));
LUT5 #(
.INIT(32'hFF873FFD))
g21_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT5 #(
.INIT(32'h8077C803))
g21_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT5 #(
.INIT(32'h80477802))
g21_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b19_n_0));
LUT5 #(
.INIT(32'hFF974FFE))
g21_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b2_n_0));
LUT5 #(
.INIT(32'h805F1803))
g21_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b20_n_0));
LUT5 #(
.INIT(32'h7FAFF7FC))
g21_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT5 #(
.INIT(32'h00081000))
g21_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b22_n_0));
LUT5 #(
.INIT(32'h7FB7E7FC))
g21_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT5 #(
.INIT(32'h8038E803))
g21_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT5 #(
.INIT(32'h00681003))
g21_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT5 #(
.INIT(32'h7F8F17FC))
g21_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b5_n_0));
LUT5 #(
.INIT(32'h0037E000))
g21_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b6_n_0));
LUT5 #(
.INIT(32'h7F8007FC))
g21_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT5 #(
.INIT(32'hFFF8AFFF))
g21_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b8_n_0));
LUT5 #(
.INIT(32'h001FE003))
g21_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g21_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT5 #(
.INIT(32'h23100072))
g22_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b0_n_0));
LUT5 #(
.INIT(32'h1C8806F8))
g22_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT5 #(
.INIT(32'h64600585))
g22_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b10_n_0));
LUT5 #(
.INIT(32'hFC6FF900))
g22_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b11_n_0));
LUT5 #(
.INIT(32'h04800700))
g22_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT5 #(
.INIT(32'h0300020E))
g22_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b13_n_0));
LUT5 #(
.INIT(32'hB7F7FB8F))
g22_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT5 #(
.INIT(32'h00000070))
g22_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b15_n_0));
LUT5 #(
.INIT(32'hC0F7FF7C))
g22_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b16_n_0));
LUT5 #(
.INIT(32'hEF0FF873))
g22_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT5 #(
.INIT(32'h4470077C))
g22_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT5 #(
.INIT(32'h03600477))
g22_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b19_n_0));
LUT5 #(
.INIT(32'h981FF974))
g22_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b2_n_0));
LUT5 #(
.INIT(32'h4C9805F1))
g22_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b20_n_0));
LUT5 #(
.INIT(32'h8317FAFF))
g22_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT5 #(
.INIT(32'h00100081))
g22_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b22_n_0));
LUT5 #(
.INIT(32'hB7E7FB7E))
g22_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT5 #(
.INIT(32'h63F0038E))
g22_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT5 #(
.INIT(32'h30E00681))
g22_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT5 #(
.INIT(32'hB0F7F8F1))
g22_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b5_n_0));
LUT5 #(
.INIT(32'h0700037E))
g22_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b6_n_0));
LUT5 #(
.INIT(32'h8007F800))
g22_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT5 #(
.INIT(32'h8367FF8A))
g22_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b8_n_0));
LUT5 #(
.INIT(32'h03E001FE))
g22_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g22_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT5 #(
.INIT(32'hF0023100))
g23_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b0_n_0));
LUT5 #(
.INIT(32'hF801C880))
g23_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hF0064600))
g23_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b10_n_0));
LUT5 #(
.INIT(32'hFFFFC6FF))
g23_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b11_n_0));
LUT5 #(
.INIT(32'hF0004800))
g23_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'h0040))
g23_b13
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g23_b13_n_0));
LUT5 #(
.INIT(32'h07FB7F7F))
g23_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b14_n_0));
LUT5 #(
.INIT(32'hF7FC0F7F))
g23_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b16_n_0));
LUT5 #(
.INIT(32'hFFFEF0FF))
g23_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'h00044700))
g23_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'h00003600))
g23_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b19_n_0));
LUT5 #(
.INIT(32'hFFF981FF))
g23_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b2_n_0));
LUT5 #(
.INIT(32'hF804C980))
g23_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b20_n_0));
LUT5 #(
.INIT(32'hF7F8317F))
g23_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'h00000100))
g23_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b22_n_0));
LUT5 #(
.INIT(32'h07FB7E7F))
g23_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT5 #(
.INIT(32'h00063F00))
g23_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT5 #(
.INIT(32'hF0030E00))
g23_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'h07FB0F7F))
g23_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b5_n_0));
LUT5 #(
.INIT(32'h00007000))
g23_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b6_n_0));
LUT5 #(
.INIT(32'h07F8007F))
g23_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b7_n_0));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT5 #(
.INIT(32'hF7F8367F))
g23_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b8_n_0));
LUT5 #(
.INIT(32'hF0003E00))
g23_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g23_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT5 #(
.INIT(32'h03FF803F))
g24_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT5 #(
.INIT(32'h077F0077))
g24_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT5 #(
.INIT(32'h037F0037))
g24_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'hFF7F7FF7))
g24_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h04000040))
g24_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT5 #(
.INIT(32'hFBFFFFBF))
g24_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT5 #(
.INIT(32'h07FF807F))
g24_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT5 #(
.INIT(32'hFB7F7FB7))
g24_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'hF8007F80))
g24_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g24_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h2F000980))
g2_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h7F000D00))
g2_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h10000280))
g2_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT5 #(
.INIT(32'hF007F701))
g2_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h84000300))
g2_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b12_n_0));
LUT5 #(
.INIT(32'h10000480))
g2_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b13_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT5 #(
.INIT(32'h2007E001))
g2_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b14_n_0));
LUT5 #(
.INIT(32'h78000300))
g2_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b15_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h285FFC49))
g2_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h44DFFCCF))
g2_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'h076017F6))
g2_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'hC8681B76))
g2_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b19_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'hFC07E001))
g2_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'hCB58034E))
g2_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT5 #(
.INIT(32'hB077F879))
g2_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'h7F800780))
g2_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b22_n_0));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT5 #(
.INIT(32'hFFE7EFF1))
g2_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'h0C001200))
g2_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT3 #(
.INIT(8'h80))
g2_b4
(.I0(a[3]),
.I1(a[4]),
.I2(a[5]),
.O(g2_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h6807E481))
g2_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b5_n_0));
LUT5 #(
.INIT(32'h48000000))
g2_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b6_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h3007E301))
g2_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b7_n_0));
LUT5 #(
.INIT(32'h7B87EB81))
g2_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b8_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h1F000B80))
g2_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g2_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT5 #(
.INIT(32'hA002F000))
g3_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'h2007F000))
g3_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h80010000))
g3_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h03FF007F))
g3_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00084000))
g3_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b12_n_0));
LUT5 #(
.INIT(32'h00110001))
g3_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b13_n_0));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h03E2007E))
g3_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b14_n_0));
LUT5 #(
.INIT(32'h00078000))
g3_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b15_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h1FF285FF))
g3_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'hDBF44DFF))
g3_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'hA4007600))
g3_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h880C8680))
g3_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b19_n_0));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT5 #(
.INIT(32'h03EFC07E))
g3_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hA41CB581))
g3_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h8FFB077F))
g3_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'h7017F801))
g3_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b22_n_0));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'hFBEFFE7E))
g3_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'h0010C001))
g3_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT3 #(
.INIT(8'h10))
g3_b4
(.I0(a[3]),
.I1(a[4]),
.I2(a[5]),
.O(g3_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'h03F6807F))
g3_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b5_n_0));
LUT5 #(
.INIT(32'h00048000))
g3_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b6_n_0));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT5 #(
.INIT(32'h03E3007E))
g3_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b7_n_0));
LUT5 #(
.INIT(32'h63F7B87F))
g3_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b8_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h2011F001))
g3_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g3_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h677A0677))
g4_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'h16B2016B))
g4_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h0EF800EF))
g4_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h93003930))
g4_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'h07B0007B))
g4_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'h80003800))
g4_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'hF6C1FF6C))
g4_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hFB0DBFB0))
g4_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h17CA417C))
g4_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'h1FF881FF))
g4_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b19_n_0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h99703997))
g4_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h0F8A40F8))
g4_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h8078F807))
g4_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h00070000))
g4_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b22_n_0));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h803FB803))
g4_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h02300023))
g4_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h07800078))
g4_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b4_n_0));
LUT5 #(
.INIT(32'h9A8639A8))
g4_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b8_n_0));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h64420644))
g4_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g4_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT5 #(
.INIT(32'h032F8032))
g5_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT5 #(
.INIT(32'h87E0787E))
g5_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'h03A0003A))
g5_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'h70505705))
g5_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'h02000020))
g5_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b12_n_0));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT5 #(
.INIT(32'h00100001))
g5_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'h88DFF88D))
g5_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT5 #(
.INIT(32'h79DFD79D))
g5_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT5 #(
.INIT(32'hF4C07F4C))
g5_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'h0EC050EC))
g5_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b19_n_0));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT5 #(
.INIT(32'h02505025))
g5_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT5 #(
.INIT(32'h48200482))
g5_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'h36700367))
g5_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'h01800018))
g5_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b22_n_0));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT5 #(
.INIT(32'h03D0003D))
g5_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h72000720))
g5_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b3_n_0));
LUT5 #(
.INIT(32'hF4307F43))
g5_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b8_n_0));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'hF40FAF40))
g5_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g5_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hC0331CF8))
g6_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'h002FD007))
g6_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h20002200))
g6_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'hFFF85F05))
g6_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT5 #(
.INIT(32'h006C8000))
g6_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b12_n_0));
LUT4 #(
.INIT(16'h8020))
g6_b13
(.I0(a[1]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g6_b13_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'h5FD70500))
g6_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT5 #(
.INIT(32'h5FE715FF))
g6_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'h7FA367FD))
g6_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT5 #(
.INIT(32'h001C8007))
g6_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'h803C3805))
g6_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b19_n_0));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h3F93F305))
g6_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT5 #(
.INIT(32'h00547000))
g6_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hFFB89F00))
g6_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'h40100400))
g6_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b22_n_0));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT5 #(
.INIT(32'hFFC70F00))
g6_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'hE0078E00))
g6_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hE03C0E00))
g6_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT5 #(
.INIT(32'h5F970500))
g6_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b5_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'h00400000))
g6_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b6_n_0));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT5 #(
.INIT(32'h1F800100))
g6_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b7_n_0));
LUT5 #(
.INIT(32'h3F8FB307))
g6_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b8_n_0));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h407094FA))
g6_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g6_b9_n_0));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT5 #(
.INIT(32'hBB750331))
g7_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'hA4C702FD))
g7_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b1_n_0));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT5 #(
.INIT(32'hAC280002))
g7_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b10_n_0));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT5 #(
.INIT(32'h5BBFFF85))
g7_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h37D406C8))
g7_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b12_n_0));
LUT5 #(
.INIT(32'h2F5A0000))
g7_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b13_n_0));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h178BFD70))
g7_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT5 #(
.INIT(32'hC0040000))
g7_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b15_n_0));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT5 #(
.INIT(32'h5C7AFE71))
g7_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b16_n_0));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT5 #(
.INIT(32'h8CF2FA36))
g7_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b17_n_0));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT5 #(
.INIT(32'h98DD01C8))
g7_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b18_n_0));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT5 #(
.INIT(32'h88AA03C3))
g7_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b19_n_0));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'hE48CF93F))
g7_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b2_n_0));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT5 #(
.INIT(32'h64350547))
g7_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b20_n_0));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT5 #(
.INIT(32'h13D4FB89))
g7_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b21_n_0));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT5 #(
.INIT(32'hEF5E0100))
g7_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b22_n_0));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT5 #(
.INIT(32'hD78FFC70))
g7_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b23_n_0));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'h83BF0078))
g7_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b3_n_0));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'h878103C0))
g7_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b4_n_0));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'h68D5F970))
g7_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b5_n_0));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'hD70E0400))
g7_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b6_n_0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h0000F800))
g7_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b7_n_0));
LUT5 #(
.INIT(32'h1FF1F8FB))
g7_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b8_n_0));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT5 #(
.INIT(32'h50010709))
g7_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g7_b9_n_0));
LUT5 #(
.INIT(32'h4B2BB752))
g8_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT5 #(
.INIT(32'h0E2A4C72))
g8_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b1_n_0));
LUT5 #(
.INIT(32'h503AC283))
g8_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b10_n_0));
LUT5 #(
.INIT(32'h3AD5BBFD))
g8_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT5 #(
.INIT(32'hC4137D41))
g8_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b12_n_0));
LUT5 #(
.INIT(32'h0212F5A1))
g8_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b13_n_0));
LUT5 #(
.INIT(32'h93D178BD))
g8_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT5 #(
.INIT(32'h0C2C0042))
g8_b15
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b15_n_0));
LUT5 #(
.INIT(32'h17C5C7AC))
g8_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b16_n_0));
LUT5 #(
.INIT(32'h79F8CF2F))
g8_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b17_n_0));
LUT5 #(
.INIT(32'hFE398DD3))
g8_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b18_n_0));
LUT5 #(
.INIT(32'h48288AA2))
g8_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b19_n_0));
LUT5 #(
.INIT(32'hC1FE48CF))
g8_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b2_n_0));
LUT5 #(
.INIT(32'h34064350))
g8_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b20_n_0));
LUT5 #(
.INIT(32'hCCC13D4C))
g8_b21
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b21_n_0));
LUT5 #(
.INIT(32'h0E3EF5E3))
g8_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b22_n_0));
LUT5 #(
.INIT(32'h9FFD78FF))
g8_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b23_n_0));
LUT5 #(
.INIT(32'h76383BF3))
g8_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b3_n_0));
LUT5 #(
.INIT(32'h91387813))
g8_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b4_n_0));
LUT5 #(
.INIT(32'h9DC68D5C))
g8_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b5_n_0));
LUT5 #(
.INIT(32'h0E3D70E3))
g8_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b6_n_0));
LUT4 #(
.INIT(16'h0802))
g8_b7
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g8_b7_n_0));
LUT5 #(
.INIT(32'hA5D1FF1D))
g8_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b8_n_0));
LUT5 #(
.INIT(32'hFD150011))
g8_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g8_b9_n_0));
LUT5 #(
.INIT(32'h4234B423))
g9_b0
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b0_n_0));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT5 #(
.INIT(32'h3C00E3C0))
g9_b1
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b1_n_0));
LUT5 #(
.INIT(32'h04C5004C))
g9_b10
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b10_n_0));
LUT5 #(
.INIT(32'hDC03ADC0))
g9_b11
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b11_n_0));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT5 #(
.INIT(32'h410C4410))
g9_b12
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b12_n_0));
LUT5 #(
.INIT(32'h7E0027E0))
g9_b13
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b13_n_0));
LUT5 #(
.INIT(32'hC0093C00))
g9_b14
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b14_n_0));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'h7C9F))
g9_b15
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g9_b15_n_0));
LUT5 #(
.INIT(32'hA5317A53))
g9_b16
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b16_n_0));
LUT5 #(
.INIT(32'h9B3799B3))
g9_b17
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b17_n_0));
LUT5 #(
.INIT(32'h04FFE04F))
g9_b18
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b18_n_0));
LUT5 #(
.INIT(32'h21C4821C))
g9_b19
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b19_n_0));
LUT5 #(
.INIT(32'hDBFC1DBF))
g9_b2
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b2_n_0));
LUT5 #(
.INIT(32'h5CC345CC))
g9_b20
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b20_n_0));
LUT4 #(
.INIT(16'hF6BD))
g9_b21
(.I0(a[2]),
.I1(a[3]),
.I2(a[4]),
.I3(a[5]),
.O(g9_b21_n_0));
LUT5 #(
.INIT(32'h3FF0E3FF))
g9_b22
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b22_n_0));
LUT5 #(
.INIT(32'hFFF9FFFF))
g9_b23
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b23_n_0));
LUT5 #(
.INIT(32'h7B3767B3))
g9_b3
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b3_n_0));
LUT5 #(
.INIT(32'h7A3917A3))
g9_b4
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b4_n_0));
LUT5 #(
.INIT(32'hBBC9DBBC))
g9_b5
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b5_n_0));
LUT5 #(
.INIT(32'h7BF0E7BF))
g9_b6
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b6_n_0));
LUT5 #(
.INIT(32'h84000840))
g9_b7
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b7_n_0));
LUT5 #(
.INIT(32'hF80A5F80))
g9_b8
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b8_n_0));
LUT5 #(
.INIT(32'h61FFD61F))
g9_b9
(.I0(a[1]),
.I1(a[2]),
.I2(a[3]),
.I3(a[4]),
.I4(a[5]),
.O(g9_b9_n_0));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0
(.I0(\spo[12]_INST_0_i_1_n_0 ),
.I1(\spo[0]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[0]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[0]_INST_0_i_3_n_0 ),
.O(spo[0]));
MUXF7 \spo[0]_INST_0_i_1
(.I0(\spo[0]_INST_0_i_4_n_0 ),
.I1(\spo[0]_INST_0_i_5_n_0 ),
.O(\spo[0]_INST_0_i_1_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0_i_10
(.I0(g3_b0_n_0),
.I1(g2_b0_n_0),
.I2(a[7]),
.I3(g1_b0_n_0),
.I4(a[6]),
.I5(g0_b1_n_0),
.O(\spo[0]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0_i_11
(.I0(g7_b0_n_0),
.I1(g6_b0_n_0),
.I2(a[7]),
.I3(g5_b0_n_0),
.I4(a[6]),
.I5(g4_b0_n_0),
.O(\spo[0]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0_i_2
(.I0(\spo[0]_INST_0_i_6_n_0 ),
.I1(\spo[0]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[0]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[0]_INST_0_i_9_n_0 ),
.O(\spo[0]_INST_0_i_2_n_0 ));
MUXF7 \spo[0]_INST_0_i_3
(.I0(\spo[0]_INST_0_i_10_n_0 ),
.I1(\spo[0]_INST_0_i_11_n_0 ),
.O(\spo[0]_INST_0_i_3_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0_i_4
(.I0(g19_b0_n_0),
.I1(g18_b0_n_0),
.I2(a[7]),
.I3(g17_b0_n_0),
.I4(a[6]),
.I5(g16_b0_n_0),
.O(\spo[0]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[0]_INST_0_i_5
(.I0(g23_b0_n_0),
.I1(g22_b0_n_0),
.I2(a[7]),
.I3(g21_b0_n_0),
.I4(a[6]),
.I5(g20_b3_n_0),
.O(\spo[0]_INST_0_i_5_n_0 ));
MUXF7 \spo[0]_INST_0_i_6
(.I0(g14_b0_n_0),
.I1(g15_b0_n_0),
.O(\spo[0]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[0]_INST_0_i_7
(.I0(g12_b0_n_0),
.I1(g13_b0_n_0),
.O(\spo[0]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[0]_INST_0_i_8
(.I0(g10_b0_n_0),
.I1(g11_b0_n_0),
.O(\spo[0]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[0]_INST_0_i_9
(.I0(g8_b0_n_0),
.I1(g9_b0_n_0),
.O(\spo[0]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[10]_INST_0
(.I0(\spo[10]_INST_0_i_1_n_0 ),
.I1(\spo[10]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[10]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[10]_INST_0_i_4_n_0 ),
.O(spo[10]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT4 #(
.INIT(16'h0004))
\spo[10]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b10_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[10]_INST_0_i_1_n_0 ));
MUXF7 \spo[10]_INST_0_i_10
(.I0(g8_b10_n_0),
.I1(g9_b10_n_0),
.O(\spo[10]_INST_0_i_10_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[10]_INST_0_i_11
(.I0(g3_b10_n_0),
.I1(g2_b10_n_0),
.I2(a[7]),
.I3(g1_b10_n_0),
.I4(a[6]),
.I5(g23_b13_n_0),
.O(\spo[10]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[10]_INST_0_i_12
(.I0(g7_b10_n_0),
.I1(g6_b10_n_0),
.I2(a[7]),
.I3(g5_b10_n_0),
.I4(a[6]),
.I5(g4_b10_n_0),
.O(\spo[10]_INST_0_i_12_n_0 ));
MUXF7 \spo[10]_INST_0_i_2
(.I0(\spo[10]_INST_0_i_5_n_0 ),
.I1(\spo[10]_INST_0_i_6_n_0 ),
.O(\spo[10]_INST_0_i_2_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[10]_INST_0_i_3
(.I0(\spo[10]_INST_0_i_7_n_0 ),
.I1(\spo[10]_INST_0_i_8_n_0 ),
.I2(a[8]),
.I3(\spo[10]_INST_0_i_9_n_0 ),
.I4(a[7]),
.I5(\spo[10]_INST_0_i_10_n_0 ),
.O(\spo[10]_INST_0_i_3_n_0 ));
MUXF7 \spo[10]_INST_0_i_4
(.I0(\spo[10]_INST_0_i_11_n_0 ),
.I1(\spo[10]_INST_0_i_12_n_0 ),
.O(\spo[10]_INST_0_i_4_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[10]_INST_0_i_5
(.I0(g19_b10_n_0),
.I1(g18_b10_n_0),
.I2(a[7]),
.I3(g17_b10_n_0),
.I4(a[6]),
.I5(g16_b10_n_0),
.O(\spo[10]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[10]_INST_0_i_6
(.I0(g23_b10_n_0),
.I1(g22_b10_n_0),
.I2(a[7]),
.I3(g21_b10_n_0),
.I4(a[6]),
.I5(g20_b19_n_0),
.O(\spo[10]_INST_0_i_6_n_0 ));
MUXF7 \spo[10]_INST_0_i_7
(.I0(g14_b10_n_0),
.I1(g15_b10_n_0),
.O(\spo[10]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[10]_INST_0_i_8
(.I0(g12_b10_n_0),
.I1(g13_b10_n_0),
.O(\spo[10]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[10]_INST_0_i_9
(.I0(g10_b10_n_0),
.I1(g11_b10_n_0),
.O(\spo[10]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[11]_INST_0
(.I0(\spo[17]_INST_0_i_1_n_0 ),
.I1(\spo[11]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[11]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[11]_INST_0_i_3_n_0 ),
.O(spo[11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[11]_INST_0_i_1
(.I0(\spo[11]_INST_0_i_4_n_0 ),
.I1(\spo[11]_INST_0_i_5_n_0 ),
.I2(a[8]),
.I3(\spo[11]_INST_0_i_6_n_0 ),
.I4(a[7]),
.I5(\spo[11]_INST_0_i_7_n_0 ),
.O(\spo[11]_INST_0_i_1_n_0 ));
MUXF7 \spo[11]_INST_0_i_10
(.I0(g10_b11_n_0),
.I1(g11_b11_n_0),
.O(\spo[11]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[11]_INST_0_i_11
(.I0(g8_b11_n_0),
.I1(g9_b11_n_0),
.O(\spo[11]_INST_0_i_11_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[11]_INST_0_i_12
(.I0(g3_b11_n_0),
.I1(g2_b11_n_0),
.I2(a[7]),
.I3(g1_b11_n_0),
.I4(a[6]),
.I5(g0_b23_n_0),
.O(\spo[11]_INST_0_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[11]_INST_0_i_13
(.I0(g7_b11_n_0),
.I1(g6_b11_n_0),
.I2(a[7]),
.I3(g5_b11_n_0),
.I4(a[6]),
.I5(g4_b11_n_0),
.O(\spo[11]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[11]_INST_0_i_2
(.I0(\spo[11]_INST_0_i_8_n_0 ),
.I1(\spo[11]_INST_0_i_9_n_0 ),
.I2(a[8]),
.I3(\spo[11]_INST_0_i_10_n_0 ),
.I4(a[7]),
.I5(\spo[11]_INST_0_i_11_n_0 ),
.O(\spo[11]_INST_0_i_2_n_0 ));
MUXF7 \spo[11]_INST_0_i_3
(.I0(\spo[11]_INST_0_i_12_n_0 ),
.I1(\spo[11]_INST_0_i_13_n_0 ),
.O(\spo[11]_INST_0_i_3_n_0 ),
.S(a[8]));
MUXF7 \spo[11]_INST_0_i_4
(.I0(g22_b11_n_0),
.I1(g23_b11_n_0),
.O(\spo[11]_INST_0_i_4_n_0 ),
.S(a[6]));
MUXF7 \spo[11]_INST_0_i_5
(.I0(g20_b11_n_0),
.I1(g21_b11_n_0),
.O(\spo[11]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[11]_INST_0_i_6
(.I0(g18_b11_n_0),
.I1(g19_b11_n_0),
.O(\spo[11]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[11]_INST_0_i_7
(.I0(g16_b11_n_0),
.I1(g17_b11_n_0),
.O(\spo[11]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[11]_INST_0_i_8
(.I0(g14_b11_n_0),
.I1(g15_b11_n_0),
.O(\spo[11]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[11]_INST_0_i_9
(.I0(g12_b11_n_0),
.I1(g13_b11_n_0),
.O(\spo[11]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[12]_INST_0
(.I0(\spo[12]_INST_0_i_1_n_0 ),
.I1(\spo[12]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[12]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[12]_INST_0_i_4_n_0 ),
.O(spo[12]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT4 #(
.INIT(16'h0004))
\spo[12]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b12_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[12]_INST_0_i_1_n_0 ));
LUT5 #(
.INIT(32'hB833B800))
\spo[12]_INST_0_i_10
(.I0(g15_b12_n_0),
.I1(a[7]),
.I2(g13_b12_n_0),
.I3(a[6]),
.I4(g12_b12_n_0),
.O(\spo[12]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[12]_INST_0_i_11
(.I0(g3_b12_n_0),
.I1(g2_b12_n_0),
.I2(a[7]),
.I3(g1_b12_n_0),
.I4(a[6]),
.I5(g23_b13_n_0),
.O(\spo[12]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[12]_INST_0_i_12
(.I0(g7_b12_n_0),
.I1(g6_b12_n_0),
.I2(a[7]),
.I3(g5_b12_n_0),
.I4(a[6]),
.I5(g4_b12_n_0),
.O(\spo[12]_INST_0_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[12]_INST_0_i_2
(.I0(\spo[12]_INST_0_i_5_n_0 ),
.I1(\spo[12]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[12]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[12]_INST_0_i_8_n_0 ),
.O(\spo[12]_INST_0_i_2_n_0 ));
MUXF7 \spo[12]_INST_0_i_3
(.I0(\spo[12]_INST_0_i_9_n_0 ),
.I1(\spo[12]_INST_0_i_10_n_0 ),
.O(\spo[12]_INST_0_i_3_n_0 ),
.S(a[8]));
MUXF7 \spo[12]_INST_0_i_4
(.I0(\spo[12]_INST_0_i_11_n_0 ),
.I1(\spo[12]_INST_0_i_12_n_0 ),
.O(\spo[12]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[12]_INST_0_i_5
(.I0(g22_b12_n_0),
.I1(g23_b12_n_0),
.O(\spo[12]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[12]_INST_0_i_6
(.I0(g20_b12_n_0),
.I1(g21_b12_n_0),
.O(\spo[12]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[12]_INST_0_i_7
(.I0(g18_b12_n_0),
.I1(g19_b12_n_0),
.O(\spo[12]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[12]_INST_0_i_8
(.I0(g16_b12_n_0),
.I1(g17_b12_n_0),
.O(\spo[12]_INST_0_i_8_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[12]_INST_0_i_9
(.I0(g11_b12_n_0),
.I1(g10_b12_n_0),
.I2(a[7]),
.I3(g9_b12_n_0),
.I4(a[6]),
.I5(g8_b12_n_0),
.O(\spo[12]_INST_0_i_9_n_0 ));
LUT5 #(
.INIT(32'h30BB3088))
\spo[13]_INST_0
(.I0(\spo[13]_INST_0_i_1_n_0 ),
.I1(a[10]),
.I2(\spo[13]_INST_0_i_2_n_0 ),
.I3(a[9]),
.I4(\spo[13]_INST_0_i_3_n_0 ),
.O(spo[13]));
MUXF7 \spo[13]_INST_0_i_1
(.I0(\spo[13]_INST_0_i_4_n_0 ),
.I1(\spo[13]_INST_0_i_5_n_0 ),
.O(\spo[13]_INST_0_i_1_n_0 ),
.S(a[8]));
MUXF7 \spo[13]_INST_0_i_10
(.I0(g6_b13_n_0),
.I1(g7_b13_n_0),
.O(\spo[13]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[13]_INST_0_i_11
(.I0(g2_b13_n_0),
.I1(g3_b13_n_0),
.O(\spo[13]_INST_0_i_11_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[13]_INST_0_i_2
(.I0(\spo[13]_INST_0_i_6_n_0 ),
.I1(\spo[13]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[13]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[13]_INST_0_i_9_n_0 ),
.O(\spo[13]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hB833B800B800B800))
\spo[13]_INST_0_i_3
(.I0(\spo[13]_INST_0_i_10_n_0 ),
.I1(a[8]),
.I2(\spo[13]_INST_0_i_11_n_0 ),
.I3(a[7]),
.I4(a[6]),
.I5(g1_b13_n_0),
.O(\spo[13]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[13]_INST_0_i_4
(.I0(g19_b13_n_0),
.I1(g18_b13_n_0),
.I2(a[7]),
.I3(g17_b13_n_0),
.I4(a[6]),
.I5(g16_b13_n_0),
.O(\spo[13]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[13]_INST_0_i_5
(.I0(g23_b13_n_0),
.I1(g22_b13_n_0),
.I2(a[7]),
.I3(g21_b13_n_0),
.I4(a[6]),
.I5(g10_b15_n_0),
.O(\spo[13]_INST_0_i_5_n_0 ));
MUXF7 \spo[13]_INST_0_i_6
(.I0(g14_b13_n_0),
.I1(g15_b13_n_0),
.O(\spo[13]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[13]_INST_0_i_7
(.I0(g12_b13_n_0),
.I1(g13_b13_n_0),
.O(\spo[13]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[13]_INST_0_i_8
(.I0(g10_b13_n_0),
.I1(g11_b13_n_0),
.O(\spo[13]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[13]_INST_0_i_9
(.I0(g8_b13_n_0),
.I1(g9_b13_n_0),
.O(\spo[13]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[14]_INST_0
(.I0(\spo[23]_INST_0_i_1_n_0 ),
.I1(\spo[14]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[14]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[14]_INST_0_i_3_n_0 ),
.O(spo[14]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[14]_INST_0_i_1
(.I0(\spo[14]_INST_0_i_4_n_0 ),
.I1(\spo[14]_INST_0_i_5_n_0 ),
.I2(a[8]),
.I3(\spo[14]_INST_0_i_6_n_0 ),
.I4(a[7]),
.I5(\spo[14]_INST_0_i_7_n_0 ),
.O(\spo[14]_INST_0_i_1_n_0 ));
MUXF7 \spo[14]_INST_0_i_10
(.I0(g10_b14_n_0),
.I1(g11_b14_n_0),
.O(\spo[14]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[14]_INST_0_i_11
(.I0(g8_b14_n_0),
.I1(g9_b14_n_0),
.O(\spo[14]_INST_0_i_11_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[14]_INST_0_i_12
(.I0(g3_b14_n_0),
.I1(g2_b14_n_0),
.I2(a[7]),
.I3(g1_b14_n_0),
.I4(a[6]),
.I5(g0_b23_n_0),
.O(\spo[14]_INST_0_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[14]_INST_0_i_13
(.I0(g7_b14_n_0),
.I1(g6_b14_n_0),
.I2(a[7]),
.I3(g5_b14_n_0),
.I4(a[6]),
.I5(g4_b14_n_0),
.O(\spo[14]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[14]_INST_0_i_2
(.I0(\spo[14]_INST_0_i_8_n_0 ),
.I1(\spo[14]_INST_0_i_9_n_0 ),
.I2(a[8]),
.I3(\spo[14]_INST_0_i_10_n_0 ),
.I4(a[7]),
.I5(\spo[14]_INST_0_i_11_n_0 ),
.O(\spo[14]_INST_0_i_2_n_0 ));
MUXF7 \spo[14]_INST_0_i_3
(.I0(\spo[14]_INST_0_i_12_n_0 ),
.I1(\spo[14]_INST_0_i_13_n_0 ),
.O(\spo[14]_INST_0_i_3_n_0 ),
.S(a[8]));
MUXF7 \spo[14]_INST_0_i_4
(.I0(g22_b14_n_0),
.I1(g23_b14_n_0),
.O(\spo[14]_INST_0_i_4_n_0 ),
.S(a[6]));
MUXF7 \spo[14]_INST_0_i_5
(.I0(g20_b14_n_0),
.I1(g21_b14_n_0),
.O(\spo[14]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[14]_INST_0_i_6
(.I0(g18_b14_n_0),
.I1(g19_b14_n_0),
.O(\spo[14]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[14]_INST_0_i_7
(.I0(g16_b14_n_0),
.I1(g17_b14_n_0),
.O(\spo[14]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[14]_INST_0_i_8
(.I0(g14_b14_n_0),
.I1(g15_b14_n_0),
.O(\spo[14]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[14]_INST_0_i_9
(.I0(g12_b14_n_0),
.I1(g13_b14_n_0),
.O(\spo[14]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT5 #(
.INIT(32'h30BB3088))
\spo[15]_INST_0
(.I0(\spo[15]_INST_0_i_1_n_0 ),
.I1(a[10]),
.I2(\spo[15]_INST_0_i_2_n_0 ),
.I3(a[9]),
.I4(\spo[15]_INST_0_i_3_n_0 ),
.O(spo[15]));
MUXF7 \spo[15]_INST_0_i_1
(.I0(\spo[15]_INST_0_i_4_n_0 ),
.I1(\spo[15]_INST_0_i_5_n_0 ),
.O(\spo[15]_INST_0_i_1_n_0 ),
.S(a[8]));
MUXF7 \spo[15]_INST_0_i_2
(.I0(\spo[15]_INST_0_i_6_n_0 ),
.I1(\spo[15]_INST_0_i_7_n_0 ),
.O(\spo[15]_INST_0_i_2_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hB8333000B8003000))
\spo[15]_INST_0_i_3
(.I0(g7_b15_n_0),
.I1(a[8]),
.I2(\spo[15]_INST_0_i_8_n_0 ),
.I3(a[7]),
.I4(a[6]),
.I5(g1_b15_n_0),
.O(\spo[15]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[15]_INST_0_i_4
(.I0(g19_b15_n_0),
.I1(g18_b15_n_0),
.I2(a[7]),
.I3(g17_b15_n_0),
.I4(a[6]),
.I5(g16_b15_n_0),
.O(\spo[15]_INST_0_i_4_n_0 ));
LUT4 #(
.INIT(16'h3808))
\spo[15]_INST_0_i_5
(.I0(g22_b15_n_0),
.I1(a[7]),
.I2(a[6]),
.I3(g4_b22_n_0),
.O(\spo[15]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[15]_INST_0_i_6
(.I0(g11_b15_n_0),
.I1(g10_b15_n_0),
.I2(a[7]),
.I3(g9_b15_n_0),
.I4(a[6]),
.I5(g8_b15_n_0),
.O(\spo[15]_INST_0_i_6_n_0 ));
LUT4 #(
.INIT(16'h8830))
\spo[15]_INST_0_i_7
(.I0(g16_b22_n_0),
.I1(a[7]),
.I2(g12_b15_n_0),
.I3(a[6]),
.O(\spo[15]_INST_0_i_7_n_0 ));
MUXF7 \spo[15]_INST_0_i_8
(.I0(g2_b15_n_0),
.I1(g3_b15_n_0),
.O(\spo[15]_INST_0_i_8_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[16]_INST_0
(.I0(\spo[16]_INST_0_i_1_n_0 ),
.I1(\spo[16]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[16]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[16]_INST_0_i_4_n_0 ),
.O(spo[16]));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT4 #(
.INIT(16'h0004))
\spo[16]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b16_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[16]_INST_0_i_1_n_0 ));
MUXF7 \spo[16]_INST_0_i_10
(.I0(g12_b16_n_0),
.I1(g13_b16_n_0),
.O(\spo[16]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[16]_INST_0_i_11
(.I0(g10_b16_n_0),
.I1(g11_b16_n_0),
.O(\spo[16]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[16]_INST_0_i_12
(.I0(g8_b16_n_0),
.I1(g9_b16_n_0),
.O(\spo[16]_INST_0_i_12_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[16]_INST_0_i_13
(.I0(g3_b16_n_0),
.I1(g2_b16_n_0),
.I2(a[7]),
.I3(g1_b16_n_0),
.I4(a[6]),
.I5(g0_b23_n_0),
.O(\spo[16]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[16]_INST_0_i_14
(.I0(g7_b16_n_0),
.I1(g6_b16_n_0),
.I2(a[7]),
.I3(g5_b16_n_0),
.I4(a[6]),
.I5(g4_b16_n_0),
.O(\spo[16]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[16]_INST_0_i_2
(.I0(\spo[16]_INST_0_i_5_n_0 ),
.I1(\spo[16]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[16]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[16]_INST_0_i_8_n_0 ),
.O(\spo[16]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[16]_INST_0_i_3
(.I0(\spo[16]_INST_0_i_9_n_0 ),
.I1(\spo[16]_INST_0_i_10_n_0 ),
.I2(a[8]),
.I3(\spo[16]_INST_0_i_11_n_0 ),
.I4(a[7]),
.I5(\spo[16]_INST_0_i_12_n_0 ),
.O(\spo[16]_INST_0_i_3_n_0 ));
MUXF7 \spo[16]_INST_0_i_4
(.I0(\spo[16]_INST_0_i_13_n_0 ),
.I1(\spo[16]_INST_0_i_14_n_0 ),
.O(\spo[16]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[16]_INST_0_i_5
(.I0(g22_b16_n_0),
.I1(g23_b16_n_0),
.O(\spo[16]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[16]_INST_0_i_6
(.I0(g20_b16_n_0),
.I1(g21_b16_n_0),
.O(\spo[16]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[16]_INST_0_i_7
(.I0(g18_b16_n_0),
.I1(g19_b16_n_0),
.O(\spo[16]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[16]_INST_0_i_8
(.I0(g16_b16_n_0),
.I1(g17_b16_n_0),
.O(\spo[16]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[16]_INST_0_i_9
(.I0(g14_b16_n_0),
.I1(g15_b16_n_0),
.O(\spo[16]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[17]_INST_0
(.I0(\spo[17]_INST_0_i_1_n_0 ),
.I1(\spo[17]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[17]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[17]_INST_0_i_4_n_0 ),
.O(spo[17]));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT3 #(
.INIT(8'h01))
\spo[17]_INST_0_i_1
(.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.O(\spo[17]_INST_0_i_1_n_0 ));
MUXF7 \spo[17]_INST_0_i_10
(.I0(g12_b17_n_0),
.I1(g13_b17_n_0),
.O(\spo[17]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[17]_INST_0_i_11
(.I0(g10_b17_n_0),
.I1(g11_b17_n_0),
.O(\spo[17]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[17]_INST_0_i_12
(.I0(g8_b17_n_0),
.I1(g9_b17_n_0),
.O(\spo[17]_INST_0_i_12_n_0 ),
.S(a[6]));
LUT5 #(
.INIT(32'hAFA0CFCF))
\spo[17]_INST_0_i_13
(.I0(g3_b17_n_0),
.I1(g2_b17_n_0),
.I2(a[7]),
.I3(g1_b17_n_0),
.I4(a[6]),
.O(\spo[17]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[17]_INST_0_i_14
(.I0(g7_b17_n_0),
.I1(g6_b17_n_0),
.I2(a[7]),
.I3(g5_b17_n_0),
.I4(a[6]),
.I5(g4_b17_n_0),
.O(\spo[17]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[17]_INST_0_i_2
(.I0(\spo[17]_INST_0_i_5_n_0 ),
.I1(\spo[17]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[17]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[17]_INST_0_i_8_n_0 ),
.O(\spo[17]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[17]_INST_0_i_3
(.I0(\spo[17]_INST_0_i_9_n_0 ),
.I1(\spo[17]_INST_0_i_10_n_0 ),
.I2(a[8]),
.I3(\spo[17]_INST_0_i_11_n_0 ),
.I4(a[7]),
.I5(\spo[17]_INST_0_i_12_n_0 ),
.O(\spo[17]_INST_0_i_3_n_0 ));
MUXF7 \spo[17]_INST_0_i_4
(.I0(\spo[17]_INST_0_i_13_n_0 ),
.I1(\spo[17]_INST_0_i_14_n_0 ),
.O(\spo[17]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[17]_INST_0_i_5
(.I0(g22_b17_n_0),
.I1(g23_b17_n_0),
.O(\spo[17]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[17]_INST_0_i_6
(.I0(g20_b17_n_0),
.I1(g21_b17_n_0),
.O(\spo[17]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[17]_INST_0_i_7
(.I0(g18_b17_n_0),
.I1(g19_b17_n_0),
.O(\spo[17]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[17]_INST_0_i_8
(.I0(g16_b17_n_0),
.I1(g17_b17_n_0),
.O(\spo[17]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[17]_INST_0_i_9
(.I0(g14_b17_n_0),
.I1(g15_b17_n_0),
.O(\spo[17]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[18]_INST_0
(.I0(\spo[18]_INST_0_i_1_n_0 ),
.I1(\spo[18]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[18]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[18]_INST_0_i_4_n_0 ),
.O(spo[18]));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT4 #(
.INIT(16'h0004))
\spo[18]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b18_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[18]_INST_0_i_1_n_0 ));
MUXF7 \spo[18]_INST_0_i_10
(.I0(g8_b18_n_0),
.I1(g9_b18_n_0),
.O(\spo[18]_INST_0_i_10_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[18]_INST_0_i_11
(.I0(g3_b18_n_0),
.I1(g2_b18_n_0),
.I2(a[7]),
.I3(g1_b18_n_0),
.I4(a[6]),
.I5(g0_b20_n_0),
.O(\spo[18]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[18]_INST_0_i_12
(.I0(g7_b18_n_0),
.I1(g6_b18_n_0),
.I2(a[7]),
.I3(g5_b18_n_0),
.I4(a[6]),
.I5(g4_b18_n_0),
.O(\spo[18]_INST_0_i_12_n_0 ));
MUXF7 \spo[18]_INST_0_i_2
(.I0(\spo[18]_INST_0_i_5_n_0 ),
.I1(\spo[18]_INST_0_i_6_n_0 ),
.O(\spo[18]_INST_0_i_2_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[18]_INST_0_i_3
(.I0(\spo[18]_INST_0_i_7_n_0 ),
.I1(\spo[18]_INST_0_i_8_n_0 ),
.I2(a[8]),
.I3(\spo[18]_INST_0_i_9_n_0 ),
.I4(a[7]),
.I5(\spo[18]_INST_0_i_10_n_0 ),
.O(\spo[18]_INST_0_i_3_n_0 ));
MUXF7 \spo[18]_INST_0_i_4
(.I0(\spo[18]_INST_0_i_11_n_0 ),
.I1(\spo[18]_INST_0_i_12_n_0 ),
.O(\spo[18]_INST_0_i_4_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[18]_INST_0_i_5
(.I0(g19_b18_n_0),
.I1(g18_b18_n_0),
.I2(a[7]),
.I3(g17_b18_n_0),
.I4(a[6]),
.I5(g16_b18_n_0),
.O(\spo[18]_INST_0_i_5_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[18]_INST_0_i_6
(.I0(g23_b18_n_0),
.I1(g22_b18_n_0),
.I2(a[7]),
.I3(g21_b18_n_0),
.I4(a[6]),
.I5(g20_b18_n_0),
.O(\spo[18]_INST_0_i_6_n_0 ));
MUXF7 \spo[18]_INST_0_i_7
(.I0(g14_b18_n_0),
.I1(g15_b18_n_0),
.O(\spo[18]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[18]_INST_0_i_8
(.I0(g12_b18_n_0),
.I1(g13_b18_n_0),
.O(\spo[18]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[18]_INST_0_i_9
(.I0(g10_b18_n_0),
.I1(g11_b18_n_0),
.O(\spo[18]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT5 #(
.INIT(32'h30BB3088))
\spo[19]_INST_0
(.I0(\spo[19]_INST_0_i_1_n_0 ),
.I1(a[10]),
.I2(\spo[19]_INST_0_i_2_n_0 ),
.I3(a[9]),
.I4(\spo[19]_INST_0_i_3_n_0 ),
.O(spo[19]));
MUXF7 \spo[19]_INST_0_i_1
(.I0(\spo[19]_INST_0_i_4_n_0 ),
.I1(\spo[19]_INST_0_i_5_n_0 ),
.O(\spo[19]_INST_0_i_1_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[19]_INST_0_i_10
(.I0(g3_b19_n_0),
.I1(g2_b19_n_0),
.I2(a[7]),
.I3(g1_b19_n_0),
.I4(a[6]),
.I5(g0_b20_n_0),
.O(\spo[19]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[19]_INST_0_i_11
(.I0(g7_b19_n_0),
.I1(g6_b19_n_0),
.I2(a[7]),
.I3(g5_b19_n_0),
.I4(a[6]),
.I5(g4_b19_n_0),
.O(\spo[19]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[19]_INST_0_i_2
(.I0(\spo[19]_INST_0_i_6_n_0 ),
.I1(\spo[19]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[19]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[19]_INST_0_i_9_n_0 ),
.O(\spo[19]_INST_0_i_2_n_0 ));
MUXF7 \spo[19]_INST_0_i_3
(.I0(\spo[19]_INST_0_i_10_n_0 ),
.I1(\spo[19]_INST_0_i_11_n_0 ),
.O(\spo[19]_INST_0_i_3_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[19]_INST_0_i_4
(.I0(g19_b19_n_0),
.I1(g18_b19_n_0),
.I2(a[7]),
.I3(g17_b19_n_0),
.I4(a[6]),
.I5(g16_b19_n_0),
.O(\spo[19]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[19]_INST_0_i_5
(.I0(g23_b19_n_0),
.I1(g22_b19_n_0),
.I2(a[7]),
.I3(g21_b19_n_0),
.I4(a[6]),
.I5(g20_b19_n_0),
.O(\spo[19]_INST_0_i_5_n_0 ));
MUXF7 \spo[19]_INST_0_i_6
(.I0(g14_b19_n_0),
.I1(g15_b19_n_0),
.O(\spo[19]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[19]_INST_0_i_7
(.I0(g12_b19_n_0),
.I1(g13_b19_n_0),
.O(\spo[19]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[19]_INST_0_i_8
(.I0(g10_b19_n_0),
.I1(g11_b19_n_0),
.O(\spo[19]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[19]_INST_0_i_9
(.I0(g8_b19_n_0),
.I1(g9_b19_n_0),
.O(\spo[19]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0
(.I0(\spo[1]_INST_0_i_1_n_0 ),
.I1(\spo[1]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[1]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[1]_INST_0_i_4_n_0 ),
.O(spo[1]));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT4 #(
.INIT(16'h0004))
\spo[1]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b1_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[1]_INST_0_i_1_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0_i_10
(.I0(g15_b1_n_0),
.I1(g1_b12_n_0),
.I2(a[7]),
.I3(g13_b1_n_0),
.I4(a[6]),
.I5(g12_b1_n_0),
.O(\spo[1]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0_i_11
(.I0(g3_b1_n_0),
.I1(g2_b1_n_0),
.I2(a[7]),
.I3(g1_b1_n_0),
.I4(a[6]),
.I5(g0_b1_n_0),
.O(\spo[1]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0_i_12
(.I0(g7_b1_n_0),
.I1(g6_b1_n_0),
.I2(a[7]),
.I3(g5_b1_n_0),
.I4(a[6]),
.I5(g4_b1_n_0),
.O(\spo[1]_INST_0_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0_i_2
(.I0(\spo[1]_INST_0_i_5_n_0 ),
.I1(\spo[1]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[1]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[1]_INST_0_i_8_n_0 ),
.O(\spo[1]_INST_0_i_2_n_0 ));
MUXF7 \spo[1]_INST_0_i_3
(.I0(\spo[1]_INST_0_i_9_n_0 ),
.I1(\spo[1]_INST_0_i_10_n_0 ),
.O(\spo[1]_INST_0_i_3_n_0 ),
.S(a[8]));
MUXF7 \spo[1]_INST_0_i_4
(.I0(\spo[1]_INST_0_i_11_n_0 ),
.I1(\spo[1]_INST_0_i_12_n_0 ),
.O(\spo[1]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[1]_INST_0_i_5
(.I0(g22_b1_n_0),
.I1(g23_b1_n_0),
.O(\spo[1]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[1]_INST_0_i_6
(.I0(g20_b1_n_0),
.I1(g21_b1_n_0),
.O(\spo[1]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[1]_INST_0_i_7
(.I0(g18_b1_n_0),
.I1(g19_b1_n_0),
.O(\spo[1]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[1]_INST_0_i_8
(.I0(g16_b1_n_0),
.I1(g17_b1_n_0),
.O(\spo[1]_INST_0_i_8_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[1]_INST_0_i_9
(.I0(g11_b1_n_0),
.I1(g10_b1_n_0),
.I2(a[7]),
.I3(g9_b1_n_0),
.I4(a[6]),
.I5(g8_b1_n_0),
.O(\spo[1]_INST_0_i_9_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[20]_INST_0
(.I0(\spo[20]_INST_0_i_1_n_0 ),
.I1(\spo[20]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[20]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[20]_INST_0_i_4_n_0 ),
.O(spo[20]));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT4 #(
.INIT(16'h0004))
\spo[20]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b20_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[20]_INST_0_i_1_n_0 ));
MUXF7 \spo[20]_INST_0_i_10
(.I0(g12_b20_n_0),
.I1(g13_b20_n_0),
.O(\spo[20]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[20]_INST_0_i_11
(.I0(g10_b20_n_0),
.I1(g11_b20_n_0),
.O(\spo[20]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[20]_INST_0_i_12
(.I0(g8_b20_n_0),
.I1(g9_b20_n_0),
.O(\spo[20]_INST_0_i_12_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[20]_INST_0_i_13
(.I0(g3_b20_n_0),
.I1(g2_b20_n_0),
.I2(a[7]),
.I3(g1_b20_n_0),
.I4(a[6]),
.I5(g0_b20_n_0),
.O(\spo[20]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[20]_INST_0_i_14
(.I0(g7_b20_n_0),
.I1(g6_b20_n_0),
.I2(a[7]),
.I3(g5_b20_n_0),
.I4(a[6]),
.I5(g4_b20_n_0),
.O(\spo[20]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[20]_INST_0_i_2
(.I0(\spo[20]_INST_0_i_5_n_0 ),
.I1(\spo[20]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[20]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[20]_INST_0_i_8_n_0 ),
.O(\spo[20]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[20]_INST_0_i_3
(.I0(\spo[20]_INST_0_i_9_n_0 ),
.I1(\spo[20]_INST_0_i_10_n_0 ),
.I2(a[8]),
.I3(\spo[20]_INST_0_i_11_n_0 ),
.I4(a[7]),
.I5(\spo[20]_INST_0_i_12_n_0 ),
.O(\spo[20]_INST_0_i_3_n_0 ));
MUXF7 \spo[20]_INST_0_i_4
(.I0(\spo[20]_INST_0_i_13_n_0 ),
.I1(\spo[20]_INST_0_i_14_n_0 ),
.O(\spo[20]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[20]_INST_0_i_5
(.I0(g22_b20_n_0),
.I1(g23_b20_n_0),
.O(\spo[20]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[20]_INST_0_i_6
(.I0(g20_b20_n_0),
.I1(g21_b20_n_0),
.O(\spo[20]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[20]_INST_0_i_7
(.I0(g18_b20_n_0),
.I1(g19_b20_n_0),
.O(\spo[20]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[20]_INST_0_i_8
(.I0(g16_b20_n_0),
.I1(g17_b20_n_0),
.O(\spo[20]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[20]_INST_0_i_9
(.I0(g14_b20_n_0),
.I1(g15_b20_n_0),
.O(\spo[20]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[21]_INST_0
(.I0(\spo[21]_INST_0_i_1_n_0 ),
.I1(\spo[21]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[21]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[21]_INST_0_i_4_n_0 ),
.O(spo[21]));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT4 #(
.INIT(16'h0004))
\spo[21]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b21_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[21]_INST_0_i_1_n_0 ));
MUXF7 \spo[21]_INST_0_i_10
(.I0(g12_b21_n_0),
.I1(g13_b21_n_0),
.O(\spo[21]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[21]_INST_0_i_11
(.I0(g10_b21_n_0),
.I1(g11_b21_n_0),
.O(\spo[21]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[21]_INST_0_i_12
(.I0(g8_b21_n_0),
.I1(g9_b21_n_0),
.O(\spo[21]_INST_0_i_12_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[21]_INST_0_i_13
(.I0(g3_b21_n_0),
.I1(g2_b21_n_0),
.I2(a[7]),
.I3(g1_b21_n_0),
.I4(a[6]),
.I5(g0_b21_n_0),
.O(\spo[21]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[21]_INST_0_i_14
(.I0(g7_b21_n_0),
.I1(g6_b21_n_0),
.I2(a[7]),
.I3(g5_b21_n_0),
.I4(a[6]),
.I5(g4_b21_n_0),
.O(\spo[21]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[21]_INST_0_i_2
(.I0(\spo[21]_INST_0_i_5_n_0 ),
.I1(\spo[21]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[21]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[21]_INST_0_i_8_n_0 ),
.O(\spo[21]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[21]_INST_0_i_3
(.I0(\spo[21]_INST_0_i_9_n_0 ),
.I1(\spo[21]_INST_0_i_10_n_0 ),
.I2(a[8]),
.I3(\spo[21]_INST_0_i_11_n_0 ),
.I4(a[7]),
.I5(\spo[21]_INST_0_i_12_n_0 ),
.O(\spo[21]_INST_0_i_3_n_0 ));
MUXF7 \spo[21]_INST_0_i_4
(.I0(\spo[21]_INST_0_i_13_n_0 ),
.I1(\spo[21]_INST_0_i_14_n_0 ),
.O(\spo[21]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[21]_INST_0_i_5
(.I0(g22_b21_n_0),
.I1(g23_b21_n_0),
.O(\spo[21]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[21]_INST_0_i_6
(.I0(g20_b21_n_0),
.I1(g21_b21_n_0),
.O(\spo[21]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[21]_INST_0_i_7
(.I0(g18_b21_n_0),
.I1(g19_b21_n_0),
.O(\spo[21]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[21]_INST_0_i_8
(.I0(g16_b21_n_0),
.I1(g17_b21_n_0),
.O(\spo[21]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[21]_INST_0_i_9
(.I0(g14_b21_n_0),
.I1(g15_b21_n_0),
.O(\spo[21]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT5 #(
.INIT(32'h30BB3088))
\spo[22]_INST_0
(.I0(\spo[22]_INST_0_i_1_n_0 ),
.I1(a[10]),
.I2(\spo[22]_INST_0_i_2_n_0 ),
.I3(a[9]),
.I4(\spo[22]_INST_0_i_3_n_0 ),
.O(spo[22]));
MUXF7 \spo[22]_INST_0_i_1
(.I0(\spo[22]_INST_0_i_4_n_0 ),
.I1(\spo[22]_INST_0_i_5_n_0 ),
.O(\spo[22]_INST_0_i_1_n_0 ),
.S(a[8]));
LUT5 #(
.INIT(32'hAFC0A0C0))
\spo[22]_INST_0_i_10
(.I0(g3_b22_n_0),
.I1(g2_b22_n_0),
.I2(a[7]),
.I3(a[6]),
.I4(g1_b22_n_0),
.O(\spo[22]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[22]_INST_0_i_11
(.I0(g7_b22_n_0),
.I1(g6_b22_n_0),
.I2(a[7]),
.I3(g5_b22_n_0),
.I4(a[6]),
.I5(g4_b22_n_0),
.O(\spo[22]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[22]_INST_0_i_2
(.I0(\spo[22]_INST_0_i_6_n_0 ),
.I1(\spo[22]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[22]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[22]_INST_0_i_9_n_0 ),
.O(\spo[22]_INST_0_i_2_n_0 ));
MUXF7 \spo[22]_INST_0_i_3
(.I0(\spo[22]_INST_0_i_10_n_0 ),
.I1(\spo[22]_INST_0_i_11_n_0 ),
.O(\spo[22]_INST_0_i_3_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[22]_INST_0_i_4
(.I0(g19_b22_n_0),
.I1(g18_b22_n_0),
.I2(a[7]),
.I3(g17_b22_n_0),
.I4(a[6]),
.I5(g16_b22_n_0),
.O(\spo[22]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[22]_INST_0_i_5
(.I0(g23_b22_n_0),
.I1(g22_b22_n_0),
.I2(a[7]),
.I3(g21_b22_n_0),
.I4(a[6]),
.I5(g20_b22_n_0),
.O(\spo[22]_INST_0_i_5_n_0 ));
MUXF7 \spo[22]_INST_0_i_6
(.I0(g14_b22_n_0),
.I1(g15_b22_n_0),
.O(\spo[22]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[22]_INST_0_i_7
(.I0(g12_b22_n_0),
.I1(g13_b22_n_0),
.O(\spo[22]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[22]_INST_0_i_8
(.I0(g10_b22_n_0),
.I1(g11_b22_n_0),
.O(\spo[22]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[22]_INST_0_i_9
(.I0(g8_b22_n_0),
.I1(g9_b22_n_0),
.O(\spo[22]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[23]_INST_0
(.I0(\spo[23]_INST_0_i_1_n_0 ),
.I1(\spo[23]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[23]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[23]_INST_0_i_4_n_0 ),
.O(spo[23]));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT4 #(
.INIT(16'h0004))
\spo[23]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b23_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[23]_INST_0_i_1_n_0 ));
MUXF7 \spo[23]_INST_0_i_10
(.I0(g12_b23_n_0),
.I1(g13_b23_n_0),
.O(\spo[23]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[23]_INST_0_i_11
(.I0(g10_b23_n_0),
.I1(g11_b23_n_0),
.O(\spo[23]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[23]_INST_0_i_12
(.I0(g8_b23_n_0),
.I1(g9_b23_n_0),
.O(\spo[23]_INST_0_i_12_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[23]_INST_0_i_13
(.I0(g3_b23_n_0),
.I1(g2_b23_n_0),
.I2(a[7]),
.I3(g1_b23_n_0),
.I4(a[6]),
.I5(g0_b23_n_0),
.O(\spo[23]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[23]_INST_0_i_14
(.I0(g7_b23_n_0),
.I1(g6_b23_n_0),
.I2(a[7]),
.I3(g5_b23_n_0),
.I4(a[6]),
.I5(g4_b23_n_0),
.O(\spo[23]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[23]_INST_0_i_2
(.I0(\spo[23]_INST_0_i_5_n_0 ),
.I1(\spo[23]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[23]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[23]_INST_0_i_8_n_0 ),
.O(\spo[23]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[23]_INST_0_i_3
(.I0(\spo[23]_INST_0_i_9_n_0 ),
.I1(\spo[23]_INST_0_i_10_n_0 ),
.I2(a[8]),
.I3(\spo[23]_INST_0_i_11_n_0 ),
.I4(a[7]),
.I5(\spo[23]_INST_0_i_12_n_0 ),
.O(\spo[23]_INST_0_i_3_n_0 ));
MUXF7 \spo[23]_INST_0_i_4
(.I0(\spo[23]_INST_0_i_13_n_0 ),
.I1(\spo[23]_INST_0_i_14_n_0 ),
.O(\spo[23]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[23]_INST_0_i_5
(.I0(g22_b23_n_0),
.I1(g23_b23_n_0),
.O(\spo[23]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[23]_INST_0_i_6
(.I0(g20_b23_n_0),
.I1(g21_b23_n_0),
.O(\spo[23]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[23]_INST_0_i_7
(.I0(g18_b23_n_0),
.I1(g19_b23_n_0),
.O(\spo[23]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[23]_INST_0_i_8
(.I0(g16_b23_n_0),
.I1(g17_b23_n_0),
.O(\spo[23]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[23]_INST_0_i_9
(.I0(g14_b23_n_0),
.I1(g15_b23_n_0),
.O(\spo[23]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[2]_INST_0
(.I0(\spo[2]_INST_0_i_1_n_0 ),
.I1(\spo[2]_INST_0_i_2_n_0 ),
.I2(a[10]),
.I3(\spo[2]_INST_0_i_3_n_0 ),
.I4(a[9]),
.I5(\spo[2]_INST_0_i_4_n_0 ),
.O(spo[2]));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT4 #(
.INIT(16'h0004))
\spo[2]_INST_0_i_1
(.I0(a[7]),
.I1(g24_b2_n_0),
.I2(a[6]),
.I3(a[8]),
.O(\spo[2]_INST_0_i_1_n_0 ));
MUXF7 \spo[2]_INST_0_i_10
(.I0(g12_b2_n_0),
.I1(g13_b2_n_0),
.O(\spo[2]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[2]_INST_0_i_11
(.I0(g10_b2_n_0),
.I1(g11_b2_n_0),
.O(\spo[2]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[2]_INST_0_i_12
(.I0(g8_b2_n_0),
.I1(g9_b2_n_0),
.O(\spo[2]_INST_0_i_12_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[2]_INST_0_i_13
(.I0(g3_b2_n_0),
.I1(g2_b2_n_0),
.I2(a[7]),
.I3(g1_b2_n_0),
.I4(a[6]),
.I5(g0_b21_n_0),
.O(\spo[2]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[2]_INST_0_i_14
(.I0(g7_b2_n_0),
.I1(g6_b2_n_0),
.I2(a[7]),
.I3(g5_b2_n_0),
.I4(a[6]),
.I5(g4_b2_n_0),
.O(\spo[2]_INST_0_i_14_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[2]_INST_0_i_2
(.I0(\spo[2]_INST_0_i_5_n_0 ),
.I1(\spo[2]_INST_0_i_6_n_0 ),
.I2(a[8]),
.I3(\spo[2]_INST_0_i_7_n_0 ),
.I4(a[7]),
.I5(\spo[2]_INST_0_i_8_n_0 ),
.O(\spo[2]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[2]_INST_0_i_3
(.I0(\spo[2]_INST_0_i_9_n_0 ),
.I1(\spo[2]_INST_0_i_10_n_0 ),
.I2(a[8]),
.I3(\spo[2]_INST_0_i_11_n_0 ),
.I4(a[7]),
.I5(\spo[2]_INST_0_i_12_n_0 ),
.O(\spo[2]_INST_0_i_3_n_0 ));
MUXF7 \spo[2]_INST_0_i_4
(.I0(\spo[2]_INST_0_i_13_n_0 ),
.I1(\spo[2]_INST_0_i_14_n_0 ),
.O(\spo[2]_INST_0_i_4_n_0 ),
.S(a[8]));
MUXF7 \spo[2]_INST_0_i_5
(.I0(g22_b2_n_0),
.I1(g23_b2_n_0),
.O(\spo[2]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[2]_INST_0_i_6
(.I0(g20_b2_n_0),
.I1(g21_b2_n_0),
.O(\spo[2]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[2]_INST_0_i_7
(.I0(g18_b2_n_0),
.I1(g19_b2_n_0),
.O(\spo[2]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[2]_INST_0_i_8
(.I0(g16_b2_n_0),
.I1(g17_b2_n_0),
.O(\spo[2]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[2]_INST_0_i_9
(.I0(g14_b2_n_0),
.I1(g15_b2_n_0),
.O(\spo[2]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[3]_INST_0
(.I0(\spo[18]_INST_0_i_1_n_0 ),
.I1(\spo[3]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[3]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[3]_INST_0_i_3_n_0 ),
.O(spo[3]));
MUXF7 \spo[3]_INST_0_i_1
(.I0(\spo[3]_INST_0_i_4_n_0 ),
.I1(\spo[3]_INST_0_i_5_n_0 ),
.O(\spo[3]_INST_0_i_1_n_0 ),
.S(a[8]));
LUT5 #(
.INIT(32'hAFC0A0C0))
\spo[3]_INST_0_i_10
(.I0(g3_b3_n_0),
.I1(g2_b3_n_0),
.I2(a[7]),
.I3(a[6]),
.I4(g1_b3_n_0),
.O(\spo[3]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[3]_INST_0_i_11
(.I0(g7_b3_n_0),
.I1(g6_b3_n_0),
.I2(a[7]),
.I3(g5_b3_n_0),
.I4(a[6]),
.I5(g4_b3_n_0),
.O(\spo[3]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[3]_INST_0_i_2
(.I0(\spo[3]_INST_0_i_6_n_0 ),
.I1(\spo[3]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[3]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[3]_INST_0_i_9_n_0 ),
.O(\spo[3]_INST_0_i_2_n_0 ));
MUXF7 \spo[3]_INST_0_i_3
(.I0(\spo[3]_INST_0_i_10_n_0 ),
.I1(\spo[3]_INST_0_i_11_n_0 ),
.O(\spo[3]_INST_0_i_3_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[3]_INST_0_i_4
(.I0(g19_b3_n_0),
.I1(g18_b3_n_0),
.I2(a[7]),
.I3(g17_b3_n_0),
.I4(a[6]),
.I5(g16_b3_n_0),
.O(\spo[3]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[3]_INST_0_i_5
(.I0(g23_b3_n_0),
.I1(g22_b3_n_0),
.I2(a[7]),
.I3(g21_b3_n_0),
.I4(a[6]),
.I5(g20_b3_n_0),
.O(\spo[3]_INST_0_i_5_n_0 ));
MUXF7 \spo[3]_INST_0_i_6
(.I0(g14_b3_n_0),
.I1(g15_b3_n_0),
.O(\spo[3]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[3]_INST_0_i_7
(.I0(g12_b3_n_0),
.I1(g13_b3_n_0),
.O(\spo[3]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[3]_INST_0_i_8
(.I0(g10_b3_n_0),
.I1(g11_b3_n_0),
.O(\spo[3]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[3]_INST_0_i_9
(.I0(g8_b3_n_0),
.I1(g9_b3_n_0),
.O(\spo[3]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[4]_INST_0
(.I0(\spo[12]_INST_0_i_1_n_0 ),
.I1(\spo[4]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[4]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[4]_INST_0_i_3_n_0 ),
.O(spo[4]));
MUXF7 \spo[4]_INST_0_i_1
(.I0(\spo[4]_INST_0_i_4_n_0 ),
.I1(\spo[4]_INST_0_i_5_n_0 ),
.O(\spo[4]_INST_0_i_1_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[4]_INST_0_i_10
(.I0(g3_b4_n_0),
.I1(g2_b4_n_0),
.I2(a[7]),
.I3(g1_b4_n_0),
.I4(a[6]),
.I5(g23_b13_n_0),
.O(\spo[4]_INST_0_i_10_n_0 ));
LUT5 #(
.INIT(32'hA0A0CFC0))
\spo[4]_INST_0_i_11
(.I0(g7_b4_n_0),
.I1(g6_b4_n_0),
.I2(a[7]),
.I3(g4_b4_n_0),
.I4(a[6]),
.O(\spo[4]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[4]_INST_0_i_2
(.I0(\spo[4]_INST_0_i_6_n_0 ),
.I1(\spo[4]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[4]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[4]_INST_0_i_9_n_0 ),
.O(\spo[4]_INST_0_i_2_n_0 ));
MUXF7 \spo[4]_INST_0_i_3
(.I0(\spo[4]_INST_0_i_10_n_0 ),
.I1(\spo[4]_INST_0_i_11_n_0 ),
.O(\spo[4]_INST_0_i_3_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[4]_INST_0_i_4
(.I0(g19_b4_n_0),
.I1(g18_b4_n_0),
.I2(a[7]),
.I3(g17_b4_n_0),
.I4(a[6]),
.I5(g16_b4_n_0),
.O(\spo[4]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[4]_INST_0_i_5
(.I0(g23_b4_n_0),
.I1(g22_b4_n_0),
.I2(a[7]),
.I3(g21_b4_n_0),
.I4(a[6]),
.I5(g20_b18_n_0),
.O(\spo[4]_INST_0_i_5_n_0 ));
MUXF7 \spo[4]_INST_0_i_6
(.I0(g14_b4_n_0),
.I1(g15_b4_n_0),
.O(\spo[4]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[4]_INST_0_i_7
(.I0(g12_b4_n_0),
.I1(g13_b4_n_0),
.O(\spo[4]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[4]_INST_0_i_8
(.I0(g10_b4_n_0),
.I1(g11_b4_n_0),
.O(\spo[4]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[4]_INST_0_i_9
(.I0(g8_b4_n_0),
.I1(g9_b4_n_0),
.O(\spo[4]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[5]_INST_0
(.I0(\spo[23]_INST_0_i_1_n_0 ),
.I1(\spo[5]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[5]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[5]_INST_0_i_3_n_0 ),
.O(spo[5]));
MUXF7 \spo[5]_INST_0_i_1
(.I0(\spo[5]_INST_0_i_4_n_0 ),
.I1(\spo[5]_INST_0_i_5_n_0 ),
.O(\spo[5]_INST_0_i_1_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[5]_INST_0_i_10
(.I0(g3_b5_n_0),
.I1(g2_b5_n_0),
.I2(a[7]),
.I3(g1_b5_n_0),
.I4(a[6]),
.I5(g0_b23_n_0),
.O(\spo[5]_INST_0_i_10_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[5]_INST_0_i_11
(.I0(g7_b5_n_0),
.I1(g6_b5_n_0),
.I2(a[7]),
.I3(g5_b14_n_0),
.I4(a[6]),
.I5(g4_b14_n_0),
.O(\spo[5]_INST_0_i_11_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[5]_INST_0_i_2
(.I0(\spo[5]_INST_0_i_6_n_0 ),
.I1(\spo[5]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[5]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[5]_INST_0_i_9_n_0 ),
.O(\spo[5]_INST_0_i_2_n_0 ));
MUXF7 \spo[5]_INST_0_i_3
(.I0(\spo[5]_INST_0_i_10_n_0 ),
.I1(\spo[5]_INST_0_i_11_n_0 ),
.O(\spo[5]_INST_0_i_3_n_0 ),
.S(a[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[5]_INST_0_i_4
(.I0(g19_b8_n_0),
.I1(g18_b5_n_0),
.I2(a[7]),
.I3(g17_b5_n_0),
.I4(a[6]),
.I5(g16_b5_n_0),
.O(\spo[5]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[5]_INST_0_i_5
(.I0(g23_b5_n_0),
.I1(g22_b5_n_0),
.I2(a[7]),
.I3(g21_b5_n_0),
.I4(a[6]),
.I5(g20_b5_n_0),
.O(\spo[5]_INST_0_i_5_n_0 ));
MUXF7 \spo[5]_INST_0_i_6
(.I0(g14_b5_n_0),
.I1(g15_b5_n_0),
.O(\spo[5]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[5]_INST_0_i_7
(.I0(g12_b5_n_0),
.I1(g13_b5_n_0),
.O(\spo[5]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[5]_INST_0_i_8
(.I0(g10_b5_n_0),
.I1(g11_b5_n_0),
.O(\spo[5]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[5]_INST_0_i_9
(.I0(g8_b5_n_0),
.I1(g9_b5_n_0),
.O(\spo[5]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT5 #(
.INIT(32'h30BB3088))
\spo[6]_INST_0
(.I0(\spo[6]_INST_0_i_1_n_0 ),
.I1(a[10]),
.I2(\spo[6]_INST_0_i_2_n_0 ),
.I3(a[9]),
.I4(\spo[6]_INST_0_i_3_n_0 ),
.O(spo[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[6]_INST_0_i_1
(.I0(\spo[6]_INST_0_i_4_n_0 ),
.I1(\spo[6]_INST_0_i_5_n_0 ),
.I2(a[8]),
.I3(\spo[6]_INST_0_i_6_n_0 ),
.I4(a[7]),
.I5(\spo[6]_INST_0_i_7_n_0 ),
.O(\spo[6]_INST_0_i_1_n_0 ));
MUXF7 \spo[6]_INST_0_i_10
(.I0(g10_b6_n_0),
.I1(g11_b6_n_0),
.O(\spo[6]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[6]_INST_0_i_11
(.I0(g8_b6_n_0),
.I1(g9_b6_n_0),
.O(\spo[6]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[6]_INST_0_i_12
(.I0(g2_b6_n_0),
.I1(g3_b6_n_0),
.O(\spo[6]_INST_0_i_12_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[6]_INST_0_i_2
(.I0(\spo[6]_INST_0_i_8_n_0 ),
.I1(\spo[6]_INST_0_i_9_n_0 ),
.I2(a[8]),
.I3(\spo[6]_INST_0_i_10_n_0 ),
.I4(a[7]),
.I5(\spo[6]_INST_0_i_11_n_0 ),
.O(\spo[6]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hE2FF0000E2000000))
\spo[6]_INST_0_i_3
(.I0(g6_b6_n_0),
.I1(a[6]),
.I2(g7_b6_n_0),
.I3(a[8]),
.I4(a[7]),
.I5(\spo[6]_INST_0_i_12_n_0 ),
.O(\spo[6]_INST_0_i_3_n_0 ));
MUXF7 \spo[6]_INST_0_i_4
(.I0(g22_b6_n_0),
.I1(g23_b6_n_0),
.O(\spo[6]_INST_0_i_4_n_0 ),
.S(a[6]));
MUXF7 \spo[6]_INST_0_i_5
(.I0(g20_b6_n_0),
.I1(g21_b6_n_0),
.O(\spo[6]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[6]_INST_0_i_6
(.I0(g18_b6_n_0),
.I1(g19_b6_n_0),
.O(\spo[6]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[6]_INST_0_i_7
(.I0(g16_b6_n_0),
.I1(g17_b6_n_0),
.O(\spo[6]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[6]_INST_0_i_8
(.I0(g14_b6_n_0),
.I1(g15_b6_n_0),
.O(\spo[6]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[6]_INST_0_i_9
(.I0(g12_b6_n_0),
.I1(g13_b6_n_0),
.O(\spo[6]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[7]_INST_0
(.I0(\spo[23]_INST_0_i_1_n_0 ),
.I1(\spo[7]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[7]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[7]_INST_0_i_3_n_0 ),
.O(spo[7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[7]_INST_0_i_1
(.I0(\spo[7]_INST_0_i_4_n_0 ),
.I1(\spo[7]_INST_0_i_5_n_0 ),
.I2(a[8]),
.I3(\spo[7]_INST_0_i_6_n_0 ),
.I4(a[7]),
.I5(\spo[7]_INST_0_i_7_n_0 ),
.O(\spo[7]_INST_0_i_1_n_0 ));
MUXF7 \spo[7]_INST_0_i_10
(.I0(g10_b7_n_0),
.I1(g11_b7_n_0),
.O(\spo[7]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[7]_INST_0_i_11
(.I0(g8_b7_n_0),
.I1(g9_b7_n_0),
.O(\spo[7]_INST_0_i_11_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[7]_INST_0_i_12
(.I0(g3_b7_n_0),
.I1(g2_b7_n_0),
.I2(a[7]),
.I3(g1_b7_n_0),
.I4(a[6]),
.I5(g0_b23_n_0),
.O(\spo[7]_INST_0_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[7]_INST_0_i_13
(.I0(g7_b7_n_0),
.I1(g6_b7_n_0),
.I2(a[7]),
.I3(g5_b14_n_0),
.I4(a[6]),
.I5(g4_b14_n_0),
.O(\spo[7]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[7]_INST_0_i_2
(.I0(\spo[7]_INST_0_i_8_n_0 ),
.I1(\spo[7]_INST_0_i_9_n_0 ),
.I2(a[8]),
.I3(\spo[7]_INST_0_i_10_n_0 ),
.I4(a[7]),
.I5(\spo[7]_INST_0_i_11_n_0 ),
.O(\spo[7]_INST_0_i_2_n_0 ));
MUXF7 \spo[7]_INST_0_i_3
(.I0(\spo[7]_INST_0_i_12_n_0 ),
.I1(\spo[7]_INST_0_i_13_n_0 ),
.O(\spo[7]_INST_0_i_3_n_0 ),
.S(a[8]));
MUXF7 \spo[7]_INST_0_i_4
(.I0(g22_b7_n_0),
.I1(g23_b7_n_0),
.O(\spo[7]_INST_0_i_4_n_0 ),
.S(a[6]));
MUXF7 \spo[7]_INST_0_i_5
(.I0(g20_b7_n_0),
.I1(g21_b7_n_0),
.O(\spo[7]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[7]_INST_0_i_6
(.I0(g18_b7_n_0),
.I1(g19_b7_n_0),
.O(\spo[7]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[7]_INST_0_i_7
(.I0(g16_b7_n_0),
.I1(g17_b7_n_0),
.O(\spo[7]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[7]_INST_0_i_8
(.I0(g14_b7_n_0),
.I1(g15_b7_n_0),
.O(\spo[7]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[7]_INST_0_i_9
(.I0(g12_b7_n_0),
.I1(g13_b7_n_0),
.O(\spo[7]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[8]_INST_0
(.I0(\spo[21]_INST_0_i_1_n_0 ),
.I1(\spo[8]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[8]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[8]_INST_0_i_3_n_0 ),
.O(spo[8]));
MUXF7 \spo[8]_INST_0_i_1
(.I0(\spo[8]_INST_0_i_4_n_0 ),
.I1(\spo[8]_INST_0_i_5_n_0 ),
.O(\spo[8]_INST_0_i_1_n_0 ),
.S(a[8]));
MUXF7 \spo[8]_INST_0_i_10
(.I0(g6_b8_n_0),
.I1(g7_b8_n_0),
.O(\spo[8]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[8]_INST_0_i_11
(.I0(g4_b8_n_0),
.I1(g5_b8_n_0),
.O(\spo[8]_INST_0_i_11_n_0 ),
.S(a[6]));
MUXF7 \spo[8]_INST_0_i_12
(.I0(g2_b8_n_0),
.I1(g3_b8_n_0),
.O(\spo[8]_INST_0_i_12_n_0 ),
.S(a[6]));
MUXF7 \spo[8]_INST_0_i_13
(.I0(g0_b8_n_0),
.I1(g1_b8_n_0),
.O(\spo[8]_INST_0_i_13_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[8]_INST_0_i_2
(.I0(\spo[8]_INST_0_i_6_n_0 ),
.I1(\spo[8]_INST_0_i_7_n_0 ),
.I2(a[8]),
.I3(\spo[8]_INST_0_i_8_n_0 ),
.I4(a[7]),
.I5(\spo[8]_INST_0_i_9_n_0 ),
.O(\spo[8]_INST_0_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[8]_INST_0_i_3
(.I0(\spo[8]_INST_0_i_10_n_0 ),
.I1(\spo[8]_INST_0_i_11_n_0 ),
.I2(a[8]),
.I3(\spo[8]_INST_0_i_12_n_0 ),
.I4(a[7]),
.I5(\spo[8]_INST_0_i_13_n_0 ),
.O(\spo[8]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[8]_INST_0_i_4
(.I0(g19_b8_n_0),
.I1(g18_b8_n_0),
.I2(a[7]),
.I3(g17_b8_n_0),
.I4(a[6]),
.I5(g16_b8_n_0),
.O(\spo[8]_INST_0_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[8]_INST_0_i_5
(.I0(g23_b8_n_0),
.I1(g22_b8_n_0),
.I2(a[7]),
.I3(g21_b8_n_0),
.I4(a[6]),
.I5(g20_b8_n_0),
.O(\spo[8]_INST_0_i_5_n_0 ));
MUXF7 \spo[8]_INST_0_i_6
(.I0(g14_b8_n_0),
.I1(g15_b8_n_0),
.O(\spo[8]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[8]_INST_0_i_7
(.I0(g12_b8_n_0),
.I1(g13_b8_n_0),
.O(\spo[8]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[8]_INST_0_i_8
(.I0(g10_b8_n_0),
.I1(g11_b8_n_0),
.O(\spo[8]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[8]_INST_0_i_9
(.I0(g8_b8_n_0),
.I1(g9_b8_n_0),
.O(\spo[8]_INST_0_i_9_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[9]_INST_0
(.I0(\spo[12]_INST_0_i_1_n_0 ),
.I1(\spo[9]_INST_0_i_1_n_0 ),
.I2(a[10]),
.I3(\spo[9]_INST_0_i_2_n_0 ),
.I4(a[9]),
.I5(\spo[9]_INST_0_i_3_n_0 ),
.O(spo[9]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[9]_INST_0_i_1
(.I0(\spo[9]_INST_0_i_4_n_0 ),
.I1(\spo[9]_INST_0_i_5_n_0 ),
.I2(a[8]),
.I3(\spo[9]_INST_0_i_6_n_0 ),
.I4(a[7]),
.I5(\spo[9]_INST_0_i_7_n_0 ),
.O(\spo[9]_INST_0_i_1_n_0 ));
MUXF7 \spo[9]_INST_0_i_10
(.I0(g10_b9_n_0),
.I1(g11_b9_n_0),
.O(\spo[9]_INST_0_i_10_n_0 ),
.S(a[6]));
MUXF7 \spo[9]_INST_0_i_11
(.I0(g8_b9_n_0),
.I1(g9_b9_n_0),
.O(\spo[9]_INST_0_i_11_n_0 ),
.S(a[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[9]_INST_0_i_12
(.I0(g3_b9_n_0),
.I1(g2_b9_n_0),
.I2(a[7]),
.I3(g1_b9_n_0),
.I4(a[6]),
.I5(g4_b14_n_0),
.O(\spo[9]_INST_0_i_12_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[9]_INST_0_i_13
(.I0(g7_b9_n_0),
.I1(g6_b9_n_0),
.I2(a[7]),
.I3(g5_b9_n_0),
.I4(a[6]),
.I5(g4_b9_n_0),
.O(\spo[9]_INST_0_i_13_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\spo[9]_INST_0_i_2
(.I0(\spo[9]_INST_0_i_8_n_0 ),
.I1(\spo[9]_INST_0_i_9_n_0 ),
.I2(a[8]),
.I3(\spo[9]_INST_0_i_10_n_0 ),
.I4(a[7]),
.I5(\spo[9]_INST_0_i_11_n_0 ),
.O(\spo[9]_INST_0_i_2_n_0 ));
MUXF7 \spo[9]_INST_0_i_3
(.I0(\spo[9]_INST_0_i_12_n_0 ),
.I1(\spo[9]_INST_0_i_13_n_0 ),
.O(\spo[9]_INST_0_i_3_n_0 ),
.S(a[8]));
MUXF7 \spo[9]_INST_0_i_4
(.I0(g22_b9_n_0),
.I1(g23_b9_n_0),
.O(\spo[9]_INST_0_i_4_n_0 ),
.S(a[6]));
MUXF7 \spo[9]_INST_0_i_5
(.I0(g20_b9_n_0),
.I1(g21_b9_n_0),
.O(\spo[9]_INST_0_i_5_n_0 ),
.S(a[6]));
MUXF7 \spo[9]_INST_0_i_6
(.I0(g18_b9_n_0),
.I1(g19_b9_n_0),
.O(\spo[9]_INST_0_i_6_n_0 ),
.S(a[6]));
MUXF7 \spo[9]_INST_0_i_7
(.I0(g16_b9_n_0),
.I1(g17_b9_n_0),
.O(\spo[9]_INST_0_i_7_n_0 ),
.S(a[6]));
MUXF7 \spo[9]_INST_0_i_8
(.I0(g14_b9_n_0),
.I1(g15_b9_n_0),
.O(\spo[9]_INST_0_i_8_n_0 ),
.S(a[6]));
MUXF7 \spo[9]_INST_0_i_9
(.I0(g12_b9_n_0),
.I1(g13_b9_n_0),
.O(\spo[9]_INST_0_i_9_n_0 ),
.S(a[6]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9144_channel (
// dac interface
dac_clk,
dac_rst,
dac_enable,
dac_data,
dma_data,
// processor interface
dac_data_sync,
dac_dds_format,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
parameter CHID = 32'h0;
parameter DP_DISABLE = 0;
// dac interface
input dac_clk;
input dac_rst;
output dac_enable;
output [63:0] dac_data;
input [63:0] dma_data;
// processor interface
input dac_data_sync;
input dac_dds_format;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg dac_enable = 'd0;
reg [63:0] dac_data = 'd0;
reg [63:0] dac_pn7_data = 'd0;
reg [63:0] dac_pn15_data = 'd0;
reg [63:0] dac_pn23_data = 'd0;
reg [63:0] dac_pn31_data = 'd0;
reg [15:0] dac_dds_phase_0_0 = 'd0;
reg [15:0] dac_dds_phase_0_1 = 'd0;
reg [15:0] dac_dds_phase_1_0 = 'd0;
reg [15:0] dac_dds_phase_1_1 = 'd0;
reg [15:0] dac_dds_phase_2_0 = 'd0;
reg [15:0] dac_dds_phase_2_1 = 'd0;
reg [15:0] dac_dds_phase_3_0 = 'd0;
reg [15:0] dac_dds_phase_3_1 = 'd0;
reg [15:0] dac_dds_incr_0 = 'd0;
reg [15:0] dac_dds_incr_1 = 'd0;
reg [63:0] dac_dds_data = 'd0;
// internal signals
wire [15:0] dac_dds_data_0_s;
wire [15:0] dac_dds_data_1_s;
wire [15:0] dac_dds_data_2_s;
wire [15:0] dac_dds_data_3_s;
wire [15:0] dac_dds_scale_1_s;
wire [15:0] dac_dds_init_1_s;
wire [15:0] dac_dds_incr_1_s;
wire [15:0] dac_dds_scale_2_s;
wire [15:0] dac_dds_init_2_s;
wire [15:0] dac_dds_incr_2_s;
wire [15:0] dac_pat_data_1_s;
wire [15:0] dac_pat_data_2_s;
wire [ 3:0] dac_data_sel_s;
// pn7 function
function [63:0] pn7;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[ 7] ^ din[ 6];
dout[62] = din[ 6] ^ din[ 5];
dout[61] = din[ 5] ^ din[ 4];
dout[60] = din[ 4] ^ din[ 3];
dout[59] = din[ 3] ^ din[ 2];
dout[58] = din[ 2] ^ din[ 1];
dout[57] = din[ 1] ^ din[ 0];
dout[56] = din[ 0] ^ din[ 7] ^ din[ 6];
dout[55] = din[ 7] ^ din[ 5];
dout[54] = din[ 6] ^ din[ 4];
dout[53] = din[ 5] ^ din[ 3];
dout[52] = din[ 4] ^ din[ 2];
dout[51] = din[ 3] ^ din[ 1];
dout[50] = din[ 2] ^ din[ 0];
dout[49] = din[ 1] ^ din[ 7] ^ din[ 6];
dout[48] = din[ 0] ^ din[ 6] ^ din[ 5];
dout[47] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[46] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[45] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[44] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[43] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[42] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[ 7] ^ din[ 6];
dout[41] = din[ 1] ^ din[ 7] ^ din[ 0] ^ din[ 5];
dout[40] = din[ 0] ^ din[ 7] ^ din[ 4];
dout[39] = din[ 7] ^ din[ 3];
dout[38] = din[ 6] ^ din[ 2];
dout[37] = din[ 5] ^ din[ 1];
dout[36] = din[ 4] ^ din[ 0];
dout[35] = din[ 3] ^ din[ 7] ^ din[ 6];
dout[34] = din[ 2] ^ din[ 6] ^ din[ 5];
dout[33] = din[ 1] ^ din[ 5] ^ din[ 4];
dout[32] = din[ 0] ^ din[ 4] ^ din[ 3];
dout[31] = din[ 7] ^ din[ 3] ^ din[ 6] ^ din[ 2];
dout[30] = din[ 6] ^ din[ 2] ^ din[ 5] ^ din[ 1];
dout[29] = din[ 5] ^ din[ 1] ^ din[ 4] ^ din[ 0];
dout[28] = din[ 4] ^ din[ 0] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[27] = din[ 3] ^ din[ 7] ^ din[ 2] ^ din[ 5];
dout[26] = din[ 2] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[25] = din[ 1] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[24] = din[ 0] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[23] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[22] = din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[21] = din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 6];
dout[20] = din[ 4] ^ din[ 0] ^ din[ 6] ^ din[ 2] ^ din[ 5];
dout[19] = din[ 3] ^ din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 1] ^ din[ 4];
dout[18] = din[ 2] ^ din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 0] ^ din[ 3];
dout[17] = din[ 1] ^ din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 7] ^ din[ 6] ^ din[ 2];
dout[16] = din[ 0] ^ din[ 4] ^ din[ 6] ^ din[ 2] ^ din[ 3] ^ din[ 5] ^ din[ 1];
dout[15] = din[ 7] ^ din[ 3] ^ din[ 5] ^ din[ 1] ^ din[ 6] ^ din[ 2] ^ din[ 4] ^ din[ 0];
dout[14] = din[ 2] ^ din[ 4] ^ din[ 0] ^ din[ 5] ^ din[ 1] ^ din[ 3] ^ din[ 7];
dout[13] = din[ 1] ^ din[ 3] ^ din[ 7] ^ din[ 4] ^ din[ 0] ^ din[ 2];
dout[12] = din[ 0] ^ din[ 2] ^ din[ 3] ^ din[ 7] ^ din[ 1];
dout[11] = din[ 7] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[10] = din[ 0] ^ din[ 1] ^ din[ 7];
dout[ 9] = din[ 7] ^ din[ 0];
dout[ 8] = din[ 7];
dout[ 7] = din[ 6];
dout[ 6] = din[ 5];
dout[ 5] = din[ 4];
dout[ 4] = din[ 3];
dout[ 3] = din[ 2];
dout[ 2] = din[ 1];
dout[ 1] = din[ 0];
dout[ 0] = din[ 7] ^ din[ 6];
pn7 = dout;
end
endfunction
// pn15 function
function [63:0] pn15;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[15] ^ din[14];
dout[62] = din[14] ^ din[13];
dout[61] = din[13] ^ din[12];
dout[60] = din[12] ^ din[11];
dout[59] = din[11] ^ din[10];
dout[58] = din[10] ^ din[ 9];
dout[57] = din[ 9] ^ din[ 8];
dout[56] = din[ 8] ^ din[ 7];
dout[55] = din[ 7] ^ din[ 6];
dout[54] = din[ 6] ^ din[ 5];
dout[53] = din[ 5] ^ din[ 4];
dout[52] = din[ 4] ^ din[ 3];
dout[51] = din[ 3] ^ din[ 2];
dout[50] = din[ 2] ^ din[ 1];
dout[49] = din[ 1] ^ din[ 0];
dout[48] = din[ 0] ^ din[15] ^ din[14];
dout[47] = din[15] ^ din[13];
dout[46] = din[14] ^ din[12];
dout[45] = din[13] ^ din[11];
dout[44] = din[12] ^ din[10];
dout[43] = din[11] ^ din[ 9];
dout[42] = din[10] ^ din[ 8];
dout[41] = din[ 9] ^ din[ 7];
dout[40] = din[ 8] ^ din[ 6];
dout[39] = din[ 7] ^ din[ 5];
dout[38] = din[ 6] ^ din[ 4];
dout[37] = din[ 5] ^ din[ 3];
dout[36] = din[ 4] ^ din[ 2];
dout[35] = din[ 3] ^ din[ 1];
dout[34] = din[ 2] ^ din[ 0];
dout[33] = din[ 1] ^ din[15] ^ din[14];
dout[32] = din[ 0] ^ din[14] ^ din[13];
dout[31] = din[15] ^ din[13] ^ din[14] ^ din[12];
dout[30] = din[14] ^ din[12] ^ din[13] ^ din[11];
dout[29] = din[13] ^ din[11] ^ din[12] ^ din[10];
dout[28] = din[12] ^ din[10] ^ din[11] ^ din[ 9];
dout[27] = din[11] ^ din[ 9] ^ din[10] ^ din[ 8];
dout[26] = din[10] ^ din[ 8] ^ din[ 9] ^ din[ 7];
dout[25] = din[ 9] ^ din[ 7] ^ din[ 8] ^ din[ 6];
dout[24] = din[ 8] ^ din[ 6] ^ din[ 7] ^ din[ 5];
dout[23] = din[ 7] ^ din[ 5] ^ din[ 6] ^ din[ 4];
dout[22] = din[ 6] ^ din[ 4] ^ din[ 5] ^ din[ 3];
dout[21] = din[ 5] ^ din[ 3] ^ din[ 4] ^ din[ 2];
dout[20] = din[ 4] ^ din[ 2] ^ din[ 3] ^ din[ 1];
dout[19] = din[ 3] ^ din[ 1] ^ din[ 2] ^ din[ 0];
dout[18] = din[ 2] ^ din[ 0] ^ din[ 1] ^ din[15] ^ din[14];
dout[17] = din[ 1] ^ din[15] ^ din[ 0] ^ din[13];
dout[16] = din[ 0] ^ din[15] ^ din[12];
dout[15] = din[15] ^ din[11];
dout[14] = din[14] ^ din[10];
dout[13] = din[13] ^ din[ 9];
dout[12] = din[12] ^ din[ 8];
dout[11] = din[11] ^ din[ 7];
dout[10] = din[10] ^ din[ 6];
dout[ 9] = din[ 9] ^ din[ 5];
dout[ 8] = din[ 8] ^ din[ 4];
dout[ 7] = din[ 7] ^ din[ 3];
dout[ 6] = din[ 6] ^ din[ 2];
dout[ 5] = din[ 5] ^ din[ 1];
dout[ 4] = din[ 4] ^ din[ 0];
dout[ 3] = din[ 3] ^ din[15] ^ din[14];
dout[ 2] = din[ 2] ^ din[14] ^ din[13];
dout[ 1] = din[ 1] ^ din[13] ^ din[12];
dout[ 0] = din[ 0] ^ din[12] ^ din[11];
pn15 = dout;
end
endfunction
// pn23 function
function [63:0] pn23;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[23] ^ din[18];
dout[62] = din[22] ^ din[17];
dout[61] = din[21] ^ din[16];
dout[60] = din[20] ^ din[15];
dout[59] = din[19] ^ din[14];
dout[58] = din[18] ^ din[13];
dout[57] = din[17] ^ din[12];
dout[56] = din[16] ^ din[11];
dout[55] = din[15] ^ din[10];
dout[54] = din[14] ^ din[ 9];
dout[53] = din[13] ^ din[ 8];
dout[52] = din[12] ^ din[ 7];
dout[51] = din[11] ^ din[ 6];
dout[50] = din[10] ^ din[ 5];
dout[49] = din[ 9] ^ din[ 4];
dout[48] = din[ 8] ^ din[ 3];
dout[47] = din[ 7] ^ din[ 2];
dout[46] = din[ 6] ^ din[ 1];
dout[45] = din[ 5] ^ din[ 0];
dout[44] = din[ 4] ^ din[23] ^ din[18];
dout[43] = din[ 3] ^ din[22] ^ din[17];
dout[42] = din[ 2] ^ din[21] ^ din[16];
dout[41] = din[ 1] ^ din[20] ^ din[15];
dout[40] = din[ 0] ^ din[19] ^ din[14];
dout[39] = din[23] ^ din[13];
dout[38] = din[22] ^ din[12];
dout[37] = din[21] ^ din[11];
dout[36] = din[20] ^ din[10];
dout[35] = din[19] ^ din[ 9];
dout[34] = din[18] ^ din[ 8];
dout[33] = din[17] ^ din[ 7];
dout[32] = din[16] ^ din[ 6];
dout[31] = din[15] ^ din[ 5];
dout[30] = din[14] ^ din[ 4];
dout[29] = din[13] ^ din[ 3];
dout[28] = din[12] ^ din[ 2];
dout[27] = din[11] ^ din[ 1];
dout[26] = din[10] ^ din[ 0];
dout[25] = din[ 9] ^ din[23] ^ din[18];
dout[24] = din[ 8] ^ din[22] ^ din[17];
dout[23] = din[ 7] ^ din[21] ^ din[16];
dout[22] = din[ 6] ^ din[20] ^ din[15];
dout[21] = din[ 5] ^ din[19] ^ din[14];
dout[20] = din[ 4] ^ din[18] ^ din[13];
dout[19] = din[ 3] ^ din[17] ^ din[12];
dout[18] = din[ 2] ^ din[16] ^ din[11];
dout[17] = din[ 1] ^ din[15] ^ din[10];
dout[16] = din[ 0] ^ din[14] ^ din[ 9];
dout[15] = din[23] ^ din[13] ^ din[18] ^ din[ 8];
dout[14] = din[22] ^ din[12] ^ din[17] ^ din[ 7];
dout[13] = din[21] ^ din[11] ^ din[16] ^ din[ 6];
dout[12] = din[20] ^ din[10] ^ din[15] ^ din[ 5];
dout[11] = din[19] ^ din[ 9] ^ din[14] ^ din[ 4];
dout[10] = din[18] ^ din[ 8] ^ din[13] ^ din[ 3];
dout[ 9] = din[17] ^ din[ 7] ^ din[12] ^ din[ 2];
dout[ 8] = din[16] ^ din[ 6] ^ din[11] ^ din[ 1];
dout[ 7] = din[15] ^ din[ 5] ^ din[10] ^ din[ 0];
dout[ 6] = din[14] ^ din[ 4] ^ din[ 9] ^ din[23] ^ din[18];
dout[ 5] = din[13] ^ din[ 3] ^ din[ 8] ^ din[22] ^ din[17];
dout[ 4] = din[12] ^ din[ 2] ^ din[ 7] ^ din[21] ^ din[16];
dout[ 3] = din[11] ^ din[ 1] ^ din[ 6] ^ din[20] ^ din[15];
dout[ 2] = din[10] ^ din[ 0] ^ din[ 5] ^ din[19] ^ din[14];
dout[ 1] = din[ 9] ^ din[23] ^ din[ 4] ^ din[13];
dout[ 0] = din[ 8] ^ din[22] ^ din[ 3] ^ din[12];
pn23 = dout;
end
endfunction
// pn31 function
function [63:0] pn31;
input [63:0] din;
reg [63:0] dout;
begin
dout[63] = din[31] ^ din[28];
dout[62] = din[30] ^ din[27];
dout[61] = din[29] ^ din[26];
dout[60] = din[28] ^ din[25];
dout[59] = din[27] ^ din[24];
dout[58] = din[26] ^ din[23];
dout[57] = din[25] ^ din[22];
dout[56] = din[24] ^ din[21];
dout[55] = din[23] ^ din[20];
dout[54] = din[22] ^ din[19];
dout[53] = din[21] ^ din[18];
dout[52] = din[20] ^ din[17];
dout[51] = din[19] ^ din[16];
dout[50] = din[18] ^ din[15];
dout[49] = din[17] ^ din[14];
dout[48] = din[16] ^ din[13];
dout[47] = din[15] ^ din[12];
dout[46] = din[14] ^ din[11];
dout[45] = din[13] ^ din[10];
dout[44] = din[12] ^ din[ 9];
dout[43] = din[11] ^ din[ 8];
dout[42] = din[10] ^ din[ 7];
dout[41] = din[ 9] ^ din[ 6];
dout[40] = din[ 8] ^ din[ 5];
dout[39] = din[ 7] ^ din[ 4];
dout[38] = din[ 6] ^ din[ 3];
dout[37] = din[ 5] ^ din[ 2];
dout[36] = din[ 4] ^ din[ 1];
dout[35] = din[ 3] ^ din[ 0];
dout[34] = din[ 2] ^ din[31] ^ din[28];
dout[33] = din[ 1] ^ din[30] ^ din[27];
dout[32] = din[ 0] ^ din[29] ^ din[26];
dout[31] = din[31] ^ din[25];
dout[30] = din[30] ^ din[24];
dout[29] = din[29] ^ din[23];
dout[28] = din[28] ^ din[22];
dout[27] = din[27] ^ din[21];
dout[26] = din[26] ^ din[20];
dout[25] = din[25] ^ din[19];
dout[24] = din[24] ^ din[18];
dout[23] = din[23] ^ din[17];
dout[22] = din[22] ^ din[16];
dout[21] = din[21] ^ din[15];
dout[20] = din[20] ^ din[14];
dout[19] = din[19] ^ din[13];
dout[18] = din[18] ^ din[12];
dout[17] = din[17] ^ din[11];
dout[16] = din[16] ^ din[10];
dout[15] = din[15] ^ din[ 9];
dout[14] = din[14] ^ din[ 8];
dout[13] = din[13] ^ din[ 7];
dout[12] = din[12] ^ din[ 6];
dout[11] = din[11] ^ din[ 5];
dout[10] = din[10] ^ din[ 4];
dout[ 9] = din[ 9] ^ din[ 3];
dout[ 8] = din[ 8] ^ din[ 2];
dout[ 7] = din[ 7] ^ din[ 1];
dout[ 6] = din[ 6] ^ din[ 0];
dout[ 5] = din[ 5] ^ din[31] ^ din[28];
dout[ 4] = din[ 4] ^ din[30] ^ din[27];
dout[ 3] = din[ 3] ^ din[29] ^ din[26];
dout[ 2] = din[ 2] ^ din[28] ^ din[25];
dout[ 1] = din[ 1] ^ din[27] ^ din[24];
dout[ 0] = din[ 0] ^ din[26] ^ din[23];
pn31 = dout;
end
endfunction
// dac data select
always @(posedge dac_clk) begin
dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
case (dac_data_sel_s)
4'h7: dac_data <= dac_pn31_data;
4'h6: dac_data <= dac_pn23_data;
4'h5: dac_data <= dac_pn15_data;
4'h4: dac_data <= dac_pn7_data;
4'h3: dac_data <= 64'd0;
4'h2: dac_data <= dma_data;
4'h1: dac_data <= { dac_pat_data_2_s, dac_pat_data_1_s,
dac_pat_data_2_s, dac_pat_data_1_s};
default: dac_data <= dac_dds_data;
endcase
end
// pn registers
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_pn7_data <= {64{1'd1}};
dac_pn15_data <= {64{1'd1}};
dac_pn23_data <= {64{1'd1}};
dac_pn31_data <= {64{1'd1}};
end else begin
dac_pn7_data <= pn7(dac_pn7_data);
dac_pn15_data <= pn15(dac_pn15_data);
dac_pn23_data <= pn23(dac_pn23_data);
dac_pn31_data <= pn31(dac_pn31_data);
end
end
// dds
always @(posedge dac_clk) begin
if (dac_data_sync == 1'b1) begin
dac_dds_phase_0_0 <= dac_dds_init_1_s;
dac_dds_phase_0_1 <= dac_dds_init_2_s;
dac_dds_phase_1_0 <= dac_dds_phase_0_0 + dac_dds_incr_1_s;
dac_dds_phase_1_1 <= dac_dds_phase_0_1 + dac_dds_incr_2_s;
dac_dds_phase_2_0 <= dac_dds_phase_1_0 + dac_dds_incr_1_s;
dac_dds_phase_2_1 <= dac_dds_phase_1_1 + dac_dds_incr_2_s;
dac_dds_phase_3_0 <= dac_dds_phase_2_0 + dac_dds_incr_1_s;
dac_dds_phase_3_1 <= dac_dds_phase_2_1 + dac_dds_incr_2_s;
dac_dds_incr_0 <= {dac_dds_incr_1_s[13:0], 2'd0};
dac_dds_incr_1 <= {dac_dds_incr_2_s[13:0], 2'd0};
dac_dds_data <= 64'd0;
end else begin
dac_dds_phase_0_0 <= dac_dds_phase_0_0 + dac_dds_incr_0;
dac_dds_phase_0_1 <= dac_dds_phase_0_1 + dac_dds_incr_1;
dac_dds_phase_1_0 <= dac_dds_phase_1_0 + dac_dds_incr_0;
dac_dds_phase_1_1 <= dac_dds_phase_1_1 + dac_dds_incr_1;
dac_dds_phase_2_0 <= dac_dds_phase_2_0 + dac_dds_incr_0;
dac_dds_phase_2_1 <= dac_dds_phase_2_1 + dac_dds_incr_1;
dac_dds_phase_3_0 <= dac_dds_phase_3_0 + dac_dds_incr_0;
dac_dds_phase_3_1 <= dac_dds_phase_3_1 + dac_dds_incr_1;
dac_dds_incr_0 <= dac_dds_incr_0;
dac_dds_incr_1 <= dac_dds_incr_1;
dac_dds_data <= { dac_dds_data_3_s, dac_dds_data_2_s,
dac_dds_data_1_s, dac_dds_data_0_s};
end
end
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_0_s = 16'd0;
end else begin
ad_dds i_dds_0 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_0_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_0_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_0_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_1_s = 16'd0;
end else begin
ad_dds i_dds_1 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_1_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_1_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_1_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_2_s = 16'd0;
end else begin
ad_dds i_dds_2 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_2_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_2_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_2_s));
end
endgenerate
generate
if (DP_DISABLE == 1) begin
assign dac_dds_data_3_s = 16'd0;
end else begin
ad_dds i_dds_3 (
.clk (dac_clk),
.dds_format (dac_dds_format),
.dds_phase_0 (dac_dds_phase_3_0),
.dds_scale_0 (dac_dds_scale_1_s),
.dds_phase_1 (dac_dds_phase_3_1),
.dds_scale_1 (dac_dds_scale_2_s),
.dds_data (dac_dds_data_3_s));
end
endgenerate
// single channel processor
up_dac_channel #(.PCORE_DAC_CHID(CHID)) i_up_dac_channel (
.dac_clk (dac_clk),
.dac_rst (dac_rst),
.dac_dds_scale_1 (dac_dds_scale_1_s),
.dac_dds_init_1 (dac_dds_init_1_s),
.dac_dds_incr_1 (dac_dds_incr_1_s),
.dac_dds_scale_2 (dac_dds_scale_2_s),
.dac_dds_init_2 (dac_dds_init_2_s),
.dac_dds_incr_2 (dac_dds_incr_2_s),
.dac_pat_data_1 (dac_pat_data_1_s),
.dac_pat_data_2 (dac_pat_data_2_s),
.dac_data_sel (dac_data_sel_s),
.dac_iqcor_enb (),
.dac_iqcor_coeff_1 (),
.dac_iqcor_coeff_2 (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_interpolation_m (),
.up_usr_interpolation_n (),
.dac_usr_datatype_be (1'b0),
.dac_usr_datatype_signed (1'b1),
.dac_usr_datatype_shift (8'd0),
.dac_usr_datatype_total_bits (8'd16),
.dac_usr_datatype_bits (8'd16),
.dac_usr_interpolation_m (16'd1),
.dac_usr_interpolation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 09:37:58 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_stub.v
// Design : system_vga_sync_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_sync,Vivado 2016.4" *)
module system_vga_sync_0_0(clk_25, rst, active, hsync, vsync, xaddr, yaddr)
/* synthesis syn_black_box black_box_pad_pin="clk_25,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]" */;
input clk_25;
input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_mem #(
parameter DATA_WIDTH = 16,
parameter ADDRESS_WIDTH = 5) (
input clka,
input wea,
input [(ADDRESS_WIDTH-1):0] addra,
input [(DATA_WIDTH-1):0] dina,
input clkb,
input reb,
input [(ADDRESS_WIDTH-1):0] addrb,
output reg [(DATA_WIDTH-1):0] doutb);
(* ram_style = "block" *)
reg [(DATA_WIDTH-1):0] m_ram[0:((2**ADDRESS_WIDTH)-1)];
always @(posedge clka) begin
if (wea == 1'b1) begin
m_ram[addra] <= dina;
end
end
always @(posedge clkb) begin
if (reb == 1'b1) begin
doutb <= m_ram[addrb];
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns/1ns
// iverilog fp16baddsub.v fp16baddsub_test.v
module FP16BAddSub_Test;
reg clk, rst;
reg [15:0] s0_arg_0;
reg [15:0] s0_arg_1;
reg s0_arg_2;
wire [15:0] s0_ret_0;
wire [15:0] s0_ret_1;
wire s0_ret_2;
wire s0_ret_3;
reg [15:0] s1_arg_0;
reg [15:0] s1_arg_1;
reg s1_arg_2;
reg s1_arg_3;
wire s1_ret_0;
wire s1_ret_1;
wire [14:0] s1_ret_2;
wire [14:0] s1_ret_3;
wire [7:0] s1_ret_4;
wire s1_ret_5;
wire s1_ret_6;
reg s2_arg_0;
reg s2_arg_1;
reg [14:0] s2_arg_2;
reg [14:0] s2_arg_3;
reg [7:0] s2_arg_4;
reg s2_arg_5;
reg s2_arg_6;
wire [15:0] s2_ret_0;
wire s2_ret_1;
wire s2_ret_2;
wire [7:0] s2_ret_3;
wire s2_ret_4;
wire s2_ret_5;
reg [15:0] s3_arg_0;
reg s3_arg_1;
reg s3_arg_2;
reg [7:0] s3_arg_3;
reg s3_arg_4;
reg s3_arg_5;
wire [14:0] s3_ret_0;
wire s3_ret_1;
wire s3_ret_2;
wire [7:0] s3_ret_3;
wire s3_ret_4;
wire s3_ret_5;
wire s3_ret_6;
reg [14:0] s4_arg_0;
reg s4_arg_1;
reg s4_arg_2;
reg [7:0] s4_arg_3;
reg s4_arg_4;
reg s4_arg_5;
reg s4_arg_6;
wire [15:0] s4_ret_0;
reg xs;
reg [7:0] xe;
reg [6:0] xf;
reg ys;
reg [7:0] ye;
reg [6:0] yf;
reg is_sub;
wire rs;
wire [7:0] re;
wire [6:0] rf;
assign rs = s4_ret_0[15:15];
assign re = s4_ret_0[14:7];
assign rf = s4_ret_0[6:0];
FP16BAddSubS0Of5
inst_0(.clk(clk), .rst(rst),
.arg_0(s0_arg_0), .arg_1(s0_arg_1), .arg_2(s0_arg_2),
.ret_0(s0_ret_0), .ret_1(s0_ret_1), .ret_2(s0_ret_2), .ret_3(s0_ret_3));
FP16BAddSubS1Of5
inst_1(.clk(clk), .rst(rst),
.arg_0(s1_arg_0), .arg_1(s1_arg_1), .arg_2(s1_arg_2), .arg_3(s1_arg_3),
.ret_0(s1_ret_0), .ret_1(s1_ret_1), .ret_2(s1_ret_2), .ret_3(s1_ret_3), .ret_4(s1_ret_4), .ret_5(s1_ret_5), .ret_6(s1_ret_6));
FP16BAddSubS2Of5
inst_2(.clk(clk), .rst(rst),
.arg_0(s2_arg_0), .arg_1(s2_arg_1), .arg_2(s2_arg_2), .arg_3(s2_arg_3), .arg_4(s2_arg_4), .arg_5(s2_arg_5), .arg_6(s2_arg_6),
.ret_0(s2_ret_0), .ret_1(s2_ret_1), .ret_2(s2_ret_2), .ret_3(s2_ret_3), .ret_4(s2_ret_4), .ret_5(s2_ret_5));
FP16BAddSubS3Of5
inst_3(.clk(clk), .rst(rst),
.arg_0(s3_arg_0), .arg_1(s3_arg_1), .arg_2(s3_arg_2), .arg_3(s3_arg_3), .arg_4(s3_arg_4), .arg_5(s3_arg_5),
.ret_0(s3_ret_0), .ret_1(s3_ret_1), .ret_2(s3_ret_2), .ret_3(s3_ret_3), .ret_4(s3_ret_4), .ret_5(s3_ret_5), .ret_6(s3_ret_6));
FP16BAddSubS4Of5
inst_4(.clk(clk), .rst(rst),
.arg_0(s4_arg_0), .arg_1(s4_arg_1), .arg_2(s4_arg_2), .arg_3(s4_arg_3), .arg_4(s4_arg_4), .arg_5(s4_arg_5), .arg_6(s4_arg_6),
.ret_0(s4_ret_0));
always @(s0_ret_0 or s0_ret_1 or s0_ret_2 or s0_ret_3) begin
s1_arg_0 <= s0_ret_0;
s1_arg_1 <= s0_ret_1;
s1_arg_2 <= s0_ret_2;
s1_arg_3 <= s0_ret_3;
$display("S0: %d %d %d %d", s0_ret_0, s0_ret_1, s0_ret_2, s0_ret_3);
end
always @(s1_ret_0 or s1_ret_1 or s1_ret_2 or s1_ret_3 or s1_ret_4 or s1_ret_5 or s1_ret_6) begin
s2_arg_0 <= s1_ret_0;
s2_arg_1 <= s1_ret_1;
s2_arg_2 <= s1_ret_2;
s2_arg_3 <= s1_ret_3;
s2_arg_4 <= s1_ret_4;
s2_arg_5 <= s1_ret_5;
s2_arg_6 <= s1_ret_6;
$display("S1: %d %d %d %d %d %d %d", s1_ret_0, s1_ret_1, s1_ret_2, s1_ret_3, s1_ret_4, s1_ret_5, s1_ret_6);
end
always @(s2_ret_0 or s2_ret_1 or s2_ret_2 or s2_ret_3 or s2_ret_4 or s2_ret_5) begin
s3_arg_0 <= s2_ret_0;
s3_arg_1 <= s2_ret_1;
s3_arg_2 <= s2_ret_2;
s3_arg_3 <= s2_ret_3;
s3_arg_4 <= s2_ret_4;
s3_arg_5 <= s2_ret_5;
$display("S2: %d %d %d %d %d %d", s2_ret_0, s2_ret_1, s2_ret_2, s2_ret_3, s2_ret_4, s2_ret_5);
end
always @(s3_ret_0 or s3_ret_1 or s3_ret_2 or s3_ret_3 or s3_ret_4 or s3_ret_5 or s3_ret_6) begin
s4_arg_0 <= s3_ret_0;
s4_arg_1 <= s3_ret_1;
s4_arg_2 <= s3_ret_2;
s4_arg_3 <= s3_ret_3;
s4_arg_4 <= s3_ret_4;
s4_arg_5 <= s3_ret_5;
s4_arg_6 <= s3_ret_6;
$display("S3: %d %d %d %d %d %d", s3_ret_0, s3_ret_1, s3_ret_2, s3_ret_3, s3_ret_4, s3_ret_5, s3_ret_6);
end
always @(s4_ret_0) begin
end
always @(xs or xe or xf or ys or ye or yf or is_sub) begin
s0_arg_0 = {xs, xe, xf};
s0_arg_1 = {ys, ye, yf};
s0_arg_2 = is_sub;
end
initial begin
// 0.0 + 0.0
is_sub <= 0;
xs <= 0; xe <= 0; xf <= 0;
ys <= 0; ye <= 0; yf <= 0;
#1
$display("0.0+0.0= %d %s", s4_ret_0, (rs == 0 && re == 0 && rf == 0) ? "OK" : "FAIL");
// 1.0 + 1.0
is_sub <= 0;
xs <= 0; xe <= 127; xf <= 0;
ys <= 0; ye <= 127; yf <= 0;
#1
$display("1.0+1.0= %d %s", s4_ret_0, (rs == 0 && re == 128 && rf == 0) ? "OK" : "FAIL");
// 1.0 + 2.0
is_sub <= 0;
xs <= 0; xe <= 127; xf <= 0;
ys <= 0; ye <= 128; yf <= 0;
#1
$display("1.0+2.0= %d %s", s4_ret_0, (rs == 0 && re == 128 && rf == 64) ? "OK" : "FAIL");
// 2.0 + 1.0
is_sub <= 0;
xs <= 0; xe <= 128; xf <= 0;
ys <= 0; ye <= 127; yf <= 0;
#1
$display("2.0+1.0= %d %s", s4_ret_0, (rs == 0 && re == 128 && rf == 64) ? "OK" : "FAIL");
// 2.0 - 1.0
is_sub <= 1;
xs <= 0; xe <= 128; xf <= 0;
ys <= 0; ye <= 127; yf <= 0;
#1
$display("2.0-1.0= %d %s", s4_ret_0, (rs == 0 && re == 127 && rf == 0) ? "OK" : "FAIL");
// 2.0 + - 1.0
is_sub <= 0;
xs <= 0; xe <= 128; xf <= 0;
ys <= 1; ye <= 127; yf <= 0;
#1
$display("2.0 + -1.0= %d %s", s4_ret_0, (rs == 0 && re == 127 && rf == 0) ? "OK" : "FAIL");
// 1.0 - 2.0
is_sub <= 1;
xs <= 0; xe <= 127; xf <= 0;
ys <= 0; ye <= 128; yf <= 0;
#1
$display("1.0-2.0= %d %s", s4_ret_0, (rs == 1 && re == 127 && rf == 0) ? "OK" : "FAIL");
// 2^-14 - 2.0
is_sub <= 1;
xs <= 0; xe <= 1; xf <= 64;
ys <= 0; ye <= 1; yf <= 63;
#1
$display("192/128 * 2^-127 - 191/64*2^127= %d %s", s4_ret_0, (rs == 0 && re == 0 && rf == 0) ? "OK" : "FAIL");
// Use this line to debug a specific case.
$display("%d %d %d", rs, re, rf);
end
endmodule // FP16BAddSub_Test
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbp (
VPWR,
VGND,
Q ,
Q_N ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
wire buf_Q ;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_pg `UNIT_DELAY u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_V |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "registers.v"
//include "reg_defines_reference_router.v"
module ip_lpm
#(parameter DATA_WIDTH = 64,
parameter NUM_QUEUES = 5,
parameter LUT_DEPTH = `ROUTER_OP_LUT_ROUTE_TABLE_DEPTH,
parameter LUT_DEPTH_BITS = log2(LUT_DEPTH)
)
(// --- Interface to the previous stage
input [DATA_WIDTH-1:0] in_data,
// --- Interface to arp_lut
output reg [31:0] next_hop_ip,
output reg [NUM_QUEUES-1:0] lpm_output_port,
output reg lpm_vld,
output reg lpm_hit,
// --- Interface to preprocess block
input word_IP_SRC_DST,
input word_IP_DST_LO,
// --- Interface to registers
// --- Read port
input [LUT_DEPTH_BITS-1:0] lpm_rd_addr, // address in table to read
input lpm_rd_req, // request a read
output [31:0] lpm_rd_ip, // ip to match in the CAM
output [31:0] lpm_rd_mask, // subnet mask
output [NUM_QUEUES-1:0] lpm_rd_oq, // output queue
output [31:0] lpm_rd_next_hop_ip, // ip addr of next hop
output lpm_rd_ack, // pulses high
// --- Write port
input [LUT_DEPTH_BITS-1:0] lpm_wr_addr,
input lpm_wr_req,
input [NUM_QUEUES-1:0] lpm_wr_oq,
input [31:0] lpm_wr_next_hop_ip, // ip addr of next hop
input [31:0] lpm_wr_ip, // data to match in the CAM
input [31:0] lpm_wr_mask,
output lpm_wr_ack,
// --- Misc
input reset,
input clk
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
//---------------------- Wires and regs----------------------------
wire cam_busy;
wire cam_match;
wire [LUT_DEPTH-1:0] cam_match_addr;
wire [31:0] cam_cmp_din, cam_cmp_data_mask;
wire [31:0] cam_din, cam_data_mask;
wire cam_we;
wire [LUT_DEPTH_BITS-1:0] cam_wr_addr;
wire [NUM_QUEUES-1:0] lookup_port_result;
wire [31:0] next_hop_ip_result;
reg dst_ip_vld;
reg [31:0] dst_ip;
wire [31:0] lpm_rd_mask_inverted;
//------------------------- Modules-------------------------------
assign lpm_rd_mask = ~lpm_rd_mask_inverted;
// 1 cycle read latency, 16 cycles write latency
// priority encoded for the smallest address.
/*
srl_cam_unencoded_32x32 lpm_cam
(
// Outputs
.busy (cam_busy),
.match (cam_match),
.match_addr (cam_match_addr),
// Inputs
.clk (clk),
.cmp_din (cam_cmp_din),
.din (cam_din),
.cmp_data_mask (cam_cmp_data_mask),
.data_mask (cam_data_mask),
.we (cam_we),
.wr_addr (cam_wr_addr));
*/
wire ready_reg;
ram_based_cam lpm_cam
(
.clk(clk),
.rst(reset),
.start_write(cam_we),
.waddr(cam_wr_addr),
.wdata(cam_din),
.wcare(cam_data_mask),
.lookup_data(cam_cmp_din),
.match_lines(cam_match_addr),
.ready(ready_reg),
.match_found(cam_match)
);
assign cam_busy = 1'b0;
assign ready_out = ready_reg;
unencoded_cam_lut_sm_lpm
#(.CMP_WIDTH (32), // IPv4 addr width
.DATA_WIDTH (32+NUM_QUEUES), // next hop ip and output queue
.LUT_DEPTH (LUT_DEPTH),
.DEFAULT_DATA (1)
) cam_lut_sm_lpm
(// --- Interface for lookups
.lookup_req (dst_ip_vld),
.lookup_cmp_data (dst_ip),
.lookup_cmp_dmask (32'h0),
.lookup_ack (lpm_vld_result),
.lookup_hit (lpm_hit_result),
.lookup_data ({lookup_port_result, next_hop_ip_result}),
// --- Interface to registers
// --- Read port
.rd_addr (lpm_rd_addr), // address in table to read
.rd_req (lpm_rd_req), // request a read
.rd_data ({lpm_rd_oq, lpm_rd_next_hop_ip}), // data found for the entry
.rd_cmp_data (lpm_rd_ip), // matching data for the entry
.rd_cmp_dmask (lpm_rd_mask_inverted), // don't cares entry
.rd_ack (lpm_rd_ack), // pulses high
// --- Write port
.wr_addr (lpm_wr_addr),
.wr_req (lpm_wr_req),
.wr_data ({lpm_wr_oq, lpm_wr_next_hop_ip}), // data found for the entry
.wr_cmp_data (lpm_wr_ip), // matching data for the entry
.wr_cmp_dmask (~lpm_wr_mask), // don't cares for the entry
.wr_ack (lpm_wr_ack),
// --- CAM interface
.cam_busy (cam_busy),
.cam_match (cam_match),
.cam_match_addr (cam_match_addr),
.cam_cmp_din (cam_cmp_din),
.cam_din (cam_din),
.cam_we (cam_we),
.cam_wr_addr (cam_wr_addr),
.cam_cmp_data_mask (cam_cmp_data_mask),
.cam_data_mask (cam_data_mask),
// --- Misc
.reset (reset),
.clk (clk));
//------------------------- Logic --------------------------------
/*****************************************************************
* find the dst IP address and do the lookup
*****************************************************************/
always @(posedge clk) begin
if(reset) begin
dst_ip <= 0;
dst_ip_vld <= 0;
end
else begin
if(word_IP_SRC_DST) begin
dst_ip[31:16] <= in_data[15:0];
end
if(word_IP_DST_LO) begin
dst_ip[15:0] <= in_data[DATA_WIDTH-1:DATA_WIDTH-16];
dst_ip_vld <= 1;
end
else begin
dst_ip_vld <= 0;
end
end // else: !if(reset)
end // always @ (posedge clk)
/*****************************************************************
* latch the outputs
*****************************************************************/
always @(posedge clk) begin
lpm_output_port <= lookup_port_result;
next_hop_ip <= (next_hop_ip_result == 0) ? dst_ip : next_hop_ip_result;
lpm_hit <= lpm_hit_result;
if(reset) begin
lpm_vld <= 0;
end
else begin
lpm_vld <= lpm_vld_result;
end // else: !if(reset)
end // always @ (posedge clk)
endmodule // ip_lpm
|
`include "rv32_opcodes.vh"
`include "constants.vh"
`default_nettype none
module src_a_mux(
input wire [`SRC_A_SEL_WIDTH-1:0] src_a_sel,
input wire [`ADDR_LEN-1:0] pc,
input wire [`DATA_LEN-1:0] rs1,
output reg [`DATA_LEN-1:0] alu_src_a
);
always @(*) begin
case (src_a_sel)
`SRC_A_RS1 : alu_src_a = rs1;
`SRC_A_PC : alu_src_a = pc;
default : alu_src_a = 0;
endcase // case (src_a_sel)
end
endmodule // src_a_mux
module src_b_mux(
input wire [`SRC_B_SEL_WIDTH-1:0] src_b_sel,
input wire [`DATA_LEN-1:0] imm,
input wire [`DATA_LEN-1:0] rs2,
output reg [`DATA_LEN-1:0] alu_src_b
);
always @(*) begin
case (src_b_sel)
`SRC_B_RS2 : alu_src_b = rs2;
`SRC_B_IMM : alu_src_b = imm;
`SRC_B_FOUR : alu_src_b = 4;
default : alu_src_b = 0;
endcase // case (src_b_sel)
end
endmodule // src_b_mux
`default_nettype wire
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:35 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_vga_sync_reset_0_0 -prefix
// system_vga_sync_reset_0_0_ system_vga_sync_reset_0_0_sim_netlist.v
// Design : system_vga_sync_reset_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_vga_sync_reset_0_0,vga_sync_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "vga_sync_reset,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_vga_sync_reset_0_0
(clk,
rst,
active,
hsync,
vsync,
xaddr,
yaddr);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 rst RST" *) input rst;
output active;
output hsync;
output vsync;
output [9:0]xaddr;
output [9:0]yaddr;
wire active;
wire clk;
wire hsync;
wire rst;
wire vsync;
wire [9:0]xaddr;
wire [9:0]yaddr;
system_vga_sync_reset_0_0_vga_sync_reset U0
(.active(active),
.clk(clk),
.hsync(hsync),
.rst(rst),
.vsync(vsync),
.xaddr(xaddr),
.yaddr(yaddr));
endmodule
module system_vga_sync_reset_0_0_vga_sync_reset
(xaddr,
yaddr,
active,
hsync,
vsync,
clk,
rst);
output [9:0]xaddr;
output [9:0]yaddr;
output active;
output hsync;
output vsync;
input clk;
input rst;
wire active;
wire active_i_1_n_0;
wire active_i_2_n_0;
wire clk;
wire \h_count_reg[0]_i_1_n_0 ;
wire \h_count_reg[9]_i_1_n_0 ;
wire \h_count_reg[9]_i_3_n_0 ;
wire \h_count_reg[9]_i_4_n_0 ;
wire hsync;
wire hsync_i_1_n_0;
wire hsync_i_2_n_0;
wire hsync_i_3_n_0;
wire [9:1]plusOp;
wire [9:0]plusOp__0;
wire rst;
wire \v_count_reg[9]_i_1_n_0 ;
wire \v_count_reg[9]_i_2_n_0 ;
wire \v_count_reg[9]_i_4_n_0 ;
wire \v_count_reg[9]_i_5_n_0 ;
wire \v_count_reg[9]_i_6_n_0 ;
wire vsync;
wire vsync_i_1_n_0;
wire vsync_i_2_n_0;
wire [9:0]xaddr;
wire [9:0]yaddr;
LUT6 #(
.INIT(64'h0000222A00000000))
active_i_1
(.I0(active_i_2_n_0),
.I1(xaddr[9]),
.I2(xaddr[7]),
.I3(xaddr[8]),
.I4(yaddr[9]),
.I5(rst),
.O(active_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h7FFF))
active_i_2
(.I0(yaddr[7]),
.I1(yaddr[5]),
.I2(yaddr[6]),
.I3(yaddr[8]),
.O(active_i_2_n_0));
FDRE #(
.INIT(1'b0))
active_reg
(.C(clk),
.CE(1'b1),
.D(active_i_1_n_0),
.Q(active),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\h_count_reg[0]_i_1
(.I0(xaddr[0]),
.O(\h_count_reg[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\h_count_reg[1]_i_1
(.I0(xaddr[0]),
.I1(xaddr[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h78))
\h_count_reg[2]_i_1
(.I0(xaddr[1]),
.I1(xaddr[0]),
.I2(xaddr[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\h_count_reg[3]_i_1
(.I0(xaddr[2]),
.I1(xaddr[0]),
.I2(xaddr[1]),
.I3(xaddr[3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\h_count_reg[4]_i_1
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\h_count_reg[5]_i_1
(.I0(xaddr[4]),
.I1(xaddr[2]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[3]),
.I5(xaddr[5]),
.O(plusOp[5]));
LUT3 #(
.INIT(8'hD2))
\h_count_reg[6]_i_1
(.I0(xaddr[5]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[6]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBF40))
\h_count_reg[7]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(xaddr[7]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF7F0080))
\h_count_reg[8]_i_1
(.I0(xaddr[7]),
.I1(xaddr[6]),
.I2(xaddr[5]),
.I3(\h_count_reg[9]_i_3_n_0 ),
.I4(xaddr[8]),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h10000000FFFFFFFF))
\h_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(xaddr[7]),
.I2(xaddr[8]),
.I3(xaddr[9]),
.I4(\h_count_reg[9]_i_4_n_0 ),
.I5(rst),
.O(\h_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hDFFFFFFF20000000))
\h_count_reg[9]_i_2
(.I0(xaddr[8]),
.I1(\h_count_reg[9]_i_3_n_0 ),
.I2(xaddr[5]),
.I3(xaddr[6]),
.I4(xaddr[7]),
.I5(xaddr[9]),
.O(plusOp[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\h_count_reg[9]_i_3
(.I0(xaddr[3]),
.I1(xaddr[1]),
.I2(xaddr[0]),
.I3(xaddr[2]),
.I4(xaddr[4]),
.O(\h_count_reg[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
\h_count_reg[9]_i_4
(.I0(xaddr[5]),
.I1(xaddr[6]),
.O(\h_count_reg[9]_i_4_n_0 ));
FDRE \h_count_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(\h_count_reg[0]_i_1_n_0 ),
.Q(xaddr[0]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(plusOp[1]),
.Q(xaddr[1]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(plusOp[2]),
.Q(xaddr[2]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[3]
(.C(clk),
.CE(1'b1),
.D(plusOp[3]),
.Q(xaddr[3]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[4]
(.C(clk),
.CE(1'b1),
.D(plusOp[4]),
.Q(xaddr[4]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[5]
(.C(clk),
.CE(1'b1),
.D(plusOp[5]),
.Q(xaddr[5]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[6]
(.C(clk),
.CE(1'b1),
.D(plusOp[6]),
.Q(xaddr[6]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[7]
(.C(clk),
.CE(1'b1),
.D(plusOp[7]),
.Q(xaddr[7]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[8]
(.C(clk),
.CE(1'b1),
.D(plusOp[8]),
.Q(xaddr[8]),
.R(\h_count_reg[9]_i_1_n_0 ));
FDRE \h_count_reg_reg[9]
(.C(clk),
.CE(1'b1),
.D(plusOp[9]),
.Q(xaddr[9]),
.R(\h_count_reg[9]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'hABEAFFFF))
hsync_i_1
(.I0(hsync_i_2_n_0),
.I1(xaddr[5]),
.I2(xaddr[6]),
.I3(hsync_i_3_n_0),
.I4(rst),
.O(hsync_i_1_n_0));
LUT3 #(
.INIT(8'hDF))
hsync_i_2
(.I0(xaddr[9]),
.I1(xaddr[8]),
.I2(xaddr[7]),
.O(hsync_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h0001FFFF))
hsync_i_3
(.I0(xaddr[2]),
.I1(xaddr[3]),
.I2(xaddr[0]),
.I3(xaddr[1]),
.I4(xaddr[4]),
.O(hsync_i_3_n_0));
FDRE #(
.INIT(1'b0))
hsync_reg
(.C(clk),
.CE(1'b1),
.D(hsync_i_1_n_0),
.Q(hsync),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT1 #(
.INIT(2'h1))
\v_count_reg[0]_i_1
(.I0(yaddr[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\v_count_reg[1]_i_1
(.I0(yaddr[0]),
.I1(yaddr[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'h78))
\v_count_reg[2]_i_1
(.I0(yaddr[1]),
.I1(yaddr[0]),
.I2(yaddr[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7F80))
\v_count_reg[3]_i_1
(.I0(yaddr[2]),
.I1(yaddr[0]),
.I2(yaddr[1]),
.I3(yaddr[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFF8000))
\v_count_reg[4]_i_1
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\v_count_reg[5]_i_1
(.I0(yaddr[4]),
.I1(yaddr[2]),
.I2(yaddr[0]),
.I3(yaddr[1]),
.I4(yaddr[3]),
.I5(yaddr[5]),
.O(plusOp__0[5]));
LUT3 #(
.INIT(8'hD2))
\v_count_reg[6]_i_1
(.I0(yaddr[5]),
.I1(\v_count_reg[9]_i_6_n_0 ),
.I2(yaddr[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hF708))
\v_count_reg[7]_i_1
(.I0(yaddr[5]),
.I1(yaddr[6]),
.I2(\v_count_reg[9]_i_6_n_0 ),
.I3(yaddr[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hBFFF4000))
\v_count_reg[8]_i_1
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[8]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h00400000FFFFFFFF))
\v_count_reg[9]_i_1
(.I0(\h_count_reg[9]_i_3_n_0 ),
.I1(\v_count_reg[9]_i_4_n_0 ),
.I2(\h_count_reg[9]_i_4_n_0 ),
.I3(yaddr[0]),
.I4(\v_count_reg[9]_i_5_n_0 ),
.I5(rst),
.O(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000001000))
\v_count_reg[9]_i_2
(.I0(xaddr[5]),
.I1(xaddr[6]),
.I2(xaddr[9]),
.I3(xaddr[8]),
.I4(xaddr[7]),
.I5(\h_count_reg[9]_i_3_n_0 ),
.O(\v_count_reg[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFF40000000))
\v_count_reg[9]_i_3
(.I0(\v_count_reg[9]_i_6_n_0 ),
.I1(yaddr[7]),
.I2(yaddr[5]),
.I3(yaddr[6]),
.I4(yaddr[8]),
.I5(yaddr[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h0002000000000000))
\v_count_reg[9]_i_4
(.I0(yaddr[9]),
.I1(xaddr[7]),
.I2(yaddr[7]),
.I3(yaddr[8]),
.I4(xaddr[9]),
.I5(xaddr[8]),
.O(\v_count_reg[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000000000020))
\v_count_reg[9]_i_5
(.I0(yaddr[3]),
.I1(yaddr[4]),
.I2(yaddr[2]),
.I3(yaddr[1]),
.I4(yaddr[6]),
.I5(yaddr[5]),
.O(\v_count_reg[9]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
\v_count_reg[9]_i_6
(.I0(yaddr[3]),
.I1(yaddr[1]),
.I2(yaddr[0]),
.I3(yaddr[2]),
.I4(yaddr[4]),
.O(\v_count_reg[9]_i_6_n_0 ));
FDRE \v_count_reg_reg[0]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[0]),
.Q(yaddr[0]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[1]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[1]),
.Q(yaddr[1]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[2]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[2]),
.Q(yaddr[2]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[3]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[3]),
.Q(yaddr[3]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[4]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[4]),
.Q(yaddr[4]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[5]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[5]),
.Q(yaddr[5]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[6]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[6]),
.Q(yaddr[6]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[7]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[7]),
.Q(yaddr[7]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[8]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[8]),
.Q(yaddr[8]),
.R(\v_count_reg[9]_i_1_n_0 ));
FDRE \v_count_reg_reg[9]
(.C(clk),
.CE(\v_count_reg[9]_i_2_n_0 ),
.D(plusOp__0[9]),
.Q(yaddr[9]),
.R(\v_count_reg[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFBFFFFFFFF))
vsync_i_1
(.I0(vsync_i_2_n_0),
.I1(yaddr[1]),
.I2(yaddr[2]),
.I3(yaddr[9]),
.I4(yaddr[4]),
.I5(rst),
.O(vsync_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h7FFFFFFF))
vsync_i_2
(.I0(yaddr[8]),
.I1(yaddr[6]),
.I2(yaddr[5]),
.I3(yaddr[7]),
.I4(yaddr[3]),
.O(vsync_i_2_n_0));
FDRE #(
.INIT(1'b0))
vsync_reg
(.C(clk),
.CE(1'b1),
.D(vsync_i_1_n_0),
.Q(vsync),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module Forward(
input EX2MEM_RegWrite,
input MEM2WB_RegWrite,
input [4:0] EX2MEM_Rd, // !!! AddrC i.e. EX2MEM_Rd
MEM2WB_Rd, // !!! AddrC i.e. MEM2WB_Rd
ID2EX_Rs,
IF2ID_Rs,
ID2EX_Rt,
IF2ID_Rt,
ID2EX_Rd,
output reg[1:0] ForwardA,
ForwardB,
output reg ForwardC,
ForwardD
);
// ForwardX: 2->ALUOut, 1->wdata, 0->DataBusA
// 2->last, 1->last last, 0->normal
always @(*) begin
if((EX2MEM_RegWrite)&&(EX2MEM_Rd!=5'h0)&&(EX2MEM_Rd==ID2EX_Rs))
ForwardA <= 2'h2;
else if( (MEM2WB_RegWrite) & (|MEM2WB_Rd) & (MEM2WB_Rd==ID2EX_Rs) & ~(EX2MEM_Rd==ID2EX_Rs&&EX2MEM_RegWrite))
ForwardA <= 2'h1;
else
ForwardA <= 2'h0;
end
always @(*) begin
if((EX2MEM_RegWrite)&(|EX2MEM_Rd)&(EX2MEM_Rd==ID2EX_Rt))
ForwardB <= 2'h2;
else if((MEM2WB_RegWrite) & (|MEM2WB_Rd) & (MEM2WB_Rd==ID2EX_Rt) & ~(EX2MEM_Rd==ID2EX_Rt&&EX2MEM_RegWrite) )
ForwardB <= 2'h1;
else
ForwardB <= 2'h0;
end
always @ (*)
if(MEM2WB_RegWrite & (|MEM2WB_Rd) & (MEM2WB_Rd == IF2ID_Rs)) // Rd ie AddrC to be written
ForwardC = 1'b1;
else
ForwardC = 1'b0;
always @ (*)
if(MEM2WB_RegWrite & (|MEM2WB_Rd) & (MEM2WB_Rd == IF2ID_Rt)) // Rd ie AddrC to be written
ForwardD = 1'b1;
else
ForwardD = 1'b0;
endmodule
// no IF2ID_Rs & IF2ID_Rt
// directly connect from `instruction` outside this module
//为产生气泡，对寄存器进行清除，产生气泡可以延后时钟周期方便转发
//jump为第二阶段，branch为第三阶段，清除寄存器延后时钟周期
module Hazard(
input ID2EX_MemRead,
Branch,
Jump,
input[4:0] ID2EX_Rt,
IF2ID_Rs,
IF2ID_Rt,
output reg PCWrite,
IF2ID_flush,
IF2ID_write,
ID2EX_flush
);
//
always @(*) begin
if(ID2EX_MemRead&((ID2EX_Rt==IF2ID_Rs)|(ID2EX_Rt==IF2ID_Rt))) begin
PCWrite = 1'b0;
IF2ID_flush = 1'b0;
IF2ID_write = 1'b0;
ID2EX_flush = 1'b1;
end else if(Jump) begin
PCWrite = 1'b1;
IF2ID_flush = 1'b1;
IF2ID_write = 1'b0;
ID2EX_flush = 1'b0;
end else if(Branch) begin
PCWrite = 1'b1;
IF2ID_flush = 1'b1;
IF2ID_write = 1'b0;
ID2EX_flush = 1'b1;
end else begin
PCWrite = 1'b1;
IF2ID_flush = 1'b0;
IF2ID_write = 1'b1;
ID2EX_flush = 1'b0;
end
end
endmodule
|
(** * Rel: Properties of Relations *)
(** This short (and optional) chapter develops some basic definitions
and a few theorems about binary relations in Coq. The key
definitions are repeated where they are actually used (in the
[Smallstep] chapter of _Programming Language Foundations_),
so readers who are already comfortable with these ideas can safely
skim or skip this chapter. However, relations are also a good
source of exercises for developing facility with Coq's basic
reasoning facilities, so it may be useful to look at this material
just after the [IndProp] chapter. *)
Set Warnings "-notation-overridden,-parsing".
From LF Require Export IndProp.
(* ################################################################# *)
(** * Relations *)
(** A binary _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X -> X -> Prop.
(** Confusingly, the Coq standard library hijacks the generic term
"relation" for this specific instance of the idea. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, whereas the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-than-or-equal-to
relation, which we usually write [n1 <= n2]. *)
Print le.
(* ====> Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m *)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(** (Why did we write it this way instead of starting with [Inductive
le : relation nat...]? Because we wanted to put the first [nat]
to the left of the [:], which makes Coq generate a somewhat nicer
induction principle for reasoning about [<=].) *)
(* ################################################################# *)
(** * Basic Properties *)
(** As anyone knows who has taken an undergraduate discrete math
course, there is a lot to be said about relations in general,
including ways of classifying relations (as reflexive, transitive,
etc.), theorems that can be proved generically about certain sorts
of relations, constructions that build one relation from another,
etc. For example... *)
(* ----------------------------------------------------------------- *)
(** *** Partial Functions *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., [R x y1]
and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Check partial_function.
(** For example, the [next_nat] relation defined earlier is a partial
function. *)
Print next_nat.
(* ====> Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n) *)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed.
(** However, the [<=] relation on numbers is not a partial
function. (Assume, for a contradiction, that [<=] is a partial
function. But then, since [0 <= 0] and [0 <= 1], it follows that
[0 = 1]. This is nonsense, so our assumption was
contradictory.) *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense. {
apply Hc with (x := 0).
- apply le_n.
- apply le_S. apply le_n. }
discriminate Nonsense. Qed.
(** **** Exercise: 2 stars, standard, optional (total_relation_not_partial)
Show that the [total_relation] defined in (an exercise in)
[IndProp] is not a partial function. *)
Theorem total_relation_not_a_partial_function :
~ (partial_function total_relation).
Proof.
intro. unfold partial_function in H.
assert (0 = 1) as Nonsense.
apply H with (x := 0).
{apply total.}
apply total.
discriminate Nonsense.
Qed.
(* [] *)
(** **** Exercise: 2 stars, standard, optional (empty_relation_partial)
Show that the [empty_relation] defined in (an exercise in)
[IndProp] is a partial function. *)
Theorem empty_relation_a_partial_function :
partial_function empty_relation.
Proof.
unfold partial_function.
intros.
inversion H.
Qed.
Print empty_relation_a_partial_function.
(* [] *)
(* ----------------------------------------------------------------- *)
(** *** Reflexive Relations *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(* ----------------------------------------------------------------- *)
(** *** Transitive Relations *)
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
- (* le_n *) apply Hnm.
- (* le_S *) apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, standard, optional (le_trans_hard_way)
We can also prove [lt_trans] more laboriously by induction,
without using [le_trans]. Do this. *)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
- apply le_S. apply Hnm.
- apply le_S. apply IHHm'o.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (lt_trans'')
Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
- inversion Hmo.
- inversion Hmo.
+ subst. apply le_S. apply Hnm.
+ subst. apply le_S. apply IHo'. apply H0.
Qed.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
- apply le_S. apply le_n.
- apply H.
Qed.
(** **** Exercise: 1 star, standard, optional (le_S_n) *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
intros.
inversion H.
- apply le_reflexive.
- subst. apply le_trans with (S n).
+ apply le_S. apply le_n.
+ apply H1.
Qed.
Print le.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (le_Sn_n_inf)
Provide an informal proof of the following theorem:
Theorem: For every [n], [~ (S n <= n)]
A formal proof of this is an optional exercise below, but try
writing an informal proof without doing the formal proof first.
Proof: *)
(* Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n | le_S : forall m : nat, n <= m -> n <= S m
*)
(*
We do induction on n.
Case 1: when n := 0, we show 1 <= 0 is contradictory.
1 <= 0 is contradictory because:
- le_n : 1 = 0 is contradictory
- le_S : to unify n <= S m with 1 <= 0,
S m = 0 is contradictory
Case 2: assume ~(S n <= n), we show that (S (S n) <= S n) is contradictory.
by Sn_le_Sm__n_le_m, to prove the goal, we now only need to show
(S n <= n) is contradictory, which is exactly the assumption.
*)
(* [] *)
(** **** Exercise: 1 star, standard, optional (le_Sn_n) *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
intros. intro.
induction n.
- inversion H.
- apply IHn. apply Sn_le_Sm__n_le_m. apply H.
Qed.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, let's look at a few other common ones... *)
(* ----------------------------------------------------------------- *)
(** *** Symmetric and Antisymmetric Relations *)
(** A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, standard, optional (le_not_symmetric) *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
unfold symmetric.
intro.
assert (1 <= 0).
{ apply H. apply le_S. apply le_n. }
inversion H0.
Qed.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, standard, optional (le_antisymmetric) *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
unfold antisymmetric.
intros.
generalize dependent b.
induction a.
- intros. destruct b.
+ reflexivity.
+ inversion H0.
- intros. destruct b.
+ inversion H.
+ apply Sn_le_Sm__n_le_m in H.
apply Sn_le_Sm__n_le_m in H0.
f_equal.
apply (IHa b H H0).
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (le_step) *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
unfold lt.
intros.
inversion H.
- subst. apply (Sn_le_Sm__n_le_m _ _ H0).
- subst. apply Sn_le_Sm__n_le_m.
apply (le_trans _ (S m0) _ H H0).
Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Equivalence Relations *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(* ----------------------------------------------------------------- *)
(** *** Partial Orders and Preorders *)
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
- (* refl *) apply le_reflexive.
- split.
+ (* antisym *) apply le_antisymmetric.
+ (* transitive. *) apply le_trans. Qed.
(* ################################################################# *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step x y (H : R x y) : clos_refl_trans R x y
| rt_refl x : clos_refl_trans R x x
| rt_trans x y z
(Hxy : clos_refl_trans R x y)
(Hyz : clos_refl_trans R y z) :
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m.
split.
- (* -> *) intro.
induction H.
+ apply rt_refl.
+ apply (rt_trans _ n m (S m)).
* apply IHle.
* apply rt_step. apply nn.
- (* <- *) intro.
induction H.
+ inversion H. apply le_S. apply le_n.
+ apply le_n.
+ apply (le_trans x y z IHclos_refl_trans1 IHclos_refl_trans2).
Qed.
(* Proof given by the book - it's the same as mine.
intros n m. split.
- (* -> *)
intro H. induction H.
+ (* le_n *) apply rt_refl.
+ (* le_S *)
apply rt_trans with m. apply IHle. apply rt_step.
apply nn.
- (* <- *)
intro H. induction H.
+ (* rt_step *) inversion H. apply le_S. apply le_n.
+ (* rt_refl *) apply le_n.
+ (* rt_trans *)
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
*)
(** The above definition of reflexive, transitive closure is natural:
it says, explicitly, that the reflexive and transitive closure of
[R] is the least relation that includes [R] and that is closed
under rules of reflexivity and transitivity. But it turns out
that this definition is not very convenient for doing proofs,
since the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions. Here is a more useful definition: *)
Inductive clos_refl_trans_1n {A : Type}
(R : relation A) (x : A)
: A -> Prop :=
| rt1n_refl : clos_refl_trans_1n R x x
| rt1n_trans (y z : A)
(Hxy : R x y) (Hrest : clos_refl_trans_1n R y z) :
clos_refl_trans_1n R x z.
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [clos_refl_trans_1n] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Lemma rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> clos_refl_trans_1n R x y.
Proof.
intros X R x y H.
apply rt1n_trans with y. apply H. apply rt1n_refl. Qed.
(** **** Exercise: 2 stars, standard, optional (rsc_trans) *)
Lemma rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
clos_refl_trans_1n R x y ->
clos_refl_trans_1n R y z ->
clos_refl_trans_1n R x z.
Proof.
intros.
generalize dependent z.
induction H.
- intros. apply H0.
- intros. apply (rt1n_trans _ _ y _).
apply Hxy. apply IHclos_refl_trans_1n. apply H0.
Qed.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, standard, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> clos_refl_trans_1n R x y.
Proof.
intros.
split.
- (* -> *)
intros.
induction H.
+ apply (rt1n_trans _ _ _ _ H).
apply rt1n_refl.
+ apply rt1n_refl.
+ apply (rsc_trans _ _ _ _ _ IHclos_refl_trans1 IHclos_refl_trans2).
- (* <- *)
intros.
induction H.
+ apply rt_refl.
+ apply (rt_trans _ x y z (rt_step R _ _ Hxy)).
apply IHclos_refl_trans_1n.
Qed.
(** [] *)
(* 2020-09-09 20:51 *)
|
module WordOpcodeBufferTest;
`include "Framework.v"
reg reset;
reg clk;
always #10 clk = ~clk;
reg [31:0] addrA;
wire [31:0] addrB;
reg writeEnable = 0;
reg [31:0] dataIn;
reg requestA;
wire requestB;
wire [31:0] outA;
wire [31:0] outB;
wire busyA;
wire busyB;
wire [15:0] displayIn = 0;
wire [31:0] displayAddr;
wire displayWE;
Display dsp(clk, displayIn);
wire [31:0] mmioInB;
wire [31:0] mmioAddrB;
wire mmioWEB;
SimpleMmu #(.BUS_WIDTH(32))mmu(clk, reset, addrA, addrB, writeEnable, dataIn, requestA, requestB, outA, outB, busyA, busyB,
displayIn,displayAddr,displayWE, mmioInB, mmioAddrB, mmioWEB);
reg [31:0] ip;
wire busy;
wire [31:0] opcode;
reg startLoading;
WordOpcodeBuffer ob(clk, reset, ip, startLoading, outB, busyB, busy, opcode, addrB, requestB);
initial begin
$dumpfile("timing.vcd");
$dumpvars(0,mmu,ob);
reset = 1;
clk = 0;
#20 reset = 0;
ip = 0;
startLoading = 1;
#300 @(negedge busy) $display("Word: Got opcode: %h = %h", ip, opcode);
#10 startLoading = 0;
ip = 4;
startLoading = 1;
#300 @(negedge busy) $display("Word: Got opcode: %h = %h", ip, opcode);
ip = 8;
startLoading = 1;
#300 @(negedge busy) $display("Word: Got opcode: %h = %h", ip, opcode);
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV3SD3_BLACKBOX_V
`define SKY130_FD_SC_MS__CLKDLYINV3SD3_BLACKBOX_V
/**
* clkdlyinv3sd3: Clock Delay Inverter 3-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv3sd3 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV3SD3_BLACKBOX_V
|
//-----------------------------------------------------------------------------
// system_axi_interconnect_1_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "axi_interconnect_v1_06_a" *)
module system_axi_interconnect_1_wrapper
(
INTERCONNECT_ACLK,
INTERCONNECT_ARESETN,
S_AXI_ARESET_OUT_N,
M_AXI_ARESET_OUT_N,
IRQ,
S_AXI_ACLK,
S_AXI_AWID,
S_AXI_AWADDR,
S_AXI_AWLEN,
S_AXI_AWSIZE,
S_AXI_AWBURST,
S_AXI_AWLOCK,
S_AXI_AWCACHE,
S_AXI_AWPROT,
S_AXI_AWQOS,
S_AXI_AWUSER,
S_AXI_AWVALID,
S_AXI_AWREADY,
S_AXI_WID,
S_AXI_WDATA,
S_AXI_WSTRB,
S_AXI_WLAST,
S_AXI_WUSER,
S_AXI_WVALID,
S_AXI_WREADY,
S_AXI_BID,
S_AXI_BRESP,
S_AXI_BUSER,
S_AXI_BVALID,
S_AXI_BREADY,
S_AXI_ARID,
S_AXI_ARADDR,
S_AXI_ARLEN,
S_AXI_ARSIZE,
S_AXI_ARBURST,
S_AXI_ARLOCK,
S_AXI_ARCACHE,
S_AXI_ARPROT,
S_AXI_ARQOS,
S_AXI_ARUSER,
S_AXI_ARVALID,
S_AXI_ARREADY,
S_AXI_RID,
S_AXI_RDATA,
S_AXI_RRESP,
S_AXI_RLAST,
S_AXI_RUSER,
S_AXI_RVALID,
S_AXI_RREADY,
M_AXI_ACLK,
M_AXI_AWID,
M_AXI_AWADDR,
M_AXI_AWLEN,
M_AXI_AWSIZE,
M_AXI_AWBURST,
M_AXI_AWLOCK,
M_AXI_AWCACHE,
M_AXI_AWPROT,
M_AXI_AWREGION,
M_AXI_AWQOS,
M_AXI_AWUSER,
M_AXI_AWVALID,
M_AXI_AWREADY,
M_AXI_WID,
M_AXI_WDATA,
M_AXI_WSTRB,
M_AXI_WLAST,
M_AXI_WUSER,
M_AXI_WVALID,
M_AXI_WREADY,
M_AXI_BID,
M_AXI_BRESP,
M_AXI_BUSER,
M_AXI_BVALID,
M_AXI_BREADY,
M_AXI_ARID,
M_AXI_ARADDR,
M_AXI_ARLEN,
M_AXI_ARSIZE,
M_AXI_ARBURST,
M_AXI_ARLOCK,
M_AXI_ARCACHE,
M_AXI_ARPROT,
M_AXI_ARREGION,
M_AXI_ARQOS,
M_AXI_ARUSER,
M_AXI_ARVALID,
M_AXI_ARREADY,
M_AXI_RID,
M_AXI_RDATA,
M_AXI_RRESP,
M_AXI_RLAST,
M_AXI_RUSER,
M_AXI_RVALID,
M_AXI_RREADY,
S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA,
S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY,
INTERCONNECT_ARESET_OUT_N,
DEBUG_AW_TRANS_SEQ,
DEBUG_AW_ARB_GRANT,
DEBUG_AR_TRANS_SEQ,
DEBUG_AR_ARB_GRANT,
DEBUG_AW_TRANS_QUAL,
DEBUG_AW_ACCEPT_CNT,
DEBUG_AW_ACTIVE_THREAD,
DEBUG_AW_ACTIVE_TARGET,
DEBUG_AW_ACTIVE_REGION,
DEBUG_AW_ERROR,
DEBUG_AW_TARGET,
DEBUG_AR_TRANS_QUAL,
DEBUG_AR_ACCEPT_CNT,
DEBUG_AR_ACTIVE_THREAD,
DEBUG_AR_ACTIVE_TARGET,
DEBUG_AR_ACTIVE_REGION,
DEBUG_AR_ERROR,
DEBUG_AR_TARGET,
DEBUG_B_TRANS_SEQ,
DEBUG_R_BEAT_CNT,
DEBUG_R_TRANS_SEQ,
DEBUG_AW_ISSUING_CNT,
DEBUG_AR_ISSUING_CNT,
DEBUG_W_BEAT_CNT,
DEBUG_W_TRANS_SEQ,
DEBUG_BID_TARGET,
DEBUG_BID_ERROR,
DEBUG_RID_TARGET,
DEBUG_RID_ERROR,
DEBUG_SR_SC_ARADDR,
DEBUG_SR_SC_ARADDRCONTROL,
DEBUG_SR_SC_AWADDR,
DEBUG_SR_SC_AWADDRCONTROL,
DEBUG_SR_SC_BRESP,
DEBUG_SR_SC_RDATA,
DEBUG_SR_SC_RDATACONTROL,
DEBUG_SR_SC_WDATA,
DEBUG_SR_SC_WDATACONTROL,
DEBUG_SC_SF_ARADDR,
DEBUG_SC_SF_ARADDRCONTROL,
DEBUG_SC_SF_AWADDR,
DEBUG_SC_SF_AWADDRCONTROL,
DEBUG_SC_SF_BRESP,
DEBUG_SC_SF_RDATA,
DEBUG_SC_SF_RDATACONTROL,
DEBUG_SC_SF_WDATA,
DEBUG_SC_SF_WDATACONTROL,
DEBUG_SF_CB_ARADDR,
DEBUG_SF_CB_ARADDRCONTROL,
DEBUG_SF_CB_AWADDR,
DEBUG_SF_CB_AWADDRCONTROL,
DEBUG_SF_CB_BRESP,
DEBUG_SF_CB_RDATA,
DEBUG_SF_CB_RDATACONTROL,
DEBUG_SF_CB_WDATA,
DEBUG_SF_CB_WDATACONTROL,
DEBUG_CB_MF_ARADDR,
DEBUG_CB_MF_ARADDRCONTROL,
DEBUG_CB_MF_AWADDR,
DEBUG_CB_MF_AWADDRCONTROL,
DEBUG_CB_MF_BRESP,
DEBUG_CB_MF_RDATA,
DEBUG_CB_MF_RDATACONTROL,
DEBUG_CB_MF_WDATA,
DEBUG_CB_MF_WDATACONTROL,
DEBUG_MF_MC_ARADDR,
DEBUG_MF_MC_ARADDRCONTROL,
DEBUG_MF_MC_AWADDR,
DEBUG_MF_MC_AWADDRCONTROL,
DEBUG_MF_MC_BRESP,
DEBUG_MF_MC_RDATA,
DEBUG_MF_MC_RDATACONTROL,
DEBUG_MF_MC_WDATA,
DEBUG_MF_MC_WDATACONTROL,
DEBUG_MC_MP_ARADDR,
DEBUG_MC_MP_ARADDRCONTROL,
DEBUG_MC_MP_AWADDR,
DEBUG_MC_MP_AWADDRCONTROL,
DEBUG_MC_MP_BRESP,
DEBUG_MC_MP_RDATA,
DEBUG_MC_MP_RDATACONTROL,
DEBUG_MC_MP_WDATA,
DEBUG_MC_MP_WDATACONTROL,
DEBUG_MP_MR_ARADDR,
DEBUG_MP_MR_ARADDRCONTROL,
DEBUG_MP_MR_AWADDR,
DEBUG_MP_MR_AWADDRCONTROL,
DEBUG_MP_MR_BRESP,
DEBUG_MP_MR_RDATA,
DEBUG_MP_MR_RDATACONTROL,
DEBUG_MP_MR_WDATA,
DEBUG_MP_MR_WDATACONTROL
);
input INTERCONNECT_ACLK;
input INTERCONNECT_ARESETN;
output [3:0] S_AXI_ARESET_OUT_N;
output [0:0] M_AXI_ARESET_OUT_N;
output IRQ;
input [3:0] S_AXI_ACLK;
input [7:0] S_AXI_AWID;
input [127:0] S_AXI_AWADDR;
input [31:0] S_AXI_AWLEN;
input [11:0] S_AXI_AWSIZE;
input [7:0] S_AXI_AWBURST;
input [7:0] S_AXI_AWLOCK;
input [15:0] S_AXI_AWCACHE;
input [11:0] S_AXI_AWPROT;
input [15:0] S_AXI_AWQOS;
input [15:0] S_AXI_AWUSER;
input [3:0] S_AXI_AWVALID;
output [3:0] S_AXI_AWREADY;
input [7:0] S_AXI_WID;
input [255:0] S_AXI_WDATA;
input [31:0] S_AXI_WSTRB;
input [3:0] S_AXI_WLAST;
input [3:0] S_AXI_WUSER;
input [3:0] S_AXI_WVALID;
output [3:0] S_AXI_WREADY;
output [7:0] S_AXI_BID;
output [7:0] S_AXI_BRESP;
output [3:0] S_AXI_BUSER;
output [3:0] S_AXI_BVALID;
input [3:0] S_AXI_BREADY;
input [7:0] S_AXI_ARID;
input [127:0] S_AXI_ARADDR;
input [31:0] S_AXI_ARLEN;
input [11:0] S_AXI_ARSIZE;
input [7:0] S_AXI_ARBURST;
input [7:0] S_AXI_ARLOCK;
input [15:0] S_AXI_ARCACHE;
input [11:0] S_AXI_ARPROT;
input [15:0] S_AXI_ARQOS;
input [15:0] S_AXI_ARUSER;
input [3:0] S_AXI_ARVALID;
output [3:0] S_AXI_ARREADY;
output [7:0] S_AXI_RID;
output [255:0] S_AXI_RDATA;
output [7:0] S_AXI_RRESP;
output [3:0] S_AXI_RLAST;
output [3:0] S_AXI_RUSER;
output [3:0] S_AXI_RVALID;
input [3:0] S_AXI_RREADY;
input [0:0] M_AXI_ACLK;
output [1:0] M_AXI_AWID;
output [31:0] M_AXI_AWADDR;
output [7:0] M_AXI_AWLEN;
output [2:0] M_AXI_AWSIZE;
output [1:0] M_AXI_AWBURST;
output [1:0] M_AXI_AWLOCK;
output [3:0] M_AXI_AWCACHE;
output [2:0] M_AXI_AWPROT;
output [3:0] M_AXI_AWREGION;
output [3:0] M_AXI_AWQOS;
output [3:0] M_AXI_AWUSER;
output [0:0] M_AXI_AWVALID;
input [0:0] M_AXI_AWREADY;
output [1:0] M_AXI_WID;
output [63:0] M_AXI_WDATA;
output [7:0] M_AXI_WSTRB;
output [0:0] M_AXI_WLAST;
output [0:0] M_AXI_WUSER;
output [0:0] M_AXI_WVALID;
input [0:0] M_AXI_WREADY;
input [1:0] M_AXI_BID;
input [1:0] M_AXI_BRESP;
input [0:0] M_AXI_BUSER;
input [0:0] M_AXI_BVALID;
output [0:0] M_AXI_BREADY;
output [1:0] M_AXI_ARID;
output [31:0] M_AXI_ARADDR;
output [7:0] M_AXI_ARLEN;
output [2:0] M_AXI_ARSIZE;
output [1:0] M_AXI_ARBURST;
output [1:0] M_AXI_ARLOCK;
output [3:0] M_AXI_ARCACHE;
output [2:0] M_AXI_ARPROT;
output [3:0] M_AXI_ARREGION;
output [3:0] M_AXI_ARQOS;
output [3:0] M_AXI_ARUSER;
output [0:0] M_AXI_ARVALID;
input [0:0] M_AXI_ARREADY;
input [1:0] M_AXI_RID;
input [63:0] M_AXI_RDATA;
input [1:0] M_AXI_RRESP;
input [0:0] M_AXI_RLAST;
input [0:0] M_AXI_RUSER;
input [0:0] M_AXI_RVALID;
output [0:0] M_AXI_RREADY;
input [31:0] S_AXI_CTRL_AWADDR;
input S_AXI_CTRL_AWVALID;
output S_AXI_CTRL_AWREADY;
input [31:0] S_AXI_CTRL_WDATA;
input S_AXI_CTRL_WVALID;
output S_AXI_CTRL_WREADY;
output [1:0] S_AXI_CTRL_BRESP;
output S_AXI_CTRL_BVALID;
input S_AXI_CTRL_BREADY;
input [31:0] S_AXI_CTRL_ARADDR;
input S_AXI_CTRL_ARVALID;
output S_AXI_CTRL_ARREADY;
output [31:0] S_AXI_CTRL_RDATA;
output [1:0] S_AXI_CTRL_RRESP;
output S_AXI_CTRL_RVALID;
input S_AXI_CTRL_RREADY;
output INTERCONNECT_ARESET_OUT_N;
output [7:0] DEBUG_AW_TRANS_SEQ;
output [7:0] DEBUG_AW_ARB_GRANT;
output [7:0] DEBUG_AR_TRANS_SEQ;
output [7:0] DEBUG_AR_ARB_GRANT;
output [0:0] DEBUG_AW_TRANS_QUAL;
output [7:0] DEBUG_AW_ACCEPT_CNT;
output [15:0] DEBUG_AW_ACTIVE_THREAD;
output [7:0] DEBUG_AW_ACTIVE_TARGET;
output [7:0] DEBUG_AW_ACTIVE_REGION;
output [7:0] DEBUG_AW_ERROR;
output [7:0] DEBUG_AW_TARGET;
output [0:0] DEBUG_AR_TRANS_QUAL;
output [7:0] DEBUG_AR_ACCEPT_CNT;
output [15:0] DEBUG_AR_ACTIVE_THREAD;
output [7:0] DEBUG_AR_ACTIVE_TARGET;
output [7:0] DEBUG_AR_ACTIVE_REGION;
output [7:0] DEBUG_AR_ERROR;
output [7:0] DEBUG_AR_TARGET;
output [7:0] DEBUG_B_TRANS_SEQ;
output [7:0] DEBUG_R_BEAT_CNT;
output [7:0] DEBUG_R_TRANS_SEQ;
output [7:0] DEBUG_AW_ISSUING_CNT;
output [7:0] DEBUG_AR_ISSUING_CNT;
output [7:0] DEBUG_W_BEAT_CNT;
output [7:0] DEBUG_W_TRANS_SEQ;
output [7:0] DEBUG_BID_TARGET;
output DEBUG_BID_ERROR;
output [7:0] DEBUG_RID_TARGET;
output DEBUG_RID_ERROR;
output [31:0] DEBUG_SR_SC_ARADDR;
output [24:0] DEBUG_SR_SC_ARADDRCONTROL;
output [31:0] DEBUG_SR_SC_AWADDR;
output [24:0] DEBUG_SR_SC_AWADDRCONTROL;
output [5:0] DEBUG_SR_SC_BRESP;
output [63:0] DEBUG_SR_SC_RDATA;
output [6:0] DEBUG_SR_SC_RDATACONTROL;
output [63:0] DEBUG_SR_SC_WDATA;
output [10:0] DEBUG_SR_SC_WDATACONTROL;
output [31:0] DEBUG_SC_SF_ARADDR;
output [24:0] DEBUG_SC_SF_ARADDRCONTROL;
output [31:0] DEBUG_SC_SF_AWADDR;
output [24:0] DEBUG_SC_SF_AWADDRCONTROL;
output [5:0] DEBUG_SC_SF_BRESP;
output [63:0] DEBUG_SC_SF_RDATA;
output [6:0] DEBUG_SC_SF_RDATACONTROL;
output [63:0] DEBUG_SC_SF_WDATA;
output [10:0] DEBUG_SC_SF_WDATACONTROL;
output [31:0] DEBUG_SF_CB_ARADDR;
output [24:0] DEBUG_SF_CB_ARADDRCONTROL;
output [31:0] DEBUG_SF_CB_AWADDR;
output [24:0] DEBUG_SF_CB_AWADDRCONTROL;
output [5:0] DEBUG_SF_CB_BRESP;
output [63:0] DEBUG_SF_CB_RDATA;
output [6:0] DEBUG_SF_CB_RDATACONTROL;
output [63:0] DEBUG_SF_CB_WDATA;
output [10:0] DEBUG_SF_CB_WDATACONTROL;
output [31:0] DEBUG_CB_MF_ARADDR;
output [24:0] DEBUG_CB_MF_ARADDRCONTROL;
output [31:0] DEBUG_CB_MF_AWADDR;
output [24:0] DEBUG_CB_MF_AWADDRCONTROL;
output [5:0] DEBUG_CB_MF_BRESP;
output [63:0] DEBUG_CB_MF_RDATA;
output [6:0] DEBUG_CB_MF_RDATACONTROL;
output [63:0] DEBUG_CB_MF_WDATA;
output [10:0] DEBUG_CB_MF_WDATACONTROL;
output [31:0] DEBUG_MF_MC_ARADDR;
output [24:0] DEBUG_MF_MC_ARADDRCONTROL;
output [31:0] DEBUG_MF_MC_AWADDR;
output [24:0] DEBUG_MF_MC_AWADDRCONTROL;
output [5:0] DEBUG_MF_MC_BRESP;
output [63:0] DEBUG_MF_MC_RDATA;
output [6:0] DEBUG_MF_MC_RDATACONTROL;
output [63:0] DEBUG_MF_MC_WDATA;
output [10:0] DEBUG_MF_MC_WDATACONTROL;
output [31:0] DEBUG_MC_MP_ARADDR;
output [24:0] DEBUG_MC_MP_ARADDRCONTROL;
output [31:0] DEBUG_MC_MP_AWADDR;
output [24:0] DEBUG_MC_MP_AWADDRCONTROL;
output [5:0] DEBUG_MC_MP_BRESP;
output [63:0] DEBUG_MC_MP_RDATA;
output [6:0] DEBUG_MC_MP_RDATACONTROL;
output [63:0] DEBUG_MC_MP_WDATA;
output [10:0] DEBUG_MC_MP_WDATACONTROL;
output [31:0] DEBUG_MP_MR_ARADDR;
output [24:0] DEBUG_MP_MR_ARADDRCONTROL;
output [31:0] DEBUG_MP_MR_AWADDR;
output [24:0] DEBUG_MP_MR_AWADDRCONTROL;
output [5:0] DEBUG_MP_MR_BRESP;
output [63:0] DEBUG_MP_MR_RDATA;
output [6:0] DEBUG_MP_MR_RDATACONTROL;
output [63:0] DEBUG_MP_MR_WDATA;
output [10:0] DEBUG_MP_MR_WDATACONTROL;
axi_interconnect
#(
.C_BASEFAMILY ( "zynq" ),
.C_NUM_SLAVE_SLOTS ( 4 ),
.C_NUM_MASTER_SLOTS ( 1 ),
.C_AXI_ID_WIDTH ( 2 ),
.C_AXI_ADDR_WIDTH ( 32 ),
.C_AXI_DATA_MAX_WIDTH ( 64 ),
.C_S_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020 ),
.C_M_AXI_DATA_WIDTH ( 512'h00000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000020000000200000002000000040 ),
.C_INTERCONNECT_DATA_WIDTH ( 64 ),
.C_S_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_PROTOCOL ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 ),
.C_M_AXI_BASE_ADDR ( 16384'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff0000000000000000 ),
.C_M_AXI_HIGH_ADDR ( 16384'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003fffffff ),
.C_S_AXI_BASE_ID ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003000000020000000100000000 ),
.C_S_AXI_THREAD_ID_WIDTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_IS_INTERCONNECT ( 16'b0000000000000000 ),
.C_S_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e10005f5e10005f5e10005f5e100 ),
.C_S_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_M_AXI_ACLK_RATIO ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000105f5e100 ),
.C_M_AXI_IS_ACLK_ASYNC ( 16'b0000000000000000 ),
.C_INTERCONNECT_ACLK_RATIO ( 100000000 ),
.C_S_AXI_SUPPORTS_WRITE ( 16'b1111111111110101 ),
.C_S_AXI_SUPPORTS_READ ( 16'b1111111111111011 ),
.C_M_AXI_SUPPORTS_WRITE ( 16'b1111111111111111 ),
.C_M_AXI_SUPPORTS_READ ( 16'b1111111111111111 ),
.C_AXI_SUPPORTS_USER_SIGNALS ( 0 ),
.C_AXI_AWUSER_WIDTH ( 4 ),
.C_AXI_ARUSER_WIDTH ( 4 ),
.C_AXI_WUSER_WIDTH ( 1 ),
.C_AXI_RUSER_WIDTH ( 1 ),
.C_AXI_BUSER_WIDTH ( 1 ),
.C_AXI_CONNECTIVITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000008 ),
.C_S_AXI_SINGLE_THREAD ( 16'b0000000000000000 ),
.C_M_AXI_SUPPORTS_REORDERING ( 16'b1111111111111111 ),
.C_S_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111110000 ),
.C_M_AXI_SUPPORTS_NARROW_BURST ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000040000000100000001 ),
.C_S_AXI_READ_ACCEPTANCE ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000004000000010000000400000001 ),
.C_M_AXI_WRITE_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_M_AXI_READ_ISSUING ( 512'h00000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000001000000010000000100000008 ),
.C_S_AXI_ARB_PRIORITY ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_SECURE ( 16'b0000000000000000 ),
.C_S_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000000000000 ),
.C_S_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020000000000 ),
.C_S_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_S_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_WRITE_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_WRITE_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_WRITE_FIFO_DELAY ( 16'b0000000000000000 ),
.C_M_AXI_READ_FIFO_DEPTH ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_READ_FIFO_TYPE ( 16'b1111111111111111 ),
.C_M_AXI_READ_FIFO_DELAY ( 16'b0000000000000000 ),
.C_S_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_S_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AW_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_AR_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_W_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_R_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_M_AXI_B_REGISTER ( 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ),
.C_INTERCONNECT_R_REGISTER ( 0 ),
.C_INTERCONNECT_CONNECTIVITY_MODE ( 1 ),
.C_USE_CTRL_PORT ( 0 ),
.C_USE_INTERRUPT ( 1 ),
.C_RANGE_CHECK ( 0 ),
.C_S_AXI_CTRL_ADDR_WIDTH ( 32 ),
.C_S_AXI_CTRL_DATA_WIDTH ( 32 ),
.C_DEBUG ( 0 ),
.C_S_AXI_DEBUG_SLOT ( 0 ),
.C_M_AXI_DEBUG_SLOT ( 0 ),
.C_MAX_DEBUG_THREADS ( 1 )
)
axi_interconnect_1 (
.INTERCONNECT_ACLK ( INTERCONNECT_ACLK ),
.INTERCONNECT_ARESETN ( INTERCONNECT_ARESETN ),
.S_AXI_ARESET_OUT_N ( S_AXI_ARESET_OUT_N ),
.M_AXI_ARESET_OUT_N ( M_AXI_ARESET_OUT_N ),
.IRQ ( IRQ ),
.S_AXI_ACLK ( S_AXI_ACLK ),
.S_AXI_AWID ( S_AXI_AWID ),
.S_AXI_AWADDR ( S_AXI_AWADDR ),
.S_AXI_AWLEN ( S_AXI_AWLEN ),
.S_AXI_AWSIZE ( S_AXI_AWSIZE ),
.S_AXI_AWBURST ( S_AXI_AWBURST ),
.S_AXI_AWLOCK ( S_AXI_AWLOCK ),
.S_AXI_AWCACHE ( S_AXI_AWCACHE ),
.S_AXI_AWPROT ( S_AXI_AWPROT ),
.S_AXI_AWQOS ( S_AXI_AWQOS ),
.S_AXI_AWUSER ( S_AXI_AWUSER ),
.S_AXI_AWVALID ( S_AXI_AWVALID ),
.S_AXI_AWREADY ( S_AXI_AWREADY ),
.S_AXI_WID ( S_AXI_WID ),
.S_AXI_WDATA ( S_AXI_WDATA ),
.S_AXI_WSTRB ( S_AXI_WSTRB ),
.S_AXI_WLAST ( S_AXI_WLAST ),
.S_AXI_WUSER ( S_AXI_WUSER ),
.S_AXI_WVALID ( S_AXI_WVALID ),
.S_AXI_WREADY ( S_AXI_WREADY ),
.S_AXI_BID ( S_AXI_BID ),
.S_AXI_BRESP ( S_AXI_BRESP ),
.S_AXI_BUSER ( S_AXI_BUSER ),
.S_AXI_BVALID ( S_AXI_BVALID ),
.S_AXI_BREADY ( S_AXI_BREADY ),
.S_AXI_ARID ( S_AXI_ARID ),
.S_AXI_ARADDR ( S_AXI_ARADDR ),
.S_AXI_ARLEN ( S_AXI_ARLEN ),
.S_AXI_ARSIZE ( S_AXI_ARSIZE ),
.S_AXI_ARBURST ( S_AXI_ARBURST ),
.S_AXI_ARLOCK ( S_AXI_ARLOCK ),
.S_AXI_ARCACHE ( S_AXI_ARCACHE ),
.S_AXI_ARPROT ( S_AXI_ARPROT ),
.S_AXI_ARQOS ( S_AXI_ARQOS ),
.S_AXI_ARUSER ( S_AXI_ARUSER ),
.S_AXI_ARVALID ( S_AXI_ARVALID ),
.S_AXI_ARREADY ( S_AXI_ARREADY ),
.S_AXI_RID ( S_AXI_RID ),
.S_AXI_RDATA ( S_AXI_RDATA ),
.S_AXI_RRESP ( S_AXI_RRESP ),
.S_AXI_RLAST ( S_AXI_RLAST ),
.S_AXI_RUSER ( S_AXI_RUSER ),
.S_AXI_RVALID ( S_AXI_RVALID ),
.S_AXI_RREADY ( S_AXI_RREADY ),
.M_AXI_ACLK ( M_AXI_ACLK ),
.M_AXI_AWID ( M_AXI_AWID ),
.M_AXI_AWADDR ( M_AXI_AWADDR ),
.M_AXI_AWLEN ( M_AXI_AWLEN ),
.M_AXI_AWSIZE ( M_AXI_AWSIZE ),
.M_AXI_AWBURST ( M_AXI_AWBURST ),
.M_AXI_AWLOCK ( M_AXI_AWLOCK ),
.M_AXI_AWCACHE ( M_AXI_AWCACHE ),
.M_AXI_AWPROT ( M_AXI_AWPROT ),
.M_AXI_AWREGION ( M_AXI_AWREGION ),
.M_AXI_AWQOS ( M_AXI_AWQOS ),
.M_AXI_AWUSER ( M_AXI_AWUSER ),
.M_AXI_AWVALID ( M_AXI_AWVALID ),
.M_AXI_AWREADY ( M_AXI_AWREADY ),
.M_AXI_WID ( M_AXI_WID ),
.M_AXI_WDATA ( M_AXI_WDATA ),
.M_AXI_WSTRB ( M_AXI_WSTRB ),
.M_AXI_WLAST ( M_AXI_WLAST ),
.M_AXI_WUSER ( M_AXI_WUSER ),
.M_AXI_WVALID ( M_AXI_WVALID ),
.M_AXI_WREADY ( M_AXI_WREADY ),
.M_AXI_BID ( M_AXI_BID ),
.M_AXI_BRESP ( M_AXI_BRESP ),
.M_AXI_BUSER ( M_AXI_BUSER ),
.M_AXI_BVALID ( M_AXI_BVALID ),
.M_AXI_BREADY ( M_AXI_BREADY ),
.M_AXI_ARID ( M_AXI_ARID ),
.M_AXI_ARADDR ( M_AXI_ARADDR ),
.M_AXI_ARLEN ( M_AXI_ARLEN ),
.M_AXI_ARSIZE ( M_AXI_ARSIZE ),
.M_AXI_ARBURST ( M_AXI_ARBURST ),
.M_AXI_ARLOCK ( M_AXI_ARLOCK ),
.M_AXI_ARCACHE ( M_AXI_ARCACHE ),
.M_AXI_ARPROT ( M_AXI_ARPROT ),
.M_AXI_ARREGION ( M_AXI_ARREGION ),
.M_AXI_ARQOS ( M_AXI_ARQOS ),
.M_AXI_ARUSER ( M_AXI_ARUSER ),
.M_AXI_ARVALID ( M_AXI_ARVALID ),
.M_AXI_ARREADY ( M_AXI_ARREADY ),
.M_AXI_RID ( M_AXI_RID ),
.M_AXI_RDATA ( M_AXI_RDATA ),
.M_AXI_RRESP ( M_AXI_RRESP ),
.M_AXI_RLAST ( M_AXI_RLAST ),
.M_AXI_RUSER ( M_AXI_RUSER ),
.M_AXI_RVALID ( M_AXI_RVALID ),
.M_AXI_RREADY ( M_AXI_RREADY ),
.S_AXI_CTRL_AWADDR ( S_AXI_CTRL_AWADDR ),
.S_AXI_CTRL_AWVALID ( S_AXI_CTRL_AWVALID ),
.S_AXI_CTRL_AWREADY ( S_AXI_CTRL_AWREADY ),
.S_AXI_CTRL_WDATA ( S_AXI_CTRL_WDATA ),
.S_AXI_CTRL_WVALID ( S_AXI_CTRL_WVALID ),
.S_AXI_CTRL_WREADY ( S_AXI_CTRL_WREADY ),
.S_AXI_CTRL_BRESP ( S_AXI_CTRL_BRESP ),
.S_AXI_CTRL_BVALID ( S_AXI_CTRL_BVALID ),
.S_AXI_CTRL_BREADY ( S_AXI_CTRL_BREADY ),
.S_AXI_CTRL_ARADDR ( S_AXI_CTRL_ARADDR ),
.S_AXI_CTRL_ARVALID ( S_AXI_CTRL_ARVALID ),
.S_AXI_CTRL_ARREADY ( S_AXI_CTRL_ARREADY ),
.S_AXI_CTRL_RDATA ( S_AXI_CTRL_RDATA ),
.S_AXI_CTRL_RRESP ( S_AXI_CTRL_RRESP ),
.S_AXI_CTRL_RVALID ( S_AXI_CTRL_RVALID ),
.S_AXI_CTRL_RREADY ( S_AXI_CTRL_RREADY ),
.INTERCONNECT_ARESET_OUT_N ( INTERCONNECT_ARESET_OUT_N ),
.DEBUG_AW_TRANS_SEQ ( DEBUG_AW_TRANS_SEQ ),
.DEBUG_AW_ARB_GRANT ( DEBUG_AW_ARB_GRANT ),
.DEBUG_AR_TRANS_SEQ ( DEBUG_AR_TRANS_SEQ ),
.DEBUG_AR_ARB_GRANT ( DEBUG_AR_ARB_GRANT ),
.DEBUG_AW_TRANS_QUAL ( DEBUG_AW_TRANS_QUAL ),
.DEBUG_AW_ACCEPT_CNT ( DEBUG_AW_ACCEPT_CNT ),
.DEBUG_AW_ACTIVE_THREAD ( DEBUG_AW_ACTIVE_THREAD ),
.DEBUG_AW_ACTIVE_TARGET ( DEBUG_AW_ACTIVE_TARGET ),
.DEBUG_AW_ACTIVE_REGION ( DEBUG_AW_ACTIVE_REGION ),
.DEBUG_AW_ERROR ( DEBUG_AW_ERROR ),
.DEBUG_AW_TARGET ( DEBUG_AW_TARGET ),
.DEBUG_AR_TRANS_QUAL ( DEBUG_AR_TRANS_QUAL ),
.DEBUG_AR_ACCEPT_CNT ( DEBUG_AR_ACCEPT_CNT ),
.DEBUG_AR_ACTIVE_THREAD ( DEBUG_AR_ACTIVE_THREAD ),
.DEBUG_AR_ACTIVE_TARGET ( DEBUG_AR_ACTIVE_TARGET ),
.DEBUG_AR_ACTIVE_REGION ( DEBUG_AR_ACTIVE_REGION ),
.DEBUG_AR_ERROR ( DEBUG_AR_ERROR ),
.DEBUG_AR_TARGET ( DEBUG_AR_TARGET ),
.DEBUG_B_TRANS_SEQ ( DEBUG_B_TRANS_SEQ ),
.DEBUG_R_BEAT_CNT ( DEBUG_R_BEAT_CNT ),
.DEBUG_R_TRANS_SEQ ( DEBUG_R_TRANS_SEQ ),
.DEBUG_AW_ISSUING_CNT ( DEBUG_AW_ISSUING_CNT ),
.DEBUG_AR_ISSUING_CNT ( DEBUG_AR_ISSUING_CNT ),
.DEBUG_W_BEAT_CNT ( DEBUG_W_BEAT_CNT ),
.DEBUG_W_TRANS_SEQ ( DEBUG_W_TRANS_SEQ ),
.DEBUG_BID_TARGET ( DEBUG_BID_TARGET ),
.DEBUG_BID_ERROR ( DEBUG_BID_ERROR ),
.DEBUG_RID_TARGET ( DEBUG_RID_TARGET ),
.DEBUG_RID_ERROR ( DEBUG_RID_ERROR ),
.DEBUG_SR_SC_ARADDR ( DEBUG_SR_SC_ARADDR ),
.DEBUG_SR_SC_ARADDRCONTROL ( DEBUG_SR_SC_ARADDRCONTROL ),
.DEBUG_SR_SC_AWADDR ( DEBUG_SR_SC_AWADDR ),
.DEBUG_SR_SC_AWADDRCONTROL ( DEBUG_SR_SC_AWADDRCONTROL ),
.DEBUG_SR_SC_BRESP ( DEBUG_SR_SC_BRESP ),
.DEBUG_SR_SC_RDATA ( DEBUG_SR_SC_RDATA ),
.DEBUG_SR_SC_RDATACONTROL ( DEBUG_SR_SC_RDATACONTROL ),
.DEBUG_SR_SC_WDATA ( DEBUG_SR_SC_WDATA ),
.DEBUG_SR_SC_WDATACONTROL ( DEBUG_SR_SC_WDATACONTROL ),
.DEBUG_SC_SF_ARADDR ( DEBUG_SC_SF_ARADDR ),
.DEBUG_SC_SF_ARADDRCONTROL ( DEBUG_SC_SF_ARADDRCONTROL ),
.DEBUG_SC_SF_AWADDR ( DEBUG_SC_SF_AWADDR ),
.DEBUG_SC_SF_AWADDRCONTROL ( DEBUG_SC_SF_AWADDRCONTROL ),
.DEBUG_SC_SF_BRESP ( DEBUG_SC_SF_BRESP ),
.DEBUG_SC_SF_RDATA ( DEBUG_SC_SF_RDATA ),
.DEBUG_SC_SF_RDATACONTROL ( DEBUG_SC_SF_RDATACONTROL ),
.DEBUG_SC_SF_WDATA ( DEBUG_SC_SF_WDATA ),
.DEBUG_SC_SF_WDATACONTROL ( DEBUG_SC_SF_WDATACONTROL ),
.DEBUG_SF_CB_ARADDR ( DEBUG_SF_CB_ARADDR ),
.DEBUG_SF_CB_ARADDRCONTROL ( DEBUG_SF_CB_ARADDRCONTROL ),
.DEBUG_SF_CB_AWADDR ( DEBUG_SF_CB_AWADDR ),
.DEBUG_SF_CB_AWADDRCONTROL ( DEBUG_SF_CB_AWADDRCONTROL ),
.DEBUG_SF_CB_BRESP ( DEBUG_SF_CB_BRESP ),
.DEBUG_SF_CB_RDATA ( DEBUG_SF_CB_RDATA ),
.DEBUG_SF_CB_RDATACONTROL ( DEBUG_SF_CB_RDATACONTROL ),
.DEBUG_SF_CB_WDATA ( DEBUG_SF_CB_WDATA ),
.DEBUG_SF_CB_WDATACONTROL ( DEBUG_SF_CB_WDATACONTROL ),
.DEBUG_CB_MF_ARADDR ( DEBUG_CB_MF_ARADDR ),
.DEBUG_CB_MF_ARADDRCONTROL ( DEBUG_CB_MF_ARADDRCONTROL ),
.DEBUG_CB_MF_AWADDR ( DEBUG_CB_MF_AWADDR ),
.DEBUG_CB_MF_AWADDRCONTROL ( DEBUG_CB_MF_AWADDRCONTROL ),
.DEBUG_CB_MF_BRESP ( DEBUG_CB_MF_BRESP ),
.DEBUG_CB_MF_RDATA ( DEBUG_CB_MF_RDATA ),
.DEBUG_CB_MF_RDATACONTROL ( DEBUG_CB_MF_RDATACONTROL ),
.DEBUG_CB_MF_WDATA ( DEBUG_CB_MF_WDATA ),
.DEBUG_CB_MF_WDATACONTROL ( DEBUG_CB_MF_WDATACONTROL ),
.DEBUG_MF_MC_ARADDR ( DEBUG_MF_MC_ARADDR ),
.DEBUG_MF_MC_ARADDRCONTROL ( DEBUG_MF_MC_ARADDRCONTROL ),
.DEBUG_MF_MC_AWADDR ( DEBUG_MF_MC_AWADDR ),
.DEBUG_MF_MC_AWADDRCONTROL ( DEBUG_MF_MC_AWADDRCONTROL ),
.DEBUG_MF_MC_BRESP ( DEBUG_MF_MC_BRESP ),
.DEBUG_MF_MC_RDATA ( DEBUG_MF_MC_RDATA ),
.DEBUG_MF_MC_RDATACONTROL ( DEBUG_MF_MC_RDATACONTROL ),
.DEBUG_MF_MC_WDATA ( DEBUG_MF_MC_WDATA ),
.DEBUG_MF_MC_WDATACONTROL ( DEBUG_MF_MC_WDATACONTROL ),
.DEBUG_MC_MP_ARADDR ( DEBUG_MC_MP_ARADDR ),
.DEBUG_MC_MP_ARADDRCONTROL ( DEBUG_MC_MP_ARADDRCONTROL ),
.DEBUG_MC_MP_AWADDR ( DEBUG_MC_MP_AWADDR ),
.DEBUG_MC_MP_AWADDRCONTROL ( DEBUG_MC_MP_AWADDRCONTROL ),
.DEBUG_MC_MP_BRESP ( DEBUG_MC_MP_BRESP ),
.DEBUG_MC_MP_RDATA ( DEBUG_MC_MP_RDATA ),
.DEBUG_MC_MP_RDATACONTROL ( DEBUG_MC_MP_RDATACONTROL ),
.DEBUG_MC_MP_WDATA ( DEBUG_MC_MP_WDATA ),
.DEBUG_MC_MP_WDATACONTROL ( DEBUG_MC_MP_WDATACONTROL ),
.DEBUG_MP_MR_ARADDR ( DEBUG_MP_MR_ARADDR ),
.DEBUG_MP_MR_ARADDRCONTROL ( DEBUG_MP_MR_ARADDRCONTROL ),
.DEBUG_MP_MR_AWADDR ( DEBUG_MP_MR_AWADDR ),
.DEBUG_MP_MR_AWADDRCONTROL ( DEBUG_MP_MR_AWADDRCONTROL ),
.DEBUG_MP_MR_BRESP ( DEBUG_MP_MR_BRESP ),
.DEBUG_MP_MR_RDATA ( DEBUG_MP_MR_RDATA ),
.DEBUG_MP_MR_RDATACONTROL ( DEBUG_MP_MR_RDATACONTROL ),
.DEBUG_MP_MR_WDATA ( DEBUG_MP_MR_WDATA ),
.DEBUG_MP_MR_WDATACONTROL ( DEBUG_MP_MR_WDATACONTROL )
);
endmodule
|
`include "./Definition.v"
// color correction registering constants
`define CC1 430 // 860.0 / 512 * 256 = 10'b 0110101110
`define CC2 127 // 253.0 / 512 * 256 = 10'b 0001111111
`define CC3 48 // 95.0 / 512 * 256 = 10'b 0000110000
`define CC4 55 // 109.0 / 512 * 256 = 10'b 0000110111
`define CC5 464 // 928.0 / 512 * 256 = 10'b 0111010000
`define CC6 154 // 307.0 / 512 * 256 = 10'b 0010011010
`define CC7 10 // 20.0 / 512 * 256 = 10'b 0000001010
`define CC8 145 // 290.0 / 512 * 256 = 10'b 0010010001
`define CC9 391 // 782.0 / 512 * 256 = 10'b 0110000111
module ColorCorrection
(
input[ `size_int - 1 : 0 ]R,
input[ `size_int - 1 : 0 ]G,
input[ `size_int - 1 : 0 ]B,
output wire[ `size_int - 1 : 0 ]R_out,
output wire[ `size_int - 1 : 0 ]G_out,
output wire[ `size_int - 1 : 0 ]B_out
);
reg[ `size_int : 0 ]R_int;
reg[ `size_int : 0 ]G_int;
reg[ `size_int : 0 ]B_int;
always@( R or G or B )
begin
R_int = ( R * `CC1 - G * `CC2 - B * `CC3 ) >> `ScaleBit;
G_int = ( -R * `CC4 + G * `CC5 - B * `CC6 ) >> `ScaleBit;
B_int = ( R * `CC7 - G * `CC8 + B * `CC9 ) >> `ScaleBit;
end
assign R_out = ( R_int[ 17 : 16 ] == 2'b00 ) ? R_int : ( R_int[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
assign G_out = ( G_int[ 17 : 16 ] == 2'b00 ) ? G_int : ( G_int[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
assign B_out = ( B_int[ 17 : 16 ] == 2'b00 ) ? B_int : ( B_int[ 17 ] == 1'b1 ) ? `MinThreshold : `MaxThreshold;
endmodule
module ColorCorrection_testbench;
reg[ `size_int - 1 : 0 ]R;
reg[ `size_int - 1 : 0 ]G;
reg[ `size_int - 1 : 0 ]B;
wire[ `size_int - 1 : 0 ]R_out;
wire[ `size_int - 1 : 0 ]G_out;
wire[ `size_int - 1 : 0 ]B_out;
ColorCorrection ColorCorrection_test( R, G, B, R_out, G_out, B_out );
initial
begin
#100
begin
R = 200 << `ScaleBit;
G = 0 << `ScaleBit;
B = 0 << `ScaleBit;
end
//X=(200*( 860.0/512)+0*(-253.0/512)+0*( -95.0/512))*256=86000
//Y=(200*(-109.0/512)+0*( 928.0/512)+0*(-307.0/512))*256=-10900
//Z=(200*( 20.0/512)+0*(-290.0/512)+0*( 782.0/512))*256=2000
#100 $display( "R_out = %d", R_out );
#100 $display( "G_out = %d", G_out );
#100 $display( "B_out = %d", B_out );
#100
begin
R = 200 << `ScaleBit;
G = 180 << `ScaleBit;
B = 160 << `ScaleBit;
end
//X=(200*( 860.0/512)+180*(-253.0/512)+160*( -95.0/512))*256=55630
//Y=(200*(-109.0/512)+180*( 928.0/512)+160*(-307.0/512))*256=48060
//Z=(200*( 20.0/512)+180*(-290.0/512)+160*( 782.0/512))*256=38460
#100 $display( "R_out = %d", R_out );
#100 $display( "G_out = %d", G_out );
#100 $display( "B_out = %d", B_out );
#100 $stop;
#100 $finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlxtp (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_LP_V
`define SKY130_FD_SC_LP__NAND3_LP_V
/**
* nand3: 3-input NAND.
*
* Verilog wrapper for nand3 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_lp (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3_lp (
Y,
A,
B,
C
);
output Y;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3 base (
.Y(Y),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_LP_V
|
// ddr3_s4_uniphy_0002.v
// This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using SOPC Builder version 11.0sp1 208 at 2011.09.28.12:45:35
`timescale 1 ps / 1 ps
module ddr3_s4_uniphy_0002 (
input wire pll_ref_clk, // pll_ref_clk.clk
input wire global_reset_n, // global_reset.reset_n
input wire soft_reset_n, // soft_reset.reset_n
output wire afi_clk, // afi_clk.clk
output wire afi_half_clk, // afi_half_clk.clk
output wire afi_reset_n, // afi_reset.reset_n
output wire [12:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire [1:0] mem_dm, // .mem_dm
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [15:0] mem_dq, // .mem_dq
inout wire [1:0] mem_dqs, // .mem_dqs
inout wire [1:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire avl_ready, // avl.waitrequest_n
input wire avl_burstbegin, // .beginbursttransfer
input wire [23:0] avl_addr, // .address
output wire avl_rdata_valid, // .readdatavalid
output wire [63:0] avl_rdata, // .readdata
input wire [63:0] avl_wdata, // .writedata
input wire [7:0] avl_be, // .byteenable
input wire avl_read_req, // .read
input wire avl_write_req, // .write
input wire [2:0] avl_size, // .burstcount
output wire local_init_done, // status.local_init_done
output wire local_cal_success, // .local_cal_success
output wire local_cal_fail, // .local_cal_fail
input wire oct_rdn, // oct.rdn
input wire oct_rup, // .rup
output wire local_powerdn_ack, // local_powerdown.local_powerdn_ack
input wire local_powerdn_req // .local_powerdn_req
);
wire [25:0] c0_afi_afi_addr; // c0:afi_addr -> p0:afi_addr
wire [1:0] c0_afi_afi_odt; // c0:afi_odt -> p0:afi_odt
wire c0_afi_afi_cal_req; // c0:afi_cal_req -> p0:afi_cal_req
wire [5:0] p0_afi_afi_wlat; // p0:afi_wlat -> c0:afi_wlat
wire [1:0] p0_afi_afi_rdata_valid; // p0:afi_rdata_valid -> c0:afi_rdata_valid
wire [1:0] c0_afi_afi_rdata_en_full; // c0:afi_rdata_en_full -> p0:afi_rdata_en_full
wire [1:0] c0_afi_afi_we_n; // c0:afi_we_n -> p0:afi_we_n
wire [5:0] c0_afi_afi_ba; // c0:afi_ba -> p0:afi_ba
wire [1:0] c0_afi_afi_cke; // c0:afi_cke -> p0:afi_cke
wire [1:0] c0_afi_afi_cs_n; // c0:afi_cs_n -> p0:afi_cs_n
wire [63:0] c0_afi_afi_wdata; // c0:afi_wdata -> p0:afi_wdata
wire [1:0] c0_afi_afi_rdata_en; // c0:afi_rdata_en -> p0:afi_rdata_en
wire [1:0] c0_afi_afi_rst_n; // c0:afi_rst_n -> p0:afi_rst_n
wire [1:0] c0_afi_afi_cas_n; // c0:afi_cas_n -> p0:afi_cas_n
wire p0_afi_afi_cal_success; // p0:afi_cal_success -> c0:afi_cal_success
wire [1:0] c0_afi_afi_ras_n; // c0:afi_ras_n -> p0:afi_ras_n
wire [5:0] p0_afi_afi_rlat; // p0:afi_rlat -> c0:afi_rlat
wire [63:0] p0_afi_afi_rdata; // p0:afi_rdata -> c0:afi_rdata
wire p0_afi_afi_cal_fail; // p0:afi_cal_fail -> c0:afi_cal_fail
wire [3:0] c0_afi_afi_wdata_valid; // c0:afi_wdata_valid -> p0:afi_wdata_valid
wire [3:0] c0_afi_afi_dqs_burst; // c0:afi_dqs_burst -> p0:afi_dqs_burst
wire [7:0] c0_afi_afi_dm; // c0:afi_dm -> p0:afi_dm
ddr3_s4_uniphy_c0 c0 (
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.local_init_done (local_init_done), // status.local_init_done
.local_cal_success (local_cal_success), // .local_cal_success
.local_cal_fail (local_cal_fail), // .local_cal_fail
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.local_powerdn_ack (local_powerdn_ack), // local_powerdown.local_powerdn_ack
.local_powerdn_req (local_powerdn_req), // .local_powerdn_req
.avl_ready (avl_ready), // avl.waitrequest_n
.avl_burstbegin (avl_burstbegin), // .beginbursttransfer
.avl_addr (avl_addr), // .address
.avl_rdata_valid (avl_rdata_valid), // .readdatavalid
.avl_rdata (avl_rdata), // .readdata
.avl_wdata (avl_wdata), // .writedata
.avl_be (avl_be), // .byteenable
.avl_read_req (avl_read_req), // .read
.avl_write_req (avl_write_req), // .write
.avl_size (avl_size) // .burstcount
);
ddr3_s4_uniphy_p0 p0 (
.global_reset_n (global_reset_n), // global_reset.reset_n
.soft_reset_n (soft_reset_n), // soft_reset.reset_n
.afi_reset_n (afi_reset_n), // afi_reset.reset_n
.afi_clk (afi_clk), // afi_clk.clk
.afi_half_clk (afi_half_clk), // afi_half_clk.clk
.pll_ref_clk (pll_ref_clk), // pll_ref_clk.clk
.afi_addr (c0_afi_afi_addr), // afi.afi_addr
.afi_ba (c0_afi_afi_ba), // .afi_ba
.afi_cke (c0_afi_afi_cke), // .afi_cke
.afi_cs_n (c0_afi_afi_cs_n), // .afi_cs_n
.afi_ras_n (c0_afi_afi_ras_n), // .afi_ras_n
.afi_we_n (c0_afi_afi_we_n), // .afi_we_n
.afi_cas_n (c0_afi_afi_cas_n), // .afi_cas_n
.afi_rst_n (c0_afi_afi_rst_n), // .afi_rst_n
.afi_odt (c0_afi_afi_odt), // .afi_odt
.afi_dqs_burst (c0_afi_afi_dqs_burst), // .afi_dqs_burst
.afi_wdata_valid (c0_afi_afi_wdata_valid), // .afi_wdata_valid
.afi_wdata (c0_afi_afi_wdata), // .afi_wdata
.afi_dm (c0_afi_afi_dm), // .afi_dm
.afi_rdata (p0_afi_afi_rdata), // .afi_rdata
.afi_rdata_en (c0_afi_afi_rdata_en), // .afi_rdata_en
.afi_rdata_en_full (c0_afi_afi_rdata_en_full), // .afi_rdata_en_full
.afi_rdata_valid (p0_afi_afi_rdata_valid), // .afi_rdata_valid
.afi_cal_success (p0_afi_afi_cal_success), // .afi_cal_success
.afi_cal_fail (p0_afi_afi_cal_fail), // .afi_cal_fail
.afi_cal_req (c0_afi_afi_cal_req), // .afi_cal_req
.afi_wlat (p0_afi_afi_wlat), // .afi_wlat
.afi_rlat (p0_afi_afi_rlat), // .afi_rlat
.oct_rdn (oct_rdn), // oct.rdn
.oct_rup (oct_rup), // .rup
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_dm (mem_dm), // .mem_dm
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.dll_delayctrl (), // (terminated)
.seriesterminationcontrol (), // (terminated)
.parallelterminationcontrol () // (terminated)
);
endmodule
|
module IF_slice_DW01_inc_0 ( A, SUM );
input [15:0] A;
output [15:0] SUM;
wire [15:2] carry;
XOR2D1BWP U1 ( .A1(carry[15]), .A2(A[15]), .Z(SUM[15]) );
HA1D0BWP U1_1_14 ( .A(A[14]), .B(carry[14]), .CO(carry[15]), .S(SUM[14]) );
HA1D0BWP U1_1_1 ( .A(A[1]), .B(A[0]), .CO(carry[2]), .S(SUM[1]) );
HA1D0BWP U1_1_2 ( .A(A[2]), .B(carry[2]), .CO(carry[3]), .S(SUM[2]) );
HA1D0BWP U1_1_3 ( .A(A[3]), .B(carry[3]), .CO(carry[4]), .S(SUM[3]) );
HA1D0BWP U1_1_4 ( .A(A[4]), .B(carry[4]), .CO(carry[5]), .S(SUM[4]) );
HA1D0BWP U1_1_5 ( .A(A[5]), .B(carry[5]), .CO(carry[6]), .S(SUM[5]) );
HA1D0BWP U1_1_6 ( .A(A[6]), .B(carry[6]), .CO(carry[7]), .S(SUM[6]) );
HA1D0BWP U1_1_7 ( .A(A[7]), .B(carry[7]), .CO(carry[8]), .S(SUM[7]) );
HA1D0BWP U1_1_8 ( .A(A[8]), .B(carry[8]), .CO(carry[9]), .S(SUM[8]) );
HA1D0BWP U1_1_9 ( .A(A[9]), .B(carry[9]), .CO(carry[10]), .S(SUM[9]) );
HA1D0BWP U1_1_10 ( .A(A[10]), .B(carry[10]), .CO(carry[11]), .S(SUM[10]) );
HA1D0BWP U1_1_11 ( .A(A[11]), .B(carry[11]), .CO(carry[12]), .S(SUM[11]) );
HA1D0BWP U1_1_12 ( .A(A[12]), .B(carry[12]), .CO(carry[13]), .S(SUM[12]) );
HA1D0BWP U1_1_13 ( .A(A[13]), .B(carry[13]), .CO(carry[14]), .S(SUM[13]) );
INVD1BWP U2 ( .I(A[0]), .ZN(SUM[0]) );
endmodule
module CPU_sim ( clk, rst, hlt );
input clk, rst, hlt;
wire cur_Ret, Call, Branch, Ret, RegWrite, \HD/N4 , \HD/N3 , \DF/FWD[0] ,
\DF/FWD[1] , \DF/FWD[2] , \DF/FWD[3] , \DF/FWD[4] , \DF/FWD[5] ,
\DF/FWD[6] , \DF/FWD[7] , \DF/FWD[8] , \DF/FWD[9] , \DF/FWD[10] ,
\DF/FWD[11] , \DF/FWD[12] , \DF/FWD[13] , \DF/MemToReg[0] ,
\DF/RegWrite[0] , \DF/RegWrite[1] , \DF/write_addr[0] ,
\DF/write_addr[1] , \DF/write_addr[2] , \DF/write_addr[3] ,
\DF/write_addr[4] , \DF/write_addr[5] , \DF/write_addr[6] ,
\DF/write_addr[7] , \IF/n54 , \IF/n53 , \IF/n52 , \IF/n51 , \IF/n50 ,
\IF/n49 , \IF/n48 , \IF/n47 , \IF/n46 , \IF/n45 , \IF/n44 , \IF/n43 ,
\IF/n42 , \IF/n41 , \IF/n40 , \IF/n39 , \IF/PC[0] , \IF/PC[1] ,
\IF/PC[2] , \IF/PC[3] , \IF/PC[4] , \IF/PC[5] , \IF/PC[6] ,
\IF/PC[7] , \IF/PC[8] , \IF/PC[9] , \IF/PC[10] , \IF/PC[11] ,
\IF/PC[12] , \IF/PC[13] , \IF/PC[14] , \IF/PC[15] ,
\ID/add_1_root_add_39_2/carry[1] , \ID/add_1_root_add_39_2/carry[2] ,
\ID/add_1_root_add_39_2/carry[3] , \ID/add_1_root_add_39_2/carry[4] ,
\ID/add_1_root_add_39_2/carry[5] , \ID/add_1_root_add_39_2/carry[6] ,
\ID/add_1_root_add_39_2/carry[7] , \ID/add_1_root_add_39_2/carry[8] ,
\ID/add_1_root_add_39_2/carry[9] , \ID/add_1_root_add_39_2/carry[10] ,
\ID/add_1_root_add_39_2/carry[11] ,
\ID/add_1_root_add_39_2/carry[12] ,
\ID/add_1_root_add_39_2/carry[13] ,
\ID/add_1_root_add_39_2/carry[14] ,
\ID/add_1_root_add_39_2/carry[15] , \ID/rst_ctrl , \ID/ReadRd ,
\ID/CallRet , \ID/LoadStore , \ID/LoadByte , \ID/BCR , \ID/tmpBCR ,
\EX/imm[0] , \EX/imm[1] , \EX/imm[2] , \EX/imm[3] , \EX/imm[4] ,
\EX/imm[5] , \EX/imm[6] , \EX/imm[7] , \EX/imm[8] , \EX/imm[9] ,
\EX/imm[10] , \EX/imm[11] , \EX/imm[12] , \EX/imm[13] , \EX/imm[14] ,
\EX/imm[15] , \EX/ALUSrc[0] , \EX/ALUSrc[1] , \EX/EX[6] , \EX/EX[7] ,
\EX/EX[8] , \EX/EX[9] , \WB/WB[0] , n89, n90, n91, n93, n94, n95, n96,
n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119,
n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n131,
n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142,
n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164,
n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186,
n187, n188, n189, n190, n192, n193, n194, n195, n196, n197, n198,
n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209,
n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220,
n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242,
n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253,
n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264,
n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275,
n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286,
n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297,
n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308,
n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319,
n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330,
n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352,
n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374,
n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
n397, n398, n399, n400, n401, n402, n403, n404, n405;
wire [13:0] FWD;
wire [15:0] PCcall;
wire [15:0] PCbranch;
wire [15:0] PCret;
wire [15:0] PC_inc_IFID;
wire [15:0] instr_IFID;
wire [3:0] write_addr;
wire [15:0] PC_inc_IDEX;
wire [15:0] PCbranch_IDEX;
wire [15:0] r0data;
wire [15:0] r1data;
wire [9:0] EX_IDEX;
wire [1:0] M_IDEX;
wire [6:0] WB_IDEX;
wire [15:0] ALU_MEMWB;
wire [2:0] flags_MEMEX;
wire [15:0] addr_EXMEM;
wire [15:0] data_EXMEM;
wire [15:0] ALU_EXMEM;
wire [2:0] flags_EXMEM;
wire [6:0] WB_EXMEM;
wire [1:0] M_EXMEM;
wire [15:0] rdata;
wire [6:0] WB_MEMWB;
wire [2:0] \HD/Stall ;
wire [14:12] \ID/instr ;
wire [15:0] \EX/b ;
wire [15:0] \EX/r0data_fwd ;
wire [15:0] \EX/offset ;
wire [2:0] \EX/bcond ;
wire [15:0] \EX/r1data ;
wire [15:0] \EX/r0data ;
wire [15:0] \EX/PC_inc ;
wire [3:0] \EX/ALUOp ;
wire [15:0] \MEM/wdata ;
wire [15:0] \MEM/addr ;
wire [1:0] \MEM/M ;
wire [15:0] \WB/MemData ;
wire [15:0] \WB/ALU ;
OR2D1BWP U105 ( .A1(n266), .A2(n250), .Z(n157) );
OR2D1BWP U115 ( .A1(\HD/Stall [2]), .A2(cur_Ret), .Z(\HD/N4 ) );
OR2D1BWP U116 ( .A1(\HD/Stall [1]), .A2(cur_Ret), .Z(\HD/N3 ) );
XOR2D1BWP U150 ( .A1(\DF/write_addr[5] ), .A2(\DF/FWD[1] ), .Z(n178) );
XOR2D1BWP U151 ( .A1(\DF/write_addr[4] ), .A2(\DF/FWD[0] ), .Z(n177) );
XNR2D1BWP U153 ( .A1(\DF/write_addr[7] ), .A2(\DF/FWD[3] ), .ZN(n184) );
XNR2D1BWP U154 ( .A1(\DF/write_addr[6] ), .A2(\DF/FWD[2] ), .ZN(n182) );
XNR2D1BWP U155 ( .A1(\DF/write_addr[3] ), .A2(\DF/FWD[3] ), .ZN(n180) );
XNR2D1BWP U156 ( .A1(n331), .A2(\DF/FWD[2] ), .ZN(n174) );
XNR2D1BWP U158 ( .A1(\DF/write_addr[1] ), .A2(\DF/FWD[1] ), .ZN(n171) );
XNR2D1BWP U159 ( .A1(\DF/write_addr[0] ), .A2(\DF/FWD[0] ), .ZN(n170) );
XNR2D1BWP U234 ( .A1(\DF/write_addr[1] ), .A2(\DF/FWD[5] ), .ZN(n223) );
XNR2D1BWP U235 ( .A1(\DF/write_addr[3] ), .A2(\DF/FWD[7] ), .ZN(n224) );
XNR2D1BWP U236 ( .A1(\DF/write_addr[0] ), .A2(\DF/FWD[4] ), .ZN(n226) );
XNR2D1BWP U237 ( .A1(n331), .A2(\DF/FWD[6] ), .ZN(n227) );
XOR2D1BWP U238 ( .A1(\DF/write_addr[5] ), .A2(\DF/FWD[5] ), .Z(n230) );
XOR2D1BWP U239 ( .A1(\DF/write_addr[4] ), .A2(\DF/FWD[4] ), .Z(n229) );
XNR2D1BWP U241 ( .A1(\DF/write_addr[7] ), .A2(\DF/FWD[7] ), .ZN(n234) );
OA31D1BWP U242 ( .A1(n235), .A2(n236), .A3(n237), .B(\DF/RegWrite[1] ), .Z(
n183) );
XOR2D1BWP U243 ( .A1(\DF/write_addr[5] ), .A2(\DF/write_addr[1] ), .Z(n237)
);
XOR2D1BWP U244 ( .A1(\DF/write_addr[4] ), .A2(\DF/write_addr[0] ), .Z(n236)
);
XNR2D1BWP U246 ( .A1(\DF/write_addr[6] ), .A2(\DF/write_addr[2] ), .ZN(n239)
);
XNR2D1BWP U247 ( .A1(\DF/write_addr[7] ), .A2(\DF/write_addr[3] ), .ZN(n238)
);
XNR2D1BWP U248 ( .A1(\DF/write_addr[6] ), .A2(\DF/FWD[6] ), .ZN(n233) );
IM \IF/instMem ( .clk(clk), .addr({\IF/PC[15] , \IF/PC[14] , \IF/PC[13] ,
\IF/PC[12] , \IF/PC[11] , \IF/PC[10] , \IF/PC[9] , \IF/PC[8] ,
\IF/PC[7] , \IF/PC[6] , \IF/PC[5] , \IF/PC[4] , \IF/PC[3] , \IF/PC[2] ,
\IF/PC[1] , \IF/PC[0] }), .rd_en(n293), .instr(instr_IFID) );
control \ID/ctrl ( .rst(\ID/rst_ctrl ), .opcode({EX_IDEX[8], \ID/instr }),
.RegWrite(WB_IDEX[2]), .ALUSrc(EX_IDEX[5:4]), .MemRead(M_IDEX[0]),
.MemToReg(WB_IDEX[0]), .LoadStore(\ID/LoadStore ), .MemWrite(M_IDEX[1]), .ALUOp(EX_IDEX[3:0]), .ReadRd(\ID/ReadRd ), .PCToMem(EX_IDEX[6]), .CallRet(
\ID/CallRet ), .Call(Call), .Branch(EX_IDEX[9]), .Ret(cur_Ret),
.LoadByte(\ID/LoadByte ), .SPAddr(EX_IDEX[7]) );
rf \ID/regFile ( .clk(clk), .p0_addr(FWD[3:0]), .p1_addr(FWD[7:4]), .p0(
r0data), .p1(r1data), .re0(n324), .re1(n324), .dst_addr(write_addr),
.dst({n404, n403, n402, n401, n400, n399, n398, n397, n396, n395, n394,
n393, n392, n391, n390, n389}), .we(RegWrite), .hlt(n323) );
ALU \EX/alu ( .nArithInstr(\EX/EX[8] ), .a(\EX/r0data_fwd ), .b(\EX/b ),
.operation(\EX/ALUOp ), .shamt({\EX/imm[3] , \EX/imm[2] , \EX/imm[1] ,
\EX/imm[0] }), .result(ALU_EXMEM), .zr(flags_EXMEM[2]), .neg(
flags_EXMEM[1]), .ov(flags_EXMEM[0]) );
decideBranch \EX/db ( .binstr(\EX/EX[9] ), .bcond(\EX/bcond ), .flags(
flags_MEMEX), .branch(Branch) );
DM \MEM/data ( .clk(clk), .addr(\MEM/addr ), .re(\MEM/M [0]), .we(
\MEM/M [1]), .wrt_data(\MEM/wdata ), .rd_data(rdata) );
IF_slice_DW01_inc_0 \IF/add_17 ( .A({\IF/PC[15] , \IF/PC[14] , \IF/PC[13] ,
\IF/PC[12] , \IF/PC[11] , \IF/PC[10] , \IF/PC[9] , \IF/PC[8] ,
\IF/PC[7] , \IF/PC[6] , \IF/PC[5] , \IF/PC[4] , \IF/PC[3] , \IF/PC[2] ,
\IF/PC[1] , \IF/PC[0] }), .SUM(PC_inc_IFID) );
DFCNQD1BWP \EX/r0data_reg[13] ( .D(r0data[13]), .CP(clk), .CDN(n284), .Q(
\EX/r0data [13]) );
DFCNQD1BWP \EX/r0data_reg[14] ( .D(r0data[14]), .CP(clk), .CDN(n284), .Q(
\EX/r0data [14]) );
DFCNQD1BWP \EX/r0data_reg[15] ( .D(r0data[15]), .CP(clk), .CDN(n284), .Q(
\EX/r0data [15]) );
DFCNQD1BWP \WB/PCret_reg[12] ( .D(rdata[12]), .CP(clk), .CDN(n291), .Q(
PCret[12]) );
DFCNQD1BWP \WB/PCret_reg[13] ( .D(rdata[13]), .CP(clk), .CDN(n291), .Q(
PCret[13]) );
DFCNQD1BWP \WB/PCret_reg[14] ( .D(rdata[14]), .CP(clk), .CDN(n302), .Q(
PCret[14]) );
DFCNQD1BWP \WB/PCret_reg[15] ( .D(rdata[15]), .CP(clk), .CDN(n304), .Q(
PCret[15]) );
DFCNQD1BWP \WB/PCret_reg[0] ( .D(rdata[0]), .CP(clk), .CDN(n290), .Q(
PCret[0]) );
DFCNQD1BWP \WB/PCret_reg[1] ( .D(rdata[1]), .CP(clk), .CDN(n290), .Q(
PCret[1]) );
DFCNQD1BWP \WB/PCret_reg[2] ( .D(rdata[2]), .CP(clk), .CDN(n290), .Q(
PCret[2]) );
DFCNQD1BWP \WB/PCret_reg[3] ( .D(rdata[3]), .CP(clk), .CDN(n290), .Q(
PCret[3]) );
DFCNQD1BWP \WB/PCret_reg[4] ( .D(rdata[4]), .CP(clk), .CDN(n290), .Q(
PCret[4]) );
DFCNQD1BWP \WB/PCret_reg[5] ( .D(rdata[5]), .CP(clk), .CDN(n290), .Q(
PCret[5]) );
DFCNQD1BWP \WB/PCret_reg[6] ( .D(rdata[6]), .CP(clk), .CDN(n291), .Q(
PCret[6]) );
DFCNQD1BWP \WB/PCret_reg[7] ( .D(rdata[7]), .CP(clk), .CDN(n291), .Q(
PCret[7]) );
DFCNQD1BWP \WB/PCret_reg[8] ( .D(rdata[8]), .CP(clk), .CDN(n291), .Q(
PCret[8]) );
DFCNQD1BWP \WB/PCret_reg[9] ( .D(rdata[9]), .CP(clk), .CDN(n291), .Q(
PCret[9]) );
DFCNQD1BWP \WB/PCret_reg[10] ( .D(rdata[10]), .CP(clk), .CDN(n291), .Q(
PCret[10]) );
DFCNQD1BWP \WB/PCret_reg[11] ( .D(rdata[11]), .CP(clk), .CDN(n291), .Q(
PCret[11]) );
DFCNQD1BWP \EX/r1data_reg[13] ( .D(r1data[13]), .CP(clk), .CDN(n285), .Q(
\EX/r1data [13]) );
DFCNQD1BWP \EX/r1data_reg[14] ( .D(r1data[14]), .CP(clk), .CDN(n285), .Q(
\EX/r1data [14]) );
DFCNQD1BWP \EX/r1data_reg[15] ( .D(r1data[15]), .CP(clk), .CDN(n285), .Q(
\EX/r1data [15]) );
DFCNQD1BWP \WB/MemData_reg[9] ( .D(rdata[9]), .CP(clk), .CDN(n288), .Q(
\WB/MemData [9]) );
DFCNQD1BWP \EX/r0data_reg[0] ( .D(r0data[0]), .CP(clk), .CDN(n286), .Q(
\EX/r0data [0]) );
DFCNQD1BWP \EX/r0data_reg[1] ( .D(r0data[1]), .CP(clk), .CDN(n286), .Q(
\EX/r0data [1]) );
DFCNQD1BWP \EX/r0data_reg[2] ( .D(r0data[2]), .CP(clk), .CDN(n286), .Q(
\EX/r0data [2]) );
DFCNQD1BWP \EX/r0data_reg[3] ( .D(r0data[3]), .CP(clk), .CDN(n286), .Q(
\EX/r0data [3]) );
DFCNQD1BWP \EX/r0data_reg[4] ( .D(r0data[4]), .CP(clk), .CDN(n286), .Q(
\EX/r0data [4]) );
DFCNQD1BWP \EX/r0data_reg[5] ( .D(r0data[5]), .CP(clk), .CDN(n286), .Q(
\EX/r0data [5]) );
DFCNQD1BWP \EX/r0data_reg[6] ( .D(r0data[6]), .CP(clk), .CDN(n286), .Q(
\EX/r0data [6]) );
DFCNQD1BWP \EX/r0data_reg[7] ( .D(r0data[7]), .CP(clk), .CDN(n285), .Q(
\EX/r0data [7]) );
DFCNQD1BWP \EX/r0data_reg[8] ( .D(r0data[8]), .CP(clk), .CDN(n285), .Q(
\EX/r0data [8]) );
DFCNQD1BWP \EX/r0data_reg[9] ( .D(r0data[9]), .CP(clk), .CDN(n285), .Q(
\EX/r0data [9]) );
DFCNQD1BWP \EX/r0data_reg[10] ( .D(r0data[10]), .CP(clk), .CDN(n285), .Q(
\EX/r0data [10]) );
DFCNQD1BWP \EX/r0data_reg[11] ( .D(r0data[11]), .CP(clk), .CDN(n285), .Q(
\EX/r0data [11]) );
DFCNQD1BWP \EX/r0data_reg[12] ( .D(r0data[12]), .CP(clk), .CDN(n284), .Q(
\EX/r0data [12]) );
DFCNQD1BWP \WB/MemData_reg[0] ( .D(rdata[0]), .CP(clk), .CDN(n288), .Q(
\WB/MemData [0]) );
DFCNQD1BWP \WB/MemData_reg[1] ( .D(rdata[1]), .CP(clk), .CDN(n288), .Q(
\WB/MemData [1]) );
DFCNQD1BWP \WB/MemData_reg[2] ( .D(rdata[2]), .CP(clk), .CDN(n288), .Q(
\WB/MemData [2]) );
DFCNQD1BWP \WB/MemData_reg[3] ( .D(rdata[3]), .CP(clk), .CDN(n288), .Q(
\WB/MemData [3]) );
DFCNQD1BWP \WB/MemData_reg[4] ( .D(rdata[4]), .CP(clk), .CDN(n288), .Q(
\WB/MemData [4]) );
DFCNQD1BWP \WB/MemData_reg[5] ( .D(rdata[5]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [5]) );
DFCNQD1BWP \WB/MemData_reg[6] ( .D(rdata[6]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [6]) );
DFCNQD1BWP \WB/MemData_reg[7] ( .D(rdata[7]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [7]) );
DFCNQD1BWP \WB/MemData_reg[8] ( .D(rdata[8]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [8]) );
DFCNQD1BWP \WB/MemData_reg[10] ( .D(rdata[10]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [10]) );
DFCNQD1BWP \WB/MemData_reg[11] ( .D(rdata[11]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [11]) );
DFCNQD1BWP \WB/MemData_reg[12] ( .D(rdata[12]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [12]) );
DFCNQD1BWP \WB/MemData_reg[13] ( .D(rdata[13]), .CP(clk), .CDN(n289), .Q(
\WB/MemData [13]) );
DFCNQD1BWP \WB/MemData_reg[14] ( .D(rdata[14]), .CP(clk), .CDN(n290), .Q(
\WB/MemData [14]) );
DFCNQD1BWP \WB/MemData_reg[15] ( .D(rdata[15]), .CP(clk), .CDN(n290), .Q(
\WB/MemData [15]) );
DFCNQD1BWP \EX/r1data_reg[0] ( .D(r1data[0]), .CP(clk), .CDN(n292), .Q(
\EX/r1data [0]) );
DFCNQD1BWP \EX/r1data_reg[1] ( .D(r1data[1]), .CP(clk), .CDN(n292), .Q(
\EX/r1data [1]) );
DFCNQD1BWP \EX/r1data_reg[2] ( .D(r1data[2]), .CP(clk), .CDN(n292), .Q(
\EX/r1data [2]) );
DFCNQD1BWP \EX/r1data_reg[3] ( .D(r1data[3]), .CP(clk), .CDN(n292), .Q(
\EX/r1data [3]) );
DFCNQD1BWP \EX/r1data_reg[4] ( .D(r1data[4]), .CP(clk), .CDN(n293), .Q(
\EX/r1data [4]) );
DFCNQD1BWP \EX/r1data_reg[5] ( .D(r1data[5]), .CP(clk), .CDN(n293), .Q(
\EX/r1data [5]) );
DFCNQD1BWP \EX/r1data_reg[6] ( .D(r1data[6]), .CP(clk), .CDN(n293), .Q(
\EX/r1data [6]) );
DFCNQD1BWP \EX/r1data_reg[7] ( .D(r1data[7]), .CP(clk), .CDN(n293), .Q(
\EX/r1data [7]) );
DFCNQD1BWP \EX/r1data_reg[8] ( .D(r1data[8]), .CP(clk), .CDN(n287), .Q(
\EX/r1data [8]) );
DFCNQD1BWP \EX/r1data_reg[9] ( .D(r1data[9]), .CP(clk), .CDN(n287), .Q(
\EX/r1data [9]) );
DFCNQD1BWP \EX/r1data_reg[10] ( .D(r1data[10]), .CP(clk), .CDN(n287), .Q(
\EX/r1data [10]) );
DFCNQD1BWP \EX/r1data_reg[11] ( .D(r1data[11]), .CP(clk), .CDN(n287), .Q(
\EX/r1data [11]) );
DFCNQD1BWP \EX/r1data_reg[12] ( .D(r1data[12]), .CP(clk), .CDN(n286), .Q(
\EX/r1data [12]) );
FA1D0BWP \ID/U55 ( .A(PC_inc_IDEX[14]), .B(n241), .CI(
\ID/add_1_root_add_39_2/carry[14] ), .CO(
\ID/add_1_root_add_39_2/carry[15] ), .S(PCbranch_IDEX[14]) );
XOR3D1BWP \ID/U65 ( .A1(PC_inc_IDEX[15]), .A2(n283), .A3(
\ID/add_1_root_add_39_2/carry[15] ), .Z(PCbranch_IDEX[15]) );
FA1D0BWP \ID/U54 ( .A(PC_inc_IDEX[13]), .B(n241), .CI(
\ID/add_1_root_add_39_2/carry[13] ), .CO(
\ID/add_1_root_add_39_2/carry[14] ), .S(PCbranch_IDEX[13]) );
FA1D0BWP \ID/U53 ( .A(PC_inc_IDEX[12]), .B(n241), .CI(
\ID/add_1_root_add_39_2/carry[12] ), .CO(
\ID/add_1_root_add_39_2/carry[13] ), .S(PCbranch_IDEX[12]) );
FA1D0BWP \ID/U52 ( .A(PC_inc_IDEX[11]), .B(n241), .CI(
\ID/add_1_root_add_39_2/carry[11] ), .CO(
\ID/add_1_root_add_39_2/carry[12] ), .S(PCbranch_IDEX[11]) );
FA1D0BWP \ID/U51 ( .A(PC_inc_IDEX[10]), .B(n241), .CI(
\ID/add_1_root_add_39_2/carry[10] ), .CO(
\ID/add_1_root_add_39_2/carry[11] ), .S(PCbranch_IDEX[10]) );
FA1D0BWP \ID/U49 ( .A(PC_inc_IDEX[8]), .B(n282), .CI(
\ID/add_1_root_add_39_2/carry[8] ), .CO(
\ID/add_1_root_add_39_2/carry[9] ), .S(PCbranch_IDEX[8]) );
FA1D0BWP \ID/U50 ( .A(PC_inc_IDEX[9]), .B(n283), .CI(
\ID/add_1_root_add_39_2/carry[9] ), .CO(
\ID/add_1_root_add_39_2/carry[10] ), .S(PCbranch_IDEX[9]) );
FA1D0BWP \ID/U48 ( .A(PC_inc_IDEX[7]), .B(n283), .CI(
\ID/add_1_root_add_39_2/carry[7] ), .CO(
\ID/add_1_root_add_39_2/carry[8] ), .S(PCbranch_IDEX[7]) );
FA1D0BWP \ID/U62 ( .A(PC_inc_IDEX[3]), .B(n280), .CI(
\ID/add_1_root_add_39_2/carry[3] ), .CO(
\ID/add_1_root_add_39_2/carry[4] ), .S(PCbranch_IDEX[3]) );
FA1D0BWP \ID/U64 ( .A(PC_inc_IDEX[6]), .B(PCcall[6]), .CI(
\ID/add_1_root_add_39_2/carry[6] ), .CO(
\ID/add_1_root_add_39_2/carry[7] ), .S(PCbranch_IDEX[6]) );
FA1D0BWP \ID/U63 ( .A(PC_inc_IDEX[5]), .B(PCcall[5]), .CI(
\ID/add_1_root_add_39_2/carry[5] ), .CO(
\ID/add_1_root_add_39_2/carry[6] ), .S(PCbranch_IDEX[5]) );
FA1D0BWP \ID/U61 ( .A(PC_inc_IDEX[4]), .B(PCcall[4]), .CI(
\ID/add_1_root_add_39_2/carry[4] ), .CO(
\ID/add_1_root_add_39_2/carry[5] ), .S(PCbranch_IDEX[4]) );
FA1D0BWP \ID/U60 ( .A(PC_inc_IDEX[2]), .B(PCcall[2]), .CI(
\ID/add_1_root_add_39_2/carry[2] ), .CO(
\ID/add_1_root_add_39_2/carry[3] ), .S(PCbranch_IDEX[2]) );
FA1D0BWP \ID/U59 ( .A(PC_inc_IDEX[1]), .B(PCcall[1]), .CI(
\ID/add_1_root_add_39_2/carry[1] ), .CO(
\ID/add_1_root_add_39_2/carry[2] ), .S(PCbranch_IDEX[1]) );
EDFCND1BWP \ID/instr_reg[11] ( .D(instr_IFID[11]), .E(n240), .CP(clk),
.CDN(n245), .Q(PCcall[11]), .QN(n332) );
EDFCND1BWP \ID/instr_reg[8] ( .D(instr_IFID[8]), .E(n321), .CP(clk), .CDN(
n245), .Q(PCcall[8]), .QN(n338) );
EDFCND1BWP \ID/instr_reg[7] ( .D(instr_IFID[7]), .E(n240), .CP(clk), .CDN(
n245), .Q(n241), .QN(n281) );
EDFCND1BWP \ID/instr_reg[6] ( .D(instr_IFID[6]), .E(n322), .CP(clk), .CDN(
n245), .Q(PCcall[6]), .QN(n335) );
EDFCND1BWP \ID/instr_reg[5] ( .D(instr_IFID[5]), .E(n322), .CP(clk), .CDN(
n245), .Q(PCcall[5]), .QN(n334) );
EDFCND1BWP \ID/instr_reg[3] ( .D(instr_IFID[3]), .E(n322), .CP(clk), .CDN(
n245), .Q(n242), .QN(n279) );
EDFCND1BWP \ID/PC_inc_reg[3] ( .D(PC_inc_IFID[3]), .E(n322), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[3]) );
EDFCND1BWP \ID/PC_inc_reg[2] ( .D(PC_inc_IFID[2]), .E(n322), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[2]) );
EDFCND1BWP \ID/PC_inc_reg[1] ( .D(PC_inc_IFID[1]), .E(n322), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[1]) );
EDFCND1BWP \ID/PC_inc_reg[0] ( .D(PC_inc_IFID[0]), .E(n322), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[0]), .QN(n333) );
EDFCND1BWP \ID/instr_reg[4] ( .D(instr_IFID[4]), .E(n319), .CP(clk), .CDN(
n245), .Q(PCcall[4]) );
EDFCND1BWP \ID/instr_reg[2] ( .D(instr_IFID[2]), .E(n319), .CP(clk), .CDN(
n245), .Q(PCcall[2]) );
EDFCND1BWP \ID/instr_reg[1] ( .D(instr_IFID[1]), .E(n319), .CP(clk), .CDN(
n245), .Q(PCcall[1]) );
EDFCND1BWP \ID/instr_reg[0] ( .D(instr_IFID[0]), .E(n319), .CP(clk), .CDN(
n245), .Q(PCcall[0]), .QN(n339) );
EDFCND1BWP \ID/instr_reg[15] ( .D(instr_IFID[15]), .E(n321), .CP(clk),
.CDN(n245), .Q(EX_IDEX[8]) );
EDFCND1BWP \ID/instr_reg[14] ( .D(instr_IFID[14]), .E(n321), .CP(clk),
.CDN(n245), .Q(\ID/instr [14]) );
EDFCND1BWP \ID/instr_reg[13] ( .D(instr_IFID[13]), .E(n321), .CP(clk),
.CDN(n245), .Q(\ID/instr [13]) );
EDFCND1BWP \ID/instr_reg[12] ( .D(instr_IFID[12]), .E(n321), .CP(clk),
.CDN(n245), .Q(\ID/instr [12]) );
EDFCND1BWP \ID/instr_reg[10] ( .D(instr_IFID[10]), .E(n321), .CP(clk),
.CDN(n245), .Q(PCcall[10]), .QN(n337) );
EDFCND1BWP \ID/instr_reg[9] ( .D(instr_IFID[9]), .E(n321), .CP(clk), .CDN(
n245), .Q(PCcall[9]), .QN(n336) );
EDFCND1BWP \ID/PC_inc_reg[5] ( .D(PC_inc_IFID[5]), .E(n321), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[5]) );
EDFCND1BWP \ID/PC_inc_reg[4] ( .D(PC_inc_IFID[4]), .E(n321), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[4]) );
EDFCND1BWP \ID/PC_inc_reg[6] ( .D(PC_inc_IFID[6]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[6]) );
EDFCND1BWP \ID/PC_inc_reg[7] ( .D(PC_inc_IFID[7]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[7]) );
EDFCND1BWP \ID/PC_inc_reg[8] ( .D(PC_inc_IFID[8]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[8]) );
EDFCND1BWP \ID/PC_inc_reg[9] ( .D(PC_inc_IFID[9]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[9]) );
EDFCND1BWP \ID/PC_inc_reg[10] ( .D(PC_inc_IFID[10]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[10]) );
EDFCND1BWP \ID/PC_inc_reg[11] ( .D(PC_inc_IFID[11]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[11]) );
EDFCND1BWP \ID/PC_inc_reg[12] ( .D(PC_inc_IFID[12]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[12]) );
EDFCND1BWP \ID/PC_inc_reg[13] ( .D(PC_inc_IFID[13]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[13]) );
EDFCND1BWP \ID/PC_inc_reg[14] ( .D(PC_inc_IFID[14]), .E(n320), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[14]) );
EDFCND1BWP \ID/PC_inc_reg[15] ( .D(PC_inc_IFID[15]), .E(n319), .CP(clk),
.CDN(n245), .Q(PC_inc_IDEX[15]) );
EDFCND1BWP \ID/BCR_reg ( .D(\ID/tmpBCR ), .E(n319), .CP(clk), .CDN(n245),
.Q(\ID/BCR ) );
DFCNQD1BWP \WB/WB_reg[6] ( .D(WB_MEMWB[6]), .CP(clk), .CDN(n306), .Q(
write_addr[3]) );
DFCNQD1BWP \WB/WB_reg[5] ( .D(WB_MEMWB[5]), .CP(clk), .CDN(n298), .Q(
write_addr[2]) );
DFCNQD1BWP \WB/WB_reg[4] ( .D(WB_MEMWB[4]), .CP(clk), .CDN(n244), .Q(
write_addr[1]) );
DFCNQD1BWP \WB/WB_reg[3] ( .D(WB_MEMWB[3]), .CP(clk), .CDN(n246), .Q(
write_addr[0]) );
DFCNQD1BWP \WB/WB_reg[2] ( .D(WB_MEMWB[2]), .CP(clk), .CDN(n246), .Q(
RegWrite) );
DFCNQD1BWP \WB/WB_reg[1] ( .D(WB_MEMWB[1]), .CP(clk), .CDN(n296), .Q(Ret)
);
DFCNQD1BWP \WB/WB_reg[0] ( .D(WB_MEMWB[0]), .CP(clk), .CDN(n244), .Q(
\WB/WB[0] ) );
DFCNQD1BWP \MEM/WB_reg[6] ( .D(WB_EXMEM[6]), .CP(clk), .CDN(n244), .Q(
WB_MEMWB[6]) );
DFCNQD1BWP \MEM/WB_reg[5] ( .D(WB_EXMEM[5]), .CP(clk), .CDN(n306), .Q(
WB_MEMWB[5]) );
DFCNQD1BWP \MEM/WB_reg[4] ( .D(WB_EXMEM[4]), .CP(clk), .CDN(n306), .Q(
WB_MEMWB[4]) );
DFCNQD1BWP \MEM/WB_reg[3] ( .D(WB_EXMEM[3]), .CP(clk), .CDN(n302), .Q(
WB_MEMWB[3]) );
DFCNQD1BWP \MEM/WB_reg[2] ( .D(WB_EXMEM[2]), .CP(clk), .CDN(n305), .Q(
WB_MEMWB[2]) );
DFCNQD1BWP \MEM/WB_reg[1] ( .D(WB_EXMEM[1]), .CP(clk), .CDN(n295), .Q(
WB_MEMWB[1]) );
DFCNQD1BWP \MEM/WB_reg[0] ( .D(WB_EXMEM[0]), .CP(clk), .CDN(n297), .Q(
WB_MEMWB[0]) );
DFCNQD1BWP \MEM/M_reg[1] ( .D(M_EXMEM[1]), .CP(clk), .CDN(n246), .Q(
\MEM/M [1]) );
DFCNQD1BWP \MEM/M_reg[0] ( .D(M_EXMEM[0]), .CP(clk), .CDN(n246), .Q(
\MEM/M [0]) );
DFCNQD1BWP \DF/write_addr_reg[3] ( .D(\DF/FWD[11] ), .CP(clk), .CDN(n246),
.Q(\DF/write_addr[3] ) );
DFCNQD1BWP \DF/write_addr_reg[2] ( .D(\DF/FWD[10] ), .CP(clk), .CDN(n244),
.Q(\DF/write_addr[2] ) );
DFCNQD1BWP \DF/write_addr_reg[1] ( .D(\DF/FWD[9] ), .CP(clk), .CDN(n244),
.Q(\DF/write_addr[1] ) );
DFCNQD1BWP \DF/write_addr_reg[0] ( .D(\DF/FWD[8] ), .CP(clk), .CDN(n244),
.Q(\DF/write_addr[0] ) );
DFCNQD1BWP \EX/PC_inc_reg[14] ( .D(PC_inc_IDEX[14]), .CP(clk), .CDN(n295),
.Q(\EX/PC_inc [14]) );
DFCNQD1BWP \EX/PC_inc_reg[13] ( .D(PC_inc_IDEX[13]), .CP(clk), .CDN(n295),
.Q(\EX/PC_inc [13]) );
DFCNQD1BWP \EX/PC_inc_reg[12] ( .D(PC_inc_IDEX[12]), .CP(clk), .CDN(n301),
.Q(\EX/PC_inc [12]) );
DFCNQD1BWP \EX/PC_inc_reg[11] ( .D(PC_inc_IDEX[11]), .CP(clk), .CDN(n246),
.Q(\EX/PC_inc [11]) );
DFCNQD1BWP \EX/PC_inc_reg[10] ( .D(PC_inc_IDEX[10]), .CP(clk), .CDN(n296),
.Q(\EX/PC_inc [10]) );
DFCNQD1BWP \EX/PC_inc_reg[9] ( .D(PC_inc_IDEX[9]), .CP(clk), .CDN(n293),
.Q(\EX/PC_inc [9]) );
DFCNQD1BWP \EX/PC_inc_reg[8] ( .D(PC_inc_IDEX[8]), .CP(clk), .CDN(n294),
.Q(\EX/PC_inc [8]) );
DFCNQD1BWP \EX/PC_inc_reg[7] ( .D(PC_inc_IDEX[7]), .CP(clk), .CDN(n246),
.Q(\EX/PC_inc [7]) );
DFCNQD1BWP \EX/PC_inc_reg[6] ( .D(PC_inc_IDEX[6]), .CP(clk), .CDN(n303),
.Q(\EX/PC_inc [6]) );
DFCNQD1BWP \EX/PC_inc_reg[5] ( .D(PC_inc_IDEX[5]), .CP(clk), .CDN(n244),
.Q(\EX/PC_inc [5]) );
DFCNQD1BWP \EX/PC_inc_reg[4] ( .D(PC_inc_IDEX[4]), .CP(clk), .CDN(n244),
.Q(\EX/PC_inc [4]) );
DFCNQD1BWP \EX/PC_inc_reg[3] ( .D(PC_inc_IDEX[3]), .CP(clk), .CDN(n246),
.Q(\EX/PC_inc [3]) );
DFCNQD1BWP \EX/PC_inc_reg[2] ( .D(PC_inc_IDEX[2]), .CP(clk), .CDN(n296),
.Q(\EX/PC_inc [2]) );
DFCNQD1BWP \EX/PC_inc_reg[1] ( .D(PC_inc_IDEX[1]), .CP(clk), .CDN(n296),
.Q(\EX/PC_inc [1]) );
DFCNQD1BWP \EX/PC_inc_reg[15] ( .D(PC_inc_IDEX[15]), .CP(clk), .CDN(n304),
.Q(\EX/PC_inc [15]) );
DFCNQD1BWP \EX/PC_inc_reg[0] ( .D(PC_inc_IDEX[0]), .CP(clk), .CDN(n300),
.Q(\EX/PC_inc [0]) );
DFCNQD1BWP \EX/EX_reg[8] ( .D(EX_IDEX[8]), .CP(clk), .CDN(n305), .Q(
\EX/EX[8] ) );
DFCNQD1BWP \DF/RegWrite_reg[0] ( .D(\DF/FWD[12] ), .CP(clk), .CDN(n244),
.Q(\DF/RegWrite[0] ) );
DFCNQD1BWP \DF/MemToReg_reg[0] ( .D(\DF/FWD[13] ), .CP(clk), .CDN(n246),
.Q(\DF/MemToReg[0] ) );
DFCNQD1BWP \EX/bcond_reg[2] ( .D(PCcall[10]), .CP(clk), .CDN(n246), .Q(
\EX/bcond [2]) );
DFCNQD1BWP \EX/bcond_reg[1] ( .D(PCcall[9]), .CP(clk), .CDN(n246), .Q(
\EX/bcond [1]) );
DFCNQD1BWP \EX/bcond_reg[0] ( .D(PCcall[8]), .CP(clk), .CDN(n244), .Q(
\EX/bcond [0]) );
DFCNQD1BWP \WB/ALU_reg[15] ( .D(ALU_MEMWB[15]), .CP(clk), .CDN(n244), .Q(
\WB/ALU [15]) );
DFCNQD1BWP \WB/ALU_reg[14] ( .D(ALU_MEMWB[14]), .CP(clk), .CDN(n244), .Q(
\WB/ALU [14]) );
DFCNQD1BWP \WB/ALU_reg[13] ( .D(ALU_MEMWB[13]), .CP(clk), .CDN(n305), .Q(
\WB/ALU [13]) );
DFCNQD1BWP \WB/ALU_reg[12] ( .D(ALU_MEMWB[12]), .CP(clk), .CDN(n305), .Q(
\WB/ALU [12]) );
DFCNQD1BWP \WB/ALU_reg[11] ( .D(ALU_MEMWB[11]), .CP(clk), .CDN(n304), .Q(
\WB/ALU [11]) );
DFCNQD1BWP \WB/ALU_reg[10] ( .D(ALU_MEMWB[10]), .CP(clk), .CDN(n299), .Q(
\WB/ALU [10]) );
DFCNQD1BWP \WB/ALU_reg[9] ( .D(ALU_MEMWB[9]), .CP(clk), .CDN(n294), .Q(
\WB/ALU [9]) );
DFCNQD1BWP \WB/ALU_reg[8] ( .D(ALU_MEMWB[8]), .CP(clk), .CDN(n303), .Q(
\WB/ALU [8]) );
DFCNQD1BWP \WB/ALU_reg[7] ( .D(ALU_MEMWB[7]), .CP(clk), .CDN(n246), .Q(
\WB/ALU [7]) );
DFCNQD1BWP \WB/ALU_reg[6] ( .D(ALU_MEMWB[6]), .CP(clk), .CDN(n246), .Q(
\WB/ALU [6]) );
DFCNQD1BWP \WB/ALU_reg[5] ( .D(ALU_MEMWB[5]), .CP(clk), .CDN(n246), .Q(
\WB/ALU [5]) );
DFCNQD1BWP \WB/ALU_reg[4] ( .D(ALU_MEMWB[4]), .CP(clk), .CDN(n244), .Q(
\WB/ALU [4]) );
DFCNQD1BWP \WB/ALU_reg[3] ( .D(ALU_MEMWB[3]), .CP(clk), .CDN(n244), .Q(
\WB/ALU [3]) );
DFCNQD1BWP \WB/ALU_reg[2] ( .D(ALU_MEMWB[2]), .CP(clk), .CDN(n244), .Q(
\WB/ALU [2]) );
DFCNQD1BWP \WB/ALU_reg[1] ( .D(ALU_MEMWB[1]), .CP(clk), .CDN(n294), .Q(
\WB/ALU [1]) );
DFCNQD1BWP \WB/ALU_reg[0] ( .D(ALU_MEMWB[0]), .CP(clk), .CDN(n294), .Q(
\WB/ALU [0]) );
DFCNQD1BWP \DF/write_addr_reg[6] ( .D(\DF/write_addr[2] ), .CP(clk), .CDN(
n297), .Q(\DF/write_addr[6] ) );
DFCNQD1BWP \EX/offset_reg[0] ( .D(PCcall[0]), .CP(clk), .CDN(n246), .Q(
\EX/offset [0]) );
DFCNQD1BWP \EX/imm_reg[0] ( .D(PCcall[0]), .CP(clk), .CDN(n287), .Q(
\EX/imm[0] ) );
DFCNQD1BWP \EX/offset_reg[4] ( .D(PCcall[4]), .CP(clk), .CDN(n301), .Q(
\EX/offset [4]) );
DFCNQD1BWP \EX/offset_reg[6] ( .D(PCcall[6]), .CP(clk), .CDN(n244), .Q(
\EX/offset [6]) );
DFCNQD1BWP \EX/offset_reg[5] ( .D(PCcall[5]), .CP(clk), .CDN(n246), .Q(
\EX/offset [5]) );
DFCNQD1BWP \DF/write_addr_reg[5] ( .D(\DF/write_addr[1] ), .CP(clk), .CDN(
n246), .Q(\DF/write_addr[5] ) );
DFCNQD1BWP \DF/write_addr_reg[4] ( .D(\DF/write_addr[0] ), .CP(clk), .CDN(
n302), .Q(\DF/write_addr[4] ) );
DFCNQD1BWP \DF/write_addr_reg[7] ( .D(\DF/write_addr[3] ), .CP(clk), .CDN(
n244), .Q(\DF/write_addr[7] ) );
DFCNQD1BWP \EX/offset_reg[2] ( .D(PCcall[2]), .CP(clk), .CDN(n244), .Q(
\EX/offset [2]) );
DFCNQD1BWP \EX/offset_reg[1] ( .D(PCcall[1]), .CP(clk), .CDN(n287), .Q(
\EX/offset [1]) );
DFCNQD1BWP \EX/imm_reg[2] ( .D(PCcall[2]), .CP(clk), .CDN(n287), .Q(
\EX/imm[2] ) );
DFCNQD1BWP \EX/imm_reg[1] ( .D(PCcall[1]), .CP(clk), .CDN(n298), .Q(
\EX/imm[1] ) );
DFCNQD1BWP \EX/offset_reg[3] ( .D(n242), .CP(clk), .CDN(n301), .Q(
\EX/offset [3]) );
DFCNQD1BWP \EX/imm_reg[15] ( .D(n242), .CP(clk), .CDN(n284), .Q(
\EX/imm[15] ) );
DFCNQD1BWP \EX/imm_reg[14] ( .D(n242), .CP(clk), .CDN(n302), .Q(
\EX/imm[14] ) );
DFCNQD1BWP \EX/imm_reg[13] ( .D(n242), .CP(clk), .CDN(n246), .Q(
\EX/imm[13] ) );
DFCNQD1BWP \EX/imm_reg[12] ( .D(n242), .CP(clk), .CDN(n246), .Q(
\EX/imm[12] ) );
DFCNQD1BWP \EX/imm_reg[11] ( .D(n242), .CP(clk), .CDN(n246), .Q(
\EX/imm[11] ) );
DFCNQD1BWP \EX/imm_reg[10] ( .D(n242), .CP(clk), .CDN(n244), .Q(
\EX/imm[10] ) );
DFCNQD1BWP \EX/imm_reg[9] ( .D(n242), .CP(clk), .CDN(n244), .Q(\EX/imm[9] )
);
DFCNQD1BWP \EX/imm_reg[8] ( .D(n242), .CP(clk), .CDN(n306), .Q(\EX/imm[8] )
);
DFCNQD1BWP \DF/RegWrite_reg[1] ( .D(\DF/RegWrite[0] ), .CP(clk), .CDN(n284),
.Q(\DF/RegWrite[1] ) );
DFCNQD1BWP \EX/PCbranch_reg[0] ( .D(PCbranch_IDEX[0]), .CP(clk), .CDN(n284),
.Q(PCbranch[0]) );
DFCNQD1BWP \EX/offset_reg[15] ( .D(n282), .CP(clk), .CDN(n299), .Q(
\EX/offset [15]) );
DFCNQD1BWP \EX/offset_reg[13] ( .D(n282), .CP(clk), .CDN(n303), .Q(
\EX/offset [13]) );
DFCNQD1BWP \EX/offset_reg[11] ( .D(n282), .CP(clk), .CDN(n292), .Q(
\EX/offset [11]) );
DFCNQD1BWP \EX/offset_reg[9] ( .D(n282), .CP(clk), .CDN(n244), .Q(
\EX/offset [9]) );
DFCNQD1BWP \EX/offset_reg[7] ( .D(n282), .CP(clk), .CDN(n246), .Q(
\EX/offset [7]) );
DFCNQD1BWP \EX/imm_reg[7] ( .D(n280), .CP(clk), .CDN(n246), .Q(\EX/imm[7] )
);
DFCNQD1BWP \EX/imm_reg[6] ( .D(n280), .CP(clk), .CDN(n295), .Q(\EX/imm[6] )
);
DFCNQD1BWP \EX/imm_reg[5] ( .D(n280), .CP(clk), .CDN(n244), .Q(\EX/imm[5] )
);
DFCNQD1BWP \EX/imm_reg[4] ( .D(n280), .CP(clk), .CDN(n244), .Q(\EX/imm[4] )
);
DFCNQD1BWP \EX/imm_reg[3] ( .D(n280), .CP(clk), .CDN(n246), .Q(\EX/imm[3] )
);
DFCNQD1BWP \EX/offset_reg[14] ( .D(n283), .CP(clk), .CDN(n292), .Q(
\EX/offset [14]) );
DFCNQD1BWP \EX/offset_reg[12] ( .D(n283), .CP(clk), .CDN(n288), .Q(
\EX/offset [12]) );
DFCNQD1BWP \EX/offset_reg[10] ( .D(n283), .CP(clk), .CDN(n244), .Q(
\EX/offset [10]) );
DFCNQD1BWP \EX/offset_reg[8] ( .D(n283), .CP(clk), .CDN(n246), .Q(
\EX/offset [8]) );
DFCNQD1BWP \EX/PCbranch_reg[1] ( .D(PCbranch_IDEX[1]), .CP(clk), .CDN(n300),
.Q(PCbranch[1]) );
DFCNQD1BWP \EX/PCbranch_reg[2] ( .D(PCbranch_IDEX[2]), .CP(clk), .CDN(n300),
.Q(PCbranch[2]) );
DFCNQD1BWP \EX/PCbranch_reg[3] ( .D(PCbranch_IDEX[3]), .CP(clk), .CDN(n244),
.Q(PCbranch[3]) );
DFCNQD1BWP \EX/PCbranch_reg[4] ( .D(PCbranch_IDEX[4]), .CP(clk), .CDN(n246),
.Q(PCbranch[4]) );
DFCNQD1BWP \EX/PCbranch_reg[5] ( .D(PCbranch_IDEX[5]), .CP(clk), .CDN(n246),
.Q(PCbranch[5]) );
DFCNQD1BWP \EX/PCbranch_reg[6] ( .D(PCbranch_IDEX[6]), .CP(clk), .CDN(n304),
.Q(PCbranch[6]) );
DFCNQD1BWP \EX/PCbranch_reg[7] ( .D(PCbranch_IDEX[7]), .CP(clk), .CDN(n244),
.Q(PCbranch[7]) );
DFCNQD1BWP \EX/PCbranch_reg[8] ( .D(PCbranch_IDEX[8]), .CP(clk), .CDN(n244),
.Q(PCbranch[8]) );
DFCNQD1BWP \MEM/wdata_reg[15] ( .D(data_EXMEM[15]), .CP(clk), .CDN(n300),
.Q(\MEM/wdata [15]) );
DFCNQD1BWP \MEM/wdata_reg[14] ( .D(data_EXMEM[14]), .CP(clk), .CDN(n292),
.Q(\MEM/wdata [14]) );
DFCNQD1BWP \MEM/wdata_reg[13] ( .D(data_EXMEM[13]), .CP(clk), .CDN(n296),
.Q(\MEM/wdata [13]) );
DFCNQD1BWP \MEM/wdata_reg[12] ( .D(data_EXMEM[12]), .CP(clk), .CDN(n246),
.Q(\MEM/wdata [12]) );
DFCNQD1BWP \MEM/wdata_reg[11] ( .D(data_EXMEM[11]), .CP(clk), .CDN(n299),
.Q(\MEM/wdata [11]) );
DFCNQD1BWP \MEM/wdata_reg[10] ( .D(data_EXMEM[10]), .CP(clk), .CDN(n292),
.Q(\MEM/wdata [10]) );
DFCNQD1BWP \MEM/wdata_reg[9] ( .D(data_EXMEM[9]), .CP(clk), .CDN(n297), .Q(
\MEM/wdata [9]) );
DFCNQD1BWP \MEM/wdata_reg[8] ( .D(data_EXMEM[8]), .CP(clk), .CDN(n246), .Q(
\MEM/wdata [8]) );
DFCNQD1BWP \MEM/wdata_reg[7] ( .D(data_EXMEM[7]), .CP(clk), .CDN(n246), .Q(
\MEM/wdata [7]) );
DFCNQD1BWP \MEM/wdata_reg[6] ( .D(data_EXMEM[6]), .CP(clk), .CDN(n244), .Q(
\MEM/wdata [6]) );
DFCNQD1BWP \MEM/wdata_reg[5] ( .D(data_EXMEM[5]), .CP(clk), .CDN(n244), .Q(
\MEM/wdata [5]) );
DFCNQD1BWP \MEM/wdata_reg[4] ( .D(data_EXMEM[4]), .CP(clk), .CDN(n244), .Q(
\MEM/wdata [4]) );
DFCNQD1BWP \MEM/wdata_reg[3] ( .D(data_EXMEM[3]), .CP(clk), .CDN(n299), .Q(
\MEM/wdata [3]) );
DFCNQD1BWP \MEM/wdata_reg[2] ( .D(data_EXMEM[2]), .CP(clk), .CDN(n300), .Q(
\MEM/wdata [2]) );
DFCNQD1BWP \MEM/wdata_reg[1] ( .D(data_EXMEM[1]), .CP(clk), .CDN(n305), .Q(
\MEM/wdata [1]) );
DFCNQD1BWP \MEM/wdata_reg[0] ( .D(data_EXMEM[0]), .CP(clk), .CDN(n298), .Q(
\MEM/wdata [0]) );
DFCNQD1BWP \EX/PCbranch_reg[9] ( .D(PCbranch_IDEX[9]), .CP(clk), .CDN(n302),
.Q(PCbranch[9]) );
DFCNQD1BWP \EX/PCbranch_reg[10] ( .D(PCbranch_IDEX[10]), .CP(clk), .CDN(
n288), .Q(PCbranch[10]) );
DFCNQD1BWP \EX/PCbranch_reg[11] ( .D(PCbranch_IDEX[11]), .CP(clk), .CDN(
n246), .Q(PCbranch[11]) );
DFCNQD1BWP \EX/EX_reg[9] ( .D(EX_IDEX[9]), .CP(clk), .CDN(n246), .Q(
\EX/EX[9] ) );
DFCNQD1BWP \EX/PCbranch_reg[12] ( .D(PCbranch_IDEX[12]), .CP(clk), .CDN(
n294), .Q(PCbranch[12]) );
DFCNQD1BWP \EX/WB_reg[0] ( .D(WB_IDEX[0]), .CP(clk), .CDN(n244), .Q(
WB_EXMEM[0]) );
DFCNQD1BWP \DF/FWD_reg[13] ( .D(WB_IDEX[0]), .CP(clk), .CDN(n244), .Q(
\DF/FWD[13] ) );
DFCNQD1BWP \EX/M_reg[1] ( .D(M_IDEX[1]), .CP(clk), .CDN(n246), .Q(
M_EXMEM[1]) );
DFCNQD1BWP \EX/EX_reg[7] ( .D(EX_IDEX[7]), .CP(clk), .CDN(n302), .Q(
\EX/EX[7] ) );
DFCNQD1BWP \EX/EX_reg[6] ( .D(EX_IDEX[6]), .CP(clk), .CDN(n299), .Q(
\EX/EX[6] ) );
DFCNQD1BWP \HD/Stall_reg[2] ( .D(cur_Ret), .CP(clk), .CDN(n284), .Q(
\HD/Stall [2]) );
DFCNQD1BWP \EX/WB_reg[1] ( .D(cur_Ret), .CP(clk), .CDN(n306), .Q(
WB_EXMEM[1]) );
DFCNQD1BWP \EX/EX_reg[3] ( .D(EX_IDEX[3]), .CP(clk), .CDN(n301), .Q(
\EX/ALUOp [3]) );
DFCNQD1BWP \EX/EX_reg[2] ( .D(EX_IDEX[2]), .CP(clk), .CDN(n244), .Q(
\EX/ALUOp [2]) );
DFCNQD1BWP \EX/M_reg[0] ( .D(M_IDEX[0]), .CP(clk), .CDN(n246), .Q(
M_EXMEM[0]) );
DFCNQD1BWP \EX/EX_reg[1] ( .D(EX_IDEX[1]), .CP(clk), .CDN(n246), .Q(
\EX/ALUOp [1]) );
DFCNQD1BWP \EX/EX_reg[0] ( .D(EX_IDEX[0]), .CP(clk), .CDN(n246), .Q(
\EX/ALUOp [0]) );
DFCNQD1BWP \EX/PCbranch_reg[13] ( .D(PCbranch_IDEX[13]), .CP(clk), .CDN(
n244), .Q(PCbranch[13]) );
DFCNQD1BWP \HD/Stall_reg[1] ( .D(\HD/N4 ), .CP(clk), .CDN(n244), .Q(
\HD/Stall [1]) );
DFCNQD1BWP \HD/Stall_reg[0] ( .D(\HD/N3 ), .CP(clk), .CDN(n244), .Q(
\HD/Stall [0]) );
DFCNQD1BWP \EX/EX_reg[5] ( .D(EX_IDEX[5]), .CP(clk), .CDN(n301), .Q(
\EX/ALUSrc[1] ) );
DFCNQD1BWP \EX/EX_reg[4] ( .D(EX_IDEX[4]), .CP(clk), .CDN(n302), .Q(
\EX/ALUSrc[0] ) );
DFCNQD1BWP \EX/PCbranch_reg[14] ( .D(PCbranch_IDEX[14]), .CP(clk), .CDN(
n300), .Q(PCbranch[14]) );
DFCNQD1BWP \EX/WB_reg[2] ( .D(WB_IDEX[2]), .CP(clk), .CDN(n246), .Q(
WB_EXMEM[2]) );
DFCNQD1BWP \DF/FWD_reg[12] ( .D(WB_IDEX[2]), .CP(clk), .CDN(n303), .Q(
\DF/FWD[12] ) );
DFCNQD1BWP \EX/WB_reg[6] ( .D(WB_IDEX[6]), .CP(clk), .CDN(n287), .Q(
WB_EXMEM[6]) );
DFCNQD1BWP \EX/WB_reg[5] ( .D(WB_IDEX[5]), .CP(clk), .CDN(n244), .Q(
WB_EXMEM[5]) );
DFCNQD1BWP \EX/WB_reg[4] ( .D(WB_IDEX[4]), .CP(clk), .CDN(n246), .Q(
WB_EXMEM[4]) );
DFCNQD1BWP \EX/WB_reg[3] ( .D(WB_IDEX[3]), .CP(clk), .CDN(n246), .Q(
WB_EXMEM[3]) );
DFCNQD1BWP \DF/FWD_reg[11] ( .D(WB_IDEX[6]), .CP(clk), .CDN(n295), .Q(
\DF/FWD[11] ) );
DFCNQD1BWP \DF/FWD_reg[10] ( .D(WB_IDEX[5]), .CP(clk), .CDN(n244), .Q(
\DF/FWD[10] ) );
DFCNQD1BWP \DF/FWD_reg[9] ( .D(WB_IDEX[4]), .CP(clk), .CDN(n244), .Q(
\DF/FWD[9] ) );
DFCNQD1BWP \DF/FWD_reg[8] ( .D(WB_IDEX[3]), .CP(clk), .CDN(n303), .Q(
\DF/FWD[8] ) );
DFCNQD1BWP \EX/PCbranch_reg[15] ( .D(PCbranch_IDEX[15]), .CP(clk), .CDN(
n301), .Q(PCbranch[15]) );
DFCNQD1BWP \DF/FWD_reg[4] ( .D(FWD[4]), .CP(clk), .CDN(n299), .Q(
\DF/FWD[4] ) );
DFCNQD1BWP \DF/FWD_reg[7] ( .D(FWD[7]), .CP(clk), .CDN(n246), .Q(
\DF/FWD[7] ) );
DFCNQD1BWP \DF/FWD_reg[6] ( .D(FWD[6]), .CP(clk), .CDN(n304), .Q(
\DF/FWD[6] ) );
DFCNQD1BWP \DF/FWD_reg[5] ( .D(FWD[5]), .CP(clk), .CDN(n245), .Q(
\DF/FWD[5] ) );
DFCNQD1BWP \DF/FWD_reg[0] ( .D(FWD[0]), .CP(clk), .CDN(n296), .Q(
\DF/FWD[0] ) );
DFCNQD1BWP \DF/FWD_reg[3] ( .D(FWD[3]), .CP(clk), .CDN(n246), .Q(
\DF/FWD[3] ) );
DFCNQD1BWP \DF/FWD_reg[2] ( .D(FWD[2]), .CP(clk), .CDN(n246), .Q(
\DF/FWD[2] ) );
DFCNQD1BWP \DF/FWD_reg[1] ( .D(FWD[1]), .CP(clk), .CDN(n244), .Q(
\DF/FWD[1] ) );
DFCNQD1BWP \MEM/ALU_reg[2] ( .D(ALU_EXMEM[2]), .CP(clk), .CDN(n244), .Q(
ALU_MEMWB[2]) );
DFCNQD1BWP \MEM/ALU_reg[1] ( .D(ALU_EXMEM[1]), .CP(clk), .CDN(n244), .Q(
ALU_MEMWB[1]) );
DFCNQD1BWP \MEM/ALU_reg[0] ( .D(ALU_EXMEM[0]), .CP(clk), .CDN(n304), .Q(
ALU_MEMWB[0]) );
DFCNQD1BWP \MEM/addr_reg[2] ( .D(addr_EXMEM[2]), .CP(clk), .CDN(n303), .Q(
\MEM/addr [2]) );
DFCNQD1BWP \MEM/ALU_reg[3] ( .D(ALU_EXMEM[3]), .CP(clk), .CDN(n301), .Q(
ALU_MEMWB[3]) );
DFCNQD1BWP \MEM/addr_reg[1] ( .D(addr_EXMEM[1]), .CP(clk), .CDN(n246), .Q(
\MEM/addr [1]) );
DFCNQD1BWP \MEM/ALU_reg[4] ( .D(ALU_EXMEM[4]), .CP(clk), .CDN(n297), .Q(
ALU_MEMWB[4]) );
DFCNQD1BWP \MEM/addr_reg[0] ( .D(addr_EXMEM[0]), .CP(clk), .CDN(n245), .Q(
\MEM/addr [0]) );
DFCNQD1BWP \MEM/addr_reg[3] ( .D(addr_EXMEM[3]), .CP(clk), .CDN(n305), .Q(
\MEM/addr [3]) );
DFCNQD1BWP \MEM/ALU_reg[5] ( .D(ALU_EXMEM[5]), .CP(clk), .CDN(n246), .Q(
ALU_MEMWB[5]) );
DFCNQD1BWP \MEM/addr_reg[4] ( .D(addr_EXMEM[4]), .CP(clk), .CDN(n246), .Q(
\MEM/addr [4]) );
DFCNQD1BWP \MEM/ALU_reg[6] ( .D(ALU_EXMEM[6]), .CP(clk), .CDN(n293), .Q(
ALU_MEMWB[6]) );
DFCNQD1BWP \MEM/addr_reg[5] ( .D(addr_EXMEM[5]), .CP(clk), .CDN(n244), .Q(
\MEM/addr [5]) );
DFCNQD1BWP \MEM/ALU_reg[7] ( .D(ALU_EXMEM[7]), .CP(clk), .CDN(n303), .Q(
ALU_MEMWB[7]) );
DFCNQD1BWP \MEM/addr_reg[6] ( .D(addr_EXMEM[6]), .CP(clk), .CDN(n244), .Q(
\MEM/addr [6]) );
DFCNQD1BWP \MEM/ALU_reg[8] ( .D(ALU_EXMEM[8]), .CP(clk), .CDN(n304), .Q(
ALU_MEMWB[8]) );
DFCNQD1BWP \MEM/addr_reg[7] ( .D(addr_EXMEM[7]), .CP(clk), .CDN(n245), .Q(
\MEM/addr [7]) );
DFCNQD1BWP \MEM/ALU_reg[9] ( .D(ALU_EXMEM[9]), .CP(clk), .CDN(n294), .Q(
ALU_MEMWB[9]) );
DFCNQD1BWP \MEM/addr_reg[8] ( .D(addr_EXMEM[8]), .CP(clk), .CDN(n246), .Q(
\MEM/addr [8]) );
DFCNQD1BWP \MEM/ALU_reg[10] ( .D(ALU_EXMEM[10]), .CP(clk), .CDN(n244), .Q(
ALU_MEMWB[10]) );
DFCNQD1BWP \MEM/addr_reg[9] ( .D(addr_EXMEM[9]), .CP(clk), .CDN(n246), .Q(
\MEM/addr [9]) );
DFCNQD1BWP \MEM/ALU_reg[11] ( .D(ALU_EXMEM[11]), .CP(clk), .CDN(n298), .Q(
ALU_MEMWB[11]) );
DFCNQD1BWP \MEM/addr_reg[10] ( .D(addr_EXMEM[10]), .CP(clk), .CDN(n245),
.Q(\MEM/addr [10]) );
DFCNQD1BWP \IF/PC_reg[11] ( .D(\IF/n43 ), .CP(clk), .CDN(n244), .Q(
\IF/PC[11] ) );
DFCNQD1BWP \IF/PC_reg[10] ( .D(\IF/n44 ), .CP(clk), .CDN(n244), .Q(
\IF/PC[10] ) );
DFCNQD1BWP \IF/PC_reg[9] ( .D(\IF/n45 ), .CP(clk), .CDN(n245), .Q(
\IF/PC[9] ) );
DFCNQD1BWP \IF/PC_reg[8] ( .D(\IF/n46 ), .CP(clk), .CDN(n297), .Q(
\IF/PC[8] ) );
DFCNQD1BWP \IF/PC_reg[7] ( .D(\IF/n47 ), .CP(clk), .CDN(n293), .Q(
\IF/PC[7] ) );
DFCNQD1BWP \IF/PC_reg[6] ( .D(\IF/n48 ), .CP(clk), .CDN(n245), .Q(
\IF/PC[6] ) );
DFCNQD1BWP \IF/PC_reg[5] ( .D(\IF/n49 ), .CP(clk), .CDN(n246), .Q(
\IF/PC[5] ) );
DFCNQD1BWP \IF/PC_reg[4] ( .D(\IF/n50 ), .CP(clk), .CDN(n306), .Q(
\IF/PC[4] ) );
DFCNQD1BWP \IF/PC_reg[3] ( .D(\IF/n51 ), .CP(clk), .CDN(n245), .Q(
\IF/PC[3] ) );
DFCNQD1BWP \IF/PC_reg[2] ( .D(\IF/n52 ), .CP(clk), .CDN(n244), .Q(
\IF/PC[2] ) );
DFCNQD1BWP \IF/PC_reg[1] ( .D(\IF/n53 ), .CP(clk), .CDN(n246), .Q(
\IF/PC[1] ) );
DFCNQD1BWP \IF/PC_reg[0] ( .D(\IF/n54 ), .CP(clk), .CDN(n245), .Q(
\IF/PC[0] ) );
DFCNQD1BWP \MEM/ALU_reg[12] ( .D(ALU_EXMEM[12]), .CP(clk), .CDN(n300), .Q(
ALU_MEMWB[12]) );
DFCNQD1BWP \MEM/addr_reg[11] ( .D(addr_EXMEM[11]), .CP(clk), .CDN(n244),
.Q(\MEM/addr [11]) );
DFCNQD1BWP \IF/PC_reg[15] ( .D(\IF/n39 ), .CP(clk), .CDN(n298), .Q(
\IF/PC[15] ) );
DFCNQD1BWP \IF/PC_reg[14] ( .D(\IF/n40 ), .CP(clk), .CDN(n246), .Q(
\IF/PC[14] ) );
DFCNQD1BWP \IF/PC_reg[13] ( .D(\IF/n41 ), .CP(clk), .CDN(n244), .Q(
\IF/PC[13] ) );
DFCNQD1BWP \IF/PC_reg[12] ( .D(\IF/n42 ), .CP(clk), .CDN(n245), .Q(
\IF/PC[12] ) );
DFCNQD1BWP \MEM/ALU_reg[13] ( .D(ALU_EXMEM[13]), .CP(clk), .CDN(n298), .Q(
ALU_MEMWB[13]) );
DFCNQD1BWP \MEM/addr_reg[12] ( .D(addr_EXMEM[12]), .CP(clk), .CDN(n297),
.Q(\MEM/addr [12]) );
DFCNQD1BWP \MEM/ALU_reg[14] ( .D(ALU_EXMEM[14]), .CP(clk), .CDN(n245), .Q(
ALU_MEMWB[14]) );
DFCNQD1BWP \MEM/addr_reg[13] ( .D(addr_EXMEM[13]), .CP(clk), .CDN(n246),
.Q(\MEM/addr [13]) );
DFCNQD1BWP \MEM/addr_reg[14] ( .D(addr_EXMEM[14]), .CP(clk), .CDN(n295),
.Q(\MEM/addr [14]) );
DFCNQD1BWP \MEM/ALU_reg[15] ( .D(ALU_EXMEM[15]), .CP(clk), .CDN(n245), .Q(
ALU_MEMWB[15]) );
DFCNQD1BWP \MEM/addr_reg[15] ( .D(addr_EXMEM[15]), .CP(clk), .CDN(n244),
.Q(\MEM/addr [15]) );
DFCNQD1BWP \MEM/flags_reg[1] ( .D(flags_EXMEM[1]), .CP(clk), .CDN(n246),
.Q(flags_MEMEX[1]) );
DFCNQD1BWP \MEM/flags_reg[0] ( .D(flags_EXMEM[0]), .CP(clk), .CDN(n245),
.Q(flags_MEMEX[0]) );
DFCNQD1BWP \MEM/flags_reg[2] ( .D(flags_EXMEM[2]), .CP(clk), .CDN(n299),
.Q(flags_MEMEX[2]) );
OAI31D1BWP U336 ( .A1(n228), .A2(n229), .A3(n230), .B(n231), .ZN(n124) );
INVD1BWP U337 ( .I(n277), .ZN(n278) );
AOI21D2BWP U338 ( .A1(\DF/FWD[13] ), .A2(\DF/FWD[12] ), .B(\HD/Stall [0]),
.ZN(n240) );
CKND16BWP U339 ( .I(n243), .ZN(n245) );
CKND2BWP U340 ( .I(n328), .ZN(n243) );
CKND16BWP U341 ( .I(n243), .ZN(n244) );
CKND16BWP U342 ( .I(n243), .ZN(n246) );
CKBD3BWP U343 ( .I(n168), .Z(n262) );
CKBD3BWP U344 ( .I(n169), .Z(n263) );
CKBD1BWP U345 ( .I(n295), .Z(n291) );
CKBD1BWP U346 ( .I(n295), .Z(n290) );
CKBD1BWP U347 ( .I(n296), .Z(n289) );
CKBD1BWP U348 ( .I(n296), .Z(n288) );
CKBD1BWP U349 ( .I(n298), .Z(n284) );
CKBD1BWP U350 ( .I(n298), .Z(n285) );
CKBD1BWP U351 ( .I(n297), .Z(n286) );
CKBD1BWP U352 ( .I(n297), .Z(n287) );
CKBD1BWP U353 ( .I(n294), .Z(n292) );
CKBD1BWP U354 ( .I(n294), .Z(n293) );
INVD1BWP U355 ( .I(\ID/ReadRd ), .ZN(n326) );
IND2D1BWP U356 ( .A1(\ID/LoadStore ), .B1(n327), .ZN(n165) );
OAI21D1BWP U357 ( .A1(\ID/CallRet ), .A2(\ID/LoadStore ), .B(n327), .ZN(n166) );
INVD1BWP U358 ( .I(\ID/CallRet ), .ZN(n325) );
CKBD1BWP U359 ( .I(n90), .Z(n272) );
CKBD1BWP U360 ( .I(n90), .Z(n271) );
CKBD1BWP U361 ( .I(n302), .Z(n295) );
CKBD1BWP U362 ( .I(n301), .Z(n296) );
CKBD1BWP U363 ( .I(n299), .Z(n298) );
CKBD1BWP U364 ( .I(n300), .Z(n297) );
CKBD1BWP U365 ( .I(n303), .Z(n294) );
CKND4BWP U366 ( .I(\WB/WB[0] ), .ZN(n405) );
CKBD1BWP U367 ( .I(n330), .Z(n252) );
CKBD1BWP U368 ( .I(n330), .Z(n251) );
CKBD1BWP U369 ( .I(n190), .Z(n255) );
CKBD1BWP U370 ( .I(n190), .Z(n254) );
INVD1BWP U371 ( .I(n247), .ZN(n257) );
INVD1BWP U372 ( .I(n247), .ZN(n256) );
INVD1BWP U373 ( .I(\ID/LoadByte ), .ZN(n327) );
CKBD3BWP U374 ( .I(Call), .Z(n250) );
IND2D1BWP U375 ( .A1(cur_Ret), .B1(n164), .ZN(\ID/tmpBCR ) );
ND2D1BWP U376 ( .A1(n125), .A2(n277), .ZN(n90) );
CKBD1BWP U377 ( .I(n89), .Z(n270) );
CKBD1BWP U378 ( .I(n89), .Z(n269) );
INVD1BWP U379 ( .I(n248), .ZN(n274) );
INVD1BWP U380 ( .I(n248), .ZN(n273) );
CKBD1BWP U381 ( .I(n308), .Z(n314) );
CKBD1BWP U382 ( .I(n307), .Z(n311) );
CKBD1BWP U383 ( .I(n307), .Z(n312) );
CKBD1BWP U384 ( .I(n308), .Z(n313) );
CKBD1BWP U385 ( .I(n309), .Z(n315) );
CKBD1BWP U386 ( .I(n309), .Z(n316) );
CKBD1BWP U387 ( .I(n310), .Z(n318) );
CKBD1BWP U388 ( .I(n310), .Z(n317) );
CKBD1BWP U389 ( .I(n305), .Z(n301) );
CKBD1BWP U390 ( .I(n306), .Z(n299) );
CKBD1BWP U391 ( .I(n306), .Z(n300) );
CKBD1BWP U392 ( .I(n304), .Z(n303) );
CKBD1BWP U393 ( .I(n305), .Z(n302) );
OAI222D1BWP U394 ( .A1(n358), .A2(n262), .B1(n384), .B2(n263), .C1(n103),
.C2(n252), .ZN(\EX/r0data_fwd [4]) );
OAI222D1BWP U395 ( .A1(n360), .A2(n262), .B1(n382), .B2(n263), .C1(n99),
.C2(n252), .ZN(\EX/r0data_fwd [6]) );
OAI222D1BWP U396 ( .A1(n357), .A2(n262), .B1(n385), .B2(n263), .C1(n105),
.C2(n252), .ZN(\EX/r0data_fwd [3]) );
OAI222D1BWP U397 ( .A1(n354), .A2(n262), .B1(n386), .B2(n263), .C1(n123),
.C2(n251), .ZN(\EX/r0data_fwd [0]) );
OAI222D1BWP U398 ( .A1(n359), .A2(n262), .B1(n383), .B2(n263), .C1(n101),
.C2(n252), .ZN(\EX/r0data_fwd [5]) );
OAI222D1BWP U399 ( .A1(n356), .A2(n262), .B1(n387), .B2(n263), .C1(n107),
.C2(n252), .ZN(\EX/r0data_fwd [2]) );
OAI222D1BWP U400 ( .A1(n355), .A2(n262), .B1(n388), .B2(n263), .C1(n109),
.C2(n252), .ZN(\EX/r0data_fwd [1]) );
CKBD3BWP U401 ( .I(n185), .Z(n253) );
ND2D1BWP U402 ( .A1(n222), .A2(n124), .ZN(n185) );
NR2XD0BWP U403 ( .A1(n124), .A2(n126), .ZN(n125) );
INVD1BWP U404 ( .I(n180), .ZN(n329) );
INVD1BWP U405 ( .I(n173), .ZN(n330) );
MOAI22D0BWP U406 ( .A1(n318), .A2(n370), .B1(ALU_EXMEM[13]), .B2(n312), .ZN(
addr_EXMEM[13]) );
MOAI22D0BWP U407 ( .A1(n317), .A2(n371), .B1(ALU_EXMEM[14]), .B2(n312), .ZN(
addr_EXMEM[14]) );
MOAI22D0BWP U408 ( .A1(n317), .A2(n372), .B1(ALU_EXMEM[15]), .B2(n313), .ZN(
addr_EXMEM[15]) );
AN2XD1BWP U409 ( .A1(n222), .A2(n126), .Z(n190) );
ND2D1BWP U410 ( .A1(n222), .A2(n125), .ZN(n247) );
OAI222D1BWP U411 ( .A1(n361), .A2(n262), .B1(n381), .B2(n263), .C1(n97),
.C2(n252), .ZN(\EX/r0data_fwd [7]) );
OAI222D1BWP U412 ( .A1(n372), .A2(n262), .B1(n373), .B2(n263), .C1(n111),
.C2(n251), .ZN(\EX/r0data_fwd [15]) );
OAI222D1BWP U413 ( .A1(n362), .A2(n262), .B1(n380), .B2(n263), .C1(n95),
.C2(n252), .ZN(\EX/r0data_fwd [8]) );
OAI222D1BWP U414 ( .A1(n368), .A2(n262), .B1(n377), .B2(n263), .C1(n119),
.C2(n251), .ZN(\EX/r0data_fwd [11]) );
OAI222D1BWP U415 ( .A1(n369), .A2(n262), .B1(n376), .B2(n263), .C1(n117),
.C2(n251), .ZN(\EX/r0data_fwd [12]) );
OAI222D1BWP U416 ( .A1(n370), .A2(n262), .B1(n375), .B2(n263), .C1(n115),
.C2(n251), .ZN(\EX/r0data_fwd [13]) );
OAI222D1BWP U417 ( .A1(n371), .A2(n262), .B1(n374), .B2(n263), .C1(n113),
.C2(n251), .ZN(\EX/r0data_fwd [14]) );
OAI222D1BWP U418 ( .A1(n364), .A2(n262), .B1(n378), .B2(n263), .C1(n121),
.C2(n251), .ZN(\EX/r0data_fwd [10]) );
OAI222D1BWP U419 ( .A1(n363), .A2(n262), .B1(n379), .B2(n263), .C1(n93),
.C2(n252), .ZN(\EX/r0data_fwd [9]) );
MOAI22D0BWP U420 ( .A1(n332), .A2(n326), .B1(n326), .B2(n280), .ZN(FWD[7])
);
CKBD3BWP U421 ( .I(n129), .Z(n264) );
INR2D1BWP U422 ( .A1(Branch), .B1(n250), .ZN(n129) );
NR2XD0BWP U423 ( .A1(Branch), .A2(n250), .ZN(n164) );
OAI22D1BWP U424 ( .A1(n338), .A2(n326), .B1(\ID/ReadRd ), .B2(n339), .ZN(
FWD[4]) );
OAI221D1BWP U425 ( .A1(n281), .A2(n165), .B1(n332), .B2(n327), .C(n166),
.ZN(FWD[3]) );
ND2D1BWP U426 ( .A1(n339), .A2(n333), .ZN(\ID/add_1_root_add_39_2/carry[1] )
);
MOAI22D0BWP U427 ( .A1(n317), .A2(n355), .B1(ALU_EXMEM[1]), .B2(n313), .ZN(
addr_EXMEM[1]) );
MOAI22D0BWP U428 ( .A1(n317), .A2(n356), .B1(ALU_EXMEM[2]), .B2(n314), .ZN(
addr_EXMEM[2]) );
MOAI22D0BWP U429 ( .A1(n315), .A2(n354), .B1(ALU_EXMEM[0]), .B2(n311), .ZN(
addr_EXMEM[0]) );
MOAI22D0BWP U430 ( .A1(n316), .A2(n357), .B1(ALU_EXMEM[3]), .B2(n314), .ZN(
addr_EXMEM[3]) );
MOAI22D0BWP U431 ( .A1(n316), .A2(n358), .B1(ALU_EXMEM[4]), .B2(n314), .ZN(
addr_EXMEM[4]) );
MOAI22D0BWP U432 ( .A1(n316), .A2(n359), .B1(ALU_EXMEM[5]), .B2(n314), .ZN(
addr_EXMEM[5]) );
MOAI22D0BWP U433 ( .A1(n315), .A2(n360), .B1(ALU_EXMEM[6]), .B2(n313), .ZN(
addr_EXMEM[6]) );
MOAI22D0BWP U434 ( .A1(n315), .A2(n361), .B1(ALU_EXMEM[7]), .B2(n313), .ZN(
addr_EXMEM[7]) );
MOAI22D0BWP U435 ( .A1(n315), .A2(n362), .B1(ALU_EXMEM[8]), .B2(n312), .ZN(
addr_EXMEM[8]) );
MOAI22D0BWP U436 ( .A1(n316), .A2(n363), .B1(ALU_EXMEM[9]), .B2(n311), .ZN(
addr_EXMEM[9]) );
MOAI22D0BWP U437 ( .A1(n318), .A2(n364), .B1(ALU_EXMEM[10]), .B2(n311), .ZN(
addr_EXMEM[10]) );
MOAI22D0BWP U438 ( .A1(n318), .A2(n368), .B1(ALU_EXMEM[11]), .B2(n311), .ZN(
addr_EXMEM[11]) );
MOAI22D0BWP U439 ( .A1(n318), .A2(n369), .B1(ALU_EXMEM[12]), .B2(n312), .ZN(
addr_EXMEM[12]) );
ND2D1BWP U440 ( .A1(n332), .A2(n325), .ZN(WB_IDEX[6]) );
ND2D1BWP U441 ( .A1(n337), .A2(n325), .ZN(WB_IDEX[5]) );
ND2D1BWP U442 ( .A1(n336), .A2(n325), .ZN(WB_IDEX[4]) );
ND2D1BWP U443 ( .A1(n338), .A2(n325), .ZN(WB_IDEX[3]) );
CKBD1BWP U444 ( .I(n240), .Z(n319) );
INVD1BWP U445 ( .I(n249), .ZN(n268) );
INVD1BWP U446 ( .I(n249), .ZN(n267) );
CKBD1BWP U447 ( .I(n189), .Z(n260) );
CKND2BWP U448 ( .I(n275), .ZN(n276) );
CKBD1BWP U449 ( .I(n188), .Z(n258) );
CKBD1BWP U450 ( .I(n189), .Z(n261) );
CKBD1BWP U451 ( .I(n188), .Z(n259) );
INVD1BWP U452 ( .I(n279), .ZN(n280) );
INVD1BWP U453 ( .I(n123), .ZN(n389) );
INVD1BWP U454 ( .I(n109), .ZN(n390) );
INVD1BWP U455 ( .I(n107), .ZN(n391) );
INVD1BWP U456 ( .I(n105), .ZN(n392) );
INVD1BWP U457 ( .I(n103), .ZN(n393) );
INVD1BWP U458 ( .I(n101), .ZN(n394) );
INVD1BWP U459 ( .I(n99), .ZN(n395) );
INVD1BWP U460 ( .I(n97), .ZN(n396) );
INVD1BWP U461 ( .I(n95), .ZN(n397) );
INVD1BWP U462 ( .I(n93), .ZN(n398) );
INVD1BWP U463 ( .I(n121), .ZN(n399) );
INVD1BWP U464 ( .I(n119), .ZN(n400) );
INVD1BWP U465 ( .I(n117), .ZN(n401) );
INVD1BWP U466 ( .I(n115), .ZN(n402) );
INVD1BWP U467 ( .I(n113), .ZN(n403) );
INVD1BWP U468 ( .I(n111), .ZN(n404) );
ND2D1BWP U469 ( .A1(n126), .A2(n277), .ZN(n89) );
CKBD1BWP U470 ( .I(n240), .Z(n320) );
CKBD1BWP U471 ( .I(n240), .Z(n321) );
CKBD1BWP U472 ( .I(n240), .Z(n322) );
OAI21D1BWP U473 ( .A1(n333), .A2(n339), .B(\ID/add_1_root_add_39_2/carry[1] ), .ZN(PCbranch_IDEX[0]) );
INVD1BWP U474 ( .I(n281), .ZN(n283) );
INVD1BWP U475 ( .I(n281), .ZN(n282) );
ND2D1BWP U476 ( .A1(n124), .A2(n277), .ZN(n248) );
CKBD1BWP U477 ( .I(n340), .Z(n309) );
CKBD1BWP U478 ( .I(n340), .Z(n307) );
CKBD1BWP U479 ( .I(n340), .Z(n308) );
CKBD1BWP U480 ( .I(n340), .Z(n310) );
CKBD1BWP U481 ( .I(n245), .Z(n306) );
CKBD1BWP U482 ( .I(n245), .Z(n304) );
CKBD1BWP U483 ( .I(n245), .Z(n305) );
IND4D1BWP U484 ( .A1(n227), .B1(n226), .B2(n224), .B3(n232), .ZN(n231) );
OAI31D1BWP U485 ( .A1(n176), .A2(n177), .A3(n178), .B(n179), .ZN(n173) );
IND4D1BWP U486 ( .A1(n174), .B1(n180), .B2(n171), .B3(n181), .ZN(n179) );
AOI22D1BWP U487 ( .A1(\WB/MemData [1]), .A2(n276), .B1(\WB/ALU [1]), .B2(
n405), .ZN(n109) );
OAI211D1BWP U488 ( .A1(n123), .A2(n253), .B(n220), .C(n221), .ZN(\EX/b [0])
);
AOI222D1BWP U489 ( .A1(\EX/ALUSrc[1] ), .A2(\EX/ALUSrc[0] ), .B1(\EX/imm[0] ), .B2(n258), .C1(\EX/offset [0]), .C2(n260), .ZN(n221) );
AOI22D1BWP U490 ( .A1(n254), .A2(ALU_MEMWB[0]), .B1(n256), .B2(
\EX/r1data [0]), .ZN(n220) );
OAI211D1BWP U491 ( .A1(n109), .A2(n253), .B(n206), .C(n207), .ZN(\EX/b [1])
);
AOI22D1BWP U492 ( .A1(\EX/imm[1] ), .A2(n258), .B1(\EX/offset [1]), .B2(n260), .ZN(n207) );
AOI22D1BWP U493 ( .A1(n254), .A2(ALU_MEMWB[1]), .B1(n256), .B2(
\EX/r1data [1]), .ZN(n206) );
OAI211D1BWP U494 ( .A1(n107), .A2(n253), .B(n204), .C(n205), .ZN(\EX/b [2])
);
AOI22D1BWP U495 ( .A1(\EX/imm[2] ), .A2(n259), .B1(\EX/offset [2]), .B2(n261), .ZN(n205) );
AOI22D1BWP U496 ( .A1(n255), .A2(ALU_MEMWB[2]), .B1(n257), .B2(
\EX/r1data [2]), .ZN(n204) );
OAI211D1BWP U497 ( .A1(n103), .A2(n253), .B(n200), .C(n201), .ZN(\EX/b [4])
);
AOI22D1BWP U498 ( .A1(\EX/imm[4] ), .A2(n259), .B1(\EX/offset [4]), .B2(n261), .ZN(n201) );
AOI22D1BWP U499 ( .A1(n255), .A2(ALU_MEMWB[4]), .B1(n257), .B2(
\EX/r1data [4]), .ZN(n200) );
OAI211D1BWP U500 ( .A1(n101), .A2(n253), .B(n198), .C(n199), .ZN(\EX/b [5])
);
AOI22D1BWP U501 ( .A1(\EX/imm[5] ), .A2(n259), .B1(\EX/offset [5]), .B2(n261), .ZN(n199) );
AOI22D1BWP U502 ( .A1(n255), .A2(ALU_MEMWB[5]), .B1(n257), .B2(
\EX/r1data [5]), .ZN(n198) );
OAI211D1BWP U503 ( .A1(n99), .A2(n253), .B(n196), .C(n197), .ZN(\EX/b [6])
);
AOI22D1BWP U504 ( .A1(\EX/imm[6] ), .A2(n259), .B1(\EX/offset [6]), .B2(n261), .ZN(n197) );
AOI22D1BWP U505 ( .A1(n255), .A2(ALU_MEMWB[6]), .B1(n257), .B2(
\EX/r1data [6]), .ZN(n196) );
OAI211D1BWP U506 ( .A1(n105), .A2(n253), .B(n202), .C(n203), .ZN(\EX/b [3])
);
AOI22D1BWP U507 ( .A1(\EX/imm[3] ), .A2(n259), .B1(\EX/offset [3]), .B2(n261), .ZN(n203) );
AOI22D1BWP U508 ( .A1(n255), .A2(ALU_MEMWB[3]), .B1(n257), .B2(
\EX/r1data [3]), .ZN(n202) );
OAI31D1BWP U509 ( .A1(n175), .A2(n174), .A3(n329), .B(n251), .ZN(n168) );
ND3D1BWP U510 ( .A1(n170), .A2(\DF/RegWrite[0] ), .A3(n171), .ZN(n175) );
ND4D1BWP U511 ( .A1(n170), .A2(\DF/RegWrite[0] ), .A3(n171), .A4(n172), .ZN(
n169) );
NR3D0BWP U512 ( .A1(n173), .A2(n174), .A3(n329), .ZN(n172) );
ND3D1BWP U513 ( .A1(n238), .A2(\DF/RegWrite[0] ), .A3(n239), .ZN(n235) );
AN4D1BWP U514 ( .A1(n223), .A2(n224), .A3(\DF/RegWrite[0] ), .A4(n225), .Z(
n126) );
INR3D0BWP U515 ( .A1(n226), .B1(\DF/MemToReg[0] ), .B2(n227), .ZN(n225) );
ND3D1BWP U516 ( .A1(n233), .A2(n183), .A3(n234), .ZN(n228) );
ND3D1BWP U517 ( .A1(n182), .A2(n183), .A3(n184), .ZN(n176) );
INVD1BWP U518 ( .I(\DF/write_addr[2] ), .ZN(n331) );
AN3XD1BWP U519 ( .A1(n170), .A2(\DF/RegWrite[0] ), .A3(\DF/MemToReg[0] ),
.Z(n181) );
AN3XD1BWP U520 ( .A1(\DF/MemToReg[0] ), .A2(\DF/RegWrite[0] ), .A3(n223),
.Z(n232) );
INVD1BWP U521 ( .I(\WB/WB[0] ), .ZN(n275) );
AOI22D1BWP U522 ( .A1(\WB/MemData [0]), .A2(n276), .B1(\WB/ALU [0]), .B2(
n405), .ZN(n123) );
AOI22D1BWP U523 ( .A1(\WB/MemData [8]), .A2(n276), .B1(\WB/ALU [8]), .B2(
n405), .ZN(n95) );
AOI22D1BWP U524 ( .A1(n276), .A2(\WB/MemData [9]), .B1(\WB/ALU [9]), .B2(
n405), .ZN(n93) );
AOI22D1BWP U525 ( .A1(\WB/MemData [2]), .A2(n276), .B1(\WB/ALU [2]), .B2(
n405), .ZN(n107) );
AOI22D1BWP U526 ( .A1(\WB/MemData [10]), .A2(n276), .B1(\WB/ALU [10]), .B2(
n405), .ZN(n121) );
AOI22D1BWP U527 ( .A1(\WB/MemData [3]), .A2(n276), .B1(\WB/ALU [3]), .B2(
n405), .ZN(n105) );
AOI22D1BWP U528 ( .A1(\WB/MemData [11]), .A2(\WB/WB[0] ), .B1(\WB/ALU [11]),
.B2(n405), .ZN(n119) );
AOI22D1BWP U529 ( .A1(\WB/MemData [4]), .A2(n276), .B1(\WB/ALU [4]), .B2(
n405), .ZN(n103) );
AOI22D1BWP U530 ( .A1(\WB/MemData [12]), .A2(\WB/WB[0] ), .B1(\WB/ALU [12]),
.B2(n405), .ZN(n117) );
AOI22D1BWP U531 ( .A1(\WB/MemData [5]), .A2(n276), .B1(\WB/ALU [5]), .B2(
n405), .ZN(n101) );
AOI22D1BWP U532 ( .A1(\WB/MemData [13]), .A2(\WB/WB[0] ), .B1(\WB/ALU [13]),
.B2(n405), .ZN(n115) );
AOI22D1BWP U533 ( .A1(\WB/MemData [6]), .A2(n276), .B1(\WB/ALU [6]), .B2(
n405), .ZN(n99) );
AOI22D1BWP U534 ( .A1(\WB/MemData [14]), .A2(\WB/WB[0] ), .B1(\WB/ALU [14]),
.B2(n405), .ZN(n113) );
AOI22D1BWP U535 ( .A1(\WB/MemData [7]), .A2(n276), .B1(\WB/ALU [7]), .B2(
n405), .ZN(n97) );
AOI22D1BWP U536 ( .A1(\WB/MemData [15]), .A2(n276), .B1(\WB/ALU [15]), .B2(
n405), .ZN(n111) );
INVD1BWP U537 ( .I(rst), .ZN(n328) );
OAI211D1BWP U538 ( .A1(n97), .A2(n253), .B(n194), .C(n195), .ZN(\EX/b [7])
);
AOI22D1BWP U539 ( .A1(\EX/imm[7] ), .A2(n259), .B1(\EX/offset [7]), .B2(n261), .ZN(n195) );
AOI22D1BWP U540 ( .A1(n255), .A2(ALU_MEMWB[7]), .B1(n257), .B2(
\EX/r1data [7]), .ZN(n194) );
OAI211D1BWP U541 ( .A1(n111), .A2(n253), .B(n208), .C(n209), .ZN(\EX/b [15])
);
AOI22D1BWP U542 ( .A1(\EX/imm[15] ), .A2(n258), .B1(\EX/offset [15]), .B2(
n260), .ZN(n209) );
AOI22D1BWP U543 ( .A1(n254), .A2(ALU_MEMWB[15]), .B1(n256), .B2(
\EX/r1data [15]), .ZN(n208) );
MOAI22D0BWP U544 ( .A1(n337), .A2(n326), .B1(n326), .B2(PCcall[2]), .ZN(
FWD[6]) );
MOAI22D0BWP U545 ( .A1(n336), .A2(n326), .B1(n326), .B2(PCcall[1]), .ZN(
FWD[5]) );
CKBD4BWP U546 ( .I(n132), .Z(n265) );
INR3D0BWP U547 ( .A1(n164), .B1(n319), .B2(Ret), .ZN(n132) );
OAI22D1BWP U548 ( .A1(n338), .A2(n327), .B1(n167), .B2(n165), .ZN(FWD[0]) );
NR2XD0BWP U549 ( .A1(\ID/CallRet ), .A2(PCcall[4]), .ZN(n167) );
OAI211D1BWP U550 ( .A1(n95), .A2(n253), .B(n192), .C(n193), .ZN(\EX/b [8])
);
AOI22D1BWP U551 ( .A1(\EX/imm[8] ), .A2(n259), .B1(\EX/offset [8]), .B2(n261), .ZN(n193) );
AOI22D1BWP U552 ( .A1(n255), .A2(ALU_MEMWB[8]), .B1(n257), .B2(
\EX/r1data [8]), .ZN(n192) );
OAI211D1BWP U553 ( .A1(n93), .A2(n253), .B(n186), .C(n187), .ZN(\EX/b [9])
);
AOI22D1BWP U554 ( .A1(\EX/imm[9] ), .A2(n259), .B1(\EX/offset [9]), .B2(n261), .ZN(n187) );
AOI22D1BWP U555 ( .A1(n255), .A2(ALU_MEMWB[9]), .B1(n257), .B2(
\EX/r1data [9]), .ZN(n186) );
OAI211D1BWP U556 ( .A1(n121), .A2(n253), .B(n218), .C(n219), .ZN(\EX/b [10])
);
AOI22D1BWP U557 ( .A1(\EX/imm[10] ), .A2(n258), .B1(\EX/offset [10]), .B2(
n260), .ZN(n219) );
AOI22D1BWP U558 ( .A1(n254), .A2(ALU_MEMWB[10]), .B1(n256), .B2(
\EX/r1data [10]), .ZN(n218) );
OAI211D1BWP U559 ( .A1(n119), .A2(n253), .B(n216), .C(n217), .ZN(\EX/b [11])
);
AOI22D1BWP U560 ( .A1(\EX/imm[11] ), .A2(n258), .B1(\EX/offset [11]), .B2(
n260), .ZN(n217) );
AOI22D1BWP U561 ( .A1(n254), .A2(ALU_MEMWB[11]), .B1(n256), .B2(
\EX/r1data [11]), .ZN(n216) );
OAI211D1BWP U562 ( .A1(n117), .A2(n253), .B(n214), .C(n215), .ZN(\EX/b [12])
);
AOI22D1BWP U563 ( .A1(\EX/imm[12] ), .A2(n258), .B1(\EX/offset [12]), .B2(
n260), .ZN(n215) );
AOI22D1BWP U564 ( .A1(n254), .A2(ALU_MEMWB[12]), .B1(n256), .B2(
\EX/r1data [12]), .ZN(n214) );
OAI211D1BWP U565 ( .A1(n115), .A2(n253), .B(n212), .C(n213), .ZN(\EX/b [13])
);
AOI22D1BWP U566 ( .A1(\EX/imm[13] ), .A2(n258), .B1(\EX/offset [13]), .B2(
n260), .ZN(n213) );
AOI22D1BWP U567 ( .A1(n254), .A2(ALU_MEMWB[13]), .B1(n256), .B2(
\EX/r1data [13]), .ZN(n212) );
OAI211D1BWP U568 ( .A1(n113), .A2(n253), .B(n210), .C(n211), .ZN(\EX/b [14])
);
AOI22D1BWP U569 ( .A1(\EX/imm[14] ), .A2(n258), .B1(\EX/offset [14]), .B2(
n260), .ZN(n211) );
AOI22D1BWP U570 ( .A1(n254), .A2(ALU_MEMWB[14]), .B1(n256), .B2(
\EX/r1data [14]), .ZN(n210) );
OAI221D1BWP U571 ( .A1(n335), .A2(n165), .B1(n337), .B2(n327), .C(n166),
.ZN(FWD[2]) );
OAI221D1BWP U572 ( .A1(n334), .A2(n165), .B1(n336), .B2(n327), .C(n166),
.ZN(FWD[1]) );
CKBD3BWP U573 ( .I(n131), .Z(n266) );
INR3D0BWP U574 ( .A1(n164), .B1(n265), .B2(Ret), .ZN(n131) );
NR2XD0BWP U575 ( .A1(\EX/ALUSrc[0] ), .A2(\EX/ALUSrc[1] ), .ZN(n222) );
IND3D1BWP U576 ( .A1(\ID/BCR ), .B1(n328), .B2(n319), .ZN(\ID/rst_ctrl ) );
INVD1BWP U577 ( .I(ALU_MEMWB[3]), .ZN(n385) );
INVD1BWP U578 ( .I(ALU_MEMWB[0]), .ZN(n386) );
INVD1BWP U579 ( .I(ALU_MEMWB[2]), .ZN(n387) );
INVD1BWP U580 ( .I(ALU_MEMWB[1]), .ZN(n388) );
INVD1BWP U581 ( .I(ALU_MEMWB[4]), .ZN(n384) );
INVD1BWP U582 ( .I(ALU_MEMWB[5]), .ZN(n383) );
INVD1BWP U583 ( .I(ALU_MEMWB[6]), .ZN(n382) );
INVD1BWP U584 ( .I(ALU_MEMWB[7]), .ZN(n381) );
INVD1BWP U585 ( .I(ALU_MEMWB[8]), .ZN(n380) );
INVD1BWP U586 ( .I(ALU_MEMWB[9]), .ZN(n379) );
INVD1BWP U587 ( .I(ALU_MEMWB[10]), .ZN(n378) );
INVD1BWP U588 ( .I(ALU_MEMWB[11]), .ZN(n377) );
INVD1BWP U589 ( .I(ALU_MEMWB[12]), .ZN(n376) );
INVD1BWP U590 ( .I(ALU_MEMWB[13]), .ZN(n375) );
INR2D1BWP U591 ( .A1(\EX/ALUSrc[1] ), .B1(\EX/ALUSrc[0] ), .ZN(n189) );
INR2D1BWP U592 ( .A1(\EX/ALUSrc[0] ), .B1(\EX/ALUSrc[1] ), .ZN(n188) );
INVD1BWP U593 ( .I(\EX/r0data [3]), .ZN(n357) );
INVD1BWP U594 ( .I(\EX/r0data [0]), .ZN(n354) );
INVD1BWP U595 ( .I(\EX/r0data [2]), .ZN(n356) );
INVD1BWP U596 ( .I(\EX/r0data [1]), .ZN(n355) );
INVD1BWP U597 ( .I(\EX/r0data [4]), .ZN(n358) );
INVD1BWP U598 ( .I(\EX/r0data [5]), .ZN(n359) );
INVD1BWP U599 ( .I(\EX/r0data [6]), .ZN(n360) );
INVD1BWP U600 ( .I(\EX/r0data [7]), .ZN(n361) );
INVD1BWP U601 ( .I(\EX/r0data [8]), .ZN(n362) );
INVD1BWP U602 ( .I(\EX/r0data [9]), .ZN(n363) );
INVD1BWP U603 ( .I(\EX/r0data [10]), .ZN(n364) );
INVD1BWP U604 ( .I(\EX/r0data [11]), .ZN(n368) );
INVD1BWP U605 ( .I(\EX/r0data [12]), .ZN(n369) );
ND2D1BWP U606 ( .A1(n162), .A2(n163), .ZN(\IF/n39 ) );
AOI22D1BWP U607 ( .A1(PCbranch[15]), .A2(n264), .B1(\IF/PC[15] ), .B2(n265),
.ZN(n162) );
AOI22D1BWP U608 ( .A1(PC_inc_IFID[15]), .A2(n157), .B1(PCret[15]), .B2(n267),
.ZN(n163) );
ND2D1BWP U609 ( .A1(n160), .A2(n161), .ZN(\IF/n40 ) );
AOI22D1BWP U610 ( .A1(PCbranch[14]), .A2(n264), .B1(\IF/PC[14] ), .B2(n265),
.ZN(n160) );
AOI22D1BWP U611 ( .A1(PC_inc_IFID[14]), .A2(n157), .B1(PCret[14]), .B2(n268),
.ZN(n161) );
ND2D1BWP U612 ( .A1(n158), .A2(n159), .ZN(\IF/n41 ) );
AOI22D1BWP U613 ( .A1(PCbranch[13]), .A2(n264), .B1(\IF/PC[13] ), .B2(n265),
.ZN(n158) );
AOI22D1BWP U614 ( .A1(PC_inc_IFID[13]), .A2(n157), .B1(PCret[13]), .B2(n267),
.ZN(n159) );
ND2D1BWP U615 ( .A1(n155), .A2(n156), .ZN(\IF/n42 ) );
AOI22D1BWP U616 ( .A1(PCbranch[12]), .A2(n264), .B1(\IF/PC[12] ), .B2(n265),
.ZN(n155) );
AOI22D1BWP U617 ( .A1(PC_inc_IFID[12]), .A2(n157), .B1(PCret[12]), .B2(n268),
.ZN(n156) );
ND2D1BWP U618 ( .A1(n153), .A2(n154), .ZN(\IF/n43 ) );
AOI22D1BWP U619 ( .A1(\IF/PC[11] ), .A2(n265), .B1(PCcall[11]), .B2(n250),
.ZN(n153) );
AOI222D1BWP U620 ( .A1(PCbranch[11]), .A2(n264), .B1(PCret[11]), .B2(n267),
.C1(PC_inc_IFID[11]), .C2(n266), .ZN(n154) );
ND2D1BWP U621 ( .A1(n151), .A2(n152), .ZN(\IF/n44 ) );
AOI22D1BWP U622 ( .A1(\IF/PC[10] ), .A2(n265), .B1(PCcall[10]), .B2(n250),
.ZN(n151) );
AOI222D1BWP U623 ( .A1(PCbranch[10]), .A2(n264), .B1(PCret[10]), .B2(n268),
.C1(PC_inc_IFID[10]), .C2(n266), .ZN(n152) );
ND2D1BWP U624 ( .A1(n149), .A2(n150), .ZN(\IF/n45 ) );
AOI22D1BWP U625 ( .A1(\IF/PC[9] ), .A2(n265), .B1(PCcall[9]), .B2(n250),
.ZN(n149) );
AOI222D1BWP U626 ( .A1(PCbranch[9]), .A2(n264), .B1(PCret[9]), .B2(n267),
.C1(PC_inc_IFID[9]), .C2(n266), .ZN(n150) );
ND2D1BWP U627 ( .A1(n147), .A2(n148), .ZN(\IF/n46 ) );
AOI22D1BWP U628 ( .A1(\IF/PC[8] ), .A2(n265), .B1(PCcall[8]), .B2(n250),
.ZN(n147) );
AOI222D1BWP U629 ( .A1(PCbranch[8]), .A2(n264), .B1(PCret[8]), .B2(n268),
.C1(PC_inc_IFID[8]), .C2(n266), .ZN(n148) );
ND2D1BWP U630 ( .A1(n143), .A2(n144), .ZN(\IF/n48 ) );
AOI22D1BWP U631 ( .A1(\IF/PC[6] ), .A2(n265), .B1(PCcall[6]), .B2(n250),
.ZN(n143) );
AOI222D1BWP U632 ( .A1(PCbranch[6]), .A2(n264), .B1(PCret[6]), .B2(n268),
.C1(PC_inc_IFID[6]), .C2(n266), .ZN(n144) );
ND2D1BWP U633 ( .A1(n141), .A2(n142), .ZN(\IF/n49 ) );
AOI22D1BWP U634 ( .A1(\IF/PC[5] ), .A2(n265), .B1(PCcall[5]), .B2(n250),
.ZN(n141) );
AOI222D1BWP U635 ( .A1(PCbranch[5]), .A2(n264), .B1(PCret[5]), .B2(n267),
.C1(PC_inc_IFID[5]), .C2(n266), .ZN(n142) );
ND2D1BWP U636 ( .A1(n139), .A2(n140), .ZN(\IF/n50 ) );
AOI22D1BWP U637 ( .A1(\IF/PC[4] ), .A2(n265), .B1(PCcall[4]), .B2(n250),
.ZN(n139) );
AOI222D1BWP U638 ( .A1(PCbranch[4]), .A2(n264), .B1(PCret[4]), .B2(n268),
.C1(PC_inc_IFID[4]), .C2(n266), .ZN(n140) );
ND2D1BWP U639 ( .A1(n137), .A2(n138), .ZN(\IF/n51 ) );
AOI22D1BWP U640 ( .A1(\IF/PC[3] ), .A2(n265), .B1(n280), .B2(n250), .ZN(n137) );
AOI222D1BWP U641 ( .A1(PCbranch[3]), .A2(n264), .B1(PCret[3]), .B2(n267),
.C1(PC_inc_IFID[3]), .C2(n266), .ZN(n138) );
ND2D1BWP U642 ( .A1(n135), .A2(n136), .ZN(\IF/n52 ) );
AOI22D1BWP U643 ( .A1(\IF/PC[2] ), .A2(n265), .B1(PCcall[2]), .B2(n250),
.ZN(n135) );
AOI222D1BWP U644 ( .A1(PCbranch[2]), .A2(n264), .B1(PCret[2]), .B2(n268),
.C1(PC_inc_IFID[2]), .C2(n266), .ZN(n136) );
ND2D1BWP U645 ( .A1(n133), .A2(n134), .ZN(\IF/n53 ) );
AOI22D1BWP U646 ( .A1(\IF/PC[1] ), .A2(n265), .B1(PCcall[1]), .B2(n250),
.ZN(n133) );
AOI222D1BWP U647 ( .A1(PCbranch[1]), .A2(n264), .B1(PCret[1]), .B2(n267),
.C1(PC_inc_IFID[1]), .C2(n266), .ZN(n134) );
ND2D1BWP U648 ( .A1(n127), .A2(n128), .ZN(\IF/n54 ) );
AOI22D1BWP U649 ( .A1(\IF/PC[0] ), .A2(n265), .B1(n250), .B2(PCcall[0]),
.ZN(n127) );
AOI222D1BWP U650 ( .A1(PCbranch[0]), .A2(n264), .B1(PCret[0]), .B2(n268),
.C1(PC_inc_IFID[0]), .C2(n266), .ZN(n128) );
ND2D1BWP U651 ( .A1(n145), .A2(n146), .ZN(\IF/n47 ) );
AOI22D1BWP U652 ( .A1(\IF/PC[7] ), .A2(n265), .B1(n241), .B2(n250), .ZN(n145) );
AOI222D1BWP U653 ( .A1(PCbranch[7]), .A2(n264), .B1(PCret[7]), .B2(n267),
.C1(PC_inc_IFID[7]), .C2(n266), .ZN(n146) );
ND2D1BWP U654 ( .A1(Ret), .A2(n164), .ZN(n249) );
INVD1BWP U655 ( .I(\EX/EX[7] ), .ZN(n340) );
INVD1BWP U656 ( .I(ALU_MEMWB[14]), .ZN(n374) );
INVD1BWP U657 ( .I(ALU_MEMWB[15]), .ZN(n373) );
OAI221D1BWP U658 ( .A1(n269), .A2(n386), .B1(n271), .B2(n341), .C(n122),
.ZN(data_EXMEM[0]) );
INVD1BWP U659 ( .I(\EX/r1data [0]), .ZN(n341) );
AOI22D1BWP U660 ( .A1(n273), .A2(n389), .B1(\EX/PC_inc [0]), .B2(\EX/EX[6] ),
.ZN(n122) );
OAI221D1BWP U661 ( .A1(n269), .A2(n373), .B1(n271), .B2(n367), .C(n110),
.ZN(data_EXMEM[15]) );
INVD1BWP U662 ( .I(\EX/r1data [15]), .ZN(n367) );
AOI22D1BWP U663 ( .A1(n273), .A2(n404), .B1(\EX/PC_inc [15]), .B2(\EX/EX[6] ), .ZN(n110) );
OAI221D1BWP U664 ( .A1(n269), .A2(n374), .B1(n271), .B2(n366), .C(n112),
.ZN(data_EXMEM[14]) );
INVD1BWP U665 ( .I(\EX/r1data [14]), .ZN(n366) );
AOI22D1BWP U666 ( .A1(n273), .A2(n403), .B1(\EX/PC_inc [14]), .B2(\EX/EX[6] ), .ZN(n112) );
OAI221D1BWP U667 ( .A1(n269), .A2(n375), .B1(n271), .B2(n365), .C(n114),
.ZN(data_EXMEM[13]) );
INVD1BWP U668 ( .I(\EX/r1data [13]), .ZN(n365) );
AOI22D1BWP U669 ( .A1(n273), .A2(n402), .B1(\EX/PC_inc [13]), .B2(\EX/EX[6] ), .ZN(n114) );
OAI221D1BWP U670 ( .A1(n269), .A2(n376), .B1(n271), .B2(n353), .C(n116),
.ZN(data_EXMEM[12]) );
INVD1BWP U671 ( .I(\EX/r1data [12]), .ZN(n353) );
AOI22D1BWP U672 ( .A1(n273), .A2(n401), .B1(\EX/PC_inc [12]), .B2(\EX/EX[6] ), .ZN(n116) );
OAI221D1BWP U673 ( .A1(n269), .A2(n377), .B1(n271), .B2(n352), .C(n118),
.ZN(data_EXMEM[11]) );
INVD1BWP U674 ( .I(\EX/r1data [11]), .ZN(n352) );
AOI22D1BWP U675 ( .A1(n273), .A2(n400), .B1(\EX/PC_inc [11]), .B2(\EX/EX[6] ), .ZN(n118) );
OAI221D1BWP U676 ( .A1(n269), .A2(n378), .B1(n271), .B2(n351), .C(n120),
.ZN(data_EXMEM[10]) );
INVD1BWP U677 ( .I(\EX/r1data [10]), .ZN(n351) );
AOI22D1BWP U678 ( .A1(n273), .A2(n399), .B1(\EX/PC_inc [10]), .B2(\EX/EX[6] ), .ZN(n120) );
OAI221D1BWP U679 ( .A1(n270), .A2(n379), .B1(n272), .B2(n350), .C(n91), .ZN(
data_EXMEM[9]) );
INVD1BWP U680 ( .I(\EX/r1data [9]), .ZN(n350) );
AOI22D1BWP U681 ( .A1(n274), .A2(n398), .B1(\EX/PC_inc [9]), .B2(n278), .ZN(
n91) );
OAI221D1BWP U682 ( .A1(n270), .A2(n380), .B1(n272), .B2(n349), .C(n94), .ZN(
data_EXMEM[8]) );
INVD1BWP U683 ( .I(\EX/r1data [8]), .ZN(n349) );
AOI22D1BWP U684 ( .A1(n274), .A2(n397), .B1(\EX/PC_inc [8]), .B2(n278), .ZN(
n94) );
OAI221D1BWP U685 ( .A1(n270), .A2(n381), .B1(n272), .B2(n348), .C(n96), .ZN(
data_EXMEM[7]) );
INVD1BWP U686 ( .I(\EX/r1data [7]), .ZN(n348) );
AOI22D1BWP U687 ( .A1(n274), .A2(n396), .B1(\EX/PC_inc [7]), .B2(n278), .ZN(
n96) );
OAI221D1BWP U688 ( .A1(n270), .A2(n382), .B1(n272), .B2(n347), .C(n98), .ZN(
data_EXMEM[6]) );
INVD1BWP U689 ( .I(\EX/r1data [6]), .ZN(n347) );
AOI22D1BWP U690 ( .A1(n274), .A2(n395), .B1(\EX/PC_inc [6]), .B2(n278), .ZN(
n98) );
OAI221D1BWP U691 ( .A1(n270), .A2(n383), .B1(n272), .B2(n346), .C(n100),
.ZN(data_EXMEM[5]) );
INVD1BWP U692 ( .I(\EX/r1data [5]), .ZN(n346) );
AOI22D1BWP U693 ( .A1(n274), .A2(n394), .B1(\EX/PC_inc [5]), .B2(n278), .ZN(
n100) );
OAI221D1BWP U694 ( .A1(n270), .A2(n384), .B1(n272), .B2(n345), .C(n102),
.ZN(data_EXMEM[4]) );
INVD1BWP U695 ( .I(\EX/r1data [4]), .ZN(n345) );
AOI22D1BWP U696 ( .A1(n274), .A2(n393), .B1(\EX/PC_inc [4]), .B2(n278), .ZN(
n102) );
OAI221D1BWP U697 ( .A1(n270), .A2(n385), .B1(n272), .B2(n344), .C(n104),
.ZN(data_EXMEM[3]) );
INVD1BWP U698 ( .I(\EX/r1data [3]), .ZN(n344) );
AOI22D1BWP U699 ( .A1(n274), .A2(n392), .B1(\EX/PC_inc [3]), .B2(n278), .ZN(
n104) );
OAI221D1BWP U700 ( .A1(n270), .A2(n387), .B1(n272), .B2(n343), .C(n106),
.ZN(data_EXMEM[2]) );
INVD1BWP U701 ( .I(\EX/r1data [2]), .ZN(n343) );
AOI22D1BWP U702 ( .A1(n274), .A2(n391), .B1(\EX/PC_inc [2]), .B2(n278), .ZN(
n106) );
OAI221D1BWP U703 ( .A1(n269), .A2(n388), .B1(n271), .B2(n342), .C(n108),
.ZN(data_EXMEM[1]) );
INVD1BWP U704 ( .I(\EX/r1data [1]), .ZN(n342) );
AOI22D1BWP U705 ( .A1(n273), .A2(n390), .B1(\EX/PC_inc [1]), .B2(\EX/EX[6] ),
.ZN(n108) );
INVD1BWP U706 ( .I(\EX/r0data [13]), .ZN(n370) );
INVD1BWP U707 ( .I(\EX/r0data [14]), .ZN(n371) );
INVD1BWP U708 ( .I(\EX/r0data [15]), .ZN(n372) );
INVD1BWP U709 ( .I(\EX/EX[6] ), .ZN(n277) );
TIELBWP U710 ( .ZN(n323) );
TIEHBWP U711 ( .Z(n324) );
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FAHCIN_BEHAVIORAL_V
`define SKY130_FD_SC_MS__FAHCIN_BEHAVIORAL_V
/**
* fahcin: Full adder, inverted carry in.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fahcin (
COUT,
SUM ,
A ,
B ,
CIN
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire ci ;
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
not not0 (ci , CIN );
xor xor0 (xor0_out_SUM, A, B, ci );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, ci );
and and2 (b_ci , B, ci );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FAHCIN_BEHAVIORAL_V |
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam_reg.v: Register-based Binary Content Addressasble Memory (BCAM) //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module bcam_reg
#( parameter CAMD = 16, // CAM depth
parameter CAMW = 4 , // CAM/pattern width
parameter PIPE = 0 , // Pipelined? (binary; 0 or 1)
parameter INOM = 1 ) // binary / Initial CAM with no match
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CAMD)-1:0] wAddr , // write address
input [ CAMW -1:0] wPatt , // write pattern
input [ CAMW -1:0] mPatt , // patern to match
output match , // match indicator
output [`log2(CAMD)-1:0] mAddr ); // matched address
// wAddr one-hot decoder
reg [CAMD-1:0] lineWEnb;
always @(*) begin
lineWEnb = {CAMD{1'b0}};
lineWEnb[wAddr] = wEnb ;
end
// write data and valid bit (MSB)
reg [CAMW:0] CAMReg [0:CAMD-1];
integer i;
always @(posedge clk, posedge rst)
for (i=0; i<CAMD; i=i+1)
if (rst && INOM) CAMReg[i] <= {(CAMW+1){1'b0}};
else if (lineWEnb[i]) CAMReg[i] <= {1'b1,wPatt};
// onehot match
reg [CAMD-1:0] matchOnehot;
always @(*)
for (i=0; i<CAMD; i=i+1)
matchOnehot[i] = (CAMReg[i] == {1'b1,mPatt});
// binary match (priority encoded) with CAMD width
// generated automatically by ./pe script
pe_camd pe_reg_inst (
.clk( clk ), // clock for pipelined priority encoder
.rst( rst ), // registers reset for pipelined priority encoder
.oht( matchOnehot ), // one-hot match input / in : [ CAMD -1:0]
.bin( mAddr ), // first match index / out: [`log2(CAMD)-1:0]
.vld( match ) // match indicator / out
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 10
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12]" *)
output wire [23 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12]" *)
input wire [23 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12]" *)
output wire [23 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *)
output wire [63 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *)
output wire [15 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *)
output wire [3 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *)
output wire [5 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *)
output wire [7 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *)
output wire [1 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *)
input wire [1 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12]" *)
input wire [23 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *)
input wire [3 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *)
input wire [1 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *)
output wire [1 : 0] m_axi_rready;
axi_crossbar_v2_1_10_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(2),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(128'Hffffffffffffffff0000000040400000),
.C_M_AXI_ADDR_WIDTH(64'H0000000000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H0000000c),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_M_AXI_READ_CONNECTIVITY(64'HFFFFFFFFFFFFFFFF),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(32'H00000000),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000008),
.C_S_AXI_READ_ACCEPTANCE(32'H00000008),
.C_M_AXI_WRITE_ISSUING(64'H0000000800000008),
.C_M_AXI_READ_ISSUING(64'H0000000800000008),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(2'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(2'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2BB2AI_TB_V
`define SKY130_FD_SC_HD__O2BB2AI_TB_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o2bb2ai.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hd__o2bb2ai dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2BB2AI_TB_V
|
// EE 471 Lab 1, Beck Pang, Spring 2015
// Main function for calling different counter onto the board
// @require: only call one counter a time
module DE1_SoC (CLOCK_50, LEDR, HEX0, HEX1, HEX2, HEX3, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output reg [9:0] LEDR;
output [6:0] HEX0, HEX1, HEX2, HEX3;
input [9:0] SW;
input [3:0] KEY;
reg [31:0] A, B, data;
reg [1:0] count, currMode;
wire clk, enter, run, res, Z, V, C, N;
wire [2:0] oper;
wire [1:0] sel;
assign clk = CLOCK_50;
//Interpreted by the system as an Enter. When Enter is pressed
// the ALU will read the state of the input switches and respond accordingly
assign enter = ~KEY[0];
//Directs the ALU to perform the specified operation and display the results.
assign run = ~KEY[1];
// sets the hex digits
assign digits = SW[3:0];
// Operation code
assign oper = SW[6:4];
// Specify whether operand A or B is to be entered or the result is to be displayed
assign sel = SW[9:8];
// controls the hex
hexOnHex hex0(data[3:0], HEX0);
hexOnHex hex1(data[7:4], HEX1);
hexOnHex hex2(data[11:8], HEX2);
hexOnHex hex3(data[15:12], HEX3);
always @(posedge clk) begin
if(enter) begin
case(sel)
0: begin
data = A;
currMode =
end
1: begin
data = B;
end
2: begin
end
3: begin
end
default:
endcase
case(oper)
0: //NOP
1: //ADD
2: //SUB
3: //AND
4: //OR
5: //XOR
6: //SLT
7: //SLL
default:
endcase
case(digits)
endcase
end
else if (run) begin
0: begin
data = A;
end
1: begin
data = B;
end
2: begin
end
3: begin
end
default:
endcase
case(oper)
0: //NOP
1: //ADD
2: //SUB
3: //AND
4: //OR
5: //XOR
6: //SLT
7: //SLL
default:
endcase
case(digits)
endcase
end
endmodule
/*
wire clk;
wire [15:0] data;
reg [6:0] hold;
reg WrEn, regWR;
reg [10:0] adx;
reg [15:0] store;
wire [1:0] state, blockSel;
wire clkControl, rst, slowClk, outSel;
reg [4:0] readAdd0, readAdd1, writeAdd;
reg [31:0] writeData;
wire [31:0] readOutput0, readOutput1;
//reg [15:0] data;
//assign data[6:0] = SW[6:0]
assign clkControl = SW[8];
assign state = SW[7:6];
assign blockSel = SW[5:4];
assign outSel = SW[3];
assign rst = SW[9];
assign data = WrEn ? 16'bZ : store;
SRAM2Kby16 memory(clk, adx, WrEn, data);
clkSlower counter(slowClk, CLOCK_50, rst);
registerFile regs(clk, readAdd0, readAdd1, writeAdd, regWR, writeData, readOutput0, readOutput1);
always @(posedge clk) begin
if(rst) begin
hold = 0;
adx = 0;
WrEn = 1;
LEDR = 0;
end else if(state == 0) begin
WrEn = 0;
adx = hold;
store = 7'b1111111 - hold;
LEDR[6:0] = hold;
end else if(state == 1) begin
WrEn = 1;
regWR = 1;
writeAdd = hold[4:0];
adx = blockSel * 32 + hold[4:0];
writeData[15:0] = data;
end else if(state == 2) begin
WrEn = 1;
regWR = 0;
readAdd0 = hold[3:0];
readAdd1 = 16 + hold[3:0];
LEDR = outSel ? readOutput0[9:0] : readOutput1[9:0];
end else if(state == 3) begin
WrEn = 0;
regWR = 0;
if(blockSel[0]) begin
readAdd1 = hold[5:2] + 16;
if(hold[0]) begin
store = readOutput1[15:0];
adx = 179 + hold[5:2];
end else begin
store = readOutput1[15:0];
adx = 145 + hold[5:2];
end
end else begin
readAdd0 = hold[5:2];
if(hold[0]) begin
store = readOutput0[15:0];
adx = 162 + hold[5:2];
end else begin
store = readOutput0[15:0];
adx = 128 + hold[5:2];
end
end
end
hold = hold + 1'b1;
end
assign clk = clkControl ? slowClk : CLOCK_50;
endmodule
module SendP2SBufferTestbench();
reg CLOCK_50; // connect to system 50 MHz clock
wire [9:0] LEDR;
reg [9:0] SW;
reg [3:0] KEY;
DE1_SoC dut (CLOCK_50, LEDR, SW, KEY);
// Set up the clocking
parameter d = 20;
initial begin
CLOCK_50 = 1;
SW = 12;
KEY = 0;
end
always #(d/2) CLOCK_50 = ~CLOCK_50;
// Set up the inputs to the design
initial begin
#(d*10); SW[9] = 1;
#d; SW[9] = 0; SW[8] = 1;
#(d*500); SW[8] = 0;
#d SW[5:0] = 64;
#d SW[5:0] = 32;
#d SW[5:0] = 16;
#d SW[5:0] = 8;
#d SW[5:0] = 120;
$stop;
end
endmodule
*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o311a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O311A_FUNCTIONAL_PP_V |
(* src = "../../verilog/extadc.v:1" *)
module ExtADC (
(* intersynth_port = "Reset_n_i", src = "../../verilog/extadc.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/extadc.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/extadc.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/extadc.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:11" *)
output SensorPower_o,
(* intersynth_conntype = "Bit", intersynth_port = "Outputs_o", src = "../../verilog/extadc.v:13" *)
output SensorStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "Inputs_i", src = "../../verilog/extadc.v:15" *)
input SensorReady_i,
(* intersynth_conntype = "Bit", intersynth_port = "AdcDoConvert_o", src = "../../verilog/extadc.v:17" *)
output AdcStart_o,
(* intersynth_conntype = "Bit", intersynth_port = "AdcConvComplete_i", src = "../../verilog/extadc.v:19" *)
input AdcDone_i,
(* intersynth_conntype = "Word", intersynth_port = "AdcValue_i", src = "../../verilog/extadc.v:21" *)
input[15:0] AdcValue_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPreset_i", src = "../../verilog/extadc.v:23" *)
input[15:0] PeriodCounterPreset_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/extadc.v:25" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/extadc.v:27" *)
input[15:0] Threshold_i
);
(* src = "../../verilog/extadc.v:142" *)
wire [15:0] \$0\Timer[15:0] ;
(* src = "../../verilog/extadc.v:169" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$2\SensorPower_o[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$2\StoreNewValue[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$2\TimerPreset[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$3\TimerEnable[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$3\TimerPreset[0:0] ;
(* src = "../../verilog/extadc.v:58" *)
wire \$4\TimerEnable[0:0] ;
wire \$procmux$190_CMP ;
wire \$procmux$193_CMP ;
wire \$procmux$194_CMP ;
wire \$procmux$199_CMP ;
wire \$procmux$202_CMP ;
wire [15:0] \$procmux$23_Y ;
(* src = "../../verilog/extadc.v:156" *)
wire [15:0] \$sub$../../verilog/extadc.v:156$12_Y ;
(* src = "../../verilog/extadc.v:167" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/extadc.v:184" *)
wire [16:0] DiffAB;
(* src = "../../verilog/extadc.v:185" *)
wire [15:0] DiffBA;
(* src = "../../verilog/extadc.v:42" *)
wire DiffTooLarge;
(* src = "../../verilog/extadc.v:43" *)
wire StoreNewValue;
(* src = "../../verilog/extadc.v:140" *)
wire [15:0] Timer;
(* src = "../../verilog/extadc.v:41" *)
wire TimerEnable;
(* src = "../../verilog/extadc.v:39" *)
wire TimerOvfl;
(* src = "../../verilog/extadc.v:40" *)
wire TimerPreset;
(* src = "../../verilog/extadc.v:166" *)
wire [15:0] Word0;
wire FSM_1_Out6_s;
wire FSM_1_Out7_s;
wire FSM_1_Out8_s;
wire FSM_1_Out9_s;
wire FSM_1_Out10_s;
wire FSM_1_Out11_s;
wire FSM_1_Out12_s;
wire FSM_1_Out13_s;
wire FSM_1_Out14_s;
wire FSM_1_CfgMode_s;
wire FSM_1_CfgClk_s;
wire FSM_1_CfgShift_s;
wire FSM_1_CfgDataIn_s;
wire FSM_1_CfgDataOut_s;
\$reduce_or #(
.A_SIGNED(0),
.A_WIDTH(3),
.Y_WIDTH(1)
) \$auto$opt_reduce.cc:130:opt_mux$710 (
.A({ \$procmux$194_CMP , \$procmux$193_CMP , \$procmux$190_CMP }),
.Y(SensorStart_o)
);
(* src = "../../verilog/extadc.v:161" *)
\$eq #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$eq$../../verilog/extadc.v:161$13 (
.A(Timer),
.B(16'b0000000000000000),
.Y(TimerOvfl)
);
FSM FSM_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(AdcDone_i),
.In1_i(DiffTooLarge),
.In2_i(Enable_i),
.In3_i(SensorReady_i),
.In4_i(TimerOvfl),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.Out0_o(\$procmux$190_CMP ),
.Out1_o(\$procmux$193_CMP ),
.Out2_o(\$procmux$194_CMP ),
.Out3_o(\$procmux$199_CMP ),
.Out4_o(\$procmux$202_CMP ),
.Out5_o(CpuIntr_o),
.Out6_o(FSM_1_Out6_s),
.Out7_o(FSM_1_Out7_s),
.Out8_o(FSM_1_Out8_s),
.Out9_o(FSM_1_Out9_s),
.Out10_o(FSM_1_Out10_s),
.Out11_o(FSM_1_Out11_s),
.Out12_o(FSM_1_Out12_s),
.Out13_o(FSM_1_Out13_s),
.Out14_o(FSM_1_Out14_s),
.CfgMode_i(FSM_1_CfgMode_s),
.CfgClk_i(FSM_1_CfgClk_s),
.CfgShift_i(FSM_1_CfgShift_s),
.CfgDataIn_i(FSM_1_CfgDataIn_s),
.CfgDataOut_o(FSM_1_CfgDataOut_s)
);
(* src = "../../verilog/extadc.v:190" *)
\$gt #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(1)
) \$gt$../../verilog/extadc.v:190$20 (
.A(AbsDiffResult),
.B(Threshold_i),
.Y(DiffTooLarge)
);
(* src = "../../verilog/extadc.v:142" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$procdff$706 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Timer[15:0] ),
.Q(Timer)
);
(* src = "../../verilog/extadc.v:169" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(16)
) \$procdff$707 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$procmux$189 (
.A(1'b0),
.B({ SensorReady_i, 1'b1 }),
.S({ \$procmux$193_CMP , \$procmux$190_CMP }),
.Y(AdcStart_o)
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$procmux$229 (
.A(1'b0),
.B({ \$2\SensorPower_o[0:0] , 1'b1 }),
.S({ \$procmux$199_CMP , SensorStart_o }),
.Y(SensorPower_o)
);
\$mux #(
.WIDTH(16)
) \$procmux$23 (
.A(Timer),
.B(\$sub$../../verilog/extadc.v:156$12_Y ),
.S(TimerEnable),
.Y(\$procmux$23_Y )
);
\$mux #(
.WIDTH(16)
) \$procmux$26 (
.A(\$procmux$23_Y ),
.B(PeriodCounterPreset_i),
.S(TimerPreset),
.Y(\$0\Timer[15:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$269 (
.A(\$procmux$190_CMP ),
.B(\$2\StoreNewValue[0:0] ),
.Y(StoreNewValue)
);
\$mux #(
.WIDTH(16)
) \$procmux$29 (
.A(Word0),
.B(AdcValue_i),
.S(StoreNewValue),
.Y(\$0\Word0[15:0] )
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$procmux$318 (
.A(1'b0),
.B({ Enable_i, \$3\TimerEnable[0:0] }),
.S({ \$procmux$202_CMP , \$procmux$199_CMP }),
.Y(TimerEnable)
);
\$pmux #(
.S_WIDTH(2),
.WIDTH(1)
) \$procmux$338 (
.A(1'b1),
.B({ \$2\TimerPreset[0:0] , \$3\TimerPreset[0:0] }),
.S({ \$procmux$202_CMP , \$procmux$199_CMP }),
.Y(TimerPreset)
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$381 (
.A(Enable_i),
.Y(\$2\TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$420 (
.A(Enable_i),
.B(TimerOvfl),
.Y(\$2\SensorPower_o[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$441 (
.A(Enable_i),
.B(\$4\TimerEnable[0:0] ),
.Y(\$3\TimerEnable[0:0] )
);
\$mux #(
.WIDTH(1)
) \$procmux$462 (
.A(1'b1),
.B(TimerOvfl),
.S(Enable_i),
.Y(\$3\TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(0),
.A_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$502 (
.A(TimerOvfl),
.Y(\$4\TimerEnable[0:0] )
);
\$and #(
.A_SIGNED(0),
.A_WIDTH(1),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(1)
) \$procmux$646 (
.A(AdcDone_i),
.B(DiffTooLarge),
.Y(\$2\StoreNewValue[0:0] )
);
(* src = "../../verilog/extadc.v:156" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(1),
.Y_WIDTH(16)
) \$sub$../../verilog/extadc.v:156$12 (
.A(Timer),
.B(1'b1),
.Y(\$sub$../../verilog/extadc.v:156$12_Y )
);
(* src = "../../verilog/extadc.v:186" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(17),
.B_SIGNED(0),
.B_WIDTH(17),
.Y_WIDTH(17)
) \$sub$../../verilog/extadc.v:186$17 (
.A({ 1'b0, AdcValue_i }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/extadc.v:187" *)
\$sub #(
.A_SIGNED(0),
.A_WIDTH(16),
.B_SIGNED(0),
.B_WIDTH(16),
.Y_WIDTH(16)
) \$sub$../../verilog/extadc.v:187$18 (
.A(Word0),
.B(AdcValue_i),
.Y(DiffBA)
);
(* src = "../../verilog/extadc.v:188" *)
\$mux #(
.WIDTH(16)
) \$ternary$../../verilog/extadc.v:188$19 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
assign SensorValue_o = Word0;
assign FSM_1_CfgMode_s = 1'b0;
assign FSM_1_CfgClk_s = 1'b0;
assign FSM_1_CfgShift_s = 1'b0;
assign FSM_1_CfgDataIn_s = 1'b0;
endmodule
|
//
// Generated by Bluespec Compiler, version 2017.07.A (build 1da80f1, 2017-07-21)
//
// On Fri Jan 18 19:54:32 EST 2019
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// valid O 1
// word_fst O 64
// word_snd O 5
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_opcode I 7 reg
// req_f7 I 7 reg
// req_rm I 3 reg
// req_rs2 I 5 reg
// req_v1 I 64 reg
// req_v2 I 64 reg
// req_v3 I 64 reg
// EN_set_verbosity I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkRISCV_FBox(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_set_verbosity, valid;
// inlined wires
reg [68 : 0] dw_result$wget;
wire dw_valid$wget, dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register requestR
reg [214 : 0] requestR;
wire [214 : 0] requestR$D_IN;
wire requestR$EN;
// register resultR
reg [69 : 0] resultR;
reg [69 : 0] resultR$D_IN;
wire resultR$EN;
// register stateR
reg [1 : 0] stateR;
reg [1 : 0] stateR$D_IN;
wire stateR$EN;
// ports of submodule fpu
reg [201 : 0] fpu$request_put;
wire [69 : 0] fpu$response_get;
wire fpu$EN_request_put,
fpu$EN_response_get,
fpu$RDY_request_put,
fpu$RDY_response_get;
// ports of submodule frmFpuF
wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ;
// rule scheduling signals
wire CAN_FIRE_RL_doFADD_D,
CAN_FIRE_RL_doFADD_S,
CAN_FIRE_RL_doFCLASS_D,
CAN_FIRE_RL_doFCLASS_S,
CAN_FIRE_RL_doFCVT_D_S,
CAN_FIRE_RL_doFCVT_D_W,
CAN_FIRE_RL_doFCVT_D_WU,
CAN_FIRE_RL_doFCVT_S_D,
CAN_FIRE_RL_doFCVT_S_W,
CAN_FIRE_RL_doFCVT_S_WU,
CAN_FIRE_RL_doFCVT_WU_D,
CAN_FIRE_RL_doFCVT_WU_S,
CAN_FIRE_RL_doFCVT_W_D,
CAN_FIRE_RL_doFCVT_W_S,
CAN_FIRE_RL_doFEQ_D,
CAN_FIRE_RL_doFEQ_S,
CAN_FIRE_RL_doFLE_D,
CAN_FIRE_RL_doFLE_S,
CAN_FIRE_RL_doFLT_D,
CAN_FIRE_RL_doFLT_S,
CAN_FIRE_RL_doFMADD_D,
CAN_FIRE_RL_doFMADD_S,
CAN_FIRE_RL_doFMAX_D,
CAN_FIRE_RL_doFMAX_S,
CAN_FIRE_RL_doFMIN_D,
CAN_FIRE_RL_doFMIN_S,
CAN_FIRE_RL_doFMSUB_D,
CAN_FIRE_RL_doFMSUB_S,
CAN_FIRE_RL_doFMUL_D,
CAN_FIRE_RL_doFMUL_S,
CAN_FIRE_RL_doFMV_D_X,
CAN_FIRE_RL_doFMV_W_X,
CAN_FIRE_RL_doFMV_X_D,
CAN_FIRE_RL_doFMV_X_W,
CAN_FIRE_RL_doFNMADD_D,
CAN_FIRE_RL_doFNMADD_S,
CAN_FIRE_RL_doFNMSUB_D,
CAN_FIRE_RL_doFNMSUB_S,
CAN_FIRE_RL_doFSGNJN_D,
CAN_FIRE_RL_doFSGNJN_S,
CAN_FIRE_RL_doFSGNJX_D,
CAN_FIRE_RL_doFSGNJX_S,
CAN_FIRE_RL_doFSGNJ_D,
CAN_FIRE_RL_doFSGNJ_S,
CAN_FIRE_RL_doFSUB_D,
CAN_FIRE_RL_doFSUB_S,
CAN_FIRE_RL_rl_drive_fpu_result,
CAN_FIRE_RL_rl_get_fpu_result,
CAN_FIRE_req,
CAN_FIRE_set_verbosity,
WILL_FIRE_RL_doFADD_D,
WILL_FIRE_RL_doFADD_S,
WILL_FIRE_RL_doFCLASS_D,
WILL_FIRE_RL_doFCLASS_S,
WILL_FIRE_RL_doFCVT_D_S,
WILL_FIRE_RL_doFCVT_D_W,
WILL_FIRE_RL_doFCVT_D_WU,
WILL_FIRE_RL_doFCVT_S_D,
WILL_FIRE_RL_doFCVT_S_W,
WILL_FIRE_RL_doFCVT_S_WU,
WILL_FIRE_RL_doFCVT_WU_D,
WILL_FIRE_RL_doFCVT_WU_S,
WILL_FIRE_RL_doFCVT_W_D,
WILL_FIRE_RL_doFCVT_W_S,
WILL_FIRE_RL_doFEQ_D,
WILL_FIRE_RL_doFEQ_S,
WILL_FIRE_RL_doFLE_D,
WILL_FIRE_RL_doFLE_S,
WILL_FIRE_RL_doFLT_D,
WILL_FIRE_RL_doFLT_S,
WILL_FIRE_RL_doFMADD_D,
WILL_FIRE_RL_doFMADD_S,
WILL_FIRE_RL_doFMAX_D,
WILL_FIRE_RL_doFMAX_S,
WILL_FIRE_RL_doFMIN_D,
WILL_FIRE_RL_doFMIN_S,
WILL_FIRE_RL_doFMSUB_D,
WILL_FIRE_RL_doFMSUB_S,
WILL_FIRE_RL_doFMUL_D,
WILL_FIRE_RL_doFMUL_S,
WILL_FIRE_RL_doFMV_D_X,
WILL_FIRE_RL_doFMV_W_X,
WILL_FIRE_RL_doFMV_X_D,
WILL_FIRE_RL_doFMV_X_W,
WILL_FIRE_RL_doFNMADD_D,
WILL_FIRE_RL_doFNMADD_S,
WILL_FIRE_RL_doFNMSUB_D,
WILL_FIRE_RL_doFNMSUB_S,
WILL_FIRE_RL_doFSGNJN_D,
WILL_FIRE_RL_doFSGNJN_S,
WILL_FIRE_RL_doFSGNJX_D,
WILL_FIRE_RL_doFSGNJX_S,
WILL_FIRE_RL_doFSGNJ_D,
WILL_FIRE_RL_doFSGNJ_S,
WILL_FIRE_RL_doFSUB_D,
WILL_FIRE_RL_doFSUB_S,
WILL_FIRE_RL_rl_drive_fpu_result,
WILL_FIRE_RL_rl_get_fpu_result,
WILL_FIRE_req,
WILL_FIRE_set_verbosity;
// inputs to muxes for submodule ports
wire [201 : 0] MUX_fpu$request_put_1__VAL_1,
MUX_fpu$request_put_1__VAL_10,
MUX_fpu$request_put_1__VAL_11,
MUX_fpu$request_put_1__VAL_12,
MUX_fpu$request_put_1__VAL_13,
MUX_fpu$request_put_1__VAL_14,
MUX_fpu$request_put_1__VAL_2,
MUX_fpu$request_put_1__VAL_3,
MUX_fpu$request_put_1__VAL_4,
MUX_fpu$request_put_1__VAL_5,
MUX_fpu$request_put_1__VAL_6,
MUX_fpu$request_put_1__VAL_7,
MUX_fpu$request_put_1__VAL_8,
MUX_fpu$request_put_1__VAL_9;
wire [69 : 0] MUX_resultR$write_1__VAL_10,
MUX_resultR$write_1__VAL_11,
MUX_resultR$write_1__VAL_12,
MUX_resultR$write_1__VAL_13,
MUX_resultR$write_1__VAL_14,
MUX_resultR$write_1__VAL_15,
MUX_resultR$write_1__VAL_16,
MUX_resultR$write_1__VAL_17,
MUX_resultR$write_1__VAL_18,
MUX_resultR$write_1__VAL_19,
MUX_resultR$write_1__VAL_2,
MUX_resultR$write_1__VAL_20,
MUX_resultR$write_1__VAL_21,
MUX_resultR$write_1__VAL_22,
MUX_resultR$write_1__VAL_23,
MUX_resultR$write_1__VAL_24,
MUX_resultR$write_1__VAL_25,
MUX_resultR$write_1__VAL_26,
MUX_resultR$write_1__VAL_27,
MUX_resultR$write_1__VAL_28,
MUX_resultR$write_1__VAL_29,
MUX_resultR$write_1__VAL_3,
MUX_resultR$write_1__VAL_30,
MUX_resultR$write_1__VAL_31,
MUX_resultR$write_1__VAL_32,
MUX_resultR$write_1__VAL_33,
MUX_resultR$write_1__VAL_34,
MUX_resultR$write_1__VAL_4,
MUX_resultR$write_1__VAL_6,
MUX_resultR$write_1__VAL_7,
MUX_resultR$write_1__VAL_8,
MUX_resultR$write_1__VAL_9;
wire [68 : 0] MUX_dw_result$wset_1__VAL_1,
MUX_dw_result$wset_1__VAL_10,
MUX_dw_result$wset_1__VAL_11,
MUX_dw_result$wset_1__VAL_12,
MUX_dw_result$wset_1__VAL_13,
MUX_dw_result$wset_1__VAL_14,
MUX_dw_result$wset_1__VAL_15,
MUX_dw_result$wset_1__VAL_16,
MUX_dw_result$wset_1__VAL_17,
MUX_dw_result$wset_1__VAL_18,
MUX_dw_result$wset_1__VAL_19,
MUX_dw_result$wset_1__VAL_2,
MUX_dw_result$wset_1__VAL_20,
MUX_dw_result$wset_1__VAL_21,
MUX_dw_result$wset_1__VAL_22,
MUX_dw_result$wset_1__VAL_23,
MUX_dw_result$wset_1__VAL_24,
MUX_dw_result$wset_1__VAL_25,
MUX_dw_result$wset_1__VAL_26,
MUX_dw_result$wset_1__VAL_27,
MUX_dw_result$wset_1__VAL_28,
MUX_dw_result$wset_1__VAL_29,
MUX_dw_result$wset_1__VAL_3,
MUX_dw_result$wset_1__VAL_30,
MUX_dw_result$wset_1__VAL_31,
MUX_dw_result$wset_1__VAL_32,
MUX_dw_result$wset_1__VAL_4,
MUX_dw_result$wset_1__VAL_5,
MUX_dw_result$wset_1__VAL_6,
MUX_dw_result$wset_1__VAL_7,
MUX_dw_result$wset_1__VAL_8,
MUX_dw_result$wset_1__VAL_9;
wire MUX_dw_result$wset_1__SEL_1,
MUX_dw_result$wset_1__SEL_2,
MUX_dw_result$wset_1__SEL_30;
// remaining internal signals
reg [51 : 0] CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114,
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115,
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116,
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117,
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118,
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119,
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56,
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57,
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45,
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46,
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54,
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55,
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41,
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42,
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607;
reg [22 : 0] CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80,
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81,
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16,
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17,
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78,
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79,
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29,
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30,
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27,
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28,
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18,
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19,
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84,
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85,
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82,
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83,
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735;
reg [10 : 0] CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102,
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103,
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104,
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105,
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106,
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107,
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49,
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50,
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44,
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43,
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52,
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53,
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39,
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40,
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528;
reg [7 : 0] CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72,
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73,
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13,
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12,
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70,
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71,
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22,
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23,
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25,
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26,
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14,
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15,
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76,
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77,
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74,
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75,
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379,
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697;
reg [2 : 0] IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40;
reg CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88,
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108,
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8,
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86,
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110,
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112,
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35,
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37,
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10,
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92,
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93;
wire [85 : 0] IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618,
b__h47607,
x__h48283,
x__h49361;
wire [68 : 0] ab__h156914;
wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68;
wire [63 : 0] IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1035,
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1051,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1034,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1036,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1050,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1052,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1122,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1123,
IF_requestR_BITS_126_TO_116_745_EQ_2047_746_AN_ETC___d3793,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3807,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3878,
res___1__h155823,
res___1__h156261,
res___1__h156271,
res___1__h156290,
res___1__h26221,
res___1__h26457,
res___1__h26467,
res___1__h26486,
res__h139089,
res__h143531,
res__h148079,
res__h150783,
res__h153478,
res__h155355,
res__h156306,
res__h156487,
res__h17825,
res__h18062,
res__h23434,
res__h24917,
res__h25986,
res__h26502,
res__h97284,
x__h140114,
x__h144662,
x__h14804,
x__h149106,
x__h151801,
x__h153678,
x__h155805,
x__h156455,
x__h16397,
x__h17147,
x__h1773,
x__h1919,
x__h19781,
x__h2053,
x__h2201,
x__h22306,
x__h22427,
x__h22565,
x__h24048,
x__h25117,
x__h26203,
x__h27370,
x__h27492,
x__h27616,
x__h27746,
x__h37694,
x__h47361,
x__h48937,
x__h49683,
x__h8662,
x__h98388;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_ETC__q60,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BIT_ETC__q65,
IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q100,
IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q94,
IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q62,
IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q68,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827,
_0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152,
_0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318,
_theResult____h120602,
_theResult____h61543,
_theResult____h79267,
_theResult___snd__h119216,
_theResult___snd__h119218,
_theResult___snd__h119225,
_theResult___snd__h119231,
_theResult___snd__h119254,
_theResult___snd__h128849,
_theResult___snd__h128860,
_theResult___snd__h128862,
_theResult___snd__h128872,
_theResult___snd__h128878,
_theResult___snd__h128901,
_theResult___snd__h137615,
_theResult___snd__h137629,
_theResult___snd__h137635,
_theResult___snd__h137653,
_theResult___snd__h69661,
_theResult___snd__h69672,
_theResult___snd__h69674,
_theResult___snd__h69684,
_theResult___snd__h69690,
_theResult___snd__h69713,
_theResult___snd__h78287,
_theResult___snd__h78289,
_theResult___snd__h78296,
_theResult___snd__h78302,
_theResult___snd__h78325,
_theResult___snd__h87514,
_theResult___snd__h87525,
_theResult___snd__h87527,
_theResult___snd__h87537,
_theResult___snd__h87543,
_theResult___snd__h87566,
_theResult___snd__h96164,
_theResult___snd__h96178,
_theResult___snd__h96184,
_theResult___snd__h96202,
b__h15050,
result__h121215,
result__h79880,
sfd__h53913,
sfdin__h128832,
sfdin__h69644,
sfdin__h87497,
x__h121310,
x__h15726,
x__h16821,
x__h79975;
wire [54 : 0] sfd___3__h35762, sfd___3__h45458, sfd__h27761, sfd__h37706;
wire [53 : 0] sfd__h119283,
sfd__h128930,
sfd__h137688,
sfd__h35789,
sfd__h36532,
sfd__h45485,
sfd__h46227,
value__h47609;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1384,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1567,
_theResult___fst_sfd__h104193,
_theResult___fst_sfd__h120019,
_theResult___fst_sfd__h120022,
_theResult___fst_sfd__h129666,
_theResult___fst_sfd__h129669,
_theResult___fst_sfd__h138448,
_theResult___fst_sfd__h138451,
_theResult___fst_sfd__h138460,
_theResult___fst_sfd__h138466,
_theResult___fst_sfd__h36486,
_theResult___fst_sfd__h37242,
_theResult___fst_sfd__h37245,
_theResult___fst_sfd__h46181,
_theResult___fst_sfd__h46936,
_theResult___fst_sfd__h46939,
_theResult___fst_sfd__h50209,
_theResult___sfd__h119921,
_theResult___sfd__h129568,
_theResult___sfd__h138350,
_theResult___sfd__h36389,
_theResult___sfd__h37145,
_theResult___sfd__h46085,
_theResult___sfd__h46840,
_theResult___snd_fst_sfd__h100339,
_theResult___snd_fst_sfd__h120025,
_theResult___snd_fst_sfd__h138454,
_theResult___snd_fst_sfd__h37248,
_theResult___snd_fst_sfd__h46942,
out___1_sfd__h98453,
out_sfd__h119924,
out_sfd__h129571,
out_sfd__h138353,
out_sfd__h36392,
out_sfd__h37148,
out_sfd__h46088,
out_sfd__h46843,
value__h49752;
wire [32 : 0] _theResult_____2__h14985,
_theResult_____2__h47542,
out1___1__h15477,
out1___1__h48034;
wire [31 : 0] IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1031,
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1045,
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1047,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1032,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1048,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d886,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d946,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d882,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d884,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d944,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1673,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1675,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1735,
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1029,
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1044,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d1737,
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d1677,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d948,
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
requestR_BITS_159_TO_128__q1,
sfd___3__h13303,
sfd___3__h7126,
sfd__h2222,
x__h14807,
x__h16400,
x__h1779,
x__h1925,
x__h2059,
x__h2207,
x__h47364,
x__h48940,
x__h97290;
wire [30 : 0] IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19;
wire [24 : 0] sfd__h13330,
sfd__h13869,
sfd__h69742,
sfd__h7153,
sfd__h7696,
sfd__h78354,
sfd__h87595,
sfd__h96237,
value__h15052;
wire [23 : 0] NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720,
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416,
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798,
_theResult___fst_sfd__h13823,
_theResult___fst_sfd__h14375,
_theResult___fst_sfd__h14378,
_theResult___fst_sfd__h61526,
_theResult___fst_sfd__h70275,
_theResult___fst_sfd__h70278,
_theResult___fst_sfd__h7650,
_theResult___fst_sfd__h78887,
_theResult___fst_sfd__h78890,
_theResult___fst_sfd__h8203,
_theResult___fst_sfd__h8206,
_theResult___fst_sfd__h88128,
_theResult___fst_sfd__h88131,
_theResult___fst_sfd__h96794,
_theResult___fst_sfd__h96797,
_theResult___fst_sfd__h96806,
_theResult___fst_sfd__h96812,
_theResult___fst_sfd__h98711,
_theResult___sfd__h13727,
_theResult___sfd__h14279,
_theResult___sfd__h70177,
_theResult___sfd__h7553,
_theResult___sfd__h78789,
_theResult___sfd__h8106,
_theResult___sfd__h88030,
_theResult___sfd__h96696,
_theResult___snd_fst_sfd__h14381,
_theResult___snd_fst_sfd__h53867,
_theResult___snd_fst_sfd__h78893,
_theResult___snd_fst_sfd__h8209,
_theResult___snd_fst_sfd__h96800,
out_sfd__h13730,
out_sfd__h14282,
out_sfd__h70180,
out_sfd__h7556,
out_sfd__h78792,
out_sfd__h8109,
out_sfd__h88033,
out_sfd__h96699,
sV1_sfd__h816,
sV2_sfd__h919,
value__h98456;
wire [19 : 0] NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917;
wire [11 : 0] IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840,
_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445,
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002,
_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314,
x__h121343,
x__h36517,
x__h46212,
x__h80008;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522,
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99,
_theResult___exp__h119920,
_theResult___exp__h129567,
_theResult___exp__h138349,
_theResult___exp__h36388,
_theResult___exp__h37144,
_theResult___exp__h46084,
_theResult___exp__h46839,
_theResult___fst_exp__h104192,
_theResult___fst_exp__h119256,
_theResult___fst_exp__h119262,
_theResult___fst_exp__h119265,
_theResult___fst_exp__h120018,
_theResult___fst_exp__h120021,
_theResult___fst_exp__h128838,
_theResult___fst_exp__h128903,
_theResult___fst_exp__h128909,
_theResult___fst_exp__h128912,
_theResult___fst_exp__h129665,
_theResult___fst_exp__h129668,
_theResult___fst_exp__h137621,
_theResult___fst_exp__h137660,
_theResult___fst_exp__h137666,
_theResult___fst_exp__h137669,
_theResult___fst_exp__h138447,
_theResult___fst_exp__h138450,
_theResult___fst_exp__h138459,
_theResult___fst_exp__h138462,
_theResult___fst_exp__h36485,
_theResult___fst_exp__h37241,
_theResult___fst_exp__h37244,
_theResult___fst_exp__h46180,
_theResult___fst_exp__h46935,
_theResult___fst_exp__h46938,
_theResult___snd_fst_exp__h120024,
_theResult___snd_fst_exp__h138453,
_theResult___snd_fst_exp__h37247,
_theResult___snd_fst_exp__h37250,
_theResult___snd_fst_exp__h37253,
_theResult___snd_fst_exp__h46941,
_theResult___snd_fst_exp__h46944,
_theResult___snd_fst_exp__h46947,
din_inc___2_exp__h138485,
din_inc___2_exp__h138515,
din_inc___2_exp__h138539,
din_inc___2_exp__h37287,
din_inc___2_exp__h46977,
out_exp__h119923,
out_exp__h129570,
out_exp__h138352,
out_exp__h36391,
out_exp__h37147,
out_exp__h46087,
out_exp__h46842,
requestR_BITS_190_TO_180_596_MINUS_1023___d1609,
x__h98397;
wire [8 : 0] IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616,
x__h13854,
x__h7681;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133,
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617,
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686,
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373,
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d385,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d703,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67,
_theResult___exp__h13726,
_theResult___exp__h14278,
_theResult___exp__h70176,
_theResult___exp__h7552,
_theResult___exp__h78788,
_theResult___exp__h8105,
_theResult___exp__h88029,
_theResult___exp__h96695,
_theResult___fst_exp__h13822,
_theResult___fst_exp__h14374,
_theResult___fst_exp__h14377,
_theResult___fst_exp__h61525,
_theResult___fst_exp__h69650,
_theResult___fst_exp__h69715,
_theResult___fst_exp__h69721,
_theResult___fst_exp__h69724,
_theResult___fst_exp__h70274,
_theResult___fst_exp__h70277,
_theResult___fst_exp__h7649,
_theResult___fst_exp__h78327,
_theResult___fst_exp__h78333,
_theResult___fst_exp__h78336,
_theResult___fst_exp__h78886,
_theResult___fst_exp__h78889,
_theResult___fst_exp__h8202,
_theResult___fst_exp__h8205,
_theResult___fst_exp__h87503,
_theResult___fst_exp__h87568,
_theResult___fst_exp__h87574,
_theResult___fst_exp__h87577,
_theResult___fst_exp__h88127,
_theResult___fst_exp__h88130,
_theResult___fst_exp__h96170,
_theResult___fst_exp__h96209,
_theResult___fst_exp__h96215,
_theResult___fst_exp__h96218,
_theResult___fst_exp__h96793,
_theResult___fst_exp__h96796,
_theResult___fst_exp__h96805,
_theResult___fst_exp__h96808,
_theResult___snd_fst_exp__h14380,
_theResult___snd_fst_exp__h14383,
_theResult___snd_fst_exp__h14386,
_theResult___snd_fst_exp__h78892,
_theResult___snd_fst_exp__h8208,
_theResult___snd_fst_exp__h8211,
_theResult___snd_fst_exp__h8214,
_theResult___snd_fst_exp__h96799,
din_inc___2_exp__h14416,
din_inc___2_exp__h8248,
din_inc___2_exp__h96827,
din_inc___2_exp__h96851,
din_inc___2_exp__h96881,
din_inc___2_exp__h96905,
out_exp__h13729,
out_exp__h14281,
out_exp__h70179,
out_exp__h7555,
out_exp__h78791,
out_exp__h8108,
out_exp__h88032,
out_exp__h96698,
sV1_exp__h815,
sV2_exp__h918,
x__h49692;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074,
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394,
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613;
wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887,
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664,
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870,
x__h139191,
x__h143663,
x__h14520,
x__h153497,
x__h16140,
x__h16899,
x__h19186,
x__h24936,
x__h37409,
x__h47077,
x__h48680,
x__h49439,
x__h8374,
x__h97405;
wire [1 : 0] IF_sfd___3126_BIT_7_THEN_2_ELSE_0__q7,
IF_sfd___3126_BIT_8_THEN_2_ELSE_0__q6,
IF_sfd___33303_BIT_7_THEN_2_ELSE_0__q21,
IF_sfd___33303_BIT_8_THEN_2_ELSE_0__q20,
IF_sfd___35458_BIT_1_THEN_2_ELSE_0__q48,
IF_sfd___35458_BIT_2_THEN_2_ELSE_0__q47,
IF_sfd___35762_BIT_1_THEN_2_ELSE_0__q34,
IF_sfd___35762_BIT_2_THEN_2_ELSE_0__q33,
IF_sfdin28832_BIT_4_THEN_2_ELSE_0__q98,
IF_sfdin7497_BIT_33_THEN_2_ELSE_0__q66,
IF_sfdin9644_BIT_33_THEN_2_ELSE_0__q61,
IF_theResult___snd19216_BIT_4_THEN_2_ELSE_0__q95,
IF_theResult___snd37615_BIT_4_THEN_2_ELSE_0__q101,
IF_theResult___snd6164_BIT_33_THEN_2_ELSE_0__q69,
IF_theResult___snd8287_BIT_33_THEN_2_ELSE_0__q63,
IF_x5726_BIT_24_THEN_2_ELSE_0__q31,
IF_x6821_BIT_24_THEN_2_ELSE_0__q32,
IF_x8283_BIT_53_THEN_2_ELSE_0__q58,
IF_x9361_BIT_53_THEN_2_ELSE_0__q59,
guard__h111304,
guard__h120612,
guard__h129679,
guard__h13313,
guard__h13839,
guard__h14983,
guard__h15537,
guard__h16600,
guard__h35772,
guard__h36502,
guard__h45468,
guard__h46197,
guard__h47540,
guard__h48094,
guard__h49140,
guard__h61553,
guard__h70288,
guard__h7136,
guard__h7666,
guard__h79277,
guard__h88141;
wire IF_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_ETC___d2820,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1286,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1401,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d325,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d475,
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d1584,
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d789,
IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191__ETC___d3638,
IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3646,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3650,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3685,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3688,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3695,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3709,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3721,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3733,
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d908,
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1699,
IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_15_ETC___d1287,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_ETC___d3630,
IF_NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1024,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3648,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3707,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3719,
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3731,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2838,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2916,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2929,
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2942,
IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2840,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2891,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2902,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2918,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2931,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2944,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1086,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d967,
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1635,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d844,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938,
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d466,
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d469,
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d478,
IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855,
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646,
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710,
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2910,
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2938,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1027,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1085,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1091,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1109,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d897,
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961,
NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263,
NOT_requestR_BITS_159_TO_128_24_EQ_0_25_26_AND_ETC___d781,
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1688,
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752,
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790,
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3855,
NOT_requestR_BITS_190_TO_180_596_ULT_requestR__ETC___d3832,
NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_ETC___d1089,
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579,
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146,
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312,
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560,
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076,
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469,
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238,
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2873,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2898,
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2925,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261,
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618,
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619,
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003,
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004,
guard__h121210,
guard__h79875,
requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766,
requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778,
requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783,
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762,
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1758,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799,
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821,
requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777,
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775,
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3831,
requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782,
requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026,
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770,
requestR_BIT_159_6_OR_requestR_BIT_158_88_OR_r_ETC___d792;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas && dw_valid$wget ;
// value method word_fst
assign word_fst = ab__h156914[68:5] ;
// value method word_snd
assign word_snd = ab__h156914[4:0] ;
// submodule fpu
mkFPU fpu(.CLK(CLK),
.RST_N(RST_N),
.request_put(fpu$request_put),
.EN_request_put(fpu$EN_request_put),
.EN_response_get(fpu$EN_response_get),
.RDY_request_put(fpu$RDY_request_put),
.response_get(fpu$response_get),
.RDY_response_get(fpu$RDY_response_get));
// submodule frmFpuF
FIFO2 #(.width(32'd1), .guarded(32'd1)) frmFpuF(.RST(RST_N),
.CLK(CLK),
.D_IN(frmFpuF$D_IN),
.ENQ(frmFpuF$ENQ),
.DEQ(frmFpuF$DEQ),
.CLR(frmFpuF$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// rule RL_doFADD_S
assign CAN_FIRE_RL_doFADD_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0 ;
assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ;
// rule RL_doFSUB_S
assign CAN_FIRE_RL_doFSUB_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h04 ;
assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ;
// rule RL_doFMUL_S
assign CAN_FIRE_RL_doFMUL_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h08 ;
assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ;
// rule RL_doFMADD_S
assign CAN_FIRE_RL_doFMADD_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000011 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ;
// rule RL_doFMSUB_S
assign CAN_FIRE_RL_doFMSUB_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000111 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ;
// rule RL_doFNMADD_S
assign CAN_FIRE_RL_doFNMADD_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001111 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ;
// rule RL_doFNMSUB_S
assign CAN_FIRE_RL_doFNMSUB_S =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001011 &&
requestR[201:200] == 2'd0 ;
assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ;
// rule RL_doFSGNJ_S
assign CAN_FIRE_RL_doFSGNJ_S = MUX_dw_result$wset_1__SEL_2 ;
assign WILL_FIRE_RL_doFSGNJ_S = MUX_dw_result$wset_1__SEL_2 ;
// rule RL_doFSGNJN_S
assign CAN_FIRE_RL_doFSGNJN_S = MUX_dw_result$wset_1__SEL_1 ;
assign WILL_FIRE_RL_doFSGNJN_S = MUX_dw_result$wset_1__SEL_1 ;
// rule RL_doFSGNJX_S
assign CAN_FIRE_RL_doFSGNJX_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ;
// rule RL_doFCVT_S_W
assign CAN_FIRE_RL_doFCVT_S_W =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ;
// rule RL_doFCVT_S_WU
assign CAN_FIRE_RL_doFCVT_S_WU =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ;
// rule RL_doFCVT_W_S
assign CAN_FIRE_RL_doFCVT_W_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ;
// rule RL_doFCVT_WU_S
assign CAN_FIRE_RL_doFCVT_WU_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ;
// rule RL_doFMIN_S
assign CAN_FIRE_RL_doFMIN_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ;
// rule RL_doFMAX_S
assign CAN_FIRE_RL_doFMAX_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ;
// rule RL_doFMV_W_X
assign CAN_FIRE_RL_doFMV_W_X =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h78 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ;
// rule RL_doFMV_X_W
assign CAN_FIRE_RL_doFMV_X_W =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ;
// rule RL_doFEQ_S
assign CAN_FIRE_RL_doFEQ_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ;
// rule RL_doFLT_S
assign CAN_FIRE_RL_doFLT_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ;
// rule RL_doFLE_S
assign CAN_FIRE_RL_doFLE_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ;
// rule RL_doFCLASS_S
assign CAN_FIRE_RL_doFCLASS_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ;
// rule RL_doFADD_D
assign CAN_FIRE_RL_doFADD_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h01 ;
assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ;
// rule RL_doFSUB_D
assign CAN_FIRE_RL_doFSUB_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h05 ;
assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ;
// rule RL_doFMUL_D
assign CAN_FIRE_RL_doFMUL_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h09 ;
assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ;
// rule RL_doFMADD_D
assign CAN_FIRE_RL_doFMADD_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000011 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ;
// rule RL_doFMSUB_D
assign CAN_FIRE_RL_doFMSUB_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1000111 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ;
// rule RL_doFNMADD_D
assign CAN_FIRE_RL_doFNMADD_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001111 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ;
// rule RL_doFNMSUB_D
assign CAN_FIRE_RL_doFNMSUB_D =
fpu$RDY_request_put && requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1001011 &&
requestR[201:200] == 2'd1 ;
assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ;
// rule RL_doFSGNJ_D
assign CAN_FIRE_RL_doFSGNJ_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ;
// rule RL_doFSGNJN_D
assign CAN_FIRE_RL_doFSGNJN_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ;
// rule RL_doFSGNJX_D
assign CAN_FIRE_RL_doFSGNJX_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ;
// rule RL_doFCVT_D_W
assign CAN_FIRE_RL_doFCVT_D_W =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ;
// rule RL_doFCVT_D_WU
assign CAN_FIRE_RL_doFCVT_D_WU =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ;
// rule RL_doFCVT_W_D
assign CAN_FIRE_RL_doFCVT_W_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ;
// rule RL_doFCVT_WU_D
assign CAN_FIRE_RL_doFCVT_WU_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ;
// rule RL_doFCVT_S_D
assign CAN_FIRE_RL_doFCVT_S_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h20 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ;
// rule RL_doFCVT_D_S
assign CAN_FIRE_RL_doFCVT_D_S =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h21 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ;
// rule RL_doFMIN_D
assign CAN_FIRE_RL_doFMIN_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ;
// rule RL_doFMAX_D
assign CAN_FIRE_RL_doFMAX_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ;
// rule RL_doFEQ_D
assign CAN_FIRE_RL_doFEQ_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ;
// rule RL_doFLT_D
assign CAN_FIRE_RL_doFLT_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ;
// rule RL_doFLE_D
assign CAN_FIRE_RL_doFLE_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ;
// rule RL_doFMV_D_X
assign CAN_FIRE_RL_doFMV_D_X =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h79 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ;
// rule RL_doFMV_X_D
assign CAN_FIRE_RL_doFMV_X_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ;
// rule RL_doFCLASS_D
assign CAN_FIRE_RL_doFCLASS_D =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ;
// rule RL_rl_get_fpu_result
assign CAN_FIRE_RL_rl_get_fpu_result =
fpu$RDY_response_get && stateR == 2'd1 ;
assign WILL_FIRE_RL_rl_get_fpu_result = CAN_FIRE_RL_rl_get_fpu_result ;
// rule RL_rl_drive_fpu_result
assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd2 ;
assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd2 ;
// inputs to muxes for submodule ports
assign MUX_dw_result$wset_1__SEL_1 =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h1 ;
assign MUX_dw_result$wset_1__SEL_2 =
requestR[214] && stateR == 2'd0 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h0 ;
assign MUX_dw_result$wset_1__SEL_30 =
WILL_FIRE_RL_doFMV_X_D || WILL_FIRE_RL_doFMV_D_X ;
assign MUX_dw_result$wset_1__VAL_1 = { x__h1919, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_2 = { x__h1773, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_3 = { x__h2053, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_4 = { x__h2201, x__h8374 } ;
assign MUX_dw_result$wset_1__VAL_5 = { x__h8662, x__h14520 } ;
assign MUX_dw_result$wset_1__VAL_6 = { x__h14804, x__h16140 } ;
assign MUX_dw_result$wset_1__VAL_7 = { x__h16397, x__h16899 } ;
assign MUX_dw_result$wset_1__VAL_8 = { x__h17147, x__h19186 } ;
assign MUX_dw_result$wset_1__VAL_9 = { x__h19781, x__h19186 } ;
assign MUX_dw_result$wset_1__VAL_10 = { x__h22306, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_11 = { x__h22427, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_12 = { x__h22565, x__h19186 } ;
assign MUX_dw_result$wset_1__VAL_13 = { x__h24048, x__h24936 } ;
assign MUX_dw_result$wset_1__VAL_14 = { x__h25117, x__h24936 } ;
assign MUX_dw_result$wset_1__VAL_15 = { x__h26203, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_16 = { x__h27370, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_17 = { x__h27492, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_18 = { x__h27616, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_19 = { x__h27746, x__h37409 } ;
assign MUX_dw_result$wset_1__VAL_20 = { x__h37694, x__h47077 } ;
assign MUX_dw_result$wset_1__VAL_21 = { x__h47361, x__h48680 } ;
assign MUX_dw_result$wset_1__VAL_22 = { x__h48937, x__h49439 } ;
assign MUX_dw_result$wset_1__VAL_23 = { x__h49683, x__h97405 } ;
assign MUX_dw_result$wset_1__VAL_24 = { x__h98388, x__h139191 } ;
assign MUX_dw_result$wset_1__VAL_25 = { x__h140114, x__h143663 } ;
assign MUX_dw_result$wset_1__VAL_26 = { x__h144662, x__h143663 } ;
assign MUX_dw_result$wset_1__VAL_27 = { x__h149106, x__h143663 } ;
assign MUX_dw_result$wset_1__VAL_28 = { x__h151801, x__h153497 } ;
assign MUX_dw_result$wset_1__VAL_29 = { x__h153678, x__h153497 } ;
assign MUX_dw_result$wset_1__VAL_30 = { requestR[191:128], 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_31 = { x__h155805, 5'd0 } ;
assign MUX_dw_result$wset_1__VAL_32 =
{ x__h156455, fpu$response_get[4:0] } ;
assign MUX_fpu$request_put_1__VAL_1 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd0 } ;
assign MUX_fpu$request_put_1__VAL_2 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd1 } ;
assign MUX_fpu$request_put_1__VAL_3 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd2 } ;
assign MUX_fpu$request_put_1__VAL_4 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd5 } ;
assign MUX_fpu$request_put_1__VAL_5 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd6 } ;
assign MUX_fpu$request_put_1__VAL_6 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd7 } ;
assign MUX_fpu$request_put_1__VAL_7 =
{ 33'h1AAAAAAAA,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19,
33'h1AAAAAAAA,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28,
_1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd8 } ;
assign MUX_fpu$request_put_1__VAL_8 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd0 } ;
assign MUX_fpu$request_put_1__VAL_9 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd1 } ;
assign MUX_fpu$request_put_1__VAL_10 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd2 } ;
assign MUX_fpu$request_put_1__VAL_11 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd5 } ;
assign MUX_fpu$request_put_1__VAL_12 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd6 } ;
assign MUX_fpu$request_put_1__VAL_13 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd7 } ;
assign MUX_fpu$request_put_1__VAL_14 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40,
4'd8 } ;
assign MUX_resultR$write_1__VAL_2 =
{ 1'd1, x__h156455, fpu$response_get[4:0] } ;
assign MUX_resultR$write_1__VAL_3 = { 1'd1, x__h155805, 5'd0 } ;
assign MUX_resultR$write_1__VAL_4 = { 1'd1, requestR[191:128], 5'd0 } ;
assign MUX_resultR$write_1__VAL_6 = { 1'd1, x__h153678, x__h153497 } ;
assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h151801, x__h153497 } ;
assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h149106, x__h143663 } ;
assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h144662, x__h143663 } ;
assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h140114, x__h143663 } ;
assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h98388, x__h139191 } ;
assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h49683, x__h97405 } ;
assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h48937, x__h49439 } ;
assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h47361, x__h48680 } ;
assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h37694, x__h47077 } ;
assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h27746, x__h37409 } ;
assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h27616, 5'd0 } ;
assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h27492, 5'd0 } ;
assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h27370, 5'd0 } ;
assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h26203, 5'd0 } ;
assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h25117, x__h24936 } ;
assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h24048, x__h24936 } ;
assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h22565, x__h19186 } ;
assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h22427, 5'd0 } ;
assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h22306, 5'd0 } ;
assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h19781, x__h19186 } ;
assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h17147, x__h19186 } ;
assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h16397, x__h16899 } ;
assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h14804, x__h16140 } ;
assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h8662, x__h14520 } ;
assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h2201, x__h8374 } ;
assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h2053, 5'd0 } ;
assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h1919, 5'd0 } ;
assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h1773, 5'd0 } ;
// inlined wires
assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ;
assign dw_valid$whas =
WILL_FIRE_RL_rl_drive_fpu_result ||
WILL_FIRE_RL_rl_get_fpu_result ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S ;
always@(WILL_FIRE_RL_doFSGNJN_S or
MUX_dw_result$wset_1__VAL_1 or
WILL_FIRE_RL_doFSGNJ_S or
MUX_dw_result$wset_1__VAL_2 or
WILL_FIRE_RL_doFSGNJX_S or
MUX_dw_result$wset_1__VAL_3 or
WILL_FIRE_RL_doFCVT_S_W or
MUX_dw_result$wset_1__VAL_4 or
WILL_FIRE_RL_doFCVT_S_WU or
MUX_dw_result$wset_1__VAL_5 or
WILL_FIRE_RL_doFCVT_W_S or
MUX_dw_result$wset_1__VAL_6 or
WILL_FIRE_RL_doFCVT_WU_S or
MUX_dw_result$wset_1__VAL_7 or
WILL_FIRE_RL_doFMIN_S or
MUX_dw_result$wset_1__VAL_8 or
WILL_FIRE_RL_doFMAX_S or
MUX_dw_result$wset_1__VAL_9 or
WILL_FIRE_RL_doFMV_W_X or
MUX_dw_result$wset_1__VAL_10 or
WILL_FIRE_RL_doFMV_X_W or
MUX_dw_result$wset_1__VAL_11 or
WILL_FIRE_RL_doFEQ_S or
MUX_dw_result$wset_1__VAL_12 or
WILL_FIRE_RL_doFLT_S or
MUX_dw_result$wset_1__VAL_13 or
WILL_FIRE_RL_doFLE_S or
MUX_dw_result$wset_1__VAL_14 or
WILL_FIRE_RL_doFCLASS_S or
MUX_dw_result$wset_1__VAL_15 or
WILL_FIRE_RL_doFSGNJ_D or
MUX_dw_result$wset_1__VAL_16 or
WILL_FIRE_RL_doFSGNJN_D or
MUX_dw_result$wset_1__VAL_17 or
WILL_FIRE_RL_doFSGNJX_D or
MUX_dw_result$wset_1__VAL_18 or
WILL_FIRE_RL_doFCVT_D_W or
MUX_dw_result$wset_1__VAL_19 or
WILL_FIRE_RL_doFCVT_D_WU or
MUX_dw_result$wset_1__VAL_20 or
WILL_FIRE_RL_doFCVT_W_D or
MUX_dw_result$wset_1__VAL_21 or
WILL_FIRE_RL_doFCVT_WU_D or
MUX_dw_result$wset_1__VAL_22 or
WILL_FIRE_RL_doFCVT_S_D or
MUX_dw_result$wset_1__VAL_23 or
WILL_FIRE_RL_doFCVT_D_S or
MUX_dw_result$wset_1__VAL_24 or
WILL_FIRE_RL_doFMIN_D or
MUX_dw_result$wset_1__VAL_25 or
WILL_FIRE_RL_doFMAX_D or
MUX_dw_result$wset_1__VAL_26 or
WILL_FIRE_RL_doFEQ_D or
MUX_dw_result$wset_1__VAL_27 or
WILL_FIRE_RL_doFLT_D or
MUX_dw_result$wset_1__VAL_28 or
WILL_FIRE_RL_doFLE_D or
MUX_dw_result$wset_1__VAL_29 or
MUX_dw_result$wset_1__SEL_30 or
MUX_dw_result$wset_1__VAL_30 or
WILL_FIRE_RL_doFCLASS_D or
MUX_dw_result$wset_1__VAL_31 or
WILL_FIRE_RL_rl_get_fpu_result or
MUX_dw_result$wset_1__VAL_32 or
WILL_FIRE_RL_rl_drive_fpu_result or resultR)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_doFSGNJN_S: dw_result$wget = MUX_dw_result$wset_1__VAL_1;
WILL_FIRE_RL_doFSGNJ_S: dw_result$wget = MUX_dw_result$wset_1__VAL_2;
WILL_FIRE_RL_doFSGNJX_S: dw_result$wget = MUX_dw_result$wset_1__VAL_3;
WILL_FIRE_RL_doFCVT_S_W: dw_result$wget = MUX_dw_result$wset_1__VAL_4;
WILL_FIRE_RL_doFCVT_S_WU: dw_result$wget = MUX_dw_result$wset_1__VAL_5;
WILL_FIRE_RL_doFCVT_W_S: dw_result$wget = MUX_dw_result$wset_1__VAL_6;
WILL_FIRE_RL_doFCVT_WU_S: dw_result$wget = MUX_dw_result$wset_1__VAL_7;
WILL_FIRE_RL_doFMIN_S: dw_result$wget = MUX_dw_result$wset_1__VAL_8;
WILL_FIRE_RL_doFMAX_S: dw_result$wget = MUX_dw_result$wset_1__VAL_9;
WILL_FIRE_RL_doFMV_W_X: dw_result$wget = MUX_dw_result$wset_1__VAL_10;
WILL_FIRE_RL_doFMV_X_W: dw_result$wget = MUX_dw_result$wset_1__VAL_11;
WILL_FIRE_RL_doFEQ_S: dw_result$wget = MUX_dw_result$wset_1__VAL_12;
WILL_FIRE_RL_doFLT_S: dw_result$wget = MUX_dw_result$wset_1__VAL_13;
WILL_FIRE_RL_doFLE_S: dw_result$wget = MUX_dw_result$wset_1__VAL_14;
WILL_FIRE_RL_doFCLASS_S: dw_result$wget = MUX_dw_result$wset_1__VAL_15;
WILL_FIRE_RL_doFSGNJ_D: dw_result$wget = MUX_dw_result$wset_1__VAL_16;
WILL_FIRE_RL_doFSGNJN_D: dw_result$wget = MUX_dw_result$wset_1__VAL_17;
WILL_FIRE_RL_doFSGNJX_D: dw_result$wget = MUX_dw_result$wset_1__VAL_18;
WILL_FIRE_RL_doFCVT_D_W: dw_result$wget = MUX_dw_result$wset_1__VAL_19;
WILL_FIRE_RL_doFCVT_D_WU: dw_result$wget = MUX_dw_result$wset_1__VAL_20;
WILL_FIRE_RL_doFCVT_W_D: dw_result$wget = MUX_dw_result$wset_1__VAL_21;
WILL_FIRE_RL_doFCVT_WU_D: dw_result$wget = MUX_dw_result$wset_1__VAL_22;
WILL_FIRE_RL_doFCVT_S_D: dw_result$wget = MUX_dw_result$wset_1__VAL_23;
WILL_FIRE_RL_doFCVT_D_S: dw_result$wget = MUX_dw_result$wset_1__VAL_24;
WILL_FIRE_RL_doFMIN_D: dw_result$wget = MUX_dw_result$wset_1__VAL_25;
WILL_FIRE_RL_doFMAX_D: dw_result$wget = MUX_dw_result$wset_1__VAL_26;
WILL_FIRE_RL_doFEQ_D: dw_result$wget = MUX_dw_result$wset_1__VAL_27;
WILL_FIRE_RL_doFLT_D: dw_result$wget = MUX_dw_result$wset_1__VAL_28;
WILL_FIRE_RL_doFLE_D: dw_result$wget = MUX_dw_result$wset_1__VAL_29;
MUX_dw_result$wset_1__SEL_30:
dw_result$wget = MUX_dw_result$wset_1__VAL_30;
WILL_FIRE_RL_doFCLASS_D: dw_result$wget = MUX_dw_result$wset_1__VAL_31;
WILL_FIRE_RL_rl_get_fpu_result:
dw_result$wget = MUX_dw_result$wset_1__VAL_32;
WILL_FIRE_RL_rl_drive_fpu_result: dw_result$wget = resultR[68:0];
default: dw_result$wget =
69'h0AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register requestR
assign requestR$D_IN =
{ 1'd1,
req_opcode,
req_f7,
req_rs2,
req_rm,
req_v1,
req_v2,
req_v3 } ;
assign requestR$EN = EN_req ;
// register resultR
always@(EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
MUX_resultR$write_1__VAL_2 or
WILL_FIRE_RL_doFCLASS_D or
MUX_resultR$write_1__VAL_3 or
WILL_FIRE_RL_doFMV_X_D or
MUX_resultR$write_1__VAL_4 or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
MUX_resultR$write_1__VAL_6 or
WILL_FIRE_RL_doFLT_D or
MUX_resultR$write_1__VAL_7 or
WILL_FIRE_RL_doFEQ_D or
MUX_resultR$write_1__VAL_8 or
WILL_FIRE_RL_doFMAX_D or
MUX_resultR$write_1__VAL_9 or
WILL_FIRE_RL_doFMIN_D or
MUX_resultR$write_1__VAL_10 or
WILL_FIRE_RL_doFCVT_D_S or
MUX_resultR$write_1__VAL_11 or
WILL_FIRE_RL_doFCVT_S_D or
MUX_resultR$write_1__VAL_12 or
WILL_FIRE_RL_doFCVT_WU_D or
MUX_resultR$write_1__VAL_13 or
WILL_FIRE_RL_doFCVT_W_D or
MUX_resultR$write_1__VAL_14 or
WILL_FIRE_RL_doFCVT_D_WU or
MUX_resultR$write_1__VAL_15 or
WILL_FIRE_RL_doFCVT_D_W or
MUX_resultR$write_1__VAL_16 or
WILL_FIRE_RL_doFSGNJX_D or
MUX_resultR$write_1__VAL_17 or
WILL_FIRE_RL_doFSGNJN_D or
MUX_resultR$write_1__VAL_18 or
WILL_FIRE_RL_doFSGNJ_D or
MUX_resultR$write_1__VAL_19 or
WILL_FIRE_RL_doFCLASS_S or
MUX_resultR$write_1__VAL_20 or
WILL_FIRE_RL_doFLE_S or
MUX_resultR$write_1__VAL_21 or
WILL_FIRE_RL_doFLT_S or
MUX_resultR$write_1__VAL_22 or
WILL_FIRE_RL_doFEQ_S or
MUX_resultR$write_1__VAL_23 or
WILL_FIRE_RL_doFMV_X_W or
MUX_resultR$write_1__VAL_24 or
WILL_FIRE_RL_doFMV_W_X or
MUX_resultR$write_1__VAL_25 or
WILL_FIRE_RL_doFMAX_S or
MUX_resultR$write_1__VAL_26 or
WILL_FIRE_RL_doFMIN_S or
MUX_resultR$write_1__VAL_27 or
WILL_FIRE_RL_doFCVT_WU_S or
MUX_resultR$write_1__VAL_28 or
WILL_FIRE_RL_doFCVT_W_S or
MUX_resultR$write_1__VAL_29 or
WILL_FIRE_RL_doFCVT_S_WU or
MUX_resultR$write_1__VAL_30 or
WILL_FIRE_RL_doFCVT_S_W or
MUX_resultR$write_1__VAL_31 or
WILL_FIRE_RL_doFSGNJX_S or
MUX_resultR$write_1__VAL_32 or
WILL_FIRE_RL_doFSGNJN_S or
MUX_resultR$write_1__VAL_33 or
WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_34)
case (1'b1)
EN_req: resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_2;
WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_3;
WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_4;
WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_4;
WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_6;
WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_7;
WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_8;
WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_9;
WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_10;
WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_11;
WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_12;
WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_13;
WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_14;
WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_15;
WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_16;
WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_17;
WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_18;
WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_19;
WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_20;
WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_21;
WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_22;
WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_23;
WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_24;
WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_25;
WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_26;
WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_27;
WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_28;
WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_29;
WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_30;
WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_31;
WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_32;
WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_33;
WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_34;
default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign resultR$EN =
EN_req || WILL_FIRE_RL_doFMV_X_D || WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFSGNJ_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_rl_get_fpu_result ;
// register stateR
always@(EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
WILL_FIRE_RL_doFCLASS_D or
WILL_FIRE_RL_doFMV_X_D or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
WILL_FIRE_RL_doFLT_D or
WILL_FIRE_RL_doFEQ_D or
WILL_FIRE_RL_doFMAX_D or
WILL_FIRE_RL_doFMIN_D or
WILL_FIRE_RL_doFCVT_D_S or
WILL_FIRE_RL_doFCVT_S_D or
WILL_FIRE_RL_doFCVT_WU_D or
WILL_FIRE_RL_doFCVT_W_D or
WILL_FIRE_RL_doFCVT_D_WU or
WILL_FIRE_RL_doFCVT_D_W or
WILL_FIRE_RL_doFSGNJX_D or
WILL_FIRE_RL_doFSGNJN_D or
WILL_FIRE_RL_doFSGNJ_D or
WILL_FIRE_RL_doFNMSUB_D or
WILL_FIRE_RL_doFNMADD_D or
WILL_FIRE_RL_doFMSUB_D or
WILL_FIRE_RL_doFMADD_D or
WILL_FIRE_RL_doFMUL_D or
WILL_FIRE_RL_doFSUB_D or
WILL_FIRE_RL_doFADD_D or
WILL_FIRE_RL_doFCLASS_S or
WILL_FIRE_RL_doFLE_S or
WILL_FIRE_RL_doFLT_S or
WILL_FIRE_RL_doFEQ_S or
WILL_FIRE_RL_doFMV_X_W or
WILL_FIRE_RL_doFMV_W_X or
WILL_FIRE_RL_doFMAX_S or
WILL_FIRE_RL_doFMIN_S or
WILL_FIRE_RL_doFCVT_WU_S or
WILL_FIRE_RL_doFCVT_W_S or
WILL_FIRE_RL_doFCVT_S_WU or
WILL_FIRE_RL_doFCVT_S_W or
WILL_FIRE_RL_doFSGNJX_S or
WILL_FIRE_RL_doFSGNJN_S or
WILL_FIRE_RL_doFSGNJ_S or
WILL_FIRE_RL_doFNMSUB_S or
WILL_FIRE_RL_doFNMADD_S or
WILL_FIRE_RL_doFMSUB_S or
WILL_FIRE_RL_doFMADD_S or
WILL_FIRE_RL_doFMUL_S or
WILL_FIRE_RL_doFSUB_S or WILL_FIRE_RL_doFADD_S)
case (1'b1)
EN_req: stateR$D_IN = 2'd0;
WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_doFNMSUB_D || WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D:
stateR$D_IN = 2'd1;
WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_doFNMSUB_S || WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S:
stateR$D_IN = 2'd1;
default: stateR$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stateR$EN =
EN_req || WILL_FIRE_RL_doFNMSUB_D || WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S ||
WILL_FIRE_RL_rl_get_fpu_result ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S ;
// submodule fpu
always@(WILL_FIRE_RL_doFADD_S or
MUX_fpu$request_put_1__VAL_1 or
WILL_FIRE_RL_doFSUB_S or
MUX_fpu$request_put_1__VAL_2 or
WILL_FIRE_RL_doFMUL_S or
MUX_fpu$request_put_1__VAL_3 or
WILL_FIRE_RL_doFMADD_S or
MUX_fpu$request_put_1__VAL_4 or
WILL_FIRE_RL_doFMSUB_S or
MUX_fpu$request_put_1__VAL_5 or
WILL_FIRE_RL_doFNMADD_S or
MUX_fpu$request_put_1__VAL_6 or
WILL_FIRE_RL_doFNMSUB_S or
MUX_fpu$request_put_1__VAL_7 or
WILL_FIRE_RL_doFADD_D or
MUX_fpu$request_put_1__VAL_8 or
WILL_FIRE_RL_doFSUB_D or
MUX_fpu$request_put_1__VAL_9 or
WILL_FIRE_RL_doFMUL_D or
MUX_fpu$request_put_1__VAL_10 or
WILL_FIRE_RL_doFMADD_D or
MUX_fpu$request_put_1__VAL_11 or
WILL_FIRE_RL_doFMSUB_D or
MUX_fpu$request_put_1__VAL_12 or
WILL_FIRE_RL_doFNMADD_D or
MUX_fpu$request_put_1__VAL_13 or
WILL_FIRE_RL_doFNMSUB_D or MUX_fpu$request_put_1__VAL_14)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_doFADD_S: fpu$request_put = MUX_fpu$request_put_1__VAL_1;
WILL_FIRE_RL_doFSUB_S: fpu$request_put = MUX_fpu$request_put_1__VAL_2;
WILL_FIRE_RL_doFMUL_S: fpu$request_put = MUX_fpu$request_put_1__VAL_3;
WILL_FIRE_RL_doFMADD_S: fpu$request_put = MUX_fpu$request_put_1__VAL_4;
WILL_FIRE_RL_doFMSUB_S: fpu$request_put = MUX_fpu$request_put_1__VAL_5;
WILL_FIRE_RL_doFNMADD_S: fpu$request_put = MUX_fpu$request_put_1__VAL_6;
WILL_FIRE_RL_doFNMSUB_S: fpu$request_put = MUX_fpu$request_put_1__VAL_7;
WILL_FIRE_RL_doFADD_D: fpu$request_put = MUX_fpu$request_put_1__VAL_8;
WILL_FIRE_RL_doFSUB_D: fpu$request_put = MUX_fpu$request_put_1__VAL_9;
WILL_FIRE_RL_doFMUL_D: fpu$request_put = MUX_fpu$request_put_1__VAL_10;
WILL_FIRE_RL_doFMADD_D: fpu$request_put = MUX_fpu$request_put_1__VAL_11;
WILL_FIRE_RL_doFMSUB_D: fpu$request_put = MUX_fpu$request_put_1__VAL_12;
WILL_FIRE_RL_doFNMADD_D:
fpu$request_put = MUX_fpu$request_put_1__VAL_13;
WILL_FIRE_RL_doFNMSUB_D:
fpu$request_put = MUX_fpu$request_put_1__VAL_14;
default: fpu$request_put =
202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fpu$EN_request_put =
WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFNMSUB_D ;
assign fpu$EN_response_get = CAN_FIRE_RL_rl_get_fpu_result ;
// submodule frmFpuF
assign frmFpuF$D_IN = 1'b0 ;
assign frmFpuF$ENQ = 1'b0 ;
assign frmFpuF$DEQ = 1'b0 ;
assign frmFpuF$CLR = 1'b0 ;
// remaining internal signals
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_ETC__q60 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076 ?
_theResult___snd__h69713 :
_theResult____h61543 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396 ?
_theResult___snd__h128901 :
_theResult____h120602 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BIT_ETC__q65 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560 ?
_theResult___snd__h87566 :
_theResult____h79267 ;
assign IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q100 =
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469 ?
_theResult___snd__h119254 :
_theResult___snd__h137653 ;
assign IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q94 =
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076 ?
_theResult___snd__h119254 :
57'd0 ;
assign IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q62 =
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238 ?
_theResult___snd__h78325 :
57'd0 ;
assign IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q68 =
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633 ?
_theResult___snd__h78325 :
_theResult___snd__h96202 ;
assign IF_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_ETC___d2820 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
((_theResult___fst_exp__h69650 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87)) :
((_theResult___fst_exp__h78336 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1286 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36) :
((x__h36517[10:0] == 11'd2047) ?
requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1401 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
guard__h35772 != 2'b0 :
x__h36517[10:0] != 11'd2047 && guard__h36502 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d325 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9) :
((x__h7681[7:0] == 8'd255) ?
requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d475 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
guard__h7136 != 2'b0 :
x__h7681[7:0] != 8'd255 && guard__h7666 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d1584 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 ?
guard__h45468 != 2'b0 :
x__h46212[10:0] != 11'd2047 && guard__h46197 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d789 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 ?
guard__h13313 != 2'b0 :
x__h13854[7:0] != 8'd255 && guard__h13839 != 2'b0 ;
assign IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 =
(_theResult____h61543[56] ?
6'd0 :
(_theResult____h61543[55] ?
6'd1 :
(_theResult____h61543[54] ?
6'd2 :
(_theResult____h61543[53] ?
6'd3 :
(_theResult____h61543[52] ?
6'd4 :
(_theResult____h61543[51] ?
6'd5 :
(_theResult____h61543[50] ?
6'd6 :
(_theResult____h61543[49] ?
6'd7 :
(_theResult____h61543[48] ?
6'd8 :
(_theResult____h61543[47] ?
6'd9 :
(_theResult____h61543[46] ?
6'd10 :
(_theResult____h61543[45] ?
6'd11 :
(_theResult____h61543[44] ?
6'd12 :
(_theResult____h61543[43] ?
6'd13 :
(_theResult____h61543[42] ?
6'd14 :
(_theResult____h61543[41] ?
6'd15 :
(_theResult____h61543[40] ?
6'd16 :
(_theResult____h61543[39] ?
6'd17 :
(_theResult____h61543[38] ?
6'd18 :
(_theResult____h61543[37] ?
6'd19 :
(_theResult____h61543[36] ?
6'd20 :
(_theResult____h61543[35] ?
6'd21 :
(_theResult____h61543[34] ?
6'd22 :
(_theResult____h61543[33] ?
6'd23 :
(_theResult____h61543[32] ?
6'd24 :
(_theResult____h61543[31] ?
6'd25 :
(_theResult____h61543[30] ?
6'd26 :
(_theResult____h61543[29] ?
6'd27 :
(_theResult____h61543[28] ?
6'd28 :
(_theResult____h61543[27] ?
6'd29 :
(_theResult____h61543[26] ?
6'd30 :
(_theResult____h61543[25] ?
6'd31 :
(_theResult____h61543[24] ?
6'd32 :
(_theResult____h61543[23] ?
6'd33 :
(_theResult____h61543[22] ?
6'd34 :
(_theResult____h61543[21] ?
6'd35 :
(_theResult____h61543[20] ?
6'd36 :
(_theResult____h61543[19] ?
6'd37 :
(_theResult____h61543[18] ?
6'd38 :
(_theResult____h61543[17] ?
6'd39 :
(_theResult____h61543[16] ?
6'd40 :
(_theResult____h61543[15] ?
6'd41 :
(_theResult____h61543[14] ?
6'd42 :
(_theResult____h61543[13] ?
6'd43 :
(_theResult____h61543[12] ?
6'd44 :
(_theResult____h61543[11] ?
6'd45 :
(_theResult____h61543[10] ?
6'd46 :
(_theResult____h61543[9] ?
6'd47 :
(_theResult____h61543[8] ?
6'd48 :
(_theResult____h61543[7] ?
6'd49 :
(_theResult____h61543[6] ?
6'd50 :
(_theResult____h61543[5] ?
6'd51 :
(_theResult____h61543[4] ?
6'd52 :
(_theResult____h61543[3] ?
6'd53 :
(_theResult____h61543[2] ?
6'd54 :
(_theResult____h61543[1] ?
6'd55 :
(_theResult____h61543[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 =
(_theResult____h120602[56] ?
6'd0 :
(_theResult____h120602[55] ?
6'd1 :
(_theResult____h120602[54] ?
6'd2 :
(_theResult____h120602[53] ?
6'd3 :
(_theResult____h120602[52] ?
6'd4 :
(_theResult____h120602[51] ?
6'd5 :
(_theResult____h120602[50] ?
6'd6 :
(_theResult____h120602[49] ?
6'd7 :
(_theResult____h120602[48] ?
6'd8 :
(_theResult____h120602[47] ?
6'd9 :
(_theResult____h120602[46] ?
6'd10 :
(_theResult____h120602[45] ?
6'd11 :
(_theResult____h120602[44] ?
6'd12 :
(_theResult____h120602[43] ?
6'd13 :
(_theResult____h120602[42] ?
6'd14 :
(_theResult____h120602[41] ?
6'd15 :
(_theResult____h120602[40] ?
6'd16 :
(_theResult____h120602[39] ?
6'd17 :
(_theResult____h120602[38] ?
6'd18 :
(_theResult____h120602[37] ?
6'd19 :
(_theResult____h120602[36] ?
6'd20 :
(_theResult____h120602[35] ?
6'd21 :
(_theResult____h120602[34] ?
6'd22 :
(_theResult____h120602[33] ?
6'd23 :
(_theResult____h120602[32] ?
6'd24 :
(_theResult____h120602[31] ?
6'd25 :
(_theResult____h120602[30] ?
6'd26 :
(_theResult____h120602[29] ?
6'd27 :
(_theResult____h120602[28] ?
6'd28 :
(_theResult____h120602[27] ?
6'd29 :
(_theResult____h120602[26] ?
6'd30 :
(_theResult____h120602[25] ?
6'd31 :
(_theResult____h120602[24] ?
6'd32 :
(_theResult____h120602[23] ?
6'd33 :
(_theResult____h120602[22] ?
6'd34 :
(_theResult____h120602[21] ?
6'd35 :
(_theResult____h120602[20] ?
6'd36 :
(_theResult____h120602[19] ?
6'd37 :
(_theResult____h120602[18] ?
6'd38 :
(_theResult____h120602[17] ?
6'd39 :
(_theResult____h120602[16] ?
6'd40 :
(_theResult____h120602[15] ?
6'd41 :
(_theResult____h120602[14] ?
6'd42 :
(_theResult____h120602[13] ?
6'd43 :
(_theResult____h120602[12] ?
6'd44 :
(_theResult____h120602[11] ?
6'd45 :
(_theResult____h120602[10] ?
6'd46 :
(_theResult____h120602[9] ?
6'd47 :
(_theResult____h120602[8] ?
6'd48 :
(_theResult____h120602[7] ?
6'd49 :
(_theResult____h120602[6] ?
6'd50 :
(_theResult____h120602[5] ?
6'd51 :
(_theResult____h120602[4] ?
6'd52 :
(_theResult____h120602[3] ?
6'd53 :
(_theResult____h120602[2] ?
6'd54 :
(_theResult____h120602[1] ?
6'd55 :
(_theResult____h120602[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 =
(_theResult____h79267[56] ?
6'd0 :
(_theResult____h79267[55] ?
6'd1 :
(_theResult____h79267[54] ?
6'd2 :
(_theResult____h79267[53] ?
6'd3 :
(_theResult____h79267[52] ?
6'd4 :
(_theResult____h79267[51] ?
6'd5 :
(_theResult____h79267[50] ?
6'd6 :
(_theResult____h79267[49] ?
6'd7 :
(_theResult____h79267[48] ?
6'd8 :
(_theResult____h79267[47] ?
6'd9 :
(_theResult____h79267[46] ?
6'd10 :
(_theResult____h79267[45] ?
6'd11 :
(_theResult____h79267[44] ?
6'd12 :
(_theResult____h79267[43] ?
6'd13 :
(_theResult____h79267[42] ?
6'd14 :
(_theResult____h79267[41] ?
6'd15 :
(_theResult____h79267[40] ?
6'd16 :
(_theResult____h79267[39] ?
6'd17 :
(_theResult____h79267[38] ?
6'd18 :
(_theResult____h79267[37] ?
6'd19 :
(_theResult____h79267[36] ?
6'd20 :
(_theResult____h79267[35] ?
6'd21 :
(_theResult____h79267[34] ?
6'd22 :
(_theResult____h79267[33] ?
6'd23 :
(_theResult____h79267[32] ?
6'd24 :
(_theResult____h79267[31] ?
6'd25 :
(_theResult____h79267[30] ?
6'd26 :
(_theResult____h79267[29] ?
6'd27 :
(_theResult____h79267[28] ?
6'd28 :
(_theResult____h79267[27] ?
6'd29 :
(_theResult____h79267[26] ?
6'd30 :
(_theResult____h79267[25] ?
6'd31 :
(_theResult____h79267[24] ?
6'd32 :
(_theResult____h79267[23] ?
6'd33 :
(_theResult____h79267[22] ?
6'd34 :
(_theResult____h79267[21] ?
6'd35 :
(_theResult____h79267[20] ?
6'd36 :
(_theResult____h79267[19] ?
6'd37 :
(_theResult____h79267[18] ?
6'd38 :
(_theResult____h79267[17] ?
6'd39 :
(_theResult____h79267[16] ?
6'd40 :
(_theResult____h79267[15] ?
6'd41 :
(_theResult____h79267[14] ?
6'd42 :
(_theResult____h79267[13] ?
6'd43 :
(_theResult____h79267[12] ?
6'd44 :
(_theResult____h79267[11] ?
6'd45 :
(_theResult____h79267[10] ?
6'd46 :
(_theResult____h79267[9] ?
6'd47 :
(_theResult____h79267[8] ?
6'd48 :
(_theResult____h79267[7] ?
6'd49 :
(_theResult____h79267[6] ?
6'd50 :
(_theResult____h79267[5] ?
6'd51 :
(_theResult____h79267[4] ?
6'd52 :
(_theResult____h79267[3] ?
6'd53 :
(_theResult____h79267[2] ?
6'd54 :
(_theResult____h79267[1] ?
6'd55 :
(_theResult____h79267[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191__ETC___d3638 =
(_theResult___fst_exp__h128838 == 11'd2047) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133 =
(guard__h61553 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h69650 :
_theResult___exp__h70176 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135 =
(guard__h61553 == 2'b0) ?
_theResult___fst_exp__h69650 :
(requestR[191] ?
_theResult___exp__h70176 :
_theResult___fst_exp__h69650) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720 =
(guard__h61553 == 2'b0 || requestR[191]) ?
sfdin__h69644[56:34] :
_theResult___sfd__h70177 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722 =
(guard__h61553 == 2'b0) ?
sfdin__h69644[56:34] :
(requestR[191] ?
_theResult___sfd__h70177 :
sfdin__h69644[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453 =
(guard__h120612 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___fst_exp__h128838 :
_theResult___exp__h129567 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455 =
(guard__h120612 == 2'b0) ?
_theResult___fst_exp__h128838 :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___exp__h129567 :
_theResult___fst_exp__h128838) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582 =
(guard__h120612 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
sfdin__h128832[56:5] :
_theResult___sfd__h129568 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584 =
(guard__h120612 == 2'b0) ?
sfdin__h128832[56:5] :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___sfd__h129568 :
sfdin__h128832[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617 =
(guard__h79277 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h87503 :
_theResult___exp__h88029 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619 =
(guard__h79277 == 2'b0) ?
_theResult___fst_exp__h87503 :
(requestR[191] ?
_theResult___exp__h88029 :
_theResult___fst_exp__h87503) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766 =
(guard__h79277 == 2'b0 || requestR[191]) ?
sfdin__h87497[56:34] :
_theResult___sfd__h88030 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768 =
(guard__h79277 == 2'b0) ?
sfdin__h87497[56:34] :
(requestR[191] ?
_theResult___sfd__h88030 :
sfdin__h87497[56:34]) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128 =
(guard__h111304 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___fst_exp__h119265 :
_theResult___exp__h119920 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130 =
(guard__h111304 == 2'b0) ?
_theResult___fst_exp__h119265 :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___exp__h119920 :
_theResult___fst_exp__h119265) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522 =
(guard__h129679 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___fst_exp__h137669 :
_theResult___exp__h138349 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524 =
(guard__h129679 == 2'b0) ?
_theResult___fst_exp__h137669 :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___exp__h138349 :
_theResult___fst_exp__h137669) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555 =
(guard__h111304 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___snd__h119216[56:5] :
_theResult___sfd__h119921 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557 =
(guard__h111304 == 2'b0) ?
_theResult___snd__h119216[56:5] :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___sfd__h119921 :
_theResult___snd__h119216[56:5]) ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601 =
(guard__h129679 == 2'b0 ||
requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___snd__h137615[56:5] :
_theResult___sfd__h138350 ;
assign IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603 =
(guard__h129679 == 2'b0) ?
_theResult___snd__h137615[56:5] :
((requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
_theResult___sfd__h138350 :
_theResult___snd__h137615[56:5]) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290 =
(guard__h70288 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h78336 :
_theResult___exp__h78788 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292 =
(guard__h70288 == 2'b0) ?
_theResult___fst_exp__h78336 :
(requestR[191] ?
_theResult___exp__h78788 :
_theResult___fst_exp__h78336) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686 =
(guard__h88141 == 2'b0 || requestR[191]) ?
_theResult___fst_exp__h96218 :
_theResult___exp__h96695 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688 =
(guard__h88141 == 2'b0) ?
_theResult___fst_exp__h96218 :
(requestR[191] ?
_theResult___exp__h96695 :
_theResult___fst_exp__h96218) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739 =
(guard__h70288 == 2'b0 || requestR[191]) ?
_theResult___snd__h78287[56:34] :
_theResult___sfd__h78789 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741 =
(guard__h70288 == 2'b0) ?
_theResult___snd__h78287[56:34] :
(requestR[191] ?
_theResult___sfd__h78789 :
_theResult___snd__h78287[56:34]) ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785 =
(guard__h88141 == 2'b0 || requestR[191]) ?
_theResult___snd__h96164[56:34] :
_theResult___sfd__h96696 ;
assign IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787 =
(guard__h88141 == 2'b0) ?
_theResult___snd__h96164[56:34] :
(requestR[191] ?
_theResult___sfd__h96696 :
_theResult___snd__h96164[56:34]) ;
assign IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3646 =
(_theResult___fst_exp__h137669 == 11'd2047) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307 =
(guard__h35772 == 2'b0) ?
11'd0 :
(requestR[159] ? _theResult___exp__h36388 : 11'd0) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333 =
(guard__h36502 == 2'b0 || requestR[159]) ?
x__h36517[10:0] :
_theResult___exp__h37144 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335 =
(guard__h36502 == 2'b0) ?
x__h36517[10:0] :
(requestR[159] ? _theResult___exp__h37144 : x__h36517[10:0]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356 =
(guard__h35772 == 2'b0 || requestR[159]) ?
sfd___3__h35762[54:3] :
_theResult___sfd__h36389 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358 =
(guard__h35772 == 2'b0) ?
sfd___3__h35762[54:3] :
(requestR[159] ?
_theResult___sfd__h36389 :
sfd___3__h35762[54:3]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374 =
(guard__h36502 == 2'b0 || requestR[159]) ?
sfd___3__h35762[53:2] :
_theResult___sfd__h37145 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376 =
(guard__h36502 == 2'b0) ?
sfd___3__h35762[53:2] :
(requestR[159] ?
_theResult___sfd__h37145 :
sfd___3__h35762[53:2]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347 =
(guard__h7136 == 2'b0) ?
8'd0 :
(requestR[159] ? _theResult___exp__h7552 : 8'd0) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373 =
(guard__h7666 == 2'b0 || requestR[159]) ?
x__h7681[7:0] :
_theResult___exp__h8105 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375 =
(guard__h7666 == 2'b0) ?
x__h7681[7:0] :
(requestR[159] ? _theResult___exp__h8105 : x__h7681[7:0]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396 =
(guard__h7136 == 2'b0 || requestR[159]) ?
sfd___3__h7126[31:9] :
_theResult___sfd__h7553 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398 =
(guard__h7136 == 2'b0) ?
sfd___3__h7126[31:9] :
(requestR[159] ?
_theResult___sfd__h7553 :
sfd___3__h7126[31:9]) ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414 =
(guard__h7666 == 2'b0 || requestR[159]) ?
sfd___3__h7126[30:8] :
_theResult___sfd__h8106 ;
assign IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416 =
(guard__h7666 == 2'b0) ?
sfd___3__h7126[30:8] :
(requestR[159] ?
_theResult___sfd__h8106 :
sfd___3__h7126[30:8]) ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1031 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919[22] ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000) ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
(IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004 ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1029) ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1035 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22]) ?
res__h18062 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1034 ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1045 =
IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004 ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1044 ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1047 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919[22]) ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
(IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000 ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1045) ;
assign IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1051 =
(sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22]) ?
res__h18062 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1050 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1032 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22]) ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1031 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1034 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22] &&
sV2_exp__h918 == 8'd255 &&
sV2_sfd__h919[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1032 } ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1036 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22]) ?
res__h17825 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1035 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1048 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22]) ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1047 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1050 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22] &&
sV2_exp__h918 == 8'd255 &&
sV2_sfd__h919[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1048 } ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1052 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22]) ?
res__h17825 :
IF_IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF__ETC___d1051 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1122 =
(sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
res___1__h26467 :
((sV1_exp__h815 == 8'd0) ? res___1__h26486 : res__h26502) ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1123 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0) ?
res___1__h26457 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1122 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 =
((sV1_exp__h815 == 8'd0) ?
(sV1_sfd__h816[22] ?
6'd2 :
(sV1_sfd__h816[21] ?
6'd3 :
(sV1_sfd__h816[20] ?
6'd4 :
(sV1_sfd__h816[19] ?
6'd5 :
(sV1_sfd__h816[18] ?
6'd6 :
(sV1_sfd__h816[17] ?
6'd7 :
(sV1_sfd__h816[16] ?
6'd8 :
(sV1_sfd__h816[15] ?
6'd9 :
(sV1_sfd__h816[14] ?
6'd10 :
(sV1_sfd__h816[13] ?
6'd11 :
(sV1_sfd__h816[12] ?
6'd12 :
(sV1_sfd__h816[11] ?
6'd13 :
(sV1_sfd__h816[10] ?
6'd14 :
(sV1_sfd__h816[9] ?
6'd15 :
(sV1_sfd__h816[8] ?
6'd16 :
(sV1_sfd__h816[7] ?
6'd17 :
(sV1_sfd__h816[6] ?
6'd18 :
(sV1_sfd__h816[5] ?
6'd19 :
(sV1_sfd__h816[4] ?
6'd20 :
(sV1_sfd__h816[3] ?
6'd21 :
(sV1_sfd__h816[2] ?
6'd22 :
(sV1_sfd__h816[1] ?
6'd23 :
(sV1_sfd__h816[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0) ?
_theResult___snd_fst_sfd__h100339 :
_theResult___fst_sfd__h138466 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3650 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
(sV1_exp__h815 == 8'd255 || sV1_exp__h815 == 8'd0) &&
sV1_sfd__h816 == 23'd0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((sV1_exp__h815 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_ETC___d3630 :
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3648) ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3685 =
(sV1_exp__h815 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 &&
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[4] :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 &&
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[4] ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3688 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0) ?
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22] :
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3685 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3695 =
(sV1_exp__h815 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 &&
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[3] :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 &&
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[3] ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3709 =
(sV1_exp__h815 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ||
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[2] :
!SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ||
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3707 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3721 =
(sV1_exp__h815 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 &&
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ||
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[1]) :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 &&
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3719 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3733 =
(sV1_exp__h815 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ||
!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 &&
_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664[0] :
!SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ||
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3731 ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d886 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815 :
((sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
32'd0 :
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d884) ;
assign IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d946 =
(sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
32'd0 :
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917[19] ?
32'hFFFFFFFF :
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d944) ;
assign IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227 =
sfd__h2222[31] ?
6'd0 :
(sfd__h2222[30] ?
6'd1 :
(sfd__h2222[29] ?
6'd2 :
(sfd__h2222[28] ?
6'd3 :
(sfd__h2222[27] ?
6'd4 :
(sfd__h2222[26] ?
6'd5 :
(sfd__h2222[25] ?
6'd6 :
(sfd__h2222[24] ?
6'd7 :
(sfd__h2222[23] ?
6'd8 :
(sfd__h2222[22] ?
6'd9 :
(sfd__h2222[21] ?
6'd10 :
(sfd__h2222[20] ?
6'd11 :
(sfd__h2222[19] ?
6'd12 :
(sfd__h2222[18] ?
6'd13 :
(sfd__h2222[17] ?
6'd14 :
(sfd__h2222[16] ?
6'd15 :
(sfd__h2222[15] ?
6'd16 :
(sfd__h2222[14] ?
6'd17 :
(sfd__h2222[13] ?
6'd18 :
(sfd__h2222[12] ?
6'd19 :
(sfd__h2222[11] ?
6'd20 :
(sfd__h2222[10] ?
6'd21 :
(sfd__h2222[9] ?
6'd22 :
(sfd__h2222[8] ?
6'd23 :
(sfd__h2222[7] ?
6'd24 :
(sfd__h2222[6] ?
6'd25 :
(sfd__h2222[5] ?
6'd26 :
(sfd__h2222[4] ?
6'd27 :
(sfd__h2222[3] ?
6'd28 :
(sfd__h2222[2] ?
6'd29 :
(sfd__h2222[1] ?
6'd30 :
(sfd__h2222[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255 =
sfd__h2222[31] ?
6'd0 :
(sfd__h2222[30] ?
6'd1 :
(sfd__h2222[29] ?
6'd2 :
(sfd__h2222[28] ?
6'd3 :
(sfd__h2222[27] ?
6'd4 :
(sfd__h2222[26] ?
6'd5 :
(sfd__h2222[25] ?
6'd6 :
(sfd__h2222[24] ?
6'd7 :
(sfd__h2222[23] ?
6'd8 :
(sfd__h2222[22] ?
6'd9 :
(sfd__h2222[21] ?
6'd10 :
(sfd__h2222[20] ?
6'd11 :
(sfd__h2222[19] ?
6'd12 :
(sfd__h2222[18] ?
6'd13 :
(sfd__h2222[17] ?
6'd14 :
(sfd__h2222[16] ?
6'd15 :
(sfd__h2222[15] ?
6'd16 :
(sfd__h2222[14] ?
6'd17 :
(sfd__h2222[13] ?
6'd18 :
(sfd__h2222[12] ?
6'd19 :
(sfd__h2222[11] ?
6'd20 :
(sfd__h2222[10] ?
6'd21 :
(sfd__h2222[9] ?
6'd22 :
(sfd__h2222[8] ?
6'd23 :
(sfd__h2222[7] ?
6'd24 :
(sfd__h2222[6] ?
6'd25 :
(sfd__h2222[5] ?
6'd26 :
(sfd__h2222[4] ?
6'd27 :
(sfd__h2222[3] ?
6'd28 :
(sfd__h2222[2] ?
6'd29 :
(sfd__h2222[1] ?
6'd30 :
(sfd__h2222[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d882 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876 ?
((x__h15726[56:25] == 32'h7FFFFFFF) ?
x__h15726[56:25] :
x__h15726[56:25] + 32'd1) :
x__h15726[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d884 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 ==
20'd1048545) ?
((_theResult_____2__h14985[32:31] == 2'b11) ?
_theResult_____2__h14985[31:0] :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815) :
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853[19] ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815 :
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d882) ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d908 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 ==
20'd1048545) ?
_theResult_____2__h14985[32:31] == 2'b11 &&
guard__h14983 != 2'd0 :
!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853[19] &&
(!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 ||
guard__h15537 != 2'd0) ;
assign IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d944 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938 ?
((x__h16821[56:25] == 32'hFFFFFFFF) ?
x__h16821[56:25] :
x__h16821[56:25] + 32'd1) :
x__h16821[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1673 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667 ?
((x__h48283[85:54] == 32'h7FFFFFFF) ?
x__h48283[85:54] :
x__h48283[85:54] + 32'd1) :
x__h48283[85:54]) :
32'd0 ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1675 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 ==
24'd16777185) ?
((_theResult_____2__h47542[32:31] == 2'b11) ?
_theResult_____2__h47542[31:0] :
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606) :
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644[23] ?
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606 :
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1673) ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1699 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 ==
24'd16777185) ?
_theResult_____2__h47542[32:31] == 2'b11 &&
guard__h47540 != 2'd0 :
!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644[23] &&
(!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 ||
guard__h48094 != 2'd0) ;
assign IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1735 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 ?
(IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729 ?
((x__h49361[85:54] == 32'hFFFFFFFF) ?
x__h49361[85:54] :
x__h49361[85:54] + 32'd1) :
x__h49361[85:54]) :
32'd0 ;
assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_15_ETC___d1287 =
(!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233) ?
requestR[159] :
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1286 ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_ETC___d3630 =
(!_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ||
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ||
_theResult___fst_exp__h119265 == 11'd2047) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109) ;
assign IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1029 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 ?
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } :
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 ;
assign IF_NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFF_ETC___d1044 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 ?
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 :
{ requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign IF_NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1024 =
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015 :
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 &&
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468 =
((SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99[10],
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99 }) -
12'd3074 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3648 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ?
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191__ETC___d3638 :
IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFF_ETC___d3646) :
requestR[191:160] == 32'hFFFFFFFF && requestR[159] ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3707 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[2] :
_theResult___fst_exp__h138450 == 11'd2047 &&
_theResult___fst_sfd__h138451 == 52'd0 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3719 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[1] :
_theResult___fst_exp__h137669 == 11'd0 &&
guard__h129679 != 2'b0 ;
assign IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3731 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681[0] :
_theResult___fst_exp__h137669 != 11'd2047 &&
guard__h129679 != 2'b0 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632 =
((SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67[7],
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67 }) -
9'd386 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2838 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
((_theResult___fst_exp__h87503 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91)) :
((_theResult___fst_exp__h96218 == 8'd255) ?
requestR[191] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93)) ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2916 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[2] :
_theResult___fst_exp__h96796 == 8'd255 &&
_theResult___fst_sfd__h96797 == 23'd0 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2929 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[1] :
_theResult___fst_exp__h96218 == 8'd0 && guard__h88141 != 2'b0 ;
assign IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2942 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[0] :
_theResult___fst_exp__h96218 != 8'd255 &&
guard__h88141 != 2'b0 ;
assign IF_requestR_BITS_126_TO_116_745_EQ_2047_746_AN_ETC___d3793 =
(requestR[126:116] == 11'd2047 && requestR[115] ||
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762) ?
requestR[191:128] :
(requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766 ?
requestR[127:64] :
res__h143531) ;
assign IF_requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_T_ETC___d1004 =
sV2_exp__h918 == 8'd0 && sV2_sfd__h919 == 23'd0 &&
requestR[127:96] == 32'hFFFFFFFF &&
requestR[95] &&
sV1_exp__h815 == 8'd0 &&
sV1_sfd__h816 == 23'd0 &&
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1384 =
(requestR[159:128] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233) ?
52'd0 :
_theResult___snd_fst_sfd__h37248 ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1567 =
(requestR[159:128] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 ||
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447) ?
52'd0 :
_theResult___snd_fst_sfd__h46942 ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d385 =
(requestR[159:128] == 32'd0 ||
!sfd__h2222[31] && !sfd__h2222[30] && !sfd__h2222[29] &&
!sfd__h2222[28] &&
!sfd__h2222[27] &&
!sfd__h2222[26] &&
!sfd__h2222[25] &&
!sfd__h2222[24] &&
!sfd__h2222[23] &&
!sfd__h2222[22] &&
!sfd__h2222[21] &&
!sfd__h2222[20] &&
!sfd__h2222[19] &&
!sfd__h2222[18] &&
!sfd__h2222[17] &&
!sfd__h2222[16] &&
!sfd__h2222[15] &&
!sfd__h2222[14] &&
!sfd__h2222[13] &&
!sfd__h2222[12] &&
!sfd__h2222[11] &&
!sfd__h2222[10] &&
!sfd__h2222[9] &&
!sfd__h2222[8] &&
!sfd__h2222[7] &&
!sfd__h2222[6] &&
!sfd__h2222[5] &&
!sfd__h2222[4] &&
!sfd__h2222[3] &&
!sfd__h2222[2] &&
!sfd__h2222[1] &&
!sfd__h2222[0]) ?
8'd0 :
_theResult___snd_fst_exp__h8214 ;
assign IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d703 =
(requestR[159:128] == 32'd0 ||
!requestR[159] &&
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579) ?
8'd0 :
_theResult___snd_fst_exp__h14386 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d1737 =
(requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
32'd0 :
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708[23] ?
32'hFFFFFFFF :
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1735) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3807 =
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762 ?
requestR[127:64] :
(requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766 ?
requestR[191:128] :
res__h148079) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3878 =
(requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
res___1__h156271 :
((requestR[190:180] == 11'd0) ?
res___1__h156290 :
res__h156306) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 =
((requestR[190:180] == 11'd0) ?
(requestR[179] ?
6'd2 :
(requestR[178] ?
6'd3 :
(requestR[177] ?
6'd4 :
(requestR[176] ?
6'd5 :
(requestR[175] ?
6'd6 :
(requestR[174] ?
6'd7 :
(requestR[173] ?
6'd8 :
(requestR[172] ?
6'd9 :
(requestR[171] ?
6'd10 :
(requestR[170] ?
6'd11 :
(requestR[169] ?
6'd12 :
(requestR[168] ?
6'd13 :
(requestR[167] ?
6'd14 :
(requestR[166] ?
6'd15 :
(requestR[165] ?
6'd16 :
(requestR[164] ?
6'd17 :
(requestR[163] ?
6'd18 :
(requestR[162] ?
6'd19 :
(requestR[161] ?
6'd20 :
(requestR[160] ?
6'd21 :
(requestR[159] ?
6'd22 :
(requestR[158] ?
6'd23 :
(requestR[157] ?
6'd24 :
(requestR[156] ?
6'd25 :
(requestR[155] ?
6'd26 :
(requestR[154] ?
6'd27 :
(requestR[153] ?
6'd28 :
(requestR[152] ?
6'd29 :
(requestR[151] ?
6'd30 :
(requestR[150] ?
6'd31 :
(requestR[149] ?
6'd32 :
(requestR[148] ?
6'd33 :
(requestR[147] ?
6'd34 :
(requestR[146] ?
6'd35 :
(requestR[145] ?
6'd36 :
(requestR[144] ?
6'd37 :
(requestR[143] ?
6'd38 :
(requestR[142] ?
6'd39 :
(requestR[141] ?
6'd40 :
(requestR[140] ?
6'd41 :
(requestR[139] ?
6'd42 :
(requestR[138] ?
6'd43 :
(requestR[137] ?
6'd44 :
(requestR[136] ?
6'd45 :
(requestR[135] ?
6'd46 :
(requestR[134] ?
6'd47 :
(requestR[133] ?
6'd48 :
(requestR[132] ?
6'd49 :
(requestR[131] ?
6'd50 :
(requestR[130] ?
6'd51 :
(requestR[129] ?
6'd52 :
(requestR[128] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2840 =
(requestR[190:180] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ?
IF_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_ETC___d2820 :
requestR[191]) :
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ?
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2838 :
requestR[191]) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2891 =
(requestR[190:180] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2873 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 &&
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[4] ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2902 =
(requestR[190:180] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2898 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 &&
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887[3] ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2918 =
(requestR[190:180] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2910 :
!SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ||
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2916 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2931 =
(requestR[190:180] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2925 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 &&
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2929 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2944 =
(requestR[190:180] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2938 :
!SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ||
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2942 ;
assign IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d1677 =
(requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0) ?
IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606 :
((requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
32'd0 :
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1675) ;
assign IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ?
_theResult___snd_fst_sfd__h53867 :
_theResult___fst_sfd__h96812 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1000 =
sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159] &&
sV2_exp__h918 == 8'd0 &&
sV2_sfd__h919 == 23'd0 &&
(requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 =
sV1_exp__h815 < sV2_exp__h918 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 =
sV1_exp__h815 == sV2_exp__h918 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015 =
sV1_sfd__h816 < sV2_sfd__h919 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 =
sV1_exp__h815 <= sV2_exp__h918 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020 =
sV1_sfd__h816 <= sV2_sfd__h919 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22] ||
sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22] ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038 ||
sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22] ||
sV2_exp__h918 == 8'd255 && sV2_sfd__h919[22] ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1086 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020) &&
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090 =
sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0 &&
sV2_exp__h918 == 8'd0 &&
sV2_sfd__h919 == 23'd0 ||
NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_ETC___d1089 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 =
(requestR[191:160] == 32'hFFFFFFFF) ?
requestR[158:128] :
31'h7FC00000 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) &&
sV1_exp__h815 == 8'd255 &&
sV1_sfd__h816 == 23'd0 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d815 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818 =
sV1_exp__h815 - 8'd127 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
-b__h15050 :
b__h15050 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d948 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
32'd0 :
((sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0) ?
32'hFFFFFFFF :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d946) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0 ||
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917[19] ||
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938 &&
x__h16821[56:25] == 32'hFFFFFFFF) ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d967 =
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956,
3'd0,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961 } ==
5'd0 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956 ;
assign IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990 =
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22] &&
sV2_exp__h918 == 8'd255 &&
sV2_sfd__h919 != 23'd0 &&
!sV2_sfd__h919[22] ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1635 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h47540 == 2'b10) ?
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[53] :
guard__h47540 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h47540 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85] &&
guard__h47540 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h48094 == 2'b10) ?
x__h48283[54] :
guard__h48094 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h48094 != 2'd0 :
requestR[194:192] == 3'h1 && x__h48283[85] &&
guard__h48094 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h49140 == 2'b10) ?
x__h49361[54] :
guard__h49140 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h49140 != 2'd0 ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d844 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h14983 == 2'b10) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[24] :
guard__h14983 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h14983 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56] &&
guard__h14983 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h15537 == 2'b10) ?
x__h15726[25] :
guard__h15537 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h15537 != 2'd0 :
requestR[194:192] == 3'h1 && x__h15726[56] &&
guard__h15537 != 2'd0) ;
assign IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d938 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h16600 == 2'b10) ?
x__h16821[25] :
guard__h16600 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h16600 != 2'd0 ;
assign IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442 =
requestR[159] ?
6'd0 :
(requestR[158] ?
6'd1 :
(requestR[157] ?
6'd2 :
(requestR[156] ?
6'd3 :
(requestR[155] ?
6'd4 :
(requestR[154] ?
6'd5 :
(requestR[153] ?
6'd6 :
(requestR[152] ?
6'd7 :
(requestR[151] ?
6'd8 :
(requestR[150] ?
6'd9 :
(requestR[149] ?
6'd10 :
(requestR[148] ?
6'd11 :
(requestR[147] ?
6'd12 :
(requestR[146] ?
6'd13 :
(requestR[145] ?
6'd14 :
(requestR[144] ?
6'd15 :
(requestR[143] ?
6'd16 :
(requestR[142] ?
6'd17 :
(requestR[141] ?
6'd18 :
(requestR[140] ?
6'd19 :
(requestR[139] ?
6'd20 :
(requestR[138] ?
6'd21 :
(requestR[137] ?
6'd22 :
(requestR[136] ?
6'd23 :
(requestR[135] ?
6'd24 :
(requestR[134] ?
6'd25 :
(requestR[133] ?
6'd26 :
(requestR[132] ?
6'd27 :
(requestR[131] ?
6'd28 :
(requestR[130] ?
6'd29 :
(requestR[129] ?
6'd30 :
(requestR[128] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613 =
requestR[159] ?
6'd0 :
(requestR[158] ?
6'd1 :
(requestR[157] ?
6'd2 :
(requestR[156] ?
6'd3 :
(requestR[155] ?
6'd4 :
(requestR[154] ?
6'd5 :
(requestR[153] ?
6'd6 :
(requestR[152] ?
6'd7 :
(requestR[151] ?
6'd8 :
(requestR[150] ?
6'd9 :
(requestR[149] ?
6'd10 :
(requestR[148] ?
6'd11 :
(requestR[147] ?
6'd12 :
(requestR[146] ?
6'd13 :
(requestR[145] ?
6'd14 :
(requestR[144] ?
6'd15 :
(requestR[143] ?
6'd16 :
(requestR[142] ?
6'd17 :
(requestR[141] ?
6'd18 :
(requestR[140] ?
6'd19 :
(requestR[139] ?
6'd20 :
(requestR[138] ?
6'd21 :
(requestR[137] ?
6'd22 :
(requestR[136] ?
6'd23 :
(requestR[135] ?
6'd24 :
(requestR[134] ?
6'd25 :
(requestR[133] ?
6'd26 :
(requestR[132] ?
6'd27 :
(requestR[131] ?
6'd28 :
(requestR[130] ?
6'd29 :
(requestR[129] ?
6'd30 :
(requestR[128] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d466 =
(sfd__h2222[31] || sfd__h2222[30] || sfd__h2222[29] ||
sfd__h2222[28] ||
sfd__h2222[27] ||
sfd__h2222[26] ||
sfd__h2222[25] ||
sfd__h2222[24] ||
sfd__h2222[23] ||
sfd__h2222[22] ||
sfd__h2222[21] ||
sfd__h2222[20] ||
sfd__h2222[19] ||
sfd__h2222[18] ||
sfd__h2222[17] ||
sfd__h2222[16] ||
sfd__h2222[15] ||
sfd__h2222[14] ||
sfd__h2222[13] ||
sfd__h2222[12] ||
sfd__h2222[11] ||
sfd__h2222[10] ||
sfd__h2222[9] ||
sfd__h2222[8] ||
sfd__h2222[7] ||
sfd__h2222[6] ||
sfd__h2222[5] ||
sfd__h2222[4] ||
sfd__h2222[3] ||
sfd__h2222[2] ||
sfd__h2222[1] ||
sfd__h2222[0]) &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 &&
_theResult___fst_exp__h8205 == 8'd255 &&
_theResult___fst_sfd__h8206 == 23'd0) ;
assign IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d469 =
(sfd__h2222[31] || sfd__h2222[30] || sfd__h2222[29] ||
sfd__h2222[28] ||
sfd__h2222[27] ||
sfd__h2222[26] ||
sfd__h2222[25] ||
sfd__h2222[24] ||
sfd__h2222[23] ||
sfd__h2222[22] ||
sfd__h2222[21] ||
sfd__h2222[20] ||
sfd__h2222[19] ||
sfd__h2222[18] ||
sfd__h2222[17] ||
sfd__h2222[16] ||
sfd__h2222[15] ||
sfd__h2222[14] ||
sfd__h2222[13] ||
sfd__h2222[12] ||
sfd__h2222[11] ||
sfd__h2222[10] ||
sfd__h2222[9] ||
sfd__h2222[8] ||
sfd__h2222[7] ||
sfd__h2222[6] ||
sfd__h2222[5] ||
sfd__h2222[4] ||
sfd__h2222[3] ||
sfd__h2222[2] ||
sfd__h2222[1] ||
sfd__h2222[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 ;
assign IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d478 =
(sfd__h2222[31] || sfd__h2222[30] || sfd__h2222[29] ||
sfd__h2222[28] ||
sfd__h2222[27] ||
sfd__h2222[26] ||
sfd__h2222[25] ||
sfd__h2222[24] ||
sfd__h2222[23] ||
sfd__h2222[22] ||
sfd__h2222[21] ||
sfd__h2222[20] ||
sfd__h2222[19] ||
sfd__h2222[18] ||
sfd__h2222[17] ||
sfd__h2222[16] ||
sfd__h2222[15] ||
sfd__h2222[14] ||
sfd__h2222[13] ||
sfd__h2222[12] ||
sfd__h2222[11] ||
sfd__h2222[10] ||
sfd__h2222[9] ||
sfd__h2222[8] ||
sfd__h2222[7] ||
sfd__h2222[6] ||
sfd__h2222[5] ||
sfd__h2222[4] ||
sfd__h2222[3] ||
sfd__h2222[2] ||
sfd__h2222[1] ||
sfd__h2222[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d475 ;
assign IF_requestR_BIT_191_186_THEN_2147483648_ELSE_2_ETC___d1606 =
requestR[191] ? 32'h80000000 : 32'h7FFFFFFF ;
assign IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618 =
requestR[191] ? -b__h47607 : b__h47607 ;
assign IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786 =
requestR[191] ?
!requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 ||
requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 &&
!requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778 :
requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 ||
requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 &&
requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783 ;
assign IF_sfd___3126_BIT_7_THEN_2_ELSE_0__q7 =
sfd___3__h7126[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___3126_BIT_8_THEN_2_ELSE_0__q6 =
sfd___3__h7126[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___33303_BIT_7_THEN_2_ELSE_0__q21 =
sfd___3__h13303[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___33303_BIT_8_THEN_2_ELSE_0__q20 =
sfd___3__h13303[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___35458_BIT_1_THEN_2_ELSE_0__q48 =
sfd___3__h45458[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___35458_BIT_2_THEN_2_ELSE_0__q47 =
sfd___3__h45458[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___35762_BIT_1_THEN_2_ELSE_0__q34 =
sfd___3__h35762[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___35762_BIT_2_THEN_2_ELSE_0__q33 =
sfd___3__h35762[2] ? 2'd2 : 2'd0 ;
assign IF_sfdin28832_BIT_4_THEN_2_ELSE_0__q98 =
sfdin__h128832[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin7497_BIT_33_THEN_2_ELSE_0__q66 =
sfdin__h87497[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin9644_BIT_33_THEN_2_ELSE_0__q61 =
sfdin__h69644[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd19216_BIT_4_THEN_2_ELSE_0__q95 =
_theResult___snd__h119216[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd37615_BIT_4_THEN_2_ELSE_0__q101 =
_theResult___snd__h137615[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd6164_BIT_33_THEN_2_ELSE_0__q69 =
_theResult___snd__h96164[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd8287_BIT_33_THEN_2_ELSE_0__q63 =
_theResult___snd__h78287[33] ? 2'd2 : 2'd0 ;
assign IF_x5726_BIT_24_THEN_2_ELSE_0__q31 = x__h15726[24] ? 2'd2 : 2'd0 ;
assign IF_x6821_BIT_24_THEN_2_ELSE_0__q32 = x__h16821[24] ? 2'd2 : 2'd0 ;
assign IF_x8283_BIT_53_THEN_2_ELSE_0__q58 = x__h48283[53] ? 2'd2 : 2'd0 ;
assign IF_x9361_BIT_53_THEN_2_ELSE_0__q59 = x__h49361[53] ? 2'd2 : 2'd0 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 =
-{ {12{IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818[7]}},
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818 } ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 +
20'd32 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852 -
20'd2 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917 =
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d852 -
20'd1 ;
assign NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 =
(NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 =
-{ {13{requestR_BITS_190_TO_180_596_MINUS_1023___d1609[10]}},
requestR_BITS_190_TO_180_596_MINUS_1023___d1609 } ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 +
24'd32 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643 -
24'd2 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644 ^
24'h800000) <=
24'd8388640 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708 =
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1643 -
24'd1 ;
assign NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 =
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708 ^
24'h800000) <=
24'd8388640 ;
assign NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2910 =
!_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ||
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[2] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_76_ETC___d2938 =
!_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ||
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[0] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[0]) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1027 =
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0 ||
sV2_exp__h918 != 8'd0 ||
sV2_sfd__h919 != 23'd0) &&
requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026 ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 =
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV2_exp__h918 != 8'd255 || sV2_sfd__h919 == 23'd0) &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1027 ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1085 =
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1013 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1015) &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1018 &&
(!IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1014 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1020) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1091 =
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV2_exp__h918 != 8'd255 || sV2_sfd__h919 == 23'd0) &&
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090 ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1109 =
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV2_exp__h918 != 8'd255 || sV2_sfd__h919 == 23'd0) &&
(requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026 ||
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1090) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047 =
!sV1_sfd__h816[21] && !sV1_sfd__h816[20] && !sV1_sfd__h816[19] &&
!sV1_sfd__h816[18] &&
!sV1_sfd__h816[17] &&
!sV1_sfd__h816[16] &&
!sV1_sfd__h816[15] &&
!sV1_sfd__h816[14] &&
!sV1_sfd__h816[13] &&
!sV1_sfd__h816[12] &&
!sV1_sfd__h816[11] &&
!sV1_sfd__h816[10] &&
!sV1_sfd__h816[9] &&
!sV1_sfd__h816[8] &&
!sV1_sfd__h816[7] &&
!sV1_sfd__h816[6] &&
!sV1_sfd__h816[5] &&
!sV1_sfd__h816[4] &&
!sV1_sfd__h816[3] &&
!sV1_sfd__h816[2] &&
!sV1_sfd__h816[1] &&
!sV1_sfd__h816[0] ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d897 =
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
((NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d820 ==
20'd1048545) ?
_theResult_____2__h14985[32:31] != 2'b11 :
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853[19] ||
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d855 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d876 &&
x__h15726[56:25] == 32'h7FFFFFFF) ;
assign NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961 =
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917[19] &&
(!NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d919 ||
guard__h16600 != 2'd0) ;
assign NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263 =
!sfd__h2222[31] && !sfd__h2222[30] && !sfd__h2222[29] &&
!sfd__h2222[28] &&
!sfd__h2222[27] &&
!sfd__h2222[26] &&
!sfd__h2222[25] &&
!sfd__h2222[24] &&
!sfd__h2222[23] &&
!sfd__h2222[22] &&
!sfd__h2222[21] &&
!sfd__h2222[20] &&
!sfd__h2222[19] &&
!sfd__h2222[18] &&
!sfd__h2222[17] &&
!sfd__h2222[16] &&
!sfd__h2222[15] &&
!sfd__h2222[14] &&
!sfd__h2222[13] &&
!sfd__h2222[12] &&
!sfd__h2222[11] &&
!sfd__h2222[10] &&
!sfd__h2222[9] &&
!sfd__h2222[8] &&
!sfd__h2222[7] &&
!sfd__h2222[6] &&
!sfd__h2222[5] &&
!sfd__h2222[4] &&
!sfd__h2222[3] &&
!sfd__h2222[2] &&
!sfd__h2222[1] &&
!sfd__h2222[0] ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 ;
assign NOT_requestR_BITS_159_TO_128_24_EQ_0_25_26_AND_ETC___d781 =
requestR[159:128] != 32'd0 &&
(requestR[159] ||
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770) &&
(!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 &&
_theResult___fst_exp__h14377 == 8'd255 &&
_theResult___fst_sfd__h14378 == 23'd0) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1688 =
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
((NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1611 ==
24'd16777185) ?
_theResult_____2__h47542[32:31] != 2'b11 :
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644[23] ||
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1646 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1667 &&
x__h48283[85:54] == 32'h7FFFFFFF) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752 =
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708[23] &&
(!NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 ||
guard__h49140 != 2'd0) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 =
(requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) &&
(requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0 ||
requestR[126:116] != 11'd0 ||
requestR[115:64] != 52'd0) &&
(requestR[191] && !requestR[127] ||
(requestR[191] || !requestR[127]) &&
IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786) ;
assign NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3855 =
(requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) &&
(requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) &&
(requestR[191] && !requestR[127] ||
(requestR[191] || !requestR[127]) &&
IF_requestR_BIT_191_186_THEN_NOT_requestR_BITS_ETC___d3786 ||
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836) ;
assign NOT_requestR_BITS_190_TO_180_596_ULT_requestR__ETC___d3832 =
!requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
!requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783) &&
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778) ;
assign NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_ETC___d1089 =
(requestR[191:160] != 32'hFFFFFFFF || !requestR[159] ||
requestR[127:96] == 32'hFFFFFFFF && requestR[95]) &&
(requestR[191:160] == 32'hFFFFFFFF && requestR[159] ||
requestR[127:96] != 32'hFFFFFFFF ||
!requestR[95]) &&
((requestR[191:160] != 32'hFFFFFFFF || !requestR[159]) ?
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1085 :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1086) ;
assign NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579 =
!requestR[158] && !requestR[157] && !requestR[156] &&
!requestR[155] &&
!requestR[154] &&
!requestR[153] &&
!requestR[152] &&
!requestR[151] &&
!requestR[150] &&
!requestR[149] &&
!requestR[148] &&
!requestR[147] &&
!requestR[146] &&
!requestR[145] &&
!requestR[144] &&
!requestR[143] &&
!requestR[142] &&
!requestR[141] &&
!requestR[140] &&
!requestR[139] &&
!requestR[138] &&
!requestR[137] &&
!requestR[136] &&
!requestR[135] &&
!requestR[134] &&
!requestR[133] &&
!requestR[132] &&
!requestR[131] &&
!requestR[130] &&
!requestR[129] &&
!requestR[128] ;
assign NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181 =
!requestR[179] && !requestR[178] && !requestR[177] &&
!requestR[176] &&
!requestR[175] &&
!requestR[174] &&
!requestR[173] &&
!requestR[172] &&
!requestR[171] &&
!requestR[170] &&
!requestR[169] &&
!requestR[168] &&
!requestR[167] &&
!requestR[166] &&
!requestR[165] &&
!requestR[164] &&
!requestR[163] &&
!requestR[162] &&
!requestR[161] &&
!requestR[160] &&
!requestR[159] &&
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 =
{ {4{IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818[7]}},
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d818 } ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 =
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 =
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 +
12'd1023 ;
assign SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q99 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] -
11'd1023 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 =
{ requestR_BITS_190_TO_180_596_MINUS_1023___d1609[10],
requestR_BITS_190_TO_180_596_MINUS_1023___d1609 } ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 =
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 ^
12'h800) <=
12'd2175 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 =
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 ^
12'h800) <
12'd1922 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 +
12'd127 ;
assign SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q67 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858 =
{ 3'd0,
_theResult___fst_exp__h69650 == 8'd0 &&
(sfdin__h69644[56:34] == 23'd0 || guard__h61553 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h70277 == 8'd255 &&
_theResult___fst_sfd__h70278 == 23'd0,
1'd0,
_theResult___fst_exp__h69650 != 8'd255 &&
guard__h61553 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3681 =
{ 3'd0,
_theResult___fst_exp__h128838 == 11'd0 &&
(sfdin__h128832[56:5] == 52'd0 || guard__h120612 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h129668 == 11'd2047 &&
_theResult___fst_sfd__h129669 == 52'd0,
1'd0,
_theResult___fst_exp__h128838 != 11'd2047 &&
guard__h120612 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2887 =
{ 3'd0,
_theResult___fst_exp__h87503 == 8'd0 &&
(sfdin__h87497[56:34] == 23'd0 || guard__h79277 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h88130 == 8'd255 &&
_theResult___fst_sfd__h88131 == 23'd0,
1'd0,
_theResult___fst_exp__h87503 != 8'd255 &&
guard__h79277 != 2'b0 } ;
assign _0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076 =
({ 6'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469 =
({ 6'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ^
12'h800) <=
(IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468 ^
12'h800) ;
assign _0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3664 =
{ 3'd0,
_theResult___fst_exp__h119265 == 11'd0 &&
guard__h111304 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h120021 == 11'd2047 &&
_theResult___fst_sfd__h120022 == 52'd0,
1'd0,
_theResult___fst_exp__h119265 != 11'd2047 &&
guard__h111304 != 2'b0 } ;
assign _0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238 =
({ 3'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633 =
({ 3'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ^
9'h100) <=
(IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632 ^
9'h100) ;
assign _0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870 =
{ 3'd0,
_theResult___fst_exp__h78336 == 8'd0 && guard__h70288 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h78889 == 8'd255 &&
_theResult___fst_sfd__h78890 == 23'd0,
1'd0,
_theResult___fst_exp__h78336 != 8'd255 &&
guard__h70288 != 2'b0 } ;
assign _0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152 =
b__h15050 >>
_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 ;
assign _0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318 =
sfd__h53913 >>
_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 ;
assign _1_CONCAT_DONTCARE_CONCAT_requestR_BITS_63_TO_3_ETC___d68 =
{ 33'h1AAAAAAAA,
requestR[63:32] == 32'hFFFFFFFF && requestR[31],
(requestR[63:32] == 32'hFFFFFFFF) ?
requestR[30:0] :
31'h7FC00000 } ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840 =
12'd3074 -
{ 6'd0,
requestR[179] ?
6'd0 :
(requestR[178] ?
6'd1 :
(requestR[177] ?
6'd2 :
(requestR[176] ?
6'd3 :
(requestR[175] ?
6'd4 :
(requestR[174] ?
6'd5 :
(requestR[173] ?
6'd6 :
(requestR[172] ?
6'd7 :
(requestR[171] ?
6'd8 :
(requestR[170] ?
6'd9 :
(requestR[169] ?
6'd10 :
(requestR[168] ?
6'd11 :
(requestR[167] ?
6'd12 :
(requestR[166] ?
6'd13 :
(requestR[165] ?
6'd14 :
(requestR[164] ?
6'd15 :
(requestR[163] ?
6'd16 :
(requestR[162] ?
6'd17 :
(requestR[161] ?
6'd18 :
(requestR[160] ?
6'd19 :
(requestR[159] ?
6'd20 :
(requestR[158] ?
6'd21 :
(requestR[157] ?
6'd22 :
(requestR[156] ?
6'd23 :
(requestR[155] ?
6'd24 :
(requestR[154] ?
6'd25 :
(requestR[153] ?
6'd26 :
(requestR[152] ?
6'd27 :
(requestR[151] ?
6'd28 :
(requestR[150] ?
6'd29 :
(requestR[149] ?
6'd30 :
(requestR[148] ?
6'd31 :
(requestR[147] ?
6'd32 :
(requestR[146] ?
6'd33 :
(requestR[145] ?
6'd34 :
(requestR[144] ?
6'd35 :
(requestR[143] ?
6'd36 :
(requestR[142] ?
6'd37 :
(requestR[141] ?
6'd38 :
(requestR[140] ?
6'd39 :
(requestR[139] ?
6'd40 :
(requestR[138] ?
6'd41 :
(requestR[137] ?
6'd42 :
(requestR[136] ?
6'd43 :
(requestR[135] ?
6'd44 :
(requestR[134] ?
6'd45 :
(requestR[133] ?
6'd46 :
(requestR[132] ?
6'd47 :
(requestR[131] ?
6'd48 :
(requestR[130] ?
6'd49 :
(requestR[129] ?
6'd50 :
(requestR[128] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 =
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 =
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1840 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2873 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 &&
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[4] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[4]) ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2898 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 &&
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[3] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[3]) ;
assign _3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d2925 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 &&
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2858[1] :
_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2870[1]) ;
assign _3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 =
12'd3074 -
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3145 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 =
(12'd32 -
{ 6'd0,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 =
(9'd32 -
{ 3'd0,
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 =
(12'd32 -
{ 6'd0,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 =
(9'd32 -
{ 3'd0,
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 =
(_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 ^
9'h100) <
9'd130 ;
assign _3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002 =
12'd3970 -
{ 7'd0,
sV1_sfd__h816[22] ?
5'd0 :
(sV1_sfd__h816[21] ?
5'd1 :
(sV1_sfd__h816[20] ?
5'd2 :
(sV1_sfd__h816[19] ?
5'd3 :
(sV1_sfd__h816[18] ?
5'd4 :
(sV1_sfd__h816[17] ?
5'd5 :
(sV1_sfd__h816[16] ?
5'd6 :
(sV1_sfd__h816[15] ?
5'd7 :
(sV1_sfd__h816[14] ?
5'd8 :
(sV1_sfd__h816[13] ?
5'd9 :
(sV1_sfd__h816[12] ?
5'd10 :
(sV1_sfd__h816[11] ?
5'd11 :
(sV1_sfd__h816[10] ?
5'd12 :
(sV1_sfd__h816[9] ?
5'd13 :
(sV1_sfd__h816[8] ?
5'd14 :
(sV1_sfd__h816[7] ?
5'd15 :
(sV1_sfd__h816[6] ?
5'd16 :
(sV1_sfd__h816[5] ?
5'd17 :
(sV1_sfd__h816[4] ?
5'd18 :
(sV1_sfd__h816[3] ?
5'd19 :
(sV1_sfd__h816[2] ?
5'd20 :
(sV1_sfd__h816[1] ?
5'd21 :
(sV1_sfd__h816[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 =
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 =
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3002 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 =
12'd3970 -
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_609___d2311 ;
assign _theResult_____2__h14985 =
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d844 ?
out1___1__h15477 :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56:24] ;
assign _theResult_____2__h47542 =
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1635 ?
out1___1__h48034 :
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85:53] ;
assign _theResult____h120602 =
((_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 ^
12'h800) <
12'd2105) ?
result__h121215 :
((value__h15052 == 25'd0) ? b__h15050 : 57'd1) ;
assign _theResult____h61543 =
(value__h47609 == 54'd0) ? sfd__h53913 : 57'd1 ;
assign _theResult____h79267 =
((_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 ^
12'h800) <
12'd2105) ?
result__h79880 :
_theResult____h61543 ;
assign _theResult___exp__h119920 =
sfd__h119283[53] ?
((_theResult___fst_exp__h119265 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h138485) :
((_theResult___fst_exp__h119265 == 11'd0 &&
sfd__h119283[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h119265) ;
assign _theResult___exp__h129567 =
sfd__h128930[53] ?
((_theResult___fst_exp__h128838 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h138515) :
((_theResult___fst_exp__h128838 == 11'd0 &&
sfd__h128930[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h128838) ;
assign _theResult___exp__h13726 =
(sfd__h13330[24] || sfd__h13330[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h138349 =
sfd__h137688[53] ?
((_theResult___fst_exp__h137669 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h138539) :
((_theResult___fst_exp__h137669 == 11'd0 &&
sfd__h137688[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h137669) ;
assign _theResult___exp__h14278 =
sfd__h13869[24] ?
((x__h13854[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h14416) :
((x__h13854[7:0] == 8'd0 && sfd__h13869[24:23] == 2'b01) ?
8'd1 :
x__h13854[7:0]) ;
assign _theResult___exp__h36388 =
(sfd__h35789[53] || sfd__h35789[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h37144 =
sfd__h36532[53] ?
((x__h36517[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h37287) :
((x__h36517[10:0] == 11'd0 && sfd__h36532[53:52] == 2'b01) ?
11'd1 :
x__h36517[10:0]) ;
assign _theResult___exp__h46084 =
(sfd__h45485[53] || sfd__h45485[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h46839 =
sfd__h46227[53] ?
((x__h46212[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h46977) :
((x__h46212[10:0] == 11'd0 && sfd__h46227[53:52] == 2'b01) ?
11'd1 :
x__h46212[10:0]) ;
assign _theResult___exp__h70176 =
sfd__h69742[24] ?
((_theResult___fst_exp__h69650 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96827) :
((_theResult___fst_exp__h69650 == 8'd0 &&
sfd__h69742[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h69650) ;
assign _theResult___exp__h7552 =
(sfd__h7153[24] || sfd__h7153[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h78788 =
sfd__h78354[24] ?
((_theResult___fst_exp__h78336 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96851) :
((_theResult___fst_exp__h78336 == 8'd0 &&
sfd__h78354[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h78336) ;
assign _theResult___exp__h8105 =
sfd__h7696[24] ?
((x__h7681[7:0] == 8'd254) ? 8'd255 : din_inc___2_exp__h8248) :
((x__h7681[7:0] == 8'd0 && sfd__h7696[24:23] == 2'b01) ?
8'd1 :
x__h7681[7:0]) ;
assign _theResult___exp__h88029 =
sfd__h87595[24] ?
((_theResult___fst_exp__h87503 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96881) :
((_theResult___fst_exp__h87503 == 8'd0 &&
sfd__h87595[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h87503) ;
assign _theResult___exp__h96695 =
sfd__h96237[24] ?
((_theResult___fst_exp__h96218 == 8'd254) ?
8'd255 :
din_inc___2_exp__h96905) :
((_theResult___fst_exp__h96218 == 8'd0 &&
sfd__h96237[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h96218) ;
assign _theResult___fst_exp__h104192 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
11'd2047 :
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 ;
assign _theResult___fst_exp__h119256 =
11'd897 -
{ 5'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ;
assign _theResult___fst_exp__h119262 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047 ||
!_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3076) ?
11'd0 :
_theResult___fst_exp__h119256 ;
assign _theResult___fst_exp__h119265 =
(sV1_exp__h815 == 8'd0) ?
_theResult___fst_exp__h119262 :
11'd897 ;
assign _theResult___fst_exp__h120018 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 ;
assign _theResult___fst_exp__h120021 =
(_theResult___fst_exp__h119265 == 11'd2047) ?
_theResult___fst_exp__h119265 :
_theResult___fst_exp__h120018 ;
assign _theResult___fst_exp__h128838 =
_theResult____h120602[56] ?
11'd2 :
_theResult___fst_exp__h128912 ;
assign _theResult___fst_exp__h128903 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 } ;
assign _theResult___fst_exp__h128909 =
(!_theResult____h120602[56] && !_theResult____h120602[55] &&
!_theResult____h120602[54] &&
!_theResult____h120602[53] &&
!_theResult____h120602[52] &&
!_theResult____h120602[51] &&
!_theResult____h120602[50] &&
!_theResult____h120602[49] &&
!_theResult____h120602[48] &&
!_theResult____h120602[47] &&
!_theResult____h120602[46] &&
!_theResult____h120602[45] &&
!_theResult____h120602[44] &&
!_theResult____h120602[43] &&
!_theResult____h120602[42] &&
!_theResult____h120602[41] &&
!_theResult____h120602[40] &&
!_theResult____h120602[39] &&
!_theResult____h120602[38] &&
!_theResult____h120602[37] &&
!_theResult____h120602[36] &&
!_theResult____h120602[35] &&
!_theResult____h120602[34] &&
!_theResult____h120602[33] &&
!_theResult____h120602[32] &&
!_theResult____h120602[31] &&
!_theResult____h120602[30] &&
!_theResult____h120602[29] &&
!_theResult____h120602[28] &&
!_theResult____h120602[27] &&
!_theResult____h120602[26] &&
!_theResult____h120602[25] &&
!_theResult____h120602[24] &&
!_theResult____h120602[23] &&
!_theResult____h120602[22] &&
!_theResult____h120602[21] &&
!_theResult____h120602[20] &&
!_theResult____h120602[19] &&
!_theResult____h120602[18] &&
!_theResult____h120602[17] &&
!_theResult____h120602[16] &&
!_theResult____h120602[15] &&
!_theResult____h120602[14] &&
!_theResult____h120602[13] &&
!_theResult____h120602[12] &&
!_theResult____h120602[11] &&
!_theResult____h120602[10] &&
!_theResult____h120602[9] &&
!_theResult____h120602[8] &&
!_theResult____h120602[7] &&
!_theResult____h120602[6] &&
!_theResult____h120602[5] &&
!_theResult____h120602[4] &&
!_theResult____h120602[3] &&
!_theResult____h120602[2] &&
!_theResult____h120602[1] &&
!_theResult____h120602[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR_BIT_ETC___d3396) ?
11'd0 :
_theResult___fst_exp__h128903 ;
assign _theResult___fst_exp__h128912 =
(!_theResult____h120602[56] && _theResult____h120602[55]) ?
11'd1 :
_theResult___fst_exp__h128909 ;
assign _theResult___fst_exp__h129665 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 ;
assign _theResult___fst_exp__h129668 =
(_theResult___fst_exp__h128838 == 11'd2047) ?
_theResult___fst_exp__h128838 :
_theResult___fst_exp__h129665 ;
assign _theResult___fst_exp__h137621 =
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] ;
assign _theResult___fst_exp__h137660 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC__q96[10:0] -
{ 5'd0,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 } ;
assign _theResult___fst_exp__h137666 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047 ||
!_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d3469) ?
11'd0 :
_theResult___fst_exp__h137660 ;
assign _theResult___fst_exp__h137669 =
(sV1_exp__h815 == 8'd0) ?
_theResult___fst_exp__h137666 :
_theResult___fst_exp__h137621 ;
assign _theResult___fst_exp__h13822 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 ;
assign _theResult___fst_exp__h138447 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 ;
assign _theResult___fst_exp__h138450 =
(_theResult___fst_exp__h137669 == 11'd2047) ?
_theResult___fst_exp__h137669 :
_theResult___fst_exp__h138447 ;
assign _theResult___fst_exp__h138459 =
(sV1_exp__h815 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ?
_theResult___snd_fst_exp__h120024 :
_theResult___fst_exp__h104192) :
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ?
_theResult___snd_fst_exp__h138453 :
_theResult___fst_exp__h104192) ;
assign _theResult___fst_exp__h138462 =
(sV1_exp__h815 == 8'd0 && sV1_sfd__h816 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h138459 ;
assign _theResult___fst_exp__h14374 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 ;
assign _theResult___fst_exp__h14377 =
(x__h13854[7:0] == 8'd255) ?
x__h13854[7:0] :
_theResult___fst_exp__h14374 ;
assign _theResult___fst_exp__h36485 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 ;
assign _theResult___fst_exp__h37241 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 ;
assign _theResult___fst_exp__h37244 =
(x__h36517[10:0] == 11'd2047) ?
x__h36517[10:0] :
_theResult___fst_exp__h37241 ;
assign _theResult___fst_exp__h46180 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 ;
assign _theResult___fst_exp__h46935 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 ;
assign _theResult___fst_exp__h46938 =
(x__h46212[10:0] == 11'd2047) ?
x__h46212[10:0] :
_theResult___fst_exp__h46935 ;
assign _theResult___fst_exp__h61525 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
8'd255 :
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 ;
assign _theResult___fst_exp__h69650 =
_theResult____h61543[56] ? 8'd2 : _theResult___fst_exp__h69724 ;
assign _theResult___fst_exp__h69715 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 } ;
assign _theResult___fst_exp__h69721 =
(!_theResult____h61543[56] && !_theResult____h61543[55] &&
!_theResult____h61543[54] &&
!_theResult____h61543[53] &&
!_theResult____h61543[52] &&
!_theResult____h61543[51] &&
!_theResult____h61543[50] &&
!_theResult____h61543[49] &&
!_theResult____h61543[48] &&
!_theResult____h61543[47] &&
!_theResult____h61543[46] &&
!_theResult____h61543[45] &&
!_theResult____h61543[44] &&
!_theResult____h61543[43] &&
!_theResult____h61543[42] &&
!_theResult____h61543[41] &&
!_theResult____h61543[40] &&
!_theResult____h61543[39] &&
!_theResult____h61543[38] &&
!_theResult____h61543[37] &&
!_theResult____h61543[36] &&
!_theResult____h61543[35] &&
!_theResult____h61543[34] &&
!_theResult____h61543[33] &&
!_theResult____h61543[32] &&
!_theResult____h61543[31] &&
!_theResult____h61543[30] &&
!_theResult____h61543[29] &&
!_theResult____h61543[28] &&
!_theResult____h61543[27] &&
!_theResult____h61543[26] &&
!_theResult____h61543[25] &&
!_theResult____h61543[24] &&
!_theResult____h61543[23] &&
!_theResult____h61543[22] &&
!_theResult____h61543[21] &&
!_theResult____h61543[20] &&
!_theResult____h61543[19] &&
!_theResult____h61543[18] &&
!_theResult____h61543[17] &&
!_theResult____h61543[16] &&
!_theResult____h61543[15] &&
!_theResult____h61543[14] &&
!_theResult____h61543[13] &&
!_theResult____h61543[12] &&
!_theResult____h61543[11] &&
!_theResult____h61543[10] &&
!_theResult____h61543[9] &&
!_theResult____h61543[8] &&
!_theResult____h61543[7] &&
!_theResult____h61543[6] &&
!_theResult____h61543[5] &&
!_theResult____h61543[4] &&
!_theResult____h61543[3] &&
!_theResult____h61543[2] &&
!_theResult____h61543[1] &&
!_theResult____h61543[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_19_ETC___d2076) ?
8'd0 :
_theResult___fst_exp__h69715 ;
assign _theResult___fst_exp__h69724 =
(!_theResult____h61543[56] && _theResult____h61543[55]) ?
8'd1 :
_theResult___fst_exp__h69721 ;
assign _theResult___fst_exp__h70274 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 ;
assign _theResult___fst_exp__h70277 =
(_theResult___fst_exp__h69650 == 8'd255) ?
_theResult___fst_exp__h69650 :
_theResult___fst_exp__h70274 ;
assign _theResult___fst_exp__h7649 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 ;
assign _theResult___fst_exp__h78327 =
8'd129 -
{ 2'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ;
assign _theResult___fst_exp__h78333 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181 ||
!_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2238) ?
8'd0 :
_theResult___fst_exp__h78327 ;
assign _theResult___fst_exp__h78336 =
(requestR[190:180] == 11'd0) ?
_theResult___fst_exp__h78333 :
8'd129 ;
assign _theResult___fst_exp__h78886 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 ;
assign _theResult___fst_exp__h78889 =
(_theResult___fst_exp__h78336 == 8'd255) ?
_theResult___fst_exp__h78336 :
_theResult___fst_exp__h78886 ;
assign _theResult___fst_exp__h8202 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 ;
assign _theResult___fst_exp__h8205 =
(x__h7681[7:0] == 8'd255) ?
x__h7681[7:0] :
_theResult___fst_exp__h8202 ;
assign _theResult___fst_exp__h87503 =
_theResult____h79267[56] ? 8'd2 : _theResult___fst_exp__h87577 ;
assign _theResult___fst_exp__h87568 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 } ;
assign _theResult___fst_exp__h87574 =
(!_theResult____h79267[56] && !_theResult____h79267[55] &&
!_theResult____h79267[54] &&
!_theResult____h79267[53] &&
!_theResult____h79267[52] &&
!_theResult____h79267[51] &&
!_theResult____h79267[50] &&
!_theResult____h79267[49] &&
!_theResult____h79267[48] &&
!_theResult____h79267[47] &&
!_theResult____h79267[46] &&
!_theResult____h79267[45] &&
!_theResult____h79267[44] &&
!_theResult____h79267[43] &&
!_theResult____h79267[42] &&
!_theResult____h79267[41] &&
!_theResult____h79267[40] &&
!_theResult____h79267[39] &&
!_theResult____h79267[38] &&
!_theResult____h79267[37] &&
!_theResult____h79267[36] &&
!_theResult____h79267[35] &&
!_theResult____h79267[34] &&
!_theResult____h79267[33] &&
!_theResult____h79267[32] &&
!_theResult____h79267[31] &&
!_theResult____h79267[30] &&
!_theResult____h79267[29] &&
!_theResult____h79267[28] &&
!_theResult____h79267[27] &&
!_theResult____h79267[26] &&
!_theResult____h79267[25] &&
!_theResult____h79267[24] &&
!_theResult____h79267[23] &&
!_theResult____h79267[22] &&
!_theResult____h79267[21] &&
!_theResult____h79267[20] &&
!_theResult____h79267[19] &&
!_theResult____h79267[18] &&
!_theResult____h79267[17] &&
!_theResult____h79267[16] &&
!_theResult____h79267[15] &&
!_theResult____h79267[14] &&
!_theResult____h79267[13] &&
!_theResult____h79267[12] &&
!_theResult____h79267[11] &&
!_theResult____h79267[10] &&
!_theResult____h79267[9] &&
!_theResult____h79267[8] &&
!_theResult____h79267[7] &&
!_theResult____h79267[6] &&
!_theResult____h79267[5] &&
!_theResult____h79267[4] &&
!_theResult____h79267[3] &&
!_theResult____h79267[2] &&
!_theResult____h79267[1] &&
!_theResult____h79267[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BITS_1_ETC___d2560) ?
8'd0 :
_theResult___fst_exp__h87568 ;
assign _theResult___fst_exp__h87577 =
(!_theResult____h79267[56] && _theResult____h79267[55]) ?
8'd1 :
_theResult___fst_exp__h87574 ;
assign _theResult___fst_exp__h88127 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 ;
assign _theResult___fst_exp__h88130 =
(_theResult___fst_exp__h87503 == 8'd255) ?
_theResult___fst_exp__h87503 :
_theResult___fst_exp__h88127 ;
assign _theResult___fst_exp__h96170 =
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] ==
8'd0) ?
8'd1 :
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] ;
assign _theResult___fst_exp__h96209 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC__q64[7:0] -
{ 2'd0,
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 } ;
assign _theResult___fst_exp__h96215 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181 ||
!_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_0__ETC___d2633) ?
8'd0 :
_theResult___fst_exp__h96209 ;
assign _theResult___fst_exp__h96218 =
(requestR[190:180] == 11'd0) ?
_theResult___fst_exp__h96215 :
_theResult___fst_exp__h96170 ;
assign _theResult___fst_exp__h96793 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 ;
assign _theResult___fst_exp__h96796 =
(_theResult___fst_exp__h96218 == 8'd255) ?
_theResult___fst_exp__h96218 :
_theResult___fst_exp__h96793 ;
assign _theResult___fst_exp__h96805 =
(requestR[190:180] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ?
_theResult___snd_fst_exp__h78892 :
_theResult___fst_exp__h61525) :
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ?
_theResult___snd_fst_exp__h96799 :
_theResult___fst_exp__h61525) ;
assign _theResult___fst_exp__h96808 =
(requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0) ?
8'd0 :
_theResult___fst_exp__h96805 ;
assign _theResult___fst_sfd__h104193 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
52'd0 :
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 ;
assign _theResult___fst_sfd__h120019 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 ;
assign _theResult___fst_sfd__h120022 =
(_theResult___fst_exp__h119265 == 11'd2047) ?
_theResult___snd__h119216[56:5] :
_theResult___fst_sfd__h120019 ;
assign _theResult___fst_sfd__h129666 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 ;
assign _theResult___fst_sfd__h129669 =
(_theResult___fst_exp__h128838 == 11'd2047) ?
sfdin__h128832[56:5] :
_theResult___fst_sfd__h129666 ;
assign _theResult___fst_sfd__h13823 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 ;
assign _theResult___fst_sfd__h138448 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 ;
assign _theResult___fst_sfd__h138451 =
(_theResult___fst_exp__h137669 == 11'd2047) ?
_theResult___snd__h137615[56:5] :
_theResult___fst_sfd__h138448 ;
assign _theResult___fst_sfd__h138460 =
(sV1_exp__h815 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3003 ?
_theResult___snd_fst_sfd__h120025 :
_theResult___fst_sfd__h104193) :
(SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3146 ?
_theResult___snd_fst_sfd__h138454 :
_theResult___fst_sfd__h104193) ;
assign _theResult___fst_sfd__h138466 =
((sV1_exp__h815 == 8'd255 || sV1_exp__h815 == 8'd0) &&
sV1_sfd__h816 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h138460 ;
assign _theResult___fst_sfd__h14375 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 ;
assign _theResult___fst_sfd__h14378 =
(x__h13854[7:0] == 8'd255) ?
sfd___3__h13303[30:8] :
_theResult___fst_sfd__h14375 ;
assign _theResult___fst_sfd__h36486 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 ;
assign _theResult___fst_sfd__h37242 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 ;
assign _theResult___fst_sfd__h37245 =
(x__h36517[10:0] == 11'd2047) ?
sfd___3__h35762[53:2] :
_theResult___fst_sfd__h37242 ;
assign _theResult___fst_sfd__h46181 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 ;
assign _theResult___fst_sfd__h46936 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 ;
assign _theResult___fst_sfd__h46939 =
(x__h46212[10:0] == 11'd2047) ?
sfd___3__h45458[53:2] :
_theResult___fst_sfd__h46936 ;
assign _theResult___fst_sfd__h50209 = { 1'd1, requestR[178:128] } ;
assign _theResult___fst_sfd__h61526 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
23'd0 :
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 ;
assign _theResult___fst_sfd__h70275 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 ;
assign _theResult___fst_sfd__h70278 =
(_theResult___fst_exp__h69650 == 8'd255) ?
sfdin__h69644[56:34] :
_theResult___fst_sfd__h70275 ;
assign _theResult___fst_sfd__h7650 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 ;
assign _theResult___fst_sfd__h78887 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 ;
assign _theResult___fst_sfd__h78890 =
(_theResult___fst_exp__h78336 == 8'd255) ?
_theResult___snd__h78287[56:34] :
_theResult___fst_sfd__h78887 ;
assign _theResult___fst_sfd__h8203 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 ;
assign _theResult___fst_sfd__h8206 =
(x__h7681[7:0] == 8'd255) ?
sfd___3__h7126[30:8] :
_theResult___fst_sfd__h8203 ;
assign _theResult___fst_sfd__h88128 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 ;
assign _theResult___fst_sfd__h88131 =
(_theResult___fst_exp__h87503 == 8'd255) ?
sfdin__h87497[56:34] :
_theResult___fst_sfd__h88128 ;
assign _theResult___fst_sfd__h96794 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 :
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 ;
assign _theResult___fst_sfd__h96797 =
(_theResult___fst_exp__h96218 == 8'd255) ?
_theResult___snd__h96164[56:34] :
_theResult___fst_sfd__h96794 ;
assign _theResult___fst_sfd__h96806 =
(requestR[190:180] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1841 ?
_theResult___snd_fst_sfd__h78893 :
_theResult___fst_sfd__h61526) :
(SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2312 ?
_theResult___snd_fst_sfd__h96800 :
_theResult___fst_sfd__h61526) ;
assign _theResult___fst_sfd__h96812 =
((requestR[190:180] == 11'd2047 || requestR[190:180] == 11'd0) &&
requestR[179:128] == 52'd0) ?
23'd0 :
_theResult___fst_sfd__h96806 ;
assign _theResult___fst_sfd__h98711 = { 1'd1, sV1_sfd__h816[21:0] } ;
assign _theResult___sfd__h119921 =
sfd__h119283[53] ?
((_theResult___fst_exp__h119265 == 11'd2046) ?
52'd0 :
sfd__h119283[52:1]) :
sfd__h119283[51:0] ;
assign _theResult___sfd__h129568 =
sfd__h128930[53] ?
((_theResult___fst_exp__h128838 == 11'd2046) ?
52'd0 :
sfd__h128930[52:1]) :
sfd__h128930[51:0] ;
assign _theResult___sfd__h13727 =
sfd__h13330[24] ? sfd__h13330[23:1] : sfd__h13330[22:0] ;
assign _theResult___sfd__h138350 =
sfd__h137688[53] ?
((_theResult___fst_exp__h137669 == 11'd2046) ?
52'd0 :
sfd__h137688[52:1]) :
sfd__h137688[51:0] ;
assign _theResult___sfd__h14279 =
sfd__h13869[24] ?
((x__h13854[7:0] == 8'd254) ? 23'd0 : sfd__h13869[23:1]) :
sfd__h13869[22:0] ;
assign _theResult___sfd__h36389 =
sfd__h35789[53] ? sfd__h35789[52:1] : sfd__h35789[51:0] ;
assign _theResult___sfd__h37145 =
sfd__h36532[53] ?
((x__h36517[10:0] == 11'd2046) ? 52'd0 : sfd__h36532[52:1]) :
sfd__h36532[51:0] ;
assign _theResult___sfd__h46085 =
sfd__h45485[53] ? sfd__h45485[52:1] : sfd__h45485[51:0] ;
assign _theResult___sfd__h46840 =
sfd__h46227[53] ?
((x__h46212[10:0] == 11'd2046) ? 52'd0 : sfd__h46227[52:1]) :
sfd__h46227[51:0] ;
assign _theResult___sfd__h70177 =
sfd__h69742[24] ?
((_theResult___fst_exp__h69650 == 8'd254) ?
23'd0 :
sfd__h69742[23:1]) :
sfd__h69742[22:0] ;
assign _theResult___sfd__h7553 =
sfd__h7153[24] ? sfd__h7153[23:1] : sfd__h7153[22:0] ;
assign _theResult___sfd__h78789 =
sfd__h78354[24] ?
((_theResult___fst_exp__h78336 == 8'd254) ?
23'd0 :
sfd__h78354[23:1]) :
sfd__h78354[22:0] ;
assign _theResult___sfd__h8106 =
sfd__h7696[24] ?
((x__h7681[7:0] == 8'd254) ? 23'd0 : sfd__h7696[23:1]) :
sfd__h7696[22:0] ;
assign _theResult___sfd__h88030 =
sfd__h87595[24] ?
((_theResult___fst_exp__h87503 == 8'd254) ?
23'd0 :
sfd__h87595[23:1]) :
sfd__h87595[22:0] ;
assign _theResult___sfd__h96696 =
sfd__h96237[24] ?
((_theResult___fst_exp__h96218 == 8'd254) ?
23'd0 :
sfd__h96237[23:1]) :
sfd__h96237[22:0] ;
assign _theResult___snd__h119216 =
(sV1_exp__h815 == 8'd0) ?
_theResult___snd__h119225 :
_theResult___snd__h119218 ;
assign _theResult___snd__h119218 = { sV1_sfd__h816, 34'd0 } ;
assign _theResult___snd__h119225 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047) ?
b__h15050 :
_theResult___snd__h119231 ;
assign _theResult___snd__h119231 =
{ IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q94[54:0],
2'd0 } ;
assign _theResult___snd__h119254 =
b__h15050 <<
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3074 ;
assign _theResult___snd__h128849 = { _theResult____h120602[55:0], 1'd0 } ;
assign _theResult___snd__h128860 =
(!_theResult____h120602[56] && _theResult____h120602[55]) ?
_theResult___snd__h128862 :
_theResult___snd__h128872 ;
assign _theResult___snd__h128862 = { _theResult____h120602[54:0], 2'd0 } ;
assign _theResult___snd__h128872 =
(!_theResult____h120602[56] && !_theResult____h120602[55] &&
!_theResult____h120602[54] &&
!_theResult____h120602[53] &&
!_theResult____h120602[52] &&
!_theResult____h120602[51] &&
!_theResult____h120602[50] &&
!_theResult____h120602[49] &&
!_theResult____h120602[48] &&
!_theResult____h120602[47] &&
!_theResult____h120602[46] &&
!_theResult____h120602[45] &&
!_theResult____h120602[44] &&
!_theResult____h120602[43] &&
!_theResult____h120602[42] &&
!_theResult____h120602[41] &&
!_theResult____h120602[40] &&
!_theResult____h120602[39] &&
!_theResult____h120602[38] &&
!_theResult____h120602[37] &&
!_theResult____h120602[36] &&
!_theResult____h120602[35] &&
!_theResult____h120602[34] &&
!_theResult____h120602[33] &&
!_theResult____h120602[32] &&
!_theResult____h120602[31] &&
!_theResult____h120602[30] &&
!_theResult____h120602[29] &&
!_theResult____h120602[28] &&
!_theResult____h120602[27] &&
!_theResult____h120602[26] &&
!_theResult____h120602[25] &&
!_theResult____h120602[24] &&
!_theResult____h120602[23] &&
!_theResult____h120602[22] &&
!_theResult____h120602[21] &&
!_theResult____h120602[20] &&
!_theResult____h120602[19] &&
!_theResult____h120602[18] &&
!_theResult____h120602[17] &&
!_theResult____h120602[16] &&
!_theResult____h120602[15] &&
!_theResult____h120602[14] &&
!_theResult____h120602[13] &&
!_theResult____h120602[12] &&
!_theResult____h120602[11] &&
!_theResult____h120602[10] &&
!_theResult____h120602[9] &&
!_theResult____h120602[8] &&
!_theResult____h120602[7] &&
!_theResult____h120602[6] &&
!_theResult____h120602[5] &&
!_theResult____h120602[4] &&
!_theResult____h120602[3] &&
!_theResult____h120602[2] &&
!_theResult____h120602[1] &&
!_theResult____h120602[0]) ?
_theResult____h120602 :
_theResult___snd__h128878 ;
assign _theResult___snd__h128878 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_requestR__ETC__q97[54:0],
2'd0 } ;
assign _theResult___snd__h128901 =
_theResult____h120602 <<
IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_191_TO__ETC___d3394 ;
assign _theResult___snd__h137615 =
(sV1_exp__h815 == 8'd0) ?
_theResult___snd__h137629 :
_theResult___snd__h119218 ;
assign _theResult___snd__h137629 =
(sV1_exp__h815 == 8'd0 && !sV1_sfd__h816[22] &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d3047) ?
b__h15050 :
_theResult___snd__h137635 ;
assign _theResult___snd__h137635 =
{ IF_0_CONCAT_IF_IF_requestR_BITS_191_TO_160_4_E_ETC__q100[54:0],
2'd0 } ;
assign _theResult___snd__h137653 =
b__h15050 <<
IF_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFF_ETC___d3468 ;
assign _theResult___snd__h69661 = { _theResult____h61543[55:0], 1'd0 } ;
assign _theResult___snd__h69672 =
(!_theResult____h61543[56] && _theResult____h61543[55]) ?
_theResult___snd__h69674 :
_theResult___snd__h69684 ;
assign _theResult___snd__h69674 = { _theResult____h61543[54:0], 2'd0 } ;
assign _theResult___snd__h69684 =
(!_theResult____h61543[56] && !_theResult____h61543[55] &&
!_theResult____h61543[54] &&
!_theResult____h61543[53] &&
!_theResult____h61543[52] &&
!_theResult____h61543[51] &&
!_theResult____h61543[50] &&
!_theResult____h61543[49] &&
!_theResult____h61543[48] &&
!_theResult____h61543[47] &&
!_theResult____h61543[46] &&
!_theResult____h61543[45] &&
!_theResult____h61543[44] &&
!_theResult____h61543[43] &&
!_theResult____h61543[42] &&
!_theResult____h61543[41] &&
!_theResult____h61543[40] &&
!_theResult____h61543[39] &&
!_theResult____h61543[38] &&
!_theResult____h61543[37] &&
!_theResult____h61543[36] &&
!_theResult____h61543[35] &&
!_theResult____h61543[34] &&
!_theResult____h61543[33] &&
!_theResult____h61543[32] &&
!_theResult____h61543[31] &&
!_theResult____h61543[30] &&
!_theResult____h61543[29] &&
!_theResult____h61543[28] &&
!_theResult____h61543[27] &&
!_theResult____h61543[26] &&
!_theResult____h61543[25] &&
!_theResult____h61543[24] &&
!_theResult____h61543[23] &&
!_theResult____h61543[22] &&
!_theResult____h61543[21] &&
!_theResult____h61543[20] &&
!_theResult____h61543[19] &&
!_theResult____h61543[18] &&
!_theResult____h61543[17] &&
!_theResult____h61543[16] &&
!_theResult____h61543[15] &&
!_theResult____h61543[14] &&
!_theResult____h61543[13] &&
!_theResult____h61543[12] &&
!_theResult____h61543[11] &&
!_theResult____h61543[10] &&
!_theResult____h61543[9] &&
!_theResult____h61543[8] &&
!_theResult____h61543[7] &&
!_theResult____h61543[6] &&
!_theResult____h61543[5] &&
!_theResult____h61543[4] &&
!_theResult____h61543[3] &&
!_theResult____h61543[2] &&
!_theResult____h61543[1] &&
!_theResult____h61543[0]) ?
_theResult____h61543 :
_theResult___snd__h69690 ;
assign _theResult___snd__h69690 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_requestR_BITS_ETC__q60[54:0],
2'd0 } ;
assign _theResult___snd__h69713 =
_theResult____h61543 <<
IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_TO_180__ETC___d2074 ;
assign _theResult___snd__h78287 =
(requestR[190:180] == 11'd0) ?
_theResult___snd__h78296 :
_theResult___snd__h78289 ;
assign _theResult___snd__h78289 = { requestR[179:128], 5'd0 } ;
assign _theResult___snd__h78296 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181) ?
sfd__h53913 :
_theResult___snd__h78302 ;
assign _theResult___snd__h78302 =
{ IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q62[54:0],
2'd0 } ;
assign _theResult___snd__h78325 =
sfd__h53913 <<
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2236 ;
assign _theResult___snd__h87514 = { _theResult____h79267[55:0], 1'd0 } ;
assign _theResult___snd__h87525 =
(!_theResult____h79267[56] && _theResult____h79267[55]) ?
_theResult___snd__h87527 :
_theResult___snd__h87537 ;
assign _theResult___snd__h87527 = { _theResult____h79267[54:0], 2'd0 } ;
assign _theResult___snd__h87537 =
(!_theResult____h79267[56] && !_theResult____h79267[55] &&
!_theResult____h79267[54] &&
!_theResult____h79267[53] &&
!_theResult____h79267[52] &&
!_theResult____h79267[51] &&
!_theResult____h79267[50] &&
!_theResult____h79267[49] &&
!_theResult____h79267[48] &&
!_theResult____h79267[47] &&
!_theResult____h79267[46] &&
!_theResult____h79267[45] &&
!_theResult____h79267[44] &&
!_theResult____h79267[43] &&
!_theResult____h79267[42] &&
!_theResult____h79267[41] &&
!_theResult____h79267[40] &&
!_theResult____h79267[39] &&
!_theResult____h79267[38] &&
!_theResult____h79267[37] &&
!_theResult____h79267[36] &&
!_theResult____h79267[35] &&
!_theResult____h79267[34] &&
!_theResult____h79267[33] &&
!_theResult____h79267[32] &&
!_theResult____h79267[31] &&
!_theResult____h79267[30] &&
!_theResult____h79267[29] &&
!_theResult____h79267[28] &&
!_theResult____h79267[27] &&
!_theResult____h79267[26] &&
!_theResult____h79267[25] &&
!_theResult____h79267[24] &&
!_theResult____h79267[23] &&
!_theResult____h79267[22] &&
!_theResult____h79267[21] &&
!_theResult____h79267[20] &&
!_theResult____h79267[19] &&
!_theResult____h79267[18] &&
!_theResult____h79267[17] &&
!_theResult____h79267[16] &&
!_theResult____h79267[15] &&
!_theResult____h79267[14] &&
!_theResult____h79267[13] &&
!_theResult____h79267[12] &&
!_theResult____h79267[11] &&
!_theResult____h79267[10] &&
!_theResult____h79267[9] &&
!_theResult____h79267[8] &&
!_theResult____h79267[7] &&
!_theResult____h79267[6] &&
!_theResult____h79267[5] &&
!_theResult____h79267[4] &&
!_theResult____h79267[3] &&
!_theResult____h79267[2] &&
!_theResult____h79267[1] &&
!_theResult____h79267[0]) ?
_theResult____h79267 :
_theResult___snd__h87543 ;
assign _theResult___snd__h87543 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_requestR_BIT_ETC__q65[54:0],
2'd0 } ;
assign _theResult___snd__h87566 =
_theResult____h79267 <<
IF_IF_3970_MINUS_SEXT_requestR_BITS_190_TO_180_ETC___d2558 ;
assign _theResult___snd__h96164 =
(requestR[190:180] == 11'd0) ?
_theResult___snd__h96178 :
_theResult___snd__h78289 ;
assign _theResult___snd__h96178 =
(requestR[190:180] == 11'd0 &&
NOT_requestR_BIT_179_767_142_AND_NOT_requestR__ETC___d2181) ?
sfd__h53913 :
_theResult___snd__h96184 ;
assign _theResult___snd__h96184 =
{ IF_0_CONCAT_IF_requestR_BITS_190_TO_180_596_EQ_ETC__q68[54:0],
2'd0 } ;
assign _theResult___snd__h96202 =
sfd__h53913 <<
IF_SEXT_requestR_BITS_190_TO_180_596_MINUS_102_ETC___d2632 ;
assign _theResult___snd_fst_exp__h120024 =
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ?
11'd0 :
_theResult___fst_exp__h120021 ;
assign _theResult___snd_fst_exp__h138453 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_theResult___fst_exp__h129668 :
_theResult___fst_exp__h138450 ;
assign _theResult___snd_fst_exp__h14380 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 ?
_theResult___fst_exp__h13822 :
_theResult___fst_exp__h14377 ;
assign _theResult___snd_fst_exp__h14383 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 ?
8'd0 :
_theResult___snd_fst_exp__h14380 ;
assign _theResult___snd_fst_exp__h14386 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 ?
_theResult___snd_fst_exp__h14383 :
8'd255 ;
assign _theResult___snd_fst_exp__h37247 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
_theResult___fst_exp__h36485 :
_theResult___fst_exp__h37244 ;
assign _theResult___snd_fst_exp__h37250 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 ?
11'd0 :
_theResult___snd_fst_exp__h37247 ;
assign _theResult___snd_fst_exp__h37253 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ?
_theResult___snd_fst_exp__h37250 :
11'd2047 ;
assign _theResult___snd_fst_exp__h46941 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 ?
_theResult___fst_exp__h46180 :
_theResult___fst_exp__h46938 ;
assign _theResult___snd_fst_exp__h46944 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 ?
11'd0 :
_theResult___snd_fst_exp__h46941 ;
assign _theResult___snd_fst_exp__h46947 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 ?
_theResult___snd_fst_exp__h46944 :
11'd2047 ;
assign _theResult___snd_fst_exp__h78892 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_theResult___fst_exp__h70277 :
_theResult___fst_exp__h78889 ;
assign _theResult___snd_fst_exp__h8208 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
_theResult___fst_exp__h7649 :
_theResult___fst_exp__h8205 ;
assign _theResult___snd_fst_exp__h8211 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d261 ?
8'd0 :
_theResult___snd_fst_exp__h8208 ;
assign _theResult___snd_fst_exp__h8214 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d259 ?
_theResult___snd_fst_exp__h8211 :
8'd255 ;
assign _theResult___snd_fst_exp__h96799 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_theResult___fst_exp__h88130 :
_theResult___fst_exp__h96796 ;
assign _theResult___snd_fst_sfd__h100339 =
(value__h98456 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h98453 ;
assign _theResult___snd_fst_sfd__h120025 =
_3970_MINUS_0_CONCAT_IF_IF_requestR_BITS_191_TO_ETC___d3004 ?
52'd0 :
_theResult___fst_sfd__h120022 ;
assign _theResult___snd_fst_sfd__h138454 =
SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFF_ETC___d3147 ?
_theResult___fst_sfd__h129669 :
_theResult___fst_sfd__h138451 ;
assign _theResult___snd_fst_sfd__h14381 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d619 ?
_theResult___fst_sfd__h13823 :
_theResult___fst_sfd__h14378 ;
assign _theResult___snd_fst_sfd__h37248 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 ?
_theResult___fst_sfd__h36486 :
_theResult___fst_sfd__h37245 ;
assign _theResult___snd_fst_sfd__h46942 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 ?
_theResult___fst_sfd__h46181 :
_theResult___fst_sfd__h46939 ;
assign _theResult___snd_fst_sfd__h53867 =
(value__h49752[51:29] == 23'd0) ?
23'd2097152 :
value__h49752[51:29] ;
assign _theResult___snd_fst_sfd__h78893 =
_3074_MINUS_0_CONCAT_IF_requestR_BIT_179_767_TH_ETC___d1842 ?
_theResult___fst_sfd__h70278 :
_theResult___fst_sfd__h78890 ;
assign _theResult___snd_fst_sfd__h8209 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d264 ?
_theResult___fst_sfd__h7650 :
_theResult___fst_sfd__h8206 ;
assign _theResult___snd_fst_sfd__h96800 =
SEXT_requestR_BITS_190_TO_180_596_MINUS_1023_6_ETC___d2313 ?
_theResult___fst_sfd__h88131 :
_theResult___fst_sfd__h96797 ;
assign ab__h156914 = dw_result$wget ;
assign b__h15050 = { value__h15052, 32'd0 } ;
assign b__h47607 = { value__h47609, 32'd0 } ;
assign din_inc___2_exp__h138485 = _theResult___fst_exp__h119265 + 11'd1 ;
assign din_inc___2_exp__h138515 = _theResult___fst_exp__h128838 + 11'd1 ;
assign din_inc___2_exp__h138539 = _theResult___fst_exp__h137669 + 11'd1 ;
assign din_inc___2_exp__h14416 = x__h13854[7:0] + 8'd1 ;
assign din_inc___2_exp__h37287 = x__h36517[10:0] + 11'd1 ;
assign din_inc___2_exp__h46977 = x__h46212[10:0] + 11'd1 ;
assign din_inc___2_exp__h8248 = x__h7681[7:0] + 8'd1 ;
assign din_inc___2_exp__h96827 = _theResult___fst_exp__h69650 + 8'd1 ;
assign din_inc___2_exp__h96851 = _theResult___fst_exp__h78336 + 8'd1 ;
assign din_inc___2_exp__h96881 = _theResult___fst_exp__h87503 + 8'd1 ;
assign din_inc___2_exp__h96905 = _theResult___fst_exp__h96218 + 8'd1 ;
assign guard__h111304 =
{ IF_theResult___snd19216_BIT_4_THEN_2_ELSE_0__q95[1],
{ _theResult___snd__h119216[3:0], 52'd0 } != 56'd0 } ;
assign guard__h120612 =
{ IF_sfdin28832_BIT_4_THEN_2_ELSE_0__q98[1],
{ sfdin__h128832[3:0], 52'd0 } != 56'd0 } ;
assign guard__h121210 = x__h121310 != 57'd0 ;
assign guard__h129679 =
{ IF_theResult___snd37615_BIT_4_THEN_2_ELSE_0__q101[1],
{ _theResult___snd__h137615[3:0], 52'd0 } != 56'd0 } ;
assign guard__h13313 =
{ IF_sfd___33303_BIT_8_THEN_2_ELSE_0__q20[1],
{ sfd___3__h13303[7:0], 23'd0 } != 31'd0 } ;
assign guard__h13839 =
{ IF_sfd___33303_BIT_7_THEN_2_ELSE_0__q21[1],
{ sfd___3__h13303[6:0], 24'd0 } != 31'd0 } ;
assign guard__h14983 =
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[23],
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[22:0],
33'd0 } !=
56'd0 } ;
assign guard__h15537 =
{ IF_x5726_BIT_24_THEN_2_ELSE_0__q31[1],
{ x__h15726[23:0], 32'd0 } != 56'd0 } ;
assign guard__h16600 =
{ IF_x6821_BIT_24_THEN_2_ELSE_0__q32[1],
{ x__h16821[23:0], 32'd0 } != 56'd0 } ;
assign guard__h35772 =
{ IF_sfd___35762_BIT_2_THEN_2_ELSE_0__q33[1],
{ sfd___3__h35762[1:0], 52'd0 } != 54'd0 } ;
assign guard__h36502 =
{ IF_sfd___35762_BIT_1_THEN_2_ELSE_0__q34[1],
{ sfd___3__h35762[0], 53'd0 } != 54'd0 } ;
assign guard__h45468 =
{ IF_sfd___35458_BIT_2_THEN_2_ELSE_0__q47[1],
{ sfd___3__h45458[1:0], 52'd0 } != 54'd0 } ;
assign guard__h46197 =
{ IF_sfd___35458_BIT_1_THEN_2_ELSE_0__q48[1],
{ sfd___3__h45458[0], 53'd0 } != 54'd0 } ;
assign guard__h47540 =
{ IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[52],
{ IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[51:0],
33'd0 } !=
85'd0 } ;
assign guard__h48094 =
{ IF_x8283_BIT_53_THEN_2_ELSE_0__q58[1],
{ x__h48283[52:0], 32'd0 } != 85'd0 } ;
assign guard__h49140 =
{ IF_x9361_BIT_53_THEN_2_ELSE_0__q59[1],
{ x__h49361[52:0], 32'd0 } != 85'd0 } ;
assign guard__h61553 =
{ IF_sfdin9644_BIT_33_THEN_2_ELSE_0__q61[1],
{ sfdin__h69644[32:0], 23'd0 } != 56'd0 } ;
assign guard__h70288 =
{ IF_theResult___snd8287_BIT_33_THEN_2_ELSE_0__q63[1],
{ _theResult___snd__h78287[32:0], 23'd0 } != 56'd0 } ;
assign guard__h7136 =
{ IF_sfd___3126_BIT_8_THEN_2_ELSE_0__q6[1],
{ sfd___3__h7126[7:0], 23'd0 } != 31'd0 } ;
assign guard__h7666 =
{ IF_sfd___3126_BIT_7_THEN_2_ELSE_0__q7[1],
{ sfd___3__h7126[6:0], 24'd0 } != 31'd0 } ;
assign guard__h79277 =
{ IF_sfdin7497_BIT_33_THEN_2_ELSE_0__q66[1],
{ sfdin__h87497[32:0], 23'd0 } != 56'd0 } ;
assign guard__h79875 = x__h79975 != 57'd0 ;
assign guard__h88141 =
{ IF_theResult___snd6164_BIT_33_THEN_2_ELSE_0__q69[1],
{ _theResult___snd__h96164[32:0], 23'd0 } != 56'd0 } ;
assign out1___1__h15477 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56:24] +
33'd1 ;
assign out1___1__h48034 =
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85:53] +
33'd1 ;
assign out___1_sfd__h98453 = { value__h98456, 29'd0 } ;
assign out_exp__h119923 =
_theResult___snd__h119216[5] ?
_theResult___exp__h119920 :
_theResult___fst_exp__h119265 ;
assign out_exp__h129570 =
sfdin__h128832[5] ?
_theResult___exp__h129567 :
_theResult___fst_exp__h128838 ;
assign out_exp__h13729 =
sfd___3__h13303[9] ? _theResult___exp__h13726 : 8'd0 ;
assign out_exp__h138352 =
_theResult___snd__h137615[5] ?
_theResult___exp__h138349 :
_theResult___fst_exp__h137669 ;
assign out_exp__h14281 =
sfd___3__h13303[8] ? _theResult___exp__h14278 : x__h13854[7:0] ;
assign out_exp__h36391 =
sfd___3__h35762[3] ? _theResult___exp__h36388 : 11'd0 ;
assign out_exp__h37147 =
sfd___3__h35762[2] ? _theResult___exp__h37144 : x__h36517[10:0] ;
assign out_exp__h46087 =
sfd___3__h45458[3] ? _theResult___exp__h46084 : 11'd0 ;
assign out_exp__h46842 =
sfd___3__h45458[2] ? _theResult___exp__h46839 : x__h46212[10:0] ;
assign out_exp__h70179 =
sfdin__h69644[34] ?
_theResult___exp__h70176 :
_theResult___fst_exp__h69650 ;
assign out_exp__h7555 = sfd___3__h7126[9] ? _theResult___exp__h7552 : 8'd0 ;
assign out_exp__h78791 =
_theResult___snd__h78287[34] ?
_theResult___exp__h78788 :
_theResult___fst_exp__h78336 ;
assign out_exp__h8108 =
sfd___3__h7126[8] ? _theResult___exp__h8105 : x__h7681[7:0] ;
assign out_exp__h88032 =
sfdin__h87497[34] ?
_theResult___exp__h88029 :
_theResult___fst_exp__h87503 ;
assign out_exp__h96698 =
_theResult___snd__h96164[34] ?
_theResult___exp__h96695 :
_theResult___fst_exp__h96218 ;
assign out_sfd__h119924 =
_theResult___snd__h119216[5] ?
_theResult___sfd__h119921 :
_theResult___snd__h119216[56:5] ;
assign out_sfd__h129571 =
sfdin__h128832[5] ?
_theResult___sfd__h129568 :
sfdin__h128832[56:5] ;
assign out_sfd__h13730 =
sfd___3__h13303[9] ?
_theResult___sfd__h13727 :
sfd___3__h13303[31:9] ;
assign out_sfd__h138353 =
_theResult___snd__h137615[5] ?
_theResult___sfd__h138350 :
_theResult___snd__h137615[56:5] ;
assign out_sfd__h14282 =
sfd___3__h13303[8] ?
_theResult___sfd__h14279 :
sfd___3__h13303[30:8] ;
assign out_sfd__h36392 =
sfd___3__h35762[3] ?
_theResult___sfd__h36389 :
sfd___3__h35762[54:3] ;
assign out_sfd__h37148 =
sfd___3__h35762[2] ?
_theResult___sfd__h37145 :
sfd___3__h35762[53:2] ;
assign out_sfd__h46088 =
sfd___3__h45458[3] ?
_theResult___sfd__h46085 :
sfd___3__h45458[54:3] ;
assign out_sfd__h46843 =
sfd___3__h45458[2] ?
_theResult___sfd__h46840 :
sfd___3__h45458[53:2] ;
assign out_sfd__h70180 =
sfdin__h69644[34] ?
_theResult___sfd__h70177 :
sfdin__h69644[56:34] ;
assign out_sfd__h7556 =
sfd___3__h7126[9] ?
_theResult___sfd__h7553 :
sfd___3__h7126[31:9] ;
assign out_sfd__h78792 =
_theResult___snd__h78287[34] ?
_theResult___sfd__h78789 :
_theResult___snd__h78287[56:34] ;
assign out_sfd__h8109 =
sfd___3__h7126[8] ?
_theResult___sfd__h8106 :
sfd___3__h7126[30:8] ;
assign out_sfd__h88033 =
sfdin__h87497[34] ?
_theResult___sfd__h88030 :
sfdin__h87497[56:34] ;
assign out_sfd__h96699 =
_theResult___snd__h96164[34] ?
_theResult___sfd__h96696 :
_theResult___snd__h96164[56:34] ;
assign requestR_BITS_126_TO_116_745_EQ_0_759_AND_requ_ETC___d3766 =
requestR[126:116] == 11'd0 && requestR[115:64] == 52'd0 &&
requestR[127] &&
requestR[190:180] == 11'd0 &&
requestR[179:128] == 52'd0 &&
!requestR[191] ;
assign requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 =
{ requestR[127:96] == 32'hFFFFFFFF && requestR[95],
(requestR[127:96] == 32'hFFFFFFFF) ?
requestR[94:64] :
31'h7FC00000 } ;
assign requestR_BITS_159_TO_128__q1 = requestR[159:128] ;
assign requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778 =
requestR[179:128] <= requestR[115:64] ;
assign requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783 =
requestR[179:128] < requestR[115:64] ;
assign requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3762 =
requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 &&
requestR[191] &&
requestR[126:116] == 11'd0 &&
requestR[115:64] == 52'd0 &&
!requestR[127] ;
assign requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836 =
requestR[190:180] == 11'd0 && requestR[179:128] == 52'd0 &&
requestR[126:116] == 11'd0 &&
requestR[115:64] == 52'd0 ||
(!requestR[191] || requestR[127]) &&
(requestR[191] || !requestR[127]) &&
(requestR[191] ?
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3831 :
NOT_requestR_BITS_190_TO_180_596_ULT_requestR__ETC___d3832) ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747 =
requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 ||
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
(NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708[23] ||
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1710 &&
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_OR_NOT__ETC___d1729 &&
x__h49361[85:54] == 32'hFFFFFFFF) ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1758 =
{ requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747,
3'd0,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752 } ==
5'd0 ||
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747 ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754 =
requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 &&
!requestR[179] &&
requestR[126:116] == 11'd2047 &&
requestR[115:64] != 52'd0 &&
!requestR[115] ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799 =
requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 &&
!requestR[179] ||
requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0 &&
!requestR[115] ;
assign requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799 ||
requestR[190:180] == 11'd2047 && requestR[179] ||
requestR[126:116] == 11'd2047 && requestR[115] ;
assign requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 =
requestR[190:180] == requestR[126:116] ;
assign requestR_BITS_190_TO_180_596_MINUS_1023___d1609 =
requestR[190:180] - 11'd1023 ;
assign requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 =
requestR[190:180] <= requestR[126:116] ;
assign requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3831 =
requestR_BITS_190_TO_180_596_ULE_requestR_BITS_ETC___d3775 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
requestR_BITS_179_TO_128_598_ULE_requestR_BITS_ETC___d3778) &&
!requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 &&
(!requestR_BITS_190_TO_180_596_EQ_requestR_BITS__ETC___d3777 ||
!requestR_BITS_179_TO_128_598_ULT_requestR_BITS_ETC___d3783) ;
assign requestR_BITS_190_TO_180_596_ULT_requestR_BITS_ETC___d3782 =
requestR[190:180] < requestR[126:116] ;
assign requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5_AND_ETC___d1026 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159] &&
(requestR[127:96] != 32'hFFFFFFFF || !requestR[95]) ||
(requestR[191:160] == 32'hFFFFFFFF && requestR[159] ||
requestR[127:96] != 32'hFFFFFFFF ||
!requestR[95]) &&
IF_NOT_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1024 ;
assign requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770 =
requestR[158] || requestR[157] || requestR[156] ||
requestR[155] ||
requestR[154] ||
requestR[153] ||
requestR[152] ||
requestR[151] ||
requestR[150] ||
requestR[149] ||
requestR[148] ||
requestR[147] ||
requestR[146] ||
requestR[145] ||
requestR[144] ||
requestR[143] ||
requestR[142] ||
requestR[141] ||
requestR[140] ||
requestR[139] ||
requestR[138] ||
requestR[137] ||
requestR[136] ||
requestR[135] ||
requestR[134] ||
requestR[133] ||
requestR[132] ||
requestR[131] ||
requestR[130] ||
requestR[129] ||
requestR[128] ;
assign requestR_BIT_159_6_OR_requestR_BIT_158_88_OR_r_ETC___d792 =
(requestR[159] ||
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770) &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618 &&
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d789 ;
assign res___1__h155823 =
(requestR[190:180] == 11'd2047 && requestR[179]) ?
64'd512 :
64'd256 ;
assign res___1__h156261 = requestR[191] ? 64'd1 : 64'd128 ;
assign res___1__h156271 = requestR[191] ? 64'd8 : 64'd16 ;
assign res___1__h156290 = requestR[191] ? 64'd4 : 64'd32 ;
assign res___1__h26221 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816[22]) ?
64'd512 :
64'd256 ;
assign res___1__h26457 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd1 :
64'd128 ;
assign res___1__h26467 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd8 :
64'd16 ;
assign res___1__h26486 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd4 :
64'd32 ;
assign res__h139089 =
{ IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3650,
x__h98397,
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614 } ;
assign res__h143531 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 ?
requestR[191:128] :
requestR[127:64] ;
assign res__h148079 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 ?
requestR[127:64] :
requestR[191:128] ;
assign res__h150783 =
((requestR[190:180] != 11'd2047 || requestR[179:128] == 52'd0) &&
(requestR[126:116] != 11'd2047 || requestR[115:64] == 52'd0) &&
requestR_BITS_190_TO_180_596_EQ_0_607_AND_requ_ETC___d3836) ?
64'd1 :
64'd0 ;
assign res__h153478 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3790 ?
64'd1 :
64'd0 ;
assign res__h155355 =
NOT_requestR_BITS_190_TO_180_596_EQ_2047_597_6_ETC___d3855 ?
64'd1 :
64'd0 ;
assign res__h156306 = requestR[191] ? 64'd2 : 64'd64 ;
assign res__h156487 = { 32'hFFFFFFFF, fpu$response_get[36:5] } ;
assign res__h17825 =
{ 32'hFFFFFFFF,
requestR_BITS_127_TO_96_2_EQ_0xFFFFFFFF_3_AND__ETC___d28 } ;
assign res__h18062 =
{ 32'hFFFFFFFF,
requestR[191:160] == 32'hFFFFFFFF && requestR[159],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign res__h23434 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1091 ?
64'd1 :
64'd0 ;
assign res__h24917 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1028 ?
64'd1 :
64'd0 ;
assign res__h25986 =
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d1109 ?
64'd1 :
64'd0 ;
assign res__h26502 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
64'd2 :
64'd64 ;
assign res__h97284 = { 32'hFFFFFFFF, x__h97290 } ;
assign result__h121215 =
{ _0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152[56:1],
_0b0_CONCAT_NOT_IF_requestR_BITS_191_TO_160_4_E_ETC___d3152[0] |
guard__h121210 } ;
assign result__h79880 =
{ _0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318[56:1],
_0b0_CONCAT_NOT_requestR_BITS_190_TO_180_596_EQ_ETC___d2318[0] |
guard__h79875 } ;
assign sV1_exp__h815 =
(requestR[191:160] == 32'hFFFFFFFF) ?
requestR[158:151] :
8'd255 ;
assign sV1_sfd__h816 =
(requestR[191:160] == 32'hFFFFFFFF) ?
requestR[150:128] :
23'd4194304 ;
assign sV2_exp__h918 =
(requestR[127:96] == 32'hFFFFFFFF) ? requestR[94:87] : 8'd255 ;
assign sV2_sfd__h919 =
(requestR[127:96] == 32'hFFFFFFFF) ?
requestR[86:64] :
23'd4194304 ;
assign sfd___3__h13303 =
requestR[159:128] <<
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d613 ;
assign sfd___3__h35762 =
sfd__h27761 <<
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d1227 ;
assign sfd___3__h45458 =
sfd__h37706 <<
IF_requestR_BIT_159_6_THEN_0_ELSE_IF_requestR__ETC___d1442 ;
assign sfd___3__h7126 =
sfd__h2222 <<
IF_IF_requestR_BIT_159_6_THEN_NEG_requestR_BIT_ETC___d255 ;
assign sfd__h119283 =
{ 1'b0,
_theResult___fst_exp__h119265 != 11'd0,
_theResult___snd__h119216[56:5] } +
54'd1 ;
assign sfd__h128930 =
{ 1'b0,
_theResult___fst_exp__h128838 != 11'd0,
sfdin__h128832[56:5] } +
54'd1 ;
assign sfd__h13330 = { 2'd0, sfd___3__h13303[31:9] } + 25'd1 ;
assign sfd__h137688 =
{ 1'b0,
_theResult___fst_exp__h137669 != 11'd0,
_theResult___snd__h137615[56:5] } +
54'd1 ;
assign sfd__h13869 =
{ 1'b0, x__h13854[7:0] != 8'd0, sfd___3__h13303[30:8] } + 25'd1 ;
assign sfd__h2222 = requestR[159] ? -requestR[159:128] : requestR[159:128] ;
assign sfd__h27761 = { sfd__h2222, 23'd0 } ;
assign sfd__h35789 = { 2'd0, sfd___3__h35762[54:3] } + 54'd1 ;
assign sfd__h36532 =
{ 1'b0, x__h36517[10:0] != 11'd0, sfd___3__h35762[53:2] } +
54'd1 ;
assign sfd__h37706 = { requestR[159:128], 23'd0 } ;
assign sfd__h45485 = { 2'd0, sfd___3__h45458[54:3] } + 54'd1 ;
assign sfd__h46227 =
{ 1'b0, x__h46212[10:0] != 11'd0, sfd___3__h45458[53:2] } +
54'd1 ;
assign sfd__h53913 = { value__h47609, 3'd0 } ;
assign sfd__h69742 =
{ 1'b0,
_theResult___fst_exp__h69650 != 8'd0,
sfdin__h69644[56:34] } +
25'd1 ;
assign sfd__h7153 = { 2'd0, sfd___3__h7126[31:9] } + 25'd1 ;
assign sfd__h7696 =
{ 1'b0, x__h7681[7:0] != 8'd0, sfd___3__h7126[30:8] } + 25'd1 ;
assign sfd__h78354 =
{ 1'b0,
_theResult___fst_exp__h78336 != 8'd0,
_theResult___snd__h78287[56:34] } +
25'd1 ;
assign sfd__h87595 =
{ 1'b0,
_theResult___fst_exp__h87503 != 8'd0,
sfdin__h87497[56:34] } +
25'd1 ;
assign sfd__h96237 =
{ 1'b0,
_theResult___fst_exp__h96218 != 8'd0,
_theResult___snd__h96164[56:34] } +
25'd1 ;
assign sfdin__h128832 =
_theResult____h120602[56] ?
_theResult___snd__h128849 :
_theResult___snd__h128860 ;
assign sfdin__h69644 =
_theResult____h61543[56] ?
_theResult___snd__h69661 :
_theResult___snd__h69672 ;
assign sfdin__h87497 =
_theResult____h79267[56] ?
_theResult___snd__h87514 :
_theResult___snd__h87525 ;
assign value__h15052 = { 1'b0, sV1_exp__h815 != 8'd0, sV1_sfd__h816 } ;
assign value__h47609 =
{ 1'b0, requestR[190:180] != 11'd0, requestR[179:128] } ;
assign value__h49752 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 &&
!requestR[179]) ?
_theResult___fst_sfd__h50209 :
requestR[179:128] ;
assign value__h98456 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 &&
!sV1_sfd__h816[22]) ?
_theResult___fst_sfd__h98711 :
sV1_sfd__h816 ;
assign x__h121310 = b__h15050 << x__h121343 ;
assign x__h121343 =
12'd57 -
_3074_MINUS_SEXT_IF_requestR_BITS_191_TO_160_4__ETC___d3148 ;
assign x__h13854 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d616 +
9'd127 ;
assign x__h139191 =
{ IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3688,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3695,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3709,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3721,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3733 } ;
assign x__h140114 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754 ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] != 52'd0 &&
!requestR[179]) ?
requestR[127:64] :
((requestR[126:116] == 11'd2047 &&
requestR[115:64] != 52'd0 &&
!requestR[115]) ?
requestR[191:128] :
((requestR[190:180] == 11'd2047 && requestR[179] &&
requestR[126:116] == 11'd2047 &&
requestR[115]) ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 && requestR[179]) ?
requestR[127:64] :
IF_requestR_BITS_126_TO_116_745_EQ_2047_746_AN_ETC___d3793)))) ;
assign x__h143663 =
{ requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3799,
4'd0 } ;
assign x__h144662 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3754 ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] != 52'd0 &&
!requestR[179]) ?
requestR[127:64] :
((requestR[126:116] == 11'd2047 &&
requestR[115:64] != 52'd0 &&
!requestR[115]) ?
requestR[191:128] :
((requestR[190:180] == 11'd2047 && requestR[179] &&
requestR[126:116] == 11'd2047 &&
requestR[115]) ?
64'h7FF8000000000000 :
((requestR[190:180] == 11'd2047 && requestR[179]) ?
requestR[127:64] :
((requestR[126:116] == 11'd2047 && requestR[115]) ?
requestR[191:128] :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3807))))) ;
assign x__h14520 =
{ 2'd0,
NOT_requestR_BITS_159_TO_128_24_EQ_0_25_26_AND_ETC___d781,
requestR[159:128] != 32'd0 &&
(requestR[159] ||
requestR_BIT_158_88_OR_requestR_BIT_157_90_OR__ETC___d770) &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618,
requestR[159:128] != 32'd0 &&
requestR_BIT_159_6_OR_requestR_BIT_158_88_OR_r_ETC___d792 } ;
assign x__h14804 = { {32{x__h14807[31]}}, x__h14807 } ;
assign x__h14807 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814 ?
32'h7FFFFFFF :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d886 ;
assign x__h149106 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 ?
64'd0 :
res__h150783 ;
assign x__h151801 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 ?
64'd0 :
res__h153478 ;
assign x__h153497 =
{ requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
requestR[126:116] == 11'd2047 && requestR[115:64] != 52'd0,
4'd0 } ;
assign x__h153678 =
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_N_ETC___d3821 ?
64'd0 :
res__h155355 ;
assign x__h155805 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ?
res___1__h155823 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
res___1__h156261 :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d3878) ;
assign x__h156455 =
fpu$response_get[69] ? res__h156487 : fpu$response_get[68:5] ;
assign x__h15726 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827 >>
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853 |
~(57'h1FFFFFFFFFFFFFF >>
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d853) &
{57{IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d827[56]}} ;
assign x__h16140 =
{ sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
sV1_exp__h815 == 8'd255 && sV1_sfd__h816 == 23'd0 ||
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d897,
3'd0,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
(sV1_exp__h815 != 8'd0 || sV1_sfd__h816 != 23'd0) &&
IF_NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0_ETC___d908 } ;
assign x__h16397 = { {32{x__h16400[31]}}, x__h16400 } ;
assign x__h16400 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d814 ?
32'hFFFFFFFF :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d948 ;
assign x__h16821 =
{ sV1_exp__h815 != 8'd0, sV1_sfd__h816, 33'd0 } >>
NEG_SEXT_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d917 ;
assign x__h16899 =
{ (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d967 :
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d956,
3'd0,
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 == 23'd0) &&
(sV1_exp__h815 != 8'd255 || sV1_sfd__h816 != 23'd0) &&
NOT_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFF_ETC___d961 } ;
assign x__h17147 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990 ?
64'hFFFFFFFF7FC00000 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1036 ;
assign x__h1773 = { 32'hFFFFFFFF, x__h1779 } ;
assign x__h1779 =
{ requestR[127:96] == 32'hFFFFFFFF && requestR[95],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign x__h19186 =
{ IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1038,
4'd0 } ;
assign x__h1919 = { 32'hFFFFFFFF, x__h1925 } ;
assign x__h1925 =
{ requestR[127:96] != 32'hFFFFFFFF || !requestR[95],
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign x__h19781 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d990 ?
64'hFFFFFFFF7FC00000 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1052 ;
assign x__h2053 = { 32'hFFFFFFFF, x__h2059 } ;
assign x__h2059 =
{ (requestR[191:160] == 32'hFFFFFFFF && requestR[159]) !=
(requestR[127:96] == 32'hFFFFFFFF && requestR[95]),
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d19 } ;
assign x__h2201 = { 32'hFFFFFFFF, x__h2207 } ;
assign x__h2207 =
{ requestR[159:128] != 32'd0 &&
(NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263 ?
requestR[159] :
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d325),
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d385,
(requestR[159:128] == 32'd0 ||
NOT_IF_requestR_BIT_159_6_THEN_NEG_requestR_BI_ETC___d263) ?
23'd0 :
_theResult___snd_fst_sfd__h8209 } ;
assign x__h22306 = { 32'hFFFFFFFF, requestR[159:128] } ;
assign x__h22427 =
{ {32{requestR_BITS_159_TO_128__q1[31]}},
requestR_BITS_159_TO_128__q1 } ;
assign x__h22565 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 ?
64'd0 :
res__h23434 ;
assign x__h24048 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 ?
64'd0 :
res__h24917 ;
assign x__h24936 =
{ sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0 ||
sV2_exp__h918 == 8'd255 && sV2_sfd__h919 != 23'd0,
4'd0 } ;
assign x__h25117 =
IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_5__ETC___d1075 ?
64'd0 :
res__h25986 ;
assign x__h26203 =
(sV1_exp__h815 == 8'd255 && sV1_sfd__h816 != 23'd0) ?
res___1__h26221 :
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d1123 ;
assign x__h27370 = { requestR[127], requestR[190:128] } ;
assign x__h27492 = { !requestR[127], requestR[190:128] } ;
assign x__h27616 = { requestR[191] != requestR[127], requestR[190:128] } ;
assign x__h27746 =
{ requestR[159:128] != 32'd0 &&
IF_NOT_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_15_ETC___d1287,
(requestR[159:128] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h37253,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1384 } ;
assign x__h36517 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1230 +
12'd1023 ;
assign x__h37409 =
{ 2'd0,
requestR[159:128] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1235 &&
_theResult___fst_exp__h37244 == 11'd2047 &&
_theResult___fst_sfd__h37245 == 52'd0),
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233,
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1231 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d1233 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6__ETC___d1401 } ;
assign x__h37694 =
{ 1'd0,
(requestR[159:128] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h46947,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d1567 } ;
assign x__h46212 =
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1445 +
12'd1023 ;
assign x__h47077 =
{ 2'd0,
requestR[159:128] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1448 &&
_theResult___fst_exp__h46938 == 11'd2047 &&
_theResult___fst_sfd__h46939 == 52'd0),
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447,
requestR[159:128] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1446 &&
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d1447 &&
IF_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THE_ETC___d1584 } ;
assign x__h47361 = { {32{x__h47364[31]}}, x__h47364 } ;
assign x__h47364 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
!requestR[191] && requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
32'h7FFFFFFF :
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d1677 ;
assign x__h48283 =
IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618 >>
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644 |
~(86'h3FFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1644) &
{86{IF_requestR_BIT_191_186_THEN_NEG_0b0_CONCAT_NO_ETC___d1618[85]}} ;
assign x__h48680 =
{ requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
requestR[190:180] == 11'd2047 && requestR[179:128] == 52'd0 ||
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1688,
3'd0,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_ETC___d1699 } ;
assign x__h48937 = { {32{x__h48940[31]}}, x__h48940 } ;
assign x__h48940 =
(requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
!requestR[191] && requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
32'hFFFFFFFF :
(requestR[191] ?
32'd0 :
((requestR[190:180] == 11'd2047 &&
requestR[179:128] == 52'd0) ?
32'hFFFFFFFF :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_AND_r_ETC___d1737)) ;
assign x__h49361 =
{ requestR[190:180] != 11'd0, requestR[179:128], 33'd0 } >>
NEG_SEXT_requestR_BITS_190_TO_180_596_MINUS_10_ETC___d1708 ;
assign x__h49439 =
{ requestR[191] ?
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1758 :
requestR_BITS_190_TO_180_596_EQ_2047_597_AND_0_ETC___d1747,
3'd0,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
NOT_requestR_BITS_190_TO_180_596_EQ_0_607_613__ETC___d1752 } ;
assign x__h49683 =
(x__h49692 == 8'd255 &&
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798[22]) ?
64'hFFFFFFFF7FC00000 :
res__h97284 ;
assign x__h49692 =
(requestR[190:180] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h96808 ;
assign x__h7681 =
_32_MINUS_0_CONCAT_IF_IF_requestR_BIT_159_6_THE_ETC___d258 +
9'd127 ;
assign x__h79975 = sfd__h53913 << x__h80008 ;
assign x__h80008 =
12'd57 -
_3970_MINUS_SEXT_requestR_BITS_190_TO_180_596_M_ETC___d2314 ;
assign x__h8374 =
{ 2'd0,
requestR[159:128] != 32'd0 &&
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d466,
requestR[159:128] != 32'd0 &&
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d469,
requestR[159:128] != 32'd0 &&
IF_requestR_BIT_159_6_THEN_NEG_requestR_BITS_1_ETC___d478 } ;
assign x__h8662 =
{ 33'h1FFFFFFFE,
IF_requestR_BITS_159_TO_128_24_EQ_0_25_OR_NOT__ETC___d703,
(requestR[159:128] == 32'd0 ||
!requestR[159] &&
NOT_requestR_BIT_158_88_89_AND_NOT_requestR_BI_ETC___d579 ||
!_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d617 ||
_32_MINUS_0_CONCAT_IF_requestR_BIT_159_6_THEN_0_ETC___d618) ?
23'd0 :
_theResult___snd_fst_sfd__h14381 } ;
assign x__h97290 =
{ (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0 ||
(requestR[190:180] == 11'd2047 ||
requestR[190:180] == 11'd0) &&
requestR[179:128] == 52'd0) ?
requestR[191] :
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2840,
x__h49692,
IF_requestR_BITS_190_TO_180_596_EQ_2047_597_AN_ETC___d2798 } ;
assign x__h97405 =
{ (requestR[190:180] == 11'd2047 && requestR[179:128] != 52'd0) ?
requestR[190:180] == 11'd2047 &&
requestR[179:128] != 52'd0 &&
!requestR[179] :
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2891,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2902,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2918,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2931,
(requestR[190:180] != 11'd2047 ||
requestR[179:128] == 52'd0) &&
(requestR[190:180] != 11'd2047 ||
requestR[179:128] != 52'd0) &&
(requestR[190:180] != 11'd0 || requestR[179:128] != 52'd0) &&
IF_requestR_BITS_190_TO_180_596_EQ_0_607_THEN__ETC___d2944 } ;
assign x__h98388 =
(x__h98397 == 11'd2047 &&
IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFFFFFFFF_ETC___d3614[51]) ?
64'h7FF8000000000000 :
res__h139089 ;
assign x__h98397 =
(sV1_exp__h815 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h138462 ;
always@(requestR)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd254;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 =
requestR[191] ? 8'd255 : 8'd254;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 =
requestR[191] ? 8'd254 : 8'd255;
default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q2 = 8'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 =
23'd8388607;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 =
requestR[191] ? 23'd0 : 23'd8388607;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 =
requestR[191] ? 23'd8388607 : 23'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q3 = 23'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd2046;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
11'd2047 :
11'd2046;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
11'd2046 :
11'd2047;
default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q4 = 11'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 =
52'hFFFFFFFFFFFFF;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 =
(requestR[191:160] == 32'hFFFFFFFF && requestR[159]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q5 = 52'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h0:
IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 =
requestR[194:192];
3'h1: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd4;
3'h2: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd3;
3'h3: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd2;
3'h4: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 = 3'd1;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x0_1_THEN_re_ETC___d40 =
3'd0;
endcase
end
always@(guard__h7136 or requestR)
begin
case (guard__h7136)
2'b0, 2'b01, 2'b10:
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8 =
requestR[159];
2'd3:
CASE_guard136_0b0_requestR_BIT_159_0b1_request_ETC__q8 =
guard__h7136 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h7136)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 =
(guard__h7136 == 2'b0) ?
requestR[159] :
(guard__h7136 == 2'b01 || guard__h7136 == 2'b10 ||
guard__h7136 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q9 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h7666 or requestR)
begin
case (guard__h7666)
2'b0, 2'b01, 2'b10:
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10 =
requestR[159];
2'd3:
CASE_guard666_0b0_requestR_BIT_159_0b1_request_ETC__q10 =
guard__h7666 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h7666)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 =
(guard__h7666 == 2'b0) ?
requestR[159] :
(guard__h7666 == 2'b01 || guard__h7666 == 2'b10 ||
guard__h7666 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q11 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h7136 or _theResult___exp__h7552)
begin
case (guard__h7136)
2'b0: CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12 =
_theResult___exp__h7552;
endcase
end
always@(requestR or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347 or
guard__h7136 or
_theResult___exp__h7552 or
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12)
begin
case (requestR[194:192])
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d347;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
(guard__h7136 == 2'b0 || requestR[159]) ?
8'd0 :
_theResult___exp__h7552;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
CASE_guard136_0b0_0_0b1_theResult___exp552_0b1_ETC__q12;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d350 =
8'd0;
endcase
end
always@(guard__h7136 or out_exp__h7555 or _theResult___exp__h7552)
begin
case (guard__h7136)
2'b0, 2'b01:
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 = 8'd0;
2'b10:
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 =
out_exp__h7555;
2'b11:
CASE_guard136_0b0_0_0b1_0_0b10_out_exp555_0b11_ETC__q13 =
_theResult___exp__h7552;
endcase
end
always@(guard__h7666 or x__h7681 or _theResult___exp__h8105)
begin
case (guard__h7666)
2'b0:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14 =
x__h7681[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14 =
_theResult___exp__h8105;
endcase
end
always@(requestR or
x__h7681 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373 or
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
x__h7681[7:0];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d375;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d373;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_theResu_ETC__q14;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d379 =
8'd0;
endcase
end
always@(guard__h7666 or
x__h7681 or out_exp__h8108 or _theResult___exp__h8105)
begin
case (guard__h7666)
2'b0, 2'b01:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 =
x__h7681[7:0];
2'b10:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 =
out_exp__h8108;
2'b11:
CASE_guard666_0b0_x681_BITS_7_TO_0_0b1_x681_BI_ETC__q15 =
_theResult___exp__h8105;
endcase
end
always@(guard__h7136 or sfd___3__h7126 or _theResult___sfd__h7553)
begin
case (guard__h7136)
2'b0:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16 =
sfd___3__h7126[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16 =
_theResult___sfd__h7553;
endcase
end
always@(requestR or
sfd___3__h7126 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396 or
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
sfd___3__h7126[31:9];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d398;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d396;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q16;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d402 =
23'd0;
endcase
end
always@(guard__h7136 or
sfd___3__h7126 or out_sfd__h7556 or _theResult___sfd__h7553)
begin
case (guard__h7136)
2'b0, 2'b01:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 =
sfd___3__h7126[31:9];
2'b10:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 =
out_sfd__h7556;
2'b11:
CASE_guard136_0b0_sfd___3126_BITS_31_TO_9_0b1__ETC__q17 =
_theResult___sfd__h7553;
endcase
end
always@(guard__h7666 or sfd___3__h7126 or _theResult___sfd__h8106)
begin
case (guard__h7666)
2'b0:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18 =
sfd___3__h7126[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18 =
_theResult___sfd__h8106;
endcase
end
always@(requestR or
sfd___3__h7126 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414 or
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
sfd___3__h7126[30:8];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d416;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d414;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q18;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d420 =
23'd0;
endcase
end
always@(guard__h7666 or
sfd___3__h7126 or out_sfd__h8109 or _theResult___sfd__h8106)
begin
case (guard__h7666)
2'b0, 2'b01:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 =
sfd___3__h7126[30:8];
2'b10:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 =
out_sfd__h8109;
2'b11:
CASE_guard666_0b0_sfd___3126_BITS_30_TO_8_0b1__ETC__q19 =
_theResult___sfd__h8106;
endcase
end
always@(guard__h13313 or out_exp__h13729 or _theResult___exp__h13726)
begin
case (guard__h13313)
2'b0, 2'b01:
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 = 8'd0;
2'b10:
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 =
out_exp__h13729;
2'b11:
CASE_guard3313_0b0_0_0b1_0_0b10_out_exp3729_0b_ETC__q22 =
_theResult___exp__h13726;
endcase
end
always@(guard__h13313 or _theResult___exp__h13726)
begin
case (guard__h13313)
2'b0: CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23 =
_theResult___exp__h13726;
endcase
end
always@(requestR or
guard__h13313 or
_theResult___exp__h13726 or
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 =
(guard__h13313 == 2'b0) ? 8'd0 : _theResult___exp__h13726;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 =
CASE_guard3313_0b0_0_0b1_theResult___exp3726_0_ETC__q23;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard3313_ETC__q24 = 8'd0;
endcase
end
always@(guard__h13839 or x__h13854 or _theResult___exp__h14278)
begin
case (guard__h13839)
2'b0:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25 =
x__h13854[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25 =
_theResult___exp__h14278;
endcase
end
always@(requestR or
x__h13854 or
guard__h13839 or
_theResult___exp__h14278 or
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
x__h13854[7:0];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
(guard__h13839 == 2'b0) ?
x__h13854[7:0] :
_theResult___exp__h14278;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_theRe_ETC__q25;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d697 =
8'd0;
endcase
end
always@(guard__h13839 or
x__h13854 or out_exp__h14281 or _theResult___exp__h14278)
begin
case (guard__h13839)
2'b0, 2'b01:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 =
x__h13854[7:0];
2'b10:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 =
out_exp__h14281;
2'b11:
CASE_guard3839_0b0_x3854_BITS_7_TO_0_0b1_x3854_ETC__q26 =
_theResult___exp__h14278;
endcase
end
always@(guard__h13839 or sfd___3__h13303 or _theResult___sfd__h14279)
begin
case (guard__h13839)
2'b0:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27 =
sfd___3__h13303[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27 =
_theResult___sfd__h14279;
endcase
end
always@(requestR or
sfd___3__h13303 or
guard__h13839 or
_theResult___sfd__h14279 or
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
sfd___3__h13303[30:8];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
(guard__h13839 == 2'b0) ?
sfd___3__h13303[30:8] :
_theResult___sfd__h14279;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q27;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d735 =
23'd0;
endcase
end
always@(guard__h13839 or
sfd___3__h13303 or out_sfd__h14282 or _theResult___sfd__h14279)
begin
case (guard__h13839)
2'b0, 2'b01:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 =
sfd___3__h13303[30:8];
2'b10:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 =
out_sfd__h14282;
2'b11:
CASE_guard3839_0b0_sfd___33303_BITS_30_TO_8_0b_ETC__q28 =
_theResult___sfd__h14279;
endcase
end
always@(guard__h13313 or sfd___3__h13303 or _theResult___sfd__h13727)
begin
case (guard__h13313)
2'b0:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29 =
sfd___3__h13303[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29 =
_theResult___sfd__h13727;
endcase
end
always@(requestR or
sfd___3__h13303 or
guard__h13313 or
_theResult___sfd__h13727 or
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
sfd___3__h13303[31:9];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
(guard__h13313 == 2'b0) ?
sfd___3__h13303[31:9] :
_theResult___sfd__h13727;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q29;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d720 =
23'd0;
endcase
end
always@(guard__h13313 or
sfd___3__h13303 or out_sfd__h13730 or _theResult___sfd__h13727)
begin
case (guard__h13313)
2'b0, 2'b01:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 =
sfd___3__h13303[31:9];
2'b10:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 =
out_sfd__h13730;
2'b11:
CASE_guard3313_0b0_sfd___33303_BITS_31_TO_9_0b_ETC__q30 =
_theResult___sfd__h13727;
endcase
end
always@(guard__h35772 or requestR)
begin
case (guard__h35772)
2'b0, 2'b01, 2'b10:
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35 =
requestR[159];
2'd3:
CASE_guard5772_0b0_requestR_BIT_159_0b1_reques_ETC__q35 =
guard__h35772 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h35772)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 =
(guard__h35772 == 2'b0) ?
requestR[159] :
(guard__h35772 == 2'b01 || guard__h35772 == 2'b10 ||
guard__h35772 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q36 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h36502 or requestR)
begin
case (guard__h36502)
2'b0, 2'b01, 2'b10:
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37 =
requestR[159];
2'd3:
CASE_guard6502_0b0_requestR_BIT_159_0b1_reques_ETC__q37 =
guard__h36502 == 2'b11 && requestR[159];
endcase
end
always@(requestR or guard__h36502)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 =
requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 =
(guard__h36502 == 2'b0) ?
requestR[159] :
(guard__h36502 == 2'b01 || guard__h36502 == 2'b10 ||
guard__h36502 == 2'b11) &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q38 =
requestR[194:192] == 3'h1 && requestR[159];
endcase
end
always@(guard__h36502 or x__h36517 or _theResult___exp__h37144)
begin
case (guard__h36502)
2'b0:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39 =
x__h36517[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39 =
_theResult___exp__h37144;
endcase
end
always@(requestR or
x__h36517 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333 or
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
x__h36517[10:0];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1335;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1333;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_theR_ETC__q39;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1339 =
11'd0;
endcase
end
always@(guard__h36502 or
x__h36517 or out_exp__h37147 or _theResult___exp__h37144)
begin
case (guard__h36502)
2'b0, 2'b01:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 =
x__h36517[10:0];
2'b10:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 =
out_exp__h37147;
2'b11:
CASE_guard6502_0b0_x6517_BITS_10_TO_0_0b1_x651_ETC__q40 =
_theResult___exp__h37144;
endcase
end
always@(guard__h36502 or sfd___3__h35762 or _theResult___sfd__h37145)
begin
case (guard__h36502)
2'b0:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41 =
sfd___3__h35762[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41 =
_theResult___sfd__h37145;
endcase
end
always@(requestR or
sfd___3__h35762 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374 or
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
sfd___3__h35762[53:2];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1376;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1374;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q41;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1380 =
52'd0;
endcase
end
always@(guard__h36502 or
sfd___3__h35762 or out_sfd__h37148 or _theResult___sfd__h37145)
begin
case (guard__h36502)
2'b0, 2'b01:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 =
sfd___3__h35762[53:2];
2'b10:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 =
out_sfd__h37148;
2'b11:
CASE_guard6502_0b0_sfd___35762_BITS_53_TO_2_0b_ETC__q42 =
_theResult___sfd__h37145;
endcase
end
always@(guard__h35772 or _theResult___exp__h36388)
begin
case (guard__h35772)
2'b0: CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43 =
_theResult___exp__h36388;
endcase
end
always@(requestR or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307 or
guard__h35772 or
_theResult___exp__h36388 or
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43)
begin
case (requestR[194:192])
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1307;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
(guard__h35772 == 2'b0 || requestR[159]) ?
11'd0 :
_theResult___exp__h36388;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
CASE_guard5772_0b0_0_0b1_theResult___exp6388_0_ETC__q43;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1310 =
11'd0;
endcase
end
always@(guard__h35772 or out_exp__h36391 or _theResult___exp__h36388)
begin
case (guard__h35772)
2'b0, 2'b01:
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 = 11'd0;
2'b10:
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 =
out_exp__h36391;
2'b11:
CASE_guard5772_0b0_0_0b1_0_0b10_out_exp6391_0b_ETC__q44 =
_theResult___exp__h36388;
endcase
end
always@(guard__h35772 or sfd___3__h35762 or _theResult___sfd__h36389)
begin
case (guard__h35772)
2'b0:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45 =
sfd___3__h35762[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45 =
_theResult___sfd__h36389;
endcase
end
always@(requestR or
sfd___3__h35762 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358 or
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356 or
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
sfd___3__h35762[54:3];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1358;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
IF_IF_IF_requestR_BIT_159_6_THEN_NEG_requestR__ETC___d1356;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q45;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1362 =
52'd0;
endcase
end
always@(guard__h35772 or
sfd___3__h35762 or out_sfd__h36392 or _theResult___sfd__h36389)
begin
case (guard__h35772)
2'b0, 2'b01:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 =
sfd___3__h35762[54:3];
2'b10:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 =
out_sfd__h36392;
2'b11:
CASE_guard5772_0b0_sfd___35762_BITS_54_TO_3_0b_ETC__q46 =
_theResult___sfd__h36389;
endcase
end
always@(guard__h45468 or out_exp__h46087 or _theResult___exp__h46084)
begin
case (guard__h45468)
2'b0, 2'b01:
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 = 11'd0;
2'b10:
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 =
out_exp__h46087;
2'b11:
CASE_guard5468_0b0_0_0b1_0_0b10_out_exp6087_0b_ETC__q49 =
_theResult___exp__h46084;
endcase
end
always@(guard__h45468 or _theResult___exp__h46084)
begin
case (guard__h45468)
2'b0: CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50 =
_theResult___exp__h46084;
endcase
end
always@(requestR or
guard__h45468 or
_theResult___exp__h46084 or
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 =
(guard__h45468 == 2'b0) ? 11'd0 : _theResult___exp__h46084;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 =
CASE_guard5468_0b0_0_0b1_theResult___exp6084_0_ETC__q50;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard5468_ETC__q51 =
11'd0;
endcase
end
always@(guard__h46197 or x__h46212 or _theResult___exp__h46839)
begin
case (guard__h46197)
2'b0:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52 =
x__h46212[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52 =
_theResult___exp__h46839;
endcase
end
always@(requestR or
x__h46212 or
guard__h46197 or
_theResult___exp__h46839 or
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
x__h46212[10:0];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
(guard__h46197 == 2'b0) ?
x__h46212[10:0] :
_theResult___exp__h46839;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_theR_ETC__q52;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1526 =
11'd0;
endcase
end
always@(guard__h46197 or
x__h46212 or out_exp__h46842 or _theResult___exp__h46839)
begin
case (guard__h46197)
2'b0, 2'b01:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 =
x__h46212[10:0];
2'b10:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 =
out_exp__h46842;
2'b11:
CASE_guard6197_0b0_x6212_BITS_10_TO_0_0b1_x621_ETC__q53 =
_theResult___exp__h46839;
endcase
end
always@(guard__h46197 or sfd___3__h45458 or _theResult___sfd__h46840)
begin
case (guard__h46197)
2'b0:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54 =
sfd___3__h45458[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54 =
_theResult___sfd__h46840;
endcase
end
always@(requestR or
sfd___3__h45458 or
guard__h46197 or
_theResult___sfd__h46840 or
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
sfd___3__h45458[53:2];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
(guard__h46197 == 2'b0) ?
sfd___3__h45458[53:2] :
_theResult___sfd__h46840;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q54;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1563 =
52'd0;
endcase
end
always@(guard__h46197 or
sfd___3__h45458 or out_sfd__h46843 or _theResult___sfd__h46840)
begin
case (guard__h46197)
2'b0, 2'b01:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 =
sfd___3__h45458[53:2];
2'b10:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 =
out_sfd__h46843;
2'b11:
CASE_guard6197_0b0_sfd___35458_BITS_53_TO_2_0b_ETC__q55 =
_theResult___sfd__h46840;
endcase
end
always@(guard__h45468 or sfd___3__h45458 or _theResult___sfd__h46085)
begin
case (guard__h45468)
2'b0:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56 =
sfd___3__h45458[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56 =
_theResult___sfd__h46085;
endcase
end
always@(requestR or
sfd___3__h45458 or
guard__h45468 or
_theResult___sfd__h46085 or
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
sfd___3__h45458[54:3];
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
(guard__h45468 == 2'b0) ?
sfd___3__h45458[54:3] :
_theResult___sfd__h46085;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q56;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d1548 =
52'd0;
endcase
end
always@(guard__h45468 or
sfd___3__h45458 or out_sfd__h46088 or _theResult___sfd__h46085)
begin
case (guard__h45468)
2'b0, 2'b01:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 =
sfd___3__h45458[54:3];
2'b10:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 =
out_sfd__h46088;
2'b11:
CASE_guard5468_0b0_sfd___35458_BITS_54_TO_3_0b_ETC__q57 =
_theResult___sfd__h46085;
endcase
end
always@(guard__h61553 or
_theResult___fst_exp__h69650 or _theResult___exp__h70176)
begin
case (guard__h61553)
2'b0:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70 =
_theResult___fst_exp__h69650;
2'b01, 2'b10, 2'b11:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70 =
_theResult___exp__h70176;
endcase
end
always@(requestR or
_theResult___fst_exp__h69650 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133 or
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
_theResult___fst_exp__h69650;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2135;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2133;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q70;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2139 =
8'd0;
endcase
end
always@(guard__h61553 or
_theResult___fst_exp__h69650 or
out_exp__h70179 or _theResult___exp__h70176)
begin
case (guard__h61553)
2'b0, 2'b01:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 =
_theResult___fst_exp__h69650;
2'b10:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 =
out_exp__h70179;
2'b11:
CASE_guard1553_0b0_theResult___fst_exp9650_0b1_ETC__q71 =
_theResult___exp__h70176;
endcase
end
always@(guard__h70288 or
_theResult___fst_exp__h78336 or _theResult___exp__h78788)
begin
case (guard__h70288)
2'b0:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72 =
_theResult___fst_exp__h78336;
2'b01, 2'b10, 2'b11:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72 =
_theResult___exp__h78788;
endcase
end
always@(requestR or
_theResult___fst_exp__h78336 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290 or
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
_theResult___fst_exp__h78336;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2292;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2290;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q72;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2296 =
8'd0;
endcase
end
always@(guard__h70288 or
_theResult___fst_exp__h78336 or
out_exp__h78791 or _theResult___exp__h78788)
begin
case (guard__h70288)
2'b0, 2'b01:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 =
_theResult___fst_exp__h78336;
2'b10:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 =
out_exp__h78791;
2'b11:
CASE_guard0288_0b0_theResult___fst_exp8336_0b1_ETC__q73 =
_theResult___exp__h78788;
endcase
end
always@(guard__h79277 or
_theResult___fst_exp__h87503 or _theResult___exp__h88029)
begin
case (guard__h79277)
2'b0:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74 =
_theResult___fst_exp__h87503;
2'b01, 2'b10, 2'b11:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74 =
_theResult___exp__h88029;
endcase
end
always@(requestR or
_theResult___fst_exp__h87503 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617 or
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
_theResult___fst_exp__h87503;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2619;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2617;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q74;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2623 =
8'd0;
endcase
end
always@(guard__h79277 or
_theResult___fst_exp__h87503 or
out_exp__h88032 or _theResult___exp__h88029)
begin
case (guard__h79277)
2'b0, 2'b01:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 =
_theResult___fst_exp__h87503;
2'b10:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 =
out_exp__h88032;
2'b11:
CASE_guard9277_0b0_theResult___fst_exp7503_0b1_ETC__q75 =
_theResult___exp__h88029;
endcase
end
always@(guard__h88141 or
_theResult___fst_exp__h96218 or _theResult___exp__h96695)
begin
case (guard__h88141)
2'b0:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76 =
_theResult___fst_exp__h96218;
2'b01, 2'b10, 2'b11:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76 =
_theResult___exp__h96695;
endcase
end
always@(requestR or
_theResult___fst_exp__h96218 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686 or
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
_theResult___fst_exp__h96218;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2688;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2686;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q76;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2692 =
8'd0;
endcase
end
always@(guard__h88141 or
_theResult___fst_exp__h96218 or
out_exp__h96698 or _theResult___exp__h96695)
begin
case (guard__h88141)
2'b0, 2'b01:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 =
_theResult___fst_exp__h96218;
2'b10:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 =
out_exp__h96698;
2'b11:
CASE_guard8141_0b0_theResult___fst_exp6218_0b1_ETC__q77 =
_theResult___exp__h96695;
endcase
end
always@(guard__h61553 or sfdin__h69644 or _theResult___sfd__h70177)
begin
case (guard__h61553)
2'b0:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78 =
sfdin__h69644[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78 =
_theResult___sfd__h70177;
endcase
end
always@(requestR or
sfdin__h69644 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722 or
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720 or
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
sfdin__h69644[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2722;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
IF_IF_IF_IF_0b0_CONCAT_NOT_requestR_BITS_190_T_ETC___d2720;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q78;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2726 =
23'd0;
endcase
end
always@(guard__h61553 or
sfdin__h69644 or out_sfd__h70180 or _theResult___sfd__h70177)
begin
case (guard__h61553)
2'b0, 2'b01:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 =
sfdin__h69644[56:34];
2'b10:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 =
out_sfd__h70180;
2'b11:
CASE_guard1553_0b0_sfdin9644_BITS_56_TO_34_0b1_ETC__q79 =
_theResult___sfd__h70177;
endcase
end
always@(guard__h70288 or
_theResult___snd__h78287 or _theResult___sfd__h78789)
begin
case (guard__h70288)
2'b0:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80 =
_theResult___snd__h78287[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80 =
_theResult___sfd__h78789;
endcase
end
always@(requestR or
_theResult___snd__h78287 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739 or
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
_theResult___snd__h78287[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2741;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2739;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q80;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2745 =
23'd0;
endcase
end
always@(guard__h70288 or
_theResult___snd__h78287 or
out_sfd__h78792 or _theResult___sfd__h78789)
begin
case (guard__h70288)
2'b0, 2'b01:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 =
_theResult___snd__h78287[56:34];
2'b10:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 =
out_sfd__h78792;
2'b11:
CASE_guard0288_0b0_theResult___snd8287_BITS_56_ETC__q81 =
_theResult___sfd__h78789;
endcase
end
always@(guard__h79277 or sfdin__h87497 or _theResult___sfd__h88030)
begin
case (guard__h79277)
2'b0:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82 =
sfdin__h87497[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82 =
_theResult___sfd__h88030;
endcase
end
always@(requestR or
sfdin__h87497 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768 or
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766 or
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
sfdin__h87497[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2768;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
IF_IF_IF_IF_3970_MINUS_SEXT_requestR_BITS_190__ETC___d2766;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q82;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2772 =
23'd0;
endcase
end
always@(guard__h79277 or
sfdin__h87497 or out_sfd__h88033 or _theResult___sfd__h88030)
begin
case (guard__h79277)
2'b0, 2'b01:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 =
sfdin__h87497[56:34];
2'b10:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 =
out_sfd__h88033;
2'b11:
CASE_guard9277_0b0_sfdin7497_BITS_56_TO_34_0b1_ETC__q83 =
_theResult___sfd__h88030;
endcase
end
always@(guard__h88141 or
_theResult___snd__h96164 or _theResult___sfd__h96696)
begin
case (guard__h88141)
2'b0:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84 =
_theResult___snd__h96164[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84 =
_theResult___sfd__h96696;
endcase
end
always@(requestR or
_theResult___snd__h96164 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787 or
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785 or
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
_theResult___snd__h96164[56:34];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2787;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
IF_IF_IF_requestR_BITS_190_TO_180_596_EQ_0_607_ETC___d2785;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q84;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d2791 =
23'd0;
endcase
end
always@(guard__h88141 or
_theResult___snd__h96164 or
out_sfd__h96699 or _theResult___sfd__h96696)
begin
case (guard__h88141)
2'b0, 2'b01:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 =
_theResult___snd__h96164[56:34];
2'b10:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 =
out_sfd__h96699;
2'b11:
CASE_guard8141_0b0_theResult___snd6164_BITS_56_ETC__q85 =
_theResult___sfd__h96696;
endcase
end
always@(guard__h61553 or requestR)
begin
case (guard__h61553)
2'b0, 2'b01, 2'b10:
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86 =
requestR[191];
2'd3:
CASE_guard1553_0b0_requestR_BIT_191_0b1_reques_ETC__q86 =
guard__h61553 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h61553)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 =
(guard__h61553 == 2'b0) ?
requestR[191] :
(guard__h61553 == 2'b01 || guard__h61553 == 2'b10 ||
guard__h61553 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q87 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h70288 or requestR)
begin
case (guard__h70288)
2'b0, 2'b01, 2'b10:
CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88 =
requestR[191];
2'd3:
CASE_guard0288_0b0_requestR_BIT_191_0b1_reques_ETC__q88 =
guard__h70288 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h70288)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 =
(guard__h70288 == 2'b0) ?
requestR[191] :
(guard__h70288 == 2'b01 || guard__h70288 == 2'b10 ||
guard__h70288 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q89 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h79277 or requestR)
begin
case (guard__h79277)
2'b0, 2'b01, 2'b10:
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90 =
requestR[191];
2'd3:
CASE_guard9277_0b0_requestR_BIT_191_0b1_reques_ETC__q90 =
guard__h79277 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h79277)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 =
(guard__h79277 == 2'b0) ?
requestR[191] :
(guard__h79277 == 2'b01 || guard__h79277 == 2'b10 ||
guard__h79277 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q91 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h88141 or requestR)
begin
case (guard__h88141)
2'b0, 2'b01, 2'b10:
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92 =
requestR[191];
2'd3:
CASE_guard8141_0b0_requestR_BIT_191_0b1_reques_ETC__q92 =
guard__h88141 == 2'b11 && requestR[191];
endcase
end
always@(requestR or guard__h88141)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 =
requestR[191];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 =
(guard__h88141 == 2'b0) ?
requestR[191] :
(guard__h88141 == 2'b01 || guard__h88141 == 2'b10 ||
guard__h88141 == 2'b11) &&
requestR[191];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q93 =
requestR[194:192] == 3'h1 && requestR[191];
endcase
end
always@(guard__h111304 or
_theResult___fst_exp__h119265 or _theResult___exp__h119920)
begin
case (guard__h111304)
2'b0:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102 =
_theResult___fst_exp__h119265;
2'b01, 2'b10, 2'b11:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102 =
_theResult___exp__h119920;
endcase
end
always@(requestR or
_theResult___fst_exp__h119265 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128 or
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
_theResult___fst_exp__h119265;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3130;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3128;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q102;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3134 =
11'd0;
endcase
end
always@(guard__h111304 or
_theResult___fst_exp__h119265 or
out_exp__h119923 or _theResult___exp__h119920)
begin
case (guard__h111304)
2'b0, 2'b01:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 =
_theResult___fst_exp__h119265;
2'b10:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 =
out_exp__h119923;
2'b11:
CASE_guard11304_0b0_theResult___fst_exp19265_0_ETC__q103 =
_theResult___exp__h119920;
endcase
end
always@(guard__h120612 or
_theResult___fst_exp__h128838 or _theResult___exp__h129567)
begin
case (guard__h120612)
2'b0:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104 =
_theResult___fst_exp__h128838;
2'b01, 2'b10, 2'b11:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104 =
_theResult___exp__h129567;
endcase
end
always@(requestR or
_theResult___fst_exp__h128838 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453 or
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
_theResult___fst_exp__h128838;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3455;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3453;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q104;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3459 =
11'd0;
endcase
end
always@(guard__h120612 or
_theResult___fst_exp__h128838 or
out_exp__h129570 or _theResult___exp__h129567)
begin
case (guard__h120612)
2'b0, 2'b01:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 =
_theResult___fst_exp__h128838;
2'b10:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 =
out_exp__h129570;
2'b11:
CASE_guard20612_0b0_theResult___fst_exp28838_0_ETC__q105 =
_theResult___exp__h129567;
endcase
end
always@(guard__h129679 or
_theResult___fst_exp__h137669 or _theResult___exp__h138349)
begin
case (guard__h129679)
2'b0:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106 =
_theResult___fst_exp__h137669;
2'b01, 2'b10, 2'b11:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106 =
_theResult___exp__h138349;
endcase
end
always@(requestR or
_theResult___fst_exp__h137669 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522 or
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
_theResult___fst_exp__h137669;
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3524;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3522;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q106;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3528 =
11'd0;
endcase
end
always@(guard__h129679 or
_theResult___fst_exp__h137669 or
out_exp__h138352 or _theResult___exp__h138349)
begin
case (guard__h129679)
2'b0, 2'b01:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 =
_theResult___fst_exp__h137669;
2'b10:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 =
out_exp__h138352;
2'b11:
CASE_guard29679_0b0_theResult___fst_exp37669_0_ETC__q107 =
_theResult___exp__h138349;
endcase
end
always@(guard__h111304 or requestR)
begin
case (guard__h111304)
2'b0, 2'b01, 2'b10:
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
2'd3:
CASE_guard11304_0b0_requestR_BITS_191_TO_160_E_ETC__q108 =
guard__h111304 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(requestR or guard__h111304)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 =
(guard__h111304 == 2'b0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
(guard__h111304 == 2'b01 || guard__h111304 == 2'b10 ||
guard__h111304 == 2'b11) &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q109 =
requestR[194:192] == 3'h1 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(guard__h120612 or requestR)
begin
case (guard__h120612)
2'b0, 2'b01, 2'b10:
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
2'd3:
CASE_guard20612_0b0_requestR_BITS_191_TO_160_E_ETC__q110 =
guard__h120612 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(requestR or guard__h120612)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 =
(guard__h120612 == 2'b0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
(guard__h120612 == 2'b01 || guard__h120612 == 2'b10 ||
guard__h120612 == 2'b11) &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q111 =
requestR[194:192] == 3'h1 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(guard__h129679 or requestR)
begin
case (guard__h129679)
2'b0, 2'b01, 2'b10:
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
2'd3:
CASE_guard29679_0b0_requestR_BITS_191_TO_160_E_ETC__q112 =
guard__h129679 == 2'b11 && requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(requestR or guard__h129679)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 =
requestR[191:160] == 32'hFFFFFFFF && requestR[159];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 =
(guard__h129679 == 2'b0) ?
requestR[191:160] == 32'hFFFFFFFF && requestR[159] :
(guard__h129679 == 2'b01 || guard__h129679 == 2'b10 ||
guard__h129679 == 2'b11) &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q113 =
requestR[194:192] == 3'h1 &&
requestR[191:160] == 32'hFFFFFFFF &&
requestR[159];
endcase
end
always@(guard__h111304 or
_theResult___snd__h119216 or _theResult___sfd__h119921)
begin
case (guard__h111304)
2'b0:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114 =
_theResult___snd__h119216[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114 =
_theResult___sfd__h119921;
endcase
end
always@(requestR or
_theResult___snd__h119216 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555 or
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
_theResult___snd__h119216[56:5];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3557;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3555;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q114;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3561 =
52'd0;
endcase
end
always@(guard__h111304 or
_theResult___snd__h119216 or
out_sfd__h119924 or _theResult___sfd__h119921)
begin
case (guard__h111304)
2'b0, 2'b01:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 =
_theResult___snd__h119216[56:5];
2'b10:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 =
out_sfd__h119924;
2'b11:
CASE_guard11304_0b0_theResult___snd19216_BITS__ETC__q115 =
_theResult___sfd__h119921;
endcase
end
always@(guard__h120612 or sfdin__h128832 or _theResult___sfd__h129568)
begin
case (guard__h120612)
2'b0:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116 =
sfdin__h128832[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116 =
_theResult___sfd__h129568;
endcase
end
always@(requestR or
sfdin__h128832 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582 or
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
sfdin__h128832[56:5];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3584;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_requestR_BITS_1_ETC___d3582;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q116;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3588 =
52'd0;
endcase
end
always@(guard__h120612 or
sfdin__h128832 or out_sfd__h129571 or _theResult___sfd__h129568)
begin
case (guard__h120612)
2'b0, 2'b01:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 =
sfdin__h128832[56:5];
2'b10:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 =
out_sfd__h129571;
2'b11:
CASE_guard20612_0b0_sfdin28832_BITS_56_TO_5_0b_ETC__q117 =
_theResult___sfd__h129568;
endcase
end
always@(guard__h129679 or
_theResult___snd__h137615 or _theResult___sfd__h138350)
begin
case (guard__h129679)
2'b0:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118 =
_theResult___snd__h137615[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118 =
_theResult___sfd__h138350;
endcase
end
always@(requestR or
_theResult___snd__h137615 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603 or
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601 or
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118)
begin
case (requestR[194:192])
3'h1:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
_theResult___snd__h137615[56:5];
3'h2:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3603;
3'h3:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
IF_IF_IF_IF_requestR_BITS_191_TO_160_4_EQ_0xFF_ETC___d3601;
3'h4:
IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q118;
default: IF_requestR_BITS_194_TO_192_0_EQ_0x4_5_THEN_IF_ETC___d3607 =
52'd0;
endcase
end
always@(guard__h129679 or
_theResult___snd__h137615 or
out_sfd__h138353 or _theResult___sfd__h138350)
begin
case (guard__h129679)
2'b0, 2'b01:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 =
_theResult___snd__h137615[56:5];
2'b10:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 =
out_sfd__h138353;
2'b11:
CASE_guard29679_0b0_theResult___snd37615_BITS__ETC__q119 =
_theResult___sfd__h138350;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
requestR <= `BSV_ASSIGNMENT_DELAY
215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
resultR <= `BSV_ASSIGNMENT_DELAY 70'h0AAAAAAAAAAAAAAAAA;
stateR <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN;
if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN;
if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
resultR = 70'h2AAAAAAAAAAAAAAAAA;
stateR = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
endmodule // mkRISCV_FBox
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_fifo.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Julius Baxter ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "ethmac_defines.v"
`include "timescale.v"
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
almost_full, full, almost_empty, empty, cnt);
parameter DATA_WIDTH = 32;
parameter DEPTH = 8;
parameter CNT_WIDTH = 3;
input clk;
input reset;
input write;
input read;
input clear;
input [DATA_WIDTH-1:0] data_in;
output [DATA_WIDTH-1:0] data_out;
output almost_full;
output full;
output almost_empty;
output empty;
output [CNT_WIDTH-1:0] cnt;
reg [CNT_WIDTH-1:0] read_pointer;
reg [CNT_WIDTH-1:0] cnt;
reg final_read;
always @ (posedge clk or posedge reset)
begin
if(reset)
cnt <= 0;
else
if(clear)
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
else
if(read ^ write)
if(read)
cnt <= cnt - 1;
else
cnt <= cnt + 1;
end
`ifdef ETH_FIFO_GENERIC
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
// This should make the synthesis tool infer a RAM
reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg;
reg clear_reg; // Register the clear pulse
reg fallthrough_read;
reg [CNT_WIDTH-1:0] fallthrough_read_addr;
always @(posedge clk)
if (reset)
fallthrough_read <= 0;
else
fallthrough_read <= empty & write;
always @(posedge clk)
if (empty & write)
fallthrough_read_addr <= waddr;
always @(posedge clk)
if (reset)
waddr <= 0;
else if (write)
waddr <= waddr + 1;
always @(posedge clk)
if (reset)
raddr <= 0;
else if (clear)
raddr <= waddr;
else if (read | clear_reg)
raddr <= raddr + 1;
always @ (posedge clk)
if (write & ~full)
fifo[waddr] <= data_in;
always @(posedge clk)
clear_reg <= clear;
always @ (posedge clk)
if (read | clear_reg)
raddr_reg <= raddr;
else if (fallthrough_read) // To pulse RE for fall-through on Xilinx
raddr_reg <= fallthrough_read_addr;
assign data_out = fifo[raddr_reg];
always @(posedge clk)
if (reset)
final_read <= 0;
else if (final_read & read & !write)
final_read <= ~final_read;
else if ((cnt == 1) & read & !write)
final_read <= 1; // Indicate last read data has been output
assign empty = ~(|cnt);
assign almost_empty = cnt==1;
assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
//assign almost_full = &cnt[CNT_WIDTH-1:0];
assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2);
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <= 0;
else
if(clear)
// Begin read pointer at 1
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};
else
if(read & ~empty)
read_pointer <= read_pointer + 1'b1;
end
`else // !`ifdef ETH_FIFO_GENERIC
reg [CNT_WIDTH-1:0] write_pointer;
always @ (posedge clk or posedge reset)
begin
if(reset)
read_pointer <= 0;
else
if(clear)
read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};
else
if(read & ~empty)
read_pointer <= read_pointer + 1'b1;
end
always @ (posedge clk or posedge reset)
begin
if(reset)
write_pointer <= 0;
else
if(clear)
write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};
else
if(write & ~full)
write_pointer <= write_pointer + 1'b1;
end
`ifdef ETH_FIFO_XILINX
generate
if (CNT_WIDTH==4)
begin
xilinx_dist_ram_16x32 fifo
( .data_out(data_out),
.we(write & ~full),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
end // if (CNT_WIDTH==4)
else if (CNT_WIDTH==6)
begin
wire [DATA_WIDTH-1:0] data_out0;
wire [DATA_WIDTH-1:0] data_out1;
wire [DATA_WIDTH-1:0] data_out2;
wire [DATA_WIDTH-1:0] data_out3;
wire we_ram0,we_ram1,we_ram2,we_ram3;
assign we_ram0 = (write_pointer[5:4]==2'b00);
assign we_ram1 = (write_pointer[5:4]==2'b01);
assign we_ram2 = (write_pointer[5:4]==2'b10);
assign we_ram3 = (write_pointer[5:4]==2'b11);
assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 :
(read_pointer[5:4]==2'b10) ? data_out2 :
(read_pointer[5:4]==2'b01) ? data_out1 : data_out0;
xilinx_dist_ram_16x32 fifo0
( .data_out(data_out0),
.we(write & ~full & we_ram0),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
xilinx_dist_ram_16x32 fifo1
( .data_out(data_out1),
.we(write & ~full & we_ram1),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
xilinx_dist_ram_16x32 fifo2
( .data_out(data_out2),
.we(write & ~full & we_ram2),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
xilinx_dist_ram_16x32 fifo3
( .data_out(data_out3),
.we(write & ~full & we_ram3),
.data_in(data_in),
.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
.wclk(clk)
);
end // if (CNT_WIDTH==6)
endgenerate
`else // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
altera_dpram_16x32 altera_dpram_16x32_inst
(
.data (data_in),
.wren (write & ~full),
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
.clock (clk),
.q (data_out)
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
`endif // `ifdef ETH_ALTERA_ALTSYNCRAM
`endif // !`ifdef ETH_FIFO_XILINX
assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full = cnt == (DEPTH-1);
assign almost_full = &cnt[CNT_WIDTH-1:0];
`endif // !`ifdef ETH_FIFO_GENERIC
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_M_V
`define SKY130_FD_SC_LP__NAND3B_M_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_m (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_m (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_M_V
|
module MPUC541 ( CLK,DS ,ED, MPYJ,DR,DI ,DOR ,DOI );
parameter total_bits = 32;
input CLK ;
wire CLK ;
input DS ;
wire DS ;
input ED; //data strobe
input MPYJ ; //the result is multiplied by -j
wire MPYJ ;
input [total_bits-1:0] DR ;
wire signed [total_bits-1:0] DR ;
input [total_bits-1:0] DI ;
wire signed [total_bits-1:0] DI ;
output [total_bits-1:0] DOR ;
reg [total_bits-1:0] DOR ;
output [total_bits-1:0] DOI ;
reg [total_bits-1:0] DOI ;
reg signed [total_bits :0] dx5;
reg signed [total_bits :0] dx3;
reg signed [total_bits-1 :0] dii;
reg signed [total_bits-1 : 0] dt;
wire signed [total_bits+1 : 0] dx5p;
wire signed [total_bits+1 : 0] dot;
reg edd,edd2, edd3; //delayed data enable impulse
reg mpyjd,mpyjd2,mpyjd3;
reg [total_bits-1:0] doo ;
reg [total_bits-1:0] droo ;
always @(posedge CLK)
begin
if (ED) begin
edd<=DS;
edd2<=edd;
edd3<=edd2;
mpyjd<=MPYJ;
mpyjd2<=mpyjd;
mpyjd3<=mpyjd2;
if (DS) begin // 0_1000_1010_1000_11
dx5<=DR+(DR >>>2); //multiply by 5
dx3<=DR+(DR >>>1); //multiply by 3,
dt<=DR;
dii<=DI;
end
else begin
dx5<=dii+(dii >>>2); //multiply by 5
dx3<=dii +(dii >>>1); //multiply by 3
dt<=dii;
end
doo<=dot >>>2;
droo<=doo;
if (edd3)
if (mpyjd3) begin
DOR<=doo;
DOI<= - droo; end
else begin
DOR<=droo;
DOI<= doo; end
end
end
assign dx5p=(dt<<1)+(dx5>>>3); // multiply by 0_1000_101
assign dot= (dx5p+(dt>>>7) +(dx3>>>11));// multiply by // 0_1000_1010_1000_11
endmodule
|
/*
* Copyright (C) 2017 Systems Group, ETHZ
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
* http://www.apache.org/licenses/LICENSE-2.0
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
`include "../framework_defines.vh"
module sw_fifo_reader #(parameter POLL_CYCLES = 32,
parameter USER_TAG = `AFU_TAG)
(
input wire clk,
input wire rst_n,
//-------------------------------------------------//
input wire [57:0] fifo_base_addr,
input wire [3:0] fifo_addr_code,
input wire setup_fifo,
input wire reads_finished,
//--------------------- FIFO to QPI ----------------//
// TX RD
output reg [57:0] fifo_tx_rd_addr,
output reg [2+USER_TAG-1:0] fifo_tx_rd_tag,
output reg fifo_tx_rd_valid,
input wire fifo_tx_rd_ready,
// TX WR
output reg [57:0] fifo_tx_wr_addr,
output reg [`IF_TAG-1:0] fifo_tx_wr_tag,
output reg fifo_tx_wr_valid,
output reg [511:0] fifo_tx_data,
input wire fifo_tx_wr_ready,
// RX RD
input wire [2+USER_TAG-1:0] fifo_rx_rd_tag,
input wire [511:0] fifo_rx_data,
input wire fifo_rx_rd_valid,
output wire fifo_rx_rd_ready,
// RX WR
input wire fifo_rx_wr_valid,
input wire [`IF_TAG-1:0] fifo_rx_wr_tag,
///////////////////////// User Logic Interface ////////////////////
input wire [USER_TAG-1:0] usr_tx_rd_tag,
input wire usr_tx_rd_valid,
input wire [57:0] usr_tx_rd_addr,
output wire usr_tx_rd_ready,
output reg [USER_TAG-1:0] usr_rx_rd_tag,
output reg [511:0] usr_rx_data,
output reg usr_rx_rd_valid,
input wire usr_rx_rd_ready
);
///////////////////////////////// Wires Declarations ////////////////////////////
wire update_status;
wire poll_again;
wire data_available;
/////////////////////////////////////// Reg Declarations /////////////////////////
reg [31:0] numPulledCLs;
reg [31:0] otherSideUpdatedBytes;
reg [31:0] sizeInNumCL;
reg [31:0] usr_rd_count;
reg [31:0] poll_count;
reg [57:0] fifo_buff_addr;
reg [57:0] fifo_struct_base;
reg [1:0] fifo_fsm_state;
reg [1:0] poll_fsm_state;
reg update_set;
reg [57:0] poll_rd_addr;
reg poll_rd_valid;
wire poll_rd_ready;
wire [511:0] poll_rx_data;
wire poll_rx_valid;
reg [31:0] readBytes;
reg [31:0] update_status_threashold;
reg write_response_pending;
reg [31:0] lastUpdatedBytes;
reg mem_pipeline;
reg [3:0] fifo_addr_code_reg;
wire mem_fifo_valid;
reg mem_fifo_re;
wire mem_fifo_full;
wire [57+USER_TAG:0] mem_fifo_dout;
wire pipe_fifo_valid;
wire pipe_fifo_re;
wire pipe_fifo_full;
wire pipe_fifo_empty;
wire [USER_TAG-1:0] pipe_fifo_dout;
/////////////////////////////////// Local Parameters /////////////////////////////////////////
localparam [1:0]
FIFO_IDLE_STATE = 2'b00,
FIFO_REQUEST_CONFIG_STATE = 2'b01,
FIFO_READ_CONFIG_STATE = 2'b10,
FIFO_RUN_STATE = 2'b11;
localparam [1:0]
POLL_IDLE_STATE = 2'b00,
POLL_REQUEST_STATE = 2'b01,
POLL_RESP_STATE = 2'b10,
POLL_VALID_STATE = 2'b11;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// Reader Requests FIFO /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
quick_fifo #(.FIFO_WIDTH(USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) pipe_fifo(
.clk (clk),
.reset_n (rst_n),
.din (mem_fifo_dout[57+USER_TAG:58]),
.we (mem_fifo_valid & mem_pipeline & (mem_fifo_dout[57:54] == fifo_addr_code_reg)),
.re (pipe_fifo_re),
.dout (pipe_fifo_dout),
.empty (pipe_fifo_empty),
.valid (pipe_fifo_valid),
.full (pipe_fifo_full),
.count (),
.almostfull ()
);
quick_fifo #(.FIFO_WIDTH(58+USER_TAG),
.FIFO_DEPTH_BITS(9),
.FIFO_ALMOSTFULL_THRESHOLD((2**9) - 8)
) mem_fifo(
.clk (clk),
.reset_n (rst_n),
.din ({usr_tx_rd_tag, usr_tx_rd_addr}),
.we (usr_tx_rd_valid),
.re (mem_fifo_re),
.dout (mem_fifo_dout),
.empty (),
.valid (mem_fifo_valid),
.full (mem_fifo_full),
.count (),
.almostfull ()
);
assign usr_tx_rd_ready = ~mem_fifo_full;
assign pipe_fifo_re = fifo_tx_rd_ready & data_available & ~poll_rd_valid;
always @(posedge clk) begin
if(~rst_n) begin
mem_pipeline <= 0;
fifo_addr_code_reg <= 0;
end
else if(setup_fifo) begin
mem_pipeline <= 1'b1;
fifo_addr_code_reg <= fifo_addr_code;
end
end
always @(*) begin
if( mem_pipeline ) begin
if( fifo_fsm_state == FIFO_RUN_STATE ) begin
if(mem_fifo_dout[57:54] == fifo_addr_code_reg) begin
mem_fifo_re <= ~pipe_fifo_full;
end
else if(fifo_tx_rd_ready & (~pipe_fifo_empty | poll_rd_valid)) begin
mem_fifo_re <= 0;
end
else begin
mem_fifo_re <= fifo_tx_rd_ready;
end
end
else begin
mem_fifo_re <= 0;
end
end
else begin
mem_fifo_re <= fifo_tx_rd_ready;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
///////////////////////////////////////// FIFO Polling Logic /////////////////////////////////////////
///////////////////////////////////////////// ////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if(~rst_n | reads_finished) begin
otherSideUpdatedBytes <= 0;
poll_fsm_state <= 0;
poll_count <= 0;
poll_rd_addr <= 0;
poll_rd_valid <= 0;
end
else begin
case (poll_fsm_state)
POLL_IDLE_STATE: begin
if (fifo_fsm_state == FIFO_RUN_STATE) begin
poll_fsm_state <= POLL_RESP_STATE;
poll_rd_addr <= fifo_struct_base + `CRB_STRUCT_PRODUCER_LINE_OFFSET;
poll_rd_valid <= 1'b1;
end
end
POLL_REQUEST_STATE: begin // This state enable reading the producer status line
if( poll_count == POLL_CYCLES) begin
poll_rd_valid <= 1'b1;
poll_fsm_state <= POLL_RESP_STATE;
end
poll_count <= poll_count + 1'b1;
end
POLL_RESP_STATE: begin
if(poll_rd_ready) poll_rd_valid <= 1'b0;
if(poll_rx_valid) begin
poll_fsm_state <= POLL_VALID_STATE;
otherSideUpdatedBytes <= poll_rx_data[63:32];
end
poll_count <= 0;
end
POLL_VALID_STATE: begin
if(poll_again) begin
poll_fsm_state <= POLL_REQUEST_STATE;
end
end
endcase
end
end
/////////////////////////////// FIFO Status Logic /////////////////////////////////
assign poll_again = (otherSideUpdatedBytes >> 6) == numPulledCLs;
assign data_available = (otherSideUpdatedBytes >> 6) > numPulledCLs;
assign poll_rd_ready = (fifo_fsm_state == FIFO_RUN_STATE) & fifo_tx_rd_ready;
always @(posedge clk) begin
if(~rst_n) begin
sizeInNumCL <= 0;
fifo_buff_addr <= 0;
fifo_struct_base <= 0;
usr_rd_count <= 0;
fifo_fsm_state <= 0;
numPulledCLs <= 0;
fifo_tx_rd_valid <= 0;
fifo_tx_rd_addr <= 0;
fifo_tx_rd_tag <= 0;
end
else begin
case (fifo_fsm_state)
FIFO_IDLE_STATE: begin
if (setup_fifo) begin
fifo_fsm_state <= FIFO_REQUEST_CONFIG_STATE;
fifo_struct_base <= fifo_base_addr;
end
if(fifo_tx_rd_ready) begin
fifo_tx_rd_valid <= mem_fifo_valid;
fifo_tx_rd_addr <= mem_fifo_dout[57:0];
fifo_tx_rd_tag <= {2'b00, mem_fifo_dout[57+USER_TAG:58]};
end
end
FIFO_REQUEST_CONFIG_STATE: begin // This state enable reading the CRB configuration line
fifo_tx_rd_valid <= 1'b1;
fifo_tx_rd_addr <= fifo_struct_base;
fifo_tx_rd_tag <= {2'b11, {USER_TAG{1'b0}}};
fifo_fsm_state <= FIFO_READ_CONFIG_STATE;
end
FIFO_READ_CONFIG_STATE: begin // This state enable reading the CRB configuration line
if(fifo_tx_rd_ready) fifo_tx_rd_valid <= 1'b0;
if(fifo_rx_rd_valid) fifo_fsm_state <= FIFO_RUN_STATE;
fifo_buff_addr <= fifo_rx_data[63:6];
sizeInNumCL <= (fifo_rx_data[127:96] >> 6) - 1;
update_status_threashold <= fifo_rx_data[159:128];
end
FIFO_RUN_STATE: begin // This state enable writing user generated to the Buffer
if(reads_finished) begin
fifo_fsm_state <= FIFO_IDLE_STATE;
end
if(fifo_tx_rd_ready) begin
if(poll_rd_valid) begin
fifo_tx_rd_valid <= 1'b1;
fifo_tx_rd_addr <= poll_rd_addr;
fifo_tx_rd_tag <= {2'b11, {USER_TAG{1'b0}}};
end
else if(~pipe_fifo_empty) begin
if(data_available & pipe_fifo_valid) begin
fifo_tx_rd_valid <= 1'b1;
fifo_tx_rd_addr <= fifo_buff_addr + usr_rd_count;
fifo_tx_rd_tag <= {2'b01, pipe_fifo_dout};
if(usr_rd_count == sizeInNumCL) begin
usr_rd_count <= 0;
end
else begin
usr_rd_count <= usr_rd_count + 1'b1;
end
numPulledCLs <= numPulledCLs + 1'b1;
end
else begin
fifo_tx_rd_valid <= 1'b0;
end
end
else if(mem_fifo_dout[57:54] != fifo_addr_code_reg) begin
fifo_tx_rd_valid <= mem_fifo_valid;
fifo_tx_rd_addr <= mem_fifo_dout[57:0];
fifo_tx_rd_tag <= {2'b00, mem_fifo_dout[57+USER_TAG:58]};
end
else begin
fifo_tx_rd_valid <= 1'b0;
end
end
end
endcase
end
end
//////////////////////////////////////////////////////////////////////////////////////
////////// RX RD
//////////////////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n) begin
usr_rx_rd_valid <= 1'b0;
end
else if( usr_rx_rd_ready ) begin
usr_rx_rd_valid <= fifo_rx_rd_valid & ~fifo_rx_rd_tag[USER_TAG+1];
end
end
always@(posedge clk) begin
if( usr_rx_rd_ready ) begin
usr_rx_data <= fifo_rx_data;
usr_rx_rd_tag <= fifo_rx_rd_tag[USER_TAG-1:0];
end
end
//assign usr_rx_data = fifo_rx_data;
//assign usr_rx_rd_valid = fifo_rx_rd_valid & ~fifo_rx_rd_tag[USER_TAG+1];
//assign usr_rx_rd_tag = fifo_rx_rd_tag[USER_TAG-1:0];
assign fifo_rx_rd_ready = (usr_rx_rd_ready)? 1'b1 : fifo_rx_rd_valid & fifo_rx_rd_tag[USER_TAG+1];
assign poll_rx_data = fifo_rx_data;
assign poll_rx_valid = fifo_rx_rd_valid & fifo_rx_rd_tag[USER_TAG+1];
/////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(~rst_n)begin
readBytes <= 0;
end
else if(fifo_rx_rd_valid & ~fifo_rx_rd_tag[USER_TAG+1] & fifo_rx_rd_tag[USER_TAG]) begin
readBytes <= readBytes + 64;
end
end
//////////////////////////////////////////////////////////////////////////////////////
///////////////////////////// FIFO Consumer Status Update ////////////////////////////
////////////////////////////// TX WR Requests Generation ////////////////////////////
always @(posedge clk) begin
if(~rst_n) begin
fifo_tx_wr_addr <= 0;
fifo_tx_wr_valid <= 0;
fifo_tx_wr_tag <= 0;
update_set <= 1'b0;
lastUpdatedBytes <= 0;
write_response_pending <= 0;
end
else begin
if(fifo_rx_wr_valid)
write_response_pending <= 1'b0;
else if(fifo_tx_wr_ready & fifo_tx_wr_valid)
write_response_pending <= 1'b1;
if(fifo_tx_wr_ready) begin
if(update_status & ~write_response_pending) begin
lastUpdatedBytes <= readBytes;
fifo_tx_data <= {448'b0, readBytes, usr_rd_count};
fifo_tx_wr_addr <= fifo_struct_base + `CRB_STRUCT_CONSUMER_LINE_OFFSET;
fifo_tx_wr_tag <= 0;
fifo_tx_wr_valid <= 1'b1;
end
else begin
fifo_tx_wr_valid <= 0;
end
end
end
end
assign update_status = ((readBytes - lastUpdatedBytes) > update_status_threashold);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_Mat2AXIvideo (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
img_rows_V_read,
img_cols_V_read,
img_data_stream_0_V_dout,
img_data_stream_0_V_empty_n,
img_data_stream_0_V_read,
img_data_stream_1_V_dout,
img_data_stream_1_V_empty_n,
img_data_stream_1_V_read,
img_data_stream_2_V_dout,
img_data_stream_2_V_empty_n,
img_data_stream_2_V_read,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 4'b1;
parameter ap_ST_st2_fsm_1 = 4'b10;
parameter ap_ST_pp0_stg0_fsm_2 = 4'b100;
parameter ap_ST_st5_fsm_3 = 4'b1000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv12_0 = 12'b000000000000;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv13_1FFF = 13'b1111111111111;
parameter ap_const_lv12_1 = 12'b1;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] img_rows_V_read;
input [11:0] img_cols_V_read;
input [7:0] img_data_stream_0_V_dout;
input img_data_stream_0_V_empty_n;
output img_data_stream_0_V_read;
input [7:0] img_data_stream_1_V_dout;
input img_data_stream_1_V_empty_n;
output img_data_stream_1_V_read;
input [7:0] img_data_stream_2_V_dout;
input img_data_stream_2_V_empty_n;
output img_data_stream_2_V_read;
output [31:0] OUTPUT_STREAM_TDATA;
output OUTPUT_STREAM_TVALID;
input OUTPUT_STREAM_TREADY;
output [3:0] OUTPUT_STREAM_TKEEP;
output [3:0] OUTPUT_STREAM_TSTRB;
output [0:0] OUTPUT_STREAM_TUSER;
output [0:0] OUTPUT_STREAM_TLAST;
output [0:0] OUTPUT_STREAM_TID;
output [0:0] OUTPUT_STREAM_TDEST;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg img_data_stream_0_V_read;
reg img_data_stream_1_V_read;
reg img_data_stream_2_V_read;
reg OUTPUT_STREAM_TVALID;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [3:0] ap_CS_fsm = 4'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_23;
reg [11:0] p_3_reg_170;
reg ap_sig_bdd_60;
wire [12:0] op2_assign_fu_186_p2;
reg [12:0] op2_assign_reg_267;
wire [0:0] exitcond3_fu_197_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_74;
wire [11:0] i_V_fu_202_p2;
reg [11:0] i_V_reg_276;
wire [0:0] exitcond4_fu_208_p2;
reg [0:0] exitcond4_reg_281;
reg ap_sig_cseq_ST_pp0_stg0_fsm_2;
reg ap_sig_bdd_85;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_sig_bdd_99;
reg ap_sig_ioackin_OUTPUT_STREAM_TREADY;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
wire [11:0] j_V_fu_213_p2;
wire [0:0] axi_last_V_fu_223_p2;
reg [0:0] axi_last_V_reg_290;
reg [11:0] p_s_reg_159;
reg ap_sig_cseq_ST_st5_fsm_3;
reg ap_sig_bdd_130;
reg [0:0] tmp_user_V_fu_96;
reg ap_reg_ioackin_OUTPUT_STREAM_TREADY = 1'b0;
wire [12:0] tmp_cast_fu_182_p1;
wire [12:0] tmp_cast_77_fu_219_p1;
reg [3:0] ap_NS_fsm;
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ioackin_OUTPUT_STREAM_TREADY
if (ap_rst == 1'b1) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_99 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_logic_1 == OUTPUT_STREAM_TREADY))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
p_3_reg_170 <= j_V_fu_213_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
p_3_reg_170 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_3)) begin
p_s_reg_159 <= i_V_reg_276;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
p_s_reg_159 <= ap_const_lv12_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
tmp_user_V_fu_96 <= ap_const_lv1_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
tmp_user_V_fu_96 <= ap_const_lv1_1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
axi_last_V_reg_290 <= axi_last_V_fu_223_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
exitcond4_reg_281 <= exitcond4_fu_208_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
i_V_reg_276 <= i_V_fu_202_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_60)) begin
op2_assign_reg_267 <= op2_assign_fu_186_p2;
end
end
/// OUTPUT_STREAM_TVALID assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_reg_ppiten_pp0_it1 or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~(ap_sig_bdd_99 & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & (ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY))) begin
OUTPUT_STREAM_TVALID = ap_const_logic_1;
end else begin
OUTPUT_STREAM_TVALID = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or exitcond3_fu_197_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (exitcond3_fu_197_p2 or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(exitcond3_fu_197_p2 == ap_const_lv1_0))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_2 assign process. ///
always @ (ap_sig_bdd_85)
begin
if (ap_sig_bdd_85) begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_74)
begin
if (ap_sig_bdd_74) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_3 assign process. ///
always @ (ap_sig_bdd_130)
begin
if (ap_sig_bdd_130) begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (OUTPUT_STREAM_TREADY or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY)) begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = OUTPUT_STREAM_TREADY;
end else begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = ap_const_logic_1;
end
end
/// img_data_stream_0_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_0_V_read = ap_const_logic_1;
end else begin
img_data_stream_0_V_read = ap_const_logic_0;
end
end
/// img_data_stream_1_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_1_V_read = ap_const_logic_1;
end else begin
img_data_stream_1_V_read = ap_const_logic_0;
end
end
/// img_data_stream_2_V_read assign process. ///
always @ (exitcond4_reg_281 or ap_sig_cseq_ST_pp0_stg0_fsm_2 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_2) & (exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
img_data_stream_2_V_read = ap_const_logic_1;
end else begin
img_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_60 or exitcond3_fu_197_p2 or exitcond4_fu_208_p2 or exitcond4_reg_281 or ap_reg_ppiten_pp0_it0 or ap_sig_bdd_99 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp0_it1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_60) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(exitcond3_fu_197_p2 == ap_const_lv1_0)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_pp0_stg0_fsm_2 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~((ap_sig_bdd_99 | ((exitcond4_reg_281 == ap_const_lv1_0) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY))) & (ap_const_logic_1 == ap_reg_ppiten_pp0_it1)) & ~(exitcond4_fu_208_p2 == ap_const_lv1_0))) begin
ap_NS_fsm = ap_ST_st5_fsm_3;
end else begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_2;
end
end
ap_ST_st5_fsm_3 :
begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign OUTPUT_STREAM_TDATA = {{{{{{ap_const_lv8_FF}, {img_data_stream_2_V_dout}}}, {img_data_stream_1_V_dout}}}, {img_data_stream_0_V_dout}};
assign OUTPUT_STREAM_TDEST = ap_const_lv1_0;
assign OUTPUT_STREAM_TID = ap_const_lv1_0;
assign OUTPUT_STREAM_TKEEP = ap_const_lv4_F;
assign OUTPUT_STREAM_TLAST = axi_last_V_reg_290;
assign OUTPUT_STREAM_TSTRB = ap_const_lv4_0;
assign OUTPUT_STREAM_TUSER = tmp_user_V_fu_96;
/// ap_sig_bdd_130 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_130 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_23 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_23 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_60 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_60 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_74 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_74 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_85 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_85 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_99 assign process. ///
always @ (img_data_stream_0_V_empty_n or img_data_stream_1_V_empty_n or img_data_stream_2_V_empty_n or exitcond4_reg_281)
begin
ap_sig_bdd_99 = (((img_data_stream_0_V_empty_n == ap_const_logic_0) & (exitcond4_reg_281 == ap_const_lv1_0)) | ((exitcond4_reg_281 == ap_const_lv1_0) & (img_data_stream_1_V_empty_n == ap_const_logic_0)) | ((exitcond4_reg_281 == ap_const_lv1_0) & (img_data_stream_2_V_empty_n == ap_const_logic_0)));
end
assign axi_last_V_fu_223_p2 = (tmp_cast_77_fu_219_p1 == op2_assign_reg_267? 1'b1: 1'b0);
assign exitcond3_fu_197_p2 = (p_s_reg_159 == img_rows_V_read? 1'b1: 1'b0);
assign exitcond4_fu_208_p2 = (p_3_reg_170 == img_cols_V_read? 1'b1: 1'b0);
assign i_V_fu_202_p2 = (p_s_reg_159 + ap_const_lv12_1);
assign j_V_fu_213_p2 = (p_3_reg_170 + ap_const_lv12_1);
assign op2_assign_fu_186_p2 = ($signed(tmp_cast_fu_182_p1) + $signed(ap_const_lv13_1FFF));
assign tmp_cast_77_fu_219_p1 = p_3_reg_170;
assign tmp_cast_fu_182_p1 = img_cols_V_read;
endmodule //image_filter_Mat2AXIvideo
|
//Legal Notice: (C)2020 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module wasca_nios2_gen2_0_cpu_test_bench (
// inputs:
D_iw,
D_iw_op,
D_iw_opx,
D_valid,
E_valid,
F_pcb,
F_valid,
R_ctrl_ld,
R_ctrl_ld_non_io,
R_dst_regnum,
R_wr_dst_reg,
W_valid,
W_vinst,
W_wr_data,
av_ld_data_aligned_unfiltered,
clk,
d_address,
d_byteenable,
d_read,
d_write,
i_address,
i_read,
i_readdata,
i_waitrequest,
reset_n,
// outputs:
av_ld_data_aligned_filtered,
test_has_ended
)
;
output [ 31: 0] av_ld_data_aligned_filtered;
output test_has_ended;
input [ 31: 0] D_iw;
input [ 5: 0] D_iw_op;
input [ 5: 0] D_iw_opx;
input D_valid;
input E_valid;
input [ 27: 0] F_pcb;
input F_valid;
input R_ctrl_ld;
input R_ctrl_ld_non_io;
input [ 4: 0] R_dst_regnum;
input R_wr_dst_reg;
input W_valid;
input [ 71: 0] W_vinst;
input [ 31: 0] W_wr_data;
input [ 31: 0] av_ld_data_aligned_unfiltered;
input clk;
input [ 27: 0] d_address;
input [ 3: 0] d_byteenable;
input d_read;
input d_write;
input [ 27: 0] i_address;
input i_read;
input [ 31: 0] i_readdata;
input i_waitrequest;
input reset_n;
wire D_is_opx_inst;
wire D_op_add;
wire D_op_addi;
wire D_op_and;
wire D_op_andhi;
wire D_op_andi;
wire D_op_beq;
wire D_op_bge;
wire D_op_bgeu;
wire D_op_blt;
wire D_op_bltu;
wire D_op_bne;
wire D_op_br;
wire D_op_break;
wire D_op_bret;
wire D_op_call;
wire D_op_callr;
wire D_op_cmpeq;
wire D_op_cmpeqi;
wire D_op_cmpge;
wire D_op_cmpgei;
wire D_op_cmpgeu;
wire D_op_cmpgeui;
wire D_op_cmplt;
wire D_op_cmplti;
wire D_op_cmpltu;
wire D_op_cmpltui;
wire D_op_cmpne;
wire D_op_cmpnei;
wire D_op_crst;
wire D_op_custom;
wire D_op_div;
wire D_op_divu;
wire D_op_eret;
wire D_op_flushd;
wire D_op_flushda;
wire D_op_flushi;
wire D_op_flushp;
wire D_op_hbreak;
wire D_op_initd;
wire D_op_initda;
wire D_op_initi;
wire D_op_intr;
wire D_op_jmp;
wire D_op_jmpi;
wire D_op_ldb;
wire D_op_ldbio;
wire D_op_ldbu;
wire D_op_ldbuio;
wire D_op_ldh;
wire D_op_ldhio;
wire D_op_ldhu;
wire D_op_ldhuio;
wire D_op_ldl;
wire D_op_ldw;
wire D_op_ldwio;
wire D_op_mul;
wire D_op_muli;
wire D_op_mulxss;
wire D_op_mulxsu;
wire D_op_mulxuu;
wire D_op_nextpc;
wire D_op_nor;
wire D_op_op_rsv02;
wire D_op_op_rsv09;
wire D_op_op_rsv10;
wire D_op_op_rsv17;
wire D_op_op_rsv18;
wire D_op_op_rsv25;
wire D_op_op_rsv26;
wire D_op_op_rsv33;
wire D_op_op_rsv34;
wire D_op_op_rsv41;
wire D_op_op_rsv42;
wire D_op_op_rsv49;
wire D_op_op_rsv57;
wire D_op_op_rsv61;
wire D_op_op_rsv62;
wire D_op_op_rsv63;
wire D_op_opx_rsv00;
wire D_op_opx_rsv10;
wire D_op_opx_rsv15;
wire D_op_opx_rsv17;
wire D_op_opx_rsv21;
wire D_op_opx_rsv25;
wire D_op_opx_rsv33;
wire D_op_opx_rsv34;
wire D_op_opx_rsv35;
wire D_op_opx_rsv42;
wire D_op_opx_rsv43;
wire D_op_opx_rsv44;
wire D_op_opx_rsv47;
wire D_op_opx_rsv50;
wire D_op_opx_rsv51;
wire D_op_opx_rsv55;
wire D_op_opx_rsv56;
wire D_op_opx_rsv60;
wire D_op_opx_rsv63;
wire D_op_or;
wire D_op_orhi;
wire D_op_ori;
wire D_op_rdctl;
wire D_op_rdprs;
wire D_op_ret;
wire D_op_rol;
wire D_op_roli;
wire D_op_ror;
wire D_op_sll;
wire D_op_slli;
wire D_op_sra;
wire D_op_srai;
wire D_op_srl;
wire D_op_srli;
wire D_op_stb;
wire D_op_stbio;
wire D_op_stc;
wire D_op_sth;
wire D_op_sthio;
wire D_op_stw;
wire D_op_stwio;
wire D_op_sub;
wire D_op_sync;
wire D_op_trap;
wire D_op_wrctl;
wire D_op_wrprs;
wire D_op_xor;
wire D_op_xorhi;
wire D_op_xori;
wire [ 31: 0] av_ld_data_aligned_filtered;
wire av_ld_data_aligned_unfiltered_0_is_x;
wire av_ld_data_aligned_unfiltered_10_is_x;
wire av_ld_data_aligned_unfiltered_11_is_x;
wire av_ld_data_aligned_unfiltered_12_is_x;
wire av_ld_data_aligned_unfiltered_13_is_x;
wire av_ld_data_aligned_unfiltered_14_is_x;
wire av_ld_data_aligned_unfiltered_15_is_x;
wire av_ld_data_aligned_unfiltered_16_is_x;
wire av_ld_data_aligned_unfiltered_17_is_x;
wire av_ld_data_aligned_unfiltered_18_is_x;
wire av_ld_data_aligned_unfiltered_19_is_x;
wire av_ld_data_aligned_unfiltered_1_is_x;
wire av_ld_data_aligned_unfiltered_20_is_x;
wire av_ld_data_aligned_unfiltered_21_is_x;
wire av_ld_data_aligned_unfiltered_22_is_x;
wire av_ld_data_aligned_unfiltered_23_is_x;
wire av_ld_data_aligned_unfiltered_24_is_x;
wire av_ld_data_aligned_unfiltered_25_is_x;
wire av_ld_data_aligned_unfiltered_26_is_x;
wire av_ld_data_aligned_unfiltered_27_is_x;
wire av_ld_data_aligned_unfiltered_28_is_x;
wire av_ld_data_aligned_unfiltered_29_is_x;
wire av_ld_data_aligned_unfiltered_2_is_x;
wire av_ld_data_aligned_unfiltered_30_is_x;
wire av_ld_data_aligned_unfiltered_31_is_x;
wire av_ld_data_aligned_unfiltered_3_is_x;
wire av_ld_data_aligned_unfiltered_4_is_x;
wire av_ld_data_aligned_unfiltered_5_is_x;
wire av_ld_data_aligned_unfiltered_6_is_x;
wire av_ld_data_aligned_unfiltered_7_is_x;
wire av_ld_data_aligned_unfiltered_8_is_x;
wire av_ld_data_aligned_unfiltered_9_is_x;
wire test_has_ended;
assign D_op_call = D_iw_op == 0;
assign D_op_jmpi = D_iw_op == 1;
assign D_op_op_rsv02 = D_iw_op == 2;
assign D_op_ldbu = D_iw_op == 3;
assign D_op_addi = D_iw_op == 4;
assign D_op_stb = D_iw_op == 5;
assign D_op_br = D_iw_op == 6;
assign D_op_ldb = D_iw_op == 7;
assign D_op_cmpgei = D_iw_op == 8;
assign D_op_op_rsv09 = D_iw_op == 9;
assign D_op_op_rsv10 = D_iw_op == 10;
assign D_op_ldhu = D_iw_op == 11;
assign D_op_andi = D_iw_op == 12;
assign D_op_sth = D_iw_op == 13;
assign D_op_bge = D_iw_op == 14;
assign D_op_ldh = D_iw_op == 15;
assign D_op_cmplti = D_iw_op == 16;
assign D_op_op_rsv17 = D_iw_op == 17;
assign D_op_op_rsv18 = D_iw_op == 18;
assign D_op_initda = D_iw_op == 19;
assign D_op_ori = D_iw_op == 20;
assign D_op_stw = D_iw_op == 21;
assign D_op_blt = D_iw_op == 22;
assign D_op_ldw = D_iw_op == 23;
assign D_op_cmpnei = D_iw_op == 24;
assign D_op_op_rsv25 = D_iw_op == 25;
assign D_op_op_rsv26 = D_iw_op == 26;
assign D_op_flushda = D_iw_op == 27;
assign D_op_xori = D_iw_op == 28;
assign D_op_stc = D_iw_op == 29;
assign D_op_bne = D_iw_op == 30;
assign D_op_ldl = D_iw_op == 31;
assign D_op_cmpeqi = D_iw_op == 32;
assign D_op_op_rsv33 = D_iw_op == 33;
assign D_op_op_rsv34 = D_iw_op == 34;
assign D_op_ldbuio = D_iw_op == 35;
assign D_op_muli = D_iw_op == 36;
assign D_op_stbio = D_iw_op == 37;
assign D_op_beq = D_iw_op == 38;
assign D_op_ldbio = D_iw_op == 39;
assign D_op_cmpgeui = D_iw_op == 40;
assign D_op_op_rsv41 = D_iw_op == 41;
assign D_op_op_rsv42 = D_iw_op == 42;
assign D_op_ldhuio = D_iw_op == 43;
assign D_op_andhi = D_iw_op == 44;
assign D_op_sthio = D_iw_op == 45;
assign D_op_bgeu = D_iw_op == 46;
assign D_op_ldhio = D_iw_op == 47;
assign D_op_cmpltui = D_iw_op == 48;
assign D_op_op_rsv49 = D_iw_op == 49;
assign D_op_custom = D_iw_op == 50;
assign D_op_initd = D_iw_op == 51;
assign D_op_orhi = D_iw_op == 52;
assign D_op_stwio = D_iw_op == 53;
assign D_op_bltu = D_iw_op == 54;
assign D_op_ldwio = D_iw_op == 55;
assign D_op_rdprs = D_iw_op == 56;
assign D_op_op_rsv57 = D_iw_op == 57;
assign D_op_flushd = D_iw_op == 59;
assign D_op_xorhi = D_iw_op == 60;
assign D_op_op_rsv61 = D_iw_op == 61;
assign D_op_op_rsv62 = D_iw_op == 62;
assign D_op_op_rsv63 = D_iw_op == 63;
assign D_op_opx_rsv00 = (D_iw_opx == 0) & D_is_opx_inst;
assign D_op_eret = (D_iw_opx == 1) & D_is_opx_inst;
assign D_op_roli = (D_iw_opx == 2) & D_is_opx_inst;
assign D_op_rol = (D_iw_opx == 3) & D_is_opx_inst;
assign D_op_flushp = (D_iw_opx == 4) & D_is_opx_inst;
assign D_op_ret = (D_iw_opx == 5) & D_is_opx_inst;
assign D_op_nor = (D_iw_opx == 6) & D_is_opx_inst;
assign D_op_mulxuu = (D_iw_opx == 7) & D_is_opx_inst;
assign D_op_cmpge = (D_iw_opx == 8) & D_is_opx_inst;
assign D_op_bret = (D_iw_opx == 9) & D_is_opx_inst;
assign D_op_opx_rsv10 = (D_iw_opx == 10) & D_is_opx_inst;
assign D_op_ror = (D_iw_opx == 11) & D_is_opx_inst;
assign D_op_flushi = (D_iw_opx == 12) & D_is_opx_inst;
assign D_op_jmp = (D_iw_opx == 13) & D_is_opx_inst;
assign D_op_and = (D_iw_opx == 14) & D_is_opx_inst;
assign D_op_opx_rsv15 = (D_iw_opx == 15) & D_is_opx_inst;
assign D_op_cmplt = (D_iw_opx == 16) & D_is_opx_inst;
assign D_op_opx_rsv17 = (D_iw_opx == 17) & D_is_opx_inst;
assign D_op_slli = (D_iw_opx == 18) & D_is_opx_inst;
assign D_op_sll = (D_iw_opx == 19) & D_is_opx_inst;
assign D_op_wrprs = (D_iw_opx == 20) & D_is_opx_inst;
assign D_op_opx_rsv21 = (D_iw_opx == 21) & D_is_opx_inst;
assign D_op_or = (D_iw_opx == 22) & D_is_opx_inst;
assign D_op_mulxsu = (D_iw_opx == 23) & D_is_opx_inst;
assign D_op_cmpne = (D_iw_opx == 24) & D_is_opx_inst;
assign D_op_opx_rsv25 = (D_iw_opx == 25) & D_is_opx_inst;
assign D_op_srli = (D_iw_opx == 26) & D_is_opx_inst;
assign D_op_srl = (D_iw_opx == 27) & D_is_opx_inst;
assign D_op_nextpc = (D_iw_opx == 28) & D_is_opx_inst;
assign D_op_callr = (D_iw_opx == 29) & D_is_opx_inst;
assign D_op_xor = (D_iw_opx == 30) & D_is_opx_inst;
assign D_op_mulxss = (D_iw_opx == 31) & D_is_opx_inst;
assign D_op_cmpeq = (D_iw_opx == 32) & D_is_opx_inst;
assign D_op_opx_rsv33 = (D_iw_opx == 33) & D_is_opx_inst;
assign D_op_opx_rsv34 = (D_iw_opx == 34) & D_is_opx_inst;
assign D_op_opx_rsv35 = (D_iw_opx == 35) & D_is_opx_inst;
assign D_op_divu = (D_iw_opx == 36) & D_is_opx_inst;
assign D_op_div = (D_iw_opx == 37) & D_is_opx_inst;
assign D_op_rdctl = (D_iw_opx == 38) & D_is_opx_inst;
assign D_op_mul = (D_iw_opx == 39) & D_is_opx_inst;
assign D_op_cmpgeu = (D_iw_opx == 40) & D_is_opx_inst;
assign D_op_initi = (D_iw_opx == 41) & D_is_opx_inst;
assign D_op_opx_rsv42 = (D_iw_opx == 42) & D_is_opx_inst;
assign D_op_opx_rsv43 = (D_iw_opx == 43) & D_is_opx_inst;
assign D_op_opx_rsv44 = (D_iw_opx == 44) & D_is_opx_inst;
assign D_op_trap = (D_iw_opx == 45) & D_is_opx_inst;
assign D_op_wrctl = (D_iw_opx == 46) & D_is_opx_inst;
assign D_op_opx_rsv47 = (D_iw_opx == 47) & D_is_opx_inst;
assign D_op_cmpltu = (D_iw_opx == 48) & D_is_opx_inst;
assign D_op_add = (D_iw_opx == 49) & D_is_opx_inst;
assign D_op_opx_rsv50 = (D_iw_opx == 50) & D_is_opx_inst;
assign D_op_opx_rsv51 = (D_iw_opx == 51) & D_is_opx_inst;
assign D_op_break = (D_iw_opx == 52) & D_is_opx_inst;
assign D_op_hbreak = (D_iw_opx == 53) & D_is_opx_inst;
assign D_op_sync = (D_iw_opx == 54) & D_is_opx_inst;
assign D_op_opx_rsv55 = (D_iw_opx == 55) & D_is_opx_inst;
assign D_op_opx_rsv56 = (D_iw_opx == 56) & D_is_opx_inst;
assign D_op_sub = (D_iw_opx == 57) & D_is_opx_inst;
assign D_op_srai = (D_iw_opx == 58) & D_is_opx_inst;
assign D_op_sra = (D_iw_opx == 59) & D_is_opx_inst;
assign D_op_opx_rsv60 = (D_iw_opx == 60) & D_is_opx_inst;
assign D_op_intr = (D_iw_opx == 61) & D_is_opx_inst;
assign D_op_crst = (D_iw_opx == 62) & D_is_opx_inst;
assign D_op_opx_rsv63 = (D_iw_opx == 63) & D_is_opx_inst;
assign D_is_opx_inst = D_iw_op == 58;
assign test_has_ended = 1'b0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Clearing 'X' data bits
assign av_ld_data_aligned_unfiltered_0_is_x = ^(av_ld_data_aligned_unfiltered[0]) === 1'bx;
assign av_ld_data_aligned_filtered[0] = (av_ld_data_aligned_unfiltered_0_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[0];
assign av_ld_data_aligned_unfiltered_1_is_x = ^(av_ld_data_aligned_unfiltered[1]) === 1'bx;
assign av_ld_data_aligned_filtered[1] = (av_ld_data_aligned_unfiltered_1_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[1];
assign av_ld_data_aligned_unfiltered_2_is_x = ^(av_ld_data_aligned_unfiltered[2]) === 1'bx;
assign av_ld_data_aligned_filtered[2] = (av_ld_data_aligned_unfiltered_2_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[2];
assign av_ld_data_aligned_unfiltered_3_is_x = ^(av_ld_data_aligned_unfiltered[3]) === 1'bx;
assign av_ld_data_aligned_filtered[3] = (av_ld_data_aligned_unfiltered_3_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[3];
assign av_ld_data_aligned_unfiltered_4_is_x = ^(av_ld_data_aligned_unfiltered[4]) === 1'bx;
assign av_ld_data_aligned_filtered[4] = (av_ld_data_aligned_unfiltered_4_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[4];
assign av_ld_data_aligned_unfiltered_5_is_x = ^(av_ld_data_aligned_unfiltered[5]) === 1'bx;
assign av_ld_data_aligned_filtered[5] = (av_ld_data_aligned_unfiltered_5_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[5];
assign av_ld_data_aligned_unfiltered_6_is_x = ^(av_ld_data_aligned_unfiltered[6]) === 1'bx;
assign av_ld_data_aligned_filtered[6] = (av_ld_data_aligned_unfiltered_6_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[6];
assign av_ld_data_aligned_unfiltered_7_is_x = ^(av_ld_data_aligned_unfiltered[7]) === 1'bx;
assign av_ld_data_aligned_filtered[7] = (av_ld_data_aligned_unfiltered_7_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[7];
assign av_ld_data_aligned_unfiltered_8_is_x = ^(av_ld_data_aligned_unfiltered[8]) === 1'bx;
assign av_ld_data_aligned_filtered[8] = (av_ld_data_aligned_unfiltered_8_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[8];
assign av_ld_data_aligned_unfiltered_9_is_x = ^(av_ld_data_aligned_unfiltered[9]) === 1'bx;
assign av_ld_data_aligned_filtered[9] = (av_ld_data_aligned_unfiltered_9_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[9];
assign av_ld_data_aligned_unfiltered_10_is_x = ^(av_ld_data_aligned_unfiltered[10]) === 1'bx;
assign av_ld_data_aligned_filtered[10] = (av_ld_data_aligned_unfiltered_10_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[10];
assign av_ld_data_aligned_unfiltered_11_is_x = ^(av_ld_data_aligned_unfiltered[11]) === 1'bx;
assign av_ld_data_aligned_filtered[11] = (av_ld_data_aligned_unfiltered_11_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[11];
assign av_ld_data_aligned_unfiltered_12_is_x = ^(av_ld_data_aligned_unfiltered[12]) === 1'bx;
assign av_ld_data_aligned_filtered[12] = (av_ld_data_aligned_unfiltered_12_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[12];
assign av_ld_data_aligned_unfiltered_13_is_x = ^(av_ld_data_aligned_unfiltered[13]) === 1'bx;
assign av_ld_data_aligned_filtered[13] = (av_ld_data_aligned_unfiltered_13_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[13];
assign av_ld_data_aligned_unfiltered_14_is_x = ^(av_ld_data_aligned_unfiltered[14]) === 1'bx;
assign av_ld_data_aligned_filtered[14] = (av_ld_data_aligned_unfiltered_14_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[14];
assign av_ld_data_aligned_unfiltered_15_is_x = ^(av_ld_data_aligned_unfiltered[15]) === 1'bx;
assign av_ld_data_aligned_filtered[15] = (av_ld_data_aligned_unfiltered_15_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[15];
assign av_ld_data_aligned_unfiltered_16_is_x = ^(av_ld_data_aligned_unfiltered[16]) === 1'bx;
assign av_ld_data_aligned_filtered[16] = (av_ld_data_aligned_unfiltered_16_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[16];
assign av_ld_data_aligned_unfiltered_17_is_x = ^(av_ld_data_aligned_unfiltered[17]) === 1'bx;
assign av_ld_data_aligned_filtered[17] = (av_ld_data_aligned_unfiltered_17_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[17];
assign av_ld_data_aligned_unfiltered_18_is_x = ^(av_ld_data_aligned_unfiltered[18]) === 1'bx;
assign av_ld_data_aligned_filtered[18] = (av_ld_data_aligned_unfiltered_18_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[18];
assign av_ld_data_aligned_unfiltered_19_is_x = ^(av_ld_data_aligned_unfiltered[19]) === 1'bx;
assign av_ld_data_aligned_filtered[19] = (av_ld_data_aligned_unfiltered_19_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[19];
assign av_ld_data_aligned_unfiltered_20_is_x = ^(av_ld_data_aligned_unfiltered[20]) === 1'bx;
assign av_ld_data_aligned_filtered[20] = (av_ld_data_aligned_unfiltered_20_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[20];
assign av_ld_data_aligned_unfiltered_21_is_x = ^(av_ld_data_aligned_unfiltered[21]) === 1'bx;
assign av_ld_data_aligned_filtered[21] = (av_ld_data_aligned_unfiltered_21_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[21];
assign av_ld_data_aligned_unfiltered_22_is_x = ^(av_ld_data_aligned_unfiltered[22]) === 1'bx;
assign av_ld_data_aligned_filtered[22] = (av_ld_data_aligned_unfiltered_22_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[22];
assign av_ld_data_aligned_unfiltered_23_is_x = ^(av_ld_data_aligned_unfiltered[23]) === 1'bx;
assign av_ld_data_aligned_filtered[23] = (av_ld_data_aligned_unfiltered_23_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[23];
assign av_ld_data_aligned_unfiltered_24_is_x = ^(av_ld_data_aligned_unfiltered[24]) === 1'bx;
assign av_ld_data_aligned_filtered[24] = (av_ld_data_aligned_unfiltered_24_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[24];
assign av_ld_data_aligned_unfiltered_25_is_x = ^(av_ld_data_aligned_unfiltered[25]) === 1'bx;
assign av_ld_data_aligned_filtered[25] = (av_ld_data_aligned_unfiltered_25_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[25];
assign av_ld_data_aligned_unfiltered_26_is_x = ^(av_ld_data_aligned_unfiltered[26]) === 1'bx;
assign av_ld_data_aligned_filtered[26] = (av_ld_data_aligned_unfiltered_26_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[26];
assign av_ld_data_aligned_unfiltered_27_is_x = ^(av_ld_data_aligned_unfiltered[27]) === 1'bx;
assign av_ld_data_aligned_filtered[27] = (av_ld_data_aligned_unfiltered_27_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[27];
assign av_ld_data_aligned_unfiltered_28_is_x = ^(av_ld_data_aligned_unfiltered[28]) === 1'bx;
assign av_ld_data_aligned_filtered[28] = (av_ld_data_aligned_unfiltered_28_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[28];
assign av_ld_data_aligned_unfiltered_29_is_x = ^(av_ld_data_aligned_unfiltered[29]) === 1'bx;
assign av_ld_data_aligned_filtered[29] = (av_ld_data_aligned_unfiltered_29_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[29];
assign av_ld_data_aligned_unfiltered_30_is_x = ^(av_ld_data_aligned_unfiltered[30]) === 1'bx;
assign av_ld_data_aligned_filtered[30] = (av_ld_data_aligned_unfiltered_30_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[30];
assign av_ld_data_aligned_unfiltered_31_is_x = ^(av_ld_data_aligned_unfiltered[31]) === 1'bx;
assign av_ld_data_aligned_filtered[31] = (av_ld_data_aligned_unfiltered_31_is_x & (R_ctrl_ld_non_io)) ? 1'b0 : av_ld_data_aligned_unfiltered[31];
always @(posedge clk)
begin
if (reset_n)
if (^(F_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/F_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(D_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/D_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(E_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/E_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(W_valid) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_valid is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid)
if (^(R_wr_dst_reg) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_wr_dst_reg is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(R_dst_regnum) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/R_dst_regnum is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_write) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_write is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write)
if (^(d_byteenable) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_byteenable is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (d_write | d_read)
if (^(d_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(d_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/d_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk)
begin
if (reset_n)
if (^(i_read) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_read is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read)
if (^(i_address) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_address is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (i_read & ~i_waitrequest)
if (^(i_readdata) === 1'bx)
begin
$write("%0d ns: ERROR: wasca_nios2_gen2_0_cpu_test_bench/i_readdata is 'x'\n", $time);
$stop;
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_ctrl_ld)
if (^(av_ld_data_aligned_unfiltered) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/av_ld_data_aligned_unfiltered is 'x'\n", $time);
end
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
end
else if (W_valid & R_wr_dst_reg)
if (^(W_wr_data) === 1'bx)
begin
$write("%0d ns: WARNING: wasca_nios2_gen2_0_cpu_test_bench/W_wr_data is 'x'\n", $time);
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
//
// assign av_ld_data_aligned_filtered = av_ld_data_aligned_unfiltered;
//
//synthesis read_comments_as_HDL off
endmodule
|
// This module implements a SPI byte-oriented master interface with
// flow-control.
//
// (c) 2005 Samuel Tardieu <[email protected]>
//
// Expected arguments:
// - Inputs
// - clock: it will be divided (see SPICLOCKDIV in the code)
// - reset: it must be maintained at least SPICLOCKDIV full cycles
// - outbuffer0 .. outbufferF: the data to write
// - towrite: the number of bytes to write, starting from outbuffer0
// - toread: the number of bytes to read, starting from inbuffer0
// - enable: a signal indicating that towrite has changed
// and that the SPI dialog must be initiated; this signal is
// sampled on a positive clock edge and must be maintained
// until the irq has been acknowledged
// - sdi: SPI data input
// - rts: peer is ready to send or receive data when a low pulse
// is generated
// - statusread: a bit toggled each time status is read
// - picintr: a bit toggle each time status has changed
// - Outputs
// - inbuffer0 .. inbufferF: the data that has been read
// - sclk: SPI clock
// - sdo: SPI data output
// - irq: a signal indicating that the requested operation has
// completed; it will go down when enable goes down
// - statusirq: signal a status change
// - status: the current status
// The SPI clock will be clock/SPICLOCKDIV/2. For example, for an input
// clock at 60MHz and a SPI clock at 5MHz use a 6 divisor.
`define SPICLOCKDIV 6
// Status read command
`define STATUS_READ 8'hAA
module spi (clock, reset, sclk, sdi, sdo,
inbuffer0, inbuffer1, inbuffer2, inbuffer3,
inbuffer4, inbuffer5, inbuffer6, inbuffer7,
inbuffer8, inbuffer9, inbufferA, inbufferB,
inbufferC, inbufferD, inbufferE, inbufferF,
outbuffer0, outbuffer1, outbuffer2, outbuffer3,
outbuffer4, outbuffer5, outbuffer6, outbuffer7,
outbuffer8, outbuffer9, outbufferA, outbufferB,
outbufferC, outbufferD, outbufferE, outbufferF,
toread, towrite, enable, irq, picintr, rts,
status, statusirq, statusread, picready, state);
output picready;
output [1:0] state;
input clock;
input reset;
output sclk;
input sdi, statusread;
output sdo, statusirq;
input rts, picintr;
output [7:0] inbuffer0, inbuffer1, inbuffer2, inbuffer3,
inbuffer4, inbuffer5, inbuffer6, inbuffer7,
inbuffer8, inbuffer9, inbufferA, inbufferB,
inbufferC, inbufferD, inbufferE, inbufferF,
status;
input [7:0] outbuffer0, outbuffer1, outbuffer2, outbuffer3,
outbuffer4, outbuffer5, outbuffer6, outbuffer7,
outbuffer8, outbuffer9, outbufferA, outbufferB,
outbufferC, outbufferD, outbufferE, outbufferF,
toread, towrite;
input enable;
output irq;
wire clock, reset, sclk, sdi, sdo, enable, picintr,
statusread;
reg [7:0] inbuffer0, inbuffer1, inbuffer2, inbuffer3,
inbuffer4, inbuffer5, inbuffer6, inbuffer7,
inbuffer8, inbuffer9, inbufferA, inbufferB,
inbufferC, inbufferD, inbufferE, inbufferF,
status;
wire [7:0] outbuffer0, outbuffer1, outbuffer2, outbuffer3,
outbuffer4, outbuffer5, outbuffer6, outbuffer7,
outbuffer8, outbuffer9, outbufferA, outbufferB,
outbufferC, outbufferD, outbufferE, outbufferF,
toread, towrite;
reg [7:0] engine_toread, engine_towrite;
wire [127:0] engine_inbuffer;
reg [127:0] engine_outbuffer;
wire engine_irq, engine_enable;
wire spiclockp, spiclockn;
reg irq, statusirq, oldpicintr, statuschanged;
spi_clock_divisor #(.clkdiv(`SPICLOCKDIV)) divisor
(.reset(reset), .clkin(clock), .clkoutp(spiclockp), .clkoutn(spiclockn));
spi_engine engine (.clock(clock), .reset(reset),
.sclk(sclk), .sdi(sdi), .sdo(sdo),
.indata(engine_inbuffer), .outdata(engine_outbuffer),
.toread(engine_toread), .towrite(engine_towrite),
.enable(engine_enable), .irq(engine_irq),
.rts(rts),
.spiclockp(spiclockp), .spiclockn(spiclockn),
.picready(picready));
reg [1:0] state;
reg prevstatusread;
`define STATE_IDLE 0
`define STATE_TRANSMITTING_USER 1
`define STATE_TRANSMITTING_STATUS 2
`define STATE_SIGNALLING 3
always @(posedge clock or negedge reset)
if (~reset)
begin
state <= `STATE_IDLE;
status <= 0;
prevstatusread <= 0;
irq <= 0;
statusirq <= 0;
oldpicintr <= 0;
statuschanged <= 0;
end
else
begin
if (picintr != oldpicintr) statuschanged <= 1;
if (statusread != prevstatusread)
begin
prevstatusread <= statusread;
statusirq <= 0;
end
casex ({state, enable, engine_irq, irq, statusirq, statuschanged})
{2'd`STATE_IDLE, 1'b1, 1'b?, 1'b0, 1'b?, 1'b?}:
// Start user request if no user IRQ is pending
begin
status[7] <= 0; // Invalidate status
statuschanged <= 1;
engine_outbuffer <=
{outbuffer0, outbuffer1, outbuffer2, outbuffer3,
outbuffer4, outbuffer5, outbuffer6, outbuffer7,
outbuffer8, outbuffer9, outbufferA, outbufferB,
outbufferC, outbufferD, outbufferE, outbufferF};
engine_toread <= toread;
engine_towrite <= towrite;
state <= `STATE_TRANSMITTING_USER;
end
{2'd`STATE_IDLE, 1'b?, 1'b?, 1'b?, 1'b?, 1'b1}:
// Start status request if status has changed
begin
irq <= 0;
engine_outbuffer <= {`STATUS_READ, 120'd0};
engine_toread <= 1;
engine_towrite <= 1;
state <= `STATE_TRANSMITTING_STATUS;
status[7] <= 0; // Invalidate status
oldpicintr <= picintr;
statuschanged <= 0;
end // case: {2'd`STATE_IDLE, 1'b?, 1'b?, 1'b?, 1'b?, 1'b1}
/*
{2'd`STATE_TRANSMITTING_USER, 1'b0, 1'b?, 1'b?, 1'b?, 1'b?}:
// Request has been aborted by user
begin
state <= `STATE_SIGNALLING;
irq <= 0;
end
*/
{2'd`STATE_TRANSMITTING_USER, 1'b?, 1'b1, 1'b?, 1'b?, 1'b?}:
// Receive answer for user
begin
{inbuffer0, inbuffer1, inbuffer2, inbuffer3,
inbuffer4, inbuffer5, inbuffer6, inbuffer7,
inbuffer8, inbuffer9, inbufferA, inbufferB,
inbufferC, inbufferD, inbufferE, inbufferF}
<= engine_inbuffer;
irq <= 1;
state <= `STATE_SIGNALLING;
end
{2'd`STATE_TRANSMITTING_STATUS, 1'b?, 1'b1, 1'b?, 1'b?, 1'b?}:
// Receive status information
begin
status <= {1'b1, engine_inbuffer[126:120]};
if ({1'b1, engine_inbuffer[126:120]} != status)
statusirq <= 1;
state <= `STATE_SIGNALLING;
end
{2'd`STATE_SIGNALLING, 1'b0, 1'b?, 1'b?, 1'b?, 1'b?}:
state <= `STATE_IDLE;
endcase
end
assign engine_enable = state == `STATE_TRANSMITTING_USER |
state == `STATE_TRANSMITTING_STATUS;
endmodule
module spi_engine (clock, reset, sclk, sdi, sdo,
indata, outdata,
toread, towrite, enable,
irq, rts, spiclockp, spiclockn, picready);
output picready;
input clock, spiclockp, spiclockn;
input reset;
output sclk;
input sdi;
output sdo;
input rts;
output [127:0] indata;
input [127:0] outdata;
input [7:0] toread, towrite;
input enable;
output irq;
wire clock, reset, sclk, sdi, sdo, enable, irq, rts;
wire [7:0] toread, towrite;
wire [127:0] indata, outdata, inbuffer;
reg [127:0] shiftinbuffer;
wire emit_enable, emit_sclk, emit_done;
wire receive_enable, receive_sclk, receive_done;
wire spiclockp, spiclockn;
reg [2:0] state;
reg [4:0] toshift;
wire [4:0] inbytes;
reg picready;
wire start_emitting, start_receiving;
reg rts_r, rts_rr;
wire rts_edge = ~rts_r & rts_rr;
spi_emit_data emitter (.clock(clock), .reset(reset),
.enable(emit_enable), .data(outdata),
.count(towrite[4:0]), .sclk(emit_sclk),
.sdo(sdo), .done(emit_done),
.spiclockp(spiclockp), .spiclockn(spiclockn),
.picready(picready), .starting(start_emitting));
spi_receive_data receiver (.clock(clock), .reset(reset),
.enable(receive_enable), .sdi(sdi),
.count(toread[4:0]), .sclk(receive_sclk),
.done(receive_done), .data(inbuffer),
.spiclockp(spiclockp), .spiclockn(spiclockn),
.picready(picready),
.starting(start_receiving));
`define STATE_IDLE 0
`define STATE_EMITTING 1
`define STATE_RECEIVING 2
`define STATE_SHIFTING 3
`define STATE_SIGNALLING 4
// State changes are sampled by submodules on spiclock, which changes
// only on negative edges of clock. This allows us to be sure that
// at least 1/2 of clock is available to setup data for submodules.
always @(posedge clock or negedge reset)
if (~reset) state <= `STATE_IDLE;
else
// Emission and reception state machine
casex ({state, enable, emit_done, receive_done, inbytes, toshift})
{3'b???, 1'b0, 1'b?, 1'b?, 5'b?, 5'b?}:
// Enable is low, reset module
state <= `STATE_IDLE;
{3'd`STATE_IDLE, 1'b1, 1'b?, 1'b?, 5'b?, 5'b?}:
// Enable is high, start module
begin
toshift <= 5'd16 - toread[4:0];
state <= `STATE_EMITTING;
end
{3'd`STATE_EMITTING, 1'b?, 1'b1, 1'b?, 5'b0, 5'b?}:
// Data has been emitted and no data is scheduled for reception
state <= `STATE_SIGNALLING;
{3'd`STATE_EMITTING, 1'b?, 1'b1, 1'b?, 5'b?, 5'b?}:
// Data has been emitted, start data reception
state <= `STATE_RECEIVING;
{3'd`STATE_RECEIVING, 1'b?, 1'b?, 1'b1, 5'b?, 5'b0}:
// Data has been received and needs no shifting
begin
shiftinbuffer <= inbuffer;
state <= `STATE_SIGNALLING;
end
{3'd`STATE_RECEIVING, 1'b1, 1'b?, 1'b1, 5'b?, 5'b?}:
// Data has been received and needs shifting
begin
shiftinbuffer <= inbuffer;
state <= `STATE_SHIFTING;
end
{3'd`STATE_SHIFTING, 1'b1, 1'b?, 1'b?, 5'b?, 5'b0}:
// Shifting has ended
state <= `STATE_SIGNALLING;
{3'd`STATE_SHIFTING, 1'b1, 1'b?, 1'b?, 5'b?, 5'b?}:
// We are shifting incoming data left 8 bits at a time
begin
shiftinbuffer <= {shiftinbuffer[119:0],8'b0};
toshift <= toshift - 5'd1;
end
endcase
always @(posedge clock or negedge reset)
if (~reset) picready <= 0;
else if (rts_edge) picready <= 1;
else if (start_emitting | start_receiving) picready <= 0;
// synchro du rts sur notre domaine de clock
always @(posedge clock or negedge reset)
if (~reset) begin rts_r <= 0; rts_rr <= 0; end
else begin rts_r <= rts; rts_rr <= rts_r; end
assign inbytes = toread[4:0];
assign sclk = emit_sclk | receive_sclk;
assign irq = state == `STATE_SIGNALLING;
assign emit_enable = state == `STATE_EMITTING;
assign receive_enable = state == `STATE_RECEIVING;
assign indata = shiftinbuffer;
endmodule
// This module divides the clock clkin by 2*clkdiv and outputs the edges
// to be used in conditions.
module spi_clock_divisor (clkin, reset, clkoutp, clkoutn);
parameter clkdiv = 2;
input clkin;
input reset;
output clkoutp, clkoutn;
wire clkin;
reg clkoutp, clkoutn;
reg clkbase, clkgen;
reg [6:0] clkcnt;
always @(posedge clkin or negedge reset)
if (~reset)
begin
clkcnt <= 0;
clkbase <= 0;
clkoutp <= 0;
clkoutn <= 0;
end
else
begin
clkoutp <= 0;
clkoutn <= 0;
if (clkcnt == clkdiv)
begin
clkcnt <= 0;
clkbase <= ~clkbase;
if (clkbase) clkoutn <= 1;
else clkoutp <= 1;
end
else clkcnt <= clkcnt + 7'd1;
end
always @(negedge clkin) clkgen <= clkbase;
endmodule
module spi_emit_data (clock, reset, enable,
data, count, sclk, sdo, done,
spiclockp, spiclockn, picready, starting);
input clock, spiclockp, spiclockn;
input reset;
input [127:0] data;
input [4:0] count;
input enable, picready;
output sclk, sdo, done, starting;
wire clock, spiclockp, spiclockn;
wire enable;
wire [127:0] data;
wire [4:0] count;
reg sclk, starting;
wire sdo, picready;
reg [127:0] latch;
reg [7:0] left;
reg ready, transmit_next;
wire done, transmitting;
always @(posedge clock or negedge reset)
if (~reset)
begin
ready <= 1;
left <= 0;
starting <= 0;
end
else
begin
if (spiclockn)
begin
sclk <= 0;
starting <= 0;
if (~enable)
begin
ready <= 1;
left <= 0;
end
else if (ready)
begin
latch <= data;
left <= {count, 3'b0};
ready <= 0;
end
else if (left > 0 && transmit_next)
begin
latch <= {latch[126:0], 1'b0};
left <= left - 8'd1;
end
end
else if (spiclockp & transmitting)
begin
if (left[2:0] != 3'b000 | picready)
begin
sclk <= 1;
transmit_next <= 1;
starting <= left[2:0] == 3'b000;
end
else transmit_next <= 0;
end
end
assign done = ~ready & (left == 0);
assign transmitting = ~ready & ~done;
assign sdo = latch[127];
endmodule
module spi_receive_data (clock, reset, enable, sdi,
count, sclk, done, data, spiclockp, spiclockn,
picready, starting);
input clock, spiclockp, spiclockn;
input reset;
input [4:0] count;
input enable, sdi, picready;
output sclk, starting, done;
output [127:0] data;
wire clock;
wire enable;
wire [127:0] data;
wire [4:0] count;
reg sclk, starting;
wire sdi, picready;
reg [127:0] latch;
reg [7:0] left;
reg sample, ready, receive_next;
wire receiving, done;
always @(negedge clock or negedge reset)
if (~reset)
begin
ready <= 1;
left <= 0;
starting <= 0;
end
else
begin
if (spiclockn)
begin
sclk <= 0;
starting <= 0;
if (~enable)
begin
ready <= 1;
left <= 0;
end
else if (ready)
begin
left <= {count, 3'b0};
ready <= 0;
end
else if (left > 0 && receive_next)
begin
latch <= {latch[126:0], sample};
left <= left - 8'd1;
end
end
else if (spiclockp && receiving)
if (left[2:0] != 3'b000 | picready)
begin
sample <= sdi;
sclk <= 1;
receive_next <= 1;
starting <= left[2:0] == 3'b000;
end
else receive_next <= 0;
end
assign done = ~ready & (left == 0);
assign receiving = ~ready & ~done;
assign data = latch;
endmodule
// This module generates an IRQ to the SH4 each time the PIC IRQ goes
// from low to high until the IRQ gets acked. Unused at this time.
module spi_irq (clock, reset, signal, irq, ack);
input signal, ack, clock, reset;
output irq;
wire clock, reset, signal, ack;
reg irq, prevsignal;
always @(posedge clock or negedge reset)
if (~reset)
begin
prevsignal <= 0;
irq <= 0;
end
else
begin
if (signal && ~prevsignal) irq <= 1;
prevsignal <= signal;
if (ack) irq <= 0;
end
endmodule
|
`timescale 1ns / 1ns
//
// Mark2A/B - main CPLD code
//
// Define this to build firmware for the Mark2B board which merges the dual CPLDs from
// the Mark2A into a single device
// `define MARK2B 1
//
// Depth of pipeline to delay switches to HS clock after an IO access.
// Modified now to count SYNCs rather than cycles
`define IO_ACCESS_DELAY_SZ 4
// Define this to force-keep some clock nets to reduce design size
`define FORCE_KEEP_CLOCK 1
// Define to drive clocks to test points tp[1:0]
//`define OBSERVE_CLOCKS 1
// Set one of these to falling edge of RAMOEB by one buffer when running with fast SRAM
//`define DELAY_RAMOEB_BY_1
`define DELAY_RAMOEB_BY_2
//`define DELAY_RAMOEB_BY_3
// Fixed clock divider now - default is /4 but can still compile with /2
`define CLKDIV4NOT2 1
// Define this for BBC MASTER support
// `define ALLOW_BBC_MASTER_HOST 1
// Decoding for fixed address areas of RAM
`define LOWMEM_1K (!cpu_data[7] & !cpu_adr[15] & !(|cpu_adr[14:10]))
`define LOWMEM_12K (!cpu_data[7] & !cpu_adr[15] & !(cpu_adr[14] | (cpu_adr[13]&cpu_adr[12])))
`define LYNNE_20K (!cpu_data[7] & !cpu_adr[15] & (cpu_adr[14] | (cpu_adr[13]&cpu_adr[12])))
// Define this to bring decoding back into the main CPLD (mainly for capacity evaluation). Note
// that the address lsb latches are still assumed external to keep the same pin out. Must be defined
// for the Mark2B board.
// `define LOCAL_DECODING 1
`ifdef MARK2B
`define ALLOW_BBC_MASTER_HOST 1
`define ALLOW_BEEB_HOST 1
`define ALLOW_ELK_HOST 1
// All-in-one CPLD - no offloading of decoding to external IC
`define LOCAL_DECODING 1
// Remove this definition to improve MHz at cost of logic
`undef FORCE_KEEP_CLOCK
// Enough macrocells to export the clock to test points
`define OBSERVE_CLOCKS 1
`else
`define ALLOW_BEEB_HOST 1
`define ALLOW_ELK_HOST 1
`endif // `ifdef MARK2B
`ifdef LOCAL_DECODING
`define ELK_PAGED_ROM_SEL 16'hFE05
`define PAGED_ROM_SEL 16'hFE30
`define BPLUS_SHADOW_RAM_SEL 16'hFE34
`define DECODED_SHADOW_REG (((`L1_BPLUS_MODE) || (`L1_MASTER_MODE)) ? (cpu_adr==`BPLUS_SHADOW_RAM_SEL) : 1'b0 )
`define DECODED_ROM_REG ((`L1_ELK_MODE)? (cpu_adr==`ELK_PAGED_ROM_SEL) : (cpu_adr==`PAGED_ROM_SEL))
// Flag FE4x (VIA) accesses and also all &FC, &FD expansion pages
`define DECODED_FE4X ((cpu_adr[15:4]==12'hFE4) || (cpu_adr[15:9]==7'b1111_110))
`else // !`ifdef LOCAL_DECODING
`define DECODED_SHADOW_REG dec_shadow_reg
`define DECODED_ROM_REG dec_rom_reg
`define DECODED_FE4X dec_fe4x
`endif // !`ifdef LOCAL_DECODING
`define MAP_CC_DATA_SZ 8
`define SHADOW_MEM_IDX 7
`define HOST_TYPE_1_IDX 6
`define HOST_TYPE_0_IDX 5
`define MAP_ROM_IDX 4
`define MAP_HSCLK_EN_IDX 2
`define BBC_PAGEREG_SZ 4 // only the bottom four ROM selection bits
`define CPLD_REG_SEL_SZ 3
`define CPLD_REG_SEL_BBC_SHADOW_IDX 2
`define CPLD_REG_SEL_MAP_CC_IDX 1
`define CPLD_REG_SEL_BBC_PAGEREG_IDX 0
`ifndef CLKDIV4NOT2
`define CLKDIV4NOT2 1
`endif
`ifdef ALLOW_ELK_HOST
`define L1_ELK_MODE (map_data_q[`HOST_TYPE_1_IDX:`HOST_TYPE_0_IDX]==2'b10)
`else
`define L1_ELK_MODE 1'b0
`endif
`ifdef ALLOW_BEEB_HOST
`define L1_BEEB_MODE (map_data_q[`HOST_TYPE_1_IDX:`HOST_TYPE_0_IDX]==2'b00)
`define L1_BPLUS_MODE (map_data_q[`HOST_TYPE_1_IDX:`HOST_TYPE_0_IDX]==2'b01)
`else
`define L1_BEEB_MODE 1'b0
`define L1_BPLUS_MODE 1'b0
`endif
`ifdef ALLOW_ELK_HOST
`define ALLOW_BEEB_OR_ELK_HOST 1
`elsif ALLOW_BEEB_HOST
`define ALLOW_BEEB_OR_ELK_HOST 1
`endif
`ifdef ALLOW_BBC_MASTER_HOST
`ifdef ALLOW_BEEB_OR_ELK_HOST
`define L1_MASTER_MODE (map_data_q[`HOST_TYPE_1_IDX:`HOST_TYPE_0_IDX]==2'b11)
`else
`define L1_MASTER_MODE (1'b1)
`endif
`else
`define L1_MASTER_MODE (1'b0)
`endif
module level1b_mk2_m (
input [15:0] cpu_adr,
input resetb,
input cpu_vpb,
input cpu_e,
input cpu_vda,
input cpu_vpa,
input bbc_phi0,
input hsclk,
input cpu_rnw,
input [1:0] j,
output [1:0] tp,
`ifdef MARK2B
input rdy,
input nmib,
input irqb,
output cpu_rstb,
output cpu_rdy,
output cpu_nmib,
output cpu_irqb,
output [15:0] bbc_adr,
`else
input dec_shadow_reg,
input dec_rom_reg,
input dec_fe4x,
inout rdy,
inout nmib,
inout irqb,
output lat_en,
output [15:12] bbc_adr,
`endif
inout [7:0] cpu_data,
inout [7:0] bbc_data,
output ram_web,
output ram_ceb,
output ram_oeb,
output [18:14] ram_adr,
output bbc_sync,
output bbc_rnw,
output bbc_phi1,
output bbc_phi2,
output cpu_phi2
);
reg [7:0] cpu_hiaddr_lat_q;
reg [7:0] cpu_data_r;
reg mos_vdu_sync_q;
reg write_thru_lat_q;
reg rom_wr_protect_lat_q;
reg [7:0] bbc_data_lat_q;
// This is the internal register controlling which features like high speed clocks etc are enabled
reg [ `CPLD_REG_SEL_SZ-1:0] cpld_reg_sel_q;
wire [ `CPLD_REG_SEL_SZ-1:0] cpld_reg_sel_d;
// This will be a copy of the BBC ROM page register so we know which ROM is selected
reg [`BBC_PAGEREG_SZ-1:0] bbc_pagereg_q;
reg [`MAP_CC_DATA_SZ-1:0] map_data_q;
reg remapped_rom47_access_r ;
reg remapped_romAB_access_r ;
reg remapped_romCF_access_r ;
reg remapped_mos_access_r ;
reg remapped_ram_access_r ;
reg cpu_a15_lat_d;
reg cpu_a14_lat_d;
reg cpu_a15_lat_q;
reg cpu_a14_lat_q;
reg [7:0] cpu_hiaddr_lat_d;
reg [ `IO_ACCESS_DELAY_SZ-1:0] io_access_pipe_q;
`ifdef ALLOW_BBC_MASTER_HOST
reg ram_at_8000;
reg mos_vdu_sync_acccon_q;
reg acccon_y; // bit 3 of FE34
reg acccon_x; // bit 2 of FE34
reg acccon_e; // bit 1 of FE34
`endif
reg rdy_q;
wire io_access_pipe_d;
reg write_thru_d;
`ifdef FORCE_KEEP_CLOCK
(* KEEP="TRUE" *) wire cpu_phi1_w;
(* KEEP="TRUE" *) wire cpu_phi2_w;
`else
wire cpu_phi1_w;
wire cpu_phi2_w;
`endif
wire hs_selected_w;
wire ls_selected_w;
wire dummy_access_w;
wire sel_hs_w;
wire native_mode_int_w;
wire himem_w;
wire hisync_w;
wire [ `CPLD_REG_SEL_SZ-1:0] cpld_reg_sel_w;
wire ckdel_w;
wire fast_clk_w;
`ifdef OBSERVE_CLOCKS
assign tp = { bbc_phi2, fast_clk_w} ; // or cpu_phi2 for switched clock
`endif
// Deglitch PHI0 input for feeding to clock switch only (mainly helps Elk, but
// also provides opportunity to extend PHI1 slightly to give more time to clock
// switch). Delay needed to CPU clock because 1MHz clock is much delayed on the
// motherboard and hold fails occur on 1Mhz bus otherwise.
(* KEEP="TRUE" *) wire ckdel_1_b;
(* KEEP="TRUE" *) wire ckdel_2;
INV ckdel0 ( .I(bbc_phi0), .O(ckdel_1_b));
INV ckdel2 ( .I(ckdel_1_b), .O(ckdel_2));
assign ckdel_w = !(bbc_phi0 & ckdel_2);
`define XC95108_7 1
`ifdef XC95108_7
(* KEEP="TRUE" *) wire ckdel_3_b;
(* KEEP="TRUE" *) wire ckdel_4;
INV ckdel3 ( .I(ckdel_2), .O(ckdel_3_b));
INV ckdel4 ( .I(ckdel_3_b), .O(ckdel_4));
assign bbc_phi1 = ckdel_3_b;
assign bbc_phi2 = ckdel_4;
`else
assign bbc_phi1 = ckdel_1_b;
assign bbc_phi2 = !ckdel_1_b;
`endif
clkctrl_phi2 U_0 (
.hsclk_in(hsclk),
.lsclk_in(ckdel_w),
.rst_b(resetb),
.hsclk_sel(sel_hs_w),
.hsclk_selected(hs_selected_w),
.cpuclk_div_sel(`CLKDIV4NOT2),
.delay_bypass(`L1_MASTER_MODE),
.lsclk_selected(ls_selected_w),
.clkout(cpu_phi1_w),
.fast_clkout(fast_clk_w)
);
assign cpu_phi2_w = !cpu_phi1_w ;
assign cpu_phi2 = cpu_phi2_w ;
assign bbc_sync = (cpu_vpa & cpu_vda) | dummy_access_w;
`ifdef MARK2B
// CPLD must do 5V/3V3 shifting on all control signals from host
assign cpu_irqb = irqb;
assign cpu_nmib = nmib;
assign cpu_rdy = rdy;
assign cpu_rstb = resetb;
`else
assign irqb = 1'bz;
assign nmib = 1'bz;
assign rdy = 1'bz;
`endif
// Native mode interrupts will be redirected to himem
assign native_mode_int_w = !cpu_vpb & !cpu_e ;
// Drive the all RAM address pins, allowing for 512K RAM connection
assign ram_adr = { cpu_hiaddr_lat_q[2:0], cpu_a15_lat_q, cpu_a14_lat_q } ;
assign lat_en = !dummy_access_w;
`ifdef DELAY_RAMOEB_BY_1
(* KEEP="TRUE" *) wire ramoeb_del_1;
BUF ramoedel1 ( .I(!cpu_rnw | cpu_phi1_w), .O(ramoeb_del_1));
`define DELAYOEB ramoeb_del_1
`elsif DELAY_RAMOEB_BY_2
(* KEEP="TRUE" *) wire ramoeb_del_1, ramoeb_del_2;
BUF ramoedel1 ( .I(!cpu_rnw | cpu_phi1_w), .O(ramoeb_del_1));
BUF ramoedel2 ( .I(ramoeb_del_1), .O(ramoeb_del_2));
`define DELAYOEB ramoeb_del_2
`elsif DELAY_RAMOEB_BY_3
(* KEEP="TRUE" *) wire ramoeb_del_1, ramoeb_del_2, ramoeb_del_3;
BUF ramoedel1 ( .I(!cpu_rnw | cpu_phi1_w), .O(ramoeb_del_1));
BUF ramoedel2 ( .I(ramoeb_del_1), .O(ramoeb_del_2));
BUF ramoedel3 ( .I(ramoeb_del_2), .O(ramoeb_del_3));
`define DELAYOEB ramoeb_del_3
`else
`define DELAYOEB 1'b0
`endif
// All addresses starting 0b11 go to the on-board RAM and 0b10 to IO space, so check just bit 6
// SRAM is enabled only in PHI2 for best operation with faster SRAM parts
assign ram_ceb = cpu_phi1_w | !(cpu_hiaddr_lat_q[6] & (cpu_vda|cpu_vpa)) ;
assign ram_web = cpu_rnw | cpu_phi1_w | rom_wr_protect_lat_q ;
assign ram_oeb = !cpu_rnw | cpu_phi1_w | `DELAYOEB ;
// All addresses starting with 0b10 go to internal IO registers which update on the
// rising edge of cpu_phi1 - use the cpu_data bus directly for the high address
// bits since it's stable by the end of phi1
assign cpld_reg_sel_w = cpld_reg_sel_q;
assign cpld_reg_sel_d[`CPLD_REG_SEL_MAP_CC_IDX] = ( cpu_data[7:6]== 2'b10);
assign cpld_reg_sel_d[`CPLD_REG_SEL_BBC_PAGEREG_IDX] = (cpu_data[7]== 1'b0) && `DECODED_ROM_REG ;
assign cpld_reg_sel_d[`CPLD_REG_SEL_BBC_SHADOW_IDX] = (cpu_data[7]== 1'b0) && `DECODED_SHADOW_REG ;
// Force dummy read access when accessing himem explicitly but not for remapped RAM accesses which can still complete
`ifdef MARK2B
`ifdef ALLOW_BBC_MASTER_HOST
assign bbc_adr = { (dummy_access_w) ? (mos_vdu_sync_q ? 16'hC000 : 16'hE000) : cpu_adr };
`else
assign bbc_adr = { (dummy_access_w) ? 16'hC000 : cpu_adr };
`endif
`else
assign bbc_adr = { (dummy_access_w) ? 4'b1100 : cpu_adr[15:12] };
`endif
// Build delay chain for use with Electron to improve xtalk (will be bypassed for other machines)
`ifdef ALLOW_ELK_HOST
(* KEEP="TRUE" *) wire bbc_rnw_pre, bbc_rnw_del, bbc_rnw_del2;
assign bbc_rnw_pre = cpu_rnw | dummy_access_w ;
BUF bbc_rnw_0( .I(bbc_rnw_pre), .O(bbc_rnw_del) );
BUF bbc_rnw_1( .I(bbc_rnw_del), .O(bbc_rnw_del2) );
// Electron needs delay on RNW to reduce xtalk
assign bbc_rnw = (`L1_ELK_MODE) ? (bbc_rnw_del2 | bbc_rnw_pre) : bbc_rnw_pre ;
`else
assign bbc_rnw = cpu_rnw | dummy_access_w ;
`endif
assign bbc_data = ( !bbc_rnw & bbc_phi2) ? cpu_data : { 8{1'bz}};
assign cpu_data = cpu_data_r;
// Check for write accesses to some of IO space (FE4x) in case we need to delay switching back to HS clock
// so that min pulse widths to sound chip/reading IO are respected
assign io_access_pipe_d = !cpu_hiaddr_lat_q[7] & `DECODED_FE4X & cpu_vda ;
// Sel the high speed clock only
// * on valid instruction fetches from himem, or
// * on valid imm/data fetches from himem _if_ hs clock is already selected, or
// * on invalid bus cycles if hs clock is already selected
assign himem_w = cpu_hiaddr_lat_q[7] & (!write_thru_lat_q | cpu_rnw );
// Allow hisync to be set for any valid program address (was opcode fetch only - ie vpa & vda)
assign hisync_w = (cpu_vpa) & cpu_hiaddr_lat_q[7];
assign sel_hs_w = (( hisync_w & !io_access_pipe_q[0] ) |
( himem_w & hs_selected_w) |
(!cpu_vpa & !cpu_vda & hs_selected_w)
) ;
assign dummy_access_w = himem_w | !ls_selected_w;
// ROM remapping
always @ ( * ) begin
// Split ROM and MOS identification to allow them to go to different banks later
remapped_mos_access_r = 0;
remapped_rom47_access_r = 0;
remapped_romAB_access_r = 0;
remapped_romCF_access_r = 0;
if (!cpu_data[7] & cpu_adr[15] & (cpu_vpa|cpu_vda) & map_data_q[`MAP_ROM_IDX]) begin
`ifdef ALLOW_BBC_MASTER_HOST
if (!cpu_adr[14]) begin
// ram_at_8000 always zero for non-Master machines
remapped_romCF_access_r = (bbc_pagereg_q[3:2] == 2'b11) & (cpu_adr[12] | cpu_adr[13] | !ram_at_8000);
remapped_romAB_access_r = (bbc_pagereg_q[3:1] == 3'b101) & (cpu_adr[12] | cpu_adr[13] | !ram_at_8000);
remapped_rom47_access_r = (bbc_pagereg_q[3:2] == 2'b01) & (cpu_adr[12] | cpu_adr[13] | !ram_at_8000);
end
else
// Remap MOS from C000-FBFF only (exclude IO space and vectors)
remapped_mos_access_r = !(&(cpu_adr[13:10])) & (cpu_adr[13] | !acccon_y);
`else
if (!cpu_adr[14]) begin
remapped_romCF_access_r = (bbc_pagereg_q[3:2] == 2'b11) ;
remapped_romAB_access_r = (bbc_pagereg_q[3:1] == 3'b101) ;
remapped_rom47_access_r = (bbc_pagereg_q[3:2] == 2'b01) ;
end
else
// Remap MOS from C000-FBFF only (exclude IO space and vectors)
remapped_mos_access_r = !(&(cpu_adr[13:10]));
`endif
end // if (!cpu_data[7] & cpu_adr[15] & (cpu_vpa|cpu_vda) & map_data_q[`MAP_ROM_IDX])
end // always @ ( * )
always @ ( * ) begin
// Remap all of RAM area now and deal with video accesses separately
remapped_ram_access_r = !cpu_data[7] & !cpu_adr[15] ;
end
always @ ( * ) begin
// Default assignments
cpu_a15_lat_d = cpu_adr[15];
cpu_a14_lat_d = cpu_adr[14];
cpu_hiaddr_lat_d = cpu_data;
write_thru_d = 1'b0;
// Native mode interrupts go to bank 0xFF (with other native 816 code)
if ( native_mode_int_w )
cpu_hiaddr_lat_d = 8'hFF;
else if ( remapped_mos_access_r )
cpu_hiaddr_lat_d = 8'hFF;
else if ( remapped_ram_access_r ) begin
if ( `LOWMEM_1K )
// All hosts, all access to bottom 1K is high speed to bank &FF
cpu_hiaddr_lat_d = 8'hFF;
`ifdef ALLOW_BBC_MASTER_HOST
else if ( `L1_MASTER_MODE ) begin
// All accesses from Master to memory above the 1K base is write-through
write_thru_d = 1'b1;
if (`LOWMEM_12K )
// All accesses to memory below LYNNE go to main bank
cpu_hiaddr_lat_d = 8'hFF;
else if (mos_vdu_sync_acccon_q )
// Shadow mode accesses using VDU calls go to alternate bank (Shadow mode
// is always enabled in Master mode)
cpu_hiaddr_lat_d = 8'hFD;
else
// Shadow mode accesses _not_ using VDU calls and non Shadow mode accesses
cpu_hiaddr_lat_d = 8'hFF;
end // if ( `L1_MASTER_MODE )
`endif // `ifdef ALLOW_BBC_MASTER_HOST
`ifdef ALLOW_BEEB_OR_ELK_HOST
else if ( !map_data_q[`SHADOW_MEM_IDX] ) begin
// Beeb/Elk accesses to rest of RAM in non-shadow mode
cpu_hiaddr_lat_d = 8'hFF;
write_thru_d = 1'b1;
end
else if ( mos_vdu_sync_q ) begin
// Beeb/Elk accesses to rest of RAM in Shadow mode but via VDU calls
cpu_hiaddr_lat_d = 8'hFF;
write_thru_d = 1'b1;
end
else begin
// Beeb/Elk accesses to rest of RAM in Shadow mode, non VDU calls
cpu_hiaddr_lat_d = 8'hFD;
end
`endif
end // if ( remapped_ram_access_r )
else if (remapped_rom47_access_r | remapped_romCF_access_r | remapped_romAB_access_r) begin
if ( remapped_rom47_access_r )
cpu_hiaddr_lat_d = 8'hFC;
else if ( remapped_romAB_access_r )
cpu_hiaddr_lat_d = 8'hFD;
else if ( remapped_romCF_access_r)
cpu_hiaddr_lat_d = 8'hFE;
cpu_a15_lat_d = bbc_pagereg_q[1];
cpu_a14_lat_d = bbc_pagereg_q[0];
end
end
// drive cpu data if we're reading internal register or making a non dummy read from lomem
always @ ( * )
if ( cpu_phi2_w & cpu_rnw )
begin
if (cpu_hiaddr_lat_q[7]) begin
if (cpld_reg_sel_w[`CPLD_REG_SEL_MAP_CC_IDX] ) begin
// Not all bits are used so assign default first, then individual bits
cpu_data_r = 8'b0 ;
cpu_data_r[`MAP_HSCLK_EN_IDX] = map_data_q[`MAP_HSCLK_EN_IDX] ;
cpu_data_r[`SHADOW_MEM_IDX] = map_data_q[`SHADOW_MEM_IDX];
cpu_data_r[`HOST_TYPE_1_IDX] = map_data_q[`HOST_TYPE_1_IDX];
cpu_data_r[`HOST_TYPE_0_IDX] = map_data_q[`HOST_TYPE_0_IDX];
cpu_data_r[`MAP_ROM_IDX] = map_data_q[`MAP_ROM_IDX];
end
else //must be RAM access
cpu_data_r = {8{1'bz}};
end
else
cpu_data_r = bbc_data_lat_q;
end
else
cpu_data_r = {8{1'bz}};
// -------------------------------------------------------------
// All inferred flops and latches below this point
// -------------------------------------------------------------
// Internal registers update on the rising edge of cpu_phi1
always @ ( negedge cpu_phi2_w )
// Synchronous reset for this register
if ( !resetb )
begin
// DIP2 = MASTER MODE startup - shadow ON, host ID, bypass clock delay, VRAM size set
map_data_q[`MAP_HSCLK_EN_IDX] <= 1'b0;
map_data_q[`MAP_ROM_IDX] <= 1'b0;
map_data_q[`HOST_TYPE_1_IDX] <= j[1]; // DIP2
map_data_q[`HOST_TYPE_0_IDX] <= j[1]; // DIP2
map_data_q[`SHADOW_MEM_IDX] <= j[1]; // DIP2
bbc_pagereg_q <= {`BBC_PAGEREG_SZ{1'b0}};
`ifdef ALLOW_BBC_MASTER_HOST
ram_at_8000 <= 1'b0;
{acccon_y, acccon_x, acccon_e} <= { 2'b00, !(`L1_MASTER_MODE) } ;
`endif
end
else
begin
if (cpld_reg_sel_w[`CPLD_REG_SEL_MAP_CC_IDX] & !cpu_rnw) begin
map_data_q[`MAP_HSCLK_EN_IDX] <= cpu_data[`MAP_HSCLK_EN_IDX] ;
map_data_q[`SHADOW_MEM_IDX] <= cpu_data[`SHADOW_MEM_IDX];
map_data_q[`HOST_TYPE_1_IDX] <= cpu_data[`HOST_TYPE_1_IDX];
map_data_q[`HOST_TYPE_0_IDX] <= cpu_data[`HOST_TYPE_0_IDX];
map_data_q[`MAP_ROM_IDX] <= cpu_data[`MAP_ROM_IDX];
end // if (cpld_reg_sel_w[`CPLD_REG_SEL_MAP_CC_IDX] & !cpu_rnw)
else if (cpld_reg_sel_w[`CPLD_REG_SEL_BBC_PAGEREG_IDX] & !cpu_rnw ) begin
bbc_pagereg_q <= cpu_data;
`ifdef ALLOW_BBC_MASTER_HOST
ram_at_8000 <= cpu_data[7] & `L1_MASTER_MODE;
`endif
end
else if (cpld_reg_sel_w[`CPLD_REG_SEL_BBC_SHADOW_IDX] & !cpu_rnw ) begin
`ifdef ALLOW_BEEB_OR_ELK_HOST
if `L1_BPLUS_MODE
map_data_q[`SHADOW_MEM_IDX] <= cpu_data[`SHADOW_MEM_IDX];
`endif
`ifdef ALLOW_BBC_MASTER_HOST
if `L1_MASTER_MODE
{acccon_y, acccon_x, acccon_e} <= cpu_data[3:1];
`endif
end
end // else: !if( !resetb )
// Sample Rdy at the start of the cycle, so it remains stable for the remainder of the cycle
always @ ( negedge cpu_phi2_w)
rdy_q <= rdy;
// Flop all the internal register sel bits on falling edge of phi1
always @ ( posedge cpu_phi2_w or negedge resetb )
if ( !resetb )
cpld_reg_sel_q <= {`CPLD_REG_SEL_SZ{1'b0}};
else
cpld_reg_sel_q <= (rdy_q & cpu_vda) ? cpld_reg_sel_d : {`CPLD_REG_SEL_SZ{1'b0}};
// Short pipeline to delay switching back to hs clock after an IO access to ensure any instruction
// timed delays are respected. This pipeline is initialised to all 1's for force slow clock on startup
// and will fill with the value of the HS clock enable register as instructions are executed.
always @ ( negedge cpu_phi2_w or negedge resetb) begin
if ( !resetb )
io_access_pipe_q <= {`IO_ACCESS_DELAY_SZ{1'b1}};
else begin
if (io_access_pipe_d )
io_access_pipe_q <= {`IO_ACCESS_DELAY_SZ{1'b1}};
else if ( cpu_vpa & cpu_vda & rdy)
io_access_pipe_q <= { !map_data_q[`MAP_HSCLK_EN_IDX], io_access_pipe_q[`IO_ACCESS_DELAY_SZ-2:1] } ;
end
end
// Instruction was fetched from VDU routines in MOS if
// - in the range FFC000 - FFDFFF (if remapped to himem )
// - OR in range 00C000 - 00DFFF if ROM remapping disabled.
always @ ( negedge cpu_phi2_w )
if ( cpu_vpa & cpu_vda ) begin
`ifdef ALLOW_BBC_MASTER_HOST
if ( acccon_y ) begin
mos_vdu_sync_q <= 1'b0;
end
else if ( map_data_q[`MAP_ROM_IDX]) begin
mos_vdu_sync_q <= ({cpu_hiaddr_lat_q[7], cpu_hiaddr_lat_q[4:0],cpu_adr[15:13]}==9'b1_11111_110);
end
else begin
mos_vdu_sync_q <= ({cpu_hiaddr_lat_q[7],cpu_adr[15:13]}==4'b0_110);
end
`else
if ( map_data_q[`MAP_ROM_IDX])
mos_vdu_sync_q <= ({cpu_hiaddr_lat_q[7], cpu_hiaddr_lat_q[4:0],cpu_adr[15:13]}==9'b1_11111_110) ;
else
mos_vdu_sync_q <= ({cpu_hiaddr_lat_q[7],cpu_adr[15:13]}==4'b0_110) ;
`endif
end // if ( cpu_vpa & cpu_vda )
`ifdef ALLOW_BBC_MASTER_HOST
always @ ( posedge cpu_phi2_w )
mos_vdu_sync_acccon_q <= (mos_vdu_sync_q) ? acccon_e: acccon_x;
`endif
// Latches for the high address bits open during PHI1
always @ ( * )
if ( rdy & rdy_q & !cpu_phi2_w )
begin
cpu_hiaddr_lat_q <= cpu_hiaddr_lat_d ;
cpu_a15_lat_q <= cpu_a15_lat_d;
cpu_a14_lat_q <= cpu_a14_lat_d;
write_thru_lat_q <= write_thru_d;
rom_wr_protect_lat_q <= remapped_mos_access_r| remapped_romCF_access_r | remapped_romAB_access_r;
end
// Latches for the BBC data open during PHI2 to be stable beyond cycle end
always @ ( * )
if ( !bbc_phi1 )
bbc_data_lat_q <= bbc_data;
endmodule // level1b_m
|
/**
* Name:
* bsg_lru_pseudo_tree_decode.v
*
* Description:
* Pseudo-Tree-LRU decode unit.
* Given input referred way_id, generates data and mask that updates
* the pseudo-LRU tree. Data and mask are chosen in a way that referred way_id is
* no longer the LRU way. The mask and data signals can be given to a
* bitmaskable memory to update the corresponding LRU bits.
*/
`include "bsg_defines.v"
module bsg_lru_pseudo_tree_decode
#(parameter `BSG_INV_PARAM(ways_p)
,localparam lg_ways_lp = `BSG_SAFE_CLOG2(ways_p)
)
(input [lg_ways_lp-1:0] way_id_i
, output logic [`BSG_SAFE_MINUS(ways_p, 2):0] data_o
, output logic [`BSG_SAFE_MINUS(ways_p, 2):0] mask_o
);
genvar i;
generate
if (ways_p == 1) begin: no_lru
assign mask_o[0] = 1'b1;
assign data_o[0] = 1'b0;
end
else begin: lru
for(i=0; i<ways_p-1; i++) begin: rof
// Mask generation
if(i == 0) begin: fi
assign mask_o[i] = 1'b1;
end
else if(i%2 == 1) begin: fi
assign mask_o[i] = mask_o[(i-1)/2] & ~way_id_i[lg_ways_lp-`BSG_SAFE_CLOG2(i+2)+1];
end
else begin: fi
assign mask_o[i] = mask_o[(i-2)/2] & way_id_i[lg_ways_lp-`BSG_SAFE_CLOG2(i+2)+1];
end
// Data generation
assign data_o[i] = mask_o[i] & ~way_id_i[lg_ways_lp-`BSG_SAFE_CLOG2(i+2)];
end
end
endgenerate
endmodule
`BSG_ABSTRACT_MODULE(bsg_lru_pseudo_tree_decode)
|
// niosII_system_tristate_conduit_pin_sharer_0.v
// This file was auto-generated from altera_tristate_conduit_pin_sharer_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:48
`timescale 1 ps / 1 ps
module niosII_system_tristate_conduit_pin_sharer_0 (
input wire clk_clk, // clk.clk
input wire reset_reset, // reset.reset
output wire request, // tcm.request
input wire grant, // .grant
output wire [0:0] generic_tristate_controller_0_tcm_byteenable_out, // .generic_tristate_controller_0_tcm_byteenable_out_out
output wire [21:0] generic_tristate_controller_0_tcm_address_out, // .generic_tristate_controller_0_tcm_address_out_out
output wire [0:0] generic_tristate_controller_0_tcm_read_n_out, // .generic_tristate_controller_0_tcm_read_n_out_out
output wire [0:0] generic_tristate_controller_0_tcm_write_n_out, // .generic_tristate_controller_0_tcm_write_n_out_out
output wire [7:0] generic_tristate_controller_0_tcm_data_out, // .generic_tristate_controller_0_tcm_data_out_out
input wire [7:0] generic_tristate_controller_0_tcm_data_in, // .generic_tristate_controller_0_tcm_data_out_in
output wire generic_tristate_controller_0_tcm_data_outen, // .generic_tristate_controller_0_tcm_data_out_outen
output wire [0:0] generic_tristate_controller_0_tcm_chipselect_n_out, // .generic_tristate_controller_0_tcm_chipselect_n_out_out
output wire [0:0] generic_tristate_controller_0_tcm_begintransfer_out, // .generic_tristate_controller_0_tcm_begintransfer_out_out
input wire tcs0_request, // tcs0.request
output wire tcs0_grant, // .grant
input wire [0:0] tcs0_byteenable_out, // .byteenable_out
input wire [21:0] tcs0_address_out, // .address_out
input wire [0:0] tcs0_read_n_out, // .read_n_out
input wire [0:0] tcs0_write_n_out, // .write_n_out
input wire [7:0] tcs0_data_out, // .data_out
output wire [7:0] tcs0_data_in, // .data_in
input wire tcs0_data_outen, // .data_outen
input wire [0:0] tcs0_chipselect_n_out, // .chipselect_n_out
input wire [0:0] tcs0_begintransfer_out // .begintransfer_out
);
wire [0:0] arbiter_grant_data; // arbiter:next_grant -> pin_sharer:next_grant
wire arbiter_grant_ready; // pin_sharer:ack -> arbiter:ack
wire pin_sharer_tcs0_arb_valid; // pin_sharer:arb_generic_tristate_controller_0_tcm -> arbiter:sink0_valid
niosII_system_tristate_conduit_pin_sharer_0_pin_sharer pin_sharer (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // reset.reset
.request (request), // tcm.request
.grant (grant), // .grant
.generic_tristate_controller_0_tcm_byteenable_out (generic_tristate_controller_0_tcm_byteenable_out), // .generic_tristate_controller_0_tcm_byteenable_out_out
.generic_tristate_controller_0_tcm_address_out (generic_tristate_controller_0_tcm_address_out), // .generic_tristate_controller_0_tcm_address_out_out
.generic_tristate_controller_0_tcm_read_n_out (generic_tristate_controller_0_tcm_read_n_out), // .generic_tristate_controller_0_tcm_read_n_out_out
.generic_tristate_controller_0_tcm_write_n_out (generic_tristate_controller_0_tcm_write_n_out), // .generic_tristate_controller_0_tcm_write_n_out_out
.generic_tristate_controller_0_tcm_data_out (generic_tristate_controller_0_tcm_data_out), // .generic_tristate_controller_0_tcm_data_out_out
.generic_tristate_controller_0_tcm_data_in (generic_tristate_controller_0_tcm_data_in), // .generic_tristate_controller_0_tcm_data_out_in
.generic_tristate_controller_0_tcm_data_outen (generic_tristate_controller_0_tcm_data_outen), // .generic_tristate_controller_0_tcm_data_out_outen
.generic_tristate_controller_0_tcm_chipselect_n_out (generic_tristate_controller_0_tcm_chipselect_n_out), // .generic_tristate_controller_0_tcm_chipselect_n_out_out
.generic_tristate_controller_0_tcm_begintransfer_out (generic_tristate_controller_0_tcm_begintransfer_out), // .generic_tristate_controller_0_tcm_begintransfer_out_out
.tcs0_request (tcs0_request), // tcs0.request
.tcs0_grant (tcs0_grant), // .grant
.tcs0_tcm_byteenable_out (tcs0_byteenable_out), // .byteenable_out
.tcs0_tcm_address_out (tcs0_address_out), // .address_out
.tcs0_tcm_read_n_out (tcs0_read_n_out), // .read_n_out
.tcs0_tcm_write_n_out (tcs0_write_n_out), // .write_n_out
.tcs0_tcm_data_out (tcs0_data_out), // .data_out
.tcs0_tcm_data_in (tcs0_data_in), // .data_in
.tcs0_tcm_data_outen (tcs0_data_outen), // .data_outen
.tcs0_tcm_chipselect_n_out (tcs0_chipselect_n_out), // .chipselect_n_out
.tcs0_tcm_begintransfer_out (tcs0_begintransfer_out), // .begintransfer_out
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.arb_generic_tristate_controller_0_tcm (pin_sharer_tcs0_arb_valid) // tcs0_arb.valid
);
niosII_system_tristate_conduit_pin_sharer_0_arbiter arbiter (
.clk (clk_clk), // clk.clk
.reset (reset_reset), // clk_reset.reset
.ack (arbiter_grant_ready), // grant.ready
.next_grant (arbiter_grant_data), // .data
.sink0_valid (pin_sharer_tcs0_arb_valid) // sink0.valid
);
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_div.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU divider; building block used by several other APU components. Outputs a pulse every n input
* pulses, where n is the divider's period. It contains a counter which is decremented on the
* arrival of each pulse. When the counter reaches 0, it is reloaded with the period and an output
* pulse is generated. A divider can also be forced to reload its counter immediately, but this
* does not output a pulse. When a divider's period is changed, the current count is not affected.
*
* apu_div_const is a variation on apu_div that has an immutable period.
***************************************************************************************************/
module apu_div
#(
parameter PERIOD_BITS = 16
)
(
input clk_in, // system clock signal
input rst_in, // reset signal
input pulse_in, // input pulse
input reload_in, // reset counter to period_in (no pulse_out generated)
input [PERIOD_BITS-1:0] period_in, // new period value
output pulse_out // divided output pulse
);
reg [PERIOD_BITS-1:0] q_cnt;
wire [PERIOD_BITS-1:0] d_cnt;
always @(posedge clk_in)
begin
if (rst_in)
q_cnt <= 0;
else
q_cnt <= d_cnt;
end
assign d_cnt = (reload_in || (pulse_in && (q_cnt == 0))) ? period_in :
(pulse_in) ? q_cnt - 1'h1 : q_cnt;
assign pulse_out = pulse_in && (q_cnt == 0);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_FUNCTIONAL_PP_V |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/05/27 14:31:02 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.3.12.2 2011/05/27 14:31:02 venkatp Exp $
**$Date: 2011/05/27 14:31:02 $
**$Author: venkatp $
**$Revision: 1.3.12.2 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_2/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module iodelay_ctrl #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name when
// multiple IP cores used in design
parameter INPUT_CLK_TYPE = "DIFFERENTIAL", // input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter RST_ACT_LOW = 1, // Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE"
// Differential Termination
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output clk_ref,
output iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_bufg;
wire clk_ref_ibufg;
wire rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input
//***************************************************************************
generate
if (INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (INPUT_CLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
end
endgenerate
//***************************************************************************
// Global clock buffer for IDELAY reference clock
//***************************************************************************
BUFG u_bufg_clk_ref
(
.O (clk_ref_bufg),
.I (clk_ref_ibufg)
);
assign clk_ref = clk_ref_bufg;
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
always @(posedge clk_ref_bufg or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r <= #TCQ rst_ref_sync_r << 1;
assign rst_ref = rst_ref_sync_r[RST_SYNC_NUM-1];
//*****************************************************************
(* IODELAY_GROUP = IODELAY_GRP *) IDELAYCTRL u_idelayctrl
(
.RDY (iodelay_ctrl_rdy),
.REFCLK (clk_ref_bufg),
.RST (rst_ref)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pcie_upconfig_fix_3451_v6.v
// Version : 2.3
//--
//-- Description: Virtex6 Workaround for Root Port Upconfigurability Bug
//--
//--
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module pcie_upconfig_fix_3451_v6 # (
parameter UPSTREAM_FACING = "TRUE",
parameter PL_FAST_TRAIN = "FALSE",
parameter LINK_CAP_MAX_LINK_WIDTH = 6'h08,
parameter TCQ = 1
)
(
input pipe_clk,
input pl_phy_lnkup_n,
input [5:0] pl_ltssm_state,
input pl_sel_lnk_rate,
input [1:0] pl_directed_link_change,
input [3:0] cfg_link_status_negotiated_width,
input [15:0] pipe_rx0_data,
input [1:0] pipe_rx0_char_isk,
output filter_pipe
);
reg reg_filter_pipe;
reg [15:0] reg_tsx_counter;
wire [15:0] tsx_counter;
wire [5:0] cap_link_width;
// Corrupting all Tsx on all lanes as soon as we do R.RC->R.RI transition to allow time for
// the core to see the TS1s on all the lanes being configured at the same time
// R.RI has a 2ms timeout.Corrupting tsxs for ~1/4 of that time
// 225 pipe_clk cycles-sim_fast_train
// 60000 pipe_clk cycles-without sim_fast_train
// Not taking any action when PLDIRECTEDLINKCHANGE is set
// Detect xx, COM then PAD,xx or COM,PAD then PAD,xx
// data0 will be the first symbol on lane 0, data1 will be the next symbol.
// Don't look for PAD on data1 since it's unnecessary.
// COM=0xbc and PAD=0xf7 (and isk).
// detect if (data & 0xb4) == 0xb4 and isk, and then
// if (data & 0x4b) == 0x08 or 0x43. This distinguishes COM and PAD, using
// no more than a 6-input LUT, so should be "free".
reg reg_filter_used, reg_com_then_pad;
reg reg_data0_b4, reg_data0_08, reg_data0_43;
reg reg_data1_b4, reg_data1_08, reg_data1_43;
reg reg_data0_com, reg_data1_com, reg_data1_pad;
wire data0_b4 = pipe_rx0_char_isk[0] &&
((pipe_rx0_data[7:0] & 8'hb4) == 8'hb4);
wire data0_08 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h08);
wire data0_43 = ((pipe_rx0_data[7:0] & 8'h4b) == 8'h43);
wire data1_b4 = pipe_rx0_char_isk[1] &&
((pipe_rx0_data[15:8] & 8'hb4) == 8'hb4);
wire data1_08 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h08);
wire data1_43 = ((pipe_rx0_data[15:8] & 8'h4b) == 8'h43);
wire data0_com = reg_data0_b4 && reg_data0_08;
wire data1_com = reg_data1_b4 && reg_data1_08;
wire data0_pad = reg_data0_b4 && reg_data0_43;
wire data1_pad = reg_data1_b4 && reg_data1_43;
wire com_then_pad0 = reg_data0_com && reg_data1_pad && data0_pad;
wire com_then_pad1 = reg_data1_com && data0_pad && data1_pad;
wire com_then_pad = (com_then_pad0 || com_then_pad1) && ~reg_filter_used;
wire filter_used = (pl_ltssm_state == 6'h20) &&
(reg_filter_pipe || reg_filter_used);
always @(posedge pipe_clk) begin
reg_data0_b4 <= #TCQ data0_b4;
reg_data0_08 <= #TCQ data0_08;
reg_data0_43 <= #TCQ data0_43;
reg_data1_b4 <= #TCQ data1_b4;
reg_data1_08 <= #TCQ data1_08;
reg_data1_43 <= #TCQ data1_43;
reg_data0_com <= #TCQ data0_com;
reg_data1_com <= #TCQ data1_com;
reg_data1_pad <= #TCQ data1_pad;
reg_com_then_pad <= #TCQ (~pl_phy_lnkup_n) ? com_then_pad : 1'b0;
reg_filter_used <= #TCQ (~pl_phy_lnkup_n) ? filter_used : 1'b0;
end
always @ (posedge pipe_clk) begin
if (pl_phy_lnkup_n) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end else if ((pl_ltssm_state == 6'h20) &&
reg_com_then_pad &&
(cfg_link_status_negotiated_width != cap_link_width) &&
(pl_directed_link_change[1:0] == 2'b00)) begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b1;
end else if (filter_pipe == 1'b1) begin
if (tsx_counter < ((PL_FAST_TRAIN == "TRUE") ? 16'd225: pl_sel_lnk_rate ? 16'd800 : 16'd400)) begin
reg_tsx_counter <= #TCQ tsx_counter + 1'b1;
reg_filter_pipe <= #TCQ 1'b1;
end else begin
reg_tsx_counter <= #TCQ 16'h0;
reg_filter_pipe <= #TCQ 1'b0;
end
end
end
assign filter_pipe = (UPSTREAM_FACING == "TRUE") ? 1'b0 : reg_filter_pipe;
assign tsx_counter = reg_tsx_counter;
assign cap_link_width = LINK_CAP_MAX_LINK_WIDTH;
endmodule
|
`timescale 1ns / 1ps
`include "collaterals.v"
`include "z80_opcode_definitions.v"
`include "aDefinitions.v"
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ([email protected])
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
module dzcpu
(
input wire iClock,
input wire iReset,
input wire [7:0] iMCUData,
output wire [7:0] oMCUData,
output wire [15:0] oMCUAddr,
output wire oMcuReadRequest,
input wire [3:0] iInterruptRequests,
output reg oMCUwe
);
wire[15:0] wPc, wRegData, wUopSrc, wX16, wY16, wZ16, wInitialPc, wInterruptVectorAddress, wXY16 ;
wire [7:0] wBitMask, wX8, wY8;
wire [8:0] wuOpBasicFlowIdx,wuOpExtendedFlowIdx, wuOpFlowIdx, wuPc;
wire wIPC,wEof, wZ, wN;
wire [13:0] wUop;
wire [4:0 ] wuCmd;
wire [4:0] wMcuAdrrSel;
wire [2:0] wUopRegReadAddr0, wUopRegReadAddr1, rUopRegWriteAddr;
wire [7:0] wB,wC,wD, wE, wH,wL,wA, wSpL, wSpH, wFlags, wUopSrcRegData0;
wire [7:0] wSHR_RegData, wUopSrcRegData1, wNextUopFlowIdx;
wire [3:0] wInterruptRequestBitMap, wInterruptRequestBitMaps_pre;
wire wInterruptsEnabled;
wire [8:0] wNextFlow; //output of Interruption MUX
reg rSetiWe,rSetiVal; // set FF_INTENABLE
reg rClearIntLatch; // clean FF_INTSIGNAL
reg rResetFlow,rFlowEnable, rRegWe, rSetMCOAddr, rOverWritePc, rCarry, rMcuReadRequest;
reg [4:0] rRegSelect;
reg [7:0] rZ80Result, rWriteSelect;
reg [15:0] rUopDstRegData;
assign wUopSrc = wUop[4:0];
assign wIPC = wUop[13]; //Increment Macro Insn program counter
assign wuCmd = wUop[9:5];
MUXFULLPARALELL_3SEL_GENERIC # ( 1'b1 ) MUX_EOF
(
.Sel( wUop[12:10] ),
.I0( 1'b0 ),.I1( 1'b0 ),.I2( 1'b0 ),.I3( 1'b0 ),
.I4( 1'b1 ), .I5( wFlags[`flag_z] ), .I6( 1'b1 ), .I7( ~wFlags[`flag_z] ),
.O( wEof )
);
dzcpu_ucode_rom urom
(
.iAddr( wuPc ),
.oUop( wUop )
);
dzcpu_ucode_lut ulut
(
.iMop( iMCUData ),
.oUopFlowIdx( wuOpBasicFlowIdx )
);
dzcpu_ucode_cblut ucblut
(
.iMop( iMCUData ),
.oUopFlowIdx( wuOpExtendedFlowIdx )
);
wire wJcbDetected, wInterruptRoutineJumpDetected;
assign wInterruptRoutineJumpDetected = ( rFlowEnable & wuCmd == `jint ) ? 1'b1 : 1'b0;
assign wJcbDetected = ( rFlowEnable & wuCmd == `jcb ) ? 1'b1 : 1'b0;
//Hold the int signal while we wait for current flow to finish
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 )FF_INTSIGNAL( iClock, iReset | rClearIntLatch, 4'b0 , iInterruptRequests, wInterruptRequestBitMaps_pre );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 )FF_INTENABLE( iClock, iReset, rFlowEnable & rSetiWe, rSetiVal, wInterruptsEnabled );
//Disregard interrupts if interrupts are disabled
assign wInterruptRequestBitMap = ( wInterruptsEnabled == 1'b1) ? wInterruptRequestBitMaps_pre : 4'b0;
UPCOUNTER_POSEDGE # (9) UPC
(
.Clock( iClock ),
.Reset( iReset | rResetFlow | wJcbDetected ),
.Initial( wNextFlow ),
.Enable( rFlowEnable ),
.Q( wuPc )
);
assign wNextFlow = (iReset) ? 9'b0 : wuOpFlowIdx;
MUXFULLPARALELL_2SEL_GENERIC # (9) MUX_NEXT_FLOW
(
.Sel({wInterruptRoutineJumpDetected,wJcbDetected}),
.I0( wuOpBasicFlowIdx ),
.I1( wuOpExtendedFlowIdx ),
.I2( `FLOW_ID_INTERRUPT ),
.I3( `FLOW_ID_INTERRUPT ),
.O( wuOpFlowIdx )
);
MUXFULLPARALELL_4SEL_GENERIC # (16) MUX_INTERRUPT
(
.Sel( wInterruptRequestBitMap ),
.I0( wPc ), //0000 No interrupts, use the normal flow
.I1( `INT_ADDR_VBLANK ), //0001 -- Interrupt routine 0x40
.I2( `INT_ADDR_LCD_STATUS_TRIGGER), //0010
.I3( `INT_ADDR_VBLANK ), //0011 -- Interrupt routine 0x40
.I4( `INT_ADDR_TIMER_OVERFLOW), //0100
.I5( `INT_ADDR_VBLANK), //0101
.I6( `INT_ADDR_TIMER_OVERFLOW), //0110
.I7( `INT_ADDR_VBLANK ), //0111
.I8( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1000
.I9( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1001
.I10( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1010
.I11( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1011
.I12( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1100
.I13( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1101
.I14( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1110
.I15( `INT_ADDR_VBLANK_JOYPAD_PRESS), //1111
.O( wInterruptVectorAddress )
);
`ifdef SKIP_BIOS
assign wInitialPc = ( rOverWritePc ) ? rUopDstRegData : 16'h100;
`else
assign wInitialPc = ( rOverWritePc ) ? rUopDstRegData : 16'b0;
`endif
UPCOUNTER_POSEDGE # (16) PC
(
.Clock( iClock ),
.Reset( iReset | rOverWritePc ),
.Initial( wInitialPc ),
`ifdef DISABLE_CPU
.Enable( 1'b0 ),
`else
.Enable( wIPC & rFlowEnable ),
`endif
.Q( wPc )
);
//--------------------------------------------------------
// Current State Logic //
reg [7:0] rCurrentState,rNextState;
always @(posedge iClock )
begin
if( iReset!=1 )
rCurrentState <= rNextState;
else
rCurrentState <= `DZCPU_AFTER_RESET;
end
//--------------------------------------------------------
always @( * )
begin
case (rCurrentState)
//----------------------------------------
`DZCPU_AFTER_RESET:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b0;
rNextState = `DZCPU_START_FLOW;
end
//----------------------------------------
`DZCPU_START_FLOW:
begin
rResetFlow = 1'b1;
rFlowEnable = 1'b0;
if (iReset)
rNextState = `DZCPU_AFTER_RESET;
else
rNextState = `DZCPU_RUN_FLOW;
end
//----------------------------------------
`DZCPU_RUN_FLOW:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b1;
if (wEof)
rNextState = `DZCPU_END_FLOW;
else
rNextState = `DZCPU_RUN_FLOW;
end
//----------------------------------------
`DZCPU_END_FLOW:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b0;
rNextState = `DZCPU_START_FLOW;
end
//----------------------------------------
default:
begin
rResetFlow = 1'b0;
rFlowEnable = 1'b0;
rNextState = `DZCPU_AFTER_RESET;
end
endcase
end
reg [13:0] rRegWriteSelect;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFB ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[0], (( rRegWriteSelect[1] & rRegWriteSelect[0])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wB );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFC ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[1], rUopDstRegData[7:0], wC );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[2], (( rRegWriteSelect[2] & rRegWriteSelect[3])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wD );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFE ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[3], rUopDstRegData[7:0], wE );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFH ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[4], (( rRegWriteSelect[4] & rRegWriteSelect[5])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wH );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFL ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[5], rUopDstRegData[7:0], wL );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFA ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[6], rUopDstRegData[7:0], wA );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FFSPL( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[7], rUopDstRegData[7:0], wSpL );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FFSPH( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[8], (( rRegWriteSelect[7] & rRegWriteSelect[8])? rUopDstRegData[15:8] : rUopDstRegData[7:0]), wSpH );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 )FFX8 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[9], rUopDstRegData[7:0], wX8 );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FFX16 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[10], rUopDstRegData[15:0], wX16 );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FFY16 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[11], rUopDstRegData[15:0], wY8 );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FFZ16 ( iClock, iReset, rFlowEnable & rRegWe & rRegWriteSelect[12], rUopDstRegData[15:0], wZ16 );
//wire[15:0] wUopDstRegData_Prev;
//FFD_POSEDGE_SYNCRONOUS_RESET # ( 16)FF_RESULT_PREV ( iClock, iReset, 1'b1, rUopDstRegData, wUopDstRegData_Prev);
reg [1:0] rFlagsZ, rFlagsN, rFlagsH, rFlagsC;
wire wFlagsWe;
wire wCarry, wCarry16, wCarry12, wHalfCarry_Inc, wHalfCarry_Add, wHalfCarry_Dec;
wire [7:0] wFlagsUpdate;
wire [3:0] wNibble;
//assign {wHalfCarry,wNibble} = (rSubFlags ==1'b0) ? wRegData[3:0] + 1'b1 : wRegData[3:0] - 1'b1;
assign wHalfCarry_Inc = ((rUopDstRegData & 16'hf) == 16'h0) ? 1'b1 : 1'b0;
assign wHalfCarry_Dec = ((rUopDstRegData & 16'hf) == 16'hf) ? 1'b1 : 1'b0;
//assign wHalfCarry_Add = rUopDstRegData[4];
assign {wHalfCarry_Add, wNibble} = wRegData[3:0] + wX16[3:0];
//assign wHalfCarry = wUopDstRegData_Prev[4]; //Need value from prev CC
assign wCarry = rUopDstRegData[8];
assign wCarry16 = rUopDstRegData[15];
assign wCarry12 = rUopDstRegData[12];
assign wFlagsWe = rFlowEnable & (wUop[ `uop_flags_update_enable ] == 1'b1 || wuCmd == `z801bop )
& ( rFlagsZ[1] | rFlagsN[1] | rFlagsH[1] | rFlagsC[1] );
assign wFlagsUpdate[`flag_z ] = ( rFlagsZ[1] == 1'b1 ) ? rFlagsZ[0] : wFlags[`flag_z ] ;
assign wFlagsUpdate[`flag_h ] = ( rFlagsH[1] == 1'b1 ) ? rFlagsH[0] : wFlags[`flag_h ] ;
assign wFlagsUpdate[`flag_n ] = ( rFlagsN[1] == 1'b1 ) ? rFlagsN[0] : wFlags[`flag_n ] ;
assign wFlagsUpdate[`flag_c ] = ( rFlagsC[1] == 1'b1 ) ? rFlagsC[0] : wFlags[`flag_c ] ;
assign wFlagsUpdate[3:0] = 4'b0;
FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( 8 )FFFLAGS( iClock, iReset, wFlagsWe , 8'hb0,wFlagsUpdate, wFlags );
FFD_POSEDGE_SYNCRONOUS_RESET_INIT # ( 5 )FFMCUADR( iClock, iReset, rFlowEnable & rSetMCOAddr, `pc , wUop[4:0], wMcuAdrrSel );
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 )FF_RREQ( iClock, iReset, rFlowEnable & ~oMCUwe, rMcuReadRequest, oMcuReadRequest );
MUXFULLPARALELL_5SEL_GENERIC # (16) MUX_MCUADR
(
.Sel( wMcuAdrrSel),
.I0({8'b0,wB}), .I1({8'b0,wC}), .I2({8'b0,wD}), .I3({8'b0,wE}),
.I4({8'b0,wH}), .I5({8'b0,wL}), .I6({wH,wL}), .I7({8'b0,wA}),
.I8(wPc), .I9({8'b0,wPc[15:8]}), .I10({wSpH,wSpL}), .I11({8'b0,wFlags}) ,
.I12({8'b0,wSpL}), .I13( {8'b0,wSpH} ), .I14( wY16 ), .I15( wZ16 ),
.I16({8'b0,wX8 }), .I17( wX16), .I18({8'hff,wC}), .I19({wD,wE}),
.I20({8'b0,wFlags }), .I21({wB,wC}), .I22({wA,wFlags}), .I23(16'b0),
.I24(16'b0), .I25({8'b0,wY8} ), .I26({wX8,wY8 }), .I27(16'b0),
.I28(16'b0), .I29(16'b0), .I30(16'b0), .I31(16'b0),
.O( oMCUAddr )
);
MUXFULLPARALELL_5SEL_GENERIC # (16) MUX_REGDATA
(
.Sel( rRegSelect),
.I0({8'b0,wB}), .I1({8'b0,wC}), .I2({8'b0,wD}), .I3({8'b0,wE}),
.I4({8'b0,wH}), .I5({8'b0,wL}), .I6({wH,wL}), .I7({8'b0,wA}),
.I8(wPc), .I9({8'b0,wPc[15:8]}), .I10({wSpH,wSpL}), .I11({8'b0,wFlags}) ,
.I12({8'b0,wSpL}), .I13( {8'b0,wSpH} ), .I14( wY16 ), .I15( wZ16 ),
.I16({8'b0,wX8 }), .I17( wX16), .I18({8'hff,wC}), .I19({wD,wE}),
.I20({8'b0,wFlags }), .I21({wB,wC}), .I22({wA,wFlags}), .I23({8'b0,iMCUData}),
.I24({15'b0,wFlags[`flag_c]}), .I25( {8'b0,wY8 } ), .I26( {wX8,wY8 }), .I27(16'b0),
.I28(16'b0), .I29(16'b0), .I30(16'b0), .I31(16'b0),
.O( wRegData )
);
MUXFULLPARALELL_5SEL_GENERIC # (8) MUX_MCUDATA_OUT
(
.Sel( rRegSelect),
.I0(wB), .I1(wC), .I2(wD), .I3(wE),
.I4(wH), .I5(wL), .I6(wL), .I7(wA),
.I8(wPc[7:0]), .I9(wPc[15:8]), .I10(wSpL), .I11(wFlags) ,
.I12(wSpL), .I13( wSpH ), .I14( wY16[7:0] ), .I15( wZ16[7:0] ),
.I16(wX8 ), .I17( wX16[7:0]), .I18(wC), .I19(wE),
.I20(wFlags ), .I21(wC), .I22(wFlags), .I23(8'b0),
.I24({7'b0,wFlags[`flag_c]}), .I25( wY8 ), .I26( wX8 ), .I27(8'b0),
.I28(8'b0), .I29(8'b0), .I30(8'b0), .I31(8'b0),
.O( oMCUData )
);
always @ ( * )
begin
case (rWriteSelect)
`b: rRegWriteSelect = 14'b00000000000001;
`c: rRegWriteSelect = 14'b00000000000010;
`bc: rRegWriteSelect = 14'b00000000000011;
`d: rRegWriteSelect = 14'b00000000000100;
`e: rRegWriteSelect = 14'b00000000001000;
`de: rRegWriteSelect = 14'b00000000001100;
`h: rRegWriteSelect = 14'b00000000010000;
`l: rRegWriteSelect = 14'b00000000100000;
`hl: rRegWriteSelect = 14'b00000000110000;
`a: rRegWriteSelect = 14'b00000001000000;
`spl: rRegWriteSelect = 14'b00000010000000;
`sph: rRegWriteSelect = 14'b00000100000000;
`sp: rRegWriteSelect = 14'b00000110000000;
`x8: rRegWriteSelect = 14'b00001000000000;
`x16: rRegWriteSelect = 14'b00010000000000;
`y8: rRegWriteSelect = 14'b00100000000000;
`xy16: rRegWriteSelect = 14'b01000000000000;
`f: rRegWriteSelect = 14'b10000000000000;
default: rRegWriteSelect = 13'b0;
endcase
end
assign wZ = (rUopDstRegData[7:0] ==8'b0) ? 1'b1 : 1'b0;
assign wN = (rUopDstRegData[7] == 1'b1) ? 1'b1 : 1'b0;
assign wSHR_RegData = wRegData >> 1;
always @ ( * )
begin
case (wuCmd)
`nop:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`sma:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b1;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b1;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`srm:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = iMCUData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`smw:
begin
oMCUwe = 1'b1;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`dec16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = wRegData - 16'd1;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`inc16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = wRegData + 1'b1;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`xorx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
rUopDstRegData = wX16 ^ {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`subx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
rUopDstRegData = wX16 - {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`xora:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `a;
rUopDstRegData = {8'b0,wA} ^ {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`anda:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `a;
rUopDstRegData = {8'b0,wA} & {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`addx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
rUopDstRegData = wX16 + {{8{wRegData[7]}},wRegData[7:0]}; //sign extended 2'complement
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`addx16u:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
rUopDstRegData = wX16 + {8'b0,wRegData[7:0]};
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`addx16r16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
rUopDstRegData = wX16 + wRegData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`spc:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = wRegData;
rOverWritePc = 1'b1;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`jint: //Jump to interrupt routine
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = `pc;
rUopDstRegData = wInterruptVectorAddress;
rOverWritePc = 1'b1;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b1;
end
`jcb: //Jump to extended Z80 flow (0xCB command)
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`srx8:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = wX8;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`srx16:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = wX16;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`z801bop:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = ( iMCUData[7:6] == 2'b01 ) ? iMCUData[5:3] : wUopSrc[7:0];
rUopDstRegData = rZ80Result;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`shl:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = {5'b0,iMCUData[2:0]};
rUopDstRegData = (wRegData << 1) + wFlags[`flag_c];
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`rrot:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = {5'b0,iMCUData[2:0]};
rUopDstRegData = {wFlags[`flag_c], wSHR_RegData[6:0] };
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`shr:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = {5'b0,iMCUData[2:0]};
rUopDstRegData = wSHR_RegData[7:0];
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`bit:
begin
oMCUwe = 1'b0;
rRegSelect = {1'b0,iMCUData[2:0]};
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = wRegData & wBitMask;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`sx8r:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x8;
rUopDstRegData = wRegData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`sx16r:
begin
oMCUwe = 1'b0;
rRegSelect = wUop[4:0];
rSetMCOAddr = 1'b0;
rRegWe = 1'b1;
rWriteSelect = `x16;
rUopDstRegData = wRegData;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`seti:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = 8'b0;
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b1;
rSetiVal = 1'b1;
rClearIntLatch = 1'b0;
end
`ceti: //Disable interruption
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = 8'b0;
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b1;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
`cibit:
begin
oMCUwe = 1'b0;
rRegSelect = `null;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = 8'b0;
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b1;
end
default:
begin
oMCUwe = 1'b0;
rRegSelect = `pc;
rSetMCOAddr = 1'b0;
rRegWe = 1'b0;
rWriteSelect = wUopSrc[7:0];
rUopDstRegData = 16'b0;
rOverWritePc = 1'b0;
rMcuReadRequest = 1'b0;
rSetiWe = 1'b0;
rSetiVal = 1'b0;
rClearIntLatch = 1'b0;
end
endcase
end
//Flags
// +----+-----+----+----+---------+
// | Z | N | H | C | 4'b0 |
// +----+-----+----+----+---------+
wire [7:0] wCurrentFlow;
wire wCBFlow, wIsCBFlow;
assign wIsCBFlow = (wuCmd == `jcb) ? 1'b1 : 1'b0;
FFD_POSEDGE_SYNCRONOUS_RESET # (8) FFD_CURFLOW (
iClock, iReset, (rResetFlow | wIsCBFlow),iMCUData, wCurrentFlow);
FFD_POSEDGE_SYNCRONOUS_RESET # (1) FFD_CBFLOW (
iClock, iReset, 1'b1 ,wIsCBFlow, wCBFlow);
always @ ( * )
begin
case ({wCBFlow,wCurrentFlow})
{1'b0,`INCr_a},{1'b0,`INCr_b},{1'b0,`INCr_c},{1'b0,`INCr_d},
{1'b0,`INCr_e},{1'b0,`INCr_h},{1'b0,`INCr_l}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0}; //Can never be neg
rFlagsH = {1'b1,wHalfCarry_Inc};
rFlagsC = {1'b0,1'b0};
end
{1'b0,`DECr_b},{1'b0,`DECr_c},{1'b0,`DECr_d},{1'b0,`DECr_e},
{1'b0,`DECr_h},{1'b0,`DECr_l},{1'b0,`DECr_a}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b1}; //Gearboy behaves like this
rFlagsH = {1'b1,wHalfCarry_Dec};
rFlagsC = {1'b0,1'b0}; //This is needed to make BIOS work...
end
{1'b0,`ADDHLHL}, {1'b0,`ADDHLDE}:
begin
rFlagsZ = {1'b0,1'b0};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b1,wCarry12};
rFlagsC = {1'b0,wCarry16};
end
{1'b0,`ADDr_a}, {1'b0,`ADDr_b}, {1'b0,`ADDr_c},{1'b0, `ADDr_d},
{1'b0,`ADDr_h}, {1'b0,`ADDr_l}, {1'b0,`ADDr_e},{1'b0, `ADDn},
{1'b0,`SUBr_a}, {1'b0,`SUBr_b}, {1'b0,`SUBr_e},{1'b0, `SUBr_d},
{1'b0,`SUBr_h}, {1'b0,`SUBr_l}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,wHalfCarry_Add};
rFlagsC = {1'b1,wCarry};
end
{1'b0,`CPn}:
begin
rFlagsZ = {1'b1,wZ}; // A == n
rFlagsN = {1'b1,1'b1};
rFlagsH = {1'b1,~wN}; //A > n
rFlagsC = {1'b1,wN}; //A < n
end
{1'b0,`ANDr_a},{1'b0,`ANDr_b},
{1'b0,`ANDr_c},
{1'b0,`ANDr_d},{1'b0,`ANDr_e},
{1'b0,`ANDr_h},{1'b0,`ANDr_l}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b1,1'b1}; //H is set
rFlagsC = {1'b1,1'b0};
end
{1'b0,`RLA}:
begin
rFlagsZ = {1'b0,1'b0};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,wA[7]};
end
{1'b0,`RRA}:
begin
rFlagsZ = {1'b0,1'b0};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,wA[0]};
end
{1'b1,`RLr_a},{1'b1,`RLr_b},{1'b1,`RLr_d},{1'b1,`RLr_e},
{1'b1,`RLr_h},{1'b1,`RLr_l},{1'b1,`RLr_c}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,wN};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,wRegData[7]};
end
{1'b0,`ORr_a}, {1'b0,`ORr_b}, {1'b0,`ORr_d},{1'b0,`ORr_c},
{1'b0,`ORr_e}, {1'b0,`ORr_h}, {1'b0,`ORr_l},
{1'b0,`XORr_a},{1'b0,`XORr_b},{1'b0,`XORr_d},{1'b0,`XORr_c},
{1'b0,`XORr_e},{1'b0,`XORr_h},{1'b0,`XORr_l},{1'b0,`XORHL}:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b1,1'b0};
rFlagsH = {1'b1,1'b0}; //H is reset
rFlagsC = {1'b1,1'b0}; //C is reset
end
{1'b1, `BIT7h }, {1'b1, `BIT7l }, {1'b1, `BIT7m }, {1'b1, `BIT7a }:
begin
rFlagsZ = {1'b1,wZ};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b0,1'b0};
rFlagsC = {1'b0,1'b0};
end
default:
begin
rFlagsZ = {1'b0,1'b0};
rFlagsN = {1'b0,1'b0};
rFlagsH = {1'b0,1'b0};
rFlagsC = {1'b0,1'b0};
end
endcase
end
DECODER_MASK_3_BITS BIT_MASK( iMCUData[5:3], wBitMask );
always @ ( * )
begin
case (iMCUData[7:3])
5'b10100: rZ80Result = wA & wRegData; //AND
5'b10101: rZ80Result = wA ^ wRegData; //XOR
5'b10110: rZ80Result = wA | wRegData; //OR
5'b01000, 5'b01001, 5'b01010, 5'b01011, 5'b01100, 5'b01101, 5'b01110, 5'b01111: rZ80Result = wRegData; //ldrr
default: rZ80Result = 8'hcc;
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_SYMBOL_V
`define SKY130_FD_SC_LP__BUSDRIVER2_SYMBOL_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__busdriver2 (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_SYMBOL_V
|
module step_ex_ld(clk, rst_, ena_, rdy_,
mem_re_, abus, dbus,
r1_dout, r0_din, r0_we_);
input clk;
input rst_;
input ena_;
output rdy_;
output mem_re_;
output[7:0] abus;
input[7:0] dbus;
input[7:0] r1_dout;
output[7:0] r0_din;
output r0_we_;
reg rdy_en;
assign rdy_ = rdy_en ? 1'b0 : 1'bZ;
reg mem_re_en;
assign mem_re_ = mem_re_en ? 1'b0 : 1'bZ;
assign abus = mem_re_en ? r1_dout : 8'bZ;
assign r0_din = mem_re_en ? dbus : 8'bZ;
reg r0_we_en;
assign r0_we_ = r0_we_en ? 1'b0 : 1'bZ;
reg[1:0] state;
always @(negedge rst_ or posedge clk)
if(!rst_) begin
rdy_en <= 0;
mem_re_en <= 0;
r0_we_en <= 0;
state <= 0;
end else begin
/*
State 0: ena_=0 state=00
rdy_en=0 mem_re_en=1 r0_we_en=0 state=01
State 1: ena_=1 state=01
rdy_en=0 mem_re_en=1 r0_we_en=1 state=10
State 2: ena_=1 state=10
rdy_en=1 mem_re_en=0 r0_we_en=0 state=00
State 3: ena_=1 state=00
rdy_en=0 mem_re_en=0 r0_we_en=0 state=00
*/
rdy_en <= state[1];
mem_re_en <= state[0] | ~ena_;
r0_we_en <= state[0];
state <= {state[0], ~ena_};
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_BEHAVIORAL_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output Other arguments
bufif1 bufif10 (Z , !D[0], S[0] );
bufif1 bufif11 (Z , !D[1], S[1] );
bufif1 bufif12 (Z , !D[2], S[2] );
bufif1 bufif13 (Z , !D[3], S[3] );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
wire Overflow_flag;
wire Underflow_flag;
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
//Date : Mon Sep 16 06:33:56 2019
//Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module design_1_wrapper
(DDR_0_addr,
DDR_0_ba,
DDR_0_cas_n,
DDR_0_ck_n,
DDR_0_ck_p,
DDR_0_cke,
DDR_0_cs_n,
DDR_0_dm,
DDR_0_dq,
DDR_0_dqs_n,
DDR_0_dqs_p,
DDR_0_odt,
DDR_0_ras_n,
DDR_0_reset_n,
DDR_0_we_n,
FIXED_IO_0_ddr_vrn,
FIXED_IO_0_ddr_vrp,
FIXED_IO_0_mio,
FIXED_IO_0_ps_clk,
FIXED_IO_0_ps_porb,
FIXED_IO_0_ps_srstb,
reset_rtl);
inout [14:0]DDR_0_addr;
inout [2:0]DDR_0_ba;
inout DDR_0_cas_n;
inout DDR_0_ck_n;
inout DDR_0_ck_p;
inout DDR_0_cke;
inout DDR_0_cs_n;
inout [3:0]DDR_0_dm;
inout [31:0]DDR_0_dq;
inout [3:0]DDR_0_dqs_n;
inout [3:0]DDR_0_dqs_p;
inout DDR_0_odt;
inout DDR_0_ras_n;
inout DDR_0_reset_n;
inout DDR_0_we_n;
inout FIXED_IO_0_ddr_vrn;
inout FIXED_IO_0_ddr_vrp;
inout [53:0]FIXED_IO_0_mio;
inout FIXED_IO_0_ps_clk;
inout FIXED_IO_0_ps_porb;
inout FIXED_IO_0_ps_srstb;
input reset_rtl;
wire [14:0]DDR_0_addr;
wire [2:0]DDR_0_ba;
wire DDR_0_cas_n;
wire DDR_0_ck_n;
wire DDR_0_ck_p;
wire DDR_0_cke;
wire DDR_0_cs_n;
wire [3:0]DDR_0_dm;
wire [31:0]DDR_0_dq;
wire [3:0]DDR_0_dqs_n;
wire [3:0]DDR_0_dqs_p;
wire DDR_0_odt;
wire DDR_0_ras_n;
wire DDR_0_reset_n;
wire DDR_0_we_n;
wire FIXED_IO_0_ddr_vrn;
wire FIXED_IO_0_ddr_vrp;
wire [53:0]FIXED_IO_0_mio;
wire FIXED_IO_0_ps_clk;
wire FIXED_IO_0_ps_porb;
wire FIXED_IO_0_ps_srstb;
wire reset_rtl;
design_1 design_1_i
(.DDR_0_addr(DDR_0_addr),
.DDR_0_ba(DDR_0_ba),
.DDR_0_cas_n(DDR_0_cas_n),
.DDR_0_ck_n(DDR_0_ck_n),
.DDR_0_ck_p(DDR_0_ck_p),
.DDR_0_cke(DDR_0_cke),
.DDR_0_cs_n(DDR_0_cs_n),
.DDR_0_dm(DDR_0_dm),
.DDR_0_dq(DDR_0_dq),
.DDR_0_dqs_n(DDR_0_dqs_n),
.DDR_0_dqs_p(DDR_0_dqs_p),
.DDR_0_odt(DDR_0_odt),
.DDR_0_ras_n(DDR_0_ras_n),
.DDR_0_reset_n(DDR_0_reset_n),
.DDR_0_we_n(DDR_0_we_n),
.FIXED_IO_0_ddr_vrn(FIXED_IO_0_ddr_vrn),
.FIXED_IO_0_ddr_vrp(FIXED_IO_0_ddr_vrp),
.FIXED_IO_0_mio(FIXED_IO_0_mio),
.FIXED_IO_0_ps_clk(FIXED_IO_0_ps_clk),
.FIXED_IO_0_ps_porb(FIXED_IO_0_ps_porb),
.FIXED_IO_0_ps_srstb(FIXED_IO_0_ps_srstb),
.reset_rtl(reset_rtl));
endmodule
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: March, 9th 2017
*/
`timescale 1ns / 1ps
/*
input sampling rate must be the same as clk frequency
interpolation the input signal accordingly to get the
right sampling rate
*/
module jt12_dac #(parameter width=12)
(
input clk,
input rst,
input signed [width-1:0] din,
output dout
);
localparam acc_w = width+1;
reg [width-1:0] nosign;
reg [acc_w-1:0] acc;
wire [acc_w-2:0] err = acc[acc_w-2:0];
assign dout = acc[acc_w-1];
always @(posedge clk)
if( rst ) begin
acc <= {(acc_w){1'b0}};
nosign <= {width{1'b0}};
end
else begin
nosign <= { ~din[width-1], din[width-2:0] };
acc <= nosign + err;
end
endmodule
|
`timescale 1ns / 1ps
module tx_DS_sel(
input txClk,
input txReset,
input ready_i,
input reqTimecode_i,
input reqSpaceAvail_i,
input reqData_i,
input reqIdle_i,
input [8:0] dat_i,
output ackTimecode_o,
output ackSpaceAvail_o,
output ackData_o,
output ackIdle_o,
output valid_o,
output [8:0] dat_o
);
reg sendingTimecode,
sendingCredit,
sendingData,
sendingIdle,
escPending;
reg [5:0] txCredit;
reg ackTimecode_o, ackSpaceAvail_o, ackData_o, ackIdle_o, valid_o;
wire haveCredit = |txCredit;
wire isBusy = |{sendingTimecode, sendingCredit, sendingData, sendingIdle, escPending};
wire isNChar = dat_i[8] == 0;
wire isEOP = (dat_i[8] == 1) && ((dat_i[1:0] == 2'b01) || (dat_i[1:0] == 2'b10));
wire isValid = isNChar | isEOP;
always @(posedge txClk) begin
sendingTimecode <= sendingTimecode;
sendingCredit <= sendingCredit;
sendingData <= sendingData;
sendingIdle <= sendingIdle;
escPending <= escPending;
txCredit <= txCredit;
valid_o <= 0;
ackTimecode_o <= 0;
ackSpaceAvail_o <= 0;
ackData_o <= 0;
ackIdle_o <= 0;
if(txReset) begin
sendingTimecode <= 0;
sendingCredit <= 0;
sendingData <= 0;
sendingIdle <= 0;
escPending <= 0;
txCredit <= 0;
end
else begin
if(~isBusy && ready_i) begin
if(reqTimecode_i) begin
ackTimecode_o <= 1;
sendingTimecode <= 1;
escPending <= 1;
dat_o <= 9'b1_0000_0011;
valid_o <= 1;
end
else if(reqSpaceAvail_i) begin
ackSpaceAvail_o <= 1;
sendingCredit <= 1;
dat_o <= 9'b1_0000_0000;
valid_o <= 1;
end
else if(reqData_i && isValid && haveCredit) begin
ackData_o <= 1;
sendingData <= 1;
dat_o <= dat_i;
valid_o <= 1;
txCredit <= txCredit - 1;
end
else if(reqData_i && ~isValid) begin
ackData_o <= 1;
end
else if(reqIdle_i) begin
ackIdle_o <= 1;
sendingIdle <= 1;
escPending <= 1;
dat_o <= 8'b1_0000_0011;
valid_o <= 1;
end
end
else if(isBusy && ready_i) begin
if(sendingTimecode && escPending && ~sendingCredit && ~sendingData && ~sendingIdle) begin
escPending <= 0;
sendingData <= 1;
dat_o <= {1'b0, timecode_i};
valid_o <= 1;
end
if(sendingTimecode && sendingData && ~sendingCredit && ~sendingIdle && ~escPending) begin
sendingTimecode <= 0;
sendingData <= 0;
end
if(~sendingTimecode && ~sendingData && ~sendingIdle && ~escPending && sendingCredit) begin
sendingCredit <= 0;
end
if(~sendingTimecode && ~sendingCredit && ~sendingData && sendingIdle && escPending) begin
escPending <= 0;
sendingCredit <= 1;
dat_o <= 9'b1_0000_0000;
valid_o <= 1;
end
if(~sendingTimecode && ~sendingData && ~escPending && sendingCredit && sendingIdle) begin
sendingCredit <= 0;
sendingIdle <= 0;
end
end
end
end
endmodule
|
`default_nettype none
module scheduler2_free_search_64to2(
input wire iENTRY0_VALID,
input wire iENTRY1_VALID,
input wire iENTRY2_VALID,
input wire iENTRY3_VALID,
input wire iENTRY4_VALID,
input wire iENTRY5_VALID,
input wire iENTRY6_VALID,
input wire iENTRY7_VALID,
input wire iENTRY8_VALID,
input wire iENTRY9_VALID,
input wire iENTRY10_VALID,
input wire iENTRY11_VALID,
input wire iENTRY12_VALID,
input wire iENTRY13_VALID,
input wire iENTRY14_VALID,
input wire iENTRY15_VALID,
input wire iENTRY16_VALID,
input wire iENTRY17_VALID,
input wire iENTRY18_VALID,
input wire iENTRY19_VALID,
input wire iENTRY20_VALID,
input wire iENTRY21_VALID,
input wire iENTRY22_VALID,
input wire iENTRY23_VALID,
input wire iENTRY24_VALID,
input wire iENTRY25_VALID,
input wire iENTRY26_VALID,
input wire iENTRY27_VALID,
input wire iENTRY28_VALID,
input wire iENTRY29_VALID,
input wire iENTRY30_VALID,
input wire iENTRY31_VALID,
input wire iENTRY32_VALID,
input wire iENTRY33_VALID,
input wire iENTRY34_VALID,
input wire iENTRY35_VALID,
input wire iENTRY36_VALID,
input wire iENTRY37_VALID,
input wire iENTRY38_VALID,
input wire iENTRY39_VALID,
input wire iENTRY40_VALID,
input wire iENTRY41_VALID,
input wire iENTRY42_VALID,
input wire iENTRY43_VALID,
input wire iENTRY44_VALID,
input wire iENTRY45_VALID,
input wire iENTRY46_VALID,
input wire iENTRY47_VALID,
input wire iENTRY48_VALID,
input wire iENTRY49_VALID,
input wire iENTRY50_VALID,
input wire iENTRY51_VALID,
input wire iENTRY52_VALID,
input wire iENTRY53_VALID,
input wire iENTRY54_VALID,
input wire iENTRY55_VALID,
input wire iENTRY56_VALID,
input wire iENTRY57_VALID,
input wire iENTRY58_VALID,
input wire iENTRY59_VALID,
input wire iENTRY60_VALID,
input wire iENTRY61_VALID,
input wire iENTRY62_VALID,
input wire iENTRY63_VALID,
//Output
output wire oSELECT0_VALID,
output wire [5:0] oSELECT0_ENTRY,
output wire oSELECT1_VALID,
output wire [5:0] oSELECT1_ENTRY
);
assign {
oSELECT1_VALID, oSELECT1_ENTRY,
oSELECT0_VALID, oSELECT0_ENTRY
} = func_free_entry_search64to2(
iENTRY0_VALID,
iENTRY1_VALID,
iENTRY2_VALID,
iENTRY3_VALID,
iENTRY4_VALID,
iENTRY5_VALID,
iENTRY6_VALID,
iENTRY7_VALID,
iENTRY8_VALID,
iENTRY9_VALID,
iENTRY10_VALID,
iENTRY11_VALID,
iENTRY12_VALID,
iENTRY13_VALID,
iENTRY14_VALID,
iENTRY15_VALID,
iENTRY16_VALID,
iENTRY17_VALID,
iENTRY18_VALID,
iENTRY19_VALID,
iENTRY20_VALID,
iENTRY21_VALID,
iENTRY22_VALID,
iENTRY23_VALID,
iENTRY24_VALID,
iENTRY25_VALID,
iENTRY26_VALID,
iENTRY27_VALID,
iENTRY28_VALID,
iENTRY29_VALID,
iENTRY30_VALID,
iENTRY31_VALID,
iENTRY32_VALID,
iENTRY33_VALID,
iENTRY34_VALID,
iENTRY35_VALID,
iENTRY36_VALID,
iENTRY37_VALID,
iENTRY38_VALID,
iENTRY39_VALID,
iENTRY40_VALID,
iENTRY41_VALID,
iENTRY42_VALID,
iENTRY43_VALID,
iENTRY44_VALID,
iENTRY45_VALID,
iENTRY46_VALID,
iENTRY47_VALID,
iENTRY48_VALID,
iENTRY49_VALID,
iENTRY50_VALID,
iENTRY51_VALID,
iENTRY52_VALID,
iENTRY53_VALID,
iENTRY54_VALID,
iENTRY55_VALID,
iENTRY56_VALID,
iENTRY57_VALID,
iENTRY58_VALID,
iENTRY59_VALID,
iENTRY60_VALID,
iENTRY61_VALID,
iENTRY62_VALID,
iENTRY63_VALID
);
//Reservation station or General Register Free Entry Search
function [13:0] func_free_entry_search64to2;
/* Output Signal
[13] : Entry 1 Valid
[12:7] : Entry 1 Table Numver
[6] : Entry 0 Valid
[5:0] : Entry 0 Table Number
*/
input func_free_entry_search64to2_entry_valid0;
input func_free_entry_search64to2_entry_valid1;
input func_free_entry_search64to2_entry_valid2;
input func_free_entry_search64to2_entry_valid3;
input func_free_entry_search64to2_entry_valid4;
input func_free_entry_search64to2_entry_valid5;
input func_free_entry_search64to2_entry_valid6;
input func_free_entry_search64to2_entry_valid7;
input func_free_entry_search64to2_entry_valid8;
input func_free_entry_search64to2_entry_valid9;
input func_free_entry_search64to2_entry_valid10;
input func_free_entry_search64to2_entry_valid11;
input func_free_entry_search64to2_entry_valid12;
input func_free_entry_search64to2_entry_valid13;
input func_free_entry_search64to2_entry_valid14;
input func_free_entry_search64to2_entry_valid15;
input func_free_entry_search64to2_entry_valid16;
input func_free_entry_search64to2_entry_valid17;
input func_free_entry_search64to2_entry_valid18;
input func_free_entry_search64to2_entry_valid19;
input func_free_entry_search64to2_entry_valid20;
input func_free_entry_search64to2_entry_valid21;
input func_free_entry_search64to2_entry_valid22;
input func_free_entry_search64to2_entry_valid23;
input func_free_entry_search64to2_entry_valid24;
input func_free_entry_search64to2_entry_valid25;
input func_free_entry_search64to2_entry_valid26;
input func_free_entry_search64to2_entry_valid27;
input func_free_entry_search64to2_entry_valid28;
input func_free_entry_search64to2_entry_valid29;
input func_free_entry_search64to2_entry_valid30;
input func_free_entry_search64to2_entry_valid31;
input func_free_entry_search64to2_entry_valid32;
input func_free_entry_search64to2_entry_valid33;
input func_free_entry_search64to2_entry_valid34;
input func_free_entry_search64to2_entry_valid35;
input func_free_entry_search64to2_entry_valid36;
input func_free_entry_search64to2_entry_valid37;
input func_free_entry_search64to2_entry_valid38;
input func_free_entry_search64to2_entry_valid39;
input func_free_entry_search64to2_entry_valid40;
input func_free_entry_search64to2_entry_valid41;
input func_free_entry_search64to2_entry_valid42;
input func_free_entry_search64to2_entry_valid43;
input func_free_entry_search64to2_entry_valid44;
input func_free_entry_search64to2_entry_valid45;
input func_free_entry_search64to2_entry_valid46;
input func_free_entry_search64to2_entry_valid47;
input func_free_entry_search64to2_entry_valid48;
input func_free_entry_search64to2_entry_valid49;
input func_free_entry_search64to2_entry_valid50;
input func_free_entry_search64to2_entry_valid51;
input func_free_entry_search64to2_entry_valid52;
input func_free_entry_search64to2_entry_valid53;
input func_free_entry_search64to2_entry_valid54;
input func_free_entry_search64to2_entry_valid55;
input func_free_entry_search64to2_entry_valid56;
input func_free_entry_search64to2_entry_valid57;
input func_free_entry_search64to2_entry_valid58;
input func_free_entry_search64to2_entry_valid59;
input func_free_entry_search64to2_entry_valid60;
input func_free_entry_search64to2_entry_valid61;
input func_free_entry_search64to2_entry_valid62;
input func_free_entry_search64to2_entry_valid63;
reg func_free_entry_search64to2_tournament_data0_valid0;
reg [5:0] func_free_entry_search64to2_tournament_data0_num0;
reg func_free_entry_search64to2_tournament_data0_valid1;
reg [5:0] func_free_entry_search64to2_tournament_data0_num1;
reg func_free_entry_search64to2_tournament_data1_valid0[0:1];
reg [5:0] func_free_entry_search64to2_tournament_data1_num0[0:1];
reg func_free_entry_search64to2_tournament_data1_valid1[0:1];
reg [5:0] func_free_entry_search64to2_tournament_data1_num1[0:1];
reg func_free_entry_search64to2_tournament_data2_valid0[0:3];
reg [5:0] func_free_entry_search64to2_tournament_data2_num0[0:3];
reg func_free_entry_search64to2_tournament_data2_valid1[0:3];
reg [5:0] func_free_entry_search64to2_tournament_data2_num1[0:3];
reg func_free_entry_search64to2_tournament_data3_valid0[0:7];
reg [5:0] func_free_entry_search64to2_tournament_data3_num0[0:7];
reg func_free_entry_search64to2_tournament_data3_valid1[0:7];
reg [5:0] func_free_entry_search64to2_tournament_data3_num1[0:7];
reg func_free_entry_search64to2_tournament_data4_valid0[0:15];
reg [5:0] func_free_entry_search64to2_tournament_data4_num0[0:15];
reg func_free_entry_search64to2_tournament_data4_valid1[0:15];
reg [5:0] func_free_entry_search64to2_tournament_data4_num1[0:15];
/*
reg func_free_entry_search64to2_tournament_data5_valid0[0:31];
reg [5:0] func_free_entry_search64to2_tournament_data5_num0[0:31];
reg func_free_entry_search64to2_tournament_data5_valid1[0:31];
reg [5:0] func_free_entry_search64to2_tournament_data5_num1[0:31];
*/
begin
//5
//4
func_free_entry_search64to2_tournament_data4_valid0[0] = func_free_entry_search64to2_entry_valid0 | func_free_entry_search64to2_entry_valid1;
func_free_entry_search64to2_tournament_data4_num0[0] = (func_free_entry_search64to2_entry_valid0)? 6'h00 : 6'h01;
func_free_entry_search64to2_tournament_data4_valid1[0] = func_free_entry_search64to2_entry_valid2 | func_free_entry_search64to2_entry_valid3;
func_free_entry_search64to2_tournament_data4_num1[0] = (func_free_entry_search64to2_entry_valid2)? 6'h02 : 6'h03;
func_free_entry_search64to2_tournament_data4_valid0[1] = func_free_entry_search64to2_entry_valid4 | func_free_entry_search64to2_entry_valid5;
func_free_entry_search64to2_tournament_data4_num0[1] = (func_free_entry_search64to2_entry_valid4)? 6'h04 : 6'h05;
func_free_entry_search64to2_tournament_data4_valid1[1] = func_free_entry_search64to2_entry_valid6 | func_free_entry_search64to2_entry_valid7;
func_free_entry_search64to2_tournament_data4_num1[1] = (func_free_entry_search64to2_entry_valid6)? 6'h06 : 6'h07;
func_free_entry_search64to2_tournament_data4_valid0[2] = func_free_entry_search64to2_entry_valid8 | func_free_entry_search64to2_entry_valid9;
func_free_entry_search64to2_tournament_data4_num0[2] = (func_free_entry_search64to2_entry_valid8)? 6'h08 : 6'h09;
func_free_entry_search64to2_tournament_data4_valid1[2] = func_free_entry_search64to2_entry_valid10 | func_free_entry_search64to2_entry_valid11;
func_free_entry_search64to2_tournament_data4_num1[2] = (func_free_entry_search64to2_entry_valid10)? 6'h0A : 6'h0B;
func_free_entry_search64to2_tournament_data4_valid0[3] = func_free_entry_search64to2_entry_valid11 | func_free_entry_search64to2_entry_valid13;
func_free_entry_search64to2_tournament_data4_num0[3] = (func_free_entry_search64to2_entry_valid12)? 6'h0C : 6'h0D;
func_free_entry_search64to2_tournament_data4_valid1[3] = func_free_entry_search64to2_entry_valid14 | func_free_entry_search64to2_entry_valid15;
func_free_entry_search64to2_tournament_data4_num1[3] = (func_free_entry_search64to2_entry_valid14)? 6'h0E : 6'h0F;
func_free_entry_search64to2_tournament_data4_valid0[4] = func_free_entry_search64to2_entry_valid16 | func_free_entry_search64to2_entry_valid17;
func_free_entry_search64to2_tournament_data4_num0[4] = (func_free_entry_search64to2_entry_valid16)? 6'h10 : 6'h11;
func_free_entry_search64to2_tournament_data4_valid1[4] = func_free_entry_search64to2_entry_valid16 | func_free_entry_search64to2_entry_valid19;
func_free_entry_search64to2_tournament_data4_num1[4] = (func_free_entry_search64to2_entry_valid18)? 6'h12 : 6'h13;
func_free_entry_search64to2_tournament_data4_valid0[5] = func_free_entry_search64to2_entry_valid20 | func_free_entry_search64to2_entry_valid21;
func_free_entry_search64to2_tournament_data4_num0[5] = (func_free_entry_search64to2_entry_valid20)? 6'h14 : 6'h15;
func_free_entry_search64to2_tournament_data4_valid1[5] = func_free_entry_search64to2_entry_valid22 | func_free_entry_search64to2_entry_valid23;
func_free_entry_search64to2_tournament_data4_num1[5] = (func_free_entry_search64to2_entry_valid22)? 6'h16 : 6'h17;
func_free_entry_search64to2_tournament_data4_valid0[6] = func_free_entry_search64to2_entry_valid24 | func_free_entry_search64to2_entry_valid25;
func_free_entry_search64to2_tournament_data4_num0[6] = (func_free_entry_search64to2_entry_valid24)? 6'h18 : 6'h19;
func_free_entry_search64to2_tournament_data4_valid1[6] = func_free_entry_search64to2_entry_valid26 | func_free_entry_search64to2_entry_valid27;
func_free_entry_search64to2_tournament_data4_num1[6] = (func_free_entry_search64to2_entry_valid26)? 6'h1A : 6'h1B;
func_free_entry_search64to2_tournament_data4_valid0[7] = func_free_entry_search64to2_entry_valid28 | func_free_entry_search64to2_entry_valid29;
func_free_entry_search64to2_tournament_data4_num0[7] = (func_free_entry_search64to2_entry_valid28)? 6'h1C : 6'h1D;
func_free_entry_search64to2_tournament_data4_valid1[7] = func_free_entry_search64to2_entry_valid30 | func_free_entry_search64to2_entry_valid31;
func_free_entry_search64to2_tournament_data4_num1[7] = (func_free_entry_search64to2_entry_valid30)? 6'h1E : 6'h1F;
func_free_entry_search64to2_tournament_data4_valid0[8] = func_free_entry_search64to2_entry_valid32 | func_free_entry_search64to2_entry_valid33;
func_free_entry_search64to2_tournament_data4_num0[8] = (func_free_entry_search64to2_entry_valid32)? 6'h20 : 6'h21;
func_free_entry_search64to2_tournament_data4_valid1[8] = func_free_entry_search64to2_entry_valid34 | func_free_entry_search64to2_entry_valid35;
func_free_entry_search64to2_tournament_data4_num1[8] = (func_free_entry_search64to2_entry_valid34)? 6'h22 : 6'h23;
func_free_entry_search64to2_tournament_data4_valid0[9] = func_free_entry_search64to2_entry_valid36 | func_free_entry_search64to2_entry_valid37;
func_free_entry_search64to2_tournament_data4_num0[9] = (func_free_entry_search64to2_entry_valid36)? 6'h24 : 6'h25;
func_free_entry_search64to2_tournament_data4_valid1[9] = func_free_entry_search64to2_entry_valid38 | func_free_entry_search64to2_entry_valid39;
func_free_entry_search64to2_tournament_data4_num1[9] = (func_free_entry_search64to2_entry_valid38)? 6'h26 : 6'h27;
func_free_entry_search64to2_tournament_data4_valid0[10] = func_free_entry_search64to2_entry_valid40 | func_free_entry_search64to2_entry_valid41;
func_free_entry_search64to2_tournament_data4_num0[10] = (func_free_entry_search64to2_entry_valid40)? 6'h28 : 6'h29;
func_free_entry_search64to2_tournament_data4_valid1[10] = func_free_entry_search64to2_entry_valid42 | func_free_entry_search64to2_entry_valid43;
func_free_entry_search64to2_tournament_data4_num1[10] = (func_free_entry_search64to2_entry_valid42)? 6'h2A : 6'h2B;
func_free_entry_search64to2_tournament_data4_valid0[11] = func_free_entry_search64to2_entry_valid44 | func_free_entry_search64to2_entry_valid45;
func_free_entry_search64to2_tournament_data4_num0[11] = (func_free_entry_search64to2_entry_valid44)? 6'h2C : 6'h2D;
func_free_entry_search64to2_tournament_data4_valid1[11] = func_free_entry_search64to2_entry_valid46 | func_free_entry_search64to2_entry_valid47;
func_free_entry_search64to2_tournament_data4_num1[11] = (func_free_entry_search64to2_entry_valid46)? 6'h2E : 6'h2F;
func_free_entry_search64to2_tournament_data4_valid0[12] = func_free_entry_search64to2_entry_valid48 | func_free_entry_search64to2_entry_valid49;
func_free_entry_search64to2_tournament_data4_num0[12] = (func_free_entry_search64to2_entry_valid48)? 6'h30 : 6'h31;
func_free_entry_search64to2_tournament_data4_valid1[12] = func_free_entry_search64to2_entry_valid50 | func_free_entry_search64to2_entry_valid51;
func_free_entry_search64to2_tournament_data4_num1[12] = (func_free_entry_search64to2_entry_valid50)? 6'h32 : 6'h33;
func_free_entry_search64to2_tournament_data4_valid0[13] = func_free_entry_search64to2_entry_valid52 | func_free_entry_search64to2_entry_valid53;
func_free_entry_search64to2_tournament_data4_num0[13] = (func_free_entry_search64to2_entry_valid52)? 6'h34 : 6'h35;
func_free_entry_search64to2_tournament_data4_valid1[13] = func_free_entry_search64to2_entry_valid54 | func_free_entry_search64to2_entry_valid55;
func_free_entry_search64to2_tournament_data4_num1[13] = (func_free_entry_search64to2_entry_valid54)? 6'h36 : 6'h37;
func_free_entry_search64to2_tournament_data4_valid0[14] = func_free_entry_search64to2_entry_valid56 | func_free_entry_search64to2_entry_valid57;
func_free_entry_search64to2_tournament_data4_num0[14] = (func_free_entry_search64to2_entry_valid56)? 6'h38 : 6'h39;
func_free_entry_search64to2_tournament_data4_valid1[14] = func_free_entry_search64to2_entry_valid58 | func_free_entry_search64to2_entry_valid59;
func_free_entry_search64to2_tournament_data4_num1[14] = (func_free_entry_search64to2_entry_valid58)? 6'h3A : 6'h3B;
func_free_entry_search64to2_tournament_data4_valid0[15] = func_free_entry_search64to2_entry_valid60 | func_free_entry_search64to2_entry_valid61;
func_free_entry_search64to2_tournament_data4_num0[15] = (func_free_entry_search64to2_entry_valid60)? 6'h3C : 6'h3D;
func_free_entry_search64to2_tournament_data4_valid1[15] = func_free_entry_search64to2_entry_valid62 | func_free_entry_search64to2_entry_valid63;
func_free_entry_search64to2_tournament_data4_num1[15] = (func_free_entry_search64to2_entry_valid62)? 6'h3E : 6'h3F;
//3
func_free_entry_search64to2_tournament_data3_valid0[0] = func_free_entry_search64to2_tournament_data4_valid0[0] || func_free_entry_search64to2_tournament_data4_valid1[0];
func_free_entry_search64to2_tournament_data3_num0[0] = (func_free_entry_search64to2_tournament_data4_valid0[0])? func_free_entry_search64to2_tournament_data4_num0[0] : func_free_entry_search64to2_tournament_data4_num1[0];
func_free_entry_search64to2_tournament_data3_valid1[0] = func_free_entry_search64to2_tournament_data4_valid0[1] || func_free_entry_search64to2_tournament_data4_valid1[1];
func_free_entry_search64to2_tournament_data3_num1[0] = (func_free_entry_search64to2_tournament_data4_valid0[1])? func_free_entry_search64to2_tournament_data4_num0[1] : func_free_entry_search64to2_tournament_data4_num1[1];
func_free_entry_search64to2_tournament_data3_valid0[1] = func_free_entry_search64to2_tournament_data4_valid0[2] || func_free_entry_search64to2_tournament_data4_valid1[2];
func_free_entry_search64to2_tournament_data3_num0[1] = (func_free_entry_search64to2_tournament_data4_valid0[2])? func_free_entry_search64to2_tournament_data4_num0[2] : func_free_entry_search64to2_tournament_data4_num1[2];
func_free_entry_search64to2_tournament_data3_valid1[1] = func_free_entry_search64to2_tournament_data4_valid0[3] || func_free_entry_search64to2_tournament_data4_valid1[3];
func_free_entry_search64to2_tournament_data3_num1[1] = (func_free_entry_search64to2_tournament_data4_valid0[3])? func_free_entry_search64to2_tournament_data4_num0[3] : func_free_entry_search64to2_tournament_data4_num1[3];
func_free_entry_search64to2_tournament_data3_valid0[2] = func_free_entry_search64to2_tournament_data4_valid0[4] || func_free_entry_search64to2_tournament_data4_valid1[4];
func_free_entry_search64to2_tournament_data3_num0[2] = (func_free_entry_search64to2_tournament_data4_valid0[4])? func_free_entry_search64to2_tournament_data4_num0[4] : func_free_entry_search64to2_tournament_data4_num1[4];
func_free_entry_search64to2_tournament_data3_valid1[2] = func_free_entry_search64to2_tournament_data4_valid0[5] || func_free_entry_search64to2_tournament_data4_valid1[5];
func_free_entry_search64to2_tournament_data3_num1[2] = (func_free_entry_search64to2_tournament_data4_valid0[5])? func_free_entry_search64to2_tournament_data4_num0[5] : func_free_entry_search64to2_tournament_data4_num1[5];
func_free_entry_search64to2_tournament_data3_valid0[3] = func_free_entry_search64to2_tournament_data4_valid0[6] || func_free_entry_search64to2_tournament_data4_valid1[6];
func_free_entry_search64to2_tournament_data3_num0[3] = (func_free_entry_search64to2_tournament_data4_valid0[6])? func_free_entry_search64to2_tournament_data4_num0[6] : func_free_entry_search64to2_tournament_data4_num1[6];
func_free_entry_search64to2_tournament_data3_valid1[3] = func_free_entry_search64to2_tournament_data4_valid0[7] || func_free_entry_search64to2_tournament_data4_valid1[7];
func_free_entry_search64to2_tournament_data3_num1[3] = (func_free_entry_search64to2_tournament_data4_valid0[7])? func_free_entry_search64to2_tournament_data4_num0[7] : func_free_entry_search64to2_tournament_data4_num1[7];
func_free_entry_search64to2_tournament_data3_valid0[4] = func_free_entry_search64to2_tournament_data4_valid0[8] || func_free_entry_search64to2_tournament_data4_valid1[8];
func_free_entry_search64to2_tournament_data3_num0[4] = (func_free_entry_search64to2_tournament_data4_valid0[8])? func_free_entry_search64to2_tournament_data4_num0[8] : func_free_entry_search64to2_tournament_data4_num1[8];
func_free_entry_search64to2_tournament_data3_valid1[4] = func_free_entry_search64to2_tournament_data4_valid0[9] || func_free_entry_search64to2_tournament_data4_valid1[9];
func_free_entry_search64to2_tournament_data3_num1[4] = (func_free_entry_search64to2_tournament_data4_valid0[9])? func_free_entry_search64to2_tournament_data4_num0[9] : func_free_entry_search64to2_tournament_data4_num1[9];
func_free_entry_search64to2_tournament_data3_valid0[5] = func_free_entry_search64to2_tournament_data4_valid0[10] || func_free_entry_search64to2_tournament_data4_valid1[10];
func_free_entry_search64to2_tournament_data3_num0[5] = (func_free_entry_search64to2_tournament_data4_valid0[10])? func_free_entry_search64to2_tournament_data4_num0[10] : func_free_entry_search64to2_tournament_data4_num1[10];
func_free_entry_search64to2_tournament_data3_valid1[5] = func_free_entry_search64to2_tournament_data4_valid0[11] || func_free_entry_search64to2_tournament_data4_valid1[11];
func_free_entry_search64to2_tournament_data3_num1[5] = (func_free_entry_search64to2_tournament_data4_valid0[11])? func_free_entry_search64to2_tournament_data4_num0[11] : func_free_entry_search64to2_tournament_data4_num1[11];
func_free_entry_search64to2_tournament_data3_valid0[6] = func_free_entry_search64to2_tournament_data4_valid0[12] || func_free_entry_search64to2_tournament_data4_valid1[12];
func_free_entry_search64to2_tournament_data3_num0[6] = (func_free_entry_search64to2_tournament_data4_valid0[12])? func_free_entry_search64to2_tournament_data4_num0[12] : func_free_entry_search64to2_tournament_data4_num1[12];
func_free_entry_search64to2_tournament_data3_valid1[6] = func_free_entry_search64to2_tournament_data4_valid0[13] || func_free_entry_search64to2_tournament_data4_valid1[13];
func_free_entry_search64to2_tournament_data3_num1[6] = (func_free_entry_search64to2_tournament_data4_valid0[13])? func_free_entry_search64to2_tournament_data4_num0[13] : func_free_entry_search64to2_tournament_data4_num1[13];
func_free_entry_search64to2_tournament_data3_valid0[7] = func_free_entry_search64to2_tournament_data4_valid0[14] || func_free_entry_search64to2_tournament_data4_valid1[14];
func_free_entry_search64to2_tournament_data3_num0[7] = (func_free_entry_search64to2_tournament_data4_valid0[14])? func_free_entry_search64to2_tournament_data4_num0[14] : func_free_entry_search64to2_tournament_data4_num1[14];
func_free_entry_search64to2_tournament_data3_valid1[7] = func_free_entry_search64to2_tournament_data4_valid0[15] || func_free_entry_search64to2_tournament_data4_valid1[15];
func_free_entry_search64to2_tournament_data3_num1[7] = (func_free_entry_search64to2_tournament_data4_valid0[15])? func_free_entry_search64to2_tournament_data4_num0[15] : func_free_entry_search64to2_tournament_data4_num1[15];
//2
func_free_entry_search64to2_tournament_data2_valid0[0] = func_free_entry_search64to2_tournament_data3_valid0[0] || func_free_entry_search64to2_tournament_data3_valid1[0];
func_free_entry_search64to2_tournament_data2_num0[0] = (func_free_entry_search64to2_tournament_data3_valid0[0])? func_free_entry_search64to2_tournament_data3_num0[0] : func_free_entry_search64to2_tournament_data3_num1[0];
func_free_entry_search64to2_tournament_data2_valid1[0] = func_free_entry_search64to2_tournament_data3_valid0[1] || func_free_entry_search64to2_tournament_data3_valid1[1];
func_free_entry_search64to2_tournament_data2_num1[0] = (func_free_entry_search64to2_tournament_data3_valid0[1])? func_free_entry_search64to2_tournament_data3_num0[1] : func_free_entry_search64to2_tournament_data3_num1[1];
func_free_entry_search64to2_tournament_data2_valid0[1] = func_free_entry_search64to2_tournament_data3_valid0[2] || func_free_entry_search64to2_tournament_data3_valid1[2];
func_free_entry_search64to2_tournament_data2_num0[1] = (func_free_entry_search64to2_tournament_data3_valid0[2])? func_free_entry_search64to2_tournament_data3_num0[2] : func_free_entry_search64to2_tournament_data3_num1[2];
func_free_entry_search64to2_tournament_data2_valid1[1] = func_free_entry_search64to2_tournament_data3_valid0[3] || func_free_entry_search64to2_tournament_data3_valid1[3];
func_free_entry_search64to2_tournament_data2_num1[1] = (func_free_entry_search64to2_tournament_data3_valid0[3])? func_free_entry_search64to2_tournament_data3_num0[3] : func_free_entry_search64to2_tournament_data3_num1[3];
func_free_entry_search64to2_tournament_data2_valid0[2] = func_free_entry_search64to2_tournament_data3_valid0[4] || func_free_entry_search64to2_tournament_data3_valid1[4];
func_free_entry_search64to2_tournament_data2_num0[2] = (func_free_entry_search64to2_tournament_data3_valid0[4])? func_free_entry_search64to2_tournament_data3_num0[4] : func_free_entry_search64to2_tournament_data3_num1[4];
func_free_entry_search64to2_tournament_data2_valid1[2] = func_free_entry_search64to2_tournament_data3_valid0[5] || func_free_entry_search64to2_tournament_data3_valid1[5];
func_free_entry_search64to2_tournament_data2_num1[2] = (func_free_entry_search64to2_tournament_data3_valid0[5])? func_free_entry_search64to2_tournament_data3_num0[5] : func_free_entry_search64to2_tournament_data3_num1[5];
func_free_entry_search64to2_tournament_data2_valid0[3] = func_free_entry_search64to2_tournament_data3_valid0[6] || func_free_entry_search64to2_tournament_data3_valid1[6];
func_free_entry_search64to2_tournament_data2_num0[3] = (func_free_entry_search64to2_tournament_data3_valid0[6])? func_free_entry_search64to2_tournament_data3_num0[6] : func_free_entry_search64to2_tournament_data3_num1[6];
func_free_entry_search64to2_tournament_data2_valid1[3] = func_free_entry_search64to2_tournament_data3_valid0[7] || func_free_entry_search64to2_tournament_data3_valid1[7];
func_free_entry_search64to2_tournament_data2_num1[3] = (func_free_entry_search64to2_tournament_data3_valid0[7])? func_free_entry_search64to2_tournament_data3_num0[7] : func_free_entry_search64to2_tournament_data3_num1[7];
//1
func_free_entry_search64to2_tournament_data1_valid0[0] = func_free_entry_search64to2_tournament_data2_valid0[0] || func_free_entry_search64to2_tournament_data2_valid1[0];
func_free_entry_search64to2_tournament_data1_num0[0] = (func_free_entry_search64to2_tournament_data2_valid0[0])? func_free_entry_search64to2_tournament_data2_num0[0] : func_free_entry_search64to2_tournament_data2_num1[0];
func_free_entry_search64to2_tournament_data1_valid1[0] = func_free_entry_search64to2_tournament_data2_valid0[1] || func_free_entry_search64to2_tournament_data2_valid1[1];
func_free_entry_search64to2_tournament_data1_num1[0] = (func_free_entry_search64to2_tournament_data2_valid0[1])? func_free_entry_search64to2_tournament_data2_num0[1] : func_free_entry_search64to2_tournament_data2_num1[1];
func_free_entry_search64to2_tournament_data1_valid0[1] = func_free_entry_search64to2_tournament_data2_valid0[2] || func_free_entry_search64to2_tournament_data2_valid1[2];
func_free_entry_search64to2_tournament_data1_num0[1] = (func_free_entry_search64to2_tournament_data2_valid0[2])? func_free_entry_search64to2_tournament_data2_num0[2] : func_free_entry_search64to2_tournament_data2_num1[2];
func_free_entry_search64to2_tournament_data1_valid1[1] = func_free_entry_search64to2_tournament_data2_valid0[3] || func_free_entry_search64to2_tournament_data2_valid1[3];
func_free_entry_search64to2_tournament_data1_num1[1] = (func_free_entry_search64to2_tournament_data2_valid0[3])? func_free_entry_search64to2_tournament_data2_num0[3] : func_free_entry_search64to2_tournament_data2_num1[3];
//0
func_free_entry_search64to2_tournament_data0_valid0 = func_free_entry_search64to2_tournament_data1_valid0[0] || func_free_entry_search64to2_tournament_data1_valid1[0];
func_free_entry_search64to2_tournament_data0_num0 = (func_free_entry_search64to2_tournament_data1_valid0[0])? func_free_entry_search64to2_tournament_data1_num0[0] : func_free_entry_search64to2_tournament_data1_num1[0];
func_free_entry_search64to2_tournament_data0_valid1 = func_free_entry_search64to2_tournament_data1_valid0[1] || func_free_entry_search64to2_tournament_data1_valid1[1];
func_free_entry_search64to2_tournament_data0_num1 = (func_free_entry_search64to2_tournament_data1_valid0[1])? func_free_entry_search64to2_tournament_data1_num0[1] : func_free_entry_search64to2_tournament_data1_num1[1];
//2 Set
if(func_free_entry_search64to2_tournament_data0_valid0 & func_free_entry_search64to2_tournament_data0_valid1)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data0_num0;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data0_num1;
end
else if(func_free_entry_search64to2_tournament_data1_valid0[0] & func_free_entry_search64to2_tournament_data1_valid1[0])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data1_num0[0];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data1_num1[0];
end
else if(func_free_entry_search64to2_tournament_data1_valid0[1] & func_free_entry_search64to2_tournament_data1_valid1[1])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data1_num0[1];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data1_num1[1];
end
else if(func_free_entry_search64to2_tournament_data2_valid0[0] & func_free_entry_search64to2_tournament_data2_valid1[0])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data2_num0[0];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data2_num1[0];
end
else if(func_free_entry_search64to2_tournament_data2_valid0[1] & func_free_entry_search64to2_tournament_data2_valid1[1])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data2_num0[1];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data2_num1[1];
end
else if(func_free_entry_search64to2_tournament_data2_valid0[2] & func_free_entry_search64to2_tournament_data2_valid1[2])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data2_num0[2];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data2_num1[2];
end
else if(func_free_entry_search64to2_tournament_data2_valid0[3] & func_free_entry_search64to2_tournament_data2_valid1[3])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data2_num0[3];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data2_num1[3];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[0] & func_free_entry_search64to2_tournament_data3_valid1[0])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[0];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[0];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[1] & func_free_entry_search64to2_tournament_data3_valid1[1])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[1];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[1];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[2] & func_free_entry_search64to2_tournament_data3_valid1[2])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[2];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[2];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[3] & func_free_entry_search64to2_tournament_data3_valid1[3])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[3];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[3];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[4] & func_free_entry_search64to2_tournament_data3_valid1[4])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[4];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[4];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[5] & func_free_entry_search64to2_tournament_data3_valid1[5])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[5];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[5];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[6] & func_free_entry_search64to2_tournament_data3_valid1[6])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[6];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[6];
end
else if(func_free_entry_search64to2_tournament_data3_valid0[7] & func_free_entry_search64to2_tournament_data3_valid1[7])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data3_num0[7];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data3_num1[7];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[0] & func_free_entry_search64to2_tournament_data4_valid1[0])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[0];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[0];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[1] & func_free_entry_search64to2_tournament_data4_valid1[1])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[1];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[1];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[2] & func_free_entry_search64to2_tournament_data4_valid1[2])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[2];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[2];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[3] & func_free_entry_search64to2_tournament_data4_valid1[3])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[3];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[3];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[4] & func_free_entry_search64to2_tournament_data4_valid1[4])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[4];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[4];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[5] & func_free_entry_search64to2_tournament_data4_valid1[5])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[5];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[5];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[6] & func_free_entry_search64to2_tournament_data4_valid1[6])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[6];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[6];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[7] & func_free_entry_search64to2_tournament_data4_valid1[7])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[7];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[7];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[8] & func_free_entry_search64to2_tournament_data4_valid1[8])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[8];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[8];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[9] & func_free_entry_search64to2_tournament_data4_valid1[9])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[9];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[9];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[10] & func_free_entry_search64to2_tournament_data4_valid1[10])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[10];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[01];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[11] & func_free_entry_search64to2_tournament_data4_valid1[11])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[11];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[11];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[12] & func_free_entry_search64to2_tournament_data4_valid1[12])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[12];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[12];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[13] & func_free_entry_search64to2_tournament_data4_valid1[13])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[13];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[13];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[14] & func_free_entry_search64to2_tournament_data4_valid1[14])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[14];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[14];
end
else if(func_free_entry_search64to2_tournament_data4_valid0[15] & func_free_entry_search64to2_tournament_data4_valid1[15])begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = func_free_entry_search64to2_tournament_data4_num0[15];
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data4_num1[15];
end
else if(func_free_entry_search64to2_entry_valid0 & func_free_entry_search64to2_entry_valid1)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd0;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd1;
end
else if(func_free_entry_search64to2_entry_valid2 & func_free_entry_search64to2_entry_valid3)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd2;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd3;
end
else if(func_free_entry_search64to2_entry_valid4 & func_free_entry_search64to2_entry_valid5)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd4;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd5;
end
else if(func_free_entry_search64to2_entry_valid6 & func_free_entry_search64to2_entry_valid7)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd6;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd7;
end
else if(func_free_entry_search64to2_entry_valid8 & func_free_entry_search64to2_entry_valid9)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd8;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd9;
end
else if(func_free_entry_search64to2_entry_valid10 & func_free_entry_search64to2_entry_valid11)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd10;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd11;
end
else if(func_free_entry_search64to2_entry_valid12 & func_free_entry_search64to2_entry_valid13)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd12;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd13;
end
else if(func_free_entry_search64to2_entry_valid14 & func_free_entry_search64to2_entry_valid15)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd14;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd15;
end
else if(func_free_entry_search64to2_entry_valid16 & func_free_entry_search64to2_entry_valid17)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd16;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd17;
end
else if(func_free_entry_search64to2_entry_valid18 & func_free_entry_search64to2_entry_valid19)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd18;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd19;
end
else if(func_free_entry_search64to2_entry_valid20 & func_free_entry_search64to2_entry_valid21)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd20;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd21;
end
else if(func_free_entry_search64to2_entry_valid22 & func_free_entry_search64to2_entry_valid23)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd22;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd23;
end
else if(func_free_entry_search64to2_entry_valid24 & func_free_entry_search64to2_entry_valid25)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd24;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd25;
end
else if(func_free_entry_search64to2_entry_valid26 & func_free_entry_search64to2_entry_valid27)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd26;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd27;
end
else if(func_free_entry_search64to2_entry_valid28 & func_free_entry_search64to2_entry_valid29)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd28;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd29;
end
else if(func_free_entry_search64to2_entry_valid30 & func_free_entry_search64to2_entry_valid31)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd30;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd31;
end
else if(func_free_entry_search64to2_entry_valid32 & func_free_entry_search64to2_entry_valid33)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd32;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd33;
end
else if(func_free_entry_search64to2_entry_valid34 & func_free_entry_search64to2_entry_valid35)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd34;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd35;
end
else if(func_free_entry_search64to2_entry_valid36 & func_free_entry_search64to2_entry_valid37)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd36;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd37;
end
else if(func_free_entry_search64to2_entry_valid38 & func_free_entry_search64to2_entry_valid39)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd38;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd39;
end
else if(func_free_entry_search64to2_entry_valid40 & func_free_entry_search64to2_entry_valid41)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd40;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd41;
end
else if(func_free_entry_search64to2_entry_valid42 & func_free_entry_search64to2_entry_valid43)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd42;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd43;
end
else if(func_free_entry_search64to2_entry_valid44 & func_free_entry_search64to2_entry_valid45)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd44;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd45;
end
else if(func_free_entry_search64to2_entry_valid46 & func_free_entry_search64to2_entry_valid47)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd46;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd47;
end
else if(func_free_entry_search64to2_entry_valid48 & func_free_entry_search64to2_entry_valid49)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd48;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd49;
end
else if(func_free_entry_search64to2_entry_valid50 & func_free_entry_search64to2_entry_valid51)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd50;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd51;
end
else if(func_free_entry_search64to2_entry_valid52 & func_free_entry_search64to2_entry_valid53)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd52;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd53;
end
else if(func_free_entry_search64to2_entry_valid54 & func_free_entry_search64to2_entry_valid55)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd54;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd55;
end
else if(func_free_entry_search64to2_entry_valid56 & func_free_entry_search64to2_entry_valid57)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd56;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd57;
end
else if(func_free_entry_search64to2_entry_valid58 & func_free_entry_search64to2_entry_valid59)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd58;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd59;
end
else if(func_free_entry_search64to2_entry_valid60 & func_free_entry_search64to2_entry_valid61)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd60;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd61;
end
else if(func_free_entry_search64to2_entry_valid62 & func_free_entry_search64to2_entry_valid63)begin
func_free_entry_search64to2[13] = 1'b1;
func_free_entry_search64to2[12:7] = 6'd62;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = 6'd63;
end
//1Set
else if(func_free_entry_search64to2_tournament_data0_valid0)begin
func_free_entry_search64to2[13] = 1'b0;
func_free_entry_search64to2[12:7] = 4'h0;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data0_num0;
end
else if(func_free_entry_search64to2_tournament_data0_valid1)begin
func_free_entry_search64to2[13] = 1'b0;
func_free_entry_search64to2[12:7] = 4'h0;
func_free_entry_search64to2[6] = 1'b1;
func_free_entry_search64to2[5:0] = func_free_entry_search64to2_tournament_data0_num1;
end
//No Empty
else begin
func_free_entry_search64to2[13] = 1'b0;
func_free_entry_search64to2[12:7] = 4'h0;
func_free_entry_search64to2[6] = 1'b0;
func_free_entry_search64to2[5:0] = 4'h0;
end
end
endfunction
endmodule
`default_nettype wire
|
// ECE 429
//FIXME: include output port busy
module memory(clock, address, data_in, access_size, rw, enable, busy, data_out);
parameter data_width = 32;
parameter address_width = 32;
parameter depth = 1048576;
// -1 for 0 based indexed
parameter bytes_in_word = 4-1;
parameter bits_in_bytes = 8-1;
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
input clock;
input [address_width-1:0] address;
input [data_width-1:0] data_in;
input [1:0] access_size;
input rw;
input enable;
// Output Ports
//FIXME: change to output port.
output reg busy;
output reg [data_width-1:0] data_out;
// Create a 1MB deep memory of 8-bits (1 byte) width
reg [7:0] mem[0:depth]; // should be [7:0] since its byte addressible memory
reg [7:0] data;
reg [7:0] byte[3:0];
reg [31:0] global_cur_addr;
reg [31:0] global_cur_addr_write;
reg [31:0] global_cur_addr_read;
integer cyc_ctr = 0;
integer cyc_ctr_write = 0;
integer i = 0;
integer words_written = 0;
integer words_read = 0;
integer write_total_words = 0;
integer read_total_words = 0;
integer fd;
integer status_read, status_write;
integer blah;
reg [31:0] fd_in;
reg [31:0] str;
always @(posedge clock, data_in, rw)
begin : WRITE
// rw = 1
if ((!rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(write_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
mem[address-start_addr+3] <= data_in[7:0];
mem[address-start_addr+2] <= data_in[15:8];
mem[address-start_addr+1] <= data_in[23:16];
mem[address-start_addr] <= data_in[31:24];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
write_total_words = 4;
// skip over the already written bytes
global_cur_addr_write = address-start_addr;
if (words_written < 4) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_written = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
write_total_words = 8;
global_cur_addr_write = address-start_addr;
if (words_written < 8) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
// 11: 16 words
else if (access_size == 2'b1_1) begin
write_total_words = 16;
global_cur_addr_write = address-start_addr;
if (words_written < 16) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
end
end
/*
00: 1 word (4-bytes)
01: 4 words (16-bytes)
10: 8 words (32-bytes)
11: 16 words (64-bytes)
*/
always @(posedge clock, address, rw)
begin : READ
if ((rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(read_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
// read 4 bytes at max in 1 clock cycle.
//assign data_out = {mem[address-start_addr], mem[address-start_addr+1], mem[address-start_addr+2], mem[address-start_addr+3]};
data_out[7:0] <= mem[address-start_addr+3];
data_out[15:8] <= mem[address-start_addr+2];
data_out[23:16] <= mem[address-start_addr+1];
data_out[31:24] <= mem[address-start_addr];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
read_total_words = 4;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 4) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
read_total_words = 8;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 8) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
// 11: 16 words
end else if (access_size == 2'b1_1) begin
read_total_words = 16;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 16) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:05:23 02/09/2017
// Design Name:
// Module Name: Display
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Display(
/* Inputs */
Value, clk,
/* Outputs */
seg, an
);
input clk; // 700 Hz
input [7:0] Value;
output reg [7:0] seg;
output reg [3:0] an;
wire [7:0] Minute0;
wire [7:0] Minute1;
wire [7:0] Second0;
wire [7:0] Second1;
reg [1:0] state;
reg [1:0] nextState;
wire [3:0] Digit1Input;
wire [3:0] Digit3Input;
wire [3:0] Digit4Input;
binary_to_BCD converter(
.A(Value),
.ONES(Digit3Input),
.TENS(Digit4Input),
.HUNDREDS(Digit1Input)
);
DisplayDigit min0 (
.clk(clk),
.Digit(Digit1Input),
.Display(Minute0)
);
DisplayDigit sec0 (
.clk(clk),
.Digit(Digit3Input),
.Display(Second0)
);
DisplayDigit sec1 (
.clk(clk),
.Digit(Digit4Input),
.Display(Second1)
);
always @(posedge clk) begin
case(state)
2'b00: begin
an = 4'b1110;
seg = Second0;
nextState = 2'b01;
end
2'b01: begin
an = 4'b1101;
seg = Second1;
nextState = 2'b10;
end
2'b10: begin
an = 4'b1011;
seg = Minute0;
nextState = 2'b11;
end
default: begin
an = 4'b0111;
seg = 8'b11111111;
nextState = 2'b00;
end
endcase
end
always @ (posedge clk) begin
state <= nextState;
end
endmodule
module DisplayDigit (
/* Input */
clk, Digit,
/* Output */
Display
);
input clk;//Clock,
input [3:0] Digit;
output reg [7:0] Display;
always @ (posedge clk) begin
case (Digit)
4'h0: Display = 8'b11000000;
4'h1: Display = 8'b11111001;
4'h2: Display = 8'b10100100;
4'h3: Display = 8'b10110000;
4'h4: Display = 8'b10011001;
4'h5: Display = 8'b10010010;
4'h6: Display = 8'b10000010;
4'h7: Display = 8'b11111000;
4'h8: Display = 8'b10000000;
4'h9: Display = 8'b10010000;
default: Display = 8'b11111111;
endcase
end
endmodule |
/**
* testbench.v
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p + 1;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic [width_p-1:0] a_r;
logic signed_r;
logic v_r;
logic [width_p-1:0] z_lo;
logic invalid_lo;
bsg_fpu_f2i #(
.e_p(8)
,.m_p(23)
) dut (
.a_i(a_r)
,.signed_i(signed_r)
,.z_o(z_lo)
,.invalid_o(invalid_lo)
);
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_r)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(tr_v_lo)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
assign {signed_li, a_li} = tr_data_lo;
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign tr_data_li = {
invalid_lo
,z_lo
};
logic [width_p-1:0] a_n;
logic signed_n;
logic v_n;
always_comb begin
if (v_r == 1'b0) begin
tr_yumi_li = tr_v_lo;
v_n = tr_v_lo;
signed_n = tr_v_lo
? tr_data_lo[width_p]
: signed_r;
a_n = tr_v_lo
? tr_data_lo[0+:width_p]
: a_r;
end
else begin
tr_yumi_li = 1'b0;
v_n = ~tr_ready_lo;
a_n = a_r;
end
end
always_ff @ (posedge clk) begin
if (reset) begin
a_r <= '0;
v_r <= 1'b0;
signed_r <= 1'b0;
end
else begin
a_r <= a_n;
v_r <= v_n;
signed_r <= signed_n;
end
end
initial begin
wait(done_lo);
$finish;
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
inclk0,
c0);
input inclk0;
output c0;
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
altpll altpll_component (
.inclk (sub_wire1),
.clk (sub_wire3),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 50,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=PLL",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module pfpu_above(
input sys_clk,
input alu_rst,
input [31:0] a,
input [31:0] b,
input valid_i,
output [31:0] r,
output reg valid_o
);
reg r_one;
always @(posedge sys_clk) begin
if(alu_rst)
valid_o <= 1'b0;
else
valid_o <= valid_i;
case({a[31], b[31]})
2'b00: r_one <= a[30:0] > b[30:0];
2'b01: r_one <= 1'b1;
2'b10: r_one <= 1'b0;
2'b11: r_one <= a[30:0] < b[30:0];
endcase
end
assign r = r_one ? 32'h3f800000: 32'h00000000;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 12
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64]" *)
output wire [95 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8]" *)
output wire [11 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64]" *)
output wire [95 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6]" *)
output wire [8 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2]" *)
output wire [2 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2]" *)
input wire [2 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64]" *)
input wire [95 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4]" *)
input wire [5 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2]" *)
input wire [2 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2]" *)
output wire [2 : 0] m_axi_rready;
axi_crossbar_v2_1_12_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(3),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(192'Hffffffffffffffff00000000412100000000000041200000),
.C_M_AXI_ADDR_WIDTH(96'H000000000000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(96'H000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(96'H000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(96'H000000010000000100000001),
.C_M_AXI_READ_ISSUING(96'H000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(96'H000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(3'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(3'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(3'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(3'H7),
.m_axi_ruser(3'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`include "../common_slice/Nlut/alut.sim.v"
`include "../common_slice/Nlut/blut.sim.v"
`include "../common_slice/Nlut/clut.sim.v"
`include "../common_slice/Nlut/dlut.sim.v"
`include "../common_slice/muxes/f7amux/f7amux.sim.v"
`include "../common_slice/muxes/f7bmux/f7bmux.sim.v"
`include "../common_slice/muxes/f8mux/f8mux.sim.v"
`include "../common_slice/routing/affmux/affmux.sim.v"
`include "../common_slice/routing/bffmux/bffmux.sim.v"
`include "../common_slice/routing/cffmux/cffmux.sim.v"
`include "../common_slice/routing/dffmux/dffmux.sim.v"
`include "../common_slice/routing/aoutmux/aoutmux.sim.v"
`include "../common_slice/routing/boutmux/boutmux.sim.v"
`include "../common_slice/routing/coutmux/coutmux.sim.v"
`include "../common_slice/routing/doutmux/doutmux.sim.v"
`include "../common_slice/routing/precyinit_mux/precyinit_mux.sim.v"
`include "../common_slice/routing/coutused/coutused.sim.v"
`include "../common_slice/routing/srusedmux/srusedmux.sim.v"
`include "../common_slice/routing/ceusedmux/ceusedmux.sim.v"
`include "../common_slice/routing/N5ffmux/a5ffmux.sim.v"
`include "../common_slice/routing/N5ffmux/b5ffmux.sim.v"
`include "../common_slice/routing/N5ffmux/c5ffmux.sim.v"
`include "../common_slice/routing/N5ffmux/d5ffmux.sim.v"
`include "../common_slice/routing/Ncy0/acy0.sim.v"
`include "../common_slice/routing/Ncy0/bcy0.sim.v"
`include "../common_slice/routing/Ncy0/ccy0.sim.v"
`include "../common_slice/routing/Ncy0/dcy0.sim.v"
`include "../common_slice/routing/Nused/aused.sim.v"
`include "../common_slice/routing/Nused/bused.sim.v"
`include "../common_slice/routing/Nused/cused.sim.v"
`include "../common_slice/routing/Nused/dused.sim.v"
`include "../common_slice/carry/carry4_vpr.sim.v"
`include "../common_slice/routing/clkinv/clkinv.sim.v"
module SLICEL(
DX, D1, D2, D3, D4, D5, D6, DMUX, D, DQ, // D port
CX, C1, C2, C3, C4, C5, C6, CMUX, C, CQ, // C port
BX, B1, B2, B3, B4, B5, B6, BMUX, B, BQ, // B port
AX, A1, A2, A3, A4, A5, A6, AMUX, A, AQ, // A port
SR, CE, CLK, // Flip flop signals
CIN, CYINIT, COUT, // Carry to/from adjacent slices
);
// D port
input wire DX;
input wire D1;
input wire D2;
input wire D3;
input wire D4;
input wire D5;
input wire D6;
output wire DMUX;
output wire D;
output wire DQ;
// D port flip-flop config
parameter D5FF_SRVAL = "SRLOW";
parameter D5FF_INIT = D5FF_SRVAL;
parameter DFF_SRVAL = "SRLOW";
parameter DFF_INIT = D5FF_SRVAL;
// C port
input wire CX;
input wire C1;
input wire C2;
input wire C3;
input wire C4;
input wire C5;
input wire C6;
output wire CMUX;
output wire C;
output wire CQ;
// B port
input wire BX;
input wire B1;
input wire B2;
input wire B3;
input wire B4;
input wire B5;
input wire B6;
output wire BMUX;
output wire B;
output wire BQ;
// A port
input wire AX;
input wire A1;
input wire A2;
input wire A3;
input wire A4;
input wire A5;
input wire A6;
output wire AMUX;
output wire A;
output wire AQ;
// Shared Flip flop signals
input wire CLK; // Clock
input wire SR; // Set/Reset
input wire CE; // Clock enable
// Reset type for all flip flops, can be;
// * None -- Ignore SR
// * Sync -- Reset occurs on clock edge
// * Async -- Reset occurs when ever
parameter SR_TYPE = "SYNC";
// The mode this unit operates in, can be;
// "FLIPFLOP" - Operate as a flip-flop (D->Q on clock low->high)
// "LATCH" - Operate as a latch (D->Q while CLK low)
parameter FF_MODE = "FLIPFLOP";
// Carry to/from adjacent slices
input wire CIN;
input wire CYINIT;
output wire COUT;
// Internal routing configuration
wire A5LUT_O5;
wire B5LUT_O5;
wire C5LUT_O5;
wire D5LUT_O5;
wire D6LUT_O6;
wire C6LUT_O6;
wire B6LUT_O6;
wire A6LUT_O6;
ALUT alut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .A5(A5), .A6(A6), .O6(A6LUT_O6), .O5(A5LUT_O5));
BLUT blut (.A1(B1), .A2(B2), .A3(B3), .A4(B4), .A5(B5), .A6(B6), .O6(B6LUT_O6), .O5(B5LUT_O5));
CLUT clut (.A1(C1), .A2(C2), .A3(C3), .A4(C4), .A5(C5), .A6(C6), .O6(C6LUT_O6), .O5(C5LUT_O5));
DLUT dlut (.A1(D1), .A2(D2), .A3(D3), .A4(D4), .A5(D5), .A6(D6), .O6(D6LUT_O6), .O5(D5LUT_O5));
wire F7AMUX_OUT;
wire F8MUX_OUT;
wire A5FFMUX_OUT;
wire B5FFMUX_OUT;
wire C5FFMUX_OUT;
wire D5FFMUX_OUT;
A5FFMUX a5ffmux (.IN_B(AX), .IN_A(A5LUT_O5), .O(A5FFMUX_OUT));
B5FFMUX b5ffmux (.IN_B(BX), .IN_A(B5LUT_O5), .O(B5FFMUX_OUT));
C5FFMUX c5ffmux (.IN_B(CX), .IN_A(C5LUT_O5), .O(C5FFMUX_OUT));
D5FFMUX d5ffmux (.IN_B(DX), .IN_A(D5LUT_O5), .O(D5FFMUX_OUT));
wire ACY0_OUT;
wire BCY0_OUT;
wire CCY0_OUT;
wire DCY0_OUT;
ACY0 acy0 (.O5(A5LUT_O5), .AX(AX), .O(ACY0_OUT));
BCY0 bcy0 (.O5(B5LUT_O5), .BX(BX), .O(BCY0_OUT));
CCY0 ccy0 (.O5(C5LUT_O5), .CX(CX), .O(CCY0_OUT));
DCY0 dcy0 (.O5(D5LUT_O5), .DX(DX), .O(DCY0_OUT));
wire F7BMUX_OUT;
F7BMUX f7bmux (.I0(D6LUT_O6), .I1(C6LUT_O6), .OUT(F7BMUX_OUT), .S0(CX));
wire F7AMUX_OUT;
F7BMUX f7amux (.I0(B6LUT_O6), .I1(A6LUT_O6), .OUT(F7AMUX_OUT), .S0(AX));
wire F8MUX_OUT;
F8MUX f8mux (.I0(F7BMUX_OUT), .I1(F7AMUX_OUT), .OUT(F8MUX_OUT), .S0(BX));
wire PRECYINIT_OUT;
PRECYINIT_MUX precyinit_mux (.C0(0), .C1(1), .CI(CIN), .CYINIT(CYINIT), .OUT(PRECYINIT_OUT));
wire [3:0] CARRY4_CO;
wire [3:0] CARRY4_O;
CARRY4_MODES carry4 (
.CO(CARRY4_CO),
.O(CARRY4_O),
.DI({ACY0_OUT, BCY0_OUT, CCY0_OUT, DCY0_OUT}),
.S({A6LUT_O6, B6LUT_O6, C6LUT_O6, D6LUT_O6}),
.CIN(PRECYINIT_OUT));
COUTUSED coutused (.IN(CARRY4_O[3]), .OUT(COUT));
wire A5FF_Q;
wire B5FF_Q;
wire C5FF_Q;
wire D5FF_Q;
AOUTMUX aoutmux (
.A5Q(A5FF_Q), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT),
.OUT(AMUX));
BOUTMUX boutmux (
.B5Q(B5FF_Q), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT),
.OUT(BMUX));
COUTMUX coutmux (
.C5Q(C5FF_Q), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT),
.OUT(CMUX));
DOUTMUX doutmux (
.D5Q(D5FF_Q), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]),
.OUT(DMUX));
wire AFFMUX_OUT;
wire BFFMUX_OUT;
wire CFFMUX_OUT;
wire DFFMUX_OUT;
AFFMUX affmux (
.AX(AX), .XOR(CARRY4_O[0]), .O6(A6LUT_O6), .O5(A5LUT_O5), .CY(CARRY4_CO[0]), .F7(F7AMUX_OUT),
.OUT(AFFMUX_OUT));
BFFMUX bffmux (
.BX(BX), .XOR(CARRY4_O[1]), .O6(B6LUT_O6), .O5(B5LUT_O5), .CY(CARRY4_CO[1]), .F8(F8MUX_OUT),
.OUT(BFFMUX_OUT));
CFFMUX cffmux (
.CX(CX), .XOR(CARRY4_O[2]), .O6(C6LUT_O6), .O5(C5LUT_O5), .CY(CARRY4_CO[2]), .F7(F7BMUX_OUT),
.OUT(CFFMUX_OUT));
DFFMUX dffmux (
.DX(DX), .XOR(CARRY4_O[3]), .O6(D6LUT_O6), .O5(D5LUT_O5), .CY(CARRY4_CO[3]),
.OUT(DFFMUX_OUT));
wire CEUSEDMUX_OUT;
wire SRUSEDMUX_OUT;
wire CLKINV_OUT;
CLKINV clkinv (.CLK(CLK), .OUT(CLKINV_OUT));
A5FF a5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(A5FFMUX_OUT), .Q(A5FF_Q));
B5FF b5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(B5FFMUX_OUT), .Q(B5FF_Q));
C5FF c5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(C5FFMUX_OUT), .Q(C5FF_Q));
D5FF d5ff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(D5FFMUX_OUT), .Q(D5FF_Q));
A5FF aff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(AFFMUX_OUT), .Q(AQ));
B5FF bff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(BFFMUX_OUT), .Q(BQ));
C5FF cff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(CFFMUX_OUT), .Q(CQ));
D5FF dff (.CE(CEUSEDMUX_OUT), .CK(CLKINV_OUT), .SR(SRUSEDMUX_OUT), .D(DFFMUX_OUT), .Q(DQ));
AUSED aused (.I0(A6LUT_O6), .O(A));
BUSED bused (.I0(B6LUT_O6), .O(B));
CUSED cused (.I0(C6LUT_O6), .O(C));
DUSED dused (.I0(D6LUT_O6), .O(D));
CEUSEDMUX ceusedmux (.IN(CE), .OUT(CEUSEDMUX_OUT));
SRUSEDMUX srusedmux (.IN(SR), .OUT(SRUSEDMUX_OUT));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222O_2_V
`define SKY130_FD_SC_MS__A222O_2_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog wrapper for a222o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a222o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a222o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a222o_2 (
X ,
A1,
A2,
B1,
B2,
C1,
C2
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a222o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.C2(C2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222O_2_V
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CPU LOW POWER MODES & DMA TRANSFER */
/*---------------------------------------------------------------------------*/
/* Test DMA transfer with the CPU Low Power modes: */
/* */
/* - LPM0 <=> CPUOFF */
/* - LPM1 <=> CPUOFF + SCG0 */
/* - LPM2 <=> CPUOFF + SCG1 */
/* - LPM3 <=> CPUOFF + SCG0 + SCG1 */
/* - LPM4 <=> CPUOFF + SCG0 + SCG1 + OSCOFF */
/* */
/* */
/* Reminder about config registers: */
/* */
/* - CPUOFF <=> turns off CPU. */
/* - SCG0 <=> turns off DCO. */
/* - SCG1 <=> turns off SMCLK. */
/* - OSCOFF <=> turns off LFXT_CLK. */
/* */
/* - DMA_CPUOFF <=> allow DMA to turn on MCLK */
/* - DMA_SCG0 <=> allow DMA to turn on DCO */
/* - DMA_SCG1 <=> allow DMA to turn on SMCLK */
/* - DMA_OSCOFF <=> allow DMA to turn on LFXT_CLK */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
`define VERY_LONG_TIMEOUT
reg dma_loop_enable;
integer dma_loop_nr;
integer cfg_idx;
integer dco_clk_cnt;
always @(negedge dco_clk)
dco_clk_cnt <= dco_clk_cnt+1;
integer mclk_dma_cnt;
always @(negedge mclk)
mclk_dma_cnt <= mclk_dma_cnt+1;
integer mclk_cpu_cnt;
always @(negedge tb_openMSP430.dut.cpu_mclk)
mclk_cpu_cnt <= mclk_cpu_cnt+1;
integer smclk_cnt;
always @(negedge smclk)
smclk_cnt <= smclk_cnt+1;
integer aclk_cnt;
always @(negedge aclk)
aclk_cnt <= aclk_cnt+1;
integer inst_cnt;
always @(inst_number)
inst_cnt <= inst_cnt+1;
// Wakeup synchronizer to generate IRQ
reg [1:0] wkup2_sync;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) wkup2_sync <= 2'b00;
else wkup2_sync <= {wkup2_sync[0], wkup[2]};
always @(wkup2_sync)
irq[`IRQ_NR-14] = wkup2_sync[1]; // IRQ-2
// Wakeup synchronizer to generate IRQ
reg [1:0] wkup3_sync;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) wkup3_sync <= 2'b00;
else wkup3_sync <= {wkup3_sync[0], wkup[3]};
always @(wkup3_sync)
irq[`IRQ_NR-13] = wkup3_sync[1]; // IRQ-3
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DMA_IF_EN
// Disable automatic DMA verification
#10;
dma_verif_on = 0;
repeat(5) @(posedge mclk);
stimulus_done = 0;
irq[`IRQ_NR-14] = 0; // IRQ-2
wkup[2] = 0;
irq[`IRQ_NR-13] = 0; // IRQ-3
wkup[3] = 0;
`ifdef ASIC_CLOCKING
`ifdef CPUOFF_EN
//--------------------------------------------------------
// ACTIVE
//--------------------------------------------------------
@(r15==16'h1001);
$display("");
$display("\nACTIVE - NO DMA");
// DCO_CLK, MCLK_CPU, MCLK_DMA, SMCLK, ACLK1, ACLK2, INST, DMA_NR
clock_check( 100 , 100 , 100 , 100 , 4 , 100 , 60 , 0 );
// Check clocks for each possible DMA wakeup configuration
for ( cfg_idx=0; cfg_idx < 16; cfg_idx=cfg_idx+1)
begin
@(r15==(16'h3000 + cfg_idx));
$display("\nLPM2 (CPUOFF+SCG1) - {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF}={%d, %d, %d, %d}\n", cfg_idx[3], cfg_idx[2], cfg_idx[1], cfg_idx[0]);
// {SCG1 , SCG0 , OSCOFF }
full_lpm_clock_check ( lpm_clocks_status ({1'b1 , 1'b0 , 1'b0 }), // Get running clocks in low power mode
// {SCG1 , SCG0 , OSCOFF } { DMA_SCG1 , DMA_SCG0 , DMA_OSCOFF, DMA_CPUOFF }
lmp_clocks_status_dma_wkup({1'b1 , 1'b0 , 1'b0 }, {cfg_idx[3],cfg_idx[2], cfg_idx[1], cfg_idx[0] })); // Get running clocks in low power mode with DMA wake-up
end
$display("");
`else
tb_skip_finish("| (CPUOFF low power mode should be enabled) |");
`endif
`else
tb_skip_finish("| (this test is not supported in FPGA mode) |");
`endif
`else
tb_skip_finish("| (DMA interface support not included) |");
`endif
stimulus_done = 1;
end
//------------------------------------------------------
// Clock check function
//------------------------------------------------------
task clock_check;
input integer dco_val;
input integer mclk_cpu_val;
input integer mclk_dma_val;
input integer smclk_val;
input integer aclk_val1;
input integer aclk_val2;
input integer inst_val;
input integer dma_val;
begin
`ifdef LFXT_DOMAIN
if (aclk_val1 != 0) @(posedge aclk);
`endif
tb_idx = 777;
#(100*50);
dco_clk_cnt = 0;
mclk_cpu_cnt = 0;
mclk_dma_cnt = 0;
smclk_cnt = 0;
tb_idx = 888;
aclk_cnt = 0;
inst_cnt = 0;
dma_loop_nr = 0;
#(100*50);
if (dco_clk_cnt !== dco_val) tb_error("====== DCO_CLK CHECK FAILED =====");
if (mclk_cpu_cnt !== mclk_cpu_val) tb_error("====== MCLK CPU CHECK FAILED =====");
if (mclk_dma_cnt !== mclk_dma_val) tb_error("====== MCLK DMA CHECK FAILED =====");
if (smclk_cnt !== smclk_val) tb_error("====== SMCLK CHECK FAILED =====");
`ifdef LFXT_DOMAIN
if (aclk_cnt !== aclk_val1) tb_error("====== ACLK1 CHECK FAILED =====");
`else
if (aclk_cnt !== aclk_val2) tb_error("====== ACLK2 CHECK FAILED =====");
`endif
if (inst_cnt < inst_val) tb_error("====== INST_NR CHECK FAILED =====");
if (dma_loop_nr !== dma_val) tb_error("====== DMA_NR CHECK FAILED =====");
dco_clk_cnt = 0;
mclk_cpu_cnt = 0;
mclk_dma_cnt = 0;
smclk_cnt = 0;
aclk_cnt = 0;
inst_cnt = 0;
dma_loop_nr = 0;
end
endtask
//------------------------------------------------------
// Check Clocks for the whole LPM sequence
//------------------------------------------------------
task full_lpm_clock_check;
input [2:0] lpm_clock_status; // { SMCLK , DCO_CLK , ACLK }
input [3:0] lpm_clock_status_dma_wkup; // { SMCLK , DCO_CLK , ACLK , MCLK_DMA }
integer lpm_dco , lpm_mclk_cpu , lpm_mclk_dma , lpm_smclk , lpm_aclk1 , lpm_aclk2 , lpm_inst , lpm_dma_nr ;
integer dma_nowkup_dco, dma_nowkup_mclk_cpu, dma_nowkup_mclk_dma, dma_nowkup_smclk, dma_nowkup_aclk1, dma_nowkup_aclk2, dma_nowkup_inst, dma_nowkup_dma_nr;
integer dma_wkup_dco , dma_wkup_mclk_cpu , dma_wkup_mclk_dma , dma_wkup_smclk , dma_wkup_aclk1 , dma_wkup_aclk2 , dma_wkup_inst , dma_wkup_dma_nr ;
begin
// Initialize target values
lpm_dco =0; lpm_mclk_cpu =0; lpm_mclk_dma =0; lpm_smclk =0; lpm_aclk1 =0; lpm_aclk2 =0; lpm_inst =0; lpm_dma_nr =0;
dma_nowkup_dco=0; dma_nowkup_mclk_cpu=0; dma_nowkup_mclk_dma=0; dma_nowkup_smclk=0; dma_nowkup_aclk1=0; dma_nowkup_aclk2=0; dma_nowkup_inst=0; dma_nowkup_dma_nr=0;
dma_wkup_dco =0; dma_wkup_mclk_cpu =0; dma_wkup_mclk_dma =0; dma_wkup_smclk =0; dma_wkup_aclk1 =0; dma_wkup_aclk2 =0; dma_wkup_inst =0; dma_wkup_dma_nr =0;
// Update depending on running clocks during the low-power mode (no DMA)
if (lpm_clock_status[0]) begin lpm_aclk1 = 4; lpm_aclk2 = 100; end
if (lpm_clock_status[1]) begin lpm_dco = 100; lpm_mclk_cpu = 0; end
if (lpm_clock_status[2]) begin lpm_smclk = 100; end
// Update depending on running clocks during the low-power mode (with DMA, with wakeup)
if (lpm_clock_status_dma_wkup[0]) begin dma_wkup_mclk_dma = 100; end else begin dma_wkup_mclk_dma = lpm_mclk_dma; end
if (lpm_clock_status_dma_wkup[1]) begin dma_wkup_aclk1 = 4; dma_wkup_aclk2 = 100; end else begin dma_wkup_aclk1 = lpm_aclk1 ; dma_wkup_aclk2 = lpm_aclk2 ; end
if (lpm_clock_status_dma_wkup[2]) begin dma_wkup_dco = 100; dma_wkup_mclk_cpu = 0; end else begin dma_wkup_dco = lpm_dco ; dma_wkup_mclk_cpu = lpm_mclk_cpu; end
if (lpm_clock_status_dma_wkup[3]) begin dma_wkup_smclk = 100; end else begin dma_wkup_smclk = lpm_smclk ; end
if (dma_wkup_smclk == 100) begin dma_wkup_dma_nr = dma_wkup_mclk_dma; end
// Update depending on running clocks during the low-power mode (with DMA, no wakeup)
if ((lpm_smclk == 100) &
lpm_clock_status_dma_wkup[0]) begin dma_nowkup_mclk_dma = 100; end
if (lpm_smclk == 100) begin dma_nowkup_dma_nr = dma_nowkup_mclk_dma; end
if (lpm_smclk == 100) begin dma_nowkup_aclk1 = dma_wkup_aclk1; dma_nowkup_aclk2 = dma_wkup_aclk2; end
else begin dma_nowkup_aclk1 = lpm_aclk1; dma_nowkup_aclk2 = lpm_aclk2; end
//---------- NO DMA - CHECK CLOCK STATUS -------------//
$display(" - NO DMA");
clock_check(lpm_dco, lpm_mclk_cpu, lpm_mclk_dma, lpm_smclk, lpm_aclk1, lpm_aclk2, lpm_inst, lpm_dma_nr );
//---------- PERFORM DMA TRANSFER NO WAKEUP - CHECK CLOCK STATUS -------------//
$display(" - WITH DMA, NO WAKE-UP");
dma_wkup = 0;
dma_loop_enable = 1;
tb_idx = 666;
clock_check(lpm_dco, lpm_mclk_cpu, dma_nowkup_mclk_dma, lpm_smclk, dma_nowkup_aclk1, dma_nowkup_aclk2, lpm_inst, dma_nowkup_dma_nr );
tb_idx = 999;
dma_loop_enable = 0;
dma_wkup = 0;
#100;
dma_tfx_cancel = 1;
#100;
dma_tfx_cancel = 0;
#100;
//---------- NO DMA - CHECK CLOCK STATUS -------------//
$display(" - NO DMA");
clock_check(lpm_dco, lpm_mclk_cpu, lpm_mclk_dma, lpm_smclk, lpm_aclk1, lpm_aclk2, lpm_inst, lpm_dma_nr );
//---------- PERFORM DMA TRANSFER WITH WAKEUP - CHECK CLOCK STATUS -------------//
$display(" - WITH DMA, WITH WAKE-UP");
dma_wkup = 1;
dma_loop_enable = 1;
clock_check(dma_wkup_dco, dma_wkup_mclk_cpu, dma_wkup_mclk_dma, dma_wkup_smclk, dma_wkup_aclk1, dma_wkup_aclk2, dma_wkup_inst, dma_wkup_dma_nr );
dma_loop_enable = 0;
dma_wkup = 0;
#100;
dma_tfx_cancel = 1;
#100;
dma_tfx_cancel = 0;
#100;
//---------- NO DMA - CHECK CLOCK STATUS -------------//
$display(" - NO DMA");
clock_check(lpm_dco, lpm_mclk_cpu, lpm_mclk_dma, lpm_smclk, lpm_aclk1, lpm_aclk2, lpm_inst, lpm_dma_nr );
//---------- PORT2 IRQ - EXITING POWER MODE -------------//
irq_exit_lp_mode;
end
endtask
//------------------------------------------------------
// ENABLE DISABLE DMA TRANSFERS
//------------------------------------------------------
// Note that we synchronize DMA transfer with SMCLK
reg [15:0] dma_loop_val;
reg dma_loop_enable_old;
initial
begin
dma_loop_enable=0;
dma_loop_val=0;
dma_loop_nr=0;
forever
begin
dma_loop_enable_old=dma_loop_enable;
if (~dma_loop_enable) @(posedge dma_loop_enable);
if (dma_loop_enable_old==0) @(posedge smclk or posedge dma_tfx_cancel);
if (~dma_tfx_cancel) dma_write_16b(16'h0000-`PMEM_SIZE, dma_loop_val, 1'b0);
if (~dma_tfx_cancel) dma_loop_nr=dma_loop_nr+1;
if (~dma_tfx_cancel)
begin
dma_loop_enable_old=dma_loop_enable;
if (~dma_loop_enable) @(posedge dma_loop_enable);
if (dma_loop_enable_old==0) @(posedge smclk or posedge dma_tfx_cancel);
if (~dma_tfx_cancel) dma_read_16b(16'h0000-`PMEM_SIZE, dma_loop_val, 1'b0);
if (~dma_tfx_cancel) dma_loop_nr=dma_loop_nr+1;
end
dma_loop_val=dma_loop_val+1;
end
end
//------------------------------------------------------
// IRQ to exit Low Power Mode
//------------------------------------------------------
task irq_exit_lp_mode;
begin
wkup[3] = 1'b1;
@(posedge irq_acc[`IRQ_NR-13]); // IRQ_ACC-3
#(10*50);
@(r13==16'hbbbb);
wkup[3] = 1'b0;
end
endtask
//----------------------------------------------------------------------------------//
// DETECT CLOCKS RESTORED WITH DMA WAKEUP //
//----------------------------------------------------------------------------------//
function [3:0] lmp_clocks_status_dma_wkup;
input [3:0] lpm_config; // { SCG1 , SCG0 , OSCOFF }
input [3:0] dma_lpm_config; // {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF }
reg [3:0] combined_lpm_config; // {DMA_SCG1, DMA_SCG0, DMA_OSCOFF, DMA_CPUOFF }
reg [2:0] lpm_rtl_support; // { SCG1 , SCG0 , OSCOFF }
begin
// Combine low power configuration with the DMA wakeup one
assign combined_lpm_config = dma_lpm_config | {~lpm_config, 1'b0};
// Get supported RTL configuration
lpm_rtl_support = 3'h0;
`ifdef OSCOFF_EN
lpm_rtl_support = lpm_rtl_support | 3'h1;
`endif
`ifdef SCG0_EN
lpm_rtl_support = lpm_rtl_support | 3'h2;
`endif
`ifdef SCG1_EN
lpm_rtl_support = lpm_rtl_support | 3'h4;
`endif
// Depending on RTL configuration, figure out which clocks are running when a DMA wakeup is applied
case(lpm_rtl_support)
// SMCLK , DCO_CLK , ACLK , MCLK_DMA
4'b000 : lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , 1'b1 , combined_lpm_config[0] };
4'b001 : lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , combined_lpm_config[1] , combined_lpm_config[0] };
4'b010 : begin
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , combined_lpm_config[2] , 1'b1 , combined_lpm_config[0] };
lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
end
4'b011 : begin
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , combined_lpm_config[2] , combined_lpm_config[1] , combined_lpm_config[0] };
lmp_clocks_status_dma_wkup = { 1'b1 , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
end
4'b100 : lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , 1'b1 , 1'b1 , combined_lpm_config[0] };
4'b101 : lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , 1'b1 , combined_lpm_config[1] , combined_lpm_config[0] };
4'b110 : begin
lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , combined_lpm_config[2] , 1'b1 , combined_lpm_config[0] };
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
end
4'b111 : begin
lmp_clocks_status_dma_wkup = { combined_lpm_config[3] , combined_lpm_config[2] , combined_lpm_config[1] , combined_lpm_config[0] };
lmp_clocks_status_dma_wkup = { combined_lpm_config[2] , 1'b1 , 1'b1 , combined_lpm_config[2] } & lmp_clocks_status_dma_wkup;
end
endcase
// If Low-Frequency oscillator is not supported, ACLK is then clocked by DCO
`ifdef LFXT_DOMAIN
`else
lmp_clocks_status_dma_wkup[1] = lmp_clocks_status_dma_wkup[2];
`endif
end
endfunction
//----------------------------------------------------------------------------------//
// DETECT CLOCKS RUNNING DURING LOW-POWER-MODE //
//----------------------------------------------------------------------------------//
function [2:0] lpm_clocks_status;
input [2:0] lpm_config; // { SCG1 , SCG0 , OSCOFF }
reg [2:0] lpm_rtl_support; // { SCG1 , SCG0 , OSCOFF }
begin
// Get supported RTL configuration
lpm_rtl_support = 3'h0;
`ifdef OSCOFF_EN
lpm_rtl_support = lpm_rtl_support | 3'h1;
`endif
`ifdef SCG0_EN
lpm_rtl_support = lpm_rtl_support | 3'h2;
`endif
`ifdef SCG1_EN
lpm_rtl_support = lpm_rtl_support | 3'h4;
`endif
// Depending on RTL configuration, figure out which clocks are running with a given Low-Power-Mode
case(lpm_rtl_support)
// SMCLK , DCO_CLK , ACLK
4'b000 : lpm_clocks_status = { 1'b1 , 1'b1 , 1'b1 };
4'b001 : lpm_clocks_status = { 1'b1 , 1'b1 , ~lpm_config[0] };
4'b010 : lpm_clocks_status = { ~lpm_config[1] , ~lpm_config[1] , 1'b1 };
4'b011 : lpm_clocks_status = { ~lpm_config[1] , ~lpm_config[1] , ~lpm_config[0] };
4'b100 : lpm_clocks_status = { ~lpm_config[2] , 1'b1 , 1'b1 };
4'b101 : lpm_clocks_status = { ~lpm_config[2] , 1'b1 , ~lpm_config[0] };
4'b110 : begin
lpm_clocks_status = { ~lpm_config[2] , ~lpm_config[1] , 1'b1 };
lpm_clocks_status = { ~lpm_config[1] , 1'b1 , 1'b1 } & lpm_clocks_status;
end
4'b111 : begin
lpm_clocks_status = { ~lpm_config[2] , ~lpm_config[1] , ~lpm_config[0] };
lpm_clocks_status = { ~lpm_config[1] , 1'b1 , 1'b1 } & lpm_clocks_status;
end
endcase
// If Low-Frequency oscillator is not supported, ACLK is then clocked by DCO
`ifdef LFXT_DOMAIN
`else
lpm_clocks_status[0] = lpm_clocks_status[1];
`endif
end
endfunction
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDFXTP_1_V
`define SKY130_FD_SC_HVL__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDFXTP_1_V
|
// system_acl_iface_acl_kernel_interface_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.26.20:40:09
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface_mm_interconnect_1 (
input wire clk_reset_clk_clk, // clk_reset_clk.clk
input wire kernel_clk_out_clk_clk, // kernel_clk_out_clk.clk
input wire address_span_extender_0_reset_reset_bridge_in_reset_reset, // address_span_extender_0_reset_reset_bridge_in_reset.reset
input wire kernel_cntrl_reset_reset_bridge_in_reset_reset, // kernel_cntrl_reset_reset_bridge_in_reset.reset
input wire sw_reset_clk_reset_reset_bridge_in_reset_reset, // sw_reset_clk_reset_reset_bridge_in_reset.reset
input wire [13:0] kernel_cntrl_m0_address, // kernel_cntrl_m0.address
output wire kernel_cntrl_m0_waitrequest, // .waitrequest
input wire [0:0] kernel_cntrl_m0_burstcount, // .burstcount
input wire [3:0] kernel_cntrl_m0_byteenable, // .byteenable
input wire kernel_cntrl_m0_read, // .read
output wire [31:0] kernel_cntrl_m0_readdata, // .readdata
output wire kernel_cntrl_m0_readdatavalid, // .readdatavalid
input wire kernel_cntrl_m0_write, // .write
input wire [31:0] kernel_cntrl_m0_writedata, // .writedata
input wire kernel_cntrl_m0_debugaccess, // .debugaccess
output wire address_span_extender_0_cntl_write, // address_span_extender_0_cntl.write
output wire address_span_extender_0_cntl_read, // .read
input wire [63:0] address_span_extender_0_cntl_readdata, // .readdata
output wire [63:0] address_span_extender_0_cntl_writedata, // .writedata
output wire [7:0] address_span_extender_0_cntl_byteenable, // .byteenable
output wire [9:0] address_span_extender_0_windowed_slave_address, // address_span_extender_0_windowed_slave.address
output wire address_span_extender_0_windowed_slave_write, // .write
output wire address_span_extender_0_windowed_slave_read, // .read
input wire [31:0] address_span_extender_0_windowed_slave_readdata, // .readdata
output wire [31:0] address_span_extender_0_windowed_slave_writedata, // .writedata
output wire [0:0] address_span_extender_0_windowed_slave_burstcount, // .burstcount
output wire [3:0] address_span_extender_0_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_0_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_0_windowed_slave_waitrequest, // .waitrequest
output wire irq_ena_0_s_write, // irq_ena_0_s.write
output wire irq_ena_0_s_read, // .read
input wire [31:0] irq_ena_0_s_readdata, // .readdata
output wire [31:0] irq_ena_0_s_writedata, // .writedata
output wire [3:0] irq_ena_0_s_byteenable, // .byteenable
input wire irq_ena_0_s_waitrequest, // .waitrequest
output wire mem_org_mode_s_write, // mem_org_mode_s.write
output wire mem_org_mode_s_read, // .read
input wire [31:0] mem_org_mode_s_readdata, // .readdata
output wire [31:0] mem_org_mode_s_writedata, // .writedata
input wire mem_org_mode_s_waitrequest, // .waitrequest
output wire sw_reset_s_write, // sw_reset_s.write
output wire sw_reset_s_read, // .read
input wire [63:0] sw_reset_s_readdata, // .readdata
output wire [63:0] sw_reset_s_writedata, // .writedata
output wire [7:0] sw_reset_s_byteenable, // .byteenable
input wire sw_reset_s_waitrequest, // .waitrequest
output wire [8:0] sys_description_rom_s1_address, // sys_description_rom_s1.address
output wire sys_description_rom_s1_write, // .write
input wire [63:0] sys_description_rom_s1_readdata, // .readdata
output wire [63:0] sys_description_rom_s1_writedata, // .writedata
output wire [7:0] sys_description_rom_s1_byteenable, // .byteenable
output wire sys_description_rom_s1_chipselect, // .chipselect
output wire sys_description_rom_s1_clken, // .clken
output wire sys_description_rom_s1_debugaccess, // .debugaccess
output wire version_id_0_s_read, // version_id_0_s.read
input wire [31:0] version_id_0_s_readdata // .readdata
);
wire kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest; // kernel_cntrl_m0_agent:av_waitrequest -> kernel_cntrl_m0_translator:uav_waitrequest
wire [2:0] kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount; // kernel_cntrl_m0_translator:uav_burstcount -> kernel_cntrl_m0_agent:av_burstcount
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_writedata; // kernel_cntrl_m0_translator:uav_writedata -> kernel_cntrl_m0_agent:av_writedata
wire [13:0] kernel_cntrl_m0_translator_avalon_universal_master_0_address; // kernel_cntrl_m0_translator:uav_address -> kernel_cntrl_m0_agent:av_address
wire kernel_cntrl_m0_translator_avalon_universal_master_0_lock; // kernel_cntrl_m0_translator:uav_lock -> kernel_cntrl_m0_agent:av_lock
wire kernel_cntrl_m0_translator_avalon_universal_master_0_write; // kernel_cntrl_m0_translator:uav_write -> kernel_cntrl_m0_agent:av_write
wire kernel_cntrl_m0_translator_avalon_universal_master_0_read; // kernel_cntrl_m0_translator:uav_read -> kernel_cntrl_m0_agent:av_read
wire [31:0] kernel_cntrl_m0_translator_avalon_universal_master_0_readdata; // kernel_cntrl_m0_agent:av_readdata -> kernel_cntrl_m0_translator:uav_readdata
wire kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess; // kernel_cntrl_m0_translator:uav_debugaccess -> kernel_cntrl_m0_agent:av_debugaccess
wire [3:0] kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable; // kernel_cntrl_m0_translator:uav_byteenable -> kernel_cntrl_m0_agent:av_byteenable
wire kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid; // kernel_cntrl_m0_agent:av_readdatavalid -> kernel_cntrl_m0_translator:uav_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_waitrequest; // address_span_extender_0_windowed_slave_translator:uav_waitrequest -> address_span_extender_0_windowed_slave_agent:m0_waitrequest
wire [2:0] address_span_extender_0_windowed_slave_agent_m0_burstcount; // address_span_extender_0_windowed_slave_agent:m0_burstcount -> address_span_extender_0_windowed_slave_translator:uav_burstcount
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_writedata; // address_span_extender_0_windowed_slave_agent:m0_writedata -> address_span_extender_0_windowed_slave_translator:uav_writedata
wire [13:0] address_span_extender_0_windowed_slave_agent_m0_address; // address_span_extender_0_windowed_slave_agent:m0_address -> address_span_extender_0_windowed_slave_translator:uav_address
wire address_span_extender_0_windowed_slave_agent_m0_write; // address_span_extender_0_windowed_slave_agent:m0_write -> address_span_extender_0_windowed_slave_translator:uav_write
wire address_span_extender_0_windowed_slave_agent_m0_lock; // address_span_extender_0_windowed_slave_agent:m0_lock -> address_span_extender_0_windowed_slave_translator:uav_lock
wire address_span_extender_0_windowed_slave_agent_m0_read; // address_span_extender_0_windowed_slave_agent:m0_read -> address_span_extender_0_windowed_slave_translator:uav_read
wire [31:0] address_span_extender_0_windowed_slave_agent_m0_readdata; // address_span_extender_0_windowed_slave_translator:uav_readdata -> address_span_extender_0_windowed_slave_agent:m0_readdata
wire address_span_extender_0_windowed_slave_agent_m0_readdatavalid; // address_span_extender_0_windowed_slave_translator:uav_readdatavalid -> address_span_extender_0_windowed_slave_agent:m0_readdatavalid
wire address_span_extender_0_windowed_slave_agent_m0_debugaccess; // address_span_extender_0_windowed_slave_agent:m0_debugaccess -> address_span_extender_0_windowed_slave_translator:uav_debugaccess
wire [3:0] address_span_extender_0_windowed_slave_agent_m0_byteenable; // address_span_extender_0_windowed_slave_agent:m0_byteenable -> address_span_extender_0_windowed_slave_translator:uav_byteenable
wire address_span_extender_0_windowed_slave_agent_rf_source_endofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_endofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_windowed_slave_agent_rf_source_valid; // address_span_extender_0_windowed_slave_agent:rf_source_valid -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_valid
wire address_span_extender_0_windowed_slave_agent_rf_source_startofpacket; // address_span_extender_0_windowed_slave_agent:rf_source_startofpacket -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rf_source_data; // address_span_extender_0_windowed_slave_agent:rf_source_data -> address_span_extender_0_windowed_slave_agent_rsp_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rf_source_ready; // address_span_extender_0_windowed_slave_agent_rsp_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rf_source_ready
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rf_sink_valid
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_windowed_slave_agent:rf_sink_startofpacket
wire [89:0] address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rsp_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rf_sink_data
wire address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rf_sink_ready -> address_span_extender_0_windowed_slave_agent_rsp_fifo:out_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_valid -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data; // address_span_extender_0_windowed_slave_agent:rdata_fifo_src_data -> address_span_extender_0_windowed_slave_agent_rdata_fifo:in_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready; // address_span_extender_0_windowed_slave_agent_rdata_fifo:in_ready -> address_span_extender_0_windowed_slave_agent:rdata_fifo_src_ready
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_valid -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_valid
wire [33:0] address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data; // address_span_extender_0_windowed_slave_agent_rdata_fifo:out_data -> address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_data
wire address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready; // address_span_extender_0_windowed_slave_agent:rdata_fifo_sink_ready -> address_span_extender_0_windowed_slave_agent_rdata_fifo:out_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> address_span_extender_0_windowed_slave_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> address_span_extender_0_windowed_slave_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> address_span_extender_0_windowed_slave_agent:cp_startofpacket
wire [88:0] cmd_mux_src_data; // cmd_mux:src_data -> address_span_extender_0_windowed_slave_agent:cp_data
wire [6:0] cmd_mux_src_channel; // cmd_mux:src_channel -> address_span_extender_0_windowed_slave_agent:cp_channel
wire cmd_mux_src_ready; // address_span_extender_0_windowed_slave_agent:cp_ready -> cmd_mux:src_ready
wire address_span_extender_0_cntl_agent_m0_waitrequest; // address_span_extender_0_cntl_translator:uav_waitrequest -> address_span_extender_0_cntl_agent:m0_waitrequest
wire [3:0] address_span_extender_0_cntl_agent_m0_burstcount; // address_span_extender_0_cntl_agent:m0_burstcount -> address_span_extender_0_cntl_translator:uav_burstcount
wire [63:0] address_span_extender_0_cntl_agent_m0_writedata; // address_span_extender_0_cntl_agent:m0_writedata -> address_span_extender_0_cntl_translator:uav_writedata
wire [13:0] address_span_extender_0_cntl_agent_m0_address; // address_span_extender_0_cntl_agent:m0_address -> address_span_extender_0_cntl_translator:uav_address
wire address_span_extender_0_cntl_agent_m0_write; // address_span_extender_0_cntl_agent:m0_write -> address_span_extender_0_cntl_translator:uav_write
wire address_span_extender_0_cntl_agent_m0_lock; // address_span_extender_0_cntl_agent:m0_lock -> address_span_extender_0_cntl_translator:uav_lock
wire address_span_extender_0_cntl_agent_m0_read; // address_span_extender_0_cntl_agent:m0_read -> address_span_extender_0_cntl_translator:uav_read
wire [63:0] address_span_extender_0_cntl_agent_m0_readdata; // address_span_extender_0_cntl_translator:uav_readdata -> address_span_extender_0_cntl_agent:m0_readdata
wire address_span_extender_0_cntl_agent_m0_readdatavalid; // address_span_extender_0_cntl_translator:uav_readdatavalid -> address_span_extender_0_cntl_agent:m0_readdatavalid
wire address_span_extender_0_cntl_agent_m0_debugaccess; // address_span_extender_0_cntl_agent:m0_debugaccess -> address_span_extender_0_cntl_translator:uav_debugaccess
wire [7:0] address_span_extender_0_cntl_agent_m0_byteenable; // address_span_extender_0_cntl_agent:m0_byteenable -> address_span_extender_0_cntl_translator:uav_byteenable
wire address_span_extender_0_cntl_agent_rf_source_endofpacket; // address_span_extender_0_cntl_agent:rf_source_endofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_endofpacket
wire address_span_extender_0_cntl_agent_rf_source_valid; // address_span_extender_0_cntl_agent:rf_source_valid -> address_span_extender_0_cntl_agent_rsp_fifo:in_valid
wire address_span_extender_0_cntl_agent_rf_source_startofpacket; // address_span_extender_0_cntl_agent:rf_source_startofpacket -> address_span_extender_0_cntl_agent_rsp_fifo:in_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rf_source_data; // address_span_extender_0_cntl_agent:rf_source_data -> address_span_extender_0_cntl_agent_rsp_fifo:in_data
wire address_span_extender_0_cntl_agent_rf_source_ready; // address_span_extender_0_cntl_agent_rsp_fifo:in_ready -> address_span_extender_0_cntl_agent:rf_source_ready
wire address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_endofpacket -> address_span_extender_0_cntl_agent:rf_sink_endofpacket
wire address_span_extender_0_cntl_agent_rsp_fifo_out_valid; // address_span_extender_0_cntl_agent_rsp_fifo:out_valid -> address_span_extender_0_cntl_agent:rf_sink_valid
wire address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket; // address_span_extender_0_cntl_agent_rsp_fifo:out_startofpacket -> address_span_extender_0_cntl_agent:rf_sink_startofpacket
wire [125:0] address_span_extender_0_cntl_agent_rsp_fifo_out_data; // address_span_extender_0_cntl_agent_rsp_fifo:out_data -> address_span_extender_0_cntl_agent:rf_sink_data
wire address_span_extender_0_cntl_agent_rsp_fifo_out_ready; // address_span_extender_0_cntl_agent:rf_sink_ready -> address_span_extender_0_cntl_agent_rsp_fifo:out_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_src_valid; // address_span_extender_0_cntl_agent:rdata_fifo_src_valid -> address_span_extender_0_cntl_agent_rdata_fifo:in_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_src_data; // address_span_extender_0_cntl_agent:rdata_fifo_src_data -> address_span_extender_0_cntl_agent_rdata_fifo:in_data
wire address_span_extender_0_cntl_agent_rdata_fifo_src_ready; // address_span_extender_0_cntl_agent_rdata_fifo:in_ready -> address_span_extender_0_cntl_agent:rdata_fifo_src_ready
wire address_span_extender_0_cntl_agent_rdata_fifo_out_valid; // address_span_extender_0_cntl_agent_rdata_fifo:out_valid -> address_span_extender_0_cntl_agent:rdata_fifo_sink_valid
wire [65:0] address_span_extender_0_cntl_agent_rdata_fifo_out_data; // address_span_extender_0_cntl_agent_rdata_fifo:out_data -> address_span_extender_0_cntl_agent:rdata_fifo_sink_data
wire address_span_extender_0_cntl_agent_rdata_fifo_out_ready; // address_span_extender_0_cntl_agent:rdata_fifo_sink_ready -> address_span_extender_0_cntl_agent_rdata_fifo:out_ready
wire sys_description_rom_s1_agent_m0_waitrequest; // sys_description_rom_s1_translator:uav_waitrequest -> sys_description_rom_s1_agent:m0_waitrequest
wire [3:0] sys_description_rom_s1_agent_m0_burstcount; // sys_description_rom_s1_agent:m0_burstcount -> sys_description_rom_s1_translator:uav_burstcount
wire [63:0] sys_description_rom_s1_agent_m0_writedata; // sys_description_rom_s1_agent:m0_writedata -> sys_description_rom_s1_translator:uav_writedata
wire [13:0] sys_description_rom_s1_agent_m0_address; // sys_description_rom_s1_agent:m0_address -> sys_description_rom_s1_translator:uav_address
wire sys_description_rom_s1_agent_m0_write; // sys_description_rom_s1_agent:m0_write -> sys_description_rom_s1_translator:uav_write
wire sys_description_rom_s1_agent_m0_lock; // sys_description_rom_s1_agent:m0_lock -> sys_description_rom_s1_translator:uav_lock
wire sys_description_rom_s1_agent_m0_read; // sys_description_rom_s1_agent:m0_read -> sys_description_rom_s1_translator:uav_read
wire [63:0] sys_description_rom_s1_agent_m0_readdata; // sys_description_rom_s1_translator:uav_readdata -> sys_description_rom_s1_agent:m0_readdata
wire sys_description_rom_s1_agent_m0_readdatavalid; // sys_description_rom_s1_translator:uav_readdatavalid -> sys_description_rom_s1_agent:m0_readdatavalid
wire sys_description_rom_s1_agent_m0_debugaccess; // sys_description_rom_s1_agent:m0_debugaccess -> sys_description_rom_s1_translator:uav_debugaccess
wire [7:0] sys_description_rom_s1_agent_m0_byteenable; // sys_description_rom_s1_agent:m0_byteenable -> sys_description_rom_s1_translator:uav_byteenable
wire sys_description_rom_s1_agent_rf_source_endofpacket; // sys_description_rom_s1_agent:rf_source_endofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_endofpacket
wire sys_description_rom_s1_agent_rf_source_valid; // sys_description_rom_s1_agent:rf_source_valid -> sys_description_rom_s1_agent_rsp_fifo:in_valid
wire sys_description_rom_s1_agent_rf_source_startofpacket; // sys_description_rom_s1_agent:rf_source_startofpacket -> sys_description_rom_s1_agent_rsp_fifo:in_startofpacket
wire [125:0] sys_description_rom_s1_agent_rf_source_data; // sys_description_rom_s1_agent:rf_source_data -> sys_description_rom_s1_agent_rsp_fifo:in_data
wire sys_description_rom_s1_agent_rf_source_ready; // sys_description_rom_s1_agent_rsp_fifo:in_ready -> sys_description_rom_s1_agent:rf_source_ready
wire sys_description_rom_s1_agent_rsp_fifo_out_endofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_endofpacket -> sys_description_rom_s1_agent:rf_sink_endofpacket
wire sys_description_rom_s1_agent_rsp_fifo_out_valid; // sys_description_rom_s1_agent_rsp_fifo:out_valid -> sys_description_rom_s1_agent:rf_sink_valid
wire sys_description_rom_s1_agent_rsp_fifo_out_startofpacket; // sys_description_rom_s1_agent_rsp_fifo:out_startofpacket -> sys_description_rom_s1_agent:rf_sink_startofpacket
wire [125:0] sys_description_rom_s1_agent_rsp_fifo_out_data; // sys_description_rom_s1_agent_rsp_fifo:out_data -> sys_description_rom_s1_agent:rf_sink_data
wire sys_description_rom_s1_agent_rsp_fifo_out_ready; // sys_description_rom_s1_agent:rf_sink_ready -> sys_description_rom_s1_agent_rsp_fifo:out_ready
wire sys_description_rom_s1_agent_rdata_fifo_src_valid; // sys_description_rom_s1_agent:rdata_fifo_src_valid -> sys_description_rom_s1_agent:rdata_fifo_sink_valid
wire [65:0] sys_description_rom_s1_agent_rdata_fifo_src_data; // sys_description_rom_s1_agent:rdata_fifo_src_data -> sys_description_rom_s1_agent:rdata_fifo_sink_data
wire sys_description_rom_s1_agent_rdata_fifo_src_ready; // sys_description_rom_s1_agent:rdata_fifo_sink_ready -> sys_description_rom_s1_agent:rdata_fifo_src_ready
wire sw_reset_s_agent_m0_waitrequest; // sw_reset_s_translator:uav_waitrequest -> sw_reset_s_agent:m0_waitrequest
wire [3:0] sw_reset_s_agent_m0_burstcount; // sw_reset_s_agent:m0_burstcount -> sw_reset_s_translator:uav_burstcount
wire [63:0] sw_reset_s_agent_m0_writedata; // sw_reset_s_agent:m0_writedata -> sw_reset_s_translator:uav_writedata
wire [13:0] sw_reset_s_agent_m0_address; // sw_reset_s_agent:m0_address -> sw_reset_s_translator:uav_address
wire sw_reset_s_agent_m0_write; // sw_reset_s_agent:m0_write -> sw_reset_s_translator:uav_write
wire sw_reset_s_agent_m0_lock; // sw_reset_s_agent:m0_lock -> sw_reset_s_translator:uav_lock
wire sw_reset_s_agent_m0_read; // sw_reset_s_agent:m0_read -> sw_reset_s_translator:uav_read
wire [63:0] sw_reset_s_agent_m0_readdata; // sw_reset_s_translator:uav_readdata -> sw_reset_s_agent:m0_readdata
wire sw_reset_s_agent_m0_readdatavalid; // sw_reset_s_translator:uav_readdatavalid -> sw_reset_s_agent:m0_readdatavalid
wire sw_reset_s_agent_m0_debugaccess; // sw_reset_s_agent:m0_debugaccess -> sw_reset_s_translator:uav_debugaccess
wire [7:0] sw_reset_s_agent_m0_byteenable; // sw_reset_s_agent:m0_byteenable -> sw_reset_s_translator:uav_byteenable
wire sw_reset_s_agent_rf_source_endofpacket; // sw_reset_s_agent:rf_source_endofpacket -> sw_reset_s_agent_rsp_fifo:in_endofpacket
wire sw_reset_s_agent_rf_source_valid; // sw_reset_s_agent:rf_source_valid -> sw_reset_s_agent_rsp_fifo:in_valid
wire sw_reset_s_agent_rf_source_startofpacket; // sw_reset_s_agent:rf_source_startofpacket -> sw_reset_s_agent_rsp_fifo:in_startofpacket
wire [125:0] sw_reset_s_agent_rf_source_data; // sw_reset_s_agent:rf_source_data -> sw_reset_s_agent_rsp_fifo:in_data
wire sw_reset_s_agent_rf_source_ready; // sw_reset_s_agent_rsp_fifo:in_ready -> sw_reset_s_agent:rf_source_ready
wire sw_reset_s_agent_rsp_fifo_out_endofpacket; // sw_reset_s_agent_rsp_fifo:out_endofpacket -> sw_reset_s_agent:rf_sink_endofpacket
wire sw_reset_s_agent_rsp_fifo_out_valid; // sw_reset_s_agent_rsp_fifo:out_valid -> sw_reset_s_agent:rf_sink_valid
wire sw_reset_s_agent_rsp_fifo_out_startofpacket; // sw_reset_s_agent_rsp_fifo:out_startofpacket -> sw_reset_s_agent:rf_sink_startofpacket
wire [125:0] sw_reset_s_agent_rsp_fifo_out_data; // sw_reset_s_agent_rsp_fifo:out_data -> sw_reset_s_agent:rf_sink_data
wire sw_reset_s_agent_rsp_fifo_out_ready; // sw_reset_s_agent:rf_sink_ready -> sw_reset_s_agent_rsp_fifo:out_ready
wire sw_reset_s_agent_rdata_fifo_src_valid; // sw_reset_s_agent:rdata_fifo_src_valid -> sw_reset_s_agent:rdata_fifo_sink_valid
wire [65:0] sw_reset_s_agent_rdata_fifo_src_data; // sw_reset_s_agent:rdata_fifo_src_data -> sw_reset_s_agent:rdata_fifo_sink_data
wire sw_reset_s_agent_rdata_fifo_src_ready; // sw_reset_s_agent:rdata_fifo_sink_ready -> sw_reset_s_agent:rdata_fifo_src_ready
wire mem_org_mode_s_agent_m0_waitrequest; // mem_org_mode_s_translator:uav_waitrequest -> mem_org_mode_s_agent:m0_waitrequest
wire [2:0] mem_org_mode_s_agent_m0_burstcount; // mem_org_mode_s_agent:m0_burstcount -> mem_org_mode_s_translator:uav_burstcount
wire [31:0] mem_org_mode_s_agent_m0_writedata; // mem_org_mode_s_agent:m0_writedata -> mem_org_mode_s_translator:uav_writedata
wire [13:0] mem_org_mode_s_agent_m0_address; // mem_org_mode_s_agent:m0_address -> mem_org_mode_s_translator:uav_address
wire mem_org_mode_s_agent_m0_write; // mem_org_mode_s_agent:m0_write -> mem_org_mode_s_translator:uav_write
wire mem_org_mode_s_agent_m0_lock; // mem_org_mode_s_agent:m0_lock -> mem_org_mode_s_translator:uav_lock
wire mem_org_mode_s_agent_m0_read; // mem_org_mode_s_agent:m0_read -> mem_org_mode_s_translator:uav_read
wire [31:0] mem_org_mode_s_agent_m0_readdata; // mem_org_mode_s_translator:uav_readdata -> mem_org_mode_s_agent:m0_readdata
wire mem_org_mode_s_agent_m0_readdatavalid; // mem_org_mode_s_translator:uav_readdatavalid -> mem_org_mode_s_agent:m0_readdatavalid
wire mem_org_mode_s_agent_m0_debugaccess; // mem_org_mode_s_agent:m0_debugaccess -> mem_org_mode_s_translator:uav_debugaccess
wire [3:0] mem_org_mode_s_agent_m0_byteenable; // mem_org_mode_s_agent:m0_byteenable -> mem_org_mode_s_translator:uav_byteenable
wire mem_org_mode_s_agent_rf_source_endofpacket; // mem_org_mode_s_agent:rf_source_endofpacket -> mem_org_mode_s_agent_rsp_fifo:in_endofpacket
wire mem_org_mode_s_agent_rf_source_valid; // mem_org_mode_s_agent:rf_source_valid -> mem_org_mode_s_agent_rsp_fifo:in_valid
wire mem_org_mode_s_agent_rf_source_startofpacket; // mem_org_mode_s_agent:rf_source_startofpacket -> mem_org_mode_s_agent_rsp_fifo:in_startofpacket
wire [89:0] mem_org_mode_s_agent_rf_source_data; // mem_org_mode_s_agent:rf_source_data -> mem_org_mode_s_agent_rsp_fifo:in_data
wire mem_org_mode_s_agent_rf_source_ready; // mem_org_mode_s_agent_rsp_fifo:in_ready -> mem_org_mode_s_agent:rf_source_ready
wire mem_org_mode_s_agent_rsp_fifo_out_endofpacket; // mem_org_mode_s_agent_rsp_fifo:out_endofpacket -> mem_org_mode_s_agent:rf_sink_endofpacket
wire mem_org_mode_s_agent_rsp_fifo_out_valid; // mem_org_mode_s_agent_rsp_fifo:out_valid -> mem_org_mode_s_agent:rf_sink_valid
wire mem_org_mode_s_agent_rsp_fifo_out_startofpacket; // mem_org_mode_s_agent_rsp_fifo:out_startofpacket -> mem_org_mode_s_agent:rf_sink_startofpacket
wire [89:0] mem_org_mode_s_agent_rsp_fifo_out_data; // mem_org_mode_s_agent_rsp_fifo:out_data -> mem_org_mode_s_agent:rf_sink_data
wire mem_org_mode_s_agent_rsp_fifo_out_ready; // mem_org_mode_s_agent:rf_sink_ready -> mem_org_mode_s_agent_rsp_fifo:out_ready
wire mem_org_mode_s_agent_rdata_fifo_src_valid; // mem_org_mode_s_agent:rdata_fifo_src_valid -> mem_org_mode_s_agent:rdata_fifo_sink_valid
wire [33:0] mem_org_mode_s_agent_rdata_fifo_src_data; // mem_org_mode_s_agent:rdata_fifo_src_data -> mem_org_mode_s_agent:rdata_fifo_sink_data
wire mem_org_mode_s_agent_rdata_fifo_src_ready; // mem_org_mode_s_agent:rdata_fifo_sink_ready -> mem_org_mode_s_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> mem_org_mode_s_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> mem_org_mode_s_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> mem_org_mode_s_agent:cp_startofpacket
wire [88:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> mem_org_mode_s_agent:cp_data
wire [6:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> mem_org_mode_s_agent:cp_channel
wire cmd_mux_004_src_ready; // mem_org_mode_s_agent:cp_ready -> cmd_mux_004:src_ready
wire version_id_0_s_agent_m0_waitrequest; // version_id_0_s_translator:uav_waitrequest -> version_id_0_s_agent:m0_waitrequest
wire [2:0] version_id_0_s_agent_m0_burstcount; // version_id_0_s_agent:m0_burstcount -> version_id_0_s_translator:uav_burstcount
wire [31:0] version_id_0_s_agent_m0_writedata; // version_id_0_s_agent:m0_writedata -> version_id_0_s_translator:uav_writedata
wire [13:0] version_id_0_s_agent_m0_address; // version_id_0_s_agent:m0_address -> version_id_0_s_translator:uav_address
wire version_id_0_s_agent_m0_write; // version_id_0_s_agent:m0_write -> version_id_0_s_translator:uav_write
wire version_id_0_s_agent_m0_lock; // version_id_0_s_agent:m0_lock -> version_id_0_s_translator:uav_lock
wire version_id_0_s_agent_m0_read; // version_id_0_s_agent:m0_read -> version_id_0_s_translator:uav_read
wire [31:0] version_id_0_s_agent_m0_readdata; // version_id_0_s_translator:uav_readdata -> version_id_0_s_agent:m0_readdata
wire version_id_0_s_agent_m0_readdatavalid; // version_id_0_s_translator:uav_readdatavalid -> version_id_0_s_agent:m0_readdatavalid
wire version_id_0_s_agent_m0_debugaccess; // version_id_0_s_agent:m0_debugaccess -> version_id_0_s_translator:uav_debugaccess
wire [3:0] version_id_0_s_agent_m0_byteenable; // version_id_0_s_agent:m0_byteenable -> version_id_0_s_translator:uav_byteenable
wire version_id_0_s_agent_rf_source_endofpacket; // version_id_0_s_agent:rf_source_endofpacket -> version_id_0_s_agent_rsp_fifo:in_endofpacket
wire version_id_0_s_agent_rf_source_valid; // version_id_0_s_agent:rf_source_valid -> version_id_0_s_agent_rsp_fifo:in_valid
wire version_id_0_s_agent_rf_source_startofpacket; // version_id_0_s_agent:rf_source_startofpacket -> version_id_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] version_id_0_s_agent_rf_source_data; // version_id_0_s_agent:rf_source_data -> version_id_0_s_agent_rsp_fifo:in_data
wire version_id_0_s_agent_rf_source_ready; // version_id_0_s_agent_rsp_fifo:in_ready -> version_id_0_s_agent:rf_source_ready
wire version_id_0_s_agent_rsp_fifo_out_endofpacket; // version_id_0_s_agent_rsp_fifo:out_endofpacket -> version_id_0_s_agent:rf_sink_endofpacket
wire version_id_0_s_agent_rsp_fifo_out_valid; // version_id_0_s_agent_rsp_fifo:out_valid -> version_id_0_s_agent:rf_sink_valid
wire version_id_0_s_agent_rsp_fifo_out_startofpacket; // version_id_0_s_agent_rsp_fifo:out_startofpacket -> version_id_0_s_agent:rf_sink_startofpacket
wire [89:0] version_id_0_s_agent_rsp_fifo_out_data; // version_id_0_s_agent_rsp_fifo:out_data -> version_id_0_s_agent:rf_sink_data
wire version_id_0_s_agent_rsp_fifo_out_ready; // version_id_0_s_agent:rf_sink_ready -> version_id_0_s_agent_rsp_fifo:out_ready
wire version_id_0_s_agent_rdata_fifo_src_valid; // version_id_0_s_agent:rdata_fifo_src_valid -> version_id_0_s_agent:rdata_fifo_sink_valid
wire [33:0] version_id_0_s_agent_rdata_fifo_src_data; // version_id_0_s_agent:rdata_fifo_src_data -> version_id_0_s_agent:rdata_fifo_sink_data
wire version_id_0_s_agent_rdata_fifo_src_ready; // version_id_0_s_agent:rdata_fifo_sink_ready -> version_id_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> version_id_0_s_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> version_id_0_s_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> version_id_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> version_id_0_s_agent:cp_data
wire [6:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> version_id_0_s_agent:cp_channel
wire cmd_mux_005_src_ready; // version_id_0_s_agent:cp_ready -> cmd_mux_005:src_ready
wire irq_ena_0_s_agent_m0_waitrequest; // irq_ena_0_s_translator:uav_waitrequest -> irq_ena_0_s_agent:m0_waitrequest
wire [2:0] irq_ena_0_s_agent_m0_burstcount; // irq_ena_0_s_agent:m0_burstcount -> irq_ena_0_s_translator:uav_burstcount
wire [31:0] irq_ena_0_s_agent_m0_writedata; // irq_ena_0_s_agent:m0_writedata -> irq_ena_0_s_translator:uav_writedata
wire [13:0] irq_ena_0_s_agent_m0_address; // irq_ena_0_s_agent:m0_address -> irq_ena_0_s_translator:uav_address
wire irq_ena_0_s_agent_m0_write; // irq_ena_0_s_agent:m0_write -> irq_ena_0_s_translator:uav_write
wire irq_ena_0_s_agent_m0_lock; // irq_ena_0_s_agent:m0_lock -> irq_ena_0_s_translator:uav_lock
wire irq_ena_0_s_agent_m0_read; // irq_ena_0_s_agent:m0_read -> irq_ena_0_s_translator:uav_read
wire [31:0] irq_ena_0_s_agent_m0_readdata; // irq_ena_0_s_translator:uav_readdata -> irq_ena_0_s_agent:m0_readdata
wire irq_ena_0_s_agent_m0_readdatavalid; // irq_ena_0_s_translator:uav_readdatavalid -> irq_ena_0_s_agent:m0_readdatavalid
wire irq_ena_0_s_agent_m0_debugaccess; // irq_ena_0_s_agent:m0_debugaccess -> irq_ena_0_s_translator:uav_debugaccess
wire [3:0] irq_ena_0_s_agent_m0_byteenable; // irq_ena_0_s_agent:m0_byteenable -> irq_ena_0_s_translator:uav_byteenable
wire irq_ena_0_s_agent_rf_source_endofpacket; // irq_ena_0_s_agent:rf_source_endofpacket -> irq_ena_0_s_agent_rsp_fifo:in_endofpacket
wire irq_ena_0_s_agent_rf_source_valid; // irq_ena_0_s_agent:rf_source_valid -> irq_ena_0_s_agent_rsp_fifo:in_valid
wire irq_ena_0_s_agent_rf_source_startofpacket; // irq_ena_0_s_agent:rf_source_startofpacket -> irq_ena_0_s_agent_rsp_fifo:in_startofpacket
wire [89:0] irq_ena_0_s_agent_rf_source_data; // irq_ena_0_s_agent:rf_source_data -> irq_ena_0_s_agent_rsp_fifo:in_data
wire irq_ena_0_s_agent_rf_source_ready; // irq_ena_0_s_agent_rsp_fifo:in_ready -> irq_ena_0_s_agent:rf_source_ready
wire irq_ena_0_s_agent_rsp_fifo_out_endofpacket; // irq_ena_0_s_agent_rsp_fifo:out_endofpacket -> irq_ena_0_s_agent:rf_sink_endofpacket
wire irq_ena_0_s_agent_rsp_fifo_out_valid; // irq_ena_0_s_agent_rsp_fifo:out_valid -> irq_ena_0_s_agent:rf_sink_valid
wire irq_ena_0_s_agent_rsp_fifo_out_startofpacket; // irq_ena_0_s_agent_rsp_fifo:out_startofpacket -> irq_ena_0_s_agent:rf_sink_startofpacket
wire [89:0] irq_ena_0_s_agent_rsp_fifo_out_data; // irq_ena_0_s_agent_rsp_fifo:out_data -> irq_ena_0_s_agent:rf_sink_data
wire irq_ena_0_s_agent_rsp_fifo_out_ready; // irq_ena_0_s_agent:rf_sink_ready -> irq_ena_0_s_agent_rsp_fifo:out_ready
wire irq_ena_0_s_agent_rdata_fifo_src_valid; // irq_ena_0_s_agent:rdata_fifo_src_valid -> irq_ena_0_s_agent:rdata_fifo_sink_valid
wire [33:0] irq_ena_0_s_agent_rdata_fifo_src_data; // irq_ena_0_s_agent:rdata_fifo_src_data -> irq_ena_0_s_agent:rdata_fifo_sink_data
wire irq_ena_0_s_agent_rdata_fifo_src_ready; // irq_ena_0_s_agent:rdata_fifo_sink_ready -> irq_ena_0_s_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> irq_ena_0_s_agent:cp_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> irq_ena_0_s_agent:cp_valid
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> irq_ena_0_s_agent:cp_startofpacket
wire [88:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> irq_ena_0_s_agent:cp_data
wire [6:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> irq_ena_0_s_agent:cp_channel
wire cmd_mux_006_src_ready; // irq_ena_0_s_agent:cp_ready -> cmd_mux_006:src_ready
wire kernel_cntrl_m0_agent_cp_endofpacket; // kernel_cntrl_m0_agent:cp_endofpacket -> router:sink_endofpacket
wire kernel_cntrl_m0_agent_cp_valid; // kernel_cntrl_m0_agent:cp_valid -> router:sink_valid
wire kernel_cntrl_m0_agent_cp_startofpacket; // kernel_cntrl_m0_agent:cp_startofpacket -> router:sink_startofpacket
wire [88:0] kernel_cntrl_m0_agent_cp_data; // kernel_cntrl_m0_agent:cp_data -> router:sink_data
wire kernel_cntrl_m0_agent_cp_ready; // router:sink_ready -> kernel_cntrl_m0_agent:cp_ready
wire address_span_extender_0_windowed_slave_agent_rp_endofpacket; // address_span_extender_0_windowed_slave_agent:rp_endofpacket -> router_001:sink_endofpacket
wire address_span_extender_0_windowed_slave_agent_rp_valid; // address_span_extender_0_windowed_slave_agent:rp_valid -> router_001:sink_valid
wire address_span_extender_0_windowed_slave_agent_rp_startofpacket; // address_span_extender_0_windowed_slave_agent:rp_startofpacket -> router_001:sink_startofpacket
wire [88:0] address_span_extender_0_windowed_slave_agent_rp_data; // address_span_extender_0_windowed_slave_agent:rp_data -> router_001:sink_data
wire address_span_extender_0_windowed_slave_agent_rp_ready; // router_001:sink_ready -> address_span_extender_0_windowed_slave_agent:rp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> rsp_demux:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> rsp_demux:sink_startofpacket
wire [88:0] router_001_src_data; // router_001:src_data -> rsp_demux:sink_data
wire [6:0] router_001_src_channel; // router_001:src_channel -> rsp_demux:sink_channel
wire router_001_src_ready; // rsp_demux:sink_ready -> router_001:src_ready
wire address_span_extender_0_cntl_agent_rp_endofpacket; // address_span_extender_0_cntl_agent:rp_endofpacket -> router_002:sink_endofpacket
wire address_span_extender_0_cntl_agent_rp_valid; // address_span_extender_0_cntl_agent:rp_valid -> router_002:sink_valid
wire address_span_extender_0_cntl_agent_rp_startofpacket; // address_span_extender_0_cntl_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [124:0] address_span_extender_0_cntl_agent_rp_data; // address_span_extender_0_cntl_agent:rp_data -> router_002:sink_data
wire address_span_extender_0_cntl_agent_rp_ready; // router_002:sink_ready -> address_span_extender_0_cntl_agent:rp_ready
wire sys_description_rom_s1_agent_rp_endofpacket; // sys_description_rom_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sys_description_rom_s1_agent_rp_valid; // sys_description_rom_s1_agent:rp_valid -> router_003:sink_valid
wire sys_description_rom_s1_agent_rp_startofpacket; // sys_description_rom_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [124:0] sys_description_rom_s1_agent_rp_data; // sys_description_rom_s1_agent:rp_data -> router_003:sink_data
wire sys_description_rom_s1_agent_rp_ready; // router_003:sink_ready -> sys_description_rom_s1_agent:rp_ready
wire sw_reset_s_agent_rp_endofpacket; // sw_reset_s_agent:rp_endofpacket -> router_004:sink_endofpacket
wire sw_reset_s_agent_rp_valid; // sw_reset_s_agent:rp_valid -> router_004:sink_valid
wire sw_reset_s_agent_rp_startofpacket; // sw_reset_s_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [124:0] sw_reset_s_agent_rp_data; // sw_reset_s_agent:rp_data -> router_004:sink_data
wire sw_reset_s_agent_rp_ready; // router_004:sink_ready -> sw_reset_s_agent:rp_ready
wire mem_org_mode_s_agent_rp_endofpacket; // mem_org_mode_s_agent:rp_endofpacket -> router_005:sink_endofpacket
wire mem_org_mode_s_agent_rp_valid; // mem_org_mode_s_agent:rp_valid -> router_005:sink_valid
wire mem_org_mode_s_agent_rp_startofpacket; // mem_org_mode_s_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [88:0] mem_org_mode_s_agent_rp_data; // mem_org_mode_s_agent:rp_data -> router_005:sink_data
wire mem_org_mode_s_agent_rp_ready; // router_005:sink_ready -> mem_org_mode_s_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_004:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [88:0] router_005_src_data; // router_005:src_data -> rsp_demux_004:sink_data
wire [6:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_004:sink_channel
wire router_005_src_ready; // rsp_demux_004:sink_ready -> router_005:src_ready
wire version_id_0_s_agent_rp_endofpacket; // version_id_0_s_agent:rp_endofpacket -> router_006:sink_endofpacket
wire version_id_0_s_agent_rp_valid; // version_id_0_s_agent:rp_valid -> router_006:sink_valid
wire version_id_0_s_agent_rp_startofpacket; // version_id_0_s_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [88:0] version_id_0_s_agent_rp_data; // version_id_0_s_agent:rp_data -> router_006:sink_data
wire version_id_0_s_agent_rp_ready; // router_006:sink_ready -> version_id_0_s_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_005:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [88:0] router_006_src_data; // router_006:src_data -> rsp_demux_005:sink_data
wire [6:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_005:sink_channel
wire router_006_src_ready; // rsp_demux_005:sink_ready -> router_006:src_ready
wire irq_ena_0_s_agent_rp_endofpacket; // irq_ena_0_s_agent:rp_endofpacket -> router_007:sink_endofpacket
wire irq_ena_0_s_agent_rp_valid; // irq_ena_0_s_agent:rp_valid -> router_007:sink_valid
wire irq_ena_0_s_agent_rp_startofpacket; // irq_ena_0_s_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [88:0] irq_ena_0_s_agent_rp_data; // irq_ena_0_s_agent:rp_data -> router_007:sink_data
wire irq_ena_0_s_agent_rp_ready; // router_007:sink_ready -> irq_ena_0_s_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_006:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire [88:0] router_007_src_data; // router_007:src_data -> rsp_demux_006:sink_data
wire [6:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_006:sink_channel
wire router_007_src_ready; // rsp_demux_006:sink_ready -> router_007:src_ready
wire router_src_endofpacket; // router:src_endofpacket -> kernel_cntrl_m0_limiter:cmd_sink_endofpacket
wire router_src_valid; // router:src_valid -> kernel_cntrl_m0_limiter:cmd_sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> kernel_cntrl_m0_limiter:cmd_sink_startofpacket
wire [88:0] router_src_data; // router:src_data -> kernel_cntrl_m0_limiter:cmd_sink_data
wire [6:0] router_src_channel; // router:src_channel -> kernel_cntrl_m0_limiter:cmd_sink_channel
wire router_src_ready; // kernel_cntrl_m0_limiter:cmd_sink_ready -> router:src_ready
wire kernel_cntrl_m0_limiter_cmd_src_endofpacket; // kernel_cntrl_m0_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire kernel_cntrl_m0_limiter_cmd_src_startofpacket; // kernel_cntrl_m0_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_cmd_src_data; // kernel_cntrl_m0_limiter:cmd_src_data -> cmd_demux:sink_data
wire [6:0] kernel_cntrl_m0_limiter_cmd_src_channel; // kernel_cntrl_m0_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire kernel_cntrl_m0_limiter_cmd_src_ready; // cmd_demux:sink_ready -> kernel_cntrl_m0_limiter:cmd_src_ready
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> kernel_cntrl_m0_limiter:rsp_sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> kernel_cntrl_m0_limiter:rsp_sink_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> kernel_cntrl_m0_limiter:rsp_sink_startofpacket
wire [88:0] rsp_mux_src_data; // rsp_mux:src_data -> kernel_cntrl_m0_limiter:rsp_sink_data
wire [6:0] rsp_mux_src_channel; // rsp_mux:src_channel -> kernel_cntrl_m0_limiter:rsp_sink_channel
wire rsp_mux_src_ready; // kernel_cntrl_m0_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire kernel_cntrl_m0_limiter_rsp_src_endofpacket; // kernel_cntrl_m0_limiter:rsp_src_endofpacket -> kernel_cntrl_m0_agent:rp_endofpacket
wire kernel_cntrl_m0_limiter_rsp_src_valid; // kernel_cntrl_m0_limiter:rsp_src_valid -> kernel_cntrl_m0_agent:rp_valid
wire kernel_cntrl_m0_limiter_rsp_src_startofpacket; // kernel_cntrl_m0_limiter:rsp_src_startofpacket -> kernel_cntrl_m0_agent:rp_startofpacket
wire [88:0] kernel_cntrl_m0_limiter_rsp_src_data; // kernel_cntrl_m0_limiter:rsp_src_data -> kernel_cntrl_m0_agent:rp_data
wire [6:0] kernel_cntrl_m0_limiter_rsp_src_channel; // kernel_cntrl_m0_limiter:rsp_src_channel -> kernel_cntrl_m0_agent:rp_channel
wire kernel_cntrl_m0_limiter_rsp_src_ready; // kernel_cntrl_m0_agent:rp_ready -> kernel_cntrl_m0_limiter:rsp_src_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [88:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [6:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [88:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire [6:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [88:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire [6:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [88:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire [6:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> cmd_mux_006:sink0_valid
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire [88:0] cmd_demux_src6_data; // cmd_demux:src6_data -> cmd_mux_006:sink0_data
wire [6:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux:src6_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [88:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [6:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire [88:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire [6:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire [88:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire [6:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire [88:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire [6:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux:sink6_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux:sink6_valid
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux:sink6_startofpacket
wire [88:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux:sink6_data
wire [6:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux:sink6_channel
wire rsp_demux_006_src0_ready; // rsp_mux:sink6_ready -> rsp_demux_006:src0_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> address_span_extender_0_cntl_cmd_width_adapter:in_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> address_span_extender_0_cntl_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> address_span_extender_0_cntl_cmd_width_adapter:in_data
wire [6:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> address_span_extender_0_cntl_cmd_width_adapter:in_channel
wire cmd_mux_001_src_ready; // address_span_extender_0_cntl_cmd_width_adapter:in_ready -> cmd_mux_001:src_ready
wire address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_endofpacket -> address_span_extender_0_cntl_agent:cp_endofpacket
wire address_span_extender_0_cntl_cmd_width_adapter_src_valid; // address_span_extender_0_cntl_cmd_width_adapter:out_valid -> address_span_extender_0_cntl_agent:cp_valid
wire address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket; // address_span_extender_0_cntl_cmd_width_adapter:out_startofpacket -> address_span_extender_0_cntl_agent:cp_startofpacket
wire [124:0] address_span_extender_0_cntl_cmd_width_adapter_src_data; // address_span_extender_0_cntl_cmd_width_adapter:out_data -> address_span_extender_0_cntl_agent:cp_data
wire address_span_extender_0_cntl_cmd_width_adapter_src_ready; // address_span_extender_0_cntl_agent:cp_ready -> address_span_extender_0_cntl_cmd_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_cmd_width_adapter_src_channel; // address_span_extender_0_cntl_cmd_width_adapter:out_channel -> address_span_extender_0_cntl_agent:cp_channel
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> sys_description_rom_s1_cmd_width_adapter:in_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> sys_description_rom_s1_cmd_width_adapter:in_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> sys_description_rom_s1_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> sys_description_rom_s1_cmd_width_adapter:in_data
wire [6:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> sys_description_rom_s1_cmd_width_adapter:in_channel
wire cmd_mux_002_src_ready; // sys_description_rom_s1_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire sys_description_rom_s1_cmd_width_adapter_src_endofpacket; // sys_description_rom_s1_cmd_width_adapter:out_endofpacket -> sys_description_rom_s1_agent:cp_endofpacket
wire sys_description_rom_s1_cmd_width_adapter_src_valid; // sys_description_rom_s1_cmd_width_adapter:out_valid -> sys_description_rom_s1_agent:cp_valid
wire sys_description_rom_s1_cmd_width_adapter_src_startofpacket; // sys_description_rom_s1_cmd_width_adapter:out_startofpacket -> sys_description_rom_s1_agent:cp_startofpacket
wire [124:0] sys_description_rom_s1_cmd_width_adapter_src_data; // sys_description_rom_s1_cmd_width_adapter:out_data -> sys_description_rom_s1_agent:cp_data
wire sys_description_rom_s1_cmd_width_adapter_src_ready; // sys_description_rom_s1_agent:cp_ready -> sys_description_rom_s1_cmd_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_cmd_width_adapter_src_channel; // sys_description_rom_s1_cmd_width_adapter:out_channel -> sys_description_rom_s1_agent:cp_channel
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> sw_reset_s_cmd_width_adapter:in_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> sw_reset_s_cmd_width_adapter:in_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> sw_reset_s_cmd_width_adapter:in_startofpacket
wire [88:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> sw_reset_s_cmd_width_adapter:in_data
wire [6:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> sw_reset_s_cmd_width_adapter:in_channel
wire cmd_mux_003_src_ready; // sw_reset_s_cmd_width_adapter:in_ready -> cmd_mux_003:src_ready
wire sw_reset_s_cmd_width_adapter_src_endofpacket; // sw_reset_s_cmd_width_adapter:out_endofpacket -> sw_reset_s_agent:cp_endofpacket
wire sw_reset_s_cmd_width_adapter_src_valid; // sw_reset_s_cmd_width_adapter:out_valid -> sw_reset_s_agent:cp_valid
wire sw_reset_s_cmd_width_adapter_src_startofpacket; // sw_reset_s_cmd_width_adapter:out_startofpacket -> sw_reset_s_agent:cp_startofpacket
wire [124:0] sw_reset_s_cmd_width_adapter_src_data; // sw_reset_s_cmd_width_adapter:out_data -> sw_reset_s_agent:cp_data
wire sw_reset_s_cmd_width_adapter_src_ready; // sw_reset_s_agent:cp_ready -> sw_reset_s_cmd_width_adapter:out_ready
wire [6:0] sw_reset_s_cmd_width_adapter_src_channel; // sw_reset_s_cmd_width_adapter:out_channel -> sw_reset_s_agent:cp_channel
wire router_002_src_endofpacket; // router_002:src_endofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_endofpacket
wire router_002_src_valid; // router_002:src_valid -> address_span_extender_0_cntl_rsp_width_adapter:in_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> address_span_extender_0_cntl_rsp_width_adapter:in_startofpacket
wire [124:0] router_002_src_data; // router_002:src_data -> address_span_extender_0_cntl_rsp_width_adapter:in_data
wire [6:0] router_002_src_channel; // router_002:src_channel -> address_span_extender_0_cntl_rsp_width_adapter:in_channel
wire router_002_src_ready; // address_span_extender_0_cntl_rsp_width_adapter:in_ready -> router_002:src_ready
wire address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_endofpacket -> rsp_demux_001:sink_endofpacket
wire address_span_extender_0_cntl_rsp_width_adapter_src_valid; // address_span_extender_0_cntl_rsp_width_adapter:out_valid -> rsp_demux_001:sink_valid
wire address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket; // address_span_extender_0_cntl_rsp_width_adapter:out_startofpacket -> rsp_demux_001:sink_startofpacket
wire [88:0] address_span_extender_0_cntl_rsp_width_adapter_src_data; // address_span_extender_0_cntl_rsp_width_adapter:out_data -> rsp_demux_001:sink_data
wire address_span_extender_0_cntl_rsp_width_adapter_src_ready; // rsp_demux_001:sink_ready -> address_span_extender_0_cntl_rsp_width_adapter:out_ready
wire [6:0] address_span_extender_0_cntl_rsp_width_adapter_src_channel; // address_span_extender_0_cntl_rsp_width_adapter:out_channel -> rsp_demux_001:sink_channel
wire router_003_src_endofpacket; // router_003:src_endofpacket -> sys_description_rom_s1_rsp_width_adapter:in_endofpacket
wire router_003_src_valid; // router_003:src_valid -> sys_description_rom_s1_rsp_width_adapter:in_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> sys_description_rom_s1_rsp_width_adapter:in_startofpacket
wire [124:0] router_003_src_data; // router_003:src_data -> sys_description_rom_s1_rsp_width_adapter:in_data
wire [6:0] router_003_src_channel; // router_003:src_channel -> sys_description_rom_s1_rsp_width_adapter:in_channel
wire router_003_src_ready; // sys_description_rom_s1_rsp_width_adapter:in_ready -> router_003:src_ready
wire sys_description_rom_s1_rsp_width_adapter_src_endofpacket; // sys_description_rom_s1_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire sys_description_rom_s1_rsp_width_adapter_src_valid; // sys_description_rom_s1_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire sys_description_rom_s1_rsp_width_adapter_src_startofpacket; // sys_description_rom_s1_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire [88:0] sys_description_rom_s1_rsp_width_adapter_src_data; // sys_description_rom_s1_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire sys_description_rom_s1_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> sys_description_rom_s1_rsp_width_adapter:out_ready
wire [6:0] sys_description_rom_s1_rsp_width_adapter_src_channel; // sys_description_rom_s1_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire router_004_src_endofpacket; // router_004:src_endofpacket -> sw_reset_s_rsp_width_adapter:in_endofpacket
wire router_004_src_valid; // router_004:src_valid -> sw_reset_s_rsp_width_adapter:in_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> sw_reset_s_rsp_width_adapter:in_startofpacket
wire [124:0] router_004_src_data; // router_004:src_data -> sw_reset_s_rsp_width_adapter:in_data
wire [6:0] router_004_src_channel; // router_004:src_channel -> sw_reset_s_rsp_width_adapter:in_channel
wire router_004_src_ready; // sw_reset_s_rsp_width_adapter:in_ready -> router_004:src_ready
wire sw_reset_s_rsp_width_adapter_src_endofpacket; // sw_reset_s_rsp_width_adapter:out_endofpacket -> rsp_demux_003:sink_endofpacket
wire sw_reset_s_rsp_width_adapter_src_valid; // sw_reset_s_rsp_width_adapter:out_valid -> rsp_demux_003:sink_valid
wire sw_reset_s_rsp_width_adapter_src_startofpacket; // sw_reset_s_rsp_width_adapter:out_startofpacket -> rsp_demux_003:sink_startofpacket
wire [88:0] sw_reset_s_rsp_width_adapter_src_data; // sw_reset_s_rsp_width_adapter:out_data -> rsp_demux_003:sink_data
wire sw_reset_s_rsp_width_adapter_src_ready; // rsp_demux_003:sink_ready -> sw_reset_s_rsp_width_adapter:out_ready
wire [6:0] sw_reset_s_rsp_width_adapter_src_channel; // sw_reset_s_rsp_width_adapter:out_channel -> rsp_demux_003:sink_channel
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> crosser:in_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> crosser:in_startofpacket
wire [88:0] cmd_demux_src0_data; // cmd_demux:src0_data -> crosser:in_data
wire [6:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> crosser:in_channel
wire cmd_demux_src0_ready; // crosser:in_ready -> cmd_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux:sink0_startofpacket
wire [88:0] crosser_out_data; // crosser:out_data -> cmd_mux:sink0_data
wire [6:0] crosser_out_channel; // crosser:out_channel -> cmd_mux:sink0_channel
wire crosser_out_ready; // cmd_mux:sink0_ready -> crosser:out_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser_001:in_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [88:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser_001:in_data
wire [6:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser_001:in_channel
wire cmd_demux_src1_ready; // crosser_001:in_ready -> cmd_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [88:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink0_data
wire [6:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_mux_001:sink0_ready -> crosser_001:out_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> crosser_002:in_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> crosser_002:in_startofpacket
wire [88:0] rsp_demux_src0_data; // rsp_demux:src0_data -> crosser_002:in_data
wire [6:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> crosser_002:in_channel
wire rsp_demux_src0_ready; // crosser_002:in_ready -> rsp_demux:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink0_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink0_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink0_startofpacket
wire [88:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink0_data
wire [6:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink0_channel
wire crosser_002_out_ready; // rsp_mux:sink0_ready -> crosser_002:out_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_003:in_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_003:in_startofpacket
wire [88:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_003:in_data
wire [6:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_003:in_channel
wire rsp_demux_001_src0_ready; // crosser_003:in_ready -> rsp_demux_001:src0_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux:sink1_startofpacket
wire [88:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux:sink1_data
wire [6:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux:sink1_channel
wire crosser_003_out_ready; // rsp_mux:sink1_ready -> crosser_003:out_ready
wire [6:0] kernel_cntrl_m0_limiter_cmd_valid_data; // kernel_cntrl_m0_limiter:cmd_src_valid -> cmd_demux:sink_valid
altera_merlin_master_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) kernel_cntrl_m0_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (kernel_cntrl_m0_address), // avalon_anti_master_0.address
.av_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.av_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.av_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.av_read (kernel_cntrl_m0_read), // .read
.av_readdata (kernel_cntrl_m0_readdata), // .readdata
.av_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.av_write (kernel_cntrl_m0_write), // .write
.av_writedata (kernel_cntrl_m0_writedata), // .writedata
.av_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_windowed_slave_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_windowed_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.uav_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.av_address (address_span_extender_0_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_0_windowed_slave_write), // .write
.av_read (address_span_extender_0_windowed_slave_read), // .read
.av_readdata (address_span_extender_0_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_0_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_0_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_0_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_0_cntl_translator (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (address_span_extender_0_cntl_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.uav_read (address_span_extender_0_cntl_agent_m0_read), // .read
.uav_write (address_span_extender_0_cntl_agent_m0_write), // .write
.uav_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.uav_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.uav_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.uav_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.uav_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.av_write (address_span_extender_0_cntl_write), // avalon_anti_slave_0.write
.av_read (address_span_extender_0_cntl_read), // .read
.av_readdata (address_span_extender_0_cntl_readdata), // .readdata
.av_writedata (address_span_extender_0_cntl_writedata), // .writedata
.av_byteenable (address_span_extender_0_cntl_byteenable), // .byteenable
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (2),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sys_description_rom_s1_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sys_description_rom_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.uav_read (sys_description_rom_s1_agent_m0_read), // .read
.uav_write (sys_description_rom_s1_agent_m0_write), // .write
.uav_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.uav_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.uav_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.uav_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sys_description_rom_s1_address), // avalon_anti_slave_0.address
.av_write (sys_description_rom_s1_write), // .write
.av_readdata (sys_description_rom_s1_readdata), // .readdata
.av_writedata (sys_description_rom_s1_writedata), // .writedata
.av_byteenable (sys_description_rom_s1_byteenable), // .byteenable
.av_chipselect (sys_description_rom_s1_chipselect), // .chipselect
.av_clken (sys_description_rom_s1_clken), // .clken
.av_debugaccess (sys_description_rom_s1_debugaccess), // .debugaccess
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (64),
.UAV_DATA_W (64),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (8),
.UAV_BYTEENABLE_W (8),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (4),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (8),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sw_reset_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sw_reset_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.uav_read (sw_reset_s_agent_m0_read), // .read
.uav_write (sw_reset_s_agent_m0_write), // .write
.uav_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.uav_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.uav_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.uav_lock (sw_reset_s_agent_m0_lock), // .lock
.uav_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.av_write (sw_reset_s_write), // avalon_anti_slave_0.write
.av_read (sw_reset_s_read), // .read
.av_readdata (sw_reset_s_readdata), // .readdata
.av_writedata (sw_reset_s_writedata), // .writedata
.av_byteenable (sw_reset_s_byteenable), // .byteenable
.av_waitrequest (sw_reset_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) mem_org_mode_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (mem_org_mode_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.uav_read (mem_org_mode_s_agent_m0_read), // .read
.uav_write (mem_org_mode_s_agent_m0_write), // .write
.uav_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.uav_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.uav_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.uav_lock (mem_org_mode_s_agent_m0_lock), // .lock
.uav_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.av_write (mem_org_mode_s_write), // avalon_anti_slave_0.write
.av_read (mem_org_mode_s_read), // .read
.av_readdata (mem_org_mode_s_readdata), // .readdata
.av_writedata (mem_org_mode_s_writedata), // .writedata
.av_waitrequest (mem_org_mode_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) version_id_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (version_id_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.uav_read (version_id_0_s_agent_m0_read), // .read
.uav_write (version_id_0_s_agent_m0_write), // .write
.uav_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.uav_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.uav_lock (version_id_0_s_agent_m0_lock), // .lock
.uav_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.av_read (version_id_0_s_read), // avalon_anti_slave_0.read
.av_readdata (version_id_0_s_readdata), // .readdata
.av_address (), // (terminated)
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (14),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) irq_ena_0_s_translator (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (irq_ena_0_s_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.uav_read (irq_ena_0_s_agent_m0_read), // .read
.uav_write (irq_ena_0_s_agent_m0_write), // .write
.uav_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.uav_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.uav_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.uav_lock (irq_ena_0_s_agent_m0_lock), // .lock
.uav_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.av_write (irq_ena_0_s_write), // avalon_anti_slave_0.write
.av_read (irq_ena_0_s_read), // .read
.av_readdata (irq_ena_0_s_readdata), // .readdata
.av_writedata (irq_ena_0_s_writedata), // .writedata
.av_byteenable (irq_ena_0_s_byteenable), // .byteenable
.av_waitrequest (irq_ena_0_s_waitrequest), // .waitrequest
.av_address (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_BEGIN_BURST (68),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_TRANS_EXCLUSIVE (55),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_THREAD_ID_H (76),
.PKT_THREAD_ID_L (76),
.PKT_CACHE_H (83),
.PKT_CACHE_L (80),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (1),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) kernel_cntrl_m0_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (kernel_cntrl_m0_translator_avalon_universal_master_0_address), // av.address
.av_write (kernel_cntrl_m0_translator_avalon_universal_master_0_write), // .write
.av_read (kernel_cntrl_m0_translator_avalon_universal_master_0_read), // .read
.av_writedata (kernel_cntrl_m0_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (kernel_cntrl_m0_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (kernel_cntrl_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (kernel_cntrl_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (kernel_cntrl_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (kernel_cntrl_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (kernel_cntrl_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (kernel_cntrl_m0_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (kernel_cntrl_m0_agent_cp_valid), // cp.valid
.cp_data (kernel_cntrl_m0_agent_cp_data), // .data
.cp_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.cp_ready (kernel_cntrl_m0_agent_cp_ready), // .ready
.rp_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // rp.valid
.rp_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rp_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rp_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_windowed_slave_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_windowed_slave_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_windowed_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_windowed_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_windowed_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_windowed_slave_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_windowed_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_windowed_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_windowed_slave_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_windowed_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_windowed_slave_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_windowed_slave_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_windowed_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_windowed_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_windowed_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_windowed_slave_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_windowed_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) address_span_extender_0_cntl_agent (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (address_span_extender_0_cntl_agent_m0_address), // m0.address
.m0_burstcount (address_span_extender_0_cntl_agent_m0_burstcount), // .burstcount
.m0_byteenable (address_span_extender_0_cntl_agent_m0_byteenable), // .byteenable
.m0_debugaccess (address_span_extender_0_cntl_agent_m0_debugaccess), // .debugaccess
.m0_lock (address_span_extender_0_cntl_agent_m0_lock), // .lock
.m0_readdata (address_span_extender_0_cntl_agent_m0_readdata), // .readdata
.m0_readdatavalid (address_span_extender_0_cntl_agent_m0_readdatavalid), // .readdatavalid
.m0_read (address_span_extender_0_cntl_agent_m0_read), // .read
.m0_waitrequest (address_span_extender_0_cntl_agent_m0_waitrequest), // .waitrequest
.m0_writedata (address_span_extender_0_cntl_agent_m0_writedata), // .writedata
.m0_write (address_span_extender_0_cntl_agent_m0_write), // .write
.rp_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (address_span_extender_0_cntl_agent_rp_ready), // .ready
.rp_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.rp_data (address_span_extender_0_cntl_agent_rp_data), // .data
.rp_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.cp_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.cp_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.cp_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // .data
.rf_source_ready (address_span_extender_0_cntl_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.rf_source_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (address_span_extender_0_cntl_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rsp_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rf_source_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rf_source_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rf_source_ready), // .ready
.in_startofpacket (address_span_extender_0_cntl_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (address_span_extender_0_cntl_agent_rf_source_endofpacket), // .endofpacket
.out_data (address_span_extender_0_cntl_agent_rsp_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rsp_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (address_span_extender_0_cntl_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (66),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) address_span_extender_0_cntl_agent_rdata_fifo (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (address_span_extender_0_cntl_agent_rdata_fifo_src_data), // in.data
.in_valid (address_span_extender_0_cntl_agent_rdata_fifo_src_valid), // .valid
.in_ready (address_span_extender_0_cntl_agent_rdata_fifo_src_ready), // .ready
.out_data (address_span_extender_0_cntl_agent_rdata_fifo_out_data), // out.data
.out_valid (address_span_extender_0_cntl_agent_rdata_fifo_out_valid), // .valid
.out_ready (address_span_extender_0_cntl_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sys_description_rom_s1_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sys_description_rom_s1_agent_m0_address), // m0.address
.m0_burstcount (sys_description_rom_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sys_description_rom_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sys_description_rom_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sys_description_rom_s1_agent_m0_lock), // .lock
.m0_readdata (sys_description_rom_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sys_description_rom_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sys_description_rom_s1_agent_m0_read), // .read
.m0_waitrequest (sys_description_rom_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sys_description_rom_s1_agent_m0_writedata), // .writedata
.m0_write (sys_description_rom_s1_agent_m0_write), // .write
.rp_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sys_description_rom_s1_agent_rp_ready), // .ready
.rp_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.rp_data (sys_description_rom_s1_agent_rp_data), // .data
.rp_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.cp_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sys_description_rom_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sys_description_rom_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sys_description_rom_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sys_description_rom_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sys_description_rom_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sys_description_rom_s1_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sys_description_rom_s1_agent_rf_source_data), // in.data
.in_valid (sys_description_rom_s1_agent_rf_source_valid), // .valid
.in_ready (sys_description_rom_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sys_description_rom_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sys_description_rom_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sys_description_rom_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sys_description_rom_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sys_description_rom_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sys_description_rom_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sys_description_rom_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (63),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (104),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (71),
.PKT_BYTEEN_L (64),
.PKT_ADDR_H (85),
.PKT_ADDR_L (72),
.PKT_TRANS_COMPRESSED_READ (86),
.PKT_TRANS_POSTED (87),
.PKT_TRANS_WRITE (88),
.PKT_TRANS_READ (89),
.PKT_TRANS_LOCK (90),
.PKT_SRC_ID_H (108),
.PKT_SRC_ID_L (106),
.PKT_DEST_ID_H (111),
.PKT_DEST_ID_L (109),
.PKT_BURSTWRAP_H (96),
.PKT_BURSTWRAP_L (96),
.PKT_BYTE_CNT_H (95),
.PKT_BYTE_CNT_L (92),
.PKT_PROTECTION_H (115),
.PKT_PROTECTION_L (113),
.PKT_RESPONSE_STATUS_H (121),
.PKT_RESPONSE_STATUS_L (120),
.PKT_BURST_SIZE_H (99),
.PKT_BURST_SIZE_L (97),
.PKT_ORI_BURST_SIZE_L (122),
.PKT_ORI_BURST_SIZE_H (124),
.ST_CHANNEL_W (7),
.ST_DATA_W (125),
.AVS_BURSTCOUNT_W (4),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sw_reset_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sw_reset_s_agent_m0_address), // m0.address
.m0_burstcount (sw_reset_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (sw_reset_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sw_reset_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (sw_reset_s_agent_m0_lock), // .lock
.m0_readdata (sw_reset_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (sw_reset_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sw_reset_s_agent_m0_read), // .read
.m0_waitrequest (sw_reset_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sw_reset_s_agent_m0_writedata), // .writedata
.m0_write (sw_reset_s_agent_m0_write), // .write
.rp_endofpacket (sw_reset_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sw_reset_s_agent_rp_ready), // .ready
.rp_valid (sw_reset_s_agent_rp_valid), // .valid
.rp_data (sw_reset_s_agent_rp_data), // .data
.rp_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (sw_reset_s_cmd_width_adapter_src_ready), // cp.ready
.cp_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.cp_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.cp_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.cp_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // .endofpacket
.cp_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.rf_sink_ready (sw_reset_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sw_reset_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sw_reset_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sw_reset_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sw_reset_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sw_reset_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sw_reset_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sw_reset_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (126),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sw_reset_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sw_reset_s_agent_rf_source_data), // in.data
.in_valid (sw_reset_s_agent_rf_source_valid), // .valid
.in_ready (sw_reset_s_agent_rf_source_ready), // .ready
.in_startofpacket (sw_reset_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sw_reset_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (sw_reset_s_agent_rsp_fifo_out_data), // out.data
.out_valid (sw_reset_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (sw_reset_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sw_reset_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sw_reset_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) mem_org_mode_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (mem_org_mode_s_agent_m0_address), // m0.address
.m0_burstcount (mem_org_mode_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (mem_org_mode_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (mem_org_mode_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (mem_org_mode_s_agent_m0_lock), // .lock
.m0_readdata (mem_org_mode_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (mem_org_mode_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (mem_org_mode_s_agent_m0_read), // .read
.m0_waitrequest (mem_org_mode_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (mem_org_mode_s_agent_m0_writedata), // .writedata
.m0_write (mem_org_mode_s_agent_m0_write), // .write
.rp_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (mem_org_mode_s_agent_rp_ready), // .ready
.rp_valid (mem_org_mode_s_agent_rp_valid), // .valid
.rp_data (mem_org_mode_s_agent_rp_data), // .data
.rp_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (mem_org_mode_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (mem_org_mode_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (mem_org_mode_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (mem_org_mode_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (mem_org_mode_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (mem_org_mode_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) mem_org_mode_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (mem_org_mode_s_agent_rf_source_data), // in.data
.in_valid (mem_org_mode_s_agent_rf_source_valid), // .valid
.in_ready (mem_org_mode_s_agent_rf_source_ready), // .ready
.in_startofpacket (mem_org_mode_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (mem_org_mode_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (mem_org_mode_s_agent_rsp_fifo_out_data), // out.data
.out_valid (mem_org_mode_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (mem_org_mode_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (mem_org_mode_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (mem_org_mode_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) version_id_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (version_id_0_s_agent_m0_address), // m0.address
.m0_burstcount (version_id_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (version_id_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (version_id_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (version_id_0_s_agent_m0_lock), // .lock
.m0_readdata (version_id_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (version_id_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (version_id_0_s_agent_m0_read), // .read
.m0_waitrequest (version_id_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (version_id_0_s_agent_m0_writedata), // .writedata
.m0_write (version_id_0_s_agent_m0_write), // .write
.rp_endofpacket (version_id_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (version_id_0_s_agent_rp_ready), // .ready
.rp_valid (version_id_0_s_agent_rp_valid), // .valid
.rp_data (version_id_0_s_agent_rp_data), // .data
.rp_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (version_id_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (version_id_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (version_id_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (version_id_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (version_id_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (version_id_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (version_id_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (version_id_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) version_id_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (version_id_0_s_agent_rf_source_data), // in.data
.in_valid (version_id_0_s_agent_rf_source_valid), // .valid
.in_ready (version_id_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (version_id_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (version_id_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (version_id_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (version_id_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (version_id_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (version_id_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (version_id_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (68),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (49),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (50),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.PKT_TRANS_READ (53),
.PKT_TRANS_LOCK (54),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (60),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_PROTECTION_H (79),
.PKT_PROTECTION_L (77),
.PKT_RESPONSE_STATUS_H (85),
.PKT_RESPONSE_STATUS_L (84),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_ORI_BURST_SIZE_L (86),
.PKT_ORI_BURST_SIZE_H (88),
.ST_CHANNEL_W (7),
.ST_DATA_W (89),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) irq_ena_0_s_agent (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (irq_ena_0_s_agent_m0_address), // m0.address
.m0_burstcount (irq_ena_0_s_agent_m0_burstcount), // .burstcount
.m0_byteenable (irq_ena_0_s_agent_m0_byteenable), // .byteenable
.m0_debugaccess (irq_ena_0_s_agent_m0_debugaccess), // .debugaccess
.m0_lock (irq_ena_0_s_agent_m0_lock), // .lock
.m0_readdata (irq_ena_0_s_agent_m0_readdata), // .readdata
.m0_readdatavalid (irq_ena_0_s_agent_m0_readdatavalid), // .readdatavalid
.m0_read (irq_ena_0_s_agent_m0_read), // .read
.m0_waitrequest (irq_ena_0_s_agent_m0_waitrequest), // .waitrequest
.m0_writedata (irq_ena_0_s_agent_m0_writedata), // .writedata
.m0_write (irq_ena_0_s_agent_m0_write), // .write
.rp_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (irq_ena_0_s_agent_rp_ready), // .ready
.rp_valid (irq_ena_0_s_agent_rp_valid), // .valid
.rp_data (irq_ena_0_s_agent_rp_data), // .data
.rp_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (irq_ena_0_s_agent_rsp_fifo_out_data), // .data
.rf_source_ready (irq_ena_0_s_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.rf_source_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (irq_ena_0_s_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (irq_ena_0_s_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (irq_ena_0_s_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (irq_ena_0_s_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (90),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) irq_ena_0_s_agent_rsp_fifo (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (irq_ena_0_s_agent_rf_source_data), // in.data
.in_valid (irq_ena_0_s_agent_rf_source_valid), // .valid
.in_ready (irq_ena_0_s_agent_rf_source_ready), // .ready
.in_startofpacket (irq_ena_0_s_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (irq_ena_0_s_agent_rf_source_endofpacket), // .endofpacket
.out_data (irq_ena_0_s_agent_rsp_fifo_out_data), // out.data
.out_valid (irq_ena_0_s_agent_rsp_fifo_out_valid), // .valid
.out_ready (irq_ena_0_s_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (irq_ena_0_s_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (irq_ena_0_s_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router router (
.sink_ready (kernel_cntrl_m0_agent_cp_ready), // sink.ready
.sink_valid (kernel_cntrl_m0_agent_cp_valid), // .valid
.sink_data (kernel_cntrl_m0_agent_cp_data), // .data
.sink_startofpacket (kernel_cntrl_m0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_agent_cp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_001 router_001 (
.sink_ready (address_span_extender_0_windowed_slave_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_windowed_slave_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_windowed_slave_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_windowed_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_windowed_slave_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_002 router_002 (
.sink_ready (address_span_extender_0_cntl_agent_rp_ready), // sink.ready
.sink_valid (address_span_extender_0_cntl_agent_rp_valid), // .valid
.sink_data (address_span_extender_0_cntl_agent_rp_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_agent_rp_endofpacket), // .endofpacket
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_003 (
.sink_ready (sys_description_rom_s1_agent_rp_ready), // sink.ready
.sink_valid (sys_description_rom_s1_agent_rp_valid), // .valid
.sink_data (sys_description_rom_s1_agent_rp_data), // .data
.sink_startofpacket (sys_description_rom_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_003 router_004 (
.sink_ready (sw_reset_s_agent_rp_ready), // sink.ready
.sink_valid (sw_reset_s_agent_rp_valid), // .valid
.sink_data (sw_reset_s_agent_rp_data), // .data
.sink_startofpacket (sw_reset_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_005 (
.sink_ready (mem_org_mode_s_agent_rp_ready), // sink.ready
.sink_valid (mem_org_mode_s_agent_rp_valid), // .valid
.sink_data (mem_org_mode_s_agent_rp_data), // .data
.sink_startofpacket (mem_org_mode_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (mem_org_mode_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_006 (
.sink_ready (version_id_0_s_agent_rp_ready), // sink.ready
.sink_valid (version_id_0_s_agent_rp_valid), // .valid
.sink_data (version_id_0_s_agent_rp_data), // .data
.sink_startofpacket (version_id_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (version_id_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_router_005 router_007 (
.sink_ready (irq_ena_0_s_agent_rp_ready), // sink.ready
.sink_valid (irq_ena_0_s_agent_rp_valid), // .valid
.sink_data (irq_ena_0_s_agent_rp_data), // .data
.sink_startofpacket (irq_ena_0_s_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (irq_ena_0_s_agent_rp_endofpacket), // .endofpacket
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (75),
.PKT_DEST_ID_L (73),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (70),
.PKT_TRANS_POSTED (51),
.PKT_TRANS_WRITE (52),
.MAX_OUTSTANDING_RESPONSES (5),
.PIPELINED (0),
.ST_DATA_W (89),
.ST_CHANNEL_W (7),
.VALID_WIDTH (7),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (59),
.PKT_BYTE_CNT_L (56),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) kernel_cntrl_m0_limiter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.cmd_src_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (kernel_cntrl_m0_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (kernel_cntrl_m0_limiter_rsp_src_valid), // .valid
.rsp_src_data (kernel_cntrl_m0_limiter_rsp_src_data), // .data
.rsp_src_channel (kernel_cntrl_m0_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (kernel_cntrl_m0_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (kernel_cntrl_m0_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (kernel_cntrl_m0_limiter_cmd_valid_data) // cmd_valid.data
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_demux cmd_demux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (kernel_cntrl_m0_limiter_cmd_src_ready), // sink.ready
.sink_channel (kernel_cntrl_m0_limiter_cmd_src_channel), // .channel
.sink_data (kernel_cntrl_m0_limiter_cmd_src_data), // .data
.sink_startofpacket (kernel_cntrl_m0_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (kernel_cntrl_m0_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (kernel_cntrl_m0_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux cmd_mux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_cmd_mux_002 cmd_mux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_src6_valid), // .valid
.sink0_channel (cmd_demux_src6_channel), // .channel
.sink0_data (cmd_demux_src6_data), // .data
.sink0_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src6_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux rsp_demux_001 (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.sink_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.sink_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_002 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.sink_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_003 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (sw_reset_s_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.sink_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.sink_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_004 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_005 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_demux_002 rsp_demux_006 (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1_rsp_mux rsp_mux (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_002_out_ready), // sink0.ready
.sink0_valid (crosser_002_out_valid), // .valid
.sink0_channel (crosser_002_out_channel), // .channel
.sink0_data (crosser_002_out_data), // .data
.sink0_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_cmd_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_001_src_valid), // sink.valid
.in_channel (cmd_mux_001_src_channel), // .channel
.in_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_001_src_ready), // .ready
.in_data (cmd_mux_001_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_cmd_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_cmd_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_cmd_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (sys_description_rom_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_cmd_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (49),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (59),
.IN_PKT_BYTE_CNT_L (56),
.IN_PKT_TRANS_COMPRESSED_READ (50),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (60),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (85),
.IN_PKT_RESPONSE_STATUS_L (84),
.IN_PKT_TRANS_EXCLUSIVE (55),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (86),
.IN_PKT_ORI_BURST_SIZE_H (88),
.IN_ST_DATA_W (89),
.OUT_PKT_ADDR_H (85),
.OUT_PKT_ADDR_L (72),
.OUT_PKT_DATA_H (63),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (71),
.OUT_PKT_BYTEEN_L (64),
.OUT_PKT_BYTE_CNT_H (95),
.OUT_PKT_BYTE_CNT_L (92),
.OUT_PKT_TRANS_COMPRESSED_READ (86),
.OUT_PKT_BURST_SIZE_H (99),
.OUT_PKT_BURST_SIZE_L (97),
.OUT_PKT_RESPONSE_STATUS_H (121),
.OUT_PKT_RESPONSE_STATUS_L (120),
.OUT_PKT_TRANS_EXCLUSIVE (91),
.OUT_PKT_BURST_TYPE_H (101),
.OUT_PKT_BURST_TYPE_L (100),
.OUT_PKT_ORI_BURST_SIZE_L (122),
.OUT_PKT_ORI_BURST_SIZE_H (124),
.OUT_ST_DATA_W (125),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_cmd_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_003_src_valid), // sink.valid
.in_channel (cmd_mux_003_src_channel), // .channel
.in_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_003_src_ready), // .ready
.in_data (cmd_mux_003_src_data), // .data
.out_endofpacket (sw_reset_s_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_cmd_width_adapter_src_data), // .data
.out_channel (sw_reset_s_cmd_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_cmd_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) address_span_extender_0_cntl_rsp_width_adapter (
.clk (kernel_clk_out_clk_clk), // clk.clk
.reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (address_span_extender_0_cntl_rsp_width_adapter_src_data), // .data
.out_channel (address_span_extender_0_cntl_rsp_width_adapter_src_channel), // .channel
.out_valid (address_span_extender_0_cntl_rsp_width_adapter_src_valid), // .valid
.out_ready (address_span_extender_0_cntl_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (address_span_extender_0_cntl_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sys_description_rom_s1_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_003_src_valid), // sink.valid
.in_channel (router_003_src_channel), // .channel
.in_startofpacket (router_003_src_startofpacket), // .startofpacket
.in_endofpacket (router_003_src_endofpacket), // .endofpacket
.in_ready (router_003_src_ready), // .ready
.in_data (router_003_src_data), // .data
.out_endofpacket (sys_description_rom_s1_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sys_description_rom_s1_rsp_width_adapter_src_data), // .data
.out_channel (sys_description_rom_s1_rsp_width_adapter_src_channel), // .channel
.out_valid (sys_description_rom_s1_rsp_width_adapter_src_valid), // .valid
.out_ready (sys_description_rom_s1_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sys_description_rom_s1_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (85),
.IN_PKT_ADDR_L (72),
.IN_PKT_DATA_H (63),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (71),
.IN_PKT_BYTEEN_L (64),
.IN_PKT_BYTE_CNT_H (95),
.IN_PKT_BYTE_CNT_L (92),
.IN_PKT_TRANS_COMPRESSED_READ (86),
.IN_PKT_BURSTWRAP_H (96),
.IN_PKT_BURSTWRAP_L (96),
.IN_PKT_BURST_SIZE_H (99),
.IN_PKT_BURST_SIZE_L (97),
.IN_PKT_RESPONSE_STATUS_H (121),
.IN_PKT_RESPONSE_STATUS_L (120),
.IN_PKT_TRANS_EXCLUSIVE (91),
.IN_PKT_BURST_TYPE_H (101),
.IN_PKT_BURST_TYPE_L (100),
.IN_PKT_ORI_BURST_SIZE_L (122),
.IN_PKT_ORI_BURST_SIZE_H (124),
.IN_ST_DATA_W (125),
.OUT_PKT_ADDR_H (49),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (59),
.OUT_PKT_BYTE_CNT_L (56),
.OUT_PKT_TRANS_COMPRESSED_READ (50),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (85),
.OUT_PKT_RESPONSE_STATUS_L (84),
.OUT_PKT_TRANS_EXCLUSIVE (55),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (86),
.OUT_PKT_ORI_BURST_SIZE_H (88),
.OUT_ST_DATA_W (89),
.ST_CHANNEL_W (7),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sw_reset_s_rsp_width_adapter (
.clk (clk_reset_clk_clk), // clk.clk
.reset (sw_reset_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (sw_reset_s_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sw_reset_s_rsp_width_adapter_src_data), // .data
.out_channel (sw_reset_s_rsp_width_adapter_src_channel), // .channel
.out_valid (sw_reset_s_rsp_width_adapter_src_valid), // .valid
.out_ready (sw_reset_s_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sw_reset_s_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src0_ready), // in.ready
.in_valid (cmd_demux_src0_valid), // .valid
.in_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_demux_src0_channel), // .channel
.in_data (cmd_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_reset_clk_clk), // in_clk.clk
.in_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (kernel_clk_out_clk_clk), // out_clk.clk
.out_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_src0_ready), // in.ready
.in_valid (rsp_demux_src0_valid), // .valid
.in_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_src0_channel), // .channel
.in_data (rsp_demux_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (89),
.BITS_PER_SYMBOL (89),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (7),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (kernel_clk_out_clk_clk), // in_clk.clk
.in_reset (address_span_extender_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_reset_clk_clk), // out_clk.clk
.out_reset (kernel_cntrl_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:26:17 03/17/2015
// Design Name:
// Module Name: alt_ctl
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alt_ctl(op,func,aluc
);
input [5:0] op,func;
output reg [4:0] aluc;
always @*
begin
case(op)
6'b000000 : begin //R type
case(func)//Same op, distinguished by function code. 17 instructions
6'b100000 : aluc = 0; //add
6'b100010 : aluc = 1; //sub
6'b100100 : aluc = 2; //and
6'b100101 : aluc = 3; //or
6'b100110 : aluc = 4; //xor
6'b101010 : aluc = 5; //slt
6'b000000 : aluc = 6; //sll
6'b000100 : aluc = 7; //sllv
6'b000011 : aluc = 8; //sra
6'b000111 : aluc = 9; //srav
6'b000010 : aluc = 10; //srl
6'b000110 : aluc = 11; //srlv
6'b000001 : aluc = 12; //slc?
6'b000010 : aluc = 13; //slcv?
6'b100111 : aluc = 14; //nor
default : aluc = 0;
endcase
end // I type
6'b001000 : aluc = 0; //addi
6'b001100 : aluc = 2; //andi
6'b001101 : aluc = 3; //ori
6'b001010 : aluc = 5; //slti
6'b001111 : aluc = 13;//lui
default : aluc = 0;
endcase
end
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ulight_fifo_data_read_en_rx (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
`timescale 1 ps / 1 ps
module IPE_PPS(
input clk,
input reset,
input [5:0] in_fpgaac_channel_num,
input in_fpgaac_cpuid_cs,//switch cpuid allocate mode 0:round robin 1:port bind
input [31:0] cpuid_valid,//lxj20131224
input in_inputctrl_pkt_wr,
input [133:0] in_inputctrl_pkt,
input in_inputctrl_valid_wr,
input in_inputctrl_valid,
output out_inputctrl_pkt_almostfull,
output out_rdma_pkt_wr,
output [133:0] out_rdma_pkt,
output out_rdma_valid_wr,
output out_rdma_valid,
input in_rdma_pkt_almostfull,
input in_tdma_pkt_wr,
input [133:0] in_tdma_pkt,
input in_tdma_valid_wr,
input in_tdma_valid,
output out_tdma_pkt_almostfull,
output out_outputctrl_pkt_wr,
output [133:0] out_outputctrl_pkt,
output out_outputctrl_valid_wr,
output out_outputctrl_valid,
input in_outputctrl_pkt_almostfull
);
EGRESS EGRESS(
.clk(clk),
.reset(reset),
.in_tdma_pkt_wr(in_tdma_pkt_wr),
.in_tdma_pkt(in_tdma_pkt),
.in_tdma_valid_wr(in_tdma_valid_wr),
.in_tdma_valid(in_tdma_valid),
.out_tdma_pkt_almostfull(out_tdma_pkt_almostfull),
.out_outputctrl_pkt_wr(out_outputctrl_pkt_wr),
.out_outputctrl_pkt(out_outputctrl_pkt),
.out_outputctrl_valid_wr(out_outputctrl_valid_wr),
.out_outputctrl_valid(out_outputctrl_valid),
.in_outputctrl_pkt_almostfull(in_outputctrl_pkt_almostfull)
);
wire in_ingress_key_wr;
wire [133:0] in_ingress_key;
wire out_ingress_key_almostfull;
wire in_ingress_valid_wr;
wire in_ingress_valid;
wire out_offset_key_wr;
wire [133:0] out_offset_key;
wire out_offset_valid;
wire out_offset_valid_wr;
wire in_offset_key_almostfull;
CLASSIFY CLASSIFY(
.clk(clk),
.reset(reset),
.in_ingress_key_wr(in_ingress_key_wr),
.in_ingress_key(in_ingress_key),
.out_ingress_key_almostfull(out_ingress_key_almostfull),
.in_ingress_valid_wr(in_ingress_valid_wr),
.in_ingress_valid(in_ingress_valid),
.out_offset_key_wr(out_offset_key_wr),
.out_offset_key(out_offset_key),
.out_offset_valid(out_offset_valid),
.out_offset_valid_wr(out_offset_valid_wr),
.in_offset_key_almostfull(in_offset_key_almostfull)
);
wire out_dispather_pkt_wr;
wire [133:0] out_dispather_pkt;
wire out_dispather_valid_wr;
wire out_dispather_valid;
wire in_dispather_pkt_almostfull;
INGRESS INGRESS(
.clk(clk),
.reset(reset),
.in_inputctrl_pkt_wr(in_inputctrl_pkt_wr),
.in_inputctrl_pkt(in_inputctrl_pkt),
.in_inputctrl_valid_wr(in_inputctrl_valid_wr),
.in_inputctrl_valid(in_inputctrl_valid),
.out_inputctrl_pkt_almostfull(out_inputctrl_pkt_almostfull),
.out_class_key_wr(in_ingress_key_wr),
.out_class_key(in_ingress_key),
.in_class_key_almostfull(out_ingress_key_almostfull),
.out_class_valid(in_ingress_valid),
.out_class_valid_wr(in_ingress_valid_wr),
.in_class_key_wr(out_offset_key_wr),
.in_class_key(out_offset_key),
.in_class_valid_wr(out_offset_valid_wr),
.in_class_valid(out_offset_valid),
.out_class_key_almostfull(in_offset_key_almostfull),
.out_dispather_pkt_wr(out_dispather_pkt_wr),
.out_dispather_pkt(out_dispather_pkt),
.out_dispather_valid_wr(out_dispather_valid_wr),
.out_dispather_valid(out_dispather_valid),
.in_dispather_pkt_almostfull(in_dispather_pkt_almostfull)
);
wire in_ppc_pkt_wr;
wire [133:0] in_ppc_pkt;
wire in_ppc_valid_wr;
wire in_ppc_valid;
wire out_ppc_pkt_almostfull;
/*wire out_ppc_pkt_wr;
wire [133:0] out_ppc_pkt;
wire out_ppc_valid_wr;
wire out_ppc_valid;
wire in_ppc_pkt_almostfull;*/
DISPATHER DISPATHER(
.clk(clk),
.reset(reset),
.in_fpgaac_channel_num(in_fpgaac_channel_num),
.in_fpgaac_cpuid_cs(in_fpgaac_cpuid_cs),
.cpuid_valid(cpuid_valid),
.in_ingress_pkt_wr(out_dispather_pkt_wr),
.in_ingress_pkt(out_dispather_pkt),
.in_ingress_valid_wr(out_dispather_valid_wr),
.in_ingress_valid(out_dispather_valid),
.out_ingress_pkt_almostfull(in_dispather_pkt_almostfull),
.out_rdma_pkt_wr(out_rdma_pkt_wr),
.out_rdma_pkt(out_rdma_pkt),
.out_rdma_valid_wr(out_rdma_valid_wr),
.out_rdma_valid(out_rdma_valid),
.in_rdma_pkt_almostfull(in_rdma_pkt_almostfull),
.in_ppc_pkt_wr(in_ppc_pkt_wr),
.in_ppc_pkt(in_ppc_pkt),
.in_ppc_valid_wr(in_ppc_valid_wr),
.in_ppc_valid(in_ppc_valid),
.out_ppc_pkt_almostfull(out_ppc_pkt_almostfull),
.out_ppc_pkt_wr(in_ppc_pkt_wr),
.out_ppc_pkt(in_ppc_pkt),
.out_ppc_valid_wr(in_ppc_valid_wr),
.out_ppc_valid(in_ppc_valid),
.in_ppc_pkt_almostfull(out_ppc_pkt_almostfull)
);
endmodule |
// *******************************************************************************************************
// ** **
// ** 24FC512.v - Microchip 24FC512 512K-BIT I2C SERIAL EEPROM (VCC = +1.7V TO +5.5V) **
// ** **
// *******************************************************************************************************
// ** **
// ** This information is distributed under license from Young Engineering. **
// ** COPYRIGHT (c) 2009 YOUNG ENGINEERING **
// ** ALL RIGHTS RESERVED **
// ** **
// ** **
// ** Young Engineering provides design expertise for the digital world **
// ** Started in 1990, Young Engineering offers products and services for your electronic design **
// ** project. We have the expertise in PCB, FPGA, ASIC, firmware, and software design. **
// ** From concept to prototype to production, we can help you. **
// ** **
// ** http://www.young-engineering.com/ **
// ** **
// *******************************************************************************************************
// ** This information is provided to you for your convenience and use with Microchip products only. **
// ** Microchip disclaims all liability arising from this information and its use. **
// ** **
// ** THIS INFORMATION IS PROVIDED "AS IS." MICROCHIP MAKES NO REPRESENTATION OR WARRANTIES OF **
// ** ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO **
// ** THE INFORMATION PROVIDED TO YOU, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, **
// ** PERFORMANCE, MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR PURPOSE. **
// ** MICROCHIP IS NOT LIABLE, UNDER ANY CIRCUMSTANCES, FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL **
// ** DAMAGES, FOR ANY REASON WHATSOEVER. **
// ** **
// ** It is your responsibility to ensure that your application meets with your specifications. **
// ** **
// *******************************************************************************************************
// ** Revision : 1.0 **
// ** Modified Date : 02/04/2009 **
// ** Revision History: **
// ** **
// ** 02/04/2009: Initial design **
// ** **
// *******************************************************************************************************
// ** TABLE OF CONTENTS **
// *******************************************************************************************************
// **---------------------------------------------------------------------------------------------------**
// ** DECLARATIONS **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** INITIALIZATION **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** CORE LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 1.01: START Bit Detection **
// ** 1.02: STOP Bit Detection **
// ** 1.03: Input Shift Register **
// ** 1.04: Input Bit Counter **
// ** 1.05: Control Byte Register **
// ** 1.06: Byte Address Register **
// ** 1.07: Write Data Buffer **
// ** 1.08: Acknowledge Generator **
// ** 1.09: Acknowledge Detect **
// ** 1.10: Write Cycle Timer **
// ** 1.11: Write Cycle Processor **
// ** 1.12: Read Data Multiplexor **
// ** 1.13: Read Data Processor **
// ** 1.14: SDA Data I/O Buffer **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** DEBUG LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 2.01: Memory Data Bytes **
// ** 2.02: Write Data Buffer **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** TIMING CHECKS **
// **---------------------------------------------------------------------------------------------------**
// ** **
// *******************************************************************************************************
`timescale 1ns/10ps
module M24FC512 (A0, A1, A2, WP, SDA, SCL, RESET);
input A0; // chip select bit
input A1; // chip select bit
input A2; // chip select bit
input WP; // write protect pin
inout SDA; // serial data I/O
input SCL; // serial data clock
input RESET; // system reset
// *******************************************************************************************************
// ** DECLARATIONS **
// *******************************************************************************************************
reg SDA_DO; // serial data - output
reg SDA_OE; // serial data - output enable
wire SDA_DriveEnable; // serial data output enable
reg SDA_DriveEnableDlyd; // serial data output enable - delayed
wire [02:00] ChipAddress; // hardwired chip address
reg [03:00] BitCounter; // serial bit counter
reg START_Rcvd; // START bit received flag
reg STOP_Rcvd; // STOP bit received flag
reg CTRL_Rcvd; // control byte received flag
reg ADHI_Rcvd; // byte address hi received flag
reg ADLO_Rcvd; // byte address lo received flag
reg MACK_Rcvd; // master acknowledge received flag
reg WrCycle; // memory write cycle
reg RdCycle; // memory read cycle
reg [07:00] ShiftRegister; // input data shift register
reg [07:00] ControlByte; // control byte register
wire RdWrBit; // read/write control bit
reg [15:00] StartAddress; // memory access starting address
reg [06:00] PageAddress; // memory page address
reg [07:00] WrDataByte [0:127]; // memory write data buffer
wire [07:00] RdDataByte; // memory read data
reg [15:00] WrCounter; // write buffer counter
reg [06:00] WrPointer; // write buffer pointer
reg [15:00] RdPointer; // read address pointer
reg WriteActive; // memory write cycle active
reg [07:00] MemoryBlock [0:65535]; // EEPROM data memory array
integer LoopIndex; // iterative loop index
integer tAA; // timing parameter
integer tWC; // timing parameter
// *******************************************************************************************************
// ** INITIALIZATION **
// *******************************************************************************************************
initial begin
`ifdef VCC_1_7V_TO_2_5V
tAA = 900; // SCL to SDA output delay
tWC = 5000000; // memory write cycle time
`else
`ifdef VCC_2_5V_TO_5_5V
tAA = 400; // SCL to SDA output delay
tWC = 5000000; // memory write cycle time
`else
tAA = 400; // SCL to SDA output delay
tWC = 5000000; // memory write cycle time
`endif
`endif
end
initial begin
SDA_DO = 0;
SDA_OE = 0;
end
initial begin
START_Rcvd = 0;
STOP_Rcvd = 0;
CTRL_Rcvd = 0;
ADHI_Rcvd = 0;
ADLO_Rcvd = 0;
MACK_Rcvd = 0;
end
initial begin
BitCounter = 0;
ControlByte = 0;
end
initial begin
WrCycle = 0;
RdCycle = 0;
WriteActive = 0;
end
assign ChipAddress = {A2,A1,A0};
// *******************************************************************************************************
// ** CORE LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 1.01: START Bit Detection
// -------------------------------------------------------------------------------------------------------
always @(negedge SDA) begin
if (SCL == 1) begin
START_Rcvd <= 1;
STOP_Rcvd <= 0;
CTRL_Rcvd <= 0;
ADHI_Rcvd <= 0;
ADLO_Rcvd <= 0;
MACK_Rcvd <= 0;
WrCycle <= #1 0;
RdCycle <= #1 0;
BitCounter <= 0;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.02: STOP Bit Detection
// -------------------------------------------------------------------------------------------------------
always @(posedge SDA) begin
if (SCL == 1) begin
START_Rcvd <= 0;
STOP_Rcvd <= 1;
CTRL_Rcvd <= 0;
ADHI_Rcvd <= 0;
ADLO_Rcvd <= 0;
MACK_Rcvd <= 0;
WrCycle <= #1 0;
RdCycle <= #1 0;
BitCounter <= 10;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.03: Input Shift Register
// -------------------------------------------------------------------------------------------------------
always @(posedge SCL) begin
ShiftRegister[00] <= SDA;
ShiftRegister[01] <= ShiftRegister[00];
ShiftRegister[02] <= ShiftRegister[01];
ShiftRegister[03] <= ShiftRegister[02];
ShiftRegister[04] <= ShiftRegister[03];
ShiftRegister[05] <= ShiftRegister[04];
ShiftRegister[06] <= ShiftRegister[05];
ShiftRegister[07] <= ShiftRegister[06];
end
// -------------------------------------------------------------------------------------------------------
// 1.04: Input Bit Counter
// -------------------------------------------------------------------------------------------------------
always @(posedge SCL) begin
if (BitCounter < 10) BitCounter <= BitCounter + 1;
end
// -------------------------------------------------------------------------------------------------------
// 1.05: Control Byte Register
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (START_Rcvd & (BitCounter == 8)) begin
if (!WriteActive & (ShiftRegister[07:01] == {4'b1010,ChipAddress[02:00]})) begin
if (ShiftRegister[00] == 0) WrCycle <= 1;
if (ShiftRegister[00] == 1) RdCycle <= 1;
ControlByte <= ShiftRegister[07:00];
CTRL_Rcvd <= 1;
end
START_Rcvd <= 0;
end
end
assign RdWrBit = ControlByte[00];
// -------------------------------------------------------------------------------------------------------
// 1.06: Byte Address Register
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (CTRL_Rcvd & (BitCounter == 8)) begin
if (RdWrBit == 0) begin
StartAddress[15:08] <= ShiftRegister[07:00];
RdPointer[15:08] <= ShiftRegister[07:00];
ADHI_Rcvd <= 1;
end
WrCounter <= 0;
WrPointer <= 0;
CTRL_Rcvd <= 0;
end
end
always @(negedge SCL) begin
if (ADHI_Rcvd & (BitCounter == 8)) begin
if (RdWrBit == 0) begin
StartAddress[07:00] <= ShiftRegister[07:00];
RdPointer[07:00] <= ShiftRegister[07:00];
ADLO_Rcvd <= 1;
end
WrCounter <= 0;
WrPointer <= 0;
ADHI_Rcvd <= 0;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.07: Write Data Buffer
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (ADLO_Rcvd & (BitCounter == 8)) begin
if (RdWrBit == 0) begin
WrDataByte[WrPointer] <= ShiftRegister[07:00];
WrCounter <= WrCounter + 1;
WrPointer <= WrPointer + 1;
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.08: Acknowledge Generator
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (!WriteActive) begin
if (BitCounter == 8) begin
if (WrCycle | (START_Rcvd & (ShiftRegister[07:01] == {4'b1010,ChipAddress[02:00]}))) begin
SDA_DO <= 0;
SDA_OE <= 1;
end
end
if (BitCounter == 9) begin
BitCounter <= 0;
if (!RdCycle) begin
SDA_DO <= 0;
SDA_OE <= 0;
end
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.09: Acknowledge Detect
// -------------------------------------------------------------------------------------------------------
always @(posedge SCL) begin
if (RdCycle & (BitCounter == 8)) begin
if ((SDA == 0) & (SDA_OE == 0)) MACK_Rcvd <= 1;
end
end
always @(negedge SCL) MACK_Rcvd <= 0;
// -------------------------------------------------------------------------------------------------------
// 1.10: Write Cycle Timer
// -------------------------------------------------------------------------------------------------------
always @(posedge STOP_Rcvd) begin
if (WrCycle & (WP == 0) & (WrCounter > 0)) begin
WriteActive = 1;
#(tWC);
WriteActive = 0;
end
end
always @(posedge STOP_Rcvd) begin
#(1.0);
STOP_Rcvd = 0;
end
// -------------------------------------------------------------------------------------------------------
// 1.11: Write Cycle Processor
// -------------------------------------------------------------------------------------------------------
always @(negedge WriteActive) begin
for (LoopIndex = 0; LoopIndex < WrCounter; LoopIndex = LoopIndex + 1) begin
PageAddress = StartAddress[06:00] + LoopIndex;
MemoryBlock[{StartAddress[15:07],PageAddress[06:00]}] = WrDataByte[LoopIndex[06:00]];
end
end
// -------------------------------------------------------------------------------------------------------
// 1.12: Read Data Multiplexor
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (BitCounter == 8) begin
if (WrCycle & ADLO_Rcvd) begin
RdPointer <= StartAddress + WrPointer + 1;
end
if (RdCycle) begin
RdPointer <= RdPointer + 1;
end
end
end
assign RdDataByte = MemoryBlock[RdPointer[15:00]];
// -------------------------------------------------------------------------------------------------------
// 1.13: Read Data Processor
// -------------------------------------------------------------------------------------------------------
always @(negedge SCL) begin
if (RdCycle) begin
if (BitCounter == 8) begin
SDA_DO <= 0;
SDA_OE <= 0;
end
else if (BitCounter == 9) begin
SDA_DO <= RdDataByte[07];
if (MACK_Rcvd) SDA_OE <= 1;
end
else begin
SDA_DO <= RdDataByte[7-BitCounter];
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.14: SDA Data I/O Buffer
// -------------------------------------------------------------------------------------------------------
bufif1 (SDA, 1'b0, SDA_DriveEnableDlyd);
assign SDA_DriveEnable = !SDA_DO & SDA_OE;
always @(SDA_DriveEnable) SDA_DriveEnableDlyd <= #(tAA) SDA_DriveEnable;
// *******************************************************************************************************
// ** DEBUG LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 2.01: Memory Data Bytes
// -------------------------------------------------------------------------------------------------------
wire [07:00] MemoryByte_000 = MemoryBlock[00];
wire [07:00] MemoryByte_001 = MemoryBlock[01];
wire [07:00] MemoryByte_002 = MemoryBlock[02];
wire [07:00] MemoryByte_003 = MemoryBlock[03];
wire [07:00] MemoryByte_004 = MemoryBlock[04];
wire [07:00] MemoryByte_005 = MemoryBlock[05];
wire [07:00] MemoryByte_006 = MemoryBlock[06];
wire [07:00] MemoryByte_007 = MemoryBlock[07];
wire [07:00] MemoryByte_008 = MemoryBlock[08];
wire [07:00] MemoryByte_009 = MemoryBlock[09];
wire [07:00] MemoryByte_00A = MemoryBlock[10];
wire [07:00] MemoryByte_00B = MemoryBlock[11];
wire [07:00] MemoryByte_00C = MemoryBlock[12];
wire [07:00] MemoryByte_00D = MemoryBlock[13];
wire [07:00] MemoryByte_00E = MemoryBlock[14];
wire [07:00] MemoryByte_00F = MemoryBlock[15];
// -------------------------------------------------------------------------------------------------------
// 2.02: Write Data Buffer
// -------------------------------------------------------------------------------------------------------
wire [07:00] WriteData_00 = WrDataByte[00];
wire [07:00] WriteData_01 = WrDataByte[01];
wire [07:00] WriteData_02 = WrDataByte[02];
wire [07:00] WriteData_03 = WrDataByte[03];
wire [07:00] WriteData_04 = WrDataByte[04];
wire [07:00] WriteData_05 = WrDataByte[05];
wire [07:00] WriteData_06 = WrDataByte[06];
wire [07:00] WriteData_07 = WrDataByte[07];
wire [07:00] WriteData_08 = WrDataByte[08];
wire [07:00] WriteData_09 = WrDataByte[09];
wire [07:00] WriteData_0A = WrDataByte[10];
wire [07:00] WriteData_0B = WrDataByte[11];
wire [07:00] WriteData_0C = WrDataByte[12];
wire [07:00] WriteData_0D = WrDataByte[13];
wire [07:00] WriteData_0E = WrDataByte[14];
wire [07:00] WriteData_0F = WrDataByte[15];
wire [07:00] WriteData_10 = WrDataByte[16];
wire [07:00] WriteData_11 = WrDataByte[17];
wire [07:00] WriteData_12 = WrDataByte[18];
wire [07:00] WriteData_13 = WrDataByte[19];
wire [07:00] WriteData_14 = WrDataByte[20];
wire [07:00] WriteData_15 = WrDataByte[21];
wire [07:00] WriteData_16 = WrDataByte[22];
wire [07:00] WriteData_17 = WrDataByte[23];
wire [07:00] WriteData_18 = WrDataByte[24];
wire [07:00] WriteData_19 = WrDataByte[25];
wire [07:00] WriteData_1A = WrDataByte[26];
wire [07:00] WriteData_1B = WrDataByte[27];
wire [07:00] WriteData_1C = WrDataByte[28];
wire [07:00] WriteData_1D = WrDataByte[29];
wire [07:00] WriteData_1E = WrDataByte[30];
wire [07:00] WriteData_1F = WrDataByte[31];
wire [07:00] WriteData_20 = WrDataByte[32];
wire [07:00] WriteData_21 = WrDataByte[33];
wire [07:00] WriteData_22 = WrDataByte[34];
wire [07:00] WriteData_23 = WrDataByte[35];
wire [07:00] WriteData_24 = WrDataByte[36];
wire [07:00] WriteData_25 = WrDataByte[37];
wire [07:00] WriteData_26 = WrDataByte[38];
wire [07:00] WriteData_27 = WrDataByte[39];
wire [07:00] WriteData_28 = WrDataByte[40];
wire [07:00] WriteData_29 = WrDataByte[41];
wire [07:00] WriteData_2A = WrDataByte[42];
wire [07:00] WriteData_2B = WrDataByte[43];
wire [07:00] WriteData_2C = WrDataByte[44];
wire [07:00] WriteData_2D = WrDataByte[45];
wire [07:00] WriteData_2E = WrDataByte[46];
wire [07:00] WriteData_2F = WrDataByte[47];
wire [07:00] WriteData_30 = WrDataByte[48];
wire [07:00] WriteData_31 = WrDataByte[49];
wire [07:00] WriteData_32 = WrDataByte[50];
wire [07:00] WriteData_33 = WrDataByte[51];
wire [07:00] WriteData_34 = WrDataByte[52];
wire [07:00] WriteData_35 = WrDataByte[53];
wire [07:00] WriteData_36 = WrDataByte[54];
wire [07:00] WriteData_37 = WrDataByte[55];
wire [07:00] WriteData_38 = WrDataByte[56];
wire [07:00] WriteData_39 = WrDataByte[57];
wire [07:00] WriteData_3A = WrDataByte[58];
wire [07:00] WriteData_3B = WrDataByte[59];
wire [07:00] WriteData_3C = WrDataByte[60];
wire [07:00] WriteData_3D = WrDataByte[61];
wire [07:00] WriteData_3E = WrDataByte[62];
wire [07:00] WriteData_3F = WrDataByte[63];
wire [07:00] WriteData_40 = WrDataByte[64];
wire [07:00] WriteData_41 = WrDataByte[65];
wire [07:00] WriteData_42 = WrDataByte[66];
wire [07:00] WriteData_43 = WrDataByte[67];
wire [07:00] WriteData_44 = WrDataByte[68];
wire [07:00] WriteData_45 = WrDataByte[69];
wire [07:00] WriteData_46 = WrDataByte[70];
wire [07:00] WriteData_47 = WrDataByte[71];
wire [07:00] WriteData_48 = WrDataByte[72];
wire [07:00] WriteData_49 = WrDataByte[73];
wire [07:00] WriteData_4A = WrDataByte[74];
wire [07:00] WriteData_4B = WrDataByte[75];
wire [07:00] WriteData_4C = WrDataByte[76];
wire [07:00] WriteData_4D = WrDataByte[77];
wire [07:00] WriteData_4E = WrDataByte[78];
wire [07:00] WriteData_4F = WrDataByte[79];
wire [07:00] WriteData_50 = WrDataByte[80];
wire [07:00] WriteData_51 = WrDataByte[81];
wire [07:00] WriteData_52 = WrDataByte[82];
wire [07:00] WriteData_53 = WrDataByte[83];
wire [07:00] WriteData_54 = WrDataByte[84];
wire [07:00] WriteData_55 = WrDataByte[85];
wire [07:00] WriteData_56 = WrDataByte[86];
wire [07:00] WriteData_57 = WrDataByte[87];
wire [07:00] WriteData_58 = WrDataByte[88];
wire [07:00] WriteData_59 = WrDataByte[89];
wire [07:00] WriteData_5A = WrDataByte[90];
wire [07:00] WriteData_5B = WrDataByte[91];
wire [07:00] WriteData_5C = WrDataByte[92];
wire [07:00] WriteData_5D = WrDataByte[93];
wire [07:00] WriteData_5E = WrDataByte[94];
wire [07:00] WriteData_5F = WrDataByte[95];
wire [07:00] WriteData_60 = WrDataByte[96];
wire [07:00] WriteData_61 = WrDataByte[97];
wire [07:00] WriteData_62 = WrDataByte[98];
wire [07:00] WriteData_63 = WrDataByte[99];
wire [07:00] WriteData_64 = WrDataByte[100];
wire [07:00] WriteData_65 = WrDataByte[101];
wire [07:00] WriteData_66 = WrDataByte[102];
wire [07:00] WriteData_67 = WrDataByte[103];
wire [07:00] WriteData_68 = WrDataByte[104];
wire [07:00] WriteData_69 = WrDataByte[105];
wire [07:00] WriteData_6A = WrDataByte[106];
wire [07:00] WriteData_6B = WrDataByte[107];
wire [07:00] WriteData_6C = WrDataByte[108];
wire [07:00] WriteData_6D = WrDataByte[109];
wire [07:00] WriteData_6E = WrDataByte[110];
wire [07:00] WriteData_6F = WrDataByte[111];
wire [07:00] WriteData_70 = WrDataByte[112];
wire [07:00] WriteData_71 = WrDataByte[113];
wire [07:00] WriteData_72 = WrDataByte[114];
wire [07:00] WriteData_73 = WrDataByte[115];
wire [07:00] WriteData_74 = WrDataByte[116];
wire [07:00] WriteData_75 = WrDataByte[117];
wire [07:00] WriteData_76 = WrDataByte[118];
wire [07:00] WriteData_77 = WrDataByte[119];
wire [07:00] WriteData_78 = WrDataByte[120];
wire [07:00] WriteData_79 = WrDataByte[121];
wire [07:00] WriteData_7A = WrDataByte[122];
wire [07:00] WriteData_7B = WrDataByte[123];
wire [07:00] WriteData_7C = WrDataByte[124];
wire [07:00] WriteData_7D = WrDataByte[125];
wire [07:00] WriteData_7E = WrDataByte[126];
wire [07:00] WriteData_7F = WrDataByte[127];
// *******************************************************************************************************
// ** TIMING CHECKS **
// *******************************************************************************************************
wire TimingCheckEnable = (RESET == 0) & (SDA_OE == 0);
wire tstSTOP = STOP_Rcvd;
specify
`ifdef VCC_1_7V_TO_2_5V
specparam
tHI = 600, // SCL pulse width - high
tLO = 1300, // SCL pulse width - low
tSU_STA = 600, // SCL to SDA setup time
tHD_STA = 600, // SCL to SDA hold time
tSU_DAT = 100, // SDA to SCL setup time
tSU_STO = 600, // SCL to SDA setup time
tSU_WP = 600, // WP to SDA setup time
tHD_WP = 1300, // WP to SDA hold time
tBUF = 1300; // Bus free time
`else
`ifdef VCC_2_5V_TO_5_5V
specparam
tHI = 500, // SCL pulse width - high
tLO = 500, // SCL pulse width - low
tSU_STA = 250, // SCL to SDA setup time
tHD_STA = 250, // SCL to SDA hold time
tSU_DAT = 100, // SDA to SCL setup time
tSU_STO = 250, // SCL to SDA setup time
tSU_WP = 600, // WP to SDA setup time
tHD_WP = 1300, // WP to SDA hold time
tBUF = 500; // Bus free time
`else
specparam
tHI = 500, // SCL pulse width - high
tLO = 500, // SCL pulse width - low
tSU_STA = 250, // SCL to SDA setup time
tHD_STA = 250, // SCL to SDA hold time
tSU_DAT = 100, // SDA to SCL setup time
tSU_STO = 250, // SCL to SDA setup time
tSU_WP = 600, // WP to SDA setup time
tHD_WP = 1300, // WP to SDA hold time
tBUF = 500; // Bus free time
`endif
`endif
$width (posedge SCL, tHI);
$width (negedge SCL, tLO);
$width (posedge SDA &&& SCL, tBUF);
$setup (posedge SCL, negedge SDA &&& TimingCheckEnable, tSU_STA);
$setup (SDA, posedge SCL &&& TimingCheckEnable, tSU_DAT);
$setup (posedge SCL, posedge SDA &&& TimingCheckEnable, tSU_STO);
$setup (WP, posedge tstSTOP &&& TimingCheckEnable, tSU_WP);
$hold (negedge SDA &&& TimingCheckEnable, negedge SCL, tHD_STA);
$hold (posedge tstSTOP &&& TimingCheckEnable, WP, tHD_WP);
endspecify
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_FUNCTIONAL_V
`define SKY130_FD_SC_LS__O21AI_FUNCTIONAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVPWRVGND_BLACKBOX_V
`define SKY130_FD_SC_LP__TAPVPWRVGND_BLACKBOX_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVPWRVGND_BLACKBOX_V
|
/* Simple external interrupt controller for MIPSfpga+ system
* managed using AHB-Lite bus
* Copyright(c) 2017 Stanislav Zhelnio
* https://github.com/zhelnio/ahb_lite_eic
*/
module priority_encoder255
(
input [ 255 : 0 ] in,
output reg detect,
output reg [ 7 : 0 ] out
);
wire [3:0] detectL;
wire [5:0] preoutL [3:0];
wire [1:0] preoutM;
//1st order entries
priority_encoder64 e10( in[ 63:0 ], detectL[0], preoutL[0] );
priority_encoder64 e11( in[ 127:64 ], detectL[1], preoutL[1] );
priority_encoder64 e12( in[ 191:128 ], detectL[2], preoutL[2] );
priority_encoder64 e13( in[ 255:192 ], detectL[3], preoutL[3] );
always @ (*)
casez(detectL)
default : {detect, out} = 9'b0;
4'b0001 : {detect, out} = { 3'b100, preoutL[0] };
4'b001? : {detect, out} = { 3'b101, preoutL[1] };
4'b01?? : {detect, out} = { 3'b110, preoutL[2] };
4'b1??? : {detect, out} = { 3'b111, preoutL[3] };
endcase
endmodule
module priority_encoder64
(
input [ 63 : 0 ] in,
output detect,
output [ 5 : 0 ] out
);
wire [7:0] detectL;
wire [2:0] preoutL [7:0];
wire [2:0] preoutM;
//3rd order entries
priority_encoder8 e30( in[ 7:0 ], detectL[0], preoutL[0] );
priority_encoder8 e31( in[ 15:8 ], detectL[1], preoutL[1] );
priority_encoder8 e32( in[ 23:16 ], detectL[2], preoutL[2] );
priority_encoder8 e33( in[ 31:24 ], detectL[3], preoutL[3] );
priority_encoder8 e34( in[ 39:32 ], detectL[4], preoutL[4] );
priority_encoder8 e35( in[ 47:40 ], detectL[5], preoutL[5] );
priority_encoder8 e36( in[ 55:48 ], detectL[6], preoutL[6] );
priority_encoder8 e37( in[ 63:56 ], detectL[7], preoutL[7] );
//2nd order entry
priority_encoder8 e20(detectL, detect, preoutM);
assign out = detect ? { preoutM, preoutL[preoutM] } : 6'b0;
endmodule
module priority_encoder8
(
input [ 7 : 0 ] in,
output reg detect,
output reg [ 2 : 0 ] out
);
always @ (*)
casez(in)
default : {detect, out} = 4'b0000;
8'b00000001 : {detect, out} = 4'b1000;
8'b0000001? : {detect, out} = 4'b1001;
8'b000001?? : {detect, out} = 4'b1010;
8'b00001??? : {detect, out} = 4'b1011;
8'b0001???? : {detect, out} = 4'b1100;
8'b001????? : {detect, out} = 4'b1101;
8'b01?????? : {detect, out} = 4'b1110;
8'b1??????? : {detect, out} = 4'b1111;
endcase
endmodule |
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_dma_write_tb;
parameter VCD_FILE = {`__FILE__,"cd"};
`include "tb_base.v"
reg req_valid = 1'b1;
wire req_ready;
reg [23:0] req_length = 'h03;
wire awvalid;
wire awready;
wire [31:0] awaddr;
wire [7:0] awlen;
wire [2:0] awsize;
wire [1:0] awburst;
wire [2:0] awprot;
wire [3:0] awcache;
wire wlast;
wire wvalid;
wire wready;
wire [3:0] wstrb;
wire [31:0] wdata;
reg [31:0] fifo_wr_din = 'b0;
reg fifo_wr_rq = 'b0;
wire fifo_wr_xfer_req;
wire bready;
wire bvalid;
wire [1:0] bresp;
always @(posedge clk) begin
if (reset != 1'b1 && req_ready == 1'b1) begin
req_valid <= 1'b1;
req_length <= req_length + 'h4;
end
end
axi_write_slave #(
.DATA_WIDTH(32)
) i_write_slave (
.clk(clk),
.reset(reset),
.awvalid(awvalid),
.awready(awready),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awprot(awprot),
.awcache(awcache),
.wready(wready),
.wvalid(wvalid),
.wdata(wdata),
.wstrb(wstrb),
.wlast(wlast),
.bvalid(bvalid),
.bready(bready),
.bresp(bresp)
);
axi_dmac_transfer #(
.DMA_DATA_WIDTH_SRC(32),
.DMA_DATA_WIDTH_DEST(32)
) i_transfer (
.m_dest_axi_aclk (clk),
.m_dest_axi_aresetn(resetn),
.m_axi_awvalid(awvalid),
.m_axi_awready(awready),
.m_axi_awaddr(awaddr),
.m_axi_awlen(awlen),
.m_axi_awsize(awsize),
.m_axi_awburst(awburst),
.m_axi_awprot(awprot),
.m_axi_awcache(awcache),
.m_axi_wready(wready),
.m_axi_wvalid(wvalid),
.m_axi_wdata(wdata),
.m_axi_wstrb(wstrb),
.m_axi_wlast(wlast),
.m_axi_bvalid(bvalid),
.m_axi_bready(bready),
.m_axi_bresp(bresp),
.ctrl_clk(clk),
.ctrl_resetn(resetn),
.ctrl_enable(1'b1),
.ctrl_pause(1'b0),
.req_eot(eot),
.req_response_ready(1'b1),
.req_valid(req_valid),
.req_ready(req_ready),
.req_dest_address(30'h7e09000),
.req_x_length(req_length),
.req_y_length(24'h00),
.req_dest_stride(24'h00),
.req_src_stride(24'h00),
.req_sync_transfer_start(1'b0),
.fifo_wr_clk(clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(1'b1),
.fifo_wr_xfer_req(fifo_wr_xfer_req)
);
always @(posedge clk) begin
if (reset) begin
fifo_wr_din <= 'b0;
fifo_wr_rq <= 'b0;
end else begin
if (fifo_wr_en) begin
fifo_wr_din <= fifo_wr_din + 'h4;
end
fifo_wr_rq <= (($random % 4) == 0);
end
end
assign fifo_wr_en = fifo_wr_rq & fifo_wr_xfer_req;
always @(posedge clk) begin
if (reset) begin
failed <= 'b0;
end else begin
failed <= failed |
i_write_slave.failed |
fifo_wr_overflow;
end
end
endmodule
|
/*
* Copyright 2020-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
(* whitebox *)
module FF(clk, D, S, R, E, Q);
input wire clk;
(* SETUP="clk 10e-12" *) (* NO_COMB *)
input wire D;
(* SETUP="clk 10e-12" *) (* NO_COMB *)
input wire E;
(* SETUP="clk 10e-12" *) (* NO_COMB *)
input wire S;
(* SETUP="clk 10e-12" *) (* NO_COMB *)
input wire R;
(* CLK_TO_Q = "clk 10e-12" *)
output reg Q;
always @(posedge clk or posedge S or posedge R) begin
if (S)
Q <= 1'b1;
else if (R)
Q <= 1'b0;
else if (E)
Q <= D;
end
endmodule
|
(*
Copyright 2014 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. If not, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export rules_useful.
Require Export sequents_useful.
(** printing |- $\vdash$ *)
(** printing -> $\rightarrow$ *)
(* begin hide *)
(* end hide *)
(**
We now prove the truth of several structural rules.
*)
(* [1] ============ THIN HYPS ============ *)
(**
The following rule says that we can always thin any tail of a list of hypotheses:
<<
H, J |- C ext t
By thinHyps ()
H |- C ext t
>>
*)
Definition rule_thin_hyps {o}
(H J : @barehypotheses o)
(C t : NTerm) :=
mk_rule
(mk_baresequent (H ++ J) (mk_concl C t))
[ mk_baresequent H (mk_concl C t) ]
[].
Lemma rule_thin_hyps_true {o} :
forall lib (H J : @barehypotheses o)
(C t : NTerm),
rule_true lib (rule_thin_hyps H J C t).
Proof.
intros.
unfold rule_thin_hyps, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
duplicate wfh as wfh'.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app.
destruct wfh as [ wfh wfj ].
generalize (hyps (mk_baresequent H (mk_concl C t)) (inl eq_refl));
intro hyp1; clear hyps.
destruct hyp1 as [ ws1 hyp1 ].
destseq; allsimpl.
proof_irr.
assert (closed_extract (H ++ J) (mk_concl C t)) as ws
by (wfseq; apply covered_app_weak_l; auto).
exists ws.
(* We prove some simple facts on our sequents *)
assert (covered C (vars_hyps H)
# covered t (nh_vars_hyps H)
# disjoint (free_vars C) (vars_hyps J)
# disjoint (free_vars t) (vars_hyps J)) as vhyps.
clear hyp1.
dwfseq; sp;
try (complete (rw fold_subset in ct;
apply subset_disjoint with (l3 := vars_hyps J) in ct; sp)).
try (complete (rw fold_subset in ce;
apply subset_disjoint with (l1 := nh_vars_hyps H) in wfj0; sp;
apply subset_disjoint with (l3 := vars_hyps J) in ce; sp)).
destruct vhyps as [ cch vhyps ].
destruct vhyps as [ cth vhyps ].
destruct vhyps as [ dcj dtj ].
(* done with proving these simple facts *)
(* we can now start proving that the rule is true *)
vr_seq_true.
vr_seq_true in hyp1.
allrw @similarity_app; exrepd; subst.
generalize (hyp1 s1a s2a); clear hyp1; intro hyp1.
autodimp hyp1 hyp.
intros s2 sim.
apply @hyps_functionality_init_seg with (s1b := s1b) (J := J) (s3 := s2b) in sim; auto.
autodimp hyp1 hyp; exrepd.
assert (disjoint (free_vars C) (dom_csub s1b)) as d1
by (allapply @similarity_dom; sp;
rterm (dom_csub s1b); rewrite vars_hyps_substitute_hyps; sp).
assert (disjoint (free_vars C) (dom_csub s2b)) as d2
by (allapply @similarity_dom; sp;
rterm (dom_csub s2b); rewrite vars_hyps_substitute_hyps; sp).
assert (disjoint (free_vars t) (dom_csub s1b)) as dt1
by (allapply @similarity_dom; sp;
rterm (dom_csub s1b); rewrite vars_hyps_substitute_hyps; sp).
assert (disjoint (free_vars t) (dom_csub s2b)) as dt2
by (allapply @similarity_dom; sp;
rterm (dom_csub s2b); rewrite vars_hyps_substitute_hyps; sp).
generalize (subset_free_vars_lsubstc_app_ex C s1a s1b wfct pC1 d1); intro; exrepd; clear_irr.
rewrite e0; clear e0.
generalize (subset_free_vars_lsubstc_app_ex C s2a s2b wfct pC2 d2); intro; exrepd; clear_irr.
rewrite e0; clear e0.
generalize (subset_free_vars_lsubstc_app_ex t s1a s1b wfce pt1 dt1); intro; exrepd; clear_irr.
rewrite e0; clear e0.
generalize (subset_free_vars_lsubstc_app_ex t s2a s2b wfce pt2 dt2); intro; exrepd; clear_irr.
rewrite e0; clear e0.
auto.
Qed.
(* begin hide *)
Lemma rule_thin_hyps_true_ex {o} :
forall lib (H : @bhyps o) J c t,
rule_true_if lib (rule_thin_hyps H J c t).
Proof.
intros.
generalize (rule_thin_hyps_true lib H J c t); intro rt.
rw <- @rule_true_eq_ex in rt.
unfold rule_true_ex in rt; sp.
Qed.
Lemma rule_thin_hyps_true2 {o} :
forall lib (H : @bhyps o) J c t,
rule_true2 lib (rule_thin_hyps H J c t).
Proof.
intros.
generalize (rule_thin_hyps_true lib H J c t); intro rt.
apply rule_true_iff_rule_true2; sp.
Qed.
Lemma rule_thin_hyps_wf {o} :
forall (H : @bhyps o) J c t,
covered c (vars_hyps H)
-> wf_rule (rule_thin_hyps H J c t).
Proof.
intros.
introv pwf m; allsimpl; repdors; subst; sp.
allunfold @pwf_sequent; wfseq; sp.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app; sp.
allapply @vswf_hypotheses_nil_if; sp.
Qed.
(* end hide *)
(* [2] ============ UNHIDE EQUALITY ============ *)
(**
The following rule says that we can always unhide an hypothesis if
the conclusion is an equality (in general this is true if the
conclusion has a trivial extract):
<<
H [x : A] J |- t1 = t2 in C
By equalityUnhide hyp(i) ()
H x : A J |- t1 = t2 in C
>>
*)
Definition rule_unhide_equality {o}
(H J : @barehypotheses o)
(A C t1 t2 : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent
(snoc H (mk_hhyp x A) ++ J)
(mk_conclax (mk_equality t1 t2 C)))
[ mk_baresequent
(snoc H (mk_hyp x A) ++ J)
(mk_conclax (mk_equality t1 t2 C)) ]
[].
Lemma rule_unhide_equality_true {o} :
forall (lib : library)
(H J : @barehypotheses o)
(A C t1 t2 : NTerm)
(x : NVar),
rule_true lib (rule_unhide_equality H J A C t1 t2 x).
Proof.
intros.
unfold rule_unhide_equality, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
(* We prove the well-formedness of things *)
destseq; allsimpl.
duplicate wfh as wfh'.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app; allrw @wf_hypotheses_snoc; allsimpl.
destruct wfh as [ wfh wfj ].
destruct wfh as [ ipa wfh ].
destruct wfh as [ nixh wfh ].
allrw @vars_hyps_snoc; allsimpl.
generalize (hyps (mk_baresequent (snoc H (mk_hyp x A) ++ J)
(mk_conclax (mk_equality t1 t2 C)))
(inl eq_refl));
clear hyps; allsimpl; intro hyp1.
destruct hyp1 as [ ws1 hyp1 ].
destseq; allsimpl; proof_irr.
exists (@covered_axiom o (nh_vars_hyps (snoc H (mk_hhyp x A) ++ J))).
(* We prove some simple facts on our sequents *)
assert (covered (mk_equality t1 t2 C) (snoc (vars_hyps H) x ++ vars_hyps J))
as vhyps.
clear hyp1.
dwfseq; sp.
allrw in_app_iff; allrw in_snoc; sp;
apply_in_hyp p; allrw in_app_iff; allrw in_snoc; sp.
(* done with proving these simple facts *)
(* we can now start proving that the rule is true *)
vr_seq_true.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
autodimp hyp1 hyp.
intros s3 sim3.
rw @similarity_hhyp in sim3; rw @eq_hyps_hhyp.
apply eqh; sp.
autodimp hyp1 hyp; exrepd; clear_irr; auto.
rw @similarity_hhyp; auto.
Qed.
(* begin hide *)
(* end hide *)
(* [4] ============ HYPOTHESIS EQUALITY ============ *)
(**
The following rule is the standard ``hypothesis'' rule:
<<
G, x : A, J |- x = x in A
By hypothesisEquality hyp(i) ()
no subgoals
>>
*)
Definition rule_hypothesis_equality {o}
(G J : @barehypotheses o)
(A : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent
(snoc G (mk_hyp x A) ++ J)
(mk_conclax (mk_equality (mk_var x) (mk_var x) A)))
[]
[].
Lemma rule_hypothesis_equality_true {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
rule_true lib (rule_hypothesis_equality G J A x).
Proof.
intros.
unfold rule_hypothesis_equality, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
duplicate wfh as wfh'.
allunfold @closed_type; allunfold @closed_extract; allsimpl.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app.
destruct wfh as [ wfh wfj ].
allrw @wf_hypotheses_snoc.
destruct wfh as [ ispvg wfh ].
destruct wfh as [ nixg wfg ].
allrw @nh_vars_hyps_snoc; allsimpl.
allrw @vars_hyps_snoc; allsimpl.
duplicate cg as ceq.
allrw @covered_equality.
destruct cg as [ cx ct ].
destruct ct as [ cx2 ca ]; GC.
allrw @vars_hyps_app; allsimpl.
allrw @vars_hyps_snoc; allsimpl.
duplicate wfct as wfct'.
rw <- @wf_equality_iff in wfct.
destruct wfct as [ wa wtt ].
destruct wtt as [ wb wtA ].
exists (@covered_axiom o (nh_vars_hyps (snoc G (mk_hyp x A) ++ J))).
(* We prove some simple facts on our sequents *)
assert (!LIn x (free_vars A)
# !LIn x (vars_hyps J)
# subset (free_vars A) (vars_hyps G)
# disjoint (free_vars A) (vars_hyps J)) as vhyps.
dwfseq.
sp;
try (complete (apply subset_disjoint with (l1 := free_vars A) in wfj2; auto;
apply subset_snoc_r; sp)).
destruct vhyps as [ nixa vhyps ].
destruct vhyps as [ nixj vhyps ].
destruct vhyps as [ sag daj ].
(* done with proving these simple facts *)
vr_seq_true.
lift_lsubst.
repeat (rewrite fold_mkc_member).
rewrite member_eq.
rw <- @member_member_iff.
rw @tequality_mkc_member.
applydup eqh in sim; clear eqh.
allrw @similarity_app; exrepd; subst; cpx.
allrw @similarity_snoc; exrepd; subst; cpx.
revert c1 cT c0 cT0; rewrite hvar_mk_hyp; intros.
allrw @eq_hyps_app; exrepd; simphyps; cpx.
apply app_split in e; repd; subst; allrewrite length_snoc; try omega; cpx; GC.
apply app_split in e0; repd; subst; allrewrite length_snoc; try omega; cpx; GC.
allrw @eq_hyps_snoc; exrepd; cpx; simphyps; cpx; GC; clear_irr.
assert (disjoint (free_vars (@mk_var o x)) (dom_csub s1b0)) as dxs1
by (simpl; rw disjoint_singleton_l;
allapply @similarity_dom; repd; rterm (dom_csub s1b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars (@mk_var o x)) (dom_csub s2b0)) as dxs2
by (simpl; rw disjoint_singleton_l;
allapply @similarity_dom; repd; rterm (dom_csub s2b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars A) (dom_csub s1b0)) as das1
by (allapply @similarity_dom; repd; rterm (dom_csub s1b0);
rewrite vars_hyps_substitute_hyps; auto).
assert (disjoint (free_vars A) (dom_csub s2b0)) as das2
by (allapply @similarity_dom; repd; rterm (dom_csub s2b0);
rewrite vars_hyps_substitute_hyps; auto).
generalize (subset_free_vars_lsubstc_app_ex
(mk_var x)
(snoc s1a (x, t0)) s1b0
w1 c1 dxs1); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
(mk_var x)
(snoc s2a (x, t3)) s2b0
w1 c0 dxs2); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
A
(snoc s1a (x, t0)) s1b0
wtA cT das1); intro; exrepd; rewrite e; clear e.
generalize (subset_free_vars_lsubstc_app_ex
A
(snoc s2a (x, t3)) s2b0
wtA cT0 das2); intro; exrepd; rewrite e; clear e.
lsubst_tac.
applydup @equality_refl in e3; sp.
split; sp; GC.
apply @tequality_preserving_equality with (A := lsubstc A wtA s1a p1); auto.
rewrite member_eq.
apply equality_sym in e3.
apply equality_refl in e3; sp.
Qed.
(* begin hide *)
(* end hide *)
(* [5] ============ INTRODUCTION ============ *)
(**
The following rule says that to prove a conclusion [C] one can
always provide an evidence [t] for that type and prove instead that
[t] is a member of [C]:
<<
H |- C ext t
By introduction t
H |- t = t in C
>>
*)
Definition rule_introduction {o}
(H : @barehypotheses o)
(C t : NTerm) :=
mk_rule
(mk_baresequent H (mk_concl C t))
[ mk_baresequent H (mk_conclax (mk_equality t t C)) ]
[ sarg_term t ].
Lemma rule_introduction_true {o} :
forall
lib
(H : @barehypotheses o)
(C t : NTerm),
rule_true lib (rule_introduction H C t).
Proof.
intros.
unfold rule_introduction, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
unfold args_constraints in cargs; allsimpl.
generalize (cargs (sarg_term t) (inl eq_refl)); clear cargs; intro arg1.
unfold arg_constraints in arg1.
(* We prove the well-formedness of things *)
destseq; allsimpl.
generalize (hyps (mk_baresequent H (mk_conclax (mk_equality t t C)))
(inl eq_refl));
simpl; intros hyp1; clear hyps.
destruct hyp1 as [ ws1 hyp1 ].
destseq; allsimpl; proof_irr; GC.
duplicate ct as ct1.
allrw @covered_equality.
destruct ct as [ cth ct ].
destruct ct as [ cth2 cch ]; GC.
assert (covered t (nh_vars_hyps H)) as ws by sp.
exists ws; GC.
vr_seq_true.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
autodimp hyp1 h.
autodimp hyp1 h.
exrepd.
lift_lsubst in t0; lift_lsubst in e; clear_irr.
rw @tequality_mkc_equality in t0; sp.
allrewrite @lsubstc_mk_axiom.
allrewrite @member_eq.
allrewrite @fold_mkc_member.
rw <- @member_member_iff in e.
spcast; apply @equality_respects_cequivc_right with (t2 := lsubstc t wfce s1 pt1); sp.
Qed.
(* begin hide *)
(* end hide *)
(* [6] ============ HYPOTHESIS ============ *)
(**
The following rule is another form of the standard ``hypothesis''
rule:
<<
G, x : A, J |- A ext x
By hypothsis hyp(i) ()
no subgoals
>>
*)
Definition rule_hypothesis {o}
(G J : @barehypotheses o)
(A : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent (snoc G (mk_hyp x A) ++ J) (mk_concl A (mk_var x)))
[]
[].
Lemma rule_hypothesis_true {o} :
forall lib (G J : @barehypotheses o)
(A : NTerm)
(x : NVar),
rule_true lib (rule_hypothesis G J A x).
Proof.
intros.
generalize (rule_introduction_true
lib
(snoc G (mk_hyp x A) ++ J)
A
(mk_var x)).
intro h.
rw <- @rule_true_eq_ex in h.
unfold rule_true_ex, rule_true_if in h; exrepd.
unfold rule_true; allsimpl; sp.
clear cargs hyps.
assert (closed_extract_baresequent
(mk_baresequent (snoc G (mk_hyp x A) ++ J) (mk_concl A (mk_var x))))
as ce by prove_seq.
exists ce; sp.
apply s; try (complete prove_seq).
sp; subst.
generalize (rule_hypothesis_equality_true lib G J A x).
intro h.
rw <- @rule_true_eq_ex in h.
unfold rule_true_ex, rule_true_if in h; exrepd.
apply s0; try (complete prove_seq).
Qed.
(* begin hide *)
(* end hide *)
(* [7] ============ THIN ============ *)
(**
The following rule says that one can always delete (or thin) an
hypothesis (as long as [J] does not depend on [x], because [H, J]
has to be well-formed):
<<
H, x : A, J |- C ext t
By thin hyp(i) ()
H, J |- C ext t
>>
*)
Definition rule_thin {o}
(G J : @barehypotheses o)
(A C t : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent (snoc G (mk_hyp x A) ++ J) (mk_concl C t))
[ mk_baresequent (G ++ J) (mk_concl C t) ]
[].
Lemma rule_thin_true {o} :
forall lib (G J : @barehypotheses o)
(A C t : NTerm)
(x : NVar),
rule_true lib (rule_thin G J A C t x).
Proof.
intros.
unfold rule_thin, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
duplicate wfh as wfh'.
allapply @vswf_hypotheses_nil_implies.
allrw @wf_hypotheses_app.
destruct wfh as [ wfh wfj ].
allrw @wf_hypotheses_snoc.
destruct wfh as [ ispvg wfh ].
destruct wfh as [ nixg wfg ].
allrw @vars_hyps_app; allsimpl.
allrw @vars_hyps_snoc; allsimpl; GC.
generalize (hyps (mk_baresequent (G ++ J) (mk_concl C t)) (inl (eq_refl)));
clear hyps; intro hyp1.
destruct hyp1 as [ ws1 hyp1 ].
destseq; allsimpl; proof_irr; GC.
assert (covered t (nh_vars_hyps (snoc G (mk_hyp x A) ++ J))) as ws
by (clear hyp1; prove_seq; apply covered_snoc_app_weak; auto).
exists ws; GC.
(* We prove some simple facts on our sequents *)
assert (! LIn x (free_vars C)
# ! LIn x (free_vars t)
# ! LIn x (vars_hyps J)
# ! LIn x (free_vars_hyps J)
# ! LIn x (hyps_free_vars J)) as vhyps.
clear hyp1.
dwfseq.
sp;
try (complete (apply ct in X; allrw in_app_iff; sp));
try (complete (apply ce in X; allrw in_app_iff; sp;
generalize (subvars_hs_vars_hyps G); intro sv1; allrw subvars_prop;
generalize (subvars_hs_vars_hyps J); intro sv2; allrw subvars_prop; sp));
try (complete (apply wfh in X; allrw in_app_iff; sp)).
destruct vhyps as [ nixc vhyps ].
destruct vhyps as [ nixt vhyps ].
destruct vhyps as [ nixj1 vhyps ].
destruct vhyps as [ nixj2 nixj3 ].
(* done with proving these simple facts *)
vr_seq_true.
rw @similarity_app in sim; exrepd; subst; cpx.
rw @similarity_snoc in s; exrepd; subst; allsimpl; cpx.
vr_seq_true in hyp1.
generalize (hyp1 (s1a0 ++ s1b) (s2a0 ++ s2b)); clear hyp1; intro hyp1.
autodimp hyp1 hyp.
intros s3 sim3.
rw @similarity_app in sim3; exrepnd; subst.
apply app_split in sim0; sp; subst;
try (complete (allapply @similarity_length; sp; omega)).
generalize (eqh (snoc s2a (x, t1) ++ s2b0)); intro h.
autodimp h hyp.
rw @similarity_app.
exists (snoc s1a (x, t1)) s1b0 (snoc s2a (x, t1)) s2b0; simpl; sp;
allrewrite length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a s2a t1 t1 w p; sp.
rewrite member_eq.
allapply @equality_refl; sp.
rewrite substitute_hyps_snoc_sub_weak; sp.
rw @eq_hyps_app in h; exrepnd.
apply app_split in h0; apply app_split in h2; sp; subst;
allrewrite length_snoc; sp;
try (complete (allapply @similarity_length; sp; omega)).
allrw @eq_hyps_snoc; exrepnd; allsimpl; cpx; GC.
rw @eq_hyps_app.
exists s1a0 s1b s2a1 s2b1; sp.
apply sub_eq_hyps_snoc_weak_iff in h1; sp.
clear_irr.
autodimp hyp1 hyp.
rw @similarity_app.
exists s1a0 s1b s2a0 s2b; sp.
rewrite substitute_hyps_snoc_sub_weak in s0; sp.
exrepd; clear_irr.
assert (lsubstc C wfct (snoc s1a0 (x, t1) ++ s1b) pC1
= lsubstc C wfct (s1a0 ++ s1b) pC0) as eq1;
try (rewrite eq1).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
assert (lsubstc C wfct (snoc s2a0 (x, t2) ++ s2b) pC2
= lsubstc C wfct (s2a0 ++ s2b) pC3) as eq2;
try (rewrite eq2).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
assert (lsubstc t wfce (snoc s1a0 (x, t1) ++ s1b) pt1
= lsubstc t wfce (s1a0 ++ s1b) pt0) as eq3;
try (rewrite eq3).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
assert (lsubstc t wfce (snoc s2a0 (x, t2) ++ s2b) pt2
= lsubstc t wfce (s2a0 ++ s2b) pt3) as eq4;
try (rewrite eq4).
apply lsubstc_eq_if_csubst; sp.
apply subset_free_vars_csub_snoc_app; sp.
sp.
Qed.
(* begin hide *)
(* end hide *)
(* [13] ============ WIDENING ============ *)
(**
The following rule state that if we are trying to prove a goal under
the assumption that [x] has type [T], then it suffices to prove the
goal under the hypothesis that [x] has type [U], as long as we can
prove that [T] is a subtype of [U], and [T] respects the equality of
[U] on the elements of [T]:
<<
H, x : T, J |- C ext t
By widening y z i
H, x : U, J |- C ext t
H, x : T, y : U, z : x = y in U |- x = y in T
H, x : T |- x in U
>>
*)
Definition rule_widening {o}
(T U C t : @NTerm o)
(x y z : NVar)
(i : nat)
(H J : barehypotheses) :=
mk_rule
(mk_baresequent
(snoc H (mk_hyp x T) ++ J)
(mk_concl C t))
[ mk_baresequent (snoc H (mk_hyp x U) ++ J)
(mk_concl C t),
mk_baresequent (snoc (snoc (snoc H (mk_hyp x T))
(mk_hyp y U))
(mk_hyp z (mk_equality (mk_var x) (mk_var y) U)))
(mk_conclax (mk_equality (mk_var x) (mk_var y) T)),
mk_baresequent (snoc H (mk_hyp x T))
(mk_conclax (mk_member (mk_var x) U))
]
[sarg_var y, sarg_var z].
Lemma rule_widening_true {o} :
forall lib (T U C t : NTerm)
(x y z : NVar)
(i : nat)
(H J : @barehypotheses o),
rule_true lib
(rule_widening
T U C t
x y z
i
H J).
Proof.
unfold rule_widening, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
clear cargs.
(* We prove the well-formedness of things *)
destseq; allsimpl.
generalize (hyps (mk_baresequent
(snoc H (mk_hyp x U) ++ J)
(mk_concl C t))
(inl eq_refl))
(hyps (mk_baresequent
(snoc (snoc (snoc H (mk_hyp x T)) (mk_hyp y U))
(mk_hyp z (mk_equality (mk_var x) (mk_var y) U)))
(mk_conclax (mk_equality (mk_var x) (mk_var y) T)))
(inr (inl eq_refl)))
(hyps (mk_baresequent
(snoc H (mk_hyp x T))
(mk_conclax (mk_member (mk_var x) U)))
(inr (inr (inl eq_refl))));
simpl; intros hyp1 hyp2 hyp3.
destruct hyp1 as [ ws1 hyp1 ].
destruct hyp2 as [ ws2 hyp2 ].
destruct hyp3 as [ ws3 hyp3 ].
destseq; allsimpl; proof_irr; GC.
clear hyps.
assert (covered t (nh_vars_hyps (snoc H (mk_hyp x T) ++ J)))
as co
by (duplicate ce1 as ce2;
allrw @nh_vars_hyps_app;
allrw @nh_vars_hyps_snoc;
allsimpl; sp).
exists co; GC.
(* We prove some simple facts on our sequents *)
assert (!LIn x (vars_hyps H)
# !LIn x (free_vars T)
# !LIn x (free_vars U)
# !(x = y)
# !LIn y (vars_hyps H)
# !LIn y (free_vars T)
# !LIn y (free_vars U)
# !LIn z (vars_hyps H)
# !LIn z (free_vars T)
# !LIn z (free_vars U)
# wf_term U
# covered T (vars_hyps H)
# covered U (vars_hyps H)) as vhyps.
clear hyp1 hyp2 hyp3.
dwfseq.
sp; try (complete (unfold covered; rw subvars_prop; sp)).
destruct vhyps as [ nixH vhyps ].
destruct vhyps as [ nixT vhyps ].
destruct vhyps as [ nixU vhyps ].
destruct vhyps as [ nixy vhyps ].
destruct vhyps as [ niyH vhyps ].
destruct vhyps as [ niyT vhyps ].
destruct vhyps as [ niyU vhyps ].
destruct vhyps as [ nizH vhyps ].
destruct vhyps as [ nizT vhyps ].
destruct vhyps as [ nizU vhyps ].
destruct vhyps as [ wfu vhyps ].
destruct vhyps as [ covTH covUH ].
(* done with proving these simple facts *)
(* we now start proving the sequent *)
vr_seq_true.
(* we split s1 and s2 *)
allrw @similarity_app; exrepd; subst; cpx.
allrw @similarity_snoc; exrepd; subst; cpx.
allsimpl.
(* we use our 1st subgoal to prove that tequality *)
vr_seq_true in hyp1.
generalize (hyp1 (snoc s1a0 (x, t1) ++ s1b)
(snoc s2a0 (x, t2) ++ s2b));
clear hyp1; intro hyp1.
autodimp hyp1 h.
introv sim.
allrw @similarity_app; exrepd; subst; allsimpl; cpx.
apply app_split in e; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
repeat (allrw @similarity_snoc; exrepd; subst; allsimpl; cpx; GC).
rw @eq_hyps_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t3)) s2b0;
allrw length_snoc; allrw; sp.
assert (cover_vars U s2a1)
as c2
by (apply @cover_vars_dom_csub_eq with (s1 := s1a); sp;
allrw @dom_csub_snoc; simpl;
allapply @similarity_dom; repd; allrw; sp).
rw @eq_hyps_snoc; simpl.
exists s1a s2a1 t0 t3 w0 p0 c2; sp.
generalize (eqh (snoc s2a1 (x, t2) ++ s2b)); intro imp.
autodimp imp hyp.
rw @similarity_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t2)) s2b; repeat (rw length_snoc); sp.
rw @similarity_snoc; simpl.
exists s1a s2a1 t0 t2 w p; sp.
rw @eq_hyps_app in imp; exrepnd.
apply app_split in imp0; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
apply app_split in imp2; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
rw @eq_hyps_snoc in imp5; exrepnd; sp; cpx.
generalize (eqh (snoc s2a1 (x, t2) ++ s2b)); intro imp.
autodimp imp hyp.
rw @similarity_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t2)) s2b; repeat (rw length_snoc); sp.
rw @similarity_snoc; simpl.
exists s1a s2a1 t0 t2 w p; sp.
rw @eq_hyps_app in imp; exrepnd.
apply app_split in imp0; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
apply app_split in imp2; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
rw @eq_hyps_snoc in imp5; exrepnd; sp; cpx; allsimpl; cpx; clear_irr.
(* from imp0 and sequent 3 *)
generalize (subtype_tequality lib s1a0 s2a H T U x t1 t4 w w0 p1 p0 c2 (wfh0, (wfct0, wfce1), (ct, ce)));
intro j; repeat (autodimp j hyp).
apply hyps_functionality_init_seg with (s3 := s2b1) in eqh; sp.
assert (cover_vars T s2a1)
as c2
by (apply @cover_vars_dom_csub_eq with (s1 := s1a); sp;
allrw @dom_csub_snoc; simpl;
allapply @similarity_dom; repd; allrw; sp).
generalize (eqh (snoc s2a1 (x, t3) ++ s2b0)); intro j; autodimp j hyp.
rw @similarity_app; simpl.
exists (snoc s1a (x, t0)) s1b0 (snoc s2a1 (x, t3)) s2b0; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
exists s1a s2a1 t0 t3 w p; sp.
generalize (strong_subtype_equality lib s1a s2a1 t0 t2 t3 T U w w0 p p0 c2 H x y z
(wfh0, (wfct0, wfce1), (ct, ce))
(wfh1, (wfct1, wfce1), (ct0, ce0)));
intro q; repeat (destimp q hyp).
repnd.
apply hyps_functionality_init_seg with (s3 := s2b) in eqh; sp.
apply @equality_commutes4 with (U := lsubstc T w s2a1 c2) (a2 := t0) (a3 := t2); sp.
rw @eq_hyps_app in j; exrepnd.
apply app_split in j0; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
apply app_split in j2; exrepd; allrw length_snoc; try (complete (allrw; sp)); subst; cpx.
(* we're done proving the hyps_functionality part for sequent 1 *)
(* we now have to prove the similarity part *)
autodimp hyp1 h.
rw @similarity_app; simpl.
exists (snoc s1a0 (x, t1)) s1b (snoc s2a0 (x, t2)) s2b; allrw length_snoc; sp.
rw @similarity_snoc; simpl.
assert (cover_vars U s1a0)
as c1 by (allrw @cover_vars_covered; allapply @similarity_dom; exrepnd; allrw; sp).
exists s1a0 s2a0 t1 t2 wfu c1; sp.
generalize (subtype_equality lib t1 t2 T U s1a0 s2a0 w wfu p c1 H x
(wfh0, (wfct0, wfce1), (ct, ce)));
intro j; repeat (autodimp j hyp).
apply hyps_functionality_init_seg with (s3 := s2b) in eqh; sp.
exrepnd; clear_irr; sp.
Qed.
(* begin hide *)
(* end hide *)
(* [18] ============ CUT ============ *)
(**
The following rule is the standard cut rule:
<<
H |- C ext t[x\u]
By cut x B
H |- B ext u
H, x : B |- C ext t
>>
*)
Definition rule_cut {o}
(H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent H (mk_concl C (subst t x u)))
[ mk_baresequent H (mk_concl B u),
mk_baresequent (snoc H (mk_hyp x B)) (mk_concl C t)
]
[sarg_var x].
Lemma rule_cut_true {o} :
forall
lib
(H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar)
(bc : disjoint (free_vars u) (bound_vars t)),
rule_true lib (rule_cut H B C t u x).
Proof.
unfold rule_cut, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
(* We prove the well-formedness of things *)
destseq; allsimpl.
generalize (hyps (mk_baresequent H (mk_concl B u))
(inl eq_refl))
(hyps (mk_baresequent (snoc H (mk_hyp x B)) (mk_concl C t))
(inr (inl eq_refl)));
simpl; intros hyp1 hyp2; clear hyps.
destruct hyp1 as [ ws1 hyp1 ].
destruct hyp2 as [ ws2 hyp2 ].
destseq; allsimpl; clear_irr; GC.
assert (covered (subst t x u) (vars_hyps (filter is_nh H))) as cv.
clear hyp1 hyp2.
dwfseq.
introv i.
generalize (eqvars_free_vars_disjoint t [(x,u)]); intro eqv.
rw eqvars_prop in eqv.
rw @fold_subst in eqv.
rw eqv in i.
rw in_app_iff in i; rw in_remove_nvars in i; allsimpl; sp.
apply not_over_or in p; sp.
apply ce in p0.
apply in_snoc in p0; sp.
allapply @in_sub_free_vars; sp.
destruct (memvar x (free_vars t)); allsimpl; sp; cpx.
exists cv.
(* We prove some simple facts on our sequents *)
assert (! LIn x (free_vars B)
/\ ! LIn x (free_vars C)
/\ ! LIn x (free_vars u)
/\ ! LIn x (vars_hyps H)
/\ wf_term u
/\ wf_term B
/\ covered u (nh_vars_hyps H)
/\ covered B (vars_hyps H)) as vhyps.
clear hyp1 hyp2.
dwfseq.
sp;
try (complete (generalize (ce0 x); sp;
generalize (subset_hs_vars_hyps H); intro k;
apply k in X0; sp));
try (complete (rw subvars_eq; unfold subset; sp)).
destruct vhyps as [ nixb vhyps ].
destruct vhyps as [ nixc vhyps ].
destruct vhyps as [ nixu vhyps ].
destruct vhyps as [ nixh vhyps ].
destruct vhyps as [ wu vhyps ].
destruct vhyps as [ wb vhyps ].
destruct vhyps as [ cuh cbh ].
(* done with proving these simple facts *)
vr_seq_true.
vr_seq_true in hyp2.
assert (cover_vars u s1)
as cu1
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
assert (cover_vars u s2)
as cu2
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
generalize (hyp2
(snoc s1 (x, lsubstc u wfce1 s1 cu1))
(snoc s2 (x, lsubstc u wfce1 s2 cu2))); clear hyp2; intro hyp2.
autodimp hyp2 hyp.
generalize (hyps_functionality_snoc lib H (mk_hyp x B) s1 (lsubstc u wfce1 s1 cu1)).
intro imp; apply imp; thin imp; try (complete auto).
introv eq sim'; allsimpl.
vr_seq_true in hyp1.
generalize (hyp1 s1 s'); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
assert (cover_vars B s1) as cvbs1 by (rw @cover_vars_eq; insub).
autodimp hyp2 hyp.
rw @similarity_snoc; simpl.
exists s1 s2 (lsubstc u wfce1 s1 cu1) (lsubstc u wfce1 s2 cu2) wfct1 cvbs1; sp.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
exrepnd.
assert (lsubstc t wfce0 (snoc s1 (x, lsubstc u wfce1 s1 cu1)) pt0
= lsubstc (subst t x u) wfce s1 pt1) as eq1.
symmetry; apply lsubstc_eq_if_csubst.
unfold csubst, subst.
rw @csub2sub_snoc; simpl.
rw <- @lsubst_swap;
try (complete (sp; allapply @in_csub2sub; sp));
try (complete (apply @isprogram_csubst; sp; rw @nt_wf_eq; sp));
try (complete (rw @dom_csub_eq; insub)).
rw @simple_lsubst_lsubst;
try (complete (simpl; sp; cpx));
try (complete (sp; allapply @in_csub2sub; sp)).
assert (lsubstc t wfce0 (snoc s2 (x, lsubstc u wfce1 s2 cu2)) pt3
= lsubstc (subst t x u) wfce s2 pt2) as eq2.
symmetry; apply lsubstc_eq_if_csubst.
unfold csubst, subst.
rw @csub2sub_snoc; simpl.
rw <- @lsubst_swap;
try (complete (sp; allapply @in_csub2sub; sp));
try (complete (apply @isprogram_csubst; sp; rw @nt_wf_eq; sp));
try (complete (rw @dom_csub_eq; insub)).
rw @simple_lsubst_lsubst;
try (complete (simpl; sp; cpx));
try (complete (sp; allapply @in_csub2sub; sp)).
rw eq1 in hyp2; rw eq2 in hyp2.
lsubst_tac; sp.
Qed.
(* begin hide *)
Lemma rule_cut_true_ex {o} :
forall lib (H : @bhyps o) B C t u x
(bc : disjoint (free_vars u) (bound_vars t)),
rule_true_if lib (rule_cut H B C t u x).
Proof.
intros.
generalize (rule_cut_true lib H B C t u x bc); intro rt.
rw <- @rule_true_eq_ex in rt.
unfold rule_true_ex in rt; sp.
Qed.
(* end hide *)
(* [19] ============ CUTH ============ *)
(**
This rule is similar to the cut rule, but is valid only if [x] is
not free in the extract:
<<
H |- C ext t
By cutH x B
H |- B ext u
H, [x : B] |- C ext t
>>
*)
Definition rule_cutH {o}
(H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar) :=
mk_rule
(mk_baresequent H (mk_concl C t))
[ mk_baresequent H (mk_concl B u),
mk_baresequent (snoc H (mk_hhyp x B)) (mk_concl C t)
]
[sarg_var x].
Lemma rule_cutH_true {o} :
forall
lib
(H : @barehypotheses o)
(B C t u : NTerm)
(x : NVar),
rule_true lib (rule_cutH H B C t u x).
Proof.
unfold rule_cutH, rule_true, closed_type_baresequent, closed_extract_baresequent; simpl.
intros.
(* We prove the well-formedness of things *)
destseq; allsimpl.
generalize (hyps (mk_baresequent H (mk_concl B u))
(inl eq_refl))
(hyps (mk_baresequent (snoc H (mk_hhyp x B)) (mk_concl C t))
(inr (inl eq_refl)));
simpl; intros hyp1 hyp2; clear hyps.
destruct hyp1 as [ ws1 hyp1 ].
destruct hyp2 as [ ws2 hyp2 ].
destseq; allsimpl; proof_irr; GC.
assert (covered t (vars_hyps (filter is_nh H))) as cv.
clear hyp1 hyp2.
dwfseq.
introv i.
apply ce in i; sp.
exists cv.
(* We prove some simple facts on our sequents *)
assert (! LIn x (free_vars B)
/\ ! LIn x (free_vars C)
/\ ! LIn x (free_vars u)
/\ ! LIn x (vars_hyps H)
/\ ! LIn x (free_vars t)
/\ wf_term u
/\ wf_term B
/\ covered u (nh_vars_hyps H)
/\ covered B (vars_hyps H)) as vhyps.
clear hyp1 hyp2.
dwfseq.
sp;
try (complete (generalize (ce0 x); sp;
generalize (subset_hs_vars_hyps H); intro k;
apply k in X0; sp));
try (complete (generalize (ce x); sp;
generalize (subset_hs_vars_hyps H); intro k;
apply k in X0; sp));
try (complete (rw subvars_eq; unfold subset; sp)).
destruct vhyps as [ nixb vhyps ].
destruct vhyps as [ nixc vhyps ].
destruct vhyps as [ nixu vhyps ].
destruct vhyps as [ nixh vhyps ].
destruct vhyps as [ nixt vhyps ].
destruct vhyps as [ wu vhyps ].
destruct vhyps as [ wb vhyps ].
destruct vhyps as [ cuh cbh ].
(* done with proving these simple facts *)
vr_seq_true.
vr_seq_true in hyp2.
assert (cover_vars u s1)
as cu1
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
assert (cover_vars u s2)
as cu2
by (rw @cover_vars_eq;
unfold covered in ce0;
insub;
apply subvars_trans with (vs2 := nh_vars_hyps H); sp).
generalize (hyp2
(snoc s1 (x, lsubstc u wfce1 s1 cu1))
(snoc s2 (x, lsubstc u wfce1 s2 cu2))); clear hyp2; intro hyp2.
autodimp hyp2 hyp.
generalize (hyps_functionality_snoc lib H (mk_hhyp x B) s1 (lsubstc u wfce1 s1 cu1)).
intro imp; apply imp; thin imp; try (complete auto).
introv eq sim'; allsimpl.
vr_seq_true in hyp1.
generalize (hyp1 s1 s'); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
assert (cover_vars B s1) as cvbs1 by (rw @cover_vars_eq; insub).
autodimp hyp2 hyp.
rw @similarity_snoc; simpl.
exists s1 s2 (lsubstc u wfce1 s1 cu1) (lsubstc u wfce1 s2 cu2) wfct1 cvbs1; sp.
vr_seq_true in hyp1.
generalize (hyp1 s1 s2); clear hyp1; intro hyp1.
repeat (autodimp hyp1 hyp); exrepnd; clear_irr; sp.
exrepnd.
lsubst_tac; sp.
Qed.
(* begin hide *)
Lemma rule_cutH_true_ex {o} :
forall lib (H : @bhyps o) B C t u x,
rule_true_if lib (rule_cutH H B C t u x).
Proof.
intros.
generalize (rule_cutH_true lib H B C t u x); intro rt.
rw <- @rule_true_eq_ex in rt.
unfold rule_true_ex in rt; sp.
Qed.
(* end hide *)
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:04:13
// Design Name:
// Module Name: pm1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module pc_ctrl_pm1 #(
parameter DATA_W_IN_BYTES = 4,
parameter ADDR_W_IN_BITS = 32,
parameter DCADDR_LOW_BIT_W = 8
) (
input wire [31:0] accum_low_period,
input wire [15:0] pulse_per_second,
input wire ready_to_read ,
output reg [31:0] clk_freq = 32'd100000000,
output reg clk_subsample = 1'd0,
output reg enable = 1'd1,
output reg use_one_pps_in = 1'd1,
input wire reg_bank_rd_start, // read start strobe
output wire reg_bank_rd_done, // read done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_rd_addr, // read address bus
output reg [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_rd_data=0,// read data bus
input wire reg_bank_wr_start, // write start strobe
output wire reg_bank_wr_done, // write done strobe
input wire [DCADDR_LOW_BIT_W - 1:0] reg_bank_wr_addr, // write address bus
input wire [(DATA_W_IN_BYTES*8) - 1:0] reg_bank_wr_data, // write data bus
input wire ACLK , // Clock source
input wire ARESETn // Reset source
);
//------------------------------------------------------------------------------
// Declare registers
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// In the basic bank these are completed straight away. Recall ....XX_start is
// a registered signal.
//------------------------------------------------------------------------------
assign reg_bank_wr_done = reg_bank_wr_start;
assign reg_bank_rd_done = reg_bank_rd_start;
//------------------------------------------------------------------------------
// Write logic
//------------------------------------------------------------------------------
always @(posedge ACLK) begin
if(!ARESETn) begin
clk_freq <= 32'd100000000;
clk_subsample <= 1'd0;
enable <= 1'd1;
use_one_pps_in <= 1'd1;
end else begin
if(reg_bank_wr_start) begin
case (reg_bank_wr_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
enable <= reg_bank_wr_data[0:0];
end
1 : begin
use_one_pps_in <= reg_bank_wr_data[0:0];
end
2 : begin
clk_freq <= reg_bank_wr_data[31:0];
end
3 : begin
clk_subsample <= reg_bank_wr_data[0:0];
end
endcase
end
end
end
//------------------------------------------------------------------------------
// READ logic
//------------------------------------------------------------------------------
always @(*) begin
// Zero the complete bus. We will set specific bits in the case
reg_bank_rd_data = 'd0;
case (reg_bank_rd_addr[DCADDR_LOW_BIT_W-1:2])
0 : begin
reg_bank_rd_data[0:0] = enable;
end
1 : begin
reg_bank_rd_data[0:0] = use_one_pps_in;
end
2 : begin
reg_bank_rd_data[31:0] = clk_freq;
end
3 : begin
reg_bank_rd_data[0:0] = clk_subsample;
end
4 : begin
reg_bank_rd_data[15:0] = pulse_per_second;
end
5 : begin
reg_bank_rd_data[31:0] = accum_low_period;
end
6 : begin
reg_bank_rd_data[0:0] = ready_to_read;
end
endcase
end
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:51:19 05/03/2016
// Design Name:
// Module Name: uart_tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module my_uart_tx8to8(
clk,
rst_n,
uart_ctl,
data_out,
data_sign,
data_valid,
rs_tx
);
input clk;
input rst_n;
input [2:0] uart_ctl;
input [7:0] data_out;
input data_sign;
output data_valid;
output rs_tx;
parameter bps9600 = 13'd5208, //baud is 9600bps
bps19200 = 13'd2603, //baud is 19200bps
bps38400 = 13'd1301, //baud is 38400bps
bps57600 = 13'd867, //baud is 57600bps
bps115200 = 13'd434, //baud is 115200bps
bps256000 = 13'd195; //baud is 115200bps
reg [12:0] cnt;
reg bps_sel;
reg [3:0] tran_cnt;
reg rs_tx;
reg sign_delay;
reg data_valid;
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
bps_sel <= 1'b0;
cnt <= 'h0;
end
else begin
case(uart_ctl)
3'h0: cnt <= (cnt == bps9600) ? 'h0 : cnt + 1'b1;
3'h1: cnt <= (cnt == bps19200) ? 'h0 : cnt + 1'b1;
3'h2: cnt <= (cnt == bps38400) ? 'h0 : cnt + 1'b1;
3'h3: cnt <= (cnt == bps57600) ? 'h0 : cnt + 1'b1;
3'h4: cnt <= (cnt == bps115200) ? 'h0 : cnt + 1'b1;
3'h5: cnt <= (cnt == bps256000) ? 'h0 : cnt + 1'b1;
default: cnt <= (cnt == bps9600) ? 'h0 : cnt + 1'b1;
endcase
bps_sel <= ~|cnt;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
sign_delay <= 1'b0;
data_valid <= 1'b0;
end
else begin
if(bps_sel) sign_delay <= 1'b0;
else if(data_sign) sign_delay <= 1'b1;
if(data_sign | sign_delay) data_valid <= 1'b0;
else if(tran_cnt== 9) data_valid <= 1'b1;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
tran_cnt <= 'h9;
end
else if (bps_sel)begin
if(tran_cnt != 9) tran_cnt <= tran_cnt + 1'b1;
else if (data_sign|sign_delay) tran_cnt <= 'h0;
end
end
always@(posedge clk or negedge rst_n)begin
if(!rst_n)begin
rs_tx <= 1'b1;
end
else if (bps_sel) begin
if(tran_cnt == 0) rs_tx <= 1'b0 ;
else if(tran_cnt == 9) rs_tx <= 1'b1;
else rs_tx <= data_out[tran_cnt - 1];
end
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
spi_sdo,
spi_sdi,
spi_cs,
spi_sclk,
led_clk_o,
gain0_o,
gain1_o,
otg_vbusoc);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input spi_sdi;
inout spi_sdo;
output spi_sclk;
output [ 1:0] spi_cs;
output led_clk_o;
output gain0_o;
output gain1_o;
input otg_vbusoc;
// internal signals
wire [34:0] gpio_i;
wire [34:0] gpio_o;
wire [34:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
wire [23:0] offload_sdi_data;
wire spi_sdo_o;
wire spi_sdo_t;
wire excitation;
assign gain0_o = gpio_o[32];
assign gain1_o = gpio_o[33];
assign gpio_i[34] = spi_sdi; // Interrupt
assign led_clk_o = excitation;
ad_iobuf #(
.DATA_WIDTH(1)
) i_sdo_iobuf (
.dio_t(spi_sdo_t),
.dio_i(spi_sdo_o),
.dio_p(spi_sdo)
);
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd)
);
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl)
);
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda)
);
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.spi_sdo (spi_sdo_o),
.spi_sdo_t (spi_sdo_t),
.spi_sdi (spi_sdi),
.spi_cs (spi_cs),
.spi_sclk (spi_sclk),
.excitation (excitation),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// wasca_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.0 145
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0 (
input wire altpll_0_c0_clk, // altpll_0_c0.clk
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset, // altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
input wire sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset, // sega_saturn_abus_slave_0_reset_reset_bridge_in_reset.reset
input wire [26:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [26:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
input wire [27:0] sega_saturn_abus_slave_0_avalon_master_address, // sega_saturn_abus_slave_0_avalon_master.address
output wire sega_saturn_abus_slave_0_avalon_master_waitrequest, // .waitrequest
input wire [0:0] sega_saturn_abus_slave_0_avalon_master_burstcount, // .burstcount
input wire sega_saturn_abus_slave_0_avalon_master_read, // .read
output wire [15:0] sega_saturn_abus_slave_0_avalon_master_readdata, // .readdata
output wire sega_saturn_abus_slave_0_avalon_master_readdatavalid, // .readdatavalid
input wire sega_saturn_abus_slave_0_avalon_master_write, // .write
input wire [15:0] sega_saturn_abus_slave_0_avalon_master_writedata, // .writedata
output wire [1:0] altpll_0_pll_slave_address, // altpll_0_pll_slave.address
output wire altpll_0_pll_slave_write, // .write
output wire altpll_0_pll_slave_read, // .read
input wire [31:0] altpll_0_pll_slave_readdata, // .readdata
output wire [31:0] altpll_0_pll_slave_writedata, // .writedata
output wire [1:0] audio_0_avalon_audio_slave_address, // audio_0_avalon_audio_slave.address
output wire audio_0_avalon_audio_slave_write, // .write
output wire audio_0_avalon_audio_slave_read, // .read
input wire [31:0] audio_0_avalon_audio_slave_readdata, // .readdata
output wire [31:0] audio_0_avalon_audio_slave_writedata, // .writedata
output wire audio_0_avalon_audio_slave_chipselect, // .chipselect
output wire [23:0] external_sdram_controller_s1_address, // external_sdram_controller_s1.address
output wire external_sdram_controller_s1_write, // .write
output wire external_sdram_controller_s1_read, // .read
input wire [15:0] external_sdram_controller_s1_readdata, // .readdata
output wire [15:0] external_sdram_controller_s1_writedata, // .writedata
output wire [1:0] external_sdram_controller_s1_byteenable, // .byteenable
input wire external_sdram_controller_s1_readdatavalid, // .readdatavalid
input wire external_sdram_controller_s1_waitrequest, // .waitrequest
output wire external_sdram_controller_s1_chipselect, // .chipselect
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [15:0] onchip_flash_0_data_address, // onchip_flash_0_data.address
output wire onchip_flash_0_data_read, // .read
input wire [31:0] onchip_flash_0_data_readdata, // .readdata
output wire [3:0] onchip_flash_0_data_burstcount, // .burstcount
input wire onchip_flash_0_data_readdatavalid, // .readdatavalid
input wire onchip_flash_0_data_waitrequest, // .waitrequest
output wire [11:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [7:0] sega_saturn_abus_slave_0_avalon_nios_address, // sega_saturn_abus_slave_0_avalon_nios.address
output wire sega_saturn_abus_slave_0_avalon_nios_write, // .write
output wire sega_saturn_abus_slave_0_avalon_nios_read, // .read
input wire [15:0] sega_saturn_abus_slave_0_avalon_nios_readdata, // .readdata
output wire [15:0] sega_saturn_abus_slave_0_avalon_nios_writedata, // .writedata
output wire [0:0] sega_saturn_abus_slave_0_avalon_nios_burstcount, // .burstcount
input wire sega_saturn_abus_slave_0_avalon_nios_readdatavalid, // .readdatavalid
input wire sega_saturn_abus_slave_0_avalon_nios_waitrequest, // .waitrequest
output wire [2:0] spi_sd_card_spi_control_port_address, // spi_sd_card_spi_control_port.address
output wire spi_sd_card_spi_control_port_write, // .write
output wire spi_sd_card_spi_control_port_read, // .read
input wire [15:0] spi_sd_card_spi_control_port_readdata, // .readdata
output wire [15:0] spi_sd_card_spi_control_port_writedata, // .writedata
output wire spi_sd_card_spi_control_port_chipselect, // .chipselect
output wire [2:0] spi_stm32_spi_control_port_address, // spi_stm32_spi_control_port.address
output wire spi_stm32_spi_control_port_write, // .write
output wire spi_stm32_spi_control_port_read, // .read
input wire [15:0] spi_stm32_spi_control_port_readdata, // .readdata
output wire [15:0] spi_stm32_spi_control_port_writedata, // .writedata
output wire spi_stm32_spi_control_port_chipselect, // .chipselect
output wire [2:0] uart_0_s1_address, // uart_0_s1.address
output wire uart_0_s1_write, // .write
output wire uart_0_s1_read, // .read
input wire [15:0] uart_0_s1_readdata, // .readdata
output wire [15:0] uart_0_s1_writedata, // .writedata
output wire uart_0_s1_begintransfer, // .begintransfer
output wire uart_0_s1_chipselect // .chipselect
);
wire sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest; // sega_saturn_abus_slave_0_avalon_master_agent:av_waitrequest -> sega_saturn_abus_slave_0_avalon_master_translator:uav_waitrequest
wire [15:0] sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata; // sega_saturn_abus_slave_0_avalon_master_agent:av_readdata -> sega_saturn_abus_slave_0_avalon_master_translator:uav_readdata
wire sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess; // sega_saturn_abus_slave_0_avalon_master_translator:uav_debugaccess -> sega_saturn_abus_slave_0_avalon_master_agent:av_debugaccess
wire [27:0] sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_address; // sega_saturn_abus_slave_0_avalon_master_translator:uav_address -> sega_saturn_abus_slave_0_avalon_master_agent:av_address
wire sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_read; // sega_saturn_abus_slave_0_avalon_master_translator:uav_read -> sega_saturn_abus_slave_0_avalon_master_agent:av_read
wire [1:0] sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable; // sega_saturn_abus_slave_0_avalon_master_translator:uav_byteenable -> sega_saturn_abus_slave_0_avalon_master_agent:av_byteenable
wire sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // sega_saturn_abus_slave_0_avalon_master_agent:av_readdatavalid -> sega_saturn_abus_slave_0_avalon_master_translator:uav_readdatavalid
wire sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock; // sega_saturn_abus_slave_0_avalon_master_translator:uav_lock -> sega_saturn_abus_slave_0_avalon_master_agent:av_lock
wire sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_write; // sega_saturn_abus_slave_0_avalon_master_translator:uav_write -> sega_saturn_abus_slave_0_avalon_master_agent:av_write
wire [15:0] sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata; // sega_saturn_abus_slave_0_avalon_master_translator:uav_writedata -> sega_saturn_abus_slave_0_avalon_master_agent:av_writedata
wire [1:0] sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount; // sega_saturn_abus_slave_0_avalon_master_translator:uav_burstcount -> sega_saturn_abus_slave_0_avalon_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> sega_saturn_abus_slave_0_avalon_master_agent:rp_valid
wire [90:0] rsp_mux_src_data; // rsp_mux:src_data -> sega_saturn_abus_slave_0_avalon_master_agent:rp_data
wire rsp_mux_src_ready; // sega_saturn_abus_slave_0_avalon_master_agent:rp_ready -> rsp_mux:src_ready
wire [9:0] rsp_mux_src_channel; // rsp_mux:src_channel -> sega_saturn_abus_slave_0_avalon_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> sega_saturn_abus_slave_0_avalon_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> sega_saturn_abus_slave_0_avalon_master_agent:rp_endofpacket
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [27:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [108:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_data_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [9:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [27:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [108:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire rsp_mux_002_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready
wire [9:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire [15:0] external_sdram_controller_s1_agent_m0_readdata; // external_sdram_controller_s1_translator:uav_readdata -> external_sdram_controller_s1_agent:m0_readdata
wire external_sdram_controller_s1_agent_m0_waitrequest; // external_sdram_controller_s1_translator:uav_waitrequest -> external_sdram_controller_s1_agent:m0_waitrequest
wire external_sdram_controller_s1_agent_m0_debugaccess; // external_sdram_controller_s1_agent:m0_debugaccess -> external_sdram_controller_s1_translator:uav_debugaccess
wire [27:0] external_sdram_controller_s1_agent_m0_address; // external_sdram_controller_s1_agent:m0_address -> external_sdram_controller_s1_translator:uav_address
wire [1:0] external_sdram_controller_s1_agent_m0_byteenable; // external_sdram_controller_s1_agent:m0_byteenable -> external_sdram_controller_s1_translator:uav_byteenable
wire external_sdram_controller_s1_agent_m0_read; // external_sdram_controller_s1_agent:m0_read -> external_sdram_controller_s1_translator:uav_read
wire external_sdram_controller_s1_agent_m0_readdatavalid; // external_sdram_controller_s1_translator:uav_readdatavalid -> external_sdram_controller_s1_agent:m0_readdatavalid
wire external_sdram_controller_s1_agent_m0_lock; // external_sdram_controller_s1_agent:m0_lock -> external_sdram_controller_s1_translator:uav_lock
wire [15:0] external_sdram_controller_s1_agent_m0_writedata; // external_sdram_controller_s1_agent:m0_writedata -> external_sdram_controller_s1_translator:uav_writedata
wire external_sdram_controller_s1_agent_m0_write; // external_sdram_controller_s1_agent:m0_write -> external_sdram_controller_s1_translator:uav_write
wire [1:0] external_sdram_controller_s1_agent_m0_burstcount; // external_sdram_controller_s1_agent:m0_burstcount -> external_sdram_controller_s1_translator:uav_burstcount
wire external_sdram_controller_s1_agent_rf_source_valid; // external_sdram_controller_s1_agent:rf_source_valid -> external_sdram_controller_s1_agent_rsp_fifo:in_valid
wire [91:0] external_sdram_controller_s1_agent_rf_source_data; // external_sdram_controller_s1_agent:rf_source_data -> external_sdram_controller_s1_agent_rsp_fifo:in_data
wire external_sdram_controller_s1_agent_rf_source_ready; // external_sdram_controller_s1_agent_rsp_fifo:in_ready -> external_sdram_controller_s1_agent:rf_source_ready
wire external_sdram_controller_s1_agent_rf_source_startofpacket; // external_sdram_controller_s1_agent:rf_source_startofpacket -> external_sdram_controller_s1_agent_rsp_fifo:in_startofpacket
wire external_sdram_controller_s1_agent_rf_source_endofpacket; // external_sdram_controller_s1_agent:rf_source_endofpacket -> external_sdram_controller_s1_agent_rsp_fifo:in_endofpacket
wire external_sdram_controller_s1_agent_rsp_fifo_out_valid; // external_sdram_controller_s1_agent_rsp_fifo:out_valid -> external_sdram_controller_s1_agent:rf_sink_valid
wire [91:0] external_sdram_controller_s1_agent_rsp_fifo_out_data; // external_sdram_controller_s1_agent_rsp_fifo:out_data -> external_sdram_controller_s1_agent:rf_sink_data
wire external_sdram_controller_s1_agent_rsp_fifo_out_ready; // external_sdram_controller_s1_agent:rf_sink_ready -> external_sdram_controller_s1_agent_rsp_fifo:out_ready
wire external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket; // external_sdram_controller_s1_agent_rsp_fifo:out_startofpacket -> external_sdram_controller_s1_agent:rf_sink_startofpacket
wire external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket; // external_sdram_controller_s1_agent_rsp_fifo:out_endofpacket -> external_sdram_controller_s1_agent:rf_sink_endofpacket
wire external_sdram_controller_s1_agent_rdata_fifo_src_valid; // external_sdram_controller_s1_agent:rdata_fifo_src_valid -> external_sdram_controller_s1_agent_rdata_fifo:in_valid
wire [17:0] external_sdram_controller_s1_agent_rdata_fifo_src_data; // external_sdram_controller_s1_agent:rdata_fifo_src_data -> external_sdram_controller_s1_agent_rdata_fifo:in_data
wire external_sdram_controller_s1_agent_rdata_fifo_src_ready; // external_sdram_controller_s1_agent_rdata_fifo:in_ready -> external_sdram_controller_s1_agent:rdata_fifo_src_ready
wire [31:0] onchip_flash_0_data_agent_m0_readdata; // onchip_flash_0_data_translator:uav_readdata -> onchip_flash_0_data_agent:m0_readdata
wire onchip_flash_0_data_agent_m0_waitrequest; // onchip_flash_0_data_translator:uav_waitrequest -> onchip_flash_0_data_agent:m0_waitrequest
wire onchip_flash_0_data_agent_m0_debugaccess; // onchip_flash_0_data_agent:m0_debugaccess -> onchip_flash_0_data_translator:uav_debugaccess
wire [27:0] onchip_flash_0_data_agent_m0_address; // onchip_flash_0_data_agent:m0_address -> onchip_flash_0_data_translator:uav_address
wire [3:0] onchip_flash_0_data_agent_m0_byteenable; // onchip_flash_0_data_agent:m0_byteenable -> onchip_flash_0_data_translator:uav_byteenable
wire onchip_flash_0_data_agent_m0_read; // onchip_flash_0_data_agent:m0_read -> onchip_flash_0_data_translator:uav_read
wire onchip_flash_0_data_agent_m0_readdatavalid; // onchip_flash_0_data_translator:uav_readdatavalid -> onchip_flash_0_data_agent:m0_readdatavalid
wire onchip_flash_0_data_agent_m0_lock; // onchip_flash_0_data_agent:m0_lock -> onchip_flash_0_data_translator:uav_lock
wire [31:0] onchip_flash_0_data_agent_m0_writedata; // onchip_flash_0_data_agent:m0_writedata -> onchip_flash_0_data_translator:uav_writedata
wire onchip_flash_0_data_agent_m0_write; // onchip_flash_0_data_agent:m0_write -> onchip_flash_0_data_translator:uav_write
wire [5:0] onchip_flash_0_data_agent_m0_burstcount; // onchip_flash_0_data_agent:m0_burstcount -> onchip_flash_0_data_translator:uav_burstcount
wire onchip_flash_0_data_agent_rf_source_valid; // onchip_flash_0_data_agent:rf_source_valid -> onchip_flash_0_data_agent_rsp_fifo:in_valid
wire [109:0] onchip_flash_0_data_agent_rf_source_data; // onchip_flash_0_data_agent:rf_source_data -> onchip_flash_0_data_agent_rsp_fifo:in_data
wire onchip_flash_0_data_agent_rf_source_ready; // onchip_flash_0_data_agent_rsp_fifo:in_ready -> onchip_flash_0_data_agent:rf_source_ready
wire onchip_flash_0_data_agent_rf_source_startofpacket; // onchip_flash_0_data_agent:rf_source_startofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_startofpacket
wire onchip_flash_0_data_agent_rf_source_endofpacket; // onchip_flash_0_data_agent:rf_source_endofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_endofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_valid; // onchip_flash_0_data_agent_rsp_fifo:out_valid -> onchip_flash_0_data_agent:rf_sink_valid
wire [109:0] onchip_flash_0_data_agent_rsp_fifo_out_data; // onchip_flash_0_data_agent_rsp_fifo:out_data -> onchip_flash_0_data_agent:rf_sink_data
wire onchip_flash_0_data_agent_rsp_fifo_out_ready; // onchip_flash_0_data_agent:rf_sink_ready -> onchip_flash_0_data_agent_rsp_fifo:out_ready
wire onchip_flash_0_data_agent_rsp_fifo_out_startofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_startofpacket -> onchip_flash_0_data_agent:rf_sink_startofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_endofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_endofpacket -> onchip_flash_0_data_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> onchip_flash_0_data_agent:cp_valid
wire [108:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> onchip_flash_0_data_agent:cp_data
wire cmd_mux_001_src_ready; // onchip_flash_0_data_agent:cp_ready -> cmd_mux_001:src_ready
wire [9:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> onchip_flash_0_data_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> onchip_flash_0_data_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> onchip_flash_0_data_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [27:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [109:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [109:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [108:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_002_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire [9:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [27:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [109:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [109:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [108:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_003_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire [9:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] audio_0_avalon_audio_slave_agent_m0_readdata; // audio_0_avalon_audio_slave_translator:uav_readdata -> audio_0_avalon_audio_slave_agent:m0_readdata
wire audio_0_avalon_audio_slave_agent_m0_waitrequest; // audio_0_avalon_audio_slave_translator:uav_waitrequest -> audio_0_avalon_audio_slave_agent:m0_waitrequest
wire audio_0_avalon_audio_slave_agent_m0_debugaccess; // audio_0_avalon_audio_slave_agent:m0_debugaccess -> audio_0_avalon_audio_slave_translator:uav_debugaccess
wire [27:0] audio_0_avalon_audio_slave_agent_m0_address; // audio_0_avalon_audio_slave_agent:m0_address -> audio_0_avalon_audio_slave_translator:uav_address
wire [3:0] audio_0_avalon_audio_slave_agent_m0_byteenable; // audio_0_avalon_audio_slave_agent:m0_byteenable -> audio_0_avalon_audio_slave_translator:uav_byteenable
wire audio_0_avalon_audio_slave_agent_m0_read; // audio_0_avalon_audio_slave_agent:m0_read -> audio_0_avalon_audio_slave_translator:uav_read
wire audio_0_avalon_audio_slave_agent_m0_readdatavalid; // audio_0_avalon_audio_slave_translator:uav_readdatavalid -> audio_0_avalon_audio_slave_agent:m0_readdatavalid
wire audio_0_avalon_audio_slave_agent_m0_lock; // audio_0_avalon_audio_slave_agent:m0_lock -> audio_0_avalon_audio_slave_translator:uav_lock
wire [31:0] audio_0_avalon_audio_slave_agent_m0_writedata; // audio_0_avalon_audio_slave_agent:m0_writedata -> audio_0_avalon_audio_slave_translator:uav_writedata
wire audio_0_avalon_audio_slave_agent_m0_write; // audio_0_avalon_audio_slave_agent:m0_write -> audio_0_avalon_audio_slave_translator:uav_write
wire [2:0] audio_0_avalon_audio_slave_agent_m0_burstcount; // audio_0_avalon_audio_slave_agent:m0_burstcount -> audio_0_avalon_audio_slave_translator:uav_burstcount
wire audio_0_avalon_audio_slave_agent_rf_source_valid; // audio_0_avalon_audio_slave_agent:rf_source_valid -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_valid
wire [109:0] audio_0_avalon_audio_slave_agent_rf_source_data; // audio_0_avalon_audio_slave_agent:rf_source_data -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_data
wire audio_0_avalon_audio_slave_agent_rf_source_ready; // audio_0_avalon_audio_slave_agent_rsp_fifo:in_ready -> audio_0_avalon_audio_slave_agent:rf_source_ready
wire audio_0_avalon_audio_slave_agent_rf_source_startofpacket; // audio_0_avalon_audio_slave_agent:rf_source_startofpacket -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_startofpacket
wire audio_0_avalon_audio_slave_agent_rf_source_endofpacket; // audio_0_avalon_audio_slave_agent:rf_source_endofpacket -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_endofpacket
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_valid -> audio_0_avalon_audio_slave_agent:rf_sink_valid
wire [109:0] audio_0_avalon_audio_slave_agent_rsp_fifo_out_data; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_data -> audio_0_avalon_audio_slave_agent:rf_sink_data
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready; // audio_0_avalon_audio_slave_agent:rf_sink_ready -> audio_0_avalon_audio_slave_agent_rsp_fifo:out_ready
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_startofpacket -> audio_0_avalon_audio_slave_agent:rf_sink_startofpacket
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_endofpacket -> audio_0_avalon_audio_slave_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> audio_0_avalon_audio_slave_agent:cp_valid
wire [108:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> audio_0_avalon_audio_slave_agent:cp_data
wire cmd_mux_004_src_ready; // audio_0_avalon_audio_slave_agent:cp_ready -> cmd_mux_004:src_ready
wire [9:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> audio_0_avalon_audio_slave_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> audio_0_avalon_audio_slave_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> audio_0_avalon_audio_slave_agent:cp_endofpacket
wire [15:0] sega_saturn_abus_slave_0_avalon_nios_agent_m0_readdata; // sega_saturn_abus_slave_0_avalon_nios_translator:uav_readdata -> sega_saturn_abus_slave_0_avalon_nios_agent:m0_readdata
wire sega_saturn_abus_slave_0_avalon_nios_agent_m0_waitrequest; // sega_saturn_abus_slave_0_avalon_nios_translator:uav_waitrequest -> sega_saturn_abus_slave_0_avalon_nios_agent:m0_waitrequest
wire sega_saturn_abus_slave_0_avalon_nios_agent_m0_debugaccess; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_debugaccess -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_debugaccess
wire [27:0] sega_saturn_abus_slave_0_avalon_nios_agent_m0_address; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_address -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_address
wire [1:0] sega_saturn_abus_slave_0_avalon_nios_agent_m0_byteenable; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_byteenable -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_byteenable
wire sega_saturn_abus_slave_0_avalon_nios_agent_m0_read; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_read -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_read
wire sega_saturn_abus_slave_0_avalon_nios_agent_m0_readdatavalid; // sega_saturn_abus_slave_0_avalon_nios_translator:uav_readdatavalid -> sega_saturn_abus_slave_0_avalon_nios_agent:m0_readdatavalid
wire sega_saturn_abus_slave_0_avalon_nios_agent_m0_lock; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_lock -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_lock
wire [15:0] sega_saturn_abus_slave_0_avalon_nios_agent_m0_writedata; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_writedata -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_writedata
wire sega_saturn_abus_slave_0_avalon_nios_agent_m0_write; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_write -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_write
wire [1:0] sega_saturn_abus_slave_0_avalon_nios_agent_m0_burstcount; // sega_saturn_abus_slave_0_avalon_nios_agent:m0_burstcount -> sega_saturn_abus_slave_0_avalon_nios_translator:uav_burstcount
wire sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_valid; // sega_saturn_abus_slave_0_avalon_nios_agent:rf_source_valid -> sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:in_valid
wire [91:0] sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_data; // sega_saturn_abus_slave_0_avalon_nios_agent:rf_source_data -> sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:in_data
wire sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_ready; // sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:in_ready -> sega_saturn_abus_slave_0_avalon_nios_agent:rf_source_ready
wire sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_startofpacket; // sega_saturn_abus_slave_0_avalon_nios_agent:rf_source_startofpacket -> sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:in_startofpacket
wire sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_endofpacket; // sega_saturn_abus_slave_0_avalon_nios_agent:rf_source_endofpacket -> sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:in_endofpacket
wire sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid; // sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:out_valid -> sega_saturn_abus_slave_0_avalon_nios_agent:rf_sink_valid
wire [91:0] sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_data; // sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:out_data -> sega_saturn_abus_slave_0_avalon_nios_agent:rf_sink_data
wire sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready; // sega_saturn_abus_slave_0_avalon_nios_agent:rf_sink_ready -> sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:out_ready
wire sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket; // sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:out_startofpacket -> sega_saturn_abus_slave_0_avalon_nios_agent:rf_sink_startofpacket
wire sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket; // sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo:out_endofpacket -> sega_saturn_abus_slave_0_avalon_nios_agent:rf_sink_endofpacket
wire [31:0] altpll_0_pll_slave_agent_m0_readdata; // altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_agent:m0_readdata
wire altpll_0_pll_slave_agent_m0_waitrequest; // altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_agent:m0_waitrequest
wire altpll_0_pll_slave_agent_m0_debugaccess; // altpll_0_pll_slave_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
wire [27:0] altpll_0_pll_slave_agent_m0_address; // altpll_0_pll_slave_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
wire [3:0] altpll_0_pll_slave_agent_m0_byteenable; // altpll_0_pll_slave_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
wire altpll_0_pll_slave_agent_m0_read; // altpll_0_pll_slave_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
wire altpll_0_pll_slave_agent_m0_readdatavalid; // altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_agent:m0_readdatavalid
wire altpll_0_pll_slave_agent_m0_lock; // altpll_0_pll_slave_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
wire [31:0] altpll_0_pll_slave_agent_m0_writedata; // altpll_0_pll_slave_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
wire altpll_0_pll_slave_agent_m0_write; // altpll_0_pll_slave_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
wire [2:0] altpll_0_pll_slave_agent_m0_burstcount; // altpll_0_pll_slave_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
wire altpll_0_pll_slave_agent_rf_source_valid; // altpll_0_pll_slave_agent:rf_source_valid -> altpll_0_pll_slave_agent_rsp_fifo:in_valid
wire [109:0] altpll_0_pll_slave_agent_rf_source_data; // altpll_0_pll_slave_agent:rf_source_data -> altpll_0_pll_slave_agent_rsp_fifo:in_data
wire altpll_0_pll_slave_agent_rf_source_ready; // altpll_0_pll_slave_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_agent:rf_source_ready
wire altpll_0_pll_slave_agent_rf_source_startofpacket; // altpll_0_pll_slave_agent:rf_source_startofpacket -> altpll_0_pll_slave_agent_rsp_fifo:in_startofpacket
wire altpll_0_pll_slave_agent_rf_source_endofpacket; // altpll_0_pll_slave_agent:rf_source_endofpacket -> altpll_0_pll_slave_agent_rsp_fifo:in_endofpacket
wire altpll_0_pll_slave_agent_rsp_fifo_out_valid; // altpll_0_pll_slave_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_agent:rf_sink_valid
wire [109:0] altpll_0_pll_slave_agent_rsp_fifo_out_data; // altpll_0_pll_slave_agent_rsp_fifo:out_data -> altpll_0_pll_slave_agent:rf_sink_data
wire altpll_0_pll_slave_agent_rsp_fifo_out_ready; // altpll_0_pll_slave_agent:rf_sink_ready -> altpll_0_pll_slave_agent_rsp_fifo:out_ready
wire altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket; // altpll_0_pll_slave_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_agent:rf_sink_startofpacket
wire altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket; // altpll_0_pll_slave_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_agent:rf_sink_endofpacket
wire altpll_0_pll_slave_agent_rdata_fifo_src_valid; // altpll_0_pll_slave_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_agent_rdata_fifo:in_valid
wire [33:0] altpll_0_pll_slave_agent_rdata_fifo_src_data; // altpll_0_pll_slave_agent:rdata_fifo_src_data -> altpll_0_pll_slave_agent_rdata_fifo:in_data
wire altpll_0_pll_slave_agent_rdata_fifo_src_ready; // altpll_0_pll_slave_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> altpll_0_pll_slave_agent:cp_valid
wire [108:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> altpll_0_pll_slave_agent:cp_data
wire cmd_mux_006_src_ready; // altpll_0_pll_slave_agent:cp_ready -> cmd_mux_006:src_ready
wire [9:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> altpll_0_pll_slave_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> altpll_0_pll_slave_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> altpll_0_pll_slave_agent:cp_endofpacket
wire [31:0] uart_0_s1_agent_m0_readdata; // uart_0_s1_translator:uav_readdata -> uart_0_s1_agent:m0_readdata
wire uart_0_s1_agent_m0_waitrequest; // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_agent:m0_waitrequest
wire uart_0_s1_agent_m0_debugaccess; // uart_0_s1_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess
wire [27:0] uart_0_s1_agent_m0_address; // uart_0_s1_agent:m0_address -> uart_0_s1_translator:uav_address
wire [3:0] uart_0_s1_agent_m0_byteenable; // uart_0_s1_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable
wire uart_0_s1_agent_m0_read; // uart_0_s1_agent:m0_read -> uart_0_s1_translator:uav_read
wire uart_0_s1_agent_m0_readdatavalid; // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_agent:m0_readdatavalid
wire uart_0_s1_agent_m0_lock; // uart_0_s1_agent:m0_lock -> uart_0_s1_translator:uav_lock
wire [31:0] uart_0_s1_agent_m0_writedata; // uart_0_s1_agent:m0_writedata -> uart_0_s1_translator:uav_writedata
wire uart_0_s1_agent_m0_write; // uart_0_s1_agent:m0_write -> uart_0_s1_translator:uav_write
wire [2:0] uart_0_s1_agent_m0_burstcount; // uart_0_s1_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount
wire uart_0_s1_agent_rf_source_valid; // uart_0_s1_agent:rf_source_valid -> uart_0_s1_agent_rsp_fifo:in_valid
wire [109:0] uart_0_s1_agent_rf_source_data; // uart_0_s1_agent:rf_source_data -> uart_0_s1_agent_rsp_fifo:in_data
wire uart_0_s1_agent_rf_source_ready; // uart_0_s1_agent_rsp_fifo:in_ready -> uart_0_s1_agent:rf_source_ready
wire uart_0_s1_agent_rf_source_startofpacket; // uart_0_s1_agent:rf_source_startofpacket -> uart_0_s1_agent_rsp_fifo:in_startofpacket
wire uart_0_s1_agent_rf_source_endofpacket; // uart_0_s1_agent:rf_source_endofpacket -> uart_0_s1_agent_rsp_fifo:in_endofpacket
wire uart_0_s1_agent_rsp_fifo_out_valid; // uart_0_s1_agent_rsp_fifo:out_valid -> uart_0_s1_agent:rf_sink_valid
wire [109:0] uart_0_s1_agent_rsp_fifo_out_data; // uart_0_s1_agent_rsp_fifo:out_data -> uart_0_s1_agent:rf_sink_data
wire uart_0_s1_agent_rsp_fifo_out_ready; // uart_0_s1_agent:rf_sink_ready -> uart_0_s1_agent_rsp_fifo:out_ready
wire uart_0_s1_agent_rsp_fifo_out_startofpacket; // uart_0_s1_agent_rsp_fifo:out_startofpacket -> uart_0_s1_agent:rf_sink_startofpacket
wire uart_0_s1_agent_rsp_fifo_out_endofpacket; // uart_0_s1_agent_rsp_fifo:out_endofpacket -> uart_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> uart_0_s1_agent:cp_valid
wire [108:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> uart_0_s1_agent:cp_data
wire cmd_mux_007_src_ready; // uart_0_s1_agent:cp_ready -> cmd_mux_007:src_ready
wire [9:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> uart_0_s1_agent:cp_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> uart_0_s1_agent:cp_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> uart_0_s1_agent:cp_endofpacket
wire [31:0] spi_sd_card_spi_control_port_agent_m0_readdata; // spi_sd_card_spi_control_port_translator:uav_readdata -> spi_sd_card_spi_control_port_agent:m0_readdata
wire spi_sd_card_spi_control_port_agent_m0_waitrequest; // spi_sd_card_spi_control_port_translator:uav_waitrequest -> spi_sd_card_spi_control_port_agent:m0_waitrequest
wire spi_sd_card_spi_control_port_agent_m0_debugaccess; // spi_sd_card_spi_control_port_agent:m0_debugaccess -> spi_sd_card_spi_control_port_translator:uav_debugaccess
wire [27:0] spi_sd_card_spi_control_port_agent_m0_address; // spi_sd_card_spi_control_port_agent:m0_address -> spi_sd_card_spi_control_port_translator:uav_address
wire [3:0] spi_sd_card_spi_control_port_agent_m0_byteenable; // spi_sd_card_spi_control_port_agent:m0_byteenable -> spi_sd_card_spi_control_port_translator:uav_byteenable
wire spi_sd_card_spi_control_port_agent_m0_read; // spi_sd_card_spi_control_port_agent:m0_read -> spi_sd_card_spi_control_port_translator:uav_read
wire spi_sd_card_spi_control_port_agent_m0_readdatavalid; // spi_sd_card_spi_control_port_translator:uav_readdatavalid -> spi_sd_card_spi_control_port_agent:m0_readdatavalid
wire spi_sd_card_spi_control_port_agent_m0_lock; // spi_sd_card_spi_control_port_agent:m0_lock -> spi_sd_card_spi_control_port_translator:uav_lock
wire [31:0] spi_sd_card_spi_control_port_agent_m0_writedata; // spi_sd_card_spi_control_port_agent:m0_writedata -> spi_sd_card_spi_control_port_translator:uav_writedata
wire spi_sd_card_spi_control_port_agent_m0_write; // spi_sd_card_spi_control_port_agent:m0_write -> spi_sd_card_spi_control_port_translator:uav_write
wire [2:0] spi_sd_card_spi_control_port_agent_m0_burstcount; // spi_sd_card_spi_control_port_agent:m0_burstcount -> spi_sd_card_spi_control_port_translator:uav_burstcount
wire spi_sd_card_spi_control_port_agent_rf_source_valid; // spi_sd_card_spi_control_port_agent:rf_source_valid -> spi_sd_card_spi_control_port_agent_rsp_fifo:in_valid
wire [109:0] spi_sd_card_spi_control_port_agent_rf_source_data; // spi_sd_card_spi_control_port_agent:rf_source_data -> spi_sd_card_spi_control_port_agent_rsp_fifo:in_data
wire spi_sd_card_spi_control_port_agent_rf_source_ready; // spi_sd_card_spi_control_port_agent_rsp_fifo:in_ready -> spi_sd_card_spi_control_port_agent:rf_source_ready
wire spi_sd_card_spi_control_port_agent_rf_source_startofpacket; // spi_sd_card_spi_control_port_agent:rf_source_startofpacket -> spi_sd_card_spi_control_port_agent_rsp_fifo:in_startofpacket
wire spi_sd_card_spi_control_port_agent_rf_source_endofpacket; // spi_sd_card_spi_control_port_agent:rf_source_endofpacket -> spi_sd_card_spi_control_port_agent_rsp_fifo:in_endofpacket
wire spi_sd_card_spi_control_port_agent_rsp_fifo_out_valid; // spi_sd_card_spi_control_port_agent_rsp_fifo:out_valid -> spi_sd_card_spi_control_port_agent:rf_sink_valid
wire [109:0] spi_sd_card_spi_control_port_agent_rsp_fifo_out_data; // spi_sd_card_spi_control_port_agent_rsp_fifo:out_data -> spi_sd_card_spi_control_port_agent:rf_sink_data
wire spi_sd_card_spi_control_port_agent_rsp_fifo_out_ready; // spi_sd_card_spi_control_port_agent:rf_sink_ready -> spi_sd_card_spi_control_port_agent_rsp_fifo:out_ready
wire spi_sd_card_spi_control_port_agent_rsp_fifo_out_startofpacket; // spi_sd_card_spi_control_port_agent_rsp_fifo:out_startofpacket -> spi_sd_card_spi_control_port_agent:rf_sink_startofpacket
wire spi_sd_card_spi_control_port_agent_rsp_fifo_out_endofpacket; // spi_sd_card_spi_control_port_agent_rsp_fifo:out_endofpacket -> spi_sd_card_spi_control_port_agent:rf_sink_endofpacket
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> spi_sd_card_spi_control_port_agent:cp_valid
wire [108:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> spi_sd_card_spi_control_port_agent:cp_data
wire cmd_mux_008_src_ready; // spi_sd_card_spi_control_port_agent:cp_ready -> cmd_mux_008:src_ready
wire [9:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> spi_sd_card_spi_control_port_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> spi_sd_card_spi_control_port_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> spi_sd_card_spi_control_port_agent:cp_endofpacket
wire [31:0] spi_stm32_spi_control_port_agent_m0_readdata; // spi_stm32_spi_control_port_translator:uav_readdata -> spi_stm32_spi_control_port_agent:m0_readdata
wire spi_stm32_spi_control_port_agent_m0_waitrequest; // spi_stm32_spi_control_port_translator:uav_waitrequest -> spi_stm32_spi_control_port_agent:m0_waitrequest
wire spi_stm32_spi_control_port_agent_m0_debugaccess; // spi_stm32_spi_control_port_agent:m0_debugaccess -> spi_stm32_spi_control_port_translator:uav_debugaccess
wire [27:0] spi_stm32_spi_control_port_agent_m0_address; // spi_stm32_spi_control_port_agent:m0_address -> spi_stm32_spi_control_port_translator:uav_address
wire [3:0] spi_stm32_spi_control_port_agent_m0_byteenable; // spi_stm32_spi_control_port_agent:m0_byteenable -> spi_stm32_spi_control_port_translator:uav_byteenable
wire spi_stm32_spi_control_port_agent_m0_read; // spi_stm32_spi_control_port_agent:m0_read -> spi_stm32_spi_control_port_translator:uav_read
wire spi_stm32_spi_control_port_agent_m0_readdatavalid; // spi_stm32_spi_control_port_translator:uav_readdatavalid -> spi_stm32_spi_control_port_agent:m0_readdatavalid
wire spi_stm32_spi_control_port_agent_m0_lock; // spi_stm32_spi_control_port_agent:m0_lock -> spi_stm32_spi_control_port_translator:uav_lock
wire [31:0] spi_stm32_spi_control_port_agent_m0_writedata; // spi_stm32_spi_control_port_agent:m0_writedata -> spi_stm32_spi_control_port_translator:uav_writedata
wire spi_stm32_spi_control_port_agent_m0_write; // spi_stm32_spi_control_port_agent:m0_write -> spi_stm32_spi_control_port_translator:uav_write
wire [2:0] spi_stm32_spi_control_port_agent_m0_burstcount; // spi_stm32_spi_control_port_agent:m0_burstcount -> spi_stm32_spi_control_port_translator:uav_burstcount
wire spi_stm32_spi_control_port_agent_rf_source_valid; // spi_stm32_spi_control_port_agent:rf_source_valid -> spi_stm32_spi_control_port_agent_rsp_fifo:in_valid
wire [109:0] spi_stm32_spi_control_port_agent_rf_source_data; // spi_stm32_spi_control_port_agent:rf_source_data -> spi_stm32_spi_control_port_agent_rsp_fifo:in_data
wire spi_stm32_spi_control_port_agent_rf_source_ready; // spi_stm32_spi_control_port_agent_rsp_fifo:in_ready -> spi_stm32_spi_control_port_agent:rf_source_ready
wire spi_stm32_spi_control_port_agent_rf_source_startofpacket; // spi_stm32_spi_control_port_agent:rf_source_startofpacket -> spi_stm32_spi_control_port_agent_rsp_fifo:in_startofpacket
wire spi_stm32_spi_control_port_agent_rf_source_endofpacket; // spi_stm32_spi_control_port_agent:rf_source_endofpacket -> spi_stm32_spi_control_port_agent_rsp_fifo:in_endofpacket
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_valid; // spi_stm32_spi_control_port_agent_rsp_fifo:out_valid -> spi_stm32_spi_control_port_agent:rf_sink_valid
wire [109:0] spi_stm32_spi_control_port_agent_rsp_fifo_out_data; // spi_stm32_spi_control_port_agent_rsp_fifo:out_data -> spi_stm32_spi_control_port_agent:rf_sink_data
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_ready; // spi_stm32_spi_control_port_agent:rf_sink_ready -> spi_stm32_spi_control_port_agent_rsp_fifo:out_ready
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket; // spi_stm32_spi_control_port_agent_rsp_fifo:out_startofpacket -> spi_stm32_spi_control_port_agent:rf_sink_startofpacket
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket; // spi_stm32_spi_control_port_agent_rsp_fifo:out_endofpacket -> spi_stm32_spi_control_port_agent:rf_sink_endofpacket
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> spi_stm32_spi_control_port_agent:cp_valid
wire [108:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> spi_stm32_spi_control_port_agent:cp_data
wire cmd_mux_009_src_ready; // spi_stm32_spi_control_port_agent:cp_ready -> cmd_mux_009:src_ready
wire [9:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> spi_stm32_spi_control_port_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> spi_stm32_spi_control_port_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> spi_stm32_spi_control_port_agent:cp_endofpacket
wire sega_saturn_abus_slave_0_avalon_master_agent_cp_valid; // sega_saturn_abus_slave_0_avalon_master_agent:cp_valid -> router:sink_valid
wire [90:0] sega_saturn_abus_slave_0_avalon_master_agent_cp_data; // sega_saturn_abus_slave_0_avalon_master_agent:cp_data -> router:sink_data
wire sega_saturn_abus_slave_0_avalon_master_agent_cp_ready; // router:sink_ready -> sega_saturn_abus_slave_0_avalon_master_agent:cp_ready
wire sega_saturn_abus_slave_0_avalon_master_agent_cp_startofpacket; // sega_saturn_abus_slave_0_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
wire sega_saturn_abus_slave_0_avalon_master_agent_cp_endofpacket; // sega_saturn_abus_slave_0_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [90:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [9:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router_001:sink_valid
wire [108:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [108:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [9:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [108:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_002:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_002:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
wire [108:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
wire [9:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
wire external_sdram_controller_s1_agent_rp_valid; // external_sdram_controller_s1_agent:rp_valid -> router_003:sink_valid
wire [90:0] external_sdram_controller_s1_agent_rp_data; // external_sdram_controller_s1_agent:rp_data -> router_003:sink_data
wire external_sdram_controller_s1_agent_rp_ready; // router_003:sink_ready -> external_sdram_controller_s1_agent:rp_ready
wire external_sdram_controller_s1_agent_rp_startofpacket; // external_sdram_controller_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire external_sdram_controller_s1_agent_rp_endofpacket; // external_sdram_controller_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [90:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [9:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire onchip_flash_0_data_agent_rp_valid; // onchip_flash_0_data_agent:rp_valid -> router_004:sink_valid
wire [108:0] onchip_flash_0_data_agent_rp_data; // onchip_flash_0_data_agent:rp_data -> router_004:sink_data
wire onchip_flash_0_data_agent_rp_ready; // router_004:sink_ready -> onchip_flash_0_data_agent:rp_ready
wire onchip_flash_0_data_agent_rp_startofpacket; // onchip_flash_0_data_agent:rp_startofpacket -> router_004:sink_startofpacket
wire onchip_flash_0_data_agent_rp_endofpacket; // onchip_flash_0_data_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [108:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [9:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_005:sink_valid
wire [108:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_005:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_005:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid
wire [108:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data
wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready
wire [9:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_006:sink_valid
wire [108:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_006:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_006:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_006:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [108:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [9:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire audio_0_avalon_audio_slave_agent_rp_valid; // audio_0_avalon_audio_slave_agent:rp_valid -> router_007:sink_valid
wire [108:0] audio_0_avalon_audio_slave_agent_rp_data; // audio_0_avalon_audio_slave_agent:rp_data -> router_007:sink_data
wire audio_0_avalon_audio_slave_agent_rp_ready; // router_007:sink_ready -> audio_0_avalon_audio_slave_agent:rp_ready
wire audio_0_avalon_audio_slave_agent_rp_startofpacket; // audio_0_avalon_audio_slave_agent:rp_startofpacket -> router_007:sink_startofpacket
wire audio_0_avalon_audio_slave_agent_rp_endofpacket; // audio_0_avalon_audio_slave_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_004:sink_valid
wire [108:0] router_007_src_data; // router_007:src_data -> rsp_demux_004:sink_data
wire router_007_src_ready; // rsp_demux_004:sink_ready -> router_007:src_ready
wire [9:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_004:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire sega_saturn_abus_slave_0_avalon_nios_agent_rp_valid; // sega_saturn_abus_slave_0_avalon_nios_agent:rp_valid -> router_008:sink_valid
wire [90:0] sega_saturn_abus_slave_0_avalon_nios_agent_rp_data; // sega_saturn_abus_slave_0_avalon_nios_agent:rp_data -> router_008:sink_data
wire sega_saturn_abus_slave_0_avalon_nios_agent_rp_ready; // router_008:sink_ready -> sega_saturn_abus_slave_0_avalon_nios_agent:rp_ready
wire sega_saturn_abus_slave_0_avalon_nios_agent_rp_startofpacket; // sega_saturn_abus_slave_0_avalon_nios_agent:rp_startofpacket -> router_008:sink_startofpacket
wire sega_saturn_abus_slave_0_avalon_nios_agent_rp_endofpacket; // sega_saturn_abus_slave_0_avalon_nios_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_005:sink_valid
wire [90:0] router_008_src_data; // router_008:src_data -> rsp_demux_005:sink_data
wire router_008_src_ready; // rsp_demux_005:sink_ready -> router_008:src_ready
wire [9:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_005:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire altpll_0_pll_slave_agent_rp_valid; // altpll_0_pll_slave_agent:rp_valid -> router_009:sink_valid
wire [108:0] altpll_0_pll_slave_agent_rp_data; // altpll_0_pll_slave_agent:rp_data -> router_009:sink_data
wire altpll_0_pll_slave_agent_rp_ready; // router_009:sink_ready -> altpll_0_pll_slave_agent:rp_ready
wire altpll_0_pll_slave_agent_rp_startofpacket; // altpll_0_pll_slave_agent:rp_startofpacket -> router_009:sink_startofpacket
wire altpll_0_pll_slave_agent_rp_endofpacket; // altpll_0_pll_slave_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_006:sink_valid
wire [108:0] router_009_src_data; // router_009:src_data -> rsp_demux_006:sink_data
wire router_009_src_ready; // rsp_demux_006:sink_ready -> router_009:src_ready
wire [9:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_006:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire uart_0_s1_agent_rp_valid; // uart_0_s1_agent:rp_valid -> router_010:sink_valid
wire [108:0] uart_0_s1_agent_rp_data; // uart_0_s1_agent:rp_data -> router_010:sink_data
wire uart_0_s1_agent_rp_ready; // router_010:sink_ready -> uart_0_s1_agent:rp_ready
wire uart_0_s1_agent_rp_startofpacket; // uart_0_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire uart_0_s1_agent_rp_endofpacket; // uart_0_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_007:sink_valid
wire [108:0] router_010_src_data; // router_010:src_data -> rsp_demux_007:sink_data
wire router_010_src_ready; // rsp_demux_007:sink_ready -> router_010:src_ready
wire [9:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_007:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire spi_sd_card_spi_control_port_agent_rp_valid; // spi_sd_card_spi_control_port_agent:rp_valid -> router_011:sink_valid
wire [108:0] spi_sd_card_spi_control_port_agent_rp_data; // spi_sd_card_spi_control_port_agent:rp_data -> router_011:sink_data
wire spi_sd_card_spi_control_port_agent_rp_ready; // router_011:sink_ready -> spi_sd_card_spi_control_port_agent:rp_ready
wire spi_sd_card_spi_control_port_agent_rp_startofpacket; // spi_sd_card_spi_control_port_agent:rp_startofpacket -> router_011:sink_startofpacket
wire spi_sd_card_spi_control_port_agent_rp_endofpacket; // spi_sd_card_spi_control_port_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_008:sink_valid
wire [108:0] router_011_src_data; // router_011:src_data -> rsp_demux_008:sink_data
wire router_011_src_ready; // rsp_demux_008:sink_ready -> router_011:src_ready
wire [9:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_008:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire spi_stm32_spi_control_port_agent_rp_valid; // spi_stm32_spi_control_port_agent:rp_valid -> router_012:sink_valid
wire [108:0] spi_stm32_spi_control_port_agent_rp_data; // spi_stm32_spi_control_port_agent:rp_data -> router_012:sink_data
wire spi_stm32_spi_control_port_agent_rp_ready; // router_012:sink_ready -> spi_stm32_spi_control_port_agent:rp_ready
wire spi_stm32_spi_control_port_agent_rp_startofpacket; // spi_stm32_spi_control_port_agent:rp_startofpacket -> router_012:sink_startofpacket
wire spi_stm32_spi_control_port_agent_rp_endofpacket; // spi_stm32_spi_control_port_agent:rp_endofpacket -> router_012:sink_endofpacket
wire router_012_src_valid; // router_012:src_valid -> rsp_demux_009:sink_valid
wire [108:0] router_012_src_data; // router_012:src_data -> rsp_demux_009:sink_data
wire router_012_src_ready; // rsp_demux_009:sink_ready -> router_012:src_ready
wire [9:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_009:sink_channel
wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> external_sdram_controller_s1_burst_adapter:sink0_valid
wire [90:0] cmd_mux_src_data; // cmd_mux:src_data -> external_sdram_controller_s1_burst_adapter:sink0_data
wire cmd_mux_src_ready; // external_sdram_controller_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [9:0] cmd_mux_src_channel; // cmd_mux:src_channel -> external_sdram_controller_s1_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> external_sdram_controller_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> external_sdram_controller_s1_burst_adapter:sink0_endofpacket
wire external_sdram_controller_s1_burst_adapter_source0_valid; // external_sdram_controller_s1_burst_adapter:source0_valid -> external_sdram_controller_s1_agent:cp_valid
wire [90:0] external_sdram_controller_s1_burst_adapter_source0_data; // external_sdram_controller_s1_burst_adapter:source0_data -> external_sdram_controller_s1_agent:cp_data
wire external_sdram_controller_s1_burst_adapter_source0_ready; // external_sdram_controller_s1_agent:cp_ready -> external_sdram_controller_s1_burst_adapter:source0_ready
wire [9:0] external_sdram_controller_s1_burst_adapter_source0_channel; // external_sdram_controller_s1_burst_adapter:source0_channel -> external_sdram_controller_s1_agent:cp_channel
wire external_sdram_controller_s1_burst_adapter_source0_startofpacket; // external_sdram_controller_s1_burst_adapter:source0_startofpacket -> external_sdram_controller_s1_agent:cp_startofpacket
wire external_sdram_controller_s1_burst_adapter_source0_endofpacket; // external_sdram_controller_s1_burst_adapter:source0_endofpacket -> external_sdram_controller_s1_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> sega_saturn_abus_slave_0_avalon_nios_burst_adapter:sink0_valid
wire [90:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> sega_saturn_abus_slave_0_avalon_nios_burst_adapter:sink0_data
wire cmd_mux_005_src_ready; // sega_saturn_abus_slave_0_avalon_nios_burst_adapter:sink0_ready -> cmd_mux_005:src_ready
wire [9:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> sega_saturn_abus_slave_0_avalon_nios_burst_adapter:sink0_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> sega_saturn_abus_slave_0_avalon_nios_burst_adapter:sink0_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> sega_saturn_abus_slave_0_avalon_nios_burst_adapter:sink0_endofpacket
wire sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_valid; // sega_saturn_abus_slave_0_avalon_nios_burst_adapter:source0_valid -> sega_saturn_abus_slave_0_avalon_nios_agent:cp_valid
wire [90:0] sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_data; // sega_saturn_abus_slave_0_avalon_nios_burst_adapter:source0_data -> sega_saturn_abus_slave_0_avalon_nios_agent:cp_data
wire sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_ready; // sega_saturn_abus_slave_0_avalon_nios_agent:cp_ready -> sega_saturn_abus_slave_0_avalon_nios_burst_adapter:source0_ready
wire [9:0] sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_channel; // sega_saturn_abus_slave_0_avalon_nios_burst_adapter:source0_channel -> sega_saturn_abus_slave_0_avalon_nios_agent:cp_channel
wire sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_startofpacket; // sega_saturn_abus_slave_0_avalon_nios_burst_adapter:source0_startofpacket -> sega_saturn_abus_slave_0_avalon_nios_agent:cp_startofpacket
wire sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_endofpacket; // sega_saturn_abus_slave_0_avalon_nios_burst_adapter:source0_endofpacket -> sega_saturn_abus_slave_0_avalon_nios_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [90:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [9:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink0_valid
wire [108:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux_001:src1_ready
wire [9:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire [108:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire [9:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire [108:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire [9:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
wire [108:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
wire [9:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src7_valid; // cmd_demux_001:src7_valid -> cmd_mux_007:sink0_valid
wire [108:0] cmd_demux_001_src7_data; // cmd_demux_001:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_001_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux_001:src7_ready
wire [9:0] cmd_demux_001_src7_channel; // cmd_demux_001:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_001_src7_startofpacket; // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_001_src7_endofpacket; // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_001_src8_valid; // cmd_demux_001:src8_valid -> cmd_mux_008:sink0_valid
wire [108:0] cmd_demux_001_src8_data; // cmd_demux_001:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_001_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux_001:src8_ready
wire [9:0] cmd_demux_001_src8_channel; // cmd_demux_001:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_001_src8_startofpacket; // cmd_demux_001:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_001_src8_endofpacket; // cmd_demux_001:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_001_src9_valid; // cmd_demux_001:src9_valid -> cmd_mux_009:sink0_valid
wire [108:0] cmd_demux_001_src9_data; // cmd_demux_001:src9_data -> cmd_mux_009:sink0_data
wire cmd_demux_001_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux_001:src9_ready
wire [9:0] cmd_demux_001_src9_channel; // cmd_demux_001:src9_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_001_src9_startofpacket; // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_001_src9_endofpacket; // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_001:sink1_valid
wire [108:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_002_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_002:src1_ready
wire [9:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_002_src2_valid; // cmd_demux_002:src2_valid -> cmd_mux_002:sink1_valid
wire [108:0] cmd_demux_002_src2_data; // cmd_demux_002:src2_data -> cmd_mux_002:sink1_data
wire cmd_demux_002_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_002:src2_ready
wire [9:0] cmd_demux_002_src2_channel; // cmd_demux_002:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_002_src2_startofpacket; // cmd_demux_002:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire cmd_demux_002_src2_endofpacket; // cmd_demux_002:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_002_src3_valid; // cmd_demux_002:src3_valid -> cmd_mux_003:sink1_valid
wire [108:0] cmd_demux_002_src3_data; // cmd_demux_002:src3_data -> cmd_mux_003:sink1_data
wire cmd_demux_002_src3_ready; // cmd_mux_003:sink1_ready -> cmd_demux_002:src3_ready
wire [9:0] cmd_demux_002_src3_channel; // cmd_demux_002:src3_channel -> cmd_mux_003:sink1_channel
wire cmd_demux_002_src3_startofpacket; // cmd_demux_002:src3_startofpacket -> cmd_mux_003:sink1_startofpacket
wire cmd_demux_002_src3_endofpacket; // cmd_demux_002:src3_endofpacket -> cmd_mux_003:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [90:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [9:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux_001:sink1_valid
wire [108:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src0_ready
wire [9:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_002:sink1_valid
wire [108:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_002:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_002:sink1_ready -> rsp_demux_001:src1_ready
wire [9:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire [108:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire [9:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_002:sink2_valid
wire [108:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_002:sink2_data
wire rsp_demux_002_src1_ready; // rsp_mux_002:sink2_ready -> rsp_demux_002:src1_ready
wire [9:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_002:sink2_channel
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_002:sink2_startofpacket
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_002:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire [108:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire [9:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_003_src1_valid; // rsp_demux_003:src1_valid -> rsp_mux_002:sink3_valid
wire [108:0] rsp_demux_003_src1_data; // rsp_demux_003:src1_data -> rsp_mux_002:sink3_data
wire rsp_demux_003_src1_ready; // rsp_mux_002:sink3_ready -> rsp_demux_003:src1_ready
wire [9:0] rsp_demux_003_src1_channel; // rsp_demux_003:src1_channel -> rsp_mux_002:sink3_channel
wire rsp_demux_003_src1_startofpacket; // rsp_demux_003:src1_startofpacket -> rsp_mux_002:sink3_startofpacket
wire rsp_demux_003_src1_endofpacket; // rsp_demux_003:src1_endofpacket -> rsp_mux_002:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
wire [108:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
wire [9:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux_001:sink7_valid
wire [108:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux_001:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux_001:sink7_ready -> rsp_demux_007:src0_ready
wire [9:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux_001:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux_001:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux_001:sink7_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux_001:sink8_valid
wire [108:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux_001:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux_001:sink8_ready -> rsp_demux_008:src0_ready
wire [9:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux_001:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux_001:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux_001:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux_001:sink9_valid
wire [108:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux_001:sink9_data
wire rsp_demux_009_src0_ready; // rsp_mux_001:sink9_ready -> rsp_demux_009:src0_ready
wire [9:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux_001:sink9_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux_001:sink9_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux_001:sink9_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_valid
wire [108:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_data
wire cmd_demux_001_src0_ready; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_ready -> cmd_demux_001:src0_ready
wire [9:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_endofpacket
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_valid -> cmd_mux:sink1_valid
wire [90:0] nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_data -> cmd_mux:sink1_data
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready; // cmd_mux:sink1_ready -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_ready
wire [9:0] nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_channel -> cmd_mux:sink1_channel
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_startofpacket -> cmd_mux:sink1_startofpacket
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:in_valid
wire [108:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:in_data
wire cmd_demux_001_src5_ready; // nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:in_ready -> cmd_demux_001:src5_ready
wire [9:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:in_channel
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:in_startofpacket
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:in_endofpacket
wire nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_valid; // nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:out_valid -> cmd_mux_005:sink0_valid
wire [90:0] nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_data; // nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:out_data -> cmd_mux_005:sink0_data
wire nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_ready; // cmd_mux_005:sink0_ready -> nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:out_ready
wire [9:0] nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_channel; // nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:out_channel -> cmd_mux_005:sink0_channel
wire nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_startofpacket; // nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:out_startofpacket -> cmd_mux_005:sink0_startofpacket
wire nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_endofpacket; // nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter:out_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:in_valid
wire [108:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:in_data
wire cmd_demux_002_src0_ready; // nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:in_ready -> cmd_demux_002:src0_ready
wire [9:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:in_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:in_endofpacket
wire nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid; // nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:out_valid -> cmd_mux:sink2_valid
wire [90:0] nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data; // nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:out_data -> cmd_mux:sink2_data
wire nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready; // cmd_mux:sink2_ready -> nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:out_ready
wire [9:0] nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel; // nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:out_channel -> cmd_mux:sink2_channel
wire nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket; // nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:out_startofpacket -> cmd_mux:sink2_startofpacket
wire nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket; // nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter:out_endofpacket -> cmd_mux:sink2_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_valid
wire [90:0] rsp_demux_src1_data; // rsp_demux:src1_data -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_data
wire rsp_demux_src1_ready; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_ready -> rsp_demux:src1_ready
wire [9:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_endofpacket
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_valid -> rsp_mux_001:sink0_valid
wire [108:0] external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_data -> rsp_mux_001:sink0_data
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready; // rsp_mux_001:sink0_ready -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_ready
wire [9:0] external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_channel -> rsp_mux_001:sink0_channel
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_startofpacket -> rsp_mux_001:sink0_startofpacket
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src2_valid; // rsp_demux:src2_valid -> external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:in_valid
wire [90:0] rsp_demux_src2_data; // rsp_demux:src2_data -> external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:in_data
wire rsp_demux_src2_ready; // external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:in_ready -> rsp_demux:src2_ready
wire [9:0] rsp_demux_src2_channel; // rsp_demux:src2_channel -> external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:in_channel
wire rsp_demux_src2_startofpacket; // rsp_demux:src2_startofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:in_startofpacket
wire rsp_demux_src2_endofpacket; // rsp_demux:src2_endofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:in_endofpacket
wire external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_valid; // external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:out_valid -> rsp_mux_002:sink0_valid
wire [108:0] external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_data; // external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:out_data -> rsp_mux_002:sink0_data
wire external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_ready; // rsp_mux_002:sink0_ready -> external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:out_ready
wire [9:0] external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_channel; // external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:out_channel -> rsp_mux_002:sink0_channel
wire external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_startofpacket; // external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:out_startofpacket -> rsp_mux_002:sink0_startofpacket
wire external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_endofpacket; // external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter:out_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:in_valid
wire [90:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:in_data
wire rsp_demux_005_src0_ready; // sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:in_ready -> rsp_demux_005:src0_ready
wire [9:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:in_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:in_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:in_endofpacket
wire sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid; // sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:out_valid -> rsp_mux_001:sink5_valid
wire [108:0] sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data; // sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:out_data -> rsp_mux_001:sink5_data
wire sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready; // rsp_mux_001:sink5_ready -> sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:out_ready
wire [9:0] sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel; // sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:out_channel -> rsp_mux_001:sink5_channel
wire sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket; // sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:out_startofpacket -> rsp_mux_001:sink5_startofpacket
wire sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket; // sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter:out_endofpacket -> rsp_mux_001:sink5_endofpacket
wire cmd_demux_001_src6_valid; // cmd_demux_001:src6_valid -> crosser:in_valid
wire [108:0] cmd_demux_001_src6_data; // cmd_demux_001:src6_data -> crosser:in_data
wire cmd_demux_001_src6_ready; // crosser:in_ready -> cmd_demux_001:src6_ready
wire [9:0] cmd_demux_001_src6_channel; // cmd_demux_001:src6_channel -> crosser:in_channel
wire cmd_demux_001_src6_startofpacket; // cmd_demux_001:src6_startofpacket -> crosser:in_startofpacket
wire cmd_demux_001_src6_endofpacket; // cmd_demux_001:src6_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_006:sink0_valid
wire [108:0] crosser_out_data; // crosser:out_data -> cmd_mux_006:sink0_data
wire crosser_out_ready; // cmd_mux_006:sink0_ready -> crosser:out_ready
wire [9:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_006:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_006:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_006:sink0_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> crosser_001:in_valid
wire [108:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> crosser_001:in_data
wire rsp_demux_006_src0_ready; // crosser_001:in_ready -> rsp_demux_006:src0_ready
wire [9:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> crosser_001:in_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> crosser_001:in_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_mux_001:sink6_valid
wire [108:0] crosser_001_out_data; // crosser_001:out_data -> rsp_mux_001:sink6_data
wire crosser_001_out_ready; // rsp_mux_001:sink6_ready -> crosser_001:out_ready
wire [9:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_mux_001:sink6_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_mux_001:sink6_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_mux_001:sink6_endofpacket
wire external_sdram_controller_s1_agent_rdata_fifo_out_valid; // external_sdram_controller_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [17:0] external_sdram_controller_s1_agent_rdata_fifo_out_data; // external_sdram_controller_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire external_sdram_controller_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> external_sdram_controller_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> external_sdram_controller_s1_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> external_sdram_controller_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // external_sdram_controller_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> external_sdram_controller_s1_agent:rdata_fifo_sink_error
wire onchip_flash_0_data_agent_rdata_fifo_src_valid; // onchip_flash_0_data_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] onchip_flash_0_data_agent_rdata_fifo_src_data; // onchip_flash_0_data_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire onchip_flash_0_data_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> onchip_flash_0_data_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> onchip_flash_0_data_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> onchip_flash_0_data_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // onchip_flash_0_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> onchip_flash_0_data_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid; // audio_0_avalon_audio_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] audio_0_avalon_audio_slave_agent_rdata_fifo_src_data; // audio_0_avalon_audio_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> audio_0_avalon_audio_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // audio_0_avalon_audio_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_error
wire sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid; // sega_saturn_abus_slave_0_avalon_nios_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [17:0] sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_data; // sega_saturn_abus_slave_0_avalon_nios_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> sega_saturn_abus_slave_0_avalon_nios_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> sega_saturn_abus_slave_0_avalon_nios_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> sega_saturn_abus_slave_0_avalon_nios_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // sega_saturn_abus_slave_0_avalon_nios_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> sega_saturn_abus_slave_0_avalon_nios_agent:rdata_fifo_sink_error
wire altpll_0_pll_slave_agent_rdata_fifo_out_valid; // altpll_0_pll_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] altpll_0_pll_slave_agent_rdata_fifo_out_data; // altpll_0_pll_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_006:in_0_data
wire altpll_0_pll_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_006:in_0_ready -> altpll_0_pll_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> altpll_0_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> altpll_0_pll_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // altpll_0_pll_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> altpll_0_pll_slave_agent:rdata_fifo_sink_error
wire uart_0_s1_agent_rdata_fifo_src_valid; // uart_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
wire [33:0] uart_0_s1_agent_rdata_fifo_src_data; // uart_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
wire uart_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_007:in_0_ready -> uart_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> uart_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> uart_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_007_out_0_ready; // uart_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> uart_0_s1_agent:rdata_fifo_sink_error
wire spi_sd_card_spi_control_port_agent_rdata_fifo_src_valid; // spi_sd_card_spi_control_port_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
wire [33:0] spi_sd_card_spi_control_port_agent_rdata_fifo_src_data; // spi_sd_card_spi_control_port_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
wire spi_sd_card_spi_control_port_agent_rdata_fifo_src_ready; // avalon_st_adapter_008:in_0_ready -> spi_sd_card_spi_control_port_agent:rdata_fifo_src_ready
wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> spi_sd_card_spi_control_port_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> spi_sd_card_spi_control_port_agent:rdata_fifo_sink_data
wire avalon_st_adapter_008_out_0_ready; // spi_sd_card_spi_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> spi_sd_card_spi_control_port_agent:rdata_fifo_sink_error
wire spi_stm32_spi_control_port_agent_rdata_fifo_src_valid; // spi_stm32_spi_control_port_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
wire [33:0] spi_stm32_spi_control_port_agent_rdata_fifo_src_data; // spi_stm32_spi_control_port_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
wire spi_stm32_spi_control_port_agent_rdata_fifo_src_ready; // avalon_st_adapter_009:in_0_ready -> spi_stm32_spi_control_port_agent:rdata_fifo_src_ready
wire avalon_st_adapter_009_out_0_valid; // avalon_st_adapter_009:out_0_valid -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_009_out_0_data; // avalon_st_adapter_009:out_0_data -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_data
wire avalon_st_adapter_009_out_0_ready; // spi_stm32_spi_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
wire [0:0] avalon_st_adapter_009_out_0_error; // avalon_st_adapter_009:out_0_error -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (28),
.AV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (2),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) sega_saturn_abus_slave_0_avalon_master_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.uav_write (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (sega_saturn_abus_slave_0_avalon_master_address), // avalon_anti_master_0.address
.av_waitrequest (sega_saturn_abus_slave_0_avalon_master_waitrequest), // .waitrequest
.av_burstcount (sega_saturn_abus_slave_0_avalon_master_burstcount), // .burstcount
.av_read (sega_saturn_abus_slave_0_avalon_master_read), // .read
.av_readdata (sega_saturn_abus_slave_0_avalon_master_readdata), // .readdata
.av_readdatavalid (sega_saturn_abus_slave_0_avalon_master_readdatavalid), // .readdatavalid
.av_write (sega_saturn_abus_slave_0_avalon_master_write), // .write
.av_writedata (sega_saturn_abus_slave_0_avalon_master_writedata), // .writedata
.av_byteenable (2'b11), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_gen2_0_data_master_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (24),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) external_sdram_controller_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (external_sdram_controller_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (external_sdram_controller_s1_agent_m0_burstcount), // .burstcount
.uav_read (external_sdram_controller_s1_agent_m0_read), // .read
.uav_write (external_sdram_controller_s1_agent_m0_write), // .write
.uav_waitrequest (external_sdram_controller_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (external_sdram_controller_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (external_sdram_controller_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (external_sdram_controller_s1_agent_m0_readdata), // .readdata
.uav_writedata (external_sdram_controller_s1_agent_m0_writedata), // .writedata
.uav_lock (external_sdram_controller_s1_agent_m0_lock), // .lock
.uav_debugaccess (external_sdram_controller_s1_agent_m0_debugaccess), // .debugaccess
.av_address (external_sdram_controller_s1_address), // avalon_anti_slave_0.address
.av_write (external_sdram_controller_s1_write), // .write
.av_read (external_sdram_controller_s1_read), // .read
.av_readdata (external_sdram_controller_s1_readdata), // .readdata
.av_writedata (external_sdram_controller_s1_writedata), // .writedata
.av_byteenable (external_sdram_controller_s1_byteenable), // .byteenable
.av_readdatavalid (external_sdram_controller_s1_readdatavalid), // .readdatavalid
.av_waitrequest (external_sdram_controller_s1_waitrequest), // .waitrequest
.av_chipselect (external_sdram_controller_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (6),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_flash_0_data_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_flash_0_data_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.uav_read (onchip_flash_0_data_agent_m0_read), // .read
.uav_write (onchip_flash_0_data_agent_m0_write), // .write
.uav_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.uav_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.uav_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.uav_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_flash_0_data_address), // avalon_anti_slave_0.address
.av_read (onchip_flash_0_data_read), // .read
.av_readdata (onchip_flash_0_data_readdata), // .readdata
.av_burstcount (onchip_flash_0_data_burstcount), // .burstcount
.av_readdatavalid (onchip_flash_0_data_readdatavalid), // .readdatavalid
.av_waitrequest (onchip_flash_0_data_waitrequest), // .waitrequest
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) audio_0_avalon_audio_slave_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (audio_0_avalon_audio_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (audio_0_avalon_audio_slave_agent_m0_burstcount), // .burstcount
.uav_read (audio_0_avalon_audio_slave_agent_m0_read), // .read
.uav_write (audio_0_avalon_audio_slave_agent_m0_write), // .write
.uav_waitrequest (audio_0_avalon_audio_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (audio_0_avalon_audio_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (audio_0_avalon_audio_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (audio_0_avalon_audio_slave_agent_m0_readdata), // .readdata
.uav_writedata (audio_0_avalon_audio_slave_agent_m0_writedata), // .writedata
.uav_lock (audio_0_avalon_audio_slave_agent_m0_lock), // .lock
.uav_debugaccess (audio_0_avalon_audio_slave_agent_m0_debugaccess), // .debugaccess
.av_address (audio_0_avalon_audio_slave_address), // avalon_anti_slave_0.address
.av_write (audio_0_avalon_audio_slave_write), // .write
.av_read (audio_0_avalon_audio_slave_read), // .read
.av_readdata (audio_0_avalon_audio_slave_readdata), // .readdata
.av_writedata (audio_0_avalon_audio_slave_writedata), // .writedata
.av_chipselect (audio_0_avalon_audio_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sega_saturn_abus_slave_0_avalon_nios_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sega_saturn_abus_slave_0_avalon_nios_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sega_saturn_abus_slave_0_avalon_nios_agent_m0_burstcount), // .burstcount
.uav_read (sega_saturn_abus_slave_0_avalon_nios_agent_m0_read), // .read
.uav_write (sega_saturn_abus_slave_0_avalon_nios_agent_m0_write), // .write
.uav_waitrequest (sega_saturn_abus_slave_0_avalon_nios_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sega_saturn_abus_slave_0_avalon_nios_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sega_saturn_abus_slave_0_avalon_nios_agent_m0_byteenable), // .byteenable
.uav_readdata (sega_saturn_abus_slave_0_avalon_nios_agent_m0_readdata), // .readdata
.uav_writedata (sega_saturn_abus_slave_0_avalon_nios_agent_m0_writedata), // .writedata
.uav_lock (sega_saturn_abus_slave_0_avalon_nios_agent_m0_lock), // .lock
.uav_debugaccess (sega_saturn_abus_slave_0_avalon_nios_agent_m0_debugaccess), // .debugaccess
.av_address (sega_saturn_abus_slave_0_avalon_nios_address), // avalon_anti_slave_0.address
.av_write (sega_saturn_abus_slave_0_avalon_nios_write), // .write
.av_read (sega_saturn_abus_slave_0_avalon_nios_read), // .read
.av_readdata (sega_saturn_abus_slave_0_avalon_nios_readdata), // .readdata
.av_writedata (sega_saturn_abus_slave_0_avalon_nios_writedata), // .writedata
.av_burstcount (sega_saturn_abus_slave_0_avalon_nios_burstcount), // .burstcount
.av_readdatavalid (sega_saturn_abus_slave_0_avalon_nios_readdatavalid), // .readdatavalid
.av_waitrequest (sega_saturn_abus_slave_0_avalon_nios_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altpll_0_pll_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (altpll_0_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altpll_0_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (altpll_0_pll_slave_agent_m0_read), // .read
.uav_write (altpll_0_pll_slave_agent_m0_write), // .write
.uav_waitrequest (altpll_0_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altpll_0_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altpll_0_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (altpll_0_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (altpll_0_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (altpll_0_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (altpll_0_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (altpll_0_pll_slave_address), // avalon_anti_slave_0.address
.av_write (altpll_0_pll_slave_write), // .write
.av_read (altpll_0_pll_slave_read), // .read
.av_readdata (altpll_0_pll_slave_readdata), // .readdata
.av_writedata (altpll_0_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_0_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_0_s1_agent_m0_read), // .read
.uav_write (uart_0_s1_agent_m0_write), // .write
.uav_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_0_s1_address), // avalon_anti_slave_0.address
.av_write (uart_0_s1_write), // .write
.av_read (uart_0_s1_read), // .read
.av_readdata (uart_0_s1_readdata), // .readdata
.av_writedata (uart_0_s1_writedata), // .writedata
.av_begintransfer (uart_0_s1_begintransfer), // .begintransfer
.av_chipselect (uart_0_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) spi_sd_card_spi_control_port_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (spi_sd_card_spi_control_port_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (spi_sd_card_spi_control_port_agent_m0_burstcount), // .burstcount
.uav_read (spi_sd_card_spi_control_port_agent_m0_read), // .read
.uav_write (spi_sd_card_spi_control_port_agent_m0_write), // .write
.uav_waitrequest (spi_sd_card_spi_control_port_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (spi_sd_card_spi_control_port_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (spi_sd_card_spi_control_port_agent_m0_byteenable), // .byteenable
.uav_readdata (spi_sd_card_spi_control_port_agent_m0_readdata), // .readdata
.uav_writedata (spi_sd_card_spi_control_port_agent_m0_writedata), // .writedata
.uav_lock (spi_sd_card_spi_control_port_agent_m0_lock), // .lock
.uav_debugaccess (spi_sd_card_spi_control_port_agent_m0_debugaccess), // .debugaccess
.av_address (spi_sd_card_spi_control_port_address), // avalon_anti_slave_0.address
.av_write (spi_sd_card_spi_control_port_write), // .write
.av_read (spi_sd_card_spi_control_port_read), // .read
.av_readdata (spi_sd_card_spi_control_port_readdata), // .readdata
.av_writedata (spi_sd_card_spi_control_port_writedata), // .writedata
.av_chipselect (spi_sd_card_spi_control_port_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) spi_stm32_spi_control_port_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (spi_stm32_spi_control_port_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (spi_stm32_spi_control_port_agent_m0_burstcount), // .burstcount
.uav_read (spi_stm32_spi_control_port_agent_m0_read), // .read
.uav_write (spi_stm32_spi_control_port_agent_m0_write), // .write
.uav_waitrequest (spi_stm32_spi_control_port_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (spi_stm32_spi_control_port_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (spi_stm32_spi_control_port_agent_m0_byteenable), // .byteenable
.uav_readdata (spi_stm32_spi_control_port_agent_m0_readdata), // .readdata
.uav_writedata (spi_stm32_spi_control_port_agent_m0_writedata), // .writedata
.uav_lock (spi_stm32_spi_control_port_agent_m0_lock), // .lock
.uav_debugaccess (spi_stm32_spi_control_port_agent_m0_debugaccess), // .debugaccess
.av_address (spi_stm32_spi_control_port_address), // avalon_anti_slave_0.address
.av_write (spi_stm32_spi_control_port_write), // .write
.av_read (spi_stm32_spi_control_port_read), // .read
.av_readdata (spi_stm32_spi_control_port_readdata), // .readdata
.av_writedata (spi_stm32_spi_control_port_writedata), // .writedata
.av_chipselect (spi_stm32_spi_control_port_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (90),
.PKT_ORI_BURST_SIZE_L (88),
.PKT_RESPONSE_STATUS_H (87),
.PKT_RESPONSE_STATUS_L (86),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_CACHE_H (85),
.PKT_CACHE_L (82),
.PKT_THREAD_ID_H (78),
.PKT_THREAD_ID_L (78),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_EXCLUSIVE (51),
.PKT_TRANS_LOCK (50),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (81),
.PKT_PROTECTION_L (79),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_POSTED (47),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (77),
.PKT_DEST_ID_L (74),
.ST_DATA_W (91),
.ST_CHANNEL_W (10),
.AV_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (2),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sega_saturn_abus_slave_0_avalon_master_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_address), // av.address
.av_write (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.av_read (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (sega_saturn_abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (sega_saturn_abus_slave_0_avalon_master_agent_cp_valid), // cp.valid
.cp_data (sega_saturn_abus_slave_0_avalon_master_agent_cp_data), // .data
.cp_startofpacket (sega_saturn_abus_slave_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (sega_saturn_abus_slave_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (sega_saturn_abus_slave_0_avalon_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (103),
.PKT_CACHE_L (100),
.PKT_THREAD_ID_H (96),
.PKT_THREAD_ID_L (96),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (69),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.ST_DATA_W (109),
.ST_CHANNEL_W (10),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (103),
.PKT_CACHE_L (100),
.PKT_THREAD_ID_H (96),
.PKT_THREAD_ID_L (96),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (69),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.ST_DATA_W (109),
.ST_CHANNEL_W (10),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_002_src_valid), // rp.valid
.rp_data (rsp_mux_002_src_data), // .data
.rp_channel (rsp_mux_002_src_channel), // .channel
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_002_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (90),
.PKT_ORI_BURST_SIZE_L (88),
.PKT_RESPONSE_STATUS_H (87),
.PKT_RESPONSE_STATUS_L (86),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_LOCK (50),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (81),
.PKT_PROTECTION_L (79),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_POSTED (47),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (77),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) external_sdram_controller_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (external_sdram_controller_s1_agent_m0_address), // m0.address
.m0_burstcount (external_sdram_controller_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (external_sdram_controller_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (external_sdram_controller_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (external_sdram_controller_s1_agent_m0_lock), // .lock
.m0_readdata (external_sdram_controller_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (external_sdram_controller_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (external_sdram_controller_s1_agent_m0_read), // .read
.m0_waitrequest (external_sdram_controller_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (external_sdram_controller_s1_agent_m0_writedata), // .writedata
.m0_write (external_sdram_controller_s1_agent_m0_write), // .write
.rp_endofpacket (external_sdram_controller_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (external_sdram_controller_s1_agent_rp_ready), // .ready
.rp_valid (external_sdram_controller_s1_agent_rp_valid), // .valid
.rp_data (external_sdram_controller_s1_agent_rp_data), // .data
.rp_startofpacket (external_sdram_controller_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (external_sdram_controller_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (external_sdram_controller_s1_burst_adapter_source0_valid), // .valid
.cp_data (external_sdram_controller_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (external_sdram_controller_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (external_sdram_controller_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (external_sdram_controller_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (external_sdram_controller_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (external_sdram_controller_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (external_sdram_controller_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (external_sdram_controller_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (external_sdram_controller_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (external_sdram_controller_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (external_sdram_controller_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (external_sdram_controller_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (external_sdram_controller_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (external_sdram_controller_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (external_sdram_controller_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) external_sdram_controller_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (external_sdram_controller_s1_agent_rf_source_data), // in.data
.in_valid (external_sdram_controller_s1_agent_rf_source_valid), // .valid
.in_ready (external_sdram_controller_s1_agent_rf_source_ready), // .ready
.in_startofpacket (external_sdram_controller_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (external_sdram_controller_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (external_sdram_controller_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (external_sdram_controller_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (external_sdram_controller_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) external_sdram_controller_s1_agent_rdata_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (external_sdram_controller_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (external_sdram_controller_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (external_sdram_controller_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (external_sdram_controller_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (external_sdram_controller_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (external_sdram_controller_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_flash_0_data_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_flash_0_data_agent_m0_address), // m0.address
.m0_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.m0_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_flash_0_data_agent_m0_read), // .read
.m0_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.m0_write (onchip_flash_0_data_agent_m0_write), // .write
.rp_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_flash_0_data_agent_rp_ready), // .ready
.rp_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.rp_data (onchip_flash_0_data_agent_rp_data), // .data
.rp_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_flash_0_data_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_flash_0_data_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_flash_0_data_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_flash_0_data_agent_rf_source_data), // in.data
.in_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.in_ready (onchip_flash_0_data_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) audio_0_avalon_audio_slave_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (audio_0_avalon_audio_slave_agent_m0_address), // m0.address
.m0_burstcount (audio_0_avalon_audio_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (audio_0_avalon_audio_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (audio_0_avalon_audio_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (audio_0_avalon_audio_slave_agent_m0_lock), // .lock
.m0_readdata (audio_0_avalon_audio_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (audio_0_avalon_audio_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (audio_0_avalon_audio_slave_agent_m0_read), // .read
.m0_waitrequest (audio_0_avalon_audio_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (audio_0_avalon_audio_slave_agent_m0_writedata), // .writedata
.m0_write (audio_0_avalon_audio_slave_agent_m0_write), // .write
.rp_endofpacket (audio_0_avalon_audio_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (audio_0_avalon_audio_slave_agent_rp_ready), // .ready
.rp_valid (audio_0_avalon_audio_slave_agent_rp_valid), // .valid
.rp_data (audio_0_avalon_audio_slave_agent_rp_data), // .data
.rp_startofpacket (audio_0_avalon_audio_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (audio_0_avalon_audio_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (audio_0_avalon_audio_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (audio_0_avalon_audio_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (audio_0_avalon_audio_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (audio_0_avalon_audio_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (audio_0_avalon_audio_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (audio_0_avalon_audio_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) audio_0_avalon_audio_slave_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (audio_0_avalon_audio_slave_agent_rf_source_data), // in.data
.in_valid (audio_0_avalon_audio_slave_agent_rf_source_valid), // .valid
.in_ready (audio_0_avalon_audio_slave_agent_rf_source_ready), // .ready
.in_startofpacket (audio_0_avalon_audio_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (audio_0_avalon_audio_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (audio_0_avalon_audio_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (90),
.PKT_ORI_BURST_SIZE_L (88),
.PKT_RESPONSE_STATUS_H (87),
.PKT_RESPONSE_STATUS_L (86),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_LOCK (50),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (81),
.PKT_PROTECTION_L (79),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_POSTED (47),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (73),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (77),
.PKT_DEST_ID_L (74),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (91),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) sega_saturn_abus_slave_0_avalon_nios_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sega_saturn_abus_slave_0_avalon_nios_agent_m0_address), // m0.address
.m0_burstcount (sega_saturn_abus_slave_0_avalon_nios_agent_m0_burstcount), // .burstcount
.m0_byteenable (sega_saturn_abus_slave_0_avalon_nios_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sega_saturn_abus_slave_0_avalon_nios_agent_m0_debugaccess), // .debugaccess
.m0_lock (sega_saturn_abus_slave_0_avalon_nios_agent_m0_lock), // .lock
.m0_readdata (sega_saturn_abus_slave_0_avalon_nios_agent_m0_readdata), // .readdata
.m0_readdatavalid (sega_saturn_abus_slave_0_avalon_nios_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sega_saturn_abus_slave_0_avalon_nios_agent_m0_read), // .read
.m0_waitrequest (sega_saturn_abus_slave_0_avalon_nios_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sega_saturn_abus_slave_0_avalon_nios_agent_m0_writedata), // .writedata
.m0_write (sega_saturn_abus_slave_0_avalon_nios_agent_m0_write), // .write
.rp_endofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rp_ready), // .ready
.rp_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rp_valid), // .valid
.rp_data (sega_saturn_abus_slave_0_avalon_nios_agent_rp_data), // .data
.rp_startofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rp_startofpacket), // .startofpacket
.cp_ready (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_ready), // cp.ready
.cp_valid (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_valid), // .valid
.cp_data (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_data), // .data
.cp_startofpacket (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_channel), // .channel
.rf_sink_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (92),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_data), // in.data
.in_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_valid), // .valid
.in_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_ready), // .ready
.in_startofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rf_source_endofpacket), // .endofpacket
.out_data (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_data), // out.data
.out_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid), // .valid
.out_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) altpll_0_pll_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (altpll_0_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (altpll_0_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (altpll_0_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altpll_0_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (altpll_0_pll_slave_agent_m0_lock), // .lock
.m0_readdata (altpll_0_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (altpll_0_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altpll_0_pll_slave_agent_m0_read), // .read
.m0_waitrequest (altpll_0_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altpll_0_pll_slave_agent_m0_writedata), // .writedata
.m0_write (altpll_0_pll_slave_agent_m0_write), // .write
.rp_endofpacket (altpll_0_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altpll_0_pll_slave_agent_rp_ready), // .ready
.rp_valid (altpll_0_pll_slave_agent_rp_valid), // .valid
.rp_data (altpll_0_pll_slave_agent_rp_data), // .data
.rp_startofpacket (altpll_0_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (altpll_0_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altpll_0_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altpll_0_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altpll_0_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altpll_0_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altpll_0_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altpll_0_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altpll_0_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (altpll_0_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altpll_0_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altpll_0_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_0_pll_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_0_pll_slave_agent_rf_source_data), // in.data
.in_valid (altpll_0_pll_slave_agent_rf_source_valid), // .valid
.in_ready (altpll_0_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (altpll_0_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altpll_0_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (altpll_0_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (altpll_0_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (altpll_0_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_0_pll_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_0_pll_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (altpll_0_pll_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (altpll_0_pll_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (altpll_0_pll_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (altpll_0_pll_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (altpll_0_pll_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_0_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_0_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_0_s1_agent_m0_lock), // .lock
.m0_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_0_s1_agent_m0_read), // .read
.m0_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.m0_write (uart_0_s1_agent_m0_write), // .write
.rp_endofpacket (uart_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_0_s1_agent_rp_ready), // .ready
.rp_valid (uart_0_s1_agent_rp_valid), // .valid
.rp_data (uart_0_s1_agent_rp_data), // .data
.rp_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_007_src_ready), // cp.ready
.cp_valid (cmd_mux_007_src_valid), // .valid
.cp_data (cmd_mux_007_src_data), // .data
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_007_src_channel), // .channel
.rf_sink_ready (uart_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
.rdata_fifo_src_ready (uart_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_0_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_0_s1_agent_rf_source_data), // in.data
.in_valid (uart_0_s1_agent_rf_source_valid), // .valid
.in_ready (uart_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) spi_sd_card_spi_control_port_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (spi_sd_card_spi_control_port_agent_m0_address), // m0.address
.m0_burstcount (spi_sd_card_spi_control_port_agent_m0_burstcount), // .burstcount
.m0_byteenable (spi_sd_card_spi_control_port_agent_m0_byteenable), // .byteenable
.m0_debugaccess (spi_sd_card_spi_control_port_agent_m0_debugaccess), // .debugaccess
.m0_lock (spi_sd_card_spi_control_port_agent_m0_lock), // .lock
.m0_readdata (spi_sd_card_spi_control_port_agent_m0_readdata), // .readdata
.m0_readdatavalid (spi_sd_card_spi_control_port_agent_m0_readdatavalid), // .readdatavalid
.m0_read (spi_sd_card_spi_control_port_agent_m0_read), // .read
.m0_waitrequest (spi_sd_card_spi_control_port_agent_m0_waitrequest), // .waitrequest
.m0_writedata (spi_sd_card_spi_control_port_agent_m0_writedata), // .writedata
.m0_write (spi_sd_card_spi_control_port_agent_m0_write), // .write
.rp_endofpacket (spi_sd_card_spi_control_port_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (spi_sd_card_spi_control_port_agent_rp_ready), // .ready
.rp_valid (spi_sd_card_spi_control_port_agent_rp_valid), // .valid
.rp_data (spi_sd_card_spi_control_port_agent_rp_data), // .data
.rp_startofpacket (spi_sd_card_spi_control_port_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (spi_sd_card_spi_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (spi_sd_card_spi_control_port_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (spi_sd_card_spi_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (spi_sd_card_spi_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (spi_sd_card_spi_control_port_agent_rsp_fifo_out_data), // .data
.rf_source_ready (spi_sd_card_spi_control_port_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (spi_sd_card_spi_control_port_agent_rf_source_valid), // .valid
.rf_source_startofpacket (spi_sd_card_spi_control_port_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (spi_sd_card_spi_control_port_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (spi_sd_card_spi_control_port_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
.rdata_fifo_src_ready (spi_sd_card_spi_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (spi_sd_card_spi_control_port_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (spi_sd_card_spi_control_port_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) spi_sd_card_spi_control_port_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (spi_sd_card_spi_control_port_agent_rf_source_data), // in.data
.in_valid (spi_sd_card_spi_control_port_agent_rf_source_valid), // .valid
.in_ready (spi_sd_card_spi_control_port_agent_rf_source_ready), // .ready
.in_startofpacket (spi_sd_card_spi_control_port_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (spi_sd_card_spi_control_port_agent_rf_source_endofpacket), // .endofpacket
.out_data (spi_sd_card_spi_control_port_agent_rsp_fifo_out_data), // out.data
.out_valid (spi_sd_card_spi_control_port_agent_rsp_fifo_out_valid), // .valid
.out_ready (spi_sd_card_spi_control_port_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (spi_sd_card_spi_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (spi_sd_card_spi_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (108),
.PKT_ORI_BURST_SIZE_L (106),
.PKT_RESPONSE_STATUS_H (105),
.PKT_RESPONSE_STATUS_L (104),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (99),
.PKT_PROTECTION_L (97),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (91),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (95),
.PKT_DEST_ID_L (92),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (109),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) spi_stm32_spi_control_port_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (spi_stm32_spi_control_port_agent_m0_address), // m0.address
.m0_burstcount (spi_stm32_spi_control_port_agent_m0_burstcount), // .burstcount
.m0_byteenable (spi_stm32_spi_control_port_agent_m0_byteenable), // .byteenable
.m0_debugaccess (spi_stm32_spi_control_port_agent_m0_debugaccess), // .debugaccess
.m0_lock (spi_stm32_spi_control_port_agent_m0_lock), // .lock
.m0_readdata (spi_stm32_spi_control_port_agent_m0_readdata), // .readdata
.m0_readdatavalid (spi_stm32_spi_control_port_agent_m0_readdatavalid), // .readdatavalid
.m0_read (spi_stm32_spi_control_port_agent_m0_read), // .read
.m0_waitrequest (spi_stm32_spi_control_port_agent_m0_waitrequest), // .waitrequest
.m0_writedata (spi_stm32_spi_control_port_agent_m0_writedata), // .writedata
.m0_write (spi_stm32_spi_control_port_agent_m0_write), // .write
.rp_endofpacket (spi_stm32_spi_control_port_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (spi_stm32_spi_control_port_agent_rp_ready), // .ready
.rp_valid (spi_stm32_spi_control_port_agent_rp_valid), // .valid
.rp_data (spi_stm32_spi_control_port_agent_rp_data), // .data
.rp_startofpacket (spi_stm32_spi_control_port_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (spi_stm32_spi_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (spi_stm32_spi_control_port_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (spi_stm32_spi_control_port_agent_rsp_fifo_out_data), // .data
.rf_source_ready (spi_stm32_spi_control_port_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (spi_stm32_spi_control_port_agent_rf_source_valid), // .valid
.rf_source_startofpacket (spi_stm32_spi_control_port_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (spi_stm32_spi_control_port_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (spi_stm32_spi_control_port_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_009_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_009_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_009_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_009_out_0_error), // .error
.rdata_fifo_src_ready (spi_stm32_spi_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (spi_stm32_spi_control_port_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (spi_stm32_spi_control_port_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (110),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) spi_stm32_spi_control_port_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (spi_stm32_spi_control_port_agent_rf_source_data), // in.data
.in_valid (spi_stm32_spi_control_port_agent_rf_source_valid), // .valid
.in_ready (spi_stm32_spi_control_port_agent_rf_source_ready), // .ready
.in_startofpacket (spi_stm32_spi_control_port_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (spi_stm32_spi_control_port_agent_rf_source_endofpacket), // .endofpacket
.out_data (spi_stm32_spi_control_port_agent_rsp_fifo_out_data), // out.data
.out_valid (spi_stm32_spi_control_port_agent_rsp_fifo_out_valid), // .valid
.out_ready (spi_stm32_spi_control_port_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
wasca_mm_interconnect_0_router router (
.sink_ready (sega_saturn_abus_slave_0_avalon_master_agent_cp_ready), // sink.ready
.sink_valid (sega_saturn_abus_slave_0_avalon_master_agent_cp_valid), // .valid
.sink_data (sega_saturn_abus_slave_0_avalon_master_agent_cp_data), // .data
.sink_startofpacket (sega_saturn_abus_slave_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (sega_saturn_abus_slave_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_002 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_003 (
.sink_ready (external_sdram_controller_s1_agent_rp_ready), // sink.ready
.sink_valid (external_sdram_controller_s1_agent_rp_valid), // .valid
.sink_data (external_sdram_controller_s1_agent_rp_data), // .data
.sink_startofpacket (external_sdram_controller_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (external_sdram_controller_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_004 router_004 (
.sink_ready (onchip_flash_0_data_agent_rp_ready), // sink.ready
.sink_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.sink_data (onchip_flash_0_data_agent_rp_data), // .data
.sink_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_004 router_005 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_004 router_006 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_007 (
.sink_ready (audio_0_avalon_audio_slave_agent_rp_ready), // sink.ready
.sink_valid (audio_0_avalon_audio_slave_agent_rp_valid), // .valid
.sink_data (audio_0_avalon_audio_slave_agent_rp_data), // .data
.sink_startofpacket (audio_0_avalon_audio_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (audio_0_avalon_audio_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_008 router_008 (
.sink_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rp_ready), // sink.ready
.sink_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rp_valid), // .valid
.sink_data (sega_saturn_abus_slave_0_avalon_nios_agent_rp_data), // .data
.sink_startofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sega_saturn_abus_slave_0_avalon_nios_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_009 (
.sink_ready (altpll_0_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (altpll_0_pll_slave_agent_rp_valid), // .valid
.sink_data (altpll_0_pll_slave_agent_rp_data), // .data
.sink_startofpacket (altpll_0_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altpll_0_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_010 (
.sink_ready (uart_0_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_0_s1_agent_rp_valid), // .valid
.sink_data (uart_0_s1_agent_rp_data), // .data
.sink_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_011 (
.sink_ready (spi_sd_card_spi_control_port_agent_rp_ready), // sink.ready
.sink_valid (spi_sd_card_spi_control_port_agent_rp_valid), // .valid
.sink_data (spi_sd_card_spi_control_port_agent_rp_data), // .data
.sink_startofpacket (spi_sd_card_spi_control_port_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (spi_sd_card_spi_control_port_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_012 (
.sink_ready (spi_stm32_spi_control_port_agent_rp_ready), // sink.ready
.sink_valid (spi_stm32_spi_control_port_agent_rp_valid), // .valid
.sink_data (spi_stm32_spi_control_port_agent_rp_data), // .data
.sink_startofpacket (spi_stm32_spi_control_port_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (spi_stm32_spi_control_port_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_012_src_ready), // src.ready
.src_valid (router_012_src_valid), // .valid
.src_data (router_012_src_data), // .data
.src_channel (router_012_src_channel), // .channel
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (68),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (91),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (53),
.OUT_BURSTWRAP_H (60),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3),
.ADAPTER_VERSION ("13.1")
) external_sdram_controller_s1_burst_adapter (
.clk (altpll_0_c0_clk), // cr0.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (external_sdram_controller_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (external_sdram_controller_s1_burst_adapter_source0_data), // .data
.source0_channel (external_sdram_controller_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (external_sdram_controller_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (external_sdram_controller_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (external_sdram_controller_s1_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (68),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (91),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (53),
.OUT_BURSTWRAP_H (60),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) sega_saturn_abus_slave_0_avalon_nios_burst_adapter (
.clk (altpll_0_c0_clk), // cr0.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_005_src_valid), // sink0.valid
.sink0_data (cmd_mux_005_src_data), // .data
.sink0_channel (cmd_mux_005_src_channel), // .channel
.sink0_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_005_src_ready), // .ready
.source0_valid (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_valid), // source0.valid
.source0_data (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_data), // .data
.source0_channel (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_channel), // .channel
.source0_startofpacket (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (sega_saturn_abus_slave_0_avalon_nios_burst_adapter_source0_ready) // .ready
);
wasca_mm_interconnect_0_cmd_demux cmd_demux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_demux_001_src6_valid), // .valid
.src6_data (cmd_demux_001_src6_data), // .data
.src6_channel (cmd_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_demux_001_src7_valid), // .valid
.src7_data (cmd_demux_001_src7_data), // .data
.src7_channel (cmd_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_001_src8_ready), // src8.ready
.src8_valid (cmd_demux_001_src8_valid), // .valid
.src8_data (cmd_demux_001_src8_data), // .data
.src8_channel (cmd_demux_001_src8_channel), // .channel
.src8_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_001_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_001_src9_ready), // src9.ready
.src9_valid (cmd_demux_001_src9_valid), // .valid
.src9_data (cmd_demux_001_src9_data), // .data
.src9_channel (cmd_demux_001_src9_channel), // .channel
.src9_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_001_src9_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_002_src2_ready), // src2.ready
.src2_valid (cmd_demux_002_src2_valid), // .valid
.src2_data (cmd_demux_002_src2_data), // .data
.src2_channel (cmd_demux_002_src2_channel), // .channel
.src2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_002_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_002_src3_ready), // src3.ready
.src3_valid (cmd_demux_002_src3_valid), // .valid
.src3_data (cmd_demux_002_src3_data), // .data
.src3_channel (cmd_demux_002_src3_channel), // .channel
.src3_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready), // sink1.ready
.sink1_valid (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid), // .valid
.sink1_channel (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel), // .channel
.sink1_data (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data), // .data
.sink1_startofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink1_endofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink2_ready (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready), // sink2.ready
.sink2_valid (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid), // .valid
.sink2_channel (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel), // .channel
.sink2_data (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data), // .data
.sink2_startofpacket (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink2_endofpacket (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src1_valid), // .valid
.sink0_channel (cmd_demux_001_src1_channel), // .channel
.sink0_data (cmd_demux_001_src1_data), // .data
.sink0_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src1_valid), // .valid
.sink1_channel (cmd_demux_002_src1_channel), // .channel
.sink1_data (cmd_demux_002_src1_data), // .data
.sink1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_001 cmd_mux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src2_valid), // .valid
.sink1_channel (cmd_demux_002_src2_channel), // .channel
.sink1_data (cmd_demux_002_src2_data), // .data
.sink1_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_001 cmd_mux_003 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src3_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src3_valid), // .valid
.sink1_channel (cmd_demux_002_src3_channel), // .channel
.sink1_data (cmd_demux_002_src3_data), // .data
.sink1_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_004 cmd_mux_004 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src4_valid), // .valid
.sink0_channel (cmd_demux_001_src4_channel), // .channel
.sink0_data (cmd_demux_001_src4_data), // .data
.sink0_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_005 cmd_mux_005 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_ready), // sink0.ready
.sink0_valid (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_valid), // .valid
.sink0_channel (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_channel), // .channel
.sink0_data (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_data), // .data
.sink0_startofpacket (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_004 cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_004 cmd_mux_007 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src7_valid), // .valid
.sink0_channel (cmd_demux_001_src7_channel), // .channel
.sink0_data (cmd_demux_001_src7_data), // .data
.sink0_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src7_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_004 cmd_mux_008 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src8_valid), // .valid
.sink0_channel (cmd_demux_001_src8_channel), // .channel
.sink0_data (cmd_demux_001_src8_data), // .data
.sink0_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src8_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_004 cmd_mux_009 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src9_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src9_valid), // .valid
.sink0_channel (cmd_demux_001_src9_channel), // .channel
.sink0_data (cmd_demux_001_src9_data), // .data
.sink0_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src9_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_src2_ready), // src2.ready
.src2_valid (rsp_demux_src2_valid), // .valid
.src2_data (rsp_demux_src2_data), // .data
.src2_channel (rsp_demux_src2_channel), // .channel
.src2_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_001 rsp_demux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_001 rsp_demux_003 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_demux_003_src1_valid), // .valid
.src1_data (rsp_demux_003_src1_data), // .data
.src1_channel (rsp_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_004 rsp_demux_004 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_demux rsp_demux_005 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_004 rsp_demux_007 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_004 rsp_demux_008 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_004 rsp_demux_009 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_012_src_ready), // sink.ready
.sink_channel (router_012_src_channel), // .channel
.sink_data (router_012_src_data), // .data
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
.sink_valid (router_012_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux rsp_mux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready), // sink0.ready
.sink0_valid (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid), // .valid
.sink0_channel (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel), // .channel
.sink0_data (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data), // .data
.sink0_startofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready), // sink5.ready
.sink5_valid (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid), // .valid
.sink5_channel (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel), // .channel
.sink5_data (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data), // .data
.sink5_startofpacket (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink5_endofpacket (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink6_ready (crosser_001_out_ready), // sink6.ready
.sink6_valid (crosser_001_out_valid), // .valid
.sink6_channel (crosser_001_out_channel), // .channel
.sink6_data (crosser_001_out_data), // .data
.sink6_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink6_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src0_valid), // .valid
.sink9_channel (rsp_demux_009_src0_channel), // .channel
.sink9_data (rsp_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_ready), // sink0.ready
.sink0_valid (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_valid), // .valid
.sink0_channel (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_channel), // .channel
.sink0_data (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_data), // .data
.sink0_startofpacket (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src1_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src1_valid), // .valid
.sink3_channel (rsp_demux_003_src1_channel), // .channel
.sink3_data (rsp_demux_003_src1_data), // .data
.sink3_startofpacket (rsp_demux_003_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (63),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (70),
.IN_PKT_TRANS_COMPRESSED_READ (64),
.IN_PKT_TRANS_WRITE (66),
.IN_PKT_BURSTWRAP_H (78),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (81),
.IN_PKT_BURST_SIZE_L (79),
.IN_PKT_RESPONSE_STATUS_H (105),
.IN_PKT_RESPONSE_STATUS_L (104),
.IN_PKT_TRANS_EXCLUSIVE (69),
.IN_PKT_BURST_TYPE_H (83),
.IN_PKT_BURST_TYPE_L (82),
.IN_PKT_ORI_BURST_SIZE_L (106),
.IN_PKT_ORI_BURST_SIZE_H (108),
.IN_ST_DATA_W (109),
.OUT_PKT_ADDR_H (45),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (57),
.OUT_PKT_BYTE_CNT_L (52),
.OUT_PKT_TRANS_COMPRESSED_READ (46),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (87),
.OUT_PKT_RESPONSE_STATUS_L (86),
.OUT_PKT_TRANS_EXCLUSIVE (51),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (88),
.OUT_PKT_ORI_BURST_SIZE_H (90),
.OUT_ST_DATA_W (91),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_001_src0_valid), // sink.valid
.in_channel (cmd_demux_001_src0_channel), // .channel
.in_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_001_src0_ready), // .ready
.in_data (cmd_demux_001_src0_data), // .data
.out_endofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data), // .data
.out_channel (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (63),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (70),
.IN_PKT_TRANS_COMPRESSED_READ (64),
.IN_PKT_TRANS_WRITE (66),
.IN_PKT_BURSTWRAP_H (78),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (81),
.IN_PKT_BURST_SIZE_L (79),
.IN_PKT_RESPONSE_STATUS_H (105),
.IN_PKT_RESPONSE_STATUS_L (104),
.IN_PKT_TRANS_EXCLUSIVE (69),
.IN_PKT_BURST_TYPE_H (83),
.IN_PKT_BURST_TYPE_L (82),
.IN_PKT_ORI_BURST_SIZE_L (106),
.IN_PKT_ORI_BURST_SIZE_H (108),
.IN_ST_DATA_W (109),
.OUT_PKT_ADDR_H (45),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (57),
.OUT_PKT_BYTE_CNT_L (52),
.OUT_PKT_TRANS_COMPRESSED_READ (46),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (87),
.OUT_PKT_RESPONSE_STATUS_L (86),
.OUT_PKT_TRANS_EXCLUSIVE (51),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (88),
.OUT_PKT_ORI_BURST_SIZE_H (90),
.OUT_ST_DATA_W (91),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_001_src5_valid), // sink.valid
.in_channel (cmd_demux_001_src5_channel), // .channel
.in_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
.in_ready (cmd_demux_001_src5_ready), // .ready
.in_data (cmd_demux_001_src5_data), // .data
.out_endofpacket (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_data), // .data
.out_channel (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_channel), // .channel
.out_valid (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_valid), // .valid
.out_ready (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (nios2_gen2_0_data_master_to_sega_saturn_abus_slave_0_avalon_nios_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (63),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (70),
.IN_PKT_TRANS_COMPRESSED_READ (64),
.IN_PKT_TRANS_WRITE (66),
.IN_PKT_BURSTWRAP_H (78),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (81),
.IN_PKT_BURST_SIZE_L (79),
.IN_PKT_RESPONSE_STATUS_H (105),
.IN_PKT_RESPONSE_STATUS_L (104),
.IN_PKT_TRANS_EXCLUSIVE (69),
.IN_PKT_BURST_TYPE_H (83),
.IN_PKT_BURST_TYPE_L (82),
.IN_PKT_ORI_BURST_SIZE_L (106),
.IN_PKT_ORI_BURST_SIZE_H (108),
.IN_ST_DATA_W (109),
.OUT_PKT_ADDR_H (45),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (57),
.OUT_PKT_BYTE_CNT_L (52),
.OUT_PKT_TRANS_COMPRESSED_READ (46),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (87),
.OUT_PKT_RESPONSE_STATUS_L (86),
.OUT_PKT_TRANS_EXCLUSIVE (51),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (88),
.OUT_PKT_ORI_BURST_SIZE_H (90),
.OUT_ST_DATA_W (91),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_002_src0_valid), // sink.valid
.in_channel (cmd_demux_002_src0_channel), // .channel
.in_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_002_src0_ready), // .ready
.in_data (cmd_demux_002_src0_data), // .data
.out_endofpacket (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data), // .data
.out_channel (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (nios2_gen2_0_instruction_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (45),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (57),
.IN_PKT_BYTE_CNT_L (52),
.IN_PKT_TRANS_COMPRESSED_READ (46),
.IN_PKT_TRANS_WRITE (48),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (58),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (87),
.IN_PKT_RESPONSE_STATUS_L (86),
.IN_PKT_TRANS_EXCLUSIVE (51),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (88),
.IN_PKT_ORI_BURST_SIZE_H (90),
.IN_ST_DATA_W (91),
.OUT_PKT_ADDR_H (63),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (70),
.OUT_PKT_TRANS_COMPRESSED_READ (64),
.OUT_PKT_BURST_SIZE_H (81),
.OUT_PKT_BURST_SIZE_L (79),
.OUT_PKT_RESPONSE_STATUS_H (105),
.OUT_PKT_RESPONSE_STATUS_L (104),
.OUT_PKT_TRANS_EXCLUSIVE (69),
.OUT_PKT_BURST_TYPE_H (83),
.OUT_PKT_BURST_TYPE_L (82),
.OUT_PKT_ORI_BURST_SIZE_L (106),
.OUT_PKT_ORI_BURST_SIZE_H (108),
.OUT_ST_DATA_W (109),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_src1_valid), // sink.valid
.in_channel (rsp_demux_src1_channel), // .channel
.in_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.in_ready (rsp_demux_src1_ready), // .ready
.in_data (rsp_demux_src1_data), // .data
.out_endofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data), // .data
.out_channel (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel), // .channel
.out_valid (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid), // .valid
.out_ready (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (45),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (57),
.IN_PKT_BYTE_CNT_L (52),
.IN_PKT_TRANS_COMPRESSED_READ (46),
.IN_PKT_TRANS_WRITE (48),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (58),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (87),
.IN_PKT_RESPONSE_STATUS_L (86),
.IN_PKT_TRANS_EXCLUSIVE (51),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (88),
.IN_PKT_ORI_BURST_SIZE_H (90),
.IN_ST_DATA_W (91),
.OUT_PKT_ADDR_H (63),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (70),
.OUT_PKT_TRANS_COMPRESSED_READ (64),
.OUT_PKT_BURST_SIZE_H (81),
.OUT_PKT_BURST_SIZE_L (79),
.OUT_PKT_RESPONSE_STATUS_H (105),
.OUT_PKT_RESPONSE_STATUS_L (104),
.OUT_PKT_TRANS_EXCLUSIVE (69),
.OUT_PKT_BURST_TYPE_H (83),
.OUT_PKT_BURST_TYPE_L (82),
.OUT_PKT_ORI_BURST_SIZE_L (106),
.OUT_PKT_ORI_BURST_SIZE_H (108),
.OUT_ST_DATA_W (109),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_src2_valid), // sink.valid
.in_channel (rsp_demux_src2_channel), // .channel
.in_startofpacket (rsp_demux_src2_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src2_endofpacket), // .endofpacket
.in_ready (rsp_demux_src2_ready), // .ready
.in_data (rsp_demux_src2_data), // .data
.out_endofpacket (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_data), // .data
.out_channel (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_channel), // .channel
.out_valid (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_valid), // .valid
.out_ready (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (external_sdram_controller_s1_to_nios2_gen2_0_instruction_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (45),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (57),
.IN_PKT_BYTE_CNT_L (52),
.IN_PKT_TRANS_COMPRESSED_READ (46),
.IN_PKT_TRANS_WRITE (48),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (58),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (87),
.IN_PKT_RESPONSE_STATUS_L (86),
.IN_PKT_TRANS_EXCLUSIVE (51),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (88),
.IN_PKT_ORI_BURST_SIZE_H (90),
.IN_ST_DATA_W (91),
.OUT_PKT_ADDR_H (63),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (70),
.OUT_PKT_TRANS_COMPRESSED_READ (64),
.OUT_PKT_BURST_SIZE_H (81),
.OUT_PKT_BURST_SIZE_L (79),
.OUT_PKT_RESPONSE_STATUS_H (105),
.OUT_PKT_RESPONSE_STATUS_L (104),
.OUT_PKT_TRANS_EXCLUSIVE (69),
.OUT_PKT_BURST_TYPE_H (83),
.OUT_PKT_BURST_TYPE_L (82),
.OUT_PKT_ORI_BURST_SIZE_L (106),
.OUT_PKT_ORI_BURST_SIZE_H (108),
.OUT_ST_DATA_W (109),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_005_src0_valid), // sink.valid
.in_channel (rsp_demux_005_src0_channel), // .channel
.in_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.in_ready (rsp_demux_005_src0_ready), // .ready
.in_data (rsp_demux_005_src0_data), // .data
.out_endofpacket (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data), // .data
.out_channel (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel), // .channel
.out_valid (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid), // .valid
.out_ready (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (sega_saturn_abus_slave_0_avalon_nios_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (109),
.BITS_PER_SYMBOL (109),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (10),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (altpll_0_c0_clk), // in_clk.clk
.in_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src6_ready), // in.ready
.in_valid (cmd_demux_001_src6_valid), // .valid
.in_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src6_channel), // .channel
.in_data (cmd_demux_001_src6_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (109),
.BITS_PER_SYMBOL (109),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (10),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_0_c0_clk), // out_clk.clk
.out_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_006_src0_ready), // in.ready
.in_valid (rsp_demux_006_src0_valid), // .valid
.in_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_006_src0_channel), // .channel
.in_data (rsp_demux_006_src0_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (external_sdram_controller_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (external_sdram_controller_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (external_sdram_controller_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (audio_0_avalon_audio_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (sega_saturn_abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (altpll_0_pll_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (altpll_0_pll_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (altpll_0_pll_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_007 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_008 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (spi_sd_card_spi_control_port_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (spi_sd_card_spi_control_port_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (spi_sd_card_spi_control_port_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_009 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (sega_saturn_abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (spi_stm32_spi_control_port_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (spi_stm32_spi_control_port_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (spi_stm32_spi_control_port_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_009_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_009_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_009_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_009_out_0_error) // .error
);
endmodule
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
// -- --
// -- This RTL describes the CP15 register block. The ports go to the MMU and --
// -- cache unit. This block connects to the CPU core. Coprocessor operations --
// -- supported are read from coprocessor and write to CPU registers or vice --
// -- versa. This is integrated within the processor. The MMU unit can easily --
// -- interface with this block. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_cp15_cb #(
parameter PHY_REGS = 64
)
(
// ----------------------------------------------------------------
// Clock and reset.
// ----------------------------------------------------------------
input wire i_clk,
input wire i_reset,
// ----------------------------------------------------------------
// Coprocessor instruction and done signal.
// ----------------------------------------------------------------
input wire [31:0] i_cp_word,
input wire i_cp_dav,
output reg o_cp_done,
// ----------------------------------------------------------------
// CPSR from processor.
// ----------------------------------------------------------------
input wire [31:0] i_cpsr,
// ----------------------------------------------------------------
// Register file RW interface
// ----------------------------------------------------------------
// Asserted if we want to control of the register file.
// Controls a MUX that selects signals.
output reg o_reg_en,
// Data to write to the register file.
output reg [31:0] o_reg_wr_data,
// Data read from the register file.
input wire [31:0] i_reg_rd_data,
// Write and read index for the register file.
output reg [$clog2(PHY_REGS)-1:0] o_reg_wr_index,
o_reg_rd_index,
// ----------------------------------------------------------------
// From MMU.
// ----------------------------------------------------------------
input wire [31:0] i_fsr,
input wire [31:0] i_far,
// -----------------------------------------------------------------
// MMU configuration signals.
// -----------------------------------------------------------------
// Domain Access Control Register.
output reg [31:0] o_dac,
// Base address of page table.
output reg [31:0] o_baddr,
// MMU enable.
output reg o_mmu_en,
// SR register.
output reg [1:0] o_sr,
// FCSE register.
output reg [7:0] o_pid,
// -----------------------------------------------------------------
// Invalidate and clean controls.
// -----------------------------------------------------------------
// Cache invalidate signal.
output reg o_dcache_inv,
output reg o_icache_inv,
// Cache clean signal.
output reg o_dcache_clean,
output reg o_icache_clean,
// TLB invalidate signal - single cycle.
output reg o_dtlb_inv,
output reg o_itlb_inv,
// Cache enable.
output reg o_dcache_en,
output reg o_icache_en,
// From MMU. Specify that cache invalidation is done.
input wire i_dcache_inv_done,
input wire i_icache_inv_done,
// From MMU. Specify that cache clean is done.
input wire i_dcache_clean_done,
input wire i_icache_clean_done
);
`include "zap_localparams.vh"
`include "zap_defines.vh"
`include "zap_functions.vh"
// ---------------------------------------------
// Variables
// ---------------------------------------------
reg [31:0] r [13:0];// Coprocessor registers. R7, R8 is write-only.
reg [3:0] state; // State variable.
// ---------------------------------------------
// Localparams
// ---------------------------------------------
// States.
localparam IDLE = 0;
localparam ACTIVE = 1;
localparam DONE = 2;
localparam READ = 3;
localparam READ_DLY = 4;
localparam TERM = 5;
localparam CLR_D_CACHE_AND = 6;
localparam CLR_D_CACHE = 7;
localparam CLR_I_CACHE = 8;
localparam CLEAN_D_CACHE = 9;
localparam CLEAN_ID_CACHE = 10;
localparam CLFLUSH_ID_CACHE = 11;
localparam CLFLUSH_D_CACHE = 12;
// Register numbers.
localparam FSR_REG = 5;
localparam FAR_REG = 6;
localparam CACHE_REG = 7;
localparam TLB_REG = 8;
localparam FCSE_REG = 13;
//{opcode_2, crm} values that are valid for this implementation.
localparam CASE_FLUSH_ID_CACHE = 7'b000_0111;
localparam CASE_FLUSH_I_CACHE = 7'b000_0101;
localparam CASE_FLUSH_D_CACHE = 7'b000_0110;
localparam CASE_CLEAN_ID_CACHE = 7'b000_1011;
localparam CASE_CLEAN_D_CACHE = 7'b000_1010;
localparam CASE_CLFLUSH_ID_CACHE = 7'b000_1111;
localparam CASE_CLFLUSH_D_CACHE = 7'b000_1110;
localparam CASE_FLUSH_ID_TLB = 7'b00?_0111;
localparam CASE_FLUSH_I_TLB = 7'b00?_0101;
localparam CASE_FLUSH_D_TLB = 7'b00?_0110;
// ---------------------------------------------
// Sequential Logic
// ---------------------------------------------
// Ties registers to output ports via a register.
always @ ( posedge i_clk )
begin
if ( i_reset )
begin
o_dcache_en <= 1'd0;
o_icache_en <= 1'd0;
o_mmu_en <= 1'd0;
o_pid <= 8'd0;
end
else
begin
o_dcache_en <= r[1][2]; // Data cache enable.
o_icache_en <= r[1][12]; // Instruction cache enable.
o_mmu_en <= r[1][0]; // MMU enable.
o_pid <= {1'd0, r[13][31:25]}; // PID register.
end
end
// Ties register ports via register.
always @ ( posedge i_clk )
begin
o_dac <= r[3]; // DAC register.
o_baddr <= r[2]; // Base address.
o_sr <= {r[1][8],r[1][9]}; // SR register.
end
// Core logic.
always @ ( posedge i_clk )
begin
if ( i_reset )
begin
state <= IDLE;
o_dcache_inv <= 1'd0;
o_icache_inv <= 1'd0;
o_dcache_clean <= 1'd0;
o_icache_clean <= 1'd0;
o_dtlb_inv <= 1'd0;
o_itlb_inv <= 1'd0;
o_reg_en <= 1'd0;
o_cp_done <= 1'd0;
o_reg_wr_data <= 0;
o_reg_wr_index <= 0;
o_reg_rd_index <= 0;
r[0] <= 32'h0;
r[1] <= 32'd0;
r[2] <= 32'd0;
r[3] <= 32'd0;
r[4] <= 32'd0;
r[5] <= 32'd0;
r[6] <= 32'd0;
r[13] <= 32'd0; //FCSE
// R0 override.
generate_r0;
// R1 override.
r[1][1] <= 1'd1;
r[1][3] <= 1'd1;
r[1][6:4] <= 3'b111;
r[1][11] <= 1'd1;
end
else
begin
// Default assignments.
o_itlb_inv <= 1'd0;
o_dtlb_inv <= 1'd0;
o_dcache_inv <= 1'd0;
o_icache_inv <= 1'd0;
o_icache_clean <= 1'd0;
o_dcache_clean <= 1'd0;
o_reg_en <= 1'd0;
o_cp_done <= 1'd0;
case ( state )
IDLE: // Idle state.
begin
o_cp_done <= 1'd0;
// Keep monitoring FSR and FAR from MMU unit. If
// produced, clock them in.
if ( i_fsr[3:0] != 4'd0 )
begin
r[FSR_REG] <= i_fsr;
r[FAR_REG] <= i_far;
end
// Coprocessor instruction.
if ( i_cp_dav && i_cp_word[`cp_id] == 15 )
begin
if ( i_cpsr[4:0] != USR )
begin
// ACTIVATE this block.
state <= ACTIVE;
o_cp_done <= 1'd0;
end
else
begin
// No permissions in USR land.
// Pretend to be done and go ahead.
o_cp_done <= 1'd1;
end
end
end
DONE: // Complete transaction.
begin
// Tell that we are done.
o_cp_done <= 1'd1;
state <= TERM;
end
TERM: // Wait state before going to IDLE.
begin
state <= IDLE;
end
READ_DLY: // Register data is clocked out in this stage.
begin
state <= READ;
end
READ: // Write value read from CPU register to coprocessor.
begin
state <= DONE;
r [ i_cp_word[`crn] ] <= i_reg_rd_data;
if (
i_cp_word[`crn] == TLB_REG // TLB control.
)
begin
casez({i_cp_word[`opcode_2], i_cp_word[`crm]})
CASE_FLUSH_ID_TLB:
begin
o_itlb_inv <= 1'd1;
o_dtlb_inv <= 1'd1;
end
CASE_FLUSH_I_TLB:
begin
o_itlb_inv <= 1'd1;
end
CASE_FLUSH_D_TLB:
begin
o_dtlb_inv <= 1'd1;
end
default:
begin
o_itlb_inv <= 1'd1;
o_dtlb_inv <= 1'd1;
end
endcase
end
else if ( i_cp_word[`crn] == CACHE_REG ) // Cache control.
begin
casez({i_cp_word[`opcode_2], i_cp_word[`crm]})
CASE_FLUSH_ID_CACHE:
begin
// Invalidate caches.
o_dcache_inv <= 1'd1;
state <= CLR_D_CACHE_AND;
end
CASE_FLUSH_D_CACHE:
begin
// Invalidate data cache.
o_dcache_inv <= 1'd1;
state <= CLR_D_CACHE;
end
CASE_FLUSH_I_CACHE:
begin
// Invalidate instruction cache.
o_icache_inv <= 1'd1;
state <= CLR_I_CACHE;
end
CASE_CLEAN_ID_CACHE, CASE_CLEAN_D_CACHE:
begin
o_dcache_clean <= 1'd1;
state <= CLEAN_D_CACHE;
end
CASE_CLFLUSH_D_CACHE:
begin
o_dcache_clean <= 1'd1;
state <= CLFLUSH_D_CACHE;
end
CASE_CLFLUSH_ID_CACHE:
begin
o_dcache_clean <= 1'd1;
state <= CLFLUSH_ID_CACHE;
end
default:
begin
o_dcache_clean <= 1'd1;
state <= CLFLUSH_ID_CACHE;
end
endcase
end
end
// States.
CLEAN_D_CACHE,
CLFLUSH_ID_CACHE,
CLFLUSH_D_CACHE:
begin
o_dcache_clean <= 1'd1;
if ( i_dcache_clean_done )
begin
o_dcache_clean <= 1'd0;
if ( state == CLFLUSH_D_CACHE )
begin
o_dcache_inv <= 1'd1;
state <= CLR_D_CACHE;
end
else if ( state == CLFLUSH_ID_CACHE )
begin
o_dcache_inv <= 1'd1;
state <= CLR_D_CACHE_AND;
end
else // CLEAN_D_CACHE
begin
state <= DONE;
end
end
end
CLR_D_CACHE, CLR_D_CACHE_AND: // Clear data cache.
begin
o_dcache_inv <= 1'd1;
// Wait for cache invalidation to complete.
if ( i_dcache_inv_done && state == CLR_D_CACHE )
begin
o_dcache_inv <= 1'd0;
state <= DONE;
end
else if ( state == CLR_D_CACHE_AND && i_dcache_inv_done )
begin
o_dcache_inv <= 1'd0;
o_icache_inv <= 1'd1;
state <= CLR_I_CACHE;
end
end
CLR_I_CACHE: // Clear instruction cache.
begin
o_icache_inv <= 1'd1;
if ( i_icache_inv_done )
begin
o_icache_inv <= 1'd0;
state <= DONE;
end
end
ACTIVE: // Access processor registers.
begin
if ( is_cc_satisfied ( i_cp_word[31:28], i_cpsr[31:28] ) )
begin
if ( i_cp_word[20] ) // Load to CPU reg.
begin
// Generate CPU Register write command. CP read.
o_reg_en <= 1'd1;
o_reg_wr_index <= translate( i_cp_word[15:12], i_cpsr[4:0] );
o_reg_wr_data <= r[ i_cp_word[19:16] ];
state <= DONE;
end
else // Store to CPU register.
begin
// Generate CPU register read command. CP write.
o_reg_en <= 1'd1;
o_reg_rd_index <= translate(i_cp_word[15:12], i_cpsr[4:0]);
o_reg_wr_index <= 16;
state <= READ_DLY;
end
end
else
begin
state <= DONE;
end
// Process unconditional words to CP15.
casez ( i_cp_word )
MCR2, MRC2, LDC2, STC2:
begin
if ( i_cp_word[20] ) // Load to CPU reg.
begin
// Register write command.
o_reg_en <= 1'd1;
o_reg_wr_index <= translate( i_cp_word[15:12], i_cpsr[4:0] );
o_reg_wr_data <= r[ i_cp_word[19:16] ];
state <= DONE;
end
else // Store to CPU register.
begin
// Generate register read command.
o_reg_en <= 1'd1;
o_reg_rd_index <= translate(i_cp_word[15:12], i_cpsr[4:0]);
o_reg_wr_index <= 16;
state <= READ_DLY;
end
end
endcase
end
endcase
// Default assignments. These bits are unchangeable.
generate_r0;
r[1][1] <= 1'd1;
r[1][3] <= 1'd1; // Write buffer always enabled.
r[1][6:4] <= 3'b111; // 0 = Little Endian, 0 = 0, 1 = 32-bit address range,
// 1 = 32-bit handlers enabled.
r[1][11] <= 1'd1;
end
end
// CPU info register.
task generate_r0;
begin
r[0][3:0] <= 4'd0;
r[0][15:4] <= 12'hAAA;
r[0][19:16] <= 4'h4;
r[0][23:20] <= 4'd0;
r[0][31:24] <= 8'd0;
end
endtask
wire [31:0] r0 = r[0];
wire [31:0] r1 = r[1];
wire [31:0] r2 = r[2];
wire [31:0] r3 = r[3];
wire [31:0] r4 = r[4];
wire [31:0] r5 = r[5];
wire [31:0] r6 = r[6];
endmodule
`default_nettype wire
// ----------------------------------------------------------------------------
// EOF
// ----------------------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_TB_V
`define SKY130_FD_SC_LS__A32O_TB_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a32o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 B2 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 B1 = 1'b0;
#460 B2 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B2 = 1'b1;
#660 B1 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B2 = 1'bx;
#840 B1 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a32o dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FAH_BEHAVIORAL_V
`define SKY130_FD_SC_LP__FAH_BEHAVIORAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__FAH_BEHAVIORAL_V |
//*****************************************************************************
// (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_axi.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:04 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v4_0_ddr2_7Series, mig_wrap_mig_7series_0_0, 2016.2" , CORE_GENERATION_INFO = "ddr2_7Series,mig_7series_v4_0,{LANGUAGE=Verilog, SYNTHESIS_TOOL=Vivado, LEVEL=CONTROLLER, AXI_ENABLE=1, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR2, AXI_ENABLE=1, CLK_PERIOD=3333, PHY_RATIO=2, CLKIN_PERIOD=4999, VCCAUX_IO=1.8V, MEMORY_TYPE=COMP, MEMORY_PART=mt47h64m16hr-25e, DQ_WIDTH=16, ECC=OFF, DATA_MASK=1, ORDERING=STRICT, BURST_MODE=8, BURST_TYPE=SEQ, OUTPUT_DRV=HIGH, USE_CS_PORT=1, USE_ODT_PORT=1, RTT_NOM=50, MEMORY_ADDRESS_MAP=BANK_ROW_COLUMN, REFCLK_FREQ=200, DEBUG_PORT=OFF, INTERNAL_VREF=1, SYSCLK_TYPE=NO_BUFFER, REFCLK_TYPE=NO_BUFFER}" *)
module mig_7series_v4_0_memc_ui_top_axi #
(
parameter TCQ = 100,
parameter DDR3_VDD_OP_VOLT = "135", // Voltage mode used for DDR3
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CA_MIRROR = "OFF", // C/A mirror opt for DDR3 dual rank
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter MASTER_PHY_CTL = 0, // The bank number where master PHY_CONTROL resides
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP0 = "IODELAY_MIG0",
parameter IODELAY_GRP1 = "IODELAY_MIG1",
parameter FPGA_SPEED_GRADE = 1,
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tCKE = 10000, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter USER_REFRESH = "OFF", // Whether user manages REF
parameter TEMP_MON_EN = "ON", // Enable/Disable tempmon
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ODT_WIDTH = 1,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter [3:0] BYTE_LANES_B0 = 4'b1111,
parameter [3:0] BYTE_LANES_B1 = 4'b1111,
parameter [3:0] BYTE_LANES_B2 = 4'b1111,
parameter [3:0] BYTE_LANES_B3 = 4'b1111,
parameter [3:0] BYTE_LANES_B4 = 4'b1111,
parameter [3:0] DATA_CTL_B0 = 4'hc,
parameter [3:0] DATA_CTL_B1 = 4'hf,
parameter [3:0] DATA_CTL_B2 = 4'hf,
parameter [3:0] DATA_CTL_B3 = 4'h0,
parameter [3:0] DATA_CTL_B4 = 4'h0,
parameter [47:0] PHY_0_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_1_BITLANES = 48'h0000_0000_0000,
parameter [47:0] PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter [143:0] CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [191:0] ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter [35:0] BANK_MAP = 36'h000_000_000,
parameter [11:0] CAS_MAP = 12'h000,
parameter [7:0] CKE_ODT_BYTE_MAP = 8'h00,
parameter [95:0] CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter [119:0] CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter [11:0] PARITY_MAP = 12'h000,
parameter [11:0] RAS_MAP = 12'h000,
parameter [11:0] WE_MAP = 12'h000,
parameter [143:0] DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter [95:0] DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [95:0] DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter [107:0] MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [107:0] MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter [15:0] CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter [11:0] CALIB_COL_ADD = 12'h000, // Calibration column address
parameter [2:0] CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IDELAY_ADJ = "ON", //ON : IDELAY-1, OFF: No change
parameter FINE_PER_BIT = "ON", //ON : Use per bit calib for complex rdlvl
parameter CENTER_COMP_MODE = "ON", //ON: use PI stg2 tap compensation
parameter PI_VAL_ADJ = "ON", //ON: PI stg2 tap -1 for centering
parameter SKIP_CALIB = "FALSE",
parameter TAPSPERKCLK = 56,
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_ADDR_WIDTH = 30,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_RD_WR_ARB_ALGORITHM = "RD_PRI_REG",
// Indicates the Arbitration
// Allowed values - "TDM", "ROUND_ROBIN",
// "RD_PRI_REG", "RD_PRI_REG_STARVE_LIMIT"
parameter C_S_AXI_REG_EN0 = 20'h00000,
// Instatiates register slices before upsizer.
// The type of register is specified for each channel
// in a vector. 4 bits per channel are used.
// C_S_AXI_REG_EN0[03:00] = AW CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[07:04] = W CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[11:08] = B CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[15:12] = AR CHANNEL REGISTER SLICE
// C_S_AXI_REG_EN0[20:16] = R CHANNEL REGISTER SLICE
// Possible values for each channel are:
//
// 0 => BYPASS = The channel is just wired through the
// module.
// 1 => FWD = The master VALID and payload signals
// are registrated.
// 2 => REV = The slave ready signal is registrated
// 3 => FWD_REV = Both FWD and REV
// 4 => SLAVE_FWD = All slave side signals and master
// VALID and payload are registrated.
// 5 => SLAVE_RDY = All slave side signals and master
// READY are registrated.
// 6 => INPUTS = Slave and Master side inputs are
// registrated.
parameter C_S_AXI_REG_EN1 = 20'h00000,
// Same as C_S_AXI_REG_EN0, but this register is after
// the upsizer
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
parameter C_S_AXI_BASEADDR = 32'h0000_0000,
// Base address of AXI4 Memory Mapped bus.
parameter C_ECC_ONOFF_RESET_VALUE = 1,
// Controls ECC on/off value at startup/reset
parameter C_ECC_CE_COUNTER_WIDTH = 8,
// The external memory to controller clock ratio.
parameter FPGA_VOLT_TYPE = "N"
)
(
// Clock and reset ports
input clk,
input clk_div2,
input rst_div2,
input [1:0] clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input mmcm_ps_clk,
input poc_sample_pd,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err_o,
output [2*nCK_PER_CLK-1:0] app_ecc_single_err,
input app_sr_req,
output app_sr_active,
input app_ref_req,
output app_ref_ack,
input app_zq_req,
output app_zq_ack,
// Ports to be used with SKIP_CALIB defined
output calib_tap_req,
input [6:0] calib_tap_addr,
input calib_tap_load,
input [7:0] calib_tap_val,
input calib_tap_load_done,
// temperature monitor ports
input [11:0] device_temp,
//phase shift clock control
output psen,
output psincdec,
input psdone,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_first_edge_cnt,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_second_edge_cnt,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [5:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [6*DQS_WIDTH-1:0] dbg_final_po_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_final_po_coarse_tap_cnt,
input aresetn,
// Slave Interface Write Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input [0:0] s_axi_awlock,
input [3:0] s_axi_awcache,
input [2:0] s_axi_awprot,
input [3:0] s_axi_awqos,
input s_axi_awvalid,
output s_axi_awready,
// Slave Interface Write Data Ports
input [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
// Slave Interface Write Response Ports
input s_axi_bready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
// Slave Interface Read Address Ports
input [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input [0:0] s_axi_arlock,
input [3:0] s_axi_arcache,
input [2:0] s_axi_arprot,
input [3:0] s_axi_arqos,
input s_axi_arvalid,
output s_axi_arready,
// Slave Interface Read Data Ports
input s_axi_rready,
output [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
// AXI CTRL port
input s_axi_ctrl_awvalid,
output s_axi_ctrl_awready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_awaddr,
// Slave Interface Write Data Ports
input s_axi_ctrl_wvalid,
output s_axi_ctrl_wready,
input [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_wdata,
// Slave Interface Write Response Ports
output s_axi_ctrl_bvalid,
input s_axi_ctrl_bready,
output [1:0] s_axi_ctrl_bresp,
// Slave Interface Read Address Ports
input s_axi_ctrl_arvalid,
output s_axi_ctrl_arready,
input [C_S_AXI_CTRL_ADDR_WIDTH-1:0] s_axi_ctrl_araddr,
// Slave Interface Read Data Ports
output s_axi_ctrl_rvalid,
input s_axi_ctrl_rready,
output [C_S_AXI_CTRL_DATA_WIDTH-1:0] s_axi_ctrl_rdata,
output [1:0] s_axi_ctrl_rresp,
// Interrupt output
output interrupt,
output init_calib_complete,
input dbg_sel_pi_incdec,
input dbg_sel_po_incdec,
input [DQS_CNT_WIDTH:0] dbg_byte_sel,
input dbg_pi_f_inc,
input dbg_pi_f_dec,
input dbg_po_f_inc,
input dbg_po_f_stg23_sel,
input dbg_po_f_dec,
output [6*DQS_WIDTH*RANKS-1:0] dbg_cpt_tap_cnt,
output [5*DQS_WIDTH*RANKS-1:0] dbg_dq_idelay_tap_cnt,
output dbg_rddata_valid,
output [6*DQS_WIDTH-1:0] dbg_wrlvl_fine_tap_cnt,
output [3*DQS_WIDTH-1:0] dbg_wrlvl_coarse_tap_cnt,
output ref_dll_lock,
input rst_phaser_ref,
input iddr_rst,
output [6*RANKS-1:0] dbg_rd_data_offset,
output [255:0] dbg_calib_top,
output [255:0] dbg_phy_wrlvl,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [255:0] dbg_phy_init,
output [255:0] dbg_prbs_rdlvl,
output [255:0] dbg_dqs_found_cal,
output [5:0] dbg_pi_counter_read_val,
output [8:0] dbg_po_counter_read_val,
output dbg_pi_phaselock_start,
output dbg_pi_phaselocked_done,
output dbg_pi_phaselock_err,
output dbg_pi_dqsfound_start,
output dbg_pi_dqsfound_done,
output dbg_pi_dqsfound_err,
output dbg_wrcal_start,
output dbg_wrcal_done,
output dbg_wrcal_err,
output [11:0] dbg_pi_dqs_found_lanes_phy4lanes,
output [11:0] dbg_pi_phase_locked_phy4lanes,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_1,
output [6*RANKS-1:0] dbg_calib_rd_data_offset_2,
output [5:0] dbg_data_offset,
output [5:0] dbg_data_offset_1,
output [5:0] dbg_data_offset_2,
output dbg_oclkdelay_calib_start,
output dbg_oclkdelay_calib_done,
output [255:0] dbg_phy_oclkdelay_cal,
output [DRAM_WIDTH*16 -1:0] dbg_oclkdelay_rd_data,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_final_dqs_tap_cnt_r,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps,
output [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps,
output [1023:0] dbg_poc
);
localparam IODELAY_GRP = (tCK <= 1500)? IODELAY_GRP1 : IODELAY_GRP0;
localparam INTERFACE = "AXI4";
// Port Interface.
// # = UI - User Interface,
// = AXI4 - AXI4 Interface.
localparam C_FAMILY = "virtex7";
localparam C_MC_DATA_WIDTH_LCL = 2*nCK_PER_CLK*DATA_WIDTH ;
// wire [6*DQS_WIDTH*RANKS-1:0] prbs_final_dqs_tap_cnt_r;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_first_edge_taps;
// wire [6*DQS_WIDTH*RANKS-1:0] dbg_prbs_second_edge_taps;
wire correct_en;
wire [2*nCK_PER_CLK-1:0] raw_not_ecc;
wire [2*nCK_PER_CLK-1:0] ecc_single;
wire [2*nCK_PER_CLK-1:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire app_correct_en;
wire app_correct_en_i;
wire [2*nCK_PER_CLK-1:0] app_raw_not_ecc;
wire [DQ_WIDTH/8-1:0] fi_xor_we;
wire [DQ_WIDTH-1:0] fi_xor_wrdata;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH/8-1:0] wr_data_mask;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_rd_data_to_axi;
wire app_rd_data_end;
wire app_rd_data_valid;
wire app_rdy;
wire app_wdf_rdy;
wire [ADDR_WIDTH-1:0] app_addr;
wire [2:0] app_cmd;
wire app_en;
wire app_hi_pri;
wire app_sz;
wire [APP_DATA_WIDTH-1:0] app_wdf_data;
wire [C_MC_DATA_WIDTH_LCL-1:0] app_wdf_data_axi_o;
wire app_wdf_end;
wire [APP_MASK_WIDTH-1:0] app_wdf_mask;
wire [C_MC_DATA_WIDTH_LCL/8-1:0] app_wdf_mask_axi_o;
wire app_wdf_wren;
wire app_sr_req_i;
wire app_sr_active_i;
wire app_ref_req_i;
wire app_ref_ack_i;
wire app_zq_req_i;
wire app_zq_ack_i;
wire rst_tg_mc;
wire error;
wire init_wrcal_complete;
reg reset /* synthesis syn_maxfan = 10 */;
reg init_calib_complete_r;
//***************************************************************************
// Added a single register stage for the calib_done to fix timing
//***************************************************************************
always @(posedge clk)
init_calib_complete_r <= init_calib_complete;
always @(posedge clk)
reset <= #TCQ (rst | rst_tg_mc);
mig_7series_v4_0_mem_intfc #
(
.TCQ (TCQ),
.DDR3_VDD_OP_VOLT (DDR3_VDD_OP_VOLT),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CA_MIRROR (CA_MIRROR),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.BANK_TYPE (BANK_TYPE),
.DATA_IO_PRIM_TYPE (DATA_IO_PRIM_TYPE),
.DATA_IO_IDLE_PWRDWN (DATA_IO_IDLE_PWRDWN),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tCKE (tCKE),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.USER_REFRESH (USER_REFRESH),
.TEMP_MON_EN (TEMP_MON_EN),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ODT_WIDTH (ODT_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CKE_MAP (CKE_MAP),
.ODT_MAP (ODT_MAP),
.CKE_ODT_AUX (CKE_ODT_AUX),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.IDELAY_ADJ (IDELAY_ADJ),
.FINE_PER_BIT (FINE_PER_BIT),
.CENTER_COMP_MODE (CENTER_COMP_MODE),
.PI_VAL_ADJ (PI_VAL_ADJ),
.TAPSPERKCLK (TAPSPERKCLK),
.SKIP_CALIB (SKIP_CALIB),
.FPGA_VOLT_TYPE (FPGA_VOLT_TYPE)
)
mem_intfc0
(
.clk (clk),
.clk_div2 (clk_div2),
.rst_div2 (rst_div2),
.clk_ref (tCK <= 1500 ? clk_ref[1] : clk_ref[0]),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.mmcm_ps_clk (mmcm_ps_clk),
.poc_sample_pd (poc_sample_pd),
.rst (rst),
.error (error),
.reset (reset),
.rst_tg_mc (rst_tg_mc),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.init_wrcal_complete (init_wrcal_complete),
.app_sr_req (app_sr_req_i),
.app_sr_active (app_sr_active_i),
.app_ref_req (app_ref_req_i),
.app_ref_ack (app_ref_ack_i),
.app_zq_req (app_zq_req_i),
.app_zq_ack (app_zq_ack_i),
// skip calibration i/f
.calib_tap_req (calib_tap_req),
.calib_tap_load (calib_tap_load),
.calib_tap_addr (calib_tap_addr),
.calib_tap_val (calib_tap_val),
.calib_tap_load_done (calib_tap_load_done),
.device_temp (device_temp),
.psen (psen),
.psincdec (psincdec),
.psdone (psdone),
.fi_xor_we (fi_xor_we),
.fi_xor_wrdata (fi_xor_wrdata),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_final_po_fine_tap_cnt (dbg_final_po_fine_tap_cnt),
.dbg_final_po_coarse_tap_cnt (dbg_final_po_coarse_tap_cnt),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.dbg_sel_pi_incdec (dbg_sel_pi_incdec),
.dbg_sel_po_incdec (dbg_sel_po_incdec),
.dbg_byte_sel (dbg_byte_sel),
.dbg_pi_f_inc (dbg_pi_f_inc),
.dbg_pi_f_dec (dbg_pi_f_dec),
.dbg_po_f_inc (dbg_po_f_inc),
.dbg_po_f_stg23_sel (dbg_po_f_stg23_sel),
.dbg_po_f_dec (dbg_po_f_dec),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_dq_idelay_tap_cnt (dbg_dq_idelay_tap_cnt),
.dbg_rddata_valid (dbg_rddata_valid),
.dbg_wrlvl_fine_tap_cnt (dbg_wrlvl_fine_tap_cnt),
.dbg_wrlvl_coarse_tap_cnt (dbg_wrlvl_coarse_tap_cnt),
.dbg_phy_wrlvl (dbg_phy_wrlvl),
.dbg_pi_counter_read_val (dbg_pi_counter_read_val),
.dbg_po_counter_read_val (dbg_po_counter_read_val),
.ref_dll_lock (ref_dll_lock),
.rst_phaser_ref (rst_phaser_ref),
.iddr_rst (iddr_rst),
.dbg_rd_data_offset (dbg_rd_data_offset),
.dbg_phy_init (dbg_phy_init),
.dbg_prbs_rdlvl (dbg_prbs_rdlvl),
.dbg_dqs_found_cal (dbg_dqs_found_cal),
.dbg_pi_phaselock_start (dbg_pi_phaselock_start),
.dbg_pi_phaselocked_done (dbg_pi_phaselocked_done),
.dbg_pi_phaselock_err (dbg_pi_phaselock_err),
.dbg_pi_dqsfound_start (dbg_pi_dqsfound_start),
.dbg_pi_dqsfound_done (dbg_pi_dqsfound_done),
.dbg_pi_dqsfound_err (dbg_pi_dqsfound_err),
.dbg_wrcal_start (dbg_wrcal_start),
.dbg_wrcal_done (dbg_wrcal_done),
.dbg_wrcal_err (dbg_wrcal_err),
.dbg_pi_dqs_found_lanes_phy4lanes (dbg_pi_dqs_found_lanes_phy4lanes),
.dbg_pi_phase_locked_phy4lanes (dbg_pi_phase_locked_phy4lanes),
.dbg_calib_rd_data_offset_1 (dbg_calib_rd_data_offset_1),
.dbg_calib_rd_data_offset_2 (dbg_calib_rd_data_offset_2),
.dbg_data_offset (dbg_data_offset),
.dbg_data_offset_1 (dbg_data_offset_1),
.dbg_data_offset_2 (dbg_data_offset_2),
.dbg_phy_oclkdelay_cal (dbg_phy_oclkdelay_cal),
.dbg_oclkdelay_rd_data (dbg_oclkdelay_rd_data),
.dbg_oclkdelay_calib_start (dbg_oclkdelay_calib_start),
.dbg_oclkdelay_calib_done (dbg_oclkdelay_calib_done),
.prbs_final_dqs_tap_cnt_r (dbg_prbs_final_dqs_tap_cnt_r),
.dbg_prbs_first_edge_taps (dbg_prbs_first_edge_taps),
.dbg_prbs_second_edge_taps (dbg_prbs_second_edge_taps),
.dbg_poc (dbg_poc[1023:0])
);
genvar o;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(o=0;o<8;o=o+1) begin
assign app_wdf_data[o*72+:72] = {app_wdf_data_axi_o[o*64+:8],app_wdf_data_axi_o[o*64+:64]} ;
assign app_wdf_mask[o*9+:9] = {app_wdf_mask_axi_o[o*8],app_wdf_mask_axi_o[o*8+:8]} ;
end
end else begin
end
end else begin
assign app_wdf_data = app_wdf_data_axi_o ;
assign app_wdf_mask = app_wdf_mask_axi_o ;
end
endgenerate
genvar e;
generate
if(ECC_TEST == "ON") begin
if(DQ_WIDTH == 72) begin
for(e=0;e<8;e=e+1) begin
assign app_rd_data_to_axi[e*64+:64] = app_rd_data[e*72+:64];
end
end
end else begin
assign app_rd_data_to_axi = app_rd_data;
end
endgenerate
mig_7series_v4_0_ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr),
.rst (reset),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.ecc_single (ecc_single),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
// ECC ports
.app_raw_not_ecc (app_raw_not_ecc),
.app_ecc_multiple_err (app_ecc_multiple_err_o),
.app_ecc_single_err (app_ecc_single_err),
.app_correct_en (app_correct_en_i),
.app_sr_req (app_sr_req),
.sr_req (app_sr_req_i),
.sr_active (app_sr_active_i),
.app_sr_active (app_sr_active),
.app_ref_req (app_ref_req),
.ref_req (app_ref_req_i),
.ref_ack (app_ref_ack_i),
.app_ref_ack (app_ref_ack),
.app_zq_req (app_zq_req),
.zq_req (app_zq_req_i),
.zq_ack (app_zq_ack_i),
.app_zq_ack (app_zq_ack)
);
mig_7series_v4_0_axi_mc #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_MC_DATA_WIDTH (C_MC_DATA_WIDTH_LCL),
.C_MC_ADDR_WIDTH (ADDR_WIDTH),
.C_MC_BURST_MODE (BURST_MODE),
.C_MC_nCK_PER_CLK (nCK_PER_CLK),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.C_RD_WR_ARB_ALGORITHM (C_RD_WR_ARB_ALGORITHM),
.C_S_AXI_REG_EN0 (C_S_AXI_REG_EN0),
.C_S_AXI_REG_EN1 (C_S_AXI_REG_EN1),
.C_ECC (ECC)
)
u_axi_mc
(
.aclk (clk),
.aresetn (aresetn),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (s_axi_awqos),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (s_axi_arqos),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// MC Master Interface
//CMD PORT
.mc_app_en (app_en),
.mc_app_cmd (app_cmd),
.mc_app_sz (app_sz),
.mc_app_addr (app_addr),
.mc_app_hi_pri (app_hi_pri),
.mc_app_rdy (app_rdy),
.mc_init_complete (init_calib_complete_r),
//DATA PORT
.mc_app_wdf_wren (app_wdf_wren),
.mc_app_wdf_mask (app_wdf_mask_axi_o),
.mc_app_wdf_data (app_wdf_data_axi_o),
.mc_app_wdf_end (app_wdf_end),
.mc_app_wdf_rdy (app_wdf_rdy),
.mc_app_rd_valid (app_rd_data_valid),
.mc_app_rd_data (app_rd_data_to_axi),
.mc_app_rd_end (app_rd_data_end),
.mc_app_ecc_multiple_err (app_ecc_multiple_err_o)
);
generate
if (ECC == "ON") begin : gen_axi_ctrl_top
reg [2*nCK_PER_CLK*DQ_WIDTH-1:0] dbg_rddata_r;
mig_7series_v4_0_axi_ctrl_top #
(
.C_S_AXI_CTRL_ADDR_WIDTH (C_S_AXI_CTRL_ADDR_WIDTH) ,
.C_S_AXI_CTRL_DATA_WIDTH (C_S_AXI_CTRL_DATA_WIDTH) ,
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH) ,
.C_S_AXI_BASEADDR (C_S_AXI_BASEADDR) ,
.C_ECC_TEST (ECC_TEST) ,
.C_DQ_WIDTH (DQ_WIDTH) ,
.C_ECC_WIDTH (ECC_WIDTH) ,
.C_MEM_ADDR_ORDER (MEM_ADDR_ORDER) ,
.C_BANK_WIDTH (BANK_WIDTH) ,
.C_ROW_WIDTH (ROW_WIDTH) ,
.C_COL_WIDTH (COL_WIDTH) ,
.C_ECC_ONOFF_RESET_VALUE (C_ECC_ONOFF_RESET_VALUE) ,
.C_ECC_CE_COUNTER_WIDTH (C_ECC_CE_COUNTER_WIDTH) ,
.C_NCK_PER_CLK (nCK_PER_CLK) ,
.C_MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH)
)
axi_ctrl_top_0
(
.aclk (clk) ,
.aresetn (aresetn) ,
.s_axi_awvalid (s_axi_ctrl_awvalid) ,
.s_axi_awready (s_axi_ctrl_awready) ,
.s_axi_awaddr (s_axi_ctrl_awaddr) ,
.s_axi_wvalid (s_axi_ctrl_wvalid) ,
.s_axi_wready (s_axi_ctrl_wready) ,
.s_axi_wdata (s_axi_ctrl_wdata) ,
.s_axi_bvalid (s_axi_ctrl_bvalid) ,
.s_axi_bready (s_axi_ctrl_bready) ,
.s_axi_bresp (s_axi_ctrl_bresp) ,
.s_axi_arvalid (s_axi_ctrl_arvalid) ,
.s_axi_arready (s_axi_ctrl_arready) ,
.s_axi_araddr (s_axi_ctrl_araddr) ,
.s_axi_rvalid (s_axi_ctrl_rvalid) ,
.s_axi_rready (s_axi_ctrl_rready) ,
.s_axi_rdata (s_axi_ctrl_rdata) ,
.s_axi_rresp (s_axi_ctrl_rresp) ,
.interrupt (interrupt) ,
.init_complete (init_calib_complete_r) ,
.ecc_single (ecc_single) ,
.ecc_multiple (ecc_multiple) ,
.ecc_err_addr (ecc_err_addr) ,
.app_correct_en (app_correct_en) ,
.dfi_rddata (dbg_rddata_r) ,
.fi_xor_we (fi_xor_we) ,
.fi_xor_wrdata (fi_xor_wrdata)
);
// dbg_rddata delayed one cycle to match ecc_*
always @(posedge clk) begin
dbg_rddata_r <= dbg_rddata;
end
//if(ECC_TEST == "ON") begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b1}};
// assign app_correct_en_i = 'b0 ;
//end else begin
// assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
// assign app_correct_en_i = app_correct_en ;
//end
assign app_raw_not_ecc = {2*nCK_PER_CLK{1'b0}};
assign app_correct_en_i = app_correct_en ;
end
else begin : gen_no_axi_ctrl_top
assign s_axi_ctrl_awready = 1'b0;
assign s_axi_ctrl_wready = 1'b0;
assign s_axi_ctrl_bvalid = 1'b0;
assign s_axi_ctrl_bresp = 2'b0;
assign s_axi_ctrl_arready = 1'b0;
assign s_axi_ctrl_rvalid = 1'b0;
assign s_axi_ctrl_rdata = {C_S_AXI_CTRL_DATA_WIDTH{1'b0}};
assign s_axi_ctrl_rresp = 2'b0;
assign interrupt = 1'b0;
assign app_correct_en = 1'b1;
assign app_raw_not_ecc = 4'b0;
assign fi_xor_we = {DQ_WIDTH/8{1'b0}};
assign fi_xor_wrdata = {DQ_WIDTH{1'b0}};
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_PP_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKDLYINV3SD1_BEHAVIORAL_PP_V |
/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
module test_fg_bd_fifo;
// Parameters
parameter ADDR_WIDTH = 10;
parameter DEST_WIDTH = 8;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg input_bd_valid = 0;
reg [7:0] input_bd_dest = 0;
reg [31:0] input_bd_burst_len = 0;
reg output_bd_ready = 0;
// Outputs
wire input_bd_ready;
wire output_bd_valid;
wire [7:0] output_bd_dest;
wire [31:0] output_bd_burst_len;
wire [ADDR_WIDTH-1:0] count;
wire [ADDR_WIDTH+32-1:0] byte_count;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_bd_valid,
input_bd_dest,
input_bd_burst_len,
output_bd_ready);
$to_myhdl(input_bd_ready,
output_bd_valid,
output_bd_dest,
output_bd_burst_len,
count,
byte_count);
// dump file
$dumpfile("test_fg_bd_fifo.lxt");
$dumpvars(0, test_fg_bd_fifo);
end
fg_bd_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEST_WIDTH(DEST_WIDTH)
)
UUT (
.clk(clk),
.rst(rst),
// burst descriptor input
.input_bd_valid(input_bd_valid),
.input_bd_ready(input_bd_ready),
.input_bd_dest(input_bd_dest),
.input_bd_burst_len(input_bd_burst_len),
// burst descriptor output
.output_bd_valid(output_bd_valid),
.output_bd_ready(output_bd_ready),
.output_bd_dest(output_bd_dest),
.output_bd_burst_len(output_bd_burst_len),
// status
.count(count),
.byte_count(byte_count)
);
endmodule
|
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