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// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`include "verilated.v"
module t;
// Note $sscanf already tested elsewhere
reg [3:0] n;
reg [63:0] q;
reg [16*8:1] wide;
reg [8:1] ochar;
reg [48*8:1] str;
reg [48*8:1] str2;
string str3;
real r;
initial begin
n = 4'b1100;
q = 64'h1234_5678_abcd_0123;
wide = "hello-there12345";
$sformat(str, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str=%0s",str); `endif
if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop;
q = {q[62:0],1'b1};
$swrite(str2, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
str3 = $sformatf("n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str3=%0s",str3); `endif
if (str3 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
$swrite(str2, "e=%e", r);
$swrite(str2, "e=%f", r);
$swrite(str2, "e=%g", r);
r = 0.01;
$swrite(str2, "e=%e f=%f g=%g", r, r, r);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop;
$swrite(str2, "mod=%m");
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "mod=top.t") $stop;
$swrite(str2, "lib=%l");
`ifdef TEST_VERBOSE $display("chkl %0s",str2); `endif
if (str2 !== "lib=t") $stop;
str3 = $sformatf("u=%u", {"a","b","c","d"}); // Value selected so is printable
`ifdef TEST_VERBOSE $display("chku %s %s",str3,str3); `endif
if (str3 !== "u=dcba") $stop;
str3 = $sformatf("v=%v", {"a","b","c","d"}); // Value selected so is printable
`ifdef TEST_VERBOSE $display("chkv %s %s",str3,str3); `endif
$sformat(ochar,"%s","c");
if (ochar != "c") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
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/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_TB_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_TB_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkdlyinv3sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__clkdlyinv3sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_TB_V
|
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
(* altera_attribute = "-name MESSAGE_DISABLE 14130", altera_attribute = "-name SYNCHRONIZER_IDENTIFICATION OFF" *) module ddr3_int_phy_alt_mem_phy (
//Clock and reset inputs:
pll_ref_clk,
global_reset_n,
soft_reset_n,
// Used to indicate PLL loss of lock for system reset management:
reset_request_n,
// Clock and reset for the controller interface:
ctl_clk,
ctl_reset_n,
// Write data interface:
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_wlat,
// Address and command interface:
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
// Read data interface:
ctl_doing_rd,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
//re-calibration request & configuration:
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
//Calibration status interface:
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
//ports to memory device(s):
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_clk,
mem_clk_n,
mem_reset_n,
// Bidirectional Memory interface signals:
mem_dq,
mem_dqs,
mem_dqs_n,
// Auxiliary clocks. Some systems may need these for debugging
// purposes, or for full-rate to half-rate bridge interfaces
aux_half_rate_clk,
aux_full_rate_clk,
// On Chip Termination: - dynamically updated values.
oct_ctl_rs_value,
oct_ctl_rt_value,
// DLL import/export ports
dqs_offset_delay_ctrl,
dqs_delay_ctrl_import,
dqs_delay_ctrl_export,
dll_reference_clk,
// Debug interface:- ALTERA USE ONLY
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
dbg_rd_data,
dbg_waitrequest
);
// Default parameter values :
parameter FAMILY = "CYCLONEIII";
parameter MEM_IF_MEMTYPE = "DDR2";
parameter SPEED_GRADE = "C6";
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 8;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter DQS_OUT_MODE = "DELAY_CHAIN2";
parameter DQS_PHASE = 9000;
parameter DQS_PHASE_SETTING = 2;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_ADDR_WIDTH = 13;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_OCT_EN = 0;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_MR_0 = 0;
parameter MEM_IF_MR_1 = 0;
parameter MEM_IF_MR_2 = 0;
parameter MEM_IF_MR_3 = 0;
parameter MEM_IF_PRESET_RLAT = 0;
parameter PLL_STEPS_PER_CYCLE = 24;
parameter SCAN_CLK_DIVIDE_BY = 4;
parameter REDUCE_SIM_TIME = 0;
parameter CAPABILITIES = 0;
parameter TINIT_TCK = 40000;
parameter TINIT_RST = 100000;
parameter DBG_A_WIDTH = 13;
parameter SEQ_STRING_ID = "seq_name";
parameter MEM_IF_CS_PER_RANK = 1; // duplicates CS, CKE, ODT, sequencer still controls 1 rank, but it is subdivided from controller perspective.
parameter MEM_IF_RANKS_PER_SLOT = 1; // how ranks are arranged into slot - needed for odt setting in the sequencer
parameter MEM_IF_RDV_PER_CHIP = 0; // multiple chips, and which gives valid data
parameter GENERATE_ADDITIONAL_DBG_RTL = 0; // DDR2 sequencer specific
parameter CAPTURE_PHASE_OFFSET = 0;
parameter MEM_IF_ADDR_CMD_PHASE = 0;
parameter DLL_EXPORT_IMPORT = "NONE";
parameter MEM_IF_DQSN_EN = 1;
parameter RANK_HAS_ADDR_SWAP = 0;
parameter INVERT_POSTAMBLE_CLK = "false";
//
localparam phy_report_prefix = "ddr3_int_phy_alt_mem_phy (top level) : ";
localparam POSTAMBLE_AWIDTH = 6;
localparam POSTAMBLE_HALFT_EN = 0;
localparam POSTAMBLE_INITIAL_LAT = 16;
localparam POSTAMBLE_RESYNC_LAT_CTL_EN = 0;
// function to set the USE_MEM_CLK_FOR_ADDR_CMD_CLK localparam based on MEM_IF_ADDR_CMD_PHASE
function integer set_mem_clk_for_ac_clk (input reg [23:0] addr_cmd_phase);
integer return_value;
begin
return_value = 0;
case (addr_cmd_phase)
0, 180 : return_value = 1;
90, 270 : return_value = 0;
default : begin
//synthesis translate_off
$display(phy_report_prefix, "Illegal value set on MEM_IF_ADDR_CMD_PHASE parameter: ", addr_cmd_phase);
$stop;
//synthesis translate_on
end
endcase
set_mem_clk_for_ac_clk = return_value;
end
endfunction
// function to set the ADDR_CMD_NEGEDGE_EN localparam based on MEM_IF_ADDR_CMD_PHASE
function integer set_ac_negedge_en(input reg [23:0] addr_cmd_phase);
integer return_value;
begin
return_value = 0;
case (addr_cmd_phase)
90, 180 : return_value = 1;
0, 270 : return_value = 0;
default : begin
//synthesis translate_off
$display(phy_report_prefix, "Illegal value set on MEM_IF_ADDR_CMD_PHASE parameter: ", addr_cmd_phase);
$stop;
//synthesis translate_on
end
endcase
set_ac_negedge_en = return_value;
end
endfunction
localparam USE_MEM_CLK_FOR_ADDR_CMD_CLK = set_mem_clk_for_ac_clk(MEM_IF_ADDR_CMD_PHASE);
localparam ADDR_CMD_NEGEDGE_EN = set_ac_negedge_en(MEM_IF_ADDR_CMD_PHASE);
localparam LOCAL_IF_DWIDTH = MEM_IF_DWIDTH*DWIDTH_RATIO;
localparam MEM_IF_POSTAMBLE_EN_WIDTH = MEM_IF_DWIDTH/MEM_IF_DQ_PER_DQS;
localparam LOCAL_IF_CLK_PS = MEM_IF_CLK_PS/(DWIDTH_RATIO/2);
localparam PLL_REF_CLK_PS = LOCAL_IF_CLK_PS;
localparam MEM_IF_DQS_CAPTURE_EN = 1;
localparam ADDR_COUNT_WIDTH = 4;
localparam RDP_RESYNC_LAT_CTL_EN = 0;
localparam DEDICATED_MEMORY_CLK_EN = 0;
localparam ADV_LAT_WIDTH = 5;
localparam CAPTURE_MIMIC_PATH = 0;
localparam DDR_MIMIC_PATH_EN = 1;
localparam MIMIC_DEBUG_EN = 0;
localparam NUM_MIMIC_SAMPLE_CYCLES = 6;
localparam NUM_DEBUG_SAMPLES_TO_STORE = 4096;
localparam ASYNCHRONOUS_AVALON_CLOCK = 1;
localparam RDV_INITIAL_LAT = ((DWIDTH_RATIO == 2) && (MEM_IF_MEMTYPE == "DDR2")) ? 25 : 23;
localparam RDP_INITIAL_LAT = 6;
localparam RESYNC_PIPELINE_DEPTH = 0;
localparam CLOCK_INDEX_WIDTH = 3;
localparam OCT_LAT_WIDTH = ADV_LAT_WIDTH;
// I/O Signal definitions :
// Clock and reset I/O :
input wire pll_ref_clk;
input wire global_reset_n;
input wire soft_reset_n;
// This is the PLL locked signal :
output wire reset_request_n;
// The controller must use this phy_clk to interface to the PHY. It is
// optional as to whether the remainder of the system uses it :
output wire ctl_clk;
output wire ctl_reset_n;
// new AFI I/Os - write data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_dqs_burst;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_wdata_valid;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_wdata;
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO -1 : 0] ctl_dm;
output wire [4 : 0] ctl_wlat;
// new AFI I/Os - addr/cmd i/f:
input wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_addr;
input wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : 0] ctl_ba;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_cas_n;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_cke;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_cs_n;
input wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1:0] ctl_odt;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_ras_n;
input wire [1 * DWIDTH_RATIO/2 -1 : 0] ctl_we_n;
input wire [DWIDTH_RATIO/2 - 1 : 0] ctl_rst_n;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctl_mem_clk_disable;
// new AFI I/Os - read data i/f:
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
output wire [MEM_IF_DWIDTH * DWIDTH_RATIO -1 : 0] ctl_rdata;
output wire [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output wire [4 : 0] ctl_rlat;
// re-calibration request and configuration:
input wire ctl_cal_req;
input wire [MEM_IF_DQS_WIDTH * MEM_IF_CS_WIDTH - 1 : 0] ctl_cal_byte_lane_sel_n;
// new AFI I/Os - status interface:
output wire ctl_cal_success;
output wire ctl_cal_fail;
output wire ctl_cal_warning;
//Outputs to DIMM :
output wire [MEM_IF_ADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
wire [MEM_IF_DWIDTH - 1 : 0] mem_d;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
output wire mem_reset_n;
//The mem_clks are outputs, but one is sometimes used for the mimic_path, so
//is looped back in. Therefore defining as an inout ensures no errors in Quartus :
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
//Bidirectional:
inout tri [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs;
inout tri [MEM_IF_DWIDTH / MEM_IF_DQ_PER_DQS - 1 : 0] mem_dqs_n;
input wire [`OCT_SERIES_TERM_CONTROL_WIDTH -1 : 0] oct_ctl_rs_value;
input wire [`OCT_PARALLEL_TERM_CONTROL_WIDTH -1 : 0] oct_ctl_rt_value;
// DQS offsetting is possible with the ArriaII hardware, however this is unsupported by the IP
// in this release :
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_offset_delay_ctrl;
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_import;
output wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_export;
output wire dll_reference_clk;
// AVALON MM Slave -- debug IF
input wire dbg_clk;
input wire dbg_reset_n;
input wire [DBG_A_WIDTH -1 : 0] dbg_addr;
input wire dbg_wr;
input wire dbg_rd;
input wire dbg_cs;
input wire [31 : 0] dbg_wr_data;
output wire [31 : 0] dbg_rd_data;
output wire dbg_waitrequest;
// Auxillary clocks. These do not have to be connected if the system
// doesn't require them :
output wire aux_half_rate_clk;
output wire aux_full_rate_clk;
// Internal signal declarations :
// Clocks :
// full-rate memory clock
wire mem_clk_2x;
// write_clk_2x is a full-rate write clock. It is -90 degress aligned to the
// system clock :
wire write_clk_2x;
wire phy_clk_1x_src;
wire phy_clk_1x;
wire ac_clk_1x;
wire ac_clk_2x;
wire cs_n_clk_1x;
wire cs_n_clk_2x;
wire postamble_clk_2x;
wire resync_clk_2x;
wire measure_clk_1x;
wire measure_clk_2x;
wire half_rate_clk;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl;
// resets, async assert, de-assert is sync'd to each clock domain
wire reset_mem_clk_2x_n;
wire reset_rdp_phy_clk_1x_n;
wire reset_phy_clk_1x_n;
wire reset_ac_clk_1x_n;
wire reset_ac_clk_2x_n;
wire reset_cs_n_clk_1x_n;
wire reset_cs_n_clk_2x_n;
wire reset_mimic_2x_n;
wire [MEM_IF_DQS_WIDTH - 1 : 0] reset_resync_clk_1x_n;
wire reset_resync_clk_2x_n;
wire reset_seq_n;
wire reset_measure_clk_1x_n;
wire reset_measure_clk_2x_n;
wire reset_poa_clk_2x_n;
wire reset_write_clk_2x_n;
// Misc signals :
wire phs_shft_busy;
wire pll_seq_reconfig_busy;
// Postamble signals :
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO /2 - 1 : 0] poa_postamble_en_preset;
wire [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] poa_postamble_en_preset_2x;
// Sequencer signals
wire seq_mmc_start;
wire seq_pll_inc_dec_n;
wire seq_pll_start_reconfig;
wire [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_dec_read_lat_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_rdp_inc_read_lat_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_poa_lat_dec_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_poa_lat_inc_1x;
wire seq_poa_protection_override_1x;
wire seq_rdp_reset_req_n;
wire seq_ac_sel;
wire [MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_addr;
wire [MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_ba;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_cas_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_ras_n;
wire [DWIDTH_RATIO/2 -1 : 0] seq_ac_we_n;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cke;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_cs_n;
wire [MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_ac_odt;
wire [DWIDTH_RATIO * MEM_IF_DM_WIDTH - 1 : 0 ] seq_wdp_dm;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_dqs_burst;
wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0 ] seq_wdp_wdata;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] seq_wdp_wdata_valid;
wire [DWIDTH_RATIO - 1 :0] seq_wdp_dqs;
wire seq_wdp_ovride;
wire [MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2) - 1 : 0] oct_rsst_sel;
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_doing_rd;
wire seq_rdata_valid_lat_inc;
wire seq_rdata_valid_lat_dec;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_rdata_valid;
reg [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dedicated_dll_delay_ctrl_r;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl_internal;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl; // Output from clk_reset block
// set pll clock index of resync and mimic clocks
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_resync_clk_index;
wire [CLOCK_INDEX_WIDTH - 1 : 0] pll_measure_clk_index;
// The clk_reset block provides the sc_clk to the sequencer and DP blocks.
wire sc_clk;
wire [MEM_IF_DQS_WIDTH - 1 : 0] sc_clk_dp;
// Mimic signals :
wire mmc_seq_done;
wire mmc_seq_value;
wire mimic_data;
wire mux_seq_controller_ready;
wire mux_seq_wdata_req;
// Read datapath signals :
// Connections from the IOE to the read datapath :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_h_2x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata_l_2x;
// Write datapath signals :
// wires from the wdp to the dpio :
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata0_1x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x;
wire [(LOCAL_IF_DWIDTH/8) - 1 : 0] ctl_mem_be;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdata_oe_l_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs3_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs2_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs1_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs0_1x;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_2x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_h_1x;
wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_dqs_oe_l_1x;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm3_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm2_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm1_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm0_1x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x;
wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_h_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] wdp_oct_l_1x;
wire [MEM_IF_DQS_WIDTH -1 : 0] seq_dqs_add_2t_delay;
wire ctl_add_1t_ac_lat_internal;
wire ctl_add_1t_odt_lat_internal;
wire ctl_add_intermediate_regs_internal;
wire ctl_negedge_en_internal;
wire ctl_mem_dqs_burst;
wire [MEM_IF_DWIDTH*DWIDTH_RATIO - 1 : 0] ctl_mem_wdata;
wire ctl_mem_wdata_valid;
// These ports are tied off for DDR,DDR2,DDR3. Registers are used to reduce Quartus warnings :
(* preserve *) reg [3 : 0] ctl_mem_dqs = 4'b1100;
wire [MEM_IF_CS_WIDTH - 1 : 0] int_rank_has_addr_swap;
//SIII declarations :
//Outputs from the dp_io block to the read_dp block :
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata3_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata2_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata1_1x;
wire [MEM_IF_DWIDTH - 1 : 0] dio_rdata0_1x;
wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_delay; // oct_lat
wire [OCT_LAT_WIDTH - 1 : 0] seq_oct_oct_extend; //oct_extend_duration
wire seq_oct_val;
wire seq_mem_clk_disable;
wire [DWIDTH_RATIO/2 - 1 : 0] seq_ac_rst_n;
wire dqs_delay_update_en;
wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dlloffset_offsetctrl_out;
// Use either the imported DQS delay or the clock/reset output :
generate
if (DLL_EXPORT_IMPORT == "IMPORT")
assign dqs_delay_ctrl_internal = dqs_delay_ctrl_import;
else
assign dqs_delay_ctrl_internal = dqs_delay_ctrl;
endgenerate
// Generate auxillary clocks:
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin
assign aux_half_rate_clk = phy_clk_1x;
assign aux_full_rate_clk = mem_clk_2x;
end
// Full-rate mode :
else
begin
assign aux_half_rate_clk = half_rate_clk;
assign aux_full_rate_clk = phy_clk_1x;
end
endgenerate
// The top level I/O should not have the "Nx" clock domain suffices, so this is
// assigned here. Also note that to avoid delta delay issues both the external and
// internal phy_clks are assigned to a common 'src' clock :
assign ctl_clk = phy_clk_1x_src;
assign phy_clk_1x = phy_clk_1x_src;
assign ctl_reset_n = reset_phy_clk_1x_n;
// Export the internally generated DQS delay :
assign dqs_delay_ctrl_export = dqs_delay_ctrl;
assign dll_reference_clk = mem_clk_2x;
// Instance I/O modules :
//
ddr3_int_phy_alt_mem_phy_dp_io #(
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_DM_PINS_EN (MEM_IF_DM_PINS_EN),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.MEM_IF_POSTAMBLE_EN_WIDTH (MEM_IF_POSTAMBLE_EN_WIDTH),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH)
) dpio (
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.resync_clk_2x (resync_clk_2x),
.postamble_clk_2x (postamble_clk_2x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.dqs_delay_ctrl (dqs_delay_ctrl_internal),
.mem_dm (mem_dm),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqsn (mem_dqs_n),
.dio_rdata_h_2x (dio_rdata_h_2x),
.dio_rdata_l_2x (dio_rdata_l_2x),
.poa_postamble_en_preset_2x (poa_postamble_en_preset_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x)
);
// Instance the read datapath :
//
ddr3_int_phy_alt_mem_phy_read_dp #(
.ADDR_COUNT_WIDTH (ADDR_COUNT_WIDTH),
.BIDIR_DPINS (1),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.FAMILY (FAMILY),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.RDP_INITIAL_LAT (RDP_INITIAL_LAT),
.RDP_RESYNC_LAT_CTL_EN (RDP_RESYNC_LAT_CTL_EN),
.RESYNC_PIPELINE_DEPTH (RESYNC_PIPELINE_DEPTH)
) rdp (
.phy_clk_1x (phy_clk_1x),
.resync_clk_2x (resync_clk_2x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x[0]),
.seq_rdp_dmx_swap (1'b0),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x[0]),
.dio_rdata_h_2x (dio_rdata_h_2x),
.dio_rdata_l_2x (dio_rdata_l_2x),
.ctl_mem_rdata (ctl_rdata)
);
// enhancements a different delay per dqs group may be implemented using the
// full vector
// Instance the write datapath :
generate
// Half-rate Write datapath :
if (DWIDTH_RATIO == 4)
begin : half_rate_wdp_gen
//
ddr3_int_phy_alt_mem_phy_write_dp #(
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("HALF"),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) wdp (
.phy_clk_1x (phy_clk_1x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_ctl_sel (seq_wdp_ovride),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x)
);
end
// Full-rate :
else
begin : full_rate_wdp_gen
//
ddr3_int_phy_alt_mem_phy_write_dp_fr #(
.BIDIR_DPINS (1),
.LOCAL_IF_DRATE ("FULL"),
.LOCAL_IF_DWIDTH (LOCAL_IF_DWIDTH),
.MEM_IF_DM_WIDTH (MEM_IF_DM_WIDTH),
.MEM_IF_DQ_PER_DQS (MEM_IF_DQ_PER_DQS),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.GENERATE_WRITE_DQS (1),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.DWIDTH_RATIO (DWIDTH_RATIO)
) wdp (
.phy_clk_1x (phy_clk_1x),
.mem_clk_2x (mem_clk_2x),
.write_clk_2x (write_clk_2x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.ctl_mem_be (ctl_dm),
.ctl_mem_dqs_burst (ctl_dqs_burst),
.ctl_mem_wdata (ctl_wdata),
.ctl_mem_wdata_valid (ctl_wdata_valid),
.seq_be (seq_wdp_dm),
.seq_dqs_burst (seq_wdp_dqs_burst),
.seq_wdata (seq_wdp_wdata),
.seq_wdata_valid (seq_wdp_wdata_valid),
.seq_ctl_sel (seq_wdp_ovride),
.wdp_wdata_h_2x (wdp_wdata_h_2x),
.wdp_wdata_l_2x (wdp_wdata_l_2x),
.wdp_wdata_oe_2x (wdp_wdata_oe_2x),
.wdp_wdqs_2x (wdp_wdqs_2x),
.wdp_wdqs_oe_2x (wdp_wdqs_oe_2x),
.wdp_dm_h_2x (wdp_dm_h_2x),
.wdp_dm_l_2x (wdp_dm_l_2x)
);
end
endgenerate
// Instance the address and command :
// A CIII ADC block is used, as the ADC clock may be set to one of four quadrant positions,
// not an arbitrary PLL phase :
generate
// Half-rate address and command :
if (DWIDTH_RATIO == 4)
begin : half_rate_adc_gen
//
ddr3_int_phy_alt_mem_phy_addr_cmd #(
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH)
) adc (
.ac_clk_1x (ac_clk_1x),
.ac_clk_2x (ac_clk_2x),
.cs_n_clk_1x (cs_n_clk_1x),
.cs_n_clk_2x (cs_n_clk_2x),
.phy_clk_1x (phy_clk_1x),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_cs_n_clk_1x_n (reset_cs_n_clk_1x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
// .ctl_negedge_en (ctl_negedge_en_internal),
.ctl_negedge_en (ADDR_CMD_NEGEDGE_EN[0 : 0]),
.ctl_mem_addr_h (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_addr_l (ctl_addr[(MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2) -1 : MEM_IF_ADDR_WIDTH]),
.ctl_mem_ba_h (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.ctl_mem_cas_n_h (ctl_cas_n[0]),
.ctl_mem_cas_n_l (ctl_cas_n[1]),
.ctl_mem_cke_h (ctl_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cke_l (ctl_cke[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_cs_n_h (ctl_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_odt_h (ctl_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_odt_l (ctl_odt[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.ctl_mem_ras_n_h (ctl_ras_n[0]),
.ctl_mem_ras_n_l (ctl_ras_n[1]),
.ctl_mem_we_n_h (ctl_we_n[0]),
.ctl_mem_we_n_l (ctl_we_n[1]),
.ctl_mem_rst_n_h (ctl_rst_n[0]),
.ctl_mem_rst_n_l (ctl_rst_n[1]),
.seq_addr_h (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_ADDR_WIDTH]),
.seq_ba_h (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH * DWIDTH_RATIO/2 -1 : MEM_IF_BANKADDR_WIDTH]),
.seq_cas_n_h (seq_ac_cas_n[0]),
.seq_cas_n_l (seq_ac_cas_n[1]),
.seq_cke_h (seq_ac_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cke_l (seq_ac_cke[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_cs_n_h (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_odt_h (seq_ac_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_odt_l (seq_ac_odt[MEM_IF_CS_WIDTH * DWIDTH_RATIO/2 - 1 : MEM_IF_CS_WIDTH]),
.seq_ras_n_h (seq_ac_ras_n[0]),
.seq_ras_n_l (seq_ac_ras_n[1]),
.seq_we_n_h (seq_ac_we_n[0]),
.seq_we_n_l (seq_ac_we_n[1]),
.seq_mem_rst_n_h (seq_ac_rst_n[0]),
.seq_mem_rst_n_l (seq_ac_rst_n[1]),
.seq_ac_sel (seq_ac_sel),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n),
.mem_rst_n (mem_reset_n)
);
end
// Full-rate :
else
begin : full_rate_adc_gen
//
ddr3_int_phy_alt_mem_phy_addr_cmd #(
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_ADDR_CMD_BUS_COUNT (1),
.MEM_IF_BANKADDR_WIDTH (MEM_IF_BANKADDR_WIDTH),
.MEM_IF_CS_WIDTH (MEM_IF_CS_WIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_ROWADDR_WIDTH (MEM_IF_ADDR_WIDTH)
) adc (
.ac_clk_1x (ac_clk_1x),
.ac_clk_2x (ac_clk_2x),
.cs_n_clk_1x (cs_n_clk_1x),
.cs_n_clk_2x (cs_n_clk_2x),
.phy_clk_1x (phy_clk_1x),
.reset_ac_clk_1x_n (reset_ac_clk_1x_n),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_cs_n_clk_1x_n (reset_cs_n_clk_1x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs_internal),
// .ctl_negedge_en (ctl_negedge_en_internal),
.ctl_negedge_en (ADDR_CMD_NEGEDGE_EN[0 : 0]),
.ctl_mem_addr_h (),
.ctl_mem_addr_l (ctl_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.ctl_mem_ba_h (),
.ctl_mem_ba_l (ctl_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.ctl_mem_cas_n_h (),
.ctl_mem_cas_n_l (ctl_cas_n[0]),
.ctl_mem_cke_h (),
.ctl_mem_cke_l (ctl_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_cs_n_h (),
.ctl_mem_cs_n_l (ctl_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_odt_h (),
.ctl_mem_odt_l (ctl_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.ctl_mem_ras_n_h (),
.ctl_mem_ras_n_l (ctl_ras_n[0]),
.ctl_mem_we_n_h (),
.ctl_mem_we_n_l (ctl_we_n[0]),
.ctl_mem_rst_n_h (),
.ctl_mem_rst_n_l (ctl_rst_n[0]),
.seq_addr_h (),
.seq_addr_l (seq_ac_addr[MEM_IF_ADDR_WIDTH -1 : 0]),
.seq_ba_h (),
.seq_ba_l (seq_ac_ba[MEM_IF_BANKADDR_WIDTH -1 : 0]),
.seq_cas_n_h (),
.seq_cas_n_l (seq_ac_cas_n[0]),
.seq_cke_h (),
.seq_cke_l (seq_ac_cke[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_cs_n_h (),
.seq_cs_n_l (seq_ac_cs_n[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_odt_h (),
.seq_odt_l (seq_ac_odt[MEM_IF_CS_WIDTH - 1 : 0]),
.seq_ras_n_h (),
.seq_ras_n_l (seq_ac_ras_n[0]),
.seq_we_n_h (),
.seq_we_n_l (seq_ac_we_n[0]),
.seq_mem_rst_n_h (),
.seq_mem_rst_n_l (seq_ac_rst_n[0]),
.seq_ac_sel (seq_ac_sel),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_cs_n (mem_cs_n),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_we_n (mem_we_n),
.mem_rst_n (mem_reset_n)
);
end
endgenerate
//
ddr3_int_phy_alt_mem_phy_postamble #(
.FAMILY (FAMILY),
.DWIDTH_RATIO (DWIDTH_RATIO),
.MEM_IF_POSTAMBLE_EN_WIDTH (MEM_IF_POSTAMBLE_EN_WIDTH),
.POSTAMBLE_AWIDTH (POSTAMBLE_AWIDTH),
.POSTAMBLE_HALFT_EN (POSTAMBLE_HALFT_EN),
.POSTAMBLE_INITIAL_LAT (POSTAMBLE_INITIAL_LAT),
.POSTAMBLE_RESYNC_LAT_CTL_EN (POSTAMBLE_RESYNC_LAT_CTL_EN)
) poa (
.phy_clk_1x (phy_clk_1x),
.poa_postamble_en_preset_2x (poa_postamble_en_preset_2x),
.postamble_clk_2x (postamble_clk_2x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.reset_poa_clk_2x_n (reset_poa_clk_2x_n),
.ctl_doing_rd_beat1_1x (merged_doing_rd[0]),
.ctl_doing_rd_beat2_1x (DWIDTH_RATIO == 4 ? merged_doing_rd[MEM_IF_DQS_WIDTH] : merged_doing_rd[0]),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x[0]),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x[0]),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x)
);
// Generate the data postamble paths (merged_doing_rd)
assign merged_doing_rd = seq_doing_rd | (ctl_doing_rd & {((DWIDTH_RATIO/2) * MEM_IF_DQS_WIDTH) {ctl_cal_success}});
assign int_rank_has_addr_swap = RANK_HAS_ADDR_SWAP[MEM_IF_CS_WIDTH - 1 : 0];
assign pll_resync_clk_index = 5;
assign pll_measure_clk_index = 7;
//
ddr3_int_phy_alt_mem_phy_seq_wrapper
//
seq_wrapper (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.ctl_cal_success (ctl_cal_success),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_warning (ctl_cal_warning),
.ctl_cal_req (ctl_cal_req),
.int_RANK_HAS_ADDR_SWAP (int_rank_has_addr_swap),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.seq_pll_select (seq_pll_select),
.phs_shft_busy (phs_shft_busy),
.pll_resync_clk_index (pll_resync_clk_index),
.pll_measure_clk_index (pll_measure_clk_index),
.sc_clk_dp (),
.scan_enable_dqs_config (),
.scan_update (),
.scan_din (),
.scan_enable_ck (),
.scan_enable_dqs (),
.scan_enable_dqsn (),
.scan_enable_dq (),
.scan_enable_dm (),
.hr_rsc_clk (1'b0), // Halfrate resync clock not required for non-SIII style families.
.seq_ac_addr (seq_ac_addr),
.seq_ac_ba (seq_ac_ba),
.seq_ac_cas_n (seq_ac_cas_n),
.seq_ac_ras_n (seq_ac_ras_n),
.seq_ac_we_n (seq_ac_we_n),
.seq_ac_cke (seq_ac_cke),
.seq_ac_cs_n (seq_ac_cs_n),
.seq_ac_odt (seq_ac_odt),
.seq_ac_rst_n (seq_ac_rst_n),
.seq_ac_sel (seq_ac_sel),
.seq_mem_clk_disable (seq_mem_clk_disable),
.ctl_add_1t_ac_lat_internal (ctl_add_1t_ac_lat_internal),
.ctl_add_1t_odt_lat_internal (ctl_add_1t_odt_lat_internal),
.ctl_add_intermediate_regs_internal (ctl_add_intermediate_regs_internal),
.seq_rdv_doing_rd (seq_doing_rd),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.seq_rdp_inc_read_lat_1x (seq_rdp_inc_read_lat_1x),
.seq_rdp_dec_read_lat_1x (seq_rdp_dec_read_lat_1x),
.ctl_rdata (ctl_rdata),
.int_rdata_valid_1t (seq_rdata_valid),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.ctl_rlat (ctl_rlat),
.seq_poa_lat_dec_1x (seq_poa_lat_dec_1x),
.seq_poa_lat_inc_1x (seq_poa_lat_inc_1x),
.seq_poa_protection_override_1x (seq_poa_protection_override_1x),
.seq_oct_oct_delay (seq_oct_oct_delay),
.seq_oct_oct_extend (seq_oct_oct_extend),
.seq_oct_val (seq_oct_val),
.seq_wdp_dqs_burst (seq_wdp_dqs_burst),
.seq_wdp_wdata_valid (seq_wdp_wdata_valid),
.seq_wdp_wdata (seq_wdp_wdata),
.seq_wdp_dm (seq_wdp_dm),
.seq_wdp_dqs (seq_wdp_dqs),
.seq_wdp_ovride (seq_wdp_ovride),
.seq_dqs_add_2t_delay (seq_dqs_add_2t_delay),
.ctl_wlat (ctl_wlat),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mem_err_out_n (1'b1),
.parity_error_n (),
.dbg_clk (dbg_clk),
.dbg_reset_n (dbg_reset_n),
.dbg_addr (dbg_addr),
.dbg_wr (dbg_wr),
.dbg_rd (dbg_rd),
.dbg_cs (dbg_cs),
.dbg_wr_data (dbg_wr_data),
.dbg_rd_data (dbg_rd_data),
.dbg_waitrequest (dbg_waitrequest)
);
// Generate rdata_valid for sequencer and control blocks
//
ddr3_int_phy_alt_mem_phy_rdata_valid #(
.FAMILY (FAMILY),
.MEM_IF_DQS_WIDTH (MEM_IF_DQS_WIDTH),
.RDATA_VALID_AWIDTH (5),
.RDATA_VALID_INITIAL_LAT (RDV_INITIAL_LAT),
.DWIDTH_RATIO (DWIDTH_RATIO)
) rdv_pipe (
.phy_clk_1x (phy_clk_1x),
.reset_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.seq_rdata_valid_lat_dec (seq_rdata_valid_lat_dec),
.seq_rdata_valid_lat_inc (seq_rdata_valid_lat_inc),
.seq_doing_rd (seq_doing_rd),
.ctl_doing_rd (ctl_doing_rd),
.ctl_cal_success (ctl_cal_success),
.ctl_rdata_valid (ctl_rdata_valid),
.seq_rdata_valid (seq_rdata_valid)
);
// Instance the AII clock and reset :
//
ddr3_int_phy_alt_mem_phy_clk_reset #(
.CLOCK_INDEX_WIDTH (CLOCK_INDEX_WIDTH),
.DLL_EXPORT_IMPORT (DLL_EXPORT_IMPORT),
.DWIDTH_RATIO (DWIDTH_RATIO),
.LOCAL_IF_CLK_PS (LOCAL_IF_CLK_PS),
.MEM_IF_CLK_PAIR_COUNT (MEM_IF_CLK_PAIR_COUNT),
.MEM_IF_CLK_PS (MEM_IF_CLK_PS),
.MEM_IF_CLK_PS_STR (MEM_IF_CLK_PS_STR),
.MEM_IF_DWIDTH (MEM_IF_DWIDTH),
.MEM_IF_MEMTYPE (MEM_IF_MEMTYPE),
.MEM_IF_DQSN_EN (MEM_IF_DQSN_EN),
.DLL_DELAY_BUFFER_MODE (DLL_DELAY_BUFFER_MODE),
.DLL_DELAY_CHAIN_LENGTH (DLL_DELAY_CHAIN_LENGTH),
.SCAN_CLK_DIVIDE_BY (SCAN_CLK_DIVIDE_BY),
.USE_MEM_CLK_FOR_ADDR_CMD_CLK (USE_MEM_CLK_FOR_ADDR_CMD_CLK),
.DQS_DELAY_CTL_WIDTH (DQS_DELAY_CTL_WIDTH),
.INVERT_POSTAMBLE_CLK (INVERT_POSTAMBLE_CLK)
) clk (
.pll_ref_clk (pll_ref_clk),
.global_reset_n (global_reset_n),
.soft_reset_n (soft_reset_n),
.seq_rdp_reset_req_n (seq_rdp_reset_req_n),
.ac_clk_2x (ac_clk_2x),
.measure_clk_2x (measure_clk_2x),
.mem_clk_2x (mem_clk_2x),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.phy_clk_1x (phy_clk_1x_src),
.postamble_clk_2x (postamble_clk_2x),
.resync_clk_2x (resync_clk_2x),
.cs_n_clk_2x (cs_n_clk_2x),
.write_clk_2x (write_clk_2x),
.half_rate_clk (half_rate_clk),
.reset_ac_clk_2x_n (reset_ac_clk_2x_n),
.reset_measure_clk_2x_n (reset_measure_clk_2x_n),
.reset_mem_clk_2x_n (reset_mem_clk_2x_n),
.reset_phy_clk_1x_n (reset_phy_clk_1x_n),
.reset_poa_clk_2x_n (reset_poa_clk_2x_n),
.reset_resync_clk_2x_n (reset_resync_clk_2x_n),
.reset_write_clk_2x_n (reset_write_clk_2x_n),
.reset_cs_n_clk_2x_n (reset_cs_n_clk_2x_n),
.reset_rdp_phy_clk_1x_n (reset_rdp_phy_clk_1x_n),
.mem_reset_n (),
.reset_request_n (reset_request_n),
.dqs_delay_ctrl (dqs_delay_ctrl),
.phs_shft_busy (phs_shft_busy),
.seq_pll_inc_dec_n (seq_pll_inc_dec_n),
.seq_pll_select (seq_pll_select),
.seq_pll_start_reconfig (seq_pll_start_reconfig),
.mimic_data_2x (mimic_data),
.seq_clk_disable (seq_mem_clk_disable),
.ctrl_clk_disable (ctl_mem_clk_disable)
);
// Instance the mimic block :
//
ddr3_int_phy_alt_mem_phy_mimic #(
.NUM_MIMIC_SAMPLE_CYCLES (NUM_MIMIC_SAMPLE_CYCLES)
) mmc (
.measure_clk (measure_clk_2x),
.reset_measure_clk_n (reset_measure_clk_2x_n),
.mimic_data_in (mimic_data),
.seq_mmc_start (seq_mmc_start),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value)
);
// If required, instance the Mimic debug block. If the debug block is used, a top level input
// for mimic_recapture_debug_data should be created.
generate
if (MIMIC_DEBUG_EN == 1)
begin : create_mimic_debug_ram
//
ddr3_int_phy_alt_mem_phy_mimic_debug #(
.NUM_DEBUG_SAMPLES_TO_STORE (NUM_DEBUG_SAMPLES_TO_STORE),
.PLL_STEPS_PER_CYCLE (PLL_STEPS_PER_CYCLE)
) mmc_debug (
.measure_clk (measure_clk_1x),
.reset_measure_clk_n (reset_measure_clk_1x_n),
.mmc_seq_done (mmc_seq_done),
.mmc_seq_value (mmc_seq_value),
.mimic_recapture_debug_data (1'b0)
);
end
endgenerate
endmodule
`default_nettype wire
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_ac (
clk_2x,
reset_2x_n,
phy_clk_1x,
ctl_add_1t_ac_lat,
ctl_negedge_en,
ctl_add_intermediate_regs,
period_sel,
seq_ac_sel,
ctl_ac_h,
ctl_ac_l,
seq_ac_h,
seq_ac_l,
mem_ac );
parameter POWER_UP_HIGH = 1;
parameter DWIDTH_RATIO = 4;
// NB. clk_2x could be either ac_clk_2x or cs_n_clk_2x :
input wire clk_2x;
input wire reset_2x_n;
input wire phy_clk_1x;
input wire ctl_add_1t_ac_lat;
input wire ctl_negedge_en;
input wire ctl_add_intermediate_regs;
input wire period_sel;
input wire seq_ac_sel;
input wire ctl_ac_h;
input wire ctl_ac_l;
input wire seq_ac_h;
input wire seq_ac_l;
output wire mem_ac;
(* preserve *) reg ac_h_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_l_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_h_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_l_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_1t = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_r = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_2r = POWER_UP_HIGH[0];
(* preserve *) reg ac_2x_mux = POWER_UP_HIGH[0];
reg ac_2x_retime = POWER_UP_HIGH[0];
reg ac_2x_retime_r = POWER_UP_HIGH[0];
reg ac_2x_deg_choice = POWER_UP_HIGH[0];
reg ac_h;
reg ac_l;
wire reset_2x ;
assign reset_2x = ~reset_2x_n;
generate
if (DWIDTH_RATIO == 4) //HR
begin : hr_mux_gen
// Half Rate DDR memory types require an extra cycle of latency :
always @(posedge phy_clk_1x)
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l <= ctl_ac_l;
ac_h <= ctl_ac_h;
end
1'b1 :
begin
ac_l <= seq_ac_l;
ac_h <= seq_ac_h;
end
endcase
end //always
end
else // FR
begin : fr_passthru_gen
// Note that "_h" is unused in full-rate and no latency
// is required :
always @*
begin
casez(seq_ac_sel)
1'b0 :
begin
ac_l <= ctl_ac_l;
end
1'b1 :
begin
ac_l <= seq_ac_l;
end
endcase
end
end
endgenerate
generate
if (DWIDTH_RATIO == 4)
begin : half_rate
// Initial registering of inputs :
always @(posedge phy_clk_1x)
begin
ac_h_r <= ac_h;
ac_l_r <= ac_l;
end
// Select high and low phases periodically to create the _2x signal :
always @*
begin
casez(period_sel)
1'b0 : ac_2x = ac_l_2r;
1'b1 : ac_2x = ac_h_2r;
default : ac_2x = 1'bx; // X propagaton
endcase
end
always @(posedge clk_2x)
begin
// Second stage of registering - on clk_2x
ac_h_2r <= ac_h_r;
ac_l_2r <= ac_l_r;
// 1t registering - used if ctl_add_1t_ac_lat is true
ac_1t <= ac_2x;
// AC_PHASE==270 requires an extra cycle of delay :
ac_2x_deg_choice <= ac_1t;
// If not at AC_PHASE==270, ctl_add_intermediate_regs shall be zero :
if (ctl_add_intermediate_regs == 1'b0)
begin
if (ctl_add_1t_ac_lat == 1'b1)
begin
ac_2x_r <= ac_1t;
end
else
begin
ac_2x_r <= ac_2x;
end
end
// If at AC_PHASE==270, ctl_add_intermediate_regs shall be one
// and an extra cycle delay is required :
else
begin
if (ctl_add_1t_ac_lat == 1'b1)
begin
ac_2x_r <= ac_2x_deg_choice;
end
else
begin
ac_2x_r <= ac_1t;
end
end
// Register the above output for use when ctl_negedge_en is set :
ac_2x_2r <= ac_2x_r;
end
// Determine whether to select the "_r" or "_2r" variant :
always @*
begin
casez(ctl_negedge_en)
1'b0 : ac_2x_mux = ac_2x_r;
1'b1 : ac_2x_mux = ac_2x_2r;
default : ac_2x_mux = 1'bx; // X propagaton
endcase
end
if (POWER_UP_HIGH == 1)
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("ON"),
.width (1)
) addr_pin (
.aset (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aclr (),
.sset (),
.sclr (),
.oe_out ()
);
end
else
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) addr_pin (
.aclr (reset_2x),
.aset (),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.sset (),
.sclr (),
.oe_out ()
);
end
end // Half-rate
// full-rate
else
begin : full_rate
always @(posedge phy_clk_1x)
begin
// 1t registering - only used if ctl_add_1t_ac_lat is true
ac_1t <= ac_l;
// add 1 addr_clock delay if "Add 1T" is set:
if (ctl_add_1t_ac_lat == 1'b1)
ac_2x <= ac_1t;
else
ac_2x <= ac_l;
end
always @(posedge clk_2x)
begin
ac_2x_deg_choice <= ac_2x;
end
// Note this is for 270 degree operation to align it to the correct clock phase.
always @*
begin
casez(ctl_add_intermediate_regs)
1'b0 : ac_2x_r = ac_2x;
1'b1 : ac_2x_r = ac_2x_deg_choice;
default : ac_2x_r = 1'bx; // X propagaton
endcase
end
always @(posedge clk_2x)
begin
ac_2x_2r <= ac_2x_r;
end
// Determine whether to select the "_r" or "_2r" variant :
always @*
begin
casez(ctl_negedge_en)
1'b0 : ac_2x_mux = ac_2x_r;
1'b1 : ac_2x_mux = ac_2x_2r;
default : ac_2x_mux = 1'bx; // X propagaton
endcase
end
if (POWER_UP_HIGH == 1)
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("ON"),
.width (1)
) addr_pin (
.aset (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aclr (),
.sclr (),
.sset (),
.oe_out ()
);
end
else
begin
altddio_out #(
.extend_oe_disable ("UNUSED"),
.intended_device_family ("Cyclone III"),
.lpm_hint ("UNUSED"),
.lpm_type ("altddio_out"),
.oe_reg ("UNUSED"),
.power_up_high ("OFF"),
.width (1)
) addr_pin (
.aclr (reset_2x),
.datain_h (ac_2x_mux),
.datain_l (ac_2x_r),
.dataout (mem_ac),
.oe (1'b1),
.outclock (clk_2x),
.outclocken (1'b1),
.aset (),
.sclr (),
.sset (),
.oe_out ()
);
end // else: !if(POWER_UP_HIGH == 1)
end // block: full_rate
endgenerate
endmodule
`default_nettype wire
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_addr_cmd ( ac_clk_1x,
ac_clk_2x,
cs_n_clk_1x,
cs_n_clk_2x,
phy_clk_1x,
reset_ac_clk_1x_n,
reset_ac_clk_2x_n,
reset_cs_n_clk_1x_n,
reset_cs_n_clk_2x_n,
// Addr/cmd interface from controller
ctl_add_1t_ac_lat,
ctl_add_1t_odt_lat,
ctl_add_intermediate_regs,
ctl_negedge_en,
ctl_mem_addr_h,
ctl_mem_addr_l,
ctl_mem_ba_h,
ctl_mem_ba_l,
ctl_mem_cas_n_h,
ctl_mem_cas_n_l,
ctl_mem_cke_h,
ctl_mem_cke_l,
ctl_mem_cs_n_h,
ctl_mem_cs_n_l,
ctl_mem_odt_h,
ctl_mem_odt_l,
ctl_mem_ras_n_h,
ctl_mem_ras_n_l,
ctl_mem_we_n_h,
ctl_mem_we_n_l,
// DDR3 Signals
ctl_mem_rst_n_h,
ctl_mem_rst_n_l,
// Interface from Sequencer, used for calibration
// as the MRS registers need to be controlled :
seq_addr_h,
seq_addr_l,
seq_ba_h,
seq_ba_l,
seq_cas_n_h,
seq_cas_n_l,
seq_cke_h,
seq_cke_l,
seq_cs_n_h,
seq_cs_n_l,
seq_odt_h,
seq_odt_l,
seq_ras_n_h,
seq_ras_n_l,
seq_we_n_h,
seq_we_n_l,
// DDR3 Signals
seq_mem_rst_n_h,
seq_mem_rst_n_l,
seq_ac_sel,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_odt,
mem_ras_n,
mem_we_n,
mem_rst_n
);
parameter DWIDTH_RATIO = 4;
parameter MEM_ADDR_CMD_BUS_COUNT = 1;
parameter MEM_IF_BANKADDR_WIDTH = 3;
parameter MEM_IF_CS_WIDTH = 2;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_ROWADDR_WIDTH = 13;
input wire cs_n_clk_1x;
input wire cs_n_clk_2x;
input wire ac_clk_1x;
input wire ac_clk_2x;
input wire phy_clk_1x;
input wire reset_ac_clk_1x_n;
input wire reset_ac_clk_2x_n;
input wire reset_cs_n_clk_1x_n;
input wire reset_cs_n_clk_2x_n;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] ctl_mem_addr_l;
input wire ctl_add_1t_ac_lat;
input wire ctl_add_1t_odt_lat;
input wire ctl_negedge_en;
input wire ctl_add_intermediate_regs;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] ctl_mem_ba_l;
input wire ctl_mem_cas_n_h;
input wire ctl_mem_cas_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cke_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cke_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cs_n_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_cs_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_odt_h;
input wire [MEM_IF_CS_WIDTH - 1:0] ctl_mem_odt_l;
input wire ctl_mem_ras_n_h;
input wire ctl_mem_ras_n_l;
input wire ctl_mem_we_n_h;
input wire ctl_mem_we_n_l;
input wire ctl_mem_rst_n_h;
input wire ctl_mem_rst_n_l;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_h;
input wire [MEM_IF_ROWADDR_WIDTH -1:0] seq_addr_l;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_h;
input wire [MEM_IF_BANKADDR_WIDTH - 1:0] seq_ba_l;
input wire seq_cas_n_h;
input wire seq_cas_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cke_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cke_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_cs_n_l;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_odt_h;
input wire [MEM_IF_CS_WIDTH - 1:0] seq_odt_l;
input wire seq_ras_n_h;
input wire seq_ras_n_l;
input wire seq_we_n_h;
input wire seq_we_n_l;
input wire seq_mem_rst_n_h;
input wire seq_mem_rst_n_l;
input wire seq_ac_sel;
output wire [MEM_IF_ROWADDR_WIDTH - 1 : 0] mem_addr;
output wire [MEM_IF_BANKADDR_WIDTH - 1 : 0] mem_ba;
output wire mem_cas_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cke;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_cs_n;
output wire [MEM_IF_CS_WIDTH - 1 : 0] mem_odt;
output wire mem_ras_n;
output wire mem_we_n;
output wire mem_rst_n;
// Periodical select registers - per group of pins
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr_2x = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] count_addr_2x_r = `ADC_NUM_PIN_GROUPS'b0;
reg [`ADC_NUM_PIN_GROUPS-1:0] period_sel_addr = `ADC_NUM_PIN_GROUPS'b0;
// Create new period select for new reset output :
reg period_sel_rst_n = 1'b0;
reg count_addr_rst_n = 1'b0;
reg count_addr_rst_n_2x = 1'b0;
reg count_addr_rst_n_2x_r = 1'b0;
generate
genvar ia;
for (ia=0; ia<`ADC_NUM_PIN_GROUPS - 1; ia=ia+1)
begin : SELECTS
always @(posedge phy_clk_1x)
begin
count_addr[ia] <= ~count_addr[ia];
end
always @(posedge ac_clk_2x)
begin
count_addr_2x[ia] <= count_addr[ia];
count_addr_2x_r[ia] <= count_addr_2x[ia];
period_sel_addr[ia] <= ~(count_addr_2x_r[ia] ^ count_addr_2x[ia]);
end
end
endgenerate
// Reset period select :
always @(posedge phy_clk_1x)
begin
count_addr_rst_n <= ~count_addr_rst_n;
end
always @(posedge ac_clk_2x)
begin
count_addr_rst_n_2x <= count_addr_rst_n ;
count_addr_rst_n_2x_r <= count_addr_rst_n_2x;
period_sel_rst_n <= ~(count_addr_rst_n_2x_r ^ count_addr_rst_n_2x );
end
//now generate cs_n period sel, off the dedicated cs_n clock :
always @(posedge phy_clk_1x)
begin
count_addr[`ADC_CS_N_PERIOD_SEL] <= ~count_addr[`ADC_CS_N_PERIOD_SEL];
end
always @(posedge cs_n_clk_2x)
begin
count_addr_2x [`ADC_CS_N_PERIOD_SEL] <= count_addr [`ADC_CS_N_PERIOD_SEL];
count_addr_2x_r[`ADC_CS_N_PERIOD_SEL] <= count_addr_2x[`ADC_CS_N_PERIOD_SEL];
period_sel_addr[`ADC_CS_N_PERIOD_SEL] <= ~(count_addr_2x_r[`ADC_CS_N_PERIOD_SEL] ^ count_addr_2x[`ADC_CS_N_PERIOD_SEL]);
end
// Create the ADDR I/O structure :
generate
genvar ib;
for (ib=0; ib<MEM_IF_ROWADDR_WIDTH; ib=ib+1)
begin : addr
//
ddr3_int_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) addr_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_ADDR_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_addr_h[ib]),
.ctl_ac_l (ctl_mem_addr_l[ib]),
.seq_ac_h (seq_addr_h[ib]),
.seq_ac_l (seq_addr_l[ib]),
.mem_ac (mem_addr[ib])
);
end
endgenerate
// Create the BANK_ADDR I/O structure :
generate
genvar ic;
for (ic=0; ic<MEM_IF_BANKADDR_WIDTH; ic=ic+1)
begin : ba
//
ddr3_int_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) ba_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_BA_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ba_h[ic]),
.ctl_ac_l (ctl_mem_ba_l[ic]),
.seq_ac_h (seq_ba_h[ic]),
.seq_ac_l (seq_ba_l[ic]),
.mem_ac (mem_ba[ic])
);
end
endgenerate
// Create the CAS_N I/O structure :
//
ddr3_int_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cas_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CAS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cas_n_h),
.ctl_ac_l (ctl_mem_cas_n_l),
.seq_ac_h (seq_cas_n_h),
.seq_ac_l (seq_cas_n_l),
.mem_ac (mem_cas_n)
);
// Create the CKE I/O structure :
generate
genvar id;
for (id=0; id<MEM_IF_CS_WIDTH; id=id+1)
begin : cke
//
ddr3_int_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cke_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CKE_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cke_h[id]),
.ctl_ac_l (ctl_mem_cke_l[id]),
.seq_ac_h (seq_cke_h[id]),
.seq_ac_l (seq_cke_l[id]),
.mem_ac (mem_cke[id])
);
end
endgenerate
// Create the CS_N I/O structure. Note that the 2x clock is different.
generate
genvar ie;
for (ie=0; ie<MEM_IF_CS_WIDTH; ie=ie+1)
begin : cs_n
//
ddr3_int_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) cs_n_struct (
.clk_2x (cs_n_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_CS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_cs_n_h[ie]),
.ctl_ac_l (ctl_mem_cs_n_l[ie]),
.seq_ac_h (seq_cs_n_h[ie]),
.seq_ac_l (seq_cs_n_l[ie]),
.mem_ac (mem_cs_n[ie])
);
end
endgenerate
// Create the ODT I/O structure :
generate
genvar ig;
if (MEM_IF_MEMTYPE != "DDR")
begin : gen_odt
for (ig=0; ig<MEM_IF_CS_WIDTH; ig=ig+1)
begin : odt
//
ddr3_int_phy_alt_mem_phy_ac #(
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
) odt_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_odt_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_ODT_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_odt_h[ig]),
.ctl_ac_l (ctl_mem_odt_l[ig]),
.seq_ac_h (seq_odt_h[ig]),
.seq_ac_l (seq_odt_l[ig]),
.mem_ac (mem_odt[ig])
);
end
end
endgenerate
// Create the RAS_N I/O structure :
//
ddr3_int_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) ras_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_RAS_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_ras_n_h),
.ctl_ac_l (ctl_mem_ras_n_l),
.seq_ac_h (seq_ras_n_h),
.seq_ac_l (seq_ras_n_l),
.mem_ac (mem_ras_n)
);
// Create the WE_N I/O structure :
//
ddr3_int_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (1),
.DWIDTH_RATIO (DWIDTH_RATIO)
) we_n_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (1'b1),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_addr[`ADC_WE_N_PERIOD_SEL]),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_we_n_h),
.ctl_ac_l (ctl_mem_we_n_l),
.seq_ac_h (seq_we_n_h),
.seq_ac_l (seq_we_n_l),
.mem_ac (mem_we_n)
);
generate
if (MEM_IF_MEMTYPE == "DDR3")
begin : ddr3_rst
// generate rst_n for DDR3
//
ddr3_int_phy_alt_mem_phy_ac # (
.POWER_UP_HIGH (0),
.DWIDTH_RATIO (DWIDTH_RATIO)
)ddr3_rst_struct (
.clk_2x (ac_clk_2x),
.reset_2x_n (reset_ac_clk_2x_n),
.phy_clk_1x (phy_clk_1x),
.ctl_add_1t_ac_lat (ctl_add_1t_ac_lat),
.ctl_negedge_en (ctl_negedge_en),
.ctl_add_intermediate_regs (ctl_add_intermediate_regs),
.period_sel (period_sel_rst_n),
.seq_ac_sel (seq_ac_sel),
.ctl_ac_h (ctl_mem_rst_n_h),
.ctl_ac_l (ctl_mem_rst_n_l),
.seq_ac_h (seq_mem_rst_n_h),
.seq_ac_l (seq_mem_rst_n_l),
.mem_ac (mem_rst_n)
);
end
else
begin : no_ddr3_rst
assign mem_rst_n = 1'b1;
end
endgenerate
endmodule
`default_nettype wire
/* Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details. */
/*////////////////////////////////////////////////////////////////////////////-
Title : Datapath IO elements
File: $RCSfile : alt_mem_phy_dp_io.v,v $
Last Modified : $Date: 2011/08/15 $
Revision : $Revision: #1 $
Abstract : NewPhy Datapath IO atoms. This block shall connect to both
the read and write datapath blocks, abstracting the I/O
elements from the remainder of the circuit. This file
uses the ALTDQ_DQS WYSIWYG which is configurable to be either
of type DQ, DQS or DQSN and just requires connecting to the
relevant IO buffers (ALTIOBUF) to create the full IO required
for DDR.
////////////////////////////////////////////////////////////////////////////-*/
`include "alt_mem_phy_defines.v"
//
module ddr3_int_phy_alt_mem_phy_dp_io (
reset_write_clk_2x_n,
resync_clk_2x,
postamble_clk_2x,
mem_clk_2x,
write_clk_2x,
dqs_delay_ctrl,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
dio_rdata_h_2x,
dio_rdata_l_2x,
poa_postamble_en_preset_2x,
wdp_dm_h_2x,
wdp_dm_l_2x,
wdp_wdata_h_2x,
wdp_wdata_l_2x,
wdp_wdata_oe_2x,
wdp_wdqs_2x,
wdp_wdqs_oe_2x
);
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_DM_PINS_EN = 1;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_DQSN_EN = 1;
parameter MEM_IF_POSTAMBLE_EN_WIDTH = 8;
parameter DQS_DELAY_CTL_WIDTH = 6;
input wire reset_write_clk_2x_n;
input wire resync_clk_2x;
input wire postamble_clk_2x;
input wire mem_clk_2x;
input wire write_clk_2x;
input wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl;
output wire [MEM_IF_DM_WIDTH - 1 : 0] mem_dm;
inout wire [MEM_IF_DWIDTH - 1 : 0] mem_dq;
inout wire [MEM_IF_DQS_WIDTH - 1 : 0] mem_dqs;
inout wire [MEM_IF_DQS_WIDTH - 1 : 0] mem_dqsn;
output reg [MEM_IF_DWIDTH - 1 : 0] dio_rdata_h_2x;
output reg [MEM_IF_DWIDTH - 1 : 0] dio_rdata_l_2x;
input wire [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] poa_postamble_en_preset_2x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_h_2x;
input wire [MEM_IF_DM_WIDTH -1 : 0] wdp_dm_l_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_h_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_l_2x;
input wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdqs_2x;
input wire [MEM_IF_DQS_WIDTH - 1 : 0] wdp_wdqs_oe_2x;
wire [MEM_IF_DWIDTH - 1 : 0] wdp_wdata_oe_2x_r;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_n_captured;
wire [MEM_IF_DWIDTH - 1 : 0] rdata_p_captured;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqs_oe_2x_r;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] wdp_wdqsn_oe_2x_r;
// The power-on low values are required to match those within ALTDQ_DQS, not for any functional reason :
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_n_ams = {MEM_IF_DWIDTH{1'b0}};
(* preserve *) reg [MEM_IF_DWIDTH - 1 : 0] rdata_p_ams = {MEM_IF_DWIDTH{1'b0}};
wire reset_write_clk_2x;
wire [MEM_IF_DWIDTH - 1 : 0] dq_ddio_dataout;
wire [MEM_IF_DWIDTH - 1 : 0] dq_datain;
wire [MEM_IF_DWIDTH - 1 : 0] dm_ddio_dataout;
wire [MEM_IF_DQS_WIDTH - 1 : 0] dqs_ddio_dataout;
wire [MEM_IF_DM_WIDTH - 1 : 0] dm_ddio_oe;
wire [MEM_IF_DQS_WIDTH - 1 : 0] dqs_buffered;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] dqs_pseudo_diff_out;
wire [(MEM_IF_DQS_WIDTH) - 1 : 0] dqsn_pseudo_diff_out;
// Create non-inverted reset for pads :
assign reset_write_clk_2x = ~reset_write_clk_2x_n;
// Read datapath functionality :
// synchronise to the resync_clk_2x_domain
always @(posedge resync_clk_2x)
begin : capture_regs
// Resynchronise :
// The comparison to 'X' is performed to prevent X's being captured in non-DQS mode
// and propagating into the sequencer's control logic. This can only occur when a Verilog SIMGEN
// model of the sequencer is being used :
if (|rdata_p_captured === 1'bX)
rdata_p_ams <= {MEM_IF_DWIDTH{1'b0}};
else
rdata_p_ams <= rdata_p_captured; // 'captured' is from the IOEs
if (|rdata_n_captured === 1'bX)
rdata_n_ams <= {MEM_IF_DWIDTH{1'b0}};
else
rdata_n_ams <= rdata_n_captured; // 'captured' is from the IOEs
// Output registers :
dio_rdata_h_2x <= rdata_p_ams;
dio_rdata_l_2x <= rdata_n_ams;
end
// DQ pins and their logic
generate
genvar i,j;
// First generate each DQS group :
for (i=0; i<MEM_IF_DQS_WIDTH ; i=i+1)
begin : dqs_group
// ALTDQ_DQS instances all WYSIWYGs for the DQ, DM and DQS/DQSN pins for a group :
//
ddr3_int_phy_alt_mem_phy_dq_dqs dq_dqs (
// DQ pin connections :
.bidir_dq_areset({MEM_IF_DQ_PER_DQS{reset_write_clk_2x}}),
.bidir_dq_input_data_in(dq_datain[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS] ), // From ibuf
.bidir_dq_input_data_out_high(rdata_n_captured[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_input_data_out_low(rdata_p_captured[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_oe_in(wdp_wdata_oe_2x[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_oe_out(wdp_wdata_oe_2x_r[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_output_data_in_high(wdp_wdata_h_2x[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_output_data_in_low(wdp_wdata_l_2x[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]),
.bidir_dq_output_data_out(dq_ddio_dataout[ (i+1)*MEM_IF_DQ_PER_DQS - 1 : i*MEM_IF_DQ_PER_DQS]), // To obuf
// Misc connections :
.dll_delayctrlin(dqs_delay_ctrl), // From DLL
.dq_input_reg_clk(dqs_buffered[i]),
.dq_output_reg_clk(write_clk_2x),
// DQS/DQSN connections :
.dqs_enable_ctrl_in(poa_postamble_en_preset_2x[i]),
.dqs_enable_ctrl_clk(postamble_clk_2x),
//NB. Inverted via dq_input_reg_clk_source=INVERTED_DQS_BUS param in ALTDQ_DQS clearbox config file :
.dqs_input_data_in(dqs_buffered[i]),
.dqs_oe_in(wdp_wdqs_oe_2x[i]),
.dqs_oe_out(wdp_wdqs_oe_2x_r[i]),
.dqs_output_data_in_high(wdp_wdqs_2x[i]), // DQS Output. From the write datapath
.dqs_output_data_in_low(1'b0),
.dqs_output_data_out(dqs_ddio_dataout[i]),
.dqs_output_reg_clk(mem_clk_2x),
.dqsn_oe_in(wdp_wdqs_oe_2x[i]), // Just use DQS OE to drive DQSN OE also
.dqsn_oe_out(wdp_wdqsn_oe_2x_r[i]),
//DM pins are implemented using unidirection DQ pins :
.output_dq_oe_in(1'b1),
.output_dq_oe_out(dm_ddio_oe[i]),
.output_dq_output_data_in_high(wdp_dm_h_2x[i]),
.output_dq_output_data_in_low(wdp_dm_l_2x[i]),
.output_dq_output_data_out(dm_ddio_dataout[i]) // To obuf
);
// For DDR, or DDR2 where DQSN is disabled, it is important to leave the DQSN
// pad unconnected, as otherwise this path remains in the netlist even
// though there is no intent to use DQSN, and it is unused as an output :
if (MEM_IF_MEMTYPE == "DDR" || (MEM_IF_MEMTYPE == "DDR2" && (MEM_IF_DQSN_EN == 0)) )
begin : ddr_no_dqsn_ibuf_gen
// Input buf
arriaii_io_ibuf dqs_inpt_ibuf(
.i (mem_dqs[i]),
.ibar (),
.o (dqs_buffered[i])
);
// The DQS Output buffer itself :
// OE input is active HIGH
arriaii_io_obuf dqs_obuf (
.i(dqs_ddio_dataout[i]),
.oe(wdp_wdqs_oe_2x_r[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dqs[i]),
.obar()
);
assign mem_dqsn[i] = 1'b0;
end
// DDR2 (with DQSN enabled) has true differential DQS inputs :
else
begin : ddr2_with_dqsn_buf_gen
// Input buffer now has DQSN input connection too :
arriaii_io_ibuf dqs_inpt_ibuf(
.i (mem_dqs[i]),
.ibar (mem_dqsn[i]),
.o (dqs_buffered[i])
);
// Need to create the DQSN output buffer, which requires the use of the
// Pseudo-diff atom :
arriaii_pseudo_diff_out dqs_pdiff_out (
.i (dqs_ddio_dataout[i]),
.o (dqs_pseudo_diff_out[i]),
.obar (dqsn_pseudo_diff_out[i])
);
// The DQS Output buffer itself, driven from 'O' output of pseudo-diff atom :
// OE input is active HIGH
arriaii_io_obuf dqs_obuf (
.i(dqs_pseudo_diff_out[i]),
.oe(wdp_wdqs_oe_2x_r[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dqs[i]),
.obar()
);
// The DQSN Output buffer itself, driven from 'OBAR' output of pseudo-diff atom :
// OE input is active HIGH
arriaii_io_obuf dqsn_obuf (
.i(dqsn_pseudo_diff_out[i]),
.oe(wdp_wdqsn_oe_2x_r[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dqsn[i]),
.obar()
);
end
// Then generate DQ pins for each group :
for (j=0; j<MEM_IF_DQ_PER_DQS ; j=j+1)
begin : dq
// The DQ buffer (output side) :
arriaii_io_obuf dq_obuf (
.i(dq_ddio_dataout[j+(i*MEM_IF_DQ_PER_DQS)]),
.oe(wdp_wdata_oe_2x_r[j+(i*MEM_IF_DQ_PER_DQS)]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dq[j+(i*MEM_IF_DQ_PER_DQS)]), //pad
.obar()
);
// The DQ buffer (input side) :
arriaii_io_ibuf # (
.simulate_z_as("gnd")
) dq_ibuf (
.i(mem_dq[j+(i*MEM_IF_DQ_PER_DQS)]),//pad
.ibar(),
.o(dq_datain[j+(i*MEM_IF_DQ_PER_DQS)])
);
end
// The DM buffer (output only) :
// DM Pin - if required :
if (MEM_IF_DM_PINS_EN)
begin : gen_dm
arriaii_io_obuf dm_obuf (
.i(dm_ddio_dataout[i]),
.oe(dm_ddio_oe[i]),
.seriesterminationcontrol(),
.devoe(),
.o(mem_dm[i]), //pad
.obar()
);
end
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
// ArriaII Clock/Reset block
//
module ddr3_int_phy_alt_mem_phy_clk_reset (
pll_ref_clk,
global_reset_n,
soft_reset_n,
seq_rdp_reset_req_n,
ac_clk_2x,
measure_clk_2x,
mem_clk_2x,
mem_clk,
mem_clk_n,
phy_clk_1x,
postamble_clk_2x,
resync_clk_2x,
cs_n_clk_2x,
write_clk_2x,
half_rate_clk,
reset_ac_clk_2x_n,
reset_measure_clk_2x_n,
reset_mem_clk_2x_n,
reset_phy_clk_1x_n,
reset_poa_clk_2x_n,
reset_resync_clk_2x_n,
reset_write_clk_2x_n,
reset_cs_n_clk_2x_n,
reset_rdp_phy_clk_1x_n,
mem_reset_n,
reset_request_n, // new output
dqs_delay_ctrl,
phs_shft_busy,
seq_pll_inc_dec_n,
seq_pll_select,
seq_pll_start_reconfig,
mimic_data_2x,
seq_clk_disable,
ctrl_clk_disable
) /* synthesis altera_attribute="SUPPRESS_DA_RULE_INTERNAL=\"R101,C104,C106\"" */;
parameter CLOCK_INDEX_WIDTH = 3;
parameter DLL_EXPORT_IMPORT = "NONE";
parameter DWIDTH_RATIO = 4;
parameter LOCAL_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PAIR_COUNT = 3;
parameter MEM_IF_CLK_PS = 4000;
parameter MEM_IF_CLK_PS_STR = "4000 ps";
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_MEMTYPE = "DDR";
parameter MEM_IF_DQSN_EN = 1;
parameter DLL_DELAY_BUFFER_MODE = "HIGH";
parameter DLL_DELAY_CHAIN_LENGTH = 8;
parameter SCAN_CLK_DIVIDE_BY = 2;
parameter USE_MEM_CLK_FOR_ADDR_CMD_CLK = 1;
parameter DQS_DELAY_CTL_WIDTH = 6;
parameter INVERT_POSTAMBLE_CLK = "false";
// Clock/reset inputs :
input global_reset_n;
input wire soft_reset_n;
input wire pll_ref_clk;
input wire seq_rdp_reset_req_n;
// Clock/reset outputs :
output ac_clk_2x;
output measure_clk_2x;
output mem_clk_2x;
inout [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
inout [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
output phy_clk_1x;
output postamble_clk_2x;
output resync_clk_2x;
output cs_n_clk_2x;
output write_clk_2x;
output wire half_rate_clk;
output wire reset_ac_clk_2x_n;
output wire reset_measure_clk_2x_n;
output wire reset_mem_clk_2x_n;
(*preserve*) (* altera_attribute = "-name global_signal off" *) output reg reset_phy_clk_1x_n;
output wire reset_poa_clk_2x_n;
output wire reset_resync_clk_2x_n;
output wire reset_write_clk_2x_n;
output wire reset_cs_n_clk_2x_n;
output wire reset_rdp_phy_clk_1x_n;
output wire mem_reset_n;
// This is the PLL locked signal :
output wire reset_request_n;
// Misc I/O :
output wire [DQS_DELAY_CTL_WIDTH - 1 : 0 ] dqs_delay_ctrl;
output wire phs_shft_busy;
input wire seq_pll_inc_dec_n;
input wire [CLOCK_INDEX_WIDTH - 1 : 0 ] seq_pll_select;
input wire seq_pll_start_reconfig;
output wire mimic_data_2x;
input wire seq_clk_disable;
input wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] ctrl_clk_disable;
// No attributes are applied to the clk/reset wires, as the fitter should be able to
// allocate GCLK/QCLK routing resources appropriately. For specific GCLk/QCLK requirements
// this HDL may be edited using the following syntax :
// (* keep, altera_attribute = "-name global_signal dual_regional_clock" *) wire resync_clk_2x;
wire global_reset_n;
reg scan_clk = 1'b0;
wire mem_clk_2x;
wire phy_clk_1x;
wire postamble_clk_2x;
wire resync_clk_2x;
wire write_clk_2x;
wire cs_n_clk_2x;
wire ac_clk_2x;
wire measure_clk_2x;
wire phy_internal_reset_n;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n;
reg [2:0] divider = 3'h0;
(*preserve*) reg seq_pll_start_reconfig_ams;
(*preserve*) reg seq_pll_start_reconfig_r;
(*preserve*) reg seq_pll_start_reconfig_2r;
(*preserve*) reg seq_pll_start_reconfig_3r;
reg pll_new_dir;
reg [CLOCK_INDEX_WIDTH - 1 : 0 ] pll_new_phase;
wire pll_phase_auto_calibrate_pulse;
(*preserve*) reg pll_reprogram_request;
wire pll_locked_src;
reg pll_locked;
(*preserve*) reg pll_reprogram_request_pulse; // 1 scan clk cycle long
(*preserve*) reg pll_reprogram_request_pulse_r;
(*preserve*) reg pll_reprogram_request_pulse_2r;
wire pll_reprogram_request_long_pulse; // 3 scan clk cycles long
(*preserve*) reg reset_master_ams;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_pdiff_in;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_buf_in;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mem_clk_n_buf_in;
wire pll_phase_done;
reg phs_shft_busy_siii;
(*preserve*) reg [2:0] seq_pll_start_reconfig_ccd_pipe;
(*preserve*) reg seq_pll_inc_dec_ccd;
(*preserve*) reg [CLOCK_INDEX_WIDTH - 1 : 0] seq_pll_select_ccd ;
(*preserve*) reg global_pre_clear;
wire global_or_soft_reset_n;
(*preserve*) reg clk_div_reset_ams_n = 1'b0;
(*preserve*) reg clk_div_reset_ams_n_r = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n = 1'b0;
(*preserve*) reg pll_reconfig_reset_ams_n_r = 1'b0;
wire clk_divider_reset_n;
wire [MEM_IF_CLK_PAIR_COUNT - 1 : 0] mimic_data_2x_internal;
wire pll_reset;
wire fb_clk;
wire pll_reconfig_reset_n;
genvar dqs_group;
// Output the PLL locked signal to be used as a reset_request_n - IE. reset when the PLL loses
// lock :
assign reset_request_n = pll_locked;
// Reset the scanclk clock divider if we either have a global_reset or the PLL loses lock
assign pll_reconfig_reset_n = global_reset_n && pll_locked;
// Clock divider circuit reset generation.
always @(posedge phy_clk_1x or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
clk_div_reset_ams_n <= 1'b0;
clk_div_reset_ams_n_r <= 1'b0;
end
else
begin
clk_div_reset_ams_n <= 1'b1;
clk_div_reset_ams_n_r <= clk_div_reset_ams_n;
end
end
// PLL reconfig and synchronisation circuit reset generation.
always @(posedge scan_clk or negedge pll_reconfig_reset_n)
begin
if (pll_reconfig_reset_n == 1'b0)
begin
pll_reconfig_reset_ams_n <= 1'b0;
pll_reconfig_reset_ams_n_r <= 1'b0;
end
else
begin
pll_reconfig_reset_ams_n <= 1'b1;
pll_reconfig_reset_ams_n_r <= pll_reconfig_reset_ams_n;
end
end
// Create the scan clock. Used for PLL reconfiguring in this block.
// Clock divider reset is the direct output of the AMS flops :
assign clk_divider_reset_n = clk_div_reset_ams_n_r;
generate
if (SCAN_CLK_DIVIDE_BY == 1)
begin : no_scan_clk_divider
always @(phy_clk_1x)
begin
scan_clk = phy_clk_1x;
end
end
else
begin : gen_scan_clk
always @(posedge phy_clk_1x or negedge clk_divider_reset_n)
begin
if (clk_divider_reset_n == 1'b0)
begin
scan_clk <= 1'b0;
divider <= 3'h0;
end
else
begin
// This method of clock division does not require "divider" to be used
// as an intermediate clock:
if (divider == (SCAN_CLK_DIVIDE_BY / 2 - 1))
begin
scan_clk <= ~scan_clk; // Toggle
divider <= 3'h0;
end
else
begin
scan_clk <= scan_clk; // Do not toggle
divider <= divider + 3'h1;
end
end
end
end
endgenerate
function [3:0] lookup_aii;
input [CLOCK_INDEX_WIDTH-1:0] seq_num;
begin
casez (seq_num)
4'b0000 : lookup_aii = 4'b0010; // Legal code
4'b0001 : lookup_aii = 4'b0011; // Legal code
4'b0010 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b0011 : lookup_aii = 4'b0101; // Legal code
4'b0100 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b0101 : lookup_aii = 4'b0110; // Legal code
4'b0110 : lookup_aii = 4'b1000; // Legal code
4'b0111 : lookup_aii = 4'b0111; // Legal code
4'b1000 : lookup_aii = 4'b0100; // Legal code
4'b1001 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1010 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1011 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1100 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1101 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1110 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
4'b1111 : lookup_aii = 4'b1111; // illegal - return code 4'b1111
default : lookup_aii = 4'bxxxx; // X propagation
endcase
end
endfunction
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_pll_inc_dec_ccd <= 1'b0;
seq_pll_select_ccd <= {CLOCK_INDEX_WIDTH{1'b0}};
seq_pll_start_reconfig_ccd_pipe <= 3'b000;
end
// Generate 'ccd' Cross Clock Domain signals :
else
begin
seq_pll_start_reconfig_ccd_pipe <= {seq_pll_start_reconfig_ccd_pipe[1:0], seq_pll_start_reconfig};
if (seq_pll_start_reconfig == 1'b1 && seq_pll_start_reconfig_ccd_pipe[0] == 1'b0)
begin
seq_pll_inc_dec_ccd <= seq_pll_inc_dec_n;
seq_pll_select_ccd <= seq_pll_select;
end
end
end
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
seq_pll_start_reconfig_ams <= 1'b0;
seq_pll_start_reconfig_r <= 1'b0;
seq_pll_start_reconfig_2r <= 1'b0;
seq_pll_start_reconfig_3r <= 1'b0;
pll_reprogram_request_pulse <= 1'b0;
pll_reprogram_request_pulse_r <= 1'b0;
pll_reprogram_request_pulse_2r <= 1'b0;
pll_reprogram_request <= 1'b0;
end
else
begin
seq_pll_start_reconfig_ams <= seq_pll_start_reconfig_ccd_pipe[2];
seq_pll_start_reconfig_r <= seq_pll_start_reconfig_ams;
seq_pll_start_reconfig_2r <= seq_pll_start_reconfig_r;
seq_pll_start_reconfig_3r <= seq_pll_start_reconfig_2r;
pll_reprogram_request_pulse <= pll_phase_auto_calibrate_pulse;
pll_reprogram_request_pulse_r <= pll_reprogram_request_pulse;
pll_reprogram_request_pulse_2r <= pll_reprogram_request_pulse_r;
pll_reprogram_request <= pll_reprogram_request_long_pulse;
end
end
// Rising-edge detect to generate a single phase shift step
assign pll_phase_auto_calibrate_pulse = ~seq_pll_start_reconfig_3r && seq_pll_start_reconfig_2r;
// extend the phase shift request pulse to be 3 scan clk cycles long.
assign pll_reprogram_request_long_pulse = pll_reprogram_request_pulse || pll_reprogram_request_pulse_r || pll_reprogram_request_pulse_2r;
// Register the Phase step settings
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
begin
pll_new_dir <= 1'b0;
pll_new_phase <= 'h0;
end
else
begin
if (pll_phase_auto_calibrate_pulse)
begin
pll_new_dir <= seq_pll_inc_dec_ccd;
pll_new_phase <= seq_pll_select_ccd;
end
end
end
// generate the busy signal - just the inverse of the done o/p from the pll, and stretched ,
//as the initial pulse might not be long enough to be catched by the sequencer
//the same circuitry in the ciii clock and reset block
always @(posedge scan_clk or negedge pll_reconfig_reset_ams_n_r)
begin
if (pll_reconfig_reset_ams_n_r == 1'b0)
phs_shft_busy_siii <= 1'b0;
else
phs_shft_busy_siii <= pll_reprogram_request || ~pll_phase_done;
end
assign phs_shft_busy = phs_shft_busy_siii;
// Gate the soft reset input (from SOPC builder for example) with the PLL
// locked signal :
assign global_or_soft_reset_n = soft_reset_n && global_reset_n;
// Create the PHY internal reset signal :
assign phy_internal_reset_n = pll_locked && global_or_soft_reset_n;
// The PLL resets only on a global reset :
assign pll_reset = !global_reset_n;
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin : half_rate
//
ddr3_int_phy_alt_mem_phy_pll pll (
.inclk0 (pll_ref_clk),
.areset (pll_reset),
.c0 (phy_clk_1x),
.c1 (mem_clk_2x),
.c2 (), //unused
.c3 (write_clk_2x),
.c4 (resync_clk_2x),
.c5 (measure_clk_2x),
.phasecounterselect (lookup_aii(pll_new_phase)),
.phasestep (pll_reprogram_request),
.phaseupdown (pll_new_dir),
.scanclk (scan_clk),
.locked (pll_locked_src),
.phasedone (pll_phase_done)
);
assign half_rate_clk = phy_clk_1x;
end
// Full-rate mode :
else
begin : full_rate
//
ddr3_int_phy_alt_mem_phy_pll pll (
.inclk0 (pll_ref_clk),
.areset (pll_reset),
.c0 (half_rate_clk),
.c1 (mem_clk_2x),
.c2 (), //unused
.c3 (write_clk_2x),
.c4 (resync_clk_2x),
.c5 (measure_clk_2x),
.phasecounterselect (lookup_aii(pll_new_phase)),
.phasestep (pll_reprogram_request),
.phaseupdown (pll_new_dir),
.scanclk (scan_clk),
.locked (pll_locked_src),
.phasedone (pll_phase_done)
);
// NB. phy_clk_1x is now full-rate, despite the "1x" naming convention :
assign phy_clk_1x = mem_clk_2x;
end
endgenerate
//synopsys translate_off
reg [19:0] pll_locked_chain = 20'h0;
always @(posedge pll_ref_clk)
begin
pll_locked_chain <= {pll_locked_chain[18:0],pll_locked_src};
end
//synopsys translate_on
always @*
begin
pll_locked = pll_locked_src;
//synopsys translate_off
pll_locked = pll_locked_chain[19];
//synopsys translate_on
end
// The postamble clock can be the inverse of the resync clock
assign postamble_clk_2x = (INVERT_POSTAMBLE_CLK == "true") ? ~resync_clk_2x : resync_clk_2x;
generate
if (USE_MEM_CLK_FOR_ADDR_CMD_CLK == 1)
begin
assign ac_clk_2x = mem_clk_2x;
assign cs_n_clk_2x = mem_clk_2x;
end
else
begin
assign ac_clk_2x = write_clk_2x;
assign cs_n_clk_2x = write_clk_2x;
end
endgenerate
generate
genvar clk_pair;
for (clk_pair = 0 ; clk_pair < MEM_IF_CLK_PAIR_COUNT; clk_pair = clk_pair + 1)
begin : DDR_CLK_OUT
arriaii_ddio_out # (
.half_rate_mode("false"),
.sync_mode("clear"), // for mem clk disable
.use_new_clocking_model("true")
) mem_clk_ddio (
.datainlo (1'b0),
.datainhi (~seq_clk_disable && ~ctrl_clk_disable[clk_pair]),
.clkhi (mem_clk_2x),
.clklo (mem_clk_2x),
//synthesis translate_off
.clk (),
//synthesis translate_on
.muxsel (mem_clk_2x),
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
.dataout (mem_clk_pdiff_in[clk_pair]),
.dfflo (),
.dffhi (),
.devpor (),
.devclrn ()
);
// Pseudo-diff used to ensure fanout of 1 from OPA/DDIO_OUT atoms :
arriaii_pseudo_diff_out mem_clk_pdiff (
.i (mem_clk_pdiff_in[clk_pair]),
.o ( mem_clk_buf_in[clk_pair]),
.obar (mem_clk_n_buf_in[clk_pair])
);
// The same output buf is for both DDR2 and 3 :
arriaii_io_obuf # (
.bus_hold("false"),
.open_drain_output("false")
) mem_clk_obuf (
.i (mem_clk_buf_in[clk_pair]),
.oe (1'b1),
// synopsys translate_off
.seriesterminationcontrol(),
.obar(),
// synopsys translate_on
.o(mem_clk[clk_pair]),
.devoe()
);
// The same output buf is used
arriaii_io_obuf # (
.bus_hold("false"),
.open_drain_output("false")
) mem_clk_n_obuf (
.i (mem_clk_n_buf_in[clk_pair]),
.oe (1'b1),
// synopsys translate_off
.seriesterminationcontrol(),
.obar(),
// synopsys translate_on
.o(mem_clk_n[clk_pair]),
.devoe()
);
end //for
endgenerate
// Mimic path uses single-ended buffer, as this is the SII scheme :
arriaii_io_ibuf fb_clk_ibuf(
.i (mem_clk[0]),
// synopsys translate_off
.ibar(),
// synopsys translate_on
.o (fb_clk)
);
// DDR2 Mimic Path Generation - in effect this is just a register :
arriaii_ddio_in ddio_mimic(
.datain (fb_clk),
.clk (measure_clk_2x),
.clkn (),
// synopsys translate_off
.devclrn(),
.devpor(),
// synopsys translate_on
.ena (1'b1),
.areset (1'b0),
.sreset (1'b0),
.regoutlo (),
.regouthi (mimic_data_2x),
.dfflo ()
);
generate
if (DLL_EXPORT_IMPORT != "IMPORT")
begin
arriaii_dll # (
.input_frequency (MEM_IF_CLK_PS_STR),
.delay_buffer_mode (DLL_DELAY_BUFFER_MODE),
.delay_chain_length (DLL_DELAY_CHAIN_LENGTH),
.delayctrlout_mode ("normal"),
.jitter_reduction ("true"),
.sim_valid_lock (1280),
.sim_low_buffer_intrinsic_delay (350),
.sim_high_buffer_intrinsic_delay (175),
.sim_buffer_delay_increment (10),
.static_delay_ctrl (0),
.lpm_type ("arriaii_dll")
) dll(
.clk (mem_clk_2x),
.aload (~pll_locked),
.delayctrlout (dqs_delay_ctrl),
.upndnout (),
.dqsupdate (),
.offsetdelayctrlclkout (),
.offsetdelayctrlout (),
.devpor (),
.devclrn (),
.upndninclkena (),
.upndnin ()
);
end
else
begin
assign dqs_delay_ctrl = {DQS_DELAY_CTL_WIDTH{1'b0}};
end
endgenerate
// Master reset generation :
always @(posedge phy_clk_1x or negedge phy_internal_reset_n)
begin
if (phy_internal_reset_n == 1'b0)
begin
reset_master_ams <= 1'b0;
global_pre_clear <= 1'b0;
end
else
begin
reset_master_ams <= 1'b1;
global_pre_clear <= reset_master_ams;
end
end
// phy_clk reset generation :
always @(posedge phy_clk_1x or negedge global_pre_clear)
begin
if (global_pre_clear == 1'b0)
begin
reset_phy_clk_1x_n <= 1'b0;
end
else
begin
reset_phy_clk_1x_n <= global_pre_clear;
end
end
// phy_clk reset generation for read datapaths :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) reset_rdp_phy_clk_pipe(
.clock (phy_clk_1x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_rdp_phy_clk_1x_n)
);
// NB. phy_clk reset is generated above.
// Instantiate the reset pipes. The 4 reset signals below are family invariant
// whilst the other resets are generated on a per-family basis :
// mem_clk reset generation :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) mem_pipe(
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (mem_reset_n)
);
// mem_clk_2x reset generation - required for SIII DDR/DDR2 support :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) mem_clk_pipe(
.clock (mem_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_mem_clk_2x_n)
);
// poa_clk_2x reset generation (also reset on sequencer re-cal request) :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) poa_clk_pipe(
.clock (postamble_clk_2x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_poa_clk_2x_n)
);
// write_clk_2x reset generation :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) write_clk_pipe(
.clock (write_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_write_clk_2x_n)
);
// ac_clk_2x reset generation :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) ac_clk_pipe_2x(
.clock (ac_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_ac_clk_2x_n)
);
// cs_clk_2x reset generation :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (4) ) cs_n_clk_pipe_2x(
.clock (cs_n_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_cs_n_clk_2x_n)
);
// measure_clk_2x reset generation :
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) measure_clk_pipe(
.clock (measure_clk_2x),
.pre_clear (global_pre_clear),
.reset_out (reset_measure_clk_2x_n)
);
// resync_clk_2x reset generation (also reset on sequencer re-cal request):
//
ddr3_int_phy_alt_mem_phy_reset_pipe # (.PIPE_DEPTH (2) ) resync_clk_2x_pipe(
.clock (resync_clk_2x),
.pre_clear (seq_rdp_reset_req_n && global_pre_clear),
.reset_out (reset_resync_clk_2x_n)
);
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_postamble ( // inputs
phy_clk_1x,
postamble_clk_2x,
reset_phy_clk_1x_n,
reset_poa_clk_2x_n,
seq_poa_lat_inc_1x,
seq_poa_lat_dec_1x,
seq_poa_protection_override_1x,
// for 2T / 2N addr/CMD drive both of these with the same value.
ctl_doing_rd_beat1_1x,
ctl_doing_rd_beat2_1x ,
// outputs
poa_postamble_en_preset_2x
) /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL = \"R105\"" */ ;
parameter FAMILY = "Stratix II";
parameter POSTAMBLE_INITIAL_LAT = 16;
parameter POSTAMBLE_RESYNC_LAT_CTL_EN = 0; // 0 means false, 1 means true
parameter POSTAMBLE_AWIDTH = 6;
parameter POSTAMBLE_HALFT_EN = 0; // 0 means false, 1 means true
parameter MEM_IF_POSTAMBLE_EN_WIDTH = 8;
parameter DWIDTH_RATIO = 4;
// clocks
input wire phy_clk_1x;
input wire postamble_clk_2x;
// resets
input wire reset_phy_clk_1x_n;
input wire reset_poa_clk_2x_n;
// control signals from sequencer
input wire seq_poa_lat_inc_1x;
input wire seq_poa_lat_dec_1x;
input wire seq_poa_protection_override_1x;
input wire ctl_doing_rd_beat1_1x;
input wire ctl_doing_rd_beat2_1x ;
// output to IOE
output wire [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] poa_postamble_en_preset_2x;
// internal wires/regs
reg [POSTAMBLE_AWIDTH - 1 : 0] rd_addr_2x;
reg [POSTAMBLE_AWIDTH - 1 : 0] wr_addr_1x;
reg [POSTAMBLE_AWIDTH - 1 : 0] next_wr_addr_1x;
reg [1:0] wr_data_1x;
wire wr_en_1x;
reg sync_seq_poa_lat_inc_1x;
reg sync_seq_poa_lat_dec_1x;
reg seq_poa_lat_inc_1x_1t;
reg seq_poa_lat_dec_1x_1t;
reg ctl_doing_rd_beat2_1x_r1;
wire postamble_en_2x;
reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] postamble_en_pos_2x;
reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] delayed_postamble_en_pos_2x;
reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] postamble_en_pos_2x_vdc;
(*preserve*) reg [MEM_IF_POSTAMBLE_EN_WIDTH-1 : 0] postamble_en_2x_r;
reg bit_order_1x;
reg ams_inc;
reg ams_dec;
// loop variables
genvar i;
////////////////////////////////////////////////////////////////////////////////
// Generate Statements to synchronise controls if necessary
////////////////////////////////////////////////////////////////////////////////
generate
if (POSTAMBLE_RESYNC_LAT_CTL_EN == 0)
begin : sync_lat_controls
always @* // combinational logic sensitivity
begin
sync_seq_poa_lat_inc_1x = seq_poa_lat_inc_1x;
sync_seq_poa_lat_dec_1x = seq_poa_lat_dec_1x;
end
end
endgenerate
generate
if (POSTAMBLE_RESYNC_LAT_CTL_EN == 1)
begin : resynch_lat_controls
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
sync_seq_poa_lat_inc_1x <= 1'b0;
sync_seq_poa_lat_dec_1x <= 1'b0;
ams_inc <= 1'b0;
ams_dec <= 1'b0;
end
else
begin
sync_seq_poa_lat_inc_1x <= ams_inc;
sync_seq_poa_lat_dec_1x <= ams_dec;
ams_inc <= seq_poa_lat_inc_1x;
ams_dec <= seq_poa_lat_dec_1x;
end
end
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// write address controller
////////////////////////////////////////////////////////////////////////////////
// seq_poa_protection_override_1x is used to overide the write data
// Otherwise use bit_order_1x to choose how word is written into RAM.
always @*
begin
if (seq_poa_protection_override_1x == 1'b1)
begin
wr_data_1x = `POA_OVERRIDE_VAL;
end
else if (bit_order_1x == 1'b0)
begin
wr_data_1x = {ctl_doing_rd_beat2_1x, ctl_doing_rd_beat1_1x};
end
else
begin
wr_data_1x = {ctl_doing_rd_beat1_1x, ctl_doing_rd_beat2_1x_r1};
end
end
always @*
begin
next_wr_addr_1x = wr_addr_1x + 1'b1;
if (sync_seq_poa_lat_dec_1x == 1'b1 && seq_poa_lat_dec_1x_1t == 1'b0)
begin
if ((bit_order_1x == 1'b0) || (DWIDTH_RATIO == 2))
begin
next_wr_addr_1x = wr_addr_1x;
end
end
else if (sync_seq_poa_lat_inc_1x == 1'b1 && seq_poa_lat_inc_1x_1t == 1'b0)
begin
if ((bit_order_1x == 1'b1) || (DWIDTH_RATIO ==2))
begin
next_wr_addr_1x = wr_addr_1x + 2'b10;
end
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wr_addr_1x <= POSTAMBLE_INITIAL_LAT[POSTAMBLE_AWIDTH - 1 : 0];
end
else
begin
wr_addr_1x <= next_wr_addr_1x;
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_doing_rd_beat2_1x_r1 <= 1'b0;
seq_poa_lat_inc_1x_1t <= 1'b0;
seq_poa_lat_dec_1x_1t <= 1'b0;
bit_order_1x <= 1'b0;
end
else
begin
ctl_doing_rd_beat2_1x_r1 <= ctl_doing_rd_beat2_1x;
seq_poa_lat_inc_1x_1t <= sync_seq_poa_lat_inc_1x;
seq_poa_lat_dec_1x_1t <= sync_seq_poa_lat_dec_1x;
if (DWIDTH_RATIO == 2)
bit_order_1x <= 1'b0;
else if (sync_seq_poa_lat_dec_1x == 1'b1 && seq_poa_lat_dec_1x_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
else if (sync_seq_poa_lat_inc_1x == 1'b1 && seq_poa_lat_inc_1x_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
end
end
///////////////////////////////////////////////////////////////////////////////////
// Instantiate the postamble dpram
///////////////////////////////////////////////////////////////////////////////////
assign wr_en_1x = 1'b1;
generate
// Half-rate mode :
if (DWIDTH_RATIO == 4)
begin : half_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**POSTAMBLE_AWIDTH )/2),
.numwords_b ((2**POSTAMBLE_AWIDTH )),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (POSTAMBLE_AWIDTH - 1),
.widthad_b (POSTAMBLE_AWIDTH),
.width_a (2),
.width_b (1),
.width_byteena_a (1)
) altsyncram_inst (
.wren_a (wr_en_1x),
.clock0 (phy_clk_1x),
.clock1 (postamble_clk_2x),
.address_a (wr_addr_1x[POSTAMBLE_AWIDTH - 2 : 0]),
.address_b (rd_addr_2x),
.data_a (wr_data_1x),
.q_b (postamble_en_2x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b (1'b1),
.q_a (),
.rden_a (),
.rden_b (1'b1),
.wren_b (1'b0),
.eccstatus ()
);
end
// Full-rate mode :
else
begin : full_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**POSTAMBLE_AWIDTH ),
.numwords_b (2**POSTAMBLE_AWIDTH ),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("UNREGISTERED"),
.power_up_uninitialized ("FALSE"),
.widthad_a (POSTAMBLE_AWIDTH),
.widthad_b (POSTAMBLE_AWIDTH),
.width_a (1),
.width_b (1),
.width_byteena_a (1)
) altsyncram_inst (
.wren_a (wr_en_1x),
.clock0 (phy_clk_1x),
.clock1 (postamble_clk_2x),
.address_a (wr_addr_1x),
.address_b (rd_addr_2x),
.data_a (wr_data_1x[0]),
.q_b (postamble_en_2x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b (1'b1),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
end
endgenerate
///////////////////////////////////////////////////////////////////////////////////
// read address generator : just a free running counter.
///////////////////////////////////////////////////////////////////////////////////
always @(posedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
rd_addr_2x <= {POSTAMBLE_AWIDTH{1'b0}};
end
else
begin
rd_addr_2x <= rd_addr_2x + 1'b1; //inc address, can wrap
end
end
///////////////////////////////////////////////////////////////////////////////////
// generate the poa_postamble_en_preset_2x signal, 2 generate statements dependent
// on generics - both contained within another generate to produce output of
// appropriate width
///////////////////////////////////////////////////////////////////////////////////
generate
for (i=0; i<MEM_IF_POSTAMBLE_EN_WIDTH; i=i+1)
begin : postamble_output_gen
always @(posedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin :pipeline_ram_op
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_2x_r[i] <= 1'b0;
end
else
begin
postamble_en_2x_r[i] <= postamble_en_2x;
end
end
always @(posedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_pos_2x[i] <= 1'b0;
end
else
begin
postamble_en_pos_2x[i] <= postamble_en_2x_r[i];
end
end
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_off
`endif
// Introduce 180degrees to model postamble insertion delay :
always @(negedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_pos_2x_vdc[i] <= 1'b0;
end
else
begin
postamble_en_pos_2x_vdc[i] <= postamble_en_pos_2x[i];
end
end
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_on
`endif
always @*
begin
delayed_postamble_en_pos_2x[i] = postamble_en_pos_2x[i];
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_off
`endif
delayed_postamble_en_pos_2x[i] = postamble_en_pos_2x_vdc[i];
`ifdef QUARTUS__SIMGEN
`else
//synopsys translate_on
`endif
end
case (POSTAMBLE_HALFT_EN)
1: begin : half_t_output
(* preserve *) reg [MEM_IF_POSTAMBLE_EN_WIDTH - 1 : 0] postamble_en_neg_2x;
always @(negedge postamble_clk_2x or negedge reset_poa_clk_2x_n)
begin
if (reset_poa_clk_2x_n == 1'b0)
begin
postamble_en_neg_2x[i] <= 1'b0;
end
else
begin
postamble_en_neg_2x[i] <= postamble_en_pos_2x[i];
end
end
assign poa_postamble_en_preset_2x[i] = postamble_en_pos_2x[i] && postamble_en_neg_2x[i];
end
0: begin : one_t_output
assign poa_postamble_en_preset_2x[i] = delayed_postamble_en_pos_2x[i];
end
endcase
end
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_read_dp ( phy_clk_1x,
resync_clk_2x,
reset_phy_clk_1x_n,
reset_resync_clk_2x_n,
seq_rdp_dec_read_lat_1x,
seq_rdp_dmx_swap,
seq_rdp_inc_read_lat_1x,
dio_rdata_h_2x,
dio_rdata_l_2x,
ctl_mem_rdata
);
parameter ADDR_COUNT_WIDTH = 4;
parameter BIDIR_DPINS = 1; // 0 for QDR only.
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_CLK_PS = 4000;
parameter FAMILY = "Stratix II";
parameter LOCAL_IF_DWIDTH = 256;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter MEM_IF_DWIDTH = 64;
parameter MEM_IF_PHY_NAME = "STRATIXII_DQS";
parameter RDP_INITIAL_LAT = 6;
parameter RDP_RESYNC_LAT_CTL_EN = 0;
parameter RESYNC_PIPELINE_DEPTH = 1;
localparam NUM_DQS_PINS = MEM_IF_DQS_WIDTH;
input wire phy_clk_1x;
input wire resync_clk_2x;
input wire reset_phy_clk_1x_n;
input wire reset_resync_clk_2x_n;
input wire seq_rdp_dec_read_lat_1x;
input wire seq_rdp_dmx_swap;
input wire seq_rdp_inc_read_lat_1x;
input wire [MEM_IF_DWIDTH-1 : 0] dio_rdata_h_2x;
input wire [MEM_IF_DWIDTH-1 : 0] dio_rdata_l_2x;
output wire [LOCAL_IF_DWIDTH-1 : 0] ctl_mem_rdata;
// concatonated read data :
wire [(2*MEM_IF_DWIDTH)-1 : 0] dio_rdata_2x;
reg [ADDR_COUNT_WIDTH - DWIDTH_RATIO/2 : 0] rd_ram_rd_addr;
reg [ADDR_COUNT_WIDTH - 1 : 0] rd_ram_wr_addr;
wire [(2*MEM_IF_DWIDTH)-1 : 0] rd_data_piped_2x;
reg inc_read_lat_sync_r;
reg dec_read_lat_sync_r;
// Optional AMS registers :
reg inc_read_lat_ams;
reg inc_read_lat_sync;
reg dec_read_lat_ams;
reg dec_read_lat_sync;
reg state;
reg dmx_swap_ams;
reg dmx_swap_sync;
reg dmx_swap_sync_r;
wire wr_addr_toggle_detect;
wire wr_addr_stall;
wire wr_addr_double_inc;
wire rd_addr_stall;
wire rd_addr_double_inc;
// Read data from ram, prior to mapping/re-ordering :
wire [LOCAL_IF_DWIDTH-1 : 0] ram_rdata_1x;
////////////////////////////////////////////////////////////////////////////////
// Write Address block
////////////////////////////////////////////////////////////////////////////////
// 'toggle detect' logic :
assign wr_addr_toggle_detect = !dmx_swap_sync_r && dmx_swap_sync;
// 'stall' logic :
assign wr_addr_stall = !(~state && wr_addr_toggle_detect);
// 'double_inc' logic :
assign wr_addr_double_inc = state && wr_addr_toggle_detect;
// Write address generation
// When no demux toggle - increment every clock cycle
// When demux toggle is detected,invert addr_stall
// if addr_stall is 1 then do nothing to address, else double increment this cycle.
always@ (posedge resync_clk_2x or negedge reset_resync_clk_2x_n)
begin
if (reset_resync_clk_2x_n == 0)
begin
rd_ram_wr_addr <= RDP_INITIAL_LAT[3:0];
state <= 1'b0;
dmx_swap_ams <= 1'b0;
dmx_swap_sync <= 1'b0;
dmx_swap_sync_r <= 1'b0;
end
else
begin
// Synchronise dmx_swap :
dmx_swap_ams <= seq_rdp_dmx_swap;
dmx_swap_sync <= dmx_swap_ams;
dmx_swap_sync_r <= dmx_swap_sync;
// RAM write address :
if (wr_addr_stall == 1'b1)
begin
rd_ram_wr_addr <= rd_ram_wr_addr + 1'b1 + wr_addr_double_inc;
end
// Maintain single bit state :
if (wr_addr_toggle_detect == 1'b1)
begin
state <= ~state;
end
end
end
////////////////////////////////////////////////////////////////////////////////
// Pipeline registers
////////////////////////////////////////////////////////////////////////////////
// Concatenate the input read data taking note of ram input datawidths
// This is concatenating rdata_p and rdata_n from a DQS group together so that the rest
// of the pipeline can use a single vector:
generate
genvar dqs_group_num;
for (dqs_group_num = 0; dqs_group_num < NUM_DQS_PINS ; dqs_group_num = dqs_group_num + 1)
begin : ddio_remap
assign dio_rdata_2x[2*MEM_IF_DQ_PER_DQS*dqs_group_num + 2*MEM_IF_DQ_PER_DQS-1: 2*MEM_IF_DQ_PER_DQS*dqs_group_num]
= { dio_rdata_l_2x[MEM_IF_DQ_PER_DQS*dqs_group_num + MEM_IF_DQ_PER_DQS-1: MEM_IF_DQ_PER_DQS*dqs_group_num],
dio_rdata_h_2x[MEM_IF_DQ_PER_DQS*dqs_group_num + MEM_IF_DQ_PER_DQS-1: MEM_IF_DQ_PER_DQS*dqs_group_num]
};
end
endgenerate
// Generate appropriate pipeline depth
generate
genvar i;
if (RESYNC_PIPELINE_DEPTH > 0)
begin : resync_pipeline_gen
// Declare pipeline registers
reg [(2*MEM_IF_DWIDTH)-1 : 0 ] pipeline_delay [0 : RESYNC_PIPELINE_DEPTH - 1] ;
for (i=0; i< RESYNC_PIPELINE_DEPTH; i = i + 1)
begin : PIPELINE
always @(posedge resync_clk_2x)
begin
if (i==0)
pipeline_delay[i] <= dio_rdata_2x;
else
pipeline_delay[i] <= pipeline_delay[i-1];
end //always
end //for
assign rd_data_piped_2x = pipeline_delay[RESYNC_PIPELINE_DEPTH-1];
end
// If pipeline registers are not configured, pass-thru :
else
begin : no_resync_pipe_gen
assign rd_data_piped_2x = dio_rdata_2x;
end
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Instantiate the read_dp dpram
////////////////////////////////////////////////////////////////////////////////
generate
if (DWIDTH_RATIO == 4)
begin : half_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**ADDR_COUNT_WIDTH )),
.numwords_b ((2**ADDR_COUNT_WIDTH )/2),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (ADDR_COUNT_WIDTH),
.widthad_b (ADDR_COUNT_WIDTH - 1),
.width_a (MEM_IF_DWIDTH*2),
.width_b (MEM_IF_DWIDTH*4),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (1'b1),
.clock0 (resync_clk_2x),
.clock1 (phy_clk_1x),
.address_a (rd_ram_wr_addr),
.address_b (rd_ram_rd_addr),
.data_a (rd_data_piped_2x),
.q_b (ram_rdata_1x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b ({(MEM_IF_DWIDTH*4){1'b1}}),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
// Read data mapping :
genvar dqs_group_num_b;
for (dqs_group_num_b = 0; dqs_group_num_b < NUM_DQS_PINS ; dqs_group_num_b = dqs_group_num_b + 1)
begin : remap_logic
assign ctl_mem_rdata [MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 2 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 3 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 3 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : MEM_IF_DWIDTH * 2 + dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
end
end // block: half_rate_dp
endgenerate
// full-rate
generate
if (DWIDTH_RATIO == 2)
begin : full_rate_ram_gen
altsyncram #(
.address_reg_b ("CLOCK1"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a ((2**ADDR_COUNT_WIDTH )),
.numwords_b ((2**ADDR_COUNT_WIDTH )),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK1"),
.power_up_uninitialized ("FALSE"),
.widthad_a (ADDR_COUNT_WIDTH),
.widthad_b (ADDR_COUNT_WIDTH),
.width_a (MEM_IF_DWIDTH*2),
.width_b (MEM_IF_DWIDTH*2),
.width_byteena_a (1)
) altsyncram_component(
.wren_a (1'b1),
.clock0 (resync_clk_2x),
.clock1 (phy_clk_1x),
.address_a (rd_ram_wr_addr),
.address_b (rd_ram_rd_addr),
.data_a (rd_data_piped_2x),
.q_b (ram_rdata_1x),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (),
.clocken3 (),
.data_b ({(MEM_IF_DWIDTH*2){1'b1}}),
.q_a (),
.rden_b (1'b1),
.rden_a (),
.wren_b (1'b0),
.eccstatus ()
);
// Read data mapping :
genvar dqs_group_num_b;
for (dqs_group_num_b = 0; dqs_group_num_b < NUM_DQS_PINS ; dqs_group_num_b = dqs_group_num_b + 1)
begin : remap_logic
assign ctl_mem_rdata [MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 0 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS ];
assign ctl_mem_rdata [MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS -1 : MEM_IF_DWIDTH * 1 + dqs_group_num_b * MEM_IF_DQ_PER_DQS ] = ram_rdata_1x [ dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + 2 * MEM_IF_DQ_PER_DQS - 1 : dqs_group_num_b * 2 * MEM_IF_DQ_PER_DQS + MEM_IF_DQ_PER_DQS ];
end
end // block: half_rate_dp
endgenerate
////////////////////////////////////////////////////////////////////////////////
// Read Address block
////////////////////////////////////////////////////////////////////////////////
// Optional Anti-metastability flops :
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin : rd_addr_ams
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_ams <= 1'b0;
inc_read_lat_sync <= 1'b0;
inc_read_lat_sync_r <= 1'b0;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= 1'b0;
dec_read_lat_sync <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// Synchronise rd_lat_inc_1x :
inc_read_lat_ams <= seq_rdp_inc_read_lat_1x;
inc_read_lat_sync <= inc_read_lat_ams;
inc_read_lat_sync_r <= inc_read_lat_sync;
// Synchronise rd_lat_inc_1x :
dec_read_lat_ams <= seq_rdp_dec_read_lat_1x;
dec_read_lat_sync <= dec_read_lat_ams;
dec_read_lat_sync_r <= dec_read_lat_sync;
end
end // always
// No anti-metastability protection required :
else
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
inc_read_lat_sync_r <= 1'b0;
dec_read_lat_sync_r <= 1'b0;
end
else
begin
// No need to re-synchronise, just register for edge detect :
inc_read_lat_sync_r <= seq_rdp_inc_read_lat_1x;
dec_read_lat_sync_r <= seq_rdp_dec_read_lat_1x;
end
end
endgenerate
generate
if (RDP_RESYNC_LAT_CTL_EN == 1)
begin : lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && inc_read_lat_sync;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && dec_read_lat_sync );
// 'stall' logic :
// assign rd_addr_stall = !( !dec_read_lat_sync_r && dec_read_lat_sync );
assign rd_addr_stall = !inc_read_lat_sync_r && inc_read_lat_sync;
end
else
begin : no_lat_ctl_en_gen
// 'toggle detect' logic :
//assign rd_addr_double_inc = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
assign rd_addr_double_inc = ( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
// 'stall' logic :
//assign rd_addr_stall = !( !dec_read_lat_sync_r && seq_rdp_dec_read_lat_1x );
assign rd_addr_stall = !inc_read_lat_sync_r && seq_rdp_inc_read_lat_1x;
end
endgenerate
always@ (posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 0)
begin
rd_ram_rd_addr <= { ADDR_COUNT_WIDTH - DWIDTH_RATIO/2 {1'b0} };
end
else
begin
// RAM read address :
if (rd_addr_stall == 1'b0)
begin
rd_ram_rd_addr <= rd_ram_rd_addr + 1'b1 + rd_addr_double_inc;
end
end
end
endmodule
//
// Note, this write datapath logic matches both the spec, and what was done in
// the beta project.
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_write_dp(
// clocks
phy_clk_1x, // half-rate clock
mem_clk_2x, // full-rate clock
write_clk_2x, // full-rate clock
// active-low resets, sync'd to clock domain
reset_phy_clk_1x_n,
reset_mem_clk_2x_n,
reset_write_clk_2x_n,
// control i/f inputs
ctl_mem_be,
ctl_mem_dqs_burst,
ctl_mem_wdata,
ctl_mem_wdata_valid,
// seq i/f inputs :
seq_be,
seq_dqs_burst,
seq_wdata,
seq_wdata_valid,
seq_ctl_sel,
// outputs to IOEs
wdp_wdata_h_2x,
wdp_wdata_l_2x,
wdp_wdata_oe_2x,
wdp_wdqs_2x,
wdp_wdqs_oe_2x,
wdp_dm_h_2x,
wdp_dm_l_2x
);
// parameter declarations
parameter MEM_IF_MEMTYPE = "DDR2";
parameter BIDIR_DPINS = 1;
parameter LOCAL_IF_DRATE = "HALF";
parameter LOCAL_IF_DWIDTH = 256;
parameter MEM_IF_DM_WIDTH = 8;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DQS_WIDTH = 8;
parameter GENERATE_WRITE_DQS = 1;
parameter MEM_IF_DWIDTH = 64;
parameter DWIDTH_RATIO = 4;
parameter MEM_IF_DM_PINS_EN = 1;
// "internal" parameter, not to get propagated from higher levels...
parameter NUM_DUPLICATE_REGS = 4; // 1 per nibble to save registers
// clocks
input wire phy_clk_1x; // half-rate system clock
input wire mem_clk_2x; // full-rate memory clock
input wire write_clk_2x; // full-rate write clock
// resets, async assert, de-assert is sync'd to each clock domain
input wire reset_phy_clk_1x_n;
input wire reset_mem_clk_2x_n;
input wire reset_write_clk_2x_n;
// control i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] ctl_mem_be; // byte enable == ~data mask
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_dqs_burst; // dqs burst indication
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] ctl_mem_wdata; // write data
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] ctl_mem_wdata_valid; // write data valid indication
// seq i/f inputs
input wire [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0] seq_be;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_dqs_burst;
input wire [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0] seq_wdata;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] seq_wdata_valid;
input wire seq_ctl_sel;
(*preserve*) output reg [MEM_IF_DWIDTH - 1 : 0 ] wdp_wdata_h_2x; // wdata_h to IOE
(*preserve*) output reg [MEM_IF_DWIDTH - 1 : 0 ] wdp_wdata_l_2x; // wdata_l to IOE
(*preserve*) output reg [MEM_IF_DM_WIDTH - 1 : 0 ] wdp_dm_h_2x; // dm_h to IOE
(*preserve*) output reg [MEM_IF_DM_WIDTH - 1 : 0 ] wdp_dm_l_2x; // dm_l to IOE
output wire [MEM_IF_DWIDTH - 1 : 0 ] wdp_wdata_oe_2x; // OE to DQ pin
output wire [MEM_IF_DQS_WIDTH - 1 : 0 ] wdp_wdqs_2x; // DQS to IOE
output wire [MEM_IF_DQS_WIDTH - 1 : 0 ] wdp_wdqs_oe_2x; // OE to DQS pin
// internal reg declarations
// registers (on a per- DQS group basis) which sync the dqs_burst_1x to phy_clk or mem_clk_2x.
// They are used to generate the DQS signal and its OE.
(*preserve*) reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0 ] dqs_burst_1x_r;
(*preserve*) reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0 ] dqs_burst_2x_r1;
(*preserve*) reg [MEM_IF_DQS_WIDTH - 1 : 0 ] dqs_burst_2x_r2;
(*preserve*) reg [MEM_IF_DQS_WIDTH - 1 : 0 ] dqs_burst_2x_r3;
(*preserve*) reg [MEM_IF_DQS_WIDTH - 1 : 0 ] dqs_burst2_1x_r;
(*preserve*) reg [MEM_IF_DQS_WIDTH - 1 : 0 ] dqs_burst2_2x_r1;
(*preserve*) reg [MEM_IF_DQS_WIDTH - 1 : 0 ] dqs_burst2_2x_r2;
(*preserve*) reg [MEM_IF_DQS_WIDTH - 1 : 0 ] dqs_burst2_2x_r3;
(*preserve*) reg [MEM_IF_DQS_WIDTH - 1 : 0 ] dqs_burst_sel;
// registers to generate the dq_oe, on a per nibble basis, to save registers.
(*preserve*) reg [(DWIDTH_RATIO/2)*MEM_IF_DWIDTH/NUM_DUPLICATE_REGS - 1 : 0 ] wdata_valid_1x_r1; // wdata_valid_1x, retimed in phy_clk_1x
(*preserve*) reg [(DWIDTH_RATIO/2)*MEM_IF_DWIDTH/NUM_DUPLICATE_REGS - 1 : 0 ] wdata_valid_1x_r2; // wdata_valid_1x_r1, retimed in phy_clk_1x
(* preserve, altera_attribute = "-name ADV_NETLIST_OPT_ALLOWED \"NEVER ALLOW\"" *) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS -1 : 0 ] dq_oe_2x; // 1 per nibble, to save registers
reg [MEM_IF_DWIDTH - 1 : 0 ] wdp_wdata_oe_2x_int; // intermediate output, gets assigned to o/p signal
reg [LOCAL_IF_DWIDTH - 1 : 0 ] mem_wdata_r1; // ctl_mem_wdata, retimed in phy_clk_1x
reg [LOCAL_IF_DWIDTH - 1 : 0 ] mem_wdata_r2; // ctl_mem_wdata_r1, retimed in phy_clk_1x
// registers used to generate the mux select signal for wdata.
(*preserve*) reg [(DWIDTH_RATIO/2)*MEM_IF_DWIDTH/NUM_DUPLICATE_REGS - 1 : 0 ] wdata_valid_1x_r; // 1 per nibble, to save registers
(*preserve*) reg [(DWIDTH_RATIO/2)*MEM_IF_DWIDTH/NUM_DUPLICATE_REGS - 1 : 0 ] wdata_valid_2x_r1; // 1 per nibble, to save registers
(*preserve*) reg [(DWIDTH_RATIO/2)*MEM_IF_DWIDTH/NUM_DUPLICATE_REGS - 1 : 0 ] wdata_valid_2x_r2; // 1 per nibble, to save registers
(*preserve*) reg [MEM_IF_DWIDTH/NUM_DUPLICATE_REGS - 1 : 0 ] wdata_sel; // 1 per nibble, to save registers
// registers used to generate the dm mux select and dm signals
reg [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0 ] mem_dm_r1;
reg [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0 ] mem_dm_r2;
(*preserve*) reg wdata_dm_1x_r; // preserved, to stop merge with wdata_valid_1x_r
(*preserve*) reg wdata_dm_2x_r1; // preserved, to stop merge with wdata_valid_2x_r1
(*preserve*) reg wdata_dm_2x_r2; // preserved, to stop merge with wdata_valid_2x_r2
(*preserve*) reg dm_sel; // preserved, to stop merge with wdata_sel
// MUX outputs....
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0 ] mem_dqs_burst;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0 ] mem_wdata_valid;
reg [MEM_IF_DM_WIDTH * DWIDTH_RATIO - 1 : 0 ] mem_be;
reg [MEM_IF_DWIDTH * DWIDTH_RATIO - 1 : 0 ] mem_wdata;
always @*
begin
// Select controller or sequencer according to the select signal :
if (seq_ctl_sel)
begin
mem_dqs_burst = seq_dqs_burst;
mem_be = seq_be;
mem_wdata = seq_wdata;
mem_wdata_valid = seq_wdata_valid;
end
else
begin
mem_dqs_burst = ctl_mem_dqs_burst;
mem_be = ctl_mem_be;
mem_wdata = ctl_mem_wdata;
mem_wdata_valid = ctl_mem_wdata_valid;
end
end
genvar a, b, c, d; // variable for generate statement
integer i, j; // variable for loop counters
/////////////////////////////////////////////////////////////////////////
// generate the following write DQS logic on a per DQS group basis.
// wdp_wdqs_2x and wdp_wdqs_oe_2x get output to the IOEs.
////////////////////////////////////////////////////////////////////////
generate
if (GENERATE_WRITE_DQS == 1)
begin
for (a=0; a<MEM_IF_DQS_WIDTH; a = a+1)
begin : gen_loop_dqs
// select signal generation
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
dqs_burst2_1x_r[a] <= 1'b0;
end
else
begin
dqs_burst2_1x_r[a] <= mem_dqs_burst[a];
end
end
always @(posedge mem_clk_2x or negedge reset_mem_clk_2x_n)
begin
if (reset_mem_clk_2x_n == 1'b0)
begin
dqs_burst2_2x_r1[a] <= 1'b0;
dqs_burst2_2x_r2[a] <= 1'b0;
dqs_burst2_2x_r3[a] <= 1'b0;
end
else
begin
dqs_burst2_2x_r1[a] <= dqs_burst2_1x_r[a];
dqs_burst2_2x_r2[a] <= dqs_burst2_2x_r1[a];
dqs_burst2_2x_r3[a] <= dqs_burst2_2x_r2[a];
end
end
always @(posedge mem_clk_2x or negedge reset_mem_clk_2x_n)
begin
if (reset_mem_clk_2x_n == 1'b0)
begin
dqs_burst_sel[a] <= 1'b0;
end
else
begin
if (~dqs_burst2_2x_r3[a] && dqs_burst2_2x_r2[a])
begin
dqs_burst_sel[a] <= 1'b0;
end
else
begin
dqs_burst_sel[a] <= ~dqs_burst_sel[a];
end
end
end
// logic for wdp_wdqs_2x and wdp_wdqs_oe_2x generation
for (b=0; b<DWIDTH_RATIO/2; b=b+1)
begin : gen_loop_hr
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
dqs_burst_1x_r[a + b*MEM_IF_DQS_WIDTH] <= 1'b0;
end
else
begin
// mem_wdata_valid lags mem_dqs_burst by 1 memory clock cycle and is 1 memory clock cycle shorter
// than mem_dqs_burst. Therefore mem_dqs_burst is used for DDR3 to prepend 1 memory cycle of preamble
// on DQS wrt to the DDR/DDR2 case
if (MEM_IF_MEMTYPE == "DDR3")
begin
dqs_burst_1x_r[a + b*MEM_IF_DQS_WIDTH] <= mem_dqs_burst[a + b*MEM_IF_DQS_WIDTH];
end
else
begin
dqs_burst_1x_r[a + b*MEM_IF_DQS_WIDTH] <= mem_wdata_valid[a + b*MEM_IF_DQS_WIDTH];
end
end
end
always @(posedge mem_clk_2x or negedge reset_mem_clk_2x_n)
begin
if (reset_mem_clk_2x_n == 1'b0)
begin
dqs_burst_2x_r1[a + b*MEM_IF_DQS_WIDTH] <= 1'b0;
end
else
begin
dqs_burst_2x_r1[a + b*MEM_IF_DQS_WIDTH] <= dqs_burst_1x_r[a + b*MEM_IF_DQS_WIDTH];
end
end
end
// HR to FR mux
always @(posedge mem_clk_2x or negedge reset_mem_clk_2x_n)
begin
if (reset_mem_clk_2x_n == 1'b0)
begin
dqs_burst_2x_r2[a] <= 1'b0;
end
else
begin
if (dqs_burst_sel[a] == 1'b1)
begin
dqs_burst_2x_r2[a] <= dqs_burst_2x_r1[a + MEM_IF_DQS_WIDTH];
end
else
begin
dqs_burst_2x_r2[a] <= dqs_burst_2x_r1[a];
end
end
end
always @(posedge mem_clk_2x or negedge reset_mem_clk_2x_n)
begin
if (reset_mem_clk_2x_n == 1'b0)
begin
dqs_burst_2x_r3[a] <= 1'b0;
end
else
begin
dqs_burst_2x_r3[a] <= dqs_burst_2x_r2[a];
end
end
assign wdp_wdqs_2x[a] = dqs_burst_2x_r3[a];
if (MEM_IF_MEMTYPE == "DDR3")
begin
assign wdp_wdqs_oe_2x[a] = dqs_burst_2x_r3[a];
end
else
begin
assign wdp_wdqs_oe_2x[a] = dqs_burst_2x_r2[a] || dqs_burst_2x_r3[a];
end
end
end
endgenerate
///////////////////////////////////////////////////////////////////
// Generate the write DQ logic.
// These are internal registers which will be used to assign to:
// wdp_wdata_h_2x, wdp_wdata_l_2x, wdp_wdata_oe_2x
// (these get output to the IOEs).
//////////////////////////////////////////////////////////////////
generate
for (a=0; a<MEM_IF_DQS_WIDTH; a=a+1) // loop over DQS
begin : wdata_valid_per_dqs
for (b=0; b<(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS); b=b+1) // iterate over repetitions required
begin : wdata_valid_duplication
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wdata_valid_1x_r1[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b] <= 1'b0;
wdata_valid_1x_r1[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b + (MEM_IF_DWIDTH/NUM_DUPLICATE_REGS)] <= 1'b0;
end
else
begin
wdata_valid_1x_r1[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b] <= mem_wdata_valid[a];
wdata_valid_1x_r1[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b + (MEM_IF_DWIDTH/NUM_DUPLICATE_REGS)] <= mem_wdata_valid[a+MEM_IF_DQS_WIDTH];
end
end
end
end
endgenerate
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wdata_valid_1x_r2 <= {((DWIDTH_RATIO/2)*(MEM_IF_DWIDTH/NUM_DUPLICATE_REGS)){1'b0}}; // one per nibble, to save registers
end
else
begin
wdata_valid_1x_r2 <= wdata_valid_1x_r1;
end
end
generate
for (b=0; b<MEM_IF_DWIDTH/NUM_DUPLICATE_REGS; b=b+1)
begin : gen_dq_oe_2x
always @(posedge write_clk_2x or negedge reset_write_clk_2x_n)
begin
if (reset_write_clk_2x_n == 1'b0)
begin
dq_oe_2x[b] <= 1'b0;
end
else
begin
if (wdata_sel[b] == 1'b1)
begin
dq_oe_2x[b] <= wdata_valid_1x_r2[b+(MEM_IF_DWIDTH/NUM_DUPLICATE_REGS)];
end
else
begin
dq_oe_2x[b] <= wdata_valid_1x_r2[b];
end
end
end
end // gen_dq_oe_2x
endgenerate
////////////////////////////////////////////////////////////////////////////////
// fanout the dq_oe_2x, which has one register per NUM_DUPLICATE_REGS
// (to save registers), to each bit of wdp_wdata_oe_2x_int and then
// assign to the output wire wdp_wdata_oe_2x( ie one oe for each DQ "pin").
////////////////////////////////////////////////////////////////////////////////
always @(dq_oe_2x)
begin
for (j=0; j<MEM_IF_DWIDTH; j=j+1)
begin
wdp_wdata_oe_2x_int[j] = dq_oe_2x[(j/NUM_DUPLICATE_REGS)];
end
end
assign wdp_wdata_oe_2x = wdp_wdata_oe_2x_int;
//////////////////////////////////////////////////////////////////////
// Generation of wdata_sel (dq mux sel logic), on a per nibble basis.
/////////////////////////////////////////////////////////////////////
generate
for (a=0; a<MEM_IF_DQS_WIDTH; a=a+1) // loop over DQS
begin : wdata_valid_per_dqs_2
for (b=0; b<(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS); b=b+1) // iterate over repetitions required
begin : wdata_valid_duplication_2
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wdata_valid_1x_r[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b] <= 1'b0;
wdata_valid_1x_r[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b + (MEM_IF_DWIDTH/NUM_DUPLICATE_REGS)] <= 1'b0;
end
else
begin
wdata_valid_1x_r[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b] <= mem_wdata_valid[a];
wdata_valid_1x_r[(a*(MEM_IF_DQ_PER_DQS/NUM_DUPLICATE_REGS)) + b + (MEM_IF_DWIDTH/NUM_DUPLICATE_REGS)] <= mem_wdata_valid[a+MEM_IF_DQS_WIDTH];
end
end
end
end
endgenerate
always @(posedge write_clk_2x)
begin
wdata_valid_2x_r1 <= wdata_valid_1x_r;
wdata_valid_2x_r2 <= wdata_valid_2x_r1;
end
generate
for (b=0; b<MEM_IF_DWIDTH/NUM_DUPLICATE_REGS; b=b+1)
begin : gen_wdata_sel
always @(posedge write_clk_2x)
begin
if (wdata_valid_2x_r1[b] & ~wdata_valid_2x_r2[b])
begin
wdata_sel[b] <= 1'b0;
end
else
begin
wdata_sel[b] <= ~wdata_sel[b];
end
end
end
endgenerate
//////////////////////////////////////////////////////////////////////
// Write DQ mapping from mem_wdata_r2 to wdata_l_2x, wdata_h_2x
//////////////////////////////////////////////////////////////////////
always @(posedge phy_clk_1x)
begin
mem_wdata_r1 <= mem_wdata;
mem_wdata_r2 <= mem_wdata_r1;
end
generate
for (c=0; c<MEM_IF_DWIDTH; c=c+1)
begin : gen_wdata
always @(posedge write_clk_2x)
begin
// c wdata_sel bit
// 0 0
// 1 0
// 2 0
// 3 0
// 4 1
// etc...
if (wdata_sel[c/NUM_DUPLICATE_REGS] == 1'b1 )
begin
wdp_wdata_l_2x[c] <= mem_wdata_r2[c + 3*MEM_IF_DWIDTH];
wdp_wdata_h_2x[c] <= mem_wdata_r2[c + 2*MEM_IF_DWIDTH];
end
else
begin
wdp_wdata_l_2x[c] <= mem_wdata_r2[c + MEM_IF_DWIDTH];
wdp_wdata_h_2x[c] <= mem_wdata_r2[c ];
end
end
end
endgenerate
///////////////////////////////////////////////////////
// Conditional generation of DM logic, based on generic
///////////////////////////////////////////////////////
generate
if (MEM_IF_DM_PINS_EN == 1'b1)
begin : dm_logic_enabled
///////////////////////////////////////////////////
// Write DM logic: dm_sel generation
//////////////////////////////////////////////////
always @(posedge phy_clk_1x)
begin
wdata_dm_1x_r <= mem_wdata_valid;
end
always @(posedge write_clk_2x)
begin
wdata_dm_2x_r1 <= wdata_dm_1x_r;
wdata_dm_2x_r2 <= wdata_dm_2x_r1;
end
always @(posedge write_clk_2x)
begin
if (wdata_dm_2x_r1 == 1 && wdata_dm_2x_r2 == 0)
begin
dm_sel <= 1'b0;
end
else
begin
dm_sel <= !dm_sel;
end
end
///////////////////////////////////////////////////////////////////
// Write DM logic: assignment to wdp_dm_h_2x, wdp_dm_l_2x
///////////////////////////////////////////////////////////////////
always @(posedge phy_clk_1x)
begin
mem_dm_r1 <= mem_be;
mem_dm_r2 <= mem_dm_r1;
end
// for loop inside a generate statement, but outside a procedural block
// is treated as a nested generate
for (d=0; d<MEM_IF_DM_WIDTH; d=d+1)
begin : gen_dm
always @(posedge write_clk_2x)
begin
// _dm_h_ is 1st and 3rd on the wire , _dm_l_ is 2nd and 4th on the wire
if (dm_sel == 1'b0)
begin
wdp_dm_l_2x[d] <= mem_dm_r2[d+MEM_IF_DM_WIDTH];
wdp_dm_h_2x[d] <= mem_dm_r2[d];
end
else
begin
wdp_dm_l_2x[d] <= mem_dm_r2[d+3*MEM_IF_DM_WIDTH];
wdp_dm_h_2x[d] <= mem_dm_r2[d+2*MEM_IF_DM_WIDTH];
end
end
end // block: gen_dm
end // block: dm_logic_enabled
endgenerate
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
`default_nettype none
//
module ddr3_int_phy_alt_mem_phy_rdata_valid ( // inputs
phy_clk_1x,
reset_phy_clk_1x_n,
seq_rdata_valid_lat_dec,
seq_rdata_valid_lat_inc,
seq_doing_rd,
ctl_doing_rd,
ctl_cal_success,
// outputs
ctl_rdata_valid,
seq_rdata_valid
);
parameter FAMILY = "CYCLONEIII";
parameter MEM_IF_DQS_WIDTH = 8;
parameter RDATA_VALID_AWIDTH = 5;
parameter RDATA_VALID_INITIAL_LAT = 16;
parameter DWIDTH_RATIO = 2;
localparam MAX_RDATA_VALID_DELAY = 2 ** RDATA_VALID_AWIDTH;
localparam RDV_DELAY_SHR_LEN = MAX_RDATA_VALID_DELAY*(DWIDTH_RATIO/2);
// clocks
input wire phy_clk_1x;
// resets
input wire reset_phy_clk_1x_n;
// control signals from sequencer
input wire seq_rdata_valid_lat_dec;
input wire seq_rdata_valid_lat_inc;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] seq_doing_rd;
input wire [MEM_IF_DQS_WIDTH * DWIDTH_RATIO / 2 -1 : 0] ctl_doing_rd;
input wire ctl_cal_success;
// output to IOE
output reg [DWIDTH_RATIO / 2 -1 : 0] ctl_rdata_valid;
output reg [DWIDTH_RATIO / 2 -1 : 0] seq_rdata_valid;
// Internal Signals / Variables
reg [RDATA_VALID_AWIDTH - 1 : 0] rd_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] wr_addr;
reg [RDATA_VALID_AWIDTH - 1 : 0] next_wr_addr;
reg [DWIDTH_RATIO/2 - 1 : 0] wr_data;
wire [DWIDTH_RATIO / 2 -1 : 0] int_rdata_valid;
reg [DWIDTH_RATIO/2 - 1 : 0] rdv_pipe_ip;
reg rdv_pipe_ip_beat2_r;
reg [MEM_IF_DQS_WIDTH * DWIDTH_RATIO/2 - 1 : 0] merged_doing_rd;
reg seq_rdata_valid_lat_dec_1t;
reg seq_rdata_valid_lat_inc_1t;
reg bit_order_1x;
// Generate the input to the RDV delay.
// Also determine the data for the OCT control & postamble paths (merged_doing_rd)
generate
if (DWIDTH_RATIO == 4)
begin : merging_doing_rd_halfrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & {(2 * MEM_IF_DQS_WIDTH) {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[ MEM_IF_DQS_WIDTH - 1 : 0];
rdv_pipe_ip[1] = | merged_doing_rd[2 * MEM_IF_DQS_WIDTH - 1 : MEM_IF_DQS_WIDTH];
end
end
else // DWIDTH_RATIO == 2
begin : merging_doing_rd_fullrate
always @*
begin
merged_doing_rd = seq_doing_rd | (ctl_doing_rd & { MEM_IF_DQS_WIDTH {ctl_cal_success}});
rdv_pipe_ip[0] = | merged_doing_rd[MEM_IF_DQS_WIDTH - 1 : 0];
end
end // else: !if(DWIDTH_RATIO == 4)
endgenerate
// Register inc/dec rdata_valid signals and generate bit_order_1x
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
seq_rdata_valid_lat_dec_1t <= 1'b0;
seq_rdata_valid_lat_inc_1t <= 1'b0;
bit_order_1x <= 1'b1;
end
else
begin
rdv_pipe_ip_beat2_r <= rdv_pipe_ip[DWIDTH_RATIO/2 - 1];
seq_rdata_valid_lat_dec_1t <= seq_rdata_valid_lat_dec;
seq_rdata_valid_lat_inc_1t <= seq_rdata_valid_lat_inc;
if (DWIDTH_RATIO == 2)
bit_order_1x <= 1'b0;
else if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
bit_order_1x <= ~bit_order_1x;
end
end
end
// write data
generate // based on DWIDTH RATIO
if (DWIDTH_RATIO == 4) // Half Rate
begin : halfrate_wdata_gen
always @* // combinational logic sensitivity
begin
if (bit_order_1x == 1'b0)
begin
wr_data = {rdv_pipe_ip[1], rdv_pipe_ip[0]};
end
else
begin
wr_data = {rdv_pipe_ip[0], rdv_pipe_ip_beat2_r};
end
end
end
else // Full-rate
begin : fullrate_wdata_gen
always @* // combinational logic sensitivity
begin
wr_data = rdv_pipe_ip;
end
end
endgenerate
// write address
always @*
begin
next_wr_addr = wr_addr + 1'b1;
if (seq_rdata_valid_lat_dec == 1'b1 && seq_rdata_valid_lat_dec_1t == 1'b0)
begin
if ((bit_order_1x == 1'b0) || (DWIDTH_RATIO == 2))
begin
next_wr_addr = wr_addr;
end
end
else if (seq_rdata_valid_lat_inc == 1'b1 && seq_rdata_valid_lat_inc_1t == 1'b0)
begin
if ((bit_order_1x == 1'b1) || (DWIDTH_RATIO ==2))
begin
next_wr_addr = wr_addr + 2'h2;
end
end
end
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
wr_addr <= RDATA_VALID_INITIAL_LAT[RDATA_VALID_AWIDTH - 1 : 0];
end
else
begin
wr_addr <= next_wr_addr;
end
end
// read address generator : just a free running counter.
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
rd_addr <= {RDATA_VALID_AWIDTH{1'b0}};
end
else
begin
rd_addr <= rd_addr + 1'b1; //inc address, can wrap
end
end
// altsyncram instance
altsyncram #(.
address_aclr_b ("NONE"),
.address_reg_b ("CLOCK0"),
.clock_enable_input_a ("BYPASS"),
.clock_enable_input_b ("BYPASS"),
.clock_enable_output_b ("BYPASS"),
.intended_device_family (FAMILY),
.lpm_type ("altsyncram"),
.numwords_a (2**RDATA_VALID_AWIDTH),
.numwords_b (2**RDATA_VALID_AWIDTH),
.operation_mode ("DUAL_PORT"),
.outdata_aclr_b ("NONE"),
.outdata_reg_b ("CLOCK0"),
.power_up_uninitialized ("FALSE"),
.widthad_a (RDATA_VALID_AWIDTH),
.widthad_b (RDATA_VALID_AWIDTH),
.width_a (DWIDTH_RATIO/2),
.width_b (DWIDTH_RATIO/2),
.width_byteena_a (1)
) altsyncram_component (
.wren_a (1'b1),
.clock0 (phy_clk_1x),
.address_a (wr_addr),
.address_b (rd_addr),
.data_a (wr_data),
.q_b (int_rdata_valid),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH_RATIO/2){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0)
);
// Generate read data valid enable signals for controller and seqencer
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
begin
ctl_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
seq_rdata_valid <= {(DWIDTH_RATIO/2){1'b0}};
end
else
begin
// shift the shift register by DWIDTH_RATIO locations
// rdv_delay_index plus (DWIDTH_RATIO/2)-1 bits counting down
ctl_rdata_valid <= int_rdata_valid & {(DWIDTH_RATIO/2){ctl_cal_success}};
seq_rdata_valid <= int_rdata_valid;
end
end
endmodule
`default_nettype wire
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_mux (
phy_clk_1x,
reset_phy_clk_1x_n,
// MUX Outputs to controller :
ctl_address,
ctl_read_req,
ctl_wdata,
ctl_write_req,
ctl_size,
ctl_be,
ctl_refresh_req,
ctl_burstbegin,
// Controller inputs to the MUX :
ctl_ready,
ctl_wdata_req,
ctl_rdata,
ctl_rdata_valid,
ctl_refresh_ack,
ctl_init_done,
// MUX Select line :
ctl_usr_mode_rdy,
// MUX inputs from local interface :
local_address,
local_read_req,
local_wdata,
local_write_req,
local_size,
local_be,
local_refresh_req,
local_burstbegin,
// MUX outputs to sequencer :
mux_seq_controller_ready,
mux_seq_wdata_req,
// MUX inputs from sequencer :
seq_mux_address,
seq_mux_read_req,
seq_mux_wdata,
seq_mux_write_req,
seq_mux_size,
seq_mux_be,
seq_mux_refresh_req,
seq_mux_burstbegin,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
local_autopch_req,
local_powerdn_req,
local_self_rfsh_req,
local_powerdn_ack,
local_self_rfsh_ack,
// Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
ctl_autopch_req,
ctl_powerdn_req,
ctl_self_rfsh_req,
ctl_powerdn_ack,
ctl_self_rfsh_ack,
// Also MUX some signals from the controller to the local interface :
local_ready,
local_wdata_req,
local_init_done,
local_rdata,
local_rdata_valid,
local_refresh_ack
);
parameter LOCAL_IF_AWIDTH = 26;
parameter LOCAL_IF_DWIDTH = 256;
parameter LOCAL_BURST_LEN_BITS = 1;
parameter MEM_IF_DQ_PER_DQS = 8;
parameter MEM_IF_DWIDTH = 64;
input wire phy_clk_1x;
input wire reset_phy_clk_1x_n;
// MUX Select line :
input wire ctl_usr_mode_rdy;
// MUX inputs from local interface :
input wire [LOCAL_IF_AWIDTH - 1 : 0] local_address;
input wire local_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] local_wdata;
input wire local_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] local_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1 : 0] local_be;
input wire local_refresh_req;
input wire local_burstbegin;
// MUX inputs from sequencer :
input wire [LOCAL_IF_AWIDTH - 1 : 0] seq_mux_address;
input wire seq_mux_read_req;
input wire [LOCAL_IF_DWIDTH - 1 : 0] seq_mux_wdata;
input wire seq_mux_write_req;
input wire [LOCAL_BURST_LEN_BITS - 1 : 0] seq_mux_size;
input wire [(LOCAL_IF_DWIDTH/8) - 1:0] seq_mux_be;
input wire seq_mux_refresh_req;
input wire seq_mux_burstbegin;
// MUX Outputs to controller :
output reg [LOCAL_IF_AWIDTH - 1 : 0] ctl_address;
output reg ctl_read_req;
output reg [LOCAL_IF_DWIDTH - 1 : 0] ctl_wdata;
output reg ctl_write_req;
output reg [LOCAL_BURST_LEN_BITS - 1 : 0] ctl_size;
output reg [(LOCAL_IF_DWIDTH/8) - 1:0] ctl_be;
output reg ctl_refresh_req;
output reg ctl_burstbegin;
// The "ready" input from the controller shall be passed to either the
// local interface if in user mode, or the sequencer :
input wire ctl_ready;
output reg local_ready;
output reg mux_seq_controller_ready;
// The controller's "wdata req" output is similarly passed to either
// the local interface if in user mode, or the sequencer :
input wire ctl_wdata_req;
output reg local_wdata_req;
output reg mux_seq_wdata_req;
input wire ctl_init_done;
output reg local_init_done;
input wire [LOCAL_IF_DWIDTH - 1 : 0] ctl_rdata;
output reg [LOCAL_IF_DWIDTH - 1 : 0] local_rdata;
input wire ctl_rdata_valid;
output reg local_rdata_valid;
input wire ctl_refresh_ack;
output reg local_refresh_ack;
//-> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (User to PHY)
input wire local_autopch_req;
input wire local_powerdn_req;
input wire local_self_rfsh_req;
output reg local_powerdn_ack;
output reg local_self_rfsh_ack;
// --> Changes made to accomodate new ports for self refresh/power-down & Auto precharge in HP Controller (PHY to Controller)
output reg ctl_autopch_req;
output reg ctl_powerdn_req;
output reg ctl_self_rfsh_req;
input wire ctl_powerdn_ack;
input wire ctl_self_rfsh_ack;
wire local_burstbegin_held;
reg burstbegin_hold;
always @(posedge phy_clk_1x or negedge reset_phy_clk_1x_n)
begin
if (reset_phy_clk_1x_n == 1'b0)
burstbegin_hold <= 1'b0;
else
begin
if (local_ready == 1'b0 && (local_write_req == 1'b1 || local_read_req == 1'b1) && local_burstbegin == 1'b1)
burstbegin_hold <= 1'b1;
else if (local_ready == 1'b1 && (local_write_req == 1'b1 || local_read_req == 1'b1))
burstbegin_hold <= 1'b0;
end
end
// Gate the local burstbegin signal with the held version :
assign local_burstbegin_held = burstbegin_hold || local_burstbegin;
always @*
begin
if (ctl_usr_mode_rdy == 1'b1)
begin
// Pass local interface signals to the controller if ready :
ctl_address = local_address;
ctl_read_req = local_read_req;
ctl_wdata = local_wdata;
ctl_write_req = local_write_req;
ctl_size = local_size;
ctl_be = local_be;
ctl_refresh_req = local_refresh_req;
ctl_burstbegin = local_burstbegin_held;
// If in user mode, pass on the controller's ready
// and wdata request signals to the local interface :
local_ready = ctl_ready;
local_wdata_req = ctl_wdata_req;
local_init_done = ctl_init_done;
local_rdata = ctl_rdata;
local_rdata_valid = ctl_rdata_valid;
local_refresh_ack = ctl_refresh_ack;
// Whilst indicate to the sequencer that the controller is busy :
mux_seq_controller_ready = 1'b0;
mux_seq_wdata_req = 1'b0;
// Autopch_req & Local_power_req changes
ctl_autopch_req = local_autopch_req;
ctl_powerdn_req = local_powerdn_req;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = ctl_powerdn_ack;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
else
begin
// Pass local interface signals to the sequencer if not in user mode :
// NB. The controller will have more address bits than the sequencer, so
// these are zero padded :
ctl_address = seq_mux_address;
ctl_read_req = seq_mux_read_req;
ctl_wdata = seq_mux_wdata;
ctl_write_req = seq_mux_write_req;
ctl_size = seq_mux_size; // NB. Should be tied-off when the mux is instanced
ctl_be = seq_mux_be; // NB. Should be tied-off when the mux is instanced
ctl_refresh_req = local_refresh_req; // NB. Should be tied-off when the mux is instanced
ctl_burstbegin = seq_mux_burstbegin; // NB. Should be tied-off when the mux is instanced
// Indicate to the local IF that the controller is busy :
local_ready = 1'b0;
local_wdata_req = 1'b0;
local_init_done = 1'b0;
local_rdata = {LOCAL_IF_DWIDTH{1'b0}};
local_rdata_valid = 1'b0;
local_refresh_ack = ctl_refresh_ack;
// If not in user mode, pass on the controller's ready
// and wdata request signals to the sequencer :
mux_seq_controller_ready = ctl_ready;
mux_seq_wdata_req = ctl_wdata_req;
// Autopch_req & Local_power_req changes
ctl_autopch_req = 1'b0;
ctl_powerdn_req = 1'b0;
ctl_self_rfsh_req = local_self_rfsh_req;
local_powerdn_ack = 1'b0;
local_self_rfsh_ack = ctl_self_rfsh_ack;
end
end
endmodule
//
`default_nettype none
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
/* -----------------------------------------------------------------------------
// module description
---------------------------------------------------------------------------- */
//
module ddr3_int_phy_alt_mem_phy_mimic(
//Inputs
//Clocks
measure_clk, // full rate clock from PLL
mimic_data_in, // Input against which the VT variations
// are tracked (e.g. memory clock)
// Active low reset
reset_measure_clk_n,
//Indicates that the mimic calibration sequence can start
seq_mmc_start, // from sequencer
//Outputs
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
input wire measure_clk;
input wire mimic_data_in;
input wire reset_measure_clk_n;
input wire seq_mmc_start;
output wire mmc_seq_done;
output wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
// Parameters
parameter NUM_MIMIC_SAMPLE_CYCLES = 6;
parameter SHIFT_REG_COUNTER_WIDTH = clogb2(NUM_MIMIC_SAMPLE_CYCLES);
reg [`MIMIC_FSM_WIDTH-1:0] mimic_state;
reg [2:0] seq_mmc_start_metastable;
wire start_edge_detected;
(* altera_attribute=" -name fast_input_register OFF"*) reg [1:0] mimic_data_in_metastable;
wire mimic_data_in_sample;
wire shift_reg_data_out_all_ones;
reg mimic_done_out;
reg mimic_value_captured;
reg [SHIFT_REG_COUNTER_WIDTH : 0] shift_reg_counter;
reg shift_reg_enable;
wire shift_reg_data_in;
reg shift_reg_s_clr;
wire shift_reg_a_clr;
reg [NUM_MIMIC_SAMPLE_CYCLES -1 : 0] shift_reg_data_out;
// shift register which contains the sampled data
always @(posedge measure_clk or posedge shift_reg_a_clr)
begin
if (shift_reg_a_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else
begin
if (shift_reg_s_clr == 1'b1)
begin
shift_reg_data_out <= {NUM_MIMIC_SAMPLE_CYCLES{1'b0}};
end
else if (shift_reg_enable == 1'b1)
begin
shift_reg_data_out <= {(shift_reg_data_out[NUM_MIMIC_SAMPLE_CYCLES -2 : 0]), shift_reg_data_in};
end
end
end
// Metastable-harden mimic_start :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
seq_mmc_start_metastable <= 0;
end
else
begin
seq_mmc_start_metastable[0] <= seq_mmc_start;
seq_mmc_start_metastable[1] <= seq_mmc_start_metastable[0];
seq_mmc_start_metastable[2] <= seq_mmc_start_metastable[1];
end
end
assign start_edge_detected = seq_mmc_start_metastable[1]
&& !seq_mmc_start_metastable[2];
// Metastable-harden mimic_data_in :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_data_in_metastable <= 0;
end
//some mimic paths configurations have another flop inside the wysiwyg ioe
else
begin
mimic_data_in_metastable[0] <= mimic_data_in;
mimic_data_in_metastable[1] <= mimic_data_in_metastable[0];
end
end
assign mimic_data_in_sample = mimic_data_in_metastable[1];
// Main FSM :
always @(posedge measure_clk or negedge reset_measure_clk_n )
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_state <= `MIMIC_IDLE;
mimic_done_out <= 1'b0;
mimic_value_captured <= 1'b0;
shift_reg_counter <= 0;
shift_reg_enable <= 1'b0;
shift_reg_s_clr <= 1'b0;
end
else
begin
case (mimic_state)
`MIMIC_IDLE : begin
shift_reg_counter <= 0;
mimic_done_out <= 1'b0;
shift_reg_s_clr <= 1'b1;
shift_reg_enable <= 1'b1;
if (start_edge_detected == 1'b1)
begin
mimic_state <= `MIMIC_SAMPLE;
shift_reg_counter <= shift_reg_counter + 1'b1;
shift_reg_s_clr <= 1'b0;
end
else
begin
mimic_state <= `MIMIC_IDLE;
end
end // case: MIMIC_IDLE
`MIMIC_SAMPLE : begin
shift_reg_counter <= shift_reg_counter + 1'b1;
if (shift_reg_counter == NUM_MIMIC_SAMPLE_CYCLES + 1)
begin
mimic_done_out <= 1'b1;
mimic_value_captured <= shift_reg_data_out_all_ones; //captured only here
shift_reg_enable <= 1'b0;
shift_reg_counter <= shift_reg_counter;
mimic_state <= `MIMIC_SEND;
end
end // case: MIMIC_SAMPLE
`MIMIC_SEND : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND1;
/* mimic_value_captured will not change during MIMIC_SEND
it will change next time mimic_done_out is asserted
mimic_done_out will be reset during MIMIC_IDLE
the purpose of the current state is to add one clock cycle
mimic_done_out will be active for 2 measure_clk clock cycles, i.e
the pulses duration will be just one sequencer clock cycle
(which is half rate) */
end // case: MIMIC_SEND
// MIMIC_SEND1 and MIMIC_SEND2 extend the mimic_done_out signal by another 2 measure_clk_2x cycles
// so it is a total of 4 measure clocks long (ie 2 half-rate clock cycles long in total)
`MIMIC_SEND1 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_SEND2;
end
`MIMIC_SEND2 : begin
mimic_done_out <= 1'b1; //redundant statement, here just for readibility
mimic_state <= `MIMIC_IDLE;
end
default : begin
mimic_state <= `MIMIC_IDLE;
end
endcase
end
end
assign shift_reg_data_out_all_ones = (( & shift_reg_data_out) == 1'b1) ? 1'b1
: 1'b0;
// Shift Register assignments
assign shift_reg_data_in = mimic_data_in_sample;
assign shift_reg_a_clr = !reset_measure_clk_n;
// Output assignments
assign mmc_seq_done = mimic_done_out;
assign mmc_seq_value = mimic_value_captured;
endmodule
`default_nettype wire
//
/* -----------------------------------------------------------------------------
// module description
----------------------------------------------------------------------------- */
//
module ddr3_int_phy_alt_mem_phy_mimic_debug(
// Inputs
// Clocks
measure_clk, // full rate clock from PLL
// Active low reset
reset_measure_clk_n,
mimic_recapture_debug_data, // from user board button
mmc_seq_done, // mimic calibration finished for the current PLL phase
mmc_seq_value // result value of the mimic calibration
);
// Parameters
parameter NUM_DEBUG_SAMPLES_TO_STORE = 4096; // can range from 4096 to 524288
parameter PLL_STEPS_PER_CYCLE = 24; // can range from 16 to 48
input wire measure_clk;
input wire reset_measure_clk_n;
input wire mimic_recapture_debug_data;
input wire mmc_seq_done;
input wire mmc_seq_value;
function integer clogb2;
input [31:0] value;
for (clogb2=0; value>0; clogb2=clogb2+1)
value = value >> 1;
endfunction // clogb2
parameter RAM_WR_ADDRESS_WIDTH = clogb2(NUM_DEBUG_SAMPLES_TO_STORE - 1); // can range from 12 to 19
reg s_clr_ram_wr_address_count;
reg [(clogb2(PLL_STEPS_PER_CYCLE)-1) : 0] mimic_sample_count;
reg [RAM_WR_ADDRESS_WIDTH-1 : 0 ] ram_write_address;
wire ram_wr_enable;
wire [0:0] debug_ram_data;
reg clear_ram_wr_enable;
reg [1:0] mimic_recapture_debug_data_metastable;
wire mimic_done_in_dbg; // for internal use, just 1 measure_clk cycles long
reg mmc_seq_done_r;
// generate mimic_done_in_debug : a single clock wide pulse based on the rising edge of mmc_seq_done:
always @ (posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0) // asynchronous reset (active low)
begin
mmc_seq_done_r <= 1'b0;
end
else
begin
mmc_seq_done_r <= mmc_seq_done;
end
end
assign mimic_done_in_dbg = mmc_seq_done && !mmc_seq_done_r;
assign ram_wr_enable = mimic_done_in_dbg && !clear_ram_wr_enable;
assign debug_ram_data[0] = mmc_seq_value;
altsyncram #(
.clock_enable_input_a ( "BYPASS"),
.clock_enable_output_a ( "BYPASS"),
.intended_device_family ( "Stratix II"),
.lpm_hint ( "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=MRAM"),
.lpm_type ( "altsyncram"),
.maximum_depth ( 4096),
.numwords_a ( 4096),
.operation_mode ( "SINGLE_PORT"),
.outdata_aclr_a ( "NONE"),
.outdata_reg_a ( "UNREGISTERED"),
.power_up_uninitialized ( "FALSE"),
.widthad_a ( 12),
.width_a ( 1),
.width_byteena_a ( 1)
)
altsyncram_component (
.wren_a ( ram_wr_enable),
.clock0 ( measure_clk),
.address_a ( ram_write_address),
.data_a ( debug_ram_data),
.q_a ( )
);
// Metastability_mimic_recapture_debug_data :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_recapture_debug_data_metastable <= 2'b0;
end
else
begin
mimic_recapture_debug_data_metastable[0] <= mimic_recapture_debug_data;
mimic_recapture_debug_data_metastable[1] <= mimic_recapture_debug_data_metastable[0];
end
end
//mimic_sample_counter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
mimic_sample_count <= 0; // (others => '0');
end
else
begin
if (mimic_done_in_dbg == 1'b1)
begin
mimic_sample_count <= mimic_sample_count + 1'b1;
if (mimic_sample_count == PLL_STEPS_PER_CYCLE-1)
begin
mimic_sample_count <= 0; //(others => '0');
end
end
end
end
//RAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b0;
end
else
begin
if (s_clr_ram_wr_address_count == 1'b1) // then --Active high synchronous reset
begin
ram_write_address <= 0; //(others => '0');
clear_ram_wr_enable <= 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b0;
if (mimic_done_in_dbg == 1'b1)
begin
if (ram_write_address != NUM_DEBUG_SAMPLES_TO_STORE-1)
begin
ram_write_address <= ram_write_address + 1'b1;
end
else
begin
clear_ram_wr_enable <= 1'b1;
end
end
end
end
end
//ClearRAMWrAddressCounter :
always @(posedge measure_clk or negedge reset_measure_clk_n)
begin
if (reset_measure_clk_n == 1'b0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
else
begin
if (mimic_recapture_debug_data_metastable[1] == 1'b1)
begin
s_clr_ram_wr_address_count <= 1'b1;
end
else if (mimic_sample_count == 0)
begin
s_clr_ram_wr_address_count <= 1'b0;
end
end
end
endmodule
//
`ifdef ALT_MEM_PHY_DEFINES
`else
`include "alt_mem_phy_defines.v"
`endif
//
module ddr3_int_phy_alt_mem_phy_reset_pipe (
input wire clock,
input wire pre_clear,
output wire reset_out
);
parameter PIPE_DEPTH = 4;
// Declare pipeline registers.
reg [PIPE_DEPTH - 1 : 0] ams_pipe;
integer i;
// begin : RESET_PIPE
always @(posedge clock or negedge pre_clear)
begin
if (pre_clear == 1'b0)
begin
ams_pipe <= 0;
end
else
begin
for (i=0; i< PIPE_DEPTH; i = i + 1)
begin
if (i==0)
ams_pipe[i] <= 1'b1;
else
ams_pipe[i] <= ams_pipe[i-1];
end
end // if-else
end // always
// end
assign reset_out = ams_pipe[PIPE_DEPTH-1];
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Sat Sep 23 13:25:26 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_xbar_1/zqynq_lab_1_design_xbar_1_sim_netlist.v
// Design : zqynq_lab_1_design_xbar_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_xbar_1,axi_crossbar_v2_1_14_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_xbar_1
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input [0:0]s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output [0:0]s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *) output [127:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]" *) output [31:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]" *) output [11:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]" *) output [7:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]" *) output [3:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]" *) output [15:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *) output [11:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]" *) output [15:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]" *) output [15:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *) output [3:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *) input [3:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *) output [127:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *) output [15:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]" *) output [3:0]m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *) output [3:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *) input [3:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *) input [7:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *) input [3:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *) output [3:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *) output [127:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]" *) output [31:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]" *) output [11:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]" *) output [7:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]" *) output [3:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]" *) output [15:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *) output [11:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]" *) output [15:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]" *) output [15:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *) output [3:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *) input [3:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *) input [127:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *) input [7:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]" *) input [3:0]m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *) input [3:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *) output [3:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [127:0]m_axi_araddr;
wire [7:0]m_axi_arburst;
wire [15:0]m_axi_arcache;
wire [31:0]m_axi_arlen;
wire [3:0]m_axi_arlock;
wire [11:0]m_axi_arprot;
wire [15:0]m_axi_arqos;
wire [3:0]m_axi_arready;
wire [15:0]m_axi_arregion;
wire [11:0]m_axi_arsize;
wire [3:0]m_axi_arvalid;
wire [127:0]m_axi_awaddr;
wire [7:0]m_axi_awburst;
wire [15:0]m_axi_awcache;
wire [31:0]m_axi_awlen;
wire [3:0]m_axi_awlock;
wire [11:0]m_axi_awprot;
wire [15:0]m_axi_awqos;
wire [3:0]m_axi_awready;
wire [15:0]m_axi_awregion;
wire [11:0]m_axi_awsize;
wire [3:0]m_axi_awvalid;
wire [3:0]m_axi_bready;
wire [7:0]m_axi_bresp;
wire [3:0]m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [3:0]m_axi_rlast;
wire [3:0]m_axi_rready;
wire [7:0]m_axi_rresp;
wire [3:0]m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire [3:0]m_axi_wlast;
wire [3:0]m_axi_wready;
wire [15:0]m_axi_wstrb;
wire [3:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [47:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [47:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [47:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "0" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_READ_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_SECURE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_M_AXI_WRITE_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "4" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *)
(* C_S_AXI_THREAD_ID_WIDTH = "12" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "4'b1111" *)
(* P_M_AXI_SUPPORTS_WRITE = "4'b1111" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[47:0]),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[3:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[47:0]),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[3:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0,1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0,1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[47:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[3:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_addr_arbiter_sasd" *)
module zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_addr_arbiter_sasd
(aa_grant_any,
m_valid_i,
SR,
aa_grant_rnw,
\m_ready_d_reg[0] ,
\m_ready_d_reg[1] ,
\gen_axi.s_axi_arready_i_reg ,
s_ready_i_reg,
E,
m_valid_i_reg,
D,
\m_axi_arqos[3] ,
f_hot2enc_return0,
\m_atarget_hot_reg[4] ,
\m_atarget_hot_reg[3] ,
\gen_axi.s_axi_wready_i_reg ,
m_ready_d0,
s_axi_wready,
m_axi_wvalid,
\gen_axi.s_axi_wready_i_reg_0 ,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[2] ,
s_axi_bvalid,
m_axi_bready,
\m_ready_d_reg[0]_0 ,
m_axi_awvalid,
\gen_axi.s_axi_awready_i_reg ,
s_axi_rid_i,
m_axi_arvalid,
\m_ready_d_reg[0]_1 ,
s_axi_awready,
s_axi_arready,
\m_atarget_enc_reg[2] ,
\gen_axi.s_axi_rlast_i_reg ,
aclk,
aresetn_d,
\m_atarget_enc_reg[2]_0 ,
\m_atarget_enc_reg[0] ,
m_ready_d,
Q,
m_ready_d_0,
mi_awready,
\m_atarget_hot_reg[4]_0 ,
\m_ready_d_reg[1]_1 ,
\m_atarget_enc_reg[1] ,
s_axi_wvalid,
s_axi_wlast,
write_cs,
\m_atarget_enc_reg[0]_0 ,
s_axi_bready,
\m_atarget_enc_reg[1]_0 ,
\gen_axi.s_axi_bvalid_i_reg ,
\m_atarget_enc_reg[2]_1 ,
\gen_axi.s_axi_awready_i_reg_0 ,
mi_arready,
mi_rvalid,
m_ready_d0_1,
aa_rready,
\gen_axi.read_cs_reg[0] ,
\m_atarget_enc_reg[1]_1 ,
s_axi_rready,
sr_rvalid,
s_axi_arqos,
s_axi_arvalid,
s_axi_awqos,
s_axi_arcache,
s_axi_awcache,
s_axi_arburst,
s_axi_awburst,
s_axi_arprot,
s_axi_awprot,
s_axi_arlock,
s_axi_awlock,
s_axi_arsize,
s_axi_awsize,
s_axi_arlen,
s_axi_awlen,
s_axi_araddr,
s_axi_awaddr,
s_axi_arid,
s_axi_awid,
s_axi_awvalid);
output aa_grant_any;
output m_valid_i;
output [0:0]SR;
output aa_grant_rnw;
output \m_ready_d_reg[0] ;
output \m_ready_d_reg[1] ;
output \gen_axi.s_axi_arready_i_reg ;
output s_ready_i_reg;
output [0:0]E;
output m_valid_i_reg;
output [4:0]D;
output [68:0]\m_axi_arqos[3] ;
output f_hot2enc_return0;
output \m_atarget_hot_reg[4] ;
output \m_atarget_hot_reg[3] ;
output \gen_axi.s_axi_wready_i_reg ;
output [0:0]m_ready_d0;
output [0:0]s_axi_wready;
output [3:0]m_axi_wvalid;
output \gen_axi.s_axi_wready_i_reg_0 ;
output \m_ready_d_reg[1]_0 ;
output \m_ready_d_reg[2] ;
output [0:0]s_axi_bvalid;
output [3:0]m_axi_bready;
output \m_ready_d_reg[0]_0 ;
output [3:0]m_axi_awvalid;
output \gen_axi.s_axi_awready_i_reg ;
output s_axi_rid_i;
output [3:0]m_axi_arvalid;
output \m_ready_d_reg[0]_1 ;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]\m_atarget_enc_reg[2] ;
output \gen_axi.s_axi_rlast_i_reg ;
input aclk;
input aresetn_d;
input \m_atarget_enc_reg[2]_0 ;
input \m_atarget_enc_reg[0] ;
input [1:0]m_ready_d;
input [1:0]Q;
input [2:0]m_ready_d_0;
input [0:0]mi_awready;
input [4:0]\m_atarget_hot_reg[4]_0 ;
input \m_ready_d_reg[1]_1 ;
input \m_atarget_enc_reg[1] ;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_wlast;
input [0:0]write_cs;
input \m_atarget_enc_reg[0]_0 ;
input [0:0]s_axi_bready;
input \m_atarget_enc_reg[1]_0 ;
input \gen_axi.s_axi_bvalid_i_reg ;
input \m_atarget_enc_reg[2]_1 ;
input \gen_axi.s_axi_awready_i_reg_0 ;
input [0:0]mi_arready;
input [0:0]mi_rvalid;
input [0:0]m_ready_d0_1;
input aa_rready;
input \gen_axi.read_cs_reg[0] ;
input \m_atarget_enc_reg[1]_1 ;
input [0:0]s_axi_rready;
input sr_rvalid;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
input [3:0]s_axi_awqos;
input [3:0]s_axi_arcache;
input [3:0]s_axi_awcache;
input [1:0]s_axi_arburst;
input [1:0]s_axi_awburst;
input [2:0]s_axi_arprot;
input [2:0]s_axi_awprot;
input [0:0]s_axi_arlock;
input [0:0]s_axi_awlock;
input [2:0]s_axi_arsize;
input [2:0]s_axi_awsize;
input [7:0]s_axi_arlen;
input [7:0]s_axi_awlen;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [11:0]s_axi_awid;
input [0:0]s_axi_awvalid;
wire [4:0]D;
wire [0:0]E;
wire [1:0]Q;
wire [0:0]SR;
wire aa_grant_any;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire f_hot2enc_return0;
wire \gen_axi.read_cs_reg[0] ;
wire \gen_axi.s_axi_arready_i_reg ;
wire \gen_axi.s_axi_awready_i_reg ;
wire \gen_axi.s_axi_awready_i_reg_0 ;
wire \gen_axi.s_axi_bvalid_i_reg ;
wire \gen_axi.s_axi_rlast_i_i_5_n_0 ;
wire \gen_axi.s_axi_rlast_i_reg ;
wire \gen_axi.s_axi_wready_i_reg ;
wire \gen_axi.s_axi_wready_i_reg_0 ;
wire \gen_no_arbiter.grant_rnw_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_1_n_0 ;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[0]_0 ;
wire \m_atarget_enc_reg[1] ;
wire \m_atarget_enc_reg[1]_0 ;
wire \m_atarget_enc_reg[1]_1 ;
wire [0:0]\m_atarget_enc_reg[2] ;
wire \m_atarget_enc_reg[2]_0 ;
wire \m_atarget_enc_reg[2]_1 ;
wire \m_atarget_hot[1]_i_2_n_0 ;
wire \m_atarget_hot[1]_i_3_n_0 ;
wire \m_atarget_hot[2]_i_2_n_0 ;
wire \m_atarget_hot[2]_i_3_n_0 ;
wire \m_atarget_hot[2]_i_4_n_0 ;
wire \m_atarget_hot_reg[3] ;
wire \m_atarget_hot_reg[4] ;
wire [4:0]\m_atarget_hot_reg[4]_0 ;
wire [68:0]\m_axi_arqos[3] ;
wire [3:0]m_axi_arvalid;
wire [3:0]m_axi_awvalid;
wire [3:0]m_axi_bready;
wire [3:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [0:0]m_ready_d0;
wire [0:0]m_ready_d0_1;
wire \m_ready_d[0]_i_4_n_0 ;
wire \m_ready_d[2]_i_6_n_0 ;
wire [2:0]m_ready_d_0;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[2] ;
wire m_valid_i;
wire m_valid_i_i_2_n_0;
wire m_valid_i_reg;
wire [0:0]mi_arready;
wire [0:0]mi_awready;
wire [0:0]mi_rvalid;
wire p_0_in1_in;
wire [69:0]s_amesg;
wire \s_arvalid_reg[0]_i_1_n_0 ;
wire \s_arvalid_reg_reg_n_0_[0] ;
wire s_awvalid_reg;
wire \s_awvalid_reg[0]_i_1_n_0 ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire s_axi_rid_i;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i;
wire s_ready_i_reg;
wire sr_rvalid;
wire [0:0]write_cs;
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h40))
\gen_axi.s_axi_arready_i_i_3
(.I0(m_ready_d[1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.O(\gen_axi.s_axi_arready_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h04))
\gen_axi.s_axi_awready_i_i_2
(.I0(m_ready_d_0[2]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.O(\gen_axi.s_axi_awready_i_reg ));
LUT6 #(
.INIT(64'h0000000000000001))
\gen_axi.s_axi_rlast_i_i_2
(.I0(\gen_axi.s_axi_rlast_i_i_5_n_0 ),
.I1(\m_axi_arqos[3] [50]),
.I2(\m_axi_arqos[3] [51]),
.I3(\m_axi_arqos[3] [48]),
.I4(\m_axi_arqos[3] [49]),
.I5(mi_rvalid),
.O(\gen_axi.s_axi_rlast_i_reg ));
LUT6 #(
.INIT(64'h0000000008000000))
\gen_axi.s_axi_rlast_i_i_3
(.I0(m_valid_i),
.I1(aa_grant_rnw),
.I2(m_ready_d[1]),
.I3(\m_atarget_hot_reg[4]_0 [4]),
.I4(mi_arready),
.I5(mi_rvalid),
.O(s_axi_rid_i));
LUT4 #(
.INIT(16'hFFFE))
\gen_axi.s_axi_rlast_i_i_5
(.I0(\m_axi_arqos[3] [44]),
.I1(\m_axi_arqos[3] [45]),
.I2(\m_axi_arqos[3] [46]),
.I3(\m_axi_arqos[3] [47]),
.O(\gen_axi.s_axi_rlast_i_i_5_n_0 ));
LUT4 #(
.INIT(16'h0040))
\gen_axi.s_axi_wready_i_i_2
(.I0(\m_ready_d_reg[1]_0 ),
.I1(s_axi_wlast),
.I2(\m_atarget_hot_reg[4]_0 [4]),
.I3(write_cs),
.O(\gen_axi.s_axi_wready_i_reg_0 ));
LUT5 #(
.INIT(32'hFBFFFFFF))
\gen_axi.s_axi_wready_i_i_3
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d_0[2]),
.I3(mi_awready),
.I4(\m_atarget_hot_reg[4]_0 [4]),
.O(\gen_axi.s_axi_wready_i_reg ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0020))
\gen_axi.write_cs[1]_i_2
(.I0(s_axi_bready),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[0]),
.O(\m_ready_d_reg[0]_0 ));
LUT6 #(
.INIT(64'hFFFFFF4700000044))
\gen_no_arbiter.grant_rnw_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_arvalid),
.I2(s_axi_awvalid),
.I3(aa_grant_any),
.I4(m_valid_i),
.I5(aa_grant_rnw),
.O(\gen_no_arbiter.grant_rnw_i_1_n_0 ));
FDRE \gen_no_arbiter.grant_rnw_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.grant_rnw_i_1_n_0 ),
.Q(aa_grant_rnw),
.R(SR));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[0]_i_1
(.I0(s_axi_arid[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[0]),
.O(s_amesg[0]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[10]_i_1
(.I0(s_axi_arid[10]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[10]),
.O(s_amesg[10]));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[11]_i_1
(.I0(aresetn_d),
.O(SR));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_amesg_i[11]_i_2
(.I0(aa_grant_any),
.O(p_0_in1_in));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[11]_i_3
(.I0(s_axi_arid[11]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[11]),
.O(s_amesg[11]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[12]_i_1
(.I0(s_axi_araddr[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[0]),
.O(s_amesg[12]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[13]_i_1
(.I0(s_axi_araddr[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[1]),
.O(s_amesg[13]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[14]_i_1
(.I0(s_axi_araddr[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[2]),
.O(s_amesg[14]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[15]_i_1
(.I0(s_axi_araddr[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[3]),
.O(s_amesg[15]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[16]_i_1
(.I0(s_axi_araddr[4]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[4]),
.O(s_amesg[16]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[17]_i_1
(.I0(s_axi_araddr[5]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[5]),
.O(s_amesg[17]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[18]_i_1
(.I0(s_axi_araddr[6]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[6]),
.O(s_amesg[18]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[19]_i_1
(.I0(s_axi_araddr[7]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[7]),
.O(s_amesg[19]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[1]_i_1
(.I0(s_axi_arid[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[1]),
.O(s_amesg[1]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[20]_i_1
(.I0(s_axi_araddr[8]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[8]),
.O(s_amesg[20]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[21]_i_1
(.I0(s_axi_araddr[9]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[9]),
.O(s_amesg[21]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[22]_i_1
(.I0(s_axi_araddr[10]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[10]),
.O(s_amesg[22]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[23]_i_1
(.I0(s_axi_araddr[11]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[11]),
.O(s_amesg[23]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[24]_i_1
(.I0(s_axi_araddr[12]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[12]),
.O(s_amesg[24]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[25]_i_1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[13]),
.O(s_amesg[25]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[26]_i_1
(.I0(s_axi_araddr[14]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[14]),
.O(s_amesg[26]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[27]_i_1
(.I0(s_axi_araddr[15]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[15]),
.O(s_amesg[27]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[28]_i_1
(.I0(s_axi_araddr[16]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[16]),
.O(s_amesg[28]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[29]_i_1
(.I0(s_axi_araddr[17]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[17]),
.O(s_amesg[29]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[2]_i_1
(.I0(s_axi_arid[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[2]),
.O(s_amesg[2]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[30]_i_1
(.I0(s_axi_araddr[18]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[18]),
.O(s_amesg[30]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[31]_i_1
(.I0(s_axi_araddr[19]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[19]),
.O(s_amesg[31]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[32]_i_1
(.I0(s_axi_araddr[20]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[20]),
.O(s_amesg[32]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[33]_i_1
(.I0(s_axi_araddr[21]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[21]),
.O(s_amesg[33]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[34]_i_1
(.I0(s_axi_araddr[22]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[22]),
.O(s_amesg[34]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[35]_i_1
(.I0(s_axi_araddr[23]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[23]),
.O(s_amesg[35]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[36]_i_1
(.I0(s_axi_araddr[24]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[24]),
.O(s_amesg[36]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[37]_i_1
(.I0(s_axi_araddr[25]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[25]),
.O(s_amesg[37]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[38]_i_1
(.I0(s_axi_araddr[26]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[26]),
.O(s_amesg[38]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[39]_i_1
(.I0(s_axi_araddr[27]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[27]),
.O(s_amesg[39]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[3]_i_1
(.I0(s_axi_arid[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[3]),
.O(s_amesg[3]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[40]_i_1
(.I0(s_axi_araddr[28]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[28]),
.O(s_amesg[40]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[41]_i_1
(.I0(s_axi_araddr[29]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[29]),
.O(s_amesg[41]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[42]_i_1
(.I0(s_axi_araddr[30]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[30]),
.O(s_amesg[42]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[43]_i_1
(.I0(s_axi_araddr[31]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awaddr[31]),
.O(s_amesg[43]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[44]_i_1
(.I0(s_axi_arlen[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[0]),
.O(s_amesg[44]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[45]_i_1
(.I0(s_axi_arlen[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[1]),
.O(s_amesg[45]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[46]_i_1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[2]),
.O(s_amesg[46]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[47]_i_1
(.I0(s_axi_arlen[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[3]),
.O(s_amesg[47]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[48]_i_1
(.I0(s_axi_arlen[4]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[4]),
.O(s_amesg[48]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[49]_i_1
(.I0(s_axi_arlen[5]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[5]),
.O(s_amesg[49]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[4]_i_1
(.I0(s_axi_arid[4]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[4]),
.O(s_amesg[4]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[50]_i_1
(.I0(s_axi_arlen[6]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[6]),
.O(s_amesg[50]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[51]_i_1
(.I0(s_axi_arlen[7]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlen[7]),
.O(s_amesg[51]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[52]_i_1
(.I0(s_axi_arsize[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awsize[0]),
.O(s_amesg[52]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[53]_i_1
(.I0(s_axi_arsize[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awsize[1]),
.O(s_amesg[53]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[54]_i_1
(.I0(s_axi_arsize[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awsize[2]),
.O(s_amesg[54]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[55]_i_1
(.I0(s_axi_arlock),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awlock),
.O(s_amesg[55]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[57]_i_1
(.I0(s_axi_arprot[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[0]),
.O(s_amesg[57]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[58]_i_1
(.I0(s_axi_arprot[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[1]),
.O(s_amesg[58]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[59]_i_1
(.I0(s_axi_arprot[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awprot[2]),
.O(s_amesg[59]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[5]_i_1
(.I0(s_axi_arid[5]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[5]),
.O(s_amesg[5]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[60]_i_1
(.I0(s_axi_arburst[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awburst[0]),
.O(s_amesg[60]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[61]_i_1
(.I0(s_axi_arburst[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awburst[1]),
.O(s_amesg[61]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[62]_i_1
(.I0(s_axi_arcache[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awcache[0]),
.O(s_amesg[62]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[63]_i_1
(.I0(s_axi_arcache[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awcache[1]),
.O(s_amesg[63]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[64]_i_1
(.I0(s_axi_arcache[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awcache[2]),
.O(s_amesg[64]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[65]_i_1
(.I0(s_axi_arcache[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awcache[3]),
.O(s_amesg[65]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[66]_i_1
(.I0(s_axi_arqos[0]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awqos[0]),
.O(s_amesg[66]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[67]_i_1
(.I0(s_axi_arqos[1]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awqos[1]),
.O(s_amesg[67]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[68]_i_1
(.I0(s_axi_arqos[2]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awqos[2]),
.O(s_amesg[68]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[69]_i_1
(.I0(s_axi_arqos[3]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awqos[3]),
.O(s_amesg[69]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[6]_i_1
(.I0(s_axi_arid[6]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[6]),
.O(s_amesg[6]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[7]_i_1
(.I0(s_axi_arid[7]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[7]),
.O(s_amesg[7]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[8]_i_1
(.I0(s_axi_arid[8]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[8]),
.O(s_amesg[8]));
LUT4 #(
.INIT(16'hFB08))
\gen_no_arbiter.m_amesg_i[9]_i_1
(.I0(s_axi_arid[9]),
.I1(s_axi_arvalid),
.I2(s_awvalid_reg),
.I3(s_axi_awid[9]),
.O(s_amesg[9]));
FDRE \gen_no_arbiter.m_amesg_i_reg[0]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[0]),
.Q(\m_axi_arqos[3] [0]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[10]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[10]),
.Q(\m_axi_arqos[3] [10]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[11]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[11]),
.Q(\m_axi_arqos[3] [11]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[12]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[12]),
.Q(\m_axi_arqos[3] [12]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[13]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[13]),
.Q(\m_axi_arqos[3] [13]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[14]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[14]),
.Q(\m_axi_arqos[3] [14]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[15]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[15]),
.Q(\m_axi_arqos[3] [15]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[16]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[16]),
.Q(\m_axi_arqos[3] [16]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[17]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[17]),
.Q(\m_axi_arqos[3] [17]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[18]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[18]),
.Q(\m_axi_arqos[3] [18]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[19]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[19]),
.Q(\m_axi_arqos[3] [19]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[1]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[1]),
.Q(\m_axi_arqos[3] [1]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[20]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[20]),
.Q(\m_axi_arqos[3] [20]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[21]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[21]),
.Q(\m_axi_arqos[3] [21]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[22]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[22]),
.Q(\m_axi_arqos[3] [22]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[23]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[23]),
.Q(\m_axi_arqos[3] [23]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[24]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[24]),
.Q(\m_axi_arqos[3] [24]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[25]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[25]),
.Q(\m_axi_arqos[3] [25]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[26]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[26]),
.Q(\m_axi_arqos[3] [26]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[27]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[27]),
.Q(\m_axi_arqos[3] [27]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[28]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[28]),
.Q(\m_axi_arqos[3] [28]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[29]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[29]),
.Q(\m_axi_arqos[3] [29]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[2]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[2]),
.Q(\m_axi_arqos[3] [2]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[30]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[30]),
.Q(\m_axi_arqos[3] [30]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[31]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[31]),
.Q(\m_axi_arqos[3] [31]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[32]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[32]),
.Q(\m_axi_arqos[3] [32]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[33]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[33]),
.Q(\m_axi_arqos[3] [33]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[34]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[34]),
.Q(\m_axi_arqos[3] [34]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[35]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[35]),
.Q(\m_axi_arqos[3] [35]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[36]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[36]),
.Q(\m_axi_arqos[3] [36]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[37]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[37]),
.Q(\m_axi_arqos[3] [37]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[38]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[38]),
.Q(\m_axi_arqos[3] [38]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[39]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[39]),
.Q(\m_axi_arqos[3] [39]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[3]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[3]),
.Q(\m_axi_arqos[3] [3]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[40]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[40]),
.Q(\m_axi_arqos[3] [40]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[41]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[41]),
.Q(\m_axi_arqos[3] [41]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[42]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[42]),
.Q(\m_axi_arqos[3] [42]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[43]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[43]),
.Q(\m_axi_arqos[3] [43]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[44]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[44]),
.Q(\m_axi_arqos[3] [44]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[45]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[45]),
.Q(\m_axi_arqos[3] [45]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[46]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[46]),
.Q(\m_axi_arqos[3] [46]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[47]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[47]),
.Q(\m_axi_arqos[3] [47]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[48]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[48]),
.Q(\m_axi_arqos[3] [48]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[49]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[49]),
.Q(\m_axi_arqos[3] [49]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[4]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[4]),
.Q(\m_axi_arqos[3] [4]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[50]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[50]),
.Q(\m_axi_arqos[3] [50]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[51]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[51]),
.Q(\m_axi_arqos[3] [51]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[52]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[52]),
.Q(\m_axi_arqos[3] [52]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[53]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[53]),
.Q(\m_axi_arqos[3] [53]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[54]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[54]),
.Q(\m_axi_arqos[3] [54]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[55]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[55]),
.Q(\m_axi_arqos[3] [55]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[57]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[57]),
.Q(\m_axi_arqos[3] [56]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[58]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[58]),
.Q(\m_axi_arqos[3] [57]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[59]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[59]),
.Q(\m_axi_arqos[3] [58]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[5]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[5]),
.Q(\m_axi_arqos[3] [5]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[60]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[60]),
.Q(\m_axi_arqos[3] [59]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[61]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[61]),
.Q(\m_axi_arqos[3] [60]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[62]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[62]),
.Q(\m_axi_arqos[3] [61]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[63]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[63]),
.Q(\m_axi_arqos[3] [62]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[64]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[64]),
.Q(\m_axi_arqos[3] [63]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[65]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[65]),
.Q(\m_axi_arqos[3] [64]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[66]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[66]),
.Q(\m_axi_arqos[3] [65]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[67]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[67]),
.Q(\m_axi_arqos[3] [66]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[68]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[68]),
.Q(\m_axi_arqos[3] [67]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[69]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[69]),
.Q(\m_axi_arqos[3] [68]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[6]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[6]),
.Q(\m_axi_arqos[3] [6]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[7]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[7]),
.Q(\m_axi_arqos[3] [7]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[8]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[8]),
.Q(\m_axi_arqos[3] [8]),
.R(SR));
FDRE \gen_no_arbiter.m_amesg_i_reg[9]
(.C(aclk),
.CE(p_0_in1_in),
.D(s_amesg[9]),
.Q(\m_axi_arqos[3] [9]),
.R(SR));
LUT6 #(
.INIT(64'h00000000DDDC0000))
\gen_no_arbiter.m_grant_hot_i[0]_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(s_axi_awvalid),
.I3(s_axi_arvalid),
.I4(aresetn_d),
.I5(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h808080808080B080))
\gen_no_arbiter.m_grant_hot_i[0]_i_2
(.I0(\m_ready_d[0]_i_4_n_0 ),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d0),
.I4(\m_ready_d[2]_i_6_n_0 ),
.I5(\m_ready_d_reg[1]_1 ),
.O(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ));
FDRE \gen_no_arbiter.m_grant_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_grant_hot_i[0]_i_1_n_0 ),
.Q(aa_grant_any),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h74))
\gen_no_arbiter.m_valid_i_i_1
(.I0(\gen_no_arbiter.m_grant_hot_i[0]_i_2_n_0 ),
.I1(m_valid_i),
.I2(aa_grant_any),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(m_valid_i),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h40))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aa_grant_any),
.I2(aresetn_d),
.O(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.s_ready_i[0]_i_1_n_0 ),
.Q(s_ready_i),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\m_atarget_enc[2]_i_1
(.I0(\m_atarget_hot_reg[4] ),
.I1(f_hot2enc_return0),
.O(\m_atarget_enc_reg[2] ));
LUT6 #(
.INIT(64'h0000000000000008))
\m_atarget_hot[0]_i_1
(.I0(\m_atarget_hot[1]_i_2_n_0 ),
.I1(aa_grant_any),
.I2(\m_axi_arqos[3] [28]),
.I3(\m_axi_arqos[3] [31]),
.I4(\m_axi_arqos[3] [30]),
.I5(\m_axi_arqos[3] [29]),
.O(D[0]));
LUT6 #(
.INIT(64'h0100000000000000))
\m_atarget_hot[1]_i_1
(.I0(\m_axi_arqos[3] [31]),
.I1(\m_axi_arqos[3] [30]),
.I2(\m_axi_arqos[3] [29]),
.I3(\m_atarget_hot[1]_i_2_n_0 ),
.I4(\m_axi_arqos[3] [28]),
.I5(aa_grant_any),
.O(D[1]));
LUT5 #(
.INIT(32'h00000400))
\m_atarget_hot[1]_i_2
(.I0(\m_atarget_hot[2]_i_3_n_0 ),
.I1(\m_axi_arqos[3] [33]),
.I2(\m_axi_arqos[3] [34]),
.I3(\m_axi_arqos[3] [36]),
.I4(\m_atarget_hot[1]_i_3_n_0 ),
.O(\m_atarget_hot[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hFE))
\m_atarget_hot[1]_i_3
(.I0(\m_axi_arqos[3] [32]),
.I1(\m_axi_arqos[3] [37]),
.I2(\m_axi_arqos[3] [35]),
.O(\m_atarget_hot[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h00200000))
\m_atarget_hot[2]_i_1
(.I0(\m_axi_arqos[3] [37]),
.I1(\m_axi_arqos[3] [32]),
.I2(\m_axi_arqos[3] [35]),
.I3(\m_atarget_hot[2]_i_2_n_0 ),
.I4(aa_grant_any),
.O(D[2]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\m_atarget_hot[2]_i_2
(.I0(\m_atarget_hot[2]_i_3_n_0 ),
.I1(\m_axi_arqos[3] [33]),
.I2(\m_axi_arqos[3] [34]),
.I3(\m_axi_arqos[3] [36]),
.I4(\m_atarget_hot[2]_i_4_n_0 ),
.O(\m_atarget_hot[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEFFFFFFFF))
\m_atarget_hot[2]_i_3
(.I0(\m_axi_arqos[3] [43]),
.I1(\m_axi_arqos[3] [39]),
.I2(\m_axi_arqos[3] [41]),
.I3(\m_axi_arqos[3] [40]),
.I4(\m_axi_arqos[3] [38]),
.I5(\m_axi_arqos[3] [42]),
.O(\m_atarget_hot[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hFFFE))
\m_atarget_hot[2]_i_4
(.I0(\m_axi_arqos[3] [28]),
.I1(\m_axi_arqos[3] [31]),
.I2(\m_axi_arqos[3] [30]),
.I3(\m_axi_arqos[3] [29]),
.O(\m_atarget_hot[2]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_hot[3]_i_1
(.I0(\m_atarget_hot_reg[3] ),
.I1(aa_grant_any),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h0001))
\m_atarget_hot[3]_i_2
(.I0(\m_axi_arqos[3] [35]),
.I1(\m_axi_arqos[3] [37]),
.I2(\m_axi_arqos[3] [32]),
.I3(\m_atarget_hot[2]_i_2_n_0 ),
.O(\m_atarget_hot_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h40))
\m_atarget_hot[4]_i_1
(.I0(f_hot2enc_return0),
.I1(\m_atarget_hot_reg[4] ),
.I2(aa_grant_any),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h1001))
\m_atarget_hot[4]_i_2
(.I0(\m_atarget_hot[2]_i_2_n_0 ),
.I1(\m_axi_arqos[3] [32]),
.I2(\m_axi_arqos[3] [37]),
.I3(\m_axi_arqos[3] [35]),
.O(f_hot2enc_return0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'hFEFF))
\m_atarget_hot[4]_i_3
(.I0(\m_axi_arqos[3] [31]),
.I1(\m_axi_arqos[3] [30]),
.I2(\m_axi_arqos[3] [29]),
.I3(\m_atarget_hot[1]_i_2_n_0 ),
.O(\m_atarget_hot_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [0]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(m_ready_d[1]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [1]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(m_ready_d[1]),
.O(m_axi_arvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [2]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(m_ready_d[1]),
.O(m_axi_arvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0080))
\m_axi_arvalid[3]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [3]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(m_ready_d[1]),
.O(m_axi_arvalid[3]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[2]),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [1]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[2]),
.O(m_axi_awvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [2]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[2]),
.O(m_axi_awvalid[2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h0020))
\m_axi_awvalid[3]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [3]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(m_ready_d_0[2]),
.O(m_axi_awvalid[3]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[0]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [0]),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[0]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[1]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [1]),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[1]));
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[2]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [2]),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h00200000))
\m_axi_bready[3]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [3]),
.I1(m_ready_d_0[0]),
.I2(m_valid_i),
.I3(aa_grant_rnw),
.I4(s_axi_bready),
.O(m_axi_bready[3]));
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[0]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [0]),
.I1(s_axi_wvalid),
.I2(m_ready_d_0[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[0]));
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[1]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [1]),
.I1(s_axi_wvalid),
.I2(m_ready_d_0[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[1]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[2]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [2]),
.I1(s_axi_wvalid),
.I2(m_ready_d_0[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[2]));
LUT5 #(
.INIT(32'h00000800))
\m_axi_wvalid[3]_INST_0
(.I0(\m_atarget_hot_reg[4]_0 [3]),
.I1(s_axi_wvalid),
.I2(m_ready_d_0[1]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_axi_wvalid[3]));
LUT5 #(
.INIT(32'h4000FFFF))
\m_payload_i[34]_i_1
(.I0(m_ready_d[0]),
.I1(aa_grant_rnw),
.I2(m_valid_i),
.I3(s_axi_rready),
.I4(sr_rvalid),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h7))
\m_ready_d[0]_i_2
(.I0(m_valid_i),
.I1(aa_grant_rnw),
.O(\m_ready_d_reg[0]_1 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'hB))
\m_ready_d[0]_i_3
(.I0(\m_ready_d[0]_i_4_n_0 ),
.I1(aresetn_d),
.O(\m_ready_d_reg[0] ));
LUT6 #(
.INIT(64'hAA80AA00AA80AA80))
\m_ready_d[0]_i_4
(.I0(m_ready_d0_1),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(m_ready_d[1]),
.I4(\m_atarget_enc_reg[0] ),
.I5(\m_atarget_enc_reg[2]_0 ),
.O(\m_ready_d[0]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hFBFF))
\m_ready_d[1]_i_2
(.I0(aa_grant_rnw),
.I1(m_valid_i),
.I2(m_ready_d_0[1]),
.I3(s_axi_wvalid),
.O(\m_ready_d_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h020F0F0F))
\m_ready_d[1]_i_3
(.I0(\m_atarget_enc_reg[2]_0 ),
.I1(\m_atarget_enc_reg[0] ),
.I2(m_ready_d[1]),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.O(\m_ready_d_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hF0F0FDF0))
\m_ready_d[2]_i_2
(.I0(\m_atarget_enc_reg[2]_1 ),
.I1(\gen_axi.s_axi_awready_i_reg_0 ),
.I2(m_ready_d_0[2]),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.O(m_ready_d0));
LUT6 #(
.INIT(64'h2020202020222020))
\m_ready_d[2]_i_3
(.I0(m_ready_d0),
.I1(\m_ready_d[2]_i_6_n_0 ),
.I2(m_ready_d_0[1]),
.I3(\m_atarget_enc_reg[1] ),
.I4(s_axi_wlast),
.I5(\m_ready_d_reg[1]_0 ),
.O(\m_ready_d_reg[2] ));
LUT6 #(
.INIT(64'h00000000FF2FFFFF))
\m_ready_d[2]_i_6
(.I0(\m_atarget_enc_reg[1]_0 ),
.I1(\gen_axi.s_axi_bvalid_i_reg ),
.I2(s_axi_bready),
.I3(aa_grant_rnw),
.I4(m_valid_i),
.I5(m_ready_d_0[0]),
.O(\m_ready_d[2]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h2A))
m_valid_i_i_1
(.I0(Q[1]),
.I1(E),
.I2(m_valid_i_i_2_n_0),
.O(m_valid_i_reg));
LUT6 #(
.INIT(64'h8AAAAAAA8AAA8AAA))
m_valid_i_i_2
(.I0(aa_rready),
.I1(m_ready_d[0]),
.I2(aa_grant_rnw),
.I3(m_valid_i),
.I4(\gen_axi.read_cs_reg[0] ),
.I5(\m_atarget_enc_reg[1]_1 ),
.O(m_valid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0040))
\s_arvalid_reg[0]_i_1
(.I0(s_awvalid_reg),
.I1(s_axi_arvalid),
.I2(aresetn_d),
.I3(s_ready_i),
.O(\s_arvalid_reg[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_arvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_arvalid_reg[0]_i_1_n_0 ),
.Q(\s_arvalid_reg_reg_n_0_[0] ),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000000D00000))
\s_awvalid_reg[0]_i_1
(.I0(s_axi_arvalid),
.I1(s_awvalid_reg),
.I2(s_axi_awvalid),
.I3(\s_arvalid_reg_reg_n_0_[0] ),
.I4(aresetn_d),
.I5(s_ready_i),
.O(\s_awvalid_reg[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_awvalid_reg_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_awvalid_reg[0]_i_1_n_0 ),
.Q(s_awvalid_reg),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h8))
\s_axi_arready[0]_INST_0
(.I0(aa_grant_rnw),
.I1(s_ready_i),
.O(s_axi_arready));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h2))
\s_axi_awready[0]_INST_0
(.I0(s_ready_i),
.I1(aa_grant_rnw),
.O(s_axi_awready));
LUT5 #(
.INIT(32'h00000400))
\s_axi_bvalid[0]_INST_0
(.I0(m_ready_d_0[0]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(aa_grant_any),
.I4(\m_atarget_enc_reg[0]_0 ),
.O(s_axi_bvalid));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00000400))
\s_axi_wready[0]_INST_0
(.I0(m_ready_d_0[1]),
.I1(m_valid_i),
.I2(aa_grant_rnw),
.I3(aa_grant_any),
.I4(\m_atarget_enc_reg[1] ),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hA8))
s_ready_i_i_1
(.I0(Q[0]),
.I1(E),
.I2(m_valid_i_i_2_n_0),
.O(s_ready_i_reg));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "0" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_READ_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_SECURE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_M_AXI_WRITE_ISSUING = "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "4" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "1" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "1" *)
(* C_S_AXI_SINGLE_THREAD = "1" *) (* C_S_AXI_THREAD_ID_WIDTH = "12" *) (* C_S_AXI_WRITE_ACCEPTANCE = "1" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_crossbar_v2_1_14_axi_crossbar" *) (* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *) (* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *)
(* P_LEN = "8" *) (* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "4'b1111" *) (* P_M_AXI_SUPPORTS_WRITE = "4'b1111" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *) (* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *) (* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [47:0]m_axi_awid;
output [127:0]m_axi_awaddr;
output [31:0]m_axi_awlen;
output [11:0]m_axi_awsize;
output [7:0]m_axi_awburst;
output [3:0]m_axi_awlock;
output [15:0]m_axi_awcache;
output [11:0]m_axi_awprot;
output [15:0]m_axi_awregion;
output [15:0]m_axi_awqos;
output [3:0]m_axi_awuser;
output [3:0]m_axi_awvalid;
input [3:0]m_axi_awready;
output [47:0]m_axi_wid;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output [3:0]m_axi_wlast;
output [3:0]m_axi_wuser;
output [3:0]m_axi_wvalid;
input [3:0]m_axi_wready;
input [47:0]m_axi_bid;
input [7:0]m_axi_bresp;
input [3:0]m_axi_buser;
input [3:0]m_axi_bvalid;
output [3:0]m_axi_bready;
output [47:0]m_axi_arid;
output [127:0]m_axi_araddr;
output [31:0]m_axi_arlen;
output [11:0]m_axi_arsize;
output [7:0]m_axi_arburst;
output [3:0]m_axi_arlock;
output [15:0]m_axi_arcache;
output [11:0]m_axi_arprot;
output [15:0]m_axi_arregion;
output [15:0]m_axi_arqos;
output [3:0]m_axi_aruser;
output [3:0]m_axi_arvalid;
input [3:0]m_axi_arready;
input [47:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_ruser;
input [3:0]m_axi_rvalid;
output [3:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [15:0]\^m_axi_araddr ;
wire [1:0]\^m_axi_arburst ;
wire [3:0]\^m_axi_arcache ;
wire [11:0]\^m_axi_arid ;
wire [0:0]\^m_axi_arlock ;
wire [2:0]\^m_axi_arprot ;
wire [3:0]\^m_axi_arqos ;
wire [3:0]m_axi_arready;
wire [2:0]\^m_axi_arsize ;
wire [3:0]m_axi_arvalid;
wire [127:112]\^m_axi_awaddr ;
wire [31:24]\^m_axi_awlen ;
wire [3:0]m_axi_awready;
wire [3:0]m_axi_awvalid;
wire [3:0]m_axi_bready;
wire [7:0]m_axi_bresp;
wire [3:0]m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [3:0]m_axi_rlast;
wire [3:0]m_axi_rready;
wire [7:0]m_axi_rresp;
wire [3:0]m_axi_rvalid;
wire [3:0]m_axi_wready;
wire [3:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[127:112] = \^m_axi_awaddr [127:112];
assign m_axi_araddr[111:96] = \^m_axi_araddr [15:0];
assign m_axi_araddr[95:80] = \^m_axi_awaddr [127:112];
assign m_axi_araddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_araddr[63:48] = \^m_axi_awaddr [127:112];
assign m_axi_araddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_araddr[31:16] = \^m_axi_awaddr [127:112];
assign m_axi_araddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_arburst[7:6] = \^m_axi_arburst [1:0];
assign m_axi_arburst[5:4] = \^m_axi_arburst [1:0];
assign m_axi_arburst[3:2] = \^m_axi_arburst [1:0];
assign m_axi_arburst[1:0] = \^m_axi_arburst [1:0];
assign m_axi_arcache[15:12] = \^m_axi_arcache [3:0];
assign m_axi_arcache[11:8] = \^m_axi_arcache [3:0];
assign m_axi_arcache[7:4] = \^m_axi_arcache [3:0];
assign m_axi_arcache[3:0] = \^m_axi_arcache [3:0];
assign m_axi_arid[47:36] = \^m_axi_arid [11:0];
assign m_axi_arid[35:24] = \^m_axi_arid [11:0];
assign m_axi_arid[23:12] = \^m_axi_arid [11:0];
assign m_axi_arid[11:0] = \^m_axi_arid [11:0];
assign m_axi_arlen[31:24] = \^m_axi_awlen [31:24];
assign m_axi_arlen[23:16] = \^m_axi_awlen [31:24];
assign m_axi_arlen[15:8] = \^m_axi_awlen [31:24];
assign m_axi_arlen[7:0] = \^m_axi_awlen [31:24];
assign m_axi_arlock[3] = \^m_axi_arlock [0];
assign m_axi_arlock[2] = \^m_axi_arlock [0];
assign m_axi_arlock[1] = \^m_axi_arlock [0];
assign m_axi_arlock[0] = \^m_axi_arlock [0];
assign m_axi_arprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_arprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_arprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_arprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_arqos[15:12] = \^m_axi_arqos [3:0];
assign m_axi_arqos[11:8] = \^m_axi_arqos [3:0];
assign m_axi_arqos[7:4] = \^m_axi_arqos [3:0];
assign m_axi_arqos[3:0] = \^m_axi_arqos [3:0];
assign m_axi_arregion[15] = \<const0> ;
assign m_axi_arregion[14] = \<const0> ;
assign m_axi_arregion[13] = \<const0> ;
assign m_axi_arregion[12] = \<const0> ;
assign m_axi_arregion[11] = \<const0> ;
assign m_axi_arregion[10] = \<const0> ;
assign m_axi_arregion[9] = \<const0> ;
assign m_axi_arregion[8] = \<const0> ;
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[11:9] = \^m_axi_arsize [2:0];
assign m_axi_arsize[8:6] = \^m_axi_arsize [2:0];
assign m_axi_arsize[5:3] = \^m_axi_arsize [2:0];
assign m_axi_arsize[2:0] = \^m_axi_arsize [2:0];
assign m_axi_aruser[3] = \<const0> ;
assign m_axi_aruser[2] = \<const0> ;
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[127:112] = \^m_axi_awaddr [127:112];
assign m_axi_awaddr[111:96] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[95:80] = \^m_axi_awaddr [127:112];
assign m_axi_awaddr[79:64] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[63:48] = \^m_axi_awaddr [127:112];
assign m_axi_awaddr[47:32] = \^m_axi_araddr [15:0];
assign m_axi_awaddr[31:16] = \^m_axi_awaddr [127:112];
assign m_axi_awaddr[15:0] = \^m_axi_araddr [15:0];
assign m_axi_awburst[7:6] = \^m_axi_arburst [1:0];
assign m_axi_awburst[5:4] = \^m_axi_arburst [1:0];
assign m_axi_awburst[3:2] = \^m_axi_arburst [1:0];
assign m_axi_awburst[1:0] = \^m_axi_arburst [1:0];
assign m_axi_awcache[15:12] = \^m_axi_arcache [3:0];
assign m_axi_awcache[11:8] = \^m_axi_arcache [3:0];
assign m_axi_awcache[7:4] = \^m_axi_arcache [3:0];
assign m_axi_awcache[3:0] = \^m_axi_arcache [3:0];
assign m_axi_awid[47:36] = \^m_axi_arid [11:0];
assign m_axi_awid[35:24] = \^m_axi_arid [11:0];
assign m_axi_awid[23:12] = \^m_axi_arid [11:0];
assign m_axi_awid[11:0] = \^m_axi_arid [11:0];
assign m_axi_awlen[31:24] = \^m_axi_awlen [31:24];
assign m_axi_awlen[23:16] = \^m_axi_awlen [31:24];
assign m_axi_awlen[15:8] = \^m_axi_awlen [31:24];
assign m_axi_awlen[7:0] = \^m_axi_awlen [31:24];
assign m_axi_awlock[3] = \^m_axi_arlock [0];
assign m_axi_awlock[2] = \^m_axi_arlock [0];
assign m_axi_awlock[1] = \^m_axi_arlock [0];
assign m_axi_awlock[0] = \^m_axi_arlock [0];
assign m_axi_awprot[11:9] = \^m_axi_arprot [2:0];
assign m_axi_awprot[8:6] = \^m_axi_arprot [2:0];
assign m_axi_awprot[5:3] = \^m_axi_arprot [2:0];
assign m_axi_awprot[2:0] = \^m_axi_arprot [2:0];
assign m_axi_awqos[15:12] = \^m_axi_arqos [3:0];
assign m_axi_awqos[11:8] = \^m_axi_arqos [3:0];
assign m_axi_awqos[7:4] = \^m_axi_arqos [3:0];
assign m_axi_awqos[3:0] = \^m_axi_arqos [3:0];
assign m_axi_awregion[15] = \<const0> ;
assign m_axi_awregion[14] = \<const0> ;
assign m_axi_awregion[13] = \<const0> ;
assign m_axi_awregion[12] = \<const0> ;
assign m_axi_awregion[11] = \<const0> ;
assign m_axi_awregion[10] = \<const0> ;
assign m_axi_awregion[9] = \<const0> ;
assign m_axi_awregion[8] = \<const0> ;
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[11:9] = \^m_axi_arsize [2:0];
assign m_axi_awsize[8:6] = \^m_axi_arsize [2:0];
assign m_axi_awsize[5:3] = \^m_axi_arsize [2:0];
assign m_axi_awsize[2:0] = \^m_axi_arsize [2:0];
assign m_axi_awuser[3] = \<const0> ;
assign m_axi_awuser[2] = \<const0> ;
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[127:96] = s_axi_wdata;
assign m_axi_wdata[95:64] = s_axi_wdata;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[47] = \<const0> ;
assign m_axi_wid[46] = \<const0> ;
assign m_axi_wid[45] = \<const0> ;
assign m_axi_wid[44] = \<const0> ;
assign m_axi_wid[43] = \<const0> ;
assign m_axi_wid[42] = \<const0> ;
assign m_axi_wid[41] = \<const0> ;
assign m_axi_wid[40] = \<const0> ;
assign m_axi_wid[39] = \<const0> ;
assign m_axi_wid[38] = \<const0> ;
assign m_axi_wid[37] = \<const0> ;
assign m_axi_wid[36] = \<const0> ;
assign m_axi_wid[35] = \<const0> ;
assign m_axi_wid[34] = \<const0> ;
assign m_axi_wid[33] = \<const0> ;
assign m_axi_wid[32] = \<const0> ;
assign m_axi_wid[31] = \<const0> ;
assign m_axi_wid[30] = \<const0> ;
assign m_axi_wid[29] = \<const0> ;
assign m_axi_wid[28] = \<const0> ;
assign m_axi_wid[27] = \<const0> ;
assign m_axi_wid[26] = \<const0> ;
assign m_axi_wid[25] = \<const0> ;
assign m_axi_wid[24] = \<const0> ;
assign m_axi_wid[23] = \<const0> ;
assign m_axi_wid[22] = \<const0> ;
assign m_axi_wid[21] = \<const0> ;
assign m_axi_wid[20] = \<const0> ;
assign m_axi_wid[19] = \<const0> ;
assign m_axi_wid[18] = \<const0> ;
assign m_axi_wid[17] = \<const0> ;
assign m_axi_wid[16] = \<const0> ;
assign m_axi_wid[15] = \<const0> ;
assign m_axi_wid[14] = \<const0> ;
assign m_axi_wid[13] = \<const0> ;
assign m_axi_wid[12] = \<const0> ;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[3] = s_axi_wlast;
assign m_axi_wlast[2] = s_axi_wlast;
assign m_axi_wlast[1] = s_axi_wlast;
assign m_axi_wlast[0] = s_axi_wlast;
assign m_axi_wstrb[15:12] = s_axi_wstrb;
assign m_axi_wstrb[11:8] = s_axi_wstrb;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[3] = \<const0> ;
assign m_axi_wuser[2] = \<const0> ;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_bid[11:0] = \^m_axi_arid [11:0];
assign s_axi_buser[0] = \<const0> ;
assign s_axi_rid[11:0] = \^m_axi_arid [11:0];
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_crossbar_sasd \gen_sasd.crossbar_sasd_0
(.Q({\^m_axi_arqos ,\^m_axi_arcache ,\^m_axi_arburst ,\^m_axi_arprot ,\^m_axi_arlock ,\^m_axi_arsize ,\^m_axi_awlen ,\^m_axi_awaddr ,\^m_axi_araddr ,\^m_axi_arid }),
.aclk(aclk),
.aresetn(aresetn),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rdata[31] ({s_axi_rdata,s_axi_rresp,s_axi_rlast}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_crossbar_sasd" *)
module zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_crossbar_sasd
(Q,
\s_axi_rdata[31] ,
s_axi_wready,
m_axi_wvalid,
s_axi_bvalid,
m_axi_bready,
m_axi_awvalid,
m_axi_arvalid,
s_axi_bresp,
s_axi_awready,
s_axi_arready,
s_axi_rvalid,
m_axi_rready,
aresetn,
aclk,
s_axi_wlast,
s_axi_rready,
s_axi_wvalid,
s_axi_bready,
m_axi_bresp,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_arready,
m_axi_awready,
m_axi_wready,
m_axi_bvalid,
m_axi_rdata,
s_axi_arqos,
s_axi_arvalid,
s_axi_awqos,
s_axi_arcache,
s_axi_awcache,
s_axi_arburst,
s_axi_awburst,
s_axi_arprot,
s_axi_awprot,
s_axi_arlock,
s_axi_awlock,
s_axi_arsize,
s_axi_awsize,
s_axi_arlen,
s_axi_awlen,
s_axi_araddr,
s_axi_awaddr,
s_axi_arid,
s_axi_awid,
s_axi_awvalid);
output [68:0]Q;
output [34:0]\s_axi_rdata[31] ;
output [0:0]s_axi_wready;
output [3:0]m_axi_wvalid;
output [0:0]s_axi_bvalid;
output [3:0]m_axi_bready;
output [3:0]m_axi_awvalid;
output [3:0]m_axi_arvalid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_awready;
output [0:0]s_axi_arready;
output [0:0]s_axi_rvalid;
output [3:0]m_axi_rready;
input aresetn;
input aclk;
input [0:0]s_axi_wlast;
input [0:0]s_axi_rready;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_bready;
input [7:0]m_axi_bresp;
input [7:0]m_axi_rresp;
input [3:0]m_axi_rlast;
input [3:0]m_axi_rvalid;
input [3:0]m_axi_arready;
input [3:0]m_axi_awready;
input [3:0]m_axi_wready;
input [3:0]m_axi_bvalid;
input [127:0]m_axi_rdata;
input [3:0]s_axi_arqos;
input [0:0]s_axi_arvalid;
input [3:0]s_axi_awqos;
input [3:0]s_axi_arcache;
input [3:0]s_axi_awcache;
input [1:0]s_axi_arburst;
input [1:0]s_axi_awburst;
input [2:0]s_axi_arprot;
input [2:0]s_axi_awprot;
input [0:0]s_axi_arlock;
input [0:0]s_axi_awlock;
input [2:0]s_axi_arsize;
input [2:0]s_axi_awsize;
input [7:0]s_axi_arlen;
input [7:0]s_axi_awlen;
input [31:0]s_axi_araddr;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [11:0]s_axi_awid;
input [0:0]s_axi_awvalid;
wire [68:0]Q;
wire aa_grant_any;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire addr_arbiter_inst_n_10;
wire addr_arbiter_inst_n_102;
wire addr_arbiter_inst_n_107;
wire addr_arbiter_inst_n_11;
wire addr_arbiter_inst_n_113;
wire addr_arbiter_inst_n_117;
wire addr_arbiter_inst_n_12;
wire addr_arbiter_inst_n_13;
wire addr_arbiter_inst_n_4;
wire addr_arbiter_inst_n_5;
wire addr_arbiter_inst_n_6;
wire addr_arbiter_inst_n_7;
wire addr_arbiter_inst_n_85;
wire addr_arbiter_inst_n_86;
wire addr_arbiter_inst_n_87;
wire addr_arbiter_inst_n_9;
wire addr_arbiter_inst_n_94;
wire addr_arbiter_inst_n_95;
wire addr_arbiter_inst_n_96;
wire any_error;
wire aresetn;
wire aresetn_d;
wire f_hot2enc_return0;
wire \gen_decerr.decerr_slave_inst_n_10 ;
wire \gen_decerr.decerr_slave_inst_n_11 ;
wire \gen_decerr.decerr_slave_inst_n_4 ;
wire \gen_decerr.decerr_slave_inst_n_5 ;
wire \gen_decerr.decerr_slave_inst_n_6 ;
wire \gen_decerr.decerr_slave_inst_n_7 ;
wire \gen_decerr.decerr_slave_inst_n_8 ;
wire \gen_decerr.decerr_slave_inst_n_9 ;
wire [2:0]m_atarget_enc;
wire \m_atarget_enc[0]_i_1_n_0 ;
wire \m_atarget_enc[1]_i_1_n_0 ;
wire [4:0]m_atarget_hot;
wire [0:0]m_atarget_hot0;
wire [3:0]m_axi_arready;
wire [3:0]m_axi_arvalid;
wire [3:0]m_axi_awready;
wire [3:0]m_axi_awvalid;
wire [3:0]m_axi_bready;
wire [7:0]m_axi_bresp;
wire [3:0]m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [3:0]m_axi_rlast;
wire [3:0]m_axi_rready;
wire [7:0]m_axi_rresp;
wire [3:0]m_axi_rvalid;
wire [3:0]m_axi_wready;
wire [3:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [2:2]m_ready_d0;
wire [0:0]m_ready_d0_0;
wire [2:0]m_ready_d_1;
wire m_valid_i;
wire [4:4]mi_arready;
wire [4:4]mi_awready;
wire [4:4]mi_rvalid;
wire p_1_in;
wire reg_slice_r_n_38;
wire reg_slice_r_n_39;
wire reg_slice_r_n_45;
wire reg_slice_r_n_46;
wire reset;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire \s_axi_bresp[0]_INST_0_i_1_n_0 ;
wire \s_axi_bresp[1]_INST_0_i_1_n_0 ;
wire [0:0]s_axi_bvalid;
wire [34:0]\s_axi_rdata[31] ;
wire s_axi_rid_i;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire splitter_ar_n_0;
wire splitter_aw_n_0;
wire splitter_aw_n_4;
wire splitter_aw_n_5;
wire splitter_aw_n_6;
wire sr_rvalid;
wire [1:1]write_cs;
zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_addr_arbiter_sasd addr_arbiter_inst
(.D({addr_arbiter_inst_n_10,addr_arbiter_inst_n_11,addr_arbiter_inst_n_12,addr_arbiter_inst_n_13,m_atarget_hot0}),
.E(p_1_in),
.Q({reg_slice_r_n_45,reg_slice_r_n_46}),
.SR(reset),
.aa_grant_any(aa_grant_any),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.f_hot2enc_return0(f_hot2enc_return0),
.\gen_axi.read_cs_reg[0] (\gen_decerr.decerr_slave_inst_n_5 ),
.\gen_axi.s_axi_arready_i_reg (addr_arbiter_inst_n_6),
.\gen_axi.s_axi_awready_i_reg (addr_arbiter_inst_n_107),
.\gen_axi.s_axi_awready_i_reg_0 (\gen_decerr.decerr_slave_inst_n_7 ),
.\gen_axi.s_axi_bvalid_i_reg (\gen_decerr.decerr_slave_inst_n_11 ),
.\gen_axi.s_axi_rlast_i_reg (addr_arbiter_inst_n_117),
.\gen_axi.s_axi_wready_i_reg (addr_arbiter_inst_n_87),
.\gen_axi.s_axi_wready_i_reg_0 (addr_arbiter_inst_n_94),
.\m_atarget_enc_reg[0] (\gen_decerr.decerr_slave_inst_n_6 ),
.\m_atarget_enc_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_10 ),
.\m_atarget_enc_reg[1] (\gen_decerr.decerr_slave_inst_n_8 ),
.\m_atarget_enc_reg[1]_0 (splitter_aw_n_6),
.\m_atarget_enc_reg[1]_1 (reg_slice_r_n_39),
.\m_atarget_enc_reg[2] (any_error),
.\m_atarget_enc_reg[2]_0 (splitter_ar_n_0),
.\m_atarget_enc_reg[2]_1 (splitter_aw_n_5),
.\m_atarget_hot_reg[3] (addr_arbiter_inst_n_86),
.\m_atarget_hot_reg[4] (addr_arbiter_inst_n_85),
.\m_atarget_hot_reg[4]_0 (m_atarget_hot),
.\m_axi_arqos[3] (Q),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d),
.m_ready_d0(m_ready_d0),
.m_ready_d0_1(m_ready_d0_0),
.m_ready_d_0(m_ready_d_1),
.\m_ready_d_reg[0] (addr_arbiter_inst_n_4),
.\m_ready_d_reg[0]_0 (addr_arbiter_inst_n_102),
.\m_ready_d_reg[0]_1 (addr_arbiter_inst_n_113),
.\m_ready_d_reg[1] (addr_arbiter_inst_n_5),
.\m_ready_d_reg[1]_0 (addr_arbiter_inst_n_95),
.\m_ready_d_reg[1]_1 (splitter_aw_n_0),
.\m_ready_d_reg[2] (addr_arbiter_inst_n_96),
.m_valid_i(m_valid_i),
.m_valid_i_reg(addr_arbiter_inst_n_9),
.mi_arready(mi_arready),
.mi_awready(mi_awready),
.mi_rvalid(mi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rid_i(s_axi_rid_i),
.s_axi_rready(s_axi_rready),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(addr_arbiter_inst_n_7),
.sr_rvalid(sr_rvalid),
.write_cs(write_cs));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_decerr_slave \gen_decerr.decerr_slave_inst
(.Q(m_atarget_hot[4]),
.SR(reset),
.aa_rready(aa_rready),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axi.write_cs_reg[1]_0 (write_cs),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_102),
.\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_87),
.\gen_no_arbiter.m_amesg_i_reg[50] (addr_arbiter_inst_n_117),
.\gen_no_arbiter.m_amesg_i_reg[51] (Q[51:44]),
.\gen_no_arbiter.m_valid_i_reg (\gen_decerr.decerr_slave_inst_n_9 ),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[0] (reg_slice_r_n_38),
.\m_atarget_enc_reg[0]_0 (splitter_aw_n_4),
.\m_atarget_hot_reg[4] (addr_arbiter_inst_n_94),
.m_axi_arready({m_axi_arready[3],m_axi_arready[0]}),
.m_axi_awready(m_axi_awready[1:0]),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rlast({m_axi_rlast[2],m_axi_rlast[0]}),
.m_axi_rvalid({m_axi_rvalid[3],m_axi_rvalid[1]}),
.m_axi_wready(m_axi_wready[2]),
.\m_ready_d_reg[0] (\gen_decerr.decerr_slave_inst_n_10 ),
.\m_ready_d_reg[0]_0 (\gen_decerr.decerr_slave_inst_n_11 ),
.\m_ready_d_reg[1] (\gen_decerr.decerr_slave_inst_n_6 ),
.\m_ready_d_reg[1]_0 (\gen_decerr.decerr_slave_inst_n_8 ),
.\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_6),
.\m_ready_d_reg[2] (\gen_decerr.decerr_slave_inst_n_7 ),
.\m_ready_d_reg[2]_0 (addr_arbiter_inst_n_107),
.m_valid_i_reg(\gen_decerr.decerr_slave_inst_n_5 ),
.mi_arready(mi_arready),
.mi_awready(mi_awready),
.mi_rvalid(mi_rvalid),
.s_axi_rid_i(s_axi_rid_i),
.\skid_buffer_reg[0] (\gen_decerr.decerr_slave_inst_n_4 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hC0E000E0))
\m_atarget_enc[0]_i_1
(.I0(Q[28]),
.I1(addr_arbiter_inst_n_86),
.I2(aresetn_d),
.I3(addr_arbiter_inst_n_85),
.I4(f_hot2enc_return0),
.O(\m_atarget_enc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT2 #(
.INIT(4'h8))
\m_atarget_enc[1]_i_1
(.I0(aresetn_d),
.I1(f_hot2enc_return0),
.O(\m_atarget_enc[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_atarget_enc[0]_i_1_n_0 ),
.Q(m_atarget_enc[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_atarget_enc[1]_i_1_n_0 ),
.Q(m_atarget_enc[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_atarget_enc_reg[2]
(.C(aclk),
.CE(1'b1),
.D(any_error),
.Q(m_atarget_enc[2]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(m_atarget_hot0),
.Q(m_atarget_hot[0]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_13),
.Q(m_atarget_hot[1]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_12),
.Q(m_atarget_hot[2]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[3]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_11),
.Q(m_atarget_hot[3]),
.R(reset));
FDRE #(
.INIT(1'b0))
\m_atarget_hot_reg[4]
(.C(aclk),
.CE(1'b1),
.D(addr_arbiter_inst_n_10),
.Q(m_atarget_hot[4]),
.R(reset));
zqynq_lab_1_design_xbar_1_axi_register_slice_v2_1_13_axic_register_slice reg_slice_r
(.E(p_1_in),
.Q(m_atarget_hot[3:0]),
.SR(reset),
.aa_grant_any(aa_grant_any),
.aa_grant_rnw(aa_grant_rnw),
.aa_rready(aa_rready),
.aclk(aclk),
.\aresetn_d_reg[0]_0 (addr_arbiter_inst_n_7),
.\aresetn_d_reg[1]_0 (addr_arbiter_inst_n_9),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[2] (\gen_decerr.decerr_slave_inst_n_4 ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rlast({m_axi_rlast[3],m_axi_rlast[1]}),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid({m_axi_rvalid[2],m_axi_rvalid[0]}),
.m_ready_d(m_ready_d[0]),
.m_ready_d0(m_ready_d0_0),
.m_valid_i(m_valid_i),
.m_valid_i_reg_0(reg_slice_r_n_39),
.m_valid_i_reg_1({reg_slice_r_n_45,reg_slice_r_n_46}),
.\s_axi_rdata[31] (\s_axi_rdata[31] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (reg_slice_r_n_38),
.sr_rvalid(sr_rvalid));
LUT5 #(
.INIT(32'hFFFF1410))
\s_axi_bresp[0]_INST_0
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_axi_bresp[4]),
.I4(\s_axi_bresp[0]_INST_0_i_1_n_0 ),
.O(s_axi_bresp[0]));
LUT6 #(
.INIT(64'h00CA000F00CA0000))
\s_axi_bresp[0]_INST_0_i_1
(.I0(m_axi_bresp[2]),
.I1(m_axi_bresp[6]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[0]),
.I5(m_axi_bresp[0]),
.O(\s_axi_bresp[0]_INST_0_i_1_n_0 ));
LUT5 #(
.INIT(32'hFFFF1410))
\s_axi_bresp[1]_INST_0
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_axi_bresp[5]),
.I4(\s_axi_bresp[1]_INST_0_i_1_n_0 ),
.O(s_axi_bresp[1]));
LUT6 #(
.INIT(64'h0A000C0F0A000C00))
\s_axi_bresp[1]_INST_0_i_1
(.I0(m_axi_bresp[7]),
.I1(m_axi_bresp[3]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[1]),
.I5(m_axi_bresp[1]),
.O(\s_axi_bresp[1]_INST_0_i_1_n_0 ));
zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter__parameterized0 splitter_ar
(.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(addr_arbiter_inst_n_4),
.\gen_no_arbiter.m_valid_i_reg (addr_arbiter_inst_n_113),
.m_atarget_enc(m_atarget_enc),
.m_axi_arready(m_axi_arready[2:1]),
.\m_payload_i_reg[0] (\s_axi_rdata[31] [0]),
.m_ready_d(m_ready_d),
.m_ready_d0(m_ready_d0_0),
.\m_ready_d_reg[1]_0 (splitter_ar_n_0),
.\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_5),
.s_axi_rready(s_axi_rready),
.sr_rvalid(sr_rvalid));
zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter splitter_aw
(.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axi.s_axi_wready_i_reg (\gen_decerr.decerr_slave_inst_n_9 ),
.\gen_no_arbiter.grant_rnw_reg (addr_arbiter_inst_n_95),
.\gen_no_arbiter.grant_rnw_reg_0 (addr_arbiter_inst_n_102),
.\gen_no_arbiter.m_valid_i_reg (splitter_aw_n_0),
.m_atarget_enc(m_atarget_enc),
.\m_atarget_enc_reg[0] (\gen_decerr.decerr_slave_inst_n_10 ),
.\m_atarget_enc_reg[1] (\gen_decerr.decerr_slave_inst_n_8 ),
.m_axi_awready(m_axi_awready[3:2]),
.m_axi_bvalid({m_axi_bvalid[2],m_axi_bvalid[0]}),
.m_axi_wready({m_axi_wready[3],m_axi_wready[1:0]}),
.m_ready_d(m_ready_d_1),
.m_ready_d0(m_ready_d0),
.\m_ready_d_reg[1]_0 (splitter_aw_n_4),
.\m_ready_d_reg[1]_1 (addr_arbiter_inst_n_96),
.\m_ready_d_reg[2]_0 (splitter_aw_n_5),
.\m_ready_d_reg[2]_1 (splitter_aw_n_6),
.s_axi_wlast(s_axi_wlast));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_decerr_slave" *)
module zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_decerr_slave
(mi_awready,
mi_rvalid,
\gen_axi.write_cs_reg[1]_0 ,
mi_arready,
\skid_buffer_reg[0] ,
m_valid_i_reg,
\m_ready_d_reg[1] ,
\m_ready_d_reg[2] ,
\m_ready_d_reg[1]_0 ,
\gen_no_arbiter.m_valid_i_reg ,
\m_ready_d_reg[0] ,
\m_ready_d_reg[0]_0 ,
SR,
aclk,
\m_atarget_hot_reg[4] ,
Q,
\m_ready_d_reg[2]_0 ,
aa_rready,
\m_ready_d_reg[1]_1 ,
\gen_no_arbiter.m_amesg_i_reg[51] ,
m_atarget_enc,
m_axi_rlast,
\m_atarget_enc_reg[0] ,
m_axi_rvalid,
m_axi_arready,
m_axi_awready,
m_axi_wready,
\m_atarget_enc_reg[0]_0 ,
m_axi_bvalid,
\gen_no_arbiter.grant_rnw_reg ,
\gen_no_arbiter.grant_rnw_reg_0 ,
\gen_no_arbiter.m_amesg_i_reg[50] ,
s_axi_rid_i,
aresetn_d);
output [0:0]mi_awready;
output [0:0]mi_rvalid;
output [0:0]\gen_axi.write_cs_reg[1]_0 ;
output [0:0]mi_arready;
output \skid_buffer_reg[0] ;
output m_valid_i_reg;
output \m_ready_d_reg[1] ;
output \m_ready_d_reg[2] ;
output \m_ready_d_reg[1]_0 ;
output \gen_no_arbiter.m_valid_i_reg ;
output \m_ready_d_reg[0] ;
output \m_ready_d_reg[0]_0 ;
input [0:0]SR;
input aclk;
input \m_atarget_hot_reg[4] ;
input [0:0]Q;
input \m_ready_d_reg[2]_0 ;
input aa_rready;
input \m_ready_d_reg[1]_1 ;
input [7:0]\gen_no_arbiter.m_amesg_i_reg[51] ;
input [2:0]m_atarget_enc;
input [1:0]m_axi_rlast;
input \m_atarget_enc_reg[0] ;
input [1:0]m_axi_rvalid;
input [1:0]m_axi_arready;
input [1:0]m_axi_awready;
input [0:0]m_axi_wready;
input \m_atarget_enc_reg[0]_0 ;
input [3:0]m_axi_bvalid;
input \gen_no_arbiter.grant_rnw_reg ;
input \gen_no_arbiter.grant_rnw_reg_0 ;
input \gen_no_arbiter.m_amesg_i_reg[50] ;
input s_axi_rid_i;
input aresetn_d;
wire [0:0]Q;
wire [0:0]SR;
wire aa_rready;
wire aclk;
wire aresetn_d;
wire \gen_axi.read_cnt[5]_i_2_n_0 ;
wire \gen_axi.read_cnt[7]_i_1_n_0 ;
wire \gen_axi.read_cnt[7]_i_3_n_0 ;
wire \gen_axi.read_cnt[7]_i_4_n_0 ;
wire [7:1]\gen_axi.read_cnt_reg__0 ;
wire [0:0]\gen_axi.read_cnt_reg__1 ;
wire \gen_axi.read_cs[0]_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_i_2_n_0 ;
wire \gen_axi.s_axi_awready_i_i_1_n_0 ;
wire \gen_axi.s_axi_bvalid_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_4_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_6_n_0 ;
wire \gen_axi.s_axi_wready_i_i_1_n_0 ;
wire \gen_axi.write_cs[0]_i_1_n_0 ;
wire \gen_axi.write_cs[1]_i_1_n_0 ;
wire \gen_axi.write_cs[1]_i_3_n_0 ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire \gen_no_arbiter.grant_rnw_reg_0 ;
wire \gen_no_arbiter.m_amesg_i_reg[50] ;
wire [7:0]\gen_no_arbiter.m_amesg_i_reg[51] ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire [2:0]m_atarget_enc;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[0]_0 ;
wire \m_atarget_hot_reg[4] ;
wire [1:0]m_axi_arready;
wire [1:0]m_axi_awready;
wire [3:0]m_axi_bvalid;
wire [1:0]m_axi_rlast;
wire [1:0]m_axi_rvalid;
wire [0:0]m_axi_wready;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[2] ;
wire \m_ready_d_reg[2]_0 ;
wire m_valid_i_reg;
wire [0:0]mi_arready;
wire [0:0]mi_awready;
wire [4:4]mi_bvalid;
wire [144:144]mi_rmesg;
wire [0:0]mi_rvalid;
wire [4:4]mi_wready;
wire [7:0]p_0_in;
wire s_axi_rid_i;
wire \skid_buffer[0]_i_2_n_0 ;
wire \skid_buffer_reg[0] ;
wire [0:0]write_cs;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h74))
\gen_axi.read_cnt[0]_i_1
(.I0(\gen_axi.read_cnt_reg__1 ),
.I1(mi_rvalid),
.I2(\gen_no_arbiter.m_amesg_i_reg[51] [0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h9F90))
\gen_axi.read_cnt[1]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [1]),
.I1(\gen_axi.read_cnt_reg__1 ),
.I2(mi_rvalid),
.I3(\gen_no_arbiter.m_amesg_i_reg[51] [1]),
.O(p_0_in[1]));
LUT5 #(
.INIT(32'hE1FFE100))
\gen_axi.read_cnt[2]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [1]),
.I1(\gen_axi.read_cnt_reg__1 ),
.I2(\gen_axi.read_cnt_reg__0 [2]),
.I3(mi_rvalid),
.I4(\gen_no_arbiter.m_amesg_i_reg[51] [2]),
.O(p_0_in[2]));
LUT6 #(
.INIT(64'hFE01FFFFFE010000))
\gen_axi.read_cnt[3]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [2]),
.I1(\gen_axi.read_cnt_reg__1 ),
.I2(\gen_axi.read_cnt_reg__0 [1]),
.I3(\gen_axi.read_cnt_reg__0 [3]),
.I4(mi_rvalid),
.I5(\gen_no_arbiter.m_amesg_i_reg[51] [3]),
.O(p_0_in[3]));
LUT4 #(
.INIT(16'h6F60))
\gen_axi.read_cnt[4]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [4]),
.I1(\gen_axi.read_cnt[5]_i_2_n_0 ),
.I2(mi_rvalid),
.I3(\gen_no_arbiter.m_amesg_i_reg[51] [4]),
.O(p_0_in[4]));
LUT5 #(
.INIT(32'hB4FFB400))
\gen_axi.read_cnt[5]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [4]),
.I1(\gen_axi.read_cnt[5]_i_2_n_0 ),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.I3(mi_rvalid),
.I4(\gen_no_arbiter.m_amesg_i_reg[51] [5]),
.O(p_0_in[5]));
LUT4 #(
.INIT(16'h0001))
\gen_axi.read_cnt[5]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [2]),
.I1(\gen_axi.read_cnt_reg__0 [3]),
.I2(\gen_axi.read_cnt_reg__1 ),
.I3(\gen_axi.read_cnt_reg__0 [1]),
.O(\gen_axi.read_cnt[5]_i_2_n_0 ));
LUT4 #(
.INIT(16'h9F90))
\gen_axi.read_cnt[6]_i_1
(.I0(\gen_axi.read_cnt[7]_i_4_n_0 ),
.I1(\gen_axi.read_cnt_reg__0 [6]),
.I2(mi_rvalid),
.I3(\gen_no_arbiter.m_amesg_i_reg[51] [6]),
.O(p_0_in[6]));
LUT6 #(
.INIT(64'h00008080F0008080))
\gen_axi.read_cnt[7]_i_1
(.I0(mi_arready),
.I1(\m_ready_d_reg[1]_1 ),
.I2(Q),
.I3(aa_rready),
.I4(mi_rvalid),
.I5(\gen_axi.read_cnt[7]_i_3_n_0 ),
.O(\gen_axi.read_cnt[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'hE1FFE100))
\gen_axi.read_cnt[7]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [6]),
.I1(\gen_axi.read_cnt[7]_i_4_n_0 ),
.I2(\gen_axi.read_cnt_reg__0 [7]),
.I3(mi_rvalid),
.I4(\gen_no_arbiter.m_amesg_i_reg[51] [7]),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h01))
\gen_axi.read_cnt[7]_i_3
(.I0(\gen_axi.read_cnt_reg__0 [7]),
.I1(\gen_axi.read_cnt[7]_i_4_n_0 ),
.I2(\gen_axi.read_cnt_reg__0 [6]),
.O(\gen_axi.read_cnt[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_axi.read_cnt[7]_i_4
(.I0(\gen_axi.read_cnt_reg__0 [5]),
.I1(\gen_axi.read_cnt_reg__0 [2]),
.I2(\gen_axi.read_cnt_reg__0 [3]),
.I3(\gen_axi.read_cnt_reg__1 ),
.I4(\gen_axi.read_cnt_reg__0 [1]),
.I5(\gen_axi.read_cnt_reg__0 [4]),
.O(\gen_axi.read_cnt[7]_i_4_n_0 ));
FDRE \gen_axi.read_cnt_reg[0]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[0]),
.Q(\gen_axi.read_cnt_reg__1 ),
.R(SR));
FDRE \gen_axi.read_cnt_reg[1]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[1]),
.Q(\gen_axi.read_cnt_reg__0 [1]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[2]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[2]),
.Q(\gen_axi.read_cnt_reg__0 [2]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[3]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[3]),
.Q(\gen_axi.read_cnt_reg__0 [3]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[4]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[4]),
.Q(\gen_axi.read_cnt_reg__0 [4]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[5]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[5]),
.Q(\gen_axi.read_cnt_reg__0 [5]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[6]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[6]),
.Q(\gen_axi.read_cnt_reg__0 [6]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[7]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[7]),
.Q(\gen_axi.read_cnt_reg__0 [7]),
.R(SR));
LUT6 #(
.INIT(64'h0FFFFFFF88008800))
\gen_axi.read_cs[0]_i_1
(.I0(mi_arready),
.I1(\m_ready_d_reg[1]_1 ),
.I2(aa_rready),
.I3(Q),
.I4(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I5(mi_rvalid),
.O(\gen_axi.read_cs[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.read_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.read_cs[0]_i_1_n_0 ),
.Q(mi_rvalid),
.R(SR));
LUT6 #(
.INIT(64'hCCCC888808888888))
\gen_axi.s_axi_arready_i_i_1
(.I0(\gen_axi.s_axi_arready_i_i_2_n_0 ),
.I1(aresetn_d),
.I2(\m_ready_d_reg[1]_1 ),
.I3(Q),
.I4(mi_arready),
.I5(mi_rvalid),
.O(\gen_axi.s_axi_arready_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h5557555555555555))
\gen_axi.s_axi_arready_i_i_2
(.I0(mi_rvalid),
.I1(\gen_axi.read_cnt_reg__0 [7]),
.I2(\gen_axi.read_cnt[7]_i_4_n_0 ),
.I3(\gen_axi.read_cnt_reg__0 [6]),
.I4(Q),
.I5(aa_rready),
.O(\gen_axi.s_axi_arready_i_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFDFDF30003333))
\gen_axi.s_axi_awready_i_i_1
(.I0(\m_ready_d_reg[2]_0 ),
.I1(write_cs),
.I2(Q),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.I4(\gen_axi.write_cs_reg[1]_0 ),
.I5(mi_awready),
.O(\gen_axi.s_axi_awready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_awready_i_i_1_n_0 ),
.Q(mi_awready),
.R(SR));
LUT6 #(
.INIT(64'hFFFFFF7FFF800000))
\gen_axi.s_axi_bvalid_i_i_1
(.I0(\gen_no_arbiter.grant_rnw_reg ),
.I1(Q),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(write_cs),
.I4(\m_atarget_hot_reg[4] ),
.I5(mi_bvalid),
.O(\gen_axi.s_axi_bvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_bvalid_i_i_1_n_0 ),
.Q(mi_bvalid),
.R(SR));
LUT6 #(
.INIT(64'hF4F4F4FFF4F4F400))
\gen_axi.s_axi_rlast_i_i_1
(.I0(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I1(mi_rvalid),
.I2(\gen_no_arbiter.m_amesg_i_reg[50] ),
.I3(s_axi_rid_i),
.I4(\gen_axi.s_axi_rlast_i_i_4_n_0 ),
.I5(mi_rmesg),
.O(\gen_axi.s_axi_rlast_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000004))
\gen_axi.s_axi_rlast_i_i_4
(.I0(\gen_axi.read_cnt_reg__0 [1]),
.I1(mi_rvalid),
.I2(\gen_axi.read_cnt_reg__0 [4]),
.I3(\gen_axi.read_cnt_reg__0 [3]),
.I4(\gen_axi.read_cnt_reg__0 [2]),
.I5(\gen_axi.s_axi_rlast_i_i_6_n_0 ),
.O(\gen_axi.s_axi_rlast_i_i_4_n_0 ));
LUT5 #(
.INIT(32'hFFFFFFF7))
\gen_axi.s_axi_rlast_i_i_6
(.I0(aa_rready),
.I1(Q),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.I3(\gen_axi.read_cnt_reg__0 [7]),
.I4(\gen_axi.read_cnt_reg__0 [6]),
.O(\gen_axi.s_axi_rlast_i_i_6_n_0 ));
FDRE \gen_axi.s_axi_rlast_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_rlast_i_i_1_n_0 ),
.Q(mi_rmesg),
.R(SR));
LUT5 #(
.INIT(32'h77770003))
\gen_axi.s_axi_wready_i_i_1
(.I0(\m_atarget_hot_reg[4] ),
.I1(write_cs),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(\gen_no_arbiter.grant_rnw_reg_0 ),
.I4(mi_wready),
.O(\gen_axi.s_axi_wready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_wready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_wready_i_i_1_n_0 ),
.Q(mi_wready),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h1A))
\gen_axi.write_cs[0]_i_1
(.I0(write_cs),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(\gen_axi.write_cs[1]_i_3_n_0 ),
.O(\gen_axi.write_cs[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hAAAABF00))
\gen_axi.write_cs[1]_i_1
(.I0(write_cs),
.I1(\gen_no_arbiter.grant_rnw_reg ),
.I2(Q),
.I3(\gen_axi.write_cs_reg[1]_0 ),
.I4(\gen_axi.write_cs[1]_i_3_n_0 ),
.O(\gen_axi.write_cs[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h8B88888888888888))
\gen_axi.write_cs[1]_i_3
(.I0(\m_atarget_hot_reg[4] ),
.I1(write_cs),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(Q),
.I4(mi_awready),
.I5(\m_ready_d_reg[2]_0 ),
.O(\gen_axi.write_cs[1]_i_3_n_0 ));
FDRE \gen_axi.write_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[0]_i_1_n_0 ),
.Q(write_cs),
.R(SR));
FDRE \gen_axi.write_cs_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[1]_i_1_n_0 ),
.Q(\gen_axi.write_cs_reg[1]_0 ),
.R(SR));
LUT5 #(
.INIT(32'hFCF7FFF7))
\gen_no_arbiter.m_grant_hot_i[0]_i_4
(.I0(mi_wready),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_wready),
.O(\gen_no_arbiter.m_valid_i_reg ));
LUT6 #(
.INIT(64'h00A00F0C00A0000C))
\m_ready_d[1]_i_5
(.I0(m_axi_arready[1]),
.I1(m_axi_arready[0]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.I5(mi_arready),
.O(\m_ready_d_reg[1] ));
LUT6 #(
.INIT(64'h00000AFC00000A0C))
\m_ready_d[2]_i_5
(.I0(mi_awready),
.I1(m_axi_awready[0]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.I5(m_axi_awready[1]),
.O(\m_ready_d_reg[2] ));
LUT6 #(
.INIT(64'h00CF0A0000C00A00))
m_valid_i_i_3
(.I0(mi_rvalid),
.I1(m_axi_rvalid[1]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[0]),
.I5(m_axi_rvalid[0]),
.O(m_valid_i_reg));
LUT6 #(
.INIT(64'h00000000FCFDFFFD))
\s_axi_bvalid[0]_INST_0_i_1
(.I0(m_axi_bvalid[0]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_bvalid[2]),
.I5(\m_ready_d_reg[0]_0 ),
.O(\m_ready_d_reg[0] ));
LUT6 #(
.INIT(64'h0F0A00C0000A00C0))
\s_axi_bvalid[0]_INST_0_i_2
(.I0(m_axi_bvalid[1]),
.I1(mi_bvalid),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_atarget_enc[0]),
.I5(m_axi_bvalid[3]),
.O(\m_ready_d_reg[0]_0 ));
LUT6 #(
.INIT(64'h00000000FCF7FFF7))
\s_axi_wready[0]_INST_0_i_1
(.I0(m_axi_wready),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(mi_wready),
.I5(\m_atarget_enc_reg[0]_0 ),
.O(\m_ready_d_reg[1]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF1000))
\skid_buffer[0]_i_1
(.I0(m_atarget_enc[2]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[1]),
.I3(m_axi_rlast[1]),
.I4(\skid_buffer[0]_i_2_n_0 ),
.I5(\m_atarget_enc_reg[0] ),
.O(\skid_buffer_reg[0] ));
LUT5 #(
.INIT(32'h00230020))
\skid_buffer[0]_i_2
(.I0(mi_rmesg),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rlast[0]),
.O(\skid_buffer[0]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_splitter" *)
module zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter
(\gen_no_arbiter.m_valid_i_reg ,
m_ready_d,
\m_ready_d_reg[1]_0 ,
\m_ready_d_reg[2]_0 ,
\m_ready_d_reg[2]_1 ,
\gen_axi.s_axi_wready_i_reg ,
s_axi_wlast,
\gen_no_arbiter.grant_rnw_reg ,
m_axi_wready,
m_atarget_enc,
m_axi_awready,
m_axi_bvalid,
m_ready_d0,
aresetn_d,
\m_ready_d_reg[1]_1 ,
\m_atarget_enc_reg[1] ,
\m_atarget_enc_reg[0] ,
\gen_no_arbiter.grant_rnw_reg_0 ,
aclk);
output \gen_no_arbiter.m_valid_i_reg ;
output [2:0]m_ready_d;
output \m_ready_d_reg[1]_0 ;
output \m_ready_d_reg[2]_0 ;
output \m_ready_d_reg[2]_1 ;
input \gen_axi.s_axi_wready_i_reg ;
input [0:0]s_axi_wlast;
input \gen_no_arbiter.grant_rnw_reg ;
input [2:0]m_axi_wready;
input [2:0]m_atarget_enc;
input [1:0]m_axi_awready;
input [1:0]m_axi_bvalid;
input [0:0]m_ready_d0;
input aresetn_d;
input \m_ready_d_reg[1]_1 ;
input \m_atarget_enc_reg[1] ;
input \m_atarget_enc_reg[0] ;
input \gen_no_arbiter.grant_rnw_reg_0 ;
input aclk;
wire aclk;
wire aresetn_d;
wire \gen_axi.s_axi_wready_i_reg ;
wire \gen_no_arbiter.grant_rnw_reg ;
wire \gen_no_arbiter.grant_rnw_reg_0 ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire [2:0]m_atarget_enc;
wire \m_atarget_enc_reg[0] ;
wire \m_atarget_enc_reg[1] ;
wire [1:0]m_axi_awready;
wire [1:0]m_axi_bvalid;
wire [2:0]m_axi_wready;
wire [2:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d[2]_i_1_n_0 ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[2]_0 ;
wire \m_ready_d_reg[2]_1 ;
wire [0:0]s_axi_wlast;
LUT5 #(
.INIT(32'h55550455))
\gen_no_arbiter.m_grant_hot_i[0]_i_3
(.I0(m_ready_d[1]),
.I1(\gen_axi.s_axi_wready_i_reg ),
.I2(\m_ready_d_reg[1]_0 ),
.I3(s_axi_wlast),
.I4(\gen_no_arbiter.grant_rnw_reg ),
.O(\gen_no_arbiter.m_valid_i_reg ));
LUT5 #(
.INIT(32'h0000BA00))
\m_ready_d[0]_i_1
(.I0(m_ready_d[0]),
.I1(\m_atarget_enc_reg[0] ),
.I2(\gen_no_arbiter.grant_rnw_reg_0 ),
.I3(aresetn_d),
.I4(\m_ready_d_reg[1]_1 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h00000000AABA0000))
\m_ready_d[1]_i_1
(.I0(m_ready_d[1]),
.I1(\m_atarget_enc_reg[1] ),
.I2(s_axi_wlast),
.I3(\gen_no_arbiter.grant_rnw_reg ),
.I4(aresetn_d),
.I5(\m_ready_d_reg[1]_1 ),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h08))
\m_ready_d[2]_i_1
(.I0(m_ready_d0),
.I1(aresetn_d),
.I2(\m_ready_d_reg[1]_1 ),
.O(\m_ready_d[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hDCFFDFFF))
\m_ready_d[2]_i_4
(.I0(m_axi_awready[1]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_awready[0]),
.O(\m_ready_d_reg[2]_0 ));
LUT5 #(
.INIT(32'hFFF4FFF7))
\m_ready_d[2]_i_7
(.I0(m_axi_bvalid[1]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_bvalid[0]),
.O(\m_ready_d_reg[2]_1 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[2]_i_1_n_0 ),
.Q(m_ready_d[2]),
.R(1'b0));
LUT6 #(
.INIT(64'h00F000AC000000AC))
\s_axi_wready[0]_INST_0_i_2
(.I0(m_axi_wready[1]),
.I1(m_axi_wready[0]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_atarget_enc[1]),
.I5(m_axi_wready[2]),
.O(\m_ready_d_reg[1]_0 ));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_splitter" *)
module zqynq_lab_1_design_xbar_1_axi_crossbar_v2_1_14_splitter__parameterized0
(\m_ready_d_reg[1]_0 ,
m_ready_d,
m_axi_arready,
m_atarget_enc,
aresetn_d,
m_ready_d0,
\m_ready_d_reg[1]_1 ,
\gen_no_arbiter.m_valid_i_reg ,
s_axi_rready,
sr_rvalid,
\m_payload_i_reg[0] ,
aresetn_d_reg,
aclk);
output \m_ready_d_reg[1]_0 ;
output [1:0]m_ready_d;
input [1:0]m_axi_arready;
input [2:0]m_atarget_enc;
input aresetn_d;
input [0:0]m_ready_d0;
input \m_ready_d_reg[1]_1 ;
input \gen_no_arbiter.m_valid_i_reg ;
input [0:0]s_axi_rready;
input sr_rvalid;
input [0:0]\m_payload_i_reg[0] ;
input aresetn_d_reg;
input aclk;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire \gen_no_arbiter.m_valid_i_reg ;
wire [2:0]m_atarget_enc;
wire [1:0]m_axi_arready;
wire [0:0]\m_payload_i_reg[0] ;
wire [1:0]m_ready_d;
wire [0:0]m_ready_d0;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire [0:0]s_axi_rready;
wire sr_rvalid;
LUT6 #(
.INIT(64'h00000000BAAAAAAA))
\m_ready_d[0]_i_1
(.I0(m_ready_d[0]),
.I1(\gen_no_arbiter.m_valid_i_reg ),
.I2(s_axi_rready),
.I3(sr_rvalid),
.I4(\m_payload_i_reg[0] ),
.I5(aresetn_d_reg),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\m_ready_d[1]_i_1
(.I0(aresetn_d),
.I1(m_ready_d0),
.I2(\m_ready_d_reg[1]_1 ),
.O(\m_ready_d[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFCDFFFDF))
\m_ready_d[1]_i_4
(.I0(m_axi_arready[0]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_arready[1]),
.O(\m_ready_d_reg[1]_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zqynq_lab_1_design_xbar_1_axi_register_slice_v2_1_13_axic_register_slice
(sr_rvalid,
aa_rready,
m_ready_d0,
\s_axi_rdata[31] ,
\skid_buffer_reg[0]_0 ,
m_valid_i_reg_0,
s_axi_rvalid,
m_axi_rready,
m_valid_i_reg_1,
\aresetn_d_reg[1]_0 ,
aclk,
\aresetn_d_reg[0]_0 ,
s_axi_rready,
m_valid_i,
aa_grant_rnw,
m_ready_d,
m_axi_rresp,
m_atarget_enc,
\m_atarget_enc_reg[2] ,
m_axi_rdata,
m_axi_rlast,
m_axi_rvalid,
aa_grant_any,
Q,
SR,
E);
output sr_rvalid;
output aa_rready;
output [0:0]m_ready_d0;
output [34:0]\s_axi_rdata[31] ;
output \skid_buffer_reg[0]_0 ;
output m_valid_i_reg_0;
output [0:0]s_axi_rvalid;
output [3:0]m_axi_rready;
output [1:0]m_valid_i_reg_1;
input \aresetn_d_reg[1]_0 ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [0:0]s_axi_rready;
input m_valid_i;
input aa_grant_rnw;
input [0:0]m_ready_d;
input [7:0]m_axi_rresp;
input [2:0]m_atarget_enc;
input \m_atarget_enc_reg[2] ;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rlast;
input [1:0]m_axi_rvalid;
input aa_grant_any;
input [3:0]Q;
input [0:0]SR;
input [0:0]E;
wire [0:0]E;
wire [3:0]Q;
wire [0:0]SR;
wire aa_grant_any;
wire aa_grant_rnw;
wire aa_rready;
wire aclk;
wire \aresetn_d_reg[0]_0 ;
wire \aresetn_d_reg[1]_0 ;
wire [2:0]m_atarget_enc;
wire \m_atarget_enc_reg[2] ;
wire [127:0]m_axi_rdata;
wire [1:0]m_axi_rlast;
wire [3:0]m_axi_rready;
wire [7:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire \m_payload_i[1]_i_2_n_0 ;
wire \m_payload_i[1]_i_3_n_0 ;
wire \m_payload_i[1]_i_4_n_0 ;
wire \m_payload_i[2]_i_2_n_0 ;
wire \m_payload_i[2]_i_3_n_0 ;
wire [0:0]m_ready_d;
wire [0:0]m_ready_d0;
wire m_valid_i;
wire m_valid_i_reg_0;
wire [1:0]m_valid_i_reg_1;
wire [34:0]\s_axi_rdata[31] ;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rvalid;
wire [34:0]skid_buffer;
wire \skid_buffer[10]_i_1_n_0 ;
wire \skid_buffer[10]_i_2_n_0 ;
wire \skid_buffer[11]_i_1_n_0 ;
wire \skid_buffer[11]_i_2_n_0 ;
wire \skid_buffer[12]_i_1_n_0 ;
wire \skid_buffer[12]_i_2_n_0 ;
wire \skid_buffer[13]_i_1_n_0 ;
wire \skid_buffer[13]_i_2_n_0 ;
wire \skid_buffer[14]_i_1_n_0 ;
wire \skid_buffer[14]_i_2_n_0 ;
wire \skid_buffer[15]_i_1_n_0 ;
wire \skid_buffer[15]_i_2_n_0 ;
wire \skid_buffer[16]_i_1_n_0 ;
wire \skid_buffer[16]_i_2_n_0 ;
wire \skid_buffer[17]_i_1_n_0 ;
wire \skid_buffer[17]_i_2_n_0 ;
wire \skid_buffer[18]_i_1_n_0 ;
wire \skid_buffer[18]_i_2_n_0 ;
wire \skid_buffer[19]_i_1_n_0 ;
wire \skid_buffer[19]_i_2_n_0 ;
wire \skid_buffer[20]_i_1_n_0 ;
wire \skid_buffer[20]_i_2_n_0 ;
wire \skid_buffer[21]_i_1_n_0 ;
wire \skid_buffer[21]_i_2_n_0 ;
wire \skid_buffer[22]_i_1_n_0 ;
wire \skid_buffer[22]_i_2_n_0 ;
wire \skid_buffer[23]_i_1_n_0 ;
wire \skid_buffer[23]_i_2_n_0 ;
wire \skid_buffer[24]_i_1_n_0 ;
wire \skid_buffer[24]_i_2_n_0 ;
wire \skid_buffer[25]_i_1_n_0 ;
wire \skid_buffer[25]_i_2_n_0 ;
wire \skid_buffer[26]_i_1_n_0 ;
wire \skid_buffer[26]_i_2_n_0 ;
wire \skid_buffer[27]_i_1_n_0 ;
wire \skid_buffer[27]_i_2_n_0 ;
wire \skid_buffer[28]_i_1_n_0 ;
wire \skid_buffer[28]_i_2_n_0 ;
wire \skid_buffer[29]_i_1_n_0 ;
wire \skid_buffer[29]_i_2_n_0 ;
wire \skid_buffer[30]_i_1_n_0 ;
wire \skid_buffer[30]_i_2_n_0 ;
wire \skid_buffer[31]_i_1_n_0 ;
wire \skid_buffer[31]_i_2_n_0 ;
wire \skid_buffer[32]_i_1_n_0 ;
wire \skid_buffer[32]_i_2_n_0 ;
wire \skid_buffer[33]_i_1_n_0 ;
wire \skid_buffer[33]_i_2_n_0 ;
wire \skid_buffer[34]_i_1_n_0 ;
wire \skid_buffer[34]_i_2_n_0 ;
wire \skid_buffer[3]_i_1_n_0 ;
wire \skid_buffer[3]_i_2_n_0 ;
wire \skid_buffer[4]_i_1_n_0 ;
wire \skid_buffer[4]_i_2_n_0 ;
wire \skid_buffer[5]_i_1_n_0 ;
wire \skid_buffer[5]_i_2_n_0 ;
wire \skid_buffer[6]_i_1_n_0 ;
wire \skid_buffer[6]_i_2_n_0 ;
wire \skid_buffer[7]_i_1_n_0 ;
wire \skid_buffer[7]_i_2_n_0 ;
wire \skid_buffer[8]_i_1_n_0 ;
wire \skid_buffer[8]_i_2_n_0 ;
wire \skid_buffer[9]_i_1_n_0 ;
wire \skid_buffer[9]_i_2_n_0 ;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire sr_rvalid;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(1'b1),
.Q(m_valid_i_reg_1[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_reg_1[0]),
.Q(m_valid_i_reg_1[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[0]_INST_0
(.I0(aa_rready),
.I1(Q[0]),
.O(m_axi_rready[0]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[1]_INST_0
(.I0(aa_rready),
.I1(Q[1]),
.O(m_axi_rready[1]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[2]_INST_0
(.I0(aa_rready),
.I1(Q[2]),
.O(m_axi_rready[2]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\m_axi_rready[3]_INST_0
(.I0(aa_rready),
.I1(Q[3]),
.O(m_axi_rready[3]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(\m_atarget_enc_reg[2] ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(\skid_buffer[10]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(\skid_buffer[11]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(\skid_buffer[12]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(\skid_buffer[13]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(\skid_buffer[14]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(\skid_buffer[15]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(\skid_buffer[16]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(\skid_buffer[17]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(\skid_buffer[18]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(\skid_buffer[19]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
LUT6 #(
.INIT(64'hCAFAFAFACAFACAFA))
\m_payload_i[1]_i_1
(.I0(\skid_buffer_reg_n_0_[1] ),
.I1(\m_payload_i[1]_i_2_n_0 ),
.I2(aa_rready),
.I3(\m_payload_i[1]_i_3_n_0 ),
.I4(\m_payload_i[1]_i_4_n_0 ),
.I5(m_axi_rresp[2]),
.O(skid_buffer[1]));
LUT6 #(
.INIT(64'h0000A0CF0000A0C0))
\m_payload_i[1]_i_2
(.I0(m_axi_rresp[6]),
.I1(m_axi_rresp[4]),
.I2(m_atarget_enc[1]),
.I3(m_atarget_enc[0]),
.I4(m_atarget_enc[2]),
.I5(m_axi_rresp[0]),
.O(\m_payload_i[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hEF))
\m_payload_i[1]_i_3
(.I0(m_atarget_enc[0]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.O(\m_payload_i[1]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFB))
\m_payload_i[1]_i_4
(.I0(m_atarget_enc[1]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.O(\m_payload_i[1]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(\skid_buffer[20]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(\skid_buffer[21]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(\skid_buffer[22]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(\skid_buffer[23]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(\skid_buffer[24]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(\skid_buffer[25]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(\skid_buffer[26]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(\skid_buffer[27]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(\skid_buffer[28]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(\skid_buffer[29]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'hE0EE))
\m_payload_i[2]_i_1
(.I0(\skid_buffer_reg_n_0_[2] ),
.I1(aa_rready),
.I2(\m_payload_i[2]_i_2_n_0 ),
.I3(\m_payload_i[2]_i_3_n_0 ),
.O(skid_buffer[2]));
LUT6 #(
.INIT(64'h030E0302FFFFFFFF))
\m_payload_i[2]_i_2
(.I0(m_axi_rresp[1]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rresp[5]),
.I5(aa_rready),
.O(\m_payload_i[2]_i_2_n_0 ));
LUT5 #(
.INIT(32'hF3F7FFF7))
\m_payload_i[2]_i_3
(.I0(m_axi_rresp[3]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rresp[7]),
.O(\m_payload_i[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(\skid_buffer[30]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(\skid_buffer[31]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(\skid_buffer[32]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(\skid_buffer[33]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_2
(.I0(\skid_buffer[34]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(\skid_buffer[3]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(\skid_buffer[4]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(\skid_buffer[5]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(\skid_buffer[6]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(\skid_buffer[7]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(\skid_buffer[8]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(\skid_buffer[9]_i_1_n_0 ),
.I1(aa_rready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(\s_axi_rdata[31] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(\s_axi_rdata[31] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(\s_axi_rdata[31] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(\s_axi_rdata[31] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(\s_axi_rdata[31] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(\s_axi_rdata[31] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(\s_axi_rdata[31] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(\s_axi_rdata[31] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(\s_axi_rdata[31] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(\s_axi_rdata[31] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(\s_axi_rdata[31] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(\s_axi_rdata[31] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(\s_axi_rdata[31] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(\s_axi_rdata[31] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(\s_axi_rdata[31] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(\s_axi_rdata[31] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(\s_axi_rdata[31] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(\s_axi_rdata[31] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(\s_axi_rdata[31] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(\s_axi_rdata[31] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(\s_axi_rdata[31] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(\s_axi_rdata[31] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(\s_axi_rdata[31] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(\s_axi_rdata[31] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(\s_axi_rdata[31] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(\s_axi_rdata[31] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(\s_axi_rdata[31] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\s_axi_rdata[31] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(\s_axi_rdata[31] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(\s_axi_rdata[31] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(\s_axi_rdata[31] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(\s_axi_rdata[31] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(\s_axi_rdata[31] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(\s_axi_rdata[31] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(\s_axi_rdata[31] [9]),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF80000000))
\m_ready_d[1]_i_2__0
(.I0(\s_axi_rdata[31] [0]),
.I1(sr_rvalid),
.I2(s_axi_rready),
.I3(m_valid_i),
.I4(aa_grant_rnw),
.I5(m_ready_d),
.O(m_ready_d0));
LUT5 #(
.INIT(32'hFFF4FFF7))
m_valid_i_i_4
(.I0(m_axi_rvalid[1]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rvalid[0]),
.O(m_valid_i_reg_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[1]_0 ),
.Q(sr_rvalid),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
\s_axi_rvalid[0]_INST_0
(.I0(sr_rvalid),
.I1(aa_grant_any),
.O(s_axi_rvalid));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(aa_rready),
.R(1'b0));
LUT5 #(
.INIT(32'h0C080008))
\skid_buffer[0]_i_3
(.I0(m_axi_rlast[0]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rlast[1]),
.O(\skid_buffer_reg[0]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[10]_i_1
(.I0(m_axi_rdata[39]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[71]),
.I5(\skid_buffer[10]_i_2_n_0 ),
.O(\skid_buffer[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[10]_i_2
(.I0(m_axi_rdata[103]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[7]),
.O(\skid_buffer[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[11]_i_1
(.I0(m_axi_rdata[72]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[40]),
.I5(\skid_buffer[11]_i_2_n_0 ),
.O(\skid_buffer[11]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[11]_i_2
(.I0(m_axi_rdata[104]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[8]),
.O(\skid_buffer[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[12]_i_1
(.I0(m_axi_rdata[73]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[41]),
.I5(\skid_buffer[12]_i_2_n_0 ),
.O(\skid_buffer[12]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[12]_i_2
(.I0(m_axi_rdata[105]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[9]),
.O(\skid_buffer[12]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[13]_i_1
(.I0(m_axi_rdata[74]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[42]),
.I5(\skid_buffer[13]_i_2_n_0 ),
.O(\skid_buffer[13]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[13]_i_2
(.I0(m_axi_rdata[106]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[10]),
.O(\skid_buffer[13]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[14]_i_1
(.I0(m_axi_rdata[43]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[75]),
.I5(\skid_buffer[14]_i_2_n_0 ),
.O(\skid_buffer[14]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[14]_i_2
(.I0(m_axi_rdata[107]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[11]),
.O(\skid_buffer[14]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[15]_i_1
(.I0(m_axi_rdata[44]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[76]),
.I5(\skid_buffer[15]_i_2_n_0 ),
.O(\skid_buffer[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0C020002))
\skid_buffer[15]_i_2
(.I0(m_axi_rdata[12]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[108]),
.O(\skid_buffer[15]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[16]_i_1
(.I0(m_axi_rdata[45]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[77]),
.I5(\skid_buffer[16]_i_2_n_0 ),
.O(\skid_buffer[16]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[16]_i_2
(.I0(m_axi_rdata[109]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[13]),
.O(\skid_buffer[16]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[17]_i_1
(.I0(m_axi_rdata[46]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[78]),
.I5(\skid_buffer[17]_i_2_n_0 ),
.O(\skid_buffer[17]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[17]_i_2
(.I0(m_axi_rdata[110]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[14]),
.O(\skid_buffer[17]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[18]_i_1
(.I0(m_axi_rdata[47]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[79]),
.I5(\skid_buffer[18]_i_2_n_0 ),
.O(\skid_buffer[18]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[18]_i_2
(.I0(m_axi_rdata[111]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[15]),
.O(\skid_buffer[18]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[19]_i_1
(.I0(m_axi_rdata[80]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[48]),
.I5(\skid_buffer[19]_i_2_n_0 ),
.O(\skid_buffer[19]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[19]_i_2
(.I0(m_axi_rdata[112]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[16]),
.O(\skid_buffer[19]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[20]_i_1
(.I0(m_axi_rdata[49]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[81]),
.I5(\skid_buffer[20]_i_2_n_0 ),
.O(\skid_buffer[20]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[20]_i_2
(.I0(m_axi_rdata[113]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[17]),
.O(\skid_buffer[20]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[21]_i_1
(.I0(m_axi_rdata[50]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[82]),
.I5(\skid_buffer[21]_i_2_n_0 ),
.O(\skid_buffer[21]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[21]_i_2
(.I0(m_axi_rdata[114]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[18]),
.O(\skid_buffer[21]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[22]_i_1
(.I0(m_axi_rdata[51]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[83]),
.I5(\skid_buffer[22]_i_2_n_0 ),
.O(\skid_buffer[22]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[22]_i_2
(.I0(m_axi_rdata[115]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[19]),
.O(\skid_buffer[22]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[23]_i_1
(.I0(m_axi_rdata[52]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[84]),
.I5(\skid_buffer[23]_i_2_n_0 ),
.O(\skid_buffer[23]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[23]_i_2
(.I0(m_axi_rdata[116]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[20]),
.O(\skid_buffer[23]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[24]_i_1
(.I0(m_axi_rdata[85]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[53]),
.I5(\skid_buffer[24]_i_2_n_0 ),
.O(\skid_buffer[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[24]_i_2
(.I0(m_axi_rdata[117]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[21]),
.O(\skid_buffer[24]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[25]_i_1
(.I0(m_axi_rdata[54]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[86]),
.I5(\skid_buffer[25]_i_2_n_0 ),
.O(\skid_buffer[25]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[25]_i_2
(.I0(m_axi_rdata[118]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[22]),
.O(\skid_buffer[25]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[26]_i_1
(.I0(m_axi_rdata[55]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[87]),
.I5(\skid_buffer[26]_i_2_n_0 ),
.O(\skid_buffer[26]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0C020002))
\skid_buffer[26]_i_2
(.I0(m_axi_rdata[23]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[119]),
.O(\skid_buffer[26]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[27]_i_1
(.I0(m_axi_rdata[56]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[88]),
.I5(\skid_buffer[27]_i_2_n_0 ),
.O(\skid_buffer[27]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[27]_i_2
(.I0(m_axi_rdata[120]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[24]),
.O(\skid_buffer[27]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[28]_i_1
(.I0(m_axi_rdata[57]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[89]),
.I5(\skid_buffer[28]_i_2_n_0 ),
.O(\skid_buffer[28]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0C020002))
\skid_buffer[28]_i_2
(.I0(m_axi_rdata[25]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[121]),
.O(\skid_buffer[28]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[29]_i_1
(.I0(m_axi_rdata[90]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[58]),
.I5(\skid_buffer[29]_i_2_n_0 ),
.O(\skid_buffer[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[29]_i_2
(.I0(m_axi_rdata[122]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[26]),
.O(\skid_buffer[29]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[30]_i_1
(.I0(m_axi_rdata[91]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[59]),
.I5(\skid_buffer[30]_i_2_n_0 ),
.O(\skid_buffer[30]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[30]_i_2
(.I0(m_axi_rdata[123]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[27]),
.O(\skid_buffer[30]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[31]_i_1
(.I0(m_axi_rdata[60]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[92]),
.I5(\skid_buffer[31]_i_2_n_0 ),
.O(\skid_buffer[31]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0C020002))
\skid_buffer[31]_i_2
(.I0(m_axi_rdata[28]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[124]),
.O(\skid_buffer[31]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[32]_i_1
(.I0(m_axi_rdata[93]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[61]),
.I5(\skid_buffer[32]_i_2_n_0 ),
.O(\skid_buffer[32]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[32]_i_2
(.I0(m_axi_rdata[125]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[29]),
.O(\skid_buffer[32]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[33]_i_1
(.I0(m_axi_rdata[62]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[94]),
.I5(\skid_buffer[33]_i_2_n_0 ),
.O(\skid_buffer[33]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[33]_i_2
(.I0(m_axi_rdata[126]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[30]),
.O(\skid_buffer[33]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[34]_i_1
(.I0(m_axi_rdata[95]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[63]),
.I5(\skid_buffer[34]_i_2_n_0 ),
.O(\skid_buffer[34]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[34]_i_2
(.I0(m_axi_rdata[127]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[31]),
.O(\skid_buffer[34]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[3]_i_1
(.I0(m_axi_rdata[64]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[32]),
.I5(\skid_buffer[3]_i_2_n_0 ),
.O(\skid_buffer[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[3]_i_2
(.I0(m_axi_rdata[96]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[0]),
.O(\skid_buffer[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[4]_i_1
(.I0(m_axi_rdata[33]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[65]),
.I5(\skid_buffer[4]_i_2_n_0 ),
.O(\skid_buffer[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[4]_i_2
(.I0(m_axi_rdata[97]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[1]),
.O(\skid_buffer[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[5]_i_1
(.I0(m_axi_rdata[34]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[66]),
.I5(\skid_buffer[5]_i_2_n_0 ),
.O(\skid_buffer[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[5]_i_2
(.I0(m_axi_rdata[98]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[2]),
.O(\skid_buffer[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[6]_i_1
(.I0(m_axi_rdata[67]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[35]),
.I5(\skid_buffer[6]_i_2_n_0 ),
.O(\skid_buffer[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'h0C020002))
\skid_buffer[6]_i_2
(.I0(m_axi_rdata[3]),
.I1(m_atarget_enc[0]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[99]),
.O(\skid_buffer[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[7]_i_1
(.I0(m_axi_rdata[36]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[68]),
.I5(\skid_buffer[7]_i_2_n_0 ),
.O(\skid_buffer[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[7]_i_2
(.I0(m_axi_rdata[100]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[4]),
.O(\skid_buffer[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00380008))
\skid_buffer[8]_i_1
(.I0(m_axi_rdata[69]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[2]),
.I4(m_axi_rdata[37]),
.I5(\skid_buffer[8]_i_2_n_0 ),
.O(\skid_buffer[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[8]_i_2
(.I0(m_axi_rdata[101]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[5]),
.O(\skid_buffer[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF03200020))
\skid_buffer[9]_i_1
(.I0(m_axi_rdata[38]),
.I1(m_atarget_enc[2]),
.I2(m_atarget_enc[0]),
.I3(m_atarget_enc[1]),
.I4(m_axi_rdata[70]),
.I5(\skid_buffer[9]_i_2_n_0 ),
.O(\skid_buffer[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'h08030800))
\skid_buffer[9]_i_2
(.I0(m_axi_rdata[102]),
.I1(m_atarget_enc[1]),
.I2(m_atarget_enc[2]),
.I3(m_atarget_enc[0]),
.I4(m_axi_rdata[6]),
.O(\skid_buffer[9]_i_2_n_0 ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(aa_rready),
.D(\m_atarget_enc_reg[2] ),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[10]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[11]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[12]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[13]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[14]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[15]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[16]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[17]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[18]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[19]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[20]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[21]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[22]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[23]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[24]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[25]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[26]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[27]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[28]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[29]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[30]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[31]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[32]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[33]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[34]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[3]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[4]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[5]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[6]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[7]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[8]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(aa_rready),
.D(\skid_buffer[9]_i_1_n_0 ),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: cpx_buf_p0.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: cpx_buf_p0
// Description: datapath portion of CPX
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
`include "sys.h"
`include "iop.h"
module cpx_buf_p0(/*AUTOARG*/
// Outputs
scache0_cpx_req_bufp0_cq, scache0_cpx_atom_bufp0_cq,
cpx_scache0_grant_bufp0_ca, cpx_spc0_data_rdy_bufp0_cx,
// Inputs
scache0_cpx_req_bufpt_cq_l, scache0_cpx_atom_bufpt_cq_l,
cpx_scache0_grant_bufp1_ca_l, cpx_spc0_data_rdy_bufp1_cx
);
output [7:0] scache0_cpx_req_bufp0_cq;
output scache0_cpx_atom_bufp0_cq;
output [7:0] cpx_scache0_grant_bufp0_ca;
output cpx_spc0_data_rdy_bufp0_cx;
input [7:0] scache0_cpx_req_bufpt_cq_l;
input scache0_cpx_atom_bufpt_cq_l;
input [7:0] cpx_scache0_grant_bufp1_ca_l;
input cpx_spc0_data_rdy_bufp1_cx;
assign scache0_cpx_req_bufp0_cq[7:0] = ~scache0_cpx_req_bufpt_cq_l[7:0];
assign scache0_cpx_atom_bufp0_cq = ~scache0_cpx_atom_bufpt_cq_l;
assign cpx_scache0_grant_bufp0_ca = ~cpx_scache0_grant_bufp1_ca_l;
assign cpx_spc0_data_rdy_bufp0_cx = cpx_spc0_data_rdy_bufp1_cx;
endmodule
|
/*
* Zet processor top level file
* Copyright (c) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet (
// Common signals
input clk_i,
input rst_i,
// Wishbone master interface - fetch
input [15:0] wbf_dat_i,
output [19:1] wbf_adr_o,
output [ 1:0] wbf_sel_o,
output wbf_cyc_o,
output wbf_stb_o,
input wbf_ack_i,
// Wishbone master interface - exec
input [15:0] wb_dat_i,
output [15:0] wb_dat_o,
output [19:1] wb_adr_o,
output wb_we_o,
output wb_tga_o, // io/mem
output [ 1:0] wb_sel_o,
output wb_stb_o,
output wb_cyc_o,
input wb_ack_i,
// Interrupt line
input intr, // interrupt request
output inta, // interrupt acknowledge
input [ 3:0] iid, // interrupt id
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [19:0] umie_adr_i;
wire [15:0] umie_dat_o;
wire [15:0] umie_dat_i;
wire umie_we_i;
wire umie_by_i;
wire umie_stb_i;
wire umie_ack_o;
wire umie_tga_i;
// Module instances
zet_core core (
.clk (clk_i),
.rst (rst_i),
.wbf_dat_i(wbf_dat_i),
.wbf_adr_o(wbf_adr_o),
.wbf_sel_o(wbf_sel_o),
.wbf_cyc_o(wbf_cyc_o),
.wbf_stb_o(wbf_stb_o),
.wbf_ack_i(wbf_ack_i),
.umie_adr_o (umie_adr_i),
.umie_dat_i (umie_dat_o),
.umie_dat_o (umie_dat_i),
.umie_we_o (umie_we_i),
.umie_by_o (umie_by_i),
.umie_stb_o (umie_stb_i),
.umie_ack_i (umie_ack_o),
.umie_tga_o (umie_tga_i),
.intr (intr),
.inta (inta),
.iid (iid)
);
zet_wb_master wb_master (
.clk (clk_i),
.rst (rst_i),
.umif_adr_i (16'b0),
.umif_dat_o (),
.umif_stb_i (1'b0),
.umif_by_i (1'b0),
.umif_ack_o (),
.umie_adr_i (umie_adr_i),
.umie_dat_o (umie_dat_o),
.umie_dat_i (umie_dat_i),
.umie_we_i (umie_we_i),
.umie_by_i (umie_by_i),
.umie_stb_i (umie_stb_i),
.umie_ack_o (umie_ack_o),
.umie_tga_i (umie_tga_i),
.wb_dat_i (wb_dat_i),
.wb_dat_o (wb_dat_o),
.wb_adr_o (wb_adr_o),
.wb_we_o (wb_we_o),
.wb_tga_o (wb_tga_o),
.wb_sel_o (wb_sel_o),
.wb_stb_o (wb_stb_o),
.wb_cyc_o (wb_cyc_o),
.wb_ack_i (wb_ack_i)
);
// Continuous assignments
assign pc = wbf_adr_o;
endmodule
|
module EP2C5(clk50M, key0, led0, led1, led2, MIDI_IN,
//VCA
a1, a2, a3, a4, ac1, ac2, ac3, ac4
);
//ports
input wire clk50M, key0, MIDI_IN;
output wire led0, led1, led2;
//генератор сброса
wire rst;
powerup_reset res_gen(.clk(clk50M), .key(~key0), .rst(rst));
//Organ outputs
//audio out's
output wire a1, a2, a3, a4;
//control out's
output wire ac1,ac2,ac3,ac4;
//synth
//MIDI вход
wire [3:0] CH_MESSAGE;
wire [3:0] CHAN;
wire [6:0] NOTE;
wire [6:0] LSB;
wire [6:0] MSB;
midi_in midi_in_0(.clk(clk50M),
.rst(rst),
.midi_in(MIDI_IN),
.chan(CHAN),
.ch_message(CH_MESSAGE),
.lsb(LSB),
.msb(MSB),
.note(NOTE));
//ловим ноту на любом, кроме 10-го барабанного канала
wire NOTE_ON = ((CH_MESSAGE==4'b1001)&&(CHAN!=4'd9)); //строб признак появления сообщения note on
wire NOTE_OFF = ((CH_MESSAGE==4'b1000)&&(CHAN!=4'd9)); //строб признак появления сообщения note off
reg note_on_reg;
initial note_on_reg <= 0;
/*
always @(posedge clk50M) begin
if (NOTE_ON) begin
note_on_reg <= 1;
end else if (NOTE_OFF) begin
note_on_reg <= 0;
end
end */
assign led0 = MIDI_IN;
assign led1 = ~note_on_reg;
assign led2 = 1'b1;
//523,31 герц А1
//50.000.000 / 523,31 = 95545,661271521660201410253960368
//frqdivmod #(.DIV(95546)) divider2(.clk(clk50M), .s_out(a1));
//12 клоков 2х частоты верхней октавы.
wire clk1, clk2, clk3, clk4, clk5, clk6, clk7, clk8, clk9, clk10, clk11, clk12;
frqdivmod #(.DIV(6327)) divider1(.clk(clk50M), .s_out(clk12));
frqdivmod #(.DIV(6704)) divider2(.clk(clk50M), .s_out(clk11));
frqdivmod #(.DIV(7102)) divider3(.clk(clk50M), .s_out(clk10));
frqdivmod #(.DIV(7525)) divider4(.clk(clk50M), .s_out(clk9));
frqdivmod #(.DIV(7972)) divider5(.clk(clk50M), .s_out(clk8));
frqdivmod #(.DIV(8446)) divider6(.clk(clk50M), .s_out(clk7));
frqdivmod #(.DIV(8948)) divider7(.clk(clk50M), .s_out(clk6));
frqdivmod #(.DIV(9480)) divider8(.clk(clk50M), .s_out(clk5));
frqdivmod #(.DIV(10044)) divider9(.clk(clk50M), .s_out(clk4));
frqdivmod #(.DIV(10641)) divider10(.clk(clk50M), .s_out(clk3));
frqdivmod #(.DIV(11274)) divider11(.clk(clk50M), .s_out(clk2));
frqdivmod #(.DIV(11945)) divider12(.clk(clk50M), .s_out(clk1));
assign clkout = clk50M;
//теперь буду тактовать счетчики по 11 бит каждый. каждый бит - след. октава вниз
reg [10:0] rg01;
reg [10:0] rg02;
reg [10:0] rg03;
reg [10:0] rg04;
reg [10:0] rg05;
reg [10:0] rg06;
reg [10:0] rg07;
reg [10:0] rg08;
reg [10:0] rg09;
reg [10:0] rg10;
reg [10:0] rg11;
reg [10:0] rg12;
initial rg01 <= 11'd0;
initial rg02 <= 11'd0;
initial rg03 <= 11'd0;
initial rg04 <= 11'd0;
initial rg05 <= 11'd0;
initial rg06 <= 11'd0;
initial rg07 <= 11'd0;
initial rg08 <= 11'd0;
initial rg09 <= 11'd0;
initial rg10 <= 11'd0;
initial rg11 <= 11'd0;
initial rg12 <= 11'd0;
reg trg01;
reg trg02;
reg trg03;
reg trg04;
reg trg05;
reg trg06;
reg trg07;
reg trg08;
reg trg09;
reg trg10;
reg trg11;
reg trg12;
initial trg01<=0;
initial trg02<=0;
initial trg03<=0;
initial trg04<=0;
initial trg05<=0;
initial trg06<=0;
initial trg07<=0;
initial trg08<=0;
initial trg09<=0;
initial trg10<=0;
initial trg11<=0;
initial trg12<=0;
always @ (posedge clk50M) begin
trg01 <= clk1;
if (clk1!=trg01) rg01 <= rg01 + 1'b1;
end
always @ (posedge clk50M) begin
trg02 <= clk2;
if (clk2!=trg02) rg02 <= rg02 + 1'b1;
end
always @ (posedge clk50M) begin
trg03 <= clk3;
if (clk3!=trg03) rg03 <= rg03 + 1'b1;
end
always @ (posedge clk50M) begin
trg04 <= clk4;
if (clk4!=trg04) rg04 <= rg04 + 1'b1;
end
always @ (posedge clk50M) begin
trg05 <= clk5;
if (clk5!=trg05) rg05 <= rg05 + 1'b1;
end
always @ (posedge clk50M) begin
trg06 <= clk6;
if (clk6!=trg06) rg06 <= rg06 + 1'b1;
end
always @ (posedge clk50M) begin
trg07 <= clk7;
if (clk7!=trg07) rg07 <= rg07 + 1'b1;
end
always @ (posedge clk50M) begin
trg08 <= clk8;
if (clk8!=trg08) rg08 <= rg08 + 1'b1;
end
always @ (posedge clk50M) begin
trg09 <= clk9;
if (clk9!=trg09) rg09 <= rg09 + 1'b1;
end
always @ (posedge clk50M) begin
trg10 <= clk10;
if (clk10!=trg10) rg10 <= rg10 + 1'b1;
end
always @ (posedge clk50M) begin
trg11 <= clk11;
if (clk11!=trg11) rg11 <= rg11 + 1'b1;
end
always @ (posedge clk50M) begin
trg12 <= clk12;
if (clk12!=trg12) rg12 <= rg12 + 1'b1;
end
//теперь надо сделать wire на 127 линий
wire [127:0] line16; //регистр 16! в понятиях органов!
genvar i;
generate
for(i = 0; i < 10; i = i + 1 ) begin : i_gen
assign line16[127 - (12*i) ] = rg12[i];
assign line16[126 - (12*i) ] = rg11[i];
assign line16[125 - (12*i) ] = rg10[i];
assign line16[124 - (12*i) ] = rg09[i];
assign line16[123 - (12*i) ] = rg08[i];
assign line16[122 - (12*i) ] = rg07[i];
assign line16[121 - (12*i) ] = rg06[i];
assign line16[120 - (12*i) ] = rg05[i];
assign line16[119 - (12*i) ] = rg04[i];
assign line16[118 - (12*i) ] = rg03[i];
assign line16[117 - (12*i) ] = rg02[i];
assign line16[116 - (12*i) ] = rg01[i];
end
endgenerate
//теперь надо сделать wire на 127 линий
wire [127:0] line8; //регистр 8! в понятиях органов!
generate
for(i = 0; i < 9; i = i + 1 ) begin : i8_gen
assign line8[127 - (12*(i+1)) ] = rg12[i];
assign line8[126 - (12*(i+1)) ] = rg11[i];
assign line8[125 - (12*(i+1)) ] = rg10[i];
assign line8[124 - (12*(i+1)) ] = rg09[i];
assign line8[123 - (12*(i+1)) ] = rg08[i];
assign line8[122 - (12*(i+1)) ] = rg07[i];
assign line8[121 - (12*(i+1)) ] = rg06[i];
assign line8[120 - (12*(i+1)) ] = rg05[i];
assign line8[119 - (12*(i+1)) ] = rg04[i];
assign line8[118 - (12*(i+1)) ] = rg03[i];
assign line8[117 - (12*(i+1)) ] = rg02[i];
assign line8[116 - (12*(i+1)) ] = rg01[i];
end
endgenerate
//теперь надо сделать wire на 127 линий
wire [127:0] line4; //регистр 4! в понятиях органов!
generate
for(i = 0; i < 8; i = i + 1 ) begin : i4_gen
assign line4[127 - (12*(i+2)) ] = rg12[i];
assign line4[126 - (12*(i+2)) ] = rg11[i];
assign line4[125 - (12*(i+2)) ] = rg10[i];
assign line4[124 - (12*(i+2)) ] = rg09[i];
assign line4[123 - (12*(i+2)) ] = rg08[i];
assign line4[122 - (12*(i+2)) ] = rg07[i];
assign line4[121 - (12*(i+2)) ] = rg06[i];
assign line4[120 - (12*(i+2)) ] = rg05[i];
assign line4[119 - (12*(i+2)) ] = rg04[i];
assign line4[118 - (12*(i+2)) ] = rg03[i];
assign line4[117 - (12*(i+2)) ] = rg02[i];
assign line4[116 - (12*(i+2)) ] = rg01[i];
end
endgenerate
//теперь надо сделать wire на 127 линий
wire [127:0] line2; //регистр 2! в понятиях органов!
generate
for(i = 0; i < 7; i = i + 1 ) begin : i2_gen
assign line2[127 - (12*(i+3)) ] = rg12[i];
assign line2[126 - (12*(i+3)) ] = rg11[i];
assign line2[125 - (12*(i+3)) ] = rg10[i];
assign line2[124 - (12*(i+3)) ] = rg09[i];
assign line2[123 - (12*(i+3)) ] = rg08[i];
assign line2[122 - (12*(i+3)) ] = rg07[i];
assign line2[121 - (12*(i+3)) ] = rg06[i];
assign line2[120 - (12*(i+3)) ] = rg05[i];
assign line2[119 - (12*(i+3)) ] = rg04[i];
assign line2[118 - (12*(i+3)) ] = rg03[i];
assign line2[117 - (12*(i+3)) ] = rg02[i];
assign line2[116 - (12*(i+3)) ] = rg01[i];
end
endgenerate
reg [127:0] keys; //регистр нажатых клавиш.
//будет использоваться, как маска
//теперь 127 линий пропускаем через маску
wire [127:0] line16_out; //регистр 16! в понятиях органов!
wire [127:0] line8_out; //регистр 8! в понятиях органов!
wire [127:0] line4_out; //регистр 4! в понятиях органов!
wire [127:0] line2_out; //регистр 4! в понятиях органов!
generate
for(i = 0; i < 128; i = i + 1 ) begin : ii_gen
assign line16_out[i] = line16[i] && keys[i];
assign line8_out[i] = line8[i] && keys[i];
assign line4_out[i] = line4[i] && keys[i];
assign line2_out[i] = line2[i] && keys[i];
end
endgenerate
//суммируем все линии в один выход (чума)
reg [7:0] line16_out_sum;
reg [7:0] line8_out_sum;
reg [7:0] line4_out_sum;
reg [7:0] line2_out_sum;
integer j;
always @(line16_out) begin
line16_out_sum = 8'd0;
for(j = 0; j < 128; j = j + 1 ) begin : j_gen
line16_out_sum = line16_out_sum + line16_out[j];
end
end
always @(line8_out) begin
line8_out_sum = 8'd0;
for(j = 0; j < 128; j = j + 1 ) begin : j1_gen
line8_out_sum = line8_out_sum + line8_out[j];
end
end
always @(line4_out) begin
line4_out_sum = 8'd0;
for(j = 0; j < 128; j = j + 1 ) begin : j2_gen
line4_out_sum = line4_out_sum + line4_out[j];
end
end
always @(line2_out) begin
line2_out_sum = 8'd0;
for(j = 0; j < 128; j = j + 1 ) begin : j3_gen
line2_out_sum = line2_out_sum + line2_out[j];
end
end
//4 ШИМ сигнала С1, С2, С3, С4
//общий для всех счетчик
reg [6:0] pwm_run;
initial pwm_run <= 7'd0;
always @(posedge clk50M) pwm_run <= pwm_run + 1'b1;
//счетчик для 8 битного ШИМ
reg [7:0] pwm2_run;
initial pwm2_run <= 8'd0;
always @(posedge clk50M) pwm2_run <= pwm2_run + 1'b1;
wire [7:0] result16;
wire [7:0] result8;
wire [7:0] result4;
wire [7:0] result2;
svca dca1(.in(line16_out_sum << 4), .cv({C1, 1'b0}), .signal_out(result16));
svca dca2(.in(line8_out_sum << 4), .cv({C2, 1'b0}), .signal_out(result8));
svca dca3(.in(line4_out_sum << 4), .cv({C3, 1'b0}), .signal_out(result4));
svca dca4(.in(line2_out_sum << 4), .cv({C4, 1'b0}), .signal_out(result2));
assign a1 = pwm2_run < result16;
assign a2 = pwm2_run < result8;
assign a3 = pwm2_run < result4;
assign a4 = pwm2_run < result2;
//данные возьму с контроллов, которые были назначены на ADSR, ибо мне лень.
//вот это надо как-то изящно упростить!
wire [6:0] C1;
wire C1_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd055))||rst; // control change & 55 control - LSB
wire [6:0] C1_value = (rst) ? 7'd00 : MSB;
reg7 C1_reg(clk50M, C1_lsb, C1_value, C1);
wire [6:0] C2;
wire C2_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd056))||rst; // control change & 56 control - LSB
wire [6:0] C2_value = (rst) ? 7'd00 : MSB;
reg7 C2_reg(clk50M, C2_lsb, C2_value, C2);
wire [6:0] C3;
wire C3_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd057))||rst; // control change & 57 control - LSB
wire [6:0] C3_value = (rst) ? 7'd00 : MSB;
reg7 C3_reg(clk50M, C3_lsb, C3_value, C3);
wire [6:0] C4;
wire C4_lsb = ((CH_MESSAGE==4'b1011)&&(LSB==7'd058))||rst; // control change & 58 control - LSB
wire [6:0] C4_value = (rst) ? 7'd00 : MSB;
reg7 C4_reg(clk50M, C4_lsb, C4_value, C4);
assign ac1 = (C1==7'd0) ? 1'b0 : pwm_run < C1;
assign ac2 = (C2==7'd0) ? 1'b0 : pwm_run < C2;
assign ac3 = (C3==7'd0) ? 1'b0 : pwm_run < C3;
assign ac4 = (C4==7'd0) ? 1'b0 : pwm_run < C4;
always @(posedge clk50M) begin
if (rst) begin
note_on_reg <= 1'b0;
keys <= 128'd0;
end else if (NOTE_ON) begin
note_on_reg <= 1'b1;
keys[NOTE] <= 1'b1;
end else if (NOTE_OFF) begin
note_on_reg <= 1'b0;
keys[NOTE] <= 1'b0;
end
end
endmodule
|
/**
* bsg_cache_non_blocking_stat_mem.v
*
* stat_mem and peripheral circuits
*
* @author tommy
*
*/
`include "bsg_defines.v"
module bsg_cache_non_blocking_stat_mem
import bsg_cache_non_blocking_pkg::*;
#(parameter `BSG_INV_PARAM(ways_p)
, parameter `BSG_INV_PARAM(sets_p)
, parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
, parameter stat_mem_pkt_width_lp=
`bsg_cache_non_blocking_stat_mem_pkt_width(ways_p,sets_p)
)
(
input clk_i
, input reset_i
, input v_i
, input [stat_mem_pkt_width_lp-1:0] stat_mem_pkt_i
, output logic [ways_p-1:0] dirty_o
, output logic [ways_p-2:0] lru_bits_o
);
// localparam
//
localparam stat_info_width_lp = `bsg_cache_non_blocking_stat_info_width(ways_p);
// stat_mem_pkt
//
`declare_bsg_cache_non_blocking_stat_mem_pkt_s(ways_p,sets_p);
bsg_cache_non_blocking_stat_mem_pkt_s stat_mem_pkt;
assign stat_mem_pkt = stat_mem_pkt_i;
// stat_mem
//
`declare_bsg_cache_non_blocking_stat_info_s(ways_p);
bsg_cache_non_blocking_stat_info_s data_li, data_lo, mask_li;
logic w_li;
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(stat_info_width_lp)
,.els_p(sets_p)
,.latch_last_read_p(1)
) stat_mem (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.w_i(w_li)
,.addr_i(stat_mem_pkt.index)
,.w_mask_i(mask_li)
,.data_i(data_li)
,.data_o(data_lo)
);
// input logic
//
logic [ways_p-1:0] way_decode_lo;
bsg_decode #(
.num_out_p(ways_p)
) way_demux (
.i(stat_mem_pkt.way_id)
,.o(way_decode_lo)
);
logic [ways_p-2:0] lru_decode_data_lo;
logic [ways_p-2:0] lru_decode_mask_lo;
bsg_lru_pseudo_tree_decode #(
.ways_p(ways_p)
) lru_decode (
.way_id_i(stat_mem_pkt.way_id)
,.data_o(lru_decode_data_lo)
,.mask_o(lru_decode_mask_lo)
);
always_comb begin
w_li = 1'b0;
data_li.lru_bits = '0;
mask_li.lru_bits = '0;
data_li.dirty = '0;
mask_li.dirty = '0;
case (stat_mem_pkt.opcode)
// read the stat_mem.
e_stat_read: begin
w_li = 1'b0;
data_li.lru_bits = '0;
mask_li.lru_bits = '0;
data_li.dirty = '0;
mask_li.dirty = '0;
end
// clear dirty bit for the block, chosen by index and way_id.
e_stat_clear_dirty: begin
w_li = 1'b1;
data_li.lru_bits = '0;
mask_li.lru_bits = '0;
data_li.dirty = '0;
mask_li.dirty = way_decode_lo;
end
// set LRU so that the chosen block is not LRU.
e_stat_set_lru: begin
w_li = 1'b1;
data_li.lru_bits = lru_decode_data_lo;
mask_li.lru_bits = lru_decode_mask_lo;
data_li.dirty = '0;
mask_li.dirty = '0;
end
// set LRU so that the chosen block is not LRU.
// Also, set the dirty bit.
e_stat_set_lru_and_dirty: begin
w_li = 1'b1;
data_li.lru_bits = lru_decode_data_lo;
mask_li.lru_bits = lru_decode_mask_lo;
data_li.dirty = {ways_p{1'b1}};
mask_li.dirty = way_decode_lo;
end
// set LRU so that the chosen block is not LRU.
// Also, clear the dirty bit.
e_stat_set_lru_and_clear_dirty: begin
w_li = 1'b1;
data_li.lru_bits = lru_decode_data_lo;
mask_li.lru_bits = lru_decode_mask_lo;
data_li.dirty = {ways_p{1'b0}};
mask_li.dirty = way_decode_lo;
end
// resets the LRU to zero, and clear the dirty bits of chosen way.
e_stat_reset: begin
w_li = 1'b1;
data_li.lru_bits = '0;
mask_li.lru_bits = {(ways_p-1){1'b1}};
data_li.dirty = '0;
mask_li.dirty = way_decode_lo;
end
default: begin
// this should never be used.
end
endcase
end
// output logic
//
assign lru_bits_o = data_lo.lru_bits;
assign dirty_o = data_lo.dirty;
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_non_blocking_stat_mem)
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.v
// Design : system_ov7670_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_0_0(clk_x2, active, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_x2,active,data[7:0],rgb[15:0]" */;
input clk_x2;
input active;
input [7:0]data;
output [15:0]rgb;
endmodule
|
module IMUL
(
input wire [3:0] A,
input wire [3:0] B,
output reg [7:0] out
);
reg rC1, rC2, rC3; //registros para los llevos
reg [2:0] rT1, rT2; //registros temporales
always @ (*) begin
//R0
out[0] =A[0] & B[0];
//R1
{rC1, out[1]} = (A[0] & B[1]) + (A[1] & B[0]);
//R2
{rC1, rT1[0]} = (A[2] & B[0]) + (A[1] & B[1]) + rC1;
{rC2, out[2]} = (A[0] & B[2]) + rT1[0];
//R3
{rC1, rT1[1]} = (A[3] & B[0]) + (A[2] & B[1]) + rC1;
{rC2, rT2[0]} = (A[1] & B[2]) + rT1[1] + rC2;
{rC3, out[3]} = (A[0] & B[3]) + rT2[0];
//R4
{rC1, rT1[2]} = (A[3] & B[1]) + rC1;
{rC2, rT2[1]} = (A[2] & B[2]) + rT1[2] + rC2;
{rC3, out[4]} = (A[1] & B[3]) + rT2[1] + rC3;
//R5
{rC2, rT2[2]} = (A[3] & B[2]) + rC2 + rC1;
{rC3, out[5]} = (A[2] & B[3]) + rT2[2] + rC3;
//R6 y R7.
{out[7], out[6]} = (A[3] & B[3]) + rC2 + rC3;
end
endmodule
module testbench;
wire [7:0] Q;
reg [3:0] a,b;
IMUL im(a,b,Q);
initial begin
$dumpfile("imul.vcd");
$dumpvars;
a = 4'hF;
b = 4'h2;
#20;
a = 4'hA;
b = 4'h5;
#20;
a = 4'hB;
b = 4'hC;
#20 $finish;
end
endmodule |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module start_for_Mat2AXIvdy_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module start_for_Mat2AXIvdy (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd1;
parameter ADDR_WIDTH = 32'd3;
parameter DEPTH = 32'd6;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
wire shiftReg_ce;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr - 1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr + 1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH - 2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
start_for_Mat2AXIvdy_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_start_for_Mat2AXIvdy_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:20:36 06/16/2014
// Design Name:
// Module Name: washing_machine
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module washing_machine(
input clk,
input power_button,
input pause_button,
input mode_button,
input stage_button,
output reg power_led,
output pause_led,
output [2:0] wash_led,
output warning_led,
output reg [3:0] an,
output reg [7:0] ag
);
reg [3:0] stage_led;
reg [4:0] time_led;
reg [2:0] blink;
reg [2:0] mode_save;
reg [2:0] wash_temp;
reg [4:0] time_limit;
reg [2:0] wash_limit;
reg [2:0] blink_limit;
reg [4:0] shutdown_count;
reg wash_done;
reg shutdown_start;
reg shutdown;
reg done_led;
reg [25:0] ns_timer;
reg real_clk;
reg [15:0] an_timer;
reg [4:0] ag_helper;
reg pause_save;
wire power_pulse;
wire pause_pulse;
wire timer_pulse;
initial
begin
stage_led = 4'b0110;
time_led = 5'b11011;
mode_save = 3'b000;
power_led = 0;
pause_save = 1;
wash_temp = 3'b000;
blink = 3'b000;
time_limit = 5'b11011;
time_led = 5'b11011;
wash_limit = 3'b111;
wash_temp = 3'b111;
blink_limit = 3'b011;
blink = 3'b011;
wash_done = 1'b0;
shutdown_count = 5'b00000;
shutdown_start = 1'b0;
shutdown = 1'b0;
done_led = 1'b0;
ns_timer = 0;
real_clk = 1'b1;
an_timer = 0;
ag = 8'b11111111;
end
always @(posedge clk)
begin
ns_timer = ns_timer+1'b1;
if (ns_timer == 50000000)
begin
ns_timer = 0;
end
if (ns_timer < 25000000)
begin
real_clk = 1'b1;
end
else
begin
real_clk = 1'b0;
end
end
always @(posedge clk)
begin
if (power_led)
begin
an_timer = an_timer+1'b1;
if (an_timer == 50000)
begin
an_timer = 0;
end
if (an_timer < 12500)
begin
an = 4'b0111;
case (stage_led)
4'b0100 : ag = 8'b10011001;
4'b0101 : ag = 8'b01001001;
4'b0110 : ag = 8'b01000001;
4'b0111 : ag = 8'b00011111;
4'b1000 : ag = 8'b00000001;
endcase
end
else if (an_timer < 25000)
begin
an = 4'b1011;
case (mode_save)
3'b000 : ag = 8'b00000011;
3'b001 : ag = 8'b10011111;
3'b010 : ag = 8'b00100101;
3'b011 : ag = 8'b00001101;
3'b100 : ag = 8'b10011001;
3'b101 : ag = 8'b01001001;
endcase
end
else if (an_timer < 37500)
begin
an = 4'b1101;
if (time_led > 19)
begin
ag = 8'b00100101;
end
else if (time_led > 9)
begin
ag = 8'b10011111;
end
else
begin
ag = 8'b11111111;
end
end
else
begin
an = 4'b1110;
if (time_led > 19)
begin
ag_helper = time_led-20;
end
else if (time_led > 9)
begin
ag_helper = time_led-10;
end
else
begin
ag_helper = time_led;
end
case (ag_helper)
5'b00000 : ag = 8'b00000011;
5'b00001 : ag = 8'b10011111;
5'b00010 : ag = 8'b00100101;
5'b00011 : ag = 8'b00001101;
5'b00100 : ag = 8'b10011001;
5'b00101 : ag = 8'b01001001;
5'b00110 : ag = 8'b01000001;
5'b00111 : ag = 8'b00011111;
5'b01000 : ag = 8'b00000001;
5'b01001 : ag = 8'b00001001;
endcase
end
end
else
begin
ag = 8'b11111111;
end
end
always @(posedge power_pulse)
begin
power_led = ~power_led;
end
always @(posedge pause_pulse or posedge power_button)
begin
if (power_button)
begin
pause_save = 1'b1;
end
else
begin
pause_save = ~pause_save;
end
end
always @(posedge pause_button or posedge wash_done or posedge power_button)
begin
if (power_button)
begin
shutdown_start = 1'b0;
end
else if (wash_done)
begin
if (pause_save)
begin
shutdown_start = 1'b1;
end
end
else
begin
if (pause_save)
begin
shutdown_start = 1'b0;
end
end
end
always @(posedge real_clk)
begin
shutdown = 1'b0;
done_led = 1'b0;
if (shutdown_start == 1'b1 && shutdown_count == 5'b01010)
begin
shutdown = 1'b1;
end
if (shutdown_start == 1'b1 && shutdown_count < 5'b00010)
begin
done_led = 1'b1;
end
end
always @(posedge real_clk or posedge wash_done)
begin
if (wash_done)
begin
shutdown_count = 5'b00000;
end
else
begin
if (shutdown_start && power_led && pause_save)
begin
shutdown_count = shutdown_count+1'b1;
if (shutdown_count == 5'b01011)
begin
shutdown_count = 5'b00000;
end
end
end
end
always @(posedge stage_button or posedge power_button)
begin
if (power_button)
begin
stage_led = 4'b0110;
end
else
begin
if (power_led && pause_save)
begin
stage_led = stage_led+1;
if (stage_led == 4'b1001)
begin
stage_led = 4'b0100;
end
end
end
end
always @(posedge mode_button or posedge wash_done or posedge power_button)
begin
if (power_button)
begin
mode_save = 3'b000;
end
else if (wash_done)
begin
mode_save = 3'b000;
end
else
begin
if (power_led && pause_save)
begin
mode_save = mode_save+1'b1;
if (mode_save == 3'b110)
begin
mode_save = 3'b000;
end
end
end
end
always @(mode_save)
begin
case (mode_save)
3'b000 : begin
time_limit = 5'b11011;
wash_limit = 3'b111;
blink_limit = 3'b011;
end
3'b001 : begin
time_limit = 5'b01100;
wash_limit = 3'b100;
blink_limit = 3'b000;
end
3'b010 : begin
time_limit = 5'b11000;
wash_limit = 3'b110;
blink_limit = 3'b010;
end
3'b011 : begin
time_limit = 5'b01100;
wash_limit = 3'b010;
blink_limit = 3'b000;
end
3'b100 : begin
time_limit = 5'b01111;
wash_limit = 3'b011;
blink_limit = 3'b001;
end
3'b101 : begin
time_limit = 5'b00011;
wash_limit = 3'b001;
blink_limit = 3'b000;
end
endcase
end
always @(posedge real_clk)
begin
wash_done = 1'b0;
if (time_led == 0)
begin
wash_done = 1'b1;
end
end
always @(posedge real_clk or posedge mode_button or posedge power_button)
begin
if (power_button)
begin
time_led = 5'b11011;
end
else if (mode_button)
begin
if (power_led && pause_save)
begin
time_led = time_limit;
end
end
else
begin
if (power_led && ~pause_save)
begin
if (time_led > 0)
begin
time_led = time_led-1'b1;
end
else
begin
time_led = 5'b11011;
end
end
end
end
always @(time_led)
begin
case (mode_save)
3'b000 : begin
if (time_led > 5'b01111)
begin
wash_temp = 3'b111;
blink = 3'b011;
end
else if (time_led > 5'b00011)
begin
wash_temp = 3'b011;
blink = 3'b001;
end
else if (time_led > 5'b00000)
begin
wash_temp = 3'b001;
blink = 3'b000;
end
else
begin
wash_temp = 3'b000;
blink = 3'b000;
end
end
3'b001 : begin
if (time_led > 5'b00000)
begin
wash_temp = 3'b100;
blink = 3'b000;
end
else
begin
wash_temp = 3'b000;
blink = 3'b000;
end
end
3'b010 : begin
if (time_led > 5'b01100)
begin
wash_temp = 3'b110;
blink = 3'b010;
end
else if (time_led > 5'b00000)
begin
wash_temp = 3'b010;
blink = 3'b000;
end
else
begin
wash_temp = 3'b000;
blink = 3'b000;
end
end
3'b011 : begin
if (time_led > 5'b00000)
begin
wash_temp = 3'b010;
blink = 3'b000;
end
else
begin
wash_temp = 3'b000;
blink = 3'b000;
end
end
3'b100 : begin
if (time_led > 5'b00011)
begin
wash_temp = 3'b011;
blink = 3'b001;
end
else if (time_led > 5'b00000)
begin
wash_temp = 3'b001;
blink = 3'b000;
end
else
begin
wash_temp = 3'b000;
blink = 3'b000;
end
end
3'b101 : begin
if (time_led > 5'b00000)
begin
wash_temp = 3'b001;
blink = 3'b000;
end
else
begin
wash_temp = 3'b000;
blink = 3'b000;
end
end
endcase
end
assign wash_led = ((wash_temp & {real_clk | pause_led, real_clk | pause_led, real_clk | pause_led}) | blink) & {power_led, power_led, power_led};
assign warning_led = ((done_led & real_clk) | power_button | pause_button | stage_button | mode_button) & power_led;
assign pause_led = pause_save & power_led;
assign power_pulse = power_button | shutdown;
assign pause_pulse = pause_button | wash_done;
assign timer_pulse = real_clk | mode_button;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211OI_SYMBOL_V
`define SKY130_FD_SC_HS__A211OI_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211OI_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: mb2cpx.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/***************************************************************************
* mb2cpx.v: An interface file to connect the CPX interface of the SPARC
* core with the MicroBlaze FSL FIFO. This is for data moving
* from the MicroBlaze core I/O subsystem to the SPARC core.
* The MicroBlaze core will be simulating an L2 Cache and
* memory/I/O subsystem, and returning simulated cache packets
* back to the SPARC core.
*
* $Id: mb2cpx.v,v 1.1 2007/06/30 00:23:39 tt147840 Exp $
***************************************************************************/
// Global header file includes
// Local header file includes
`include "ccx2mb.h"
module mb2cpx (
// Outputs
cpx_spc_data_rdy_cx2,
cpx_spc_data_cx2,
cpx_fsl_s_read,
// Inputs
rclk,
reset_l,
fsl_cpx_s_exists,
fsl_cpx_s_control,
fsl_cpx_s_data
);
parameter CPX_GEAR_RATIO = (((`CPX_WIDTH+1-1)/`FSL_D_WIDTH)+1);
parameter CPX_FSL_EXTRA_BITS = (`FSL_D_WIDTH * CPX_GEAR_RATIO) -
(`CPX_WIDTH+1);
//=============================================
// Outputs
// SPARC/CPX interface
output cpx_spc_data_rdy_cx2;
output [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
// MicroBlaze FSL Interface
output cpx_fsl_s_read;
//=============================================
// Inputs
input rclk;
input reset_l;
// MicroBlaze FSL Interface
input fsl_cpx_s_exists;
input fsl_cpx_s_control;
input [`FSL_D_WIDTH-1:0] fsl_cpx_s_data;
//=============================================
// Wire definitions for outputs
// SPARC/CPX interface
wire cpx_spc_data_rdy_cx2;
wire [`CPX_WIDTH-1:0] cpx_spc_data_cx2;
// MicroBlaze FSL Interface
wire cpx_fsl_s_read;
wire atomic_txn;
wire cpx_shift_out;
reg [CPX_GEAR_RATIO*`FSL_D_WIDTH-1:0] fsl_input_reg;
reg [`CPX_WIDTH-1:0] cpx_output_reg;
// Atomic transaction indicator is MSB of the first packet
assign atomic_txn = fsl_cpx_s_data[`FSL_D_WIDTH-CPX_FSL_EXTRA_BITS-1];
// Input Shift Register: Shift 32-bit chunks into wider shift register
always @(posedge rclk) begin
fsl_input_reg <= (fsl_cpx_s_exists && cpx_fsl_s_read) ?
{fsl_input_reg[(CPX_GEAR_RATIO -1)*`FSL_D_WIDTH-1:0],
fsl_cpx_s_data} :
fsl_input_reg;
end
// Output register
always @(posedge rclk) begin
cpx_output_reg <= cpx_shift_out ? fsl_input_reg[`CPX_WIDTH-1:0] :
cpx_output_reg;
end
assign cpx_spc_data_cx2 = cpx_spc_data_rdy_cx2 ? cpx_output_reg : {`CPX_WIDTH{1'b0}};
//=============================================
// State Machine Instance
mb2cpx_sm cpx_sm (
// Outputs
.cpx_fsl_s_read(cpx_fsl_s_read),
.cpx_shift_out(cpx_shift_out),
.cpx_spc_data_rdy_cx2(cpx_spc_data_rdy_cx2),
// Inputs
.rclk(rclk),
.reset_l(reset_l),
.fsl_cpx_s_exists(fsl_cpx_s_exists),
.fsl_cpx_s_control(fsl_cpx_s_control),
.atomic_txn(atomic_txn)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A41OI_1_V
`define SKY130_FD_SC_MS__A41OI_1_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a41oi_1 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A41OI_1_V
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: [email protected]
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module asram16_if
(
// General
clk_i,
rst_i,
timing_ctrl_i,
// Asynchronous SRAM interface
sram_address_o,
sram_data_o,
sram_data_i,
sram_oe_o,
sram_cs_o,
sram_be_o,
sram_we_o,
sram_dir_out_o,
// Internal access
address_i,
data_i,
data_o,
rd_i,
wr_i,
ack_o,
busy_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter [31:0] EXT_ADDR_WIDTH = 17;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input [(32 - 1):0] timing_ctrl_i /*verilator public*/;
output [(EXT_ADDR_WIDTH - 1):0] sram_address_o /*verilator public*/;
output [(16 - 1):0] sram_data_o /*verilator public*/;
input [(16 - 1):0] sram_data_i /*verilator public*/;
output sram_oe_o /*verilator public*/;
output sram_cs_o /*verilator public*/;
output [(2 - 1):0] sram_be_o /*verilator public*/;
output sram_we_o /*verilator public*/;
output sram_dir_out_o /*verilator public*/;
input [(32 - 1):0] address_i /*verilator public*/;
input [(32 - 1):0] data_i /*verilator public*/;
output [(32 - 1):0] data_o /*verilator public*/;
input rd_i /*verilator public*/;
input [(4 - 1):0] wr_i /*verilator public*/;
output ack_o /*verilator public*/;
output busy_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
// State Machine status
reg [3:0] reg_state;
parameter MEM_IDLE = 4'd0;
parameter MEM_WRITE_DATA1 = 4'd1;
parameter MEM_WRITE_SETUP2 = 4'd2;
parameter MEM_WRITE_DATA2 = 4'd3;
parameter MEM_READ_DATA1 = 4'd4;
parameter MEM_READ_DATA2 = 4'd5;
parameter MEM_READ_WAIT1 = 4'd6;
parameter MEM_READ_WAIT2 = 4'd7;
parameter MEM_WRITE_WAIT1 = 4'd8;
parameter MEM_WRITE_WAIT2 = 4'd9;
parameter MEM_WRITE_HOLD = 4'd10;
reg [(EXT_ADDR_WIDTH - 1):0] v_reg_address;
reg [(EXT_ADDR_WIDTH - 1):0] reg_address;
reg [(32 - 1):0] reg_data_o;
reg [(32 - 1):0] reg_data_i;
reg [(4 - 1):0] reg_wr;
reg [3:0] reg_wait;
reg [(EXT_ADDR_WIDTH - 1):0] sram_address_o;
reg [(16 - 1):0] sram_data_o;
reg sram_oe_o;
wire sram_cs_o;
reg [(2 - 1):0] sram_be_o;
reg sram_we_o;
reg sram_dir_out_o;
wire [(32 - 1):0] data_o;
reg ack_o;
wire busy_o;
//-----------------------------------------------------------------
// Implementation
//-----------------------------------------------------------------
always @ (posedge clk_i or posedge rst_i )
begin
if (rst_i == 1'b1)
begin
sram_oe_o <= 1'b1;
sram_we_o <= 1'b1;
sram_address_o <= {(EXT_ADDR_WIDTH - 0){1'b0}};
sram_data_o <= 16'h0000;
sram_be_o <= 2'b11;
sram_dir_out_o <= 1'b1;
ack_o <= 1'b0;
reg_address <= {(EXT_ADDR_WIDTH - 0){1'b0}};
reg_data_o <= 32'h00000000;
reg_data_i <= 32'h00000000;
reg_wr <= 4'b0000;
reg_wait <= 4'b0000;
reg_state <= MEM_IDLE;
end
else
begin
ack_o <= 1'b0;
case (reg_state)
//-------------------------------
// MEM_IDLE
//-------------------------------
MEM_IDLE :
begin
// Convert to word address
v_reg_address = address_i[EXT_ADDR_WIDTH:1];
// Write operation
if (wr_i != 4'b0000)
begin
// Store operation details
reg_address <= v_reg_address;
reg_data_o <= data_i;
reg_data_i <= 32'h00000000;
reg_wr <= wr_i;
sram_dir_out_o <= 1'b1;
// Write upper word and possibly the lower word
if (wr_i[3:2] != 2'b00)
begin
// Start first cycle
sram_address_o <= v_reg_address;
sram_data_o <= data_i[31:16];
sram_be_o <= ~wr_i[3:2];
sram_we_o <= 1'b0;
// Write wait states? (WRITE_WAIT_CYCLES)
if (timing_ctrl_i[3:0] != 4'b0000)
begin
reg_wait <= timing_ctrl_i[3:0];
reg_state <= MEM_WRITE_WAIT1;
end
// No wait states for WRITEs
else
reg_state <= MEM_WRITE_DATA1;
end
// Write lower word only
else
begin
// Start last cycle
sram_address_o <= (v_reg_address + 1);
sram_data_o <= data_i[15:0];
sram_be_o <= ~wr_i[1:0];
sram_we_o <= 1'b0;
// Write wait states? (WRITE_WAIT_CYCLES)
if (timing_ctrl_i[3:0] != 4'b0000)
begin
reg_wait <= timing_ctrl_i[3:0];
reg_state <= MEM_WRITE_WAIT2;
end
// No wait states for WRITEs
else
reg_state <= MEM_WRITE_DATA2;
end
end
// Read operation
else if (rd_i == 1'b1)
begin
// Store operation details
reg_address <= v_reg_address;
reg_data_o <= 32'h00000000;
reg_data_i <= 32'h00000000;
reg_wr <= 4'b0000;
// Start first cycle
sram_address_o <= v_reg_address;
sram_data_o <= 16'h0000;
sram_be_o <= 2'b00;
sram_we_o <= 1'b1;
sram_oe_o <= 1'b0;
sram_dir_out_o <= 1'b0;
// Read wait states? (READ_WAIT_CYCLES)
if (timing_ctrl_i[7:4] != 4'b0000)
begin
reg_wait <= timing_ctrl_i[7:4];
reg_state <= MEM_READ_WAIT1;
end
// No wait states for READs
else
reg_state <= MEM_READ_DATA1;
end
// No operation
else
begin
sram_dir_out_o <= 1'b1;
reg_state <= MEM_IDLE;
end
end
//-------------------------------
// MEM_WRITE_DATA1
//-------------------------------
MEM_WRITE_DATA1 :
begin
// Perform write
sram_we_o <= 1'b1;
// Next Address
reg_address <= (reg_address + 1);
// Write to lower word?
if (reg_wr[1:0]!=2'b00)
begin
// Write hold states? (WRITE_HOLD_CYCLES)
if (timing_ctrl_i[11:8] != 4'b0000)
begin
reg_wait <= timing_ctrl_i[11:8];
reg_state <= MEM_WRITE_HOLD;
end
// No wait states for WRITEs
else
reg_state <= MEM_WRITE_SETUP2;
end
else
begin
// Done!
reg_state <= MEM_IDLE;
ack_o <= 1'b1;
end
end
//-------------------------------
// MEM_WRITE_SETUP2
//-------------------------------
MEM_WRITE_SETUP2 :
begin
// Setup write for lower word
sram_address_o <= reg_address;
sram_be_o <= ~reg_wr[1:0];
sram_data_o <= reg_data_o[15:0];
sram_we_o <= 1'b0;
// Write wait states? (WRITE_WAIT_CYCLES)
if (timing_ctrl_i[3:0] != 4'b0000)
begin
reg_wait <= timing_ctrl_i[3:0];
reg_state <= MEM_WRITE_WAIT2;
end
// No wait states for WRITEs
else
reg_state <= MEM_WRITE_DATA2;
end
//-------------------------------
// MEM_WRITE_DATA2
//-------------------------------
MEM_WRITE_DATA2 :
begin
// Perform write
sram_we_o <= 1'b1;
// Done!
reg_state <= MEM_IDLE;
ack_o <= 1'b1;
end
//-------------------------------
// MEM_READ_DATA1
//-------------------------------
MEM_READ_DATA1 :
begin
// Keep OE low during multi-cycle read
sram_oe_o <= 1'b0;
// Load upper word
reg_data_i <= {sram_data_i[15:0],16'h0000};
// Next Address
v_reg_address = (reg_address + 1);
// Output next address
sram_address_o <= v_reg_address[(EXT_ADDR_WIDTH - 1):0];
reg_address <= v_reg_address;
// Read wait states? (READ_WAIT_CYCLES)
if (timing_ctrl_i[7:4] != 4'b0000)
begin
reg_wait <= timing_ctrl_i[7:4];
reg_state <= MEM_READ_WAIT2;
end
// No wait states for READs
else
reg_state <= MEM_READ_DATA2;
end
//-------------------------------
// MEM_READ_DATA2
//-------------------------------
MEM_READ_DATA2 :
begin
// Load lower word
reg_data_i <= {reg_data_i[31:16],sram_data_i[15:0]};
// Deselect RAM
sram_oe_o <= 1'b1;
// Done!
ack_o <= 1'b1;
reg_state <= MEM_IDLE;
end
//-------------------------------
// MEM_READ_WAIT1
//-------------------------------
MEM_READ_WAIT1 :
begin
// Decrement wait state counter
reg_wait <= reg_wait - 1;
// Wait expired?
if (reg_wait == 4'b0001)
begin
reg_state <= MEM_READ_DATA1;
end
end
//-------------------------------
// MEM_READ_WAIT2
//-------------------------------
MEM_READ_WAIT2 :
begin
// Decrement wait state counter
reg_wait <= reg_wait - 1;
// Wait expired?
if (reg_wait == 4'b0001)
begin
reg_state <= MEM_READ_DATA2;
end
end
//-------------------------------
// MEM_WRITE_WAIT1
//-------------------------------
MEM_WRITE_WAIT1 :
begin
// Decrement wait state counter
reg_wait <= reg_wait - 1;
// Wait expired?
if (reg_wait == 4'b0001)
begin
reg_state <= MEM_WRITE_DATA1;
end
end
//-------------------------------
// MEM_WRITE_WAIT2
//-------------------------------
MEM_WRITE_WAIT2 :
begin
// Decrement wait state counter
reg_wait <= reg_wait - 1;
// Wait expired?
if (reg_wait == 4'b0001)
begin
reg_state <= MEM_WRITE_DATA2;
end
end
//-------------------------------
// MEM_WRITE_HOLD
//-------------------------------
MEM_WRITE_HOLD :
begin
// Decrement wait state counter
reg_wait <= reg_wait - 1;
// Wait expired?
if (reg_wait == 4'b0001)
begin
reg_state <= MEM_WRITE_SETUP2;
end
end
default :
reg_state <= MEM_IDLE;
endcase
end
end
//-----------------------------------------------
// Combinatorial
//-----------------------------------------------
assign data_o = reg_data_i;
assign busy_o = (reg_state != MEM_IDLE) ? 1'b1 : 1'b0;
assign sram_cs_o = 1'b0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O221A_TB_V
`define SKY130_FD_SC_LP__O221A_TB_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o221a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__o221a dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O221A_TB_V
|
`default_nettype none
module reservation_search16to2(
input wire iINFO0,
input wire iINFO1,
input wire iINFO2,
input wire iINFO3,
input wire iINFO4,
input wire iINFO5,
input wire iINFO6,
input wire iINFO7,
input wire iINFO8,
input wire iINFO9,
input wire iINFO10,
input wire iINFO11,
input wire iINFO12,
input wire iINFO13,
input wire iINFO14,
input wire iINFO15,
output wire oPICKUP_0_VALID,
output wire [3:0] oPICLUP_0_NUM,
output wire oPICKUP_1_VALID,
output wire [3:0] oPICLUP_1_NUM
);
//Reservation Station Entry Search(16Entry | 2Picup)
function [9:0] func_rb_entry_search16to2;
/* Output Signal
[9] : Entry 1 Valid
[8:5] : Entry 1 Table Numver
[4] : Entry 0 Valid
[3:0] : Entry 0 Table Number
*/
input func_rb_entry_search16to2_entry_valid0;
input func_rb_entry_search16to2_entry_valid1;
input func_rb_entry_search16to2_entry_valid2;
input func_rb_entry_search16to2_entry_valid3;
input func_rb_entry_search16to2_entry_valid4;
input func_rb_entry_search16to2_entry_valid5;
input func_rb_entry_search16to2_entry_valid6;
input func_rb_entry_search16to2_entry_valid7;
input func_rb_entry_search16to2_entry_valid8;
input func_rb_entry_search16to2_entry_valid9;
input func_rb_entry_search16to2_entry_valid10;
input func_rb_entry_search16to2_entry_valid11;
input func_rb_entry_search16to2_entry_valid12;
input func_rb_entry_search16to2_entry_valid13;
input func_rb_entry_search16to2_entry_valid14;
input func_rb_entry_search16to2_entry_valid15;
reg func_rb_entry_search16to2_tournament_data0_valid0;
reg [3:0] func_rb_entry_search16to2_tournament_data0_num0;
reg func_rb_entry_search16to2_tournament_data0_valid1;
reg [3:0] func_rb_entry_search16to2_tournament_data0_num1;
reg func_rb_entry_search16to2_tournament_data1_valid0[0:1];
reg [3:0] func_rb_entry_search16to2_tournament_data1_num0[0:1];
reg func_rb_entry_search16to2_tournament_data1_valid1[0:1];
reg [3:0] func_rb_entry_search16to2_tournament_data1_num1[0:1];
reg func_rb_entry_search16to2_tournament_data2_valid0[0:3];
reg [3:0] func_rb_entry_search16to2_tournament_data2_num0[0:3];
reg func_rb_entry_search16to2_tournament_data2_valid1[0:3];
reg [3:0] func_rb_entry_search16to2_tournament_data2_num1[0:3];
reg func_rb_entry_search16to2_tournament_data3_valid0[0:7];
reg [3:0] func_rb_entry_search16to2_tournament_data3_num0[0:7];
reg func_rb_entry_search16to2_tournament_data3_valid1[0:7];
reg [3:0] func_rb_entry_search16to2_tournament_data3_num1[0:7];
begin
//3
func_rb_entry_search16to2_tournament_data3_valid0[0] = func_rb_entry_search16to2_entry_valid0;
func_rb_entry_search16to2_tournament_data3_num0[0] = 4'h0;
func_rb_entry_search16to2_tournament_data3_valid1[0] = func_rb_entry_search16to2_entry_valid1;
func_rb_entry_search16to2_tournament_data3_num1[0] = 4'h1;
func_rb_entry_search16to2_tournament_data3_valid0[1] = func_rb_entry_search16to2_entry_valid2;
func_rb_entry_search16to2_tournament_data3_num0[1] = 4'h2;
func_rb_entry_search16to2_tournament_data3_valid1[1] = func_rb_entry_search16to2_entry_valid3;
func_rb_entry_search16to2_tournament_data3_num1[1] = 4'h3;
func_rb_entry_search16to2_tournament_data3_valid0[2] = func_rb_entry_search16to2_entry_valid4;
func_rb_entry_search16to2_tournament_data3_num0[2] = 4'h4;
func_rb_entry_search16to2_tournament_data3_valid1[2] = func_rb_entry_search16to2_entry_valid5;
func_rb_entry_search16to2_tournament_data3_num1[2] = 4'h5;
func_rb_entry_search16to2_tournament_data3_valid0[3] = func_rb_entry_search16to2_entry_valid6;
func_rb_entry_search16to2_tournament_data3_num0[3] = 4'h6;
func_rb_entry_search16to2_tournament_data3_valid1[3] = func_rb_entry_search16to2_entry_valid7;
func_rb_entry_search16to2_tournament_data3_num1[3] = 4'h7;
func_rb_entry_search16to2_tournament_data3_valid0[4] = func_rb_entry_search16to2_entry_valid8;
func_rb_entry_search16to2_tournament_data3_num0[4] = 4'h8;
func_rb_entry_search16to2_tournament_data3_valid1[4] = func_rb_entry_search16to2_entry_valid9;
func_rb_entry_search16to2_tournament_data3_num1[4] = 4'h9;
func_rb_entry_search16to2_tournament_data3_valid0[5] = func_rb_entry_search16to2_entry_valid10;
func_rb_entry_search16to2_tournament_data3_num0[5] = 4'hA;
func_rb_entry_search16to2_tournament_data3_valid1[5] = func_rb_entry_search16to2_entry_valid11;
func_rb_entry_search16to2_tournament_data3_num1[5] = 4'hB;
func_rb_entry_search16to2_tournament_data3_valid0[6] = func_rb_entry_search16to2_entry_valid12;
func_rb_entry_search16to2_tournament_data3_num0[6] = 4'hC;
func_rb_entry_search16to2_tournament_data3_valid1[6] = func_rb_entry_search16to2_entry_valid13;
func_rb_entry_search16to2_tournament_data3_num1[6] = 4'hD;
func_rb_entry_search16to2_tournament_data3_valid0[7] = func_rb_entry_search16to2_entry_valid14;
func_rb_entry_search16to2_tournament_data3_num0[7] = 4'hE;
func_rb_entry_search16to2_tournament_data3_valid1[7] = func_rb_entry_search16to2_entry_valid15;
func_rb_entry_search16to2_tournament_data3_num1[7] = 4'hF;
//2
func_rb_entry_search16to2_tournament_data2_valid0[0] = func_rb_entry_search16to2_tournament_data3_valid0[0] || func_rb_entry_search16to2_tournament_data3_valid1[0];
func_rb_entry_search16to2_tournament_data2_num0[0] = (func_rb_entry_search16to2_tournament_data3_valid0[0])? func_rb_entry_search16to2_tournament_data3_num0[0] : func_rb_entry_search16to2_tournament_data3_num1[0];
func_rb_entry_search16to2_tournament_data2_valid1[0] = func_rb_entry_search16to2_tournament_data3_valid0[1] || func_rb_entry_search16to2_tournament_data3_valid1[1];
func_rb_entry_search16to2_tournament_data2_num1[0] = (func_rb_entry_search16to2_tournament_data3_valid0[1])? func_rb_entry_search16to2_tournament_data3_num0[1] : func_rb_entry_search16to2_tournament_data3_num1[1];
func_rb_entry_search16to2_tournament_data2_valid0[1] = func_rb_entry_search16to2_tournament_data3_valid0[2] || func_rb_entry_search16to2_tournament_data3_valid1[2];
func_rb_entry_search16to2_tournament_data2_num0[1] = (func_rb_entry_search16to2_tournament_data3_valid0[2])? func_rb_entry_search16to2_tournament_data3_num0[2] : func_rb_entry_search16to2_tournament_data3_num1[2];
func_rb_entry_search16to2_tournament_data2_valid1[1] = func_rb_entry_search16to2_tournament_data3_valid0[3] || func_rb_entry_search16to2_tournament_data3_valid1[3];
func_rb_entry_search16to2_tournament_data2_num1[1] = (func_rb_entry_search16to2_tournament_data3_valid0[3])? func_rb_entry_search16to2_tournament_data3_num0[3] : func_rb_entry_search16to2_tournament_data3_num1[3];
func_rb_entry_search16to2_tournament_data2_valid0[2] = func_rb_entry_search16to2_tournament_data3_valid0[4] || func_rb_entry_search16to2_tournament_data3_valid1[4];
func_rb_entry_search16to2_tournament_data2_num0[2] = (func_rb_entry_search16to2_tournament_data3_valid0[4])? func_rb_entry_search16to2_tournament_data3_num0[4] : func_rb_entry_search16to2_tournament_data3_num1[4];
func_rb_entry_search16to2_tournament_data2_valid1[2] = func_rb_entry_search16to2_tournament_data3_valid0[5] || func_rb_entry_search16to2_tournament_data3_valid1[5];
func_rb_entry_search16to2_tournament_data2_num1[2] = (func_rb_entry_search16to2_tournament_data3_valid0[5])? func_rb_entry_search16to2_tournament_data3_num0[5] : func_rb_entry_search16to2_tournament_data3_num1[5];
func_rb_entry_search16to2_tournament_data2_valid0[3] = func_rb_entry_search16to2_tournament_data3_valid0[6] || func_rb_entry_search16to2_tournament_data3_valid1[6];
func_rb_entry_search16to2_tournament_data2_num0[3] = (func_rb_entry_search16to2_tournament_data3_valid0[6])? func_rb_entry_search16to2_tournament_data3_num0[6] : func_rb_entry_search16to2_tournament_data3_num1[6];
func_rb_entry_search16to2_tournament_data2_valid1[3] = func_rb_entry_search16to2_tournament_data3_valid0[7] || func_rb_entry_search16to2_tournament_data3_valid1[7];
func_rb_entry_search16to2_tournament_data2_num1[3] = (func_rb_entry_search16to2_tournament_data3_valid0[7])? func_rb_entry_search16to2_tournament_data3_num0[7] : func_rb_entry_search16to2_tournament_data3_num1[7];
//1
func_rb_entry_search16to2_tournament_data1_valid0[0] = func_rb_entry_search16to2_tournament_data2_valid0[0] || func_rb_entry_search16to2_tournament_data2_valid1[0];
func_rb_entry_search16to2_tournament_data1_num0[0] = (func_rb_entry_search16to2_tournament_data2_valid0[0])? func_rb_entry_search16to2_tournament_data2_num0[0] : func_rb_entry_search16to2_tournament_data2_num1[0];
func_rb_entry_search16to2_tournament_data1_valid1[0] = func_rb_entry_search16to2_tournament_data2_valid0[1] || func_rb_entry_search16to2_tournament_data2_valid1[1];
func_rb_entry_search16to2_tournament_data1_num1[0] = (func_rb_entry_search16to2_tournament_data2_valid0[1])? func_rb_entry_search16to2_tournament_data2_num0[1] : func_rb_entry_search16to2_tournament_data2_num1[1];
func_rb_entry_search16to2_tournament_data1_valid0[1] = func_rb_entry_search16to2_tournament_data2_valid0[2] || func_rb_entry_search16to2_tournament_data2_valid1[2];
func_rb_entry_search16to2_tournament_data1_num0[1] = (func_rb_entry_search16to2_tournament_data2_valid0[2])? func_rb_entry_search16to2_tournament_data2_num0[2] : func_rb_entry_search16to2_tournament_data2_num1[2];
func_rb_entry_search16to2_tournament_data1_valid1[1] = func_rb_entry_search16to2_tournament_data2_valid0[3] || func_rb_entry_search16to2_tournament_data2_valid1[3];
func_rb_entry_search16to2_tournament_data1_num1[1] = (func_rb_entry_search16to2_tournament_data2_valid0[3])? func_rb_entry_search16to2_tournament_data2_num0[3] : func_rb_entry_search16to2_tournament_data2_num1[3];
//0
func_rb_entry_search16to2_tournament_data0_valid0 = func_rb_entry_search16to2_tournament_data1_valid0[0] || func_rb_entry_search16to2_tournament_data1_valid1[0];
func_rb_entry_search16to2_tournament_data0_num0 = (func_rb_entry_search16to2_tournament_data1_valid0[0])? func_rb_entry_search16to2_tournament_data1_num0[0] : func_rb_entry_search16to2_tournament_data1_num1[0];
func_rb_entry_search16to2_tournament_data0_valid1 = func_rb_entry_search16to2_tournament_data1_valid0[1] || func_rb_entry_search16to2_tournament_data1_valid1[1];
func_rb_entry_search16to2_tournament_data0_num1 = (func_rb_entry_search16to2_tournament_data1_valid0[1])? func_rb_entry_search16to2_tournament_data1_num0[1] : func_rb_entry_search16to2_tournament_data1_num1[1];
//2 Set
if(func_rb_entry_search16to2_tournament_data0_valid0 & func_rb_entry_search16to2_tournament_data0_valid1)begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data0_num0;
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data0_num1;
end
else if(func_rb_entry_search16to2_tournament_data1_valid0[0] & func_rb_entry_search16to2_tournament_data1_valid1[0])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data1_num0[0];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data1_num1[0];
end
else if(func_rb_entry_search16to2_tournament_data1_valid0[1] & func_rb_entry_search16to2_tournament_data1_valid1[1])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data1_num0[1];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data1_num1[1];
end
else if(func_rb_entry_search16to2_tournament_data2_valid0[0] & func_rb_entry_search16to2_tournament_data2_valid1[0])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data2_num0[0];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data2_num1[0];
end
else if(func_rb_entry_search16to2_tournament_data2_valid0[1] & func_rb_entry_search16to2_tournament_data2_valid1[1])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data2_num0[1];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data2_num1[1];
end
else if(func_rb_entry_search16to2_tournament_data2_valid0[2] & func_rb_entry_search16to2_tournament_data2_valid1[2])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data2_num0[2];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data2_num1[2];
end
else if(func_rb_entry_search16to2_tournament_data2_valid0[3] & func_rb_entry_search16to2_tournament_data2_valid1[3])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data2_num0[3];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data2_num1[3];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[0] & func_rb_entry_search16to2_tournament_data3_valid1[0])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[0];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[0];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[1] & func_rb_entry_search16to2_tournament_data3_valid1[1])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[1];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[1];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[2] & func_rb_entry_search16to2_tournament_data3_valid1[2])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[2];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[2];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[3] & func_rb_entry_search16to2_tournament_data3_valid1[3])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[3];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[3];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[4] & func_rb_entry_search16to2_tournament_data3_valid1[4])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[4];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[4];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[5] & func_rb_entry_search16to2_tournament_data3_valid1[5])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[5];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[5];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[6] & func_rb_entry_search16to2_tournament_data3_valid1[6])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[6];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[6];
end
else if(func_rb_entry_search16to2_tournament_data3_valid0[7] & func_rb_entry_search16to2_tournament_data3_valid1[7])begin
func_rb_entry_search16to2[9] = 1'b1;
func_rb_entry_search16to2[8:5] = func_rb_entry_search16to2_tournament_data3_num0[7];
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data3_num1[7];
end
//1Set
else if(func_rb_entry_search16to2_tournament_data0_valid0)begin
func_rb_entry_search16to2[9] = 1'b0;
func_rb_entry_search16to2[8:5] = 4'h0;
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data0_num0;
end
else if(func_rb_entry_search16to2_tournament_data0_valid1)begin
func_rb_entry_search16to2[9] = 1'b0;
func_rb_entry_search16to2[8:5] = 4'h0;
func_rb_entry_search16to2[4] = 1'b1;
func_rb_entry_search16to2[3:0] = func_rb_entry_search16to2_tournament_data0_num1;
end
//No Free
else begin
func_rb_entry_search16to2[9] = 1'b0;
func_rb_entry_search16to2[8:5] = 4'h0;
func_rb_entry_search16to2[4] = 1'b0;
func_rb_entry_search16to2[3:0] = 4'h0;
end
end
endfunction
assign {oPICKUP_1_VALID, oPICLUP_1_NUM, oPICKUP_0_VALID, oPICLUP_0_NUM}
= func_rb_entry_search16to2(
iINFO0, iINFO1, iINFO2, iINFO3,
iINFO4, iINFO5, iINFO6, iINFO7,
iINFO8, iINFO9, iINFO10, iINFO11,
iINFO12, iINFO13, iINFO14, iINFO15
);
endmodule
`default_nettype wire
|
// Verilog asynchronous look-up table for LED brightness / gamma correction.
// Copyright (c) 2013 Jared Boone, ShareBrained Technology, Inc.
//
// This file is part of the Medusa project.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module gamma (
input [7:0] v_i,
output reg [7:0] v_o
);
always @(v_i) begin
case(v_i)
0: v_o = 0;
1: v_o = 1;
2: v_o = 1;
3: v_o = 1;
4: v_o = 1;
5: v_o = 1;
6: v_o = 1;
7: v_o = 1;
8: v_o = 1;
9: v_o = 1;
10: v_o = 1;
11: v_o = 1;
12: v_o = 1;
13: v_o = 1;
14: v_o = 1;
15: v_o = 1;
16: v_o = 1;
17: v_o = 1;
18: v_o = 1;
19: v_o = 1;
20: v_o = 1;
21: v_o = 1;
22: v_o = 1;
23: v_o = 1;
24: v_o = 1;
25: v_o = 1;
26: v_o = 1;
27: v_o = 1;
28: v_o = 1;
29: v_o = 1;
30: v_o = 1;
31: v_o = 1;
32: v_o = 1;
33: v_o = 2;
34: v_o = 2;
35: v_o = 2;
36: v_o = 2;
37: v_o = 2;
38: v_o = 2;
39: v_o = 2;
40: v_o = 2;
41: v_o = 3;
42: v_o = 3;
43: v_o = 3;
44: v_o = 3;
45: v_o = 3;
46: v_o = 4;
47: v_o = 4;
48: v_o = 4;
49: v_o = 4;
50: v_o = 4;
51: v_o = 5;
52: v_o = 5;
53: v_o = 5;
54: v_o = 5;
55: v_o = 6;
56: v_o = 6;
57: v_o = 6;
58: v_o = 6;
59: v_o = 7;
60: v_o = 7;
61: v_o = 7;
62: v_o = 7;
63: v_o = 8;
64: v_o = 8;
65: v_o = 8;
66: v_o = 9;
67: v_o = 9;
68: v_o = 9;
69: v_o = 10;
70: v_o = 10;
71: v_o = 10;
72: v_o = 11;
73: v_o = 11;
74: v_o = 12;
75: v_o = 12;
76: v_o = 12;
77: v_o = 13;
78: v_o = 13;
79: v_o = 14;
80: v_o = 14;
81: v_o = 15;
82: v_o = 15;
83: v_o = 15;
84: v_o = 16;
85: v_o = 16;
86: v_o = 17;
87: v_o = 17;
88: v_o = 18;
89: v_o = 18;
90: v_o = 19;
91: v_o = 19;
92: v_o = 20;
93: v_o = 20;
94: v_o = 21;
95: v_o = 22;
96: v_o = 22;
97: v_o = 23;
98: v_o = 23;
99: v_o = 24;
100: v_o = 25;
101: v_o = 25;
102: v_o = 26;
103: v_o = 26;
104: v_o = 27;
105: v_o = 28;
106: v_o = 28;
107: v_o = 29;
108: v_o = 30;
109: v_o = 30;
110: v_o = 31;
111: v_o = 32;
112: v_o = 33;
113: v_o = 33;
114: v_o = 34;
115: v_o = 35;
116: v_o = 36;
117: v_o = 36;
118: v_o = 37;
119: v_o = 38;
120: v_o = 39;
121: v_o = 40;
122: v_o = 40;
123: v_o = 41;
124: v_o = 42;
125: v_o = 43;
126: v_o = 44;
127: v_o = 45;
128: v_o = 46;
129: v_o = 46;
130: v_o = 47;
131: v_o = 48;
132: v_o = 49;
133: v_o = 50;
134: v_o = 51;
135: v_o = 52;
136: v_o = 53;
137: v_o = 54;
138: v_o = 55;
139: v_o = 56;
140: v_o = 57;
141: v_o = 58;
142: v_o = 59;
143: v_o = 60;
144: v_o = 61;
145: v_o = 62;
146: v_o = 63;
147: v_o = 64;
148: v_o = 65;
149: v_o = 67;
150: v_o = 68;
151: v_o = 69;
152: v_o = 70;
153: v_o = 71;
154: v_o = 72;
155: v_o = 73;
156: v_o = 75;
157: v_o = 76;
158: v_o = 77;
159: v_o = 78;
160: v_o = 80;
161: v_o = 81;
162: v_o = 82;
163: v_o = 83;
164: v_o = 85;
165: v_o = 86;
166: v_o = 87;
167: v_o = 89;
168: v_o = 90;
169: v_o = 91;
170: v_o = 93;
171: v_o = 94;
172: v_o = 95;
173: v_o = 97;
174: v_o = 98;
175: v_o = 99;
176: v_o = 101;
177: v_o = 102;
178: v_o = 104;
179: v_o = 105;
180: v_o = 107;
181: v_o = 108;
182: v_o = 110;
183: v_o = 111;
184: v_o = 113;
185: v_o = 114;
186: v_o = 116;
187: v_o = 117;
188: v_o = 119;
189: v_o = 121;
190: v_o = 122;
191: v_o = 124;
192: v_o = 125;
193: v_o = 127;
194: v_o = 129;
195: v_o = 130;
196: v_o = 132;
197: v_o = 134;
198: v_o = 135;
199: v_o = 137;
200: v_o = 139;
201: v_o = 141;
202: v_o = 142;
203: v_o = 144;
204: v_o = 146;
205: v_o = 148;
206: v_o = 150;
207: v_o = 151;
208: v_o = 153;
209: v_o = 155;
210: v_o = 157;
211: v_o = 159;
212: v_o = 161;
213: v_o = 163;
214: v_o = 165;
215: v_o = 166;
216: v_o = 168;
217: v_o = 170;
218: v_o = 172;
219: v_o = 174;
220: v_o = 176;
221: v_o = 178;
222: v_o = 180;
223: v_o = 182;
224: v_o = 184;
225: v_o = 186;
226: v_o = 189;
227: v_o = 191;
228: v_o = 193;
229: v_o = 195;
230: v_o = 197;
231: v_o = 199;
232: v_o = 201;
233: v_o = 204;
234: v_o = 206;
235: v_o = 208;
236: v_o = 210;
237: v_o = 212;
238: v_o = 215;
239: v_o = 217;
240: v_o = 219;
241: v_o = 221;
242: v_o = 224;
243: v_o = 226;
244: v_o = 228;
245: v_o = 231;
246: v_o = 233;
247: v_o = 235;
248: v_o = 238;
249: v_o = 240;
250: v_o = 243;
251: v_o = 245;
252: v_o = 248;
253: v_o = 250;
254: v_o = 253;
255: v_o = 255;
default: v_o = 0;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
`define SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__einvp (
Z ,
A ,
TE
);
// Module ports
output Z ;
input A ;
input TE;
// Name Output Other arguments
notif1 notif10 (Z , A, TE );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__EINVP_FUNCTIONAL_V |
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
//
// Magnus Karlsson 20140818 RAM is now 64KB
//
// RR20140816 ROM to use new unscrambled code and preset with $readmemh
// ROM is now 4KB ($F000..$FFFF) and preset with interpreter/booter/runner
// RAM may be expanded to fill available space up to 60KB
// RR20140816 Bigger Hub RAM & No ROM
// RAM is 48KB and remaps 48-64KB to 32-48KB
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 16KB x 32 (64KB) ram with byte-write enables ($0000..$FFFF)
reg [7:0] ram3 [16*1024-1:0]; // 4 x 16KB
reg [7:0] ram2 [16*1024-1:0];
reg [7:0] ram1 [16*1024-1:0];
reg [7:0] ram0 [16*1024-1:0];
// pre-load ROM
initial
begin
$readmemh ("ROM_$F000-$FFFF_BYTE_0.spin", ram0, 15*1024);
$readmemh ("ROM_$F000-$FFFF_BYTE_1.spin", ram1, 15*1024);
$readmemh ("ROM_$F000-$FFFF_BYTE_2.spin", ram2, 15*1024);
$readmemh ("ROM_$F000-$FFFF_BYTE_3.spin", ram3, 15*1024);
end
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && w && wb[3])
ram3[a[13:0]] <= d[31:24];
if (ena_bus)
ram_q3 <= ram3[a[13:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && w && wb[2])
ram2[a[13:0]] <= d[23:16];
if (ena_bus)
ram_q2 <= ram2[a[13:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && w && wb[1])
ram1[a[13:0]] <= d[15:8];
if (ena_bus)
ram_q1 <= ram1[a[13:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && w && wb[0])
ram0[a[13:0]] <= d[7:0];
if (ena_bus)
ram_q0 <= ram0[a[13:0]];
end
assign q = {ram_q3, ram_q2, ram_q1, ram_q0};
endmodule
|
module rc_pipe_top (
input wire RESET_n,
input wire PCLK,
input wire clk_250,
input wire ffs_plol,
input wire TxDetectRx_Loopback,
input wire [1:0] PowerDown,
input wire ctc_disable,
input wire TxElecIdle_in,
input wire RxPolarity_in,
input wire [7:0] RxData_in,
input wire RxDataK_in,
input wire [2:0] RxStatus_in,
input wire RxValid_in,
input wire RxElecIdle_in,
input wire ff_rx_fclk_chx,
//----------------- RK BEGIN ------------------------------
input wire pcie_con_x,
input wire pcs_wait_done,
input wire start_mask,
input wire detsm_done,
output reg RxElecIdle_chx_8, //Not from CTC
//----------------- RK END --------------------------------
output wire [7:0] TxData_out,
output wire TxDataK_out,
output wire TxElecIdle_out,
output wire RxPolarity_out,
`ifdef DataWidth_8 //--------- 8-bit PIPE
input wire [7:0] TxData_in,
input wire TxDataK_in,
output wire [7:0] RxData_out,
output wire RxDataK_out,
`else //---------16-bit PIPE
input wire [15:0] TxData_in,
input wire [1:0] TxDataK_in,
output wire [15:0] RxData_out,
output wire [1:0] RxDataK_out,
`endif
output wire [2:0] RxStatus_out,
output wire RxValid_out,
output wire RxElecIdle_out,
output reg ffc_fb_loopback
);
// =============================================================================
// Parameters
// =============================================================================
localparam PCS_EDB = 8'hFE;
localparam PCS_COMMA = 8'hBC;
// =============================================================================
// Wires & Regs
// =============================================================================
wire ctc_skip_added;
wire ctc_skip_removed;
wire ctc_over_flow;
wire ctc_under_flow;
reg [7:0] RxData_chx_reg /* synthesis syn_srlstyle="registers" */;
reg RxDataK_chx_reg /* synthesis syn_srlstyle="registers" */;
reg RxValid_chx_reg /* synthesis syn_srlstyle="registers" */;
//reg RxElecIdle_reg;
reg [2:0] RxStatus_chx_reg /* synthesis syn_srlstyle="registers" */;
// =============================================================================
integer i, m;
wire [7:0] RxData_chx_s;
wire RxDataK_chx_s;
wire RxValid_chx_s;
wire RxElecIdle_chx_s;
wire [2:0] RxStatus_chx_s;
reg [7:0] TxData_chx_s /* synthesis syn_srlstyle="registers" */;
reg TxDataK_chx_s /* synthesis syn_srlstyle="registers" */;
`ifdef DataWidth_8 //--------- 8-bit PIPE
reg [7:0] RxData_chx /* synthesis syn_srlstyle="registers" */;
reg RxDataK_chx /* synthesis syn_srlstyle="registers" */;
wire [7:0] TxData_chx;
wire TxDataK_chx;
`else //---------16-bit PIPE
reg [15:0] RxData_chx /* synthesis syn_srlstyle="registers" */;
reg [1:0] RxDataK_chx /* synthesis syn_srlstyle="registers" */;
wire [15:0] TxData_chx;
wire [1:0] TxDataK_chx;
`endif
reg RxElecIdle_chx /* synthesis syn_srlstyle="registers" */;
reg RxValid_chx /* synthesis syn_srlstyle="registers" */;
reg [2:0] RxStatus_chx /* synthesis syn_srlstyle="registers" */;
`ifdef DataWidth_8 //--------- 8-bit PIPE
// COMMA alignment with RxValid Rising Edge
wire comma_chx;
`endif
// CTC Outputs
wire[7:0] RxData_chx_8;
wire RxDataK_chx_8;
wire[2:0] RxStatus_chx_8;
//reg RxElecIdle_chx_8; //Not from CTC OUTPUT
wire RxValid_chx_8;
`ifdef DataWidth_16 //--------- 16-bit PIPE
reg drate_enable_tx;
reg drate_enable_rx;
reg PLOL_sync;
reg PLOL_hclk /* synthesis syn_srlstyle="registers" */;
// COMMA alignment with RxValid Rising Edge
wire commaH_chx;
wire commaL_chx;
// RX_GEAR Outputs
wire[27:0] Rx_chx;
wire [1:0] RxDataK_chx_16;
wire [15:0] RxData_chx_16;
wire [5:0] RxStatus_chx_16;
wire RxValid_chx_16;
wire RxElecIdle_chx_16;
// TX-PATH
wire TxElecIdle_chx_8;
wire[7:0] TxData_chx_8;
wire TxDataK_chx_8;
`endif
//---- X4 : Recoverd clks
//---- X1 : PLL 250 clk
`ifdef X4
reg pcs_wait_done_chx_sync;
reg ei_ctc_chx_sync;
reg ei_ctc_chx /* synthesis syn_srlstyle="registers" */;
wire chx_RESET_n;
`endif
reg pcs_wait_done_chx /* synthesis syn_srlstyle="registers" */;
reg ctc_reset_chx;
reg start_mask_sync;
reg start_mask_fclk /* synthesis syn_srlstyle="registers" */;
reg [15:0] rxelec_ctc_delay_chx /* synthesis syn_srlstyle="registers" */;
reg [20:0] rxvalid_delay_chx /* synthesis syn_srlstyle="registers" */;
reg TxElecIdle_chx_s /* synthesis syn_srlstyle="registers" */;
// =============================================================================
//-------- RX PATH INPUTS
//From SERDES (Inputs)
assign RxData_chx_s = RxData_in;
assign RxDataK_chx_s = RxDataK_in;
assign RxValid_chx_s = RxValid_in;
assign RxStatus_chx_s = RxStatus_in;
assign RxElecIdle_chx_s = RxElecIdle_in;
//--------- RX PATH OUTPUTS
//X4 : From CTC/RX_GEAR (Outputs) TO PIPE
assign RxData_out = RxData_chx;
assign RxDataK_out = RxDataK_chx;
assign RxValid_out = RxValid_chx ;
assign RxStatus_out = RxStatus_chx;
assign RxElecIdle_out = RxElecIdle_chx;
//-------- TX PATH INPUTS
//From PIPE (Inputs)
assign TxData_chx = TxData_in;
assign TxDataK_chx = TxDataK_in;
assign TxElecIdle_chx = TxElecIdle_in;
//-------- TX PATH OUTPUTS
//From Input/TX_GEAR (Outputs) TO SERDES
assign TxData_out = TxData_chx_s;
assign TxDataK_out = TxDataK_chx_s;
assign TxElecIdle_out = TxElecIdle_chx_s;
// =============================================================================
`ifdef X4 //X4 CTC --> Recovered clks
always @(posedge ff_rx_fclk_chx or negedge RESET_n) begin
if(!RESET_n) begin
pcs_wait_done_chx_sync <= 1'b0;
pcs_wait_done_chx <= 1'b0;
ei_ctc_chx_sync <= 1'b1;
ei_ctc_chx <= 1'b1;
ctc_reset_chx <= 1'b0;
end
else begin
// For CTC write enable/RESET (RLOL qualified with EI)
// RxEI should be LOW & pcs_wait_done should be HIGH for CTC
// to start, otherwise CTC will be held in RESET
ctc_reset_chx <= ~ei_ctc_chx & pcs_wait_done_chx;
//Sync.
// For RxValid Mask
pcs_wait_done_chx_sync <= pcs_wait_done;
pcs_wait_done_chx <= pcs_wait_done_chx_sync;
ei_ctc_chx_sync <= RxElecIdle_chx_8; //Masked RxElecIdle
ei_ctc_chx <= ei_ctc_chx_sync;
end
end
`endif //X4
`ifdef X1 //X1 no CTC --> No Recovered clks
always @(posedge clk_250 or negedge RESET_n) begin
if(!RESET_n) begin
ctc_reset_chx <= 1'b0;
pcs_wait_done_chx <= 1'b0;
end
else begin
//No Sync is required
ctc_reset_chx <= ~RxElecIdle_chx_8 & pcs_wait_done_chx;
pcs_wait_done_chx <= pcs_wait_done;
end
end
`endif //X1
// =============================================================================
// EI bypass CTC : Create equal delay (250 PLL clk)
// No CDR clk when EI is HIGH
// =============================================================================
always @(posedge clk_250 or negedge RESET_n) begin
if(!RESET_n) begin
start_mask_sync <= 1'b0;
start_mask_fclk <= 1'b0;
RxElecIdle_chx_8 <= 1'b1;
rxelec_ctc_delay_chx <= 16'hFFFF;
end
else begin
start_mask_sync <= start_mask;
start_mask_fclk <= start_mask_sync;
// Min. 12 : 250 clks for EI Mask
// RxElecIdle_chx_8 is the Masked RxElecIdle siganl
RxElecIdle_chx_8 <= rxelec_ctc_delay_chx[15] | start_mask_fclk;
for (m= 0;m<15;m=m+1) begin
if (m == 0) begin
//rxelec_ctc_delay_chx[0] <= Int_RxElecIdle_chx;
rxelec_ctc_delay_chx[0] <= RxElecIdle_chx_s;
rxelec_ctc_delay_chx[1] <= rxelec_ctc_delay_chx[0];
end
else begin
rxelec_ctc_delay_chx[m+1] <= rxelec_ctc_delay_chx[m];
end
end
end
end
// =============================================================================
// ====TX PATH===
// For X1 or X4
// =============================================================================
always @(posedge clk_250 or negedge RESET_n) begin
if(!RESET_n) begin
TxData_chx_s <= 0;
TxDataK_chx_s <= 0;
TxElecIdle_chx_s <= 1'b1;
end
else begin
`ifdef DataWidth_8 //--------- 8-bit PIPE Take from PIPE --------
TxData_chx_s <= TxData_chx;
TxDataK_chx_s <= TxDataK_chx;
TxElecIdle_chx_s <= TxElecIdle_chx;
`endif // 8-bit
`ifdef DataWidth_16 //---------16-bit PIPE Take from TX_GEAR -----
TxData_chx_s <= TxData_chx_8;
TxDataK_chx_s <= TxDataK_chx_8;
TxElecIdle_chx_s <= TxElecIdle_chx_8;
`endif // 16-bit
end
end
// =============================================================================
// ====RX PATH===
// COMMON for X4/X1
// =============================================================================
// =============================================================================
// The RxValid_chx signal is going low early before the data comming
// out of PCS, so delay this signal
// Delayed by 21 Clocks * 4 ns = 84 ns;
// =============================================================================
wire clk_new;
`ifdef X4
assign clk_new = ff_rx_fclk_chx;
`endif
`ifdef X1
assign clk_new = clk_250;
`endif
always @(posedge clk_new or negedge RESET_n) begin //X1: clk 250 X4: Recovered clk
if(!RESET_n) begin
RxDataK_chx_reg <= 1'b0;
RxData_chx_reg <= 8'h00;
RxValid_chx_reg <= 1'b0;
rxvalid_delay_chx <= 0;
RxStatus_chx_reg <= 3'b000;
end
else begin
//X4: To CTC --- X1: To CTC Bypass
RxDataK_chx_reg <= RxDataK_chx_s;
RxData_chx_reg <= RxData_chx_s;
RxValid_chx_reg <= rxvalid_delay_chx[20];
RxStatus_chx_reg <= RxStatus_chx_s;
for (i= 0;i<20;i=i+1) begin
if (i == 0) begin
rxvalid_delay_chx[0] <= RxValid_chx_s & pcs_wait_done_chx;
rxvalid_delay_chx[1] <= rxvalid_delay_chx[0];
end
else begin
rxvalid_delay_chx[i+1] <= rxvalid_delay_chx[i];
end
end
end
end
// =================================================================
// RxData Input (From SERDES TO CTC ) - 8-bit PIPE
// RxData output (From CTC) -- 8-bit PIPE
//
// RxData Input (From SERDES TO CTC TO Rx_gear) - 16-bit PIPE
// RxData output (From Rx_gear) - 16-bit PIPE
// =============================================================================
`ifdef DataWidth_8 //--------- 8-bit PIPE Take from CTC ---------
assign comma_chx = (RxDataK_chx_8 && (RxData_chx_8 == PCS_COMMA)) ? 1'b1 : 1'b0;
always @(posedge PCLK or negedge RESET_n) begin //250 PLL clk
if(!RESET_n) begin
RxDataK_chx <= 1'b0;
RxData_chx <= 8'h0;
RxElecIdle_chx <= 1'b1;
RxValid_chx <= 1'b0;
RxStatus_chx <= 3'b000;
end
else begin
RxData_chx <= RxData_chx_8;
RxDataK_chx <= RxDataK_chx_8;
// RxValid Rising Edge should be with COMMA
if (RxValid_chx_8 && comma_chx)
RxValid_chx <= 1'b1;
else if (~RxValid_chx_8)
RxValid_chx <= 1'b0;
if (detsm_done) begin
if (pcie_con_x) //No Sync. is required
RxStatus_chx <= 3'b011; //DETECTED
else
RxStatus_chx <= 3'b000; //NOT DETECTED
end
else begin
RxStatus_chx <= RxStatus_chx_8;
end
RxElecIdle_chx <= RxElecIdle_chx_8;
end
end
`endif //--------- 8-bit PIPE -------------------------------------
`ifdef DataWidth_16 //---------16-bit PIPE Take from RX_GEAR -----
assign RxData_chx_16 = {Rx_chx[27:20],Rx_chx[13:6]};
assign RxDataK_chx_16 = {Rx_chx[19],Rx_chx[5]};
assign RxStatus_chx_16 = {Rx_chx[18:16],Rx_chx[4:2]};
assign RxElecIdle_chx_16 = (Rx_chx[15] | Rx_chx[1]);
assign RxValid_chx_16 = (Rx_chx[14] | Rx_chx[0]);
assign commaH_chx = (RxDataK_chx_16[1] && (RxData_chx_16[15:8] == PCS_COMMA)) ? 1'b1 : 1'b0;
assign commaL_chx = (RxDataK_chx_16[0] && (RxData_chx_16[7:0] == PCS_COMMA)) ? 1'b1 : 1'b0;
always @(posedge PCLK or negedge RESET_n) begin //125 PLL clk
if(!RESET_n) begin
RxDataK_chx <= 2'b0;
RxData_chx <= 16'h0;
RxElecIdle_chx <= 1'b1;
RxValid_chx <= 1'b0;
RxStatus_chx <= 3'b000;
end
else begin
RxData_chx <= RxData_chx_16;
RxDataK_chx <= RxDataK_chx_16;
// RxValid Rising Edge should be with COMMA
if (RxValid_chx_16 && (commaH_chx || commaL_chx))
RxValid_chx <= 1'b1;
else if (~RxValid_chx_16)
RxValid_chx <= 1'b0;
if (detsm_done) begin
if (pcie_con_x) //No Sync. is required
RxStatus_chx <= 3'b011; //DETECTED
else
RxStatus_chx <= 3'b000; //NOT DETECTED
end
else begin
if((RxStatus_chx_16[2:0] == 3'b001) || (RxStatus_chx_16[5:3] == 3'b001))
RxStatus_chx <= 3'b001; //SKIP added
else if((RxStatus_chx_16[2:0] == 3'b010) || (RxStatus_chx_16[5:3] == 3'b010))
RxStatus_chx <= 3'b010; //SKIP deleted
else
RxStatus_chx <= 3'b000;
end
RxElecIdle_chx <= RxElecIdle_chx_16;
end
end
`endif //---------16-bit PIPE -------------------------------------
// =================================================================
// CTC instantiation only for X4
// =================================================================
`ifdef X4 //X4 8-bit/16-bit
//Both should be HIGH for CTC to start
assign chx_RESET_n = RESET_n & ctc_reset_chx;
ctc u0_ctc
(
//------- Inputs
.rst_n (chx_RESET_n),
.clk_in (ff_rx_fclk_chx),
.clk_out (clk_250),
.ctc_disable (ctc_disable),
.data_in (RxData_chx_reg),
.kcntl_in (RxDataK_chx_reg),
.status_in (RxStatus_chx_reg),
.lanesync_in (RxValid_chx_reg),
//------- Outputs
.ctc_read_enable (),
.ctc_skip_added (ctc_skip_added),
.ctc_skip_removed (ctc_skip_removed),
.ctc_data_out (RxData_chx_8),
.ctc_kcntl_out (RxDataK_chx_8),
.ctc_status_out (RxStatus_chx_8),
.ctc_lanesync_out (RxValid_chx_8),
.ctc_under_flow (ctc_under_flow),
.ctc_over_flow (ctc_over_flow)
);
`else //X1 8-bit/16-bit : Pass the Data as it is (bypass CTC)
assign RxData_chx_8 = (ctc_reset_chx) ? RxData_chx_reg : 0;
assign RxDataK_chx_8 = (ctc_reset_chx) ? RxDataK_chx_reg : 0;
assign RxStatus_chx_8 = (ctc_reset_chx) ? RxStatus_chx_reg : 0;
assign RxValid_chx_8 = (ctc_reset_chx) ? RxValid_chx_reg : 0;
`endif // X4
// =============================================================================
// Rxdata : From CTC --> Rx_gear -- 16-bit PIPE -- X4/X1
// =============================================================================
`ifdef DataWidth_16 //---------16-bit PIPE RX/TX_GEAR ------------
// ==========================================================================
// Generating drate_enable_rx for rx_gear -- 125 Mhz clk
// ==========================================================================
always @(posedge PCLK or negedge RESET_n) begin
if(!RESET_n) begin
drate_enable_rx <= 1'b0;
PLOL_sync <= 1'b1;
PLOL_hclk <= 1'b1;
end
else begin
// Sync.
PLOL_sync <= ffs_plol;
PLOL_hclk <= PLOL_sync;
if(PLOL_hclk == 1'b1) //No lock
drate_enable_rx <= 1'b0;
else // Enable required for RxElecIdle passing
drate_enable_rx <= 1'b1;
end
end
// ==========================================================================
// Generating drate_enable_tx for tx_gear -- 125 Mhz clk
// ==========================================================================
always @(posedge PCLK or negedge RESET_n) begin
if(!RESET_n) begin
drate_enable_tx <= 1'b0;
end
else begin
if(PLOL_hclk == 1'b1) //No lock
drate_enable_tx <= 1'b0;
else if (detsm_done == 1'b1) // detection is done
drate_enable_tx <= 1'b1;
end
end
// convert 8 bit data to 16 bits ----RX_GEAR
rx_gear #( .GWIDTH(14)) u1_rx_gear (
// Clock and Reset
.clk_125 ( PCLK ),
.clk_250 ( clk_250 ),
.rst_n ( RESET_n ),
// Inputs
.drate_enable (drate_enable_rx),
.data_in ({RxData_chx_8,RxDataK_chx_8,RxStatus_chx_8,RxElecIdle_chx_8,RxValid_chx_8}),
// Outputs
.data_out (Rx_chx )
);
// convert 16 bit data to 8 bits ----TX_GEAR
tx_gear #( .GWIDTH(20)) u1_tx_gear (
// Clock and Reset
.clk_125 ( PCLK ),
.clk_250 ( clk_250 ),
.rst_n ( RESET_n ),
// Inputs
.drate_enable (drate_enable_tx ),
.data_in ( {TxElecIdle_chx,TxData_chx[15:8],TxDataK_chx[1],TxElecIdle_chx,TxData_chx[7:0],TxDataK_chx[0]}),
// Outputs
.data_out ( {TxElecIdle_chx_8,TxData_chx_8,TxDataK_chx_8} )
);
`endif //---------16-bit PIPE -------------------------------------
// =============================================================================
//Assert slave loopback as long as TxDetectRx_Loopback is asserted by FPGA side
//when Serdes is in normal mode and TxElecIdle_ch0 is inactive.
// =============================================================================
always @(posedge PCLK or negedge RESET_n) begin
if(!RESET_n) begin
ffc_fb_loopback <= 1'b0;
end
else begin
ffc_fb_loopback <= ((PowerDown == 2'b00) & TxDetectRx_Loopback & !TxElecIdle_chx) ? 1'b1: 1'b0;
end
end
// =============================================================================
// synchronize RxPolarity signal to RX recovered clock (all modes)
// =============================================================================
reg sync1_RxPolarity ;
reg sync2_RxPolarity /* synthesis syn_srlstyle="registers" */;
always @(posedge ff_rx_fclk_chx or negedge RESET_n) begin
if(!RESET_n) begin
sync1_RxPolarity <= 'h0;
sync2_RxPolarity <= 'h0;
end
else begin
sync1_RxPolarity <= RxPolarity_in ;
sync2_RxPolarity <= sync1_RxPolarity ;
end
end
assign RxPolarity_out = sync2_RxPolarity ;
endmodule
// =============================================================================
|
//MODULE REFERENCE
`define tenv_clock tenv_clock
`define tenv_descstd_device tenv_descstd_device
`define tenv_usbhost tenv_usbhost
`define tenv_usbdev tenv_usbdev
module tenv_test;
//IFACE
reg start=0;
//LOCAL
localparam block_name="tenv_test";
integer seed;
integer i;
//TASKS
`include "tenv_test/tenv_test.tcase_powered.v"
`include "tenv_test/tenv_test.tcase_default.v"
`include "tenv_test/tenv_test.tcase_addressed.v"
`include "tenv_test/tenv_test.tcase_configured.v"
`include "tenv_test/tenv_test.tcase_suspended.v"
`include "tenv_test/tenv_test.tcase_trfer_bulkint.v"
`include "tenv_test/tenv_test.tcase_trfer_isoch.v"
`include "tenv_test/tenv_test.tcase_trfer_control.v"
`include "tenv_test/tenv_test.tcase_bitstream.v"
`include "tenv_test/tenv_test.tcase_reply_delay.v"
`include "tenv_test/tenv_test.trsac.v"
`include "tenv_test/tenv_test.check_data.v"
`include "tenv_test/tenv_test.check_descdev.v"
initial forever
begin
wait(start==1);
$timeformat(-9, 0, " ns", 10);
#100;
$write("%0t [%0s]: ",$realtime,block_name);
$write("--- Functional verification of \"usb_devtrsac\" ---\n");
fork
begin:TEST_SEQUENCE
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$write("FULL SPEED FUNCTION");
$write("\n");
//LAUNCH CLOCKS
`tenv_clock.x4_timehigh=10;
`tenv_clock.x4_timelow=11;
`tenv_clock.x4_en=1;
@(posedge `tenv_clock.x4);
//INIT
`tenv_usbdev.speed=1;//SELECT FULL SPEED
`tenv_usbdev.ep_enable=15'h7FFF;//ENABLE ALL EP
`tenv_usbdev.ep_isoch=15'd000_0000_0000_0000;
`tenv_usbdev.ep_intnoretry=15'b000_0000_0000_0000;
`tenv_usbhost.speed=`tenv_usbdev.speed;
`tenv_usbhost.bit_time=`tenv_clock.x4_period*4;
//TESTCASES
tcase_powered;
tcase_default;
tcase_addressed;
tcase_configured;
tcase_suspended;
tcase_trfer_bulkint;
tcase_trfer_isoch;
tcase_trfer_control;
tcase_bitstream;
tcase_reply_delay;
//STOP CLOCKS
@(negedge `tenv_clock.x4);
`tenv_clock.x4_en=0;
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$write("LOW SPEED FUNCTION");
$write("\n");
//LAUNCH CLOCKS
`tenv_clock.x4_timehigh=83;
`tenv_clock.x4_timelow=84;
`tenv_clock.x4_en=1;
@(posedge `tenv_clock.x4);
//INIT
`tenv_usbdev.speed=0;//SELECT LOW SPEED
`tenv_usbdev.ep_enable=15'h7FFF;//ENABLE ALL EP
`tenv_usbdev.ep_isoch=15'd000_0000_0000_0000;
`tenv_usbdev.ep_intnoretry=15'b000_0000_0000_0000;
`tenv_usbhost.speed=`tenv_usbdev.speed;
`tenv_usbhost.bit_time=`tenv_clock.x4_period*4;
//TESTCASES
tcase_powered;
tcase_default;
tcase_addressed;
tcase_configured;
tcase_suspended;
tcase_trfer_bulkint;
tcase_trfer_control;
tcase_bitstream;
tcase_reply_delay;
$write("\n");
$write("%0t [%0s]: ",$realtime,block_name);
$write("--- Functional verification of \"usb_devtrsac\" ");
$write("is successfull ---\n");
disable TIMEBOMB;
end//TEST_SEQUENCE
begin:TIMEBOMB
repeat(300) #(1000*1000);//100 ms
$write ("\n");
$write ("%0t [%0s]: ",$realtime,block_name);
$display("Error - test time is run out.");
disable TEST_SEQUENCE;
end//TIMEBOMB
join
start=0;
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_receiver.v ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver logic ////
//// ////
//// Known problems (limits): ////
//// None known ////
//// ////
//// To Do: ////
//// Thourough testing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2001/05/17 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.28 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.27 2001/12/30 20:39:13 mohor
// More than one character was stored in case of break. End of the break
// was not detected correctly.
//
// Revision 1.26 2001/12/20 13:28:27 mohor
// Missing declaration of rf_push_q fixed.
//
// Revision 1.25 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.24 2001/12/19 08:03:34 mohor
// Warnings cleared.
//
// Revision 1.23 2001/12/19 07:33:54 mohor
// Synplicity was having troubles with the comment.
//
// Revision 1.22 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.21 2001/12/13 10:31:16 mohor
// timeout irq must be set regardless of the rda irq (rda irq does not reset the
// timeout counter).
//
// Revision 1.20 2001/12/10 19:52:05 gorban
// Igor fixed break condition bugs
//
// Revision 1.19 2001/12/06 14:51:04 gorban
// Bug in LSR[0] is fixed.
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
//
// Revision 1.18 2001/12/03 21:44:29 gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.17 2001/11/28 19:36:39 gorban
// Fixed: timeout and break didn't pay attention to current data format when counting time
//
// Revision 1.16 2001/11/27 22:17:09 gorban
// Fixed bug that prevented synthesis in uart_receiver.v
//
// Revision 1.15 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.14 2001/11/10 12:43:21 gorban
// Logic Synthesis bugs fixed. Some other minor changes
//
// Revision 1.13 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.12 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.11 2001/10/31 15:19:22 gorban
// Fixes to break and timeout conditions
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.6 2001/06/23 11:21:48 gorban
// DL made 16-bit long. Fixed transmission/reception bugs.
//
// Revision 1.5 2001/06/02 14:28:14 gorban
// Fixed receiver and transmitter. Major bug fixed.
//
// Revision 1.4 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:49 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/21 19:12:02 gorban
// Corrected some Linter messages.
//
// Revision 1.1 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:11+02 jacob
// Initial revision
//
//
// synopsys translate_off
//`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;
output [9:0] counter_t;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push_pulse;
reg [3:0] rstate;
reg [3:0] rcounter16;
reg [2:0] rbit_counter;
reg [7:0] rshift; // receiver shift register
reg rparity; // received parity
reg rparity_error;
reg rframing_error; // framing error flag
reg rbit_in;
reg rparity_xor;
reg [7:0] counter_b; // counts the 0 (low) signals
reg rf_push_q;
// RX FIFO signals
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire rf_error_bit; // an error (parity or framing) is inside the fifo
wire break_error = (counter_b == 0);
// RX FIFO instance
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
.clk( clk ),
.wb_rst_i( wb_rst_i ),
.data_in( rf_data_in ),
.data_out( rf_data_out ),
.push( rf_push_pulse ),
.pop( rf_pop ),
.overrun( rf_overrun ),
.count( rf_count ),
.error_bit( rf_error_bit ),
.fifo_reset( rx_reset ),
.reset_status(lsr_mask)
);
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
parameter sr_rec_bit = 4'd2;
parameter sr_rec_parity = 4'd3;
parameter sr_rec_stop = 4'd4;
parameter sr_check_parity = 4'd5;
parameter sr_rec_prepare = 4'd6;
parameter sr_end_bit = 4'd7;
parameter sr_ca_lc_parity = 4'd8;
parameter sr_wait1 = 4'd9;
parameter sr_push = 4'd10;
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
begin
rstate <= #1 sr_idle;
rbit_in <= #1 1'b0;
rcounter16 <= #1 0;
rbit_counter <= #1 0;
rparity_xor <= #1 1'b0;
rframing_error <= #1 1'b0;
rparity_error <= #1 1'b0;
rparity <= #1 1'b0;
rshift <= #1 0;
rf_push <= #1 1'b0;
rf_data_in <= #1 0;
end
else
if (enable)
begin
case (rstate)
sr_idle : begin
rf_push <= #1 1'b0;
rf_data_in <= #1 0;
rcounter16 <= #1 4'b1110;
if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
begin
rstate <= #1 sr_rec_start;
end
end
sr_rec_start : begin
rf_push <= #1 1'b0;
if (rcounter16_eq_7) // check the pulse
if (srx_pad_i==1'b1) // no start bit
rstate <= #1 sr_idle;
else // start bit detected
rstate <= #1 sr_rec_prepare;
rcounter16 <= #1 rcounter16_minus_1;
end
sr_rec_prepare:begin
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rbit_counter <= #1 3'b100;
2'b01 : rbit_counter <= #1 3'b101;
2'b10 : rbit_counter <= #1 3'b110;
2'b11 : rbit_counter <= #1 3'b111;
endcase
if (rcounter16_eq_0)
begin
rstate <= #1 sr_rec_bit;
rcounter16 <= #1 4'b1110;
rshift <= #1 0;
end
else
rstate <= #1 sr_rec_prepare;
rcounter16 <= #1 rcounter16_minus_1;
end
sr_rec_bit : begin
if (rcounter16_eq_0)
rstate <= #1 sr_end_bit;
if (rcounter16_eq_7) // read the bit
case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]};
2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]};
2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]};
2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]};
endcase
rcounter16 <= #1 rcounter16_minus_1;
end
sr_end_bit : begin
if (rbit_counter==3'b0) // no more bits in word
if (lcr[`UART_LC_PE]) // choose state based on parity
rstate <= #1 sr_rec_parity;
else
begin
rstate <= #1 sr_rec_stop;
rparity_error <= #1 1'b0; // no parity - no error :)
end
else // else we have more bits to read
begin
rstate <= #1 sr_rec_bit;
rbit_counter <= #1 rbit_counter - 1'b1;
end
rcounter16 <= #1 4'b1110;
end
sr_rec_parity: begin
if (rcounter16_eq_7) // read the parity
begin
rparity <= #1 srx_pad_i;
rstate <= #1 sr_ca_lc_parity;
end
rcounter16 <= #1 rcounter16_minus_1;
end
sr_ca_lc_parity : begin // rcounter equals 6
rcounter16 <= #1 rcounter16_minus_1;
rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data
rstate <= #1 sr_check_parity;
end
sr_check_parity: begin // rcounter equals 5
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1
2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1
2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd
2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0
endcase
rcounter16 <= #1 rcounter16_minus_1;
rstate <= #1 sr_wait1;
end
sr_wait1 : if (rcounter16_eq_0)
begin
rstate <= #1 sr_rec_stop;
rcounter16 <= #1 4'b1110;
end
else
rcounter16 <= #1 rcounter16_minus_1;
sr_rec_stop : begin
if (rcounter16_eq_7) // read the parity
begin
rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit)
rstate <= #1 sr_push;
end
rcounter16 <= #1 rcounter16_minus_1;
end
sr_push : begin
///////////////////////////////////////
// $display($time, ": received: %b", rf_data_in);
if(srx_pad_i | break_error)
begin
if(break_error)
rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
else
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= #1 1'b1;
rstate <= #1 sr_idle;
end
else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
begin
rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= #1 1'b1;
rcounter16 <= #1 4'b1110;
rstate <= #1 sr_rec_start;
end
end
default : rstate <= #1 sr_idle;
endcase
end // if (enable)
end // always of receiver
always @ (posedge clk or posedge wb_rst_i)
begin
if(wb_rst_i)
rf_push_q <= 0;
else
rf_push_q <= #1 rf_push;
end
assign rf_push_pulse = rf_push & ~rf_push_q;
//
// Break condition detection.
// Works in conjuction with the receiver state machine
reg [9:0] toc_value; // value to be set to timeout counter
always @(lcr)
case (lcr[3:0])
4'b0000 : toc_value = 447; // 7 bits
4'b0100 : toc_value = 479; // 7.5 bits
4'b0001, 4'b1000 : toc_value = 511; // 8 bits
4'b1100 : toc_value = 543; // 8.5 bits
4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
4'b1111 : toc_value = 767; // 12 bits
endcase // case(lcr[3:0])
wire [7:0] brc_value; // value to be set to break counter
assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_b <= #1 8'd159;
else
if (srx_pad_i)
counter_b <= #1 brc_value; // character time length - 1
else
if(enable & counter_b != 8'b0) // only work on enable times break not reached.
counter_b <= #1 counter_b - 1; // decrement break counter
end // always of break condition detection
///
/// Timeout condition detection
reg [9:0] counter_t; // counts the timeout condition clocks
always @(posedge clk or posedge wb_rst_i)
begin
if (wb_rst_i)
counter_t <= #1 10'd639; // 10 bits for the default 8N1
else
if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
counter_t <= #1 toc_value;
else
if (enable && counter_t != 10'b0) // we don't want to underflow
counter_t <= #1 counter_t - 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NAND2_PP_SYMBOL_V
/**
* nand2: 2-input NAND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand2 (
//# {{data|Data Signals}}
input A ,
input B ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND2_PP_SYMBOL_V
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module Stack (
CLK,
RESET,
PUSH,
POP,
D,
Q
);
parameter WIDTH = 11;
parameter DEPTH_POW = 7;
parameter DEPTH = 1 << DEPTH_POW;
input CLK;
input RESET;
input PUSH;
input POP;
input [WIDTH - 1:0] D;
output reg [WIDTH - 1:0] Q;
reg [DEPTH_POW - 1:0] PTR;
reg [WIDTH - 1:0] STACK [0:DEPTH - 1];
always @ (posedge CLK)
if(RESET)
PTR <= 0;
else if(PUSH)
PTR <= PTR + 1;
else if(POP)
PTR <= PTR - 1;
always @ (posedge CLK)
if(PUSH || POP)
begin
if(PUSH)
begin
STACK[PTR] <= D;
end
Q <= STACK[PTR - 1];
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 07:02:41 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0_1/system_ov7670_vga_1_0_stub.v
// Design : system_ov7670_vga_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_vga,Vivado 2016.4" *)
module system_ov7670_vga_1_0(pclk, data, rgb)
/* synthesis syn_black_box black_box_pad_pin="pclk,data[7:0],rgb[15:0]" */;
input pclk;
input [7:0]data;
output [15:0]rgb;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// serial data output interface: serdes(x8) or oddr(x2) output module
`timescale 1ps/1ps
module ad_serdes_clk (
// clock and divided clock
mmcm_rst,
clk_in_p,
clk_in_n,
clk,
div_clk,
// drp interface
up_clk,
up_rstn,
up_drp_sel,
up_drp_wr,
up_drp_addr,
up_drp_wdata,
up_drp_rdata,
up_drp_ready,
up_drp_locked);
// parameters
parameter SERDES_OR_DDR_N = 1;
parameter MMCM_OR_BUFR_N = 1;
parameter MMCM_DEVICE_TYPE = 0;
parameter MMCM_CLKIN_PERIOD = 1.667;
parameter MMCM_VCO_DIV = 6;
parameter MMCM_VCO_MUL = 12.000;
parameter MMCM_CLK0_DIV = 2.000;
parameter MMCM_CLK1_DIV = 6;
// clock and divided clock
input mmcm_rst;
input clk_in_p;
input clk_in_n;
output clk;
output div_clk;
// drp interface
input up_clk;
input up_rstn;
input up_drp_sel;
input up_drp_wr;
input [11:0] up_drp_addr;
input [15:0] up_drp_wdata;
output [15:0] up_drp_rdata;
output up_drp_ready;
output up_drp_locked;
// internal signals
wire clk_in_s;
// instantiations
IBUFGDS i_clk_in_ibuf (
.I (clk_in_p),
.IB (clk_in_n),
.O (clk_in_s));
generate
if (MMCM_OR_BUFR_N == 1) begin
ad_mmcm_drp #(
.MMCM_DEVICE_TYPE (MMCM_DEVICE_TYPE),
.MMCM_CLKIN_PERIOD (MMCM_CLKIN_PERIOD),
.MMCM_VCO_DIV (MMCM_VCO_DIV),
.MMCM_VCO_MUL (MMCM_VCO_MUL),
.MMCM_CLK0_DIV (MMCM_CLK0_DIV),
.MMCM_CLK1_DIV (MMCM_CLK1_DIV))
i_mmcm_drp (
.clk (clk_in_s),
.mmcm_rst (mmcm_rst),
.mmcm_clk_0 (clk),
.mmcm_clk_1 (div_clk),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_drp_sel (up_drp_sel),
.up_drp_wr (up_drp_wr),
.up_drp_addr (up_drp_addr),
.up_drp_wdata (up_drp_wdata),
.up_drp_rdata (up_drp_rdata),
.up_drp_ready (up_drp_ready),
.up_drp_locked (up_drp_locked));
end
if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 0)) begin
BUFR #(.BUFR_DIVIDE("BYPASS")) i_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (clk));
assign div_clk = clk;
end
if ((MMCM_OR_BUFR_N == 0) && (SERDES_OR_DDR_N == 1)) begin
BUFIO i_clk_buf (
.I (clk_in_s),
.O (clk));
BUFR #(.BUFR_DIVIDE("4")) i_div_clk_buf (
.CLR (1'b0),
.CE (1'b1),
.I (clk_in_s),
.O (div_clk));
end
endgenerate
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* TOP2049 Open Source programming suite
*
* Universal device tester
* FPGA bottomhalf implementation
*
* Copyright (c) 2010-2012 Michael Buesch <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
`include "common.vh"
`BOTTOMHALF_BEGIN(unitest, 8, 1)
reg [47:0] zif_output_en;
reg [47:0] zif_output;
reg [47:0] zif_osc_en;
reg zif_osc;
reg [23:0] osc_divider;
reg [23:0] osc_div_cnt;
`INITIAL_NONE
always @(posedge osc_signal) begin
if (osc_div_cnt + 1 >= osc_divider) begin
osc_div_cnt <= 0;
zif_osc <= ~zif_osc;
end else begin
osc_div_cnt <= osc_div_cnt + 1;
end
end
`DATAWRITE_BEGIN
/* osc_divider is rightshifted by one and thus divided by two,
* because the oscillator always additionally divides by two. */
`ADDR(8'h00): osc_divider[6:0] <= in_data >> 1;
`ADDR(8'h01): osc_divider[14:7] <= in_data;
`ADDR(8'h02): osc_divider[22:15] <= in_data;
`ADDR(8'h03): osc_divider[23] <= in_data[0];
`ADDR(8'h20): zif_osc_en[7:0] <= in_data;
`ADDR(8'h21): zif_osc_en[15:8] <= in_data;
`ADDR(8'h22): zif_osc_en[23:16] <= in_data;
`ADDR(8'h23): zif_osc_en[31:24] <= in_data;
`ADDR(8'h24): zif_osc_en[39:32] <= in_data;
`ADDR(8'h25): zif_osc_en[47:40] <= in_data;
`ADDR(8'h40): zif_output_en[7:0] <= in_data;
`ADDR(8'h41): zif_output_en[15:8] <= in_data;
`ADDR(8'h42): zif_output_en[23:16] <= in_data;
`ADDR(8'h43): zif_output_en[31:24] <= in_data;
`ADDR(8'h44): zif_output_en[39:32] <= in_data;
`ADDR(8'h45): zif_output_en[47:40] <= in_data;
`ADDR(8'h60): zif_output[7:0] <= in_data;
`ADDR(8'h61): zif_output[15:8] <= in_data;
`ADDR(8'h62): zif_output[23:16] <= in_data;
`ADDR(8'h63): zif_output[31:24] <= in_data;
`ADDR(8'h64): zif_output[39:32] <= in_data;
`ADDR(8'h65): zif_output[47:40] <= in_data;
`DATAWRITE_END
`DATAREAD_BEGIN
`ADDR(8'h60): out_data <= zif[8:1];
`ADDR(8'h61): out_data <= zif[16:9];
`ADDR(8'h62): out_data <= zif[24:17];
`ADDR(8'h63): out_data <= zif[32:25];
`ADDR(8'h64): out_data <= zif[40:33];
`ADDR(8'h65): out_data <= zif[48:41];
`DATAREAD_END
bufif1(zif[1], zif_output[0] | (zif_osc & zif_osc_en[0]), zif_output_en[0]);
bufif1(zif[2], zif_output[1] | (zif_osc & zif_osc_en[1]), zif_output_en[1]);
bufif1(zif[3], zif_output[2] | (zif_osc & zif_osc_en[2]), zif_output_en[2]);
bufif1(zif[4], zif_output[3] | (zif_osc & zif_osc_en[3]), zif_output_en[3]);
bufif1(zif[5], zif_output[4] | (zif_osc & zif_osc_en[4]), zif_output_en[4]);
bufif1(zif[6], zif_output[5] | (zif_osc & zif_osc_en[5]), zif_output_en[5]);
bufif1(zif[7], zif_output[6] | (zif_osc & zif_osc_en[6]), zif_output_en[6]);
bufif1(zif[8], zif_output[7] | (zif_osc & zif_osc_en[7]), zif_output_en[7]);
bufif1(zif[9], zif_output[8] | (zif_osc & zif_osc_en[8]), zif_output_en[8]);
bufif1(zif[10], zif_output[9] | (zif_osc & zif_osc_en[9]), zif_output_en[9]);
bufif1(zif[11], zif_output[10] | (zif_osc & zif_osc_en[10]), zif_output_en[10]);
bufif1(zif[12], zif_output[11] | (zif_osc & zif_osc_en[11]), zif_output_en[11]);
bufif1(zif[13], zif_output[12] | (zif_osc & zif_osc_en[12]), zif_output_en[12]);
bufif1(zif[14], zif_output[13] | (zif_osc & zif_osc_en[13]), zif_output_en[13]);
bufif1(zif[15], zif_output[14] | (zif_osc & zif_osc_en[14]), zif_output_en[14]);
bufif1(zif[16], zif_output[15] | (zif_osc & zif_osc_en[15]), zif_output_en[15]);
bufif1(zif[17], zif_output[16] | (zif_osc & zif_osc_en[16]), zif_output_en[16]);
bufif1(zif[18], zif_output[17] | (zif_osc & zif_osc_en[17]), zif_output_en[17]);
bufif1(zif[19], zif_output[18] | (zif_osc & zif_osc_en[18]), zif_output_en[18]);
bufif1(zif[20], zif_output[19] | (zif_osc & zif_osc_en[19]), zif_output_en[19]);
bufif1(zif[21], zif_output[20] | (zif_osc & zif_osc_en[20]), zif_output_en[20]);
bufif1(zif[22], zif_output[21] | (zif_osc & zif_osc_en[21]), zif_output_en[21]);
bufif1(zif[23], zif_output[22] | (zif_osc & zif_osc_en[22]), zif_output_en[22]);
bufif1(zif[24], zif_output[23] | (zif_osc & zif_osc_en[23]), zif_output_en[23]);
bufif1(zif[25], zif_output[24] | (zif_osc & zif_osc_en[24]), zif_output_en[24]);
bufif1(zif[26], zif_output[25] | (zif_osc & zif_osc_en[25]), zif_output_en[25]);
bufif1(zif[27], zif_output[26] | (zif_osc & zif_osc_en[26]), zif_output_en[26]);
bufif1(zif[28], zif_output[27] | (zif_osc & zif_osc_en[27]), zif_output_en[27]);
bufif1(zif[29], zif_output[28] | (zif_osc & zif_osc_en[28]), zif_output_en[28]);
bufif1(zif[30], zif_output[29] | (zif_osc & zif_osc_en[29]), zif_output_en[29]);
bufif1(zif[31], zif_output[30] | (zif_osc & zif_osc_en[30]), zif_output_en[30]);
bufif1(zif[32], zif_output[31] | (zif_osc & zif_osc_en[31]), zif_output_en[31]);
bufif1(zif[33], zif_output[32] | (zif_osc & zif_osc_en[32]), zif_output_en[32]);
bufif1(zif[34], zif_output[33] | (zif_osc & zif_osc_en[33]), zif_output_en[33]);
bufif1(zif[35], zif_output[34] | (zif_osc & zif_osc_en[34]), zif_output_en[34]);
bufif1(zif[36], zif_output[35] | (zif_osc & zif_osc_en[35]), zif_output_en[35]);
bufif1(zif[37], zif_output[36] | (zif_osc & zif_osc_en[36]), zif_output_en[36]);
bufif1(zif[38], zif_output[37] | (zif_osc & zif_osc_en[37]), zif_output_en[37]);
bufif1(zif[39], zif_output[38] | (zif_osc & zif_osc_en[38]), zif_output_en[38]);
bufif1(zif[40], zif_output[39] | (zif_osc & zif_osc_en[39]), zif_output_en[39]);
bufif1(zif[41], zif_output[40] | (zif_osc & zif_osc_en[40]), zif_output_en[40]);
bufif1(zif[42], zif_output[41] | (zif_osc & zif_osc_en[41]), zif_output_en[41]);
bufif1(zif[43], zif_output[42] | (zif_osc & zif_osc_en[42]), zif_output_en[42]);
bufif1(zif[44], zif_output[43] | (zif_osc & zif_osc_en[43]), zif_output_en[43]);
bufif1(zif[45], zif_output[44] | (zif_osc & zif_osc_en[44]), zif_output_en[44]);
bufif1(zif[46], zif_output[45] | (zif_osc & zif_osc_en[45]), zif_output_en[45]);
bufif1(zif[47], zif_output[46] | (zif_osc & zif_osc_en[46]), zif_output_en[46]);
bufif1(zif[48], zif_output[47] | (zif_osc & zif_osc_en[47]), zif_output_en[47]);
`BOTTOMHALF_END
|
//#############################################################################
//# Function: Carry Save Adder (3:2) #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_csa32 #(parameter DW = 1 // data width
)
( input [DW-1:0] in0, //input
input [DW-1:0] in1,//input
input [DW-1:0] in2,//input
output [DW-1:0] s, //sum
output [DW-1:0] c //carry
);
`ifdef CFG_ASIC
genvar i;
for (i=0;i<DW;i=i+1)
begin
asic_csa32 asic_csa32 (.s(s[i]),
.c(c[i]),
.in2(in2[i]),
.in1(in1[i]),
.in0(in0[i]));
end
`else
assign s[DW-1:0] = in0[DW-1:0] ^ in1[DW-1:0] ^ in2[DW-1:0];
assign c[DW-1:0] = (in0[DW-1:0] & in1[DW-1:0]) |
(in1[DW-1:0] & in2[DW-1:0]) |
(in2[DW-1:0] & in0[DW-1:0] );
`endif // !`ifdef CFG_ASIC
endmodule // oh_csa32
|
/*
This file is part of Fusion-Core-ISA.
Fusion-Core-ISA is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
Fusion-Core-ISA is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with Fusion-Core-ISA. If not, see <http://www.gnu.org/licenses/>.
*/
module shift_right_32(
input[31:0] a, //value to be shifted
output[31:0] out //output
);
//shifts everything right by 1
assign out[0] = a[1];
assign out[1] = a[2];
assign out[2] = a[3];
assign out[3] = a[4];
assign out[4] = a[5];
assign out[5] = a[6];
assign out[6] = a[7];
assign out[7] = a[8];
assign out[8] = a[9];
assign out[9] = a[10];
assign out[10] = a[11];
assign out[11] = a[12];
assign out[12] = a[13];
assign out[13] = a[14];
assign out[14] = a[15];
assign out[15] = a[16];
assign out[16] = a[17];
assign out[17] = a[18];
assign out[18] = a[19];
assign out[19] = a[20];
assign out[20] = a[21];
assign out[21] = a[22];
assign out[22] = a[23];
assign out[23] = a[24];
assign out[24] = a[25];
assign out[25] = a[26];
assign out[26] = a[27];
assign out[27] = a[28];
assign out[28] = a[29];
assign out[29] = a[30];
assign out[30] = a[31];
assign out[31] = a[31];
endmodule
|
// file: SystemClockUnit_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge LOCKED)
module SystemClockUnit_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
// Status and control signals
wire LOCKED;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
reg [13:0] timeout_counter = 14'b00000000000000;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
$display ("Timing checks are not valid");
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*19.5)
COUNTER_RESET = 0;
#(PER1*1)
$display ("Timing checks are valid");
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
always@(posedge CLK_IN1) begin
timeout_counter <= timeout_counter + 1'b1;
if (timeout_counter == 14'b10000000000000) begin
if (LOCKED != 1'b1) begin
$display("ERROR : NO LOCK signal");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
end
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
SystemClockUnit_exdes
dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT),
// Status and control signals
.LOCKED (LOCKED));
// Freq Check
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
// IP Revision: 8
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dist_mem_gen_0 (
a,
spo
);
input wire [14 : 0] a;
output wire [7 : 0] spo;
dist_mem_gen_v8_0 #(
.C_FAMILY("zynq"),
.C_ADDR_WIDTH(15),
.C_DEFAULT_DATA("0"),
.C_DEPTH(32768),
.C_HAS_CLK(0),
.C_HAS_D(0),
.C_HAS_DPO(0),
.C_HAS_DPRA(0),
.C_HAS_I_CE(0),
.C_HAS_QDPO(0),
.C_HAS_QDPO_CE(0),
.C_HAS_QDPO_CLK(0),
.C_HAS_QDPO_RST(0),
.C_HAS_QDPO_SRST(0),
.C_HAS_QSPO(0),
.C_HAS_QSPO_CE(0),
.C_HAS_QSPO_RST(0),
.C_HAS_QSPO_SRST(0),
.C_HAS_SPO(1),
.C_HAS_WE(0),
.C_MEM_INIT_FILE("dist_mem_gen_0.mif"),
.C_ELABORATION_DIR("./"),
.C_MEM_TYPE(0),
.C_PIPELINE_STAGES(0),
.C_QCE_JOINED(0),
.C_QUALIFY_WE(0),
.C_READ_MIF(1),
.C_REG_A_D_INPUTS(0),
.C_REG_DPRA_INPUT(0),
.C_SYNC_ENABLE(1),
.C_WIDTH(8),
.C_PARSER_TYPE(1)
) inst (
.a(a),
.d(8'B0),
.dpra(15'B0),
.clk(1'D0),
.we(1'D0),
.i_ce(1'D1),
.qspo_ce(1'D1),
.qdpo_ce(1'D1),
.qdpo_clk(1'D0),
.qspo_rst(1'D0),
.qdpo_rst(1'D0),
.qspo_srst(1'D0),
.qdpo_srst(1'D0),
.spo(spo),
.dpo(),
.qspo(),
.qdpo()
);
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:clk_gen:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module kuuga_test_harness_clk_gen_0_0 (
clk,
sync_rst
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk CLK" *)
output wire clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 sync_rst RST" *)
output wire sync_rst;
clk_gen #(
.CLOCK_PERIOD(10),
.INITIAL_RESET_CLOCK_CYCLES(250),
.RESET_POLARITY(1)
) inst (
.clk(clk),
.clk_n(),
.clk_p(),
.sync_rst(sync_rst)
);
endmodule
|
/*
* HIFIFO: Harmon Instruments PCI Express to FIFO
* Copyright (C) 2014 Harmon Instruments, LLC
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/
*/
`timescale 1ns/1ps
module hififo_tpc_fifo
(
input clock,
input reset,
output [31:0] status,
output interrupt,
// writes and read completions
input [63:0] rx_data,
input rx_data_valid,
// to PCI TX
output reg wr_valid = 0,
input wr_ready,
output [63:0] wr_data,
output [63:0] wr_addr,
output reg wr_last,
// FIFO
input fifo_clock,
input fifo_write,
input [63:0] fifo_data,
output fifo_ready
);
reg [4:0] state = 0;
wire o_almost_empty;
wire request_valid;
wire fifo_read = (wr_ready && wr_valid)
|| ((state != 0) && (state < 30));
always @ (posedge clock)
begin
if(reset)
wr_valid <= 1'b0;
else
wr_valid <= ((state == 0) || (state > 29))
&& request_valid && ~o_almost_empty;
wr_last <= state == 29;
if(reset)
state <= 1'b0;
else if(state == 0)
state <= wr_ready ? 5'd15 : 5'd0;
else
state <= state + 1'b1;
end
fwft_fifo #(.NBITS(64)) data_fifo
(
.reset(reset),
.i_clock(fifo_clock),
.i_data(fifo_data),
.i_valid(fifo_write),
.i_ready(fifo_ready),
.o_clock(clock),
.o_read(fifo_read),
.o_data(wr_data),
.o_valid(),
.o_almost_empty(o_almost_empty)
);
hififo_fetch_descriptor #(.BS(3)) fetch_descriptor
(
.clock(clock),
.reset(reset),
.request_addr(wr_addr),
.request_valid(request_valid),
.request_ack(fifo_read),
.wvalid(rx_data_valid),
.wdata(rx_data),
.status(status),
.interrupt(interrupt)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR2B_SYMBOL_V
`define SKY130_FD_SC_HDLL__NOR2B_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR2B_SYMBOL_V
|
`include "define.v"
`define primitive_op1(name, op, inT, outT) \
module __primitive_``name`` #( \
parameter in0N = `inT``N, \
parameter out0N = `outT``N \
)( \
`input(simple, in0N, 0), \
`output(simple, out0N, 0) \
); \
assign out0 = op in0; \
endmodule
`define primitive_op2(name, op, inT, outT) \
module __primitive_``name`` #( \
parameter in0N = `inT``N, \
parameter in1N = `inT``N, \
parameter out0N = `outT``N \
)( \
`input(simple, in0N, 0), \
`input(simple, in1N, 1), \
`output(simple, out0N, 0) \
); \
assign out0 = in0 op in1; \
endmodule
`primitive_op2(eq, ==, int, sym)
`primitive_op2(neq, !=, int, sym)
`primitive_op2(mod, %, int, int)
`primitive_op2(div, /, int, int)
`primitive_op1(not, !, sym, sym)
`primitive_op2(mul, *, int, int)
`primitive_op2(add, +, int, int)
`primitive_op2(sub, -, int, int)
`primitive_op2(shiftl, <<, int, int)
`primitive_op2(shiftr, >>, int, int)
`primitive_op2(gt, >, int, sym)
`primitive_op2(gte, >=, int, sym)
`primitive_op2(lt, <, int, sym)
`primitive_op2(lte, <=, int, sym)
`primitive_op1(complement, ~, int, int)
`primitive_op2(bitand, &, int, int)
`primitive_op2(bitor, |, int, int)
`primitive_op2(bitxor, ^, int, int)
module __primitive_ap01 #(
parameter in0N = `intN,
parameter out1N = `intN,
parameter out0N = 0
)(
`sync_ports,
`input(stream, in0N, 0),
`output(stream, out0N, 0),
`output(simple, out1N, 1)
);
assign out0 = in0 >> out1N;
assign out1 = in0;
assign out0_valid = in0_valid;
assign out_valid = in0_valid && `valid(out1);
assign in0_ready = out0_ready & out_ready;
assign in_ready = `true;
endmodule
module __primitive_ap02 #(
parameter in0N = `intN,
parameter out1N = `intN,
parameter out2N = `intN,
parameter out0N = 0
)(
`sync_ports,
`input(stream, in0N, 0),
`output(stream, out0N, 0),
`output(simple, out1N, 1),
`output(simple, out2N, 2)
);
assign out0 = in0 >> (out1N + out2N);
assign out1 = in0 >> out2N;
assign out2 = in0;
assign out0_valid = in0_valid;
assign out_valid = in0_valid && `valid(out1) && `valid(out2);
assign in0_ready = out0_ready & out_ready;
assign in_ready = `true;
endmodule
/* ------------------------------------------------------ *
NOTE ON READY/VALID DEPENDENCIES
* ------------------------------------------------------ *
`in_ready` can depend on `in_valid` asynchronously,
but `out_valid` cannot depend on `out_ready`.
This is to prevent loops, so that the
flow is from source to sink and back.
* ------------------------------------------------------ */
module __primitive_ap20 #(
parameter in0N = `intN,
parameter in1N = `intN,
parameter in2N = `intN,
parameter out0N = in0N + in1N + in2N
)(
`sync_ports,
`input(simple, in0N, 0),
`input(simple, in1N, 1),
`input(stream, in2N, 2),
`output(stream, out0N, 0)
);
assign out0 = { in0, in1, in2 };
assign out0_valid = in_valid & in2_valid;
assign in2_ready = out0_ready;
assign in_ready = in_valid & out0_ready;
assign out_valid = `true;
endmodule
module __primitive_pushr1 #(
parameter in0N = `intN,
parameter in1N = `intN,
parameter out0N = `intN
)(
`sync_ports,
`input(stream, in0N, 0),
`input(simple, in1N, 1),
`output(stream, out0N, 0)
);
assign out0 = { in0, in1 };
assign out0_valid = in_valid & in0_valid;
assign in0_ready = out0_ready;
assign in_ready = in_valid & out0_ready;
assign out_valid = `true;
endmodule
module __primitive_pushr2 #(
parameter in0N = `intN,
parameter in1N = `intN,
parameter in2N = `intN,
parameter out0N = in0N + in1N + in2N
)(
`sync_ports,
`input(stream, in0N, 0),
`input(simple, in1N, 1),
`input(simple, in2N, 2),
`output(stream, out0N, 0)
);
assign out0 = { in0, in1, in2 };
assign out0_valid = in_valid & in0_valid;
assign in0_ready = out0_ready;
assign in_ready = in_valid & out0_ready;
assign out_valid = `true;
endmodule
module transparent_buffer #(
parameter N = `intN
)(
input wire clk,
input wire nrst,
`input(stream, N, 0),
`output(stream, N, 0)
);
reg [N-1:0] data;
reg data_valid;
assign in0_ready = !data_valid | out0_ready;
assign out0_valid = data_valid | in0_valid;
assign out0 = !data_valid ? in0 : data; // transparent when ready & valid
always @(posedge clk) begin
if(!nrst) begin // reset
`reset(data_valid);
end
else begin
if(!in0_valid && out0_ready) begin // drain
`reset(data_valid);
end
else if(in0_valid && !out0_ready) begin // fill
data <= in0;
if(!out0_ready) `set(data_valid);
end
end
end
endmodule
module __primitive_read_array #(
parameter in0AN = `addrN,
parameter in0DN = `intN,
parameter in1N = `intN,
parameter out1N = `intN,
parameter out0AN = `addrN,
parameter out0DN = `intN
)(
`sync_ports,
`input(Array, (in0AN, in0DN), 0),
`input(simple, in1N, 1),
`output(Array, (out0AN, out0DN), 0),
`output(simple, out1N, 1)
);
reg pending;
wire buf_ready;
// three-way setup:
// 1. <- ready
// 2. -> valid (active)
// 3. <- addr, we, di (success)
wire active = in_valid & buf_ready & !pending & nrst;
wire success = active & in0_valid;
assign in0_addr = success ? in1 : out0_addr;
assign in0_we = !success & out0_we;
assign in0_di = out0_di;
assign out0 = in0;
assign in0_ready = active | out0_ready;
assign out0_valid = !active & in0_valid;
assign in_ready = active & in0_valid;
transparent_buffer #(.N(out1N))
buffer(.clk(clk),
.nrst(nrst),
.in0(in0),
.in0_valid(in0_valid & !pending),
.in0_ready(buf_ready),
.out0(out1),
.out0_valid(out_valid),
.out0_ready(out_ready));
always @(posedge clk) begin
if(!nrst) `reset(pending);
else if(in_ready) pending <= out0_ready;
end
endmodule
module __primitive_write_array #(
parameter in0AN = `addrN,
parameter in0DN = `intN,
parameter in1N = `intN,
parameter in2N = `intN,
parameter out0AN = `addrN,
parameter out0DN = `intN
)(
`sync_ports,
`input(Array, (in0AN, in0DN), 0),
`input(simple, in1N, 1),
`input(simple, in2N, 2),
`output(Array, (out0AN, out0DN), 0)
);
reg pending;
// three-way setup:
// 1. <- ready
// 2. -> valid (active)
// 3. <- addr, we, di (success)
wire active = in_valid & !pending & nrst;
wire success = active & in0_valid;
assign in0_addr = success ? in1 : out0_addr;
assign in0_we = success | out0_we;
assign in0_di = success ? in2 : out0_di;
assign out0 = in0;
assign out_valid = `true;
assign in0_ready = active | out0_ready;
assign out0_valid = !active & in0_valid;
assign in_ready = active & in0_valid;
always @(posedge clk) begin
if(!nrst) `reset(pending);
else if(in_ready) pending <= out0_ready;
end
endmodule
module dup_stream #(
parameter N = 1
)(
input wire clk,
input wire in_valid,
output wire in_ready,
output wire [N-1:0] out_valid,
input wire [N-1:0] out_ready
);
generate
if(N == 1) begin
assign in_ready = out_ready[0];
assign out_valid[0] = in_valid;
end
else begin
reg [0:N-1] pending_prev;
assign in_ready = ~| pending;
assign out_valid = in_valid ? pending_prev : 0;
wire [0:N-1] pending = pending_prev & ~out_ready;
always @(posedge clk) begin
pending_prev <= in_ready ? ~0 : pending;
end
end
endgenerate
endmodule
module dup_Array #(
parameter N = 1
)(
input wire clk,
input wire in_valid,
output wire in_ready,
output wire [0:N-1] out_valid,
input wire [0:N-1] out_ready
);
generate
if(N == 1) begin
assign in_ready = out_ready;
assign out_valid = in_valid;
end
else begin
reg [0:N-1] done;
assign in_ready = | out_ready;
assign out_valid = in_valid ? pending & ~(pending - 1) : 0; // select MSB
wire [0:N-1] pending = out_ready & ~done;
always @(posedge clk) begin
done <= pending & ~out_valid ? done | out_valid : 0;
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31OI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A31OI_PP_SYMBOL_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31OI_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_0_V
`define SKY130_FD_SC_LP__A21BO_0_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21bo with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21bo.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_0 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21bo_0 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21bo base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_0_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFRBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DFRBP_FUNCTIONAL_PP_V
/**
* dfrbp: Delay flop, inverted reset, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_df_p_r_pg/sky130_fd_sc_hs__u_df_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dfrbp (
VPWR ,
VGND ,
Q ,
Q_N ,
CLK ,
D ,
RESET_B
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input CLK ;
input D ;
input RESET_B;
// Local signals
wire buf_Q;
wire RESET;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hs__u_df_p_r_pg `UNIT_DELAY u_df_p_r_pg0 (buf_Q , D, CLK, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not1 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFRBP_FUNCTIONAL_PP_V |
//
// CONFIDENTIAL AND PROPRIETARY SOFTWARE OF ARM Physical IP, INC.
//
// Copyright (c) 1993-2013 ARM Physical IP, Inc. All Rights Reserved.
//
// Use of this Software is subject to the terms and conditions of the
// applicable license agreement with ARM Physical IP, Inc. In addition,
// this Software is protected by patents, copyright law and international
// treaties.
//
// The copyright notice(s) in this Software does not indicate actual or
// intended publication of this Software.
//
// name: Advantage Single-Port Register File Generator
// TSMC 90nm CLN90G Process
// version: 2007Q2V1
// comment:
// configuration: -instname "I_Cache" -words 128 -bits 32 -frequency 100 -ring_width 2.0 -mux 1 -write_mask off -wp_size 8 -top_layer "met5-9" -power_type rings -horiz met3 -vert met2 -redundancy off -rcols 1 -rrows 0 -bmux off -ema on -cust_comment "" -bus_notation on -left_bus_delim "[" -right_bus_delim "]" -pwr_gnd_rename "VDD:VDD,VSS:VSS" -prefix "" -pin_space 0.0 -name_case upper -check_instname on -diodes on -inside_ring_type VSS -drive 4 -asvm off -corners ff_1.1_-40.0,ff_1.1_125.0,tt_1.0_25.0,ss_0.9_125.0
//
// Verilog model for Synchronous Single-Port Register File
//
// Instance Name: I_Cache
// Words: 128
// Bits: 32
// Mux: 1
// Drive: 4
// Write Mask: Off
// Extra Margin Adjustment: On
// Accelerated Retention Test: Off
// Redundant Rows: 0
// Redundant Columns: 0
// Test Muxes Off
//
// Creation Date: 2013-03-11 09:15:48Z
// Version: 2007Q2V1
//
// Modeling Assumptions: This model supports full gate level simulation
// including proper x-handling and timing check behavior. Unit
// delay timing is included in the model. Back-annotation of SDF
// (v2.1) is supported. SDF can be created utilyzing the delay
// calculation views provided with this generator and supported
// delay calculators. All buses are modeled [MSB:LSB]. All
// ports are padded with Verilog primitives.
//
// Modeling Limitations: None.
//
// Known Bugs: None.
//
// Known Work Arounds: N/A
//
`timescale 1 ns/1 ps
`celldefine
module I_Cache (
Q,
CLK,
CEN,
WEN,
A,
D,
EMA
);
parameter BITS = 32;
parameter WORD_DEPTH = 128;
parameter ADDR_WIDTH = 7;
parameter WORDX = {BITS{1'bx}};
parameter WORD1 = {BITS{1'b1}};
parameter ADDRX = {ADDR_WIDTH{1'bx}};
parameter ADDR1 = {ADDR_WIDTH{1'b1}};
parameter WEN_WIDTH = 1;
parameter WP_SIZE = 32 ;
parameter RCOLS = 0;
parameter MASKX = {WEN_WIDTH{1'bx}};
parameter MASK1 = {WEN_WIDTH{1'b1}};
parameter MASK0 = {WEN_WIDTH{1'b0}};
parameter MUX = 1;
parameter COL_ADDR_WIDTH = 0;
parameter RROWS = 0;
parameter UPM_WIDTH = 3;
parameter UPM0 = {UPM_WIDTH{1'b0}};
parameter RCA_WIDTH = 1;
parameter RED_COLUMNS = 1;
output [31:0] Q;
input CLK;
input CEN;
input WEN;
input [6:0] A;
input [31:0] D;
input [2:0] EMA;
reg [BITS+RED_COLUMNS-1:0] mem [0:WORD_DEPTH-1];
reg [BITS+RED_COLUMNS-1:0] rows [(MUX*4)-1:0]; // added 2 bits for column redundancy
reg NOT_CEN;
reg NOT_WEN;
reg NOT_A6;
reg NOT_A5;
reg NOT_A4;
reg NOT_A3;
reg NOT_A2;
reg NOT_A1;
reg NOT_A0;
reg [ADDR_WIDTH-1:0] NOT_A;
reg NOT_D31;
reg NOT_D30;
reg NOT_D29;
reg NOT_D28;
reg NOT_D27;
reg NOT_D26;
reg NOT_D25;
reg NOT_D24;
reg NOT_D23;
reg NOT_D22;
reg NOT_D21;
reg NOT_D20;
reg NOT_D19;
reg NOT_D18;
reg NOT_D17;
reg NOT_D16;
reg NOT_D15;
reg NOT_D14;
reg NOT_D13;
reg NOT_D12;
reg NOT_D11;
reg NOT_D10;
reg NOT_D9;
reg NOT_D8;
reg NOT_D7;
reg NOT_D6;
reg NOT_D5;
reg NOT_D4;
reg NOT_D3;
reg NOT_D2;
reg NOT_D1;
reg NOT_D0;
reg [BITS-1:0] NOT_D;
reg NOT_EMA2;
reg NOT_EMA1;
reg NOT_EMA0;
reg [UPM_WIDTH-1:0] NOT_EMA;
reg NOT_CLK_PER;
reg NOT_CLK_MINH;
reg NOT_CLK_MINL;
reg LAST_NOT_CEN;
reg LAST_NOT_WEN;
reg [ADDR_WIDTH-1:0] LAST_NOT_A;
reg [BITS-1:0] LAST_NOT_D;
reg [UPM_WIDTH-1:0] LAST_NOT_EMA;
reg LAST_NOT_CLK_PER;
reg LAST_NOT_CLK_MINH;
reg LAST_NOT_CLK_MINL;
wire [BITS-1:0] _Q;
wire _CLK;
wire _CEN;
wire _WEN;
wire [ADDR_WIDTH-1:0] _A;
wire [BITS-1:0] _D;
wire [UPM_WIDTH-1:0] _EMA;
wire CEN_flag;
wire TCEN_flag;
wire flag;
wire D_flag;
wire cyc_flag;
wire EMA2eq0andEMA1eq0andEMA0eq0;
wire EMA2eq0andEMA1eq0andEMA0eq1;
wire EMA2eq0andEMA1eq1andEMA0eq0;
wire EMA2eq0andEMA1eq1andEMA0eq1;
wire EMA2eq1andEMA1eq0andEMA0eq0;
wire EMA2eq1andEMA1eq0andEMA0eq1;
wire EMA2eq1andEMA1eq1andEMA0eq0;
wire EMA2eq1andEMA1eq1andEMA0eq1;
reg LATCHED_CEN;
reg LATCHED_WEN;
reg [ADDR_WIDTH-1:0] LATCHED_A;
reg [BITS-1:0] LATCHED_D;
reg [UPM_WIDTH-1:0] LATCHED_EMA;
reg [BITS-1:0] Qi;
reg [BITS-1:0] LAST_Qi;
reg [BITS-1:0] dummy_qb;
reg LAST_CLK;
reg [BITS+RED_COLUMNS-1:0] last_status [(MUX*2)-1:0];
task update_notifier_buses;
begin
NOT_A = {
NOT_A6,
NOT_A5,
NOT_A4,
NOT_A3,
NOT_A2,
NOT_A1,
NOT_A0};
NOT_D = {
NOT_D31,
NOT_D30,
NOT_D29,
NOT_D28,
NOT_D27,
NOT_D26,
NOT_D25,
NOT_D24,
NOT_D23,
NOT_D22,
NOT_D21,
NOT_D20,
NOT_D19,
NOT_D18,
NOT_D17,
NOT_D16,
NOT_D15,
NOT_D14,
NOT_D13,
NOT_D12,
NOT_D11,
NOT_D10,
NOT_D9,
NOT_D8,
NOT_D7,
NOT_D6,
NOT_D5,
NOT_D4,
NOT_D3,
NOT_D2,
NOT_D1,
NOT_D0};
NOT_EMA = {
NOT_EMA2,
NOT_EMA1,
NOT_EMA0};
end
endtask
task mem_cycle;
inout [BITS-1:0] q;
inout [BITS-1:0] other_q;
input cen;
input [WEN_WIDTH-1:0] wen;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input [UPM_WIDTH-1:0] ema;
input artn;
input ten;
input ben;
input tcen;
input [WEN_WIDTH-1:0] twen;
input [ADDR_WIDTH-1:0] ta;
input [BITS-1:0] td;
input rren;
input rra;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input contention_flag;
input [BITS-1:0] other_cren;
input port; // 0 for A port, 1 for B port
integer mask_section ;
integer lsb ;
integer msb ;
reg CENi;
reg [WEN_WIDTH-1:0] WENi;
reg [ADDR_WIDTH-1:0] Ai;
reg [BITS-1:0] Di;
reg ValidDummyPinsi;
begin
CENi = ten ? cen : tcen;
Ai = ten ? a : ta;
WENi = ten ? wen : twen;
Di = ten ? d : td;
ValidDummyPinsi = (^({ema,artn}) !== 1'bx);
if ( (artn !== 1'b1) & (WENi !== MASK1) & (WENi !== MASK0))
begin
$display("ARTN is active and all bits of WEN are not active or inactive");
$display("Setting WEN bus to x");
WENi = MASKX;
end
if (!valid_cren(cren))
begin
$display("CREN is in an invalid state");
$display("Setting CREN bus to x");
cren = WORDX;
end
for (mask_section=0;mask_section<WEN_WIDTH; mask_section=mask_section+1)
begin
lsb = (mask_section)*(WP_SIZE) ;
msb = BITS <= (lsb+WP_SIZE-1) ? (BITS-1) : (lsb+WP_SIZE-1) ;
casez({WENi[mask_section],CENi,ValidDummyPinsi})
3'b101: begin
read_mem(q,other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,0,contention_flag,port);
end
3'b001: begin
write_mem(other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,0,contention_flag,other_cren,port);
write_thru(q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,0);
end
3'b?1?: ;
3'b10?,
3'b1x?: begin
read_mem(q,other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,port);
end
3'b00?,
3'b0x?: begin
write_mem(other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,other_cren,port);
write_thru(q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1);
end
3'bx0?,
3'bxx?: begin
write_mem(other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,other_cren,port);
read_mem(q,other_q,Ai,Di,rren,rra,cren,1'b0,
msb,lsb,1,contention_flag,port);
end
endcase
end
end
endtask
task read_mem;
inout [BITS-1:0] q;
inout [BITS-1:0] other_q;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input rren;
input radd;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input msb;
input lsb;
input xout;
input contention;
input port;
integer msb;
integer lsb;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
reg [BITS+RED_COLUMNS-1:0] other_status;
reg [BITS+RED_COLUMNS-1:0] status;
integer m;
integer n;
begin
if (rren === 1'bx)
begin
for (n=lsb; n<=msb; n=n+1) q[n] = 1'bx ;
x_mem;
x_rows;
end
else
begin
if (!valid_address(a,rren,radd))
begin
for (n=lsb; n<=msb; n=n+1) q[n] = 1'bx ;
if (rren === 1'b1)
begin
x_mem;
end
else if (rren === 1'b0)
begin
casez({radd,1'b0})
2'bxx: x_rows;
2'bx?: begin
x_row(0,1'b0);
x_row(1,1'b0);
end
2'b?x: begin
x_row(radd,0);
x_row(radd,1);
end
default:
x_row(radd,1'b0);
endcase
end
end
else
begin
if (rren === 1'b1)
tmpdata = mem[a];
else if (rren === 1'b0)
tmpdata = rows[{1'b0,radd}];
status = last_status[port];
other_status = last_status[!port];
for (n=lsb; n<=msb; n=n+1)
begin
if (cren[n] === 1'b1)
begin
if ((other_status[n] === 1'b0) & contention)
begin
tmpdata[n] = 1'bx;
q[n] = 1'bx;
end
else
begin
q[n] = xout ? 1'bx : tmpdata[n];
status[n] = 1'b1;
end
end
else if (cren[n] === 1'b0)
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
if ((other_status[n+rca+1] === 1'b0) & contention)
begin
tmpdata[n+rca+1] = 1'bx;
q[n] = 1'bx;
end
else
begin
q[n] = xout ? 1'bx : tmpdata[n+rca+1];
status[n+rca+1] = 1'b1;
end
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
if ((other_status[n+m+1] === 1'b0) & contention)
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b1;
end
q[n] = 1'bx;
end
else
begin
if ((other_status[n+1] === 1'b0) & contention)
begin
tmpdata[n+1] = 1'bx;
q[n] = 1'bx;
end
else
begin
q[n] = xout ? 1'bx : tmpdata[n+1];
status[n+1] = 1'b1;
end
end
end
else
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
if ((other_status[n+rca+1] === 1'b0) & contention)
tmpdata[n+rca+1] = 1'bx;
status[n] = 1'b1;
status[n+rca+1] = 1'b1;
q[n] = 1'bx;
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
for (m=0; m<RED_COLUMNS; m=m+1)
begin
if ((other_status[n+m+1] === 1'b0) & contention)
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b1;
end
status[n] = 1'b1;
q[n] = 1'bx;
end
else
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
if ((other_status[n+1] === 1'b0) & contention)
tmpdata[n+1] = 1'bx;
q[n] = 1'bx;
status[n] = 1'b1;
status[n+1] = 1'b1;
end
end
end
if (rren === 1'b1)
mem[a] = tmpdata;
else if (rren === 1'b0)
rows[{1'b0,radd}] = tmpdata;
last_status[port] = status;
if (msb == BITS-1)
begin
if (rren === 1'b1)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_mem(a,BITS+m,tmpdata[BITS+m]);
end
end
else if (rren === 1'b0)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_rows(a,BITS+m,tmpdata[BITS+m],radd,1'b0);
end
end
update_status(status,port);
end
end
end
end
endtask
task write_mem;
inout [BITS-1:0] other_q;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input rren;
input radd;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input msb;
input lsb;
input xout;
input contention;
input [BITS-1:0] other_cren;
input port;
integer msb;
integer lsb;
integer m;
integer n;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
reg [BITS+RED_COLUMNS-1:0] other_status;
reg [BITS+RED_COLUMNS-1:0] status;
reg [ADDR_WIDTH-1:0] tmpaddr;
begin
if (rren === 1'bx)
begin
x_mem;
x_rows;
end
else
begin
if (!valid_address(a,rren,radd))
begin
if (rren === 1'b1)
begin
x_mem;
end
else if (rren === 1'b0)
begin
casez({radd,1'b0})
2'bxx: x_rows;
2'bx?: begin
x_row(0,1'b0);
x_row(1,1'b0);
end
2'b?x: begin
x_row(radd,0);
x_row(radd,1);
end
default:
x_row(radd,1'b0);
endcase
end
end
else
begin
if (rren === 1'b1)
tmpdata = mem[a];
else if (rren === 1'b0)
tmpdata = rows[{1'b0,radd}];
status = last_status[port];
other_status = last_status[!port];
for (n=lsb; n<=msb; n=n+1)
begin
if (cren[n] === 1'b1)
begin
if ((other_status[n] === 1'b0) & contention)
tmpdata[n] = 1'bx;
else if ((other_status[n] === 1'b1) & contention)
begin
tmpdata[n] = 1'bx;
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
end
else
begin
tmpdata[n] = xout ? 1'bx : d[n];
status[n] = 1'b0;
end
if ((n < BITS-1) & (cren[n+1] === 1'b0))
begin
if ((other_status[n+1] === 1'b0) & contention)
tmpdata[n+1] = 1'bx;
else if ((other_status[n+1] === 1'b1) & contention)
begin
tmpdata[n+1] = 1'bx;
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
else if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
end
else
begin
tmpdata[n+1] = xout ? 1'bx : d[n];
status[n+1] = 1'b0;
end
end
else if ((n < BITS-1) & (cren[n+1] === 1'bx))
begin
tmpdata[n+1] = 1'bx;
status[n+1] = 1'b0;
if ((other_status[n+1] === 1'b1) & contention)
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
else if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
end
end
else if (cren[n] === 1'b0)
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
if ((other_status[n+rca+1] === 1'b0) & contention)
tmpdata[n+rca+1] = 1'bx;
else if ((other_status[n+rca+1] === 1'b1) & contention)
begin
tmpdata[n+rca+1] = 1'bx;
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
end
else
begin
tmpdata[n+rca+1] = xout ? 1'bx : d[n];
status[n+rca+1] = 1'b0;
end
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b0;
if ((other_status[n+m+1] === 1'b1) & contention)
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
end
end
else
begin
if ((other_status[n+1] === 1'b0) & contention)
tmpdata[n+1] = 1'bx;
else if ((other_status[n+1] === 1'b1) & contention)
begin
tmpdata[n+1] = 1'bx;
if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
else if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
end
else
begin
tmpdata[n+1] = xout ? 1'bx : d[n];
status[n+1] = 1'b0;
end
end
if (n === 0)
begin
if ((other_status[0] === 1'b0) & contention)
tmpdata[0] = 1'bx;
else if ((other_status[0] === 1'b1) & contention)
begin
tmpdata[0] = 1'bx;
if (other_cren[0] === 1'b1)
other_q[0] = 1'bx;
end
else
begin
tmpdata[0] = xout ? 1'bx : 1'b0;
status[0] = 1'b0;
end
end
end
else
begin
if ((n == BITS-1) & (^(rca) !== 1'bx))
begin
tmpdata[n] = 1'bx;
tmpdata[n+rca+1] = 1'bx;
status[n] = 1'b0;
status[n+rca+1] = 1'b0;
if ((other_status[n] === 1'b1) & contention)
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
if ((other_status[n+rca+1] === 1'b1) & contention)
other_q[n] = 1'bx;
end
else if ((n == BITS-1) & (^(rca) === 1'bx))
begin
tmpdata[n] = 1'bx;
status[n] = 1'b0;
for (m=0; m<RED_COLUMNS; m=m+1)
begin
tmpdata[n+m+1] = 1'bx;
status[n+m+1] = 1'b0;
if ((other_status[n+m+1] === 1'b1) & contention)
other_q[n] = 1'bx;
end
if ((other_status[n] === 1'b1) & contention)
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
end
else
begin
tmpdata[n] = 1'bx;
tmpdata[n+1] = 1'bx;
status[n] = 1'b0;
status[n+1] = 1'b0;
if ((other_status[n] === 1'b1) & contention)
if (other_cren[n] === 1'b1)
other_q[n] = 1'bx;
else if (other_cren[n-1] === 1'b0)
other_q[n-1] = 1'bx;
if ((other_status[n+1] === 1'b1) & contention)
if (other_cren[n+1] === 1'b1)
other_q[n+1] = 1'bx;
else if (other_cren[n] === 1'b0)
other_q[n] = 1'bx;
end
end
end
if (rren === 1'b1)
mem[a]=tmpdata;
else if (rren === 1'b0)
rows[{1'b0,radd}] = tmpdata;
last_status[port] = status;
// copy the redundent columns to all all combinations of ymux addresses
if (msb == BITS-1)
begin
if (rren === 1'b1)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_mem(a,BITS+m,tmpdata[BITS+m]);
end
end
else if (rren === 1'b0)
begin
for (m=0; m<RED_COLUMNS; m=m+1)
begin
replace_bit_in_rows(a,BITS+m,tmpdata[BITS+m],radd,1'b0);
end
end
update_status(status,port);
end
end
end
end
endtask
task write_thru;
inout [BITS-1:0] q;
input [ADDR_WIDTH-1:0] a;
input [BITS-1:0] d;
input rren;
input radd;
input [BITS-1:0] cren;
input [RCA_WIDTH-1:0] rca;
input msb;
input lsb;
input xout;
integer msb;
integer lsb;
integer n;
begin
if (^cren !== 1'bx)
for (n=lsb;n<=msb;n=n+1) q[n] = xout ? 1'bx : d[n] ;
else
for (n=lsb;n<=msb;n=n+1) q[n] = 1'bx ;
end
endtask
task update_last_notifiers;
begin
LAST_NOT_CEN = NOT_CEN;
LAST_NOT_WEN = NOT_WEN;
LAST_NOT_A = NOT_A;
LAST_NOT_D = NOT_D;
LAST_NOT_EMA = NOT_EMA;
LAST_NOT_CLK_PER = NOT_CLK_PER;
LAST_NOT_CLK_MINH = NOT_CLK_MINH;
LAST_NOT_CLK_MINL = NOT_CLK_MINL;
end
endtask
task latch_inputs;
begin
LATCHED_CEN = _CEN;
LATCHED_WEN = _WEN;
LATCHED_A = _A;
LATCHED_D = _D;
LATCHED_EMA = _EMA;
end
endtask
task x_inputs;
integer n;
begin
LATCHED_CEN = (NOT_CEN!==LAST_NOT_CEN) ? 1'bx : LATCHED_CEN ;
LATCHED_WEN = (NOT_WEN!==LAST_NOT_WEN) ? 1'bx : LATCHED_WEN ;
for (n=0; n<ADDR_WIDTH; n=n+1)
begin
LATCHED_A[n] = (NOT_A[n]!==LAST_NOT_A[n]) ? 1'bx : LATCHED_A[n] ;
end
for (n=0; n<BITS; n=n+1)
begin
LATCHED_D[n] = (NOT_D[n]!==LAST_NOT_D[n]) ? 1'bx : LATCHED_D[n] ;
end
for (n=0; n<UPM_WIDTH; n=n+1)
begin
LATCHED_EMA[n] = (NOT_EMA[n]!==LAST_NOT_EMA[n]) ? 1'bx : LATCHED_EMA[n] ;
end
end
endtask
task update_status;
input [BITS+RED_COLUMNS-1:0] val;
input port;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
integer n;
begin
for (n=0; n<=MUX-1; n=n+1)
begin
tmpdata = last_status[port];
tmpdata[BITS+RED_COLUMNS-1:BITS] = val[BITS+RED_COLUMNS-1:BITS];
last_status[port] = tmpdata;
end
end
endtask // update_status
task clear_status;
input port;
reg tmpaddr;
integer n;
begin
for (n=0; n<=MUX-1; n=n+1)
begin
tmpaddr = port;
last_status[tmpaddr] = {WORDX,{RED_COLUMNS{1'bx}}};
end
end
endtask // clear_status
task replace_bit_in_mem;
input [ADDR_WIDTH-1:0] a;
input pos;
input data;
integer pos;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
reg [ADDR_WIDTH-1:0] tmpaddr;
integer n;
begin
tmpdata = mem[a];
tmpdata[pos] = data;
mem[a] = tmpdata;
end
endtask // replace_bit_in_mem
task replace_bit_in_rows;
input [ADDR_WIDTH-1:0] a;
input pos;
input data;
input radd;
input bank_address;
integer pos;
reg [BITS+RED_COLUMNS-1:0] tmpdata;
integer n;
begin
tmpdata = rows[{bank_address,radd}];
tmpdata[pos] = data;
rows[{bank_address,radd}] = tmpdata;
end
endtask // replace_bit_in_rows
task x_mem;
integer n;
begin
for (n=0; n<WORD_DEPTH; n=n+1)
mem[n]={WORDX,{RED_COLUMNS{1'bx}}}; // add 2 bits for column redundancy
end
endtask
task x_rows;
integer n;
begin
for (n=0; n<MUX*4; n=n+1)
rows[n]={WORDX,{RED_COLUMNS{1'bx}}}; // add 2 bits for column redundancy
end
endtask
task x_row;
input radd;
input bank_address;
integer n;
reg [COL_ADDR_WIDTH+1:0] tmpaddr;
begin
for (n=0; n<MUX; n=n+1)
begin
tmpaddr = n;
tmpaddr[COL_ADDR_WIDTH] = radd;
tmpaddr[COL_ADDR_WIDTH+1] = bank_address;
rows[tmpaddr]={WORDX,{RED_COLUMNS{1'bx}}}; // add 2 bit for column redundancy
end
end
endtask // x_rows
task process_violations;
begin
if ((NOT_CLK_PER!==LAST_NOT_CLK_PER) ||
(NOT_CLK_MINH!==LAST_NOT_CLK_MINH) ||
(NOT_CLK_MINL!==LAST_NOT_CLK_MINL))
begin
if (LATCHED_CEN !== 1'b1)
begin
x_mem;
Qi = WORDX ;
end
end
else
begin
update_notifier_buses;
x_inputs;
mem_cycle(Qi,
dummy_qb,
LATCHED_CEN,
LATCHED_WEN,
LATCHED_A,
LATCHED_D,
LATCHED_EMA,
1'b1,
1'b1,
1'b1,
1'b1,
MASK1,
ADDR1,
WORD1,
1'b1,
1'b1,
WORD1,
1'b1,
1'b0,
WORD1,
0
);
end
update_last_notifiers;
end
endtask
function valid_address;
input [ADDR_WIDTH-1:0] a;
input rren;
input radd;
begin
if (rren === 1'b1)
valid_address = (^(a) !== 1'bx);
else if (rren === 1'b0)
valid_address = (^{radd} !== 1'bx);
else
valid_address = 0;
end
endfunction
function valid_cren;
input [BITS-1:0] cren;
reg [BITS-1:0] data;
begin
data = cren;
while (data[0] == 1'b1)
data = data >> 1;
if (~|data === 1'b1)
valid_cren = 1;
else
valid_cren = 0;
end
endfunction // valid_cren
function is_contention;
input [ADDR_WIDTH-1:0] aa;
input [ADDR_WIDTH-1:0] ab;
input [ADDR_WIDTH-1:0] taa;
input [ADDR_WIDTH-1:0] tab;
input rrena;
input rrenb;
input tena;
input tenb;
input rraa;
input rrab;
input [BITS-1:0] crena;
input [BITS-1:0] crenb;
input [RCA_WIDTH-1:0] rcaa;
input [RCA_WIDTH-1:0] rcab;
input [WEN_WIDTH-1:0] wena;
input [WEN_WIDTH-1:0] wenb;
input [WEN_WIDTH-1:0] twena;
input [WEN_WIDTH-1:0] twenb;
input cena;
input cenb;
input tcena;
input tcenb;
input artna;
input artnb;
reg [ADDR_WIDTH-1:0] adda;
reg [ADDR_WIDTH-1:0] addb;
reg [ADDR_WIDTH-1:COL_ADDR_WIDTH] row_adda;
reg [ADDR_WIDTH-1:COL_ADDR_WIDTH] row_addb;
reg add_colision;
reg col_add_colision;
reg row_add_colision;
reg rra_colision;
reg rca_colision;
reg both_ports_reading;
reg [WEN_WIDTH-1:0] wenai;
reg [WEN_WIDTH-1:0] wenbi;
begin
wenai = (tena ? wena : twena);
wenbi = (tenb ? wenb : twenb);
if ( (artna !== 1'b1) & (wenai !== MASK1) & (wenai !== MASK0))
wenai = MASKX;
if ( (artnb !== 1'b1) & (wenbi !== MASK1) & (wenbi !== MASK0))
wenbi = MASKX;
if (!valid_cren(crena))
crena = WORDX;
if (!valid_cren(crenb))
crenb = WORDX;
col_add_colision = 1'b1;
rra_colision = (rraa == rrab) | ((rraa == rrab) === 1'bx);
adda = (tena ? aa : taa);
addb = (tenb ? ab : tab);
add_colision = (adda == addb) | (^adda === 1'bx) | (^addb === 1'bx);
row_adda = (tena ? aa[ADDR_WIDTH-1:COL_ADDR_WIDTH] : taa[ADDR_WIDTH-1:COL_ADDR_WIDTH]);
row_addb = (tenb ? ab[ADDR_WIDTH-1:COL_ADDR_WIDTH] : tab[ADDR_WIDTH-1:COL_ADDR_WIDTH]);
row_add_colision = (row_adda == row_addb) | (^row_adda === 1'bx) | (^row_addb === 1'bx);
rca_colision = 1'b1;
both_ports_reading = (wenai === MASK1) &
(wenbi === MASK1);
is_contention =
// if either rrena or rrenb are unkown the whole memory is corrupted.
(((rrena === 1'bx) |
(rrenb === 1'bx) |
// in redundant row array
((rrena !== 1'b1) & (rrenb !== 1'b1) & ((rraa === 1'bx) | (rrab === 1'bx))) |
((rrena !== 1'b1) & (rrenb !== 1'b1) & col_add_colision & rra_colision) |
// in normal array
((rrena !== 1'b0) & (rrenb !== 1'b0) & add_colision) |
// redundant column in normal array
((rrena !== 1'b0) & (rrenb !== 1'b0) & row_add_colision &
(crena[BITS-1] !== 1'b1) & (crenb[BITS-1] !== 1'b1) & rca_colision) |
// redundant column in rednundant row
((rrena !== 1'b1) & (rrenb !== 1'b1) & rra_colision &
(crena[BITS-1] !== 1'b1) & (crenb[BITS-1] !== 1'b1) &
((wenai[WEN_WIDTH-1] !== 1'b1) | (wenbi[WEN_WIDTH-1] !== 1'b1)) &
rca_colision)) &
!both_ports_reading &
((tena ? cena : tcena) !== 1'b1) &
((tenb ? cenb : tcenb) !== 1'b1)) ;
end
endfunction
buf (Q[31], _Q[31]);
buf (Q[30], _Q[30]);
buf (Q[29], _Q[29]);
buf (Q[28], _Q[28]);
buf (Q[27], _Q[27]);
buf (Q[26], _Q[26]);
buf (Q[25], _Q[25]);
buf (Q[24], _Q[24]);
buf (Q[23], _Q[23]);
buf (Q[22], _Q[22]);
buf (Q[21], _Q[21]);
buf (Q[20], _Q[20]);
buf (Q[19], _Q[19]);
buf (Q[18], _Q[18]);
buf (Q[17], _Q[17]);
buf (Q[16], _Q[16]);
buf (Q[15], _Q[15]);
buf (Q[14], _Q[14]);
buf (Q[13], _Q[13]);
buf (Q[12], _Q[12]);
buf (Q[11], _Q[11]);
buf (Q[10], _Q[10]);
buf (Q[9], _Q[9]);
buf (Q[8], _Q[8]);
buf (Q[7], _Q[7]);
buf (Q[6], _Q[6]);
buf (Q[5], _Q[5]);
buf (Q[4], _Q[4]);
buf (Q[3], _Q[3]);
buf (Q[2], _Q[2]);
buf (Q[1], _Q[1]);
buf (Q[0], _Q[0]);
buf (_CLK, CLK);
buf (_CEN, CEN);
buf (_WEN, WEN);
buf (_A[6], A[6]);
buf (_A[5], A[5]);
buf (_A[4], A[4]);
buf (_A[3], A[3]);
buf (_A[2], A[2]);
buf (_A[1], A[1]);
buf (_A[0], A[0]);
buf (_D[31], D[31]);
buf (_D[30], D[30]);
buf (_D[29], D[29]);
buf (_D[28], D[28]);
buf (_D[27], D[27]);
buf (_D[26], D[26]);
buf (_D[25], D[25]);
buf (_D[24], D[24]);
buf (_D[23], D[23]);
buf (_D[22], D[22]);
buf (_D[21], D[21]);
buf (_D[20], D[20]);
buf (_D[19], D[19]);
buf (_D[18], D[18]);
buf (_D[17], D[17]);
buf (_D[16], D[16]);
buf (_D[15], D[15]);
buf (_D[14], D[14]);
buf (_D[13], D[13]);
buf (_D[12], D[12]);
buf (_D[11], D[11]);
buf (_D[10], D[10]);
buf (_D[9], D[9]);
buf (_D[8], D[8]);
buf (_D[7], D[7]);
buf (_D[6], D[6]);
buf (_D[5], D[5]);
buf (_D[4], D[4]);
buf (_D[3], D[3]);
buf (_D[2], D[2]);
buf (_D[1], D[1]);
buf (_D[0], D[0]);
buf (_EMA[2], EMA[2]);
buf (_EMA[1], EMA[1]);
buf (_EMA[0], EMA[0]);
assign _Q = Qi ;
assign CEN_flag = 1'b1; // use this for cen
assign flag = !_CEN; // use this for normal mission-mode inputs
assign D_flag = !(_CEN || _WEN);
assign cyc_flag = !_CEN; // use this for non-muxed inputs.
assign EMA2eq0andEMA1eq0andEMA0eq0 = !_EMA[2] && !_EMA[1] && !_EMA[0];
assign EMA2eq0andEMA1eq0andEMA0eq1 = !_EMA[2] && !_EMA[1] && _EMA[0];
assign EMA2eq0andEMA1eq1andEMA0eq0 = !_EMA[2] && _EMA[1] && !_EMA[0];
assign EMA2eq0andEMA1eq1andEMA0eq1 = !_EMA[2] && _EMA[1] && _EMA[0];
assign EMA2eq1andEMA1eq0andEMA0eq0 = _EMA[2] && !_EMA[1] && !_EMA[0];
assign EMA2eq1andEMA1eq0andEMA0eq1 = _EMA[2] && !_EMA[1] && _EMA[0];
assign EMA2eq1andEMA1eq1andEMA0eq0 = _EMA[2] && _EMA[1] && !_EMA[0];
assign EMA2eq1andEMA1eq1andEMA0eq1 = _EMA[2] && _EMA[1] && _EMA[0];
always @(
NOT_CEN or
NOT_WEN or
NOT_A6 or
NOT_A5 or
NOT_A4 or
NOT_A3 or
NOT_A2 or
NOT_A1 or
NOT_A0 or
NOT_D31 or
NOT_D30 or
NOT_D29 or
NOT_D28 or
NOT_D27 or
NOT_D26 or
NOT_D25 or
NOT_D24 or
NOT_D23 or
NOT_D22 or
NOT_D21 or
NOT_D20 or
NOT_D19 or
NOT_D18 or
NOT_D17 or
NOT_D16 or
NOT_D15 or
NOT_D14 or
NOT_D13 or
NOT_D12 or
NOT_D11 or
NOT_D10 or
NOT_D9 or
NOT_D8 or
NOT_D7 or
NOT_D6 or
NOT_D5 or
NOT_D4 or
NOT_D3 or
NOT_D2 or
NOT_D1 or
NOT_D0 or
NOT_EMA2 or
NOT_EMA1 or
NOT_EMA0 or
NOT_CLK_PER or
NOT_CLK_MINH or
NOT_CLK_MINL
)
begin
process_violations;
end
always @( _CLK )
begin
casez({LAST_CLK,_CLK})
2'b01: begin
latch_inputs;
clear_status(0);
mem_cycle(Qi,
dummy_qb,
LATCHED_CEN,
LATCHED_WEN,
LATCHED_A,
LATCHED_D,
LATCHED_EMA,
1'b1,
1'b1,
1'b1,
1'b1,
MASK1,
ADDR1,
WORD1,
1'b1,
1'b1,
WORD1,
1'b1,
1'b0,
WORD1,
0
);
end
2'b10,
2'bx?,
2'b00,
2'b11: ;
2'b?x: begin
x_mem;
Qi = WORDX ;
end
endcase
LAST_CLK = _CLK;
end
specify
$setuphold(posedge CLK &&& CEN_flag, posedge CEN, 1.000, 0.500, NOT_CEN);
$setuphold(posedge CLK &&& CEN_flag, negedge CEN, 1.000, 0.500, NOT_CEN);
$setuphold(posedge CLK &&& flag, posedge WEN, 1.000, 0.500, NOT_WEN);
$setuphold(posedge CLK &&& flag, negedge WEN, 1.000, 0.500, NOT_WEN);
$setuphold(posedge CLK &&& flag, posedge A[6], 1.000, 0.500, NOT_A6);
$setuphold(posedge CLK &&& flag, negedge A[6], 1.000, 0.500, NOT_A6);
$setuphold(posedge CLK &&& flag, posedge A[5], 1.000, 0.500, NOT_A5);
$setuphold(posedge CLK &&& flag, negedge A[5], 1.000, 0.500, NOT_A5);
$setuphold(posedge CLK &&& flag, posedge A[4], 1.000, 0.500, NOT_A4);
$setuphold(posedge CLK &&& flag, negedge A[4], 1.000, 0.500, NOT_A4);
$setuphold(posedge CLK &&& flag, posedge A[3], 1.000, 0.500, NOT_A3);
$setuphold(posedge CLK &&& flag, negedge A[3], 1.000, 0.500, NOT_A3);
$setuphold(posedge CLK &&& flag, posedge A[2], 1.000, 0.500, NOT_A2);
$setuphold(posedge CLK &&& flag, negedge A[2], 1.000, 0.500, NOT_A2);
$setuphold(posedge CLK &&& flag, posedge A[1], 1.000, 0.500, NOT_A1);
$setuphold(posedge CLK &&& flag, negedge A[1], 1.000, 0.500, NOT_A1);
$setuphold(posedge CLK &&& flag, posedge A[0], 1.000, 0.500, NOT_A0);
$setuphold(posedge CLK &&& flag, negedge A[0], 1.000, 0.500, NOT_A0);
$setuphold(posedge CLK &&& D_flag, posedge D[31], 1.000, 0.500, NOT_D31);
$setuphold(posedge CLK &&& D_flag, negedge D[31], 1.000, 0.500, NOT_D31);
$setuphold(posedge CLK &&& D_flag, posedge D[30], 1.000, 0.500, NOT_D30);
$setuphold(posedge CLK &&& D_flag, negedge D[30], 1.000, 0.500, NOT_D30);
$setuphold(posedge CLK &&& D_flag, posedge D[29], 1.000, 0.500, NOT_D29);
$setuphold(posedge CLK &&& D_flag, negedge D[29], 1.000, 0.500, NOT_D29);
$setuphold(posedge CLK &&& D_flag, posedge D[28], 1.000, 0.500, NOT_D28);
$setuphold(posedge CLK &&& D_flag, negedge D[28], 1.000, 0.500, NOT_D28);
$setuphold(posedge CLK &&& D_flag, posedge D[27], 1.000, 0.500, NOT_D27);
$setuphold(posedge CLK &&& D_flag, negedge D[27], 1.000, 0.500, NOT_D27);
$setuphold(posedge CLK &&& D_flag, posedge D[26], 1.000, 0.500, NOT_D26);
$setuphold(posedge CLK &&& D_flag, negedge D[26], 1.000, 0.500, NOT_D26);
$setuphold(posedge CLK &&& D_flag, posedge D[25], 1.000, 0.500, NOT_D25);
$setuphold(posedge CLK &&& D_flag, negedge D[25], 1.000, 0.500, NOT_D25);
$setuphold(posedge CLK &&& D_flag, posedge D[24], 1.000, 0.500, NOT_D24);
$setuphold(posedge CLK &&& D_flag, negedge D[24], 1.000, 0.500, NOT_D24);
$setuphold(posedge CLK &&& D_flag, posedge D[23], 1.000, 0.500, NOT_D23);
$setuphold(posedge CLK &&& D_flag, negedge D[23], 1.000, 0.500, NOT_D23);
$setuphold(posedge CLK &&& D_flag, posedge D[22], 1.000, 0.500, NOT_D22);
$setuphold(posedge CLK &&& D_flag, negedge D[22], 1.000, 0.500, NOT_D22);
$setuphold(posedge CLK &&& D_flag, posedge D[21], 1.000, 0.500, NOT_D21);
$setuphold(posedge CLK &&& D_flag, negedge D[21], 1.000, 0.500, NOT_D21);
$setuphold(posedge CLK &&& D_flag, posedge D[20], 1.000, 0.500, NOT_D20);
$setuphold(posedge CLK &&& D_flag, negedge D[20], 1.000, 0.500, NOT_D20);
$setuphold(posedge CLK &&& D_flag, posedge D[19], 1.000, 0.500, NOT_D19);
$setuphold(posedge CLK &&& D_flag, negedge D[19], 1.000, 0.500, NOT_D19);
$setuphold(posedge CLK &&& D_flag, posedge D[18], 1.000, 0.500, NOT_D18);
$setuphold(posedge CLK &&& D_flag, negedge D[18], 1.000, 0.500, NOT_D18);
$setuphold(posedge CLK &&& D_flag, posedge D[17], 1.000, 0.500, NOT_D17);
$setuphold(posedge CLK &&& D_flag, negedge D[17], 1.000, 0.500, NOT_D17);
$setuphold(posedge CLK &&& D_flag, posedge D[16], 1.000, 0.500, NOT_D16);
$setuphold(posedge CLK &&& D_flag, negedge D[16], 1.000, 0.500, NOT_D16);
$setuphold(posedge CLK &&& D_flag, posedge D[15], 1.000, 0.500, NOT_D15);
$setuphold(posedge CLK &&& D_flag, negedge D[15], 1.000, 0.500, NOT_D15);
$setuphold(posedge CLK &&& D_flag, posedge D[14], 1.000, 0.500, NOT_D14);
$setuphold(posedge CLK &&& D_flag, negedge D[14], 1.000, 0.500, NOT_D14);
$setuphold(posedge CLK &&& D_flag, posedge D[13], 1.000, 0.500, NOT_D13);
$setuphold(posedge CLK &&& D_flag, negedge D[13], 1.000, 0.500, NOT_D13);
$setuphold(posedge CLK &&& D_flag, posedge D[12], 1.000, 0.500, NOT_D12);
$setuphold(posedge CLK &&& D_flag, negedge D[12], 1.000, 0.500, NOT_D12);
$setuphold(posedge CLK &&& D_flag, posedge D[11], 1.000, 0.500, NOT_D11);
$setuphold(posedge CLK &&& D_flag, negedge D[11], 1.000, 0.500, NOT_D11);
$setuphold(posedge CLK &&& D_flag, posedge D[10], 1.000, 0.500, NOT_D10);
$setuphold(posedge CLK &&& D_flag, negedge D[10], 1.000, 0.500, NOT_D10);
$setuphold(posedge CLK &&& D_flag, posedge D[9], 1.000, 0.500, NOT_D9);
$setuphold(posedge CLK &&& D_flag, negedge D[9], 1.000, 0.500, NOT_D9);
$setuphold(posedge CLK &&& D_flag, posedge D[8], 1.000, 0.500, NOT_D8);
$setuphold(posedge CLK &&& D_flag, negedge D[8], 1.000, 0.500, NOT_D8);
$setuphold(posedge CLK &&& D_flag, posedge D[7], 1.000, 0.500, NOT_D7);
$setuphold(posedge CLK &&& D_flag, negedge D[7], 1.000, 0.500, NOT_D7);
$setuphold(posedge CLK &&& D_flag, posedge D[6], 1.000, 0.500, NOT_D6);
$setuphold(posedge CLK &&& D_flag, negedge D[6], 1.000, 0.500, NOT_D6);
$setuphold(posedge CLK &&& D_flag, posedge D[5], 1.000, 0.500, NOT_D5);
$setuphold(posedge CLK &&& D_flag, negedge D[5], 1.000, 0.500, NOT_D5);
$setuphold(posedge CLK &&& D_flag, posedge D[4], 1.000, 0.500, NOT_D4);
$setuphold(posedge CLK &&& D_flag, negedge D[4], 1.000, 0.500, NOT_D4);
$setuphold(posedge CLK &&& D_flag, posedge D[3], 1.000, 0.500, NOT_D3);
$setuphold(posedge CLK &&& D_flag, negedge D[3], 1.000, 0.500, NOT_D3);
$setuphold(posedge CLK &&& D_flag, posedge D[2], 1.000, 0.500, NOT_D2);
$setuphold(posedge CLK &&& D_flag, negedge D[2], 1.000, 0.500, NOT_D2);
$setuphold(posedge CLK &&& D_flag, posedge D[1], 1.000, 0.500, NOT_D1);
$setuphold(posedge CLK &&& D_flag, negedge D[1], 1.000, 0.500, NOT_D1);
$setuphold(posedge CLK &&& D_flag, posedge D[0], 1.000, 0.500, NOT_D0);
$setuphold(posedge CLK &&& D_flag, negedge D[0], 1.000, 0.500, NOT_D0);
$setuphold(posedge CLK &&& cyc_flag, posedge EMA[2], 1.000, 0.500, NOT_EMA2);
$setuphold(posedge CLK &&& cyc_flag, negedge EMA[2], 1.000, 0.500, NOT_EMA2);
$setuphold(posedge CLK &&& cyc_flag, posedge EMA[1], 1.000, 0.500, NOT_EMA1);
$setuphold(posedge CLK &&& cyc_flag, negedge EMA[1], 1.000, 0.500, NOT_EMA1);
$setuphold(posedge CLK &&& cyc_flag, posedge EMA[0], 1.000, 0.500, NOT_EMA0);
$setuphold(posedge CLK &&& cyc_flag, negedge EMA[0], 1.000, 0.500, NOT_EMA0);
$width(posedge CLK, 1.000, 0, NOT_CLK_MINH);
$width(negedge CLK, 1.000, 0, NOT_CLK_MINL);
`ifdef NO_SDTC
$period(posedge CLK, 3.000, NOT_CLK_PER);
`else
$period(posedge CLK &&& EMA2eq0andEMA1eq0andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq0andEMA1eq0andEMA0eq1, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq0andEMA1eq1andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq0andEMA1eq1andEMA0eq1, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq0andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq0andEMA0eq1, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq1andEMA0eq0, 3.000, NOT_CLK_PER);
$period(posedge CLK &&& EMA2eq1andEMA1eq1andEMA0eq1, 3.000, NOT_CLK_PER);
`endif
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[31])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[30])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[29])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[28])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[27])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[26])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[25])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[24])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[23])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[22])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[21])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[20])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[19])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[18])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[17])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[16])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[15])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[14])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[13])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[12])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[11])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[10])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[9])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[8])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[7])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[6])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[5])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[4])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[3])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[2])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[1])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b0) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b0) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b0))
(CLK => Q[0])=(1.000, 1.000);
if ((EMA[2] == 1'b1) && (EMA[1] == 1'b1) && (EMA[0] == 1'b1))
(CLK => Q[0])=(1.000, 1.000);
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_4_V
`define SKY130_FD_SC_MS__EBUFN_4_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_4 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_4 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_4_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: RAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.1 Build 243 01/31/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module RAM (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [15:0] address_a;
input [15:0] address_b;
input clock_a;
input clock_b;
input [15:0] data_a;
input [15:0] data_b;
input wren_a;
input wren_b;
output [15:0] q_a;
output [15:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] sub_wire1;
wire [15:0] q_a = sub_wire0[15:0];
wire [15:0] q_b = sub_wire1[15:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.init_file = "RAM.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.numwords_b = 65536,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "OLD_DATA",
altsyncram_component.read_during_write_mode_port_b = "OLD_DATA",
altsyncram_component.widthad_a = 16,
altsyncram_component.widthad_b = 16,
altsyncram_component.width_a = 16,
altsyncram_component.width_b = 16,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1048576"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "RAM.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "1"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "1"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INIT_FILE STRING "RAM.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "OLD_DATA"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "OLD_DATA"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 16 0 INPUT NODEFVAL "address_a[15..0]"
// Retrieval info: USED_PORT: address_b 0 0 16 0 INPUT NODEFVAL "address_b[15..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL "data_a[15..0]"
// Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL "data_b[15..0]"
// Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL "q_a[15..0]"
// Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL "q_b[15..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address_a 0 0 16 0
// Retrieval info: CONNECT: @address_b 0 0 16 0 address_b 0 0 16 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
// Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL RAM_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:20:45 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W32 ( add_sub, in1, in2, res );
input [31:0] in1;
input [31:0] in2;
output [32:0] res;
input add_sub;
wire n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27,
n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41,
n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69,
n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108, n109,
n110, n111, n112, n113, n114, n115, n116, n117, n118, n119, n120,
n121, n122, n123, n124, n125, n126, n127, n128, n129, n130, n131,
n132, n133, n134, n135, n136, n137, n138, n139, n140, n141, n142,
n143, n144, n145, n146, n147, n148, n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158, n159, n160, n161, n162, n163, n164,
n165, n166, n167, n168, n169, n170, n171, n172, n173, n174, n175,
n176, n177, n178, n179, n180, n181, n182, n183, n184, n185, n186,
n187, n188, n189, n190, n191, n192, n193, n194, n195, n196, n197,
n198, n199, n200, n201, n202, n203, n204, n205, n206, n207, n208,
n209, n210, n211, n212, n213, n214, n215, n216, n217, n218, n219,
n220, n221, n222, n223, n224, n225, n226, n227, n228, n229, n230,
n231, n232, n233, n234, n235, n236, n237, n238, n239, n240, n241,
n242, n243, n244, n245, n246, n247, n248, n249, n250, n251, n252,
n253, n254, n255, n256, n257, n258, n259, n260, n261, n262, n263,
n264, n265, n266, n267, n268, n269, n270, n271, n272, n273, n274,
n275, n276, n277, n278, n279, n280, n281, n282, n283, n284, n285,
n286, n287, n288, n289, n290, n291, n292, n293, n294, n295, n296;
AO21X2TS U48 ( .A0(n165), .A1(n193), .B0(n164), .Y(res[32]) );
XOR2X2TS U49 ( .A(n174), .B(n173), .Y(res[28]) );
XOR2X2TS U50 ( .A(n178), .B(n177), .Y(res[27]) );
XOR2X2TS U51 ( .A(n183), .B(n182), .Y(res[29]) );
NAND2X1TS U52 ( .A(n43), .B(n176), .Y(n177) );
NAND2X1TS U53 ( .A(n42), .B(n181), .Y(n182) );
NAND2X1TS U54 ( .A(n172), .B(n171), .Y(n173) );
NAND2X1TS U55 ( .A(n202), .B(n44), .Y(n203) );
NOR2X1TS U56 ( .A(n186), .B(n184), .Y(n165) );
NAND2XLTS U57 ( .A(n40), .B(n222), .Y(n223) );
NAND2XLTS U58 ( .A(n41), .B(n194), .Y(n195) );
NAND2X1TS U59 ( .A(n15), .B(n239), .Y(n241) );
NAND2XLTS U60 ( .A(n38), .B(n207), .Y(n208) );
NAND2XLTS U61 ( .A(n216), .B(n215), .Y(n217) );
OAI21X1TS U62 ( .A0(n186), .A1(n190), .B0(n187), .Y(n164) );
INVX2TS U63 ( .A(n184), .Y(n191) );
INVX3TS U64 ( .A(n196), .Y(n218) );
INVX2TS U65 ( .A(n220), .Y(n227) );
NAND2X2TS U66 ( .A(n162), .B(in1[30]), .Y(n190) );
NAND2X4TS U67 ( .A(n22), .B(n196), .Y(n21) );
NOR2X2TS U68 ( .A(n162), .B(in1[30]), .Y(n184) );
NOR2X1TS U69 ( .A(n276), .B(in2[5]), .Y(n280) );
CLKMX2X2TS U70 ( .A(in2[30]), .B(n58), .S0(n152), .Y(n162) );
NAND2X2TS U71 ( .A(n157), .B(in1[28]), .Y(n171) );
INVX2TS U72 ( .A(n194), .Y(n175) );
NOR2X1TS U73 ( .A(n57), .B(in2[30]), .Y(n55) );
CLKINVX1TS U74 ( .A(n202), .Y(n135) );
NOR2X1TS U75 ( .A(n269), .B(in2[3]), .Y(n273) );
NAND2X4TS U76 ( .A(n216), .B(n212), .Y(n206) );
INVX6TS U77 ( .A(n124), .Y(n212) );
NAND2BX1TS U78 ( .AN(in2[29]), .B(n140), .Y(n57) );
OR2X2TS U79 ( .A(n133), .B(in1[24]), .Y(n38) );
NAND2X2TS U80 ( .A(n154), .B(in1[26]), .Y(n194) );
NAND2X2TS U81 ( .A(n129), .B(in1[22]), .Y(n215) );
NAND2X2TS U82 ( .A(n112), .B(in1[21]), .Y(n222) );
NAND2X4TS U83 ( .A(n130), .B(in1[23]), .Y(n211) );
MX2X1TS U84 ( .A(in2[29]), .B(n141), .S0(n152), .Y(n158) );
CLKMX2X4TS U85 ( .A(in2[21]), .B(n108), .S0(n152), .Y(n112) );
NOR2X6TS U86 ( .A(n130), .B(in1[23]), .Y(n124) );
OR2X4TS U87 ( .A(n154), .B(in1[26]), .Y(n41) );
XNOR2X2TS U88 ( .A(n120), .B(in2[20]), .Y(n109) );
XNOR2X1TS U89 ( .A(n100), .B(in2[18]), .Y(n97) );
XNOR2X1TS U90 ( .A(n125), .B(in2[25]), .Y(n126) );
MX2X2TS U91 ( .A(in2[17]), .B(n93), .S0(add_sub), .Y(n94) );
NOR2X2TS U92 ( .A(n54), .B(in2[24]), .Y(n125) );
NOR2X2TS U93 ( .A(n54), .B(n142), .Y(n143) );
BUFX3TS U94 ( .A(add_sub), .Y(n16) );
CLKINVX1TS U95 ( .A(n120), .Y(n116) );
INVX2TS U96 ( .A(n106), .Y(n91) );
NAND2X1TS U97 ( .A(n145), .B(n149), .Y(n142) );
BUFX8TS U98 ( .A(n88), .Y(n106) );
NOR2X2TS U99 ( .A(in2[25]), .B(in2[24]), .Y(n145) );
AND2X2TS U100 ( .A(n96), .B(n52), .Y(n105) );
NOR2X1TS U101 ( .A(in2[22]), .B(in2[23]), .Y(n53) );
NOR2X2TS U102 ( .A(in2[21]), .B(in2[20]), .Y(n121) );
NOR2X2TS U103 ( .A(in2[17]), .B(in2[16]), .Y(n96) );
BUFX6TS U104 ( .A(add_sub), .Y(n152) );
BUFX8TS U105 ( .A(add_sub), .Y(n294) );
NOR2X6TS U106 ( .A(in2[5]), .B(in2[4]), .Y(n18) );
NOR2X6TS U107 ( .A(in2[6]), .B(in2[7]), .Y(n19) );
INVX12TS U108 ( .A(in2[8]), .Y(n258) );
INVX12TS U109 ( .A(in2[9]), .Y(n49) );
NOR2X1TS U110 ( .A(in2[19]), .B(in2[18]), .Y(n52) );
NOR2X6TS U111 ( .A(in2[3]), .B(in2[2]), .Y(n17) );
XNOR2X1TS U112 ( .A(n107), .B(in2[21]), .Y(n108) );
NAND2X1TS U113 ( .A(n273), .B(n272), .Y(n276) );
CLKMX2X2TS U114 ( .A(in2[19]), .B(n102), .S0(add_sub), .Y(n103) );
INVX2TS U115 ( .A(n211), .Y(n131) );
NAND2X4TS U116 ( .A(n69), .B(in1[12]), .Y(n255) );
NAND2X1TS U117 ( .A(n111), .B(in1[20]), .Y(n225) );
OR2X2TS U118 ( .A(n134), .B(in1[25]), .Y(n44) );
NAND2X1TS U119 ( .A(n158), .B(in1[29]), .Y(n181) );
OAI21X2TS U120 ( .A0(n218), .A1(n201), .B0(n200), .Y(n204) );
AO21X4TS U121 ( .A0(n196), .A1(n139), .B0(n138), .Y(n14) );
AND2X4TS U122 ( .A(n139), .B(n23), .Y(n22) );
NAND2X4TS U123 ( .A(n42), .B(n180), .Y(n161) );
MX2X2TS U124 ( .A(in2[31]), .B(n56), .S0(n152), .Y(n163) );
NOR2X6TS U125 ( .A(n157), .B(in1[28]), .Y(n170) );
INVX2TS U126 ( .A(n207), .Y(n198) );
NAND2X2TS U127 ( .A(n134), .B(in1[25]), .Y(n202) );
MX2X4TS U128 ( .A(in2[28]), .B(n153), .S0(n152), .Y(n157) );
OAI21X4TS U129 ( .A0(n205), .A1(n137), .B0(n136), .Y(n138) );
INVX2TS U130 ( .A(n206), .Y(n197) );
NAND2X2TS U131 ( .A(n188), .B(n187), .Y(n189) );
NAND2X2TS U132 ( .A(n191), .B(n190), .Y(n192) );
AOI21X2TS U133 ( .A0(n40), .A1(n221), .B0(n113), .Y(n114) );
NAND2X4TS U134 ( .A(n43), .B(n41), .Y(n166) );
NOR2X4TS U135 ( .A(n163), .B(in1[31]), .Y(n186) );
NAND2X2TS U136 ( .A(n163), .B(in1[31]), .Y(n187) );
OR2X4TS U137 ( .A(n94), .B(in1[17]), .Y(n47) );
OR2X4TS U138 ( .A(n158), .B(in1[29]), .Y(n42) );
XNOR2X1TS U139 ( .A(n140), .B(in2[29]), .Y(n141) );
NOR2X4TS U140 ( .A(n91), .B(in2[16]), .Y(n92) );
NOR2X2TS U141 ( .A(n120), .B(in2[20]), .Y(n107) );
NOR2X4TS U142 ( .A(in2[11]), .B(in2[10]), .Y(n50) );
XOR2X1TS U143 ( .A(n224), .B(n223), .Y(res[21]) );
OAI21X1TS U144 ( .A0(n25), .A1(n32), .B0(in1[16]), .Y(n239) );
OR2X2TS U145 ( .A(n25), .B(n33), .Y(n15) );
AOI21X2TS U146 ( .A0(n44), .A1(n198), .B0(n135), .Y(n136) );
OR2X4TS U147 ( .A(n36), .B(n26), .Y(n31) );
NAND2X2TS U148 ( .A(n99), .B(in1[18]), .Y(n232) );
MX2X2TS U149 ( .A(in2[25]), .B(n126), .S0(n152), .Y(n134) );
MX2X2TS U150 ( .A(in2[27]), .B(n144), .S0(n152), .Y(n155) );
XNOR2X2TS U151 ( .A(n147), .B(in2[26]), .Y(n148) );
XNOR2X2TS U152 ( .A(n92), .B(in2[17]), .Y(n93) );
NAND2X2TS U153 ( .A(n116), .B(n121), .Y(n117) );
XNOR2X2TS U154 ( .A(n143), .B(in2[27]), .Y(n144) );
NOR2X2TS U155 ( .A(n100), .B(in2[18]), .Y(n101) );
NAND2BXLTS U156 ( .AN(in1[7]), .B(n283), .Y(res[7]) );
NAND2BXLTS U157 ( .AN(in1[6]), .B(n278), .Y(res[6]) );
MX2X2TS U158 ( .A(in2[15]), .B(n86), .S0(n152), .Y(n87) );
NAND2BXLTS U159 ( .AN(in1[11]), .B(n287), .Y(res[11]) );
NAND2BXLTS U160 ( .AN(in1[9]), .B(n296), .Y(res[9]) );
NAND2BXLTS U161 ( .AN(in1[10]), .B(n291), .Y(res[10]) );
NAND2BXLTS U162 ( .AN(in1[5]), .B(n275), .Y(res[5]) );
NAND2BXLTS U163 ( .AN(in1[4]), .B(n271), .Y(res[4]) );
NAND2BXLTS U164 ( .AN(in1[8]), .B(n260), .Y(res[8]) );
NAND2BXLTS U165 ( .AN(in1[3]), .B(n268), .Y(res[3]) );
INVX4TS U166 ( .A(n61), .Y(n68) );
NAND2BXLTS U167 ( .AN(in1[1]), .B(n262), .Y(res[1]) );
NAND2BXLTS U168 ( .AN(in1[2]), .B(n264), .Y(res[2]) );
OR2X2TS U169 ( .A(n142), .B(in2[27]), .Y(n150) );
OR2X1TS U170 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
NOR2X6TS U171 ( .A(n77), .B(in1[13]), .Y(n250) );
BUFX12TS U172 ( .A(n59), .Y(n84) );
AND2X6TS U173 ( .A(n64), .B(n292), .Y(n67) );
BUFX4TS U174 ( .A(n63), .Y(n292) );
OR2X2TS U175 ( .A(n111), .B(in1[20]), .Y(n45) );
NAND2X8TS U176 ( .A(n258), .B(n49), .Y(n288) );
NAND2X4TS U177 ( .A(n84), .B(n71), .Y(n73) );
NAND2X2TS U178 ( .A(n133), .B(in1[24]), .Y(n207) );
OR2X4TS U179 ( .A(n112), .B(in1[21]), .Y(n40) );
NOR2X4TS U180 ( .A(in2[13]), .B(in2[12]), .Y(n83) );
NAND3X8TS U181 ( .A(n31), .B(n29), .C(n28), .Y(n237) );
OR2X8TS U182 ( .A(n80), .B(in1[14]), .Y(n39) );
NOR2X6TS U183 ( .A(n242), .B(n246), .Y(n35) );
NAND2X4TS U184 ( .A(in2[11]), .B(n294), .Y(n62) );
AOI21X4TS U185 ( .A0(n43), .A1(n175), .B0(n156), .Y(n167) );
NAND2X2TS U186 ( .A(n155), .B(in1[27]), .Y(n176) );
XNOR2X1TS U187 ( .A(n151), .B(in2[28]), .Y(n153) );
XNOR2X2TS U188 ( .A(n117), .B(in2[22]), .Y(n118) );
NAND2X8TS U189 ( .A(n59), .B(n83), .Y(n78) );
XNOR2X1TS U190 ( .A(n78), .B(in2[14]), .Y(n79) );
AOI21X2TS U191 ( .A0(n227), .A1(n45), .B0(n221), .Y(n224) );
XOR2X4TS U192 ( .A(n85), .B(in2[15]), .Y(n86) );
NAND3X4TS U193 ( .A(n84), .B(n83), .C(n82), .Y(n85) );
NAND2X4TS U194 ( .A(n106), .B(n96), .Y(n100) );
NAND4X4TS U195 ( .A(n88), .B(n105), .C(n121), .D(n53), .Y(n54) );
NOR3X4TS U196 ( .A(n54), .B(in2[28]), .C(n150), .Y(n140) );
XNOR2X2TS U197 ( .A(n204), .B(n203), .Y(res[25]) );
NAND2X4TS U198 ( .A(n243), .B(n34), .Y(n33) );
NOR3X8TS U199 ( .A(n78), .B(in2[15]), .C(in2[14]), .Y(n88) );
AOI21X4TS U200 ( .A0(n132), .A1(n212), .B0(n131), .Y(n205) );
MXI2X4TS U201 ( .A(n119), .B(n118), .S0(n16), .Y(n129) );
NAND2X4TS U202 ( .A(n44), .B(n38), .Y(n137) );
XOR2X1TS U203 ( .A(n24), .B(n189), .Y(res[31]) );
MX2X4TS U204 ( .A(in2[23]), .B(n123), .S0(n152), .Y(n130) );
XNOR2X2TS U205 ( .A(n122), .B(in2[23]), .Y(n123) );
NOR2X4TS U206 ( .A(n206), .B(n137), .Y(n139) );
INVX2TS U207 ( .A(in2[12]), .Y(n71) );
CLKINVX6TS U208 ( .A(n255), .Y(n70) );
NAND2X4TS U209 ( .A(n77), .B(in1[13]), .Y(n251) );
NAND2X4TS U210 ( .A(n94), .B(in1[17]), .Y(n236) );
NAND2X4TS U211 ( .A(n32), .B(in1[16]), .Y(n28) );
INVX2TS U212 ( .A(n152), .Y(n75) );
CLKBUFX2TS U213 ( .A(n35), .Y(n25) );
INVX2TS U214 ( .A(n243), .Y(n32) );
NAND2X2TS U215 ( .A(n146), .B(n145), .Y(n147) );
INVX2TS U216 ( .A(n176), .Y(n156) );
INVX2TS U217 ( .A(in2[4]), .Y(n272) );
INVX2TS U218 ( .A(in2[6]), .Y(n279) );
NAND2X4TS U219 ( .A(n87), .B(in1[15]), .Y(n243) );
INVX2TS U220 ( .A(n248), .Y(n81) );
NOR2X2TS U221 ( .A(n87), .B(in1[15]), .Y(n242) );
INVX2TS U222 ( .A(n37), .Y(n27) );
NOR2BX1TS U223 ( .AN(n90), .B(add_sub), .Y(n37) );
INVX2TS U224 ( .A(n236), .Y(n95) );
NAND2X2TS U225 ( .A(n103), .B(in1[19]), .Y(n228) );
OR2X2TS U226 ( .A(n103), .B(in1[19]), .Y(n46) );
OR2X4TS U227 ( .A(n155), .B(in1[27]), .Y(n43) );
INVX2TS U228 ( .A(n167), .Y(n168) );
NOR2X6TS U229 ( .A(n166), .B(n170), .Y(n180) );
OAI21X1TS U230 ( .A0(in2[11]), .A1(add_sub), .B0(in1[11]), .Y(n65) );
NAND2BX2TS U231 ( .AN(n62), .B(n284), .Y(n61) );
INVX2TS U232 ( .A(in2[13]), .Y(n72) );
INVX2TS U233 ( .A(in2[16]), .Y(n90) );
NAND2X4TS U234 ( .A(n36), .B(n34), .Y(n30) );
INVX2TS U235 ( .A(n33), .Y(n26) );
INVX2TS U236 ( .A(in2[18]), .Y(n98) );
NOR3BX1TS U237 ( .AN(n121), .B(n120), .C(in2[22]), .Y(n122) );
INVX2TS U238 ( .A(n161), .Y(n23) );
INVX2TS U239 ( .A(n181), .Y(n159) );
NAND2X1TS U240 ( .A(n40), .B(n45), .Y(n115) );
INVX2TS U241 ( .A(n222), .Y(n113) );
INVX2TS U242 ( .A(in2[2]), .Y(n265) );
INVX2TS U243 ( .A(n225), .Y(n221) );
CLKBUFX2TS U244 ( .A(n219), .Y(n220) );
INVX2TS U245 ( .A(n210), .Y(n216) );
NOR2X2TS U246 ( .A(n129), .B(in1[22]), .Y(n210) );
INVX2TS U247 ( .A(n215), .Y(n132) );
AOI21X1TS U248 ( .A0(n199), .A1(n38), .B0(n198), .Y(n200) );
INVX2TS U249 ( .A(n205), .Y(n199) );
XNOR2X1TS U250 ( .A(n292), .B(n258), .Y(n259) );
NOR2XLTS U251 ( .A(n292), .B(in2[8]), .Y(n293) );
NOR2XLTS U252 ( .A(n292), .B(n288), .Y(n289) );
NOR2XLTS U253 ( .A(n292), .B(n284), .Y(n285) );
NAND2X1TS U254 ( .A(n48), .B(n255), .Y(n256) );
NAND2X1TS U255 ( .A(n252), .B(n251), .Y(n254) );
INVX2TS U256 ( .A(n250), .Y(n252) );
NAND2X1TS U257 ( .A(n39), .B(n248), .Y(n249) );
NAND2X1TS U258 ( .A(n244), .B(n243), .Y(n245) );
INVX2TS U259 ( .A(n242), .Y(n244) );
INVX2TS U260 ( .A(n36), .Y(n240) );
NAND2X1TS U261 ( .A(n47), .B(n236), .Y(n238) );
XOR2XLTS U262 ( .A(n235), .B(n234), .Y(res[18]) );
NAND2X1TS U263 ( .A(n233), .B(n232), .Y(n235) );
INVX2TS U264 ( .A(n231), .Y(n233) );
NAND2X1TS U265 ( .A(n46), .B(n228), .Y(n229) );
XNOR2X1TS U266 ( .A(n227), .B(n226), .Y(res[20]) );
NAND2X1TS U267 ( .A(n45), .B(n225), .Y(n226) );
XOR2X1TS U268 ( .A(n218), .B(n217), .Y(res[22]) );
XNOR2X1TS U269 ( .A(n214), .B(n213), .Y(res[23]) );
NAND2X1TS U270 ( .A(n212), .B(n211), .Y(n213) );
OAI21X2TS U271 ( .A0(n218), .A1(n210), .B0(n215), .Y(n214) );
XNOR2X1TS U272 ( .A(n209), .B(n208), .Y(res[24]) );
OAI21X2TS U273 ( .A0(n218), .A1(n206), .B0(n205), .Y(n209) );
NAND2X1TS U274 ( .A(n197), .B(n38), .Y(n201) );
XNOR2X1TS U275 ( .A(n14), .B(n195), .Y(res[26]) );
INVX2TS U276 ( .A(n170), .Y(n172) );
XNOR2X1TS U277 ( .A(n193), .B(n192), .Y(res[30]) );
INVX2TS U278 ( .A(n186), .Y(n188) );
INVX2TS U279 ( .A(in1[16]), .Y(n34) );
NOR2X2TS U280 ( .A(n99), .B(in1[18]), .Y(n231) );
INVX2TS U281 ( .A(n190), .Y(n185) );
NAND4X8TS U282 ( .A(n266), .B(n19), .C(n18), .D(n17), .Y(n63) );
NOR2X8TS U283 ( .A(in2[0]), .B(in2[1]), .Y(n266) );
NAND3X8TS U284 ( .A(n21), .B(n160), .C(n20), .Y(n193) );
NAND2BX4TS U285 ( .AN(n161), .B(n138), .Y(n20) );
AOI21X4TS U286 ( .A0(n193), .A1(n191), .B0(n185), .Y(n24) );
OAI2BB1X4TS U287 ( .A0N(n16), .A1N(n89), .B0(n27), .Y(n36) );
NAND2X8TS U288 ( .A(n35), .B(n30), .Y(n29) );
AOI21X4TS U289 ( .A0(n237), .A1(n47), .B0(n95), .Y(n234) );
XOR2XLTS U290 ( .A(n254), .B(n253), .Y(res[13]) );
XNOR2X1TS U291 ( .A(n230), .B(n229), .Y(res[19]) );
NAND2X8TS U292 ( .A(n106), .B(n105), .Y(n120) );
XOR2XLTS U293 ( .A(n246), .B(n245), .Y(res[15]) );
OR2X8TS U294 ( .A(n69), .B(in1[12]), .Y(n48) );
NAND2X1TS U295 ( .A(n75), .B(in2[13]), .Y(n74) );
INVX2TS U296 ( .A(n228), .Y(n104) );
INVX2TS U297 ( .A(n166), .Y(n169) );
NAND2BX4TS U298 ( .AN(n288), .B(n50), .Y(n51) );
NOR2X8TS U299 ( .A(n63), .B(n51), .Y(n59) );
INVX2TS U300 ( .A(in2[26]), .Y(n149) );
XNOR2X1TS U301 ( .A(n55), .B(in2[31]), .Y(n56) );
XOR2X1TS U302 ( .A(n57), .B(in2[30]), .Y(n58) );
XOR2X4TS U303 ( .A(n84), .B(in2[12]), .Y(n60) );
MXI2X4TS U304 ( .A(n71), .B(n60), .S0(add_sub), .Y(n257) );
OR2X2TS U305 ( .A(n288), .B(in2[10]), .Y(n284) );
INVX2TS U306 ( .A(n62), .Y(n64) );
OR2X8TS U307 ( .A(n84), .B(n65), .Y(n66) );
NOR3X8TS U308 ( .A(n68), .B(n67), .C(n66), .Y(n69) );
AOI21X4TS U309 ( .A0(n257), .A1(n48), .B0(n70), .Y(n253) );
XOR2X4TS U310 ( .A(n73), .B(n72), .Y(n76) );
OAI21X4TS U311 ( .A0(n76), .A1(n75), .B0(n74), .Y(n77) );
OAI21X4TS U312 ( .A0(n253), .A1(n250), .B0(n251), .Y(n247) );
INVX2TS U313 ( .A(in2[14]), .Y(n82) );
MXI2X4TS U314 ( .A(n82), .B(n79), .S0(add_sub), .Y(n80) );
NAND2X6TS U315 ( .A(n80), .B(in1[14]), .Y(n248) );
AOI21X4TS U316 ( .A0(n247), .A1(n39), .B0(n81), .Y(n246) );
XOR2X1TS U317 ( .A(n106), .B(in2[16]), .Y(n89) );
MXI2X2TS U318 ( .A(n98), .B(n97), .S0(add_sub), .Y(n99) );
OAI21X4TS U319 ( .A0(n234), .A1(n231), .B0(n232), .Y(n230) );
XNOR2X1TS U320 ( .A(n101), .B(in2[19]), .Y(n102) );
AOI21X4TS U321 ( .A0(n230), .A1(n46), .B0(n104), .Y(n219) );
INVX2TS U322 ( .A(in2[20]), .Y(n110) );
MXI2X2TS U323 ( .A(n110), .B(n109), .S0(n16), .Y(n111) );
OAI21X4TS U324 ( .A0(n219), .A1(n115), .B0(n114), .Y(n196) );
INVX2TS U325 ( .A(in2[22]), .Y(n119) );
INVX2TS U326 ( .A(in2[24]), .Y(n128) );
XNOR2X1TS U327 ( .A(n54), .B(in2[24]), .Y(n127) );
MXI2X2TS U328 ( .A(n128), .B(n127), .S0(n16), .Y(n133) );
INVX2TS U329 ( .A(n54), .Y(n146) );
MXI2X4TS U330 ( .A(n149), .B(n148), .S0(n16), .Y(n154) );
NOR2X1TS U331 ( .A(n54), .B(n150), .Y(n151) );
OAI21X4TS U332 ( .A0(n167), .A1(n170), .B0(n171), .Y(n179) );
AOI21X4TS U333 ( .A0(n179), .A1(n42), .B0(n159), .Y(n160) );
AOI21X4TS U334 ( .A0(n14), .A1(n169), .B0(n168), .Y(n174) );
AOI21X4TS U335 ( .A0(n14), .A1(n41), .B0(n175), .Y(n178) );
AOI21X4TS U336 ( .A0(n14), .A1(n180), .B0(n179), .Y(n183) );
XNOR2X1TS U337 ( .A(n238), .B(n237), .Y(res[17]) );
XNOR2X1TS U338 ( .A(n241), .B(n240), .Y(res[16]) );
XNOR2X1TS U339 ( .A(n247), .B(n249), .Y(res[14]) );
XNOR2X1TS U340 ( .A(n257), .B(n256), .Y(res[12]) );
MXI2X1TS U341 ( .A(in2[8]), .B(n259), .S0(n294), .Y(n260) );
XOR2X1TS U342 ( .A(in2[0]), .B(in2[1]), .Y(n261) );
MXI2X1TS U343 ( .A(in2[1]), .B(n261), .S0(n16), .Y(n262) );
XNOR2X1TS U344 ( .A(n266), .B(in2[2]), .Y(n263) );
MXI2X1TS U345 ( .A(in2[2]), .B(n263), .S0(n294), .Y(n264) );
NAND2X1TS U346 ( .A(n266), .B(n265), .Y(n269) );
XOR2X1TS U347 ( .A(n269), .B(in2[3]), .Y(n267) );
MXI2X1TS U348 ( .A(in2[3]), .B(n267), .S0(n294), .Y(n268) );
XNOR2X1TS U349 ( .A(n273), .B(in2[4]), .Y(n270) );
MXI2X1TS U350 ( .A(in2[4]), .B(n270), .S0(n294), .Y(n271) );
XOR2X1TS U351 ( .A(n276), .B(in2[5]), .Y(n274) );
MXI2X1TS U352 ( .A(in2[5]), .B(n274), .S0(n294), .Y(n275) );
XNOR2X1TS U353 ( .A(n280), .B(in2[6]), .Y(n277) );
MXI2X1TS U354 ( .A(in2[6]), .B(n277), .S0(n294), .Y(n278) );
NAND2X1TS U355 ( .A(n280), .B(n279), .Y(n281) );
XOR2X1TS U356 ( .A(n281), .B(in2[7]), .Y(n282) );
MXI2X1TS U357 ( .A(in2[7]), .B(n282), .S0(n294), .Y(n283) );
XNOR2X1TS U358 ( .A(n285), .B(in2[11]), .Y(n286) );
MXI2X1TS U359 ( .A(in2[11]), .B(n286), .S0(n16), .Y(n287) );
XNOR2X1TS U360 ( .A(n289), .B(in2[10]), .Y(n290) );
MXI2X1TS U361 ( .A(in2[10]), .B(n290), .S0(n294), .Y(n291) );
XNOR2X1TS U362 ( .A(n293), .B(in2[9]), .Y(n295) );
MXI2X1TS U363 ( .A(in2[9]), .B(n295), .S0(n294), .Y(n296) );
initial $sdf_annotate("Approx_adder_LOALPL12_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:23:24
// Design Name:
// Module Name: tb_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module axi4_task_sim #(
parameter DATA_W_IN_BYTES = 4,
parameter ADDR_W_IN_BITS = 10,
parameter DCADDR_LOW_BIT_W = 8,
parameter DCADDR_STROBE_MEM_SEG = 2,
parameter CLK_GEN_PERIOD_IN_PS = 10000
) (
// AXI interface control signals
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim AWADDR" *) output reg [(ADDR_W_IN_BITS)-1 : 0] S_AXI_AWADDR , // Write channel Protection type. This signal indicates the // privilege and security level of the transaction and whether // the transaction is a data access or an instruction access.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim AWPROT" *) output reg [2 : 0] S_AXI_AWPROT , // Write address valid. This signal indicates that the master signaling // valid write address and control information.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim AWVALID" *) output reg S_AXI_AWVALID , // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim AWREADY" *) input wire S_AXI_AWREADY , // Write data (issued by master acceped by Slave)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim WDATA" *) output reg [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_WDATA , // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim WSTRB" *) output reg [DATA_W_IN_BYTES-1 : 0] S_AXI_WSTRB , // Write valid. This signal indicates that valid write // data and strobes are available.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim WVALID" *) output reg S_AXI_WVALID , // Write ready. This signal indicates that the slave // can accept the write data.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim WREADY" *) input wire S_AXI_WREADY , // Write response. This signal indicates the status // of the write transaction.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim BRESP" *) input wire [1 : 0] S_AXI_BRESP , // Write response valid. This signal indicates that the channel // is signaling a valid write response.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim BVALID" *) input wire S_AXI_BVALID , // Response ready. This signal indicates that the master // can accept a write response.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim BREADY" *) output reg S_AXI_BREADY , // Read address (issued by master acceped by Slave)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim ARADDR" *) output reg [(ADDR_W_IN_BITS)-1 : 0] S_AXI_ARADDR , // Protection type. This signal indicates the privilege // and security level of the transaction and whether the // transaction is a data access or an instruction access.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim ARPROT" *) output reg [2 : 0] S_AXI_ARPROT , // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim ARVALID" *) output reg S_AXI_ARVALID , // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim ARREADY" *) input wire S_AXI_ARREADY , // Read data (issued by slave)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim RDATA" *) input wire [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_RDATA , // Read response. This signal indicates the status of the // read transfer.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim RRESP" *) input wire [1 : 0] S_AXI_RRESP , // Read valid. This signal indicates that the channel is signaling the required read data.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim RVALID" *) input wire S_AXI_RVALID , // Read ready. This signal indicates that the master can accept the read data and response information.
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 axi4_task_sim RREADY" *) output reg S_AXI_RREADY , //
// Clock & reset for registers
output reg ACLK, // Clock source
output reg ARESETn // Reset source
);
// internal signals
reg [(DATA_W_IN_BYTES*8) - 1:0] read_data; //
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
always begin
ACLK = 1'b0;
#(CLK_GEN_PERIOD_IN_PS/2) ACLK = 1'b1;
#(CLK_GEN_PERIOD_IN_PS/2);
end
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
initial begin
wait_aclk_cycles_for_to(200);
end
initial begin
initialise_axi_inputs();
ARESETn = 1;
wait_aclk_cycles(2);
ARESETn = 0;
wait_aclk_cycles(20);
ARESETn = 1;
wait_aclk_cycles(60);
// bank_rd_data = 44;
axi_read('h20,read_data);
axi_write('h20,33);
// bank_rd_data = 49;
axi_read('h20,read_data);
wait_aclk_cycles(20);
axi_write('h00_00,'h0);
axi_write('h00_00,'hff);
axi_write('h01_00,'h1);
axi_write('h02_00,'h2);
axi_read('h00_00,read_data);
axi_read('h01_00,read_data);
axi_read('h02_00,read_data);
axi_read('h04_00,read_data);
axi_write('h1_0000,'h2);
axi_read('h1_0000,read_data);
axi_read('h1_0000,read_data);
axi_read('h1_0000,read_data);
$stop;
end
//------------------------------------------------------------------------------
// Initialise IO
//------------------------------------------------------------------------------
task initialise_axi_inputs;
begin
S_AXI_AWADDR = 'd0;
S_AXI_AWPROT = 'd0;
S_AXI_AWVALID = 'd0;
S_AXI_WDATA = 'd0;
S_AXI_WSTRB = 'd0;
S_AXI_WVALID = 'd0;
S_AXI_BREADY = 'd0;
S_AXI_ARADDR = 'd0;
S_AXI_ARPROT = 'd0;
S_AXI_ARVALID = 'd0;
S_AXI_RREADY = 'd0;
end
endtask
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
task axi_read;
input [(ADDR_W_IN_BITS)-1 : 0] ADDR;
output [(DATA_W_IN_BYTES*8) - 1:0] DATA;
begin
@(posedge ACLK);
S_AXI_ARADDR <= ADDR;
S_AXI_ARPROT <= 'd0;
S_AXI_ARVALID <= 'd1;
S_AXI_RREADY <= 'd1; // This can be high as xfer starts
@(posedge ACLK);
while( S_AXI_ARREADY == 'd0 )
@(posedge ACLK);
S_AXI_ARVALID <= 'd0;
while( S_AXI_RVALID == 'd0 )
@(posedge ACLK);
S_AXI_RREADY <= 'd0;
DATA <= S_AXI_RDATA;
// S_AXI_RRESP
end
endtask
task axi_write;
input [(ADDR_W_IN_BITS)-1 : 0] ADDR;
input [(DATA_W_IN_BYTES*8) - 1:0] DATA;
reg [1:0] got_flags;
begin
got_flags=0;
@(posedge ACLK);
S_AXI_AWADDR <= ADDR;
S_AXI_AWPROT <= 'd0;
S_AXI_AWVALID <= 'd1;
S_AXI_WVALID <= 'd1;
S_AXI_WDATA <= DATA;
@(posedge ACLK);
// while( (S_AXI_AWREADY & S_AXI_WREADY) == 'd0 )
// @(posedge ACLK);
// Keep a record of both ready signals reception. We need to loop until both
// have been received
got_flags = got_flags | {S_AXI_AWREADY,S_AXI_WREADY};
while( got_flags != 'd3 ) begin
got_flags = got_flags | {S_AXI_AWREADY,S_AXI_WREADY};
if (S_AXI_AWREADY)
S_AXI_AWVALID <= 1'd0;
if (S_AXI_WREADY)
S_AXI_WVALID <= 1'd0;
@(posedge ACLK);
end
// We still need these as if the ready signals came back strsight away, the while
// loop is not executed and the signals not cleared
S_AXI_AWVALID <= 'd0;
S_AXI_WVALID <= 'd0;
while( S_AXI_BREADY == 'd0 )begin
if (S_AXI_BVALID)
S_AXI_BREADY <= 'd1;
@(posedge ACLK);
end
S_AXI_BREADY <= 'd0;
// @(posedge ACLK);
// S_AXI_BREADY <= 'd0;
end
endtask
task wait_aclk_cycles_for_to;
input reg [31 : 0] cycles;
begin
while( cycles > 'd0 ) begin
@(posedge ACLK);
cycles = cycles - 'd1;
end
$display("---ERROR simulation timeout!");
$stop;
end
endtask
task wait_aclk_cycles;
input reg [31 : 0] cycles;
begin
while( cycles > 'd0 ) begin
@(posedge ACLK);
cycles = cycles - 'd1;
end
end
endtask
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt51_kon(
input rst,
input clk,
input [3:0] keyon_op,
input [2:0] keyon_ch,
input [1:0] cur_op,
input [2:0] cur_ch,
input up_keyon,
input csm,
input overflow_A,
output reg keyon_II
);
//reg csm_copy;
reg din;
wire drop;
reg [3:0] cur_op_hot;
always @(posedge clk)
keyon_II <= (csm&&overflow_A) || drop;
always @(*) begin
case( cur_op )
2'd0: cur_op_hot = 4'b0001; // S1 / M1
2'd1: cur_op_hot = 4'b0100; // S3 / M2
2'd2: cur_op_hot = 4'b0010; // S2 / C1
2'd3: cur_op_hot = 4'b1000; // S4 / C2
endcase
din = keyon_ch==cur_ch && up_keyon ? |(keyon_op&cur_op_hot) : drop;
end
jt51_sh #(.width(1),.stages(32)) u_konch(
.clk ( clk ),
.din ( din ),
.drop ( drop )
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A2111O_FUNCTIONAL_PP_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2111o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , C1, B1, and0_out, D1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111O_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND4BB_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND4BB_PP_BLACKBOX_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND4BB_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:39 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_ilmb_bram_if_cntlr_0/system_ilmb_bram_if_cntlr_0_sim_netlist.v
// Design : system_ilmb_bram_if_cntlr_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ilmb_bram_if_cntlr_0,lmb_bram_if_cntlr,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "lmb_bram_if_cntlr,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ilmb_bram_if_cntlr_0
(LMB_Clk,
LMB_Rst,
LMB_ABus,
LMB_WriteDBus,
LMB_AddrStrobe,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_Addr_A,
BRAM_EN_A,
BRAM_WEN_A,
BRAM_Dout_A,
BRAM_Din_A);
(* x_interface_info = "xilinx.com:signal:clock:1.0 CLK.LMB_Clk CLK" *) input LMB_Clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 RST.LMB_Rst RST" *) input LMB_Rst;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ABUS" *) input [0:31]LMB_ABus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITEDBUS" *) input [0:31]LMB_WriteDBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB ADDRSTROBE" *) input LMB_AddrStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READSTROBE" *) input LMB_ReadStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WRITESTROBE" *) input LMB_WriteStrobe;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB BE" *) input [0:3]LMB_BE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READDBUS" *) output [0:31]Sl_DBus;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB READY" *) output Sl_Ready;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB WAIT" *) output Sl_Wait;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB UE" *) output Sl_UE;
(* x_interface_info = "xilinx.com:interface:lmb:1.0 SLMB CE" *) output Sl_CE;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT RST" *) output BRAM_Rst_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT CLK" *) output BRAM_Clk_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT ADDR" *) output [0:31]BRAM_Addr_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT EN" *) output BRAM_EN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT WE" *) output [0:3]BRAM_WEN_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DIN" *) output [0:31]BRAM_Dout_A;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORT DOUT" *) input [0:31]BRAM_Din_A;
wire [0:31]BRAM_Addr_A;
wire BRAM_Clk_A;
wire [0:31]BRAM_Din_A;
wire [0:31]BRAM_Dout_A;
wire BRAM_EN_A;
wire BRAM_Rst_A;
wire [0:3]BRAM_WEN_A;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
wire [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_ReadStrobe;
wire LMB_Rst;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
wire Sl_CE;
wire [0:31]Sl_DBus;
wire Sl_Ready;
wire Sl_UE;
wire Sl_Wait;
wire NLW_U0_CE_UNCONNECTED;
wire NLW_U0_Interrupt_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED;
wire NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED;
wire NLW_U0_Sl1_CE_UNCONNECTED;
wire NLW_U0_Sl1_Ready_UNCONNECTED;
wire NLW_U0_Sl1_UE_UNCONNECTED;
wire NLW_U0_Sl1_Wait_UNCONNECTED;
wire NLW_U0_Sl2_CE_UNCONNECTED;
wire NLW_U0_Sl2_Ready_UNCONNECTED;
wire NLW_U0_Sl2_UE_UNCONNECTED;
wire NLW_U0_Sl2_Wait_UNCONNECTED;
wire NLW_U0_Sl3_CE_UNCONNECTED;
wire NLW_U0_Sl3_Ready_UNCONNECTED;
wire NLW_U0_Sl3_UE_UNCONNECTED;
wire NLW_U0_Sl3_Wait_UNCONNECTED;
wire NLW_U0_UE_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED;
wire [31:0]NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED;
wire [1:0]NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED;
wire [0:31]NLW_U0_Sl1_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl2_DBus_UNCONNECTED;
wire [0:31]NLW_U0_Sl3_DBus_UNCONNECTED;
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_BRAM_AWIDTH = "32" *)
(* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *)
(* C_ECC = "0" *)
(* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *)
(* C_ECC_STATUS_REGISTERS = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FAULT_INJECT = "0" *)
(* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000000111111111111111" *)
(* C_INTERCONNECT = "0" *)
(* C_LMB_AWIDTH = "32" *)
(* C_LMB_DWIDTH = "32" *)
(* C_MASK = "64'b0000000000000000000000000000000010000000000000000000000000000000" *)
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *)
(* C_S_AXI_CTRL_ADDR_WIDTH = "32" *)
(* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *)
(* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *)
(* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *)
system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr U0
(.BRAM_Addr_A(BRAM_Addr_A),
.BRAM_Clk_A(BRAM_Clk_A),
.BRAM_Din_A(BRAM_Din_A),
.BRAM_Dout_A(BRAM_Dout_A),
.BRAM_EN_A(BRAM_EN_A),
.BRAM_Rst_A(BRAM_Rst_A),
.BRAM_WEN_A(BRAM_WEN_A),
.CE(NLW_U0_CE_UNCONNECTED),
.Interrupt(NLW_U0_Interrupt_UNCONNECTED),
.LMB1_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_AddrStrobe(1'b0),
.LMB1_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB1_ReadStrobe(1'b0),
.LMB1_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB1_WriteStrobe(1'b0),
.LMB2_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_AddrStrobe(1'b0),
.LMB2_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB2_ReadStrobe(1'b0),
.LMB2_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB2_WriteStrobe(1'b0),
.LMB3_ABus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_AddrStrobe(1'b0),
.LMB3_BE({1'b0,1'b0,1'b0,1'b0}),
.LMB3_ReadStrobe(1'b0),
.LMB3_WriteDBus({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.LMB3_WriteStrobe(1'b0),
.LMB_ABus(LMB_ABus),
.LMB_AddrStrobe(LMB_AddrStrobe),
.LMB_BE(LMB_BE),
.LMB_Clk(LMB_Clk),
.LMB_ReadStrobe(LMB_ReadStrobe),
.LMB_Rst(LMB_Rst),
.LMB_WriteDBus(LMB_WriteDBus),
.LMB_WriteStrobe(LMB_WriteStrobe),
.S_AXI_CTRL_ACLK(1'b0),
.S_AXI_CTRL_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_ARESETN(1'b0),
.S_AXI_CTRL_ARREADY(NLW_U0_S_AXI_CTRL_ARREADY_UNCONNECTED),
.S_AXI_CTRL_ARVALID(1'b0),
.S_AXI_CTRL_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_AWREADY(NLW_U0_S_AXI_CTRL_AWREADY_UNCONNECTED),
.S_AXI_CTRL_AWVALID(1'b0),
.S_AXI_CTRL_BREADY(1'b0),
.S_AXI_CTRL_BRESP(NLW_U0_S_AXI_CTRL_BRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_BVALID(NLW_U0_S_AXI_CTRL_BVALID_UNCONNECTED),
.S_AXI_CTRL_RDATA(NLW_U0_S_AXI_CTRL_RDATA_UNCONNECTED[31:0]),
.S_AXI_CTRL_RREADY(1'b0),
.S_AXI_CTRL_RRESP(NLW_U0_S_AXI_CTRL_RRESP_UNCONNECTED[1:0]),
.S_AXI_CTRL_RVALID(NLW_U0_S_AXI_CTRL_RVALID_UNCONNECTED),
.S_AXI_CTRL_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WREADY(NLW_U0_S_AXI_CTRL_WREADY_UNCONNECTED),
.S_AXI_CTRL_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_CTRL_WVALID(1'b0),
.Sl1_CE(NLW_U0_Sl1_CE_UNCONNECTED),
.Sl1_DBus(NLW_U0_Sl1_DBus_UNCONNECTED[0:31]),
.Sl1_Ready(NLW_U0_Sl1_Ready_UNCONNECTED),
.Sl1_UE(NLW_U0_Sl1_UE_UNCONNECTED),
.Sl1_Wait(NLW_U0_Sl1_Wait_UNCONNECTED),
.Sl2_CE(NLW_U0_Sl2_CE_UNCONNECTED),
.Sl2_DBus(NLW_U0_Sl2_DBus_UNCONNECTED[0:31]),
.Sl2_Ready(NLW_U0_Sl2_Ready_UNCONNECTED),
.Sl2_UE(NLW_U0_Sl2_UE_UNCONNECTED),
.Sl2_Wait(NLW_U0_Sl2_Wait_UNCONNECTED),
.Sl3_CE(NLW_U0_Sl3_CE_UNCONNECTED),
.Sl3_DBus(NLW_U0_Sl3_DBus_UNCONNECTED[0:31]),
.Sl3_Ready(NLW_U0_Sl3_Ready_UNCONNECTED),
.Sl3_UE(NLW_U0_Sl3_UE_UNCONNECTED),
.Sl3_Wait(NLW_U0_Sl3_Wait_UNCONNECTED),
.Sl_CE(Sl_CE),
.Sl_DBus(Sl_DBus),
.Sl_Ready(Sl_Ready),
.Sl_UE(Sl_UE),
.Sl_Wait(Sl_Wait),
.UE(NLW_U0_UE_UNCONNECTED));
endmodule
(* C_BASEADDR = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* C_BRAM_AWIDTH = "32" *) (* C_CE_COUNTER_WIDTH = "0" *)
(* C_CE_FAILING_REGISTERS = "0" *) (* C_ECC = "0" *) (* C_ECC_ONOFF_REGISTER = "0" *)
(* C_ECC_ONOFF_RESET_VALUE = "1" *) (* C_ECC_STATUS_REGISTERS = "0" *) (* C_FAMILY = "artix7" *)
(* C_FAULT_INJECT = "0" *) (* C_HIGHADDR = "64'b0000000000000000000000000000000000000000000000000111111111111111" *) (* C_INTERCONNECT = "0" *)
(* C_LMB_AWIDTH = "32" *) (* C_LMB_DWIDTH = "32" *) (* C_MASK = "64'b0000000000000000000000000000000010000000000000000000000000000000" *)
(* C_MASK1 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK2 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *) (* C_MASK3 = "64'b0000000000000000000000000000000000000000100000000000000000000000" *)
(* C_NUM_LMB = "1" *) (* C_S_AXI_CTRL_ADDR_WIDTH = "32" *) (* C_S_AXI_CTRL_BASEADDR = "32'b11111111111111111111111111111111" *)
(* C_S_AXI_CTRL_DATA_WIDTH = "32" *) (* C_S_AXI_CTRL_HIGHADDR = "32'b00000000000000000000000000000000" *) (* C_UE_FAILING_REGISTERS = "0" *)
(* C_WRITE_ACCESS = "2" *) (* ORIG_REF_NAME = "lmb_bram_if_cntlr" *)
module system_ilmb_bram_if_cntlr_0_lmb_bram_if_cntlr
(LMB_Clk,
LMB_Rst,
LMB_ABus,
LMB_WriteDBus,
LMB_AddrStrobe,
LMB_ReadStrobe,
LMB_WriteStrobe,
LMB_BE,
Sl_DBus,
Sl_Ready,
Sl_Wait,
Sl_UE,
Sl_CE,
LMB1_ABus,
LMB1_WriteDBus,
LMB1_AddrStrobe,
LMB1_ReadStrobe,
LMB1_WriteStrobe,
LMB1_BE,
Sl1_DBus,
Sl1_Ready,
Sl1_Wait,
Sl1_UE,
Sl1_CE,
LMB2_ABus,
LMB2_WriteDBus,
LMB2_AddrStrobe,
LMB2_ReadStrobe,
LMB2_WriteStrobe,
LMB2_BE,
Sl2_DBus,
Sl2_Ready,
Sl2_Wait,
Sl2_UE,
Sl2_CE,
LMB3_ABus,
LMB3_WriteDBus,
LMB3_AddrStrobe,
LMB3_ReadStrobe,
LMB3_WriteStrobe,
LMB3_BE,
Sl3_DBus,
Sl3_Ready,
Sl3_Wait,
Sl3_UE,
Sl3_CE,
BRAM_Rst_A,
BRAM_Clk_A,
BRAM_Addr_A,
BRAM_EN_A,
BRAM_WEN_A,
BRAM_Dout_A,
BRAM_Din_A,
S_AXI_CTRL_ACLK,
S_AXI_CTRL_ARESETN,
S_AXI_CTRL_AWADDR,
S_AXI_CTRL_AWVALID,
S_AXI_CTRL_AWREADY,
S_AXI_CTRL_WDATA,
S_AXI_CTRL_WSTRB,
S_AXI_CTRL_WVALID,
S_AXI_CTRL_WREADY,
S_AXI_CTRL_BRESP,
S_AXI_CTRL_BVALID,
S_AXI_CTRL_BREADY,
S_AXI_CTRL_ARADDR,
S_AXI_CTRL_ARVALID,
S_AXI_CTRL_ARREADY,
S_AXI_CTRL_RDATA,
S_AXI_CTRL_RRESP,
S_AXI_CTRL_RVALID,
S_AXI_CTRL_RREADY,
UE,
CE,
Interrupt);
input LMB_Clk;
input LMB_Rst;
input [0:31]LMB_ABus;
input [0:31]LMB_WriteDBus;
input LMB_AddrStrobe;
input LMB_ReadStrobe;
input LMB_WriteStrobe;
input [0:3]LMB_BE;
output [0:31]Sl_DBus;
output Sl_Ready;
output Sl_Wait;
output Sl_UE;
output Sl_CE;
input [0:31]LMB1_ABus;
input [0:31]LMB1_WriteDBus;
input LMB1_AddrStrobe;
input LMB1_ReadStrobe;
input LMB1_WriteStrobe;
input [0:3]LMB1_BE;
output [0:31]Sl1_DBus;
output Sl1_Ready;
output Sl1_Wait;
output Sl1_UE;
output Sl1_CE;
input [0:31]LMB2_ABus;
input [0:31]LMB2_WriteDBus;
input LMB2_AddrStrobe;
input LMB2_ReadStrobe;
input LMB2_WriteStrobe;
input [0:3]LMB2_BE;
output [0:31]Sl2_DBus;
output Sl2_Ready;
output Sl2_Wait;
output Sl2_UE;
output Sl2_CE;
input [0:31]LMB3_ABus;
input [0:31]LMB3_WriteDBus;
input LMB3_AddrStrobe;
input LMB3_ReadStrobe;
input LMB3_WriteStrobe;
input [0:3]LMB3_BE;
output [0:31]Sl3_DBus;
output Sl3_Ready;
output Sl3_Wait;
output Sl3_UE;
output Sl3_CE;
output BRAM_Rst_A;
output BRAM_Clk_A;
output [0:31]BRAM_Addr_A;
output BRAM_EN_A;
output [0:3]BRAM_WEN_A;
output [0:31]BRAM_Dout_A;
input [0:31]BRAM_Din_A;
input S_AXI_CTRL_ACLK;
input S_AXI_CTRL_ARESETN;
input [31:0]S_AXI_CTRL_AWADDR;
input S_AXI_CTRL_AWVALID;
output S_AXI_CTRL_AWREADY;
input [31:0]S_AXI_CTRL_WDATA;
input [3:0]S_AXI_CTRL_WSTRB;
input S_AXI_CTRL_WVALID;
output S_AXI_CTRL_WREADY;
output [1:0]S_AXI_CTRL_BRESP;
output S_AXI_CTRL_BVALID;
input S_AXI_CTRL_BREADY;
input [31:0]S_AXI_CTRL_ARADDR;
input S_AXI_CTRL_ARVALID;
output S_AXI_CTRL_ARREADY;
output [31:0]S_AXI_CTRL_RDATA;
output [1:0]S_AXI_CTRL_RRESP;
output S_AXI_CTRL_RVALID;
input S_AXI_CTRL_RREADY;
output UE;
output CE;
output Interrupt;
wire \<const0> ;
wire [0:31]BRAM_Din_A;
wire [0:3]BRAM_WEN_A;
wire [0:31]LMB_ABus;
wire LMB_AddrStrobe;
wire [0:3]LMB_BE;
wire LMB_Clk;
wire LMB_Rst;
wire [0:31]LMB_WriteDBus;
wire LMB_WriteStrobe;
wire \No_ECC.Sl_Rdy_i_1_n_0 ;
wire \No_ECC.lmb_as_i_1_n_0 ;
wire Sl_Rdy;
wire Sl_Ready;
wire lmb_as;
assign BRAM_Addr_A[0:31] = LMB_ABus;
assign BRAM_Clk_A = LMB_Clk;
assign BRAM_Dout_A[0:31] = LMB_WriteDBus;
assign BRAM_EN_A = LMB_AddrStrobe;
assign BRAM_Rst_A = \<const0> ;
assign CE = \<const0> ;
assign Interrupt = \<const0> ;
assign S_AXI_CTRL_ARREADY = \<const0> ;
assign S_AXI_CTRL_AWREADY = \<const0> ;
assign S_AXI_CTRL_BRESP[1] = \<const0> ;
assign S_AXI_CTRL_BRESP[0] = \<const0> ;
assign S_AXI_CTRL_BVALID = \<const0> ;
assign S_AXI_CTRL_RDATA[31] = \<const0> ;
assign S_AXI_CTRL_RDATA[30] = \<const0> ;
assign S_AXI_CTRL_RDATA[29] = \<const0> ;
assign S_AXI_CTRL_RDATA[28] = \<const0> ;
assign S_AXI_CTRL_RDATA[27] = \<const0> ;
assign S_AXI_CTRL_RDATA[26] = \<const0> ;
assign S_AXI_CTRL_RDATA[25] = \<const0> ;
assign S_AXI_CTRL_RDATA[24] = \<const0> ;
assign S_AXI_CTRL_RDATA[23] = \<const0> ;
assign S_AXI_CTRL_RDATA[22] = \<const0> ;
assign S_AXI_CTRL_RDATA[21] = \<const0> ;
assign S_AXI_CTRL_RDATA[20] = \<const0> ;
assign S_AXI_CTRL_RDATA[19] = \<const0> ;
assign S_AXI_CTRL_RDATA[18] = \<const0> ;
assign S_AXI_CTRL_RDATA[17] = \<const0> ;
assign S_AXI_CTRL_RDATA[16] = \<const0> ;
assign S_AXI_CTRL_RDATA[15] = \<const0> ;
assign S_AXI_CTRL_RDATA[14] = \<const0> ;
assign S_AXI_CTRL_RDATA[13] = \<const0> ;
assign S_AXI_CTRL_RDATA[12] = \<const0> ;
assign S_AXI_CTRL_RDATA[11] = \<const0> ;
assign S_AXI_CTRL_RDATA[10] = \<const0> ;
assign S_AXI_CTRL_RDATA[9] = \<const0> ;
assign S_AXI_CTRL_RDATA[8] = \<const0> ;
assign S_AXI_CTRL_RDATA[7] = \<const0> ;
assign S_AXI_CTRL_RDATA[6] = \<const0> ;
assign S_AXI_CTRL_RDATA[5] = \<const0> ;
assign S_AXI_CTRL_RDATA[4] = \<const0> ;
assign S_AXI_CTRL_RDATA[3] = \<const0> ;
assign S_AXI_CTRL_RDATA[2] = \<const0> ;
assign S_AXI_CTRL_RDATA[1] = \<const0> ;
assign S_AXI_CTRL_RDATA[0] = \<const0> ;
assign S_AXI_CTRL_RRESP[1] = \<const0> ;
assign S_AXI_CTRL_RRESP[0] = \<const0> ;
assign S_AXI_CTRL_RVALID = \<const0> ;
assign S_AXI_CTRL_WREADY = \<const0> ;
assign Sl1_CE = \<const0> ;
assign Sl1_DBus[0] = \<const0> ;
assign Sl1_DBus[1] = \<const0> ;
assign Sl1_DBus[2] = \<const0> ;
assign Sl1_DBus[3] = \<const0> ;
assign Sl1_DBus[4] = \<const0> ;
assign Sl1_DBus[5] = \<const0> ;
assign Sl1_DBus[6] = \<const0> ;
assign Sl1_DBus[7] = \<const0> ;
assign Sl1_DBus[8] = \<const0> ;
assign Sl1_DBus[9] = \<const0> ;
assign Sl1_DBus[10] = \<const0> ;
assign Sl1_DBus[11] = \<const0> ;
assign Sl1_DBus[12] = \<const0> ;
assign Sl1_DBus[13] = \<const0> ;
assign Sl1_DBus[14] = \<const0> ;
assign Sl1_DBus[15] = \<const0> ;
assign Sl1_DBus[16] = \<const0> ;
assign Sl1_DBus[17] = \<const0> ;
assign Sl1_DBus[18] = \<const0> ;
assign Sl1_DBus[19] = \<const0> ;
assign Sl1_DBus[20] = \<const0> ;
assign Sl1_DBus[21] = \<const0> ;
assign Sl1_DBus[22] = \<const0> ;
assign Sl1_DBus[23] = \<const0> ;
assign Sl1_DBus[24] = \<const0> ;
assign Sl1_DBus[25] = \<const0> ;
assign Sl1_DBus[26] = \<const0> ;
assign Sl1_DBus[27] = \<const0> ;
assign Sl1_DBus[28] = \<const0> ;
assign Sl1_DBus[29] = \<const0> ;
assign Sl1_DBus[30] = \<const0> ;
assign Sl1_DBus[31] = \<const0> ;
assign Sl1_Ready = \<const0> ;
assign Sl1_UE = \<const0> ;
assign Sl1_Wait = \<const0> ;
assign Sl2_CE = \<const0> ;
assign Sl2_DBus[0] = \<const0> ;
assign Sl2_DBus[1] = \<const0> ;
assign Sl2_DBus[2] = \<const0> ;
assign Sl2_DBus[3] = \<const0> ;
assign Sl2_DBus[4] = \<const0> ;
assign Sl2_DBus[5] = \<const0> ;
assign Sl2_DBus[6] = \<const0> ;
assign Sl2_DBus[7] = \<const0> ;
assign Sl2_DBus[8] = \<const0> ;
assign Sl2_DBus[9] = \<const0> ;
assign Sl2_DBus[10] = \<const0> ;
assign Sl2_DBus[11] = \<const0> ;
assign Sl2_DBus[12] = \<const0> ;
assign Sl2_DBus[13] = \<const0> ;
assign Sl2_DBus[14] = \<const0> ;
assign Sl2_DBus[15] = \<const0> ;
assign Sl2_DBus[16] = \<const0> ;
assign Sl2_DBus[17] = \<const0> ;
assign Sl2_DBus[18] = \<const0> ;
assign Sl2_DBus[19] = \<const0> ;
assign Sl2_DBus[20] = \<const0> ;
assign Sl2_DBus[21] = \<const0> ;
assign Sl2_DBus[22] = \<const0> ;
assign Sl2_DBus[23] = \<const0> ;
assign Sl2_DBus[24] = \<const0> ;
assign Sl2_DBus[25] = \<const0> ;
assign Sl2_DBus[26] = \<const0> ;
assign Sl2_DBus[27] = \<const0> ;
assign Sl2_DBus[28] = \<const0> ;
assign Sl2_DBus[29] = \<const0> ;
assign Sl2_DBus[30] = \<const0> ;
assign Sl2_DBus[31] = \<const0> ;
assign Sl2_Ready = \<const0> ;
assign Sl2_UE = \<const0> ;
assign Sl2_Wait = \<const0> ;
assign Sl3_CE = \<const0> ;
assign Sl3_DBus[0] = \<const0> ;
assign Sl3_DBus[1] = \<const0> ;
assign Sl3_DBus[2] = \<const0> ;
assign Sl3_DBus[3] = \<const0> ;
assign Sl3_DBus[4] = \<const0> ;
assign Sl3_DBus[5] = \<const0> ;
assign Sl3_DBus[6] = \<const0> ;
assign Sl3_DBus[7] = \<const0> ;
assign Sl3_DBus[8] = \<const0> ;
assign Sl3_DBus[9] = \<const0> ;
assign Sl3_DBus[10] = \<const0> ;
assign Sl3_DBus[11] = \<const0> ;
assign Sl3_DBus[12] = \<const0> ;
assign Sl3_DBus[13] = \<const0> ;
assign Sl3_DBus[14] = \<const0> ;
assign Sl3_DBus[15] = \<const0> ;
assign Sl3_DBus[16] = \<const0> ;
assign Sl3_DBus[17] = \<const0> ;
assign Sl3_DBus[18] = \<const0> ;
assign Sl3_DBus[19] = \<const0> ;
assign Sl3_DBus[20] = \<const0> ;
assign Sl3_DBus[21] = \<const0> ;
assign Sl3_DBus[22] = \<const0> ;
assign Sl3_DBus[23] = \<const0> ;
assign Sl3_DBus[24] = \<const0> ;
assign Sl3_DBus[25] = \<const0> ;
assign Sl3_DBus[26] = \<const0> ;
assign Sl3_DBus[27] = \<const0> ;
assign Sl3_DBus[28] = \<const0> ;
assign Sl3_DBus[29] = \<const0> ;
assign Sl3_DBus[30] = \<const0> ;
assign Sl3_DBus[31] = \<const0> ;
assign Sl3_Ready = \<const0> ;
assign Sl3_UE = \<const0> ;
assign Sl3_Wait = \<const0> ;
assign Sl_CE = \<const0> ;
assign Sl_DBus[0:31] = BRAM_Din_A;
assign Sl_UE = \<const0> ;
assign Sl_Wait = \<const0> ;
assign UE = \<const0> ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h20))
\BRAM_WEN_A[0]_INST_0
(.I0(LMB_WriteStrobe),
.I1(LMB_ABus[0]),
.I2(LMB_BE[0]),
.O(BRAM_WEN_A[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h40))
\BRAM_WEN_A[1]_INST_0
(.I0(LMB_ABus[0]),
.I1(LMB_WriteStrobe),
.I2(LMB_BE[1]),
.O(BRAM_WEN_A[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
\BRAM_WEN_A[2]_INST_0
(.I0(LMB_ABus[0]),
.I1(LMB_WriteStrobe),
.I2(LMB_BE[2]),
.O(BRAM_WEN_A[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
\BRAM_WEN_A[3]_INST_0
(.I0(LMB_ABus[0]),
.I1(LMB_WriteStrobe),
.I2(LMB_BE[3]),
.O(BRAM_WEN_A[3]));
GND GND
(.G(\<const0> ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h1))
\No_ECC.Sl_Rdy_i_1
(.I0(LMB_ABus[0]),
.I1(LMB_Rst),
.O(\No_ECC.Sl_Rdy_i_1_n_0 ));
FDRE \No_ECC.Sl_Rdy_reg
(.C(LMB_Clk),
.CE(1'b1),
.D(\No_ECC.Sl_Rdy_i_1_n_0 ),
.Q(Sl_Rdy),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h2))
\No_ECC.lmb_as_i_1
(.I0(LMB_AddrStrobe),
.I1(LMB_Rst),
.O(\No_ECC.lmb_as_i_1_n_0 ));
FDRE \No_ECC.lmb_as_reg
(.C(LMB_Clk),
.CE(1'b1),
.D(\No_ECC.lmb_as_i_1_n_0 ),
.Q(lmb_as),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
Sl_Ready_INST_0
(.I0(Sl_Rdy),
.I1(lmb_as),
.O(Sl_Ready));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// Code ok to distribute
module autoasciienum_auto();
reg [2:0] /* auto enum sm_psm */ sm_psm;
reg [2:0] /* auto enum sm_ps2 */ sm_ps2;
localparam [2:0] // auto enum sm_psm
PSM_IDL = 0,
PSM_RST = 6,
PSM_ZOT = 7;
localparam [2:0] // auto enum sm_ps2
PS2_IDL = 0,
PS2_FOO = 1;
/*AUTOASCIIENUM("sm_psm", "_sm_psm__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_psm__ascii; // Decode of sm_psm
always @(sm_psm) begin
case ({sm_psm})
PSM_IDL: _sm_psm__ascii = "psmidl";
PSM_RST: _sm_psm__ascii = "psmrst";
PSM_ZOT: _sm_psm__ascii = "psmzot";
default: _sm_psm__ascii = "%Error";
endcase
end
// End of automatics
/*AUTOASCIIENUM("sm_ps2", "_sm_ps2__ascii", "_")*/
// Beginning of automatic ASCII enum decoding
reg [47:0] _sm_ps2__ascii; // Decode of sm_ps2
always @(sm_ps2) begin
case ({sm_ps2})
PS2_IDL: _sm_ps2__ascii = "ps2idl";
PS2_FOO: _sm_ps2__ascii = "ps2foo";
default: _sm_ps2__ascii = "%Error";
endcase
end
// End of automatics
endmodule : autoasciienum_auto
|
//------------------------------------------------------------------------------
// Title : Demo testbench
// Project : Tri-Mode Ethernet MAC
//------------------------------------------------------------------------------
// File : demo_tb.v
// -----------------------------------------------------------------------------
// (c) Copyright 2004-2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
// -----------------------------------------------------------------------------
// Description: This testbench will exercise the ports of the MAC core
// to demonstrate the functionality.
//------------------------------------------------------------------------------
//
// This testbench performs the following operations on the MAC core
// and its design example:
// - The MDIO interface will respond to a read request with data to prevent the
// example design thinking it is real hardware
// - Four frames are then pushed into the receiver from the PHY
// interface (GMII/MII or RGMII):
// The first is of minimum length (Length/Type = Length = 46 bytes).
// The second frame sets Length/Type to Type = 0x8000.
// The third frame has an error inserted.
// The fourth frame only sends 4 bytes of data: the remainder of the
// data field is padded up to the minimum frame length i.e. 46 bytes.
// - These frames are then parsed from the MAC into the MAC's design
// example. The design example provides a MAC user loopback
// function so that frames which are received without error will be
// looped back to the MAC transmitter and transmitted back to the
// testbench. The testbench verifies that this data matches that
// previously injected into the receiver.
//----------------------------------------------------------------------
// DEMONSTRATION TESTBENCH |
// |
// |
// ---------------------------------------------- |
// | TOP LEVEL WRAPPER (DUT) | |
// | ------------------- ---------------- | |
// | | USER LOOPBACK | | TRI-MODE | | |
// | | DESIGN EXAMPLE | | ETHERNET MAC | | |
// | | | | CORE | | |
// | | | | | | Monitor |
// | | ------->|--->| Tx |--------> Frames |
// | | | | | PHY | | |
// | | | | | I/F | | |
// | | | | | | | |
// | | | | | | | |
// | | | | | | | |
// | | | | | Rx | | |
// | | | | | PHY | | |
// | | --------|<---| I/F |<-------- Generate |
// | | | | | | Frames |
// | ------------------- ---------------- | |
// --------------------------------^------------- |
// | |
// | |
// Stimulate |
// Management I/F |
// (if present) |
// |
//----------------------------------------------------------------------
`timescale 1ps / 1ps
//------------------------------------------------------------------------------
// This module abstracts the frame data for simpler manipulation
//------------------------------------------------------------------------------
module frame_typ;
// data field
reg [7:0] data [0:61];
reg valid [0:61];
reg error [0:61];
// Indicate to the testbench that the frame contains an error
reg bad_frame;
`define FRAME_TYP [8*62+62+62+8*4+4+4+8*4+4+4+1:1]
reg `FRAME_TYP bits;
function `FRAME_TYP tobits;
input dummy;
begin
bits = {data[ 0], data[ 1], data[ 2], data[ 3], data[ 4],
data[ 5], data[ 6], data[ 7], data[ 8], data[ 9],
data[10], data[11], data[12], data[13], data[14],
data[15], data[16], data[17], data[18], data[19],
data[20], data[21], data[22], data[23], data[24],
data[25], data[26], data[27], data[28], data[29],
data[30], data[31], data[32], data[33], data[34],
data[35], data[36], data[37], data[38], data[39],
data[40], data[41], data[42], data[43], data[44],
data[45], data[46], data[47], data[48], data[49],
data[50], data[51], data[52], data[53], data[54],
data[55], data[56], data[57], data[58], data[59],
data[60], data[61],
valid[ 0], valid[ 1], valid[ 2], valid[ 3], valid[ 4],
valid[ 5], valid[ 6], valid[ 7], valid[ 8], valid[ 9],
valid[10], valid[11], valid[12], valid[13], valid[14],
valid[15], valid[16], valid[17], valid[18], valid[19],
valid[20], valid[21], valid[22], valid[23], valid[24],
valid[25], valid[26], valid[27], valid[28], valid[29],
valid[30], valid[31], valid[32], valid[33], valid[34],
valid[35], valid[36], valid[37], valid[38], valid[39],
valid[40], valid[41], valid[42], valid[43], valid[44],
valid[45], valid[46], valid[47], valid[48], valid[49],
valid[50], valid[51], valid[52], valid[53], valid[54],
valid[55], valid[56], valid[57], valid[58], valid[59],
valid[60], valid[61],
error[ 0], error[ 1], error[ 2], error[ 3], error[ 4],
error[ 5], error[ 6], error[ 7], error[ 8], error[ 9],
error[10], error[11], error[12], error[13], error[14],
error[15], error[16], error[17], error[18], error[19],
error[20], error[21], error[22], error[23], error[24],
error[25], error[26], error[27], error[28], error[29],
error[30], error[31], error[32], error[33], error[34],
error[35], error[36], error[37], error[38], error[39],
error[40], error[41], error[42], error[43], error[44],
error[45], error[46], error[47], error[48], error[49],
error[50], error[51], error[52], error[53], error[54],
error[55], error[56], error[57], error[58], error[59],
error[60], error[61],
bad_frame};
tobits = bits;
end
endfunction // tobits
task frombits;
input `FRAME_TYP frame;
begin
bits = frame;
{data[ 0], data[ 1], data[ 2], data[ 3], data[ 4],
data[ 5], data[ 6], data[ 7], data[ 8], data[ 9],
data[10], data[11], data[12], data[13], data[14],
data[15], data[16], data[17], data[18], data[19],
data[20], data[21], data[22], data[23], data[24],
data[25], data[26], data[27], data[28], data[29],
data[30], data[31], data[32], data[33], data[34],
data[35], data[36], data[37], data[38], data[39],
data[40], data[41], data[42], data[43], data[44],
data[45], data[46], data[47], data[48], data[49],
data[50], data[51], data[52], data[53], data[54],
data[55], data[56], data[57], data[58], data[59],
data[60], data[61],
valid[ 0], valid[ 1], valid[ 2], valid[ 3], valid[ 4],
valid[ 5], valid[ 6], valid[ 7], valid[ 8], valid[ 9],
valid[10], valid[11], valid[12], valid[13], valid[14],
valid[15], valid[16], valid[17], valid[18], valid[19],
valid[20], valid[21], valid[22], valid[23], valid[24],
valid[25], valid[26], valid[27], valid[28], valid[29],
valid[30], valid[31], valid[32], valid[33], valid[34],
valid[35], valid[36], valid[37], valid[38], valid[39],
valid[40], valid[41], valid[42], valid[43], valid[44],
valid[45], valid[46], valid[47], valid[48], valid[49],
valid[50], valid[51], valid[52], valid[53], valid[54],
valid[55], valid[56], valid[57], valid[58], valid[59],
valid[60], valid[61],
error[ 0], error[ 1], error[ 2], error[ 3], error[ 4],
error[ 5], error[ 6], error[ 7], error[ 8], error[ 9],
error[10], error[11], error[12], error[13], error[14],
error[15], error[16], error[17], error[18], error[19],
error[20], error[21], error[22], error[23], error[24],
error[25], error[26], error[27], error[28], error[29],
error[30], error[31], error[32], error[33], error[34],
error[35], error[36], error[37], error[38], error[39],
error[40], error[41], error[42], error[43], error[44],
error[45], error[46], error[47], error[48], error[49],
error[50], error[51], error[52], error[53], error[54],
error[55], error[56], error[57], error[58], error[59],
error[60], error[61],
bad_frame} = bits;
end
endtask // frombits
endmodule // frame_typ
//------------------------------------------------------------------------------
// This module is the demonstration testbench
//------------------------------------------------------------------------------
module testbench;
//parameter TB_MODE = "BIST";
parameter TB_MODE = "DEMO";
//----------------------------------------------------------------------------
// types to support frame data
//----------------------------------------------------------------------------
frame_typ frame0();
frame_typ frame1();
frame_typ frame2();
frame_typ frame3();
frame_typ rx_stimulus_working_frame();
frame_typ tx_monitor_working_frame();
//----------------------------------------------------------------------------
// Stimulus - Frame data
//----------------------------------------------------------------------------
// The following constant holds the stimulus for the testbench. It is
// an ordered array of frames, with frame 0 the first to be injected
// into the core transmit interface by the testbench.
//----------------------------------------------------------------------------
initial
begin
//-----------
// Frame 0
//-----------
frame0.data[0] = 8'hDA; frame0.valid[0] = 1'b1; frame0.error[0] = 1'b0; // Destination Address (DA)
frame0.data[1] = 8'h02; frame0.valid[1] = 1'b1; frame0.error[1] = 1'b0;
frame0.data[2] = 8'h03; frame0.valid[2] = 1'b1; frame0.error[2] = 1'b0;
frame0.data[3] = 8'h04; frame0.valid[3] = 1'b1; frame0.error[3] = 1'b0;
frame0.data[4] = 8'h05; frame0.valid[4] = 1'b1; frame0.error[4] = 1'b0;
frame0.data[5] = 8'h06; frame0.valid[5] = 1'b1; frame0.error[5] = 1'b0;
frame0.data[6] = 8'h5A; frame0.valid[6] = 1'b1; frame0.error[6] = 1'b0; // Source Address (5A)
frame0.data[7] = 8'h02; frame0.valid[7] = 1'b1; frame0.error[7] = 1'b0;
frame0.data[8] = 8'h03; frame0.valid[8] = 1'b1; frame0.error[8] = 1'b0;
frame0.data[9] = 8'h04; frame0.valid[9] = 1'b1; frame0.error[9] = 1'b0;
frame0.data[10] = 8'h05; frame0.valid[10] = 1'b1; frame0.error[10] = 1'b0;
frame0.data[11] = 8'h06; frame0.valid[11] = 1'b1; frame0.error[11] = 1'b0;
frame0.data[12] = 8'h00; frame0.valid[12] = 1'b1; frame0.error[12] = 1'b0;
frame0.data[13] = 8'h2E; frame0.valid[13] = 1'b1; frame0.error[13] = 1'b0; // Length/Type = Length = 46
frame0.data[14] = 8'h01; frame0.valid[14] = 1'b1; frame0.error[14] = 1'b0;
frame0.data[15] = 8'h02; frame0.valid[15] = 1'b1; frame0.error[15] = 1'b0;
frame0.data[16] = 8'h03; frame0.valid[16] = 1'b1; frame0.error[16] = 1'b0;
frame0.data[17] = 8'h04; frame0.valid[17] = 1'b1; frame0.error[17] = 1'b0;
frame0.data[18] = 8'h05; frame0.valid[18] = 1'b1; frame0.error[18] = 1'b0;
frame0.data[19] = 8'h06; frame0.valid[19] = 1'b1; frame0.error[19] = 1'b0;
frame0.data[20] = 8'h07; frame0.valid[20] = 1'b1; frame0.error[20] = 1'b0;
frame0.data[21] = 8'h08; frame0.valid[21] = 1'b1; frame0.error[21] = 1'b0;
frame0.data[22] = 8'h09; frame0.valid[22] = 1'b1; frame0.error[22] = 1'b0;
frame0.data[23] = 8'h0A; frame0.valid[23] = 1'b1; frame0.error[23] = 1'b0;
frame0.data[24] = 8'h0B; frame0.valid[24] = 1'b1; frame0.error[24] = 1'b0;
frame0.data[25] = 8'h0C; frame0.valid[25] = 1'b1; frame0.error[25] = 1'b0;
frame0.data[26] = 8'h0D; frame0.valid[26] = 1'b1; frame0.error[26] = 1'b0;
frame0.data[27] = 8'h0E; frame0.valid[27] = 1'b1; frame0.error[27] = 1'b0;
frame0.data[28] = 8'h0F; frame0.valid[28] = 1'b1; frame0.error[28] = 1'b0;
frame0.data[29] = 8'h10; frame0.valid[29] = 1'b1; frame0.error[29] = 1'b0;
frame0.data[30] = 8'h11; frame0.valid[30] = 1'b1; frame0.error[30] = 1'b0;
frame0.data[31] = 8'h12; frame0.valid[31] = 1'b1; frame0.error[31] = 1'b0;
frame0.data[32] = 8'h13; frame0.valid[32] = 1'b1; frame0.error[32] = 1'b0;
frame0.data[33] = 8'h14; frame0.valid[33] = 1'b1; frame0.error[33] = 1'b0;
frame0.data[34] = 8'h15; frame0.valid[34] = 1'b1; frame0.error[34] = 1'b0;
frame0.data[35] = 8'h16; frame0.valid[35] = 1'b1; frame0.error[35] = 1'b0;
frame0.data[36] = 8'h17; frame0.valid[36] = 1'b1; frame0.error[36] = 1'b0;
frame0.data[37] = 8'h18; frame0.valid[37] = 1'b1; frame0.error[37] = 1'b0;
frame0.data[38] = 8'h19; frame0.valid[38] = 1'b1; frame0.error[38] = 1'b0;
frame0.data[39] = 8'h1A; frame0.valid[39] = 1'b1; frame0.error[39] = 1'b0;
frame0.data[40] = 8'h1B; frame0.valid[40] = 1'b1; frame0.error[40] = 1'b0;
frame0.data[41] = 8'h1C; frame0.valid[41] = 1'b1; frame0.error[41] = 1'b0;
frame0.data[42] = 8'h1D; frame0.valid[42] = 1'b1; frame0.error[42] = 1'b0;
frame0.data[43] = 8'h1E; frame0.valid[43] = 1'b1; frame0.error[43] = 1'b0;
frame0.data[44] = 8'h1F; frame0.valid[44] = 1'b1; frame0.error[44] = 1'b0;
frame0.data[45] = 8'h20; frame0.valid[45] = 1'b1; frame0.error[45] = 1'b0;
frame0.data[46] = 8'h21; frame0.valid[46] = 1'b1; frame0.error[46] = 1'b0;
frame0.data[47] = 8'h22; frame0.valid[47] = 1'b1; frame0.error[47] = 1'b0;
frame0.data[48] = 8'h23; frame0.valid[48] = 1'b1; frame0.error[48] = 1'b0;
frame0.data[49] = 8'h24; frame0.valid[49] = 1'b1; frame0.error[49] = 1'b0;
frame0.data[50] = 8'h25; frame0.valid[50] = 1'b1; frame0.error[50] = 1'b0;
frame0.data[51] = 8'h26; frame0.valid[51] = 1'b1; frame0.error[51] = 1'b0;
frame0.data[52] = 8'h27; frame0.valid[52] = 1'b1; frame0.error[52] = 1'b0;
frame0.data[53] = 8'h28; frame0.valid[53] = 1'b1; frame0.error[53] = 1'b0;
frame0.data[54] = 8'h29; frame0.valid[54] = 1'b1; frame0.error[54] = 1'b0;
frame0.data[55] = 8'h2A; frame0.valid[55] = 1'b1; frame0.error[55] = 1'b0;
frame0.data[56] = 8'h2B; frame0.valid[56] = 1'b1; frame0.error[56] = 1'b0;
frame0.data[57] = 8'h2C; frame0.valid[57] = 1'b1; frame0.error[57] = 1'b0;
frame0.data[58] = 8'h2D; frame0.valid[58] = 1'b1; frame0.error[58] = 1'b0;
frame0.data[59] = 8'h2E; frame0.valid[59] = 1'b1; frame0.error[59] = 1'b0; // 46th Byte of Data
// unused
frame0.data[60] = 8'h00; frame0.valid[60] = 1'b0; frame0.error[60] = 1'b0;
frame0.data[61] = 8'h00; frame0.valid[61] = 1'b0; frame0.error[61] = 1'b0;
// No error in this frame
frame0.bad_frame = 1'b0;
//-----------
// Frame 1
//-----------
frame1.data[0] = 8'hDA; frame1.valid[0] = 1'b1; frame1.error[0] = 1'b0; // Destination Address (DA)
frame1.data[1] = 8'h02; frame1.valid[1] = 1'b1; frame1.error[1] = 1'b0;
frame1.data[2] = 8'h03; frame1.valid[2] = 1'b1; frame1.error[2] = 1'b0;
frame1.data[3] = 8'h04; frame1.valid[3] = 1'b1; frame1.error[3] = 1'b0;
frame1.data[4] = 8'h05; frame1.valid[4] = 1'b1; frame1.error[4] = 1'b0;
frame1.data[5] = 8'h06; frame1.valid[5] = 1'b1; frame1.error[5] = 1'b0;
frame1.data[6] = 8'h5A; frame1.valid[6] = 1'b1; frame1.error[6] = 1'b0; // Source Address (5A)
frame1.data[7] = 8'h02; frame1.valid[7] = 1'b1; frame1.error[7] = 1'b0;
frame1.data[8] = 8'h03; frame1.valid[8] = 1'b1; frame1.error[8] = 1'b0;
frame1.data[9] = 8'h04; frame1.valid[9] = 1'b1; frame1.error[9] = 1'b0;
frame1.data[10] = 8'h05; frame1.valid[10] = 1'b1; frame1.error[10] = 1'b0;
frame1.data[11] = 8'h06; frame1.valid[11] = 1'b1; frame1.error[11] = 1'b0;
frame1.data[12] = 8'h80; frame1.valid[12] = 1'b1; frame1.error[12] = 1'b0; // Length/Type = Type = 8000
frame1.data[13] = 8'h00; frame1.valid[13] = 1'b1; frame1.error[13] = 1'b0;
frame1.data[14] = 8'h01; frame1.valid[14] = 1'b1; frame1.error[14] = 1'b0;
frame1.data[15] = 8'h02; frame1.valid[15] = 1'b1; frame1.error[15] = 1'b0;
frame1.data[16] = 8'h03; frame1.valid[16] = 1'b1; frame1.error[16] = 1'b0;
frame1.data[17] = 8'h04; frame1.valid[17] = 1'b1; frame1.error[17] = 1'b0;
frame1.data[18] = 8'h05; frame1.valid[18] = 1'b1; frame1.error[18] = 1'b0;
frame1.data[19] = 8'h06; frame1.valid[19] = 1'b1; frame1.error[19] = 1'b0;
frame1.data[20] = 8'h07; frame1.valid[20] = 1'b1; frame1.error[20] = 1'b0;
frame1.data[21] = 8'h08; frame1.valid[21] = 1'b1; frame1.error[21] = 1'b0;
frame1.data[22] = 8'h09; frame1.valid[22] = 1'b1; frame1.error[22] = 1'b0;
frame1.data[23] = 8'h0A; frame1.valid[23] = 1'b1; frame1.error[23] = 1'b0;
frame1.data[24] = 8'h0B; frame1.valid[24] = 1'b1; frame1.error[24] = 1'b0;
frame1.data[25] = 8'h0C; frame1.valid[25] = 1'b1; frame1.error[25] = 1'b0;
frame1.data[26] = 8'h0D; frame1.valid[26] = 1'b1; frame1.error[26] = 1'b0;
frame1.data[27] = 8'h0E; frame1.valid[27] = 1'b1; frame1.error[27] = 1'b0;
frame1.data[28] = 8'h0F; frame1.valid[28] = 1'b1; frame1.error[28] = 1'b0;
frame1.data[29] = 8'h10; frame1.valid[29] = 1'b1; frame1.error[29] = 1'b0;
frame1.data[30] = 8'h11; frame1.valid[30] = 1'b1; frame1.error[30] = 1'b0;
frame1.data[31] = 8'h12; frame1.valid[31] = 1'b1; frame1.error[31] = 1'b0;
frame1.data[32] = 8'h13; frame1.valid[32] = 1'b1; frame1.error[32] = 1'b0;
frame1.data[33] = 8'h14; frame1.valid[33] = 1'b1; frame1.error[33] = 1'b0;
frame1.data[34] = 8'h15; frame1.valid[34] = 1'b1; frame1.error[34] = 1'b0;
frame1.data[35] = 8'h16; frame1.valid[35] = 1'b1; frame1.error[35] = 1'b0;
frame1.data[36] = 8'h17; frame1.valid[36] = 1'b1; frame1.error[36] = 1'b0;
frame1.data[37] = 8'h18; frame1.valid[37] = 1'b1; frame1.error[37] = 1'b0;
frame1.data[38] = 8'h19; frame1.valid[38] = 1'b1; frame1.error[38] = 1'b0;
frame1.data[39] = 8'h1A; frame1.valid[39] = 1'b1; frame1.error[39] = 1'b0;
frame1.data[40] = 8'h1B; frame1.valid[40] = 1'b1; frame1.error[40] = 1'b0;
frame1.data[41] = 8'h1C; frame1.valid[41] = 1'b1; frame1.error[41] = 1'b0;
frame1.data[42] = 8'h1D; frame1.valid[42] = 1'b1; frame1.error[42] = 1'b0;
frame1.data[43] = 8'h1E; frame1.valid[43] = 1'b1; frame1.error[43] = 1'b0;
frame1.data[44] = 8'h1F; frame1.valid[44] = 1'b1; frame1.error[44] = 1'b0;
frame1.data[45] = 8'h20; frame1.valid[45] = 1'b1; frame1.error[45] = 1'b0;
frame1.data[46] = 8'h21; frame1.valid[46] = 1'b1; frame1.error[46] = 1'b0;
frame1.data[47] = 8'h22; frame1.valid[47] = 1'b1; frame1.error[47] = 1'b0;
frame1.data[48] = 8'h23; frame1.valid[48] = 1'b1; frame1.error[48] = 1'b0;
frame1.data[49] = 8'h24; frame1.valid[49] = 1'b1; frame1.error[49] = 1'b0;
frame1.data[50] = 8'h25; frame1.valid[50] = 1'b1; frame1.error[50] = 1'b0;
frame1.data[51] = 8'h26; frame1.valid[51] = 1'b1; frame1.error[51] = 1'b0;
frame1.data[52] = 8'h27; frame1.valid[52] = 1'b1; frame1.error[52] = 1'b0;
frame1.data[53] = 8'h28; frame1.valid[53] = 1'b1; frame1.error[53] = 1'b0;
frame1.data[54] = 8'h29; frame1.valid[54] = 1'b1; frame1.error[54] = 1'b0;
frame1.data[55] = 8'h2A; frame1.valid[55] = 1'b1; frame1.error[55] = 1'b0;
frame1.data[56] = 8'h2B; frame1.valid[56] = 1'b1; frame1.error[56] = 1'b0;
frame1.data[57] = 8'h2C; frame1.valid[57] = 1'b1; frame1.error[57] = 1'b0;
frame1.data[58] = 8'h2D; frame1.valid[58] = 1'b1; frame1.error[58] = 1'b0;
frame1.data[59] = 8'h2E; frame1.valid[59] = 1'b1; frame1.error[59] = 1'b0;
frame1.data[60] = 8'h2F; frame1.valid[60] = 1'b1; frame1.error[60] = 1'b0; // 47th Data byte
// unused
frame1.data[61] = 8'h00; frame1.valid[61] = 1'b0; frame1.error[61] = 1'b0;
// No error in this frame
frame1.bad_frame = 1'b0;
//-----------
// Frame 2
//-----------
frame2.data[0] = 8'hDA; frame2.valid[0] = 1'b1; frame2.error[0] = 1'b0; // Destination Address (DA)
frame2.data[1] = 8'h02; frame2.valid[1] = 1'b1; frame2.error[1] = 1'b0;
frame2.data[2] = 8'h03; frame2.valid[2] = 1'b1; frame2.error[2] = 1'b0;
frame2.data[3] = 8'h04; frame2.valid[3] = 1'b1; frame2.error[3] = 1'b0;
frame2.data[4] = 8'h05; frame2.valid[4] = 1'b1; frame2.error[4] = 1'b0;
frame2.data[5] = 8'h06; frame2.valid[5] = 1'b1; frame2.error[5] = 1'b0;
frame2.data[6] = 8'h5A; frame2.valid[6] = 1'b1; frame2.error[6] = 1'b0; // Source Address (5A)
frame2.data[7] = 8'h02; frame2.valid[7] = 1'b1; frame2.error[7] = 1'b0;
frame2.data[8] = 8'h03; frame2.valid[8] = 1'b1; frame2.error[8] = 1'b0;
frame2.data[9] = 8'h04; frame2.valid[9] = 1'b1; frame2.error[9] = 1'b0;
frame2.data[10] = 8'h05; frame2.valid[10] = 1'b1; frame2.error[10] = 1'b0;
frame2.data[11] = 8'h06; frame2.valid[11] = 1'b1; frame2.error[11] = 1'b0;
frame2.data[12] = 8'h00; frame2.valid[12] = 1'b1; frame2.error[12] = 1'b0;
frame2.data[13] = 8'h2E; frame2.valid[13] = 1'b1; frame2.error[13] = 1'b0; // Length/Type = Length = 46
frame2.data[14] = 8'h01; frame2.valid[14] = 1'b1; frame2.error[14] = 1'b0;
frame2.data[15] = 8'h02; frame2.valid[15] = 1'b1; frame2.error[15] = 1'b0;
frame2.data[16] = 8'h03; frame2.valid[16] = 1'b1; frame2.error[16] = 1'b0;
frame2.data[17] = 8'h00; frame2.valid[17] = 1'b1; frame2.error[17] = 1'b0; // Underrun this frame
frame2.data[18] = 8'h00; frame2.valid[18] = 1'b1; frame2.error[18] = 1'b0;
frame2.data[19] = 8'h00; frame2.valid[19] = 1'b1; frame2.error[19] = 1'b0;
frame2.data[20] = 8'h00; frame2.valid[20] = 1'b1; frame2.error[20] = 1'b0;
frame2.data[21] = 8'h00; frame2.valid[21] = 1'b1; frame2.error[21] = 1'b0;
frame2.data[22] = 8'h00; frame2.valid[22] = 1'b1; frame2.error[22] = 1'b0;
frame2.data[23] = 8'h00; frame2.valid[23] = 1'b1; frame2.error[23] = 1'b1; // Error asserted
frame2.data[24] = 8'h00; frame2.valid[24] = 1'b1; frame2.error[24] = 1'b0;
frame2.data[25] = 8'h00; frame2.valid[25] = 1'b1; frame2.error[25] = 1'b0;
frame2.data[26] = 8'h00; frame2.valid[26] = 1'b1; frame2.error[26] = 1'b0;
frame2.data[27] = 8'h00; frame2.valid[27] = 1'b1; frame2.error[27] = 1'b0;
frame2.data[28] = 8'h00; frame2.valid[28] = 1'b1; frame2.error[28] = 1'b0;
frame2.data[29] = 8'h00; frame2.valid[29] = 1'b1; frame2.error[29] = 1'b0;
frame2.data[30] = 8'h00; frame2.valid[30] = 1'b1; frame2.error[30] = 1'b0;
frame2.data[31] = 8'h00; frame2.valid[31] = 1'b1; frame2.error[31] = 1'b0;
frame2.data[32] = 8'h00; frame2.valid[32] = 1'b1; frame2.error[32] = 1'b0;
frame2.data[33] = 8'h00; frame2.valid[33] = 1'b1; frame2.error[33] = 1'b0;
frame2.data[34] = 8'h00; frame2.valid[34] = 1'b1; frame2.error[34] = 1'b0;
frame2.data[35] = 8'h00; frame2.valid[35] = 1'b1; frame2.error[35] = 1'b0;
frame2.data[36] = 8'h00; frame2.valid[36] = 1'b1; frame2.error[36] = 1'b0;
frame2.data[37] = 8'h00; frame2.valid[37] = 1'b1; frame2.error[37] = 1'b0;
frame2.data[38] = 8'h00; frame2.valid[38] = 1'b1; frame2.error[38] = 1'b0;
frame2.data[39] = 8'h00; frame2.valid[39] = 1'b1; frame2.error[39] = 1'b0;
frame2.data[40] = 8'h00; frame2.valid[40] = 1'b1; frame2.error[40] = 1'b0;
frame2.data[41] = 8'h00; frame2.valid[41] = 1'b1; frame2.error[41] = 1'b0;
frame2.data[42] = 8'h00; frame2.valid[42] = 1'b1; frame2.error[42] = 1'b0;
frame2.data[43] = 8'h00; frame2.valid[43] = 1'b1; frame2.error[43] = 1'b0;
frame2.data[44] = 8'h00; frame2.valid[44] = 1'b1; frame2.error[44] = 1'b0;
frame2.data[45] = 8'h00; frame2.valid[45] = 1'b1; frame2.error[45] = 1'b0;
frame2.data[46] = 8'h00; frame2.valid[46] = 1'b1; frame2.error[46] = 1'b0;
frame2.data[47] = 8'h00; frame2.valid[47] = 1'b1; frame2.error[47] = 1'b0;
frame2.data[48] = 8'h00; frame2.valid[48] = 1'b1; frame2.error[48] = 1'b0;
frame2.data[49] = 8'h00; frame2.valid[49] = 1'b1; frame2.error[49] = 1'b0;
frame2.data[50] = 8'h00; frame2.valid[50] = 1'b1; frame2.error[50] = 1'b0;
frame2.data[51] = 8'h00; frame2.valid[51] = 1'b1; frame2.error[51] = 1'b0;
frame2.data[52] = 8'h00; frame2.valid[52] = 1'b1; frame2.error[52] = 1'b0;
frame2.data[53] = 8'h00; frame2.valid[53] = 1'b1; frame2.error[53] = 1'b0;
frame2.data[54] = 8'h00; frame2.valid[54] = 1'b1; frame2.error[54] = 1'b0;
frame2.data[55] = 8'h00; frame2.valid[55] = 1'b1; frame2.error[55] = 1'b0;
frame2.data[56] = 8'h00; frame2.valid[56] = 1'b1; frame2.error[56] = 1'b0;
frame2.data[57] = 8'h00; frame2.valid[57] = 1'b1; frame2.error[57] = 1'b0;
frame2.data[58] = 8'h00; frame2.valid[58] = 1'b1; frame2.error[58] = 1'b0;
frame2.data[59] = 8'h00; frame2.valid[59] = 1'b1; frame2.error[59] = 1'b0;
// unused
frame2.data[60] = 8'h00; frame2.valid[60] = 1'b0; frame2.error[60] = 1'b0;
frame2.data[61] = 8'h00; frame2.valid[61] = 1'b0; frame2.error[61] = 1'b0;
// Error this frame
frame2.bad_frame = 1'b1;
//-----------
// Frame 3
//-----------
frame3.data[0] = 8'hDA; frame3.valid[0] = 1'b1; frame3.error[0] = 1'b0; // Destination Address (DA)
frame3.data[1] = 8'h02; frame3.valid[1] = 1'b1; frame3.error[1] = 1'b0;
frame3.data[2] = 8'h03; frame3.valid[2] = 1'b1; frame3.error[2] = 1'b0;
frame3.data[3] = 8'h04; frame3.valid[3] = 1'b1; frame3.error[3] = 1'b0;
frame3.data[4] = 8'h05; frame3.valid[4] = 1'b1; frame3.error[4] = 1'b0;
frame3.data[5] = 8'h06; frame3.valid[5] = 1'b1; frame3.error[5] = 1'b0;
frame3.data[6] = 8'h5A; frame3.valid[6] = 1'b1; frame3.error[6] = 1'b0; // Source Address (5A)
frame3.data[7] = 8'h02; frame3.valid[7] = 1'b1; frame3.error[7] = 1'b0;
frame3.data[8] = 8'h03; frame3.valid[8] = 1'b1; frame3.error[8] = 1'b0;
frame3.data[9] = 8'h04; frame3.valid[9] = 1'b1; frame3.error[9] = 1'b0;
frame3.data[10] = 8'h05; frame3.valid[10] = 1'b1; frame3.error[10] = 1'b0;
frame3.data[11] = 8'h06; frame3.valid[11] = 1'b1; frame3.error[11] = 1'b0;
frame3.data[12] = 8'h00; frame3.valid[12] = 1'b1; frame3.error[12] = 1'b0;
frame3.data[13] = 8'h03; frame3.valid[13] = 1'b1; frame3.error[13] = 1'b0; // Length/Type = Length = 03
frame3.data[14] = 8'h01; frame3.valid[14] = 1'b1; frame3.error[14] = 1'b0; // Therefore padding is required
frame3.data[15] = 8'h02; frame3.valid[15] = 1'b1; frame3.error[15] = 1'b0;
frame3.data[16] = 8'h03; frame3.valid[16] = 1'b1; frame3.error[16] = 1'b0;
frame3.data[17] = 8'h00; frame3.valid[17] = 1'b1; frame3.error[17] = 1'b0; // Padding starts here
frame3.data[18] = 8'h00; frame3.valid[18] = 1'b1; frame3.error[18] = 1'b0;
frame3.data[19] = 8'h00; frame3.valid[19] = 1'b1; frame3.error[19] = 1'b0;
frame3.data[20] = 8'h00; frame3.valid[20] = 1'b1; frame3.error[20] = 1'b0;
frame3.data[21] = 8'h00; frame3.valid[21] = 1'b1; frame3.error[21] = 1'b0;
frame3.data[22] = 8'h00; frame3.valid[22] = 1'b1; frame3.error[22] = 1'b0;
frame3.data[23] = 8'h00; frame3.valid[23] = 1'b1; frame3.error[23] = 1'b0;
frame3.data[24] = 8'h00; frame3.valid[24] = 1'b1; frame3.error[24] = 1'b0;
frame3.data[25] = 8'h00; frame3.valid[25] = 1'b1; frame3.error[25] = 1'b0;
frame3.data[26] = 8'h00; frame3.valid[26] = 1'b1; frame3.error[26] = 1'b0;
frame3.data[27] = 8'h00; frame3.valid[27] = 1'b1; frame3.error[27] = 1'b0;
frame3.data[28] = 8'h00; frame3.valid[28] = 1'b1; frame3.error[28] = 1'b0;
frame3.data[29] = 8'h00; frame3.valid[29] = 1'b1; frame3.error[29] = 1'b0;
frame3.data[30] = 8'h00; frame3.valid[30] = 1'b1; frame3.error[30] = 1'b0;
frame3.data[31] = 8'h00; frame3.valid[31] = 1'b1; frame3.error[31] = 1'b0;
frame3.data[32] = 8'h00; frame3.valid[32] = 1'b1; frame3.error[32] = 1'b0;
frame3.data[33] = 8'h00; frame3.valid[33] = 1'b1; frame3.error[33] = 1'b0;
frame3.data[34] = 8'h00; frame3.valid[34] = 1'b1; frame3.error[34] = 1'b0;
frame3.data[35] = 8'h00; frame3.valid[35] = 1'b1; frame3.error[35] = 1'b0;
frame3.data[36] = 8'h00; frame3.valid[36] = 1'b1; frame3.error[36] = 1'b0;
frame3.data[37] = 8'h00; frame3.valid[37] = 1'b1; frame3.error[37] = 1'b0;
frame3.data[38] = 8'h00; frame3.valid[38] = 1'b1; frame3.error[38] = 1'b0;
frame3.data[39] = 8'h00; frame3.valid[39] = 1'b1; frame3.error[39] = 1'b0;
frame3.data[40] = 8'h00; frame3.valid[40] = 1'b1; frame3.error[40] = 1'b0;
frame3.data[41] = 8'h00; frame3.valid[41] = 1'b1; frame3.error[41] = 1'b0;
frame3.data[42] = 8'h00; frame3.valid[42] = 1'b1; frame3.error[42] = 1'b0;
frame3.data[43] = 8'h00; frame3.valid[43] = 1'b1; frame3.error[43] = 1'b0;
frame3.data[44] = 8'h00; frame3.valid[44] = 1'b1; frame3.error[44] = 1'b0;
frame3.data[45] = 8'h00; frame3.valid[45] = 1'b1; frame3.error[45] = 1'b0;
frame3.data[46] = 8'h00; frame3.valid[46] = 1'b1; frame3.error[46] = 1'b0;
frame3.data[47] = 8'h00; frame3.valid[47] = 1'b1; frame3.error[47] = 1'b0;
frame3.data[48] = 8'h00; frame3.valid[48] = 1'b1; frame3.error[48] = 1'b0;
frame3.data[49] = 8'h00; frame3.valid[49] = 1'b1; frame3.error[49] = 1'b0;
frame3.data[50] = 8'h00; frame3.valid[50] = 1'b1; frame3.error[50] = 1'b0;
frame3.data[51] = 8'h00; frame3.valid[51] = 1'b1; frame3.error[51] = 1'b0;
frame3.data[52] = 8'h00; frame3.valid[52] = 1'b1; frame3.error[52] = 1'b0;
frame3.data[53] = 8'h00; frame3.valid[53] = 1'b1; frame3.error[53] = 1'b0;
frame3.data[54] = 8'h00; frame3.valid[54] = 1'b1; frame3.error[54] = 1'b0;
frame3.data[55] = 8'h00; frame3.valid[55] = 1'b1; frame3.error[55] = 1'b0;
frame3.data[56] = 8'h00; frame3.valid[56] = 1'b1; frame3.error[56] = 1'b0;
frame3.data[57] = 8'h00; frame3.valid[57] = 1'b1; frame3.error[57] = 1'b0;
frame3.data[58] = 8'h00; frame3.valid[58] = 1'b1; frame3.error[58] = 1'b0;
frame3.data[59] = 8'h00; frame3.valid[59] = 1'b1; frame3.error[59] = 1'b0;
// unused
frame3.data[60] = 8'h00; frame3.valid[60] = 1'b0; frame3.error[60] = 1'b0;
frame3.data[61] = 8'h00; frame3.valid[61] = 1'b0; frame3.error[61] = 1'b0;
// No error in this frame
frame3.bad_frame = 1'b0;
end
//--------------------------------------------------------------------
// CRC engine
//--------------------------------------------------------------------
task calc_crc;
input [7:0] data;
inout [31:0] fcs;
reg [31:0] crc;
reg crc_feedback;
integer I;
begin
crc = ~ fcs;
for (I = 0; I < 8; I = I + 1)
begin
crc_feedback = crc[0] ^ data[I];
crc[0] = crc[1];
crc[1] = crc[2];
crc[2] = crc[3];
crc[3] = crc[4];
crc[4] = crc[5];
crc[5] = crc[6] ^ crc_feedback;
crc[6] = crc[7];
crc[7] = crc[8];
crc[8] = crc[9] ^ crc_feedback;
crc[9] = crc[10] ^ crc_feedback;
crc[10] = crc[11];
crc[11] = crc[12];
crc[12] = crc[13];
crc[13] = crc[14];
crc[14] = crc[15];
crc[15] = crc[16] ^ crc_feedback;
crc[16] = crc[17];
crc[17] = crc[18];
crc[18] = crc[19];
crc[19] = crc[20] ^ crc_feedback;
crc[20] = crc[21] ^ crc_feedback;
crc[21] = crc[22] ^ crc_feedback;
crc[22] = crc[23];
crc[23] = crc[24] ^ crc_feedback;
crc[24] = crc[25] ^ crc_feedback;
crc[25] = crc[26];
crc[26] = crc[27] ^ crc_feedback;
crc[27] = crc[28] ^ crc_feedback;
crc[28] = crc[29];
crc[29] = crc[30] ^ crc_feedback;
crc[30] = crc[31] ^ crc_feedback;
crc[31] = crc_feedback;
end
// return the CRC result
fcs = ~ crc;
end
endtask // calc_crc
//----------------------------------------------------------------------------
// Test Bench signals and constants
//----------------------------------------------------------------------------
// Delay to provide setup and hold timing at the GMII/RGMII.
parameter dly = 4800; // relaxed timing from requirement of 6ns
parameter gtx_period = 2500; // ps
// testbench signals
reg gtx_clk;
reg reset;
wire mdc;
wire mdio;
reg [5:0] mdio_count;
reg last_mdio;
reg mdio_read;
reg mdio_addr;
reg mdio_fail;
wire gmii_tx_clk;
wire gmii_tx_en;
wire gmii_tx_er;
wire [7:0] gmii_txd;
wire gmii_rx_clk;
reg gmii_rx_dv;
reg gmii_rx_er;
reg [7:0] gmii_rxd;
wire gmii_col;
wire gmii_crs;
// testbench control semaphores
reg tx_monitor_finished_1G;
reg management_config_finished;
reg [1:0] mac_speed;
reg update_speed;
wire test_half_duplex;
// if set the axi_lite_sm must be set also
// Demo tb only supports this at 10Mb/s or 100Mb/s
assign test_half_duplex = 1'b0;
wire [7:0] gmii_rxd_dut;
wire gmii_rx_dv_dut;
wire gmii_rx_er_dut;
reg gen_tx_data;
reg check_tx_data;
reg config_bist;
wire frame_error;
reg error_seen;
wire serial_response;
// select between loopback or local data
assign gmii_rxd_dut = (TB_MODE == "BIST") ? gmii_txd : gmii_rxd;
assign gmii_rx_dv_dut = (TB_MODE == "BIST") ? gmii_tx_en : gmii_rx_dv;
assign gmii_rx_er_dut = (TB_MODE == "BIST") ? gmii_tx_er : gmii_rx_er;
//----------------------------------------------------------------------------
// Wire up Device Under Test
//----------------------------------------------------------------------------
tri_mode_eth_mac_v5_2_example_design dut
(
// asynchronous reset
.glbl_rst (reset),
// 200MHz clock input from board
.clk_in_p (gtx_clk),
.clk_in_n (!gtx_clk),
.phy_resetn (),
// GMII Interface
//---------------
.gmii_txd (gmii_txd),
.gmii_tx_en (gmii_tx_en),
.gmii_tx_er (gmii_tx_er),
.gmii_tx_clk (gmii_tx_clk),
.gmii_rxd (gmii_rxd_dut),
.gmii_rx_dv (gmii_rx_dv_dut),
.gmii_rx_er (gmii_rx_er_dut),
.gmii_rx_clk (gmii_rx_clk),
.gmii_col (gmii_crs),
.gmii_crs (gmii_col),
// MDIO Interface
//---------------
.mdio (mdio),
.mdc (mdc),
// Serialised statistics vectors
//------------------------------
.tx_statistics_s (),
.rx_statistics_s (),
// Serialised Pause interface controls
//------------------------------------
.pause_req_s (1'b0),
// Main example design controls
//-----------------------------
.mac_speed (mac_speed),
.update_speed (update_speed),
.config_board (config_bist),
.serial_response (serial_response),
.gen_tx_data (gen_tx_data),
.chk_tx_data (check_tx_data),
.reset_error (1'b0),
.frame_error (frame_error),
.frame_errorn (),
.activity_flash (),
.activity_flashn ()
);
//---------------------------------------------------------------------------
//-- If the simulation is still going then
//-- something has gone wrong
//---------------------------------------------------------------------------
initial
begin
if (TB_MODE == "BIST")
#600000000;
else
#100000000;
$display("** ERROR: Simulation Running Forever");
$stop;
end
//----------------------------------------------------------------------------
// Simulate the MDIO -
// respond with sensible data to mdio reads and accept writes
//----------------------------------------------------------------------------
// expect mdio to try and read from reg addr 1 - return all 1's if we don't
// want any other mdio accesses
// if any other response then mdio will write to reg_addr 9 then 4 then 0
// (may check for expected write data?)
// finally mdio read from reg addr 1 until bit 5 is seen high
// NOTE - do not check any other bits so could drive all high again..
// count through the mdio transfer
always @(posedge mdc or posedge reset)
begin
if (reset) begin
mdio_count <= 0;
last_mdio <= 1'b0;
end
else begin
last_mdio <= mdio;
if (mdio_count >= 32) begin
mdio_count <= 0;
end
else if (mdio_count != 0) begin
mdio_count <= mdio_count + 1;
end
else begin // only get here if mdio state is 0 - now look for a start
if ((mdio === 1'b1) && (last_mdio === 1'b0))
mdio_count <= 1;
end
end
end
assign mdio = (mdio_read & (mdio_count >= 14) & (mdio_count <= 31)) ? 1'b1 : 1'bz;
// only respond to phy addr 7 and reg address == 1 (PHY_STATUS)
always @(posedge mdc or posedge reset)
begin
if (reset) begin
mdio_read <= 1'b0;
mdio_addr <= 1'b1; // this will go low if the address doesn't match required
mdio_fail <= 1'b0;
end
else
begin
if (mdio_count == 2) begin
mdio_addr <= 1'b1; // new access so address needs to be revalidated
if ({last_mdio,mdio} === 2'b10)
mdio_read <= 1'b1;
else // take a write as a default as won't drive at the wrong time
mdio_read <= 1'b0;
end
else if ((mdio_count <= 12)) begin
// check address is phy addr/reg addr are correct
if (mdio_count <= 7 & mdio_count >= 5) begin
if (mdio !== 1'b1)
mdio_addr <= 1'b0;
end
else begin
if (mdio !== 1'b0)
mdio_addr <= 1'b0;
end
end
else if ((mdio_count == 14)) begin
if (!mdio_read & (mdio | !last_mdio)) begin
$display("FAIL : Write TA phase is incorrect at %t ps", $time);
end
end
else if ((mdio_count >= 15) & (mdio_count <= 30) & mdio_addr) begin
if (!mdio_read) begin
if (mdio_count == 20) begin
if (mdio) begin
mdio_fail <= 1;
$display("FAIL : Expected bit 10 of mdio write data to be 0 at %t ps", $time);
end
end
else begin
if (!mdio) begin
mdio_fail <= 1;
$display("FAIL : Expected all except bit 10 of mdio write data to be 1 at %t ps", $time);
end
end
end
end
end
end
//----------------------------------------------------------------------------
// Clock drivers
//----------------------------------------------------------------------------
// drives gtx_clk at 125 MHz
initial
begin
gtx_clk <= 1'b0;
#80000;
forever
begin
gtx_clk <= 1'b0;
#gtx_period;
gtx_clk <= 1'b1;
#gtx_period;
end
end
// Receiver and transmitter clocks are the same in this simulation
assign gmii_rx_clk = gmii_tx_clk;
//----------------------------------------------------------------------------
// A Task to reset the MAC
//----------------------------------------------------------------------------
task mac_reset;
begin
$display("** Note: Resetting core...");
reset <= 1'b1;
#400000
reset <= 1'b0;
$display("** Note: Timing checks are valid");
end
endtask // mac_reset;
// monitor frame error and output error when asserted (with timestamp)
always @(posedge gtx_clk or posedge reset)
begin
if (reset) begin
error_seen <= 0;
end
else if (frame_error & !error_seen) begin
error_seen <= 1;
$display("ERROR: frame mismatch at time %t ps", $time);
end
end
//----------------------------------------------------------------------------
// Management process. This process waits for setup to complete by monitoring the mdio
// (the host always runs at gtx_clk so the setup after mdio accesses are complete
// doesn't take long) and then allows packets to be sent
//----------------------------------------------------------------------------
initial
begin : p_management
mac_speed <= 2'b10;
update_speed <= 1'b0;
gen_tx_data <= 1'b0;
check_tx_data <= 1'b0;
config_bist <= 0;
// reset the core
mac_reset;
// check mdio
// wait for the mdio access and remainder of setup accesses (internal)
wait (mdio_count == 32);
wait (mdio_count == 0);
if (TB_MODE == "BIST") begin
gen_tx_data <= 1'b1;
check_tx_data <= 1'b1;
// run for a set time and then stop
repeat (15000) @(posedge gtx_clk);
// Our work here is done
if (frame_error)
$display("ERROR: Frame mismatch seen");
else if (serial_response)
$display("ERROR: AXI4 Lite state Machine error. Incorrect or non-existant PTP frame.");
else
$display("** failure: Simulation Stopped");
$stop;
end
else begin
// Signal that configuration is complete. Other processes will now
// be allowed to run.
management_config_finished = 1;
// The stimulus process will now send 4 frames at 1Gb/s.
//------------------------------------------------------------------
// Wait for 1G monitor process to complete.
wait (tx_monitor_finished_1G == 1);
management_config_finished = 0;
// Our work here is done
$display("** failure: Simulation Stopped");
$stop;
end
end // p_management
//----------------------------------------------------------------------------
// Create the GMII Half Duplex signals to simulate an attached PHY device
//----------------------------------------------------------------------------
assign gmii_col = (gmii_tx_en | gmii_tx_er) & (gmii_rx_dv | gmii_rx_er);
assign gmii_crs = (gmii_tx_en | gmii_tx_er) | (gmii_rx_dv | gmii_rx_er);
//----------------------------------------------------------------------------
// Procedure to inject a frame into the receiver at 1Gb/s
//----------------------------------------------------------------------------
task send_frame_1g;
input `FRAME_TYP frame;
integer column_index;
integer I;
reg [31:0] fcs;
begin
// import the frame into scratch space
rx_stimulus_working_frame.frombits(frame);
column_index = 0;
// Reset the FCS calculation
fcs = 32'b0;
@(posedge gmii_rx_clk);
// Adding the preamble field
for (I = 0; I < 7; I = I + 1)
begin
#dly;
gmii_rxd <= 8'h55;
gmii_rx_dv <= 1'b1;
@(posedge gmii_rx_clk);
end
// Adding the Start of Frame Delimiter (SFD)
#dly;
gmii_rxd <= 8'hD5;
gmii_rx_dv <= 1'b1;
@(posedge gmii_rx_clk);
// loop over columns in frame.
while (rx_stimulus_working_frame.valid[column_index] !== 1'b0)
begin
// send one column of data
#dly;
gmii_rxd <= rx_stimulus_working_frame.data[column_index];
gmii_rx_dv <= rx_stimulus_working_frame.valid[column_index];
gmii_rx_er <= rx_stimulus_working_frame.error[column_index];
calc_crc(rx_stimulus_working_frame.data[column_index], fcs);
column_index = column_index + 1;
@(posedge gmii_rx_clk);
end
// Send the CRC.
for (I = 0; I < 4; I = I + 1)
begin
#dly;
case(I)
0 : gmii_rxd <= fcs[7:0];
1 : gmii_rxd <= fcs[15:8];
2 : gmii_rxd <= fcs[23:16];
3 : gmii_rxd <= fcs[31:24];
endcase
gmii_rx_dv <= 1'b1;
gmii_rx_er <= 1'b0;
@(posedge gmii_rx_clk);
end
// Clear the data lines.
#dly;
gmii_rxd <= 8'h0;
gmii_rx_dv <= 1'b0;
// Adding the minimum Interframe gap for a receiver (8 idles)
for (I = 0; I < 9; I = I + 1)
@(posedge gmii_rx_clk);
end
endtask // send_frame_1g;
//----------------------------------------------------------------------------
// Stimulus process. This process will inject frames of data into the
// PHY side of the receiver.
//----------------------------------------------------------------------------
initial
begin : p_rx_stimulus
// Initialise stimulus
gmii_rxd = 8'h0;
gmii_rx_dv = 1'b0;
gmii_rx_er = 1'b0;
// Send four frames through the MAC and Design Exampled
// at each state Ethernet speed
// -- frame 0 = standard frame
// -- frame 1 = type frame
// -- frame 2 = frame containing an error
// -- frame 3 = standard frame with padding
//-----------------------------------------------------
// 1 Gb/s speed
//-----------------------------------------------------
// Wait for the Management MDIO transaction to finish.
while (management_config_finished !== 1)
// wait for the internal resets to settle before staring to send traffic
#800000;
$display("Rx Stimulus: sending 4 frames at 1G ... ");
send_frame_1g(frame0.tobits(0));
send_frame_1g(frame1.tobits(1));
send_frame_1g(frame2.tobits(2));
send_frame_1g(frame3.tobits(3));
wait (tx_monitor_finished_1G == 1);
#10000;
end // p_rx_stimulus
//----------------------------------------------------------------------------
// A Task to check a transmitted frame at 1Gb/s
//----------------------------------------------------------------------------
task check_frame_1g;
input `FRAME_TYP frame;
integer column_index;
integer I;
reg [8*4:0] string;
reg [31:0] fcs;
begin
// import the frame into scratch space
tx_monitor_working_frame.frombits(frame);
column_index = 0;
// If the current frame had an error inserted then it would have
// been dropped by the FIFO in the design example. Therefore
// exit this task and move immediately on to the next frame.
if (tx_monitor_working_frame.bad_frame !== 1'b1)
begin
// Reset the fcs calculation
fcs = 32'b0;
// wait until the first real column of data to come out of RX client
while (gmii_tx_en !== 1'b1)
@(posedge gmii_tx_clk);
// Parse over the preamble field
while (gmii_txd === 8'h55)
@(posedge gmii_tx_clk);
// Parse over the SFD
@(posedge gmii_tx_clk);
if (TB_MODE == "DEMO") begin
// Start comparing transmitted data to received data
$display("** Note: Comparing Transmitted Frame with Injected Frame");
// frame has started, loop over columns of frame
while (tx_monitor_working_frame.valid[column_index] !== 1'b0)
begin
// The transmitted Destination Address was the Source Address
// of the injected frame
if (column_index < 6)
begin
if (gmii_tx_en !== tx_monitor_working_frame.valid[column_index+6])
$display("** ERROR: gmii_tx_en incorrect during Destination Address at %t", $realtime, "ps");
if (gmii_txd !== tx_monitor_working_frame.data[(column_index+6)])
$display("** ERROR: gmii_txd incorrect during Destination Address at %t", $realtime, "ps");
end
// The transmitted Source Address was the Destination Address
// of the injected frame
else if (column_index < 12)
begin
if (gmii_tx_en !== tx_monitor_working_frame.valid[column_index-6])
$display("** ERROR: gmii_tx_en incorrect during Source Address at %t", $realtime, "ps");
if (gmii_txd !== tx_monitor_working_frame.data[(column_index-6)])
$display("** ERROR: gmii_txd incorrect during Source Address at %t", $realtime, "ps");
end
// check all other data in the frame
else
begin
if (gmii_tx_en !== tx_monitor_working_frame.valid[column_index])
$display("** ERROR: gmii_tx_en incorrect at %t", $realtime, "ps");
if (gmii_txd !== tx_monitor_working_frame.data[column_index])
$display("** ERROR: gmii_txd incorrect at %t", $realtime, "ps");
end
// calculate expected crc for the frame
calc_crc(gmii_txd, fcs);
// wait for next column of data
column_index = column_index + 1;
@(posedge gmii_tx_clk);
end
// Check the FCS
// Having checked all data columns, txd must contain FCS.
for (I = 0; I < 4; I = I + 1)
begin
if (gmii_tx_en !== 1'b1)
$display("** ERROR: gmii_tx_en incorrect during FCS field at %t", $realtime, "ps");
case(I)
0 : if (gmii_txd !== fcs[7:0])
$display("** ERROR: gmii_txd incorrect during FCS field at %t", $realtime, "ps");
1 : if (gmii_txd !== fcs[15:8])
$display("** ERROR: gmii_txd incorrect during FCS field at %t", $realtime, "ps");
2 : if (gmii_txd !== fcs[23:16])
$display("** ERROR: gmii_txd incorrect during FCS field at %t", $realtime, "ps");
3 : if (gmii_txd !== fcs[31:24])
$display("** ERROR: gmii_txd incorrect during FCS field at %t", $realtime, "ps");
endcase
@(posedge gmii_tx_clk);
end
end
else begin
// this is the BIST tb mode - want to idnetify the frame type - VLAN or not to help with the bandwidth calc
// check the type field and if equal to 81 then classify as vlan (could do more but that should be adequate)
string = "";
while (gmii_tx_en) begin
if (column_index == 12 & gmii_txd == 8'h81) begin
string = "VLAN";
end
// wait for next column of data
column_index = column_index + 1;
@(posedge gmii_tx_clk);
end
end
end
end
endtask // check_frame_1g
//----------------------------------------------------------------------------
// Monitor process. This process checks the data coming out of the
// transmitter to make sure that it matches that inserted into the
// receiver.
//----------------------------------------------------------------------------
initial
begin : p_tx_monitor
tx_monitor_finished_1G <= 0;
if (TB_MODE == "DEMO") begin
// Compare the transmitted frame to the received frames
// -- frame 0 = minimum length frame
// -- frame 1 = type frame
// -- frame 2 = errored frame
// -- frame 3 = padded frame
// Repeated for all stated speeds.
//-----------------------------------------------------
// wait for the reset to complete before starting monitor
@(negedge reset);
// 1 Gb/s speed
//-----------------------------------------------------
// Check the frames
check_frame_1g(frame0.tobits(0));
check_frame_1g(frame1.tobits(0));
check_frame_1g(frame2.tobits(0));
check_frame_1g(frame3.tobits(0));
#200000
tx_monitor_finished_1G <= 1;
end
else begin
forever check_frame_1g(frame0.tobits(0));
end
end // p_tx_monitor
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
`define SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
/**
* udp_isolatchhv_pp$PLG$S: Power isolating latch (for HV). Includes
* VPWR, LVPWR, and VGND power pins with
* active high sleep pin (SLEEP).
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_isolatchhv_pp$PLG$S (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input SLEEP ,
input LVPWR ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_ISOLATCHHV_PP_PLG_S_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V
/**
* macro_sparecell: Macro cell for metal-mask-only revisioning,
* containing inverter, 2-input NOR, 2-input NAND,
* and constant cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../conb/sky130_fd_sc_hd__conb.v"
`include "../nor2/sky130_fd_sc_hd__nor2.v"
`include "../inv/sky130_fd_sc_hd__inv.v"
`include "../nand2/sky130_fd_sc_hd__nand2.v"
`celldefine
module sky130_fd_sc_hd__macro_sparecell (
LO ,
VGND,
VNB ,
VPB ,
VPWR
);
// Module ports
output LO ;
input VGND;
input VNB ;
input VPB ;
input VPWR;
// Local signals
wire nor2left ;
wire invleft ;
wire nor2right;
wire invright ;
wire nd2left ;
wire nd2right ;
wire tielo ;
wire net7 ;
// Name Output Other arguments
sky130_fd_sc_hd__inv_2 inv0 (.A(nor2left) , .Y(invleft), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__inv_2 inv1 (.A(nor2right), .Y(invright), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__nor2_2 nor20 (.B(nd2left) , .A(nd2left), .Y(nor2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__nor2_2 nor21 (.B(nd2right) , .A(nd2right), .Y(nor2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB));
sky130_fd_sc_hd__nand2_2 nand20 (.B(tielo) , .A(tielo), .Y(nd2right), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__nand2_2 nand21 (.B(tielo) , .A(tielo), .Y(nd2left), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
sky130_fd_sc_hd__conb_1 conb0 (.LO(tielo) , .HI(net7), .VPWR(VPWR), .VGND(VGND), .VNB(VNB), .VPB(VPB) );
buf buf0 (LO , tielo );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_BEHAVIORAL_PP_V |
module core161c(
input wire clk,
input wire reset,
input wire power,
input wire sw_single_step,
input wire sw_restart,
input wire membus_wr_rs_p0,
input wire membus_rq_cyc_p0,
input wire membus_rd_rq_p0,
input wire membus_wr_rq_p0,
input wire [21:35] membus_ma_p0,
input wire [18:21] membus_sel_p0,
input wire membus_fmc_select_p0,
input wire [0:35] membus_mb_in_p0,
output wire membus_addr_ack_p0,
output wire membus_rd_rs_p0,
output wire [0:35] membus_mb_out_p0,
input wire membus_wr_rs_p1,
input wire membus_rq_cyc_p1,
input wire membus_rd_rq_p1,
input wire membus_wr_rq_p1,
input wire [21:35] membus_ma_p1,
input wire [18:21] membus_sel_p1,
input wire membus_fmc_select_p1,
input wire [0:35] membus_mb_in_p1,
output wire membus_addr_ack_p1,
output wire membus_rd_rs_p1,
output wire [0:35] membus_mb_out_p1,
input wire membus_wr_rs_p2,
input wire membus_rq_cyc_p2,
input wire membus_rd_rq_p2,
input wire membus_wr_rq_p2,
input wire [21:35] membus_ma_p2,
input wire [18:21] membus_sel_p2,
input wire membus_fmc_select_p2,
input wire [0:35] membus_mb_in_p2,
output wire membus_addr_ack_p2,
output wire membus_rd_rs_p2,
output wire [0:35] membus_mb_out_p2,
input wire membus_wr_rs_p3,
input wire membus_rq_cyc_p3,
input wire membus_rd_rq_p3,
input wire membus_wr_rq_p3,
input wire [21:35] membus_ma_p3,
input wire [18:21] membus_sel_p3,
input wire membus_fmc_select_p3,
input wire [0:35] membus_mb_in_p3,
output wire membus_addr_ack_p3,
output wire membus_rd_rs_p3,
output wire [0:35] membus_mb_out_p3
);
/* Jumpers */
parameter memsel_p0 = 4'b0;
parameter memsel_p1 = 4'b0;
parameter memsel_p2 = 4'b0;
parameter memsel_p3 = 4'b0;
reg [22:35] cma;
reg cma_rd_rq;
reg cma_wr_rq;
reg [0:35] cmb;
reg cmc_p0_act, cmc_p1_act, cmc_p2_act, cmc_p3_act;
reg cmc_last_proc;
reg cmc_rd;
reg cmc_inhibit; // not really used
reg cmc_wr;
reg cmc_await_rq = 0;
reg cmc_proc_rs = 0;
reg cmc_pse_sync;
reg cmc_stop;
wire cyc_rq_p0 = memsel_p0 == membus_sel_p0 &
~membus_fmc_select_p0 & membus_rq_cyc_p0;
wire cyc_rq_p1 = memsel_p1 == membus_sel_p1 &
~membus_fmc_select_p1 & membus_rq_cyc_p1;
wire cyc_rq_p2 = memsel_p2 == membus_sel_p2 &
~membus_fmc_select_p2 & membus_rq_cyc_p2;
wire cyc_rq_p3 = memsel_p3 == membus_sel_p3 &
~membus_fmc_select_p3 & membus_rq_cyc_p3;
wire cmpc_p0_rq = cyc_rq_p0 & cmc_await_rq;
wire cmpc_p1_rq = cyc_rq_p1 & cmc_await_rq;
wire cmpc_p2_rq = cyc_rq_p2 & cmc_await_rq;
wire cmpc_p3_rq = cyc_rq_p3 & cmc_await_rq;
wire wr_rs = cmc_p0_act ? membus_wr_rs_p0 :
cmc_p1_act ? membus_wr_rs_p1 :
cmc_p2_act ? membus_wr_rs_p2 :
cmc_p3_act ? membus_wr_rs_p3 : 1'b0;
wire rd_rq = cmc_p0_act ? membus_rd_rq_p0 :
cmc_p1_act ? membus_rd_rq_p1 :
cmc_p2_act ? membus_rd_rq_p2 :
cmc_p3_act ? membus_rd_rq_p3 : 1'b0;
wire wr_rq = cmc_p0_act ? membus_wr_rq_p0 :
cmc_p1_act ? membus_wr_rq_p1 :
cmc_p2_act ? membus_wr_rq_p2 :
cmc_p3_act ? membus_wr_rq_p3 : 1'b0;
wire [21:35] ma = cmc_p0_act ? membus_ma_p0 :
cmc_p1_act ? membus_ma_p1 :
cmc_p2_act ? membus_ma_p2 :
cmc_p3_act ? membus_ma_p3 : 15'b0;
wire [0:35] mb_in = cmc_p0_act ? membus_mb_in_p0 :
cmc_p1_act ? membus_mb_in_p1 :
cmc_p2_act ? membus_mb_in_p2 :
cmc_p3_act ? membus_mb_in_p3 : 36'b0;
assign membus_addr_ack_p0 = cmc_addr_ack & cmc_p0_act;
assign membus_rd_rs_p0 = cmc_rd_rs & cmc_p0_act;
assign membus_mb_out_p0 = cmc_p0_act ? mb_out : 36'b0;
assign membus_addr_ack_p1 = cmc_addr_ack & cmc_p1_act;
assign membus_rd_rs_p1 = cmc_rd_rs & cmc_p1_act;
assign membus_mb_out_p1 = cmc_p1_act ? mb_out : 36'b0;
assign membus_addr_ack_p2 = cmc_addr_ack & cmc_p2_act;
assign membus_rd_rs_p2 = cmc_rd_rs & cmc_p2_act;
assign membus_mb_out_p2 = cmc_p2_act ? mb_out : 36'b0;
assign membus_addr_ack_p3 = cmc_addr_ack & cmc_p3_act;
assign membus_rd_rs_p3 = cmc_rd_rs & cmc_p3_act;
assign membus_mb_out_p3 = cmc_p3_act ? mb_out : 36'b0;
wire cmc_addr_ack;
wire cmc_rd_rs;
wire [0:35] mb_out = mb_pulse_out ? sa : 36'b0;
wire cmpc_rs_strb;
wire cmc_pwr_clr;
wire cmc_pwr_start;
wire cmc_key_restart;
wire cmc_state_clr;
wire cmc_cmb_clr;
wire cmc_strb_sa;
wire cmc_proc_rs_P;
wire mb_pulse_out;
wire cmc_wr_rs;
wire cmc_t0;
wire cmc_t1;
wire cmc_t2;
wire cmc_t4;
wire cmc_t5;
wire cmc_t6;
wire cmc_t7;
wire cmc_t8;
wire cmc_t9;
wire cmc_t9a;
wire cmc_t10;
wire cmc_t11;
wire cmc_t12;
// power-on timing is totally wrong
pg cmc_pg0(.clk(clk), .reset(reset), .in(power), .p(cmc_pwr_clr));
pg cmc_pg1(.clk(clk), .reset(reset),
.in(sw_restart & cmc_stop), .p(cmc_key_restart));
pg cmc_pg2(.clk(clk), .reset(reset),
.in(cmpc_p0_rq | cmpc_p1_rq | cmpc_p2_rq | cmpc_p3_rq),
.p(cmc_t0));
pg cmc_pg4(.clk(clk), .reset(reset), .in(wr_rs), .p(cmpc_rs_strb));
pg cmc_pg5(.clk(clk), .reset(reset), .in(cmc_proc_rs), .p(cmc_proc_rs_P));
pg cmc_pg6(.clk(clk), .reset(reset), .in(cmc_pse_sync & cmc_proc_rs), .p(cmc_wr_rs));
pa cmc_pa0(.clk(clk), .reset(reset), .in(cmc_pwr_clr | cmc_t9a_D), .p(cmc_t12));
pa cmc_pa1(.clk(clk), .reset(reset), .in(cmc_pwr_clr_D), .p(cmc_pwr_start));
pa cmc_pa2(.clk(clk), .reset(reset),
.in(cmc_t9a & ~cmc_stop | cmc_pwr_start | cmc_key_restart),
.p(cmc_t10));
pa cmc_pa3(.clk(clk), .reset(reset), .in(cmc_t10_D), .p(cmc_t11));
pa cmc_pa4(.clk(clk), .reset(reset),
.in(cmc_t10 | ~cma_wr_rq & cmc_strb_sa_D1 | cmc_proc_rs_P),
.p(cmc_state_clr));
pa cmc_pa5(.clk(clk), .reset(reset),
.in(cmc_t0 | cmc_strb_sa_D2 & cma_wr_rq),
.p(cmc_cmb_clr));
pa cmc_pa6(.clk(clk), .reset(reset), .in(cmc_t0_D), .p(cmc_t1));
pa cmc_pa7(.clk(clk), .reset(reset), .in(cmc_t1_D), .p(cmc_t2));
pa cmc_pa8(.clk(clk), .reset(reset), .in(cmc_t2_D0), .p(cmc_t4));
pa cmc_pa9(.clk(clk), .reset(reset), .in(cmc_t4_D), .p(cmc_t5));
pa cmc_pa10(.clk(clk), .reset(reset),
.in(cmc_t5 & ~cma_wr_rq | cmc_wr_rs),
.p(cmc_t6));
pa cmc_pa11(.clk(clk), .reset(reset), .in(cmc_t6_D), .p(cmc_t7));
pa cmc_pa12(.clk(clk), .reset(reset), .in(cmc_t7_D), .p(cmc_t8));
pa cmc_pa13(.clk(clk), .reset(reset), .in(cmc_t8_D), .p(cmc_t9));
pa cmc_pa14(.clk(clk), .reset(reset), .in(cmc_t9_D), .p(cmc_t9a));
pa cmc_pa15(.clk(clk), .reset(reset),
.in(cmc_t2_D1 & cma_rd_rq),
.p(cmc_strb_sa));
// not on schematics
bd cmc_bd0(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_addr_ack));
bd cmc_bd1(.clk(clk), .reset(reset), .in(cmc_strb_sa_D0), .p(cmc_rd_rs));
bd cmc_bd2(.clk(clk), .reset(reset), .in(cmc_strb_sa), .p(mb_pulse_out));
wire cmc_pwr_clr_D;
wire cmc_t0_D, cmc_t1_D, cmc_t2_D0, cmc_t2_D1, cmc_t4_D;
wire cmc_t6_D, cmc_t7_D, cmc_t8_D, cmc_t9_D, cmc_t9a_D, cmc_t10_D;
wire cmc_strb_sa_D0, cmc_strb_sa_D1, cmc_strb_sa_D2;
dly100ns cmc_dly0(.clk(clk), .reset(reset), .in(cmc_pwr_clr), .p(cmc_pwr_clr_D));
dly100ns cmc_dly1(.clk(clk), .reset(reset), .in(cmc_t10), .p(cmc_t10_D));
dly200ns cmc_dly2(.clk(clk), .reset(reset), .in(cmc_t0), .p(cmc_t0_D));
dly1us cmc_dly3(.clk(clk), .reset(reset), .in(cmc_t1), .p(cmc_t1_D));
dly1us cmc_dly4(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D0));
dly200ns cmc_dly5(.clk(clk), .reset(reset), .in(cmc_t4), .p(cmc_t4_D));
dly200ns cmc_dly6(.clk(clk), .reset(reset), .in(cmc_t6), .p(cmc_t6_D));
dly200ns cmc_dly7(.clk(clk), .reset(reset), .in(cmc_t7), .p(cmc_t7_D));
dly1us cmc_dly8(.clk(clk), .reset(reset), .in(cmc_t8), .p(cmc_t8_D));
dly400ns cmc_dly9(.clk(clk), .reset(reset), .in(cmc_t9), .p(cmc_t9_D));
dly200ns cmc_dly10(.clk(clk), .reset(reset), .in(cmc_t9a), .p(cmc_t9a_D));
dly800ns cmc_dly11(.clk(clk), .reset(reset), .in(cmc_t2), .p(cmc_t2_D1));
dly100ns cmc_dly12(.clk(clk), .reset(reset),
.in(cmc_strb_sa), .p(cmc_strb_sa_D0));
dly200ns cmc_dly13(.clk(clk), .reset(reset),
.in(cmc_strb_sa), .p(cmc_strb_sa_D1));
dly250ns cmc_dly14(.clk(clk), .reset(reset),
.in(cmc_strb_sa), .p(cmc_strb_sa_D2));
// wire [0:35] sa = core[cma]; // "sense amplifiers"
reg [0:35] sa; // "sense amplifiers"
reg [0:35] core[0:'o40000-1];
wire [13:0] core_addr = cma[22:35];
reg core_rd, core_wr;
always @(posedge clk or posedge reset) begin
if(reset) begin
cmc_await_rq <= 0;
cmc_last_proc <= 0;
cmc_proc_rs <= 0;
core_rd <= 0;
core_wr <= 0;
sa <= 0;
end else begin
if(core_rd) begin
sa <= core[core_addr];
core_rd <= 0;
end else if(core_wr) begin
core[core_addr] <= cmb;
core_wr <= 0;
end
if(cmc_state_clr) begin
cmc_p0_act <= 0;
cmc_p1_act <= 0;
cmc_p2_act <= 0;
cmc_p3_act <= 0;
end
cmb <= cmb | mb_in;
if(cmc_cmb_clr)
cmb <= 0;
if(cmc_strb_sa)
cmb <= cmb | sa;
if(cmpc_rs_strb)
cmc_proc_rs <= 1;
if(cmc_t0) begin
cmc_await_rq <= 0;
cmc_proc_rs <= 0;
cmc_pse_sync <= 0;
cmc_stop <= 0;
cma <= 0;
cma_rd_rq <= 0;
cma_wr_rq <= 0;
// this happens between t0 and t1 */
if(cmpc_p0_rq)
cmc_p0_act <= 1;
else if(cmpc_p1_rq)
cmc_p1_act <= 1;
else if(cmpc_p2_rq) begin
if(~cmpc_p3_rq | cmc_last_proc)
cmc_p2_act <= 1;
end else if(cmpc_p3_rq) begin
if(~cmpc_p2_rq | ~cmc_last_proc)
cmc_p3_act <= 1;
end
end
if(cmc_t1) begin // this seems to be missing from the schematics
cma <= cma | ma[22:35];
if(rd_rq)
cma_rd_rq <= 1;
if(wr_rq)
cma_wr_rq <= 1;
end
if(cmc_t2) begin
cmc_rd <= 1;
if(cmc_p2_act)
cmc_last_proc <= 0;
if(cmc_p3_act)
cmc_last_proc <= 1;
core_rd <= 1;
sa <= 0;
/// sa <= core[cma[22:35]];
end
/// if(cmc_t4)
/// /* As a hack zero core here */
/// core[cma[22:35]] <= 0;
if(cmc_t5) begin
cmc_rd <= 0;
cmc_pse_sync <= 1;
end
if(cmc_t7) begin
cmc_inhibit <= 1;
if(sw_single_step)
cmc_stop <= 1;
end
if(cmc_t8) begin
cmc_wr <= 1;
end
if(cmc_t9 & cmc_wr)
/* again a hack. core is written some time after t8.
* (cmc_wr is always set here) */
// core[cma[22:35]] <= core[cma[22:35]] | cmb;
/// core[cma[22:35]] <= cmb;
core_wr <= 1;
if(cmc_t11)
cmc_await_rq <= 1;
if(cmc_t12) begin
cmc_rd <= 0;
cmc_inhibit <= 0;
cmc_wr <= 0;
end
end
end
endmodule
|
// ======================================================================
// PWM_MUX.v generated from TopDesign.cysch
// 03/09/2015 at 14:50
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PSOC5LP 3
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_PANTHER 4
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4D 2
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 3
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 4
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 6
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 3
`define CYDEV_CHIP_REVISION_USED 17
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// TCPWM_P4_v2_0(Clock_CheckTolerance=true, Clock_desired_freq=12, Clock_desired_freq_unit=6, Clock_divisor=1, Clock_FractDividerDenominator=0, Clock_FractDividerNumerator=0, Clock_FractDividerUsed=false, Clock_is_direct=false, Clock_is_divider=false, Clock_is_freq=true, Clock_minus_tolerance=5, Clock_ph_align_clock_id=, Clock_ph_align_clock_name=, Clock_plus_tolerance=5, Clock_source_clock_id=, Clock_source_clock_name=, PinVisibility_index=false, PinVisibility_kill=false, PinVisibility_phiA=false, PinVisibility_phiB=false, PinVisibility_switch=false, PWMCompare=65535, PWMCompareBuf=65535, PWMCompareSwap=0, PWMCountMode=3, PWMCountPresent=false, PWMDeadTimeCycle=0, PWMInterruptMask=1, PWMKillEvent=0, PWMLinenSignal=0, PWMLineSignal=0, PWMMode=4, PWMPeriod=65535, PWMPeriodBuf=65535, PWMPeriodSwap=0, PWMPrescaler=0, PWMReloadMode=0, PWMReloadPresent=false, PWMRunMode=0, PWMSetAlign=0, PWMStartMode=0, PWMStartPresent=false, PWMStopEvent=0, PWMStopMode=0, PWMStopPresent=false, PWMSwitchMode=0, PWMSwitchPresent=false, QuadEncodingModes=0, QuadIndexMode=0, QuadIndexPresent=false, QuadInterruptMask=1, QuadPhiAMode=3, QuadPhiBMode=3, QuadStopMode=0, QuadStopPresent=false, TCCaptureMode=1, TCCapturePresent=true, TCCompare=65535, TCCompareBuf=65535, TCCompareSwap=0, TCCompCapMode=2, TCCountingModes=0, TCCountMode=3, TCCountPresent=false, TCInterruptMask=2, TCPeriod=65535, TCPrescaler=0, TCPWMCapturePresent=false, TCPWMConfig=1, TCPWMCountPresent=false, TCPWMReloadPresent=false, TCPWMStartPresent=false, TCPWMStopPresent=false, TCReloadMode=0, TCReloadPresent=true, TCRunMode=0, TCStartMode=0, TCStartPresent=true, TCStopMode=1, TCStopPresent=true, TermMode_capture=0, TermMode_cc=0, TermMode_clock=0, TermMode_count=0, TermMode_interrupt=0, TermMode_line=0, TermMode_line_n=0, TermMode_ov=0, TermMode_reload=0, TermMode_start=0, TermMode_stop=0, TermMode_un=0, TermModeStates=, TermVisibility_capture=true, TermVisibility_cc=true, TermVisibility_clock=true, TermVisibility_count=false, TermVisibility_interrupt=true, TermVisibility_line=false, TermVisibility_line_n=false, TermVisibility_ov=true, TermVisibility_reload=true, TermVisibility_start=true, TermVisibility_stop=true, TermVisibility_un=true, CY_COMPONENT_NAME=TCPWM_P4_v2_0, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=Timer_1, CY_INSTANCE_SHORT_NAME=Timer_1, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.1 SP1, INSTANCE_NAME=Timer_1, )
module TCPWM_P4_v2_0_0 (
stop,
count,
reload,
start,
capture,
interrupt,
ov,
un,
cc,
clock,
line,
line_n);
input stop;
input count;
input reload;
input start;
input capture;
output interrupt;
output ov;
output un;
output cc;
input clock;
output line;
output line_n;
wire Net_64;
wire Net_63;
wire Net_85;
wire Net_62;
wire Net_110;
wire Net_95;
wire Net_106;
wire Net_104;
wire Net_109;
wire Net_98;
wire Net_108;
wire Net_101;
wire Net_66;
wire Net_81;
wire Net_75;
wire Net_69;
wire Net_82;
wire Net_72;
cy_m0s8_tcpwm_v1_0 cy_m0s8_tcpwm_1 (
.capture(Net_75),
.underflow(un),
.overflow(ov),
.line_out_compl(line_n),
.line_out(line),
.compare_match(cc),
.interrupt(interrupt),
.count(Net_69),
.reload(Net_66),
.stop(Net_82),
.start(Net_72),
.clock(Net_81));
// VMux_reload (cy_virtualmux_v1_0)
assign Net_66 = reload;
// VMux_count (cy_virtualmux_v1_0)
assign Net_69 = count;
// VMux_start (cy_virtualmux_v1_0)
assign Net_72 = start;
// VMux_capture (cy_virtualmux_v1_0)
assign Net_75 = capture;
// VMux_stop (cy_virtualmux_v1_0)
assign Net_82 = stop;
// VMux_clock (cy_virtualmux_v1_0)
assign Net_81 = clock;
endmodule
// Component: mux_v1_10
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\mux_v1_10"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\mux_v1_10\mux_v1_10.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\mux_v1_10"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.1\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\mux_v1_10\mux_v1_10.v"
`endif
// top
module top ;
wire Net_167;
wire Net_166;
wire Net_165;
wire Net_159;
wire Net_158;
wire Net_157;
wire Net_163;
wire Net_162;
wire Net_161;
wire Net_155;
wire Net_154;
wire Net_153;
wire Net_66;
wire Net_63;
wire Net_62;
wire Net_61;
wire Net_60;
wire Net_59;
wire Net_57;
wire Net_180;
wire Net_64;
wire Net_58;
wire Net_582;
TCPWM_P4_v2_0_0 Timer_1 (
.stop(Net_582),
.reload(Net_582),
.start(Net_582),
.count(1'b1),
.capture(Net_582),
.interrupt(Net_58),
.ov(Net_59),
.un(Net_60),
.cc(Net_61),
.line(Net_62),
.line_n(Net_63),
.clock(Net_64));
cy_clock_v1_0
#(.id("8f032cb4-5dbe-4262-8122-a7586d2a3513"),
.source_clock_id(""),
.divisor(0),
.period("1000000000"),
.is_direct(0),
.is_digital(0))
Clock_4
(.clock_out(Net_64));
cy_isr_v1_0
#(.int_type(2'b10))
ISR
(.int_signal(Net_58));
wire [0:0] tmpOE__INPUT_SELECT_net;
wire [0:0] tmpIO_0__INPUT_SELECT_net;
wire [0:0] tmpINTERRUPT_0__INPUT_SELECT_net;
electrical [0:0] tmpSIOVREF__INPUT_SELECT_net;
cy_psoc3_pins_v1_10
#(.id("5873dc09-554c-4efa-a7ac-417ac7427101"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
INPUT_SELECT
(.oe(tmpOE__INPUT_SELECT_net),
.y({1'b0}),
.fb({Net_180}),
.io({tmpIO_0__INPUT_SELECT_net[0:0]}),
.siovref(tmpSIOVREF__INPUT_SELECT_net),
.interrupt({tmpINTERRUPT_0__INPUT_SELECT_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__INPUT_SELECT_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// -- Mux start --
if (1)
begin : Turret_Mux_6
reg tmp__Turret_Mux_6_reg;
always @(Net_153 or Net_154 or Net_180)
begin
case (Net_180)
1'b0 : tmp__Turret_Mux_6_reg = Net_153;
1'b1 : tmp__Turret_Mux_6_reg = Net_154;
endcase
end
assign Net_155 = tmp__Turret_Mux_6_reg;
end
// -- Mux end --
// -- Mux start --
if (1)
begin : Turret_Mux_8
reg tmp__Turret_Mux_8_reg;
always @(Net_161 or Net_162 or Net_180)
begin
case (Net_180)
1'b0 : tmp__Turret_Mux_8_reg = Net_161;
1'b1 : tmp__Turret_Mux_8_reg = Net_162;
endcase
end
assign Net_163 = tmp__Turret_Mux_8_reg;
end
// -- Mux end --
// -- Mux start --
if (1)
begin : Turret_Mux_7
reg tmp__Turret_Mux_7_reg;
always @(Net_157 or Net_158 or Net_180)
begin
case (Net_180)
1'b0 : tmp__Turret_Mux_7_reg = Net_157;
1'b1 : tmp__Turret_Mux_7_reg = Net_158;
endcase
end
assign Net_159 = tmp__Turret_Mux_7_reg;
end
// -- Mux end --
wire [0:0] tmpOE__CONTROL_net;
wire [0:0] tmpIO_0__CONTROL_net;
wire [0:0] tmpINTERRUPT_0__CONTROL_net;
electrical [0:0] tmpSIOVREF__CONTROL_net;
cy_psoc3_pins_v1_10
#(.id("e1cae64b-61e6-442e-801d-76154795a3dd"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
CONTROL
(.oe(tmpOE__CONTROL_net),
.y({1'b0}),
.fb({Net_582}),
.io({tmpIO_0__CONTROL_net[0:0]}),
.siovref(tmpSIOVREF__CONTROL_net),
.interrupt({tmpINTERRUPT_0__CONTROL_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__CONTROL_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LED_net;
wire [0:0] tmpFB_0__LED_net;
wire [0:0] tmpIO_0__LED_net;
wire [0:0] tmpINTERRUPT_0__LED_net;
electrical [0:0] tmpSIOVREF__LED_net;
cy_psoc3_pins_v1_10
#(.id("ef8b41b3-8af3-4024-b8b5-125bd61badfb"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
LED
(.oe(tmpOE__LED_net),
.y({1'b0}),
.fb({tmpFB_0__LED_net[0:0]}),
.io({tmpIO_0__LED_net[0:0]}),
.siovref(tmpSIOVREF__LED_net),
.interrupt({tmpINTERRUPT_0__LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// -- Mux start --
if (1)
begin : Turret_Mux_9
reg tmp__Turret_Mux_9_reg;
always @(Net_165 or Net_166 or Net_180)
begin
case (Net_180)
1'b0 : tmp__Turret_Mux_9_reg = Net_165;
1'b1 : tmp__Turret_Mux_9_reg = Net_166;
endcase
end
assign Net_167 = tmp__Turret_Mux_9_reg;
end
// -- Mux end --
wire [0:0] tmpOE__Drive_Right_MCU_net;
wire [0:0] tmpIO_0__Drive_Right_MCU_net;
wire [0:0] tmpINTERRUPT_0__Drive_Right_MCU_net;
electrical [0:0] tmpSIOVREF__Drive_Right_MCU_net;
cy_psoc3_pins_v1_10
#(.id("340a82c6-54d6-4536-9617-8b2782e699e1"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Drive_Right_MCU
(.oe(tmpOE__Drive_Right_MCU_net),
.y({1'b0}),
.fb({Net_153}),
.io({tmpIO_0__Drive_Right_MCU_net[0:0]}),
.siovref(tmpSIOVREF__Drive_Right_MCU_net),
.interrupt({tmpINTERRUPT_0__Drive_Right_MCU_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Drive_Right_MCU_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Drive_Right_Backup_net;
wire [0:0] tmpIO_0__Drive_Right_Backup_net;
wire [0:0] tmpINTERRUPT_0__Drive_Right_Backup_net;
electrical [0:0] tmpSIOVREF__Drive_Right_Backup_net;
cy_psoc3_pins_v1_10
#(.id("350d78d7-9e11-4357-bd72-e336d1a20fd1"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Drive_Right_Backup
(.oe(tmpOE__Drive_Right_Backup_net),
.y({1'b0}),
.fb({Net_154}),
.io({tmpIO_0__Drive_Right_Backup_net[0:0]}),
.siovref(tmpSIOVREF__Drive_Right_Backup_net),
.interrupt({tmpINTERRUPT_0__Drive_Right_Backup_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Drive_Right_Backup_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Drive_Left_MCU_net;
wire [0:0] tmpIO_0__Drive_Left_MCU_net;
wire [0:0] tmpINTERRUPT_0__Drive_Left_MCU_net;
electrical [0:0] tmpSIOVREF__Drive_Left_MCU_net;
cy_psoc3_pins_v1_10
#(.id("fd1127e7-4ac2-40d0-8ca2-a43df3fca05e"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Drive_Left_MCU
(.oe(tmpOE__Drive_Left_MCU_net),
.y({1'b0}),
.fb({Net_157}),
.io({tmpIO_0__Drive_Left_MCU_net[0:0]}),
.siovref(tmpSIOVREF__Drive_Left_MCU_net),
.interrupt({tmpINTERRUPT_0__Drive_Left_MCU_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Drive_Left_MCU_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Drive_Left_Backup_net;
wire [0:0] tmpIO_0__Drive_Left_Backup_net;
wire [0:0] tmpINTERRUPT_0__Drive_Left_Backup_net;
electrical [0:0] tmpSIOVREF__Drive_Left_Backup_net;
cy_psoc3_pins_v1_10
#(.id("c37f1b90-4819-49af-955b-bf542e88b728"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Drive_Left_Backup
(.oe(tmpOE__Drive_Left_Backup_net),
.y({1'b0}),
.fb({Net_158}),
.io({tmpIO_0__Drive_Left_Backup_net[0:0]}),
.siovref(tmpSIOVREF__Drive_Left_Backup_net),
.interrupt({tmpINTERRUPT_0__Drive_Left_Backup_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Drive_Left_Backup_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Camera_Pan_MCU_net;
wire [0:0] tmpIO_0__Camera_Pan_MCU_net;
wire [0:0] tmpINTERRUPT_0__Camera_Pan_MCU_net;
electrical [0:0] tmpSIOVREF__Camera_Pan_MCU_net;
cy_psoc3_pins_v1_10
#(.id("0e7c51d4-aef8-4b3d-8520-4caaea73c53c"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Camera_Pan_MCU
(.oe(tmpOE__Camera_Pan_MCU_net),
.y({1'b0}),
.fb({Net_161}),
.io({tmpIO_0__Camera_Pan_MCU_net[0:0]}),
.siovref(tmpSIOVREF__Camera_Pan_MCU_net),
.interrupt({tmpINTERRUPT_0__Camera_Pan_MCU_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Camera_Pan_MCU_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Camera_Pan_Backup_net;
wire [0:0] tmpIO_0__Camera_Pan_Backup_net;
wire [0:0] tmpINTERRUPT_0__Camera_Pan_Backup_net;
electrical [0:0] tmpSIOVREF__Camera_Pan_Backup_net;
cy_psoc3_pins_v1_10
#(.id("fe137c29-1e68-4de1-83e5-e8575abeacdf"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Camera_Pan_Backup
(.oe(tmpOE__Camera_Pan_Backup_net),
.y({1'b0}),
.fb({Net_162}),
.io({tmpIO_0__Camera_Pan_Backup_net[0:0]}),
.siovref(tmpSIOVREF__Camera_Pan_Backup_net),
.interrupt({tmpINTERRUPT_0__Camera_Pan_Backup_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Camera_Pan_Backup_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Camera_Tilt_MCU_net;
wire [0:0] tmpIO_0__Camera_Tilt_MCU_net;
wire [0:0] tmpINTERRUPT_0__Camera_Tilt_MCU_net;
electrical [0:0] tmpSIOVREF__Camera_Tilt_MCU_net;
cy_psoc3_pins_v1_10
#(.id("e0e56a05-85ce-4362-8864-184e0734ab58"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Camera_Tilt_MCU
(.oe(tmpOE__Camera_Tilt_MCU_net),
.y({1'b0}),
.fb({Net_165}),
.io({tmpIO_0__Camera_Tilt_MCU_net[0:0]}),
.siovref(tmpSIOVREF__Camera_Tilt_MCU_net),
.interrupt({tmpINTERRUPT_0__Camera_Tilt_MCU_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Camera_Tilt_MCU_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Camera_Tilt_Backup_net;
wire [0:0] tmpIO_0__Camera_Tilt_Backup_net;
wire [0:0] tmpINTERRUPT_0__Camera_Tilt_Backup_net;
electrical [0:0] tmpSIOVREF__Camera_Tilt_Backup_net;
cy_psoc3_pins_v1_10
#(.id("204437f7-6e91-419a-bc62-240c71c65f2c"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Camera_Tilt_Backup
(.oe(tmpOE__Camera_Tilt_Backup_net),
.y({1'b0}),
.fb({Net_166}),
.io({tmpIO_0__Camera_Tilt_Backup_net[0:0]}),
.siovref(tmpSIOVREF__Camera_Tilt_Backup_net),
.interrupt({tmpINTERRUPT_0__Camera_Tilt_Backup_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Camera_Tilt_Backup_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Drive_Right_net;
wire [0:0] tmpFB_0__Drive_Right_net;
wire [0:0] tmpIO_0__Drive_Right_net;
wire [0:0] tmpINTERRUPT_0__Drive_Right_net;
electrical [0:0] tmpSIOVREF__Drive_Right_net;
cy_psoc3_pins_v1_10
#(.id("e851a3b9-efb8-48be-bbb8-b303b216c393"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Drive_Right
(.oe(tmpOE__Drive_Right_net),
.y({Net_155}),
.fb({tmpFB_0__Drive_Right_net[0:0]}),
.io({tmpIO_0__Drive_Right_net[0:0]}),
.siovref(tmpSIOVREF__Drive_Right_net),
.interrupt({tmpINTERRUPT_0__Drive_Right_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Drive_Right_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Drive_Left_net;
wire [0:0] tmpFB_0__Drive_Left_net;
wire [0:0] tmpIO_0__Drive_Left_net;
wire [0:0] tmpINTERRUPT_0__Drive_Left_net;
electrical [0:0] tmpSIOVREF__Drive_Left_net;
cy_psoc3_pins_v1_10
#(.id("15279825-9274-4f3c-ace8-045f65b21860"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Drive_Left
(.oe(tmpOE__Drive_Left_net),
.y({Net_159}),
.fb({tmpFB_0__Drive_Left_net[0:0]}),
.io({tmpIO_0__Drive_Left_net[0:0]}),
.siovref(tmpSIOVREF__Drive_Left_net),
.interrupt({tmpINTERRUPT_0__Drive_Left_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Drive_Left_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Camera_Pan_net;
wire [0:0] tmpFB_0__Camera_Pan_net;
wire [0:0] tmpIO_0__Camera_Pan_net;
wire [0:0] tmpINTERRUPT_0__Camera_Pan_net;
electrical [0:0] tmpSIOVREF__Camera_Pan_net;
cy_psoc3_pins_v1_10
#(.id("9ae1b4e3-4f1c-45a5-9de9-a1a85cb059d5"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Camera_Pan
(.oe(tmpOE__Camera_Pan_net),
.y({Net_163}),
.fb({tmpFB_0__Camera_Pan_net[0:0]}),
.io({tmpIO_0__Camera_Pan_net[0:0]}),
.siovref(tmpSIOVREF__Camera_Pan_net),
.interrupt({tmpINTERRUPT_0__Camera_Pan_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Camera_Pan_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Camera_Tilt_net;
wire [0:0] tmpFB_0__Camera_Tilt_net;
wire [0:0] tmpIO_0__Camera_Tilt_net;
wire [0:0] tmpINTERRUPT_0__Camera_Tilt_net;
electrical [0:0] tmpSIOVREF__Camera_Tilt_net;
cy_psoc3_pins_v1_10
#(.id("f5a36d19-a254-45f0-b254-ea06997facf5"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
Camera_Tilt
(.oe(tmpOE__Camera_Tilt_net),
.y({Net_167}),
.fb({tmpFB_0__Camera_Tilt_net[0:0]}),
.io({tmpIO_0__Camera_Tilt_net[0:0]}),
.siovref(tmpSIOVREF__Camera_Tilt_net),
.interrupt({tmpINTERRUPT_0__Camera_Tilt_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Camera_Tilt_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
module dct_top_2d(
clk,
rst,
inverse,
i_valid,
i_transize,
tq_sel_i,
i_data_0,
i_data_1,
i_data_2,
i_data_3,
i_data_4,
i_data_5,
i_data_6,
i_data_7,
i_data_8,
i_data_9,
i_data_10,
i_data_11,
i_data_12,
i_data_13,
i_data_14,
i_data_15,
i_data_16,
i_data_17,
i_data_18,
i_data_19,
i_data_20,
i_data_21,
i_data_22,
i_data_23,
i_data_24,
i_data_25,
i_data_26,
i_data_27,
i_data_28,
i_data_29,
i_data_30,
i_data_31,
o_valid,
o_data_0,
o_data_1,
o_data_2,
o_data_3,
o_data_4,
o_data_5,
o_data_6,
o_data_7,
o_data_8,
o_data_9,
o_data_10,
o_data_11,
o_data_12,
o_data_13,
o_data_14,
o_data_15,
o_data_16,
o_data_17,
o_data_18,
o_data_19,
o_data_20,
o_data_21,
o_data_22,
o_data_23,
o_data_24,
o_data_25,
o_data_26,
o_data_27,
o_data_28,
o_data_29,
o_data_30,
o_data_31
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk;
input rst;
input inverse;
input i_valid;
input [1:0] i_transize;
input [1:0] tq_sel_i;
input signed [15:0] i_data_0;
input signed [15:0] i_data_1;
input signed [15:0] i_data_2;
input signed [15:0] i_data_3;
input signed [15:0] i_data_4;
input signed [15:0] i_data_5;
input signed [15:0] i_data_6;
input signed [15:0] i_data_7;
input signed [15:0] i_data_8;
input signed [15:0] i_data_9;
input signed [15:0] i_data_10;
input signed [15:0] i_data_11;
input signed [15:0] i_data_12;
input signed [15:0] i_data_13;
input signed [15:0] i_data_14;
input signed [15:0] i_data_15;
input signed [15:0] i_data_16;
input signed [15:0] i_data_17;
input signed [15:0] i_data_18;
input signed [15:0] i_data_19;
input signed [15:0] i_data_20;
input signed [15:0] i_data_21;
input signed [15:0] i_data_22;
input signed [15:0] i_data_23;
input signed [15:0] i_data_24;
input signed [15:0] i_data_25;
input signed [15:0] i_data_26;
input signed [15:0] i_data_27;
input signed [15:0] i_data_28;
input signed [15:0] i_data_29;
input signed [15:0] i_data_30;
input signed [15:0] i_data_31;
output o_valid;
output signed [15:0] o_data_0;
output signed [15:0] o_data_1;
output signed [15:0] o_data_2;
output signed [15:0] o_data_3;
output signed [15:0] o_data_4;
output signed [15:0] o_data_5;
output signed [15:0] o_data_6;
output signed [15:0] o_data_7;
output signed [15:0] o_data_8;
output signed [15:0] o_data_9;
output signed [15:0] o_data_10;
output signed [15:0] o_data_11;
output signed [15:0] o_data_12;
output signed [15:0] o_data_13;
output signed [15:0] o_data_14;
output signed [15:0] o_data_15;
output signed [15:0] o_data_16;
output signed [15:0] o_data_17;
output signed [15:0] o_data_18;
output signed [15:0] o_data_19;
output signed [15:0] o_data_20;
output signed [15:0] o_data_21;
output signed [15:0] o_data_22;
output signed [15:0] o_data_23;
output signed [15:0] o_data_24;
output signed [15:0] o_data_25;
output signed [15:0] o_data_26;
output signed [15:0] o_data_27;
output signed [15:0] o_data_28;
output signed [15:0] o_data_29;
output signed [15:0] o_data_30;
output signed [15:0] o_data_31;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire i_val;
wire row;
wire i_d_valid;
wire signed [15:0] i_d_0 ;
wire signed [15:0] i_d_1 ;
wire signed [15:0] i_d_2 ;
wire signed [15:0] i_d_3 ;
wire signed [15:0] i_d_4 ;
wire signed [15:0] i_d_5 ;
wire signed [15:0] i_d_6 ;
wire signed [15:0] i_d_7 ;
wire signed [15:0] i_d_8 ;
wire signed [15:0] i_d_9 ;
wire signed [15:0] i_d_10;
wire signed [15:0] i_d_11;
wire signed [15:0] i_d_12;
wire signed [15:0] i_d_13;
wire signed [15:0] i_d_14;
wire signed [15:0] i_d_15;
wire signed [15:0] i_d_16;
wire signed [15:0] i_d_17;
wire signed [15:0] i_d_18;
wire signed [15:0] i_d_19;
wire signed [15:0] i_d_20;
wire signed [15:0] i_d_21;
wire signed [15:0] i_d_22;
wire signed [15:0] i_d_23;
wire signed [15:0] i_d_24;
wire signed [15:0] i_d_25;
wire signed [15:0] i_d_26;
wire signed [15:0] i_d_27;
wire signed [15:0] i_d_28;
wire signed [15:0] i_d_29;
wire signed [15:0] i_d_30;
wire signed [15:0] i_d_31;
wire o_d_valid;
wire signed [15:0] o_d_0 ;
wire signed [15:0] o_d_1 ;
wire signed [15:0] o_d_2 ;
wire signed [15:0] o_d_3 ;
wire signed [15:0] o_d_4 ;
wire signed [15:0] o_d_5 ;
wire signed [15:0] o_d_6 ;
wire signed [15:0] o_d_7 ;
wire signed [15:0] o_d_8 ;
wire signed [15:0] o_d_9 ;
wire signed [15:0] o_d_10;
wire signed [15:0] o_d_11;
wire signed [15:0] o_d_12;
wire signed [15:0] o_d_13;
wire signed [15:0] o_d_14;
wire signed [15:0] o_d_15;
wire signed [15:0] o_d_16;
wire signed [15:0] o_d_17;
wire signed [15:0] o_d_18;
wire signed [15:0] o_d_19;
wire signed [15:0] o_d_20;
wire signed [15:0] o_d_21;
wire signed [15:0] o_d_22;
wire signed [15:0] o_d_23;
wire signed [15:0] o_d_24;
wire signed [15:0] o_d_25;
wire signed [15:0] o_d_26;
wire signed [15:0] o_d_27;
wire signed [15:0] o_d_28;
wire signed [15:0] o_d_29;
wire signed [15:0] o_d_30;
wire signed [15:0] o_d_31;
wire i_s_valid;
wire signed [15:0] i_s_0 ;
wire signed [15:0] i_s_1 ;
wire signed [15:0] i_s_2 ;
wire signed [15:0] i_s_3 ;
wire signed [15:0] i_s_4 ;
wire signed [15:0] i_s_5 ;
wire signed [15:0] i_s_6 ;
wire signed [15:0] i_s_7 ;
wire signed [15:0] i_s_8 ;
wire signed [15:0] i_s_9 ;
wire signed [15:0] i_s_10;
wire signed [15:0] i_s_11;
wire signed [15:0] i_s_12;
wire signed [15:0] i_s_13;
wire signed [15:0] i_s_14;
wire signed [15:0] i_s_15;
wire signed [15:0] i_s_16;
wire signed [15:0] i_s_17;
wire signed [15:0] i_s_18;
wire signed [15:0] i_s_19;
wire signed [15:0] i_s_20;
wire signed [15:0] i_s_21;
wire signed [15:0] i_s_22;
wire signed [15:0] i_s_23;
wire signed [15:0] i_s_24;
wire signed [15:0] i_s_25;
wire signed [15:0] i_s_26;
wire signed [15:0] i_s_27;
wire signed [15:0] i_s_28;
wire signed [15:0] i_s_29;
wire signed [15:0] i_s_30;
wire signed [15:0] i_s_31;
wire o_s_valid;
wire signed [15:0] o_s_0 ;
wire signed [15:0] o_s_1 ;
wire signed [15:0] o_s_2 ;
wire signed [15:0] o_s_3 ;
wire signed [15:0] o_s_4 ;
wire signed [15:0] o_s_5 ;
wire signed [15:0] o_s_6 ;
wire signed [15:0] o_s_7 ;
wire signed [15:0] o_s_8 ;
wire signed [15:0] o_s_9 ;
wire signed [15:0] o_s_10;
wire signed [15:0] o_s_11;
wire signed [15:0] o_s_12;
wire signed [15:0] o_s_13;
wire signed [15:0] o_s_14;
wire signed [15:0] o_s_15;
wire signed [15:0] o_s_16;
wire signed [15:0] o_s_17;
wire signed [15:0] o_s_18;
wire signed [15:0] o_s_19;
wire signed [15:0] o_s_20;
wire signed [15:0] o_s_21;
wire signed [15:0] o_s_22;
wire signed [15:0] o_s_23;
wire signed [15:0] o_s_24;
wire signed [15:0] o_s_25;
wire signed [15:0] o_s_26;
wire signed [15:0] o_s_27;
wire signed [15:0] o_s_28;
wire signed [15:0] o_s_29;
wire signed [15:0] o_s_30;
wire signed [15:0] o_s_31;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg counter_en;
reg counter_val_en;
reg [2:0] counter;
reg [4:0] counter_val;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign i_val=i_valid||counter_val_en;
assign row=~(i_val||counter_en);
assign i_d_valid=row?o_s_valid:i_valid;
assign i_d_0 =row?o_s_0 :i_data_0 ;
assign i_d_1 =row?o_s_1 :i_data_1 ;
assign i_d_2 =row?o_s_2 :i_data_2 ;
assign i_d_3 =row?o_s_3 :i_data_3 ;
assign i_d_4 =row?o_s_4 :i_data_4 ;
assign i_d_5 =row?o_s_5 :i_data_5 ;
assign i_d_6 =row?o_s_6 :i_data_6 ;
assign i_d_7 =row?o_s_7 :i_data_7 ;
assign i_d_8 =row?o_s_8 :i_data_8 ;
assign i_d_9 =row?o_s_9 :i_data_9 ;
assign i_d_10=row?o_s_10:i_data_10;
assign i_d_11=row?o_s_11:i_data_11;
assign i_d_12=row?o_s_12:i_data_12;
assign i_d_13=row?o_s_13:i_data_13;
assign i_d_14=row?o_s_14:i_data_14;
assign i_d_15=row?o_s_15:i_data_15;
assign i_d_16=row?o_s_16:i_data_16;
assign i_d_17=row?o_s_17:i_data_17;
assign i_d_18=row?o_s_18:i_data_18;
assign i_d_19=row?o_s_19:i_data_19;
assign i_d_20=row?o_s_20:i_data_20;
assign i_d_21=row?o_s_21:i_data_21;
assign i_d_22=row?o_s_22:i_data_22;
assign i_d_23=row?o_s_23:i_data_23;
assign i_d_24=row?o_s_24:i_data_24;
assign i_d_25=row?o_s_25:i_data_25;
assign i_d_26=row?o_s_26:i_data_26;
assign i_d_27=row?o_s_27:i_data_27;
assign i_d_28=row?o_s_28:i_data_28;
assign i_d_29=row?o_s_29:i_data_29;
assign i_d_30=row?o_s_30:i_data_30;
assign i_d_31=row?o_s_31:i_data_31;
assign i_s_valid=row?1'b0:o_d_valid;
assign i_s_0 =row?16'b0:o_d_0 ;
assign i_s_1 =row?16'b0:o_d_1 ;
assign i_s_2 =row?16'b0:o_d_2 ;
assign i_s_3 =row?16'b0:o_d_3 ;
assign i_s_4 =row?16'b0:o_d_4 ;
assign i_s_5 =row?16'b0:o_d_5 ;
assign i_s_6 =row?16'b0:o_d_6 ;
assign i_s_7 =row?16'b0:o_d_7 ;
assign i_s_8 =row?16'b0:o_d_8 ;
assign i_s_9 =row?16'b0:o_d_9 ;
assign i_s_10 =row?16'b0:o_d_10;
assign i_s_11 =row?16'b0:o_d_11;
assign i_s_12 =row?16'b0:o_d_12;
assign i_s_13 =row?16'b0:o_d_13;
assign i_s_14 =row?16'b0:o_d_14;
assign i_s_15 =row?16'b0:o_d_15;
assign i_s_16 =row?16'b0:o_d_16;
assign i_s_17 =row?16'b0:o_d_17;
assign i_s_18 =row?16'b0:o_d_18;
assign i_s_19 =row?16'b0:o_d_19;
assign i_s_20 =row?16'b0:o_d_20;
assign i_s_21 =row?16'b0:o_d_21;
assign i_s_22 =row?16'b0:o_d_22;
assign i_s_23 =row?16'b0:o_d_23;
assign i_s_24 =row?16'b0:o_d_24;
assign i_s_25 =row?16'b0:o_d_25;
assign i_s_26 =row?16'b0:o_d_26;
assign i_s_27 =row?16'b0:o_d_27;
assign i_s_28 =row?16'b0:o_d_28;
assign i_s_29 =row?16'b0:o_d_29;
assign i_s_30 =row?16'b0:o_d_30;
assign i_s_31 =row?16'b0:o_d_31;
assign o_valid=row?o_d_valid:1'b0;
assign o_data_0 =row?o_d_0 :16'b0;
assign o_data_1 =row?o_d_1 :16'b0;
assign o_data_2 =row?o_d_2 :16'b0;
assign o_data_3 =row?o_d_3 :16'b0;
assign o_data_4 =row?o_d_4 :16'b0;
assign o_data_5 =row?o_d_5 :16'b0;
assign o_data_6 =row?o_d_6 :16'b0;
assign o_data_7 =row?o_d_7 :16'b0;
assign o_data_8 =row?o_d_8 :16'b0;
assign o_data_9 =row?o_d_9 :16'b0;
assign o_data_10=row?o_d_10:16'b0;
assign o_data_11=row?o_d_11:16'b0;
assign o_data_12=row?o_d_12:16'b0;
assign o_data_13=row?o_d_13:16'b0;
assign o_data_14=row?o_d_14:16'b0;
assign o_data_15=row?o_d_15:16'b0;
assign o_data_16=row?o_d_16:16'b0;
assign o_data_17=row?o_d_17:16'b0;
assign o_data_18=row?o_d_18:16'b0;
assign o_data_19=row?o_d_19:16'b0;
assign o_data_20=row?o_d_20:16'b0;
assign o_data_21=row?o_d_21:16'b0;
assign o_data_22=row?o_d_22:16'b0;
assign o_data_23=row?o_d_23:16'b0;
assign o_data_24=row?o_d_24:16'b0;
assign o_data_25=row?o_d_25:16'b0;
assign o_data_26=row?o_d_26:16'b0;
assign o_data_27=row?o_d_27:16'b0;
assign o_data_28=row?o_d_28:16'b0;
assign o_data_29=row?o_d_29:16'b0;
assign o_data_30=row?o_d_30:16'b0;
assign o_data_31=row?o_d_31:16'b0;
// ********************************************
//
// Sequential Logic
//
// ********************************************
always@(posedge clk or negedge rst)
if(!rst)
counter_val<=5'd0;
else
if(i_valid)
case(i_transize)
2'b00:
counter_val<=5'd0;
2'b01:
if(counter_val==5'd1)
counter_val<=5'd0;
else
counter_val<=counter_val+1'b1;
2'b10:
if(counter_val==5'd7)
counter_val<=5'd0;
else
counter_val<=counter_val+1'b1;
2'b11:
if(counter_val==5'd31)
counter_val<=5'd0;
else
counter_val<=counter_val+1'b1;
endcase
always@(posedge clk or negedge rst)
if(!rst)
counter_val_en<=1'b0;
else
case(i_transize)
2'b00:counter_val_en<=1'b0;
2'b01:begin
if((counter_val==5'd0)&&(i_valid))
counter_val_en<=1'b1;
else if((counter_val==5'd1)&&(i_valid))
counter_val_en<=1'b0;
end
2'b10:begin
if((counter_val==5'd0)&&(i_valid))
counter_val_en<=1'b1;
else if((counter_val==5'd7)&&(i_valid))
counter_val_en<=1'b0;
end
2'b11:begin
if((counter_val==5'd0)&&(i_valid))
counter_val_en<=1'b1;
else if((counter_val==5'd31)&&(i_valid))
counter_val_en<=1'b0;
end
endcase
always@(posedge clk or negedge rst)
if(!rst)
counter_en<=1'b0;
else
case(i_transize)
2'b00:begin
if(i_valid)
counter_en<=1'b1;
else if(counter==3'd4)
begin
counter_en<=1'b0;
end
end
2'b01:begin
if(i_valid&&(counter_val==5'd1))
counter_en<=1'b1;
else if(counter==3'd5)
begin
counter_en<=1'b0;
end
end
2'b10:begin
if(i_valid&&(counter_val==5'd7))
counter_en<=1'b1;
else if(counter==3'd5)
begin
counter_en<=1'b0;
end
end
2'b11:begin
if(i_valid&&(counter_val==5'd31))
counter_en<=1'b1;
else if(counter==3'd5)
begin
counter_en<=1'b0;
end
end
endcase
always@(posedge clk or negedge rst)
if(!rst)
counter<=3'd0;
else if(((i_transize=='d0)&&(counter==3'd4))||
((i_transize=='d1)&&(counter==3'd5))||
((i_transize=='d2)&&(counter==3'd5))||
((i_transize=='d3)&&(counter==3'd5)))
counter <= 3'd0;
else if(counter_en)
counter<=counter+1'b1;
else
counter<=3'd0;
// ********************************************
//
// Sub Modules
//
// ********************************************
dct_top dct_top_0(
clk,
rst,
row,
i_d_valid,
inverse,
i_transize,
tq_sel_i,
i_d_0,
i_d_1,
i_d_2,
i_d_3,
i_d_4,
i_d_5,
i_d_6,
i_d_7,
i_d_8,
i_d_9,
i_d_10,
i_d_11,
i_d_12,
i_d_13,
i_d_14,
i_d_15,
i_d_16,
i_d_17,
i_d_18,
i_d_19,
i_d_20,
i_d_21,
i_d_22,
i_d_23,
i_d_24,
i_d_25,
i_d_26,
i_d_27,
i_d_28,
i_d_29,
i_d_30,
i_d_31,
o_d_valid,
o_d_0,
o_d_1,
o_d_2,
o_d_3,
o_d_4,
o_d_5,
o_d_6,
o_d_7,
o_d_8,
o_d_9,
o_d_10,
o_d_11,
o_d_12,
o_d_13,
o_d_14,
o_d_15,
o_d_16,
o_d_17,
o_d_18,
o_d_19,
o_d_20,
o_d_21,
o_d_22,
o_d_23,
o_d_24,
o_d_25,
o_d_26,
o_d_27,
o_d_28,
o_d_29,
o_d_30,
o_d_31
);
transform_memory transform_memory_top0(
clk,
rst,
i_s_valid,
i_transize,
i_s_0,
i_s_1,
i_s_2,
i_s_3,
i_s_4,
i_s_5,
i_s_6,
i_s_7,
i_s_8,
i_s_9,
i_s_10,
i_s_11,
i_s_12,
i_s_13,
i_s_14,
i_s_15,
i_s_16,
i_s_17,
i_s_18,
i_s_19,
i_s_20,
i_s_21,
i_s_22,
i_s_23,
i_s_24,
i_s_25,
i_s_26,
i_s_27,
i_s_28,
i_s_29,
i_s_30,
i_s_31,
o_s_valid,
o_s_0,
o_s_1,
o_s_2,
o_s_3,
o_s_4,
o_s_5,
o_s_6,
o_s_7,
o_s_8,
o_s_9,
o_s_10,
o_s_11,
o_s_12,
o_s_13,
o_s_14,
o_s_15,
o_s_16,
o_s_17,
o_s_18,
o_s_19,
o_s_20,
o_s_21,
o_s_22,
o_s_23,
o_s_24,
o_s_25,
o_s_26,
o_s_27,
o_s_28,
o_s_29,
o_s_30,
o_s_31
);
endmodule
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used *
* solely for design, simulation, implementation and creation of *
* design files limited to Xilinx devices or technologies. Use *
* with non-Xilinx devices or technologies is expressly prohibited *
* and immediately terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" *
* SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR *
* XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION *
* AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION *
* OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS *
* IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, *
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE *
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY *
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *
* FOR A PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support *
* appliances, devices, or systems. Use in such applications are *
* expressly prohibited. *
* *
* (c) Copyright 1995-2007 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
// You must compile the wrapper file ram_8x512_lo.v when simulating
// the core, ram_8x512_lo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
`timescale 1ns/1ps
module ram_8x512_lo(
addr,
clk,
din,
dout,
en,
we);
input [8 : 0] addr;
input clk;
input [7 : 0] din;
output [7 : 0] dout;
input en;
input we;
// synthesis translate_off
BLKMEMSP_V6_2 #(
.c_addr_width(9),
.c_default_data("0"),
.c_depth(512),
.c_enable_rlocs(0),
.c_has_default_data(1),
.c_has_din(1),
.c_has_en(1),
.c_has_limit_data_pitch(0),
.c_has_nd(0),
.c_has_rdy(0),
.c_has_rfd(0),
.c_has_sinit(0),
.c_has_we(1),
.c_limit_data_pitch(18),
.c_mem_init_file("mif_file_16_1"),
.c_pipe_stages(0),
.c_reg_inputs(0),
.c_sinit_value("0"),
.c_width(8),
.c_write_mode(0),
.c_ybottom_addr("0"),
.c_yclk_is_rising(1),
.c_yen_is_high(0),
.c_yhierarchy("hierarchy1"),
.c_ymake_bmm(0),
.c_yprimitive_type("16kx1"),
.c_ysinit_is_high(1),
.c_ytop_addr("1024"),
.c_yuse_single_primitive(0),
.c_ywe_is_high(0),
.c_yydisable_warnings(1))
inst (
.ADDR(addr),
.CLK(clk),
.DIN(din),
.DOUT(dout),
.EN(en),
.WE(we),
.ND(),
.RFD(),
.RDY(),
.SINIT());
// synthesis translate_on
// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of ram_8x512_lo is "black_box"
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a buffer that holds characters to be displayed on a *
* VGA or LCD screen. *
* *
******************************************************************************/
module nios_system_Char_Buffer_with_DMA (
// Inputs
clk,
reset,
ctrl_address,
ctrl_byteenable,
ctrl_chipselect,
ctrl_read,
ctrl_write,
ctrl_writedata,
buf_address,
buf_byteenable,
buf_chipselect,
buf_read,
buf_write,
buf_writedata,
stream_ready,
// Bidirectionals
// Outputs
ctrl_readdata,
buf_readdata,
buf_waitrequest,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 8;
parameter ENLARGE_CHAR = 0;
parameter AW = 13;
parameter BUFFER_SIZE = 8192;
parameter PIXELS = 640;
parameter LINES = 480;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input ctrl_address;
input [ 3: 0] ctrl_byteenable;
input ctrl_chipselect;
input ctrl_read;
input ctrl_write;
input [31: 0] ctrl_writedata;
input [(AW-1): 0] buf_address;
input buf_byteenable;
input buf_chipselect;
input buf_read;
input buf_write;
input [ 7: 0] buf_writedata;
input stream_ready;
// Bidirectionals
// Outputs
output reg [31: 0] ctrl_readdata;
output reg [ 7: 0] buf_readdata;
output buf_waitrequest;
output [39: 0] stream_data;
output stream_startofpacket;
output stream_endofpacket;
output [ 1: 0] stream_empty;
output stream_valid;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
//localparam NUMBER_OF_BITS_FOR_X_COORD = 10;
//localparam NUMBER_OF_BITS_FOR_Y_COORD = 9;
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
wire [DW: 1] char_data_to_buffer;
wire [DW: 1] char_data_from_buffer;
wire [AW: 1] cur_char_position;
wire [15: 0] cur_char_for_display;
wire cur_char_data;
wire [ 9: 0] char_red;
wire [ 9: 0] char_green;
wire [ 9: 0] char_blue;
// Internal Registers
reg [31: 0] control_reg;
reg [ 1: 0] delayed_buf_waitrequest;
reg clear_screen;
reg [ 9: 0] x_position;
reg [ 8: 0] y_position;
reg [ 5: 0] delayed_x_position;
reg [ 5: 0] delayed_y_position;
reg [ 3: 0] delayed_startofpacket;
reg [ 3: 0] delayed_endofpacket;
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
always @(posedge clk)
begin
if (reset)
ctrl_readdata <= 32'h00000000;
else if (ctrl_chipselect & ctrl_read & ctrl_address)
ctrl_readdata <= {16'd60, 16'd80};
else if (ctrl_chipselect & ctrl_read)
ctrl_readdata <= control_reg;
end
always @(posedge clk)
begin
if (reset)
buf_readdata <= 8'h00;
else if (buf_chipselect & buf_read)
buf_readdata <= {1'b0, char_data_from_buffer[7:1]};
end
// Internal Registers
always @(posedge clk)
begin
if (reset)
control_reg <= 32'h00010000;
else if (ctrl_chipselect & ctrl_write & ~ctrl_address)
begin
if (ctrl_byteenable[0])
control_reg[ 7: 0] <= ctrl_writedata[ 7: 0];
if (ctrl_byteenable[1])
control_reg[15: 8] <= ctrl_writedata[15: 8];
if (ctrl_byteenable[2])
control_reg[23:16] <= ctrl_writedata[23:16];
if (ctrl_byteenable[3])
control_reg[31:24] <= ctrl_writedata[31:24];
end
else if (clear_screen & stream_ready &
(x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
control_reg[16] <= 1'b0;
end
always @(posedge clk)
begin
if (reset)
delayed_buf_waitrequest <= 2'h0;
else if (buf_chipselect & buf_read)
delayed_buf_waitrequest <= {delayed_buf_waitrequest[0], 1'b1};
else
delayed_buf_waitrequest <= 2'h0;
end
always @(posedge clk)
begin
if (reset)
clear_screen <= 1'b1;
else if (~(control_reg[16]))
clear_screen <= 1'b0;
else if ((x_position == 10'h000) && (y_position == 9'h000))
clear_screen <= 1'b1;
end
always @(posedge clk)
begin
if (reset)
x_position <= 10'h000;
else if (stream_ready)
begin
if (x_position == (PIXELS - 1))
x_position <= 10'h000;
else
x_position <= x_position + 10'h001;
end
end
always @(posedge clk)
begin
if (reset)
y_position <= 9'h000;
else if (stream_ready && (x_position == (PIXELS - 1)))
begin
if (y_position == (LINES - 1))
y_position <= 9'h000;
else
y_position <= y_position + 9'h001;
end
end
always @(posedge clk)
begin
if (reset)
begin
delayed_x_position <= 6'h00;
delayed_y_position <= 6'h00;
end
else if (stream_ready)
begin
delayed_x_position <= {delayed_x_position[2:0],
x_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
delayed_y_position <= {delayed_y_position[2:0],
y_position[(ENLARGE_CHAR+2):ENLARGE_CHAR]};
end
end
always @(posedge clk)
begin
if (reset)
delayed_startofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_startofpacket[3:1] <= delayed_startofpacket[2:0];
if ((x_position == 10'h000) && (y_position == 9'h000))
delayed_startofpacket[0] <= 1'b1;
else
delayed_startofpacket[0] <= 1'b0;
end
end
always @(posedge clk)
begin
if (reset)
delayed_endofpacket <= 4'h0;
else if (stream_ready)
begin
delayed_endofpacket[3:1] <= delayed_endofpacket[2:0];
if ((x_position == (PIXELS - 1)) && (y_position == (LINES - 1)))
delayed_endofpacket[0] <= 1'b1;
else
delayed_endofpacket[0] <= 1'b0;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign buf_waitrequest =
(buf_chipselect & buf_read) & ~delayed_buf_waitrequest[1];
assign stream_data[39:30] = {10{cur_char_data}};
assign stream_data[29: 0] = {char_red, char_green, char_blue};
assign stream_startofpacket = delayed_startofpacket[3];
assign stream_endofpacket = delayed_endofpacket[3];
assign stream_empty = 2'h0;
assign stream_valid = 1'b1;
// Internal Assignments
assign char_data_to_buffer = {control_reg[(DW-8):0], buf_writedata[6:0]};
assign cur_char_position =
{y_position[8:(3 + ENLARGE_CHAR)], x_position[9:(3 + ENLARGE_CHAR)]};
assign char_red = {10{cur_char_data}};
assign char_green = {10{cur_char_data}};
assign char_blue = {10{cur_char_data}};
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
altsyncram Char_Buffer_Memory (
// Inputs
.clock0 (clk),
.address_a (buf_address),
.wren_a (buf_byteenable & buf_chipselect & buf_write),
.data_a (char_data_to_buffer),
.clock1 (clk),
.clocken1 (stream_ready),
.address_b (cur_char_position),
.wren_b (clear_screen),
.data_b ({{(DW - 7){1'b0}}, 7'h20}),
// Bidirectionals
// Outputs
.q_a (char_data_from_buffer),
.q_b (cur_char_for_display),
// Unused
.rden_b (1'b1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.clocken0 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.byteena_a (1'b1),
.byteena_b (1'b1),
.rden_a (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0)
);
defparam
Char_Buffer_Memory.init_file = "UNUSED",
Char_Buffer_Memory.intended_device_family = "Cyclone II",
Char_Buffer_Memory.lpm_type = "altsyncram",
Char_Buffer_Memory.operation_mode = "BIDIR_DUAL_PORT",
Char_Buffer_Memory.read_during_write_mode_mixed_ports = "DONT_CARE",
Char_Buffer_Memory.power_up_uninitialized = "FALSE",
Char_Buffer_Memory.address_reg_b = "CLOCK1",
Char_Buffer_Memory.indata_reg_b = "CLOCK1",
Char_Buffer_Memory.wrcontrol_wraddress_reg_b = "CLOCK1",
Char_Buffer_Memory.clock_enable_input_a = "BYPASS",
Char_Buffer_Memory.clock_enable_input_b = "NORMAL",
Char_Buffer_Memory.clock_enable_output_a = "BYPASS",
Char_Buffer_Memory.clock_enable_output_b = "NORMAL",
Char_Buffer_Memory.numwords_a = BUFFER_SIZE,
Char_Buffer_Memory.numwords_b = BUFFER_SIZE,
Char_Buffer_Memory.outdata_aclr_a = "NONE",
Char_Buffer_Memory.outdata_aclr_b = "NONE",
Char_Buffer_Memory.outdata_reg_a = "CLOCK0",
Char_Buffer_Memory.outdata_reg_b = "CLOCK1",
Char_Buffer_Memory.widthad_a = AW,
Char_Buffer_Memory.widthad_b = AW,
Char_Buffer_Memory.width_a = DW,
Char_Buffer_Memory.width_b = DW,
Char_Buffer_Memory.width_byteena_a = 1,
Char_Buffer_Memory.width_byteena_b = 1;
altera_up_video_128_character_rom Character_Rom (
// Inputs
.clk (clk),
.clk_en (stream_ready),
.character (cur_char_for_display[ 6: 0]),
.x_coordinate (delayed_x_position[ 5: 3]),
.y_coordinate (delayed_y_position[ 5: 3]),
// Bidirectionals
// Outputs
.character_data (cur_char_data)
);
endmodule
|
(** * ProofObjects: Working with Explicit Evidence in Coq *)
Require Export MoreLogic.
(* ##################################################### *)
(** We have seen that Coq has mechanisms both for _programming_,
using inductive data types (like [nat] or [list]) and functions
over these types, and for _proving_ properties of these programs,
using inductive propositions (like [ev] or [eq]), implication, and
universal quantification. So far, we have treated these mechanisms
as if they were quite separate, and for many purposes this is
a good way to think. But we have also seen hints that Coq's programming and
proving facilities are closely related. For example, the
keyword [Inductive] is used to declare both data types and
propositions, and [->] is used both to describe the type of
functions on data and logical implication. This is not just a
syntactic accident! In fact, programs and proofs in Coq are almost
the same thing. In this chapter we will study how this works.
We have already seen the fundamental idea: provability in Coq is
represented by concrete _evidence_. When we construct the proof
of a basic proposition, we are actually building a tree of evidence,
which can be thought of as a data structure. If the proposition
is an implication like [A -> B], then its proof will be an
evidence _transformer_: a recipe for converting evidence for
A into evidence for B. So at a fundamental level, proofs are simply
programs that manipulate evidence.
*)
(**
Q. If evidence is data, what are propositions themselves?
A. They are types!
Look again at the formal definition of the [beautiful] property. *)
Print beautiful.
(* ==>
Inductive beautiful : nat -> Prop :=
b_0 : beautiful 0
| b_3 : beautiful 3
| b_5 : beautiful 5
| b_sum : forall n m : nat, beautiful n -> beautiful m -> beautiful (n + m)
*)
(** *** *)
(** The trick is to introduce an alternative pronunciation of "[:]".
Instead of "has type," we can also say "is a proof of." For
example, the second line in the definition of [beautiful] declares
that [b_0 : beautiful 0]. Instead of "[b_0] has type
[beautiful 0]," we can say that "[b_0] is a proof of [beautiful 0]."
Similarly for [b_3] and [b_5]. *)
(** *** *)
(** This pun between types and propositions (between [:] as "has type"
and [:] as "is a proof of" or "is evidence for") is called the
_Curry-Howard correspondence_. It proposes a deep connection
between the world of logic and the world of computation.
<<
propositions ~ types
proofs ~ data values
>>
Many useful insights follow from this connection. To begin with, it
gives us a natural interpretation of the type of [b_sum] constructor: *)
Check b_sum.
(* ===> b_sum : forall n m,
beautiful n ->
beautiful m ->
beautiful (n+m) *)
(** This can be read "[b_sum] is a constructor that takes four
arguments -- two numbers, [n] and [m], and two pieces of evidence,
for the propositions [beautiful n] and [beautiful m], respectively --
and yields evidence for the proposition [beautiful (n+m)]." *)
(** Now let's look again at a previous proof involving [beautiful]. *)
Theorem eight_is_beautiful: beautiful 8.
Proof.
apply b_sum with (n := 3) (m := 5).
apply b_3.
apply b_5. Qed.
(** Just as with ordinary data values and functions, we can use the [Print]
command to see the _proof object_ that results from this proof script. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5
: beautiful 8 *)
(** In view of this, we might wonder whether we can write such
an expression ourselves. Indeed, we can: *)
Check (b_sum 3 5 b_3 b_5).
(* ===> beautiful (3 + 5) *)
(** The expression [b_sum 3 5 b_3 b_5] can be thought of as
instantiating the parameterized constructor [b_sum] with the
specific arguments [3] [5] and the corresponding proof objects for
its premises [beautiful 3] and [beautiful 5] (Coq is smart enough
to figure out that 3+5=8). Alternatively, we can think of [b_sum]
as a primitive "evidence constructor" that, when applied to two
particular numbers, wants to be further applied to evidence that
those two numbers are beautiful; its type,
forall n m, beautiful n -> beautiful m -> beautiful (n+m),
expresses this functionality, in the same way that the polymorphic
type [forall X, list X] in the previous chapter expressed the fact
that the constructor [nil] can be thought of as a function from
types to empty lists with elements of that type. *)
(** This gives us an alternative way to write the proof that [8] is
beautiful: *)
Theorem eight_is_beautiful': beautiful 8.
Proof.
apply (b_sum 3 5 b_3 b_5).
Qed.
(** Notice that we're using [apply] here in a new way: instead of just
supplying the _name_ of a hypothesis or previously proved theorem
whose type matches the current goal, we are supplying an
_expression_ that directly builds evidence with the required
type. *)
(* ##################################################### *)
(** * Proof Scripts and Proof Objects *)
(** These proof objects lie at the core of how Coq operates.
When Coq is following a proof script, what is happening internally
is that it is gradually constructing a proof object -- a term
whose type is the proposition being proved. The tactics between
the [Proof] command and the [Qed] instruct Coq how to build up a
term of the required type. To see this process in action, let's
use the [Show Proof] command to display the current state of the
proof tree at various points in the following tactic proof. *)
Theorem eight_is_beautiful'': beautiful 8.
Proof.
Show Proof.
apply b_sum with (n:=3) (m:=5).
Show Proof.
apply b_3.
Show Proof.
apply b_5.
Show Proof.
Qed.
(** At any given moment, Coq has constructed a term with some
"holes" (indicated by [?1], [?2], and so on), and it knows what
type of evidence is needed at each hole. *)
(**
Each of the holes corresponds to a subgoal, and the proof is
finished when there are no more subgoals. At this point, the
[Theorem] command gives a name to the evidence we've built and
stores it in the global context. *)
(** Tactic proofs are useful and convenient, but they are not
essential: in principle, we can always construct the required
evidence by hand, as shown above. Then we can use [Definition]
(rather than [Theorem]) to give a global name directly to a
piece of evidence. *)
Definition eight_is_beautiful''' : beautiful 8 :=
b_sum 3 5 b_3 b_5.
(** All these different ways of building the proof lead to exactly the
same evidence being saved in the global environment. *)
Print eight_is_beautiful.
(* ===> eight_is_beautiful = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'.
(* ===> eight_is_beautiful' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful''.
(* ===> eight_is_beautiful'' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
Print eight_is_beautiful'''.
(* ===> eight_is_beautiful''' = b_sum 3 5 b_3 b_5 : beautiful 8 *)
(** **** Exercise: 1 star (six_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [6] is [beautiful]. *)
Theorem six_is_beautiful :
beautiful 6.
Proof.
apply b_sum with (n:=3) (m:=3).
apply b_3. apply b_3.
Qed.
Definition six_is_beautiful' : beautiful 6 :=
b_sum 3 3 b_3 b_3.
(** [] *)
(** **** Exercise: 1 star (nine_is_beautiful) *)
(** Give a tactic proof and a proof object showing that [9] is [beautiful]. *)
Theorem nine_is_beautiful :
beautiful 9.
Proof.
apply b_sum with (n:=3) (m:=6).
apply b_3. apply six_is_beautiful.
Qed.
Definition nine_is_beautiful' : beautiful 9 :=
b_sum 3 6 b_3 six_is_beautiful.
(** [] *)
(* ##################################################### *)
(** * Quantification, Implications and Functions *)
(** In Coq's computational universe (where we've mostly been living
until this chapter), there are two sorts of values with arrows in
their types: _constructors_ introduced by [Inductive]-ly defined
data types, and _functions_.
Similarly, in Coq's logical universe, there are two ways of giving
evidence for an implication: constructors introduced by
[Inductive]-ly defined propositions, and... functions!
For example, consider this statement: *)
Theorem b_plus3: forall n, beautiful n -> beautiful (3+n).
Proof.
intros n H.
apply b_sum.
apply b_3.
apply H.
Qed.
(** What is the proof object corresponding to [b_plus3]?
We're looking for an expression whose _type_ is [forall n,
beautiful n -> beautiful (3+n)] -- that is, a _function_ that
takes two arguments (one number and a piece of evidence) and
returns a piece of evidence! Here it is: *)
Definition b_plus3' : forall n, beautiful n -> beautiful (3+n) :=
fun (n : nat) => fun (H : beautiful n) =>
b_sum 3 n b_3 H.
Check b_plus3'.
(* ===> b_plus3' : forall n : nat, beautiful n -> beautiful (3+n) *)
(** Recall that [fun n => blah] means "the function that, given [n],
yields [blah]." Another equivalent way to write this definition is: *)
Definition b_plus3'' (n : nat) (H : beautiful n) : beautiful (3+n) :=
b_sum 3 n b_3 H.
Check b_plus3''.
(* ===> b_plus3'' : forall n, beautiful n -> beautiful (3+n) *)
(** When we view the proposition being proved by [b_plus3] as a function type,
one aspect of it may seem a little unusual. The second argument's
type, [beautiful n], mentions the _value_ of the first argument, [n].
While such _dependent types_ are not commonly found in programming
languages, even functional ones like ML or Haskell, they can
be useful there too.
Notice that both implication ([->]) and quantification ([forall])
correspond to functions on evidence. In fact, they are really the
same thing: [->] is just a shorthand for a degenerate use of
[forall] where there is no dependency, i.e., no need to give a name
to the type on the LHS of the arrow. *)
(** For example, consider this proposition: *)
Definition beautiful_plus3 : Prop :=
forall n, forall (E : beautiful n), beautiful (n+3).
(** A proof term inhabiting this proposition would be a function
with two arguments: a number [n] and some evidence [E] that [n] is
beautiful. But the name [E] for this evidence is not used in the
rest of the statement of [funny_prop1], so it's a bit silly to
bother making up a name for it. We could write it like this
instead, using the dummy identifier [_] in place of a real
name: *)
Definition beautiful_plus3' : Prop :=
forall n, forall (_ : beautiful n), beautiful (n+3).
(** Or, equivalently, we can write it in more familiar notation: *)
Definition beatiful_plus3'' : Prop :=
forall n, beautiful n -> beautiful (n+3).
(** In general, "[P -> Q]" is just syntactic sugar for
"[forall (_:P), Q]". *)
(** **** Exercise: 2 stars b_times2 *)
(** Give a proof object corresponding to the theorem [b_times2] from Prop.v *)
Definition b_times2': forall n, beautiful n -> beautiful (2*n) :=
fun (n : nat) => fun (B : beautiful n) =>
b_sum n (n + 0) B (b_sum n 0 B b_0).
(** [] *)
(** **** Exercise: 2 stars, optional (gorgeous_plus13_po) *)
(** Give a proof object corresponding to the theorem [gorgeous_plus13] from Prop.v *)
Definition gorgeous_plus13_po: forall n, gorgeous n -> gorgeous (13+n):=
fun (n : nat) => fun (G : gorgeous n) =>
g_plus3 (10+n) (g_plus5 (5+n) (g_plus5 n G)).
(** [] *)
(** It is particularly revealing to look at proof objects involving the
logical connectives that we defined with inductive propositions in Logic.v. *)
Theorem and_example :
(beautiful 0) /\ (beautiful 3).
Proof.
apply conj.
(* Case "left". *) apply b_0.
(* Case "right". *) apply b_3. Qed.
(** Let's take a look at the proof object for the above theorem. *)
Print and_example.
(* ===> conj (beautiful 0) (beautiful 3) b_0 b_3
: beautiful 0 /\ beautiful 3 *)
(** Note that the proof is of the form
conj (beautiful 0) (beautiful 3)
(...pf of beautiful 3...) (...pf of beautiful 3...)
as you'd expect, given the type of [conj]. *)
(** **** Exercise: 1 star, optional (case_proof_objects) *)
(** The [Case] tactics were commented out in the proof of
[and_example] to avoid cluttering the proof object. What would
you guess the proof object will look like if we uncomment them?
Try it and see. *)
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros P Q H.
inversion H as [HP HQ].
split.
(* Case "left". *) apply HQ.
(* Case "right". *) apply HP. Qed.
(** Once again, we have commented out the [Case] tactics to make the
proof object for this theorem easier to understand. It is still
a little complicated, but after performing some simple reduction
steps, we can see that all that is really happening is taking apart
a record containing evidence for [P] and [Q] and rebuilding it in the
opposite order: *)
Print and_commut.
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
(fun H0 : Q /\ P => H0)
match H with
| conj HP HQ => (fun (HP0 : P) (HQ0 : Q) => conj Q P HQ0 HP0) HP HQ
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** After simplifying some direct application of [fun] expressions to arguments,
we get: *)
(* ===>
and_commut =
fun (P Q : Prop) (H : P /\ Q) =>
match H with
| conj HP HQ => conj Q P HQ HP
end
: forall P Q : Prop, P /\ Q -> Q /\ P *)
(** **** Exercise: 2 stars, optional (conj_fact) *)
(** Construct a proof object demonstrating the following proposition. *)
Definition conj_fact : forall P Q R, P /\ Q -> Q /\ R -> P /\ R :=
fun (P Q R : Prop) (H : P /\ Q) (H0 : Q /\ R) =>
match H with
| conj HP HQ => match H0 with
| conj HQ HR => conj P R HP HR
end
end.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (beautiful_iff_gorgeous) *)
(** We have seen that the families of propositions [beautiful] and
[gorgeous] actually characterize the same set of numbers.
Prove that [beautiful n <-> gorgeous n] for all [n]. Just for
fun, write your proof as an explicit proof object, rather than
using tactics. (_Hint_: if you make use of previously defined
theorems, you should only need a single line!) *)
Definition beautiful_iff_gorgeous :
forall n, beautiful n <-> gorgeous n :=
fun n : nat =>
conj (beautiful n -> gorgeous n)
(gorgeous n -> beautiful n)
(beautiful__gorgeous n)
(gorgeous__beautiful n).
(** [] *)
(** **** Exercise: 2 stars, optional (or_commut'') *)
(** Try to write down an explicit proof object for [or_commut] (without
using [Print] to peek at the ones we already defined!). *)
Definition or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P :=
fun (P Q : Prop) (H : P \/ Q) =>
match H with
| or_introl HP => (or_intror Q P) HP
| or_intror HQ => (or_introl Q P) HQ
end.
(** [] *)
(** Recall that we model an existential for a property as a pair consisting of
a witness value and a proof that the witness obeys that property.
We can choose to construct the proof explicitly.
For example, consider this existentially quantified proposition: *)
Check ex.
Definition some_nat_is_even : Prop :=
ex _ ev.
(** To prove this proposition, we need to choose a particular number
as witness -- say, 4 -- and give some evidence that that number is
even. *)
Definition snie : some_nat_is_even :=
ex_intro _ ev 4 (ev_SS 2 (ev_SS 0 ev_0)).
(** **** Exercise: 2 stars, optional (ex_beautiful_Sn) *)
(** Complete the definition of the following proof object: *)
Definition p : ex _ (fun n => beautiful (S n)) :=
ex_intro _ (fun n => beautiful (S n)) 2 b_3.
(** [] *)
(* ##################################################### *)
(** * Giving Explicit Arguments to Lemmas and Hypotheses *)
(** Even when we are using tactic-based proof, it can be very useful to
understand the underlying functional nature of implications and quantification.
For example, it is often convenient to [apply] or [rewrite]
using a lemma or hypothesis with one or more quantifiers or
assumptions already instantiated in order to direct what
happens. For example: *)
Check plus_comm.
(* ==>
plus_comm
: forall n m : nat, n + m = m + n *)
Lemma plus_comm_r : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
(* rewrite plus_comm. *)
(* rewrites in the first possible spot; not what we want *)
rewrite (plus_comm b a). (* directs rewriting to the right spot *)
reflexivity. Qed.
(** In this case, giving just one argument would be sufficient. *)
Lemma plus_comm_r' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm b).
reflexivity. Qed.
(** Arguments must be given in order, but wildcards (_)
may be used to skip arguments that Coq can infer. *)
Lemma plus_comm_r'' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite (plus_comm _ a).
reflexivity. Qed.
(** The author of a lemma can choose to declare easily inferable arguments
to be implicit, just as with functions and constructors.
The [with] clauses we've already seen is really just a way of
specifying selected arguments by name rather than position: *)
Lemma plus_comm_r''' : forall a b c, c + (b + a) = c + (a + b).
Proof.
intros a b c.
rewrite plus_comm with (n := b).
reflexivity. Qed.
(** **** Exercise: 2 stars (trans_eq_example_redux) *)
(** Redo the proof of the following theorem (from MoreCoq.v) using
an [apply] of [trans_eq] but _not_ using a [with] clause. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros.
apply (trans_eq _ _ _ _ H H0).
Qed.
(** [] *)
(* ##################################################### *)
(** * Programming with Tactics (Optional) *)
(** If we can build proofs with explicit terms rather than
tactics, you may be wondering if we can build programs using
tactics rather than explicit terms. Sure! *)
Definition add1 : nat -> nat.
intro n.
Show Proof.
apply S.
Show Proof.
apply n. Defined.
Print add1.
(* ==>
add1 = fun n : nat => S n
: nat -> nat
*)
Eval compute in add1 2.
(* ==> 3 : nat *)
(** Notice that we terminate the [Definition] with a [.] rather than with
[:=] followed by a term. This tells Coq to enter proof scripting mode
to build an object of type [nat -> nat]. Also, we terminate the proof
with [Defined] rather than [Qed]; this makes the definition _transparent_
so that it can be used in computation like a normally-defined function.
This feature is mainly useful for writing functions with dependent types,
which we won't explore much further in this book.
But it does illustrate the uniformity and orthogonality of the basic ideas in Coq. *)
(* $Date: 2014-08-23 15:24:59 -0400 (Sat, 23 Aug 2014) $ *)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:50:34 03/11/2015
// Design Name:
// Module Name: delay_line
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module delayLine #(
parameter DELAY = 0,
parameter WIDTH = 8
)(
input ce,
input rst,
input clk,
input [WIDTH - 1:0] in,
output [WIDTH - 1:0] out
);
wire [WIDTH - 1:0] chain [DELAY:0];
assign chain[0] = in;
assign out = chain[DELAY];
genvar i;
generate
for(i = 0; i < DELAY; i = i + 1)
begin : chain_connector
wlatch #(
.WIDTH(WIDTH)
)
lat (
.ce(ce),
.rst(rst),
.clk(clk),
.in(chain[i]),
.out(chain[i + 1])
);
end
endgenerate
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board ADV7181 video chip.*
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_adv7181 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter INPUT_CONTROL = 16'h0040;
parameter CHROMA_GAIN_1 = 16'h2df4;
parameter CHROMA_GAIN_2 = 16'h2e00;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
// Video Config Data
10 : data <= {8'h40, 16'h1500};
11 : data <= {8'h40, 16'h1741};
12 : data <= {8'h40, 16'h3a16};
13 : data <= {8'h40, 16'h5004};
14 : data <= {8'h40, 16'hc305};
15 : data <= {8'h40, 16'hc480};
16 : data <= {8'h40, 16'h0e80};
17 : data <= {8'h40, 16'h5004};
18 : data <= {8'h40, 16'h5218};
19 : data <= {8'h40, 16'h58ed};
20 : data <= {8'h40, 16'h77c5};
21 : data <= {8'h40, 16'h7c93};
22 : data <= {8'h40, 16'h7d00};
23 : data <= {8'h40, 16'hd048};
24 : data <= {8'h40, 16'hd5a0};
25 : data <= {8'h40, 16'hd7ea};
26 : data <= {8'h40, 16'he43e};
27 : data <= {8'h40, 16'hea0f};
28 : data <= {8'h40, 16'h3112};
29 : data <= {8'h40, 16'h3281};
30 : data <= {8'h40, 16'h3384};
31 : data <= {8'h40, 16'h37A0};
32 : data <= {8'h40, 16'he580};
33 : data <= {8'h40, 16'he603};
34 : data <= {8'h40, 16'he785};
35 : data <= {8'h40, 16'h5004};
36 : data <= {8'h40, 16'h5100};
37 : data <= {8'h40, INPUT_CONTROL};
38 : data <= {8'h40, 16'h1000};
39 : data <= {8'h40, 16'h0402};
40 : data <= {8'h40, 16'h0860};
41 : data <= {8'h40, 16'h0a18};
42 : data <= {8'h40, 16'h1100};
43 : data <= {8'h40, 16'h2b00};
44 : data <= {8'h40, 16'h2c8c};
45 : data <= {8'h40, CHROMA_GAIN_1};
46 : data <= {8'h40, CHROMA_GAIN_2};
47 : data <= {8'h40, 16'h2ff4};
48 : data <= {8'h40, 16'h30d2};
49 : data <= {8'h40, 16'h0e05};
default : data <= {8'h00, 16'h0000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/******************************************************************************
* (C) Copyright 2014 AMIQ Consulting
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* NAME: amiq_eth_ve_top.sv
* PROJECT: amiq_eth
* Description: This file declares the top module from which the UVM flow is run
*******************************************************************************/
`ifndef __AMIQ_ETH_VE_TOP
`define __AMIQ_ETH_VE_TOP
`timescale 10ns/10ns
`include "amiq_eth_ve_pkg.sv"
import uvm_pkg::*;
import amiq_eth_ve_pkg::*;
//top module for starting the UVM flow
module amiq_eth_ve_top;
initial begin
run_test();
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR2_BLACKBOX_V
/**
* nor2: 2-input NOR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2_BLACKBOX_V
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_errorStatus (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iop_fpga.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module iop_fpga(reset_l, gclk,
cpu_id,
spc_pcx_req_pq,
spc_pcx_atom_pq,
spc_pcx_data_pa,
pcx_spc_grant_px,
cpx_spc_data_rdy_cx2,
cpx_spc_data_cx2
);
output [4:0] spc_pcx_req_pq;
output spc_pcx_atom_pq;
output [123:0] spc_pcx_data_pa;
input [4:0] pcx_spc_grant_px;
input cpx_spc_data_rdy_cx2;
input [144:0] cpx_spc_data_cx2;
input reset_l;
input gclk;
input [1:0] cpu_id;
parameter C_EXT_RESET_HIGH = 0;
// WIRE Definitions for unused outputs
wire spc_sscan_so;
wire spc_scanout0;
wire spc_scanout1;
wire tst_ctu_mbist_done;
wire tst_ctu_mbist_fail;
wire spc_efc_ifuse_data;
wire spc_efc_dfuse_data;
// WIRE Definitions for constraint
wire [3:0] const_cpuid;
wire [7:0] const_maskid = 8'h20;
wire ctu_tck = 1'b0;
wire ctu_sscan_se = 1'b0;
wire ctu_sscan_snap = 1'b0;
wire [3:0] ctu_sscan_tid = 4'h1;
wire ctu_tst_mbist_enable = 1'b0;
wire efc_spc_fuse_clk1 = 1'b0;
wire efc_spc_fuse_clk2 = 1'b0;
wire efc_spc_ifuse_ashift = 1'b0;
wire efc_spc_ifuse_dshift = 1'b0;
wire efc_spc_ifuse_data = 1'b0;
wire efc_spc_dfuse_ashift = 1'b0;
wire efc_spc_dfuse_dshift = 1'b0;
wire efc_spc_dfuse_data = 1'b0;
wire ctu_tst_macrotest = 1'b0;
wire ctu_tst_scan_disable = 1'b0;
wire ctu_tst_short_chain = 1'b0;
wire global_shift_enable = 1'b0;
wire ctu_tst_scanmode = 1'b0;
wire spc_scanin0 = 1'b0;
wire spc_scanin1 = 1'b0;
// Reset Related Signals
wire cluster_cken;
wire cmp_grst_l;
wire cmp_arst_l;
wire ctu_tst_pre_grst_l;
wire adbginit_l;
wire gdbginit_l;
reg reset_l_sync;
wire reset_l_int;
reg sync;
// CPU ID
assign const_cpuid = {2'b00, cpu_id};
// Reset Logic
assign cmp_arst_l = reset_l_int;
assign adbginit_l = reset_l_int;
reg [7:0] reset_delay;
// Synchronize the incoming reset net into the gclk domain
always @(posedge gclk) begin
{reset_l_sync, sync} <= {sync, reset_l};
end
assign reset_l_int = C_EXT_RESET_HIGH ? ~reset_l_sync : reset_l_sync;
always @(posedge gclk) begin
if(~reset_l_int) begin
reset_delay <= 8'b0;
end else
if(reset_delay != 8'hff)
reset_delay <= reset_delay + 8'b1;
end
assign cluster_cken = (reset_delay > 8'd20) ? 1'b1 : 1'b0;
assign ctu_tst_pre_grst_l = (reset_delay > 8'd60) ? 1'b1 : 1'b0;
assign gdbginit_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
assign cmp_grst_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
sparc sparc0 (
.spc_pcx_req_pq (spc_pcx_req_pq),
.spc_pcx_atom_pq (spc_pcx_atom_pq),
.spc_pcx_data_pa (spc_pcx_data_pa),
.spc_sscan_so (spc_sscan_so),
.spc_scanout0 (spc_scanout0),
.spc_scanout1 (spc_scanout1),
.tst_ctu_mbist_done (tst_ctu_mbist_done),
.tst_ctu_mbist_fail (tst_ctu_mbist_fail),
.spc_efc_ifuse_data (spc_efc_ifuse_data),
.spc_efc_dfuse_data (spc_efc_dfuse_data),
.pcx_spc_grant_px (pcx_spc_grant_px),
.cpx_spc_data_rdy_cx2 (cpx_spc_data_rdy_cx2),
.cpx_spc_data_cx2 (cpx_spc_data_cx2),
.const_cpuid (const_cpuid),
.const_maskid (const_maskid),
.ctu_tck (ctu_tck),
.ctu_sscan_se (ctu_sscan_se),
.ctu_sscan_snap (ctu_sscan_snap),
.ctu_sscan_tid (ctu_sscan_tid),
.ctu_tst_mbist_enable (ctu_tst_mbist_enable),
.efc_spc_fuse_clk1 (efc_spc_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc_fuse_clk2),
.efc_spc_ifuse_ashift (efc_spc_ifuse_ashift),
.efc_spc_ifuse_dshift (efc_spc_ifuse_dshift),
.efc_spc_ifuse_data (efc_spc_ifuse_data),
.efc_spc_dfuse_ashift (efc_spc_dfuse_ashift),
.efc_spc_dfuse_dshift (efc_spc_dfuse_dshift),
.efc_spc_dfuse_data (efc_spc_dfuse_data),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (spc_scanin0),
.spc_scanin1 (spc_scanin1),
.cluster_cken (cluster_cken),
.gclk (gclk),
.cmp_grst_l (cmp_grst_l),
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_TB_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_TB_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap.v"
module top();
// Inputs are registered
reg A;
reg VPWRIN;
reg VPWR;
reg VGND;
reg VPB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
VPWRIN = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VPWRIN = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VPB = 1'b1;
#180 VPWR = 1'b1;
#200 VPWRIN = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VPB = 1'b0;
#280 VPWR = 1'b0;
#300 VPWRIN = 1'b0;
#320 VPWRIN = 1'b1;
#340 VPWR = 1'b1;
#360 VPB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWRIN = 1'bx;
#440 VPWR = 1'bx;
#460 VPB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap dut (.A(A), .VPWRIN(VPWRIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_TB_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:51:26 09/02/2013
// Design Name: siete_segmentos_principal
// Module Name: C:/Users/Fabian/Documents/Taller Diseno/Xilinx/Lab1/sietesegmentos/pruebaalonso.v
// Project Name: sietesegmentos
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: siete_segmentos_principal
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module pruebaalonso;
// Inputs
reg bitA;
reg bitB;
reg bitC;
reg bitD;
reg en1;
reg en2;
reg en3;
reg en4;
// Outputs
wire seg_a;
wire seg_b;
wire seg_c;
wire seg_d;
wire seg_e;
wire seg_f;
wire seg_g;
wire s_seg1;
wire s_seg2;
wire s_seg3;
wire s_seg4;
// Instantiate the Unit Under Test (UUT)
siete_segmentos_principal uut (
.bitA(bitA),
.bitB(bitB),
.bitC(bitC),
.bitD(bitD),
.en1(en1),
.en2(en2),
.en3(en3),
.en4(en4),
.seg_a(seg_a),
.seg_b(seg_b),
.seg_c(seg_c),
.seg_d(seg_d),
.seg_e(seg_e),
.seg_f(seg_f),
.seg_g(seg_g),
.s_seg1(s_seg1),
.s_seg2(s_seg2),
.s_seg3(s_seg3),
.s_seg4(s_seg4)
);
initial begin
// Initialize Inputs
bitA = 0;
bitB = 0;
bitC = 0;
bitD = 0;
en1 = 0;
en2 = 0;
en3 = 0;
en4 = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
bitD = 1;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ad
//
// Generated
// by: wig
// on: Mon Oct 24 15:17:36 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ad.v,v 1.2 2005/10/24 15:50:24 wig Exp $
// $Date: 2005/10/24 15:50:24 $
// $Log: ent_ad.v,v $
// Revision 1.2 2005/10/24 15:50:24 wig
// added 'reg detection to ::out column
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.64 2005/10/20 17:28:26 lutscher Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ad
//
// No `defines in this module
module ent_ad
//
// Generated module inst_ad
//
(
port_ad_2 // Use internally test2, no port generated
);
// Generated Module Outputs:
output port_ad_2;
// Generated Wires:
reg port_ad_2;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ad
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ms__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire SET_B_delayed ;
wire RESET_B_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
wire cond_D ;
wire cond_SCD ;
wire cond_SCE ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_ms__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, mux_out, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
assign cond_D = ( ( SCE_delayed === 1'b0 ) && condb );
assign cond_SCD = ( ( SCE_delayed === 1'b1 ) && condb );
assign cond_SCE = ( ( D_delayed !== SCD_delayed ) && condb );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_BEHAVIORAL_V |
// -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer with Packet FIFO
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_r_upsizer_pktfifo #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_ID_WIDTH = 1,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter C_CLK_CONV = 1'b0,
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1,
// Log2 of Up-Sizing ratio for data.
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Global Signals
input wire S_AXI_ACLK,
input wire M_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire M_AXI_ARESETN,
// Command Interface
input wire [C_AXI_ADDR_WIDTH-1:0] cmd_si_addr,
input wire [C_AXI_ID_WIDTH-1:0] cmd_si_id,
input wire [8-1:0] cmd_si_len,
input wire [3-1:0] cmd_si_size,
input wire [2-1:0] cmd_si_burst,
output wire cmd_ready,
// Slave Interface Write Address Port
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [8-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [4-1:0] S_AXI_ARREGION,
input wire [4-1:0] S_AXI_ARQOS,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [8-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [4-1:0] M_AXI_ARREGION,
output wire [4-1:0] M_AXI_ARQOS,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
input wire SAMPLE_CYCLE_EARLY,
input wire SAMPLE_CYCLE
);
assign cmd_ready = 1'b1;
localparam integer P_SI_BYTES = C_S_AXI_DATA_WIDTH / 8;
localparam integer P_MI_BYTES = C_M_AXI_DATA_WIDTH / 8;
localparam integer P_MAX_BYTES = 1024 / 8;
localparam integer P_SI_SIZE = f_ceil_log2(P_SI_BYTES);
localparam integer P_MI_SIZE = f_ceil_log2(P_MI_BYTES);
localparam integer P_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer P_RATIO_LOG = f_ceil_log2(P_RATIO);
localparam integer P_NUM_BUF = (P_RATIO == 2) ? 4 : 8;
localparam integer P_BUF_LIMIT = P_NUM_BUF - 1;
localparam integer P_NUM_BUF_LOG = f_ceil_log2(P_NUM_BUF);
localparam integer P_M_RBUFFER_DEPTH = 512;
localparam integer P_M_RBUFFER_DEPTH_LOG = 9;
localparam integer P_S_RBUFFER_DEPTH = P_M_RBUFFER_DEPTH * P_RATIO;
localparam integer P_S_RBUFFER_DEPTH_LOG = f_ceil_log2(P_S_RBUFFER_DEPTH);
localparam integer P_M_RBUFFER_WORDS = P_M_RBUFFER_DEPTH / P_NUM_BUF;
localparam integer P_M_RBUFFER_WORDS_LOG = f_ceil_log2(P_M_RBUFFER_WORDS);
localparam integer P_S_RBUFFER_WORDS = P_M_RBUFFER_WORDS * P_RATIO;
localparam integer P_S_RBUFFER_WORDS_LOG = f_ceil_log2(P_S_RBUFFER_WORDS);
localparam integer P_M_RBUFFER_BYTES = P_M_RBUFFER_WORDS * P_MI_BYTES;
localparam integer P_M_RBUFFER_BYTES_LOG = f_ceil_log2(P_M_RBUFFER_BYTES);
localparam integer P_MAX_RBUFFER_BYTES_LOG = f_ceil_log2((P_M_RBUFFER_DEPTH / 4) * P_MAX_BYTES);
localparam [1:0] P_INCR = 2'b01, P_WRAP = 2'b10, P_FIXED = 2'b00;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_NUM_RAMB = C_M_AXI_DATA_WIDTH / 32;
localparam integer P_S_RAMB_WIDTH = C_S_AXI_DATA_WIDTH / P_NUM_RAMB;
localparam integer P_S_RAMB_PWIDTH = (P_S_RAMB_WIDTH < 8) ? P_S_RAMB_WIDTH : ((P_SI_BYTES * 9) / P_NUM_RAMB);
localparam integer P_S_CMD_WIDTH = P_MI_SIZE+4 + C_AXI_ID_WIDTH + 4 + 3 + 8 + 3 + 2;
localparam integer P_M_CMD_WIDTH = P_MI_SIZE+4 + C_AXI_ID_WIDTH + 8 + 3 + 2;
localparam integer P_ARFIFO_WIDTH = 29 + C_AXI_ADDR_WIDTH + C_AXI_ID_WIDTH;
localparam integer P_COMMON_CLOCK = (C_CLK_CONV & C_AXI_IS_ACLK_ASYNC) ? 0 : 1;
genvar i;
genvar j;
reg S_AXI_ARREADY_i;
reg M_AXI_RREADY_i;
reg M_AXI_ARVALID_i;
wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR_i;
wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID_i;
wire [7:0] M_AXI_ARLEN_i;
wire [2:0] M_AXI_ARSIZE_i;
wire [1:0] M_AXI_ARBURST_i;
wire M_AXI_ARLOCK_i;
wire ar_push;
wire ar_fifo_ready;
wire ar_fifo_valid;
wire ar_pop;
wire s_rbuf_en;
wire [P_NUM_RAMB-1:0] m_rbuf_en;
reg [P_NUM_BUF_LOG-1:0] s_buf;
reg [P_NUM_BUF_LOG-1:0] m_buf;
reg [P_NUM_BUF_LOG-1:0] buf_cnt;
wire buf_limit;
reg [7:0] s_rcnt;
wire [P_NUM_RAMB*16-1 : 0] s_rdata ;
wire [C_M_AXI_DATA_WIDTH-1 : 0] m_rdata ;
reg [1:0] s_rburst;
reg [2:0] s_rsize;
reg [3:0] s_wrap_cnt;
reg s_rvalid;
reg s_rvalid_d1;
reg s_rvalid_d2;
reg first_rvalid_d1;
reg s_rlast;
reg s_rlast_d1;
reg s_rlast_d2;
wire [1:0] s_rresp;
wire [3:0] s_rresp_i;
wire [1:0] m_rresp;
wire [3:0] m_rresp_i;
reg [1:0] s_rresp_reg;
reg [1:0] m_rresp_reg;
reg [1:0] s_rresp_d1;
reg [1:0] s_rresp_d2;
reg [1:0] s_rresp_first;
reg [1:0] m_rburst;
reg [2:0] m_rsize;
reg [3:0] m_wrap_cnt;
wire s_cmd_push;
wire s_cmd_pop;
wire s_cmd_empty;
wire s_cmd_full;
wire m_cmd_push;
wire m_cmd_pop;
wire m_cmd_empty;
wire m_cmd_full;
reg m_cmd_valid;
wire [P_S_CMD_WIDTH-1 : 0] s_ar_cmd;
wire [P_S_CMD_WIDTH-1 : 0] s_r_cmd;
wire [P_M_CMD_WIDTH-1 : 0] m_ar_cmd;
wire [P_M_CMD_WIDTH-1 : 0] m_r_cmd;
wire [P_MI_SIZE+4-1:0] s_cmd_addr;
wire [C_AXI_ID_WIDTH-1:0] s_cmd_id;
reg [C_AXI_ID_WIDTH-1:0] s_id_reg;
reg [C_AXI_ID_WIDTH-1:0] s_id_d1;
reg [C_AXI_ID_WIDTH-1:0] s_id_d2;
wire [3:0] s_cmd_conv_len;
reg [3:0] s_conv_len;
wire [2:0] s_cmd_conv_size;
reg [2:0] s_conv_size;
wire [7:0] s_cmd_len;
wire [2:0] s_cmd_size;
wire [1:0] s_cmd_burst;
wire [P_MI_SIZE+4-1:0] m_cmd_addr;
wire [C_AXI_ID_WIDTH-1:0] m_cmd_id;
wire [7:0] m_cmd_len;
wire [2:0] m_cmd_size;
wire [1:0] m_cmd_burst;
wire m_transfer;
wire rresp_fifo_push;
wire rresp_fifo_pop;
wire rresp_fifo_empty;
wire rresp_fifo_full;
reg rresp_wrap;
wire rresp_reuse;
reg s_rresp_fifo_stall;
reg m_rresp_fifo_stall;
wire s_eol;
reg [P_M_RBUFFER_BYTES_LOG-1:0] s_raddr;
reg [P_M_RBUFFER_BYTES_LOG-1:0] m_raddr;
wire [P_M_RBUFFER_BYTES_LOG-1:0] m_raddr_incr;
reg [P_M_RBUFFER_BYTES_LOG-1:0] s_wrap_addr;
reg [P_M_RBUFFER_BYTES_LOG-1:0] m_wrap_addr;
wire [13:0] s_rbuf_addr;
wire [13:0] m_rbuf_addr;
wire [3:0] m_rbuf_we;
reg large_incr_last;
reg [3:0] large_incr_mask;
wire m_aclk;
wire m_aresetn;
wire s_aresetn;
wire ar_fifo_s_aclk;
wire ar_fifo_m_aclk;
wire ar_fifo_aresetn;
wire s_fifo_rst;
wire m_fifo_rst;
wire rresp_fifo_clk;
wire rresp_fifo_wrclk;
wire rresp_fifo_rdclk;
wire rresp_fifo_rst;
wire s_sample_cycle;
wire s_sample_cycle_early;
wire m_sample_cycle;
wire m_sample_cycle_early;
wire fast_aclk;
reg reset_r;
reg s_reset_r;
reg m_reset_r;
reg fast_aresetn_r;
reg fast_reset_r;
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// RAMB SI-side port address
function [13:0] f_s_rbuf_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [1:0] burst,
input [P_NUM_BUF_LOG-1:0] s_buf
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] sparse_addr;
begin
if (burst == P_FIXED) begin
sparse_addr = addr;
end else begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 3], addr_i[0:0], addr_i[2:0]};
default: sparse_addr = addr_i;
endcase
4: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 4], addr_i[1:0], addr_i[3:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 4], addr_i[1:1], addr_i[3:0]};
default: sparse_addr = addr_i;
endcase
5: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 5], addr_i[2:0], addr_i[4:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 5], addr_i[2:1], addr_i[4:0]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 5], addr_i[2:2], addr_i[4:0]};
default: sparse_addr = addr_i;
endcase
6: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:1], addr_i[5:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:1], addr_i[5:0]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:2], addr_i[5:0]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 6], addr_i[3:3], addr_i[5:0]};
default: sparse_addr = addr_i;
endcase
7: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:2], addr_i[6:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:2], addr_i[6:0]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:2], addr_i[6:0]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:3], addr_i[6:0]};
3'h4: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : 7], addr_i[4:4], addr_i[6:0]};
default: sparse_addr = addr_i;
endcase
endcase
end
f_s_rbuf_addr = {s_buf, {14-P_NUM_BUF_LOG{1'b0}}};
f_s_rbuf_addr[13-P_NUM_BUF_LOG : 5-P_RATIO_LOG] = sparse_addr[P_SI_SIZE +: 9+P_RATIO_LOG-P_NUM_BUF_LOG];
end
endfunction
// RAMB MI-side port address
function [13:0] f_m_rbuf_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [1:0] burst,
input [P_NUM_BUF_LOG-1:0] m_buf
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] sparse_addr;
begin
addr_i = addr;
if (burst == P_FIXED) begin
sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
end else begin
case (P_MI_SIZE)
3: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[0:0]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
4: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[1:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[1:1]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
5: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[2:0]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[2:1]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[2:2]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
6: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:1]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:1]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:2]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[3:3]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
7: case (size)
3'h0: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:2]};
3'h1: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:2]};
3'h2: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:2]};
3'h3: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:3]};
3'h4: sparse_addr = {addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE], addr_i[4:4]};
default: sparse_addr = addr_i[P_MAX_RBUFFER_BYTES_LOG-1 : P_MI_SIZE];
endcase
endcase
end
f_m_rbuf_addr = {m_buf, sparse_addr[0 +: 9-P_NUM_BUF_LOG], 5'b0};
end
endfunction
// RAMB MI-side port write-enables
function [3:0] f_m_rbuf_we
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h2: f_m_rbuf_we = addr_i[2] ? 4'b1100 : 4'b0011;
3'h3: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[2:1];
endcase
4: case (size)
3'h3: f_m_rbuf_we = addr_i[3] ? 4'b1100 : 4'b0011;
3'h4: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[3:2];
endcase
5: case (size)
3'h4: f_m_rbuf_we = addr_i[4] ? 4'b1100 : 4'b0011;
3'h5: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[4:3];
endcase
6: case (size)
3'h5: f_m_rbuf_we = addr_i[5] ? 4'b1100 : 4'b0011;
3'h6: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[5:4];
endcase
7: case (size)
3'h6: f_m_rbuf_we = addr_i[6] ? 4'b1100 : 4'b0011;
3'h7: f_m_rbuf_we = 4'b1111;
default: f_m_rbuf_we = 4'b0001 << addr_i[6:5];
endcase
endcase
end
endfunction
// RAMB MI-side write-enable mask for last beat of long unaligned INCR burst wrapping to 1st buffer addr.
// Only applies to full-size SI bursts when RATIO = 2 or 4.
function [3:0] f_large_incr_mask
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
reg [3:0] result;
begin
addr_i = addr;
result = 4'b1111;
case (P_MI_SIZE)
3: result = 4'b0011;
4: case (P_SI_SIZE)
3'h3: result = 4'b0011;
3'h2: case (addr_i[3:2])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
5: case (P_SI_SIZE)
3'h4: result = 4'b0011;
3'h3: case (addr_i[4:3])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
6: case (P_SI_SIZE)
3'h5: result = 4'b0011;
3'h4: case (addr_i[5:4])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
7: case (P_SI_SIZE)
3'h6: result = 4'b0011;
3'h5: case (addr_i[6:5])
2'b01: result = 4'b0001;
2'b10: result = 4'b0011;
2'b11: result = 4'b0111;
endcase
endcase
endcase
f_large_incr_mask = result;
end
endfunction
// RAMB MI-side port-enables
function [P_NUM_RAMB-1:0] f_m_rbuf_en
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size
);
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
6: case (size)
3'h0: f_m_rbuf_en = addr_i[0] ? 16'hFF00 : 16'h00FF;
default: f_m_rbuf_en = 16'hFFFF;
endcase
7: case (size)
3'h0: case (addr_i[1:0])
2'b00: f_m_rbuf_en = 32'h000000FF;
2'b01: f_m_rbuf_en = 32'h0000FF00;
2'b10: f_m_rbuf_en = 32'h00FF0000;
2'b11: f_m_rbuf_en = 32'hFF000000;
endcase
3'h1: f_m_rbuf_en = addr_i[1] ? 32'hFFFF0000 : 32'h0000FFFF;
default: f_m_rbuf_en = 32'hFFFFFFFF;
endcase
default: f_m_rbuf_en = {P_NUM_RAMB{1'b1}};
endcase
end
endfunction
// SI-side buffer line fault detection
function f_s_eol
(
input [P_MI_SIZE-1:0] addr,
input [2:0] s_size,
input [2:0] m_size
);
reg [7-1:0] addr_i;
begin
addr_i = addr;
if (m_size == P_MI_SIZE) begin
case (P_MI_SIZE)
3: case (s_size)
3'h0: f_s_eol = &(addr_i[2:0]);
3'h1: f_s_eol = &(addr_i[2:1]);
3'h2: f_s_eol = &(addr_i[2:2]);
endcase
4: case (s_size)
3'h0: f_s_eol = &(addr_i[3:0]);
3'h1: f_s_eol = &(addr_i[3:1]);
3'h2: f_s_eol = &(addr_i[3:2]);
3'h3: f_s_eol = &(addr_i[3:3]);
endcase
5: case (s_size)
3'h0: f_s_eol = &(addr_i[4:0]);
3'h1: f_s_eol = &(addr_i[4:1]);
3'h2: f_s_eol = &(addr_i[4:2]);
3'h3: f_s_eol = &(addr_i[4:3]);
3'h4: f_s_eol = &(addr_i[4:4]);
endcase
6: case (s_size)
3'h0: f_s_eol = &(addr_i[5:0]);
3'h1: f_s_eol = &(addr_i[5:1]);
3'h2: f_s_eol = &(addr_i[5:2]);
3'h3: f_s_eol = &(addr_i[5:3]);
3'h4: f_s_eol = &(addr_i[5:4]);
3'h5: f_s_eol = &(addr_i[5:5]);
endcase
7: case (s_size)
3'h0: f_s_eol = &(addr_i[6:0]);
3'h1: f_s_eol = &(addr_i[6:1]);
3'h2: f_s_eol = &(addr_i[6:2]);
3'h3: f_s_eol = &(addr_i[6:3]);
3'h4: f_s_eol = &(addr_i[6:4]);
3'h5: f_s_eol = &(addr_i[6:5]);
3'h6: f_s_eol = &(addr_i[6:6]);
endcase
endcase
end else begin
// Assumes that AR transform is either fully-packed (m_size == P_MI_SIZE) or unpacked (m_size == s_size), no intermediate sizes.
f_s_eol = 1'b1;
end
end
endfunction
// Number of SI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_s_wrap_cnt
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
default: start = addr_i[ 2 +: 4];
endcase
3: case (size[1:0])
2'h0: start = addr_i[ 0 +: 4];
2'h1: start = addr_i[ 1 +: 4];
2'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
endcase
f_s_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Number of MI transfers until wrapping (0 = wrap after first transfer; 4'hF = no wrapping)
function [3:0] f_m_wrap_cnt
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [3:0] start;
reg [P_MAX_RBUFFER_BYTES_LOG-1:0] addr_i;
begin
addr_i = addr;
case (P_MI_SIZE)
3: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
default: start = addr_i[ 3 +: 4];
endcase
4: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
default: start = addr_i[ 4 +: 4];
endcase
5: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
default: start = addr_i[ 5 +: 4];
endcase
6: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
default: start = addr_i[ 6 +: 4];
endcase
7: case (size)
3'h0: start = addr_i[ 0 +: 4];
3'h1: start = addr_i[ 1 +: 4];
3'h2: start = addr_i[ 2 +: 4];
3'h3: start = addr_i[ 3 +: 4];
3'h4: start = addr_i[ 4 +: 4];
3'h5: start = addr_i[ 5 +: 4];
3'h6: start = addr_i[ 6 +: 4];
default: start = addr_i[ 7 +: 4];
endcase
endcase
f_m_wrap_cnt = {len[3:1], 1'b1} & ~start;
end
endfunction
// Mask of address bits used to point to first SI wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_s_wrap_mask = {len[3:3], 3'b111 };
3'h1: f_s_wrap_mask = {len[3:2], 3'b110 };
3'h2: f_s_wrap_mask = {len[3:1], 3'b100 };
endcase
4: case (size)
3'h0: f_s_wrap_mask = 4'b1111 ;
3'h1: f_s_wrap_mask = {len[3:3], 4'b1110 };
3'h2: f_s_wrap_mask = {len[3:2], 4'b1100 };
3'h3: f_s_wrap_mask = {len[3:1], 4'b1000 };
endcase
5: case (size)
3'h0: f_s_wrap_mask = 5'b11111 ;
3'h1: f_s_wrap_mask = 5'b11110 ;
3'h2: f_s_wrap_mask = {len[3:3], 5'b11100 };
3'h3: f_s_wrap_mask = {len[3:2], 5'b11000 };
3'h4: f_s_wrap_mask = {len[3:1], 5'b10000 };
endcase
6: case (size)
3'h0: f_s_wrap_mask = 6'b111111 ;
3'h1: f_s_wrap_mask = 6'b111110 ;
3'h2: f_s_wrap_mask = 6'b111100 ;
3'h3: f_s_wrap_mask = {len[3:3], 6'b111000 };
3'h4: f_s_wrap_mask = {len[3:2], 6'b110000 };
3'h5: f_s_wrap_mask = {len[3:1], 6'b100000 };
endcase
7: case (size)
3'h0: f_s_wrap_mask = 7'b1111111 ;
3'h1: f_s_wrap_mask = 7'b1111110 ;
3'h2: f_s_wrap_mask = 7'b1111100 ;
3'h3: f_s_wrap_mask = 7'b1111000 ;
3'h4: f_s_wrap_mask = {len[3:3], 7'b1110000};
3'h5: f_s_wrap_mask = {len[3:2], 7'b1100000};
3'h6: f_s_wrap_mask = {len[3:1], 7'b1000000};
endcase
endcase
end
endfunction
// Mask of address bits used to point to first MI wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_wrap_mask
(
input [2:0] size,
input [7:0] len
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_m_wrap_mask = {len[3:3], 3'b111 };
3'h1: f_m_wrap_mask = {len[3:2], 3'b110 };
3'h2: f_m_wrap_mask = {len[3:1], 3'b100 };
3'h3: f_m_wrap_mask = {len[3:1], 4'b1000 };
endcase
4: case (size)
3'h0: f_m_wrap_mask = 4'b1111 ;
3'h1: f_m_wrap_mask = {len[3:3], 4'b1110 };
3'h2: f_m_wrap_mask = {len[3:2], 4'b1100 };
3'h3: f_m_wrap_mask = {len[3:1], 4'b1000 };
3'h4: f_m_wrap_mask = {len[3:1], 5'b10000 };
endcase
5: case (size)
3'h0: f_m_wrap_mask = 5'b11111 ;
3'h1: f_m_wrap_mask = 5'b11110 ;
3'h2: f_m_wrap_mask = {len[3:3], 5'b11100 };
3'h3: f_m_wrap_mask = {len[3:2], 5'b11000 };
3'h4: f_m_wrap_mask = {len[3:1], 5'b10000 };
3'h5: f_m_wrap_mask = {len[3:1], 6'b100000 };
endcase
6: case (size)
3'h0: f_m_wrap_mask = 6'b111111 ;
3'h1: f_m_wrap_mask = 6'b111110 ;
3'h2: f_m_wrap_mask = 6'b111100 ;
3'h3: f_m_wrap_mask = {len[3:3], 6'b111000 };
3'h4: f_m_wrap_mask = {len[3:2], 6'b110000 };
3'h5: f_m_wrap_mask = {len[3:1], 6'b100000 };
3'h6: f_m_wrap_mask = {len[3:1], 7'b1000000 };
endcase
7: case (size)
3'h0: f_m_wrap_mask = 7'b1111111 ;
3'h1: f_m_wrap_mask = 7'b1111110 ;
3'h2: f_m_wrap_mask = 7'b1111100 ;
3'h3: f_m_wrap_mask = 7'b1111000 ;
3'h4: f_m_wrap_mask = {len[3:3], 7'b1110000 };
3'h5: f_m_wrap_mask = {len[3:2], 7'b1100000 };
3'h6: f_m_wrap_mask = {len[3:1], 7'b1000000 };
3'h7: f_m_wrap_mask = {len[3:1], 8'b10000000};
endcase
endcase
end
endfunction
// Address of SI transfer following wrap
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_wrap_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [P_M_RBUFFER_BYTES_LOG-1:0] mask;
begin
case (P_MI_SIZE)
3: case (size)
3'h0: mask = { ~len[2:1], 1'b0};
3'h1: mask = { ~len[1:1], 2'b0};
default: mask = 3'b0 ;
endcase
4: case (size)
3'h0: mask = { ~len[3:1], 1'b0};
3'h1: mask = { ~len[2:1], 2'b0};
3'h2: mask = { ~len[1:1], 3'b0};
default: mask = 4'b0 ;
endcase
5: case (size)
3'h0: mask = {1'b1 , ~len[3:1], 1'b0};
3'h1: mask = { ~len[3:1], 2'b0};
3'h2: mask = { ~len[2:1], 3'b0};
3'h3: mask = { ~len[1:1], 4'b0};
default: mask = 5'b0 ;
endcase
6: case (size)
3'h0: mask = {2'b11 , ~len[3:1], 1'b0};
3'h1: mask = {1'b1 , ~len[3:1], 2'b0};
3'h2: mask = { ~len[3:1], 3'b0};
3'h3: mask = { ~len[2:1], 4'b0};
3'h4: mask = { ~len[1:1], 5'b0};
default: mask = 6'b0 ;
endcase
7: case (size)
3'h0: mask = {3'b111, ~len[3:1], 1'b0};
3'h1: mask = {2'b11 , ~len[3:1], 2'b0};
3'h2: mask = {1'b1 , ~len[3:1], 3'b0};
3'h3: mask = { ~len[3:1], 4'b0};
3'h4: mask = { ~len[2:1], 5'b0};
3'h5: mask = { ~len[1:1], 6'b0};
default: mask = 7'b0 ;
endcase
endcase
f_s_wrap_addr = addr & mask;
end
endfunction
// Address of MI transfer following wrap
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_wrap_addr
(
input [P_M_RBUFFER_BYTES_LOG-1:0] addr,
input [2:0] size,
input [7:0] len
);
reg [P_M_RBUFFER_BYTES_LOG-1:0] mask;
begin
case (P_MI_SIZE)
3: case (size)
3'h0: mask = { ~len[2:1], 1'b0};
3'h1: mask = { ~len[1:1], 2'b0};
default: mask = 3'b0 ;
endcase
4: case (size)
3'h0: mask = { ~len[3:1], 1'b0};
3'h1: mask = { ~len[2:1], 2'b0};
3'h2: mask = { ~len[1:1], 3'b0};
default: mask = 4'b0 ;
endcase
5: case (size)
3'h0: mask = {1'b1 , ~len[3:1], 1'b0};
3'h1: mask = { ~len[3:1], 2'b0};
3'h2: mask = { ~len[2:1], 3'b0};
3'h3: mask = { ~len[1:1], 4'b0};
default: mask = 5'b0 ;
endcase
6: case (size)
3'h0: mask = {2'b11 , ~len[3:1], 1'b0};
3'h1: mask = {1'b1 , ~len[3:1], 2'b0};
3'h2: mask = { ~len[3:1], 3'b0};
3'h3: mask = { ~len[2:1], 4'b0};
3'h4: mask = { ~len[1:1], 5'b0};
default: mask = 6'b0 ;
endcase
7: case (size)
3'h0: mask = {3'b111, ~len[3:1], 1'b0};
3'h1: mask = {2'b11 , ~len[3:1], 2'b0};
3'h2: mask = {1'b1 , ~len[3:1], 3'b0};
3'h3: mask = { ~len[3:1], 4'b0};
3'h4: mask = { ~len[2:1], 5'b0};
3'h5: mask = { ~len[1:1], 6'b0};
default: mask = 7'b0 ;
endcase
endcase
f_m_wrap_addr = addr & mask;
end
endfunction
// Mask of address bits used to point to first SI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_size_mask
(
input [2:0] size
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_s_size_mask = 3'b111;
3'h1: f_s_size_mask = 3'b110;
3'h2: f_s_size_mask = 3'b100;
endcase
4: case (size)
3'h0: f_s_size_mask = 4'b1111;
3'h1: f_s_size_mask = 4'b1110;
3'h2: f_s_size_mask = 4'b1100;
3'h3: f_s_size_mask = 4'b1000;
endcase
5: case (size)
3'h0: f_s_size_mask = 5'b11111;
3'h1: f_s_size_mask = 5'b11110;
3'h2: f_s_size_mask = 5'b11100;
3'h3: f_s_size_mask = 5'b11000;
3'h4: f_s_size_mask = 5'b10000;
endcase
6: case (size)
3'h0: f_s_size_mask = 6'b111111;
3'h1: f_s_size_mask = 6'b111110;
3'h2: f_s_size_mask = 6'b111100;
3'h3: f_s_size_mask = 6'b111000;
3'h4: f_s_size_mask = 6'b110000;
3'h5: f_s_size_mask = 6'b100000;
endcase
7: case (size)
3'h0: f_s_size_mask = 7'b1111111;
3'h1: f_s_size_mask = 7'b1111110;
3'h2: f_s_size_mask = 7'b1111100;
3'h3: f_s_size_mask = 7'b1111000;
3'h4: f_s_size_mask = 7'b1110000;
3'h5: f_s_size_mask = 7'b1100000;
3'h6: f_s_size_mask = 7'b1000000;
endcase
endcase
end
endfunction
// Mask of address bits used to point to first MI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_size_mask
(
input [2:0] size
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_m_size_mask = 3'b111;
3'h1: f_m_size_mask = 3'b110;
3'h2: f_m_size_mask = 3'b100;
3'h3: f_m_size_mask = 3'b000;
endcase
4: case (size)
3'h0: f_m_size_mask = 4'b1111;
3'h1: f_m_size_mask = 4'b1110;
3'h2: f_m_size_mask = 4'b1100;
3'h3: f_m_size_mask = 4'b1000;
3'h4: f_m_size_mask = 4'b0000;
endcase
5: case (size)
3'h0: f_m_size_mask = 5'b11111;
3'h1: f_m_size_mask = 5'b11110;
3'h2: f_m_size_mask = 5'b11100;
3'h3: f_m_size_mask = 5'b11000;
3'h4: f_m_size_mask = 5'b10000;
3'h5: f_m_size_mask = 5'b00000;
endcase
6: case (size)
3'h0: f_m_size_mask = 6'b111111;
3'h1: f_m_size_mask = 6'b111110;
3'h2: f_m_size_mask = 6'b111100;
3'h3: f_m_size_mask = 6'b111000;
3'h4: f_m_size_mask = 6'b110000;
3'h5: f_m_size_mask = 6'b100000;
3'h6: f_m_size_mask = 6'b000000;
endcase
7: case (size)
3'h0: f_m_size_mask = 7'b1111111;
3'h1: f_m_size_mask = 7'b1111110;
3'h2: f_m_size_mask = 7'b1111100;
3'h3: f_m_size_mask = 7'b1111000;
3'h4: f_m_size_mask = 7'b1110000;
3'h5: f_m_size_mask = 7'b1100000;
3'h6: f_m_size_mask = 7'b1000000;
3'h7: f_m_size_mask = 7'b0000000;
endcase
endcase
end
endfunction
// Address increment for SI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_s_size_incr
(
input [2:0] size
);
begin
case (P_SI_SIZE)
2: case (size[1:0])
2'h0: f_s_size_incr = 4'b001;
2'h1: f_s_size_incr = 4'b010;
2'h2: f_s_size_incr = 4'b100;
endcase
3: case (size[1:0])
2'h0: f_s_size_incr = 4'b0001;
2'h1: f_s_size_incr = 4'b0010;
2'h2: f_s_size_incr = 4'b0100;
2'h3: f_s_size_incr = 4'b1000;
endcase
4: case (size)
3'h0: f_s_size_incr = 5'b00001;
3'h1: f_s_size_incr = 5'b00010;
3'h2: f_s_size_incr = 5'b00100;
3'h3: f_s_size_incr = 5'b01000;
3'h4: f_s_size_incr = 5'b10000;
endcase
5: case (size)
3'h0: f_s_size_incr = 6'b000001;
3'h1: f_s_size_incr = 6'b000010;
3'h2: f_s_size_incr = 6'b000100;
3'h3: f_s_size_incr = 6'b001000;
3'h4: f_s_size_incr = 6'b010000;
3'h5: f_s_size_incr = 6'b100000;
endcase
6: case (size)
3'h0: f_s_size_incr = 7'b0000001;
3'h1: f_s_size_incr = 7'b0000010;
3'h2: f_s_size_incr = 7'b0000100;
3'h3: f_s_size_incr = 7'b0001000;
3'h4: f_s_size_incr = 7'b0010000;
3'h5: f_s_size_incr = 7'b0100000;
3'h6: f_s_size_incr = 7'b1000000;
endcase
endcase
end
endfunction
// Address increment for MI non-wrap transfer.
function [P_M_RBUFFER_BYTES_LOG-1:0] f_m_size_incr
(
input [2:0] size
);
begin
case (P_MI_SIZE)
3: case (size)
3'h0: f_m_size_incr = 4'b0001;
3'h1: f_m_size_incr = 4'b0010;
3'h2: f_m_size_incr = 4'b0100;
3'h3: f_m_size_incr = 4'b1000;
endcase
4: case (size)
3'h0: f_m_size_incr = 5'b00001;
3'h1: f_m_size_incr = 5'b00010;
3'h2: f_m_size_incr = 5'b00100;
3'h3: f_m_size_incr = 5'b01000;
3'h4: f_m_size_incr = 5'b10000;
endcase
5: case (size)
3'h0: f_m_size_incr = 6'b000001;
3'h1: f_m_size_incr = 6'b000010;
3'h2: f_m_size_incr = 6'b000100;
3'h3: f_m_size_incr = 6'b001000;
3'h4: f_m_size_incr = 6'b010000;
3'h5: f_m_size_incr = 6'b100000;
endcase
6: case (size)
3'h0: f_m_size_incr = 7'b0000001;
3'h1: f_m_size_incr = 7'b0000010;
3'h2: f_m_size_incr = 7'b0000100;
3'h3: f_m_size_incr = 7'b0001000;
3'h4: f_m_size_incr = 7'b0010000;
3'h5: f_m_size_incr = 7'b0100000;
3'h6: f_m_size_incr = 7'b1000000;
endcase
7: case (size)
3'h0: f_m_size_incr = 8'b00000001;
3'h1: f_m_size_incr = 8'b00000010;
3'h2: f_m_size_incr = 8'b00000100;
3'h3: f_m_size_incr = 8'b00001000;
3'h4: f_m_size_incr = 8'b00010000;
3'h5: f_m_size_incr = 8'b00100000;
3'h6: f_m_size_incr = 8'b01000000;
3'h7: f_m_size_incr = 8'b10000000;
endcase
endcase
end
endfunction
generate
if (C_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = M_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign ar_fifo_s_aclk = S_AXI_ACLK;
assign ar_fifo_m_aclk = M_AXI_ACLK;
assign ar_fifo_aresetn = S_AXI_ARESETN & M_AXI_ARESETN;
assign s_fifo_rst = ~S_AXI_ARESETN;
assign m_fifo_rst = ~M_AXI_ARESETN;
assign rresp_fifo_clk = 1'b0;
assign rresp_fifo_wrclk = M_AXI_ACLK;
assign rresp_fifo_rdclk = S_AXI_ACLK;
assign rresp_fifo_rst = ~S_AXI_ARESETN | ~M_AXI_ARESETN;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
end else begin : gen_sync_conv
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = M_AXI_ACLK;
end else begin : gen_fastclk_si
assign fast_aclk = S_AXI_ACLK;
end
assign m_aclk = M_AXI_ACLK;
assign m_aresetn = fast_aresetn_r;
assign s_aresetn = fast_aresetn_r;
assign ar_fifo_s_aclk = fast_aclk;
assign ar_fifo_m_aclk = 1'b0;
assign ar_fifo_aresetn = fast_aresetn_r;
assign s_fifo_rst = fast_reset_r;
assign m_fifo_rst = fast_reset_r;
assign rresp_fifo_clk = fast_aclk;
assign rresp_fifo_wrclk = 1'b0;
assign rresp_fifo_rdclk = 1'b0;
assign rresp_fifo_rst = fast_reset_r;
assign s_sample_cycle_early = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE_EARLY;
assign s_sample_cycle = P_SI_LT_MI ? 1'b1 : SAMPLE_CYCLE;
assign m_sample_cycle_early = P_SI_LT_MI ? SAMPLE_CYCLE_EARLY : 1'b1;
assign m_sample_cycle = P_SI_LT_MI ? SAMPLE_CYCLE : 1'b1;
always @(posedge fast_aclk) begin
if (~S_AXI_ARESETN | ~M_AXI_ARESETN) begin
fast_aresetn_r <= 1'b0;
fast_reset_r <= 1'b1;
end else if (S_AXI_ARESETN & M_AXI_ARESETN & SAMPLE_CYCLE_EARLY) begin
fast_aresetn_r <= 1'b1;
fast_reset_r <= 1'b0;
end
end
end
end else begin : gen_no_clk_conv
assign m_aclk = S_AXI_ACLK;
assign m_aresetn = S_AXI_ARESETN;
assign s_aresetn = S_AXI_ARESETN;
assign ar_fifo_s_aclk = S_AXI_ACLK;
assign ar_fifo_m_aclk = 1'b0;
assign ar_fifo_aresetn = S_AXI_ARESETN;
assign s_fifo_rst = reset_r;
assign m_fifo_rst = reset_r;
assign rresp_fifo_clk = S_AXI_ACLK;
assign rresp_fifo_wrclk = 1'b0;
assign rresp_fifo_rdclk = 1'b0;
assign rresp_fifo_rst = reset_r;
assign fast_aclk = S_AXI_ACLK;
assign s_sample_cycle_early = 1'b1;
assign s_sample_cycle = 1'b1;
assign m_sample_cycle_early = 1'b1;
assign m_sample_cycle = 1'b1;
always @(posedge S_AXI_ACLK) begin
reset_r <= ~S_AXI_ARESETN;
end
end
for (i=0; i<P_NUM_RAMB; i=i+1) begin : gen_rdata
for (j=0; j<32; j=j+1) begin : gen_m_rdata
assign m_rdata[i*32+j] = M_AXI_RDATA[j*P_NUM_RAMB+i];
end
for (j=0; j<P_S_RAMB_WIDTH; j=j+1) begin : gen_s_rdata
assign S_AXI_RDATA[j*P_NUM_RAMB+i] = s_rdata[i*16+j];
end
end // gen_rdata
assign S_AXI_ARREADY = S_AXI_ARREADY_i;
assign S_AXI_RVALID = s_rvalid_d2;
assign S_AXI_RRESP = s_rresp_d2;
assign S_AXI_RLAST = s_rlast_d2;
assign S_AXI_RID = s_id_d2;
assign s_rbuf_en = ~s_rvalid_d2 | S_AXI_RREADY;
assign buf_limit = buf_cnt == P_BUF_LIMIT;
assign s_cmd_pop = (s_rbuf_en | ~s_rvalid) & (s_rcnt == 0) & ~s_cmd_empty & ~rresp_fifo_empty & ~s_rresp_fifo_stall;
assign s_eol = f_s_eol(s_raddr, s_rsize, s_conv_size) | (s_rburst == P_FIXED);
assign rresp_fifo_pop = (s_rbuf_en | ~s_rvalid) & (((s_rcnt == 0) ? ~s_cmd_empty : (s_eol & ~rresp_wrap)) | s_rresp_fifo_stall) &
~rresp_fifo_empty & m_sample_cycle; // Sample strobe when RRESP FIFO is on faster M_AXI_ACLK.
assign rresp_reuse = (s_rbuf_en | ~s_rvalid) & s_eol & rresp_wrap;
assign ar_push = S_AXI_ARVALID & S_AXI_ARREADY_i & m_sample_cycle; // Sample strobe when AR FIFO is on faster M_AXI_ACLK.
assign s_cmd_push = S_AXI_ARVALID & S_AXI_ARREADY_i;
assign s_ar_cmd = {cmd_si_addr[0 +: P_MI_SIZE+4], cmd_si_id, S_AXI_ARLEN[3:0], S_AXI_ARSIZE, cmd_si_len, cmd_si_size, cmd_si_burst};
assign s_cmd_addr = s_r_cmd[(20+C_AXI_ID_WIDTH) +: P_MI_SIZE+4];
assign s_cmd_id = s_r_cmd[20 +: C_AXI_ID_WIDTH];
assign s_cmd_conv_len = s_r_cmd[16 +: 4];
assign s_cmd_conv_size = s_r_cmd[13 +: 3];
assign s_cmd_len = s_r_cmd[5 +: 8];
assign s_cmd_size = s_r_cmd[2 +: 3];
assign s_cmd_burst = s_r_cmd[0 +: 2];
assign s_rbuf_addr = f_s_rbuf_addr(s_raddr, s_conv_size, s_rburst, s_buf);
assign s_rresp = s_rresp_i[1:0];
always @(posedge S_AXI_ACLK) begin
if (~s_aresetn) begin
S_AXI_ARREADY_i <= 1'b0;
buf_cnt <= 0;
end else begin
if (ar_push) begin
S_AXI_ARREADY_i <= 1'b0;
end else if (ar_fifo_ready & ~s_cmd_full & ~buf_limit) begin
S_AXI_ARREADY_i <= 1'b1; // pre-assert READY
end
if (s_cmd_push & ~s_cmd_pop) begin
buf_cnt <= buf_cnt + 1;
end else if (~s_cmd_push & s_cmd_pop & (buf_cnt != 0)) begin
buf_cnt <= buf_cnt - 1;
end
end
end
always @(posedge S_AXI_ACLK) begin
if (~s_aresetn) begin
s_rvalid <= 1'b0;
s_rvalid_d1 <= 1'b0;
s_rvalid_d2 <= 1'b0;
first_rvalid_d1 <= 1'b0;
s_rlast <= 1'b0;
s_rlast_d1 <= 1'b0;
s_rlast_d2 <= 1'b0;
s_rcnt <= 0;
s_buf <= 0;
rresp_wrap <= 1'b0;
s_rresp_fifo_stall <= 1'b0;
s_rresp_d2 <= 2'b00;
s_id_d2 <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if (s_rbuf_en) begin
s_rvalid_d2 <= s_rvalid_d1;
s_rvalid_d1 <= s_rvalid;
s_rlast_d2 <= s_rlast_d1;
s_rlast_d1 <= s_rlast;
if (first_rvalid_d1) begin
s_rresp_d2 <= s_rresp_d1;
s_id_d2 <= s_id_d1;
end
if (s_rvalid) begin
first_rvalid_d1 <= 1'b1; // forever
end
end
if (s_cmd_pop) begin
s_rlast <= (s_cmd_len == 0);
end else if (s_rvalid & s_rbuf_en & (s_rcnt != 0)) begin
s_rlast <= (s_rcnt == 1);
end
if ((s_rcnt == 0) & ~s_rresp_fifo_stall) begin
if (s_cmd_pop) begin
s_rvalid <= 1'b1;
s_rcnt <= s_cmd_len;
rresp_wrap <= (s_cmd_burst == P_WRAP) & (s_cmd_conv_len == 0);
s_buf <= s_buf + 1;
end else if (s_rbuf_en) begin
s_rvalid <= 1'b0;
end
end else begin
if (s_rvalid & s_rbuf_en) begin
s_rcnt <= s_rcnt - 1;
end
if ((s_eol & ~rresp_wrap) | s_rresp_fifo_stall) begin
if (rresp_fifo_pop) begin
rresp_wrap <= (s_rburst == P_WRAP) && (s_conv_len == 1); // Last rresp pop of wrap burst
s_rvalid <= 1'b1;
s_rresp_fifo_stall <= 1'b0;
end else if (s_rbuf_en) begin
s_rvalid <= 1'b0;
s_rresp_fifo_stall <= 1'b1;
end
end
end
end
end
always @(posedge S_AXI_ACLK) begin
if (s_rbuf_en) begin
s_rresp_d1 <= s_rresp_reg;
s_id_d1 <= s_id_reg;
end
if (s_cmd_pop) begin
if (s_cmd_burst == P_WRAP) begin
s_raddr <= s_cmd_addr & f_s_wrap_mask(s_cmd_size, s_cmd_len);
end else begin
s_raddr <= s_cmd_addr & f_s_size_mask(s_cmd_size);
end
s_rsize <= s_cmd_size;
s_rburst <= s_cmd_burst;
s_id_reg <= s_cmd_id;
s_wrap_cnt <= f_s_wrap_cnt(s_cmd_addr, s_cmd_size, s_cmd_len);
s_wrap_addr <= f_s_wrap_addr(s_cmd_addr, s_cmd_size, s_cmd_len);
s_conv_size <= s_cmd_conv_size;
s_conv_len <= s_cmd_conv_len; // MI len to count wrap beats for rresp reuse.
s_rresp_first <= s_rresp; // Save first beat of wrap burst.
end else if (s_rvalid & s_rbuf_en & (s_rcnt != 0)) begin
if ((s_rburst == P_WRAP) && (s_wrap_cnt == 0)) begin
s_raddr <= s_wrap_addr;
end else if (s_rburst == P_FIXED) begin
s_raddr <= s_raddr + P_MI_BYTES;
end else begin
s_raddr <= s_raddr + f_s_size_incr(s_rsize);
end
s_wrap_cnt <= s_wrap_cnt - 1;
end
if (rresp_fifo_pop) begin
s_rresp_reg <= s_rresp;
if (~s_cmd_pop) begin
s_conv_len <= s_conv_len - 1; // Count rresp pops during wrap burst
end
end else if (rresp_reuse) begin // SI wrap revisits first buffer line; reuse firt rresp.
s_rresp_reg <= s_rresp_first;
end
end
assign M_AXI_ARADDR = M_AXI_ARADDR_i;
assign M_AXI_ARLEN = M_AXI_ARLEN_i;
assign M_AXI_ARSIZE = M_AXI_ARSIZE_i;
assign M_AXI_ARBURST = M_AXI_ARBURST_i;
assign M_AXI_ARLOCK = {1'b0,M_AXI_ARLOCK_i};
assign M_AXI_ARVALID = M_AXI_ARVALID_i;
assign M_AXI_RREADY = M_AXI_RREADY_i;
assign ar_pop = M_AXI_ARVALID_i & M_AXI_ARREADY & s_sample_cycle; // Sample strobe when AR FIFO is on faster S_AXI_ACLK.
assign m_cmd_push = M_AXI_ARVALID_i & M_AXI_ARREADY;
assign m_transfer = M_AXI_RREADY_i & M_AXI_RVALID;
assign rresp_fifo_push = (m_transfer | m_rresp_fifo_stall) & ~rresp_fifo_full & s_sample_cycle; // Sample strobe when RRESP FIFO is on faster S_AXI_ACLK.
assign m_cmd_pop = ((m_transfer & M_AXI_RLAST) | (~m_cmd_valid & ~rresp_fifo_full)) & ~m_cmd_empty;
assign m_rresp = m_rresp_fifo_stall ? m_rresp_reg : M_AXI_RRESP;
assign m_rresp_i = {2'b0, m_rresp};
assign m_ar_cmd = {M_AXI_ARADDR_i[0 +: P_MI_SIZE+4], M_AXI_ARID_i, M_AXI_ARLEN_i, M_AXI_ARSIZE_i, M_AXI_ARBURST_i};
assign m_cmd_addr = m_r_cmd[(13+C_AXI_ID_WIDTH) +: P_MI_SIZE+4];
assign m_cmd_id = m_r_cmd[13 +: C_AXI_ID_WIDTH];
assign m_cmd_len = m_r_cmd[5 +: 8];
assign m_cmd_size = m_r_cmd[2 +: 3];
assign m_cmd_burst = m_r_cmd[0 +: 2];
assign m_rbuf_addr = f_m_rbuf_addr(m_raddr, m_rsize, m_rburst, m_buf);
assign m_rbuf_we = (large_incr_last ? large_incr_mask : 4'b1111) & f_m_rbuf_we(m_raddr, m_rsize);
assign m_rbuf_en = f_m_rbuf_en(m_raddr, m_rsize) & {P_NUM_RAMB{m_transfer}};
assign m_raddr_incr = m_raddr + f_m_size_incr(m_rsize);
always @(posedge m_aclk) begin
if (~m_aresetn) begin
M_AXI_ARVALID_i <= 1'b0;
end else begin
if (ar_pop) begin
M_AXI_ARVALID_i <= 1'b0;
end else if (ar_fifo_valid & ~m_cmd_full & (~m_cmd_valid | (M_AXI_ARID_i == m_cmd_id))) begin
M_AXI_ARVALID_i <= 1'b1;
end
end
end
always @(posedge m_aclk) begin
if (~m_aresetn) begin
m_buf <= 0;
M_AXI_RREADY_i <= 1'b0;
m_cmd_valid <= 1'b0;
m_rresp_fifo_stall <= 1'b0;
end else begin
if (M_AXI_RREADY_i) begin
if (M_AXI_RVALID) begin
m_rresp_reg <= M_AXI_RRESP;
if (rresp_fifo_full) begin
M_AXI_RREADY_i <= 1'b0;
m_rresp_fifo_stall <= 1'b1;
end
if (M_AXI_RLAST & m_cmd_empty) begin
M_AXI_RREADY_i <= 1'b0;
m_cmd_valid <= 1'b0;
end
end
end else if (~rresp_fifo_full) begin
m_rresp_fifo_stall <= 1'b0;
if (m_cmd_valid) begin
M_AXI_RREADY_i <= 1'b1;
end else if (~m_cmd_empty) begin
m_cmd_valid <= 1'b1;
M_AXI_RREADY_i <= 1'b1;
end
end
if (m_cmd_pop) begin
m_buf <= m_buf + 1;
end
end
end
always @(posedge m_aclk) begin
if (m_cmd_pop) begin
if (m_cmd_burst == P_WRAP) begin
m_raddr <= m_cmd_addr & f_m_wrap_mask(m_cmd_size, m_cmd_len);
end else begin
m_raddr <= m_cmd_addr & f_m_size_mask(m_cmd_size);
end
m_rsize <= m_cmd_size;
m_rburst <= m_cmd_burst;
m_wrap_cnt <= f_m_wrap_cnt(m_cmd_addr, m_cmd_size, m_cmd_len);
m_wrap_addr <= f_m_wrap_addr(m_cmd_addr, m_cmd_size, m_cmd_len);
large_incr_last <= 1'b0;
large_incr_mask <= f_large_incr_mask(m_cmd_addr);
end else if (m_transfer) begin
if ((m_rburst == P_WRAP) && (m_wrap_cnt == 0)) begin
m_raddr <= m_wrap_addr;
end else if (m_rburst == P_FIXED) begin
m_raddr <= m_raddr + P_MI_BYTES;
end else begin
if (~|m_raddr_incr) begin // Addr pointer is about to wrap to zero?
large_incr_last <= 1'b1;
end
m_raddr <= m_raddr_incr;
end
m_wrap_cnt <= m_wrap_cnt - 1;
end
end
for (i=0; i<P_NUM_RAMB; i=i+1) begin : gen_ramb
RAMB18E1 #(
.READ_WIDTH_A(P_S_RAMB_PWIDTH),
.WRITE_WIDTH_B(36),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.SIM_COLLISION_CHECK("NONE"),
.DOA_REG(1),
.DOB_REG(1),
.RAM_MODE("SDP"),
.READ_WIDTH_B(0),
.WRITE_WIDTH_A(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.SIM_DEVICE("7SERIES"),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST")
) ramb_inst (
.DOADO(s_rdata[(i*16) +: 16]),
.DIADI(m_rdata[(i*32) +: 16]),
.DIBDI(m_rdata[(i*32+16) +: 16]),
.WEBWE(m_rbuf_we),
.ADDRARDADDR(s_rbuf_addr),
.ADDRBWRADDR(m_rbuf_addr),
.ENARDEN(s_rbuf_en),
.REGCEAREGCE(s_rbuf_en),
.ENBWREN(m_rbuf_en[i]),
.CLKARDCLK(S_AXI_ACLK),
.CLKBWRCLK(m_aclk),
.RSTRAMARSTRAM(1'b0),
.RSTREGARSTREG(1'b0),
.WEA(2'b0),
.DIPADIP(2'b0),
.DIPBDIP(2'b0),
.REGCEB(1'b1),
.RSTRAMB(1'b0),
.RSTREGB(1'b0),
.DOBDO(),
.DOPADOP(),
.DOPBDOP()
);
end
fifo_generator_v12_0 #(
.C_FAMILY(C_FAMILY),
.C_COMMON_CLOCK(P_COMMON_CLOCK),
.C_MEMORY_TYPE(1),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_DIN_WIDTH_WACH(P_ARFIFO_WIDTH),
.C_DIN_WIDTH_WDCH(37),
.C_DIN_WIDTH_WRCH(2+C_AXI_ID_WIDTH),
.C_DIN_WIDTH_RACH(P_ARFIFO_WIDTH),
.C_DIN_WIDTH_RDCH(35+C_AXI_ID_WIDTH),
.C_AXIS_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(1),
.C_AXI_ID_WIDTH(C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH(C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(2),
.C_IMPLEMENTATION_TYPE_WACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_WDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_WRCH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RACH(P_COMMON_CLOCK ? 2 : 12),
.C_IMPLEMENTATION_TYPE_RDCH(P_COMMON_CLOCK ? 1 : 11),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(32),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(5),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(P_COMMON_CLOCK ? 2 : 0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(30),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(14),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0)
) dw_fifogen_ar (
.s_aclk(ar_fifo_s_aclk),
.m_aclk(ar_fifo_m_aclk),
.s_aresetn(ar_fifo_aresetn),
.s_axi_arid (cmd_si_id),
.s_axi_araddr (S_AXI_ARADDR),
.s_axi_arlen (S_AXI_ARLEN),
.s_axi_arsize (S_AXI_ARSIZE),
.s_axi_arburst (S_AXI_ARBURST),
.s_axi_arlock (S_AXI_ARLOCK[0]),
.s_axi_arcache (S_AXI_ARCACHE),
.s_axi_arprot (S_AXI_ARPROT),
.s_axi_arqos (S_AXI_ARQOS),
.s_axi_arregion (S_AXI_ARREGION),
.s_axi_aruser (1'b0),
.s_axi_arvalid (ar_push),
.s_axi_arready (ar_fifo_ready),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid (M_AXI_ARID_i),
.m_axi_araddr (M_AXI_ARADDR_i),
.m_axi_arlen (M_AXI_ARLEN_i),
.m_axi_arsize (M_AXI_ARSIZE_i),
.m_axi_arburst (M_AXI_ARBURST_i),
.m_axi_arlock (M_AXI_ARLOCK_i),
.m_axi_arcache (M_AXI_ARCACHE),
.m_axi_arprot (M_AXI_ARPROT),
.m_axi_arqos (M_AXI_ARQOS),
.m_axi_arregion (M_AXI_ARREGION),
.m_axi_aruser (),
.m_axi_arvalid (ar_fifo_valid),
.m_axi_arready (ar_pop),
.m_axi_rid({C_AXI_ID_WIDTH{1'b0}}),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axi_awid({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_awaddr({C_AXI_ADDR_WIDTH{1'b0}}),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(1'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid({C_AXI_ID_WIDTH{1'b0}}),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wuser(),
.m_axi_wlast(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid({C_AXI_ID_WIDTH{1'b0}}),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(5'b0),
.axi_ar_prog_empty_thresh(5'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
fifo_generator_v12_0 #(
.C_DIN_WIDTH(P_S_CMD_WIDTH),
.C_DOUT_WIDTH(P_S_CMD_WIDTH),
.C_RD_DEPTH(32),
.C_RD_PNTR_WIDTH(5),
.C_RD_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_PNTR_WIDTH(5),
.C_WR_DATA_COUNT_WIDTH(5),
.C_DATA_COUNT_WIDTH(5),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) s_cmd_fifo (
.clk(S_AXI_ACLK),
.srst(s_fifo_rst),
.din(s_ar_cmd),
.dout(s_r_cmd),
.full(s_cmd_full),
.empty(s_cmd_empty),
.wr_en(s_cmd_push),
.rd_en(s_cmd_pop),
.backup(1'b0),
.backup_marker(1'b0),
.rst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
fifo_generator_v12_0 #(
.C_DIN_WIDTH(P_M_CMD_WIDTH),
.C_DOUT_WIDTH(P_M_CMD_WIDTH),
.C_RD_DEPTH(32),
.C_RD_PNTR_WIDTH(5),
.C_RD_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(32),
.C_WR_PNTR_WIDTH(5),
.C_WR_DATA_COUNT_WIDTH(5),
.C_DATA_COUNT_WIDTH(5),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) m_cmd_fifo (
.clk(m_aclk),
.srst(m_fifo_rst),
.din(m_ar_cmd),
.dout(m_r_cmd),
.full(m_cmd_full),
.empty(m_cmd_empty),
.wr_en(m_cmd_push),
.rd_en(m_cmd_pop),
.backup(1'b0),
.backup_marker(1'b0),
.rst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.prog_empty_thresh(5'b0),
.prog_empty_thresh_assert(5'b0),
.prog_empty_thresh_negate(5'b0),
.prog_full_thresh(5'b0),
.prog_full_thresh_assert(5'b0),
.prog_full_thresh_negate(5'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
fifo_generator_v12_0 #(
.C_DIN_WIDTH(4),
.C_DOUT_WIDTH(4),
.C_RD_DEPTH(512),
.C_RD_PNTR_WIDTH(9),
.C_RD_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_PNTR_WIDTH(9),
.C_WR_DATA_COUNT_WIDTH(9),
.C_DATA_COUNT_WIDTH(9),
.C_COMMON_CLOCK(P_COMMON_CLOCK),
.C_COUNT_TYPE(0),
.C_DEFAULT_VALUE("BlankString"),
.C_DOUT_RST_VAL("0"),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(P_COMMON_CLOCK ? 0 : 1),
.C_HAS_SRST(P_COMMON_CLOCK ? 1 : 0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(P_COMMON_CLOCK ? 0 : 2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(31),
.C_PROG_FULL_THRESH_NEGATE_VAL(30),
.C_PROG_FULL_TYPE(0),
.C_RD_FREQ(1),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_FREQ(1),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2)
) dw_fifogen_rresp (
.clk(rresp_fifo_clk),
.wr_clk(rresp_fifo_wrclk),
.rd_clk(rresp_fifo_rdclk),
.srst(P_COMMON_CLOCK ? rresp_fifo_rst : 1'b0),
.rst(P_COMMON_CLOCK ? 1'b0 : rresp_fifo_rst),
.wr_rst(1'b0),
.rd_rst(1'b0),
.din(m_rresp_i),
.dout(s_rresp_i),
.full(rresp_fifo_full),
.empty(rresp_fifo_empty),
.wr_en(rresp_fifo_push),
.rd_en(rresp_fifo_pop),
.backup(1'b0),
.backup_marker(1'b0),
.prog_empty_thresh(9'b0),
.prog_empty_thresh_assert(9'b0),
.prog_empty_thresh_negate(9'b0),
.prog_full_thresh(9'b0),
.prog_full_thresh_assert(9'b0),
.prog_full_thresh_negate(9'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.almost_full(),
.wr_ack(),
.overflow(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.m_aclk(1'b0),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.s_axi_awid(4'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(4'b0),
.s_axi_wdata(64'b0),
.s_axi_wstrb(8'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'b0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(4'b0),
.m_axi_bresp(2'b0),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_bready(),
.s_axi_arid(4'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(4'b0),
.m_axi_rdata(64'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(4'b0),
.axi_b_prog_empty_thresh(4'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
endgenerate
endmodule
|
/*
* async_fifo: asynchronous FIFO, 18 bits wide
*
* (C) Arlet Ottens <[email protected]>
*/
module async_fifo(
input clka,
input [17:0] in,
input wr,
output full,
input clkb,
output [17:0] out,
input rd,
output empty );
reg [10:0] head_a = 0;
reg [10:0] head_a_b = 0;
reg [10:0] head_b = 0;
reg [10:0] tail_b = 0;
reg [10:0] tail_b_a = 0;
reg [10:0] tail_a = 0;
wire [10:0] size_a = (head_a - tail_a);
assign full = (size_a >= 11'h200);
assign empty = (tail_b == head_b);
RAMB16_S18_S18 mem(
.CLKA(clka),
.ADDRA(head_a[9:0]),
.DIA(in[15:0]),
.DIPA(in[17:16]),
.WEA(1'b1),
.ENA(wr & ~full),
.SSRA(1'b0),
.CLKB(clkb),
.ADDRB(tail_b[9:0]),
.DOB(out[15:0]),
.DOPB(out[17:16]),
.ENB(rd & ~empty),
.WEB(1'b0),
.SSRB(1'b0)
);
handshake handshake(
.clka(clka),
.clkb(clkb),
.sync_a(sync_a),
.sync_b(sync_b) );
/*
* clka domain
*/
always @(posedge clka)
if( wr & ~full )
head_a <= head_a + 1;
always @(posedge clka)
if( sync_a ) begin
head_a_b <= head_a;
tail_a <= tail_b_a;
end
/*
* clkb domain
*/
always @(posedge clkb)
if( sync_b ) begin
head_b <= head_a_b;
tail_b_a <= tail_b;
end
always @(posedge clkb)
if( rd & ~empty )
tail_b <= tail_b + 1;
endmodule
|
`default_nettype none
`define CLKFBOUT_MULT 2
// ============================================================================
module top
(
input wire clk,
input wire rst,
input wire [7:0] sw,
output wire [9:0] led,
inout wire io
);
localparam DATA_WIDTH = `DATA_WIDTH_DEFINE;
localparam DATA_RATE = `DATA_RATE_DEFINE;
// ============================================================================
// Clock & reset
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
wire CLK;
BUFG bufg(.I(clk), .O(CLK));
always @(posedge CLK)
if (rst)
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire RST = rst_sr[0];
// ============================================================================
// Clocks for ISERDES
wire PRE_BUFG_SYSCLK;
wire PRE_BUFG_CLKDIV;
wire SYSCLK;
wire CLKDIV;
wire O_LOCKED;
wire clk_fb_i;
wire clk_fb_o;
localparam DIVIDE_RATE = DATA_RATE == "SDR" ? DATA_WIDTH : DATA_WIDTH / 2;
PLLE2_ADV #(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.CLKIN1_PERIOD (10.0), // 100MHz
.CLKFBOUT_MULT (`CLKFBOUT_MULT),
.CLKOUT0_DIVIDE (`CLKFBOUT_MULT * 4), // SYSCLK, 25MHz
.CLKOUT1_DIVIDE ((`CLKFBOUT_MULT * 4) * DIVIDE_RATE), // CLKDIV, 25MHz / DIVIDE RATE
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1'd1)
)
pll
(
.CLKIN1 (CLK),
.CLKINSEL (1),
.RST (RST),
.PWRDWN (0),
.LOCKED (O_LOCKED),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (PRE_BUFG_SYSCLK),
.CLKOUT1 (PRE_BUFG_CLKDIV)
);
BUFG bufg_clk(.I(PRE_BUFG_SYSCLK), .O(SYSCLK));
BUFG bufg_clkdiv(.I(PRE_BUFG_CLKDIV), .O(CLKDIV));
// ============================================================================
// Test uints
wire [7:0] OUTPUTS;
wire [7:0] INPUTS = sw[7:0];
localparam MASK = DATA_WIDTH == 2 ? 8'b00000011 :
DATA_WIDTH == 3 ? 8'b00000111 :
DATA_WIDTH == 4 ? 8'b00001111 :
DATA_WIDTH == 5 ? 8'b00011111 :
DATA_WIDTH == 6 ? 8'b00111111 :
DATA_WIDTH == 7 ? 8'b01111111 :
/*DATA_WIDTH == 8*/ 8'b11111111;
wire [7:0] MASKED_INPUTS = INPUTS & MASK;
wire I_DAT;
wire O_DAT;
wire T_DAT;
IOBUF iobuf(.I(O_DAT), .O(I_DAT), .T(T_DAT), .IO(io));
serdes_test #
(
.DATA_WIDTH (DATA_WIDTH),
.DATA_RATE (DATA_RATE)
)
serdes_test
(
.SYSCLK (SYSCLK),
.CLKDIV (CLKDIV),
.RST (RST),
.OUTPUTS (OUTPUTS),
.INPUTS (MASKED_INPUTS),
.I_DAT (I_DAT),
.O_DAT (O_DAT),
.T_DAT (T_DAT)
);
wire [7:0] MASKED_OUTPUTS = OUTPUTS & MASK;
// ============================================================================
// I/O connections
reg [23:0] heartbeat_cnt;
always @(posedge SYSCLK)
heartbeat_cnt <= heartbeat_cnt + 1;
assign led[0] = heartbeat_cnt[22];
assign led[8:1] = MASKED_OUTPUTS;
endmodule
|
module InstrucDecoder (instr[31:26],RegDst, j, br,Mem2Reg,ALUop,MemWrEn,ALUsrc,writeSel);
input [31:26] instr;
output reg RegDst,j, br,Mem2Reg,ALUop,MemWrEn,ALUsrc,writeSel;
parameter nop=6'b101100,add=6'b100000, sub=6'b100010, AND=6'b100100, OR=6'b100101, XOR=6'b100110, slt=6'b101010,
sll=6'b000000, lw=6'b100011, sw=6'b101011, j=6'b000010, jr=6'b001000, bgt=6'b101101;
always @(*)
begin
case(instr)
nop: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn = 0;
ALUsrc = 0;
writeSel = 0;
end
add: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn = 0;
ALUsrc = 0;
writeSel = 1;
end
sub: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn = 0;
ALUsrc = 0;
writeSel = 1;
end
AND: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn = 0;
ALUsrc = 0;
writeSel = 1;
end
OR: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn = 0;
ALUsrc = 0;
writeSel = 1;
end
XOR: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn = 0;
ALUsrc = 0;
writeSel = 1;
end
slt: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn = 0;
ALUsrc = 0;
writeSel = 1;
end
sll: begin
RegDst = 1;
j = 0;
br = 0;
Mem2Reg = 0;
ALUop = 1;
MemWrEn =0;
ALUsrc = 0;
writeSel = 1;
end
lw: begin
RegDst = 0;
j = 0;
br = 0;
Mem2Reg = 1;
ALUop = 0;
MemWrEn = 1;
ALUsrc = 1;
writeSel = 0;
end
sw: begin
RegDst = 0;
j = 0;
br = 0;
Mem2Reg = 1;
ALUop = 0;
MemWrEn = 1;
ALUsrc = 1;
writeSel = 0;
end
j: begin
RegDst = 0;
j = 1;
br = 0;
Mem2Reg = 1;
ALUop = 0;
MemWrEn = 0;
ALUsrc = 1;
writeSel = 0;
end
jr: begin
RegDst = 0;
j = 1;
br = 0;
Mem2Reg = 1;
ALUop = 0;
MemWrEn = 0;
ALUsrc = 1;
writeSel = 0;
end
bgt: begin
RegDst = 0;
j = 0;
br = 1;
Mem2Reg = 1;
ALUop = 0;
MemWrEn = 0;
ALUsrc = 1;
writeSel = 0;
end
default:
RegDst = 1'bx;
j = 1'bx;
br = 1'bx;
Mem2Reg = 1'bx;
ALUop = 1'bx;
MemWrEn = 1'bx;
ALUsrc = 1'bx;
writeSel = 1'bx;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INV_FUNCTIONAL_V
`define SKY130_FD_SC_LP__INV_FUNCTIONAL_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__inv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__INV_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4_1_V
`define SKY130_FD_SC_MS__NOR4_1_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4_1_V
|
module MODE0(outR, outI, a, b);
input [15:0] a, b;
output signed [17:0] outR, outI;
wire signed [7:0] aR, aI;
wire signed [7:0] bR, bI;
wire signed [17:0] r1, r2;
wire signed [17:0] i1, i2;
assign aR = a[15:8]; assign aI = a[7:0];
assign bR = b[15:8]; assign bI = b[7:0];
assign r1 = aR*bR; assign r2 = aI*bI;
assign i1 = aR*bI; assign i2 = aI*bR;
assign outR = r1 - r2;
assign outI = i1 + i2;
endmodule
module Online_test2(
clk,
rst_n,
in_valid,
in,
in_mode,
out_valid,
out
);
//---------------------------------
// input and output declaration
//---------------------------------
input clk;
input rst_n;
input in_valid;
input [15:0] in;
input in_mode;
output reg out_valid;
output reg [35:0] out;
//----------------------------------
// reg and wire declaration
//---------------------------------
reg inMod;
reg rstState;
reg [5:0] cnt1, cnt2;
reg [15:0] a0, b0, a1, b1;
reg signed [17:0] rea, img;
reg [35:0] o0, o2, o4, o6, o8, o10;
wire signed [17:0] m00R, m00I, m01R, m01I, m10R, m10I, m11R, m11I;
wire [3:0] a01, a02, a03, a04;
wire [3:0] a11, a12, a13, a14;
wire [3:0] b01, b02, b03, b04;
wire [3:0] b11, b12, b13, b14;
//---------------------------------
// parameter declaration
//---------------------------------
MODE0 m00(m00R,m00I,a0,b0);
MODE0 m01(m01R,m01I,a0,b1);
MODE0 m10(m10R,m10I,a1,b0);
MODE0 m11(m11R,m11I,a1,b1);
assign a01 = a0[15:12]; assign a02 = a0[11:8]; assign a03 = a0[7:4]; assign a04 = a0[3:0];
assign a11 = a1[15:12]; assign a12 = a1[11:8]; assign a13 = a1[7:4]; assign a14 = a1[3:0];
assign b01 = b0[15:12]; assign b02 = b0[11:8]; assign b03 = b0[7:4]; assign b04 = b0[3:0];
assign b11 = b1[15:12]; assign b12 = b1[11:8]; assign b13 = b1[7:4]; assign b14 = b1[3:0];
//----------------------------------
//
// My design
//
//----------------------------------
always@(posedge clk) begin
if(in_mode == 1) inMod = 1; else;
if(in_mode == 0) inMod = 0; else;
if(rst_n == 1 || rstState == 1) begin
out_valid = 0;
out = 0;
rstState = 0;
cnt1 = 0;
cnt2 = 0;
o0 = 0; o2 = 0; o4 = 0; o6 = 0; o8 = 0; o10 = 0;
end
else;
if(in_valid == 1) begin
cnt1 = cnt1+1;
case(cnt1)
1: a0 = in;
2: a1 = in;
3: b0 = in;
4: b1 = in;
default:;
endcase
end
else;
if(cnt1 > 0 && in_valid == 0) begin
cnt2 = cnt2+1;
case(inMod)
0: begin
case(cnt2)
1: begin
out[35:18] = m00R;
out[17:0] = m00I;
out_valid = 1;
end
2: begin
rea = m01R + m10R;
img = m01I + m10I;
out[35:18] = rea;
out[17:0] = img;
out_valid = 1;
end
3: begin
out[35:18] = m11R;
out[17:0] = m11I;
out_valid = 1;
end
default: begin
rstState = 1;
out_valid = 0;
end
endcase
end
1: begin
case(cnt2)
1: begin
case(a01)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a02)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a03)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a04)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a11)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a12)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a13)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a14)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b01)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b02)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b03)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b04)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b11)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b12)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b13)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(b14)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
case(a01)
0: o0 = o0+1;
2: o2 = o2+1;
4: o4 = o4+1;
6: o6 = o6+1;
8: o8 = o8+1;
10: o10 = o10+1;
endcase
end
2: begin
out = o0;
out_valid = 1;
end
3: begin
out = o2;
out_valid = 1;
end
4: begin
out = o4;
out_valid = 1;
end
5: begin
out = o6;
out_valid = 1;
end
6: begin
out = o8;
out_valid = 1;
end
7: begin
out = o10;
out_valid = 1;
end
default: begin
rstState = 1;
out_valid = 0;
end
endcase
end
default:;
endcase
end
else;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31O_1_V
`define SKY130_FD_SC_HS__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31O_1_V
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Tag RAM
// File : de3d_tc_tag_ram.v
// Author : Jim MacLeod
// Created : 14-May-2011
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
module de3d_tc_tag_ram
(
// Inputs
input de_clk, /* DE clock. */
input de_rstn, /* DE reset. */
input [3:0] cur_mipmap, /* Current mipmap level */
input ee_s0_loadn, /* Load even, even, set 0 RAM. */
input ee_s1_loadn, /* Load even, even , set 1 RAM. */
input eo_s0_loadn, /* Load even, odd, set 0 RAM. */
input eo_s1_loadn, /* Load even, odd, set 1 RAM. */
input oe_s0_loadn, /* Load odd, even, set 0 RAM. */
input oe_s1_loadn, /* Load odd, even, set 1 RAM. */
input oo_s0_loadn, /* Load odd, odd, set 0 RAM. */
input oo_s1_loadn, /* Load odd, odd, set 1 RAM. */
input [4:0] ee_tag_adr_rd, /* Address for even, even RAM. */
input [4:0] eo_tag_adr_rd, /* Address for even, odd RAM. */
input [4:0] oe_tag_adr_rd, /* Address for odd, even RAM. */
input [4:0] oo_tag_adr_rd, /* Address for odd, odd RAM. */
input [4:0] ee_tag_adr_wr, /* Address for even, even RAM. */
input [4:0] eo_tag_adr_wr, /* Address for even, odd RAM. */
input [4:0] oe_tag_adr_wr, /* Address for odd, even RAM. */
input [4:0] oo_tag_adr_wr, /* Address for odd, odd RAM. */
input [7:0] ee_tag_dat_in, /* Data in for even, even RAM. */
input [7:0] eo_tag_dat_in, /* Data in for even, odd RAM. */
input [7:0] oe_tag_dat_in, /* Data in for odd, even RAM. */
input [7:0] oo_tag_dat_in, /* Data in for odd, odd RAM. */
input tag_ram_csn, /* Enable Tag RAM for read or write. */
// Outputs
output [23:0] ee_tag_dat_out, /* Data out for even, even RAM. */
output [23:0] eo_tag_dat_out, /* Data out for even, odd RAM. */
output [23:0] oe_tag_dat_out, /* Data out for odd, even RAM. */
output [23:0] oo_tag_dat_out /* Data out for odd, odd RAM. */
);
// reg [11:0] ram_ee_0 [0:31];
// reg [11:0] ram_ee_1 [0:31];
// reg [11:0] ram_eo_0 [0:31];
// reg [11:0] ram_eo_1 [0:31];
// reg [11:0] ram_oe_0 [0:31];
// reg [11:0] ram_oe_1 [0:31];
// reg [11:0] ram_oo_0 [0:31];
// reg [11:0] ram_oo_1 [0:31];
/*
`ifdef RTL_SIM
reg [5:0] clear_count;
initial begin
for(clear_count = 0; clear_count < 32; clear_count = clear_count + 1) begin
ram_ee_0[clear_count] = 12'h0;
ram_ee_1[clear_count] = 12'h0;
ram_eo_0[clear_count] = 12'h0;
ram_eo_1[clear_count] = 12'h0;
ram_oe_0[clear_count] = 12'h0;
ram_oe_1[clear_count] = 12'h0;
ram_oo_0[clear_count] = 12'h0;
ram_oo_1[clear_count] = 12'h0;
end
end
`endif
*/
// Set 0.
// always @(posedge de_clk) if(!ee_s0_loadn & !tag_ram_csn) ram_ee_0[ee_tag_adr] <= {cur_mipmap,ee_tag_dat_in};
// always @* ee_tag_dat_out[11:0] = ram_ee_0[ee_tag_adr];
// Set 1.
// always @(posedge de_clk) if(!ee_s1_loadn & !tag_ram_csn) ram_ee_1[ee_tag_adr] <= {cur_mipmap,ee_tag_dat_in};
// always @* ee_tag_dat_out[23:12] = ram_ee_1[ee_tag_adr];
// Set 0, 1.
ram_tag s0_s1_ee_tag
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.tag_s0_loadn (ee_s0_loadn),
.tag_s1_loadn (ee_s1_loadn),
.tag_ram_csn (tag_ram_csn),
.tag_adr_wr (ee_tag_adr_wr),
.tag_adr_rd (ee_tag_adr_rd),
.tag_dat_in ({cur_mipmap, ee_tag_dat_in}),
.tag_dat_out (ee_tag_dat_out)
);
// Set 0.
// always @(posedge de_clk) if(!eo_s0_loadn & !tag_ram_csn) ram_eo_0[eo_tag_adr] <= {cur_mipmap,eo_tag_dat_in};
// always @* eo_tag_dat_out[11:0] = ram_eo_0[ee_tag_adr];
// Set 1.
// always @(posedge de_clk) if(!eo_s1_loadn & !tag_ram_csn) ram_eo_1[eo_tag_adr] <= {cur_mipmap,eo_tag_dat_in};
// always @* eo_tag_dat_out[23:12] = ram_eo_1[eo_tag_adr];
// Set 0, 1.
ram_tag s0_s1_eo_tag
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.tag_s0_loadn (eo_s0_loadn),
.tag_s1_loadn (eo_s1_loadn),
.tag_ram_csn (tag_ram_csn),
.tag_adr_wr (eo_tag_adr_wr),
.tag_adr_rd (eo_tag_adr_rd),
.tag_dat_in ({cur_mipmap, eo_tag_dat_in}),
.tag_dat_out (eo_tag_dat_out)
);
// Set 0.
// always @(posedge de_clk) if(!oe_s0_loadn & !tag_ram_csn) ram_oe_0[oe_tag_adr] <= {cur_mipmap,oe_tag_dat_in};
// always @* oe_tag_dat_out[11:0] = ram_oe_0[oe_tag_adr];
// Set 1.
// always @(posedge de_clk) if(!oe_s1_loadn & !tag_ram_csn) ram_oe_1[oe_tag_adr] <= {cur_mipmap,oe_tag_dat_in};
// always @* oe_tag_dat_out[23:12] = ram_oe_1[oe_tag_adr];
ram_tag s0_s1_oe_tag
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.tag_s0_loadn (oe_s0_loadn),
.tag_s1_loadn (oe_s1_loadn),
.tag_ram_csn (tag_ram_csn),
.tag_adr_wr (oe_tag_adr_wr),
.tag_adr_rd (oe_tag_adr_rd),
.tag_dat_in ({cur_mipmap, oe_tag_dat_in}),
.tag_dat_out (oe_tag_dat_out)
);
// Set 0.
// always @(posedge de_clk) if(!oo_s0_loadn & !tag_ram_csn) ram_oo_0[oo_tag_adr] <= {cur_mipmap,oo_tag_dat_in};
// always @* oo_tag_dat_out[11:0] = ram_oo_0[oo_tag_adr];
// Set 1.
// always @(posedge de_clk) if(!oo_s1_loadn & !tag_ram_csn) ram_oo_1[oo_tag_adr] <= {cur_mipmap,oo_tag_dat_in};
// always @* oo_tag_dat_out[23:12] = ram_oo_1[oo_tag_adr];
ram_tag s0_s1_oo_tag
(
.de_clk (de_clk),
.de_rstn (de_rstn),
.tag_s0_loadn (oo_s0_loadn),
.tag_s1_loadn (oo_s1_loadn),
.tag_ram_csn (tag_ram_csn),
.tag_adr_wr (oo_tag_adr_wr),
.tag_adr_rd (oo_tag_adr_rd),
.tag_dat_in ({cur_mipmap, oo_tag_dat_in}),
.tag_dat_out (oo_tag_dat_out)
);
endmodule
module ram_tag
(
input de_clk,
input de_rstn,
input tag_s0_loadn,
input tag_s1_loadn,
input tag_ram_csn,
input [4:0] tag_adr_wr,
input [4:0] tag_adr_rd,
input [11:0] tag_dat_in,
output reg [23:0] tag_dat_out
);
reg [11:0] ram_tag0_s0;
reg [11:0] ram_tag1_s0;
reg [11:0] ram_tag2_s0;
reg [11:0] ram_tag3_s0;
reg [11:0] ram_tag4_s0;
reg [11:0] ram_tag5_s0;
reg [11:0] ram_tag6_s0;
reg [11:0] ram_tag7_s0;
reg [11:0] ram_tag8_s0;
reg [11:0] ram_tag9_s0;
reg [11:0] ram_tag10_s0;
reg [11:0] ram_tag11_s0;
reg [11:0] ram_tag12_s0;
reg [11:0] ram_tag13_s0;
reg [11:0] ram_tag14_s0;
reg [11:0] ram_tag15_s0;
reg [11:0] ram_tag16_s0;
reg [11:0] ram_tag17_s0;
reg [11:0] ram_tag18_s0;
reg [11:0] ram_tag19_s0;
reg [11:0] ram_tag20_s0;
reg [11:0] ram_tag21_s0;
reg [11:0] ram_tag22_s0;
reg [11:0] ram_tag23_s0;
reg [11:0] ram_tag24_s0;
reg [11:0] ram_tag25_s0;
reg [11:0] ram_tag26_s0;
reg [11:0] ram_tag27_s0;
reg [11:0] ram_tag28_s0;
reg [11:0] ram_tag29_s0;
reg [11:0] ram_tag30_s0;
reg [11:0] ram_tag31_s0;
reg [11:0] ram_tag0_s1;
reg [11:0] ram_tag1_s1;
reg [11:0] ram_tag2_s1;
reg [11:0] ram_tag3_s1;
reg [11:0] ram_tag4_s1;
reg [11:0] ram_tag5_s1;
reg [11:0] ram_tag6_s1;
reg [11:0] ram_tag7_s1;
reg [11:0] ram_tag8_s1;
reg [11:0] ram_tag9_s1;
reg [11:0] ram_tag10_s1;
reg [11:0] ram_tag11_s1;
reg [11:0] ram_tag12_s1;
reg [11:0] ram_tag13_s1;
reg [11:0] ram_tag14_s1;
reg [11:0] ram_tag15_s1;
reg [11:0] ram_tag16_s1;
reg [11:0] ram_tag17_s1;
reg [11:0] ram_tag18_s1;
reg [11:0] ram_tag19_s1;
reg [11:0] ram_tag20_s1;
reg [11:0] ram_tag21_s1;
reg [11:0] ram_tag22_s1;
reg [11:0] ram_tag23_s1;
reg [11:0] ram_tag24_s1;
reg [11:0] ram_tag25_s1;
reg [11:0] ram_tag26_s1;
reg [11:0] ram_tag27_s1;
reg [11:0] ram_tag28_s1;
reg [11:0] ram_tag29_s1;
reg [11:0] ram_tag30_s1;
reg [11:0] ram_tag31_s1;
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
ram_tag0_s0 <= 12'h0;
ram_tag1_s0 <= 12'h0;
ram_tag2_s0 <= 12'h0;
ram_tag3_s0 <= 12'h0;
ram_tag4_s0 <= 12'h0;
ram_tag5_s0 <= 12'h0;
ram_tag6_s0 <= 12'h0;
ram_tag7_s0 <= 12'h0;
ram_tag8_s0 <= 12'h0;
ram_tag9_s0 <= 12'h0;
ram_tag10_s0 <= 12'h0;
ram_tag11_s0 <= 12'h0;
ram_tag12_s0 <= 12'h0;
ram_tag13_s0 <= 12'h0;
ram_tag14_s0 <= 12'h0;
ram_tag15_s0 <= 12'h0;
ram_tag16_s0 <= 12'h0;
ram_tag17_s0 <= 12'h0;
ram_tag18_s0 <= 12'h0;
ram_tag19_s0 <= 12'h0;
ram_tag20_s0 <= 12'h0;
ram_tag21_s0 <= 12'h0;
ram_tag22_s0 <= 12'h0;
ram_tag23_s0 <= 12'h0;
ram_tag24_s0 <= 12'h0;
ram_tag25_s0 <= 12'h0;
ram_tag26_s0 <= 12'h0;
ram_tag27_s0 <= 12'h0;
ram_tag28_s0 <= 12'h0;
ram_tag29_s0 <= 12'h0;
ram_tag30_s0 <= 12'h0;
ram_tag31_s0 <= 12'h0;
end
else if(!tag_s0_loadn & !tag_ram_csn) begin
case(tag_adr_wr)
5'd0: ram_tag0_s0 <= tag_dat_in;
5'd1: ram_tag1_s0 <= tag_dat_in;
5'd2: ram_tag2_s0 <= tag_dat_in;
5'd3: ram_tag3_s0 <= tag_dat_in;
5'd4: ram_tag4_s0 <= tag_dat_in;
5'd5: ram_tag5_s0 <= tag_dat_in;
5'd6: ram_tag6_s0 <= tag_dat_in;
5'd7: ram_tag7_s0 <= tag_dat_in;
5'd8: ram_tag8_s0 <= tag_dat_in;
5'd9: ram_tag9_s0 <= tag_dat_in;
5'd10: ram_tag10_s0 <= tag_dat_in;
5'd11: ram_tag11_s0 <= tag_dat_in;
5'd12: ram_tag12_s0 <= tag_dat_in;
5'd13: ram_tag13_s0 <= tag_dat_in;
5'd14: ram_tag14_s0 <= tag_dat_in;
5'd15: ram_tag15_s0 <= tag_dat_in;
5'd16: ram_tag16_s0 <= tag_dat_in;
5'd17: ram_tag17_s0 <= tag_dat_in;
5'd18: ram_tag18_s0 <= tag_dat_in;
5'd19: ram_tag19_s0 <= tag_dat_in;
5'd20: ram_tag20_s0 <= tag_dat_in;
5'd21: ram_tag21_s0 <= tag_dat_in;
5'd22: ram_tag22_s0 <= tag_dat_in;
5'd23: ram_tag23_s0 <= tag_dat_in;
5'd24: ram_tag24_s0 <= tag_dat_in;
5'd25: ram_tag25_s0 <= tag_dat_in;
5'd26: ram_tag26_s0 <= tag_dat_in;
5'd27: ram_tag27_s0 <= tag_dat_in;
5'd28: ram_tag28_s0 <= tag_dat_in;
5'd29: ram_tag29_s0 <= tag_dat_in;
5'd30: ram_tag30_s0 <= tag_dat_in;
5'd31: ram_tag31_s0 <= tag_dat_in;
endcase
end
end
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) begin
ram_tag0_s1 <= 12'h0;
ram_tag1_s1 <= 12'h0;
ram_tag2_s1 <= 12'h0;
ram_tag3_s1 <= 12'h0;
ram_tag4_s1 <= 12'h0;
ram_tag5_s1 <= 12'h0;
ram_tag6_s1 <= 12'h0;
ram_tag7_s1 <= 12'h0;
ram_tag8_s1 <= 12'h0;
ram_tag9_s1 <= 12'h0;
ram_tag10_s1 <= 12'h0;
ram_tag11_s1 <= 12'h0;
ram_tag12_s1 <= 12'h0;
ram_tag13_s1 <= 12'h0;
ram_tag14_s1 <= 12'h0;
ram_tag15_s1 <= 12'h0;
ram_tag16_s1 <= 12'h0;
ram_tag17_s1 <= 12'h0;
ram_tag18_s1 <= 12'h0;
ram_tag19_s1 <= 12'h0;
ram_tag20_s1 <= 12'h0;
ram_tag21_s1 <= 12'h0;
ram_tag22_s1 <= 12'h0;
ram_tag23_s1 <= 12'h0;
ram_tag24_s1 <= 12'h0;
ram_tag25_s1 <= 12'h0;
ram_tag26_s1 <= 12'h0;
ram_tag27_s1 <= 12'h0;
ram_tag28_s1 <= 12'h0;
ram_tag29_s1 <= 12'h0;
ram_tag30_s1 <= 12'h0;
ram_tag31_s1 <= 12'h0;
end
else if(!tag_s1_loadn & !tag_ram_csn) begin
case(tag_adr_wr)
5'd0: ram_tag0_s1 <= tag_dat_in;
5'd1: ram_tag1_s1 <= tag_dat_in;
5'd2: ram_tag2_s1 <= tag_dat_in;
5'd3: ram_tag3_s1 <= tag_dat_in;
5'd4: ram_tag4_s1 <= tag_dat_in;
5'd5: ram_tag5_s1 <= tag_dat_in;
5'd6: ram_tag6_s1 <= tag_dat_in;
5'd7: ram_tag7_s1 <= tag_dat_in;
5'd8: ram_tag8_s1 <= tag_dat_in;
5'd9: ram_tag9_s1 <= tag_dat_in;
5'd10: ram_tag10_s1 <= tag_dat_in;
5'd11: ram_tag11_s1 <= tag_dat_in;
5'd12: ram_tag12_s1 <= tag_dat_in;
5'd13: ram_tag13_s1 <= tag_dat_in;
5'd14: ram_tag14_s1 <= tag_dat_in;
5'd15: ram_tag15_s1 <= tag_dat_in;
5'd16: ram_tag16_s1 <= tag_dat_in;
5'd17: ram_tag17_s1 <= tag_dat_in;
5'd18: ram_tag18_s1 <= tag_dat_in;
5'd19: ram_tag19_s1 <= tag_dat_in;
5'd20: ram_tag20_s1 <= tag_dat_in;
5'd21: ram_tag21_s1 <= tag_dat_in;
5'd22: ram_tag22_s1 <= tag_dat_in;
5'd23: ram_tag23_s1 <= tag_dat_in;
5'd24: ram_tag24_s1 <= tag_dat_in;
5'd25: ram_tag25_s1 <= tag_dat_in;
5'd26: ram_tag26_s1 <= tag_dat_in;
5'd27: ram_tag27_s1 <= tag_dat_in;
5'd28: ram_tag28_s1 <= tag_dat_in;
5'd29: ram_tag29_s1 <= tag_dat_in;
5'd30: ram_tag30_s1 <= tag_dat_in;
5'd31: ram_tag31_s1 <= tag_dat_in;
endcase
end
end
always @* begin
case(tag_adr_rd)
5'd0: tag_dat_out = {ram_tag0_s1, ram_tag0_s0};
5'd1: tag_dat_out = {ram_tag1_s1, ram_tag1_s0};
5'd2: tag_dat_out = {ram_tag2_s1, ram_tag2_s0};
5'd3: tag_dat_out = {ram_tag3_s1, ram_tag3_s0};
5'd4: tag_dat_out = {ram_tag4_s1, ram_tag4_s0};
5'd5: tag_dat_out = {ram_tag5_s1, ram_tag5_s0};
5'd6: tag_dat_out = {ram_tag6_s1, ram_tag6_s0};
5'd7: tag_dat_out = {ram_tag7_s1, ram_tag7_s0};
5'd8: tag_dat_out = {ram_tag8_s1, ram_tag8_s0};
5'd9: tag_dat_out = {ram_tag9_s1, ram_tag9_s0};
5'd10: tag_dat_out = {ram_tag10_s1, ram_tag10_s0};
5'd11: tag_dat_out = {ram_tag11_s1, ram_tag11_s0};
5'd12: tag_dat_out = {ram_tag12_s1, ram_tag12_s0};
5'd13: tag_dat_out = {ram_tag13_s1, ram_tag13_s0};
5'd14: tag_dat_out = {ram_tag14_s1, ram_tag14_s0};
5'd15: tag_dat_out = {ram_tag15_s1, ram_tag15_s0};
5'd16: tag_dat_out = {ram_tag16_s1, ram_tag16_s0};
5'd17: tag_dat_out = {ram_tag17_s1, ram_tag17_s0};
5'd18: tag_dat_out = {ram_tag18_s1, ram_tag18_s0};
5'd19: tag_dat_out = {ram_tag19_s1, ram_tag19_s0};
5'd20: tag_dat_out = {ram_tag20_s1, ram_tag20_s0};
5'd21: tag_dat_out = {ram_tag21_s1, ram_tag21_s0};
5'd22: tag_dat_out = {ram_tag22_s1, ram_tag22_s0};
5'd23: tag_dat_out = {ram_tag23_s1, ram_tag23_s0};
5'd24: tag_dat_out = {ram_tag24_s1, ram_tag24_s0};
5'd25: tag_dat_out = {ram_tag25_s1, ram_tag25_s0};
5'd26: tag_dat_out = {ram_tag26_s1, ram_tag26_s0};
5'd27: tag_dat_out = {ram_tag27_s1, ram_tag27_s0};
5'd28: tag_dat_out = {ram_tag28_s1, ram_tag28_s0};
5'd29: tag_dat_out = {ram_tag29_s1, ram_tag29_s0};
5'd30: tag_dat_out = {ram_tag30_s1, ram_tag30_s0};
5'd31: tag_dat_out = {ram_tag31_s1, ram_tag31_s0};
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon May 29 22:11:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_1/system_xlconstant_0_1_stub.v
// Design : system_xlconstant_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_xlconstant_0_1(dout)
/* synthesis syn_black_box black_box_pad_pin="dout[31:0]" */;
output [31:0]dout;
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:35:10 $
// \ \ / \ Date Created: 05/12/10
// \___\/\___\
//
//Device: 7 Series
//Design Name: ddr_prbs_gen
// Overview:
// Implements a "pseudo-PRBS" generator. Basically this is a standard
// PRBS generator (using an linear feedback shift register) along with
// logic to force the repetition of the sequence after 2^PRBS_WIDTH
// samples (instead of 2^PRBS_WIDTH - 1). The LFSR is based on the design
// from Table 1 of XAPP 210. Note that only 8- and 10-tap long LFSR chains
// are supported in this code
// Parameter Requirements:
// 1. PRBS_WIDTH = 8 or 10
// 2. PRBS_WIDTH >= 2*nCK_PER_CLK
// Output notes:
// The output of this module consists of 2*nCK_PER_CLK bits, these contain
// the value of the LFSR output for the next 2*CK_PER_CLK bit times. Note
// that prbs_o[0] contains the bit value for the "earliest" bit time.
//
//Reference:
//Revision History:
//
//*****************************************************************************
/******************************************************************************
**$Id: ddr_prbs_gen.v,v 1.1 2011/06/02 08:35:10 mishra Exp $
**$Date: 2011/06/02 08:35:10 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/phy/ddr_prbs_gen.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_0_ddr_prbs_gen #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter PRBS_WIDTH = 64 // LFSR shift register length
)
(
input clk_i, // input clock
input clk_en_i, // clock enable
input rst_i, // synchronous reset
input [PRBS_WIDTH-1:0] prbs_seed_i, // initial LFSR seed
input phy_if_empty, // IN_FIFO empty flag
input prbs_rdlvl_start, // PRBS read lveling start
output [PRBS_WIDTH-1:0] prbs_o // generated pseudo random data
);
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
// Number of internal clock cycles before the PRBS sequence will repeat
localparam PRBS_SEQ_LEN_CYCLES = 128;
localparam PRBS_SEQ_LEN_CYCLES_BITS = clogb2(PRBS_SEQ_LEN_CYCLES);
reg phy_if_empty_r;
reg reseed_prbs_r;
reg [PRBS_SEQ_LEN_CYCLES_BITS-1:0] sample_cnt_r;
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
//***************************************************************************
always @(posedge clk_i) begin
phy_if_empty_r <= #TCQ phy_if_empty;
end
//***************************************************************************
// Generate PRBS reset signal to ensure that PRBS sequence repeats after
// every 2**PRBS_WIDTH samples. Basically what happens is that we let the
// LFSR run for an extra cycle after "truly PRBS" 2**PRBS_WIDTH - 1
// samples have past. Once that extra cycle is finished, we reseed the LFSR
always @(posedge clk_i)
begin
if (rst_i || ~clk_en_i) begin
sample_cnt_r <= #TCQ 'b0;
reseed_prbs_r <= #TCQ 1'b0;
end else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
// The rollver count should always be [(power of 2) - 1]
sample_cnt_r <= #TCQ sample_cnt_r + 1;
// Assert PRBS reset signal so that it is simultaneously with the
// last sample of the sequence
if (sample_cnt_r == PRBS_SEQ_LEN_CYCLES - 2)
reseed_prbs_r <= #TCQ 1'b1;
else
reseed_prbs_r <= #TCQ 1'b0;
end
end
always @ (posedge clk_i)
begin
//reset it to a known good state to prevent it locks up
if ((reseed_prbs_r && clk_en_i) || rst_i || ~clk_en_i) begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4];
end
else if (clk_en_i && (~phy_if_empty_r || ~prbs_rdlvl_start)) begin
lfsr_q[PRBS_WIDTH:31] <= #TCQ lfsr_q[PRBS_WIDTH-1:30];
lfsr_q[30] <= #TCQ lfsr_q[16] ^ lfsr_q[13] ^ lfsr_q[5] ^ lfsr_q[1];
lfsr_q[29:9] <= #TCQ lfsr_q[28:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
`include "divider.vh"
`default_nettype none
//-- Servo test
module osc(input wire clk,
output wire s0,
output wire s1,
output wire led0);
parameter WAIT_DELAY = `T_50ms + `T_10ms;
//-- Fichero con la rom
parameter ROMFILE0 = "rom0.list";
parameter ROMFILE1 = "rom1.list";
//-- Numero de bits de la direccione
parameter AW = 5;
parameter DW = 8;
//-- Just for debugging
assign led0 = s0;
wire [7:0] pos0;
wire [7:0] pos1;
//-- Intantiate the servo unit
ServoUnit
SERVO0 (.clk(clk),
.pos({1'b0,pos0[7:1]} + 8'd64),
.servo(s0));
ServoUnit
SERVO1 (.clk(clk),
.pos({1'b0,pos1[7:1]} + 8'd64),
.servo(s1));
wire tic;
dividerp1 #(WAIT_DELAY)
TIMMER0 (.clk(clk),
.timer_ena(1'b1),
.clk_out(tic));
reg [AW-1: 0] addr = 0; //-- Bus de direcciones
reg [DW-1: 0] data; //-- Bus de datos
always @(posedge clk)
if (tic)
addr <= addr + 1;
genrom
#( .ROMFILE(ROMFILE0), //-- Asignacion de parametros
.AW(AW),
.DW(DW))
ROM0 ( //-- coneion de cables
.clk(clk),
.addr(addr),
.data(pos0)
);
genrom
#( .ROMFILE(ROMFILE1), //-- Asignacion de parametros
.AW(AW),
.DW(DW))
ROM1 ( //-- coneion de cables
.clk(clk),
.addr(addr),
.data(pos1)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 28 18:34:35 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_debounce_0_0 -prefix
// system_debounce_0_0_ system_debounce_0_0_sim_netlist.v
// Design : system_debounce_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_debounce_0_0_debounce
(signal_out,
clk,
signal_in);
output signal_out;
input clk;
input signal_in;
wire \c[0]_i_3_n_0 ;
wire \c[0]_i_4_n_0 ;
wire \c[0]_i_5_n_0 ;
wire \c[0]_i_6_n_0 ;
wire \c[12]_i_2_n_0 ;
wire \c[12]_i_3_n_0 ;
wire \c[12]_i_4_n_0 ;
wire \c[12]_i_5_n_0 ;
wire \c[16]_i_2_n_0 ;
wire \c[16]_i_3_n_0 ;
wire \c[16]_i_4_n_0 ;
wire \c[16]_i_5_n_0 ;
wire \c[20]_i_2_n_0 ;
wire \c[20]_i_3_n_0 ;
wire \c[20]_i_4_n_0 ;
wire \c[20]_i_5_n_0 ;
wire \c[4]_i_2_n_0 ;
wire \c[4]_i_3_n_0 ;
wire \c[4]_i_4_n_0 ;
wire \c[4]_i_5_n_0 ;
wire \c[8]_i_2_n_0 ;
wire \c[8]_i_3_n_0 ;
wire \c[8]_i_4_n_0 ;
wire \c[8]_i_5_n_0 ;
wire [23:0]c_reg;
wire \c_reg[0]_i_2_n_0 ;
wire \c_reg[0]_i_2_n_1 ;
wire \c_reg[0]_i_2_n_2 ;
wire \c_reg[0]_i_2_n_3 ;
wire \c_reg[0]_i_2_n_4 ;
wire \c_reg[0]_i_2_n_5 ;
wire \c_reg[0]_i_2_n_6 ;
wire \c_reg[0]_i_2_n_7 ;
wire \c_reg[12]_i_1_n_0 ;
wire \c_reg[12]_i_1_n_1 ;
wire \c_reg[12]_i_1_n_2 ;
wire \c_reg[12]_i_1_n_3 ;
wire \c_reg[12]_i_1_n_4 ;
wire \c_reg[12]_i_1_n_5 ;
wire \c_reg[12]_i_1_n_6 ;
wire \c_reg[12]_i_1_n_7 ;
wire \c_reg[16]_i_1_n_0 ;
wire \c_reg[16]_i_1_n_1 ;
wire \c_reg[16]_i_1_n_2 ;
wire \c_reg[16]_i_1_n_3 ;
wire \c_reg[16]_i_1_n_4 ;
wire \c_reg[16]_i_1_n_5 ;
wire \c_reg[16]_i_1_n_6 ;
wire \c_reg[16]_i_1_n_7 ;
wire \c_reg[20]_i_1_n_1 ;
wire \c_reg[20]_i_1_n_2 ;
wire \c_reg[20]_i_1_n_3 ;
wire \c_reg[20]_i_1_n_4 ;
wire \c_reg[20]_i_1_n_5 ;
wire \c_reg[20]_i_1_n_6 ;
wire \c_reg[20]_i_1_n_7 ;
wire \c_reg[4]_i_1_n_0 ;
wire \c_reg[4]_i_1_n_1 ;
wire \c_reg[4]_i_1_n_2 ;
wire \c_reg[4]_i_1_n_3 ;
wire \c_reg[4]_i_1_n_4 ;
wire \c_reg[4]_i_1_n_5 ;
wire \c_reg[4]_i_1_n_6 ;
wire \c_reg[4]_i_1_n_7 ;
wire \c_reg[8]_i_1_n_0 ;
wire \c_reg[8]_i_1_n_1 ;
wire \c_reg[8]_i_1_n_2 ;
wire \c_reg[8]_i_1_n_3 ;
wire \c_reg[8]_i_1_n_4 ;
wire \c_reg[8]_i_1_n_5 ;
wire \c_reg[8]_i_1_n_6 ;
wire \c_reg[8]_i_1_n_7 ;
wire clear;
wire clk;
wire signal_in;
wire signal_out;
wire signal_out_i_1_n_0;
wire signal_out_i_2_n_0;
wire signal_out_i_3_n_0;
wire signal_out_i_4_n_0;
wire signal_out_i_5_n_0;
wire [3:3]\NLW_c_reg[20]_i_1_CO_UNCONNECTED ;
LUT1 #(
.INIT(2'h1))
\c[0]_i_1
(.I0(signal_in),
.O(clear));
LUT1 #(
.INIT(2'h2))
\c[0]_i_3
(.I0(c_reg[3]),
.O(\c[0]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[0]_i_4
(.I0(c_reg[2]),
.O(\c[0]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[0]_i_5
(.I0(c_reg[1]),
.O(\c[0]_i_5_n_0 ));
LUT1 #(
.INIT(2'h1))
\c[0]_i_6
(.I0(c_reg[0]),
.O(\c[0]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_2
(.I0(c_reg[15]),
.O(\c[12]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_3
(.I0(c_reg[14]),
.O(\c[12]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_4
(.I0(c_reg[13]),
.O(\c[12]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[12]_i_5
(.I0(c_reg[12]),
.O(\c[12]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_2
(.I0(c_reg[19]),
.O(\c[16]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_3
(.I0(c_reg[18]),
.O(\c[16]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_4
(.I0(c_reg[17]),
.O(\c[16]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[16]_i_5
(.I0(c_reg[16]),
.O(\c[16]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_2
(.I0(c_reg[23]),
.O(\c[20]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_3
(.I0(c_reg[22]),
.O(\c[20]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_4
(.I0(c_reg[21]),
.O(\c[20]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[20]_i_5
(.I0(c_reg[20]),
.O(\c[20]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_2
(.I0(c_reg[7]),
.O(\c[4]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_3
(.I0(c_reg[6]),
.O(\c[4]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_4
(.I0(c_reg[5]),
.O(\c[4]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[4]_i_5
(.I0(c_reg[4]),
.O(\c[4]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_2
(.I0(c_reg[11]),
.O(\c[8]_i_2_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_3
(.I0(c_reg[10]),
.O(\c[8]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_4
(.I0(c_reg[9]),
.O(\c[8]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\c[8]_i_5
(.I0(c_reg[8]),
.O(\c[8]_i_5_n_0 ));
FDRE \c_reg[0]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_7 ),
.Q(c_reg[0]),
.R(clear));
CARRY4 \c_reg[0]_i_2
(.CI(1'b0),
.CO({\c_reg[0]_i_2_n_0 ,\c_reg[0]_i_2_n_1 ,\c_reg[0]_i_2_n_2 ,\c_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b1}),
.O({\c_reg[0]_i_2_n_4 ,\c_reg[0]_i_2_n_5 ,\c_reg[0]_i_2_n_6 ,\c_reg[0]_i_2_n_7 }),
.S({\c[0]_i_3_n_0 ,\c[0]_i_4_n_0 ,\c[0]_i_5_n_0 ,\c[0]_i_6_n_0 }));
FDRE \c_reg[10]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_5 ),
.Q(c_reg[10]),
.R(clear));
FDRE \c_reg[11]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_4 ),
.Q(c_reg[11]),
.R(clear));
FDRE \c_reg[12]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_7 ),
.Q(c_reg[12]),
.R(clear));
CARRY4 \c_reg[12]_i_1
(.CI(\c_reg[8]_i_1_n_0 ),
.CO({\c_reg[12]_i_1_n_0 ,\c_reg[12]_i_1_n_1 ,\c_reg[12]_i_1_n_2 ,\c_reg[12]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[12]_i_1_n_4 ,\c_reg[12]_i_1_n_5 ,\c_reg[12]_i_1_n_6 ,\c_reg[12]_i_1_n_7 }),
.S({\c[12]_i_2_n_0 ,\c[12]_i_3_n_0 ,\c[12]_i_4_n_0 ,\c[12]_i_5_n_0 }));
FDRE \c_reg[13]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_6 ),
.Q(c_reg[13]),
.R(clear));
FDRE \c_reg[14]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_5 ),
.Q(c_reg[14]),
.R(clear));
FDRE \c_reg[15]
(.C(clk),
.CE(1'b1),
.D(\c_reg[12]_i_1_n_4 ),
.Q(c_reg[15]),
.R(clear));
FDRE \c_reg[16]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_7 ),
.Q(c_reg[16]),
.R(clear));
CARRY4 \c_reg[16]_i_1
(.CI(\c_reg[12]_i_1_n_0 ),
.CO({\c_reg[16]_i_1_n_0 ,\c_reg[16]_i_1_n_1 ,\c_reg[16]_i_1_n_2 ,\c_reg[16]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[16]_i_1_n_4 ,\c_reg[16]_i_1_n_5 ,\c_reg[16]_i_1_n_6 ,\c_reg[16]_i_1_n_7 }),
.S({\c[16]_i_2_n_0 ,\c[16]_i_3_n_0 ,\c[16]_i_4_n_0 ,\c[16]_i_5_n_0 }));
FDRE \c_reg[17]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_6 ),
.Q(c_reg[17]),
.R(clear));
FDRE \c_reg[18]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_5 ),
.Q(c_reg[18]),
.R(clear));
FDRE \c_reg[19]
(.C(clk),
.CE(1'b1),
.D(\c_reg[16]_i_1_n_4 ),
.Q(c_reg[19]),
.R(clear));
FDRE \c_reg[1]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_6 ),
.Q(c_reg[1]),
.R(clear));
FDRE \c_reg[20]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_7 ),
.Q(c_reg[20]),
.R(clear));
CARRY4 \c_reg[20]_i_1
(.CI(\c_reg[16]_i_1_n_0 ),
.CO({\NLW_c_reg[20]_i_1_CO_UNCONNECTED [3],\c_reg[20]_i_1_n_1 ,\c_reg[20]_i_1_n_2 ,\c_reg[20]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[20]_i_1_n_4 ,\c_reg[20]_i_1_n_5 ,\c_reg[20]_i_1_n_6 ,\c_reg[20]_i_1_n_7 }),
.S({\c[20]_i_2_n_0 ,\c[20]_i_3_n_0 ,\c[20]_i_4_n_0 ,\c[20]_i_5_n_0 }));
FDRE \c_reg[21]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_6 ),
.Q(c_reg[21]),
.R(clear));
FDRE \c_reg[22]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_5 ),
.Q(c_reg[22]),
.R(clear));
FDRE \c_reg[23]
(.C(clk),
.CE(1'b1),
.D(\c_reg[20]_i_1_n_4 ),
.Q(c_reg[23]),
.R(clear));
FDRE \c_reg[2]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_5 ),
.Q(c_reg[2]),
.R(clear));
FDRE \c_reg[3]
(.C(clk),
.CE(1'b1),
.D(\c_reg[0]_i_2_n_4 ),
.Q(c_reg[3]),
.R(clear));
FDRE \c_reg[4]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_7 ),
.Q(c_reg[4]),
.R(clear));
CARRY4 \c_reg[4]_i_1
(.CI(\c_reg[0]_i_2_n_0 ),
.CO({\c_reg[4]_i_1_n_0 ,\c_reg[4]_i_1_n_1 ,\c_reg[4]_i_1_n_2 ,\c_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[4]_i_1_n_4 ,\c_reg[4]_i_1_n_5 ,\c_reg[4]_i_1_n_6 ,\c_reg[4]_i_1_n_7 }),
.S({\c[4]_i_2_n_0 ,\c[4]_i_3_n_0 ,\c[4]_i_4_n_0 ,\c[4]_i_5_n_0 }));
FDRE \c_reg[5]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_6 ),
.Q(c_reg[5]),
.R(clear));
FDRE \c_reg[6]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_5 ),
.Q(c_reg[6]),
.R(clear));
FDRE \c_reg[7]
(.C(clk),
.CE(1'b1),
.D(\c_reg[4]_i_1_n_4 ),
.Q(c_reg[7]),
.R(clear));
FDRE \c_reg[8]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_7 ),
.Q(c_reg[8]),
.R(clear));
CARRY4 \c_reg[8]_i_1
(.CI(\c_reg[4]_i_1_n_0 ),
.CO({\c_reg[8]_i_1_n_0 ,\c_reg[8]_i_1_n_1 ,\c_reg[8]_i_1_n_2 ,\c_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\c_reg[8]_i_1_n_4 ,\c_reg[8]_i_1_n_5 ,\c_reg[8]_i_1_n_6 ,\c_reg[8]_i_1_n_7 }),
.S({\c[8]_i_2_n_0 ,\c[8]_i_3_n_0 ,\c[8]_i_4_n_0 ,\c[8]_i_5_n_0 }));
FDRE \c_reg[9]
(.C(clk),
.CE(1'b1),
.D(\c_reg[8]_i_1_n_6 ),
.Q(c_reg[9]),
.R(clear));
LUT5 #(
.INIT(32'h80000000))
signal_out_i_1
(.I0(signal_out_i_2_n_0),
.I1(signal_out_i_3_n_0),
.I2(signal_out_i_4_n_0),
.I3(c_reg[0]),
.I4(signal_out_i_5_n_0),
.O(signal_out_i_1_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_2
(.I0(c_reg[3]),
.I1(c_reg[4]),
.I2(c_reg[1]),
.I3(c_reg[2]),
.I4(c_reg[6]),
.I5(c_reg[5]),
.O(signal_out_i_2_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_3
(.I0(c_reg[21]),
.I1(c_reg[22]),
.I2(c_reg[19]),
.I3(c_reg[20]),
.I4(signal_in),
.I5(c_reg[23]),
.O(signal_out_i_3_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_4
(.I0(c_reg[15]),
.I1(c_reg[16]),
.I2(c_reg[13]),
.I3(c_reg[14]),
.I4(c_reg[18]),
.I5(c_reg[17]),
.O(signal_out_i_4_n_0));
LUT6 #(
.INIT(64'h8000000000000000))
signal_out_i_5
(.I0(c_reg[9]),
.I1(c_reg[10]),
.I2(c_reg[7]),
.I3(c_reg[8]),
.I4(c_reg[12]),
.I5(c_reg[11]),
.O(signal_out_i_5_n_0));
FDRE signal_out_reg
(.C(clk),
.CE(1'b1),
.D(signal_out_i_1_n_0),
.Q(signal_out),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_debounce_0_0,debounce,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "debounce,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_debounce_0_0
(clk,
signal_in,
signal_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input signal_in;
output signal_out;
wire clk;
wire signal_in;
wire signal_out;
system_debounce_0_0_debounce U0
(.clk(clk),
.signal_in(signal_in),
.signal_out(signal_out));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
/*
Group Members: Thomas Hudson and Warren Seto
Lab Name: Combinational Logic
Project Name: eng312_proj2
Design Name: four_bit_adder.v
Design Description: Verilog Module for Four Bit Ripple Adder using full_adder implementation
*/
module four_bit_adder
(
input [3:0] A,
input [3:0] B,
output [4:0] SUM
);
// The first carry is zero
wire CARRY0;
assign CARRY0 = 1'b0;
// Four full adders are combined together into one 4-bit ripple adder
full_adder op1 (A[0], B[0], CARRY0, SUM[0], CARRY1);
full_adder op2 (A[1], B[1], CARRY1, SUM[1], CARRY2);
full_adder op3 (A[2], B[2], CARRY2, SUM[2], CARRY3);
full_adder op4 (A[3], B[3], CARRY3, SUM[3], SUM[4]);
endmodule
// A full adder module that will be used in this 4-bit adder implementation
module full_adder
(
input A,
input B,
input CARRY_IN,
output SUM,
output CARRY_OUT
);
// This uses two exclusive OR (XOR) gates to SUM three inputs
assign SUM = (A ^ B) ^ CARRY_IN;
// This uses three OR gates to detect a CARRY_OUT from three inputs
assign CARRY_OUT = (A & ~B & CARRY_IN) | (~A & B & CARRY_IN) | (A & B);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__a32oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A32OI_BEHAVIORAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
// (c) Copyright 2008 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
///////////////////////////////////////////////////////////////////////////////
//
// RX_STREAM
//
//
// Description: The RX_LL module receives data from the Aurora Channel,
// converts it to a simple streaming format. This module expects
// all data to be carried in a single, infinite frame, and it
// expects the data data in lanes to be all valid or all invalid
//
// This module supports 4 2-byte lane designs.
//
//
`timescale 1 ns / 1 ps
module aur1_RX_STREAM
(
// LocalLink PDU Interface
RX_D,
RX_SRC_RDY_N,
// Global Logic Interface
START_RX,
// Aurora Lane Interface
RX_PAD,
RX_PE_DATA,
RX_PE_DATA_V,
RX_SCP,
RX_ECP,
// System Interface
USER_CLK
);
`define DLY #1
//***********************************Port Declarations*******************************
// LocalLink PDU Interface
output [0:63] RX_D;
output RX_SRC_RDY_N;
// Global Logic Interface
input START_RX;
// Aurora Lane Interface
input [0:3] RX_PAD;
input [0:63] RX_PE_DATA;
input [0:3] RX_PE_DATA_V;
input [0:3] RX_SCP;
input [0:3] RX_ECP;
// System Interface
input USER_CLK;
//************************Register Declarations********************
reg infinite_frame_started_r;
//***********************Main Body of Code*************************
//Don't start presenting data until the infinite frame starts
always @(posedge USER_CLK)
if(!START_RX)
infinite_frame_started_r <= `DLY 1'b0;
else if(RX_SCP > 4'd0)
infinite_frame_started_r <= `DLY 1'b1;
assign RX_D = RX_PE_DATA;
assign RX_SRC_RDY_N = !(RX_PE_DATA_V[0] && infinite_frame_started_r);
endmodule
|
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:54:55 02/16/2014
// Design Name:
// Module Name: ula
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ula_radas (
// Clocks
input wire clk28,
input wire clkregs, // clock to load registers
input wire clk14, // 14MHz master clock
input wire clk7,
input wire cpuclk,
output wire CPUContention,
input wire rst_n, // reset para volver al modo normal
// CPU interface
input wire [15:0] a,
input wire mreq_n,
input wire iorq_n,
input wire rd_n,
input wire wr_n,
output wire int_n,
input wire [7:0] din,
output reg [7:0] dout,
input wire rasterint_enable,
input wire vretraceint_disable,
input wire [8:0] raster_line,
output wire raster_int_in_progress,
// VRAM interface
output reg [13:0] va, // 16KB videoram
input wire [7:0] vramdata,
// ZX-UNO register interface
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire regaddr_changed,
// I/O ports
input wire ear,
input wire [4:0] kbd,
output reg mic,
output reg spk,
input wire issue2_keyboard,
input wire [1:0] mode,
input wire ioreqbank,
input wire disable_contention,
input wire access_to_contmem,
output wire doc_ext_option,
input wire enable_timexmmu,
input wire disable_timexscr,
input wire disable_ulaplus,
input wire disable_radas,
input wire csync_option,
// Video
output wire [2:0] r,
output wire [2:0] g,
output wire [2:0] b,
output wire hsync,
output wire vsync,
output wire csync,
output wire y_n
);
parameter
BHPIXEL = 0,
EHPIXEL = 255,
BVPIXEL = 0,
EVPIXEL = 191,
BVSYNC = 248;
parameter
ULA48K = 2'b00,
ULA128K = 2'b01,
PENTAGON = 2'b10,
RESERVED = 2'b11;
// RGB inputs to sync module
reg [2:0] ri;
reg [2:0] gi;
reg [2:0] bi;
// Counters from sync module
wire [8:0] hc;
wire [8:0] vc;
// Initial values for Radastanian mode pixel and border palette bank
reg radasborderpalettehalf = 1'b0;
reg [1:0] radaspixelpalettequarter = 2'b00;
// Initial values for synch, syncv for all supported timings
reg [8:0] hinit48k = 9'd112;
reg [8:0] vinit48k = 9'd0;
reg [8:0] hinit128k = 9'd116;
reg [8:0] vinit128k = 9'd0;
reg [8:0] hinitpen = 9'd110;
reg [8:0] vinitpen = 9'd0;
// Initial values for offset and padding in Radastanian mode, used for HW scroller
reg [13:0] radasoffset = 14'h0000;
reg [7:0] radaspadding = 8'h00;
reg ffbitmapofs = 1'b0;
reg [7:0] lastdatatoradasoffset = 8'h00;
// Signal when the vertical counter is in the line that we use to make the INT signal
wire in_int_line;
reg clkhalf14 = 1'b0;
always @(posedge clk14)
clkhalf14 <= ~clkhalf14;
pal_sync_generator syncs (
.clk(clk7),
.mode(mode),
.rasterint_enable(rasterint_enable),
.vretraceint_disable(vretraceint_disable),
.raster_line(raster_line),
.raster_int_in_progress(raster_int_in_progress),
.csync_option(csync_option),
.hinit48k(hinit48k),
.vinit48k(vinit48k),
.hinit128k(hinit128k),
.vinit128k(vinit128k),
.hinitpen(hinitpen),
.vinitpen(vinitpen),
.ri(ri),
.gi(gi),
.bi(bi),
.hcnt(hc),
.vcnt(vc),
.ro(r),
.go(g),
.bo(b),
.hsync(hsync),
.vsync(vsync),
.csync(csync),
.int_n(int_n)
);
///////////////////////////////////////////////
// ULA datapath
///////////////////////////////////////////////
// Control signals generated from the control unit
// or the rest of modules
reg BitmapDataLoad;
reg AttrDataLoad;
reg WriteToPortFE;
reg SerializerLoad;
reg TimexConfigLoad;
reg AttrOutputLoad;
reg PaletteRegLoad;
reg ConfigRegLoad;
reg PaletteLoad;
reg BitmapAddr;
reg AttrAddr;
reg CALoad;
reg VideoEnable;
wire RadasEnabled; // =1 is el modo radastaniano está habilitado
// BitmapData register
reg [7:0] BitmapData = 8'h00;
always @(posedge clk7) begin
if (BitmapDataLoad)
BitmapData <= vramdata;
end
// AttrData register
reg [7:0] AttrData = 8'h00;
always @(posedge clk7) begin
if (AttrDataLoad)
AttrData <= vramdata;
end
// Border register
reg [2:0] Border = 3'b010; // initial border colour is red
always @(posedge clkregs) begin
if (WriteToPortFE)
Border <= din[2:0];
end
// BitmapSerializer register
reg [7:0] BitmapSerializer = 8'h00;
wire SerialOutput = BitmapSerializer[7];
always @(posedge clk7) begin
if (SerializerLoad)
BitmapSerializer <= BitmapData;
else
BitmapSerializer <= {BitmapSerializer[6:0],1'b0};
end
// BitmapSerializerHR register
reg [15:0] BitmapSerializerHR = 8'h00;
wire SerialOutputHR = BitmapSerializerHR[15];
always @(posedge clk14) begin
if (SerializerLoad && clkhalf14) // load enable only for a single 14MHz cycle
BitmapSerializerHR <= {BitmapData,AttrData};
else
BitmapSerializerHR <= {BitmapSerializerHR[14:0],1'b0};
end
// Timex config register
reg [7:0] TimexConfigReg = 8'h00;
wire PG = TimexConfigReg[0];
wire HCL = TimexConfigReg[1];
wire HR = TimexConfigReg[2];
assign doc_ext_option = enable_timexmmu & TimexConfigReg[7];
wire [2:0] HRInk = TimexConfigReg[5:3];
always @(posedge clkregs) begin
if (rst_n == 1'b0)
TimexConfigReg <= 8'h00;
else if (TimexConfigLoad)
TimexConfigReg <= din;
end
// Combinational logic between AttrData and AttrOutput
reg [7:0] InputToAttrOutput;
always @* begin
InputToAttrOutput = AttrData;
case ({VideoEnable,HR})
2'b00 : InputToAttrOutput = (RadasEnabled)? {radasborderpalettehalf,Border,radasborderpalettehalf,Border} : {2'b00,Border,3'b000};
2'b01,
2'b11 : InputToAttrOutput = {2'b01,~HRInk,HRInk};
2'b10 : InputToAttrOutput = AttrData;
endcase
end
// AttrOutput register
reg [7:0] AttrOutput = 8'h00;
reg [7:0] BorderColorDelayed; // used to delay 0.5T the assignment from border to AttrOutput while in Pentagon mode
wire [2:0] StdPaperColour = AttrOutput[5:3];
wire [2:0] StdInkColour = AttrOutput[2:0];
wire Bright = AttrOutput[6];
wire Flash = AttrOutput[7];
always @(posedge clk7) begin
BorderColorDelayed <= {2'b00,Border,3'b000}; // update always BorderColorDelayed
if (mode == PENTAGON && (hc<(BHPIXEL+8) || hc>(EHPIXEL+12) || vc<BVPIXEL || vc>EVPIXEL))
AttrOutput <= BorderColorDelayed; // and in next pixel clock, update AttrOutput if in border and Pentagon mode is on
else if (AttrOutputLoad)
AttrOutput <= InputToAttrOutput;
end
// Combinational logic to generate pixel bit
reg Pixel;
always @* begin
if (HR)
Pixel = SerialOutputHR;
else
Pixel = SerialOutput;
end
// Flash!
reg [4:0] FlashCounter = 5'h00;
wire FlashFF = FlashCounter[4];
wire PixelWFlash = Pixel ^ (Flash & FlashFF);
always @(posedge clk7) begin
if (vc==BVSYNC && hc==0)
FlashCounter <= FlashCounter + 1;
end
// Standard ULA final 4-bit IGRB colour
reg [3:0] StdPixelColour;
always @* begin
if (PixelWFlash)
StdPixelColour = {Bright,StdInkColour};
else
StdPixelColour = {Bright,StdPaperColour};
end
// LUT-based translatator from IGRB to 9-bit GRB
`define none 3'b000
`define half 3'b101
`define full 3'b111
reg [8:0] Std9bitColour;
always @* begin
case (StdPixelColour) // speccy colour to GGGRRRBBB colour. If you want to alter the standard palette,
// this is what you need to touch ;)
0,8: Std9bitColour = {`none,`none,`none};
1: Std9bitColour = {`none,`none,`half};
2: Std9bitColour = {`none,`half,`none};
3: Std9bitColour = {`none,`half,`half};
4: Std9bitColour = {`half,`none,`none};
5: Std9bitColour = {`half,`none,`half};
6: Std9bitColour = {`half,`half,`none};
7: Std9bitColour = {`half,`half,`half};
9: Std9bitColour = {`none,`none,`full};
10: Std9bitColour = {`none,`full,`none};
11: Std9bitColour = {`none,`full,`full};
12: Std9bitColour = {`full,`none,`none};
13: Std9bitColour = {`full,`none,`full};
14: Std9bitColour = {`full,`full,`none};
15: Std9bitColour = {`full,`full,`full};
default: Std9bitColour = {`none,`none,`none};
endcase
end
// PaletteReg register (ULAplus)
reg [6:0] PaletteReg = 7'h00;
always @(posedge clkregs) begin
if (PaletteRegLoad)
PaletteReg <= din[6:0];
end
// ConfigReg register (ULAplus)
reg ConfigReg = 1'b0;
always @(posedge clkregs) begin
if (rst_n == 1'b0)
ConfigReg <= 1'b0;
else if (ConfigRegLoad)
ConfigReg <= din[0];
end
// RadasCtrl register
reg [1:0] RadasCtrl = 2'b00;
always @(posedge clkregs) begin
if (rst_n == 1'b0)
RadasCtrl <= 2'b00;
else if (zxuno_addr == RADASCTRL && zxuno_regwr == 1'b1 && disable_radas == 1'b0)
RadasCtrl <= din[1:0];
end
assign RadasEnabled = &RadasCtrl[1:0];
wire ULAplusEnabled = ConfigReg | RadasEnabled;
// Palette LUT
wire [7:0] PaletteEntryToCPU;
wire [7:0] ULAplusPaperColour;
wire [7:0] ULAplusInkColour;
wire [5:0] AddressA1 = (RadasEnabled)? {radaspixelpalettequarter,InputToAttrOutput[7:4]} :
{InputToAttrOutput[7:6],1'b1,InputToAttrOutput[5:3]};
wire [5:0] AddressA2 = (RadasEnabled)? {radaspixelpalettequarter,InputToAttrOutput[3:0]} :
{InputToAttrOutput[7:6],1'b0,InputToAttrOutput[2:0]};
lut palette (
.clk(clk28),
.load(PaletteLoad),
.din(din),
.a1(AddressA1),
.a2(AddressA2),
.a3(PaletteReg[5:0]),
.do1(ULAplusPaperColour),
.do2(ULAplusInkColour),
.do3(PaletteEntryToCPU)
);
// AttrPlusOutput register
reg [15:0] AttrPlusOutput = 16'h0000;
always @(posedge clk7) begin
if (AttrOutputLoad)
AttrPlusOutput <= {ULAplusPaperColour,ULAplusInkColour};
end
// ULAplus final 8-bit GGGRRRBB colour
reg [7:0] ULAplusPixelColour;
always @* begin
case ({RadasEnabled,hc[1],Pixel})
3'b000,
3'b010 : ULAplusPixelColour = AttrPlusOutput[15:8];
3'b001,
3'b011 : ULAplusPixelColour = AttrPlusOutput[7:0];
3'b100,
3'b101 : ULAplusPixelColour = AttrPlusOutput[15:8]; // pixel izquierdo del par
3'b110,
3'b111 : ULAplusPixelColour = AttrPlusOutput[7:0]; // pixel derecho del par
default : ULAplusPixelColour = AttrPlusOutput[15:8];
endcase
end
// 332-GRB to 333-GRB (blue turns from B1 B0 into B1 B0 B1)
wire [8:0] ULAplus9bitColour = {ULAplusPixelColour,ULAplusPixelColour[1]};
// Final stage. Final colour is connected to PAL generator
always @* begin
if (ULAplusEnabled) begin
gi = ULAplus9bitColour[8:6];
ri = ULAplus9bitColour[5:3];
bi = ULAplus9bitColour[2:0];
end
else begin
gi = Std9bitColour[8:6];
ri = Std9bitColour[5:3];
bi = Std9bitColour[2:0];
end
end
// Column address register (CA)
reg [4:0] CA = 5'h00;
always @(posedge clk7) begin
if (CALoad)
CA <= hc[7:3];
end
// VRAM Address generation
wire [8:0] hcd = hc + 9'hFF8; // hc delayed 8 ticks
always @* begin
if (!RadasEnabled) begin
if (BitmapAddr) begin
va = {PG,vc[7:6],vc[2:0],vc[5:3],CA};
end
else if (AttrAddr) begin
if (HCL==1'b0)
va = {PG,3'b110,vc[7:3],CA};
else
va = {1'b1,vc[7:6],vc[2:0],vc[5:3],CA};
end
else
va = 14'hZZZZ;
end
else begin
//va = {PG,vc[7:1],hcd[7:2]};
va = {PG,vc[7:1],hcd[7:2]} + radasoffset + vc[7:1]*radaspadding;
end
end
///////////////////////////////////////////////
// ULA control unit
///////////////////////////////////////////////
// control data flow from VRAM to RGB output
reg Border_n;
always @* begin
if (vc>=BVPIXEL && vc<=EVPIXEL && hc>=BHPIXEL && hc<=EHPIXEL)
Border_n = 1;
else
Border_n = 0;
end
always @* begin
BitmapDataLoad = 1'b0;
AttrDataLoad = 1'b0;
SerializerLoad = 1'b0;
VideoEnable = 1'b0;
AttrOutputLoad = 1'b0;
BitmapAddr = 1'b0;
AttrAddr = 1'b0;
CALoad = 1'b0;
if (!RadasEnabled) begin // Control para los modos estándar
if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin // VidEN_n is low here: paper area
VideoEnable = 1'b1;
if (hc[2:0]==3'd4) begin
SerializerLoad = 1'b1; // updated every 8 pixel clocks, if we are in paper area
end
end
if (hc[2:0] == 3'd4) begin // hc=4,12,20,28,etc
AttrOutputLoad = 1'b1; // updated every 8 pixel clocks
end
if (hc[2:0]==3'd3) begin
CALoad = 1'b1;
end
if (hc>=BHPIXEL && hc<=EHPIXEL && vc>=BVPIXEL && vc<=EVPIXEL) begin
if (hc[3:0]==4'd8 || hc[3:0]==4'd12) begin
BitmapAddr = 1'b1;
end
if (hc[3:0]==4'd9 || hc[3:0]==4'd13) begin
BitmapAddr = 1'b1;
BitmapDataLoad = 1'b1;
end
if (hc[3:0]==4'd10 || hc[3:0]==4'd14) begin
AttrAddr = 1'b1;
end
if (hc[3:0]==4'd11 || hc[3:0]==4'd15) begin
AttrAddr = 1'b1;
AttrDataLoad = 1'b1;
end
end
end
else begin // Control para el modo radastaniano
if (hc[1:0]==2'b11) begin // trasladamos dos píxeles a la salida
AttrOutputLoad = 1'b1;
end
if (hc>=(BHPIXEL+8) && hc<=(EHPIXEL+8) && vc>=BVPIXEL && vc<=EVPIXEL) begin // VidEN_n is low here: paper area
VideoEnable = 1'b1;
if (hc[1:0]==2'b01) begin // sólo durante video activo: se lee la memoria de pantalla
AttrDataLoad = 1'b1;
end
end
end
end
///////////////////////////////////////////////
// ULA interface with CPU
///////////////////////////////////////////////
parameter
TIMEXPORT = 8'hFF,
TIMEXMMU = 8'hF4,
ULAPLUSADDR = 16'hBF3B,
ULAPLUSDATA = 16'hFF3B;
parameter
HOFFS48K = 8'h80,
VOFFS48K = 8'h81,
HOFFS128K = 8'h82,
VOFFS128K = 8'h83,
HOFFSPEN = 8'h84,
VOFFSPEN = 8'h85;
parameter
RADASCTRL = 8'h40,
RADASOFFSET = 8'h41,
RADASPADDING = 8'h42,
RADASPALBANK = 8'h43;
// Z80 writes values into registers
// Port 0xFE
always @(posedge clkregs) begin
if (WriteToPortFE) begin
{spk,mic} <= din[4:3];
end
end
// TIMEX and ULAplus ports
always @* begin
TimexConfigLoad = 1'b0;
PaletteRegLoad = 1'b0;
ConfigRegLoad = 1'b0;
PaletteLoad = 1'b0;
WriteToPortFE = 1'b0;
if (iorq_n==1'b0 && wr_n==1'b0) begin
if (a[0]==1'b0 && a[7:0]!=TIMEXMMU)
WriteToPortFE = 1'b1;
else if (a[7:0]==TIMEXPORT && !disable_timexscr)
TimexConfigLoad = 1'b1;
else if (a==ULAPLUSADDR && !disable_ulaplus)
PaletteRegLoad = 1'b1;
else if (a==ULAPLUSDATA && !disable_ulaplus) begin
if (PaletteReg[6]==1'b0) // writting a new value into palette LUT
PaletteLoad = 1'b1;
else
ConfigRegLoad = 1'b1; // writting a new value into ULAplus config register
end
end
end
// Sync and radastanian palette adjustment
always @(posedge clkregs) begin
if (zxuno_regwr == 1'b1) begin
case (zxuno_addr)
HOFFS48K: hinit48k <= {din,1'b0};
VOFFS48K: vinit48k <= {din,1'b0};
HOFFS128K: hinit128k <= {din,1'b0};
VOFFS128K: vinit128k <= {din,1'b0};
HOFFSPEN: hinitpen <= {din,1'b0};
VOFFSPEN: vinitpen <= {din,1'b0};
RADASPALBANK: {radasborderpalettehalf,radaspixelpalettequarter} <= din[2:0];
endcase
end
end
// Control de offsets del modo radastaniano
reg offset_reg_accessed = 1'b0;
always @(posedge clkregs) begin
if (rst_n == 1'b0) begin
ffbitmapofs <= 1'b0;
radasoffset <= 14'h0000;
radaspadding <= 8'h00;
end
else begin
if (regaddr_changed && zxuno_addr == RADASOFFSET)
ffbitmapofs <= 1'b0;
else if (offset_reg_accessed == 1'b0 && zxuno_addr == RADASOFFSET && (zxuno_regrd == 1'b1 || zxuno_regwr == 1'b1)) begin
if (zxuno_regwr == 1'b1 && ffbitmapofs == 1'b0) begin
radasoffset[7:0] <= din;
end
else if (zxuno_regwr == 1'b1 && ffbitmapofs == 1'b1) begin
radasoffset[13:8] <= din[5:0];
end
else if (zxuno_regrd == 1'b1 && ffbitmapofs == 1'b0) begin
lastdatatoradasoffset <= radasoffset[7:0];
end
else if (zxuno_regrd == 1'b1 && ffbitmapofs == 1'b1) begin
lastdatatoradasoffset <= {2'b00,radasoffset[13:8]};
end
ffbitmapofs <= ~ffbitmapofs;
offset_reg_accessed <= 1'b1;
end
else if (zxuno_regwr == 1'b1 && zxuno_addr == RADASPADDING) begin
radaspadding <= din;
end
if (offset_reg_accessed == 1'b1 && zxuno_regwr == 1'b0 && zxuno_regwr == 1'b0)
offset_reg_accessed <= 1'b0;
end
end
reg post_processed_ear; // EAR signal after being altered by the keyboard current issue
always @* begin
if (issue2_keyboard)
post_processed_ear = ear ^ (spk | mic);
else
post_processed_ear = ear ^ spk;
end
// Z80 gets values from registers (or floating bus)
always @* begin
dout = 8'hFF;
if (iorq_n==1'b0 && rd_n==1'b0) begin
if (a[0]==1'b0 && a[7:0]!=8'hF4)
dout = {1'b1,post_processed_ear,1'b1,kbd};
else if (a==ULAPLUSADDR && !disable_ulaplus)
dout = {1'b0,PaletteReg};
else if (a==ULAPLUSDATA && PaletteReg[6]==1'b0 && !disable_ulaplus)
dout = PaletteEntryToCPU;
else if (a==ULAPLUSDATA && PaletteReg[6]==1'b1 && !disable_ulaplus)
dout = {7'b0000000,ConfigReg};
else if (a[7:0]==TIMEXPORT && enable_timexmmu && !disable_timexscr)
dout = TimexConfigReg;
else if (zxuno_addr == HOFFS48K && zxuno_regrd == 1'b1)
dout = hinit48k[8:1];
else if (zxuno_addr == VOFFS48K && zxuno_regrd == 1'b1)
dout = vinit48k[8:1];
else if (zxuno_addr == HOFFS128K && zxuno_regrd == 1'b1)
dout = hinit128k[8:1];
else if (zxuno_addr == VOFFS128K && zxuno_regrd == 1'b1)
dout = vinit128k[8:1];
else if (zxuno_addr == HOFFSPEN && zxuno_regrd == 1'b1)
dout = hinitpen[8:1];
else if (zxuno_addr == VOFFSPEN && zxuno_regrd == 1'b1)
dout = vinitpen[8:1];
else if (zxuno_addr == RADASCTRL && zxuno_regrd == 1'b1 && !disable_radas)
dout = {6'b000000,RadasCtrl};
else if (zxuno_addr == RADASOFFSET && zxuno_regrd == 1'b1 && !disable_radas)
dout = lastdatatoradasoffset;
else if (zxuno_addr == RADASPADDING && zxuno_regrd == 1'b1 && !disable_radas)
dout = radaspadding;
else if (zxuno_addr == RADASPALBANK && zxuno_regrd == 1'b1 && !disable_radas)
dout = {5'b00000, radasborderpalettehalf,radaspixelpalettequarter};
else begin
if (BitmapAddr || AttrAddr)
dout = vramdata;
else
dout = 8'hFF;
end
end
end
///////////////////////////////////
// AUXILIARY SIGNALS FOR CONTENTION CONTROL
///////////////////////////////////
wire iorequla = !iorq_n && (a[0]==0);
wire iorequlaplus = !iorq_n && (a==ULAPLUSADDR || a==ULAPLUSDATA);
wire ioreqall_n = !(iorequlaplus || iorequla || ioreqbank);
///////////////////////////////////
// CPU CLOCK GENERATION (Altwasser method)
///////////////////////////////////
//`define MASTERCPUCLK clk7
// reg ioreqtw3 = 0;
// reg mreqt23 = 0;
// wire N1y2 = ~access_to_contmem | ioreqall_n;
// wire N3 = hc[3:0]>=4'd4;
// wire N4 = ~Border_n | ~ioreqtw3 | ~mreqt23 | ~cpuclk;
// wire N5 = ~(N1y2 | N3 | N4);
// wire N6 = ~(hc[3:0]>=4'd4 | ~Border_n | ~cpuclk | ioreqall_n | ~ioreqtw3);
//
// always @(posedge cpuclk) begin
// ioreqtw3 <= ioreqall_n;
// mreqt23 <= mreq_n;
// end
//
// wire Nor1 = (~access_to_contmem & ioreqall_n) | (hc[3:0]<4'd12) |
// (~Border_n | ~ioreqtw3 | ~cpuclk | ~mreqt23);
// wire Nor2 = (hc[3:0]<4'd4) | ~Border_n | ~cpuclk | ioreqall_n | ~ioreqtw3;
// wire CLKContention = ~Nor1 | ~Nor2;
//
// always @(posedge cpuclk) begin
// if (!CLKContention) begin
// ioreqtw3 <= ioreqall_n;
// mreqt23 <= mreq_n;
// end
// end
//
// assign CPUContention = ~(!CLKContention || RadasEnabled || disable_contention);
///////////////////////////////////
// CPU CLOCK GENERATION (CSmith method)
///////////////////////////////////
reg MayContend_n;
always @(negedge clk7) begin // esto era negedge clk7 en el esquemático
if (hc[3:0]>4'd3 && Border_n==1'b1)
MayContend_n <= 1'b0;
else
MayContend_n <= 1'b1;
end
reg CauseContention_n;
always @* begin
if ((access_to_contmem || !ioreqall_n) && !RadasEnabled && !disable_contention)
CauseContention_n = 1'b0;
else
CauseContention_n = 1'b1;
end
reg CancelContention = 1'b1;
always @(posedge cpuclk) begin
if (!mreq_n || !ioreqall_n)
CancelContention <= 1'b1;
else
CancelContention <= 1'b0;
end
//assign cpuclk = (~(MayContend_n | CauseContention_n | CancelContention)) | hc[0];
assign CPUContention = (~(MayContend_n | CauseContention_n | CancelContention));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_MUX_2TO1_SYMBOL_V
`define SKY130_FD_SC_HS__UDP_MUX_2TO1_SYMBOL_V
/**
* udp_mux_2to1: Two to one multiplexer
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_mux_2to1 (
//# {{data|Data Signals}}
input A0,
input A1,
output X ,
//# {{control|Control Signals}}
input S
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_MUX_2TO1_SYMBOL_V
|
module font_rom(
input clk,
input [11:0] address,
output reg [7:0] out);
reg [7:0] font_rom [4095:0];
//Source file: Untitled.raw
//Size: 65536 bytes
//Output file: Untitled.raw.dat
//ASCII 0x00 ' '
initial begin : once
font_rom[0] <= 8'b00000000;
font_rom[1] <= 8'b00000000;
font_rom[2] <= 8'b00000000;
font_rom[3] <= 8'b00000000;
font_rom[4] <= 8'b00000000;
font_rom[5] <= 8'b00000000;
font_rom[6] <= 8'b00000000;
font_rom[7] <= 8'b00000000;
font_rom[8] <= 8'b00000000;
font_rom[9] <= 8'b00000000;
font_rom[10] <= 8'b00000000;
font_rom[11] <= 8'b00000000;
font_rom[12] <= 8'b00000000;
font_rom[13] <= 8'b00000000;
font_rom[14] <= 8'b00000000;
font_rom[15] <= 8'b00000000;
font_rom[16] <= 8'b00000000;
font_rom[17] <= 8'b00000000;
font_rom[18] <= 8'b00000000;
font_rom[19] <= 8'b00000000;
font_rom[20] <= 8'b00000000;
font_rom[21] <= 8'b00000000;
font_rom[22] <= 8'b00000000;
font_rom[23] <= 8'b00000000;
font_rom[24] <= 8'b00000000;
font_rom[25] <= 8'b00000000;
font_rom[26] <= 8'b00000000;
font_rom[27] <= 8'b00000000;
font_rom[28] <= 8'b00000000;
font_rom[29] <= 8'b00000000;
font_rom[30] <= 8'b00000000;
font_rom[31] <= 8'b00000000;
//ASCII 0x01 ' '
font_rom[32] <= 8'b00000000;
font_rom[33] <= 8'b00000000;
font_rom[34] <= 8'b00000000;
font_rom[35] <= 8'b00000000;
font_rom[36] <= 8'b00000000;
font_rom[37] <= 8'b00000000;
font_rom[38] <= 8'b00000000;
font_rom[39] <= 8'b00000000;
font_rom[40] <= 8'b00000000;
font_rom[41] <= 8'b00000000;
font_rom[42] <= 8'b00000000;
font_rom[43] <= 8'b00000000;
font_rom[44] <= 8'b00000000;
font_rom[45] <= 8'b00000000;
font_rom[46] <= 8'b00000000;
font_rom[47] <= 8'b00000000;
font_rom[48] <= 8'b00000000;
font_rom[49] <= 8'b00000000;
font_rom[50] <= 8'b00000000;
font_rom[51] <= 8'b00000000;
font_rom[52] <= 8'b00000000;
font_rom[53] <= 8'b00000000;
font_rom[54] <= 8'b00000000;
font_rom[55] <= 8'b00000000;
font_rom[56] <= 8'b00000000;
font_rom[57] <= 8'b00000000;
font_rom[58] <= 8'b00000000;
font_rom[59] <= 8'b00000000;
font_rom[60] <= 8'b00000000;
font_rom[61] <= 8'b00000000;
font_rom[62] <= 8'b00000000;
font_rom[63] <= 8'b00000000;
//ASCII 0x02 ' '
font_rom[64] <= 8'b00000000;
font_rom[65] <= 8'b00000000;
font_rom[66] <= 8'b00000000;
font_rom[67] <= 8'b00000000;
font_rom[68] <= 8'b00000000;
font_rom[69] <= 8'b00000000;
font_rom[70] <= 8'b00000000;
font_rom[71] <= 8'b00000000;
font_rom[72] <= 8'b00000000;
font_rom[73] <= 8'b00000000;
font_rom[74] <= 8'b00000000;
font_rom[75] <= 8'b00000000;
font_rom[76] <= 8'b00000000;
font_rom[77] <= 8'b00000000;
font_rom[78] <= 8'b00000000;
font_rom[79] <= 8'b00000000;
font_rom[80] <= 8'b00000000;
font_rom[81] <= 8'b00000000;
font_rom[82] <= 8'b00000000;
font_rom[83] <= 8'b00000000;
font_rom[84] <= 8'b00000111;
font_rom[85] <= 8'b10000000;
font_rom[86] <= 8'b00000000;
font_rom[87] <= 8'b10000000;
font_rom[88] <= 8'b00000000;
font_rom[89] <= 8'b10000000;
font_rom[90] <= 8'b00000000;
font_rom[91] <= 8'b10000000;
font_rom[92] <= 8'b00000000;
font_rom[93] <= 8'b10000000;
font_rom[94] <= 8'b00000000;
font_rom[95] <= 8'b10000000;
//ASCII 0x03 ' '
font_rom[96] <= 8'b00000000;
font_rom[97] <= 8'b00000000;
font_rom[98] <= 8'b00000000;
font_rom[99] <= 8'b00000000;
font_rom[100] <= 8'b00000000;
font_rom[101] <= 8'b00000000;
font_rom[102] <= 8'b00000000;
font_rom[103] <= 8'b00000000;
font_rom[104] <= 8'b00000000;
font_rom[105] <= 8'b10000000;
font_rom[106] <= 8'b00000000;
font_rom[107] <= 8'b10000000;
font_rom[108] <= 8'b00000000;
font_rom[109] <= 8'b10000000;
font_rom[110] <= 8'b00000000;
font_rom[111] <= 8'b10000000;
font_rom[112] <= 8'b00000000;
font_rom[113] <= 8'b10000000;
font_rom[114] <= 8'b00000000;
font_rom[115] <= 8'b10000000;
font_rom[116] <= 8'b00000000;
font_rom[117] <= 8'b11100000;
font_rom[118] <= 8'b00000000;
font_rom[119] <= 8'b00000000;
font_rom[120] <= 8'b00000000;
font_rom[121] <= 8'b00000000;
font_rom[122] <= 8'b00000000;
font_rom[123] <= 8'b00000000;
font_rom[124] <= 8'b00000000;
font_rom[125] <= 8'b00000000;
font_rom[126] <= 8'b00000000;
font_rom[127] <= 8'b00000000;
//ASCII 0x04 ' '
font_rom[128] <= 8'b00000000;
font_rom[129] <= 8'b00000000;
font_rom[130] <= 8'b00000000;
font_rom[131] <= 8'b00000000;
font_rom[132] <= 8'b00000000;
font_rom[133] <= 8'b00000000;
font_rom[134] <= 8'b00000000;
font_rom[135] <= 8'b00000000;
font_rom[136] <= 8'b00000000;
font_rom[137] <= 8'b10000000;
font_rom[138] <= 8'b00000000;
font_rom[139] <= 8'b10000000;
font_rom[140] <= 8'b00000000;
font_rom[141] <= 8'b10000000;
font_rom[142] <= 8'b00000000;
font_rom[143] <= 8'b10000000;
font_rom[144] <= 8'b00000000;
font_rom[145] <= 8'b10000000;
font_rom[146] <= 8'b00000000;
font_rom[147] <= 8'b10000000;
font_rom[148] <= 8'b00000111;
font_rom[149] <= 8'b10000000;
font_rom[150] <= 8'b00000000;
font_rom[151] <= 8'b00000000;
font_rom[152] <= 8'b00000000;
font_rom[153] <= 8'b00000000;
font_rom[154] <= 8'b00000000;
font_rom[155] <= 8'b00000000;
font_rom[156] <= 8'b00000000;
font_rom[157] <= 8'b00000000;
font_rom[158] <= 8'b00000000;
font_rom[159] <= 8'b00000000;
//ASCII 0x05 ' '
font_rom[160] <= 8'b00000000;
font_rom[161] <= 8'b00000000;
font_rom[162] <= 8'b00000000;
font_rom[163] <= 8'b00000000;
font_rom[164] <= 8'b00000000;
font_rom[165] <= 8'b00000000;
font_rom[166] <= 8'b00000000;
font_rom[167] <= 8'b00000000;
font_rom[168] <= 8'b00000000;
font_rom[169] <= 8'b10000000;
font_rom[170] <= 8'b00000000;
font_rom[171] <= 8'b10000000;
font_rom[172] <= 8'b00000000;
font_rom[173] <= 8'b10000000;
font_rom[174] <= 8'b00000000;
font_rom[175] <= 8'b10000000;
font_rom[176] <= 8'b00000000;
font_rom[177] <= 8'b10000000;
font_rom[178] <= 8'b00000000;
font_rom[179] <= 8'b10000000;
font_rom[180] <= 8'b00000000;
font_rom[181] <= 8'b10000000;
font_rom[182] <= 8'b00000000;
font_rom[183] <= 8'b10000000;
font_rom[184] <= 8'b00000000;
font_rom[185] <= 8'b10000000;
font_rom[186] <= 8'b00000000;
font_rom[187] <= 8'b10000000;
font_rom[188] <= 8'b00000000;
font_rom[189] <= 8'b10000000;
font_rom[190] <= 8'b00000000;
font_rom[191] <= 8'b10000000;
//ASCII 0x06 ' '
font_rom[192] <= 8'b00000000;
font_rom[193] <= 8'b00000000;
font_rom[194] <= 8'b00000000;
font_rom[195] <= 8'b00000000;
font_rom[196] <= 8'b00000000;
font_rom[197] <= 8'b00000000;
font_rom[198] <= 8'b00000000;
font_rom[199] <= 8'b00000000;
font_rom[200] <= 8'b00000000;
font_rom[201] <= 8'b00000000;
font_rom[202] <= 8'b00000000;
font_rom[203] <= 8'b00000000;
font_rom[204] <= 8'b00000000;
font_rom[205] <= 8'b00000000;
font_rom[206] <= 8'b00000000;
font_rom[207] <= 8'b00000000;
font_rom[208] <= 8'b00000000;
font_rom[209] <= 8'b00000000;
font_rom[210] <= 8'b00000000;
font_rom[211] <= 8'b00000000;
font_rom[212] <= 8'b00000111;
font_rom[213] <= 8'b11100000;
font_rom[214] <= 8'b00000000;
font_rom[215] <= 8'b00000000;
font_rom[216] <= 8'b00000000;
font_rom[217] <= 8'b00000000;
font_rom[218] <= 8'b00000000;
font_rom[219] <= 8'b00000000;
font_rom[220] <= 8'b00000000;
font_rom[221] <= 8'b00000000;
font_rom[222] <= 8'b00000000;
font_rom[223] <= 8'b00000000;
//ASCII 0x07 ' '
font_rom[224] <= 8'b00000000;
font_rom[225] <= 8'b00000000;
font_rom[226] <= 8'b00000000;
font_rom[227] <= 8'b00000000;
font_rom[228] <= 8'b00000000;
font_rom[229] <= 8'b00000000;
font_rom[230] <= 8'b00000000;
font_rom[231] <= 8'b00000000;
font_rom[232] <= 8'b00000000;
font_rom[233] <= 8'b00000000;
font_rom[234] <= 8'b00000000;
font_rom[235] <= 8'b00000000;
font_rom[236] <= 8'b00000000;
font_rom[237] <= 8'b00000000;
font_rom[238] <= 8'b00000001;
font_rom[239] <= 8'b10000000;
font_rom[240] <= 8'b00000011;
font_rom[241] <= 8'b11000000;
font_rom[242] <= 8'b00000011;
font_rom[243] <= 8'b11000000;
font_rom[244] <= 8'b00000011;
font_rom[245] <= 8'b11000000;
font_rom[246] <= 8'b00000001;
font_rom[247] <= 8'b10000000;
font_rom[248] <= 8'b00000000;
font_rom[249] <= 8'b00000000;
font_rom[250] <= 8'b00000000;
font_rom[251] <= 8'b00000000;
font_rom[252] <= 8'b00000000;
font_rom[253] <= 8'b00000000;
font_rom[254] <= 8'b00000000;
font_rom[255] <= 8'b00000000;
//ASCII 0x08 ' '
font_rom[256] <= 8'b00000000;
font_rom[257] <= 8'b00000000;
font_rom[258] <= 8'b00000000;
font_rom[259] <= 8'b00000000;
font_rom[260] <= 8'b00000000;
font_rom[261] <= 8'b00000000;
font_rom[262] <= 8'b00000000;
font_rom[263] <= 8'b00000000;
font_rom[264] <= 8'b00000111;
font_rom[265] <= 8'b11100000;
font_rom[266] <= 8'b00000111;
font_rom[267] <= 8'b11100000;
font_rom[268] <= 8'b00000111;
font_rom[269] <= 8'b11100000;
font_rom[270] <= 8'b00000110;
font_rom[271] <= 8'b01100000;
font_rom[272] <= 8'b00000100;
font_rom[273] <= 8'b00100000;
font_rom[274] <= 8'b00000100;
font_rom[275] <= 8'b00100000;
font_rom[276] <= 8'b00000100;
font_rom[277] <= 8'b00100000;
font_rom[278] <= 8'b00000110;
font_rom[279] <= 8'b01100000;
font_rom[280] <= 8'b00000111;
font_rom[281] <= 8'b11100000;
font_rom[282] <= 8'b00000111;
font_rom[283] <= 8'b11100000;
font_rom[284] <= 8'b00000111;
font_rom[285] <= 8'b11100000;
font_rom[286] <= 8'b00000111;
font_rom[287] <= 8'b11100000;
//ASCII 0x09 ' '
font_rom[288] <= 8'b00000000;
font_rom[289] <= 8'b00000000;
font_rom[290] <= 8'b00000000;
font_rom[291] <= 8'b00000000;
font_rom[292] <= 8'b00000000;
font_rom[293] <= 8'b00000000;
font_rom[294] <= 8'b00000000;
font_rom[295] <= 8'b00000000;
font_rom[296] <= 8'b00000000;
font_rom[297] <= 8'b00000000;
font_rom[298] <= 8'b00000000;
font_rom[299] <= 8'b00000000;
font_rom[300] <= 8'b00000000;
font_rom[301] <= 8'b00000000;
font_rom[302] <= 8'b00000000;
font_rom[303] <= 8'b00000000;
font_rom[304] <= 8'b00000000;
font_rom[305] <= 8'b00000000;
font_rom[306] <= 8'b00000000;
font_rom[307] <= 8'b00000000;
font_rom[308] <= 8'b00000000;
font_rom[309] <= 8'b00000000;
font_rom[310] <= 8'b00000000;
font_rom[311] <= 8'b00000000;
font_rom[312] <= 8'b00000000;
font_rom[313] <= 8'b00000000;
font_rom[314] <= 8'b00000000;
font_rom[315] <= 8'b00000000;
font_rom[316] <= 8'b00000000;
font_rom[317] <= 8'b00000000;
font_rom[318] <= 8'b00000000;
font_rom[319] <= 8'b00000000;
//ASCII 0x0A ' '
font_rom[320] <= 8'b00000000;
font_rom[321] <= 8'b00000000;
font_rom[322] <= 8'b00000000;
font_rom[323] <= 8'b00000000;
font_rom[324] <= 8'b00000000;
font_rom[325] <= 8'b00000000;
font_rom[326] <= 8'b00000000;
font_rom[327] <= 8'b00000000;
font_rom[328] <= 8'b00000000;
font_rom[329] <= 8'b00000000;
font_rom[330] <= 8'b00000000;
font_rom[331] <= 8'b00000000;
font_rom[332] <= 8'b00000000;
font_rom[333] <= 8'b00000000;
font_rom[334] <= 8'b00000000;
font_rom[335] <= 8'b00000000;
font_rom[336] <= 8'b00000000;
font_rom[337] <= 8'b00000000;
font_rom[338] <= 8'b00000000;
font_rom[339] <= 8'b00000000;
font_rom[340] <= 8'b00000000;
font_rom[341] <= 8'b00000000;
font_rom[342] <= 8'b00000000;
font_rom[343] <= 8'b00000000;
font_rom[344] <= 8'b00000000;
font_rom[345] <= 8'b00000000;
font_rom[346] <= 8'b00000000;
font_rom[347] <= 8'b00000000;
font_rom[348] <= 8'b00000000;
font_rom[349] <= 8'b00000000;
font_rom[350] <= 8'b00000000;
font_rom[351] <= 8'b00000000;
//ASCII 0x0B ' '
font_rom[352] <= 8'b00000000;
font_rom[353] <= 8'b00000000;
font_rom[354] <= 8'b00000000;
font_rom[355] <= 8'b00000000;
font_rom[356] <= 8'b00000000;
font_rom[357] <= 8'b00000000;
font_rom[358] <= 8'b00000000;
font_rom[359] <= 8'b00000000;
font_rom[360] <= 8'b00000000;
font_rom[361] <= 8'b00000000;
font_rom[362] <= 8'b00000000;
font_rom[363] <= 8'b11100000;
font_rom[364] <= 8'b00000000;
font_rom[365] <= 8'b01100000;
font_rom[366] <= 8'b00000000;
font_rom[367] <= 8'b01100000;
font_rom[368] <= 8'b00000000;
font_rom[369] <= 8'b10100000;
font_rom[370] <= 8'b00000000;
font_rom[371] <= 8'b10000000;
font_rom[372] <= 8'b00000001;
font_rom[373] <= 8'b10000000;
font_rom[374] <= 8'b00000010;
font_rom[375] <= 8'b01000000;
font_rom[376] <= 8'b00000010;
font_rom[377] <= 8'b01000000;
font_rom[378] <= 8'b00000001;
font_rom[379] <= 8'b10000000;
font_rom[380] <= 8'b00000000;
font_rom[381] <= 8'b00000000;
font_rom[382] <= 8'b00000000;
font_rom[383] <= 8'b00000000;
//ASCII 0x0C ' '
font_rom[384] <= 8'b00000000;
font_rom[385] <= 8'b00000000;
font_rom[386] <= 8'b00000000;
font_rom[387] <= 8'b00000000;
font_rom[388] <= 8'b00000000;
font_rom[389] <= 8'b00000000;
font_rom[390] <= 8'b00000000;
font_rom[391] <= 8'b00000000;
font_rom[392] <= 8'b00000000;
font_rom[393] <= 8'b00000000;
font_rom[394] <= 8'b00000001;
font_rom[395] <= 8'b11000000;
font_rom[396] <= 8'b00000010;
font_rom[397] <= 8'b00100000;
font_rom[398] <= 8'b00000010;
font_rom[399] <= 8'b00100000;
font_rom[400] <= 8'b00000001;
font_rom[401] <= 8'b11000000;
font_rom[402] <= 8'b00000000;
font_rom[403] <= 8'b10000000;
font_rom[404] <= 8'b00000011;
font_rom[405] <= 8'b11100000;
font_rom[406] <= 8'b00000000;
font_rom[407] <= 8'b10000000;
font_rom[408] <= 8'b00000000;
font_rom[409] <= 8'b10000000;
font_rom[410] <= 8'b00000000;
font_rom[411] <= 8'b10000000;
font_rom[412] <= 8'b00000000;
font_rom[413] <= 8'b00000000;
font_rom[414] <= 8'b00000000;
font_rom[415] <= 8'b00000000;
//ASCII 0x0D ' '
font_rom[416] <= 8'b00000000;
font_rom[417] <= 8'b00000000;
font_rom[418] <= 8'b00000000;
font_rom[419] <= 8'b00000000;
font_rom[420] <= 8'b00000000;
font_rom[421] <= 8'b00000000;
font_rom[422] <= 8'b00000000;
font_rom[423] <= 8'b00000000;
font_rom[424] <= 8'b00000000;
font_rom[425] <= 8'b00000000;
font_rom[426] <= 8'b00000000;
font_rom[427] <= 8'b00000000;
font_rom[428] <= 8'b00000000;
font_rom[429] <= 8'b00000000;
font_rom[430] <= 8'b00000000;
font_rom[431] <= 8'b00000000;
font_rom[432] <= 8'b00000000;
font_rom[433] <= 8'b00000000;
font_rom[434] <= 8'b00000000;
font_rom[435] <= 8'b00000000;
font_rom[436] <= 8'b00000000;
font_rom[437] <= 8'b00000000;
font_rom[438] <= 8'b00000000;
font_rom[439] <= 8'b00000000;
font_rom[440] <= 8'b00000000;
font_rom[441] <= 8'b00000000;
font_rom[442] <= 8'b00000000;
font_rom[443] <= 8'b00000000;
font_rom[444] <= 8'b00000000;
font_rom[445] <= 8'b00000000;
font_rom[446] <= 8'b00000000;
font_rom[447] <= 8'b00000000;
//ASCII 0x0E ' '
font_rom[448] <= 8'b00000000;
font_rom[449] <= 8'b00000000;
font_rom[450] <= 8'b00000000;
font_rom[451] <= 8'b00000000;
font_rom[452] <= 8'b00000000;
font_rom[453] <= 8'b00000000;
font_rom[454] <= 8'b00000000;
font_rom[455] <= 8'b00000000;
font_rom[456] <= 8'b00000000;
font_rom[457] <= 8'b00000000;
font_rom[458] <= 8'b00000000;
font_rom[459] <= 8'b01100000;
font_rom[460] <= 8'b00000001;
font_rom[461] <= 8'b10100000;
font_rom[462] <= 8'b00000001;
font_rom[463] <= 8'b01100000;
font_rom[464] <= 8'b00000001;
font_rom[465] <= 8'b10100000;
font_rom[466] <= 8'b00000001;
font_rom[467] <= 8'b00100000;
font_rom[468] <= 8'b00000001;
font_rom[469] <= 8'b00100000;
font_rom[470] <= 8'b00000001;
font_rom[471] <= 8'b01100000;
font_rom[472] <= 8'b00000011;
font_rom[473] <= 8'b01100000;
font_rom[474] <= 8'b00000011;
font_rom[475] <= 8'b00000000;
font_rom[476] <= 8'b00000000;
font_rom[477] <= 8'b00000000;
font_rom[478] <= 8'b00000000;
font_rom[479] <= 8'b00000000;
//ASCII 0x0F ' '
font_rom[480] <= 8'b00000000;
font_rom[481] <= 8'b00000000;
font_rom[482] <= 8'b00000000;
font_rom[483] <= 8'b00000000;
font_rom[484] <= 8'b00000000;
font_rom[485] <= 8'b00000000;
font_rom[486] <= 8'b00000000;
font_rom[487] <= 8'b00000000;
font_rom[488] <= 8'b00000000;
font_rom[489] <= 8'b00000000;
font_rom[490] <= 8'b00000010;
font_rom[491] <= 8'b10100000;
font_rom[492] <= 8'b00000010;
font_rom[493] <= 8'b10100000;
font_rom[494] <= 8'b00000001;
font_rom[495] <= 8'b01000000;
font_rom[496] <= 8'b00000001;
font_rom[497] <= 8'b01000000;
font_rom[498] <= 8'b00000011;
font_rom[499] <= 8'b01100000;
font_rom[500] <= 8'b00000001;
font_rom[501] <= 8'b01000000;
font_rom[502] <= 8'b00000001;
font_rom[503] <= 8'b01000000;
font_rom[504] <= 8'b00000010;
font_rom[505] <= 8'b10100000;
font_rom[506] <= 8'b00000010;
font_rom[507] <= 8'b10100000;
font_rom[508] <= 8'b00000000;
font_rom[509] <= 8'b00000000;
font_rom[510] <= 8'b00000000;
font_rom[511] <= 8'b00000000;
//ASCII 0x10 ' '
font_rom[512] <= 8'b00000000;
font_rom[513] <= 8'b00000000;
font_rom[514] <= 8'b00000000;
font_rom[515] <= 8'b00000000;
font_rom[516] <= 8'b00000000;
font_rom[517] <= 8'b00000000;
font_rom[518] <= 8'b00000000;
font_rom[519] <= 8'b00000000;
font_rom[520] <= 8'b00000000;
font_rom[521] <= 8'b10000000;
font_rom[522] <= 8'b00000000;
font_rom[523] <= 8'b10000000;
font_rom[524] <= 8'b00000000;
font_rom[525] <= 8'b10000000;
font_rom[526] <= 8'b00000000;
font_rom[527] <= 8'b10000000;
font_rom[528] <= 8'b00000000;
font_rom[529] <= 8'b10000000;
font_rom[530] <= 8'b00000000;
font_rom[531] <= 8'b10000000;
font_rom[532] <= 8'b00000111;
font_rom[533] <= 8'b11100000;
font_rom[534] <= 8'b00000000;
font_rom[535] <= 8'b10000000;
font_rom[536] <= 8'b00000000;
font_rom[537] <= 8'b10000000;
font_rom[538] <= 8'b00000000;
font_rom[539] <= 8'b10000000;
font_rom[540] <= 8'b00000000;
font_rom[541] <= 8'b10000000;
font_rom[542] <= 8'b00000000;
font_rom[543] <= 8'b10000000;
//ASCII 0x11 ' '
font_rom[544] <= 8'b00000000;
font_rom[545] <= 8'b00000000;
font_rom[546] <= 8'b00000000;
font_rom[547] <= 8'b00000000;
font_rom[548] <= 8'b00000000;
font_rom[549] <= 8'b00000000;
font_rom[550] <= 8'b00000000;
font_rom[551] <= 8'b00000000;
font_rom[552] <= 8'b00000000;
font_rom[553] <= 8'b00000000;
font_rom[554] <= 8'b00000000;
font_rom[555] <= 8'b00100000;
font_rom[556] <= 8'b00000000;
font_rom[557] <= 8'b01100000;
font_rom[558] <= 8'b00000000;
font_rom[559] <= 8'b11100000;
font_rom[560] <= 8'b00000001;
font_rom[561] <= 8'b11100000;
font_rom[562] <= 8'b00000011;
font_rom[563] <= 8'b11100000;
font_rom[564] <= 8'b00000001;
font_rom[565] <= 8'b11100000;
font_rom[566] <= 8'b00000000;
font_rom[567] <= 8'b11100000;
font_rom[568] <= 8'b00000000;
font_rom[569] <= 8'b01100000;
font_rom[570] <= 8'b00000000;
font_rom[571] <= 8'b00100000;
font_rom[572] <= 8'b00000000;
font_rom[573] <= 8'b00000000;
font_rom[574] <= 8'b00000000;
font_rom[575] <= 8'b00000000;
//ASCII 0x12 ' '
font_rom[576] <= 8'b00000000;
font_rom[577] <= 8'b00000000;
font_rom[578] <= 8'b00000000;
font_rom[579] <= 8'b00000000;
font_rom[580] <= 8'b00000000;
font_rom[581] <= 8'b00000000;
font_rom[582] <= 8'b00000000;
font_rom[583] <= 8'b00000000;
font_rom[584] <= 8'b00000000;
font_rom[585] <= 8'b10000000;
font_rom[586] <= 8'b00000001;
font_rom[587] <= 8'b11000000;
font_rom[588] <= 8'b00000000;
font_rom[589] <= 8'b10000000;
font_rom[590] <= 8'b00000000;
font_rom[591] <= 8'b10000000;
font_rom[592] <= 8'b00000000;
font_rom[593] <= 8'b10000000;
font_rom[594] <= 8'b00000000;
font_rom[595] <= 8'b10000000;
font_rom[596] <= 8'b00000000;
font_rom[597] <= 8'b10000000;
font_rom[598] <= 8'b00000000;
font_rom[599] <= 8'b10000000;
font_rom[600] <= 8'b00000001;
font_rom[601] <= 8'b11000000;
font_rom[602] <= 8'b00000000;
font_rom[603] <= 8'b10000000;
font_rom[604] <= 8'b00000000;
font_rom[605] <= 8'b00000000;
font_rom[606] <= 8'b00000000;
font_rom[607] <= 8'b00000000;
//ASCII 0x13 ' '
font_rom[608] <= 8'b00000000;
font_rom[609] <= 8'b00000000;
font_rom[610] <= 8'b00000000;
font_rom[611] <= 8'b00000000;
font_rom[612] <= 8'b00000000;
font_rom[613] <= 8'b00000000;
font_rom[614] <= 8'b00000000;
font_rom[615] <= 8'b00000000;
font_rom[616] <= 8'b00000001;
font_rom[617] <= 8'b01000000;
font_rom[618] <= 8'b00000001;
font_rom[619] <= 8'b01000000;
font_rom[620] <= 8'b00000001;
font_rom[621] <= 8'b01000000;
font_rom[622] <= 8'b00000001;
font_rom[623] <= 8'b01000000;
font_rom[624] <= 8'b00000001;
font_rom[625] <= 8'b01000000;
font_rom[626] <= 8'b00000001;
font_rom[627] <= 8'b01000000;
font_rom[628] <= 8'b00000001;
font_rom[629] <= 8'b01000000;
font_rom[630] <= 8'b00000000;
font_rom[631] <= 8'b00000000;
font_rom[632] <= 8'b00000001;
font_rom[633] <= 8'b01000000;
font_rom[634] <= 8'b00000001;
font_rom[635] <= 8'b01000000;
font_rom[636] <= 8'b00000000;
font_rom[637] <= 8'b00000000;
font_rom[638] <= 8'b00000000;
font_rom[639] <= 8'b00000000;
//ASCII 0x14 ' '
font_rom[640] <= 8'b00000000;
font_rom[641] <= 8'b00000000;
font_rom[642] <= 8'b00000000;
font_rom[643] <= 8'b00000000;
font_rom[644] <= 8'b00000000;
font_rom[645] <= 8'b00000000;
font_rom[646] <= 8'b00000000;
font_rom[647] <= 8'b00000000;
font_rom[648] <= 8'b00000001;
font_rom[649] <= 8'b11100000;
font_rom[650] <= 8'b00000010;
font_rom[651] <= 8'b10100000;
font_rom[652] <= 8'b00000010;
font_rom[653] <= 8'b10100000;
font_rom[654] <= 8'b00000010;
font_rom[655] <= 8'b10100000;
font_rom[656] <= 8'b00000001;
font_rom[657] <= 8'b10100000;
font_rom[658] <= 8'b00000000;
font_rom[659] <= 8'b10100000;
font_rom[660] <= 8'b00000000;
font_rom[661] <= 8'b10100000;
font_rom[662] <= 8'b00000000;
font_rom[663] <= 8'b10100000;
font_rom[664] <= 8'b00000000;
font_rom[665] <= 8'b10100000;
font_rom[666] <= 8'b00000000;
font_rom[667] <= 8'b10100000;
font_rom[668] <= 8'b00000000;
font_rom[669] <= 8'b00000000;
font_rom[670] <= 8'b00000000;
font_rom[671] <= 8'b00000000;
//ASCII 0x15 ' '
font_rom[672] <= 8'b00000000;
font_rom[673] <= 8'b00000000;
font_rom[674] <= 8'b00000000;
font_rom[675] <= 8'b00000000;
font_rom[676] <= 8'b00000000;
font_rom[677] <= 8'b00000000;
font_rom[678] <= 8'b00000000;
font_rom[679] <= 8'b00000000;
font_rom[680] <= 8'b00000000;
font_rom[681] <= 8'b10000000;
font_rom[682] <= 8'b00000000;
font_rom[683] <= 8'b10000000;
font_rom[684] <= 8'b00000000;
font_rom[685] <= 8'b10000000;
font_rom[686] <= 8'b00000000;
font_rom[687] <= 8'b10000000;
font_rom[688] <= 8'b00000000;
font_rom[689] <= 8'b10000000;
font_rom[690] <= 8'b00000000;
font_rom[691] <= 8'b10000000;
font_rom[692] <= 8'b00000111;
font_rom[693] <= 8'b11100000;
font_rom[694] <= 8'b00000000;
font_rom[695] <= 8'b00000000;
font_rom[696] <= 8'b00000000;
font_rom[697] <= 8'b00000000;
font_rom[698] <= 8'b00000000;
font_rom[699] <= 8'b00000000;
font_rom[700] <= 8'b00000000;
font_rom[701] <= 8'b00000000;
font_rom[702] <= 8'b00000000;
font_rom[703] <= 8'b00000000;
//ASCII 0x16 ' '
font_rom[704] <= 8'b00000000;
font_rom[705] <= 8'b00000000;
font_rom[706] <= 8'b00000000;
font_rom[707] <= 8'b00000000;
font_rom[708] <= 8'b00000000;
font_rom[709] <= 8'b00000000;
font_rom[710] <= 8'b00000000;
font_rom[711] <= 8'b00000000;
font_rom[712] <= 8'b00000000;
font_rom[713] <= 8'b00000000;
font_rom[714] <= 8'b00000000;
font_rom[715] <= 8'b00000000;
font_rom[716] <= 8'b00000000;
font_rom[717] <= 8'b00000000;
font_rom[718] <= 8'b00000000;
font_rom[719] <= 8'b00000000;
font_rom[720] <= 8'b00000000;
font_rom[721] <= 8'b00000000;
font_rom[722] <= 8'b00000000;
font_rom[723] <= 8'b00000000;
font_rom[724] <= 8'b00000111;
font_rom[725] <= 8'b11100000;
font_rom[726] <= 8'b00000000;
font_rom[727] <= 8'b10000000;
font_rom[728] <= 8'b00000000;
font_rom[729] <= 8'b10000000;
font_rom[730] <= 8'b00000000;
font_rom[731] <= 8'b10000000;
font_rom[732] <= 8'b00000000;
font_rom[733] <= 8'b10000000;
font_rom[734] <= 8'b00000000;
font_rom[735] <= 8'b10000000;
//ASCII 0x17 ' '
font_rom[736] <= 8'b00000000;
font_rom[737] <= 8'b00000000;
font_rom[738] <= 8'b00000000;
font_rom[739] <= 8'b00000000;
font_rom[740] <= 8'b00000000;
font_rom[741] <= 8'b00000000;
font_rom[742] <= 8'b00000000;
font_rom[743] <= 8'b00000000;
font_rom[744] <= 8'b00000000;
font_rom[745] <= 8'b10000000;
font_rom[746] <= 8'b00000000;
font_rom[747] <= 8'b10000000;
font_rom[748] <= 8'b00000000;
font_rom[749] <= 8'b10000000;
font_rom[750] <= 8'b00000000;
font_rom[751] <= 8'b10000000;
font_rom[752] <= 8'b00000000;
font_rom[753] <= 8'b10000000;
font_rom[754] <= 8'b00000000;
font_rom[755] <= 8'b10000000;
font_rom[756] <= 8'b00000111;
font_rom[757] <= 8'b10000000;
font_rom[758] <= 8'b00000000;
font_rom[759] <= 8'b10000000;
font_rom[760] <= 8'b00000000;
font_rom[761] <= 8'b10000000;
font_rom[762] <= 8'b00000000;
font_rom[763] <= 8'b10000000;
font_rom[764] <= 8'b00000000;
font_rom[765] <= 8'b10000000;
font_rom[766] <= 8'b00000000;
font_rom[767] <= 8'b10000000;
//ASCII 0x18 ' '
font_rom[768] <= 8'b00000000;
font_rom[769] <= 8'b00000000;
font_rom[770] <= 8'b00000000;
font_rom[771] <= 8'b00000000;
font_rom[772] <= 8'b00000000;
font_rom[773] <= 8'b00000000;
font_rom[774] <= 8'b00000000;
font_rom[775] <= 8'b00000000;
font_rom[776] <= 8'b00000000;
font_rom[777] <= 8'b10000000;
font_rom[778] <= 8'b00000001;
font_rom[779] <= 8'b11000000;
font_rom[780] <= 8'b00000000;
font_rom[781] <= 8'b10000000;
font_rom[782] <= 8'b00000000;
font_rom[783] <= 8'b10000000;
font_rom[784] <= 8'b00000000;
font_rom[785] <= 8'b10000000;
font_rom[786] <= 8'b00000000;
font_rom[787] <= 8'b10000000;
font_rom[788] <= 8'b00000000;
font_rom[789] <= 8'b10000000;
font_rom[790] <= 8'b00000000;
font_rom[791] <= 8'b10000000;
font_rom[792] <= 8'b00000000;
font_rom[793] <= 8'b10000000;
font_rom[794] <= 8'b00000000;
font_rom[795] <= 8'b10000000;
font_rom[796] <= 8'b00000000;
font_rom[797] <= 8'b00000000;
font_rom[798] <= 8'b00000000;
font_rom[799] <= 8'b00000000;
//ASCII 0x19 ' '
font_rom[800] <= 8'b00000000;
font_rom[801] <= 8'b00000000;
font_rom[802] <= 8'b00000000;
font_rom[803] <= 8'b00000000;
font_rom[804] <= 8'b00000000;
font_rom[805] <= 8'b00000000;
font_rom[806] <= 8'b00000000;
font_rom[807] <= 8'b00000000;
font_rom[808] <= 8'b00000000;
font_rom[809] <= 8'b10000000;
font_rom[810] <= 8'b00000000;
font_rom[811] <= 8'b10000000;
font_rom[812] <= 8'b00000000;
font_rom[813] <= 8'b10000000;
font_rom[814] <= 8'b00000000;
font_rom[815] <= 8'b10000000;
font_rom[816] <= 8'b00000000;
font_rom[817] <= 8'b10000000;
font_rom[818] <= 8'b00000000;
font_rom[819] <= 8'b10000000;
font_rom[820] <= 8'b00000000;
font_rom[821] <= 8'b11100000;
font_rom[822] <= 8'b00000000;
font_rom[823] <= 8'b10000000;
font_rom[824] <= 8'b00000000;
font_rom[825] <= 8'b10000000;
font_rom[826] <= 8'b00000000;
font_rom[827] <= 8'b10000000;
font_rom[828] <= 8'b00000000;
font_rom[829] <= 8'b10000000;
font_rom[830] <= 8'b00000000;
font_rom[831] <= 8'b10000000;
//ASCII 0x1A ' '
font_rom[832] <= 8'b00000000;
font_rom[833] <= 8'b00000000;
font_rom[834] <= 8'b00000000;
font_rom[835] <= 8'b00000000;
font_rom[836] <= 8'b00000000;
font_rom[837] <= 8'b00000000;
font_rom[838] <= 8'b00000000;
font_rom[839] <= 8'b00000000;
font_rom[840] <= 8'b00000000;
font_rom[841] <= 8'b00000000;
font_rom[842] <= 8'b00000000;
font_rom[843] <= 8'b00000000;
font_rom[844] <= 8'b00000000;
font_rom[845] <= 8'b00000000;
font_rom[846] <= 8'b00000000;
font_rom[847] <= 8'b00000000;
font_rom[848] <= 8'b00000000;
font_rom[849] <= 8'b01000000;
font_rom[850] <= 8'b00000011;
font_rom[851] <= 8'b11100000;
font_rom[852] <= 8'b00000000;
font_rom[853] <= 8'b01000000;
font_rom[854] <= 8'b00000000;
font_rom[855] <= 8'b00000000;
font_rom[856] <= 8'b00000000;
font_rom[857] <= 8'b00000000;
font_rom[858] <= 8'b00000000;
font_rom[859] <= 8'b00000000;
font_rom[860] <= 8'b00000000;
font_rom[861] <= 8'b00000000;
font_rom[862] <= 8'b00000000;
font_rom[863] <= 8'b00000000;
//ASCII 0x1B ' '
font_rom[864] <= 8'b00000000;
font_rom[865] <= 8'b00000000;
font_rom[866] <= 8'b00000000;
font_rom[867] <= 8'b00000000;
font_rom[868] <= 8'b00000000;
font_rom[869] <= 8'b00000000;
font_rom[870] <= 8'b00000000;
font_rom[871] <= 8'b00000000;
font_rom[872] <= 8'b00000000;
font_rom[873] <= 8'b00000000;
font_rom[874] <= 8'b00000000;
font_rom[875] <= 8'b00000000;
font_rom[876] <= 8'b00000000;
font_rom[877] <= 8'b00000000;
font_rom[878] <= 8'b00000000;
font_rom[879] <= 8'b00000000;
font_rom[880] <= 8'b00000001;
font_rom[881] <= 8'b00000000;
font_rom[882] <= 8'b00000011;
font_rom[883] <= 8'b11100000;
font_rom[884] <= 8'b00000001;
font_rom[885] <= 8'b00000000;
font_rom[886] <= 8'b00000000;
font_rom[887] <= 8'b00000000;
font_rom[888] <= 8'b00000000;
font_rom[889] <= 8'b00000000;
font_rom[890] <= 8'b00000000;
font_rom[891] <= 8'b00000000;
font_rom[892] <= 8'b00000000;
font_rom[893] <= 8'b00000000;
font_rom[894] <= 8'b00000000;
font_rom[895] <= 8'b00000000;
//ASCII 0x1C ' '
font_rom[896] <= 8'b00000000;
font_rom[897] <= 8'b00000000;
font_rom[898] <= 8'b00000000;
font_rom[899] <= 8'b00000000;
font_rom[900] <= 8'b00000000;
font_rom[901] <= 8'b00000000;
font_rom[902] <= 8'b00000000;
font_rom[903] <= 8'b00000000;
font_rom[904] <= 8'b00000000;
font_rom[905] <= 8'b00000000;
font_rom[906] <= 8'b00000000;
font_rom[907] <= 8'b00000000;
font_rom[908] <= 8'b00000000;
font_rom[909] <= 8'b00000000;
font_rom[910] <= 8'b00000000;
font_rom[911] <= 8'b00000000;
font_rom[912] <= 8'b00000000;
font_rom[913] <= 8'b00000000;
font_rom[914] <= 8'b00000000;
font_rom[915] <= 8'b00000000;
font_rom[916] <= 8'b00000000;
font_rom[917] <= 8'b00000000;
font_rom[918] <= 8'b00000000;
font_rom[919] <= 8'b00000000;
font_rom[920] <= 8'b00000000;
font_rom[921] <= 8'b00000000;
font_rom[922] <= 8'b00000000;
font_rom[923] <= 8'b00000000;
font_rom[924] <= 8'b00000000;
font_rom[925] <= 8'b00000000;
font_rom[926] <= 8'b00000000;
font_rom[927] <= 8'b00000000;
//ASCII 0x1D ' '
font_rom[928] <= 8'b00000000;
font_rom[929] <= 8'b00000000;
font_rom[930] <= 8'b00000000;
font_rom[931] <= 8'b00000000;
font_rom[932] <= 8'b00000000;
font_rom[933] <= 8'b00000000;
font_rom[934] <= 8'b00000000;
font_rom[935] <= 8'b00000000;
font_rom[936] <= 8'b00000000;
font_rom[937] <= 8'b00000000;
font_rom[938] <= 8'b00000000;
font_rom[939] <= 8'b00000000;
font_rom[940] <= 8'b00000000;
font_rom[941] <= 8'b00000000;
font_rom[942] <= 8'b00000000;
font_rom[943] <= 8'b00000000;
font_rom[944] <= 8'b00000000;
font_rom[945] <= 8'b00000000;
font_rom[946] <= 8'b00000000;
font_rom[947] <= 8'b00000000;
font_rom[948] <= 8'b00000000;
font_rom[949] <= 8'b00000000;
font_rom[950] <= 8'b00000000;
font_rom[951] <= 8'b00000000;
font_rom[952] <= 8'b00000000;
font_rom[953] <= 8'b00000000;
font_rom[954] <= 8'b00000000;
font_rom[955] <= 8'b00000000;
font_rom[956] <= 8'b00000000;
font_rom[957] <= 8'b00000000;
font_rom[958] <= 8'b00000000;
font_rom[959] <= 8'b00000000;
//ASCII 0x1E ' '
font_rom[960] <= 8'b00000000;
font_rom[961] <= 8'b00000000;
font_rom[962] <= 8'b00000000;
font_rom[963] <= 8'b00000000;
font_rom[964] <= 8'b00000000;
font_rom[965] <= 8'b00000000;
font_rom[966] <= 8'b00000000;
font_rom[967] <= 8'b00000000;
font_rom[968] <= 8'b00000000;
font_rom[969] <= 8'b00000000;
font_rom[970] <= 8'b00000000;
font_rom[971] <= 8'b00000000;
font_rom[972] <= 8'b00000000;
font_rom[973] <= 8'b00000000;
font_rom[974] <= 8'b00000000;
font_rom[975] <= 8'b00000000;
font_rom[976] <= 8'b00000000;
font_rom[977] <= 8'b00000000;
font_rom[978] <= 8'b00000000;
font_rom[979] <= 8'b00000000;
font_rom[980] <= 8'b00000000;
font_rom[981] <= 8'b00000000;
font_rom[982] <= 8'b00000000;
font_rom[983] <= 8'b00000000;
font_rom[984] <= 8'b00000000;
font_rom[985] <= 8'b00000000;
font_rom[986] <= 8'b00000000;
font_rom[987] <= 8'b00000000;
font_rom[988] <= 8'b00000000;
font_rom[989] <= 8'b00000000;
font_rom[990] <= 8'b00000000;
font_rom[991] <= 8'b00000000;
//ASCII 0x1F ' '
font_rom[992] <= 8'b00000000;
font_rom[993] <= 8'b00000000;
font_rom[994] <= 8'b00000000;
font_rom[995] <= 8'b00000000;
font_rom[996] <= 8'b00000000;
font_rom[997] <= 8'b00000000;
font_rom[998] <= 8'b00000000;
font_rom[999] <= 8'b00000000;
font_rom[1000] <= 8'b00000000;
font_rom[1001] <= 8'b00000000;
font_rom[1002] <= 8'b00000000;
font_rom[1003] <= 8'b00000000;
font_rom[1004] <= 8'b00000000;
font_rom[1005] <= 8'b00000000;
font_rom[1006] <= 8'b00000000;
font_rom[1007] <= 8'b00000000;
font_rom[1008] <= 8'b00000000;
font_rom[1009] <= 8'b00000000;
font_rom[1010] <= 8'b00000000;
font_rom[1011] <= 8'b00000000;
font_rom[1012] <= 8'b00000000;
font_rom[1013] <= 8'b00000000;
font_rom[1014] <= 8'b00000000;
font_rom[1015] <= 8'b00000000;
font_rom[1016] <= 8'b00000000;
font_rom[1017] <= 8'b00000000;
font_rom[1018] <= 8'b00000000;
font_rom[1019] <= 8'b00000000;
font_rom[1020] <= 8'b00000000;
font_rom[1021] <= 8'b00000000;
font_rom[1022] <= 8'b00000000;
font_rom[1023] <= 8'b00000000;
//ASCII 0x20 ' '
font_rom[1024] <= 8'b00000000;
font_rom[1025] <= 8'b00000000;
font_rom[1026] <= 8'b00000000;
font_rom[1027] <= 8'b00000000;
font_rom[1028] <= 8'b00000000;
font_rom[1029] <= 8'b00000000;
font_rom[1030] <= 8'b00000000;
font_rom[1031] <= 8'b00000000;
font_rom[1032] <= 8'b00000000;
font_rom[1033] <= 8'b00000000;
font_rom[1034] <= 8'b00000000;
font_rom[1035] <= 8'b00000000;
font_rom[1036] <= 8'b00000000;
font_rom[1037] <= 8'b00000000;
font_rom[1038] <= 8'b00000000;
font_rom[1039] <= 8'b00000000;
font_rom[1040] <= 8'b00000000;
font_rom[1041] <= 8'b00000000;
font_rom[1042] <= 8'b00000000;
font_rom[1043] <= 8'b00000000;
font_rom[1044] <= 8'b00000000;
font_rom[1045] <= 8'b00000000;
font_rom[1046] <= 8'b00000000;
font_rom[1047] <= 8'b00000000;
font_rom[1048] <= 8'b00000000;
font_rom[1049] <= 8'b00000000;
font_rom[1050] <= 8'b00000000;
font_rom[1051] <= 8'b00000000;
font_rom[1052] <= 8'b00000000;
font_rom[1053] <= 8'b00000000;
font_rom[1054] <= 8'b00000000;
font_rom[1055] <= 8'b00000000;
//ASCII 0x21 '!'
font_rom[1056] <= 8'b00000000;
font_rom[1057] <= 8'b00000000;
font_rom[1058] <= 8'b00000000;
font_rom[1059] <= 8'b00000000;
font_rom[1060] <= 8'b00000000;
font_rom[1061] <= 8'b00000000;
font_rom[1062] <= 8'b00000000;
font_rom[1063] <= 8'b00000000;
font_rom[1064] <= 8'b00000011;
font_rom[1065] <= 8'b00000000;
font_rom[1066] <= 8'b00000011;
font_rom[1067] <= 8'b00000000;
font_rom[1068] <= 8'b00000011;
font_rom[1069] <= 8'b00000000;
font_rom[1070] <= 8'b00000011;
font_rom[1071] <= 8'b00000000;
font_rom[1072] <= 8'b00000011;
font_rom[1073] <= 8'b00000000;
font_rom[1074] <= 8'b00000011;
font_rom[1075] <= 8'b00000000;
font_rom[1076] <= 8'b00000011;
font_rom[1077] <= 8'b00000000;
font_rom[1078] <= 8'b00000000;
font_rom[1079] <= 8'b00000000;
font_rom[1080] <= 8'b00000011;
font_rom[1081] <= 8'b00000000;
font_rom[1082] <= 8'b00000000;
font_rom[1083] <= 8'b00000000;
font_rom[1084] <= 8'b00000000;
font_rom[1085] <= 8'b00000000;
font_rom[1086] <= 8'b00000000;
font_rom[1087] <= 8'b00000000;
//ASCII 0x22 '"'
font_rom[1088] <= 8'b00000000;
font_rom[1089] <= 8'b00000000;
font_rom[1090] <= 8'b00000000;
font_rom[1091] <= 8'b00000000;
font_rom[1092] <= 8'b00000000;
font_rom[1093] <= 8'b00000000;
font_rom[1094] <= 8'b00000000;
font_rom[1095] <= 8'b00000000;
font_rom[1096] <= 8'b00000000;
font_rom[1097] <= 8'b00000000;
font_rom[1098] <= 8'b00000011;
font_rom[1099] <= 8'b11000000;
font_rom[1100] <= 8'b00000011;
font_rom[1101] <= 8'b11000000;
font_rom[1102] <= 8'b00000011;
font_rom[1103] <= 8'b11000000;
font_rom[1104] <= 8'b00000000;
font_rom[1105] <= 8'b00000000;
font_rom[1106] <= 8'b00000000;
font_rom[1107] <= 8'b00000000;
font_rom[1108] <= 8'b00000000;
font_rom[1109] <= 8'b00000000;
font_rom[1110] <= 8'b00000000;
font_rom[1111] <= 8'b00000000;
font_rom[1112] <= 8'b00000000;
font_rom[1113] <= 8'b00000000;
font_rom[1114] <= 8'b00000000;
font_rom[1115] <= 8'b00000000;
font_rom[1116] <= 8'b00000000;
font_rom[1117] <= 8'b00000000;
font_rom[1118] <= 8'b00000000;
font_rom[1119] <= 8'b00000000;
//ASCII 0x23 '#'
font_rom[1120] <= 8'b00000000;
font_rom[1121] <= 8'b00000000;
font_rom[1122] <= 8'b00000000;
font_rom[1123] <= 8'b00000000;
font_rom[1124] <= 8'b00000000;
font_rom[1125] <= 8'b00000000;
font_rom[1126] <= 8'b00000000;
font_rom[1127] <= 8'b00000000;
font_rom[1128] <= 8'b00000000;
font_rom[1129] <= 8'b00000000;
font_rom[1130] <= 8'b00000001;
font_rom[1131] <= 8'b00110000;
font_rom[1132] <= 8'b00000011;
font_rom[1133] <= 8'b00110000;
font_rom[1134] <= 8'b00001111;
font_rom[1135] <= 8'b11111000;
font_rom[1136] <= 8'b00000011;
font_rom[1137] <= 8'b01100000;
font_rom[1138] <= 8'b00000110;
font_rom[1139] <= 8'b01100000;
font_rom[1140] <= 8'b00011111;
font_rom[1141] <= 8'b11111000;
font_rom[1142] <= 8'b00000110;
font_rom[1143] <= 8'b11000000;
font_rom[1144] <= 8'b00001100;
font_rom[1145] <= 8'b11000000;
font_rom[1146] <= 8'b00000000;
font_rom[1147] <= 8'b00000000;
font_rom[1148] <= 8'b00000000;
font_rom[1149] <= 8'b00000000;
font_rom[1150] <= 8'b00000000;
font_rom[1151] <= 8'b00000000;
//ASCII 0x24 '$'
font_rom[1152] <= 8'b00000000;
font_rom[1153] <= 8'b00000000;
font_rom[1154] <= 8'b00000000;
font_rom[1155] <= 8'b00000000;
font_rom[1156] <= 8'b00000000;
font_rom[1157] <= 8'b00000000;
font_rom[1158] <= 8'b00000000;
font_rom[1159] <= 8'b00000000;
font_rom[1160] <= 8'b00000011;
font_rom[1161] <= 8'b00000000;
font_rom[1162] <= 8'b00000111;
font_rom[1163] <= 8'b11100000;
font_rom[1164] <= 8'b00001111;
font_rom[1165] <= 8'b00000000;
font_rom[1166] <= 8'b00001111;
font_rom[1167] <= 8'b00000000;
font_rom[1168] <= 8'b00000111;
font_rom[1169] <= 8'b11000000;
font_rom[1170] <= 8'b00000011;
font_rom[1171] <= 8'b01100000;
font_rom[1172] <= 8'b00000011;
font_rom[1173] <= 8'b01100000;
font_rom[1174] <= 8'b00000011;
font_rom[1175] <= 8'b11100000;
font_rom[1176] <= 8'b00001111;
font_rom[1177] <= 8'b11000000;
font_rom[1178] <= 8'b00000011;
font_rom[1179] <= 8'b00000000;
font_rom[1180] <= 8'b00000011;
font_rom[1181] <= 8'b00000000;
font_rom[1182] <= 8'b00000000;
font_rom[1183] <= 8'b00000000;
//ASCII 0x25 '%'
font_rom[1184] <= 8'b00000000;
font_rom[1185] <= 8'b00000000;
font_rom[1186] <= 8'b00000000;
font_rom[1187] <= 8'b00000000;
font_rom[1188] <= 8'b00000000;
font_rom[1189] <= 8'b00000000;
font_rom[1190] <= 8'b00000000;
font_rom[1191] <= 8'b00000000;
font_rom[1192] <= 8'b00000000;
font_rom[1193] <= 8'b01100000;
font_rom[1194] <= 8'b00000111;
font_rom[1195] <= 8'b01000000;
font_rom[1196] <= 8'b00001111;
font_rom[1197] <= 8'b11000000;
font_rom[1198] <= 8'b00001111;
font_rom[1199] <= 8'b11000000;
font_rom[1200] <= 8'b00000111;
font_rom[1201] <= 8'b10000000;
font_rom[1202] <= 8'b00000001;
font_rom[1203] <= 8'b11110000;
font_rom[1204] <= 8'b00000011;
font_rom[1205] <= 8'b11011000;
font_rom[1206] <= 8'b00000011;
font_rom[1207] <= 8'b11011000;
font_rom[1208] <= 8'b00000110;
font_rom[1209] <= 8'b01110000;
font_rom[1210] <= 8'b00000000;
font_rom[1211] <= 8'b00000000;
font_rom[1212] <= 8'b00000000;
font_rom[1213] <= 8'b00000000;
font_rom[1214] <= 8'b00000000;
font_rom[1215] <= 8'b00000000;
//ASCII 0x26 '&'
font_rom[1216] <= 8'b00000000;
font_rom[1217] <= 8'b00000000;
font_rom[1218] <= 8'b00000000;
font_rom[1219] <= 8'b00000000;
font_rom[1220] <= 8'b00000000;
font_rom[1221] <= 8'b00000000;
font_rom[1222] <= 8'b00000000;
font_rom[1223] <= 8'b00000000;
font_rom[1224] <= 8'b00000000;
font_rom[1225] <= 8'b00000000;
font_rom[1226] <= 8'b00000011;
font_rom[1227] <= 8'b10000000;
font_rom[1228] <= 8'b00000011;
font_rom[1229] <= 8'b10000000;
font_rom[1230] <= 8'b00000011;
font_rom[1231] <= 8'b10000000;
font_rom[1232] <= 8'b00000111;
font_rom[1233] <= 8'b01100000;
font_rom[1234] <= 8'b00001101;
font_rom[1235] <= 8'b11100000;
font_rom[1236] <= 8'b00001100;
font_rom[1237] <= 8'b11000000;
font_rom[1238] <= 8'b00001100;
font_rom[1239] <= 8'b11000000;
font_rom[1240] <= 8'b00000111;
font_rom[1241] <= 8'b11100000;
font_rom[1242] <= 8'b00000000;
font_rom[1243] <= 8'b00000000;
font_rom[1244] <= 8'b00000000;
font_rom[1245] <= 8'b00000000;
font_rom[1246] <= 8'b00000000;
font_rom[1247] <= 8'b00000000;
//ASCII 0x27 '''
font_rom[1248] <= 8'b00000000;
font_rom[1249] <= 8'b00000000;
font_rom[1250] <= 8'b00000000;
font_rom[1251] <= 8'b00000000;
font_rom[1252] <= 8'b00000000;
font_rom[1253] <= 8'b00000000;
font_rom[1254] <= 8'b00000000;
font_rom[1255] <= 8'b00000000;
font_rom[1256] <= 8'b00000000;
font_rom[1257] <= 8'b00000000;
font_rom[1258] <= 8'b00000001;
font_rom[1259] <= 8'b10000000;
font_rom[1260] <= 8'b00000001;
font_rom[1261] <= 8'b10000000;
font_rom[1262] <= 8'b00000001;
font_rom[1263] <= 8'b10000000;
font_rom[1264] <= 8'b00000000;
font_rom[1265] <= 8'b00000000;
font_rom[1266] <= 8'b00000000;
font_rom[1267] <= 8'b00000000;
font_rom[1268] <= 8'b00000000;
font_rom[1269] <= 8'b00000000;
font_rom[1270] <= 8'b00000000;
font_rom[1271] <= 8'b00000000;
font_rom[1272] <= 8'b00000000;
font_rom[1273] <= 8'b00000000;
font_rom[1274] <= 8'b00000000;
font_rom[1275] <= 8'b00000000;
font_rom[1276] <= 8'b00000000;
font_rom[1277] <= 8'b00000000;
font_rom[1278] <= 8'b00000000;
font_rom[1279] <= 8'b00000000;
//ASCII 0x28 '('
font_rom[1280] <= 8'b00000000;
font_rom[1281] <= 8'b00000000;
font_rom[1282] <= 8'b00000000;
font_rom[1283] <= 8'b00000000;
font_rom[1284] <= 8'b00000000;
font_rom[1285] <= 8'b00000000;
font_rom[1286] <= 8'b00000000;
font_rom[1287] <= 8'b00000000;
font_rom[1288] <= 8'b00000000;
font_rom[1289] <= 8'b11000000;
font_rom[1290] <= 8'b00000001;
font_rom[1291] <= 8'b10000000;
font_rom[1292] <= 8'b00000011;
font_rom[1293] <= 8'b00000000;
font_rom[1294] <= 8'b00000011;
font_rom[1295] <= 8'b00000000;
font_rom[1296] <= 8'b00000011;
font_rom[1297] <= 8'b00000000;
font_rom[1298] <= 8'b00000011;
font_rom[1299] <= 8'b00000000;
font_rom[1300] <= 8'b00000011;
font_rom[1301] <= 8'b00000000;
font_rom[1302] <= 8'b00000011;
font_rom[1303] <= 8'b00000000;
font_rom[1304] <= 8'b00000011;
font_rom[1305] <= 8'b00000000;
font_rom[1306] <= 8'b00000001;
font_rom[1307] <= 8'b10000000;
font_rom[1308] <= 8'b00000000;
font_rom[1309] <= 8'b11000000;
font_rom[1310] <= 8'b00000000;
font_rom[1311] <= 8'b00000000;
//ASCII 0x29 ')'
font_rom[1312] <= 8'b00000000;
font_rom[1313] <= 8'b00000000;
font_rom[1314] <= 8'b00000000;
font_rom[1315] <= 8'b00000000;
font_rom[1316] <= 8'b00000000;
font_rom[1317] <= 8'b00000000;
font_rom[1318] <= 8'b00000000;
font_rom[1319] <= 8'b00000000;
font_rom[1320] <= 8'b00000011;
font_rom[1321] <= 8'b00000000;
font_rom[1322] <= 8'b00000011;
font_rom[1323] <= 8'b10000000;
font_rom[1324] <= 8'b00000001;
font_rom[1325] <= 8'b10000000;
font_rom[1326] <= 8'b00000001;
font_rom[1327] <= 8'b10000000;
font_rom[1328] <= 8'b00000000;
font_rom[1329] <= 8'b11000000;
font_rom[1330] <= 8'b00000000;
font_rom[1331] <= 8'b11000000;
font_rom[1332] <= 8'b00000000;
font_rom[1333] <= 8'b11000000;
font_rom[1334] <= 8'b00000000;
font_rom[1335] <= 8'b10000000;
font_rom[1336] <= 8'b00000001;
font_rom[1337] <= 8'b10000000;
font_rom[1338] <= 8'b00000001;
font_rom[1339] <= 8'b10000000;
font_rom[1340] <= 8'b00000011;
font_rom[1341] <= 8'b00000000;
font_rom[1342] <= 8'b00000000;
font_rom[1343] <= 8'b00000000;
//ASCII 0x2A '*'
font_rom[1344] <= 8'b00000000;
font_rom[1345] <= 8'b00000000;
font_rom[1346] <= 8'b00000000;
font_rom[1347] <= 8'b00000000;
font_rom[1348] <= 8'b00000000;
font_rom[1349] <= 8'b00000000;
font_rom[1350] <= 8'b00000000;
font_rom[1351] <= 8'b00000000;
font_rom[1352] <= 8'b00000000;
font_rom[1353] <= 8'b00000000;
font_rom[1354] <= 8'b00000011;
font_rom[1355] <= 8'b00000000;
font_rom[1356] <= 8'b00000111;
font_rom[1357] <= 8'b11000000;
font_rom[1358] <= 8'b00000011;
font_rom[1359] <= 8'b10000000;
font_rom[1360] <= 8'b00000110;
font_rom[1361] <= 8'b11000000;
font_rom[1362] <= 8'b00000000;
font_rom[1363] <= 8'b00000000;
font_rom[1364] <= 8'b00000000;
font_rom[1365] <= 8'b00000000;
font_rom[1366] <= 8'b00000000;
font_rom[1367] <= 8'b00000000;
font_rom[1368] <= 8'b00000000;
font_rom[1369] <= 8'b00000000;
font_rom[1370] <= 8'b00000000;
font_rom[1371] <= 8'b00000000;
font_rom[1372] <= 8'b00000000;
font_rom[1373] <= 8'b00000000;
font_rom[1374] <= 8'b00000000;
font_rom[1375] <= 8'b00000000;
//ASCII 0x2B '+'
font_rom[1376] <= 8'b00000000;
font_rom[1377] <= 8'b00000000;
font_rom[1378] <= 8'b00000000;
font_rom[1379] <= 8'b00000000;
font_rom[1380] <= 8'b00000000;
font_rom[1381] <= 8'b00000000;
font_rom[1382] <= 8'b00000000;
font_rom[1383] <= 8'b00000000;
font_rom[1384] <= 8'b00000000;
font_rom[1385] <= 8'b00000000;
font_rom[1386] <= 8'b00000000;
font_rom[1387] <= 8'b00000000;
font_rom[1388] <= 8'b00000000;
font_rom[1389] <= 8'b00000000;
font_rom[1390] <= 8'b00000001;
font_rom[1391] <= 8'b10000000;
font_rom[1392] <= 8'b00000001;
font_rom[1393] <= 8'b10000000;
font_rom[1394] <= 8'b00000111;
font_rom[1395] <= 8'b11100000;
font_rom[1396] <= 8'b00000001;
font_rom[1397] <= 8'b10000000;
font_rom[1398] <= 8'b00000001;
font_rom[1399] <= 8'b10000000;
font_rom[1400] <= 8'b00000000;
font_rom[1401] <= 8'b00000000;
font_rom[1402] <= 8'b00000000;
font_rom[1403] <= 8'b00000000;
font_rom[1404] <= 8'b00000000;
font_rom[1405] <= 8'b00000000;
font_rom[1406] <= 8'b00000000;
font_rom[1407] <= 8'b00000000;
//ASCII 0x2C ','
font_rom[1408] <= 8'b00000000;
font_rom[1409] <= 8'b00000000;
font_rom[1410] <= 8'b00000000;
font_rom[1411] <= 8'b00000000;
font_rom[1412] <= 8'b00000000;
font_rom[1413] <= 8'b00000000;
font_rom[1414] <= 8'b00000000;
font_rom[1415] <= 8'b00000000;
font_rom[1416] <= 8'b00000000;
font_rom[1417] <= 8'b00000000;
font_rom[1418] <= 8'b00000000;
font_rom[1419] <= 8'b00000000;
font_rom[1420] <= 8'b00000000;
font_rom[1421] <= 8'b00000000;
font_rom[1422] <= 8'b00000000;
font_rom[1423] <= 8'b00000000;
font_rom[1424] <= 8'b00000000;
font_rom[1425] <= 8'b00000000;
font_rom[1426] <= 8'b00000000;
font_rom[1427] <= 8'b00000000;
font_rom[1428] <= 8'b00000000;
font_rom[1429] <= 8'b00000000;
font_rom[1430] <= 8'b00000000;
font_rom[1431] <= 8'b00000000;
font_rom[1432] <= 8'b00000001;
font_rom[1433] <= 8'b10000000;
font_rom[1434] <= 8'b00000011;
font_rom[1435] <= 8'b00000000;
font_rom[1436] <= 8'b00000000;
font_rom[1437] <= 8'b00000000;
font_rom[1438] <= 8'b00000000;
font_rom[1439] <= 8'b00000000;
//ASCII 0x2D '-'
font_rom[1440] <= 8'b00000000;
font_rom[1441] <= 8'b00000000;
font_rom[1442] <= 8'b00000000;
font_rom[1443] <= 8'b00000000;
font_rom[1444] <= 8'b00000000;
font_rom[1445] <= 8'b00000000;
font_rom[1446] <= 8'b00000000;
font_rom[1447] <= 8'b00000000;
font_rom[1448] <= 8'b00000000;
font_rom[1449] <= 8'b00000000;
font_rom[1450] <= 8'b00000000;
font_rom[1451] <= 8'b00000000;
font_rom[1452] <= 8'b00000000;
font_rom[1453] <= 8'b00000000;
font_rom[1454] <= 8'b00000000;
font_rom[1455] <= 8'b00000000;
font_rom[1456] <= 8'b00000000;
font_rom[1457] <= 8'b00000000;
font_rom[1458] <= 8'b00000000;
font_rom[1459] <= 8'b00000000;
font_rom[1460] <= 8'b00000011;
font_rom[1461] <= 8'b11000000;
font_rom[1462] <= 8'b00000000;
font_rom[1463] <= 8'b00000000;
font_rom[1464] <= 8'b00000000;
font_rom[1465] <= 8'b00000000;
font_rom[1466] <= 8'b00000000;
font_rom[1467] <= 8'b00000000;
font_rom[1468] <= 8'b00000000;
font_rom[1469] <= 8'b00000000;
font_rom[1470] <= 8'b00000000;
font_rom[1471] <= 8'b00000000;
//ASCII 0x2E '.'
font_rom[1472] <= 8'b00000000;
font_rom[1473] <= 8'b00000000;
font_rom[1474] <= 8'b00000000;
font_rom[1475] <= 8'b00000000;
font_rom[1476] <= 8'b00000000;
font_rom[1477] <= 8'b00000000;
font_rom[1478] <= 8'b00000000;
font_rom[1479] <= 8'b00000000;
font_rom[1480] <= 8'b00000000;
font_rom[1481] <= 8'b00000000;
font_rom[1482] <= 8'b00000000;
font_rom[1483] <= 8'b00000000;
font_rom[1484] <= 8'b00000000;
font_rom[1485] <= 8'b00000000;
font_rom[1486] <= 8'b00000000;
font_rom[1487] <= 8'b00000000;
font_rom[1488] <= 8'b00000000;
font_rom[1489] <= 8'b00000000;
font_rom[1490] <= 8'b00000000;
font_rom[1491] <= 8'b00000000;
font_rom[1492] <= 8'b00000000;
font_rom[1493] <= 8'b00000000;
font_rom[1494] <= 8'b00000000;
font_rom[1495] <= 8'b00000000;
font_rom[1496] <= 8'b00000011;
font_rom[1497] <= 8'b00000000;
font_rom[1498] <= 8'b00000000;
font_rom[1499] <= 8'b00000000;
font_rom[1500] <= 8'b00000000;
font_rom[1501] <= 8'b00000000;
font_rom[1502] <= 8'b00000000;
font_rom[1503] <= 8'b00000000;
//ASCII 0x2F '/'
font_rom[1504] <= 8'b00000000;
font_rom[1505] <= 8'b00000000;
font_rom[1506] <= 8'b00000000;
font_rom[1507] <= 8'b00000000;
font_rom[1508] <= 8'b00000000;
font_rom[1509] <= 8'b00000000;
font_rom[1510] <= 8'b00000000;
font_rom[1511] <= 8'b00000000;
font_rom[1512] <= 8'b00000000;
font_rom[1513] <= 8'b11000000;
font_rom[1514] <= 8'b00000000;
font_rom[1515] <= 8'b11000000;
font_rom[1516] <= 8'b00000000;
font_rom[1517] <= 8'b10000000;
font_rom[1518] <= 8'b00000001;
font_rom[1519] <= 8'b10000000;
font_rom[1520] <= 8'b00000001;
font_rom[1521] <= 8'b00000000;
font_rom[1522] <= 8'b00000011;
font_rom[1523] <= 8'b00000000;
font_rom[1524] <= 8'b00000010;
font_rom[1525] <= 8'b00000000;
font_rom[1526] <= 8'b00000110;
font_rom[1527] <= 8'b00000000;
font_rom[1528] <= 8'b00000110;
font_rom[1529] <= 8'b00000000;
font_rom[1530] <= 8'b00000000;
font_rom[1531] <= 8'b00000000;
font_rom[1532] <= 8'b00000000;
font_rom[1533] <= 8'b00000000;
font_rom[1534] <= 8'b00000000;
font_rom[1535] <= 8'b00000000;
//ASCII 0x30 '0'
font_rom[1536] <= 8'b00000000;
font_rom[1537] <= 8'b00000000;
font_rom[1538] <= 8'b00000000;
font_rom[1539] <= 8'b00000000;
font_rom[1540] <= 8'b00000000;
font_rom[1541] <= 8'b00000000;
font_rom[1542] <= 8'b00000000;
font_rom[1543] <= 8'b00000000;
font_rom[1544] <= 8'b00000000;
font_rom[1545] <= 8'b00000000;
font_rom[1546] <= 8'b00000111;
font_rom[1547] <= 8'b11000000;
font_rom[1548] <= 8'b00001100;
font_rom[1549] <= 8'b11000000;
font_rom[1550] <= 8'b00001100;
font_rom[1551] <= 8'b01000000;
font_rom[1552] <= 8'b00001000;
font_rom[1553] <= 8'b01100000;
font_rom[1554] <= 8'b00001000;
font_rom[1555] <= 8'b01100000;
font_rom[1556] <= 8'b00001100;
font_rom[1557] <= 8'b11000000;
font_rom[1558] <= 8'b00001100;
font_rom[1559] <= 8'b11000000;
font_rom[1560] <= 8'b00000111;
font_rom[1561] <= 8'b11000000;
font_rom[1562] <= 8'b00000000;
font_rom[1563] <= 8'b00000000;
font_rom[1564] <= 8'b00000000;
font_rom[1565] <= 8'b00000000;
font_rom[1566] <= 8'b00000000;
font_rom[1567] <= 8'b00000000;
//ASCII 0x31 '1'
font_rom[1568] <= 8'b00000000;
font_rom[1569] <= 8'b00000000;
font_rom[1570] <= 8'b00000000;
font_rom[1571] <= 8'b00000000;
font_rom[1572] <= 8'b00000000;
font_rom[1573] <= 8'b00000000;
font_rom[1574] <= 8'b00000000;
font_rom[1575] <= 8'b00000000;
font_rom[1576] <= 8'b00000000;
font_rom[1577] <= 8'b00000000;
font_rom[1578] <= 8'b00000001;
font_rom[1579] <= 8'b10000000;
font_rom[1580] <= 8'b00000011;
font_rom[1581] <= 8'b10000000;
font_rom[1582] <= 8'b00000000;
font_rom[1583] <= 8'b10000000;
font_rom[1584] <= 8'b00000001;
font_rom[1585] <= 8'b10000000;
font_rom[1586] <= 8'b00000001;
font_rom[1587] <= 8'b10000000;
font_rom[1588] <= 8'b00000001;
font_rom[1589] <= 8'b10000000;
font_rom[1590] <= 8'b00000001;
font_rom[1591] <= 8'b10000000;
font_rom[1592] <= 8'b00000011;
font_rom[1593] <= 8'b11000000;
font_rom[1594] <= 8'b00000000;
font_rom[1595] <= 8'b00000000;
font_rom[1596] <= 8'b00000000;
font_rom[1597] <= 8'b00000000;
font_rom[1598] <= 8'b00000000;
font_rom[1599] <= 8'b00000000;
//ASCII 0x32 '2'
font_rom[1600] <= 8'b00000000;
font_rom[1601] <= 8'b00000000;
font_rom[1602] <= 8'b00000000;
font_rom[1603] <= 8'b00000000;
font_rom[1604] <= 8'b00000000;
font_rom[1605] <= 8'b00000000;
font_rom[1606] <= 8'b00000000;
font_rom[1607] <= 8'b00000000;
font_rom[1608] <= 8'b00000000;
font_rom[1609] <= 8'b00000000;
font_rom[1610] <= 8'b00000111;
font_rom[1611] <= 8'b10000000;
font_rom[1612] <= 8'b00001100;
font_rom[1613] <= 8'b11000000;
font_rom[1614] <= 8'b00000000;
font_rom[1615] <= 8'b11000000;
font_rom[1616] <= 8'b00000001;
font_rom[1617] <= 8'b11000000;
font_rom[1618] <= 8'b00000011;
font_rom[1619] <= 8'b00000000;
font_rom[1620] <= 8'b00000110;
font_rom[1621] <= 8'b00000000;
font_rom[1622] <= 8'b00001100;
font_rom[1623] <= 8'b00000000;
font_rom[1624] <= 8'b00001111;
font_rom[1625] <= 8'b11000000;
font_rom[1626] <= 8'b00000000;
font_rom[1627] <= 8'b00000000;
font_rom[1628] <= 8'b00000000;
font_rom[1629] <= 8'b00000000;
font_rom[1630] <= 8'b00000000;
font_rom[1631] <= 8'b00000000;
//ASCII 0x33 '3'
font_rom[1632] <= 8'b00000000;
font_rom[1633] <= 8'b00000000;
font_rom[1634] <= 8'b00000000;
font_rom[1635] <= 8'b00000000;
font_rom[1636] <= 8'b00000000;
font_rom[1637] <= 8'b00000000;
font_rom[1638] <= 8'b00000000;
font_rom[1639] <= 8'b00000000;
font_rom[1640] <= 8'b00000000;
font_rom[1641] <= 8'b00000000;
font_rom[1642] <= 8'b00000111;
font_rom[1643] <= 8'b10000000;
font_rom[1644] <= 8'b00001100;
font_rom[1645] <= 8'b11000000;
font_rom[1646] <= 8'b00000000;
font_rom[1647] <= 8'b11000000;
font_rom[1648] <= 8'b00000011;
font_rom[1649] <= 8'b10000000;
font_rom[1650] <= 8'b00000000;
font_rom[1651] <= 8'b11000000;
font_rom[1652] <= 8'b00000000;
font_rom[1653] <= 8'b11000000;
font_rom[1654] <= 8'b00001100;
font_rom[1655] <= 8'b11000000;
font_rom[1656] <= 8'b00000111;
font_rom[1657] <= 8'b10000000;
font_rom[1658] <= 8'b00000000;
font_rom[1659] <= 8'b00000000;
font_rom[1660] <= 8'b00000000;
font_rom[1661] <= 8'b00000000;
font_rom[1662] <= 8'b00000000;
font_rom[1663] <= 8'b00000000;
//ASCII 0x34 '4'
font_rom[1664] <= 8'b00000000;
font_rom[1665] <= 8'b00000000;
font_rom[1666] <= 8'b00000000;
font_rom[1667] <= 8'b00000000;
font_rom[1668] <= 8'b00000000;
font_rom[1669] <= 8'b00000000;
font_rom[1670] <= 8'b00000000;
font_rom[1671] <= 8'b00000000;
font_rom[1672] <= 8'b00000000;
font_rom[1673] <= 8'b00000000;
font_rom[1674] <= 8'b00000001;
font_rom[1675] <= 8'b10000000;
font_rom[1676] <= 8'b00000011;
font_rom[1677] <= 8'b10000000;
font_rom[1678] <= 8'b00000011;
font_rom[1679] <= 8'b10000000;
font_rom[1680] <= 8'b00000110;
font_rom[1681] <= 8'b10000000;
font_rom[1682] <= 8'b00001100;
font_rom[1683] <= 8'b10000000;
font_rom[1684] <= 8'b00001111;
font_rom[1685] <= 8'b11100000;
font_rom[1686] <= 8'b00000000;
font_rom[1687] <= 8'b10000000;
font_rom[1688] <= 8'b00000000;
font_rom[1689] <= 8'b10000000;
font_rom[1690] <= 8'b00000000;
font_rom[1691] <= 8'b00000000;
font_rom[1692] <= 8'b00000000;
font_rom[1693] <= 8'b00000000;
font_rom[1694] <= 8'b00000000;
font_rom[1695] <= 8'b00000000;
//ASCII 0x35 '5'
font_rom[1696] <= 8'b00000000;
font_rom[1697] <= 8'b00000000;
font_rom[1698] <= 8'b00000000;
font_rom[1699] <= 8'b00000000;
font_rom[1700] <= 8'b00000000;
font_rom[1701] <= 8'b00000000;
font_rom[1702] <= 8'b00000000;
font_rom[1703] <= 8'b00000000;
font_rom[1704] <= 8'b00000000;
font_rom[1705] <= 8'b00000000;
font_rom[1706] <= 8'b00001111;
font_rom[1707] <= 8'b11000000;
font_rom[1708] <= 8'b00001100;
font_rom[1709] <= 8'b00000000;
font_rom[1710] <= 8'b00001111;
font_rom[1711] <= 8'b11000000;
font_rom[1712] <= 8'b00001100;
font_rom[1713] <= 8'b11000000;
font_rom[1714] <= 8'b00000000;
font_rom[1715] <= 8'b01100000;
font_rom[1716] <= 8'b00000000;
font_rom[1717] <= 8'b01100000;
font_rom[1718] <= 8'b00001100;
font_rom[1719] <= 8'b11000000;
font_rom[1720] <= 8'b00000111;
font_rom[1721] <= 8'b10000000;
font_rom[1722] <= 8'b00000000;
font_rom[1723] <= 8'b00000000;
font_rom[1724] <= 8'b00000000;
font_rom[1725] <= 8'b00000000;
font_rom[1726] <= 8'b00000000;
font_rom[1727] <= 8'b00000000;
//ASCII 0x36 '6'
font_rom[1728] <= 8'b00000000;
font_rom[1729] <= 8'b00000000;
font_rom[1730] <= 8'b00000000;
font_rom[1731] <= 8'b00000000;
font_rom[1732] <= 8'b00000000;
font_rom[1733] <= 8'b00000000;
font_rom[1734] <= 8'b00000000;
font_rom[1735] <= 8'b00000000;
font_rom[1736] <= 8'b00000000;
font_rom[1737] <= 8'b00000000;
font_rom[1738] <= 8'b00000011;
font_rom[1739] <= 8'b10000000;
font_rom[1740] <= 8'b00000111;
font_rom[1741] <= 8'b00000000;
font_rom[1742] <= 8'b00000110;
font_rom[1743] <= 8'b00000000;
font_rom[1744] <= 8'b00001111;
font_rom[1745] <= 8'b10000000;
font_rom[1746] <= 8'b00001100;
font_rom[1747] <= 8'b11000000;
font_rom[1748] <= 8'b00001100;
font_rom[1749] <= 8'b11000000;
font_rom[1750] <= 8'b00001100;
font_rom[1751] <= 8'b11000000;
font_rom[1752] <= 8'b00000111;
font_rom[1753] <= 8'b10000000;
font_rom[1754] <= 8'b00000000;
font_rom[1755] <= 8'b00000000;
font_rom[1756] <= 8'b00000000;
font_rom[1757] <= 8'b00000000;
font_rom[1758] <= 8'b00000000;
font_rom[1759] <= 8'b00000000;
//ASCII 0x37 '7'
font_rom[1760] <= 8'b00000000;
font_rom[1761] <= 8'b00000000;
font_rom[1762] <= 8'b00000000;
font_rom[1763] <= 8'b00000000;
font_rom[1764] <= 8'b00000000;
font_rom[1765] <= 8'b00000000;
font_rom[1766] <= 8'b00000000;
font_rom[1767] <= 8'b00000000;
font_rom[1768] <= 8'b00000000;
font_rom[1769] <= 8'b00000000;
font_rom[1770] <= 8'b00001111;
font_rom[1771] <= 8'b11100000;
font_rom[1772] <= 8'b00000000;
font_rom[1773] <= 8'b11000000;
font_rom[1774] <= 8'b00000001;
font_rom[1775] <= 8'b10000000;
font_rom[1776] <= 8'b00000011;
font_rom[1777] <= 8'b00000000;
font_rom[1778] <= 8'b00000011;
font_rom[1779] <= 8'b00000000;
font_rom[1780] <= 8'b00000011;
font_rom[1781] <= 8'b00000000;
font_rom[1782] <= 8'b00000110;
font_rom[1783] <= 8'b00000000;
font_rom[1784] <= 8'b00000110;
font_rom[1785] <= 8'b00000000;
font_rom[1786] <= 8'b00000000;
font_rom[1787] <= 8'b00000000;
font_rom[1788] <= 8'b00000000;
font_rom[1789] <= 8'b00000000;
font_rom[1790] <= 8'b00000000;
font_rom[1791] <= 8'b00000000;
//ASCII 0x38 '8'
font_rom[1792] <= 8'b00000000;
font_rom[1793] <= 8'b00000000;
font_rom[1794] <= 8'b00000000;
font_rom[1795] <= 8'b00000000;
font_rom[1796] <= 8'b00000000;
font_rom[1797] <= 8'b00000000;
font_rom[1798] <= 8'b00000000;
font_rom[1799] <= 8'b00000000;
font_rom[1800] <= 8'b00000000;
font_rom[1801] <= 8'b00000000;
font_rom[1802] <= 8'b00000111;
font_rom[1803] <= 8'b10000000;
font_rom[1804] <= 8'b00001100;
font_rom[1805] <= 8'b11000000;
font_rom[1806] <= 8'b00001100;
font_rom[1807] <= 8'b11000000;
font_rom[1808] <= 8'b00000111;
font_rom[1809] <= 8'b10000000;
font_rom[1810] <= 8'b00001100;
font_rom[1811] <= 8'b11000000;
font_rom[1812] <= 8'b00001100;
font_rom[1813] <= 8'b11000000;
font_rom[1814] <= 8'b00001100;
font_rom[1815] <= 8'b11000000;
font_rom[1816] <= 8'b00000111;
font_rom[1817] <= 8'b10000000;
font_rom[1818] <= 8'b00000000;
font_rom[1819] <= 8'b00000000;
font_rom[1820] <= 8'b00000000;
font_rom[1821] <= 8'b00000000;
font_rom[1822] <= 8'b00000000;
font_rom[1823] <= 8'b00000000;
//ASCII 0x39 '9'
font_rom[1824] <= 8'b00000000;
font_rom[1825] <= 8'b00000000;
font_rom[1826] <= 8'b00000000;
font_rom[1827] <= 8'b00000000;
font_rom[1828] <= 8'b00000000;
font_rom[1829] <= 8'b00000000;
font_rom[1830] <= 8'b00000000;
font_rom[1831] <= 8'b00000000;
font_rom[1832] <= 8'b00000000;
font_rom[1833] <= 8'b00000000;
font_rom[1834] <= 8'b00000111;
font_rom[1835] <= 8'b10000000;
font_rom[1836] <= 8'b00001100;
font_rom[1837] <= 8'b11000000;
font_rom[1838] <= 8'b00001100;
font_rom[1839] <= 8'b01100000;
font_rom[1840] <= 8'b00001100;
font_rom[1841] <= 8'b01100000;
font_rom[1842] <= 8'b00000111;
font_rom[1843] <= 8'b11000000;
font_rom[1844] <= 8'b00000000;
font_rom[1845] <= 8'b11000000;
font_rom[1846] <= 8'b00000011;
font_rom[1847] <= 8'b10000000;
font_rom[1848] <= 8'b00001110;
font_rom[1849] <= 8'b00000000;
font_rom[1850] <= 8'b00000000;
font_rom[1851] <= 8'b00000000;
font_rom[1852] <= 8'b00000000;
font_rom[1853] <= 8'b00000000;
font_rom[1854] <= 8'b00000000;
font_rom[1855] <= 8'b00000000;
//ASCII 0x3A ':'
font_rom[1856] <= 8'b00000000;
font_rom[1857] <= 8'b00000000;
font_rom[1858] <= 8'b00000000;
font_rom[1859] <= 8'b00000000;
font_rom[1860] <= 8'b00000000;
font_rom[1861] <= 8'b00000000;
font_rom[1862] <= 8'b00000000;
font_rom[1863] <= 8'b00000000;
font_rom[1864] <= 8'b00000000;
font_rom[1865] <= 8'b00000000;
font_rom[1866] <= 8'b00000000;
font_rom[1867] <= 8'b00000000;
font_rom[1868] <= 8'b00000000;
font_rom[1869] <= 8'b00000000;
font_rom[1870] <= 8'b00000011;
font_rom[1871] <= 8'b00000000;
font_rom[1872] <= 8'b00000000;
font_rom[1873] <= 8'b00000000;
font_rom[1874] <= 8'b00000000;
font_rom[1875] <= 8'b00000000;
font_rom[1876] <= 8'b00000000;
font_rom[1877] <= 8'b00000000;
font_rom[1878] <= 8'b00000011;
font_rom[1879] <= 8'b00000000;
font_rom[1880] <= 8'b00000000;
font_rom[1881] <= 8'b00000000;
font_rom[1882] <= 8'b00000000;
font_rom[1883] <= 8'b00000000;
font_rom[1884] <= 8'b00000000;
font_rom[1885] <= 8'b00000000;
font_rom[1886] <= 8'b00000000;
font_rom[1887] <= 8'b00000000;
//ASCII 0x3B ';'
font_rom[1888] <= 8'b00000000;
font_rom[1889] <= 8'b00000000;
font_rom[1890] <= 8'b00000000;
font_rom[1891] <= 8'b00000000;
font_rom[1892] <= 8'b00000000;
font_rom[1893] <= 8'b00000000;
font_rom[1894] <= 8'b00000000;
font_rom[1895] <= 8'b00000000;
font_rom[1896] <= 8'b00000000;
font_rom[1897] <= 8'b00000000;
font_rom[1898] <= 8'b00000000;
font_rom[1899] <= 8'b00000000;
font_rom[1900] <= 8'b00000000;
font_rom[1901] <= 8'b00000000;
font_rom[1902] <= 8'b00000011;
font_rom[1903] <= 8'b00000000;
font_rom[1904] <= 8'b00000000;
font_rom[1905] <= 8'b00000000;
font_rom[1906] <= 8'b00000000;
font_rom[1907] <= 8'b00000000;
font_rom[1908] <= 8'b00000000;
font_rom[1909] <= 8'b00000000;
font_rom[1910] <= 8'b00000000;
font_rom[1911] <= 8'b00000000;
font_rom[1912] <= 8'b00000011;
font_rom[1913] <= 8'b00000000;
font_rom[1914] <= 8'b00000010;
font_rom[1915] <= 8'b00000000;
font_rom[1916] <= 8'b00000000;
font_rom[1917] <= 8'b00000000;
font_rom[1918] <= 8'b00000000;
font_rom[1919] <= 8'b00000000;
//ASCII 0x3C '<'
font_rom[1920] <= 8'b00000000;
font_rom[1921] <= 8'b00000000;
font_rom[1922] <= 8'b00000000;
font_rom[1923] <= 8'b00000000;
font_rom[1924] <= 8'b00000000;
font_rom[1925] <= 8'b00000000;
font_rom[1926] <= 8'b00000000;
font_rom[1927] <= 8'b00000000;
font_rom[1928] <= 8'b00000000;
font_rom[1929] <= 8'b00000000;
font_rom[1930] <= 8'b00000000;
font_rom[1931] <= 8'b00000000;
font_rom[1932] <= 8'b00000000;
font_rom[1933] <= 8'b00000000;
font_rom[1934] <= 8'b00000001;
font_rom[1935] <= 8'b10000000;
font_rom[1936] <= 8'b00000011;
font_rom[1937] <= 8'b10000000;
font_rom[1938] <= 8'b00000111;
font_rom[1939] <= 8'b00000000;
font_rom[1940] <= 8'b00000011;
font_rom[1941] <= 8'b00000000;
font_rom[1942] <= 8'b00000001;
font_rom[1943] <= 8'b10000000;
font_rom[1944] <= 8'b00000000;
font_rom[1945] <= 8'b00000000;
font_rom[1946] <= 8'b00000000;
font_rom[1947] <= 8'b00000000;
font_rom[1948] <= 8'b00000000;
font_rom[1949] <= 8'b00000000;
font_rom[1950] <= 8'b00000000;
font_rom[1951] <= 8'b00000000;
//ASCII 0x3D '='
font_rom[1952] <= 8'b00000000;
font_rom[1953] <= 8'b00000000;
font_rom[1954] <= 8'b00000000;
font_rom[1955] <= 8'b00000000;
font_rom[1956] <= 8'b00000000;
font_rom[1957] <= 8'b00000000;
font_rom[1958] <= 8'b00000000;
font_rom[1959] <= 8'b00000000;
font_rom[1960] <= 8'b00000000;
font_rom[1961] <= 8'b00000000;
font_rom[1962] <= 8'b00000000;
font_rom[1963] <= 8'b00000000;
font_rom[1964] <= 8'b00000000;
font_rom[1965] <= 8'b00000000;
font_rom[1966] <= 8'b00000111;
font_rom[1967] <= 8'b11000000;
font_rom[1968] <= 8'b00000000;
font_rom[1969] <= 8'b00000000;
font_rom[1970] <= 8'b00000000;
font_rom[1971] <= 8'b00000000;
font_rom[1972] <= 8'b00000111;
font_rom[1973] <= 8'b11000000;
font_rom[1974] <= 8'b00000000;
font_rom[1975] <= 8'b00000000;
font_rom[1976] <= 8'b00000000;
font_rom[1977] <= 8'b00000000;
font_rom[1978] <= 8'b00000000;
font_rom[1979] <= 8'b00000000;
font_rom[1980] <= 8'b00000000;
font_rom[1981] <= 8'b00000000;
font_rom[1982] <= 8'b00000000;
font_rom[1983] <= 8'b00000000;
//ASCII 0x3E '>'
font_rom[1984] <= 8'b00000000;
font_rom[1985] <= 8'b00000000;
font_rom[1986] <= 8'b00000000;
font_rom[1987] <= 8'b00000000;
font_rom[1988] <= 8'b00000000;
font_rom[1989] <= 8'b00000000;
font_rom[1990] <= 8'b00000000;
font_rom[1991] <= 8'b00000000;
font_rom[1992] <= 8'b00000000;
font_rom[1993] <= 8'b00000000;
font_rom[1994] <= 8'b00000000;
font_rom[1995] <= 8'b00000000;
font_rom[1996] <= 8'b00000000;
font_rom[1997] <= 8'b00000000;
font_rom[1998] <= 8'b00000011;
font_rom[1999] <= 8'b00000000;
font_rom[2000] <= 8'b00000001;
font_rom[2001] <= 8'b10000000;
font_rom[2002] <= 8'b00000000;
font_rom[2003] <= 8'b11000000;
font_rom[2004] <= 8'b00000001;
font_rom[2005] <= 8'b10000000;
font_rom[2006] <= 8'b00000011;
font_rom[2007] <= 8'b00000000;
font_rom[2008] <= 8'b00000000;
font_rom[2009] <= 8'b00000000;
font_rom[2010] <= 8'b00000000;
font_rom[2011] <= 8'b00000000;
font_rom[2012] <= 8'b00000000;
font_rom[2013] <= 8'b00000000;
font_rom[2014] <= 8'b00000000;
font_rom[2015] <= 8'b00000000;
//ASCII 0x3F '?'
font_rom[2016] <= 8'b00000000;
font_rom[2017] <= 8'b00000000;
font_rom[2018] <= 8'b00000000;
font_rom[2019] <= 8'b00000000;
font_rom[2020] <= 8'b00000000;
font_rom[2021] <= 8'b00000000;
font_rom[2022] <= 8'b00000000;
font_rom[2023] <= 8'b00000000;
font_rom[2024] <= 8'b00000000;
font_rom[2025] <= 8'b00000000;
font_rom[2026] <= 8'b00000111;
font_rom[2027] <= 8'b10000000;
font_rom[2028] <= 8'b00000000;
font_rom[2029] <= 8'b11000000;
font_rom[2030] <= 8'b00000000;
font_rom[2031] <= 8'b01000000;
font_rom[2032] <= 8'b00000000;
font_rom[2033] <= 8'b11000000;
font_rom[2034] <= 8'b00000011;
font_rom[2035] <= 8'b10000000;
font_rom[2036] <= 8'b00000011;
font_rom[2037] <= 8'b00000000;
font_rom[2038] <= 8'b00000000;
font_rom[2039] <= 8'b00000000;
font_rom[2040] <= 8'b00000110;
font_rom[2041] <= 8'b00000000;
font_rom[2042] <= 8'b00000000;
font_rom[2043] <= 8'b00000000;
font_rom[2044] <= 8'b00000000;
font_rom[2045] <= 8'b00000000;
font_rom[2046] <= 8'b00000000;
font_rom[2047] <= 8'b00000000;
//ASCII 0x40 '@'
font_rom[2048] <= 8'b00000000;
font_rom[2049] <= 8'b00000000;
font_rom[2050] <= 8'b00000000;
font_rom[2051] <= 8'b00000000;
font_rom[2052] <= 8'b00000000;
font_rom[2053] <= 8'b00000000;
font_rom[2054] <= 8'b00000000;
font_rom[2055] <= 8'b00000000;
font_rom[2056] <= 8'b00000111;
font_rom[2057] <= 8'b11000000;
font_rom[2058] <= 8'b00001100;
font_rom[2059] <= 8'b01100000;
font_rom[2060] <= 8'b00011011;
font_rom[2061] <= 8'b10110000;
font_rom[2062] <= 8'b00011111;
font_rom[2063] <= 8'b10110000;
font_rom[2064] <= 8'b00011111;
font_rom[2065] <= 8'b10110000;
font_rom[2066] <= 8'b00011111;
font_rom[2067] <= 8'b11110000;
font_rom[2068] <= 8'b00011000;
font_rom[2069] <= 8'b00000000;
font_rom[2070] <= 8'b00001100;
font_rom[2071] <= 8'b01100000;
font_rom[2072] <= 8'b00000111;
font_rom[2073] <= 8'b11000000;
font_rom[2074] <= 8'b00000000;
font_rom[2075] <= 8'b00000000;
font_rom[2076] <= 8'b00000000;
font_rom[2077] <= 8'b00000000;
font_rom[2078] <= 8'b00000000;
font_rom[2079] <= 8'b00000000;
//ASCII 0x41 'A'
font_rom[2080] <= 8'b00000000;
font_rom[2081] <= 8'b00000000;
font_rom[2082] <= 8'b00000000;
font_rom[2083] <= 8'b00000000;
font_rom[2084] <= 8'b00000000;
font_rom[2085] <= 8'b00000000;
font_rom[2086] <= 8'b00000000;
font_rom[2087] <= 8'b00000000;
font_rom[2088] <= 8'b00000000;
font_rom[2089] <= 8'b00000000;
font_rom[2090] <= 8'b00000000;
font_rom[2091] <= 8'b11000000;
font_rom[2092] <= 8'b00000001;
font_rom[2093] <= 8'b11000000;
font_rom[2094] <= 8'b00000011;
font_rom[2095] <= 8'b11000000;
font_rom[2096] <= 8'b00000011;
font_rom[2097] <= 8'b11000000;
font_rom[2098] <= 8'b00000111;
font_rom[2099] <= 8'b11100000;
font_rom[2100] <= 8'b00000110;
font_rom[2101] <= 8'b01100000;
font_rom[2102] <= 8'b00001100;
font_rom[2103] <= 8'b01100000;
font_rom[2104] <= 8'b00001100;
font_rom[2105] <= 8'b01100000;
font_rom[2106] <= 8'b00000000;
font_rom[2107] <= 8'b00000000;
font_rom[2108] <= 8'b00000000;
font_rom[2109] <= 8'b00000000;
font_rom[2110] <= 8'b00000000;
font_rom[2111] <= 8'b00000000;
//ASCII 0x42 'B'
font_rom[2112] <= 8'b00000000;
font_rom[2113] <= 8'b00000000;
font_rom[2114] <= 8'b00000000;
font_rom[2115] <= 8'b00000000;
font_rom[2116] <= 8'b00000000;
font_rom[2117] <= 8'b00000000;
font_rom[2118] <= 8'b00000000;
font_rom[2119] <= 8'b00000000;
font_rom[2120] <= 8'b00000000;
font_rom[2121] <= 8'b00000000;
font_rom[2122] <= 8'b00000111;
font_rom[2123] <= 8'b10000000;
font_rom[2124] <= 8'b00001100;
font_rom[2125] <= 8'b11000000;
font_rom[2126] <= 8'b00001100;
font_rom[2127] <= 8'b11000000;
font_rom[2128] <= 8'b00001100;
font_rom[2129] <= 8'b11000000;
font_rom[2130] <= 8'b00001111;
font_rom[2131] <= 8'b10000000;
font_rom[2132] <= 8'b00001100;
font_rom[2133] <= 8'b11100000;
font_rom[2134] <= 8'b00001100;
font_rom[2135] <= 8'b11000000;
font_rom[2136] <= 8'b00001111;
font_rom[2137] <= 8'b10000000;
font_rom[2138] <= 8'b00000000;
font_rom[2139] <= 8'b00000000;
font_rom[2140] <= 8'b00000000;
font_rom[2141] <= 8'b00000000;
font_rom[2142] <= 8'b00000000;
font_rom[2143] <= 8'b00000000;
//ASCII 0x43 'C'
font_rom[2144] <= 8'b00000000;
font_rom[2145] <= 8'b00000000;
font_rom[2146] <= 8'b00000000;
font_rom[2147] <= 8'b00000000;
font_rom[2148] <= 8'b00000000;
font_rom[2149] <= 8'b00000000;
font_rom[2150] <= 8'b00000000;
font_rom[2151] <= 8'b00000000;
font_rom[2152] <= 8'b00000000;
font_rom[2153] <= 8'b00000000;
font_rom[2154] <= 8'b00000011;
font_rom[2155] <= 8'b11100000;
font_rom[2156] <= 8'b00000111;
font_rom[2157] <= 8'b01100000;
font_rom[2158] <= 8'b00000110;
font_rom[2159] <= 8'b00000000;
font_rom[2160] <= 8'b00001100;
font_rom[2161] <= 8'b00000000;
font_rom[2162] <= 8'b00001100;
font_rom[2163] <= 8'b00000000;
font_rom[2164] <= 8'b00001100;
font_rom[2165] <= 8'b00000000;
font_rom[2166] <= 8'b00001100;
font_rom[2167] <= 8'b11000000;
font_rom[2168] <= 8'b00000111;
font_rom[2169] <= 8'b10000000;
font_rom[2170] <= 8'b00000000;
font_rom[2171] <= 8'b00000000;
font_rom[2172] <= 8'b00000000;
font_rom[2173] <= 8'b00000000;
font_rom[2174] <= 8'b00000000;
font_rom[2175] <= 8'b00000000;
//ASCII 0x44 'D'
font_rom[2176] <= 8'b00000000;
font_rom[2177] <= 8'b00000000;
font_rom[2178] <= 8'b00000000;
font_rom[2179] <= 8'b00000000;
font_rom[2180] <= 8'b00000000;
font_rom[2181] <= 8'b00000000;
font_rom[2182] <= 8'b00000000;
font_rom[2183] <= 8'b00000000;
font_rom[2184] <= 8'b00000000;
font_rom[2185] <= 8'b00000000;
font_rom[2186] <= 8'b00001110;
font_rom[2187] <= 8'b00000000;
font_rom[2188] <= 8'b00001111;
font_rom[2189] <= 8'b10000000;
font_rom[2190] <= 8'b00001100;
font_rom[2191] <= 8'b11100000;
font_rom[2192] <= 8'b00001100;
font_rom[2193] <= 8'b01100000;
font_rom[2194] <= 8'b00001100;
font_rom[2195] <= 8'b00100000;
font_rom[2196] <= 8'b00001100;
font_rom[2197] <= 8'b01100000;
font_rom[2198] <= 8'b00001100;
font_rom[2199] <= 8'b01100000;
font_rom[2200] <= 8'b00000111;
font_rom[2201] <= 8'b11000000;
font_rom[2202] <= 8'b00000000;
font_rom[2203] <= 8'b00000000;
font_rom[2204] <= 8'b00000000;
font_rom[2205] <= 8'b00000000;
font_rom[2206] <= 8'b00000000;
font_rom[2207] <= 8'b00000000;
//ASCII 0x45 'E'
font_rom[2208] <= 8'b00000000;
font_rom[2209] <= 8'b00000000;
font_rom[2210] <= 8'b00000000;
font_rom[2211] <= 8'b00000000;
font_rom[2212] <= 8'b00000000;
font_rom[2213] <= 8'b00000000;
font_rom[2214] <= 8'b00000000;
font_rom[2215] <= 8'b00000000;
font_rom[2216] <= 8'b00000000;
font_rom[2217] <= 8'b00000000;
font_rom[2218] <= 8'b00001111;
font_rom[2219] <= 8'b11100000;
font_rom[2220] <= 8'b00001100;
font_rom[2221] <= 8'b00000000;
font_rom[2222] <= 8'b00001100;
font_rom[2223] <= 8'b00000000;
font_rom[2224] <= 8'b00001111;
font_rom[2225] <= 8'b11000000;
font_rom[2226] <= 8'b00001100;
font_rom[2227] <= 8'b00000000;
font_rom[2228] <= 8'b00001100;
font_rom[2229] <= 8'b00000000;
font_rom[2230] <= 8'b00001100;
font_rom[2231] <= 8'b00000000;
font_rom[2232] <= 8'b00001111;
font_rom[2233] <= 8'b11000000;
font_rom[2234] <= 8'b00000000;
font_rom[2235] <= 8'b00000000;
font_rom[2236] <= 8'b00000000;
font_rom[2237] <= 8'b00000000;
font_rom[2238] <= 8'b00000000;
font_rom[2239] <= 8'b00000000;
//ASCII 0x46 'F'
font_rom[2240] <= 8'b00000000;
font_rom[2241] <= 8'b00000000;
font_rom[2242] <= 8'b00000000;
font_rom[2243] <= 8'b00000000;
font_rom[2244] <= 8'b00000000;
font_rom[2245] <= 8'b00000000;
font_rom[2246] <= 8'b00000000;
font_rom[2247] <= 8'b00000000;
font_rom[2248] <= 8'b00000000;
font_rom[2249] <= 8'b00000000;
font_rom[2250] <= 8'b00000111;
font_rom[2251] <= 8'b11100000;
font_rom[2252] <= 8'b00000110;
font_rom[2253] <= 8'b00000000;
font_rom[2254] <= 8'b00000110;
font_rom[2255] <= 8'b00000000;
font_rom[2256] <= 8'b00000111;
font_rom[2257] <= 8'b11100000;
font_rom[2258] <= 8'b00000110;
font_rom[2259] <= 8'b00000000;
font_rom[2260] <= 8'b00000110;
font_rom[2261] <= 8'b00000000;
font_rom[2262] <= 8'b00000110;
font_rom[2263] <= 8'b00000000;
font_rom[2264] <= 8'b00000110;
font_rom[2265] <= 8'b00000000;
font_rom[2266] <= 8'b00000000;
font_rom[2267] <= 8'b00000000;
font_rom[2268] <= 8'b00000000;
font_rom[2269] <= 8'b00000000;
font_rom[2270] <= 8'b00000000;
font_rom[2271] <= 8'b00000000;
//ASCII 0x47 'G'
font_rom[2272] <= 8'b00000000;
font_rom[2273] <= 8'b00000000;
font_rom[2274] <= 8'b00000000;
font_rom[2275] <= 8'b00000000;
font_rom[2276] <= 8'b00000000;
font_rom[2277] <= 8'b00000000;
font_rom[2278] <= 8'b00000000;
font_rom[2279] <= 8'b00000000;
font_rom[2280] <= 8'b00000000;
font_rom[2281] <= 8'b00000000;
font_rom[2282] <= 8'b00000011;
font_rom[2283] <= 8'b11000000;
font_rom[2284] <= 8'b00000110;
font_rom[2285] <= 8'b01100000;
font_rom[2286] <= 8'b00000110;
font_rom[2287] <= 8'b00000000;
font_rom[2288] <= 8'b00001100;
font_rom[2289] <= 8'b00000000;
font_rom[2290] <= 8'b00001111;
font_rom[2291] <= 8'b11100000;
font_rom[2292] <= 8'b00001100;
font_rom[2293] <= 8'b01100000;
font_rom[2294] <= 8'b00001100;
font_rom[2295] <= 8'b01100000;
font_rom[2296] <= 8'b00000111;
font_rom[2297] <= 8'b11000000;
font_rom[2298] <= 8'b00000000;
font_rom[2299] <= 8'b00000000;
font_rom[2300] <= 8'b00000000;
font_rom[2301] <= 8'b00000000;
font_rom[2302] <= 8'b00000000;
font_rom[2303] <= 8'b00000000;
//ASCII 0x48 'H'
font_rom[2304] <= 8'b00000000;
font_rom[2305] <= 8'b00000000;
font_rom[2306] <= 8'b00000000;
font_rom[2307] <= 8'b00000000;
font_rom[2308] <= 8'b00000000;
font_rom[2309] <= 8'b00000000;
font_rom[2310] <= 8'b00000000;
font_rom[2311] <= 8'b00000000;
font_rom[2312] <= 8'b00000000;
font_rom[2313] <= 8'b00000000;
font_rom[2314] <= 8'b00001100;
font_rom[2315] <= 8'b00110000;
font_rom[2316] <= 8'b00001100;
font_rom[2317] <= 8'b00100000;
font_rom[2318] <= 8'b00001100;
font_rom[2319] <= 8'b00100000;
font_rom[2320] <= 8'b00001111;
font_rom[2321] <= 8'b11100000;
font_rom[2322] <= 8'b00001110;
font_rom[2323] <= 8'b01100000;
font_rom[2324] <= 8'b00001100;
font_rom[2325] <= 8'b01100000;
font_rom[2326] <= 8'b00001100;
font_rom[2327] <= 8'b01100000;
font_rom[2328] <= 8'b00001100;
font_rom[2329] <= 8'b01100000;
font_rom[2330] <= 8'b00000000;
font_rom[2331] <= 8'b00000000;
font_rom[2332] <= 8'b00000000;
font_rom[2333] <= 8'b00000000;
font_rom[2334] <= 8'b00000000;
font_rom[2335] <= 8'b00000000;
//ASCII 0x49 'I'
font_rom[2336] <= 8'b00000000;
font_rom[2337] <= 8'b00000000;
font_rom[2338] <= 8'b00000000;
font_rom[2339] <= 8'b00000000;
font_rom[2340] <= 8'b00000000;
font_rom[2341] <= 8'b00000000;
font_rom[2342] <= 8'b00000000;
font_rom[2343] <= 8'b00000000;
font_rom[2344] <= 8'b00000000;
font_rom[2345] <= 8'b00000000;
font_rom[2346] <= 8'b00000111;
font_rom[2347] <= 8'b11100000;
font_rom[2348] <= 8'b00000001;
font_rom[2349] <= 8'b00000000;
font_rom[2350] <= 8'b00000011;
font_rom[2351] <= 8'b00000000;
font_rom[2352] <= 8'b00000011;
font_rom[2353] <= 8'b00000000;
font_rom[2354] <= 8'b00000011;
font_rom[2355] <= 8'b00000000;
font_rom[2356] <= 8'b00000001;
font_rom[2357] <= 8'b00000000;
font_rom[2358] <= 8'b00000001;
font_rom[2359] <= 8'b00000000;
font_rom[2360] <= 8'b00000111;
font_rom[2361] <= 8'b11000000;
font_rom[2362] <= 8'b00000000;
font_rom[2363] <= 8'b00000000;
font_rom[2364] <= 8'b00000000;
font_rom[2365] <= 8'b00000000;
font_rom[2366] <= 8'b00000000;
font_rom[2367] <= 8'b00000000;
//ASCII 0x4A 'J'
font_rom[2368] <= 8'b00000000;
font_rom[2369] <= 8'b00000000;
font_rom[2370] <= 8'b00000000;
font_rom[2371] <= 8'b00000000;
font_rom[2372] <= 8'b00000000;
font_rom[2373] <= 8'b00000000;
font_rom[2374] <= 8'b00000000;
font_rom[2375] <= 8'b00000000;
font_rom[2376] <= 8'b00000000;
font_rom[2377] <= 8'b00000000;
font_rom[2378] <= 8'b00000111;
font_rom[2379] <= 8'b11100000;
font_rom[2380] <= 8'b00000001;
font_rom[2381] <= 8'b10000000;
font_rom[2382] <= 8'b00000001;
font_rom[2383] <= 8'b10000000;
font_rom[2384] <= 8'b00000001;
font_rom[2385] <= 8'b10000000;
font_rom[2386] <= 8'b00000001;
font_rom[2387] <= 8'b10000000;
font_rom[2388] <= 8'b00001101;
font_rom[2389] <= 8'b10000000;
font_rom[2390] <= 8'b00001101;
font_rom[2391] <= 8'b10000000;
font_rom[2392] <= 8'b00000111;
font_rom[2393] <= 8'b00000000;
font_rom[2394] <= 8'b00000000;
font_rom[2395] <= 8'b00000000;
font_rom[2396] <= 8'b00000000;
font_rom[2397] <= 8'b00000000;
font_rom[2398] <= 8'b00000000;
font_rom[2399] <= 8'b00000000;
//ASCII 0x4B 'K'
font_rom[2400] <= 8'b00000000;
font_rom[2401] <= 8'b00000000;
font_rom[2402] <= 8'b00000000;
font_rom[2403] <= 8'b00000000;
font_rom[2404] <= 8'b00000000;
font_rom[2405] <= 8'b00000000;
font_rom[2406] <= 8'b00000000;
font_rom[2407] <= 8'b00000000;
font_rom[2408] <= 8'b00000000;
font_rom[2409] <= 8'b00000000;
font_rom[2410] <= 8'b00000100;
font_rom[2411] <= 8'b11100000;
font_rom[2412] <= 8'b00000100;
font_rom[2413] <= 8'b11000000;
font_rom[2414] <= 8'b00000101;
font_rom[2415] <= 8'b10000000;
font_rom[2416] <= 8'b00000111;
font_rom[2417] <= 8'b00000000;
font_rom[2418] <= 8'b00000111;
font_rom[2419] <= 8'b00000000;
font_rom[2420] <= 8'b00000111;
font_rom[2421] <= 8'b10000000;
font_rom[2422] <= 8'b00000101;
font_rom[2423] <= 8'b11000000;
font_rom[2424] <= 8'b00000100;
font_rom[2425] <= 8'b11100000;
font_rom[2426] <= 8'b00000000;
font_rom[2427] <= 8'b00000000;
font_rom[2428] <= 8'b00000000;
font_rom[2429] <= 8'b00000000;
font_rom[2430] <= 8'b00000000;
font_rom[2431] <= 8'b00000000;
//ASCII 0x4C 'L'
font_rom[2432] <= 8'b00000000;
font_rom[2433] <= 8'b00000000;
font_rom[2434] <= 8'b00000000;
font_rom[2435] <= 8'b00000000;
font_rom[2436] <= 8'b00000000;
font_rom[2437] <= 8'b00000000;
font_rom[2438] <= 8'b00000000;
font_rom[2439] <= 8'b00000000;
font_rom[2440] <= 8'b00000000;
font_rom[2441] <= 8'b00000000;
font_rom[2442] <= 8'b00000110;
font_rom[2443] <= 8'b00000000;
font_rom[2444] <= 8'b00000110;
font_rom[2445] <= 8'b00000000;
font_rom[2446] <= 8'b00000110;
font_rom[2447] <= 8'b00000000;
font_rom[2448] <= 8'b00000110;
font_rom[2449] <= 8'b00000000;
font_rom[2450] <= 8'b00000110;
font_rom[2451] <= 8'b00000000;
font_rom[2452] <= 8'b00000110;
font_rom[2453] <= 8'b00000000;
font_rom[2454] <= 8'b00000110;
font_rom[2455] <= 8'b00000000;
font_rom[2456] <= 8'b00000111;
font_rom[2457] <= 8'b11100000;
font_rom[2458] <= 8'b00000000;
font_rom[2459] <= 8'b00000000;
font_rom[2460] <= 8'b00000000;
font_rom[2461] <= 8'b00000000;
font_rom[2462] <= 8'b00000000;
font_rom[2463] <= 8'b00000000;
//ASCII 0x4D 'M'
font_rom[2464] <= 8'b00000000;
font_rom[2465] <= 8'b00000000;
font_rom[2466] <= 8'b00000000;
font_rom[2467] <= 8'b00000000;
font_rom[2468] <= 8'b00000000;
font_rom[2469] <= 8'b00000000;
font_rom[2470] <= 8'b00000000;
font_rom[2471] <= 8'b00000000;
font_rom[2472] <= 8'b00000000;
font_rom[2473] <= 8'b00000000;
font_rom[2474] <= 8'b00000110;
font_rom[2475] <= 8'b01100000;
font_rom[2476] <= 8'b00001110;
font_rom[2477] <= 8'b01100000;
font_rom[2478] <= 8'b00001110;
font_rom[2479] <= 8'b11100000;
font_rom[2480] <= 8'b00001110;
font_rom[2481] <= 8'b11100000;
font_rom[2482] <= 8'b00001110;
font_rom[2483] <= 8'b11110000;
font_rom[2484] <= 8'b00011011;
font_rom[2485] <= 8'b10110000;
font_rom[2486] <= 8'b00011011;
font_rom[2487] <= 8'b10110000;
font_rom[2488] <= 8'b00011011;
font_rom[2489] <= 8'b10110000;
font_rom[2490] <= 8'b00000000;
font_rom[2491] <= 8'b00000000;
font_rom[2492] <= 8'b00000000;
font_rom[2493] <= 8'b00000000;
font_rom[2494] <= 8'b00000000;
font_rom[2495] <= 8'b00000000;
//ASCII 0x4E 'N'
font_rom[2496] <= 8'b00000000;
font_rom[2497] <= 8'b00000000;
font_rom[2498] <= 8'b00000000;
font_rom[2499] <= 8'b00000000;
font_rom[2500] <= 8'b00000000;
font_rom[2501] <= 8'b00000000;
font_rom[2502] <= 8'b00000000;
font_rom[2503] <= 8'b00000000;
font_rom[2504] <= 8'b00000000;
font_rom[2505] <= 8'b00000000;
font_rom[2506] <= 8'b00001100;
font_rom[2507] <= 8'b00110000;
font_rom[2508] <= 8'b00001110;
font_rom[2509] <= 8'b00110000;
font_rom[2510] <= 8'b00001111;
font_rom[2511] <= 8'b00011000;
font_rom[2512] <= 8'b00001111;
font_rom[2513] <= 8'b00011000;
font_rom[2514] <= 8'b00001101;
font_rom[2515] <= 8'b10011000;
font_rom[2516] <= 8'b00001100;
font_rom[2517] <= 8'b11011000;
font_rom[2518] <= 8'b00001100;
font_rom[2519] <= 8'b01111000;
font_rom[2520] <= 8'b00001100;
font_rom[2521] <= 8'b00110000;
font_rom[2522] <= 8'b00000000;
font_rom[2523] <= 8'b00000000;
font_rom[2524] <= 8'b00000000;
font_rom[2525] <= 8'b00000000;
font_rom[2526] <= 8'b00000000;
font_rom[2527] <= 8'b00000000;
//ASCII 0x4F 'O'
font_rom[2528] <= 8'b00000000;
font_rom[2529] <= 8'b00000000;
font_rom[2530] <= 8'b00000000;
font_rom[2531] <= 8'b00000000;
font_rom[2532] <= 8'b00000000;
font_rom[2533] <= 8'b00000000;
font_rom[2534] <= 8'b00000000;
font_rom[2535] <= 8'b00000000;
font_rom[2536] <= 8'b00000000;
font_rom[2537] <= 8'b00000000;
font_rom[2538] <= 8'b00000011;
font_rom[2539] <= 8'b11100000;
font_rom[2540] <= 8'b00000110;
font_rom[2541] <= 8'b00110000;
font_rom[2542] <= 8'b00001100;
font_rom[2543] <= 8'b00011000;
font_rom[2544] <= 8'b00001100;
font_rom[2545] <= 8'b00011000;
font_rom[2546] <= 8'b00001100;
font_rom[2547] <= 8'b00010000;
font_rom[2548] <= 8'b00001100;
font_rom[2549] <= 8'b00110000;
font_rom[2550] <= 8'b00001110;
font_rom[2551] <= 8'b01100000;
font_rom[2552] <= 8'b00000011;
font_rom[2553] <= 8'b11000000;
font_rom[2554] <= 8'b00000000;
font_rom[2555] <= 8'b00000000;
font_rom[2556] <= 8'b00000000;
font_rom[2557] <= 8'b00000000;
font_rom[2558] <= 8'b00000000;
font_rom[2559] <= 8'b00000000;
//ASCII 0x50 'P'
font_rom[2560] <= 8'b00000000;
font_rom[2561] <= 8'b00000000;
font_rom[2562] <= 8'b00000000;
font_rom[2563] <= 8'b00000000;
font_rom[2564] <= 8'b00000000;
font_rom[2565] <= 8'b00000000;
font_rom[2566] <= 8'b00000000;
font_rom[2567] <= 8'b00000000;
font_rom[2568] <= 8'b00000000;
font_rom[2569] <= 8'b00000000;
font_rom[2570] <= 8'b00000111;
font_rom[2571] <= 8'b10000000;
font_rom[2572] <= 8'b00000110;
font_rom[2573] <= 8'b11000000;
font_rom[2574] <= 8'b00000110;
font_rom[2575] <= 8'b01100000;
font_rom[2576] <= 8'b00000110;
font_rom[2577] <= 8'b01100000;
font_rom[2578] <= 8'b00000110;
font_rom[2579] <= 8'b11000000;
font_rom[2580] <= 8'b00000111;
font_rom[2581] <= 8'b10000000;
font_rom[2582] <= 8'b00000110;
font_rom[2583] <= 8'b00000000;
font_rom[2584] <= 8'b00000110;
font_rom[2585] <= 8'b00000000;
font_rom[2586] <= 8'b00000000;
font_rom[2587] <= 8'b00000000;
font_rom[2588] <= 8'b00000000;
font_rom[2589] <= 8'b00000000;
font_rom[2590] <= 8'b00000000;
font_rom[2591] <= 8'b00000000;
//ASCII 0x51 'Q'
font_rom[2592] <= 8'b00000000;
font_rom[2593] <= 8'b00000000;
font_rom[2594] <= 8'b00000000;
font_rom[2595] <= 8'b00000000;
font_rom[2596] <= 8'b00000000;
font_rom[2597] <= 8'b00000000;
font_rom[2598] <= 8'b00000000;
font_rom[2599] <= 8'b00000000;
font_rom[2600] <= 8'b00000000;
font_rom[2601] <= 8'b00000000;
font_rom[2602] <= 8'b00000111;
font_rom[2603] <= 8'b11100000;
font_rom[2604] <= 8'b00001100;
font_rom[2605] <= 8'b01110000;
font_rom[2606] <= 8'b00011000;
font_rom[2607] <= 8'b00110000;
font_rom[2608] <= 8'b00011000;
font_rom[2609] <= 8'b00010000;
font_rom[2610] <= 8'b00011000;
font_rom[2611] <= 8'b00011000;
font_rom[2612] <= 8'b00011001;
font_rom[2613] <= 8'b10110000;
font_rom[2614] <= 8'b00001101;
font_rom[2615] <= 8'b11110000;
font_rom[2616] <= 8'b00000111;
font_rom[2617] <= 8'b11100000;
font_rom[2618] <= 8'b00000000;
font_rom[2619] <= 8'b00110000;
font_rom[2620] <= 8'b00000000;
font_rom[2621] <= 8'b00011000;
font_rom[2622] <= 8'b00000000;
font_rom[2623] <= 8'b00000000;
//ASCII 0x52 'R'
font_rom[2624] <= 8'b00000000;
font_rom[2625] <= 8'b00000000;
font_rom[2626] <= 8'b00000000;
font_rom[2627] <= 8'b00000000;
font_rom[2628] <= 8'b00000000;
font_rom[2629] <= 8'b00000000;
font_rom[2630] <= 8'b00000000;
font_rom[2631] <= 8'b00000000;
font_rom[2632] <= 8'b00000000;
font_rom[2633] <= 8'b00000000;
font_rom[2634] <= 8'b00001111;
font_rom[2635] <= 8'b00000000;
font_rom[2636] <= 8'b00001101;
font_rom[2637] <= 8'b11000000;
font_rom[2638] <= 8'b00001100;
font_rom[2639] <= 8'b11000000;
font_rom[2640] <= 8'b00001100;
font_rom[2641] <= 8'b11000000;
font_rom[2642] <= 8'b00001111;
font_rom[2643] <= 8'b10000000;
font_rom[2644] <= 8'b00001111;
font_rom[2645] <= 8'b10000000;
font_rom[2646] <= 8'b00001100;
font_rom[2647] <= 8'b11000000;
font_rom[2648] <= 8'b00001100;
font_rom[2649] <= 8'b01100000;
font_rom[2650] <= 8'b00000000;
font_rom[2651] <= 8'b00000000;
font_rom[2652] <= 8'b00000000;
font_rom[2653] <= 8'b00000000;
font_rom[2654] <= 8'b00000000;
font_rom[2655] <= 8'b00000000;
//ASCII 0x53 'S'
font_rom[2656] <= 8'b00000000;
font_rom[2657] <= 8'b00000000;
font_rom[2658] <= 8'b00000000;
font_rom[2659] <= 8'b00000000;
font_rom[2660] <= 8'b00000000;
font_rom[2661] <= 8'b00000000;
font_rom[2662] <= 8'b00000000;
font_rom[2663] <= 8'b00000000;
font_rom[2664] <= 8'b00000000;
font_rom[2665] <= 8'b00000000;
font_rom[2666] <= 8'b00000011;
font_rom[2667] <= 8'b11100000;
font_rom[2668] <= 8'b00000110;
font_rom[2669] <= 8'b00000000;
font_rom[2670] <= 8'b00000110;
font_rom[2671] <= 8'b00000000;
font_rom[2672] <= 8'b00000111;
font_rom[2673] <= 8'b11000000;
font_rom[2674] <= 8'b00000000;
font_rom[2675] <= 8'b01100000;
font_rom[2676] <= 8'b00000000;
font_rom[2677] <= 8'b00100000;
font_rom[2678] <= 8'b00001100;
font_rom[2679] <= 8'b01100000;
font_rom[2680] <= 8'b00000111;
font_rom[2681] <= 8'b11000000;
font_rom[2682] <= 8'b00000000;
font_rom[2683] <= 8'b00000000;
font_rom[2684] <= 8'b00000000;
font_rom[2685] <= 8'b00000000;
font_rom[2686] <= 8'b00000000;
font_rom[2687] <= 8'b00000000;
//ASCII 0x54 'T'
font_rom[2688] <= 8'b00000000;
font_rom[2689] <= 8'b00000000;
font_rom[2690] <= 8'b00000000;
font_rom[2691] <= 8'b00000000;
font_rom[2692] <= 8'b00000000;
font_rom[2693] <= 8'b00000000;
font_rom[2694] <= 8'b00000000;
font_rom[2695] <= 8'b00000000;
font_rom[2696] <= 8'b00000000;
font_rom[2697] <= 8'b00000000;
font_rom[2698] <= 8'b00001111;
font_rom[2699] <= 8'b11110000;
font_rom[2700] <= 8'b00000011;
font_rom[2701] <= 8'b00000000;
font_rom[2702] <= 8'b00000011;
font_rom[2703] <= 8'b00000000;
font_rom[2704] <= 8'b00000001;
font_rom[2705] <= 8'b00000000;
font_rom[2706] <= 8'b00000001;
font_rom[2707] <= 8'b00000000;
font_rom[2708] <= 8'b00000001;
font_rom[2709] <= 8'b00000000;
font_rom[2710] <= 8'b00000001;
font_rom[2711] <= 8'b00000000;
font_rom[2712] <= 8'b00000001;
font_rom[2713] <= 8'b00000000;
font_rom[2714] <= 8'b00000000;
font_rom[2715] <= 8'b00000000;
font_rom[2716] <= 8'b00000000;
font_rom[2717] <= 8'b00000000;
font_rom[2718] <= 8'b00000000;
font_rom[2719] <= 8'b00000000;
//ASCII 0x55 'U'
font_rom[2720] <= 8'b00000000;
font_rom[2721] <= 8'b00000000;
font_rom[2722] <= 8'b00000000;
font_rom[2723] <= 8'b00000000;
font_rom[2724] <= 8'b00000000;
font_rom[2725] <= 8'b00000000;
font_rom[2726] <= 8'b00000000;
font_rom[2727] <= 8'b00000000;
font_rom[2728] <= 8'b00000000;
font_rom[2729] <= 8'b00000000;
font_rom[2730] <= 8'b00001100;
font_rom[2731] <= 8'b00100000;
font_rom[2732] <= 8'b00001100;
font_rom[2733] <= 8'b00100000;
font_rom[2734] <= 8'b00001100;
font_rom[2735] <= 8'b00100000;
font_rom[2736] <= 8'b00001100;
font_rom[2737] <= 8'b01100000;
font_rom[2738] <= 8'b00001100;
font_rom[2739] <= 8'b01100000;
font_rom[2740] <= 8'b00001100;
font_rom[2741] <= 8'b01100000;
font_rom[2742] <= 8'b00000100;
font_rom[2743] <= 8'b01100000;
font_rom[2744] <= 8'b00000111;
font_rom[2745] <= 8'b11000000;
font_rom[2746] <= 8'b00000000;
font_rom[2747] <= 8'b00000000;
font_rom[2748] <= 8'b00000000;
font_rom[2749] <= 8'b00000000;
font_rom[2750] <= 8'b00000000;
font_rom[2751] <= 8'b00000000;
//ASCII 0x56 'V'
font_rom[2752] <= 8'b00000000;
font_rom[2753] <= 8'b00000000;
font_rom[2754] <= 8'b00000000;
font_rom[2755] <= 8'b00000000;
font_rom[2756] <= 8'b00000000;
font_rom[2757] <= 8'b00000000;
font_rom[2758] <= 8'b00000000;
font_rom[2759] <= 8'b00000000;
font_rom[2760] <= 8'b00000000;
font_rom[2761] <= 8'b00000000;
font_rom[2762] <= 8'b00001100;
font_rom[2763] <= 8'b01100000;
font_rom[2764] <= 8'b00001100;
font_rom[2765] <= 8'b01100000;
font_rom[2766] <= 8'b00000100;
font_rom[2767] <= 8'b11000000;
font_rom[2768] <= 8'b00000110;
font_rom[2769] <= 8'b11000000;
font_rom[2770] <= 8'b00000110;
font_rom[2771] <= 8'b11000000;
font_rom[2772] <= 8'b00000111;
font_rom[2773] <= 8'b10000000;
font_rom[2774] <= 8'b00000011;
font_rom[2775] <= 8'b10000000;
font_rom[2776] <= 8'b00000011;
font_rom[2777] <= 8'b00000000;
font_rom[2778] <= 8'b00000000;
font_rom[2779] <= 8'b00000000;
font_rom[2780] <= 8'b00000000;
font_rom[2781] <= 8'b00000000;
font_rom[2782] <= 8'b00000000;
font_rom[2783] <= 8'b00000000;
//ASCII 0x57 'W'
font_rom[2784] <= 8'b00000000;
font_rom[2785] <= 8'b00000000;
font_rom[2786] <= 8'b00000000;
font_rom[2787] <= 8'b00000000;
font_rom[2788] <= 8'b00000000;
font_rom[2789] <= 8'b00000000;
font_rom[2790] <= 8'b00000000;
font_rom[2791] <= 8'b00000000;
font_rom[2792] <= 8'b00000000;
font_rom[2793] <= 8'b00000000;
font_rom[2794] <= 8'b00110001;
font_rom[2795] <= 8'b10011000;
font_rom[2796] <= 8'b00110011;
font_rom[2797] <= 8'b10011000;
font_rom[2798] <= 8'b00011011;
font_rom[2799] <= 8'b10011000;
font_rom[2800] <= 8'b00011011;
font_rom[2801] <= 8'b10110000;
font_rom[2802] <= 8'b00011110;
font_rom[2803] <= 8'b10110000;
font_rom[2804] <= 8'b00011110;
font_rom[2805] <= 8'b11100000;
font_rom[2806] <= 8'b00001100;
font_rom[2807] <= 8'b11100000;
font_rom[2808] <= 8'b00001100;
font_rom[2809] <= 8'b11100000;
font_rom[2810] <= 8'b00000000;
font_rom[2811] <= 8'b00000000;
font_rom[2812] <= 8'b00000000;
font_rom[2813] <= 8'b00000000;
font_rom[2814] <= 8'b00000000;
font_rom[2815] <= 8'b00000000;
//ASCII 0x58 'X'
font_rom[2816] <= 8'b00000000;
font_rom[2817] <= 8'b00000000;
font_rom[2818] <= 8'b00000000;
font_rom[2819] <= 8'b00000000;
font_rom[2820] <= 8'b00000000;
font_rom[2821] <= 8'b00000000;
font_rom[2822] <= 8'b00000000;
font_rom[2823] <= 8'b00000000;
font_rom[2824] <= 8'b00000000;
font_rom[2825] <= 8'b00000000;
font_rom[2826] <= 8'b00001100;
font_rom[2827] <= 8'b00110000;
font_rom[2828] <= 8'b00000110;
font_rom[2829] <= 8'b01100000;
font_rom[2830] <= 8'b00000011;
font_rom[2831] <= 8'b11000000;
font_rom[2832] <= 8'b00000011;
font_rom[2833] <= 8'b10000000;
font_rom[2834] <= 8'b00000011;
font_rom[2835] <= 8'b10000000;
font_rom[2836] <= 8'b00000111;
font_rom[2837] <= 8'b11000000;
font_rom[2838] <= 8'b00001110;
font_rom[2839] <= 8'b01100000;
font_rom[2840] <= 8'b00001100;
font_rom[2841] <= 8'b01110000;
font_rom[2842] <= 8'b00000000;
font_rom[2843] <= 8'b00000000;
font_rom[2844] <= 8'b00000000;
font_rom[2845] <= 8'b00000000;
font_rom[2846] <= 8'b00000000;
font_rom[2847] <= 8'b00000000;
//ASCII 0x59 'Y'
font_rom[2848] <= 8'b00000000;
font_rom[2849] <= 8'b00000000;
font_rom[2850] <= 8'b00000000;
font_rom[2851] <= 8'b00000000;
font_rom[2852] <= 8'b00000000;
font_rom[2853] <= 8'b00000000;
font_rom[2854] <= 8'b00000000;
font_rom[2855] <= 8'b00000000;
font_rom[2856] <= 8'b00000000;
font_rom[2857] <= 8'b00000000;
font_rom[2858] <= 8'b00011000;
font_rom[2859] <= 8'b01100000;
font_rom[2860] <= 8'b00001100;
font_rom[2861] <= 8'b11000000;
font_rom[2862] <= 8'b00000110;
font_rom[2863] <= 8'b11000000;
font_rom[2864] <= 8'b00000111;
font_rom[2865] <= 8'b10000000;
font_rom[2866] <= 8'b00000011;
font_rom[2867] <= 8'b10000000;
font_rom[2868] <= 8'b00000011;
font_rom[2869] <= 8'b10000000;
font_rom[2870] <= 8'b00000011;
font_rom[2871] <= 8'b00000000;
font_rom[2872] <= 8'b00000110;
font_rom[2873] <= 8'b00000000;
font_rom[2874] <= 8'b00000000;
font_rom[2875] <= 8'b00000000;
font_rom[2876] <= 8'b00000000;
font_rom[2877] <= 8'b00000000;
font_rom[2878] <= 8'b00000000;
font_rom[2879] <= 8'b00000000;
//ASCII 0x5A 'Z'
font_rom[2880] <= 8'b00000000;
font_rom[2881] <= 8'b00000000;
font_rom[2882] <= 8'b00000000;
font_rom[2883] <= 8'b00000000;
font_rom[2884] <= 8'b00000000;
font_rom[2885] <= 8'b00000000;
font_rom[2886] <= 8'b00000000;
font_rom[2887] <= 8'b00000000;
font_rom[2888] <= 8'b00000000;
font_rom[2889] <= 8'b00000000;
font_rom[2890] <= 8'b00001111;
font_rom[2891] <= 8'b11110000;
font_rom[2892] <= 8'b00000000;
font_rom[2893] <= 8'b11100000;
font_rom[2894] <= 8'b00000001;
font_rom[2895] <= 8'b10000000;
font_rom[2896] <= 8'b00000011;
font_rom[2897] <= 8'b00000000;
font_rom[2898] <= 8'b00000011;
font_rom[2899] <= 8'b00000000;
font_rom[2900] <= 8'b00000110;
font_rom[2901] <= 8'b00000000;
font_rom[2902] <= 8'b00001100;
font_rom[2903] <= 8'b00000000;
font_rom[2904] <= 8'b00001111;
font_rom[2905] <= 8'b11110000;
font_rom[2906] <= 8'b00000000;
font_rom[2907] <= 8'b00000000;
font_rom[2908] <= 8'b00000000;
font_rom[2909] <= 8'b00000000;
font_rom[2910] <= 8'b00000000;
font_rom[2911] <= 8'b00000000;
//ASCII 0x5B '['
font_rom[2912] <= 8'b00000000;
font_rom[2913] <= 8'b00000000;
font_rom[2914] <= 8'b00000000;
font_rom[2915] <= 8'b00000000;
font_rom[2916] <= 8'b00000000;
font_rom[2917] <= 8'b00000000;
font_rom[2918] <= 8'b00000000;
font_rom[2919] <= 8'b00000000;
font_rom[2920] <= 8'b00000011;
font_rom[2921] <= 8'b11000000;
font_rom[2922] <= 8'b00000011;
font_rom[2923] <= 8'b00000000;
font_rom[2924] <= 8'b00000011;
font_rom[2925] <= 8'b00000000;
font_rom[2926] <= 8'b00000011;
font_rom[2927] <= 8'b00000000;
font_rom[2928] <= 8'b00000011;
font_rom[2929] <= 8'b00000000;
font_rom[2930] <= 8'b00000011;
font_rom[2931] <= 8'b00000000;
font_rom[2932] <= 8'b00000011;
font_rom[2933] <= 8'b00000000;
font_rom[2934] <= 8'b00000011;
font_rom[2935] <= 8'b00000000;
font_rom[2936] <= 8'b00000011;
font_rom[2937] <= 8'b00000000;
font_rom[2938] <= 8'b00000011;
font_rom[2939] <= 8'b00000000;
font_rom[2940] <= 8'b00000011;
font_rom[2941] <= 8'b11000000;
font_rom[2942] <= 8'b00000000;
font_rom[2943] <= 8'b00000000;
//ASCII 0x5C '\'
font_rom[2944] <= 8'b00000000;
font_rom[2945] <= 8'b00000000;
font_rom[2946] <= 8'b00000000;
font_rom[2947] <= 8'b00000000;
font_rom[2948] <= 8'b00000000;
font_rom[2949] <= 8'b00000000;
font_rom[2950] <= 8'b00000000;
font_rom[2951] <= 8'b00000000;
font_rom[2952] <= 8'b00000000;
font_rom[2953] <= 8'b00000000;
font_rom[2954] <= 8'b00000011;
font_rom[2955] <= 8'b00000000;
font_rom[2956] <= 8'b00000001;
font_rom[2957] <= 8'b10000000;
font_rom[2958] <= 8'b00000001;
font_rom[2959] <= 8'b10000000;
font_rom[2960] <= 8'b00000000;
font_rom[2961] <= 8'b11000000;
font_rom[2962] <= 8'b00000000;
font_rom[2963] <= 8'b11000000;
font_rom[2964] <= 8'b00000000;
font_rom[2965] <= 8'b11000000;
font_rom[2966] <= 8'b00000000;
font_rom[2967] <= 8'b01100000;
font_rom[2968] <= 8'b00000000;
font_rom[2969] <= 8'b01100000;
font_rom[2970] <= 8'b00000000;
font_rom[2971] <= 8'b00110000;
font_rom[2972] <= 8'b00000000;
font_rom[2973] <= 8'b00000000;
font_rom[2974] <= 8'b00000000;
font_rom[2975] <= 8'b00000000;
//ASCII 0x5D ']'
font_rom[2976] <= 8'b00000000;
font_rom[2977] <= 8'b00000000;
font_rom[2978] <= 8'b00000000;
font_rom[2979] <= 8'b00000000;
font_rom[2980] <= 8'b00000000;
font_rom[2981] <= 8'b00000000;
font_rom[2982] <= 8'b00000000;
font_rom[2983] <= 8'b00000000;
font_rom[2984] <= 8'b00000011;
font_rom[2985] <= 8'b11000000;
font_rom[2986] <= 8'b00000000;
font_rom[2987] <= 8'b11000000;
font_rom[2988] <= 8'b00000000;
font_rom[2989] <= 8'b11000000;
font_rom[2990] <= 8'b00000000;
font_rom[2991] <= 8'b11000000;
font_rom[2992] <= 8'b00000000;
font_rom[2993] <= 8'b11000000;
font_rom[2994] <= 8'b00000000;
font_rom[2995] <= 8'b11000000;
font_rom[2996] <= 8'b00000000;
font_rom[2997] <= 8'b11000000;
font_rom[2998] <= 8'b00000000;
font_rom[2999] <= 8'b11000000;
font_rom[3000] <= 8'b00000000;
font_rom[3001] <= 8'b11000000;
font_rom[3002] <= 8'b00000000;
font_rom[3003] <= 8'b11000000;
font_rom[3004] <= 8'b00000011;
font_rom[3005] <= 8'b11000000;
font_rom[3006] <= 8'b00000000;
font_rom[3007] <= 8'b00000000;
//ASCII 0x5E '^'
font_rom[3008] <= 8'b00000000;
font_rom[3009] <= 8'b00000000;
font_rom[3010] <= 8'b00000000;
font_rom[3011] <= 8'b00000000;
font_rom[3012] <= 8'b00000000;
font_rom[3013] <= 8'b00000000;
font_rom[3014] <= 8'b00000000;
font_rom[3015] <= 8'b00000000;
font_rom[3016] <= 8'b00000000;
font_rom[3017] <= 8'b11000000;
font_rom[3018] <= 8'b00000001;
font_rom[3019] <= 8'b11100000;
font_rom[3020] <= 8'b00000011;
font_rom[3021] <= 8'b00110000;
font_rom[3022] <= 8'b00000000;
font_rom[3023] <= 8'b00000000;
font_rom[3024] <= 8'b00000000;
font_rom[3025] <= 8'b00000000;
font_rom[3026] <= 8'b00000000;
font_rom[3027] <= 8'b00000000;
font_rom[3028] <= 8'b00000000;
font_rom[3029] <= 8'b00000000;
font_rom[3030] <= 8'b00000000;
font_rom[3031] <= 8'b00000000;
font_rom[3032] <= 8'b00000000;
font_rom[3033] <= 8'b00000000;
font_rom[3034] <= 8'b00000000;
font_rom[3035] <= 8'b00000000;
font_rom[3036] <= 8'b00000000;
font_rom[3037] <= 8'b00000000;
font_rom[3038] <= 8'b00000000;
font_rom[3039] <= 8'b00000000;
//ASCII 0x5F '_'
font_rom[3040] <= 8'b00000000;
font_rom[3041] <= 8'b00000000;
font_rom[3042] <= 8'b00000000;
font_rom[3043] <= 8'b00000000;
font_rom[3044] <= 8'b00000000;
font_rom[3045] <= 8'b00000000;
font_rom[3046] <= 8'b00000000;
font_rom[3047] <= 8'b00000000;
font_rom[3048] <= 8'b00000000;
font_rom[3049] <= 8'b00000000;
font_rom[3050] <= 8'b00000000;
font_rom[3051] <= 8'b00000000;
font_rom[3052] <= 8'b00000000;
font_rom[3053] <= 8'b00000000;
font_rom[3054] <= 8'b00000000;
font_rom[3055] <= 8'b00000000;
font_rom[3056] <= 8'b00000000;
font_rom[3057] <= 8'b00000000;
font_rom[3058] <= 8'b00000000;
font_rom[3059] <= 8'b00000000;
font_rom[3060] <= 8'b00000000;
font_rom[3061] <= 8'b00000000;
font_rom[3062] <= 8'b00000000;
font_rom[3063] <= 8'b00000000;
font_rom[3064] <= 8'b00000000;
font_rom[3065] <= 8'b00000000;
font_rom[3066] <= 8'b00000000;
font_rom[3067] <= 8'b00000000;
font_rom[3068] <= 8'b00011111;
font_rom[3069] <= 8'b11100000;
font_rom[3070] <= 8'b00000000;
font_rom[3071] <= 8'b00000000;
//ASCII 0x60 '`'
font_rom[3072] <= 8'b00000000;
font_rom[3073] <= 8'b00000000;
font_rom[3074] <= 8'b00000000;
font_rom[3075] <= 8'b00000000;
font_rom[3076] <= 8'b00000000;
font_rom[3077] <= 8'b00000000;
font_rom[3078] <= 8'b00000000;
font_rom[3079] <= 8'b00000000;
font_rom[3080] <= 8'b00000110;
font_rom[3081] <= 8'b00000000;
font_rom[3082] <= 8'b00000011;
font_rom[3083] <= 8'b00000000;
font_rom[3084] <= 8'b00000000;
font_rom[3085] <= 8'b00000000;
font_rom[3086] <= 8'b00000000;
font_rom[3087] <= 8'b00000000;
font_rom[3088] <= 8'b00000000;
font_rom[3089] <= 8'b00000000;
font_rom[3090] <= 8'b00000000;
font_rom[3091] <= 8'b00000000;
font_rom[3092] <= 8'b00000000;
font_rom[3093] <= 8'b00000000;
font_rom[3094] <= 8'b00000000;
font_rom[3095] <= 8'b00000000;
font_rom[3096] <= 8'b00000000;
font_rom[3097] <= 8'b00000000;
font_rom[3098] <= 8'b00000000;
font_rom[3099] <= 8'b00000000;
font_rom[3100] <= 8'b00000000;
font_rom[3101] <= 8'b00000000;
font_rom[3102] <= 8'b00000000;
font_rom[3103] <= 8'b00000000;
//ASCII 0x61 'a'
font_rom[3104] <= 8'b00000000;
font_rom[3105] <= 8'b00000000;
font_rom[3106] <= 8'b00000000;
font_rom[3107] <= 8'b00000000;
font_rom[3108] <= 8'b00000000;
font_rom[3109] <= 8'b00000000;
font_rom[3110] <= 8'b00000000;
font_rom[3111] <= 8'b00000000;
font_rom[3112] <= 8'b00000000;
font_rom[3113] <= 8'b00000000;
font_rom[3114] <= 8'b00000000;
font_rom[3115] <= 8'b00000000;
font_rom[3116] <= 8'b00000000;
font_rom[3117] <= 8'b00000000;
font_rom[3118] <= 8'b00000011;
font_rom[3119] <= 8'b11000000;
font_rom[3120] <= 8'b00000110;
font_rom[3121] <= 8'b11000000;
font_rom[3122] <= 8'b00000110;
font_rom[3123] <= 8'b11000000;
font_rom[3124] <= 8'b00000100;
font_rom[3125] <= 8'b11000000;
font_rom[3126] <= 8'b00000110;
font_rom[3127] <= 8'b11000000;
font_rom[3128] <= 8'b00000111;
font_rom[3129] <= 8'b11100000;
font_rom[3130] <= 8'b00000000;
font_rom[3131] <= 8'b00000000;
font_rom[3132] <= 8'b00000000;
font_rom[3133] <= 8'b00000000;
font_rom[3134] <= 8'b00000000;
font_rom[3135] <= 8'b00000000;
//ASCII 0x62 'b'
font_rom[3136] <= 8'b00000000;
font_rom[3137] <= 8'b00000000;
font_rom[3138] <= 8'b00000000;
font_rom[3139] <= 8'b00000000;
font_rom[3140] <= 8'b00000000;
font_rom[3141] <= 8'b00000000;
font_rom[3142] <= 8'b00000000;
font_rom[3143] <= 8'b00000000;
font_rom[3144] <= 8'b00000110;
font_rom[3145] <= 8'b00000000;
font_rom[3146] <= 8'b00000110;
font_rom[3147] <= 8'b00000000;
font_rom[3148] <= 8'b00000110;
font_rom[3149] <= 8'b00000000;
font_rom[3150] <= 8'b00000111;
font_rom[3151] <= 8'b11000000;
font_rom[3152] <= 8'b00000110;
font_rom[3153] <= 8'b01000000;
font_rom[3154] <= 8'b00000110;
font_rom[3155] <= 8'b01100000;
font_rom[3156] <= 8'b00000110;
font_rom[3157] <= 8'b01100000;
font_rom[3158] <= 8'b00000110;
font_rom[3159] <= 8'b11000000;
font_rom[3160] <= 8'b00000111;
font_rom[3161] <= 8'b11000000;
font_rom[3162] <= 8'b00000000;
font_rom[3163] <= 8'b00000000;
font_rom[3164] <= 8'b00000000;
font_rom[3165] <= 8'b00000000;
font_rom[3166] <= 8'b00000000;
font_rom[3167] <= 8'b00000000;
//ASCII 0x63 'c'
font_rom[3168] <= 8'b00000000;
font_rom[3169] <= 8'b00000000;
font_rom[3170] <= 8'b00000000;
font_rom[3171] <= 8'b00000000;
font_rom[3172] <= 8'b00000000;
font_rom[3173] <= 8'b00000000;
font_rom[3174] <= 8'b00000000;
font_rom[3175] <= 8'b00000000;
font_rom[3176] <= 8'b00000000;
font_rom[3177] <= 8'b00000000;
font_rom[3178] <= 8'b00000000;
font_rom[3179] <= 8'b00000000;
font_rom[3180] <= 8'b00000000;
font_rom[3181] <= 8'b00000000;
font_rom[3182] <= 8'b00000001;
font_rom[3183] <= 8'b11000000;
font_rom[3184] <= 8'b00000011;
font_rom[3185] <= 8'b01100000;
font_rom[3186] <= 8'b00000110;
font_rom[3187] <= 8'b00000000;
font_rom[3188] <= 8'b00000110;
font_rom[3189] <= 8'b00000000;
font_rom[3190] <= 8'b00000110;
font_rom[3191] <= 8'b01100000;
font_rom[3192] <= 8'b00000011;
font_rom[3193] <= 8'b11000000;
font_rom[3194] <= 8'b00000000;
font_rom[3195] <= 8'b00000000;
font_rom[3196] <= 8'b00000000;
font_rom[3197] <= 8'b00000000;
font_rom[3198] <= 8'b00000000;
font_rom[3199] <= 8'b00000000;
//ASCII 0x64 'd'
font_rom[3200] <= 8'b00000000;
font_rom[3201] <= 8'b00000000;
font_rom[3202] <= 8'b00000000;
font_rom[3203] <= 8'b00000000;
font_rom[3204] <= 8'b00000000;
font_rom[3205] <= 8'b00000000;
font_rom[3206] <= 8'b00000000;
font_rom[3207] <= 8'b00000000;
font_rom[3208] <= 8'b00000000;
font_rom[3209] <= 8'b01100000;
font_rom[3210] <= 8'b00000000;
font_rom[3211] <= 8'b01100000;
font_rom[3212] <= 8'b00000000;
font_rom[3213] <= 8'b01000000;
font_rom[3214] <= 8'b00000011;
font_rom[3215] <= 8'b11000000;
font_rom[3216] <= 8'b00000110;
font_rom[3217] <= 8'b11000000;
font_rom[3218] <= 8'b00000110;
font_rom[3219] <= 8'b01000000;
font_rom[3220] <= 8'b00000110;
font_rom[3221] <= 8'b01000000;
font_rom[3222] <= 8'b00000110;
font_rom[3223] <= 8'b11000000;
font_rom[3224] <= 8'b00000011;
font_rom[3225] <= 8'b11100000;
font_rom[3226] <= 8'b00000000;
font_rom[3227] <= 8'b00000000;
font_rom[3228] <= 8'b00000000;
font_rom[3229] <= 8'b00000000;
font_rom[3230] <= 8'b00000000;
font_rom[3231] <= 8'b00000000;
//ASCII 0x65 'e'
font_rom[3232] <= 8'b00000000;
font_rom[3233] <= 8'b00000000;
font_rom[3234] <= 8'b00000000;
font_rom[3235] <= 8'b00000000;
font_rom[3236] <= 8'b00000000;
font_rom[3237] <= 8'b00000000;
font_rom[3238] <= 8'b00000000;
font_rom[3239] <= 8'b00000000;
font_rom[3240] <= 8'b00000000;
font_rom[3241] <= 8'b00000000;
font_rom[3242] <= 8'b00000000;
font_rom[3243] <= 8'b00000000;
font_rom[3244] <= 8'b00000000;
font_rom[3245] <= 8'b00000000;
font_rom[3246] <= 8'b00000011;
font_rom[3247] <= 8'b11000000;
font_rom[3248] <= 8'b00000110;
font_rom[3249] <= 8'b01000000;
font_rom[3250] <= 8'b00000111;
font_rom[3251] <= 8'b11000000;
font_rom[3252] <= 8'b00000111;
font_rom[3253] <= 8'b00000000;
font_rom[3254] <= 8'b00000110;
font_rom[3255] <= 8'b01100000;
font_rom[3256] <= 8'b00000011;
font_rom[3257] <= 8'b11000000;
font_rom[3258] <= 8'b00000000;
font_rom[3259] <= 8'b00000000;
font_rom[3260] <= 8'b00000000;
font_rom[3261] <= 8'b00000000;
font_rom[3262] <= 8'b00000000;
font_rom[3263] <= 8'b00000000;
//ASCII 0x66 'f'
font_rom[3264] <= 8'b00000000;
font_rom[3265] <= 8'b00000000;
font_rom[3266] <= 8'b00000000;
font_rom[3267] <= 8'b00000000;
font_rom[3268] <= 8'b00000000;
font_rom[3269] <= 8'b00000000;
font_rom[3270] <= 8'b00000000;
font_rom[3271] <= 8'b00000000;
font_rom[3272] <= 8'b00000001;
font_rom[3273] <= 8'b11000000;
font_rom[3274] <= 8'b00000001;
font_rom[3275] <= 8'b00000000;
font_rom[3276] <= 8'b00000011;
font_rom[3277] <= 8'b00000000;
font_rom[3278] <= 8'b00000111;
font_rom[3279] <= 8'b11000000;
font_rom[3280] <= 8'b00000011;
font_rom[3281] <= 8'b00000000;
font_rom[3282] <= 8'b00000011;
font_rom[3283] <= 8'b00000000;
font_rom[3284] <= 8'b00000011;
font_rom[3285] <= 8'b00000000;
font_rom[3286] <= 8'b00000011;
font_rom[3287] <= 8'b00000000;
font_rom[3288] <= 8'b00000011;
font_rom[3289] <= 8'b00000000;
font_rom[3290] <= 8'b00000000;
font_rom[3291] <= 8'b00000000;
font_rom[3292] <= 8'b00000000;
font_rom[3293] <= 8'b00000000;
font_rom[3294] <= 8'b00000000;
font_rom[3295] <= 8'b00000000;
//ASCII 0x67 'g'
font_rom[3296] <= 8'b00000000;
font_rom[3297] <= 8'b00000000;
font_rom[3298] <= 8'b00000000;
font_rom[3299] <= 8'b00000000;
font_rom[3300] <= 8'b00000000;
font_rom[3301] <= 8'b00000000;
font_rom[3302] <= 8'b00000000;
font_rom[3303] <= 8'b00000000;
font_rom[3304] <= 8'b00000000;
font_rom[3305] <= 8'b00000000;
font_rom[3306] <= 8'b00000000;
font_rom[3307] <= 8'b00000000;
font_rom[3308] <= 8'b00000000;
font_rom[3309] <= 8'b00000000;
font_rom[3310] <= 8'b00000011;
font_rom[3311] <= 8'b11000000;
font_rom[3312] <= 8'b00000110;
font_rom[3313] <= 8'b01100000;
font_rom[3314] <= 8'b00000110;
font_rom[3315] <= 8'b01100000;
font_rom[3316] <= 8'b00000100;
font_rom[3317] <= 8'b11000000;
font_rom[3318] <= 8'b00000110;
font_rom[3319] <= 8'b11000000;
font_rom[3320] <= 8'b00000111;
font_rom[3321] <= 8'b11000000;
font_rom[3322] <= 8'b00000000;
font_rom[3323] <= 8'b11000000;
font_rom[3324] <= 8'b00000000;
font_rom[3325] <= 8'b11000000;
font_rom[3326] <= 8'b00000111;
font_rom[3327] <= 8'b10000000;
//ASCII 0x68 'h'
font_rom[3328] <= 8'b00000000;
font_rom[3329] <= 8'b00000000;
font_rom[3330] <= 8'b00000000;
font_rom[3331] <= 8'b00000000;
font_rom[3332] <= 8'b00000000;
font_rom[3333] <= 8'b00000000;
font_rom[3334] <= 8'b00000000;
font_rom[3335] <= 8'b00000000;
font_rom[3336] <= 8'b00000110;
font_rom[3337] <= 8'b00000000;
font_rom[3338] <= 8'b00000110;
font_rom[3339] <= 8'b00000000;
font_rom[3340] <= 8'b00000110;
font_rom[3341] <= 8'b00000000;
font_rom[3342] <= 8'b00000111;
font_rom[3343] <= 8'b11000000;
font_rom[3344] <= 8'b00000111;
font_rom[3345] <= 8'b11000000;
font_rom[3346] <= 8'b00000110;
font_rom[3347] <= 8'b11000000;
font_rom[3348] <= 8'b00000110;
font_rom[3349] <= 8'b11000000;
font_rom[3350] <= 8'b00000110;
font_rom[3351] <= 8'b11000000;
font_rom[3352] <= 8'b00000110;
font_rom[3353] <= 8'b01100000;
font_rom[3354] <= 8'b00000000;
font_rom[3355] <= 8'b00000000;
font_rom[3356] <= 8'b00000000;
font_rom[3357] <= 8'b00000000;
font_rom[3358] <= 8'b00000000;
font_rom[3359] <= 8'b00000000;
//ASCII 0x69 'i'
font_rom[3360] <= 8'b00000000;
font_rom[3361] <= 8'b00000000;
font_rom[3362] <= 8'b00000000;
font_rom[3363] <= 8'b00000000;
font_rom[3364] <= 8'b00000000;
font_rom[3365] <= 8'b00000000;
font_rom[3366] <= 8'b00000000;
font_rom[3367] <= 8'b00000000;
font_rom[3368] <= 8'b00000000;
font_rom[3369] <= 8'b00000000;
font_rom[3370] <= 8'b00000001;
font_rom[3371] <= 8'b10000000;
font_rom[3372] <= 8'b00000000;
font_rom[3373] <= 8'b00000000;
font_rom[3374] <= 8'b00000001;
font_rom[3375] <= 8'b10000000;
font_rom[3376] <= 8'b00000001;
font_rom[3377] <= 8'b10000000;
font_rom[3378] <= 8'b00000001;
font_rom[3379] <= 8'b10000000;
font_rom[3380] <= 8'b00000001;
font_rom[3381] <= 8'b10000000;
font_rom[3382] <= 8'b00000001;
font_rom[3383] <= 8'b10000000;
font_rom[3384] <= 8'b00000001;
font_rom[3385] <= 8'b10000000;
font_rom[3386] <= 8'b00000000;
font_rom[3387] <= 8'b00000000;
font_rom[3388] <= 8'b00000000;
font_rom[3389] <= 8'b00000000;
font_rom[3390] <= 8'b00000000;
font_rom[3391] <= 8'b00000000;
//ASCII 0x6A 'j'
font_rom[3392] <= 8'b00000000;
font_rom[3393] <= 8'b00000000;
font_rom[3394] <= 8'b00000000;
font_rom[3395] <= 8'b00000000;
font_rom[3396] <= 8'b00000000;
font_rom[3397] <= 8'b00000000;
font_rom[3398] <= 8'b00000000;
font_rom[3399] <= 8'b00000000;
font_rom[3400] <= 8'b00000000;
font_rom[3401] <= 8'b00000000;
font_rom[3402] <= 8'b00000001;
font_rom[3403] <= 8'b10000000;
font_rom[3404] <= 8'b00000000;
font_rom[3405] <= 8'b00000000;
font_rom[3406] <= 8'b00000001;
font_rom[3407] <= 8'b10000000;
font_rom[3408] <= 8'b00000001;
font_rom[3409] <= 8'b10000000;
font_rom[3410] <= 8'b00000001;
font_rom[3411] <= 8'b10000000;
font_rom[3412] <= 8'b00000001;
font_rom[3413] <= 8'b10000000;
font_rom[3414] <= 8'b00000001;
font_rom[3415] <= 8'b10000000;
font_rom[3416] <= 8'b00000001;
font_rom[3417] <= 8'b10000000;
font_rom[3418] <= 8'b00000001;
font_rom[3419] <= 8'b10000000;
font_rom[3420] <= 8'b00000111;
font_rom[3421] <= 8'b10000000;
font_rom[3422] <= 8'b00000011;
font_rom[3423] <= 8'b10000000;
//ASCII 0x6B 'k'
font_rom[3424] <= 8'b00000000;
font_rom[3425] <= 8'b00000000;
font_rom[3426] <= 8'b00000000;
font_rom[3427] <= 8'b00000000;
font_rom[3428] <= 8'b00000000;
font_rom[3429] <= 8'b00000000;
font_rom[3430] <= 8'b00000000;
font_rom[3431] <= 8'b00000000;
font_rom[3432] <= 8'b00000110;
font_rom[3433] <= 8'b00000000;
font_rom[3434] <= 8'b00000110;
font_rom[3435] <= 8'b00000000;
font_rom[3436] <= 8'b00000110;
font_rom[3437] <= 8'b00000000;
font_rom[3438] <= 8'b00000110;
font_rom[3439] <= 8'b11100000;
font_rom[3440] <= 8'b00000110;
font_rom[3441] <= 8'b11000000;
font_rom[3442] <= 8'b00000111;
font_rom[3443] <= 8'b10000000;
font_rom[3444] <= 8'b00000111;
font_rom[3445] <= 8'b11000000;
font_rom[3446] <= 8'b00000110;
font_rom[3447] <= 8'b11000000;
font_rom[3448] <= 8'b00000110;
font_rom[3449] <= 8'b01100000;
font_rom[3450] <= 8'b00000000;
font_rom[3451] <= 8'b00000000;
font_rom[3452] <= 8'b00000000;
font_rom[3453] <= 8'b00000000;
font_rom[3454] <= 8'b00000000;
font_rom[3455] <= 8'b00000000;
//ASCII 0x6C 'l'
font_rom[3456] <= 8'b00000000;
font_rom[3457] <= 8'b00000000;
font_rom[3458] <= 8'b00000000;
font_rom[3459] <= 8'b00000000;
font_rom[3460] <= 8'b00000000;
font_rom[3461] <= 8'b00000000;
font_rom[3462] <= 8'b00000000;
font_rom[3463] <= 8'b00000000;
font_rom[3464] <= 8'b00000011;
font_rom[3465] <= 8'b00000000;
font_rom[3466] <= 8'b00000011;
font_rom[3467] <= 8'b00000000;
font_rom[3468] <= 8'b00000011;
font_rom[3469] <= 8'b00000000;
font_rom[3470] <= 8'b00000011;
font_rom[3471] <= 8'b00000000;
font_rom[3472] <= 8'b00000011;
font_rom[3473] <= 8'b00000000;
font_rom[3474] <= 8'b00000011;
font_rom[3475] <= 8'b00000000;
font_rom[3476] <= 8'b00000011;
font_rom[3477] <= 8'b00000000;
font_rom[3478] <= 8'b00000011;
font_rom[3479] <= 8'b00000000;
font_rom[3480] <= 8'b00000011;
font_rom[3481] <= 8'b00000000;
font_rom[3482] <= 8'b00000000;
font_rom[3483] <= 8'b00000000;
font_rom[3484] <= 8'b00000000;
font_rom[3485] <= 8'b00000000;
font_rom[3486] <= 8'b00000000;
font_rom[3487] <= 8'b00000000;
//ASCII 0x6D 'm'
font_rom[3488] <= 8'b00000000;
font_rom[3489] <= 8'b00000000;
font_rom[3490] <= 8'b00000000;
font_rom[3491] <= 8'b00000000;
font_rom[3492] <= 8'b00000000;
font_rom[3493] <= 8'b00000000;
font_rom[3494] <= 8'b00000000;
font_rom[3495] <= 8'b00000000;
font_rom[3496] <= 8'b00000000;
font_rom[3497] <= 8'b00000000;
font_rom[3498] <= 8'b00000000;
font_rom[3499] <= 8'b00000000;
font_rom[3500] <= 8'b00000000;
font_rom[3501] <= 8'b00000000;
font_rom[3502] <= 8'b00001111;
font_rom[3503] <= 8'b11100000;
font_rom[3504] <= 8'b00001111;
font_rom[3505] <= 8'b11100000;
font_rom[3506] <= 8'b00001101;
font_rom[3507] <= 8'b11100000;
font_rom[3508] <= 8'b00001101;
font_rom[3509] <= 8'b10100000;
font_rom[3510] <= 8'b00001101;
font_rom[3511] <= 8'b10110000;
font_rom[3512] <= 8'b00001101;
font_rom[3513] <= 8'b10110000;
font_rom[3514] <= 8'b00000000;
font_rom[3515] <= 8'b00000000;
font_rom[3516] <= 8'b00000000;
font_rom[3517] <= 8'b00000000;
font_rom[3518] <= 8'b00000000;
font_rom[3519] <= 8'b00000000;
//ASCII 0x6E 'n'
font_rom[3520] <= 8'b00000000;
font_rom[3521] <= 8'b00000000;
font_rom[3522] <= 8'b00000000;
font_rom[3523] <= 8'b00000000;
font_rom[3524] <= 8'b00000000;
font_rom[3525] <= 8'b00000000;
font_rom[3526] <= 8'b00000000;
font_rom[3527] <= 8'b00000000;
font_rom[3528] <= 8'b00000000;
font_rom[3529] <= 8'b00000000;
font_rom[3530] <= 8'b00000000;
font_rom[3531] <= 8'b00000000;
font_rom[3532] <= 8'b00000000;
font_rom[3533] <= 8'b00000000;
font_rom[3534] <= 8'b00000111;
font_rom[3535] <= 8'b11000000;
font_rom[3536] <= 8'b00000111;
font_rom[3537] <= 8'b11000000;
font_rom[3538] <= 8'b00000110;
font_rom[3539] <= 8'b01100000;
font_rom[3540] <= 8'b00000110;
font_rom[3541] <= 8'b01100000;
font_rom[3542] <= 8'b00000110;
font_rom[3543] <= 8'b01100000;
font_rom[3544] <= 8'b00000110;
font_rom[3545] <= 8'b01100000;
font_rom[3546] <= 8'b00000000;
font_rom[3547] <= 8'b00000000;
font_rom[3548] <= 8'b00000000;
font_rom[3549] <= 8'b00000000;
font_rom[3550] <= 8'b00000000;
font_rom[3551] <= 8'b00000000;
//ASCII 0x6F 'o'
font_rom[3552] <= 8'b00000000;
font_rom[3553] <= 8'b00000000;
font_rom[3554] <= 8'b00000000;
font_rom[3555] <= 8'b00000000;
font_rom[3556] <= 8'b00000000;
font_rom[3557] <= 8'b00000000;
font_rom[3558] <= 8'b00000000;
font_rom[3559] <= 8'b00000000;
font_rom[3560] <= 8'b00000000;
font_rom[3561] <= 8'b00000000;
font_rom[3562] <= 8'b00000000;
font_rom[3563] <= 8'b00000000;
font_rom[3564] <= 8'b00000000;
font_rom[3565] <= 8'b00000000;
font_rom[3566] <= 8'b00000011;
font_rom[3567] <= 8'b11000000;
font_rom[3568] <= 8'b00000110;
font_rom[3569] <= 8'b11000000;
font_rom[3570] <= 8'b00000110;
font_rom[3571] <= 8'b01000000;
font_rom[3572] <= 8'b00000110;
font_rom[3573] <= 8'b01000000;
font_rom[3574] <= 8'b00000110;
font_rom[3575] <= 8'b11000000;
font_rom[3576] <= 8'b00000011;
font_rom[3577] <= 8'b10000000;
font_rom[3578] <= 8'b00000000;
font_rom[3579] <= 8'b00000000;
font_rom[3580] <= 8'b00000000;
font_rom[3581] <= 8'b00000000;
font_rom[3582] <= 8'b00000000;
font_rom[3583] <= 8'b00000000;
//ASCII 0x70 'p'
font_rom[3584] <= 8'b00000000;
font_rom[3585] <= 8'b00000000;
font_rom[3586] <= 8'b00000000;
font_rom[3587] <= 8'b00000000;
font_rom[3588] <= 8'b00000000;
font_rom[3589] <= 8'b00000000;
font_rom[3590] <= 8'b00000000;
font_rom[3591] <= 8'b00000000;
font_rom[3592] <= 8'b00000000;
font_rom[3593] <= 8'b00000000;
font_rom[3594] <= 8'b00000000;
font_rom[3595] <= 8'b00000000;
font_rom[3596] <= 8'b00000000;
font_rom[3597] <= 8'b00000000;
font_rom[3598] <= 8'b00000111;
font_rom[3599] <= 8'b11000000;
font_rom[3600] <= 8'b00000110;
font_rom[3601] <= 8'b11000000;
font_rom[3602] <= 8'b00000110;
font_rom[3603] <= 8'b01100000;
font_rom[3604] <= 8'b00000110;
font_rom[3605] <= 8'b01100000;
font_rom[3606] <= 8'b00000110;
font_rom[3607] <= 8'b11000000;
font_rom[3608] <= 8'b00000111;
font_rom[3609] <= 8'b11000000;
font_rom[3610] <= 8'b00000110;
font_rom[3611] <= 8'b00000000;
font_rom[3612] <= 8'b00000110;
font_rom[3613] <= 8'b00000000;
font_rom[3614] <= 8'b00000110;
font_rom[3615] <= 8'b00000000;
//ASCII 0x71 'q'
font_rom[3616] <= 8'b00000000;
font_rom[3617] <= 8'b00000000;
font_rom[3618] <= 8'b00000000;
font_rom[3619] <= 8'b00000000;
font_rom[3620] <= 8'b00000000;
font_rom[3621] <= 8'b00000000;
font_rom[3622] <= 8'b00000000;
font_rom[3623] <= 8'b00000000;
font_rom[3624] <= 8'b00000000;
font_rom[3625] <= 8'b00000000;
font_rom[3626] <= 8'b00000000;
font_rom[3627] <= 8'b00000000;
font_rom[3628] <= 8'b00000000;
font_rom[3629] <= 8'b00000000;
font_rom[3630] <= 8'b00000011;
font_rom[3631] <= 8'b11000000;
font_rom[3632] <= 8'b00000110;
font_rom[3633] <= 8'b11000000;
font_rom[3634] <= 8'b00000110;
font_rom[3635] <= 8'b11000000;
font_rom[3636] <= 8'b00000110;
font_rom[3637] <= 8'b11000000;
font_rom[3638] <= 8'b00000110;
font_rom[3639] <= 8'b11000000;
font_rom[3640] <= 8'b00000011;
font_rom[3641] <= 8'b11000000;
font_rom[3642] <= 8'b00000000;
font_rom[3643] <= 8'b11000000;
font_rom[3644] <= 8'b00000000;
font_rom[3645] <= 8'b11000000;
font_rom[3646] <= 8'b00000000;
font_rom[3647] <= 8'b11000000;
//ASCII 0x72 'r'
font_rom[3648] <= 8'b00000000;
font_rom[3649] <= 8'b00000000;
font_rom[3650] <= 8'b00000000;
font_rom[3651] <= 8'b00000000;
font_rom[3652] <= 8'b00000000;
font_rom[3653] <= 8'b00000000;
font_rom[3654] <= 8'b00000000;
font_rom[3655] <= 8'b00000000;
font_rom[3656] <= 8'b00000000;
font_rom[3657] <= 8'b00000000;
font_rom[3658] <= 8'b00000000;
font_rom[3659] <= 8'b00000000;
font_rom[3660] <= 8'b00000000;
font_rom[3661] <= 8'b00000000;
font_rom[3662] <= 8'b00000011;
font_rom[3663] <= 8'b11100000;
font_rom[3664] <= 8'b00000011;
font_rom[3665] <= 8'b01100000;
font_rom[3666] <= 8'b00000011;
font_rom[3667] <= 8'b00000000;
font_rom[3668] <= 8'b00000011;
font_rom[3669] <= 8'b00000000;
font_rom[3670] <= 8'b00000011;
font_rom[3671] <= 8'b00000000;
font_rom[3672] <= 8'b00000011;
font_rom[3673] <= 8'b00000000;
font_rom[3674] <= 8'b00000000;
font_rom[3675] <= 8'b00000000;
font_rom[3676] <= 8'b00000000;
font_rom[3677] <= 8'b00000000;
font_rom[3678] <= 8'b00000000;
font_rom[3679] <= 8'b00000000;
//ASCII 0x73 's'
font_rom[3680] <= 8'b00000000;
font_rom[3681] <= 8'b00000000;
font_rom[3682] <= 8'b00000000;
font_rom[3683] <= 8'b00000000;
font_rom[3684] <= 8'b00000000;
font_rom[3685] <= 8'b00000000;
font_rom[3686] <= 8'b00000000;
font_rom[3687] <= 8'b00000000;
font_rom[3688] <= 8'b00000000;
font_rom[3689] <= 8'b00000000;
font_rom[3690] <= 8'b00000000;
font_rom[3691] <= 8'b00000000;
font_rom[3692] <= 8'b00000000;
font_rom[3693] <= 8'b00000000;
font_rom[3694] <= 8'b00000000;
font_rom[3695] <= 8'b11100000;
font_rom[3696] <= 8'b00000011;
font_rom[3697] <= 8'b00000000;
font_rom[3698] <= 8'b00000011;
font_rom[3699] <= 8'b10000000;
font_rom[3700] <= 8'b00000000;
font_rom[3701] <= 8'b11000000;
font_rom[3702] <= 8'b00000000;
font_rom[3703] <= 8'b01100000;
font_rom[3704] <= 8'b00000111;
font_rom[3705] <= 8'b11000000;
font_rom[3706] <= 8'b00000000;
font_rom[3707] <= 8'b00000000;
font_rom[3708] <= 8'b00000000;
font_rom[3709] <= 8'b00000000;
font_rom[3710] <= 8'b00000000;
font_rom[3711] <= 8'b00000000;
//ASCII 0x74 't'
font_rom[3712] <= 8'b00000000;
font_rom[3713] <= 8'b00000000;
font_rom[3714] <= 8'b00000000;
font_rom[3715] <= 8'b00000000;
font_rom[3716] <= 8'b00000000;
font_rom[3717] <= 8'b00000000;
font_rom[3718] <= 8'b00000000;
font_rom[3719] <= 8'b00000000;
font_rom[3720] <= 8'b00000000;
font_rom[3721] <= 8'b00000000;
font_rom[3722] <= 8'b00000001;
font_rom[3723] <= 8'b10000000;
font_rom[3724] <= 8'b00000001;
font_rom[3725] <= 8'b10000000;
font_rom[3726] <= 8'b00000111;
font_rom[3727] <= 8'b11000000;
font_rom[3728] <= 8'b00000001;
font_rom[3729] <= 8'b10000000;
font_rom[3730] <= 8'b00000001;
font_rom[3731] <= 8'b10000000;
font_rom[3732] <= 8'b00000001;
font_rom[3733] <= 8'b10000000;
font_rom[3734] <= 8'b00000001;
font_rom[3735] <= 8'b10000000;
font_rom[3736] <= 8'b00000001;
font_rom[3737] <= 8'b10000000;
font_rom[3738] <= 8'b00000000;
font_rom[3739] <= 8'b00000000;
font_rom[3740] <= 8'b00000000;
font_rom[3741] <= 8'b00000000;
font_rom[3742] <= 8'b00000000;
font_rom[3743] <= 8'b00000000;
//ASCII 0x75 'u'
font_rom[3744] <= 8'b00000000;
font_rom[3745] <= 8'b00000000;
font_rom[3746] <= 8'b00000000;
font_rom[3747] <= 8'b00000000;
font_rom[3748] <= 8'b00000000;
font_rom[3749] <= 8'b00000000;
font_rom[3750] <= 8'b00000000;
font_rom[3751] <= 8'b00000000;
font_rom[3752] <= 8'b00000000;
font_rom[3753] <= 8'b00000000;
font_rom[3754] <= 8'b00000000;
font_rom[3755] <= 8'b00000000;
font_rom[3756] <= 8'b00000000;
font_rom[3757] <= 8'b00000000;
font_rom[3758] <= 8'b00000110;
font_rom[3759] <= 8'b01000000;
font_rom[3760] <= 8'b00000110;
font_rom[3761] <= 8'b01000000;
font_rom[3762] <= 8'b00000110;
font_rom[3763] <= 8'b01000000;
font_rom[3764] <= 8'b00000110;
font_rom[3765] <= 8'b01000000;
font_rom[3766] <= 8'b00000110;
font_rom[3767] <= 8'b01000000;
font_rom[3768] <= 8'b00000111;
font_rom[3769] <= 8'b11000000;
font_rom[3770] <= 8'b00000000;
font_rom[3771] <= 8'b00000000;
font_rom[3772] <= 8'b00000000;
font_rom[3773] <= 8'b00000000;
font_rom[3774] <= 8'b00000000;
font_rom[3775] <= 8'b00000000;
//ASCII 0x76 'v'
font_rom[3776] <= 8'b00000000;
font_rom[3777] <= 8'b00000000;
font_rom[3778] <= 8'b00000000;
font_rom[3779] <= 8'b00000000;
font_rom[3780] <= 8'b00000000;
font_rom[3781] <= 8'b00000000;
font_rom[3782] <= 8'b00000000;
font_rom[3783] <= 8'b00000000;
font_rom[3784] <= 8'b00000000;
font_rom[3785] <= 8'b00000000;
font_rom[3786] <= 8'b00000000;
font_rom[3787] <= 8'b00000000;
font_rom[3788] <= 8'b00000000;
font_rom[3789] <= 8'b00000000;
font_rom[3790] <= 8'b00000100;
font_rom[3791] <= 8'b11000000;
font_rom[3792] <= 8'b00000110;
font_rom[3793] <= 8'b11000000;
font_rom[3794] <= 8'b00000110;
font_rom[3795] <= 8'b11000000;
font_rom[3796] <= 8'b00000011;
font_rom[3797] <= 8'b10000000;
font_rom[3798] <= 8'b00000011;
font_rom[3799] <= 8'b10000000;
font_rom[3800] <= 8'b00000011;
font_rom[3801] <= 8'b00000000;
font_rom[3802] <= 8'b00000000;
font_rom[3803] <= 8'b00000000;
font_rom[3804] <= 8'b00000000;
font_rom[3805] <= 8'b00000000;
font_rom[3806] <= 8'b00000000;
font_rom[3807] <= 8'b00000000;
//ASCII 0x77 'w'
font_rom[3808] <= 8'b00000000;
font_rom[3809] <= 8'b00000000;
font_rom[3810] <= 8'b00000000;
font_rom[3811] <= 8'b00000000;
font_rom[3812] <= 8'b00000000;
font_rom[3813] <= 8'b00000000;
font_rom[3814] <= 8'b00000000;
font_rom[3815] <= 8'b00000000;
font_rom[3816] <= 8'b00000000;
font_rom[3817] <= 8'b00000000;
font_rom[3818] <= 8'b00000000;
font_rom[3819] <= 8'b00000000;
font_rom[3820] <= 8'b00000000;
font_rom[3821] <= 8'b00000000;
font_rom[3822] <= 8'b00001101;
font_rom[3823] <= 8'b11100000;
font_rom[3824] <= 8'b00001111;
font_rom[3825] <= 8'b11100000;
font_rom[3826] <= 8'b00001111;
font_rom[3827] <= 8'b11100000;
font_rom[3828] <= 8'b00001111;
font_rom[3829] <= 8'b11100000;
font_rom[3830] <= 8'b00001111;
font_rom[3831] <= 8'b11000000;
font_rom[3832] <= 8'b00000110;
font_rom[3833] <= 8'b11000000;
font_rom[3834] <= 8'b00000000;
font_rom[3835] <= 8'b00000000;
font_rom[3836] <= 8'b00000000;
font_rom[3837] <= 8'b00000000;
font_rom[3838] <= 8'b00000000;
font_rom[3839] <= 8'b00000000;
//ASCII 0x78 'x'
font_rom[3840] <= 8'b00000000;
font_rom[3841] <= 8'b00000000;
font_rom[3842] <= 8'b00000000;
font_rom[3843] <= 8'b00000000;
font_rom[3844] <= 8'b00000000;
font_rom[3845] <= 8'b00000000;
font_rom[3846] <= 8'b00000000;
font_rom[3847] <= 8'b00000000;
font_rom[3848] <= 8'b00000000;
font_rom[3849] <= 8'b00000000;
font_rom[3850] <= 8'b00000000;
font_rom[3851] <= 8'b00000000;
font_rom[3852] <= 8'b00000000;
font_rom[3853] <= 8'b00000000;
font_rom[3854] <= 8'b00001100;
font_rom[3855] <= 8'b11000000;
font_rom[3856] <= 8'b00000111;
font_rom[3857] <= 8'b11000000;
font_rom[3858] <= 8'b00000011;
font_rom[3859] <= 8'b10000000;
font_rom[3860] <= 8'b00000111;
font_rom[3861] <= 8'b00000000;
font_rom[3862] <= 8'b00001111;
font_rom[3863] <= 8'b10000000;
font_rom[3864] <= 8'b00001100;
font_rom[3865] <= 8'b11000000;
font_rom[3866] <= 8'b00000000;
font_rom[3867] <= 8'b00000000;
font_rom[3868] <= 8'b00000000;
font_rom[3869] <= 8'b00000000;
font_rom[3870] <= 8'b00000000;
font_rom[3871] <= 8'b00000000;
//ASCII 0x79 'y'
font_rom[3872] <= 8'b00000000;
font_rom[3873] <= 8'b00000000;
font_rom[3874] <= 8'b00000000;
font_rom[3875] <= 8'b00000000;
font_rom[3876] <= 8'b00000000;
font_rom[3877] <= 8'b00000000;
font_rom[3878] <= 8'b00000000;
font_rom[3879] <= 8'b00000000;
font_rom[3880] <= 8'b00000000;
font_rom[3881] <= 8'b00000000;
font_rom[3882] <= 8'b00000000;
font_rom[3883] <= 8'b00000000;
font_rom[3884] <= 8'b00000000;
font_rom[3885] <= 8'b00000000;
font_rom[3886] <= 8'b00001100;
font_rom[3887] <= 8'b01100000;
font_rom[3888] <= 8'b00001100;
font_rom[3889] <= 8'b11000000;
font_rom[3890] <= 8'b00000110;
font_rom[3891] <= 8'b11000000;
font_rom[3892] <= 8'b00000011;
font_rom[3893] <= 8'b10000000;
font_rom[3894] <= 8'b00000011;
font_rom[3895] <= 8'b10000000;
font_rom[3896] <= 8'b00000001;
font_rom[3897] <= 8'b10000000;
font_rom[3898] <= 8'b00000011;
font_rom[3899] <= 8'b00000000;
font_rom[3900] <= 8'b00000011;
font_rom[3901] <= 8'b00000000;
font_rom[3902] <= 8'b00000110;
font_rom[3903] <= 8'b00000000;
//ASCII 0x7A 'z'
font_rom[3904] <= 8'b00000000;
font_rom[3905] <= 8'b00000000;
font_rom[3906] <= 8'b00000000;
font_rom[3907] <= 8'b00000000;
font_rom[3908] <= 8'b00000000;
font_rom[3909] <= 8'b00000000;
font_rom[3910] <= 8'b00000000;
font_rom[3911] <= 8'b00000000;
font_rom[3912] <= 8'b00000000;
font_rom[3913] <= 8'b00000000;
font_rom[3914] <= 8'b00000000;
font_rom[3915] <= 8'b00000000;
font_rom[3916] <= 8'b00000000;
font_rom[3917] <= 8'b00000000;
font_rom[3918] <= 8'b00000111;
font_rom[3919] <= 8'b11100000;
font_rom[3920] <= 8'b00000000;
font_rom[3921] <= 8'b11000000;
font_rom[3922] <= 8'b00000001;
font_rom[3923] <= 8'b10000000;
font_rom[3924] <= 8'b00000001;
font_rom[3925] <= 8'b10000000;
font_rom[3926] <= 8'b00000011;
font_rom[3927] <= 8'b00000000;
font_rom[3928] <= 8'b00000111;
font_rom[3929] <= 8'b11100000;
font_rom[3930] <= 8'b00000000;
font_rom[3931] <= 8'b00000000;
font_rom[3932] <= 8'b00000000;
font_rom[3933] <= 8'b00000000;
font_rom[3934] <= 8'b00000000;
font_rom[3935] <= 8'b00000000;
//ASCII 0x7B '{'
font_rom[3936] <= 8'b00000000;
font_rom[3937] <= 8'b00000000;
font_rom[3938] <= 8'b00000000;
font_rom[3939] <= 8'b00000000;
font_rom[3940] <= 8'b00000000;
font_rom[3941] <= 8'b00000000;
font_rom[3942] <= 8'b00000000;
font_rom[3943] <= 8'b00000000;
font_rom[3944] <= 8'b00000001;
font_rom[3945] <= 8'b11000000;
font_rom[3946] <= 8'b00000011;
font_rom[3947] <= 8'b00000000;
font_rom[3948] <= 8'b00000011;
font_rom[3949] <= 8'b00000000;
font_rom[3950] <= 8'b00000011;
font_rom[3951] <= 8'b00000000;
font_rom[3952] <= 8'b00000011;
font_rom[3953] <= 8'b00000000;
font_rom[3954] <= 8'b00000111;
font_rom[3955] <= 8'b00000000;
font_rom[3956] <= 8'b00000011;
font_rom[3957] <= 8'b00000000;
font_rom[3958] <= 8'b00000011;
font_rom[3959] <= 8'b00000000;
font_rom[3960] <= 8'b00000011;
font_rom[3961] <= 8'b00000000;
font_rom[3962] <= 8'b00000011;
font_rom[3963] <= 8'b00000000;
font_rom[3964] <= 8'b00000001;
font_rom[3965] <= 8'b11000000;
font_rom[3966] <= 8'b00000000;
font_rom[3967] <= 8'b00000000;
//ASCII 0x7C '|'
font_rom[3968] <= 8'b00000000;
font_rom[3969] <= 8'b00000000;
font_rom[3970] <= 8'b00000000;
font_rom[3971] <= 8'b00000000;
font_rom[3972] <= 8'b00000000;
font_rom[3973] <= 8'b00000000;
font_rom[3974] <= 8'b00000000;
font_rom[3975] <= 8'b00000000;
font_rom[3976] <= 8'b00000001;
font_rom[3977] <= 8'b10000000;
font_rom[3978] <= 8'b00000001;
font_rom[3979] <= 8'b10000000;
font_rom[3980] <= 8'b00000001;
font_rom[3981] <= 8'b10000000;
font_rom[3982] <= 8'b00000001;
font_rom[3983] <= 8'b10000000;
font_rom[3984] <= 8'b00000001;
font_rom[3985] <= 8'b10000000;
font_rom[3986] <= 8'b00000001;
font_rom[3987] <= 8'b10000000;
font_rom[3988] <= 8'b00000001;
font_rom[3989] <= 8'b10000000;
font_rom[3990] <= 8'b00000001;
font_rom[3991] <= 8'b10000000;
font_rom[3992] <= 8'b00000001;
font_rom[3993] <= 8'b10000000;
font_rom[3994] <= 8'b00000001;
font_rom[3995] <= 8'b10000000;
font_rom[3996] <= 8'b00000001;
font_rom[3997] <= 8'b10000000;
font_rom[3998] <= 8'b00000000;
font_rom[3999] <= 8'b00000000;
//ASCII 0x7D '}'
font_rom[4000] <= 8'b00000000;
font_rom[4001] <= 8'b00000000;
font_rom[4002] <= 8'b00000000;
font_rom[4003] <= 8'b00000000;
font_rom[4004] <= 8'b00000000;
font_rom[4005] <= 8'b00000000;
font_rom[4006] <= 8'b00000000;
font_rom[4007] <= 8'b00000000;
font_rom[4008] <= 8'b00000111;
font_rom[4009] <= 8'b00000000;
font_rom[4010] <= 8'b00000001;
font_rom[4011] <= 8'b10000000;
font_rom[4012] <= 8'b00000001;
font_rom[4013] <= 8'b10000000;
font_rom[4014] <= 8'b00000001;
font_rom[4015] <= 8'b10000000;
font_rom[4016] <= 8'b00000001;
font_rom[4017] <= 8'b10000000;
font_rom[4018] <= 8'b00000001;
font_rom[4019] <= 8'b11000000;
font_rom[4020] <= 8'b00000001;
font_rom[4021] <= 8'b10000000;
font_rom[4022] <= 8'b00000001;
font_rom[4023] <= 8'b10000000;
font_rom[4024] <= 8'b00000001;
font_rom[4025] <= 8'b10000000;
font_rom[4026] <= 8'b00000001;
font_rom[4027] <= 8'b10000000;
font_rom[4028] <= 8'b00000111;
font_rom[4029] <= 8'b00000000;
font_rom[4030] <= 8'b00000000;
font_rom[4031] <= 8'b00000000;
//ASCII 0x7E '~'
font_rom[4032] <= 8'b00000000;
font_rom[4033] <= 8'b00000000;
font_rom[4034] <= 8'b00000000;
font_rom[4035] <= 8'b00000000;
font_rom[4036] <= 8'b00000000;
font_rom[4037] <= 8'b00000000;
font_rom[4038] <= 8'b00000000;
font_rom[4039] <= 8'b00000000;
font_rom[4040] <= 8'b00000000;
font_rom[4041] <= 8'b00000000;
font_rom[4042] <= 8'b00000000;
font_rom[4043] <= 8'b00000000;
font_rom[4044] <= 8'b00000000;
font_rom[4045] <= 8'b00000000;
font_rom[4046] <= 8'b00000111;
font_rom[4047] <= 8'b01000000;
font_rom[4048] <= 8'b00001111;
font_rom[4049] <= 8'b11000000;
font_rom[4050] <= 8'b00001101;
font_rom[4051] <= 8'b11000000;
font_rom[4052] <= 8'b00000000;
font_rom[4053] <= 8'b00000000;
font_rom[4054] <= 8'b00000000;
font_rom[4055] <= 8'b00000000;
font_rom[4056] <= 8'b00000000;
font_rom[4057] <= 8'b00000000;
font_rom[4058] <= 8'b00000000;
font_rom[4059] <= 8'b00000000;
font_rom[4060] <= 8'b00000000;
font_rom[4061] <= 8'b00000000;
font_rom[4062] <= 8'b00000000;
font_rom[4063] <= 8'b00000000;
//ASCII 0x7F ''
font_rom[4064] <= 8'b00000000;
font_rom[4065] <= 8'b00000000;
font_rom[4066] <= 8'b00000000;
font_rom[4067] <= 8'b00000000;
font_rom[4068] <= 8'b00000000;
font_rom[4069] <= 8'b00000000;
font_rom[4070] <= 8'b00000000;
font_rom[4071] <= 8'b00000000;
font_rom[4072] <= 8'b00000011;
font_rom[4073] <= 8'b10000000;
font_rom[4074] <= 8'b00000010;
font_rom[4075] <= 8'b10000000;
font_rom[4076] <= 8'b00000010;
font_rom[4077] <= 8'b10000000;
font_rom[4078] <= 8'b00000010;
font_rom[4079] <= 8'b10000000;
font_rom[4080] <= 8'b00000010;
font_rom[4081] <= 8'b10000000;
font_rom[4082] <= 8'b00000010;
font_rom[4083] <= 8'b10000000;
font_rom[4084] <= 8'b00000010;
font_rom[4085] <= 8'b10000000;
font_rom[4086] <= 8'b00000011;
font_rom[4087] <= 8'b10000000;
font_rom[4088] <= 8'b00000000;
font_rom[4089] <= 8'b00000000;
font_rom[4090] <= 8'b00000000;
font_rom[4091] <= 8'b00000000;
font_rom[4092] <= 8'b00000000;
font_rom[4093] <= 8'b00000000;
font_rom[4094] <= 8'b00000000;
font_rom[4095] <= 8'b00000000;
end
always @(posedge clk) begin
out <= font_rom[address];
end
endmodule |
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module top
(
input wire clk,
output wire ser_tx,
input wire ser_rx,
input wire [15:0] sw,
output wire [15:0] led
);
// ============================================================================
reg rst = 1;
reg rst1 = 1;
reg rst2 = 1;
reg rst3 = 1;
assign led[0] = rst;
assign led[13:1] = sw[13:1];
assign led[14] = ^sw;
assign led[15] = ser_rx;
always @(posedge clk) begin
rst3 <= 0;
rst2 <= rst3;
rst1 <= rst2;
rst <= rst1;
end
// ============================================================================
//
scalable_proc #
(
.NUM_PROCESSING_UNITS (3),
.UART_PRESCALER ((100000000) / (500000))
)
scalable_proc
(
.CLK (clk),
.RST (rst),
.UART_TX (ser_tx),
.UART_RX (ser_rx)
);
endmodule
|
module main(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
input int_n,
input nmi_n,
input wait_n,
output res,
inout [7:0] d,
output [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
input [15:0] rd,
input [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output reg [1:0] vred,
output reg [1:0] vgrn,
output reg [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
input ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
input [2:0] ide_a,
input [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
input vg_clk,
output vg_cs_n,
output vg_res_n,
input vg_hrdy,
input vg_rclk,
input vg_rawr,
input [1:0] vg_a, // disk drive selection
input vg_wrd,
input vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
input spiint_n
);
//--Dummy----------------------------------------------------------------------
assign iorq1_n = 1'b1;
assign iorq2_n = 1'b1;
assign res= 1'b1;
assign rwe_n = 1'b1;
assign rucas_n = 1'b1;
assign rlcas_n = 1'b1;
assign rras0_n = 1'b1;
assign rras1_n = 1'b1;
assign ay_bdir = 1'b0;
assign ay_bc1 = 1'b0;
assign vg_cs_n = 1'b1;
assign vg_res_n = 1'b0;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs0_n = 1'b1;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign a[15:14] = 2'b00;
//-----------------------------------------------------------------------------
reg [2:0] main_osc;
always @(posedge fclk)
main_osc <= main_osc + 3'h1;
assign clkz_out = main_osc[2]; // 3.5 MHz
assign beep = spiint_n;
//--Video----------------------------------------------------------------------
localparam HBLNK_BEG = 9'd384;
localparam CSYNC_CUT = 9'd415;
//localparam CSYNC_CUT2 = 9'd382;
localparam HSYNC_BEG = 9'd0;
localparam HSYNC_END = 9'd33;
localparam HSYNC_END2 = 9'd53;
localparam HBLNK_END = 9'd128;
localparam HMAX = 9'd447;
localparam VBLNK_BEG = 10'd512; // 256
localparam VSYNC_BEG = 10'd0; // 0
localparam VSYNC_END = 10'd4; // 2
localparam VBLNK_END = 10'd128; // 64
localparam VMAX = 10'd623; // 311
reg [8:0] hcount;
reg [9:0] vcount;
reg [5:0] hcharcount;
reg [2:0] vcharline;
reg [6:0] voffset;
reg hsync, hblank, vsync, vblank, csync;
wire [9:0] video_addr;
wire [6:0] charcode;
wire [7:0] charpix;
wire pixel;
wire [5:0] fcolor;
wire [5:0] bcolor;
wire [5:0] color;
always @(posedge fclk)
begin
//
if ( {(main_osc[1]&scr_tv_mode),main_osc[0]}==2'h0 )
begin
if ( hcount[2:0]==3'h0 )
begin
if ( hblank )
hcharcount <= 6'h00;
else
hcharcount <= hcharcount + 6'h01;
end
if ( hcount==HMAX )
hcount <= 9'd0;
else
hcount <= hcount + 9'd1;
if ( hcount==HBLNK_BEG )
hblank <= 1'b1;
else if ( hcount==HBLNK_END )
hblank <= 1'b0;
if ( hcount==HSYNC_BEG )
begin
hsync <= 1'b1;
if ( vc0 )
csync <= 1'b1;
end
if ( (~scr_tv_mode) && (hcount==HSYNC_END2) )
begin
hsync <= 1'b0;
if ( !vsync )
csync <= 1'b0;
end
if ( scr_tv_mode && (hcount==HSYNC_END) )
begin
hsync <= 1'b0;
if ( !vsync )
csync <= 1'b0;
end
if ( (~vc0) && (hcount==HBLNK_BEG) ) // localparam CSYNC_CUT2 = 9'd382;
csync <= 1'b0;
if ( scr_tv_mode && (hcount==CSYNC_CUT) )
csync <= 1'b0;
vgrn[1] <= color[5];
vgrn[0] <= color[4];
vred[1] <= color[3];
vred[0] <= color[2];
vblu[1] <= color[1];
vblu[0] <= color[0];
end
//
if ( (main_osc[1:0]==2'h3) && (hcount==HSYNC_BEG) )
begin
if ( vblank )
begin
voffset <= 7'd0;
vcharline <= 3'h0;
end
else
begin
if ( (vcharline==3'h7) && vc0 )
voffset <= voffset + 7'd4; // 32 / 8 = 4
vcharline <= vcharline + {2'b00,vc0};
end
if ( {vcount[9:1],vc0}==VMAX )
vcount <= 10'd0;
else
vcount <= {vcount[9:1],vc0} + 10'd1;
if ( vcount==VBLNK_BEG )
vblank <= 1'b1;
else if ( vcount==VBLNK_END )
vblank <= 1'b0;
if ( vcount==VSYNC_BEG )
vsync <= 1'b1;
else if ( vcount==VSYNC_END )
vsync <= 1'b0;
end
//
end
assign vc0 = vcount[0] | scr_tv_mode;
assign video_addr = { voffset[6:0], 3'h0 } + { 4'h0, hcharcount[5:0] };
lpm_ram_dp0 scr_mem ( .data(scr_char), .rdaddress(video_addr), .wraddress(scr_addr), .wren(scr_wren_c), .q(charcode) );
lpm_rom0 chargen ( .address({ charcode, vcharline[2:0] }), .q(charpix) );
assign fcolor = 6'b111111;
assign bcolor = 6'b000001;
assign pixel = charpix[~(hcount[2:0]-3'h1)];
assign color = (hblank | vblank) ? 6'h00 : ( pixel ? fcolor : bcolor ) ;
assign vhsync = hsync;
assign vvsync = vsync;
assign vcsync = ~csync;
//--AVRSPI--FlashROM-----------------------------------------------------------
localparam SD_CS0 = 8'h57;
localparam SD_CS1 = 8'h5f;
localparam FLASH_LOADDR = 8'hf0;
localparam FLASH_MIDADDR = 8'hf1;
localparam FLASH_HIADDR = 8'hf2;
localparam FLASH_DATA = 8'hf3;
localparam FLASH_CTRL = 8'hf4;
localparam SCR_LOADDR = 8'h40;
localparam SCR_HIADDR = 8'h41;
localparam SCR_CHAR = 8'h44;
localparam SCR_MODE = 8'h4e;
reg [7:0] number;
reg [7:0] indata;
reg [7:0] outdata;
reg [2:0] bitptr;
reg [1:0] spick_resync;
reg [1:0] spicsn_resync;
reg [18:0] flash_addr;
reg flash_cs;
reg flash_oe;
reg flash_we;
reg [7:0] flash_data_out;
reg [9:0] scr_addr;
reg [6:0] scr_char;
reg scr_wren_c;
reg scr_tv_mode;
wire spicsn_rising;
wire spicsn_falling;
wire sd_selected;
always @(posedge spick)
begin
if ( spics_n )
number <= { number[6:0], spido };
else
indata <= { indata[6:0], spido };
end
always @(negedge spick or posedge spics_n)
begin
if ( spics_n )
bitptr <= 3'b111;
else
bitptr <= bitptr - 3'b001;
end
always @(posedge fclk)
begin
spicsn_resync <= { spicsn_resync[0], spics_n };
if ( spicsn_rising )
case ( number )
FLASH_LOADDR: flash_addr[7:0] <= indata;
FLASH_MIDADDR: flash_addr[15:8] <= indata;
FLASH_HIADDR: flash_addr[18:16] <= indata[2:0];
FLASH_DATA: flash_data_out <= indata;
FLASH_CTRL: begin
flash_cs <= indata[0];
flash_oe <= indata[1];
flash_we <= indata[2];
end
SCR_LOADDR: scr_addr[7:0] <= indata;
SCR_HIADDR: scr_addr[9:8] <= indata[1:0];
SCR_CHAR: begin
scr_char <= indata[6:0];
scr_wren_c <= 1'b1;
end
SCR_MODE: scr_tv_mode <= ~indata[0];
endcase
if ( spicsn_falling )
begin
scr_wren_c <= 1'b0;
if ( number==SCR_CHAR )
scr_addr <= scr_addr + 10'd1;
if ( number==FLASH_DATA )
outdata <= d;
else
outdata <= 8'hff;
end
end
assign spicsn_rising = (spicsn_resync==2'b01);
assign spicsn_falling = (spicsn_resync==2'b10);
assign sd_selected = ( ( (number==SD_CS0) || (number==SD_CS1) ) && (~spics_n) );
assign spidi = sd_selected ? sddi : outdata[bitptr];
assign sddo = sd_selected ? spido : 1'b1;
assign sdclk = sd_selected ? spick : 1'b0;
assign sdcs_n = !( (number==SD_CS0) && (~spics_n) );
assign a[13:0] = flash_addr[13:0];
assign rompg0_n = ~flash_addr[14];
assign { rompg4, rompg3, rompg2, dos_n } = flash_addr[18:15];
assign csrom = flash_cs;
assign romoe_n = ~flash_oe;
assign romwe_n = ~flash_we;
assign d = flash_oe ? 8'bZZZZZZZZ : flash_data_out;
//-----------------------------------------------------------------------------
endmodule
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Set Universe Polymorphism.
Definition crelation (A : Type) := A -> A -> Type.
Definition arrow (A B : Type) := A -> B.
Definition flip {A B C : Type} (f : A -> B -> C) := fun x y => f y x.
Definition iffT (A B : Type) := ((A -> B) * (B -> A))%type.
(** We allow to unfold the [crelation] definition while doing morphism search. *)
Section Defs.
Context {A : Type}.
(** We rebind crelational properties in separate classes to be able to overload each proof. *)
Class Reflexive (R : crelation A) :=
reflexivity : forall x : A, R x x.
Definition complement (R : crelation A) : crelation A :=
fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement iffT.
(** These are convertible. *)
Lemma complement_inverse R : complement (flip R) = flip (complement R).
Proof. reflexivity. Qed.
Class Irreflexive (R : crelation A) :=
irreflexivity : Reflexive (complement R).
Class Symmetric (R : crelation A) :=
symmetry : forall {x y}, R x y -> R y x.
Class Asymmetric (R : crelation A) :=
asymmetry : forall {x y}, R x y -> (complement R y x : Type).
Class Transitive (R : crelation A) :=
transitivity : forall {x y z}, R x y -> R y z -> R x z.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder (R : crelation A) := {
PreOrder_Reflexive :> Reflexive R | 2 ;
PreOrder_Transitive :> Transitive R | 2 }.
(** A [StrictOrder] is both Irreflexive and Transitive. *)
Class StrictOrder (R : crelation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R }.
(** By definition, a strict order is also asymmetric *)
Global Instance StrictOrder_Asymmetric `(StrictOrder R) : Asymmetric R.
Proof. firstorder. Qed.
(** A partial equivalence crelation is Symmetric and Transitive. *)
Class PER (R : crelation A) := {
PER_Symmetric :> Symmetric R | 3 ;
PER_Transitive :> Transitive R | 3 }.
(** Equivalence crelations. *)
Class Equivalence (R : crelation A) := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Global Instance Equivalence_PER {R} `(Equivalence R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence crelation on the carrier. *)
Class Antisymmetric eqA `{equ : Equivalence eqA} (R : crelation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Class subrelation (R R' : crelation A) :=
is_subrelation : forall {x y}, R x y -> R' x y.
(** Any symmetric crelation is equal to its inverse. *)
Lemma subrelation_symmetric R `(Symmetric R) : subrelation (flip R) R.
Proof. hnf. intros x y H'. red in H'. apply symmetry. assumption. Qed.
Section flip.
Lemma flip_Reflexive `{Reflexive R} : Reflexive (flip R).
Proof. tauto. Qed.
Program Definition flip_Irreflexive `(Irreflexive R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Program Definition flip_Antisymmetric `(Antisymmetric eqA R) :
Antisymmetric eqA (flip R).
Proof. firstorder. Qed.
(** Inversing the larger structures *)
Lemma flip_PreOrder `(PreOrder R) : PreOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_StrictOrder `(StrictOrder R) : StrictOrder (flip R).
Proof. firstorder. Qed.
Lemma flip_PER `(PER R) : PER (flip R).
Proof. firstorder. Qed.
Lemma flip_Equivalence `(Equivalence R) : Equivalence (flip R).
Proof. firstorder. Qed.
End flip.
Section complement.
Definition complement_Irreflexive `(Reflexive R)
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric R) : Symmetric (complement R).
Proof. firstorder. Qed.
End complement.
(** Rewrite crelation on a given support: declares a crelation as a rewrite
crelation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
crelations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation (RA : crelation A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite crelation. *)
Global Instance equivalence_rewrite_crelation `(Equivalence eqA) : RewriteRelation eqA.
(** Leibniz equality. *)
Section Leibniz.
Global Instance eq_Reflexive : Reflexive (@eq A) := @eq_refl A.
Global Instance eq_Symmetric : Symmetric (@eq A) := @eq_sym A.
Global Instance eq_Transitive : Transitive (@eq A) := @eq_trans A.
(** Leibinz equality [eq] is an equivalence crelation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Global Program Instance eq_equivalence : Equivalence (@eq A) | 10.
End Leibniz.
End Defs.
(** Default rewrite crelations handled by [setoid_rewrite]. *)
Instance: RewriteRelation impl.
Instance: RewriteRelation iff.
(** Hints to drive the typeclass resolution avoiding loops
due to the use of full unification. *)
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply complement_Irreflexive : typeclass_instances.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Antisymmetric (flip _)) => class_apply flip_Antisymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Hint Extern 3 (StrictOrder (flip _)) => class_apply flip_StrictOrder : typeclass_instances.
Hint Extern 3 (PreOrder (flip _)) => class_apply flip_PreOrder : typeclass_instances.
Hint Extern 4 (subrelation (flip _) _) =>
class_apply @subrelation_symmetric : typeclass_instances.
Hint Resolve irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for crelations. *)
Ltac solve_crelation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_crelation : crelations.
(** We can already dualize all these properties. *)
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_crelation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ dintuition ]).
Local Obligation Tactic := simpl_crelation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Instance iff_Reflexive : Reflexive iff := iff_refl.
Instance iff_Symmetric : Symmetric iff := iff_sym.
Instance iff_Transitive : Transitive iff := iff_trans.
(** Logical equivalence [iff] is an equivalence crelation. *)
Program Instance iff_equivalence : Equivalence iff.
Program Instance arrow_Reflexive : Reflexive arrow.
Program Instance arrow_Transitive : Transitive arrow.
Instance iffT_Reflexive : Reflexive iffT.
Proof. firstorder. Defined.
Instance iffT_Symmetric : Symmetric iffT.
Proof. firstorder. Defined.
Instance iffT_Transitive : Transitive iffT.
Proof. firstorder. Defined.
(** We now develop a generalization of results on crelations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary crelations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
(** We define the various operations which define the algebra on binary crelations *)
Section Binary.
Context {A : Type}.
Definition relation_equivalence : crelation (crelation A) :=
fun R R' => forall x y, iffT (R x y) (R' x y).
Global Instance: RewriteRelation relation_equivalence.
Definition relation_conjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => prod (R x y) (R' x y).
Definition relation_disjunction (R : crelation A) (R' : crelation A) : crelation A :=
fun x y => sum (R x y) (R' x y).
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Global Instance relation_equivalence_equivalence :
Equivalence relation_equivalence.
Proof. split; red; unfold relation_equivalence, iffT. firstorder.
firstorder.
intros. specialize (X x0 y0). specialize (X0 x0 y0). firstorder.
Qed.
Global Instance relation_implication_preorder : PreOrder (@subrelation A).
Proof. firstorder. Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence crelation
on the carrier. *)
Class PartialOrder eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (flip R)).
(** The equivalence proof is sufficient for proving that [R] must be a
morphism for equivalence (see Morphisms). It is also sufficient to
show that [R] is antisymmetric w.r.t. [eqA] *)
Global Instance partial_order_antisym `(PartialOrder eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
apply H. firstorder.
Qed.
Lemma PartialOrder_inverse `(PartialOrder eqA R) : PartialOrder eqA (flip R).
Proof. unfold flip; constructor; unfold flip. intros. apply H. apply symmetry. apply X.
unfold relation_conjunction. intros [H1 H2]. apply H. constructor; assumption. Qed.
End Binary.
Hint Extern 3 (PartialOrder (flip _)) => class_apply PartialOrder_inverse : typeclass_instances.
(** The partial order defined by subrelation and crelation equivalence. *)
(* Program Instance subrelation_partial_order : *)
(* ! PartialOrder (crelation A) relation_equivalence subrelation. *)
(* Obligation Tactic := idtac. *)
(* Next Obligation. *)
(* Proof. *)
(* intros x. refine (fun x => x). *)
(* Qed. *)
Typeclasses Opaque relation_equivalence.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41OI_TB_V
`define SKY130_FD_SC_LS__A41OI_TB_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a41oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg A4;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
A4 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 A4 = 1'b0;
#100 B1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 A3 = 1'b1;
#260 A4 = 1'b1;
#280 B1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 A3 = 1'b0;
#440 A4 = 1'b0;
#460 B1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 B1 = 1'b1;
#660 A4 = 1'b1;
#680 A3 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 B1 = 1'bx;
#840 A4 = 1'bx;
#860 A3 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ls__a41oi dut (.A1(A1), .A2(A2), .A3(A3), .A4(A4), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41OI_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSTP_SYMBOL_V
`define SKY130_FD_SC_MS__DFSTP_SYMBOL_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__dfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSTP_SYMBOL_V
|
// Queues up writes (color and Z) to the frame buffer.
`define PIPELINED
module Write_FIFO
#(parameter FIFO_DEPTH=32, FIFO_DEPTH_LOG2=5)
(
// Clock and reset.
input wire clock,
input wire reset_n,
// Memory interface for writing color pixels.
output reg [28:0] write_color_address,
output wire [7:0] write_color_burstcount,
input wire write_color_waitrequest,
output reg [63:0] write_color_writedata,
output reg [7:0] write_color_byteenable,
output reg write_color_write,
// Memory interface for writing Z pixels.
output reg [28:0] write_z_address,
output wire [7:0] write_z_burstcount,
input wire write_z_waitrequest,
output reg [63:0] write_z_writedata,
output reg [7:0] write_z_byteenable,
output reg write_z_write,
// FIFO controls.
input wire enqueue,
input wire [28:0] color_address,
input wire [63:0] color,
input wire [28:0] z_address,
input wire [63:0] z,
input wire [1:0] pixel_active, // Bit 0 is the left-most pixel.
output wire [FIFO_DEPTH_LOG2-1:0] size,
// Indicates an internal error that should be displayed to the user during
// debugging.
output reg [7:0] error
);
/* verilator lint_off WIDTH */
// Constants.
assign write_color_burstcount = 8'h01;
assign write_z_burstcount = 8'h01;
`ifdef PIPELINED
// State.
reg [187:0] slot1;
wire [28:0] slot1_color_address = slot1[28:0];
wire [63:0] slot1_color = slot1[92:29];
wire [28:0] slot1_z_address = slot1[121:93];
wire [63:0] slot1_z = slot1[185:122];
wire [1:0] slot1_pixel_active = slot1[187:186];
wire [7:0] slot1_byte_enable = {{4{slot1_pixel_active[1]}}, {4{slot1_pixel_active[0]}}};
reg slot1_full;
reg [187:0] slot2;
reg slot2_full;
// According to the Avalon-MM spec, the waitrequest lines should only be
// inspected when we're trying to read or write. They can be any value at
// other times. So we make these signals to take that into account.
wire color_wait = write_color_write && write_color_waitrequest;
wire z_wait = write_z_write && write_z_waitrequest;
// Keep track of whether there was data in the queue when we read it.
reg got_queue_data;
`else
// State machine.
localparam STATE_INIT = 2'h0;
localparam STATE_READ = 2'h1;
localparam STATE_WRITE = 2'h2;
localparam STATE_WAIT = 2'h3;
reg [1:0] state;
`endif
// Pack the FIFO data.
wire [187:0] fifo_write_data = {
pixel_active,
z,
z_address,
color,
color_address
};
// Unpack the FIFO data.
wire [187:0] fifo_read_data;
wire [28:0] fifo_color_address = fifo_read_data[28:0];
wire [63:0] fifo_color = fifo_read_data[92:29];
wire [28:0] fifo_z_address = fifo_read_data[121:93];
wire [63:0] fifo_z = fifo_read_data[185:122];
wire [1:0] fifo_pixel_active = fifo_read_data[187:186];
wire [7:0] fifo_byte_enable = {{4{fifo_pixel_active[1]}}, {4{fifo_pixel_active[0]}}};
// FIFO implementation.
wire fifo_empty;
/* verilator lint_off UNUSED */
wire fifo_full;
/* verilator lint_on UNUSED */
reg fifo_read;
/* verilator lint_off PINMISSING */
scfifo #(.add_ram_output_register("OFF"),
.intended_device_family("CYCLONEV"),
.lpm_numwords(FIFO_DEPTH),
.lpm_showahead("OFF"),
.lpm_type("scfifo"),
.lpm_width(188),
.lpm_widthu(FIFO_DEPTH_LOG2),
.overflow_checking("ON"),
.underflow_checking("ON"),
.use_eab("ON")) fifo(
.aclr(!reset_n),
.clock(clock),
.data(fifo_write_data),
.empty(fifo_empty),
.full(fifo_full),
.usedw(size),
.q(fifo_read_data),
.rdreq(fifo_read),
.wrreq(enqueue));
/* verilator lint_on PINMISSING */
// Dequeuing.
always @(posedge clock or negedge reset_n) begin
if (!reset_n) begin
// Memory.
write_color_address <= 1'b0;
write_color_writedata <= 1'b0;
write_color_byteenable <= 1'b0;
write_color_write <= 1'b0;
write_z_address <= 1'b0;
write_z_writedata <= 1'b0;
write_z_byteenable <= 1'b0;
write_z_write <= 1'b0;
// FIFO.
fifo_read <= 1'b0;
`ifdef PIPELINED
// State.
slot1 <= 1'b0;
slot1_full <= 1'b0;
slot2 <= 1'b0;
slot2_full <= 1'b0;
error <= 1'b0;
got_queue_data <= 1'b0;
`else
// State machine.
state <= STATE_INIT;
`endif
end else begin
`ifdef PIPELINED
// Only read from the queue if we're not asked to wait for memory,
// and we have no slots with data. Since it takes a few clock
// cycles for us to realize that we should wait, we need some
// slots to dump the data into in the meantime.
fifo_read <= !color_wait && !z_wait && !slot1_full;
// One clock after fifo_read, the empty signal indicates whether the queue
// was empty when we tried to read it.
got_queue_data <= fifo_read && !fifo_empty;
// Default to no error unless something happens below.
error <= 1'b0;
// Two clocks after fifo_read, the data is ready. Pack everything
// we know into a single value we can switch on.
casez ({got_queue_data, color_wait, z_wait, slot1_full, slot2_full})
5'b0_00_00: begin
// No new data, not waiting, no old data. Nothing to do.
write_color_write <= 1'b0;
write_z_write <= 1'b0;
end
5'b?_??_01: begin
// Can't have slot2 filled without slot1 filled; raise an error.
error <= 8'h80;
end
5'b0_00_10: begin
// No new data, but we have old data that can be written.
write_color_address <= slot1_color_address;
write_color_writedata <= slot1_color;
write_color_byteenable <= slot1_byte_enable;
write_color_write <= slot1_color_address != 1'b0;
write_z_address <= slot1_z_address;
write_z_writedata <= slot1_z;
write_z_byteenable <= slot1_byte_enable;
write_z_write <= slot1_z_address != 1'b0;
slot1_full <= 1'b0;
end
5'b0_00_11: begin
// No new data, but we have old data that can be written.
write_color_address <= slot1_color_address;
write_color_writedata <= slot1_color;
write_color_byteenable <= slot1_byte_enable;
write_color_write <= slot1_color_address != 1'b0;
write_z_address <= slot1_z_address;
write_z_writedata <= slot1_z;
write_z_byteenable <= slot1_byte_enable;
write_z_write <= slot1_z_address != 1'b0;
slot1 <= slot2;
slot2_full <= 1'b0;
end
5'b0_11_00, 5'b0_01_00, 5'b0_10_00,
5'b0_11_10, 5'b0_01_10, 5'b0_10_10,
5'b0_11_11, 5'b0_01_11, 5'b0_10_11: begin
// Waiting for memory but no new data. Doesn't matter
// what's in the slots, they'll wait.
write_color_write <= color_wait;
write_z_write <= z_wait;
end
5'b1_00_00: begin
// Got new data, can use it right away.
write_color_address <= fifo_color_address;
write_color_writedata <= fifo_color;
write_color_byteenable <= fifo_byte_enable;
write_color_write <= fifo_color_address != 1'b0;
write_z_address <= fifo_z_address;
write_z_writedata <= fifo_z;
write_z_byteenable <= fifo_byte_enable;
write_z_write <= fifo_z_address != 1'b0;
end
5'b1_00_10: begin
// Got new data, replace slot1 and send slot1 to memory.
write_color_address <= slot1_color_address;
write_color_writedata <= slot1_color;
write_color_byteenable <= slot1_byte_enable;
write_color_write <= slot1_color_address != 1'b0;
write_z_address <= slot1_z_address;
write_z_writedata <= slot1_z;
write_z_byteenable <= slot1_byte_enable;
write_z_write <= slot1_z_address != 1'b0;
slot1 <= fifo_read_data;
end
5'b1_00_11: begin
// Got new data, replace slot2, slot2 to slot1, and send
// slot1 to memory.
write_color_address <= slot1_color_address;
write_color_writedata <= slot1_color;
write_color_byteenable <= slot1_byte_enable;
write_color_write <= slot1_color_address != 1'b0;
write_z_address <= slot1_z_address;
write_z_writedata <= slot1_z;
write_z_byteenable <= slot1_byte_enable;
write_z_write <= slot1_z_address != 1'b0;
slot1 <= slot2;
slot2 <= fifo_read_data;
end
5'b1_11_00, 5'b1_01_00, 5'b1_10_00: begin
// Have new data but can't write to memory. Put it in slot1.
slot1 <= fifo_read_data;
slot1_full <= 1'b1;
write_color_write <= color_wait;
write_z_write <= z_wait;
end
5'b1_11_10, 5'b1_01_10, 5'b1_10_10: begin
// Have new data but can't write to memory and slot1 is
// full. Put it in slot2.
slot2 <= fifo_read_data;
slot2_full <= 1'b1;
write_color_write <= color_wait;
write_z_write <= z_wait;
end
5'b1_11_11, 5'b1_01_11, 5'b1_10_11: begin
// In principle this can't happen because we wouldn't have asked to
// read from the queue. Raise an error.
error <= 8'h40 | {got_queue_data, color_wait, z_wait, slot1_full, slot2_full};
end
default: begin
// I think I covered all the cases, but put this here just
// in case.
error <= {got_queue_data, color_wait, z_wait, slot1_full, slot2_full};
end
endcase
`else
case (state)
STATE_INIT: begin
if (!fifo_empty) begin
fifo_read <= 1'b1;
state <= STATE_READ;
end
end
STATE_READ: begin
fifo_read <= 1'b0;
state <= STATE_WRITE;
end
STATE_WRITE: begin
// Grab the data.
/// fifo_read_data_reg <= fifo_read_data;
// Also set the various memory write parameters.
write_color_address <= fifo_color_address;
write_color_writedata <= fifo_color;
write_color_byteenable <= fifo_byte_enable;
write_color_write <= fifo_color_address != 1'b0;
write_z_address <= fifo_z_address;
write_z_writedata <= fifo_z;
write_z_byteenable <= fifo_byte_enable;
write_z_write <= fifo_z_address != 1'b0;
state <= STATE_WAIT;
end
STATE_WAIT: begin
if (write_color_write && !write_color_waitrequest) begin
write_color_write <= 1'b0;
end
if (write_z_write && !write_z_waitrequest) begin
write_z_write <= 1'b0;
end
if ((!write_color_write || !write_color_waitrequest) &&
(!write_z_write || !write_z_waitrequest)) begin
// All done.
state <= STATE_INIT;
end
end
default: begin
state <= STATE_INIT;
end
endcase
`endif
end
end
/* verilator lint_on WIDTH */
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module master_0_b2p_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input [ 7: 0] in_channel,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket
);
reg out_channel;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = in_channel ;
// Suppress channels that are higher than the destination's max_channel.
if (in_channel > 0) begin
out_valid = 0;
// Simulation Message goes here.
end
end
endmodule
|
/*******************************************************************************
* File Name: CRC_UART_v0_1.v
* Version `$CY_MAJOR_VERSION`.`$CY_MINOR_VERSION`
*
* Description:
* This file provides a top level model of the CRC componnent
* defining and all of the necessary interconnect.
*
* Note:
* None
********************************************************************************
* Control and Status Register definitions
********************************************************************************
*
* Control Register Definition
*
* ctrl_enable => 0 = disable CRC
* 1 = enable CRC
*
* ctrl_reset => Software reset for dtrig. Firstly must be set "1",
* after that - "0". This is emulate rising edge for reset
* triggers.
*
********************************************************************************
* Data Path register definitions
********************************************************************************
* INSTANCE NAME: DatapathName
* DESCRIPTION:
* REGISTER USAGE:
* F0 => Copy of lower half of seed valu
* F1 => Copy of upper half of seed value
* D0 => Lower half of polynomial value
* D1 => Upper half of polynomial value
* A0 => Lower half of seed value
* A1 => Upper half of seed value
*
********************************************************************************
* I*O Signals:
********************************************************************************
* IO SIGNALS:
* di input Input Data
* reset input Reset
* clock input Data clock
* enable input Enable
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
`include "cypress.v"
`ifdef CRC_UART_v0_1_V_ALREADY_INCLUDED
`else
`define CRC_UART_v0_1_V_ALREADY_INCLUDED
module CRC_UART_v0_1
(
input wire clock,
input wire reset,
input wire enable,
input wire di
);
/**************************************************************************/
/* Parameters */
/**************************************************************************/
localparam CRC_8_BIT = 7'd8;
localparam CRC_16_BIT = 7'd16;
localparam CRC_24_BIT = 7'd24;
localparam CRC_32_BIT = 7'd32;
localparam CRC_40_BIT = 7'd40;
localparam CRC_48_BIT = 7'd48;
localparam CRC_56_BIT = 7'd56;
localparam CRC_64_BIT = 7'd64;
parameter [6:0] Resolution = CRC_8_BIT;
localparam CRC_CFG_TDM_DISABLE = 1'd0;
localparam CRC_CFG_TDM_ENABLE = 1'd1;
parameter TimeMultiplexing = CRC_CFG_TDM_DISABLE;
/* UDB Revision definitions */
localparam CY_UDB_V0 = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_5A);
localparam CY_UDB_V1 = (!CY_UDB_V0);
/* Silicon definition */
localparam PSOC4A = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_4A);
/* Control Register Bits (Bits 7-1 are unused )*/
localparam CRC_CTRL_ENABLE = 3'h0; /* Enable CRC */
localparam CRC_CTRL_RESET = 3'h1; /* Reset CRC */
/* State Machine States */
localparam CRC_STATE_CALC_LOWER = 2'd0; /* Calculate Lower Half */
localparam CRC_STATE_CALC_UPPER = 2'd1; /* Calculate Upper Half */
localparam CRC_STATE_SAVE_LOWER = 2'd2; /* Save Lower Half */
localparam CRC_STATE_SAVE_UPPER = 2'd3; /* Save Upper Half */
localparam [2:0] dpPOVal = (Resolution <= CRC_8_BIT) ? (Resolution - 1):
(Resolution <= CRC_16_BIT) ? (Resolution - 9):
(Resolution <= CRC_24_BIT) ? (Resolution - 17):
(Resolution <= CRC_32_BIT) ? (Resolution - 25):
(Resolution <= CRC_40_BIT) ? (Resolution - 33):
(Resolution <= CRC_48_BIT) ? (Resolution - 41):
(Resolution <= CRC_56_BIT) ? (Resolution - 49):
(Resolution <= CRC_64_BIT) ? (Resolution - 57): 0;
localparam [2:0] dpMsbVal = (Resolution < CRC_8_BIT) ? (Resolution - 1) : 7;
localparam dpconfig0 =
{
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment:Calculate Lower Half */
`CS_ALU_OP__XOR, `CS_SRCA_A1, `CS_SRCB_D1,
`CS_SHFT_OP___SL, `CS_A0_SRC_NONE, `CS_A1_SRC__ALU,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment:Calculate Upper Half*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment:Save Lower Half*/
`CS_ALU_OP_PASS, `CS_SRCA_A1, `CS_SRCB_D1,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment:Save Upper Half*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment:*/
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment:*/
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_ROUTE, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_ENBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
};
/* Internal signals */
wire clk;
wire so;
wire ci;
wire si;
wire cmsb;
wire si_final;
wire so_chain;
wire si_d;
wire si_c;
wire si_b;
wire si_a;
wire so_d;
wire so_c;
wire so_b;
wire so_a;
wire [7:0] sc_out_a;
wire [7:0] sc_out_b;
wire [7:0] sc_out_c;
wire [7:0] sc_out_d;
wire [7:0] sc_out;
wire [2:0] cs_addr;
wire enable_final;
wire reset_final;
wire ctrl_enable;
wire ctrl_reset;
wire save_so;
wire save;
wire dcfg;
wire clk_ctrl;
wire so_reg1;
wire [7:0] control; /* Control Register Output */
reg so_reg;
reg ci_temp;
reg sc_temp;
reg [1:0] state;
wire ci_mult;
/**************************************************************************/
/* Hierarchy - instantiating another module */
/**************************************************************************/
generate
if ((TimeMultiplexing == CRC_CFG_TDM_DISABLE) || PSOC4A)
begin
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
Sync1(
/* input */.clock_in(clock),
/* input */.enable(enable),
/* output */.clock_out(clk)
);
end
else
begin
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE))
Sync1(
/* input */.clock_in(clock),
/* input */.enable(enable_final),
/* output */.clock_out(clk)
);
end
endgenerate
generate
if (CY_UDB_V0)
begin: AsyncCtrl
cy_psoc3_control #(.cy_force_order(`TRUE))
CtrlReg (
/* output 07:00] */.control(control)
);
end
else
begin: SyncCtrl
cy_psoc3_control #(.cy_force_order(`TRUE), .cy_ctrl_mode_1(8'h0), .cy_ctrl_mode_0(8'h0))
CtrlReg (
/* output [07:00] */ .control(control)
);
end
endgenerate
generate
if ((Resolution > CRC_48_BIT) && (TimeMultiplexing == CRC_CFG_TDM_ENABLE))
begin : b3
cy_psoc3_dp #(.cy_dpconfig(dpconfig0))
CRCdp_d(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si_d),
/* input */ .route_ci(ci_mult),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(so_d),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0),
/* output */ .co(),
/* input */ .sir(1'b0),
/* output */ .sor(),
/* input */ .sil(1'b0),
/* output */ .sol(),
/* input */ .msbi(1'b0),
/* output */ .msbo(),
/* input [01:00] */ .cei(2'b0),
/* output [01:00] */ .ceo(),
/* input [01:00] */ .cli(2'b0),
/* output [01:00] */ .clo(),
/* input [01:00] */ .zi(2'b0),
/* output [01:00] */ .zo(),
/* input [01:00] */ .fi(2'b0),
/* output [01:00] */ .fo(),
/* input [01:00] */ .capi(2'b0),
/* output [01:00] */ .capo(),
/* input */ .cfbi(1'b0),
/* output */ .cfbo(),
/* input [07:00] */ .pi(8'b0),
/* output [07:00] */ .po(sc_out_d[7:0])
);
end
if ((Resolution > CRC_32_BIT) && (TimeMultiplexing == CRC_CFG_TDM_ENABLE))
begin : b2
cy_psoc3_dp #(.cy_dpconfig(dpconfig0))
CRCdp_c(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si_c),
/* input */ .route_ci(ci_mult),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(so_c),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0),
/* output */ .co(),
/* input */ .sir(1'b0),
/* output */ .sor(),
/* input */ .sil(1'b0),
/* output */ .sol(),
/* input */ .msbi(1'b0),
/* output */ .msbo(),
/* input [01:00] */ .cei(2'b0),
/* output [01:00] */ .ceo(),
/* input [01:00] */ .cli(2'b0),
/* output [01:00] */ .clo(),
/* input [01:00] */ .zi(2'b0),
/* output [01:00] */ .zo(),
/* input [01:00] */ .fi(2'b0),
/* output [01:00] */ .fo(),
/* input [01:00] */ .capi(2'b0),
/* output [01:00] */ .capo(),
/* input */ .cfbi(1'b0),
/* output */ .cfbo(),
/* input [07:00] */ .pi(8'b0),
/* output [07:00] */ .po(sc_out_c[7:0])
);
end
if ((Resolution > CRC_16_BIT) && (TimeMultiplexing == CRC_CFG_TDM_ENABLE))
begin : b1
cy_psoc3_dp #(.cy_dpconfig(dpconfig0))
CRCdp_b(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si_b),
/* input */ .route_ci(ci_mult),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(),
/* output */ .so(so_b),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0),
/* output */ .co(),
/* input */ .sir(1'b0),
/* output */ .sor(),
/* input */ .sil(1'b0),
/* output */ .sol(),
/* input */ .msbi(1'b0),
/* output */ .msbo(),
/* input [01:00] */ .cei(2'b0),
/* output [01:00] */ .ceo(),
/* input [01:00] */ .cli(2'b0),
/* output [01:00] */ .clo(),
/* input [01:00] */ .zi(2'b0),
/* output [01:00] */ .zo(),
/* input [01:00] */ .fi(2'b0),
/* output [01:00] */ .fo(),
/* input [01:00] */ .capi(2'b0),
/* output [01:00] */ .capo(),
/* input */ .cfbi(1'b0),
/* output */ .cfbo(),
/* input [07:00] */ .pi(8'b0),
/* output [07:00] */ .po(sc_out_b[7:0])
);
end
if ((Resolution > CRC_8_BIT) && (TimeMultiplexing == CRC_CFG_TDM_ENABLE))
begin : b0
cy_psoc3_dp #(.cy_dpconfig(dpconfig0))
CRCdp_a(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si),
/* input */ .route_ci(ci_mult),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(cmsb),
/* output */ .so(so_a),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat(),
/* input */ .ci(1'b0),
/* output */ .co(),
/* input */ .sir(1'b0),
/* output */ .sor(),
/* input */ .sil(1'b0),
/* output */ .sol(),
/* input */ .msbi(1'b0),
/* output */ .msbo(),
/* input [01:00] */ .cei(2'b0),
/* output [01:00] */ .ceo(),
/* input [01:00] */ .cli(2'b0),
/* output [01:00] */ .clo(),
/* input [01:00] */ .zi(2'b0),
/* output [01:00] */ .zo(),
/* input [01:00] */ .fi(2'b0),
/* output [01:00] */ .fo(),
/* input [01:00] */ .capi(2'b0),
/* output [01:00] */ .capo(),
/* input */ .cfbi(1'b0),
/* output */ .cfbo(),
/* input [07:00] */ .pi(8'b0),
/* output [07:00] */ .po(sc_out_a[7:0])
);
end
endgenerate
generate
if ((Resolution <= CRC_8_BIT) && (TimeMultiplexing == CRC_CFG_TDM_DISABLE))
begin : sC8
cy_psoc3_dp8 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpMsbVal, `SC_MSB_NOCHN,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_ENBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) CRCdp(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si),
/* input */ .route_ci(ci),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output */ .ce0(),
/* output */ .cl0(),
/* output */ .z0(),
/* output */ .ff0(),
/* output */ .ce1(),
/* output */ .cl1(),
/* output */ .z1(),
/* output */ .ff1(),
/* output */ .ov_msb(),
/* output */ .co_msb(),
/* output */ .cmsb(cmsb),
/* output */ .so(),
/* output */ .f0_bus_stat(),
/* output */ .f0_blk_stat(),
/* output */ .f1_bus_stat(),
/* output */ .f1_blk_stat()
);
end
else if ((Resolution <= CRC_16_BIT) && (TimeMultiplexing == CRC_CFG_TDM_DISABLE))
begin : sC16
cy_psoc3_dp16 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_CHNED,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment:MSB Chain */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_ENBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_b(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_CHAIN,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpPOVal, `SC_MSB_NOCHN,
`SC_FB_CHNED, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment:FB Chain and MSB enable */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) CRCdp(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si),
/* input */ .route_ci(ci),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output [01:00] */ .ce0(),
/* output [01:00] */ .cl0(),
/* output [01:00] */ .z0(),
/* output [01:00] */ .ff0(),
/* output [01:00] */ .ce1(),
/* output [01:00] */ .cl1(),
/* output [01:00] */ .z1(),
/* output [01:00] */ .ff1(),
/* output [01:00] */ .ov_msb(),
/* output [01:00] */ .co_msb(),
/* output [01:00] */ .cmsb({cmsb, nc1}),
/* output [01:00] */ .so(),
/* output [01:00] */ .f0_bus_stat(),
/* output [01:00] */ .f0_blk_stat(),
/* output [01:00] */ .f1_bus_stat(),
/* output [01:00] */ .f1_blk_stat()
);
end
else if ((Resolution <= CRC_24_BIT) && (TimeMultiplexing == CRC_CFG_TDM_DISABLE))
begin : sC24
cy_psoc3_dp24 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_CHNED,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_ENBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_b(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_CHNED,
`SC_FB_CHNED, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_c(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpPOVal, `SC_MSB_NOCHN,
`SC_FB_CHNED, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) CRCdp(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si),
/* input */ .route_ci(ci),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output [02:00] */ .ce0(),
/* output [02:00] */ .cl0(),
/* output [02:00] */ .z0(),
/* output [02:00] */ .ff0(),
/* output [02:00] */ .ce1(),
/* output [02:00] */ .cl1(),
/* output [02:00] */ .z1(),
/* output [02:00] */ .ff1(),
/* output [02:00] */ .ov_msb(),
/* output [02:00] */ .co_msb(),
/* output [02:00] */ .cmsb({cmsb, nc1, nc2}),
/* output [02:00] */ .so(),
/* output [02:00] */ .f0_bus_stat(),
/* output [02:00] */ .f0_blk_stat(),
/* output [02:00] */ .f1_bus_stat(),
/* output [02:00] */ .f1_blk_stat()
);
end
else if ((Resolution <= CRC_32_BIT) && (TimeMultiplexing == CRC_CFG_TDM_DISABLE))
begin : sC32
cy_psoc3_dp32 #(.cy_dpconfig_a(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_ROUTE, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
`SC_FB_NOCHN, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_ENBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_b(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_CHNED,
`SC_FB_CHNED, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_c(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_DSBL, `SC_MSB_BIT7, `SC_MSB_CHNED,
`SC_FB_CHNED, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
}), .cy_dpconfig_d(
{
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG0 Comment: */
`CS_ALU_OP__XOR, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP___SL, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE,
`CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG1 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG2 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG3 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG4 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG5 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG6 Comment: */
`CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0,
`CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC___F1,
`CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA,
`CS_CMP_SEL_CFGA, /*CS_REG7 Comment: */
8'hFF, 8'h00, /*SC_REG4 Comment: */
8'hFF, 8'hFF, /*SC_REG5 Comment: */
`SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH,
`SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL,
`SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI,
`SC_SI_A_CHAIN, /*SC_REG6 Comment: */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0,
1'b0, `SC_FIFO1_BUS, `SC_FIFO0_BUS,
`SC_MSB_ENBL, dpPOVal, `SC_MSB_NOCHN,
`SC_FB_CHNED, `SC_CMP1_NOCHN,
`SC_CMP0_NOCHN, /*SC_REG7 Comment: */
10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX,
`SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL,
`SC_WRK16CAT_DSBL /*SC_REG8 Comment: */
})) CRCdp(
/* input */ .clk(clk),
/* input [02:00] */ .cs_addr(cs_addr),
/* input */ .route_si(si),
/* input */ .route_ci(ci),
/* input */ .f0_load(1'b0),
/* input */ .f1_load(1'b0),
/* input */ .d0_load(1'b0),
/* input */ .d1_load(1'b0),
/* output [03:00] */ .ce0(),
/* output [03:00] */ .cl0(),
/* output [03:00] */ .z0(),
/* output [03:00] */ .ff0(),
/* output [03:00] */ .ce1(),
/* output [03:00] */ .cl1(),
/* output [03:00] */ .z1(),
/* output [03:00] */ .ff1(),
/* output [03:00] */ .ov_msb(),
/* output [03:00] */ .co_msb(),
/* output [03:00] */ .cmsb({cmsb, nc1, nc2, nc3}),
/* output [03:00] */ .so(),
/* output [03:00] */ .f0_bus_stat(),
/* output [03:00] */ .f0_blk_stat(),
/* output [03:00] */ .f1_bus_stat(),
/* output [03:00] */ .f1_blk_stat()
);
end
endgenerate
/**************************************************************************/
/* Synchronous procedures */
/**************************************************************************/
generate
/* Time Multiplexing Logic */
if (TimeMultiplexing == CRC_CFG_TDM_ENABLE)
begin
always @(posedge clk or posedge reset_final)
begin
if (reset_final)
state <= 2'b11;
else
case (state)
CRC_STATE_CALC_LOWER: state <= CRC_STATE_SAVE_LOWER;
CRC_STATE_SAVE_LOWER: state <= CRC_STATE_CALC_UPPER;
CRC_STATE_CALC_UPPER: state <= CRC_STATE_SAVE_UPPER;
CRC_STATE_SAVE_UPPER: state <= CRC_STATE_CALC_LOWER;
default: state <= CRC_STATE_CALC_LOWER;
endcase
end
/* sync so */
always @(posedge clk)
begin
if (reset_final)
begin
so_reg <= 1'b1;
end
else if (save_so)
begin
so_reg<= so;
end
else so_reg<=so_reg;
end
/* ci */
always @(posedge clk)
begin
if (reset_final)
ci_temp <= 1'b1;
else if (save)
begin
ci_temp <= ci;
end
else ci_temp<=ci_temp;
end
/* si */
always @(posedge clk)
begin
if (reset_final)
sc_temp <= 1'b1;
else if (save)
begin
sc_temp <= sc_out[dpPOVal];
end
else sc_temp<=sc_temp;
end
end
endgenerate
/**************************************************************************/
/* Combinatorial procedures */
/**************************************************************************/
/* Chain Datapathes */
generate
if (TimeMultiplexing == CRC_CFG_TDM_ENABLE)
begin
if (Resolution <= CRC_16_BIT)
begin
assign so = so_a;
assign sc_out = sc_out_a;
end
else if (Resolution <= CRC_24_BIT)
begin
assign si_b = dcfg ? si : so_a;
assign so = so_b;
assign sc_out = sc_out_b;
end
else if (Resolution <= CRC_32_BIT)
begin
assign si_b = so_a;
assign so = so_b;
assign sc_out = sc_out_b;
end
else if (Resolution <= CRC_40_BIT)
begin
assign si_c = so_b;
assign si_b = dcfg ? si : so_a;
assign so = so_c;
assign sc_out = sc_out_c;
end
else if (Resolution <= CRC_48_BIT)
begin
assign si_c = so_b;
assign si_b = so_a;
assign so = so_c;
assign sc_out = sc_out_c;
end
else if (Resolution <= CRC_56_BIT)
begin
assign si_d = so_c;
assign si_c = so_b;
assign si_b = dcfg ? si : so_a;
assign so = so_d;
assign sc_out = sc_out_d;
end
else if (Resolution <= CRC_64_BIT)
begin
assign si_d = so_c;
assign si_c = so_b;
assign si_b = so_a;
assign so = so_d;
assign sc_out = sc_out_d;
end
end
endgenerate
generate
if (TimeMultiplexing == CRC_CFG_TDM_DISABLE)
begin
assign cs_addr = {reset, 1'b0, enable_final};
assign ci = cmsb ^ di;
assign si = cmsb ^ di;
end
else
begin
assign cs_addr = {reset, state[1:0]};
assign ci = dcfg ? sc_out[dpPOVal] : ci_temp;
assign si = dcfg ? so_reg : sc_temp ^ di;
assign ci_mult = ci ^ di;
end
endgenerate
/* Control Signals */
assign ctrl_enable = control[CRC_CTRL_ENABLE];
assign ctrl_reset = control[CRC_CTRL_RESET];
assign save = state[1];
assign save_so = ~save;
assign dcfg = state[0];
assign reset_final = ctrl_reset | reset;
assign enable_final = ctrl_enable & enable;
endmodule /* CRC_UART_v0_1 */
`endif /* CRC_UART_v0_1_V_ALREADY_INCLUDED */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_SYMBOL_V
`define SKY130_FD_SC_HVL__O21AI_SYMBOL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__o21ai (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_rfifo.v (Modified from uart_fifo.v) ////
//// ////
//// ////
//// This file is part of the "UART 16550 compatible" project ////
//// http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Documentation related to this project: ////
//// - http://www.opencores.org/cores/uart16550/ ////
//// ////
//// Projects compatibility: ////
//// - WISHBONE ////
//// RS232 Protocol ////
//// 16550D uart (mostly supported) ////
//// ////
//// Overview (main Features): ////
//// UART core receiver FIFO ////
//// ////
//// To Do: ////
//// Nothing. ////
//// ////
//// Author(s): ////
//// - [email protected] ////
//// - Jacob Gorban ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// Created: 2001/05/12 ////
//// Last Updated: 2002/07/22 ////
//// (See log for the revision history) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/06/11 16:37:47 gorban
// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
//
// Revision 1.2 2002/07/29 21:16:18 gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1 2002/07/22 23:02:23 gorban
// Bug Fixes:
// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
// Problem reported by Kenny.Tung.
// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
// * Made FIFO's as general inferrable memory where possible.
// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
// * Added optional baudrate output (baud_o).
// This is identical to BAUDOUT* signal on 16550 chip.
// It outputs 16xbit_clock_rate - the divided clock.
// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16 2001/12/20 13:25:46 mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15 2001/12/18 09:01:07 mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14 2001/12/17 14:46:48 mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13 2001/11/26 21:38:54 gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12 2001/11/08 14:54:23 mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11 2001/11/07 17:51:52 gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10 2001/10/20 09:58:40 gorban
// Small synopsis fixes
//
// Revision 1.9 2001/08/24 21:01:12 mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8 2001/08/24 08:48:10 mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7 2001/08/23 16:05:05 mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3 2001/05/31 20:08:01 gorban
// FIFO changes and other corrections.
//
// Revision 1.3 2001/05/27 17:37:48 gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2 2001/05/17 18:34:18 gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0 2001-05-17 21:27:12+02 jacob
// Initial revision
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "uart_defines.v"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
// Control signals
push, // push strobe, active high
pop, // pop strobe, active high
// status signals
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
// FIFO parameters
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
// flags FIFO
reg [2:0] fifo[fifo_depth-1:0];
// FIFO pointers
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 4'h1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
(.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10] <= 0;
fifo[11] <= 0;
fifo[12] <= 0;
fifo[13] <= 0;
fifo[14] <= 0;
fifo[15] <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth) // overrun condition
begin
top <= top_plus_1;
fifo[top] <= data_in[2:0];
count <= count + 5'd1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= 0;
bottom <= bottom + 4'd1;
count <= count - 5'd1;
end
2'b11 : begin
bottom <= bottom + 4'd1;
top <= top_plus_1;
fifo[top] <= data_in[2:0];
end
default: ;
endcase
end
end // always
always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= 1'b1;
end // always
// please note though that data_out is only valid one clock after pop signal
assign data_out = {data8_out,fifo[bottom]};
// Additional logic for detection of error conditions (parity and framing) inside the FIFO
// for the Line Status Register bit 7
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
// a 1 is returned if any of the error bits in the fifo is 1
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule
|
`include "../src/rom.v"
`include "../src/serializer.v"
`include "../src/transmitter.v"
`include "../src/receiver.v"
`include "../src/comparator.v"
`include "../src/trx_path.v"
`default_nettype none
`timescale 1ns / 1ps
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 10000)
$finish;
// ============================================================================
wire s_dat;
trx_path #
(
.WIDTH (8),
.MODE ("SDR")
)
trx_path
(
.CLK (CLK),
.RST (RST),
.O_DAT (s_dat),
.I_DAT (s_dat)
);
endmodule
|
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