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`timescale 1ns / 1ps
module Gato_FSM(
clk,
reset,
state,
p1_mm,
p2_mm,
//entradas que son salidas de la otra maquina de estados
p1_tie,
p1_loss,
p1_win,
p2_tie,
p2_loss,
p2_win,
//salidas que van hacia a otra maquina de estados
verifica_status,
turno_p1,
turno_p2,
win_game,
loss_game,
tie_game
);
input clk, reset;
input p1_mm, p2_mm;
input p1_tie, p1_loss, p1_win, p2_tie, p2_loss, p2_win;
output reg turno_p1, turno_p2;
output reg verifica_status;
output reg win_game, loss_game, tie_game;
output [3:0] state;
reg [3:0] state, nextState;
//Estados de las FSM
parameter P1_Move = 0;
parameter P1_Status = 1;
parameter P2_Move = 2;
parameter P2_Status = 3;
parameter Win = 4;
parameter Tie = 5;
parameter Loss = 6;
initial turno_p1 <= 1'b1;
initial turno_p2 <= 1'b0;
//Asignación sincrona del singuiente estado
always @(posedge clk or posedge reset)
begin
if (reset)
state <= P1_Move;
else
state <= nextState;
end
//Asignacion asincrona de los estados
always @(state or p1_mm or p2_mm or p1_win or p1_loss or p1_tie or p2_win or p2_loss or p2_tie)
begin
nextState = 3'bxxx;
case(state)
P1_Move:
begin
verifica_status <= 1'b0;
turno_p1 <= 1'b1;
turno_p2 <= 1'b0;
if (p1_mm == 1'b0)
nextState = P1_Move;
else if (p1_mm == 1'b1)
nextState = P1_Status;
end
P1_Status:
begin
verifica_status <= 1'b1;
turno_p1 <= 1'b0;
turno_p2 <= 1'b1;
if (p1_tie == 1'b1 & p1_loss == 1'b0 & p1_win == 1'b0)
nextState = Tie;
else if (p1_win == 1'b1 & p1_tie == 1'b0 & p1_loss == 1'b0)
nextState = Loss;
else if (p2_mm == 1'b0)
nextState = P2_Move;
end
P2_Move:
begin
verifica_status <= 1'b0;
turno_p1 <= 1'b0;
turno_p2 <= 1'b1;
if (p2_mm == 1'b0)
nextState = P2_Move;
else if (p2_mm == 1'b1)
nextState = P2_Status;
end
P2_Status:
begin
verifica_status <= 1'b1;
turno_p1 <= 1'b1;
turno_p2 <= 1'b0;
if (p2_tie == 1'b1 & p2_loss == 1'b0 & p2_win == 1'b0)
nextState = Tie;
else if (p2_win == 1'b1 & p2_tie == 1'b0 & p2_loss == 1'b0)
nextState = Win;
else if (p1_mm == 1'b0)
nextState = P1_Move;
end
Win:
begin
win_game <= 1'b1;
nextState = Win;
end
Tie:
begin
tie_game <= 1'b1;
nextState = Tie;
end
Loss:
begin
loss_game <= 1'b1;
nextState = Loss;
end
default: nextState = P1_Move;
endcase
end
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module main(
`ifdef MK2
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
output [22:0] ROM_ADDR,
output ROM_CE,
input MCU_OVR,
/* debug */
output p113_out,
`endif
`ifdef MK3
input SNES_CIC_CLK,
/* Bus 1: 2x PSRAM, 64Mbit, 16bit, 70ns */
output [21:0] ROM_ADDR,
output ROM_1CE,
output ROM_2CE,
output ROM_ZZ,
/* debug */
output PM6_out,
output PN6_out,
input PT5_in,
`endif
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
inout [15:0] ROM_DATA,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
input SPI_SCK,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK
);
`define upper(i) (8*(i+1)-1)
`define lower(i) (8*(i+0)-0)
wire CLK2;
wire dspx_dp_enable;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [7:0] SAVERAM_BASE;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
//wire [7:0] dac_volume;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [7:0] DMA_SNES_DATA_IN;
wire [7:0] DMA_SNES_DATA_OUT;
wire [7:0] CTX_SNES_DATA_IN;
wire [7:0] DSPX_SNES_DATA_IN;
wire [7:0] DSPX_SNES_DATA_OUT;
wire [23:0] dspx_pgm_data;
wire [10:0] dspx_pgm_addr;
wire dspx_pgm_we;
wire [15:0] dspx_dat_data;
wire [10:0] dspx_dat_addr;
wire dspx_dat_we;
wire [15:0] featurebits;
wire feat_cmd_unlock = featurebits[5];
wire r213f_enable;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [13:0] DBG_msu_address;
wire DBG_msu_reg_oe_rising;
wire DBG_msu_reg_oe_falling;
wire DBG_msu_reg_we_rising;
wire [2:0] SD_DMA_DBG_clkcnt;
wire [10:0] SD_DMA_DBG_cyclecnt;
wire [9:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
wire [7:0] reg_group;
wire [7:0] reg_index;
wire [7:0] reg_value;
wire [7:0] reg_invmask;
wire reg_we;
wire [7:0] reg_read;
reg [7:0] SNES_PARDr = 8'b11111111;
reg [7:0] SNES_PAWRr = 8'b11111111;
reg [7:0] SNES_READr = 8'b11111111;
reg [7:0] SNES_WRITEr = 8'b11111111;
reg [7:0] SNES_CPU_CLKr = 8'b00000000;
reg [7:0] SNES_ROMSELr = 8'b11111111;
reg [7:0] SNES_PULSEr = 8'b11111111;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
reg loop_enable = 0;
reg [7:0] loop_data = 8'h80; // BRA
// exe region
reg exe_present; initial exe_present = 0;
wire map_unlock;
reg map_Fx_rd_unlock_r; initial map_Fx_rd_unlock_r = 0;
reg map_Fx_wr_unlock_r; initial map_Fx_wr_unlock_r = 0;
reg map_Ex_rd_unlock_r; initial map_Ex_rd_unlock_r = 0;
reg map_Ex_wr_unlock_r; initial map_Ex_wr_unlock_r = 0;
reg map_snescmd_rd_unlock_r; initial map_snescmd_rd_unlock_r = 0;
reg map_snescmd_wr_unlock_r; initial map_snescmd_wr_unlock_r = 0;
reg SNES_SNOOPRD_DATA_OE = 0;
reg SNES_SNOOPWR_DATA_OE = 0;
reg SNES_SNOOPPAWR_DATA_OE = 0;
reg SNES_SNOOPPARD_DATA_OE = 0;
reg [3:0] SNES_SNOOPRD_count;
reg [3:0] SNES_SNOOPWR_count;
reg [3:0] SNES_SNOOPPAWR_count;
reg [3:0] SNES_SNOOPPARD_count;
reg [7:0] CTX_DINr;
reg CTX_DIRr;
// early signals for snooping bus
wire SNES_PAWR_start_early = ((SNES_PAWRr[4:1] | SNES_PAWRr[5:2]) == 4'b1110);
wire SNES_RD_start_early = ((SNES_READr[6:1] | SNES_READr[7:2]) == 6'b111100);
wire [23:0] SNES_ADDR = (SNES_ADDRr[5] & SNES_ADDRr[4]);
wire [7:0] SNES_PA = (SNES_PAr[5] & SNES_PAr[4]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
reg [23:0] SNES_ADDR_early; always @(posedge CLK2) SNES_ADDR_early <= (SNES_ADDRr[3] & SNES_ADDRr[2]);
wire SNES_PULSE_IN = SNES_READ_IN & SNES_WRITE_IN & ~SNES_CPU_CLK_IN;
wire SNES_PULSE_end = (SNES_PULSEr[6:1] == 6'b000011);
wire SNES_PARD_start = (SNES_PARDr[6:1] == 6'b111110);
wire SNES_PARD_end = (SNES_PARDr[6:1] == 6'b000001);
// Sample PAWR data earlier on CPU accesses, later on DMA accesses...
wire SNES_PAWR_start = (SNES_PAWRr[7:1] == (({SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h02100) ? 7'b1110000 : 7'b1000000));
wire SNES_PAWR_end = (SNES_PAWRr[6:1] == 6'b000001);
wire SNES_RD_start = (SNES_READr[6:1] == 6'b111110);
wire SNES_RD_end = (SNES_READr[6:1] == 6'b000001);
wire SNES_WR_start = (SNES_WRITEr[6:1] == 6'b111000);
wire SNES_WR_end = (SNES_WRITEr[6:1] == 6'b000001);
wire SNES_cycle_start = (SNES_CPU_CLKr[6:1] == 6'b000001);
wire SNES_cycle_end = (SNES_CPU_CLKr[6:1] == 6'b111110);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_READ_late = SNES_READr[5] & SNES_READr[4];
wire SNES_READ_narrow = SNES_READ | SNES_READ_late;
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_PAWR = SNES_PAWRr[2] & SNES_PAWRr[1];
wire SNES_ROMSEL_EARLY = (SNES_ROMSELr[2] & SNES_ROMSELr[1]);
wire SNES_WRITE_early = SNES_WRITEr[1] & SNES_WRITEr[0];
reg SNES_SNOOPPARD_end;
reg SNES_SNOOPPAWR_end;
reg SNES_SNOOPRD_end;
reg SNES_SNOOPWR_end;
always @(posedge CLK2) begin
if (SNES_reset_strobe) begin
SNES_SNOOPPARD_end <= 0;
SNES_SNOOPPAWR_end <= 0;
SNES_SNOOPRD_end <= 0;
SNES_SNOOPWR_end <= 0;
end
else begin
SNES_SNOOPPARD_end <= SNES_SNOOPPARD_count == 4;
SNES_SNOOPPAWR_end <= SNES_SNOOPPAWR_count == 4;
SNES_SNOOPRD_end <= SNES_SNOOPRD_count == 4;
SNES_SNOOPWR_end <= SNES_SNOOPWR_count == 4;
end
end
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire SD_DMA_TO_ROM;
wire free_slot = (SNES_PULSE_end | free_strobe) & ~SD_DMA_TO_ROM;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= (~ROM_HIT | loop_enable);
end
always @(posedge CLK2) begin
SNES_PULSEr <= {SNES_PULSEr[6:0], SNES_PULSE_IN};
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_PAWRr <= {SNES_PAWRr[6:0], SNES_PAWR_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
// count of write low
if (SNES_reset_strobe | SNES_SNOOPPAWR_end) begin
SNES_SNOOPPAWR_count <= 0;
SNES_SNOOPPAWR_DATA_OE <= 0;
end
else if (SNES_PAWR_start_early) begin
SNES_SNOOPPAWR_count <= 1;
SNES_SNOOPPAWR_DATA_OE <= 1;
end
else if (|SNES_SNOOPPAWR_count) begin
SNES_SNOOPPAWR_count <= SNES_SNOOPPAWR_count + 1;
end
// count of write low
if (SNES_reset_strobe | SNES_SNOOPPARD_end) begin
SNES_SNOOPPARD_count <= 0;
SNES_SNOOPPARD_DATA_OE <= 0;
end
// avoid triggering OE signals on 213f to avoid problem with region override
// do not sniff external B-bus (>=$2184, e.g. Satellaview)
else if (SNES_PARD_start & ~r213f_enable & (SNES_PA < 8'h84)) begin
SNES_SNOOPPARD_count <= 1;
SNES_SNOOPPARD_DATA_OE <= 1;
end
else if (|SNES_SNOOPPARD_count) begin
SNES_SNOOPPARD_count <= SNES_SNOOPPARD_count + 1;
end
// count of write low
if (SNES_reset_strobe | SNES_SNOOPWR_end) begin
SNES_SNOOPWR_count <= 0;
SNES_SNOOPWR_DATA_OE <= 0;
end
else if (SNES_WR_start) begin
SNES_SNOOPWR_count <= 1;
SNES_SNOOPWR_DATA_OE <= 1;
end
else if (|SNES_SNOOPWR_count) begin
SNES_SNOOPWR_count <= SNES_SNOOPWR_count + 1;
end
// count of write low
if (SNES_reset_strobe | SNES_SNOOPRD_end) begin
SNES_SNOOPRD_count <= 0;
SNES_SNOOPRD_DATA_OE <= 0;
end
else if (SNES_RD_start_early) begin
SNES_SNOOPRD_count <= 1;
SNES_SNOOPRD_DATA_OE <= 1;
end
else if (|SNES_SNOOPRD_count) begin
SNES_SNOOPRD_count <= SNES_SNOOPRD_count + 1;
end
end
parameter ST_IDLE = 11'b00000000001;
parameter ST_MCU_RD_ADDR = 11'b00000000010;
parameter ST_MCU_RD_END = 11'b00000000100;
parameter ST_MCU_WR_ADDR = 11'b00000001000;
parameter ST_MCU_WR_END = 11'b00000010000;
parameter ST_CTX_WR_ADDR = 11'b00000100000;
parameter ST_CTX_WR_END = 11'b00001000000;
parameter ST_DMA_RD_ADDR = 11'b00010000000;
parameter ST_DMA_RD_END = 11'b00100000000;
parameter ST_DMA_WR_ADDR = 11'b01000000000;
parameter ST_DMA_WR_END = 11'b10000000000;
parameter SNES_DEAD_TIMEOUT = 17'd96000; // 1ms
parameter ROM_CYCLE_LEN = 4'd7;
reg [10:0] STATE;
initial STATE = ST_IDLE;
assign DSPX_SNES_DATA_IN = BUS_DATA;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign DMA_SNES_DATA_IN = BUS_DATA;
assign CTX_SNES_DATA_IN = CTX_DIRr ? CTX_DINr : SNES_DATAr[0];
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
assign SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
wire [23:0] CTX_ADDR;
wire [15:0] CTX_DOUT;
ctx snes_ctx (
.clkin(CLK2),
.reset(SNES_reset_strobe),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_RD_end_PRE(SNES_RD_end),
.SNES_WR_end_PRE(SNES_SNOOPWR_end),
.SNES_PARD_end_PRE(SNES_SNOOPPARD_end),
.SNES_PAWR_end_PRE(SNES_SNOOPPAWR_end),
.SNES_DATA_IN_PRE(CTX_SNES_DATA_IN), // needs to handle PA accesses, too
//.OE_RD_ENABLE(ctx_rd_enable),
.OE_WR_ENABLE(ctx_wr_enable),
.OE_PAWR_ENABLE(ctx_pawr_enable),
.OE_PARD_ENABLE(ctx_pard_enable),
.BUS_WRQ(CTX_WRQ),
.BUS_RDY(CTX_RDY),
.snescmd_unlock(snescmd_unlock),
.ROM_ADDR(CTX_ADDR),
.ROM_DATA(CTX_DOUT),
.ROM_WORD_ENABLE(CTX_WORD),
.DBG(CTX_DBG)
);
wire [23:0] DMA_ADDR;
wire [15:0] DMA_DOUT;
reg [15:0] DMA_DINr;
dma snes_dma (
.clkin(CLK2),
.reset(SNES_reset_strobe),
.enable(dma_enable),
.reg_addr(SNES_ADDR[3:0]),
.reg_data_in(DMA_SNES_DATA_IN),
.reg_data_out(DMA_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_we_rising(SNES_WR_end),
.loop_enable(DMA_LOOP_ENABLE),
.BUS_RDY(DMA_RDY),
.BUS_RRQ(DMA_RRQ),
.BUS_WRQ(DMA_WRQ),
.ROM_ADDR(DMA_ADDR),
.ROM_DATA_OUT(DMA_DOUT),
.ROM_DATA_IN(DMA_DINr),
.ROM_WORD_ENABLE(DMA_WORD)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
wire [15:0] dsp_feat;
`ifndef MK2_DEBUG
upd77c25 snes_dspx (
.DI(DSPX_SNES_DATA_IN),
.DO(DSPX_SNES_DATA_OUT),
.A0(DSPX_A0),
.enable(dspx_enable),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.RST(~dspx_reset),
.CLK(CLK2),
.PGM_WR(dspx_pgm_we),
.PGM_DI(dspx_pgm_data),
.PGM_WR_ADDR(dspx_pgm_addr),
.DAT_WR(dspx_dat_we),
.DAT_DI(dspx_dat_data),
.DAT_WR_ADDR(dspx_dat_addr),
.DP_enable(dspx_dp_enable),
.DP_ADDR(SNES_ADDR[10:0]),
.dsp_feat(dsp_feat)
);
`endif
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_base_out(SAVERAM_BASE),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.reg_group_out(reg_group),
.reg_index_out(reg_index),
.reg_value_out(reg_value),
.reg_invmask_out(reg_invmask),
.reg_we_out(reg_we),
.reg_read_out(reg_read),
//.trc_config_data_in(trc_config_data),
.dspx_pgm_data_out(dspx_pgm_data),
.dspx_pgm_addr_out(dspx_pgm_addr),
.dspx_pgm_we_out(dspx_pgm_we),
.dspx_dat_data_out(dspx_dat_data),
.dspx_dat_addr_out(dspx_dat_addr),
.dspx_dat_we_out(dspx_dat_we),
.dspx_reset_out(dspx_reset),
.featurebits_out(featurebits),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR_early(SNES_ADDR_early), // requested address from SNES
.SNES_WRITE_early(SNES_WRITE_early),
.SNES_PA(SNES_PA),
.SNES_ROMSEL(SNES_ROMSEL),
.ROM_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.ROM_HIT(ROM_HIT), // want to access RAM0
.IS_SAVERAM(IS_SAVERAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.IS_PATCH(IS_PATCH),
.SAVERAM_BASE(SAVERAM_BASE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
.map_unlock(map_unlock),
.map_Ex_rd_unlock(map_Ex_rd_unlock_r),
.map_Ex_wr_unlock(map_Ex_wr_unlock_r),
.map_Fx_rd_unlock(map_Fx_rd_unlock_r),
.map_Fx_wr_unlock(map_Fx_wr_unlock_r),
.snescmd_unlock(snescmd_unlock),
//MSU-1
.msu_enable(msu_enable),
//DMA-1
.dma_enable(dma_enable),
//uPD77C25
.dspx_enable(dspx_enable),
.dspx_dp_enable(dspx_dp_enable),
.dspx_a0(DSPX_A0),
.r213f_enable(r213f_enable),
.r2100_hit(r2100_hit),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.branch3_enable(branch3_enable),
.exe_enable(exe_enable),
.map_enable(map_enable)
);
// flop all snes_addr outputs
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.branch3_enable(branch3_enable),
.exe_present(exe_present),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.SNES_cycle_start(SNES_cycle_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.feat_cmd_unlock_in(feat_cmd_unlock),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock),
.map_unlock(map_unlock)
);
wire [7:0] snescmd_dout;
parameter ST_R213F_ARMED = 4'b0001;
parameter ST_R213F_WAITBUS = 4'b0010;
parameter ST_R213F_OVERRIDE = 4'b0100;
parameter ST_R213F_HOLD = 4'b1000;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [3:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 1;
initial r213f_state = ST_R213F_ARMED;
initial r213f_delay = 3'b001;
reg [7:0] r2100r = 0;
reg r2100_forcewrite = 0;
reg r2100_forcewrite_pre = 0;
wire [3:0] r2100_limit = featurebits[10:7];
wire [3:0] r2100_limited = (SNES_DATA[3:0] > r2100_limit) ? r2100_limit : SNES_DATA[3:0];
wire r2100_patch = featurebits[6];
wire r2100_enable = r2100_hit & (r2100_patch | ~(&r2100_limit));
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
r2100_forcewrite <= r2100_forcewrite_pre;
end
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD) ? (r213f_forceread ? 8'bZ : r213fr)
:(r2100_enable & ~SNES_PAWR & r2100_forcewrite) ? r2100r
:(((~SNES_READ & ((~SNES_SNOOPPAWR_DATA_OE & ~SNES_SNOOPPARD_DATA_OE) | ~SNES_ROMSEL_EARLY)))
& ~(r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
? (dspx_enable ? DSPX_SNES_DATA_OUT
:dspx_dp_enable ? DSPX_SNES_DATA_OUT
:msu_enable ? MSU_SNES_DATA_OUT
:dma_enable ? DMA_SNES_DATA_OUT
:(cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
// put spinloop below cheat so we don't overwrite jmp target after NMI
:loop_enable ? loop_data
:((snescmd_unlock | feat_cmd_unlock | map_snescmd_rd_unlock_r) & snescmd_enable) ? snescmd_dout
:(ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
// CTX
reg CTX_WR_PENDr;
initial CTX_WR_PENDr = 0;
reg [23:0] CTX_ROM_ADDRr;
initial CTX_ROM_ADDRr = 24'h0;
reg [15:0] CTX_ROM_DATAr;
initial CTX_ROM_DATAr = 16'h0000;
reg CTX_ROM_WORDr;
initial CTX_ROM_WORDr = 1'b0;
// DMA
reg DMA_WR_PENDr;
initial DMA_WR_PENDr = 0;
reg DMA_RD_PENDr;
initial DMA_RD_PENDr = 0;
reg [23:0] DMA_ROM_ADDRr;
initial DMA_ROM_ADDRr = 24'h0;
reg [15:0] DMA_ROM_DATAr;
initial DMA_ROM_DATAr = 16'h0000;
reg DMA_ROM_WORDr;
initial DMA_ROM_WORDr = 1'b0;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
// CTX
reg RQ_CTX_RDYr;
initial RQ_CTX_RDYr = 1'b1;
assign CTX_RDY = RQ_CTX_RDYr;
// DMA
reg RQ_DMA_RDYr;
initial RQ_DMA_RDYr = 1'b1;
assign DMA_RDY = RQ_DMA_RDYr;
wire MCU_WE_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_WR_HIT = |(STATE & (ST_MCU_WR_ADDR | ST_MCU_WR_END));
wire MCU_RD_HIT = |(STATE & (ST_MCU_RD_ADDR | ST_MCU_RD_END));
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
// CTX
wire CTX_WE_HIT = |(STATE & ST_CTX_WR_ADDR);
wire CTX_WR_HIT = |(STATE & (ST_CTX_WR_ADDR | ST_CTX_WR_END));
wire CTX_HIT = CTX_WR_HIT;
// DMA
wire DMA_WE_HIT = |(STATE & ST_DMA_WR_ADDR);
wire DMA_WR_HIT = |(STATE & (ST_DMA_WR_ADDR | ST_DMA_WR_END));
wire DMA_RD_HIT = |(STATE & (ST_DMA_RD_ADDR | ST_DMA_RD_END));
wire DMA_HIT = DMA_WR_HIT | DMA_RD_HIT;
`ifdef MK2
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST)
);
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : CTX_HIT ? CTX_ROM_ADDRr[23:1] : DMA_HIT ? DMA_ROM_ADDRr[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : CTX_HIT ? CTX_ROM_ADDRr[0] : DMA_HIT ? DMA_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
//always @(posedge CLK2) ROM_ADDR_PRE <= (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : CTX_HIT ? CTX_ROM_ADDRr[23:1] : DMA_HIT ? DMA_ROM_ADDRr[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
//always @(posedge CLK2) ROM_ADDR0_PRE <= (SD_DMA_TO_ROM) ? MCU_ADDR[0] : CTX_HIT ? CTX_ROM_ADDRr[0] : DMA_HIT ? DMA_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_CE = 1'b0;
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[9:0]), // input [9 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [9 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
`ifdef MK3
pll snes_pll(
.inclk0(CLKIN),
.c0(CLK2),
// .c1(CLK192),
.locked(DCM_LOCKED),
.areset(DCM_RST)
);
wire ROM_ADDR22;
assign ROM_ADDR22 = (SD_DMA_TO_ROM) ? MCU_ADDR[1] : CTX_HIT ? CTX_ROM_ADDRr[1] : DMA_HIT ? DMA_ROM_ADDRr[1] : MCU_HIT ? ROM_ADDRr[1] : MAPPED_SNES_ADDR[1];
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:2] : CTX_HIT ? CTX_ROM_ADDRr[23:2] : DMA_HIT ? DMA_ROM_ADDRr[23:2] : MCU_HIT ? ROM_ADDRr[23:2] : MAPPED_SNES_ADDR[23:2];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : CTX_HIT ? CTX_ROM_ADDRr[0] : DMA_HIT ? DMA_ROM_ADDRr[0] : MCU_HIT ? ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign ROM_ZZ = 1'b1;
assign ROM_1CE = ROM_ADDR22;
assign ROM_2CE = ~ROM_ADDR22;
snescmd_buf snescmd (
.clock(CLK2), // input clka
.wren_a(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & snescmd_enable)), // input [0 : 0] wea
.address_a(SNES_ADDR[9:0]), // input [8 : 0] addra
.data_a(SNES_DATA), // input [7 : 0] dina
.q_a(snescmd_dout), // output [7 : 0] douta
.wren_b(snescmd_we_mcu), // input [0 : 0] web
.address_b(snescmd_addr_mcu), // input [9 : 0] addrb
.data_b(snescmd_data_out_mcu), // input [7 : 0] dinb
.q_b(snescmd_data_in_mcu) // output [7 : 0] doutb
);
`endif
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
// context engine request
always @(posedge CLK2) begin
if(CTX_WRQ) begin
CTX_WR_PENDr <= 1'b1;
RQ_CTX_RDYr <= 1'b0;
CTX_ROM_ADDRr <= CTX_ADDR;
CTX_ROM_DATAr <= CTX_DOUT;
CTX_ROM_WORDr <= CTX_WORD;
end
else if(STATE & ST_CTX_WR_END) begin
CTX_WR_PENDr <= 1'b0;
RQ_CTX_RDYr <= 1'b1;
end
end
// MCU r/w request
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
// dma engine request
always @(posedge CLK2) begin
if(DMA_RRQ) begin
DMA_RD_PENDr <= 1'b1;
RQ_DMA_RDYr <= 1'b0;
DMA_ROM_ADDRr <= DMA_ADDR;
DMA_ROM_WORDr <= DMA_WORD;
end
else if(DMA_WRQ) begin
DMA_WR_PENDr <= 1'b1;
RQ_DMA_RDYr <= 1'b0;
DMA_ROM_ADDRr <= DMA_ADDR;
DMA_ROM_DATAr <= DMA_DOUT;
DMA_ROM_WORDr <= DMA_WORD;
end
else if(STATE & (ST_DMA_RD_END | ST_DMA_WR_END)) begin
DMA_RD_PENDr <= 1'b0;
DMA_WR_PENDr <= 1'b0;
RQ_DMA_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 18'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
CTX_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
CTX_DIRr <= SNES_DATABUS_DIR;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(free_slot | SNES_DEADr) begin
if(CTX_WR_PENDr) begin
STATE <= ST_CTX_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(DMA_RD_PENDr) begin
STATE <= ST_DMA_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(DMA_WR_PENDr) begin
STATE <= ST_DMA_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_CTX_WR_ADDR: begin
STATE <= ST_CTX_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_CTX_WR_END;
end
ST_DMA_RD_ADDR: begin
STATE <= ST_DMA_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_DMA_RD_END;
// FIXME: seems like the lower byte is the upper byte (BIG ENDIAN)? Maybe a bug in the DMA addressing logic.
DMA_DINr <= (ROM_ADDR0 ? ROM_DATA : {ROM_DATA[7:0],ROM_DATA[15:8]});
end
ST_DMA_WR_ADDR: begin
STATE <= ST_DMA_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_DMA_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END, ST_CTX_WR_END, ST_DMA_RD_END, ST_DMA_WR_END: begin
STATE <= ST_IDLE;
end
endcase
end
/***********************
* R213F read patching *
***********************/
always @(posedge CLK2) begin
case(r213f_state)
ST_R213F_HOLD: begin
r213f_state <= ST_R213F_HOLD;
if(SNES_cycle_end) begin
r213f_forceread <= 1'b1;
r213f_state <= ST_R213F_ARMED;
end
end
ST_R213F_ARMED: begin
r213f_state <= ST_R213F_ARMED;
if(SNES_PARD_start & r213f_enable) begin
r213f_delay <= 3'b001;
r213f_state <= ST_R213F_WAITBUS;
end
end
ST_R213F_WAITBUS: begin
r213f_state <= ST_R213F_WAITBUS;
r213f_delay <= r213f_delay - 1;
if(r213f_delay == 3'b000) begin
r213f_state <= ST_R213F_OVERRIDE;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
end
end
ST_R213F_OVERRIDE: begin
r213f_state <= ST_R213F_HOLD;
r213f_forceread <= 1'b0;
end
endcase
end
/*********************************
* R2100 patching (experimental) *
*********************************/
reg [3:0] r2100_bright = 0;
reg [3:0] r2100_bright_orig = 0;
always @(posedge CLK2) begin
if(SNES_PULSE_end) r2100_forcewrite_pre <= 1'b0;
else if(SNES_PAWR_start & r2100_hit) begin
if(r2100_patch & SNES_DATA[7]) begin
// keep previous brightness during forced blanking so there is no DAC step
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b010, r2100_bright}; // 0xAx
end else if (r2100_patch && SNES_DATA == 8'h00 && r2100r[7]) begin
// extend forced blanking when game goes from blanking to brightness 0 (Star Fox top of screen)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {1'b1, 3'b111, r2100_bright}; // 0xFx
end else if (r2100_patch && SNES_DATA[3:0] < 4'h8 && r2100_bright_orig > 4'hd) begin
// substitute big brightness changes with brightness 0 (so it is visible on 1CHIP)
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b011, 4'h0}; // 0x3x / 0xBx(!)
end else if (r2100_patch | ~(&r2100_limit)) begin
// save brightness, limit brightness
r2100_bright <= r2100_limited;
r2100_bright_orig <= SNES_DATA[3:0];
if (~(&r2100_limit) && SNES_DATA[3:0] > r2100_limit) begin
r2100_forcewrite_pre <= 1'b1;
r2100r <= {SNES_DATA[7], 3'b100, r2100_limited}; // 0x4x / 0xCx
end
end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) begin
MCU_WRITE_1<= MCU_WRITE;
end
assign ROM_DATA[7:0] = (ROM_ADDR0 || (!SD_DMA_TO_ROM && CTX_HIT && CTX_ROM_WORDr) || (!SD_DMA_TO_ROM && DMA_HIT && DMA_ROM_WORDr))
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: CTX_WR_HIT ? CTX_ROM_DATAr[15:8]
: DMA_WR_HIT ? DMA_ROM_DATAr[15:8]
: (ROM_HIT & ~loop_enable & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: CTX_WR_HIT ? CTX_ROM_DATAr[7:0]
: DMA_WR_HIT ? DMA_ROM_DATAr[7:0]
: (ROM_HIT & ~loop_enable & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
? MCU_WRITE
: CTX_WE_HIT ? 1'b0
: DMA_WE_HIT ? 1'b0
: (ROM_HIT & ~loop_enable & IS_WRITABLE & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WE_HIT ? 1'b0
: 1'b1;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = ~ROM_ADDR0 & ~(~SD_DMA_TO_ROM & CTX_HIT & CTX_ROM_WORDr) & ~(~SD_DMA_TO_ROM & DMA_HIT & DMA_ROM_WORDr);
reg ReadOrWrite_r; always @(posedge CLK2) ReadOrWrite_r <= ~(SNES_READr[1] & SNES_READr[0] & SNES_WRITEr[1] & SNES_WRITEr[0]);
assign SNES_DATABUS_OE = ((dspx_enable | dspx_dp_enable) & ReadOrWrite_r) ? 1'b0 :
(msu_enable & ReadOrWrite_r) ? 1'b0 :
(dma_enable & ReadOrWrite_r) ? 1'b0 :
(loop_enable & ~SNES_READ_narrow) ? 1'b0 :
(snescmd_enable & ReadOrWrite_r) ? (~(snescmd_unlock | feat_cmd_unlock | (map_snescmd_wr_unlock_r & ~SNES_WRITE) | (map_snescmd_rd_unlock_r & ~SNES_READ_narrow))) :
(r213f_enable & ~SNES_PARD) ? 1'b0 :
(r2100_enable & ~SNES_PAWR) ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
(ctx_wr_enable & SNES_SNOOPWR_DATA_OE) ? 1'b0 :
(ctx_pawr_enable & SNES_SNOOPPAWR_DATA_OE)? 1'b0 :
(ctx_pard_enable & SNES_SNOOPPARD_DATA_OE)? 1'b0 :
((IS_ROM & SNES_ROMSEL)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
|(SNES_READ_narrow & SNES_WRITE)
);
/* data bus direction: 0 = SNES -> FPGA; 1 = FPGA -> SNES
* data bus is always SNES -> FPGA to avoid fighting except when:
* a) the SNES wants to read
* b) we want to force a value on the bus
*/
assign SNES_DATABUS_DIR = ((~SNES_READ & ((~SNES_SNOOPPAWR_DATA_OE & ~SNES_SNOOPPARD_DATA_OE) | ROM_HIT)) | (~SNES_PARD & (r213f_enable)))
? (1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
^ (r2100_enable & ~SNES_PAWR & ~r2100_forcewrite & ~IS_ROM & ~IS_WRITABLE))
: ((~SNES_PAWR & r2100_enable) ? r2100_forcewrite
: 1'b0);
assign SNES_IRQ = 1'b0;
// Detect writes and handle dynamic NMI hook and address map unlock registers.
reg snescmd_addr_exe_r; always @(posedge CLK2) snescmd_addr_exe_r <= {2'b11,snescmd_addr_mcu} == 12'hC00;
reg snescmd_addr_map_r; always @(posedge CLK2) snescmd_addr_map_r <= {2'b10,snescmd_addr_mcu} == 12'hBB2;
always @(posedge CLK2) begin
// dynamic NMI hook enable/disable detected on writes to $2C00 from either SNES or MCU
if (SNES_WR_end & (snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & exe_enable) exe_present <= (SNES_DATA != 0) ? 1 : 0;
// snescmd_addr_mcu is 10 bits. $2C00 is inteleaved with $2A00 such that $2C00 comes first at 0
else if (snescmd_we_mcu & snescmd_addr_exe_r) exe_present <= (snescmd_data_out_mcu != 0) ? 1 : 0;
// address map unlock detected on writes from either SNES or MCU
if (SNES_WR_end & (snescmd_unlock | feat_cmd_unlock | map_snescmd_wr_unlock_r) & map_enable) {map_Fx_rd_unlock_r,map_Fx_wr_unlock_r,map_Ex_rd_unlock_r,map_Ex_wr_unlock_r,map_snescmd_rd_unlock_r,map_snescmd_wr_unlock_r} <= SNES_DATA;
else if (snescmd_we_mcu & snescmd_addr_map_r) {map_Fx_rd_unlock_r,map_Fx_wr_unlock_r,map_Ex_rd_unlock_r,map_Ex_wr_unlock_r,map_snescmd_rd_unlock_r,map_snescmd_wr_unlock_r} <= snescmd_data_out_mcu;
end
// spin loop state machine
// This is used to put the SNES into a spin loop. It replaces the current instruction fetch with a branch
// to itself. Upon release it lets the SNES fetch.
reg loop_state;
initial loop_state = 0;
parameter [`upper(2):0] loop_code = { 8'h80, 8'hFE }; // BRA $FE
always @(posedge CLK2) begin
if (!loop_enable) begin
loop_enable <= DMA_LOOP_ENABLE;
end
else begin
case (loop_state)
0: begin
if (SNES_RD_end) begin
loop_state <= 1;
loop_data <= loop_code[`upper(0):`lower(0)];
end
end
1: begin
if (SNES_RD_end) begin
loop_state <= 0;
loop_data <= loop_code[`upper(1):`lower(1)];
loop_enable <= DMA_LOOP_ENABLE;
end
end
endcase
end
end
`ifdef MK2_DEBUG
wire [35:0] CONTROL;
wire [7:0] TRIG0w = {
SNES_READ_IN,
SNES_WRITE_IN,
SNES_CPU_CLK_IN,
SNES_READ,
SNES_WRITE,
SNES_CPU_CLK,
SNES_DATABUS_OE,
SNES_DATABUS_DIR
};
wire [31:0] TRIG1w = {
SNES_ADDR_IN,
SNES_DATA_IN
};
wire [40:0] TRIG2w = {
SNES_ADDR,
SNES_DATA,
BUS_DATA
};
wire [3:0] TRIG3w = {
SNES_cycle_start,
SNES_RD_start,
SNES_RD_end,
SNES_WR_end
};
wire [25:0] TRIG4w = {
ROM_WE,
ROM_BHE,
ROM_BLE,
ROM_ADDR
};
reg [7:0] TRIG0;
reg [31:0] TRIG1;
reg [40:0] TRIG2;
reg [3:0] TRIG3;
reg [25:0] TRIG4;
always @(posedge CLK2) begin
TRIG0 <= TRIG0w;
TRIG1 <= TRIG1w;
TRIG2 <= TRIG2w;
TRIG3 <= TRIG3w;
TRIG4 <= TRIG4w;
end
/*
wire [35:0] CONTROL0;
chipscope_icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_icon snes_icon (
.CONTROL0(CONTROL) // INOUT BUS [35:0]
);
chipscope_ila snes_ila (
.CONTROL(CONTROL), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(TRIG0), // IN BUS [7:0]
.TRIG1(TRIG1), // IN BUS [31:0]
.TRIG2(TRIG2), // IN BUS [39:0]
.TRIG3(TRIG3), // IN BUS [3:0]
.TRIG4(TRIG4) // IN BUS [25:0]
);
*/
`endif
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: memory.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module memory (
address,
clock,
q);
input [4:0] address;
input clock;
output [8:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [8:0] sub_wire0;
wire [8:0] q = sub_wire0[8:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({9{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "inst_mem.mif",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 5,
altsyncram_component.width_a = 9,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "inst_mem.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "9"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "inst_mem.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 9 0 OUTPUT NODEFVAL "q[8..0]"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 9 0 @q_a 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL memory_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_PP_SYMBOL_V
`define SKY130_FD_SC_LS__AND4_PP_SYMBOL_V
/**
* and4: 4-input AND.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__and4 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_PP_SYMBOL_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// tdpram.v: Generic true dual-ported RAM with data flow-through //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module tdpram
#( parameter MEMD = 2*1024, // memory depth
parameter DATAW = 16 , // data width
parameter IZERO = 0 , // binary / Initial RAM with zeros (has priority over IFILE)
parameter IFILE = "" ) // initialization hex file (don't pass extension), optional
( input clk , // clock
input wEnbA , // write enable for port A
input wEnbB , // write enable for port B
input [`log2(MEMD)-1:0] addrA , // write addresses - packed from nWPORTS write ports
input [`log2(MEMD)-1:0] addrB , // write addresses - packed from nWPORTS write ports
input [DATAW -1:0] wDataA, // write data - packed from nRPORTS read ports
input [DATAW -1:0] wDataB, // write data - packed from nRPORTS read ports
output reg [DATAW -1:0] rDataA, // read data - packed from nRPORTS read ports
output reg [DATAW -1:0] rDataB); // read data - packed from nRPORTS read ports
// initialize RAM, with zeros if IZERO or file if IFLE.
integer i;
reg [DATAW-1:0] mem [0:MEMD-1]; // memory array
initial
if (IZERO)
for (i=0; i<MEMD; i=i+1) mem[i] = {DATAW{1'b0}};
else
if (IFILE != "") $readmemh({IFILE,".hex"}, mem);
// PORT A
always @(posedge clk) begin
// write/read; nonblocking statement to read old data
if (wEnbA) begin
mem[addrA] <= wDataA; // Change into blocking statement (=) to read new data
rDataA <= wDataA; // flow-through
end else
rDataA <= mem[addrA]; //Change into blocking statement (=) to read new data
end
// PORT B
always @(posedge clk) begin
// write/read; nonblocking statement to read old data
if (wEnbB) begin
mem[addrB] <= wDataB; // Change into blocking statement (=) to read new data
rDataB <= wDataB; // flow-through
end else
rDataB <= mem[addrB]; //Change into blocking statement (=) to read new data
end
endmodule
|
/*
Distributed under the MIT licesnse.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this start_of_frametware and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is furnished
to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
//ft_master_interface.v
/*
* Change log
* 10/23/2013
* -Fixed a bug in the response where the full response is always sent even
* when a Ping was returned
* -Added interrupts to the full 13 charater response type
*
*/
`timescale 1ns/1ps
`include "cbuilder_defines.v"
`define PING_RESP ((~`COMMAND_PING) & (4'hF))
`define WRITE_RESP ((~`COMMAND_WRITE) & (4'hF))
`define READ_RESP ((~`COMMAND_READ) & (4'hF))
`define RESET_RESP ((~`COMMAND_RESET) & (4'hF))
`define MASTER_ADDR_RESP ((~`COMMAND_MASTER_ADDR) & (4'hF))
`define CORE_DUMP_RESP ((~`COMMAND_CORE_DUMP) & (4'hF))
`define ID_DWORD 32'hCD15DBE5
`define ID_RESP (~`ID_DWORD)
`define STANDARD_RESPONSE 5
`define PING_RESPONSE 2
module ppfifo_host_interface (
//boilerplate
input rst,
input clk,
//master interface
input i_master_ready,
output o_ih_reset,
output reg o_ih_ready,
output reg [31:0] o_in_command,
output reg [31:0] o_in_address,
output reg [31:0] o_in_data,
output reg [27:0] o_in_data_count,
output reg o_oh_ready,
input i_oh_en,
input [31:0] i_out_status,
input [31:0] i_out_address,
input [31:0] i_out_data,
input [27:0] i_out_data_count,
input i_ing_en,
output reg o_ing_fin,
input i_egr_en,
output reg o_egr_fin,
//Ingress Ping Pong FIFO
input i_ingress_rdy,
output reg o_ingress_act,
output reg o_ingress_stb,
input [23:0] i_ingress_size,
input [31:0] i_ingress_data,
//Egress Ping Pong FIFO
input [1:0] i_egress_rdy,
output reg [1:0] o_egress_act,
output reg o_egress_stb,
input [23:0] i_egress_size,
output reg [31:0] o_egress_data
);
//local wires/registers
localparam IDLE = 0;
//XXX: Don't know what to do with this signal yet
reg [23:0] data_count;
reg [23:0] in_data_count;
reg [31:0] id;
//input handler specific states
localparam WAIT_FOR_START = 4'h1;
localparam READ_ID = 4'h2;
localparam READ_COMMAND = 4'h3;
localparam READ_DATA_COUNT = 4'h4;
localparam READ_ADDRESS = 4'h5;
localparam PROCESS_COMMAND = 4'h6;
localparam WAIT_FOR_DATA = 4'h7;
localparam NOTIFY_MASTER = 4'h8;
localparam FLUSH_FIFO = 4'h9;
reg [3:0] ih_state;
reg [23:0] local_data_count;
//output handler specific states
localparam WAIT_FOR_STATUS = 1;
localparam WRITE_TO_FIFO = 2;
localparam WRITE_DATA = 3;
localparam FINISHED = 4;
reg [3:0] oh_state;
reg [23:0] out_fifo_count;
wire [31:0] out_packet [0:4];
reg [3:0] out_packet_pos;
reg [7:0] out_packet_count;
reg [23:0] out_data_count;
reg [23:0] out_data_pos;
reg [3:0] oh_status;
wire in_fifo_has_data;
//modules
//asynchronous logic
assign in_fifo_has_data = (o_ingress_act && (in_data_count < i_ingress_size));
assign out_packet[0] = `ID_RESP;
assign out_packet[1] = i_out_status;
assign out_packet[2] = i_out_data_count + 1;
assign out_packet[3] = i_out_address;
assign out_packet[4] = i_out_data;
assign o_ih_reset = 0;
//synchronous logic
//state machine to assemble 32 bit words from the incomming 8 bit words
//Assembler
//state machine to read data from the in FIFO and send it to the master
//dissassembler
always @ (posedge clk ) begin
//Deassert Strobes
o_ingress_stb <= 0;
o_ih_ready <= 0;
if (rst) begin
ih_state <= IDLE;
o_in_command <= 0;
o_in_address <= 0;
o_in_data <= 0;
o_in_data_count <= 0;
local_data_count <= 0;
o_ingress_act <= 0;
in_data_count <= 0;
o_ing_fin <= 0;
end
else begin
//Look for available Ping Pong FIFO
if (i_ingress_rdy && !o_ingress_act) begin
in_data_count <= 0;
o_ingress_act <= 1;
end
case (ih_state)
IDLE: begin
o_ing_fin <= 0;
if (i_ing_en) begin
ih_state <= WAIT_FOR_START;
end
end
WAIT_FOR_START: begin
if (in_fifo_has_data) begin
o_ingress_stb <= 1;
in_data_count <= in_data_count + 1;
ih_state <= READ_ID;
id <= i_ingress_data;
end
end
READ_ID: begin
if (id == `ID_DWORD) begin
ih_state <= READ_COMMAND;
o_ingress_stb <= 1;
end
else begin
ih_state <= WAIT_FOR_START;
end
end
READ_COMMAND: begin
if (in_fifo_has_data) begin
in_data_count <= in_data_count + 1;
o_ingress_stb <= 1;
end
if (o_ingress_stb) begin
o_in_command <= i_ingress_data;
ih_state <= READ_DATA_COUNT;
end
end
READ_DATA_COUNT: begin
if (in_fifo_has_data) begin
in_data_count <= in_data_count + 1;
o_ingress_stb <= 1;
end
if (o_ingress_stb) begin
o_in_data_count <= i_ingress_data;
ih_state <= READ_ADDRESS;
end
end
READ_ADDRESS: begin
if (in_fifo_has_data) begin
local_data_count <= 0;
in_data_count <= in_data_count + 1;
o_ingress_stb <= 1;
end
if (o_ingress_stb) begin
o_in_address <= i_ingress_data;
o_ingress_stb <= 0;
ih_state <= PROCESS_COMMAND;
end
end
PROCESS_COMMAND: begin
if (o_in_command[3:0] == `COMMAND_PING) begin
$display("Reading PING command");
ih_state <= NOTIFY_MASTER;
end
else if (o_in_command[3:0] == `COMMAND_RESET) begin
$display("Reading RESET command");
ih_state <= IDLE;
end
else if (o_in_command[3:0] == `COMMAND_READ) begin
$display("Reading READ command");
ih_state <= NOTIFY_MASTER;
end
else if (o_in_command[3:0] == `COMMAND_WRITE) begin
$display("Reading WRITE command");
ih_state <= WAIT_FOR_DATA;
end
else begin
$display("Reading OTHER command (Not supported right now)");
ih_state <= FLUSH_FIFO;
end
end
WAIT_FOR_DATA: begin
if (!o_ih_ready && i_master_ready) begin
if (in_fifo_has_data) begin
o_in_data <= i_ingress_data;
if(local_data_count < o_in_data_count) begin
local_data_count <= local_data_count + 1;
o_ingress_stb <= 1;
in_data_count <= in_data_count + 1;
end
//$display ("Go to Notify Master!");
ih_state <= NOTIFY_MASTER;
o_ih_ready <= 1;
end
else if (o_ingress_act)begin
o_ingress_act <= 0;
end
end
end
NOTIFY_MASTER: begin
//$display("In Notify Master!");
if (i_master_ready) begin
o_ih_ready <= 1;
if ((o_in_command[3:0] == `COMMAND_WRITE) && (local_data_count < o_in_data_count)) begin
ih_state <= WAIT_FOR_DATA;
end
else begin
ih_state <= FLUSH_FIFO;
end
end
end
FLUSH_FIFO: begin
o_ing_fin <= 1;
if (in_fifo_has_data) begin
o_ingress_stb <= 1;
in_data_count <= in_data_count + 1;
end
else begin
o_ingress_act <= 0;
ih_state <= WAIT_FOR_START;
end
end
default: begin
ih_state <= IDLE;
end
endcase
end
end
integer i;
//state machine to read data from the master and send it to the out FIFO
always @ (posedge clk ) begin
o_egress_stb <= 0;
o_oh_ready <= 0;
if (rst) begin
//Output handler
oh_state <= IDLE;
//Output FIFO
out_fifo_count <= 0;
o_egress_act <= 0;
o_egress_data <= 0;
out_packet_count <= 0;
oh_status <= 0;
out_packet_pos <= 0;
out_data_count <= 0;
out_data_pos <= 0;
o_egr_fin <= 0;
end
else begin
//Get an Output FIFO
if ((i_egress_rdy > 0) && (o_egress_act == 0)) begin
out_fifo_count <= 0;
if (i_egress_rdy[0]) begin
o_egress_act[0] <= 1;
end
else begin
o_egress_act[1] <= 1;
end
end
case (oh_state)
IDLE: begin
//Wait for status
//It is strange to have this fall through state right now but later I might find a reason to NOT
// Leave this state
o_egr_fin <= 0;
if (i_egr_en) begin
oh_state <= WAIT_FOR_STATUS;
end
end
WAIT_FOR_STATUS: begin
if (o_egress_act > 0) begin
o_oh_ready <= 1;
if (i_oh_en) begin
out_data_count <= i_out_data_count[23:0] + 1;
out_data_pos <= 1; //Account for the first piece of data sent out with the first packet
out_packet_pos <= 0;
o_oh_ready <= 0;
if ( (i_out_status[3:0] == `READ_RESP) ||
(i_out_status[3:0] == `PERIPH_INTERRUPT)) begin
$display ("Standard Response!");
out_packet_count <= `STANDARD_RESPONSE;
oh_state <= WRITE_TO_FIFO;
end
else begin
$display ("No Response");
out_packet_count <= 0;
//oh_state <= IDLE;
end
end
end
if (i_egress_size == 0) begin
o_oh_ready <= 0;
o_egress_act <= 0;
end
end
WRITE_TO_FIFO: begin
if ((o_egress_act > 0) && (out_fifo_count < i_egress_size)) begin
if (out_packet_pos < out_packet_count) begin
o_egress_data <= out_packet[out_packet_pos];
out_packet_pos <= out_packet_pos + 1;
out_fifo_count <= out_fifo_count + 1;
o_egress_stb <= 1;
end
else begin
//were done sending the initial packet, check to see if there is more data to send
//release this FIFO because the output FIFO is starving
if (out_data_pos < out_data_count) begin
oh_state <= WRITE_DATA;
end
else begin
o_egress_act <= 0;
oh_state <= FINISHED;
end
end
end
else begin
o_egress_act <= 0;
end
end
WRITE_DATA: begin
if (o_egress_act > 0) begin
if (out_fifo_count < i_egress_size) begin
o_oh_ready <= 1;
if (i_oh_en && o_oh_ready) begin
o_oh_ready <= 0;
o_egress_data <= i_out_data;
out_fifo_count <= out_fifo_count + 1;
o_egress_stb <= 1;
out_data_pos <= out_data_pos + 1;
if ((out_fifo_count + 1) < i_egress_size) begin
o_oh_ready <= 0;
end
end
end
else begin
o_egress_act <= 0;
end
end
if (out_data_pos >= out_data_count) begin
oh_state <= FINISHED;
o_egress_act <= 0;
end
end
FINISHED: begin
o_egr_fin <= 1;
if (!i_egr_en) begin
o_egr_fin <= 0;
oh_state <= IDLE;
end
end
default: begin
//Should not have gotten here
o_egress_act <= 0;
oh_state <= IDLE;
end
endcase
end
end
endmodule
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : mem_bilo.v
// Author : Yufeng Bai
// Created : 2015-04-27
// Description : Memory Buf Block Input, Line Output
//
//-------------------------------------------------------------------
//
// Modified : 2014-08-18 by HLL
// Description : db supported
// Modified : 2015-09-19 by HLL
// Description : load_db_chroma & store_db_chroma provided in the order of uvuvuv...
//
//-------------------------------------------------------------------
`include "enc_defines.v"
module mem_bilo_db (
clk ,
rst_n ,
wen_i ,
wsel_i ,
w4x4_x_i ,
w4x4_y_i ,
wdata_i ,
ren_i ,
raddr_i ,
rdata_o
);
// ********************************************
//
// Parameter DECLARATION
//
// ********************************************
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input clk ; //clock
input rst_n ; //reset signal
input wen_i ; //
input [1:0] wsel_i ; //
input [3:0] w4x4_x_i ; //
input [4:0] w4x4_y_i ; //
input [`PIXEL_WIDTH*16-1:0] wdata_i ; //
input ren_i ; //
input [7:0] raddr_i ; //
output [`PIXEL_WIDTH*32-1:0] rdata_o ; //
// ********************************************
//
// Signals DECLARATION
//
// ********************************************
// R/W Data & Address
wire [`PIXEL_WIDTH*4-1:0] w_4x4_l0 ,
w_4x4_l1 ,
w_4x4_l2 ,
w_4x4_l3 ;
reg [1:0] b0_waddr_l, b0_raddr_l,
b1_waddr_l, b1_raddr_l,
b2_waddr_l, b2_raddr_l,
b3_waddr_l, b3_raddr_l;
reg [5:0] waddr_h;
wire extra_line;
wire [7:0] b0_waddr, b0_raddr,
b1_waddr, b1_raddr,
b2_waddr, b2_raddr,
b3_waddr, b3_raddr;
reg [`PIXEL_WIDTH*8-1:0] b0_wdata,
b1_wdata,
b2_wdata,
b3_wdata;
reg [1:0] raddr_r;
wire [`PIXEL_WIDTH*8-1:0] b0_rdata,
b2_rdata,
b1_rdata,
b3_rdata;
reg [`PIXEL_WIDTH*32-1:0] b_rdata;
// R/W Control
wire [1:0] b0_wen,
b1_wen,
b2_wen,
b3_wen;
wire b0_ren,
b1_ren,
b2_ren,
b3_ren;
// ********************************************
//
// Logic DECLARATION
//
// ********************************************
// --------------------------------------------
// Memory Banks
//---------------------------------------------
//-------------- MEM Write ----------------//
assign b0_wen = wen_i ? ( (!wsel_i[1]) ? ({~w4x4_x_i[0], w4x4_x_i[0]}) : ({~wsel_i[0], wsel_i[0]}) ) : 2'b00;
assign b1_wen = wen_i ? ( (!wsel_i[1]) ? ({~w4x4_x_i[0], w4x4_x_i[0]}) : ({~wsel_i[0], wsel_i[0]}) ) : 2'b00;
assign b2_wen = wen_i ? ( (!wsel_i[1]) ? ({~w4x4_x_i[0], w4x4_x_i[0]}) : ({~wsel_i[0], wsel_i[0]}) ) : 2'b00;
assign b3_wen = wen_i ? ( (!wsel_i[1]) ? ({~w4x4_x_i[0], w4x4_x_i[0]}) : ({~wsel_i[0], wsel_i[0]}) ) : 2'b00;
assign w_4x4_l0 = wdata_i[`PIXEL_WIDTH*16-1:`PIXEL_WIDTH*12];
assign w_4x4_l1 = wdata_i[`PIXEL_WIDTH*12-1:`PIXEL_WIDTH*8];
assign w_4x4_l2 = wdata_i[`PIXEL_WIDTH*8 -1:`PIXEL_WIDTH*4];
assign w_4x4_l3 = wdata_i[`PIXEL_WIDTH*4 -1:`PIXEL_WIDTH*0];
always @(*) begin
if( !wsel_i[1] )
case( w4x4_x_i[2:1] )
2'd0: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l0, w_4x4_l0, w_4x4_l1, w_4x4_l1, w_4x4_l2, w_4x4_l2, w_4x4_l3, w_4x4_l3 };
2'd1: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l2, w_4x4_l2, w_4x4_l3, w_4x4_l3, w_4x4_l0, w_4x4_l0, w_4x4_l1, w_4x4_l1 };
2'd2: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l3, w_4x4_l3, w_4x4_l0, w_4x4_l0, w_4x4_l1, w_4x4_l1, w_4x4_l2, w_4x4_l2 };
2'd3: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l1, w_4x4_l1, w_4x4_l2, w_4x4_l2, w_4x4_l3, w_4x4_l3, w_4x4_l0, w_4x4_l0 };
endcase
else begin
case( w4x4_x_i[1:0] )
2'd0: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l0, w_4x4_l0, w_4x4_l1, w_4x4_l1, w_4x4_l2, w_4x4_l2, w_4x4_l3, w_4x4_l3 };
2'd1: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l2, w_4x4_l2, w_4x4_l3, w_4x4_l3, w_4x4_l0, w_4x4_l0, w_4x4_l1, w_4x4_l1 };
2'd2: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l3, w_4x4_l3, w_4x4_l0, w_4x4_l0, w_4x4_l1, w_4x4_l1, w_4x4_l2, w_4x4_l2 };
2'd3: {b0_wdata, b1_wdata, b2_wdata, b3_wdata} = { w_4x4_l1, w_4x4_l1, w_4x4_l2, w_4x4_l2, w_4x4_l3, w_4x4_l3, w_4x4_l0, w_4x4_l0 };
endcase
end
end
always @(*) begin
if( !wsel_i[1] )
case( w4x4_x_i[2:1] )
2'd0 : begin b0_waddr_l=2'd0; b1_waddr_l=2'd1; b2_waddr_l=2'd2; b3_waddr_l=2'd3; end
2'd1 : begin b0_waddr_l=2'd2; b1_waddr_l=2'd3; b2_waddr_l=2'd0; b3_waddr_l=2'd1; end
2'd2 : begin b0_waddr_l=2'd3; b1_waddr_l=2'd0; b2_waddr_l=2'd1; b3_waddr_l=2'd2; end
2'd3 : begin b0_waddr_l=2'd1; b1_waddr_l=2'd2; b2_waddr_l=2'd3; b3_waddr_l=2'd0; end
endcase
else begin
case( w4x4_x_i[1:0] )
2'd0 : begin b0_waddr_l=2'd0; b1_waddr_l=2'd1; b2_waddr_l=2'd2; b3_waddr_l=2'd3; end
2'd1 : begin b0_waddr_l=2'd2; b1_waddr_l=2'd3; b2_waddr_l=2'd0; b3_waddr_l=2'd1; end
2'd2 : begin b0_waddr_l=2'd3; b1_waddr_l=2'd0; b2_waddr_l=2'd1; b3_waddr_l=2'd2; end
2'd3 : begin b0_waddr_l=2'd1; b1_waddr_l=2'd2; b2_waddr_l=2'd3; b3_waddr_l=2'd0; end
endcase
end
end
assign extra_line = (~wsel_i[1] & w4x4_y_i[4]) | (wsel_i[1] & w4x4_y_i[3]); // top y | top u,v
always @(*) begin
case( {extra_line, wsel_i[1]} )
2'b00: waddr_h = { 1'b0, w4x4_y_i[3], w4x4_x_i[3] ,w4x4_y_i[2:0] }; // cur y
2'b01: waddr_h = { 1'b1, 1'b0 , w4x4_y_i[2:0] ,w4x4_x_i[2] }; // cur u,v
2'b10: waddr_h = { 1'b1, 1'b1 , 1'b0 ,{2'b00,w4x4_x_i[3]} }; // top y
2'b11: waddr_h = { 1'b1, 1'b1 , 1'b0 ,{2'b01,w4x4_x_i[2]} }; // top u,v
endcase
end
assign b0_waddr = {waddr_h, b0_waddr_l};
assign b1_waddr = {waddr_h, b1_waddr_l};
assign b2_waddr = {waddr_h, b2_waddr_l};
assign b3_waddr = {waddr_h, b3_waddr_l};
/*
<--- 64 pixel ---> <- 32p -> <- 32p ->
----------------- --------- ---------
| luma-A | luma-B | | U-C | | V-D |
----------------- -------- ---------
| | | | | | |
| luma0 | luma1 | | U | | V |
| | | | | | |
|-----------------| -------- --------
| | |
| luma2 | luma3 |
| | |
-----------------
mem arraged as below:
-------- _
| | /|\
| luma0 | |
| | |
-------- |
| | |
| luma1 | |
| | |
-------- |
| | |
| luma2 | |
| | |
--------
| | |
| luma3 | |
| | |
-------- 208
| | |
| | |
| | |
-- UV -- |
| | |
| | |
| | |
-------- |
| luma-A | |
-------- |
| luma-B | |
-------- |
| | |
-- UV -- |
| | |
-------- \|/
*/
//-------------- MEM Read ----------------//
assign b0_ren = ren_i;
assign b1_ren = ren_i;
assign b2_ren = ren_i;
assign b3_ren = ren_i;
// address generater
assign b0_raddr = raddr_i;
assign b1_raddr = raddr_i;
assign b2_raddr = raddr_i;
assign b3_raddr = raddr_i;
// data alignment
always@(posedge clk or negedge rst_n) begin
if (!rst_n) begin
raddr_r <= 'b0;
end
else begin
raddr_r <= raddr_i[1:0];
end
end
always @(*) begin
case (raddr_r)
2'd0: b_rdata = {b0_rdata, b2_rdata, b1_rdata, b3_rdata};
2'd1: b_rdata = {b1_rdata, b3_rdata, b2_rdata, b0_rdata};
2'd2: b_rdata = {b2_rdata, b0_rdata, b3_rdata, b1_rdata};
2'd3: b_rdata = {b3_rdata, b1_rdata, b0_rdata, b2_rdata};
endcase
end
assign rdata_o = b_rdata;
// MEM Modules
buf_ram_2p_64x208 buf_pre_0(
.clk ( clk ),
.a_we ( b0_wen ),
.a_addr ( b0_waddr ),
.a_data_i ( b0_wdata ),
.b_re ( b0_ren ),
.b_addr ( b0_raddr ),
.b_data_o ( b0_rdata )
);
buf_ram_2p_64x208 buf_pre_1(
.clk ( clk ),
.a_we ( b1_wen ),
.a_addr ( b1_waddr ),
.a_data_i ( b1_wdata ),
.b_re ( b1_ren ),
.b_addr ( b1_raddr ),
.b_data_o ( b1_rdata )
);
buf_ram_2p_64x208 buf_pre_2(
.clk ( clk ),
.a_we ( b2_wen ),
.a_addr ( b2_waddr ),
.a_data_i ( b2_wdata ),
.b_re ( b2_ren ),
.b_addr ( b2_raddr ),
.b_data_o ( b2_rdata )
);
buf_ram_2p_64x208 buf_pre_3(
.clk ( clk ),
.a_we ( b3_wen ),
.a_addr ( b3_waddr ),
.a_data_i ( b3_wdata ),
.b_re ( b3_ren ),
.b_addr ( b3_raddr ),
.b_data_o ( b3_rdata )
);
endmodule
|
`define STATE_INIT 2'b00
`define STATE_W_FETCH 2'b01
`define STATE_END 2'b10
module FETCH(
input clk,
input f_enable,
input write_mode,
input [31:0] addr,
input [31:0] data_i,
input [1:0] thread,
output reg [31:0] data_o,
output reg ack,
input W_CLK,
input W_ACK,
input [31:0] W_DATA_I,
output reg [31:0] W_DATA_O,
output reg [31:0] W_ADDR,
output reg W_WRITE
);
reg read_from_bus;
reg [1:0] state; // 0: 0 -- read input | 1 -- fetch; 1: 00
reg [1:0] w_state;
reg w_buff;
reg w_ack_local;
wire [4:0] reg_select;
reg [31:0] registers[0:32];
assign reg_select = {thread, addr[2:0]};
initial
begin
state <= `STATE_INIT;
w_state <= 2'b00;
data_o <= 0;
ack <= 0;
end
always @(posedge clk)
begin
case (state)
`STATE_INIT:
if (f_enable)
begin
if (addr[31:28] == 4'hF)
begin
if (write_mode)
registers[reg_select] <= data_i;
else
data_o <= registers[reg_select];
ack <= 1;
end
else
begin
read_from_bus <= 1;
state <= `STATE_W_FETCH;
end
end
else
ack <= 0;
`STATE_W_FETCH: // load from WBUS
begin
if (w_ack_local)
begin
data_o <= w_buff;
ack <= 1;
state <= `STATE_INIT;
end
end
endcase
end
always @(posedge W_CLK)
begin
if (read_from_bus)
case (w_state)
2'b00:
begin
W_ADDR <= addr;
w_state <= 2'b01;
W_DATA_O <= data_i;
W_WRITE <= write_mode;
end
2'b01:
if (W_ACK) // wait W_BUS ack
begin
w_buff <= W_DATA_I;
w_ack_local <= 1;
w_state <= 2'b10;
end
2'b10:
begin
w_ack_local <= 0;
w_state <= 2'b00;
W_ADDR <= 32'hz;
end
default:
w_ack_local <= 0;
endcase
end
endmodule
|
/* amiga_clk.v */
/* 2012, [email protected] */
module amiga_clk (
input wire rst, // asynhronous reset input
input wire clk_in, // input clock ( 27.000000MHz)
output wire clk_114, // SDRAM ctrl clock (114.750000MHz)
output wire clk_sdram, // SDRAM output clock (114.750000MHz, -146.25 deg)
output wire clk_28, // 28MHz output clock ( 28.375160MHz)
output wire clk_7, // 7MHz output clock ( 7.171875MHz)
output wire clk7_en, // 7MHz output clock enable (on 28MHz clock domain)
output wire clk7n_en, // 7MHz negedge output clock enable (on 28MHz clock domain)
output wire c1, // clk28m clock domain signal synchronous with clk signal
output wire c3, // clk28m clock domain signal synchronous with clk signal delayed by 90 degrees
output wire cck, // colour clock output (3.54 MHz)
output wire [ 10-1:0] eclk, // 0.709379 MHz clock enable output (clk domain pulse)
output wire locked // PLL locked output
);
//// simulation clocks ////
`ifdef SOC_SIM
reg clk_114_r;
reg clk_28_r;
reg clk_sdram_r;
reg pll_locked_r;
initial begin
pll_locked_r = 1'b0;
wait (!rst);
#50;
pll_locked_r = 1'b1;
end
initial begin
clk_114_r = 1'b1;
#1;
wait (pll_locked_r);
#3;
forever #4.357 clk_114_r = ~clk_114_r;
end
initial begin
clk_28_r = 1'b1;
#1;
wait (pll_locked_r);
#5;
forever #17.428 clk_28_r = ~clk_28_r;
end
initial begin
clk_sdram_r = 1'b1;
#1;
wait (pll_locked_r);
#3;
forever #4.357 clk_sdram_r = ~clk_sdram_r;
end
assign clk_114 = clk_114_r;
assign clk_28 = clk_28_r;
assign clk_sdram = clk_sdram_r;
assign locked = pll_locked_r;
`else
//// hardware clocks ////
// device-specific PLL/DCM
`ifdef MINIMIG_ALTERA
amiga_clk_altera amiga_clk_i (
.areset (rst ),
.inclk0 (clk_in ),
.c0 (clk_sdram),
.c1 (clk_114 ),
.c2 (clk_28 ),
.locked (locked )
);
`endif
`ifdef MINIMIG_XILINX
amiga_clk_xilinx amiga_clk_i (
.areset (rst ),
.inclk0 (clk_in ),
.c0 (clk_114 ),
.c1 (clk_28 ),
.c2 (clk_sdram),
.locked (locked )
);
`endif
`endif
//// generated clocks ////
// 7MHz
reg [2-1:0] clk7_cnt = 2'b10;
reg clk7_en_reg = 1'b1;
reg clk7n_en_reg = 1'b1;
always @ (posedge clk_28, negedge locked) begin
if (!locked) begin
clk7_cnt <= 2'b10;
clk7_en_reg <= #1 1'b1;
clk7n_en_reg <= #1 1'b1;
end else begin
clk7_cnt <= clk7_cnt + 2'b01;
clk7_en_reg <= #1 (clk7_cnt == 2'b00);
clk7n_en_reg <= #1 (clk7_cnt == 2'b10);
end
end
assign clk_7 = clk7_cnt[1];
assign clk7_en = clk7_en_reg;
assign clk7n_en = clk7n_en_reg;
// amiga clocks & clock enables
// __ __ __ __ __
// clk_28 __/ \__/ \__/ \__/ \__/
// ___________ __
// clk_7 __/ \___________/
// ___________ __
// c1 __/ \___________/ <- clk28m domain
// ___________
// c3 ________/ \________ <- clk28m domain
//
// clk_28 clock domain signal synchronous with clk signal delayed by 90 degrees
reg c3_r = 1'b0;
always @(posedge clk_28) begin
c3_r <= clk_7;
end
assign c3 = c3_r;
// clk28m clock domain signal synchronous with clk signal
reg c1_r = 1'b0;
always @(posedge clk_28) begin
c1_r <= ~c3_r;
end
assign c1 = c1_r;
// counter used to generate e clock enable
reg [3:0] e_cnt = 4'b0000;
always @(posedge clk_7) begin
if (e_cnt[3] && e_cnt[0])
e_cnt[3:0] <= 4'd0;
else
e_cnt[3:0] <= e_cnt[3:0] + 4'd1;
end
// CCK clock output
assign cck = ~e_cnt[0];
// 0.709379 MHz clock enable output (clk domain pulse)
assign eclk[0] = ~e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & ~e_cnt[0]; // e_cnt == 0
assign eclk[1] = ~e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & e_cnt[0]; // e_cnt == 1
assign eclk[2] = ~e_cnt[3] & ~e_cnt[2] & e_cnt[1] & ~e_cnt[0]; // e_cnt == 2
assign eclk[3] = ~e_cnt[3] & ~e_cnt[2] & e_cnt[1] & e_cnt[0]; // e_cnt == 3
assign eclk[4] = ~e_cnt[3] & e_cnt[2] & ~e_cnt[1] & ~e_cnt[0]; // e_cnt == 4
assign eclk[5] = ~e_cnt[3] & e_cnt[2] & ~e_cnt[1] & e_cnt[0]; // e_cnt == 5
assign eclk[6] = ~e_cnt[3] & e_cnt[2] & e_cnt[1] & ~e_cnt[0]; // e_cnt == 6
assign eclk[7] = ~e_cnt[3] & e_cnt[2] & e_cnt[1] & e_cnt[0]; // e_cnt == 7
assign eclk[8] = e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & ~e_cnt[0]; // e_cnt == 8
assign eclk[9] = e_cnt[3] & ~e_cnt[2] & ~e_cnt[1] & e_cnt[0]; // e_cnt == 9
endmodule
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 6
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_zynq_snick_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "gcd_zynq_snick_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TR\
ANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDT\
H=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_GP1=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=TRUE,C_FCLK_CLK1_BUF=FALSE,C_FCLK_CLK2_BUF=FALSE,C_FCLK_CLK3_BUF=FALSE,C_PACKAGE_NAME=clg400,C_GP0_EN_MODIFIA\
BLE_TXN=1,C_GP1_EN_MODIFIABLE_TXN=1}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_zynq_snick_processing_system7_0_0 (
GPIO_I,
GPIO_O,
GPIO_T,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_CLK1,
FCLK_CLK2,
FCLK_CLK3,
FCLK_RESET0_N,
FCLK_RESET1_N,
FCLK_RESET2_N,
FCLK_RESET3_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *)
input wire [63 : 0] GPIO_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *)
output wire [63 : 0] GPIO_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *)
output wire [63 : 0] GPIO_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 49999947, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0, NUM_READ\
_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *)
input wire [0 : 0] IRQ_F2P;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 99999893, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK1" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK" *)
output wire FCLK_CLK1;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK2, FREQ_HZ 153845993, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK2" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK2 CLK" *)
output wire FCLK_CLK2;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK3, FREQ_HZ 199999786, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK3" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *)
output wire FCLK_CLK3;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET1_N, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET1_N RST" *)
output wire FCLK_RESET1_N;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET2_N, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET2_N RST" *)
output wire FCLK_RESET2_N;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET3_N, POLARITY ACTIVE_LOW" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET3_N RST" *)
output wire FCLK_RESET3_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *)
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("TRUE"),
.C_FCLK_CLK1_BUF("FALSE"),
.C_FCLK_CLK2_BUF("FALSE"),
.C_FCLK_CLK3_BUF("FALSE"),
.C_PACKAGE_NAME("clg400"),
.C_GP0_EN_MODIFIABLE_TXN(1),
.C_GP1_EN_MODIFIABLE_TXN(1)
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(),
.ENET0_PTP_DELAY_REQ_TX(),
.ENET0_PTP_PDELAY_REQ_RX(),
.ENET0_PTP_PDELAY_REQ_TX(),
.ENET0_PTP_PDELAY_RESP_RX(),
.ENET0_PTP_PDELAY_RESP_TX(),
.ENET0_PTP_SYNC_FRAME_RX(),
.ENET0_PTP_SYNC_FRAME_TX(),
.ENET0_SOF_RX(),
.ENET0_SOF_TX(),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_T(GPIO_T),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(),
.TTC0_WAVE1_OUT(),
.TTC0_WAVE2_OUT(),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(),
.USB0_VBUS_PWRSELECT(),
.USB0_VBUS_PWRFAULT(1'B0),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(IRQ_F2P),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(FCLK_CLK2),
.FCLK_CLK3(FCLK_CLK3),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(FCLK_RESET1_N),
.FCLK_RESET2_N(FCLK_RESET2_N),
.FCLK_RESET3_N(FCLK_RESET3_N),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__XOR2_BLACKBOX_V
`define SKY130_FD_SC_HD__XOR2_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__XOR2_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR2B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR2B_PP_SYMBOL_V
/**
* nor2b: 2-input NOR, first input inverted.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor2b (
//# {{data|Data Signals}}
input A ,
input B_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR2B_PP_SYMBOL_V
|
module ID (
input rst,
input[`InstAddrWidth-1:0] pc_plus4,
input[`InstDataWidth-1:0] inst,
output[`RegAddrWidth-1:0] reg1_addr,
output[`RegAddrWidth-1:0] reg2_addr,
output WriteReg,
output MemOrAlu,
output WriteMem,
output ReadMem,
output[`ALUTypeWidth-1:0] AluType,
output[`ALUOpWidth-1:0] AluOp,
output AluSrcA,
output AluSrcB,
output RegDes,
output ImmSigned,
output is_jal,
output[`RegAddrWidth-1:0] rt,
output[`RegAddrWidth-1:0] rd,
output[`RegDataWidth-1:0] imm_signed,
output[`RegDataWidth-1:0] imm_unsigned,
output[`RegDataWidth-1:0] shamt,
output[`OpcodeWidth-1:0] opcode
);
decoder decode(
.rst(rst),
.inst(inst),
.WriteReg(WriteReg),
.MemOrAlu(MemOrAlu),
.WriteMem(WriteMem),
.ReadMem(ReadMem),
.AluType(AluType),
.AluOp(AluOp),
.AluSrcA(AluSrcA),
.AluSrcB(AluSrcB),
.RegDes(RegDes),
.ImmSigned(ImmSigned),
.is_jal(is_jal)
);
assign reg1_addr = inst[`RsBus];
assign reg2_addr = inst[`RtBus];
assign rt = inst[`RtBus];
assign rd = inst[`RdBus];
assign imm_signed = {{16{inst[15]}}, inst[`ImmBus]};
assign imm_unsigned = {16'b0, inst[`ImmBus]};
assign shamt = {27'b0, inst[`SaBus]};
assign opcode = inst[`OpcodeBus];
endmodule |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_jp_sstl_oebscan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_jp_sstl_oebscan(bsr_si ,update_dr ,in ,bsr_hiz_l ,
test_mode_oe ,mode_ctl ,shift_dr ,clock_dr ,out_type ,bsr_so ,out
);
output bsr_so ;
output out ;
input bsr_si ;
input update_dr ;
input in ;
input bsr_hiz_l ;
input test_mode_oe ;
input mode_ctl ;
input shift_dr ;
input clock_dr ;
input out_type ;
wire upd_hiz ;
wire net32 ;
wire net40 ;
wire net44 ;
wire net51 ;
wire net53 ;
wire net55 ;
wire net60 ;
bw_u1_muxi21_2x bs_mux (
.z (net44 ),
.d0 (in ),
.d1 (upd_hiz ),
.s (net32 ) );
bw_u1_inv_1x se_inv (
.z (net53 ),
.a (test_mode_oe ) );
bw_u1_nand3_1x hiz_nand (
.z (net55 ),
.a (net51 ),
.b (bsr_hiz_l ),
.c (net53 ) );
bw_u1_inv_2x ctl_inv2x (
.z (net32 ),
.a (net60 ) );
bw_io_jp_bs_baseblk bs_baseblk (
.upd_q (net51 ),
.bsr_si (bsr_si ),
.update_dr (update_dr ),
.clock_dr (clock_dr ),
.shift_dr (shift_dr ),
.bsr_so (bsr_so ),
.in (in ) );
bw_u1_nand2_1x hiz_se_nand (
.z (upd_hiz ),
.a (net55 ),
.b (net40 ) );
bw_u1_nand2_1x se_nand (
.z (net40 ),
.a (test_mode_oe ),
.b (out_type ) );
bw_u1_inv_5x out_inv5x (
.z (out ),
.a (net44 ) );
bw_u1_nor2_1x ctl_nor1x (
.z (net60 ),
.a (mode_ctl ),
.b (test_mode_oe ) );
endmodule
|
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This block takes the length and forms the appropriate burst count.
Whenever one of the short access enables are asserted this block
will post a burst of one. Posting a burst of one isn't necessary
but it will make it possible to add byte enable support to the
read master at a later date.
Revision History:
1.0 First version
1.1 Added generate logic around the internal burst count logic to prevent zero
replication simulation bug. In the case of a non-bursting master the
burst count is just hardcoded to 1.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module read_burst_control (
address,
length,
maximum_burst_count,
short_first_access_enable,
short_last_access_enable,
short_first_and_last_access_enable,
burst_count
);
parameter BURST_ENABLE = 1; // set to 0 to hardwire the address and write signals straight out
parameter BURST_COUNT_WIDTH = 3;
parameter WORD_SIZE_LOG2 = 2; // log2(DATA WIDTH/8)
parameter ADDRESS_WIDTH = 32;
parameter LENGTH_WIDTH = 32;
parameter BURST_WRAPPING_SUPPORT = 1; // set 1 for on, set 0 for off. This parameter can't be enabled when hte master supports programmable burst.
localparam BURST_OFFSET_WIDTH = (BURST_COUNT_WIDTH == 1)? 1: (BURST_COUNT_WIDTH-1);
input [ADDRESS_WIDTH-1:0] address;
input [LENGTH_WIDTH-1:0] length;
input [BURST_COUNT_WIDTH-1:0] maximum_burst_count; // will be either a hardcoded input or programmable
input short_first_access_enable;
input short_last_access_enable;
input short_first_and_last_access_enable;
output wire [BURST_COUNT_WIDTH-1:0] burst_count;
wire [BURST_COUNT_WIDTH-1:0] posted_burst; // when the burst statemachine is used this will be the burst count posted to the fabric
reg [BURST_COUNT_WIDTH-1:0] internal_burst_count; // muxes posted_burst, posted_burst_d1, and '1' since we need to be able to post bursts of '1' for short accesses
wire burst_of_one_enable; // asserted when partial word accesses are occuring
wire short_burst_enable;
wire [BURST_OFFSET_WIDTH-1:0] burst_offset;
assign burst_offset = address[BURST_OFFSET_WIDTH+WORD_SIZE_LOG2-1:WORD_SIZE_LOG2];
// for unaligned or partial transfers we must use a burst length of 1 so that
assign burst_of_one_enable = (short_first_access_enable == 1) | (short_last_access_enable == 1) | (short_first_and_last_access_enable == 1) | // when performing partial accesses use a burst length of 1
((BURST_WRAPPING_SUPPORT == 1) & (burst_offset != 0)); // when the burst boundary offset is non-zero then the master isn't in burst alignment yet as so a burst of 1 needs to be posted
assign short_burst_enable = ((length >> WORD_SIZE_LOG2) < maximum_burst_count);
generate
if ((BURST_ENABLE == 1) & (BURST_COUNT_WIDTH > 1))
begin
always @ (maximum_burst_count or length or short_burst_enable or burst_of_one_enable)
begin
case ({short_burst_enable, burst_of_one_enable})
2'b00 : internal_burst_count = maximum_burst_count;
2'b01 : internal_burst_count = 1; // this is when the master starts unaligned
2'b10 : internal_burst_count = ((length >> WORD_SIZE_LOG2) & {(BURST_COUNT_WIDTH-1){1'b1}}); // this could be followed by a burst of 1 if there are a few bytes leftover
2'b11 : internal_burst_count = 1; // burst of 1 needs to win, this is when the master starts with very little data to transfer
endcase
end
assign burst_count = internal_burst_count;
end
else
begin
assign burst_count = 1; // this will be stubbed at the top level but will be used for the address and pending reads incrementing
end
endgenerate
endmodule
|
//
// Generated by Bluespec Compiler (build 0fccbb13)
//
//
// Ports:
// Name I/O size props
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1 reg
// valid O 1
// word_fst O 64
// word_snd O 5
// verbosity I 4
// CLK I 1 clock
// RST_N I 1 reset
// req_opcode I 7
// req_f7 I 7
// req_rm I 3
// req_rs2 I 5
// req_v1 I 64
// req_v2 I 64
// req_v3 I 64
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFBox_Core(verbosity,
CLK,
RST_N,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_opcode,
req_f7,
req_rm,
req_rs2,
req_v1,
req_v2,
req_v3,
EN_req,
valid,
word_fst,
word_snd);
input [3 : 0] verbosity;
input CLK;
input RST_N;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [6 : 0] req_opcode;
input [6 : 0] req_f7;
input [2 : 0] req_rm;
input [4 : 0] req_rs2;
input [63 : 0] req_v1;
input [63 : 0] req_v2;
input [63 : 0] req_v3;
input EN_req;
// value method valid
output valid;
// value method word_fst
output [63 : 0] word_fst;
// value method word_snd
output [4 : 0] word_snd;
// signals for module outputs
wire [63 : 0] word_fst;
wire [4 : 0] word_snd;
wire RDY_server_reset_request_put, RDY_server_reset_response_get, valid;
// inlined wires
wire [68 : 0] dw_result$wget;
wire dw_valid$wget, dw_valid$whas;
// register requestR
reg [214 : 0] requestR;
wire [214 : 0] requestR$D_IN;
wire requestR$EN;
// register resultR
reg [69 : 0] resultR;
reg [69 : 0] resultR$D_IN;
wire resultR$EN;
// register stateR
reg [1 : 0] stateR;
reg [1 : 0] stateR$D_IN;
wire stateR$EN;
// ports of submodule fpu
reg [201 : 0] fpu$server_core_request_put;
wire [69 : 0] fpu$server_core_response_get;
wire fpu$EN_server_core_request_put,
fpu$EN_server_core_response_get,
fpu$EN_server_reset_request_put,
fpu$EN_server_reset_response_get,
fpu$RDY_server_core_request_put,
fpu$RDY_server_core_response_get,
fpu$RDY_server_reset_request_put,
fpu$RDY_server_reset_response_get;
// ports of submodule frmFpuF
wire frmFpuF$CLR, frmFpuF$DEQ, frmFpuF$D_IN, frmFpuF$ENQ;
// ports of submodule resetReqsF
wire resetReqsF$CLR,
resetReqsF$DEQ,
resetReqsF$EMPTY_N,
resetReqsF$ENQ,
resetReqsF$FULL_N;
// ports of submodule resetRspsF
wire resetRspsF$CLR,
resetRspsF$DEQ,
resetRspsF$EMPTY_N,
resetRspsF$ENQ,
resetRspsF$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_doFADD_D,
CAN_FIRE_RL_doFADD_S,
CAN_FIRE_RL_doFCLASS_D,
CAN_FIRE_RL_doFCLASS_S,
CAN_FIRE_RL_doFCVT_D_L,
CAN_FIRE_RL_doFCVT_D_LU,
CAN_FIRE_RL_doFCVT_D_S,
CAN_FIRE_RL_doFCVT_D_W,
CAN_FIRE_RL_doFCVT_D_WU,
CAN_FIRE_RL_doFCVT_LU_D,
CAN_FIRE_RL_doFCVT_LU_S,
CAN_FIRE_RL_doFCVT_L_D,
CAN_FIRE_RL_doFCVT_L_S,
CAN_FIRE_RL_doFCVT_S_D,
CAN_FIRE_RL_doFCVT_S_L,
CAN_FIRE_RL_doFCVT_S_LU,
CAN_FIRE_RL_doFCVT_S_W,
CAN_FIRE_RL_doFCVT_S_WU,
CAN_FIRE_RL_doFCVT_WU_D,
CAN_FIRE_RL_doFCVT_WU_S,
CAN_FIRE_RL_doFCVT_W_D,
CAN_FIRE_RL_doFCVT_W_S,
CAN_FIRE_RL_doFDIV_D,
CAN_FIRE_RL_doFDIV_S,
CAN_FIRE_RL_doFEQ_D,
CAN_FIRE_RL_doFEQ_S,
CAN_FIRE_RL_doFLE_D,
CAN_FIRE_RL_doFLE_S,
CAN_FIRE_RL_doFLT_D,
CAN_FIRE_RL_doFLT_S,
CAN_FIRE_RL_doFMADD_D,
CAN_FIRE_RL_doFMADD_S,
CAN_FIRE_RL_doFMAX_D,
CAN_FIRE_RL_doFMAX_S,
CAN_FIRE_RL_doFMIN_D,
CAN_FIRE_RL_doFMIN_S,
CAN_FIRE_RL_doFMSUB_D,
CAN_FIRE_RL_doFMSUB_S,
CAN_FIRE_RL_doFMUL_D,
CAN_FIRE_RL_doFMUL_S,
CAN_FIRE_RL_doFMV_D_X,
CAN_FIRE_RL_doFMV_W_X,
CAN_FIRE_RL_doFMV_X_D,
CAN_FIRE_RL_doFMV_X_W,
CAN_FIRE_RL_doFNMADD_D,
CAN_FIRE_RL_doFNMADD_S,
CAN_FIRE_RL_doFNMSUB_D,
CAN_FIRE_RL_doFNMSUB_S,
CAN_FIRE_RL_doFSGNJN_D,
CAN_FIRE_RL_doFSGNJN_S,
CAN_FIRE_RL_doFSGNJX_D,
CAN_FIRE_RL_doFSGNJX_S,
CAN_FIRE_RL_doFSGNJ_D,
CAN_FIRE_RL_doFSGNJ_S,
CAN_FIRE_RL_doFSQRT_D,
CAN_FIRE_RL_doFSQRT_S,
CAN_FIRE_RL_doFSUB_D,
CAN_FIRE_RL_doFSUB_S,
CAN_FIRE_RL_rl_drive_fpu_result,
CAN_FIRE_RL_rl_get_fpu_result,
CAN_FIRE_RL_rl_reset_begin,
CAN_FIRE_RL_rl_reset_end,
CAN_FIRE_req,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
WILL_FIRE_RL_doFADD_D,
WILL_FIRE_RL_doFADD_S,
WILL_FIRE_RL_doFCLASS_D,
WILL_FIRE_RL_doFCLASS_S,
WILL_FIRE_RL_doFCVT_D_L,
WILL_FIRE_RL_doFCVT_D_LU,
WILL_FIRE_RL_doFCVT_D_S,
WILL_FIRE_RL_doFCVT_D_W,
WILL_FIRE_RL_doFCVT_D_WU,
WILL_FIRE_RL_doFCVT_LU_D,
WILL_FIRE_RL_doFCVT_LU_S,
WILL_FIRE_RL_doFCVT_L_D,
WILL_FIRE_RL_doFCVT_L_S,
WILL_FIRE_RL_doFCVT_S_D,
WILL_FIRE_RL_doFCVT_S_L,
WILL_FIRE_RL_doFCVT_S_LU,
WILL_FIRE_RL_doFCVT_S_W,
WILL_FIRE_RL_doFCVT_S_WU,
WILL_FIRE_RL_doFCVT_WU_D,
WILL_FIRE_RL_doFCVT_WU_S,
WILL_FIRE_RL_doFCVT_W_D,
WILL_FIRE_RL_doFCVT_W_S,
WILL_FIRE_RL_doFDIV_D,
WILL_FIRE_RL_doFDIV_S,
WILL_FIRE_RL_doFEQ_D,
WILL_FIRE_RL_doFEQ_S,
WILL_FIRE_RL_doFLE_D,
WILL_FIRE_RL_doFLE_S,
WILL_FIRE_RL_doFLT_D,
WILL_FIRE_RL_doFLT_S,
WILL_FIRE_RL_doFMADD_D,
WILL_FIRE_RL_doFMADD_S,
WILL_FIRE_RL_doFMAX_D,
WILL_FIRE_RL_doFMAX_S,
WILL_FIRE_RL_doFMIN_D,
WILL_FIRE_RL_doFMIN_S,
WILL_FIRE_RL_doFMSUB_D,
WILL_FIRE_RL_doFMSUB_S,
WILL_FIRE_RL_doFMUL_D,
WILL_FIRE_RL_doFMUL_S,
WILL_FIRE_RL_doFMV_D_X,
WILL_FIRE_RL_doFMV_W_X,
WILL_FIRE_RL_doFMV_X_D,
WILL_FIRE_RL_doFMV_X_W,
WILL_FIRE_RL_doFNMADD_D,
WILL_FIRE_RL_doFNMADD_S,
WILL_FIRE_RL_doFNMSUB_D,
WILL_FIRE_RL_doFNMSUB_S,
WILL_FIRE_RL_doFSGNJN_D,
WILL_FIRE_RL_doFSGNJN_S,
WILL_FIRE_RL_doFSGNJX_D,
WILL_FIRE_RL_doFSGNJX_S,
WILL_FIRE_RL_doFSGNJ_D,
WILL_FIRE_RL_doFSGNJ_S,
WILL_FIRE_RL_doFSQRT_D,
WILL_FIRE_RL_doFSQRT_S,
WILL_FIRE_RL_doFSUB_D,
WILL_FIRE_RL_doFSUB_S,
WILL_FIRE_RL_rl_drive_fpu_result,
WILL_FIRE_RL_rl_get_fpu_result,
WILL_FIRE_RL_rl_reset_begin,
WILL_FIRE_RL_rl_reset_end,
WILL_FIRE_req,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get;
// inputs to muxes for submodule ports
wire [214 : 0] MUX_requestR$write_1__VAL_2;
wire [201 : 0] MUX_fpu$server_core_request_put_1__VAL_1,
MUX_fpu$server_core_request_put_1__VAL_10,
MUX_fpu$server_core_request_put_1__VAL_11,
MUX_fpu$server_core_request_put_1__VAL_12,
MUX_fpu$server_core_request_put_1__VAL_13,
MUX_fpu$server_core_request_put_1__VAL_14,
MUX_fpu$server_core_request_put_1__VAL_15,
MUX_fpu$server_core_request_put_1__VAL_16,
MUX_fpu$server_core_request_put_1__VAL_17,
MUX_fpu$server_core_request_put_1__VAL_18,
MUX_fpu$server_core_request_put_1__VAL_2,
MUX_fpu$server_core_request_put_1__VAL_3,
MUX_fpu$server_core_request_put_1__VAL_4,
MUX_fpu$server_core_request_put_1__VAL_5,
MUX_fpu$server_core_request_put_1__VAL_6,
MUX_fpu$server_core_request_put_1__VAL_7,
MUX_fpu$server_core_request_put_1__VAL_8,
MUX_fpu$server_core_request_put_1__VAL_9;
wire [69 : 0] MUX_resultR$write_1__VAL_10,
MUX_resultR$write_1__VAL_11,
MUX_resultR$write_1__VAL_12,
MUX_resultR$write_1__VAL_13,
MUX_resultR$write_1__VAL_14,
MUX_resultR$write_1__VAL_15,
MUX_resultR$write_1__VAL_16,
MUX_resultR$write_1__VAL_17,
MUX_resultR$write_1__VAL_18,
MUX_resultR$write_1__VAL_19,
MUX_resultR$write_1__VAL_20,
MUX_resultR$write_1__VAL_21,
MUX_resultR$write_1__VAL_22,
MUX_resultR$write_1__VAL_23,
MUX_resultR$write_1__VAL_24,
MUX_resultR$write_1__VAL_25,
MUX_resultR$write_1__VAL_26,
MUX_resultR$write_1__VAL_27,
MUX_resultR$write_1__VAL_28,
MUX_resultR$write_1__VAL_29,
MUX_resultR$write_1__VAL_3,
MUX_resultR$write_1__VAL_30,
MUX_resultR$write_1__VAL_31,
MUX_resultR$write_1__VAL_32,
MUX_resultR$write_1__VAL_33,
MUX_resultR$write_1__VAL_34,
MUX_resultR$write_1__VAL_35,
MUX_resultR$write_1__VAL_36,
MUX_resultR$write_1__VAL_37,
MUX_resultR$write_1__VAL_38,
MUX_resultR$write_1__VAL_39,
MUX_resultR$write_1__VAL_4,
MUX_resultR$write_1__VAL_40,
MUX_resultR$write_1__VAL_41,
MUX_resultR$write_1__VAL_42,
MUX_resultR$write_1__VAL_43,
MUX_resultR$write_1__VAL_6,
MUX_resultR$write_1__VAL_7,
MUX_resultR$write_1__VAL_8,
MUX_resultR$write_1__VAL_9;
wire [68 : 0] MUX_dw_result$wset_1__VAL_1;
wire MUX_dw_result$wset_1__SEL_1;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h1224;
reg [31 : 0] v__h1777;
reg [31 : 0] v__h1966;
reg [31 : 0] v__h2168;
reg [31 : 0] v__h2418;
reg [31 : 0] v__h2593;
reg [31 : 0] v__h2768;
reg [31 : 0] v__h2950;
reg [31 : 0] v__h3139;
reg [31 : 0] v__h3337;
reg [31 : 0] v__h3520;
reg [31 : 0] v__h3693;
reg [31 : 0] v__h3882;
reg [31 : 0] v__h16640;
reg [31 : 0] v__h28741;
reg [31 : 0] v__h35941;
reg [31 : 0] v__h42829;
reg [31 : 0] v__h44905;
reg [31 : 0] v__h45689;
reg [31 : 0] v__h47303;
reg [31 : 0] v__h48090;
reg [31 : 0] v__h50764;
reg [31 : 0] v__h53335;
reg [31 : 0] v__h53495;
reg [31 : 0] v__h53671;
reg [31 : 0] v__h55194;
reg [31 : 0] v__h56303;
reg [31 : 0] v__h57430;
reg [31 : 0] v__h57911;
reg [31 : 0] v__h58124;
reg [31 : 0] v__h58311;
reg [31 : 0] v__h58491;
reg [31 : 0] v__h58676;
reg [31 : 0] v__h58848;
reg [31 : 0] v__h59020;
reg [31 : 0] v__h59199;
reg [31 : 0] v__h59386;
reg [31 : 0] v__h59583;
reg [31 : 0] v__h59744;
reg [31 : 0] v__h59907;
reg [31 : 0] v__h60075;
reg [31 : 0] v__h71274;
reg [31 : 0] v__h82193;
reg [31 : 0] v__h83807;
reg [31 : 0] v__h84594;
reg [31 : 0] v__h97596;
reg [31 : 0] v__h110093;
reg [31 : 0] v__h112152;
reg [31 : 0] v__h112936;
reg [31 : 0] v__h167802;
reg [31 : 0] v__h213792;
reg [31 : 0] v__h218378;
reg [31 : 0] v__h222864;
reg [31 : 0] v__h225599;
reg [31 : 0] v__h227516;
reg [31 : 0] v__h229453;
reg [31 : 0] v__h229605;
reg [31 : 0] v__h229762;
reg [31 : 0] v__h1218;
reg [31 : 0] v__h1771;
reg [31 : 0] v__h1960;
reg [31 : 0] v__h2162;
reg [31 : 0] v__h2412;
reg [31 : 0] v__h2587;
reg [31 : 0] v__h2762;
reg [31 : 0] v__h2944;
reg [31 : 0] v__h3133;
reg [31 : 0] v__h3331;
reg [31 : 0] v__h3514;
reg [31 : 0] v__h3687;
reg [31 : 0] v__h3876;
reg [31 : 0] v__h16634;
reg [31 : 0] v__h28735;
reg [31 : 0] v__h35935;
reg [31 : 0] v__h42823;
reg [31 : 0] v__h44899;
reg [31 : 0] v__h45683;
reg [31 : 0] v__h47297;
reg [31 : 0] v__h48084;
reg [31 : 0] v__h50758;
reg [31 : 0] v__h53329;
reg [31 : 0] v__h53489;
reg [31 : 0] v__h53665;
reg [31 : 0] v__h55188;
reg [31 : 0] v__h56297;
reg [31 : 0] v__h57424;
reg [31 : 0] v__h57905;
reg [31 : 0] v__h58118;
reg [31 : 0] v__h58305;
reg [31 : 0] v__h58485;
reg [31 : 0] v__h58670;
reg [31 : 0] v__h58842;
reg [31 : 0] v__h59014;
reg [31 : 0] v__h59193;
reg [31 : 0] v__h59380;
reg [31 : 0] v__h59577;
reg [31 : 0] v__h59738;
reg [31 : 0] v__h59901;
reg [31 : 0] v__h60069;
reg [31 : 0] v__h71268;
reg [31 : 0] v__h82187;
reg [31 : 0] v__h83801;
reg [31 : 0] v__h84588;
reg [31 : 0] v__h97590;
reg [31 : 0] v__h110087;
reg [31 : 0] v__h112146;
reg [31 : 0] v__h112930;
reg [31 : 0] v__h167796;
reg [31 : 0] v__h213786;
reg [31 : 0] v__h218372;
reg [31 : 0] v__h222858;
reg [31 : 0] v__h225593;
reg [31 : 0] v__h227510;
reg [31 : 0] v__h229447;
reg [31 : 0] v__h229599;
reg [31 : 0] v__h229756;
// synopsys translate_on
// remaining internal signals
reg [51 : 0] CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78,
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79,
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175,
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176,
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93,
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94,
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113,
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114,
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111,
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112,
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91,
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92,
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107,
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108,
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103,
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104,
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171,
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172,
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173,
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174,
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82,
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83,
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146;
reg [22 : 0] CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64,
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65,
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62,
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63,
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135,
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136,
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137,
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138,
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51,
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52,
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139,
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140,
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53,
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54,
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21,
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22,
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23,
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24,
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141,
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142,
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39,
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40,
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37,
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38,
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606;
reg [10 : 0] CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76,
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77,
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163,
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164,
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86,
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87,
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32,
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33,
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109,
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110,
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89,
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90,
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106,
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105,
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101,
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102,
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159,
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160,
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161,
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162,
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81,
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80,
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067;
reg [7 : 0] CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57,
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58,
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60,
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61,
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127,
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128,
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129,
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130,
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44,
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43,
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131,
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132,
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49,
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50,
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18,
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17,
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19,
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20,
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133,
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134,
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29,
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30,
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35,
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36,
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59,
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565;
reg [2 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61;
reg CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74,
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169,
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143,
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145,
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45,
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147,
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47,
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13,
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15,
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149,
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97,
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99,
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165,
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167,
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75,
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98;
wire [117 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224,
b__h110422,
x__h111322,
x__h112661;
wire [88 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757,
b__h43158,
x__h44058,
x__h45414;
wire [85 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731,
b__h82525,
x__h83201,
x__h84319;
wire [64 : 0] _1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
_theResult_____2__h110357,
_theResult_____2__h43093,
out1___1__h111073,
out1___1__h43809;
wire [63 : 0] IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1816,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1876,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2111,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2112,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2113,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2128,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2129,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2130,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2206,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2207,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1878,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3283,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3337,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5333,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5348,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5426,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1812,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1814,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1874,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3279,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3281,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3335,
requestR_BITS_127_TO_64__q3,
requestR_BITS_191_TO_128__q1,
requestR_BITS_63_TO_0__q8,
res___1__h229866,
res___1__h230304,
res___1__h230314,
res___1__h230333,
res___1__h57534,
res___1__h57770,
res___1__h57780,
res___1__h57799,
res__h166745,
res__h212818,
res__h217300,
res__h221886,
res__h224628,
res__h227363,
res__h229280,
res__h230349,
res__h230541,
res__h3932,
res__h48859,
res__h49096,
res__h54627,
res__h56150,
res__h57259,
res__h57815,
sfd___3__h15005,
sfd___3__h27286,
sfd__h3990,
x__h110179,
x__h112240,
x__h113022,
x__h16727,
x__h167888,
x__h213882,
x__h218468,
x__h222950,
x__h225685,
x__h227602,
x__h229846,
x__h230460,
x__h28828,
x__h3429,
x__h36028,
x__h3605,
x__h3778,
x__h42915,
x__h44993,
x__h45775,
x__h47391,
x__h48180,
x__h50854,
x__h53419,
x__h53579,
x__h53757,
x__h55280,
x__h56389,
x__h57514,
x__h59668,
x__h59829,
x__h59992,
x__h60162,
x__h71361,
x__h82279,
x__h83895,
x__h84681,
x__h97683;
wire [56 : 0] IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_ETC__q117,
IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_reques_ETC__q154,
IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR__ETC__q122,
IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q151,
IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q157,
IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q119,
IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q125,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908,
_0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691,
_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858,
_theResult____h126028,
_theResult____h146240,
_theResult____h191843,
_theResult___snd__h135401,
_theResult___snd__h135412,
_theResult___snd__h135414,
_theResult___snd__h135424,
_theResult___snd__h135430,
_theResult___snd__h135453,
_theResult___snd__h145260,
_theResult___snd__h145262,
_theResult___snd__h145269,
_theResult___snd__h145275,
_theResult___snd__h145298,
_theResult___snd__h155742,
_theResult___snd__h155753,
_theResult___snd__h155755,
_theResult___snd__h155765,
_theResult___snd__h155771,
_theResult___snd__h155794,
_theResult___snd__h165625,
_theResult___snd__h165639,
_theResult___snd__h165645,
_theResult___snd__h165663,
_theResult___snd__h190457,
_theResult___snd__h190459,
_theResult___snd__h190466,
_theResult___snd__h190472,
_theResult___snd__h190495,
_theResult___snd__h201345,
_theResult___snd__h201356,
_theResult___snd__h201358,
_theResult___snd__h201368,
_theResult___snd__h201374,
_theResult___snd__h201397,
_theResult___snd__h211344,
_theResult___snd__h211358,
_theResult___snd__h211364,
_theResult___snd__h211382,
b__h46021,
result__h146853,
result__h192456,
sfd__h117253,
sfdin__h135384,
sfdin__h155725,
sfdin__h201328,
x__h146948,
x__h192551,
x__h46697,
x__h47815;
wire [54 : 0] sfd___3__h69389, sfd___3__h80336, sfd__h60177, sfd__h71373;
wire [53 : 0] sfd__h108263,
sfd__h109005,
sfd__h190524,
sfd__h201426,
sfd__h211417,
sfd__h69416,
sfd__h70159,
sfd__h80363,
sfd__h81105,
sfd__h95738,
sfd__h96481,
value__h82527;
wire [51 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2496,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2680,
_theResult___fst_sfd__h108959,
_theResult___fst_sfd__h109714,
_theResult___fst_sfd__h109717,
_theResult___fst_sfd__h113549,
_theResult___fst_sfd__h174201,
_theResult___fst_sfd__h191260,
_theResult___fst_sfd__h191263,
_theResult___fst_sfd__h202162,
_theResult___fst_sfd__h202165,
_theResult___fst_sfd__h212177,
_theResult___fst_sfd__h212180,
_theResult___fst_sfd__h212189,
_theResult___fst_sfd__h212195,
_theResult___fst_sfd__h70113,
_theResult___fst_sfd__h70869,
_theResult___fst_sfd__h70872,
_theResult___fst_sfd__h81059,
_theResult___fst_sfd__h81814,
_theResult___fst_sfd__h81817,
_theResult___fst_sfd__h96435,
_theResult___fst_sfd__h97191,
_theResult___fst_sfd__h97194,
_theResult___sfd__h108863,
_theResult___sfd__h109618,
_theResult___sfd__h191162,
_theResult___sfd__h202064,
_theResult___sfd__h212079,
_theResult___sfd__h70016,
_theResult___sfd__h70772,
_theResult___sfd__h80963,
_theResult___sfd__h81718,
_theResult___sfd__h96338,
_theResult___sfd__h97094,
_theResult___snd_fst_sfd__h109720,
_theResult___snd_fst_sfd__h169840,
_theResult___snd_fst_sfd__h191266,
_theResult___snd_fst_sfd__h212183,
_theResult___snd_fst_sfd__h70875,
_theResult___snd_fst_sfd__h81820,
_theResult___snd_fst_sfd__h97197,
out___1_sfd__h167954,
out_sfd__h108866,
out_sfd__h109621,
out_sfd__h191165,
out_sfd__h202067,
out_sfd__h212082,
out_sfd__h70019,
out_sfd__h70775,
out_sfd__h80966,
out_sfd__h81721,
out_sfd__h96341,
out_sfd__h97097,
value__h113092;
wire [32 : 0] _theResult_____2__h45956,
_theResult_____2__h82460,
out1___1__h46448,
out1___1__h82952;
wire [31 : 0] IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1967,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2022,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2108,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2109,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2123,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2125,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2126,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2024,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2790,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2851,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1963,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1965,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d2020,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2786,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2788,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2849,
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2106,
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2122,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
requestR_BITS_191_TO_128_BITS_31_TO_0__q2,
sfd___3__h34458,
sfd___3__h41374,
sfd__h28849,
x__h166751,
x__h28834,
x__h3436,
x__h3612,
x__h3785,
x__h3975,
x__h45778,
x__h47394,
x__h82282,
x__h83898;
wire [30 : 0] IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37;
wire [24 : 0] sfd__h135482,
sfd__h145327,
sfd__h15032,
sfd__h15575,
sfd__h155823,
sfd__h165698,
sfd__h27313,
sfd__h27852,
sfd__h34485,
sfd__h35025,
sfd__h41401,
sfd__h41940,
value__h43160;
wire [23 : 0] NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308;
wire [22 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260,
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338,
_theResult___fst_sfd__h126011,
_theResult___fst_sfd__h136015,
_theResult___fst_sfd__h136018,
_theResult___fst_sfd__h145860,
_theResult___fst_sfd__h145863,
_theResult___fst_sfd__h15529,
_theResult___fst_sfd__h156356,
_theResult___fst_sfd__h156359,
_theResult___fst_sfd__h16082,
_theResult___fst_sfd__h16085,
_theResult___fst_sfd__h166255,
_theResult___fst_sfd__h166258,
_theResult___fst_sfd__h166267,
_theResult___fst_sfd__h166273,
_theResult___fst_sfd__h168212,
_theResult___fst_sfd__h27806,
_theResult___fst_sfd__h28358,
_theResult___fst_sfd__h28361,
_theResult___fst_sfd__h34979,
_theResult___fst_sfd__h35532,
_theResult___fst_sfd__h35535,
_theResult___fst_sfd__h41894,
_theResult___fst_sfd__h42446,
_theResult___fst_sfd__h42449,
_theResult___sfd__h135917,
_theResult___sfd__h145762,
_theResult___sfd__h15432,
_theResult___sfd__h156258,
_theResult___sfd__h15985,
_theResult___sfd__h166157,
_theResult___sfd__h27710,
_theResult___sfd__h28262,
_theResult___sfd__h34882,
_theResult___sfd__h35435,
_theResult___sfd__h41798,
_theResult___sfd__h42350,
_theResult___snd_fst_sfd__h117207,
_theResult___snd_fst_sfd__h145866,
_theResult___snd_fst_sfd__h16088,
_theResult___snd_fst_sfd__h166261,
_theResult___snd_fst_sfd__h28364,
_theResult___snd_fst_sfd__h35538,
_theResult___snd_fst_sfd__h42452,
out_sfd__h135920,
out_sfd__h145765,
out_sfd__h15435,
out_sfd__h156261,
out_sfd__h15988,
out_sfd__h166160,
out_sfd__h27713,
out_sfd__h28265,
out_sfd__h34885,
out_sfd__h35438,
out_sfd__h41801,
out_sfd__h42353,
sV1_sfd__h1473,
sV2_sfd__h1598,
value__h167957;
wire [19 : 0] NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993;
wire [11 : 0] IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420,
_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558,
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541,
_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068,
x__h108990,
x__h146981,
x__h192584,
x__h70144,
x__h81090,
x__h96466;
wire [10 : 0] IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992,
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061,
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2996,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156,
_theResult___exp__h108862,
_theResult___exp__h109617,
_theResult___exp__h191161,
_theResult___exp__h202063,
_theResult___exp__h212078,
_theResult___exp__h70015,
_theResult___exp__h70771,
_theResult___exp__h80962,
_theResult___exp__h81717,
_theResult___exp__h96337,
_theResult___exp__h97093,
_theResult___fst_exp__h108958,
_theResult___fst_exp__h109713,
_theResult___fst_exp__h109716,
_theResult___fst_exp__h174200,
_theResult___fst_exp__h190497,
_theResult___fst_exp__h190503,
_theResult___fst_exp__h190506,
_theResult___fst_exp__h191259,
_theResult___fst_exp__h191262,
_theResult___fst_exp__h201334,
_theResult___fst_exp__h201399,
_theResult___fst_exp__h201405,
_theResult___fst_exp__h201408,
_theResult___fst_exp__h202161,
_theResult___fst_exp__h202164,
_theResult___fst_exp__h211350,
_theResult___fst_exp__h211389,
_theResult___fst_exp__h211395,
_theResult___fst_exp__h211398,
_theResult___fst_exp__h212176,
_theResult___fst_exp__h212179,
_theResult___fst_exp__h212188,
_theResult___fst_exp__h212191,
_theResult___fst_exp__h70112,
_theResult___fst_exp__h70868,
_theResult___fst_exp__h70871,
_theResult___fst_exp__h81058,
_theResult___fst_exp__h81813,
_theResult___fst_exp__h81816,
_theResult___fst_exp__h96434,
_theResult___fst_exp__h97190,
_theResult___fst_exp__h97193,
_theResult___snd_fst_exp__h109719,
_theResult___snd_fst_exp__h109722,
_theResult___snd_fst_exp__h109725,
_theResult___snd_fst_exp__h191265,
_theResult___snd_fst_exp__h212182,
_theResult___snd_fst_exp__h70874,
_theResult___snd_fst_exp__h70877,
_theResult___snd_fst_exp__h70880,
_theResult___snd_fst_exp__h81819,
_theResult___snd_fst_exp__h81822,
_theResult___snd_fst_exp__h81825,
_theResult___snd_fst_exp__h97196,
_theResult___snd_fst_exp__h97199,
_theResult___snd_fst_exp__h97202,
din_inc___2_exp__h109755,
din_inc___2_exp__h212214,
din_inc___2_exp__h212244,
din_inc___2_exp__h212268,
din_inc___2_exp__h70914,
din_inc___2_exp__h81855,
din_inc___2_exp__h97236,
out_exp__h108865,
out_exp__h109620,
out_exp__h191164,
out_exp__h202066,
out_exp__h212081,
out_exp__h70018,
out_exp__h70774,
out_exp__h80965,
out_exp__h81720,
out_exp__h96340,
out_exp__h97096,
x__h167898;
wire [8 : 0] IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969,
x__h15560,
x__h27837,
x__h35010,
x__h41925;
wire [7 : 0] IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713,
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157,
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559,
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1439,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d571,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124,
_theResult___exp__h135916,
_theResult___exp__h145761,
_theResult___exp__h15431,
_theResult___exp__h156257,
_theResult___exp__h15984,
_theResult___exp__h166156,
_theResult___exp__h27709,
_theResult___exp__h28261,
_theResult___exp__h34881,
_theResult___exp__h35434,
_theResult___exp__h41797,
_theResult___exp__h42349,
_theResult___fst_exp__h126010,
_theResult___fst_exp__h135390,
_theResult___fst_exp__h135455,
_theResult___fst_exp__h135461,
_theResult___fst_exp__h135464,
_theResult___fst_exp__h136014,
_theResult___fst_exp__h136017,
_theResult___fst_exp__h145300,
_theResult___fst_exp__h145306,
_theResult___fst_exp__h145309,
_theResult___fst_exp__h145859,
_theResult___fst_exp__h145862,
_theResult___fst_exp__h15528,
_theResult___fst_exp__h155731,
_theResult___fst_exp__h155796,
_theResult___fst_exp__h155802,
_theResult___fst_exp__h155805,
_theResult___fst_exp__h156355,
_theResult___fst_exp__h156358,
_theResult___fst_exp__h16081,
_theResult___fst_exp__h16084,
_theResult___fst_exp__h165631,
_theResult___fst_exp__h165670,
_theResult___fst_exp__h165676,
_theResult___fst_exp__h165679,
_theResult___fst_exp__h166254,
_theResult___fst_exp__h166257,
_theResult___fst_exp__h166266,
_theResult___fst_exp__h166269,
_theResult___fst_exp__h27805,
_theResult___fst_exp__h28357,
_theResult___fst_exp__h28360,
_theResult___fst_exp__h34978,
_theResult___fst_exp__h35531,
_theResult___fst_exp__h35534,
_theResult___fst_exp__h41893,
_theResult___fst_exp__h42445,
_theResult___fst_exp__h42448,
_theResult___snd_fst_exp__h145865,
_theResult___snd_fst_exp__h16087,
_theResult___snd_fst_exp__h16090,
_theResult___snd_fst_exp__h16093,
_theResult___snd_fst_exp__h166260,
_theResult___snd_fst_exp__h28363,
_theResult___snd_fst_exp__h28366,
_theResult___snd_fst_exp__h28369,
_theResult___snd_fst_exp__h35537,
_theResult___snd_fst_exp__h35540,
_theResult___snd_fst_exp__h35543,
_theResult___snd_fst_exp__h42451,
_theResult___snd_fst_exp__h42454,
_theResult___snd_fst_exp__h42457,
din_inc___2_exp__h16127,
din_inc___2_exp__h166288,
din_inc___2_exp__h166312,
din_inc___2_exp__h166342,
din_inc___2_exp__h166366,
din_inc___2_exp__h28399,
din_inc___2_exp__h35577,
din_inc___2_exp__h42487,
out_exp__h135919,
out_exp__h145764,
out_exp__h15434,
out_exp__h156260,
out_exp__h15987,
out_exp__h166159,
out_exp__h27712,
out_exp__h28264,
out_exp__h34884,
out_exp__h35437,
out_exp__h41800,
out_exp__h42352,
sV1_exp__h1472,
sV2_exp__h1597,
x__h113032;
wire [6 : 0] IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966,
requestR_BITS_206_TO_200__q177;
wire [5 : 0] IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654,
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933,
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776;
wire [4 : 0] _0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425,
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203,
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408,
fcsr__h3933,
x__h109855,
x__h111943,
x__h112739,
x__h166866,
x__h212920,
x__h217430,
x__h227382,
x__h28503,
x__h35703,
x__h42591,
x__h44696,
x__h45492,
x__h47094,
x__h47893,
x__h50220,
x__h56169,
x__h71036,
x__h81955,
x__h83598,
x__h84397,
x__h97358;
wire [1 : 0] IF_sfd___30336_BIT_1_THEN_2_ELSE_0__q85,
IF_sfd___30336_BIT_2_THEN_2_ELSE_0__q84,
IF_sfd___31374_BIT_7_THEN_2_ELSE_0__q56,
IF_sfd___31374_BIT_8_THEN_2_ELSE_0__q55,
IF_sfd___34458_BIT_7_THEN_2_ELSE_0__q42,
IF_sfd___34458_BIT_8_THEN_2_ELSE_0__q41,
IF_sfd___35005_BIT_10_THEN_2_ELSE_0__q12,
IF_sfd___35005_BIT_11_THEN_2_ELSE_0__q11,
IF_sfd___35005_BIT_39_THEN_2_ELSE_0__q10,
IF_sfd___35005_BIT_40_THEN_2_ELSE_0__q9,
IF_sfd___37286_BIT_10_THEN_2_ELSE_0__q28,
IF_sfd___37286_BIT_11_THEN_2_ELSE_0__q27,
IF_sfd___37286_BIT_39_THEN_2_ELSE_0__q26,
IF_sfd___37286_BIT_40_THEN_2_ELSE_0__q25,
IF_sfd___39389_BIT_1_THEN_2_ELSE_0__q71,
IF_sfd___39389_BIT_2_THEN_2_ELSE_0__q70,
IF_sfdin01328_BIT_4_THEN_2_ELSE_0__q155,
IF_sfdin35384_BIT_33_THEN_2_ELSE_0__q118,
IF_sfdin55725_BIT_33_THEN_2_ELSE_0__q123,
IF_theResult___snd11344_BIT_4_THEN_2_ELSE_0__q158,
IF_theResult___snd45260_BIT_33_THEN_2_ELSE_0__q120,
IF_theResult___snd65625_BIT_33_THEN_2_ELSE_0__q126,
IF_theResult___snd90457_BIT_4_THEN_2_ELSE_0__q152,
IF_x11322_BIT_53_THEN_2_ELSE_0__q115,
IF_x12661_BIT_53_THEN_2_ELSE_0__q116,
IF_x3201_BIT_53_THEN_2_ELSE_0__q95,
IF_x4058_BIT_24_THEN_2_ELSE_0__q66,
IF_x4319_BIT_53_THEN_2_ELSE_0__q96,
IF_x5414_BIT_24_THEN_2_ELSE_0__q67,
IF_x6697_BIT_24_THEN_2_ELSE_0__q68,
IF_x7815_BIT_24_THEN_2_ELSE_0__q69,
guard__h108246,
guard__h108975,
guard__h110355,
guard__h111133,
guard__h112440,
guard__h126038,
guard__h136028,
guard__h146250,
guard__h15015,
guard__h15545,
guard__h156369,
guard__h181312,
guard__h191853,
guard__h202175,
guard__h27296,
guard__h27822,
guard__h34468,
guard__h34995,
guard__h41384,
guard__h41910,
guard__h43091,
guard__h43869,
guard__h45193,
guard__h45954,
guard__h46508,
guard__h47594,
guard__h69399,
guard__h70129,
guard__h80346,
guard__h81075,
guard__h82458,
guard__h83012,
guard__h84098,
guard__h95721,
guard__h96451;
wire IF_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_21_ETC___d4358,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1379,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1529,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2398,
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2513,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1718,
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d2697,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2937,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d3054,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d511,
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d693,
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1174,
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d3208,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5188,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5189,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5224,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5227,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5234,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5248,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5260,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5272,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1520,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1523,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1532,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1774,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1896,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1925,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2043,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2167,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2748,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3045,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3048,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3057,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3241,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4378,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4429,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4440,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4456,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4469,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4482,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4617,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5010,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d684,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d687,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d696,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1837,
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1983,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2812,
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3298,
IF_NOT_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_B_ETC___d2399,
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_ETC___d5169,
IF_NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2101,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5186,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5246,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5258,
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5270,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4376,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4454,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4467,
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4480,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1165,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1168,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1177,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1709,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1712,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1721,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2169,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2872,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3199,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3202,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3211,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3357,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5373,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936,
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252,
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310,
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4448,
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4476,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1826,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1975,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2104,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2166,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2172,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2192,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887,
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1059,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1666,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2801,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3156,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3290,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5374,
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5399,
NOT_verbosity_ULE_1_6___d27,
NOT_verbosity_ULE_2_01___d702,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685,
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852,
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853,
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656,
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935,
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100,
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615,
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008,
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778,
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4411,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4436,
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4463,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345,
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560,
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561,
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542,
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447,
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971,
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972,
guard__h146848,
guard__h192451;
// action method server_reset_request_put
assign RDY_server_reset_request_put = resetReqsF$FULL_N ;
assign CAN_FIRE_server_reset_request_put = resetReqsF$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get = resetRspsF$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get = resetRspsF$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas && dw_valid$wget ;
// value method word_fst
assign word_fst = dw_result$wget[68:5] ;
// value method word_snd
assign word_snd = dw_result$wget[4:0] ;
// submodule fpu
mkFPU fpu(.CLK(CLK),
.RST_N(RST_N),
.server_core_request_put(fpu$server_core_request_put),
.EN_server_core_request_put(fpu$EN_server_core_request_put),
.EN_server_core_response_get(fpu$EN_server_core_response_get),
.EN_server_reset_request_put(fpu$EN_server_reset_request_put),
.EN_server_reset_response_get(fpu$EN_server_reset_response_get),
.RDY_server_core_request_put(fpu$RDY_server_core_request_put),
.server_core_response_get(fpu$server_core_response_get),
.RDY_server_core_response_get(fpu$RDY_server_core_response_get),
.RDY_server_reset_request_put(fpu$RDY_server_reset_request_put),
.RDY_server_reset_response_get(fpu$RDY_server_reset_response_get));
// submodule frmFpuF
FIFO2 #(.width(32'd1), .guarded(1'd1)) frmFpuF(.RST(RST_N),
.CLK(CLK),
.D_IN(frmFpuF$D_IN),
.ENQ(frmFpuF$ENQ),
.DEQ(frmFpuF$DEQ),
.CLR(frmFpuF$CLR),
.D_OUT(),
.FULL_N(),
.EMPTY_N());
// submodule resetReqsF
FIFO20 #(.guarded(1'd1)) resetReqsF(.RST(RST_N),
.CLK(CLK),
.ENQ(resetReqsF$ENQ),
.DEQ(resetReqsF$DEQ),
.CLR(resetReqsF$CLR),
.FULL_N(resetReqsF$FULL_N),
.EMPTY_N(resetReqsF$EMPTY_N));
// submodule resetRspsF
FIFO20 #(.guarded(1'd1)) resetRspsF(.RST(RST_N),
.CLK(CLK),
.ENQ(resetRspsF$ENQ),
.DEQ(resetRspsF$DEQ),
.CLR(resetRspsF$CLR),
.FULL_N(resetRspsF$FULL_N),
.EMPTY_N(resetRspsF$EMPTY_N));
// rule RL_rl_reset_end
assign CAN_FIRE_RL_rl_reset_end =
fpu$RDY_server_reset_response_get && resetRspsF$FULL_N &&
stateR == 2'd0 ;
assign WILL_FIRE_RL_rl_reset_end = CAN_FIRE_RL_rl_reset_end ;
// rule RL_doFADD_S
assign CAN_FIRE_RL_doFADD_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0 ;
assign WILL_FIRE_RL_doFADD_S = CAN_FIRE_RL_doFADD_S ;
// rule RL_doFSUB_S
assign CAN_FIRE_RL_doFSUB_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h04 ;
assign WILL_FIRE_RL_doFSUB_S = CAN_FIRE_RL_doFSUB_S ;
// rule RL_doFMUL_S
assign CAN_FIRE_RL_doFMUL_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h08 ;
assign WILL_FIRE_RL_doFMUL_S = CAN_FIRE_RL_doFMUL_S ;
// rule RL_doFMADD_S
assign CAN_FIRE_RL_doFMADD_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFMADD_S = CAN_FIRE_RL_doFMADD_S ;
// rule RL_doFMSUB_S
assign CAN_FIRE_RL_doFMSUB_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFMSUB_S = CAN_FIRE_RL_doFMSUB_S ;
// rule RL_doFNMADD_S
assign CAN_FIRE_RL_doFNMADD_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFNMADD_S = CAN_FIRE_RL_doFNMADD_S ;
// rule RL_doFNMSUB_S
assign CAN_FIRE_RL_doFNMSUB_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd0 ;
assign WILL_FIRE_RL_doFNMSUB_S = CAN_FIRE_RL_doFNMSUB_S ;
// rule RL_doFDIV_S
assign CAN_FIRE_RL_doFDIV_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0C ;
assign WILL_FIRE_RL_doFDIV_S = CAN_FIRE_RL_doFDIV_S ;
// rule RL_doFSQRT_S
assign CAN_FIRE_RL_doFSQRT_S =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h2C ;
assign WILL_FIRE_RL_doFSQRT_S = CAN_FIRE_RL_doFSQRT_S ;
// rule RL_doFSGNJ_S
assign CAN_FIRE_RL_doFSGNJ_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFSGNJ_S = CAN_FIRE_RL_doFSGNJ_S ;
// rule RL_doFSGNJN_S
assign CAN_FIRE_RL_doFSGNJN_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFSGNJN_S = CAN_FIRE_RL_doFSGNJN_S ;
// rule RL_doFSGNJX_S
assign CAN_FIRE_RL_doFSGNJX_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h10 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_S = CAN_FIRE_RL_doFSGNJX_S ;
// rule RL_doFCVT_S_L
assign CAN_FIRE_RL_doFCVT_S_L =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_S_L = CAN_FIRE_RL_doFCVT_S_L ;
// rule RL_doFCVT_S_LU
assign CAN_FIRE_RL_doFCVT_S_LU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_S_LU = CAN_FIRE_RL_doFCVT_S_LU ;
// rule RL_doFCVT_S_W
assign CAN_FIRE_RL_doFCVT_S_W =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_S_W = CAN_FIRE_RL_doFCVT_S_W ;
// rule RL_doFCVT_S_WU
assign CAN_FIRE_RL_doFCVT_S_WU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h68 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_WU = CAN_FIRE_RL_doFCVT_S_WU ;
// rule RL_doFCVT_L_S
assign CAN_FIRE_RL_doFCVT_L_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_L_S = CAN_FIRE_RL_doFCVT_L_S ;
// rule RL_doFCVT_LU_S
assign CAN_FIRE_RL_doFCVT_LU_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_LU_S = CAN_FIRE_RL_doFCVT_LU_S ;
// rule RL_doFCVT_W_S
assign CAN_FIRE_RL_doFCVT_W_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_S = CAN_FIRE_RL_doFCVT_W_S ;
// rule RL_doFCVT_WU_S
assign CAN_FIRE_RL_doFCVT_WU_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h60 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_S = CAN_FIRE_RL_doFCVT_WU_S ;
// rule RL_doFMIN_S
assign CAN_FIRE_RL_doFMIN_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_S = CAN_FIRE_RL_doFMIN_S ;
// rule RL_doFMAX_S
assign CAN_FIRE_RL_doFMAX_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h14 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_S = CAN_FIRE_RL_doFMAX_S ;
// rule RL_doFMV_W_X
assign CAN_FIRE_RL_doFMV_W_X =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h78 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_W_X = CAN_FIRE_RL_doFMV_W_X ;
// rule RL_doFMV_X_W
assign CAN_FIRE_RL_doFMV_X_W =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_W = CAN_FIRE_RL_doFMV_X_W ;
// rule RL_doFEQ_S
assign CAN_FIRE_RL_doFEQ_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_S = CAN_FIRE_RL_doFEQ_S ;
// rule RL_doFLT_S
assign CAN_FIRE_RL_doFLT_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_S = CAN_FIRE_RL_doFLT_S ;
// rule RL_doFLE_S
assign CAN_FIRE_RL_doFLE_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h50 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_S = CAN_FIRE_RL_doFLE_S ;
// rule RL_doFCLASS_S
assign CAN_FIRE_RL_doFCLASS_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h70 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_S = CAN_FIRE_RL_doFCLASS_S ;
// rule RL_doFADD_D
assign CAN_FIRE_RL_doFADD_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h01 ;
assign WILL_FIRE_RL_doFADD_D = CAN_FIRE_RL_doFADD_D ;
// rule RL_doFSUB_D
assign CAN_FIRE_RL_doFSUB_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h05 ;
assign WILL_FIRE_RL_doFSUB_D = CAN_FIRE_RL_doFSUB_D ;
// rule RL_doFMUL_D
assign CAN_FIRE_RL_doFMUL_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h09 ;
assign WILL_FIRE_RL_doFMUL_D = CAN_FIRE_RL_doFMUL_D ;
// rule RL_doFMADD_D
assign CAN_FIRE_RL_doFMADD_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFMADD_D = CAN_FIRE_RL_doFMADD_D ;
// rule RL_doFMSUB_D
assign CAN_FIRE_RL_doFMSUB_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1000111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFMSUB_D = CAN_FIRE_RL_doFMSUB_D ;
// rule RL_doFNMADD_D
assign CAN_FIRE_RL_doFNMADD_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001111 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFNMADD_D = CAN_FIRE_RL_doFNMADD_D ;
// rule RL_doFNMSUB_D
assign CAN_FIRE_RL_doFNMSUB_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1001011 &&
requestR_BITS_206_TO_200__q177[1:0] == 2'd1 ;
assign WILL_FIRE_RL_doFNMSUB_D = CAN_FIRE_RL_doFNMSUB_D ;
// rule RL_doFDIV_D
assign CAN_FIRE_RL_doFDIV_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h0D ;
assign WILL_FIRE_RL_doFDIV_D = CAN_FIRE_RL_doFDIV_D ;
// rule RL_doFSQRT_D
assign CAN_FIRE_RL_doFSQRT_D =
fpu$RDY_server_core_request_put && requestR[214] &&
stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h2D ;
assign WILL_FIRE_RL_doFSQRT_D = CAN_FIRE_RL_doFSQRT_D ;
// rule RL_doFSGNJ_D
assign CAN_FIRE_RL_doFSGNJ_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFSGNJ_D = CAN_FIRE_RL_doFSGNJ_D ;
// rule RL_doFSGNJN_D
assign CAN_FIRE_RL_doFSGNJN_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFSGNJN_D = CAN_FIRE_RL_doFSGNJN_D ;
// rule RL_doFSGNJX_D
assign CAN_FIRE_RL_doFSGNJX_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h11 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFSGNJX_D = CAN_FIRE_RL_doFSGNJX_D ;
// rule RL_doFCVT_D_W
assign CAN_FIRE_RL_doFCVT_D_W =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_W = CAN_FIRE_RL_doFCVT_D_W ;
// rule RL_doFCVT_D_WU
assign CAN_FIRE_RL_doFCVT_D_WU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_D_WU = CAN_FIRE_RL_doFCVT_D_WU ;
// rule RL_doFCVT_W_D
assign CAN_FIRE_RL_doFCVT_W_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_W_D = CAN_FIRE_RL_doFCVT_W_D ;
// rule RL_doFCVT_WU_D
assign CAN_FIRE_RL_doFCVT_WU_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_WU_D = CAN_FIRE_RL_doFCVT_WU_D ;
// rule RL_doFCVT_D_L
assign CAN_FIRE_RL_doFCVT_D_L =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_D_L = CAN_FIRE_RL_doFCVT_D_L ;
// rule RL_doFCVT_D_LU
assign CAN_FIRE_RL_doFCVT_D_LU =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h69 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_D_LU = CAN_FIRE_RL_doFCVT_D_LU ;
// rule RL_doFCVT_L_D
assign CAN_FIRE_RL_doFCVT_L_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd2 ;
assign WILL_FIRE_RL_doFCVT_L_D = CAN_FIRE_RL_doFCVT_L_D ;
// rule RL_doFCVT_LU_D
assign CAN_FIRE_RL_doFCVT_LU_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h61 &&
requestR[199:195] == 5'd3 ;
assign WILL_FIRE_RL_doFCVT_LU_D = CAN_FIRE_RL_doFCVT_LU_D ;
// rule RL_doFCVT_S_D
assign CAN_FIRE_RL_doFCVT_S_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h20 &&
requestR[199:195] == 5'd1 ;
assign WILL_FIRE_RL_doFCVT_S_D = CAN_FIRE_RL_doFCVT_S_D ;
// rule RL_doFCVT_D_S
assign CAN_FIRE_RL_doFCVT_D_S =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h21 &&
requestR[199:195] == 5'd0 ;
assign WILL_FIRE_RL_doFCVT_D_S = CAN_FIRE_RL_doFCVT_D_S ;
// rule RL_doFMIN_D
assign CAN_FIRE_RL_doFMIN_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMIN_D = CAN_FIRE_RL_doFMIN_D ;
// rule RL_doFMAX_D
assign CAN_FIRE_RL_doFMAX_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h15 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFMAX_D = CAN_FIRE_RL_doFMAX_D ;
// rule RL_doFEQ_D
assign CAN_FIRE_RL_doFEQ_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h2 ;
assign WILL_FIRE_RL_doFEQ_D = CAN_FIRE_RL_doFEQ_D ;
// rule RL_doFLT_D
assign CAN_FIRE_RL_doFLT_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFLT_D = CAN_FIRE_RL_doFLT_D ;
// rule RL_doFLE_D
assign CAN_FIRE_RL_doFLE_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h51 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFLE_D = CAN_FIRE_RL_doFLE_D ;
// rule RL_doFMV_D_X
assign CAN_FIRE_RL_doFMV_D_X =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h79 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_D_X = CAN_FIRE_RL_doFMV_D_X ;
// rule RL_doFMV_X_D
assign CAN_FIRE_RL_doFMV_X_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h0 ;
assign WILL_FIRE_RL_doFMV_X_D = CAN_FIRE_RL_doFMV_X_D ;
// rule RL_doFCLASS_D
assign CAN_FIRE_RL_doFCLASS_D =
requestR[214] && stateR == 2'd1 &&
requestR[213:207] == 7'b1010011 &&
requestR[206:200] == 7'h71 &&
requestR[194:192] == 3'h1 ;
assign WILL_FIRE_RL_doFCLASS_D = CAN_FIRE_RL_doFCLASS_D ;
// rule RL_rl_get_fpu_result
assign CAN_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ;
assign WILL_FIRE_RL_rl_get_fpu_result = MUX_dw_result$wset_1__SEL_1 ;
// rule RL_rl_drive_fpu_result
assign CAN_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ;
assign WILL_FIRE_RL_rl_drive_fpu_result = stateR == 2'd3 ;
// rule RL_rl_reset_begin
assign CAN_FIRE_RL_rl_reset_begin =
fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ;
assign WILL_FIRE_RL_rl_reset_begin = CAN_FIRE_RL_rl_reset_begin ;
// inputs to muxes for submodule ports
assign MUX_dw_result$wset_1__SEL_1 =
fpu$RDY_server_core_response_get && stateR == 2'd2 ;
assign MUX_dw_result$wset_1__VAL_1 =
{ x__h230460, fpu$server_core_response_get[4:0] } ;
assign MUX_fpu$server_core_request_put_1__VAL_1 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd0 } ;
assign MUX_fpu$server_core_request_put_1__VAL_2 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd1 } ;
assign MUX_fpu$server_core_request_put_1__VAL_3 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd2 } ;
assign MUX_fpu$server_core_request_put_1__VAL_4 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd5 } ;
assign MUX_fpu$server_core_request_put_1__VAL_5 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd6 } ;
assign MUX_fpu$server_core_request_put_1__VAL_6 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd7 } ;
assign MUX_fpu$server_core_request_put_1__VAL_7 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
_1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd8 } ;
assign MUX_fpu$server_core_request_put_1__VAL_8 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
33'h1AAAAAAAA,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48,
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd3 } ;
assign MUX_fpu$server_core_request_put_1__VAL_9 =
{ 33'h1AAAAAAAA,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37,
130'h15555555555555554AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd4 } ;
assign MUX_fpu$server_core_request_put_1__VAL_10 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd0 } ;
assign MUX_fpu$server_core_request_put_1__VAL_11 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd1 } ;
assign MUX_fpu$server_core_request_put_1__VAL_12 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd2 } ;
assign MUX_fpu$server_core_request_put_1__VAL_13 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd5 } ;
assign MUX_fpu$server_core_request_put_1__VAL_14 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd6 } ;
assign MUX_fpu$server_core_request_put_1__VAL_15 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd7 } ;
assign MUX_fpu$server_core_request_put_1__VAL_16 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
1'd0,
requestR[63:0],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd8 } ;
assign MUX_fpu$server_core_request_put_1__VAL_17 =
{ 1'd0,
requestR[191:128],
1'd0,
requestR[127:64],
65'h0AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd3 } ;
assign MUX_fpu$server_core_request_put_1__VAL_18 =
{ 1'd0,
requestR[191:128],
130'h15555555555555554AAAAAAAAAAAAAAAA,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61,
4'd4 } ;
assign MUX_requestR$write_1__VAL_2 =
{ 1'd1,
req_opcode,
req_f7,
req_rs2,
req_rm,
req_v1,
req_v2,
req_v3 } ;
assign MUX_resultR$write_1__VAL_3 =
{ 1'd1, x__h230460, fpu$server_core_response_get[4:0] } ;
assign MUX_resultR$write_1__VAL_4 = { 1'd1, x__h229846, 5'd0 } ;
assign MUX_resultR$write_1__VAL_6 = { 1'd1, requestR[191:128], 5'd0 } ;
assign MUX_resultR$write_1__VAL_7 = { 1'd1, x__h227602, x__h227382 } ;
assign MUX_resultR$write_1__VAL_8 = { 1'd1, x__h225685, x__h227382 } ;
assign MUX_resultR$write_1__VAL_9 = { 1'd1, x__h222950, x__h217430 } ;
assign MUX_resultR$write_1__VAL_10 = { 1'd1, x__h218468, x__h217430 } ;
assign MUX_resultR$write_1__VAL_11 = { 1'd1, x__h213882, x__h217430 } ;
assign MUX_resultR$write_1__VAL_12 = { 1'd1, x__h167888, x__h212920 } ;
assign MUX_resultR$write_1__VAL_13 = { 1'd1, x__h113022, x__h166866 } ;
assign MUX_resultR$write_1__VAL_14 = { 1'd1, x__h112240, x__h112739 } ;
assign MUX_resultR$write_1__VAL_15 = { 1'd1, x__h110179, x__h111943 } ;
assign MUX_resultR$write_1__VAL_16 = { 1'd1, x__h97683, x__h109855 } ;
assign MUX_resultR$write_1__VAL_17 = { 1'd1, x__h84681, x__h97358 } ;
assign MUX_resultR$write_1__VAL_18 = { 1'd1, x__h83895, x__h84397 } ;
assign MUX_resultR$write_1__VAL_19 = { 1'd1, x__h82279, x__h83598 } ;
assign MUX_resultR$write_1__VAL_20 = { 1'd1, x__h71361, x__h81955 } ;
assign MUX_resultR$write_1__VAL_21 = { 1'd1, x__h60162, x__h71036 } ;
assign MUX_resultR$write_1__VAL_22 = { 1'd1, x__h59992, 5'd0 } ;
assign MUX_resultR$write_1__VAL_23 = { 1'd1, x__h59829, 5'd0 } ;
assign MUX_resultR$write_1__VAL_24 = { 1'd1, x__h59668, 5'd0 } ;
assign MUX_resultR$write_1__VAL_25 = { 1'd1, x__h57514, 5'd0 } ;
assign MUX_resultR$write_1__VAL_26 = { 1'd1, x__h56389, x__h56169 } ;
assign MUX_resultR$write_1__VAL_27 = { 1'd1, x__h55280, x__h56169 } ;
assign MUX_resultR$write_1__VAL_28 = { 1'd1, x__h53757, x__h50220 } ;
assign MUX_resultR$write_1__VAL_29 = { 1'd1, x__h53579, 5'd0 } ;
assign MUX_resultR$write_1__VAL_30 = { 1'd1, x__h53419, 5'd0 } ;
assign MUX_resultR$write_1__VAL_31 = { 1'd1, x__h50854, x__h50220 } ;
assign MUX_resultR$write_1__VAL_32 = { 1'd1, x__h48180, x__h50220 } ;
assign MUX_resultR$write_1__VAL_33 = { 1'd1, x__h47391, x__h47893 } ;
assign MUX_resultR$write_1__VAL_34 = { 1'd1, x__h45775, x__h47094 } ;
assign MUX_resultR$write_1__VAL_35 = { 1'd1, x__h44993, x__h45492 } ;
assign MUX_resultR$write_1__VAL_36 = { 1'd1, x__h42915, x__h44696 } ;
assign MUX_resultR$write_1__VAL_37 = { 1'd1, x__h36028, x__h42591 } ;
assign MUX_resultR$write_1__VAL_38 = { 1'd1, x__h28828, x__h35703 } ;
assign MUX_resultR$write_1__VAL_39 = { 1'd1, x__h16727, x__h28503 } ;
assign MUX_resultR$write_1__VAL_40 = { 1'd1, res__h3932, fcsr__h3933 } ;
assign MUX_resultR$write_1__VAL_41 = { 1'd1, x__h3778, 5'd0 } ;
assign MUX_resultR$write_1__VAL_42 = { 1'd1, x__h3605, 5'd0 } ;
assign MUX_resultR$write_1__VAL_43 = { 1'd1, x__h3429, 5'd0 } ;
// inlined wires
assign dw_valid$wget = !WILL_FIRE_RL_rl_drive_fpu_result || resultR[69] ;
assign dw_valid$whas =
WILL_FIRE_RL_rl_drive_fpu_result ||
WILL_FIRE_RL_rl_get_fpu_result ;
assign dw_result$wget =
WILL_FIRE_RL_rl_get_fpu_result ?
MUX_dw_result$wset_1__VAL_1 :
resultR[68:0] ;
// register requestR
assign requestR$D_IN =
WILL_FIRE_RL_rl_reset_begin ?
215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA :
MUX_requestR$write_1__VAL_2 ;
assign requestR$EN = WILL_FIRE_RL_rl_reset_begin || EN_req ;
// register resultR
always@(WILL_FIRE_RL_rl_reset_begin or
EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
MUX_resultR$write_1__VAL_3 or
WILL_FIRE_RL_doFCLASS_D or
MUX_resultR$write_1__VAL_4 or
WILL_FIRE_RL_doFMV_X_D or
MUX_resultR$write_1__VAL_6 or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
MUX_resultR$write_1__VAL_7 or
WILL_FIRE_RL_doFLT_D or
MUX_resultR$write_1__VAL_8 or
WILL_FIRE_RL_doFEQ_D or
MUX_resultR$write_1__VAL_9 or
WILL_FIRE_RL_doFMAX_D or
MUX_resultR$write_1__VAL_10 or
WILL_FIRE_RL_doFMIN_D or
MUX_resultR$write_1__VAL_11 or
WILL_FIRE_RL_doFCVT_D_S or
MUX_resultR$write_1__VAL_12 or
WILL_FIRE_RL_doFCVT_S_D or
MUX_resultR$write_1__VAL_13 or
WILL_FIRE_RL_doFCVT_LU_D or
MUX_resultR$write_1__VAL_14 or
WILL_FIRE_RL_doFCVT_L_D or
MUX_resultR$write_1__VAL_15 or
WILL_FIRE_RL_doFCVT_D_LU or
MUX_resultR$write_1__VAL_16 or
WILL_FIRE_RL_doFCVT_D_L or
MUX_resultR$write_1__VAL_17 or
WILL_FIRE_RL_doFCVT_WU_D or
MUX_resultR$write_1__VAL_18 or
WILL_FIRE_RL_doFCVT_W_D or
MUX_resultR$write_1__VAL_19 or
WILL_FIRE_RL_doFCVT_D_WU or
MUX_resultR$write_1__VAL_20 or
WILL_FIRE_RL_doFCVT_D_W or
MUX_resultR$write_1__VAL_21 or
WILL_FIRE_RL_doFSGNJX_D or
MUX_resultR$write_1__VAL_22 or
WILL_FIRE_RL_doFSGNJN_D or
MUX_resultR$write_1__VAL_23 or
WILL_FIRE_RL_doFSGNJ_D or
MUX_resultR$write_1__VAL_24 or
WILL_FIRE_RL_doFCLASS_S or
MUX_resultR$write_1__VAL_25 or
WILL_FIRE_RL_doFLE_S or
MUX_resultR$write_1__VAL_26 or
WILL_FIRE_RL_doFLT_S or
MUX_resultR$write_1__VAL_27 or
WILL_FIRE_RL_doFEQ_S or
MUX_resultR$write_1__VAL_28 or
WILL_FIRE_RL_doFMV_X_W or
MUX_resultR$write_1__VAL_29 or
WILL_FIRE_RL_doFMV_W_X or
MUX_resultR$write_1__VAL_30 or
WILL_FIRE_RL_doFMAX_S or
MUX_resultR$write_1__VAL_31 or
WILL_FIRE_RL_doFMIN_S or
MUX_resultR$write_1__VAL_32 or
WILL_FIRE_RL_doFCVT_WU_S or
MUX_resultR$write_1__VAL_33 or
WILL_FIRE_RL_doFCVT_W_S or
MUX_resultR$write_1__VAL_34 or
WILL_FIRE_RL_doFCVT_LU_S or
MUX_resultR$write_1__VAL_35 or
WILL_FIRE_RL_doFCVT_L_S or
MUX_resultR$write_1__VAL_36 or
WILL_FIRE_RL_doFCVT_S_WU or
MUX_resultR$write_1__VAL_37 or
WILL_FIRE_RL_doFCVT_S_W or
MUX_resultR$write_1__VAL_38 or
WILL_FIRE_RL_doFCVT_S_LU or
MUX_resultR$write_1__VAL_39 or
WILL_FIRE_RL_doFCVT_S_L or
MUX_resultR$write_1__VAL_40 or
WILL_FIRE_RL_doFSGNJX_S or
MUX_resultR$write_1__VAL_41 or
WILL_FIRE_RL_doFSGNJN_S or
MUX_resultR$write_1__VAL_42 or
WILL_FIRE_RL_doFSGNJ_S or MUX_resultR$write_1__VAL_43)
case (1'b1)
WILL_FIRE_RL_rl_reset_begin || EN_req:
resultR$D_IN = 70'h0AAAAAAAAAAAAAAAAA;
WILL_FIRE_RL_rl_get_fpu_result: resultR$D_IN = MUX_resultR$write_1__VAL_3;
WILL_FIRE_RL_doFCLASS_D: resultR$D_IN = MUX_resultR$write_1__VAL_4;
WILL_FIRE_RL_doFMV_X_D: resultR$D_IN = MUX_resultR$write_1__VAL_6;
WILL_FIRE_RL_doFMV_D_X: resultR$D_IN = MUX_resultR$write_1__VAL_6;
WILL_FIRE_RL_doFLE_D: resultR$D_IN = MUX_resultR$write_1__VAL_7;
WILL_FIRE_RL_doFLT_D: resultR$D_IN = MUX_resultR$write_1__VAL_8;
WILL_FIRE_RL_doFEQ_D: resultR$D_IN = MUX_resultR$write_1__VAL_9;
WILL_FIRE_RL_doFMAX_D: resultR$D_IN = MUX_resultR$write_1__VAL_10;
WILL_FIRE_RL_doFMIN_D: resultR$D_IN = MUX_resultR$write_1__VAL_11;
WILL_FIRE_RL_doFCVT_D_S: resultR$D_IN = MUX_resultR$write_1__VAL_12;
WILL_FIRE_RL_doFCVT_S_D: resultR$D_IN = MUX_resultR$write_1__VAL_13;
WILL_FIRE_RL_doFCVT_LU_D: resultR$D_IN = MUX_resultR$write_1__VAL_14;
WILL_FIRE_RL_doFCVT_L_D: resultR$D_IN = MUX_resultR$write_1__VAL_15;
WILL_FIRE_RL_doFCVT_D_LU: resultR$D_IN = MUX_resultR$write_1__VAL_16;
WILL_FIRE_RL_doFCVT_D_L: resultR$D_IN = MUX_resultR$write_1__VAL_17;
WILL_FIRE_RL_doFCVT_WU_D: resultR$D_IN = MUX_resultR$write_1__VAL_18;
WILL_FIRE_RL_doFCVT_W_D: resultR$D_IN = MUX_resultR$write_1__VAL_19;
WILL_FIRE_RL_doFCVT_D_WU: resultR$D_IN = MUX_resultR$write_1__VAL_20;
WILL_FIRE_RL_doFCVT_D_W: resultR$D_IN = MUX_resultR$write_1__VAL_21;
WILL_FIRE_RL_doFSGNJX_D: resultR$D_IN = MUX_resultR$write_1__VAL_22;
WILL_FIRE_RL_doFSGNJN_D: resultR$D_IN = MUX_resultR$write_1__VAL_23;
WILL_FIRE_RL_doFSGNJ_D: resultR$D_IN = MUX_resultR$write_1__VAL_24;
WILL_FIRE_RL_doFCLASS_S: resultR$D_IN = MUX_resultR$write_1__VAL_25;
WILL_FIRE_RL_doFLE_S: resultR$D_IN = MUX_resultR$write_1__VAL_26;
WILL_FIRE_RL_doFLT_S: resultR$D_IN = MUX_resultR$write_1__VAL_27;
WILL_FIRE_RL_doFEQ_S: resultR$D_IN = MUX_resultR$write_1__VAL_28;
WILL_FIRE_RL_doFMV_X_W: resultR$D_IN = MUX_resultR$write_1__VAL_29;
WILL_FIRE_RL_doFMV_W_X: resultR$D_IN = MUX_resultR$write_1__VAL_30;
WILL_FIRE_RL_doFMAX_S: resultR$D_IN = MUX_resultR$write_1__VAL_31;
WILL_FIRE_RL_doFMIN_S: resultR$D_IN = MUX_resultR$write_1__VAL_32;
WILL_FIRE_RL_doFCVT_WU_S: resultR$D_IN = MUX_resultR$write_1__VAL_33;
WILL_FIRE_RL_doFCVT_W_S: resultR$D_IN = MUX_resultR$write_1__VAL_34;
WILL_FIRE_RL_doFCVT_LU_S: resultR$D_IN = MUX_resultR$write_1__VAL_35;
WILL_FIRE_RL_doFCVT_L_S: resultR$D_IN = MUX_resultR$write_1__VAL_36;
WILL_FIRE_RL_doFCVT_S_WU: resultR$D_IN = MUX_resultR$write_1__VAL_37;
WILL_FIRE_RL_doFCVT_S_W: resultR$D_IN = MUX_resultR$write_1__VAL_38;
WILL_FIRE_RL_doFCVT_S_LU: resultR$D_IN = MUX_resultR$write_1__VAL_39;
WILL_FIRE_RL_doFCVT_S_L: resultR$D_IN = MUX_resultR$write_1__VAL_40;
WILL_FIRE_RL_doFSGNJX_S: resultR$D_IN = MUX_resultR$write_1__VAL_41;
WILL_FIRE_RL_doFSGNJN_S: resultR$D_IN = MUX_resultR$write_1__VAL_42;
WILL_FIRE_RL_doFSGNJ_S: resultR$D_IN = MUX_resultR$write_1__VAL_43;
default: resultR$D_IN = 70'h2AAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
assign resultR$EN =
WILL_FIRE_RL_rl_reset_begin || EN_req ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFSGNJ_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFCVT_S_L ||
WILL_FIRE_RL_doFCVT_S_LU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_L_S ||
WILL_FIRE_RL_doFCVT_LU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_D_L ||
WILL_FIRE_RL_doFCVT_D_LU ||
WILL_FIRE_RL_doFCVT_L_D ||
WILL_FIRE_RL_doFCVT_LU_D ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_rl_get_fpu_result ;
// register stateR
always@(WILL_FIRE_RL_rl_reset_begin or
EN_req or
WILL_FIRE_RL_rl_get_fpu_result or
WILL_FIRE_RL_doFCLASS_D or
WILL_FIRE_RL_doFMV_X_D or
WILL_FIRE_RL_doFMV_D_X or
WILL_FIRE_RL_doFLE_D or
WILL_FIRE_RL_doFLT_D or
WILL_FIRE_RL_doFEQ_D or
WILL_FIRE_RL_doFMAX_D or
WILL_FIRE_RL_doFMIN_D or
WILL_FIRE_RL_doFCVT_D_S or
WILL_FIRE_RL_doFCVT_S_D or
WILL_FIRE_RL_doFCVT_LU_D or
WILL_FIRE_RL_doFCVT_L_D or
WILL_FIRE_RL_doFCVT_D_LU or
WILL_FIRE_RL_doFCVT_D_L or
WILL_FIRE_RL_doFCVT_WU_D or
WILL_FIRE_RL_doFCVT_W_D or
WILL_FIRE_RL_doFCVT_D_WU or
WILL_FIRE_RL_doFCVT_D_W or
WILL_FIRE_RL_doFSGNJX_D or
WILL_FIRE_RL_doFSGNJN_D or
WILL_FIRE_RL_doFSGNJ_D or
WILL_FIRE_RL_doFSQRT_D or
WILL_FIRE_RL_doFDIV_D or
WILL_FIRE_RL_doFNMSUB_D or
WILL_FIRE_RL_doFNMADD_D or
WILL_FIRE_RL_doFMSUB_D or
WILL_FIRE_RL_doFMADD_D or
WILL_FIRE_RL_doFMUL_D or
WILL_FIRE_RL_doFSUB_D or
WILL_FIRE_RL_doFADD_D or
WILL_FIRE_RL_doFCLASS_S or
WILL_FIRE_RL_doFLE_S or
WILL_FIRE_RL_doFLT_S or
WILL_FIRE_RL_doFEQ_S or
WILL_FIRE_RL_doFMV_X_W or
WILL_FIRE_RL_doFMV_W_X or
WILL_FIRE_RL_doFMAX_S or
WILL_FIRE_RL_doFMIN_S or
WILL_FIRE_RL_doFCVT_WU_S or
WILL_FIRE_RL_doFCVT_W_S or
WILL_FIRE_RL_doFCVT_LU_S or
WILL_FIRE_RL_doFCVT_L_S or
WILL_FIRE_RL_doFCVT_S_WU or
WILL_FIRE_RL_doFCVT_S_W or
WILL_FIRE_RL_doFCVT_S_LU or
WILL_FIRE_RL_doFCVT_S_L or
WILL_FIRE_RL_doFSGNJX_S or
WILL_FIRE_RL_doFSGNJN_S or
WILL_FIRE_RL_doFSGNJ_S or
WILL_FIRE_RL_doFSQRT_S or
WILL_FIRE_RL_doFDIV_S or
WILL_FIRE_RL_doFNMSUB_S or
WILL_FIRE_RL_doFNMADD_S or
WILL_FIRE_RL_doFMSUB_S or
WILL_FIRE_RL_doFMADD_S or
WILL_FIRE_RL_doFMUL_S or
WILL_FIRE_RL_doFSUB_S or
WILL_FIRE_RL_doFADD_S or WILL_FIRE_RL_rl_reset_end)
case (1'b1)
WILL_FIRE_RL_rl_reset_begin: stateR$D_IN = 2'd0;
EN_req: stateR$D_IN = 2'd1;
WILL_FIRE_RL_rl_get_fpu_result || WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_LU_D ||
WILL_FIRE_RL_doFCVT_L_D ||
WILL_FIRE_RL_doFCVT_D_LU ||
WILL_FIRE_RL_doFCVT_D_L ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D:
stateR$D_IN = 2'd3;
WILL_FIRE_RL_doFSQRT_D || WILL_FIRE_RL_doFDIV_D ||
WILL_FIRE_RL_doFNMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_doFCLASS_S || WILL_FIRE_RL_doFLE_S || WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_LU_S ||
WILL_FIRE_RL_doFCVT_L_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_LU ||
WILL_FIRE_RL_doFCVT_S_L ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S:
stateR$D_IN = 2'd3;
WILL_FIRE_RL_doFSQRT_S || WILL_FIRE_RL_doFDIV_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S:
stateR$D_IN = 2'd2;
WILL_FIRE_RL_rl_reset_end: stateR$D_IN = 2'd1;
default: stateR$D_IN = 2'b10 /* unspecified value */ ;
endcase
assign stateR$EN =
WILL_FIRE_RL_rl_reset_begin || WILL_FIRE_RL_rl_reset_end ||
EN_req ||
WILL_FIRE_RL_doFSQRT_D ||
WILL_FIRE_RL_doFDIV_D ||
WILL_FIRE_RL_doFNMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFSQRT_S ||
WILL_FIRE_RL_doFDIV_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFADD_S ||
WILL_FIRE_RL_rl_get_fpu_result ||
WILL_FIRE_RL_doFCLASS_D ||
WILL_FIRE_RL_doFMV_X_D ||
WILL_FIRE_RL_doFMV_D_X ||
WILL_FIRE_RL_doFLE_D ||
WILL_FIRE_RL_doFLT_D ||
WILL_FIRE_RL_doFEQ_D ||
WILL_FIRE_RL_doFMAX_D ||
WILL_FIRE_RL_doFMIN_D ||
WILL_FIRE_RL_doFCVT_D_S ||
WILL_FIRE_RL_doFCVT_S_D ||
WILL_FIRE_RL_doFCVT_LU_D ||
WILL_FIRE_RL_doFCVT_L_D ||
WILL_FIRE_RL_doFCVT_D_LU ||
WILL_FIRE_RL_doFCVT_D_L ||
WILL_FIRE_RL_doFCVT_WU_D ||
WILL_FIRE_RL_doFCVT_W_D ||
WILL_FIRE_RL_doFCVT_D_WU ||
WILL_FIRE_RL_doFCVT_D_W ||
WILL_FIRE_RL_doFSGNJX_D ||
WILL_FIRE_RL_doFSGNJN_D ||
WILL_FIRE_RL_doFSGNJ_D ||
WILL_FIRE_RL_doFCLASS_S ||
WILL_FIRE_RL_doFLE_S ||
WILL_FIRE_RL_doFLT_S ||
WILL_FIRE_RL_doFEQ_S ||
WILL_FIRE_RL_doFMV_X_W ||
WILL_FIRE_RL_doFMV_W_X ||
WILL_FIRE_RL_doFMAX_S ||
WILL_FIRE_RL_doFMIN_S ||
WILL_FIRE_RL_doFCVT_WU_S ||
WILL_FIRE_RL_doFCVT_W_S ||
WILL_FIRE_RL_doFCVT_LU_S ||
WILL_FIRE_RL_doFCVT_L_S ||
WILL_FIRE_RL_doFCVT_S_WU ||
WILL_FIRE_RL_doFCVT_S_W ||
WILL_FIRE_RL_doFCVT_S_LU ||
WILL_FIRE_RL_doFCVT_S_L ||
WILL_FIRE_RL_doFSGNJX_S ||
WILL_FIRE_RL_doFSGNJN_S ||
WILL_FIRE_RL_doFSGNJ_S ;
// submodule fpu
always@(WILL_FIRE_RL_doFADD_S or
MUX_fpu$server_core_request_put_1__VAL_1 or
WILL_FIRE_RL_doFSUB_S or
MUX_fpu$server_core_request_put_1__VAL_2 or
WILL_FIRE_RL_doFMUL_S or
MUX_fpu$server_core_request_put_1__VAL_3 or
WILL_FIRE_RL_doFMADD_S or
MUX_fpu$server_core_request_put_1__VAL_4 or
WILL_FIRE_RL_doFMSUB_S or
MUX_fpu$server_core_request_put_1__VAL_5 or
WILL_FIRE_RL_doFNMADD_S or
MUX_fpu$server_core_request_put_1__VAL_6 or
WILL_FIRE_RL_doFNMSUB_S or
MUX_fpu$server_core_request_put_1__VAL_7 or
WILL_FIRE_RL_doFDIV_S or
MUX_fpu$server_core_request_put_1__VAL_8 or
WILL_FIRE_RL_doFSQRT_S or
MUX_fpu$server_core_request_put_1__VAL_9 or
WILL_FIRE_RL_doFADD_D or
MUX_fpu$server_core_request_put_1__VAL_10 or
WILL_FIRE_RL_doFSUB_D or
MUX_fpu$server_core_request_put_1__VAL_11 or
WILL_FIRE_RL_doFMUL_D or
MUX_fpu$server_core_request_put_1__VAL_12 or
WILL_FIRE_RL_doFMADD_D or
MUX_fpu$server_core_request_put_1__VAL_13 or
WILL_FIRE_RL_doFMSUB_D or
MUX_fpu$server_core_request_put_1__VAL_14 or
WILL_FIRE_RL_doFNMADD_D or
MUX_fpu$server_core_request_put_1__VAL_15 or
WILL_FIRE_RL_doFNMSUB_D or
MUX_fpu$server_core_request_put_1__VAL_16 or
WILL_FIRE_RL_doFDIV_D or
MUX_fpu$server_core_request_put_1__VAL_17 or
WILL_FIRE_RL_doFSQRT_D or MUX_fpu$server_core_request_put_1__VAL_18)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_doFADD_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_1;
WILL_FIRE_RL_doFSUB_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_2;
WILL_FIRE_RL_doFMUL_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_3;
WILL_FIRE_RL_doFMADD_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_4;
WILL_FIRE_RL_doFMSUB_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_5;
WILL_FIRE_RL_doFNMADD_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_6;
WILL_FIRE_RL_doFNMSUB_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_7;
WILL_FIRE_RL_doFDIV_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_8;
WILL_FIRE_RL_doFSQRT_S:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_9;
WILL_FIRE_RL_doFADD_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_10;
WILL_FIRE_RL_doFSUB_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_11;
WILL_FIRE_RL_doFMUL_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_12;
WILL_FIRE_RL_doFMADD_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_13;
WILL_FIRE_RL_doFMSUB_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_14;
WILL_FIRE_RL_doFNMADD_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_15;
WILL_FIRE_RL_doFNMSUB_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_16;
WILL_FIRE_RL_doFDIV_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_17;
WILL_FIRE_RL_doFSQRT_D:
fpu$server_core_request_put =
MUX_fpu$server_core_request_put_1__VAL_18;
default: fpu$server_core_request_put =
202'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fpu$EN_server_core_request_put =
WILL_FIRE_RL_doFADD_S || WILL_FIRE_RL_doFSUB_S ||
WILL_FIRE_RL_doFMUL_S ||
WILL_FIRE_RL_doFMADD_S ||
WILL_FIRE_RL_doFMSUB_S ||
WILL_FIRE_RL_doFNMADD_S ||
WILL_FIRE_RL_doFNMSUB_S ||
WILL_FIRE_RL_doFDIV_S ||
WILL_FIRE_RL_doFSQRT_S ||
WILL_FIRE_RL_doFADD_D ||
WILL_FIRE_RL_doFSUB_D ||
WILL_FIRE_RL_doFMUL_D ||
WILL_FIRE_RL_doFMADD_D ||
WILL_FIRE_RL_doFMSUB_D ||
WILL_FIRE_RL_doFNMADD_D ||
WILL_FIRE_RL_doFNMSUB_D ||
WILL_FIRE_RL_doFDIV_D ||
WILL_FIRE_RL_doFSQRT_D ;
assign fpu$EN_server_core_response_get = MUX_dw_result$wset_1__SEL_1 ;
assign fpu$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_begin ;
assign fpu$EN_server_reset_response_get = CAN_FIRE_RL_rl_reset_end ;
// submodule frmFpuF
assign frmFpuF$D_IN = 1'b0 ;
assign frmFpuF$ENQ = 1'b0 ;
assign frmFpuF$DEQ = 1'b0 ;
assign frmFpuF$CLR = CAN_FIRE_RL_rl_reset_begin ;
// submodule resetReqsF
assign resetReqsF$ENQ = EN_server_reset_request_put ;
assign resetReqsF$DEQ =
fpu$RDY_server_reset_request_put && resetReqsF$EMPTY_N ;
assign resetReqsF$CLR = 1'b0 ;
// submodule resetRspsF
assign resetRspsF$ENQ =
fpu$RDY_server_reset_response_get && resetRspsF$FULL_N &&
stateR == 2'd0 ;
assign resetRspsF$DEQ = EN_server_reset_response_get ;
assign resetRspsF$CLR = 1'b0 ;
// remaining internal signals
assign IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_ETC__q117 =
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656 ?
_theResult___snd__h135453 :
_theResult____h126028 ;
assign IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_reques_ETC__q154 =
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935 ?
_theResult___snd__h201397 :
_theResult____h191843 ;
assign IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR__ETC__q122 =
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100 ?
_theResult___snd__h155794 :
_theResult____h146240 ;
assign IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q151 =
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615 ?
_theResult___snd__h190495 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q157 =
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008 ?
_theResult___snd__h190495 :
_theResult___snd__h211382 ;
assign IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q119 =
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778 ?
_theResult___snd__h145298 :
57'd0 ;
assign IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q125 =
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173 ?
_theResult___snd__h145298 :
_theResult___snd__h165663 ;
assign IF_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_21_ETC___d4358 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
((_theResult___fst_exp__h135390 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144)) :
((_theResult___fst_exp__h145309 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1379 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46) :
((x__h35010[7:0] == 8'd255) ?
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1529 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
guard__h34468 != 2'b0 :
x__h35010[7:0] != 8'd255 && guard__h34995 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2398 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73) :
((x__h70144[10:0] == 11'd2047) ?
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75)) ;
assign IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2513 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
guard__h69399 != 2'b0 :
x__h70144[10:0] != 11'd2047 && guard__h70129 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1718 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 ?
guard__h41384 != 2'b0 :
x__h41925[7:0] != 8'd255 && guard__h41910 != 2'b0 ;
assign IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d2697 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 ?
guard__h80346 != 2'b0 :
x__h81090[10:0] != 11'd2047 && guard__h81075 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2937 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98) :
((x__h96466[10:0] == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100)) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d3054 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
guard__h95721 != 2'b0 :
x__h96466[10:0] != 11'd2047 && guard__h96451 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d511 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14) :
((x__h15560[7:0] == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16)) ;
assign IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d693 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
guard__h15015 != 2'b0 :
x__h15560[7:0] != 8'd255 && guard__h15545 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1174 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 ?
guard__h27296 != 2'b0 :
x__h27837[7:0] != 8'd255 && guard__h27822 != 2'b0 ;
assign IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d3208 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 ?
guard__h108246 != 2'b0 :
x__h108990[10:0] != 11'd2047 && guard__h108975 != 2'b0 ;
assign IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 =
(_theResult____h126028[56] ?
6'd0 :
(_theResult____h126028[55] ?
6'd1 :
(_theResult____h126028[54] ?
6'd2 :
(_theResult____h126028[53] ?
6'd3 :
(_theResult____h126028[52] ?
6'd4 :
(_theResult____h126028[51] ?
6'd5 :
(_theResult____h126028[50] ?
6'd6 :
(_theResult____h126028[49] ?
6'd7 :
(_theResult____h126028[48] ?
6'd8 :
(_theResult____h126028[47] ?
6'd9 :
(_theResult____h126028[46] ?
6'd10 :
(_theResult____h126028[45] ?
6'd11 :
(_theResult____h126028[44] ?
6'd12 :
(_theResult____h126028[43] ?
6'd13 :
(_theResult____h126028[42] ?
6'd14 :
(_theResult____h126028[41] ?
6'd15 :
(_theResult____h126028[40] ?
6'd16 :
(_theResult____h126028[39] ?
6'd17 :
(_theResult____h126028[38] ?
6'd18 :
(_theResult____h126028[37] ?
6'd19 :
(_theResult____h126028[36] ?
6'd20 :
(_theResult____h126028[35] ?
6'd21 :
(_theResult____h126028[34] ?
6'd22 :
(_theResult____h126028[33] ?
6'd23 :
(_theResult____h126028[32] ?
6'd24 :
(_theResult____h126028[31] ?
6'd25 :
(_theResult____h126028[30] ?
6'd26 :
(_theResult____h126028[29] ?
6'd27 :
(_theResult____h126028[28] ?
6'd28 :
(_theResult____h126028[27] ?
6'd29 :
(_theResult____h126028[26] ?
6'd30 :
(_theResult____h126028[25] ?
6'd31 :
(_theResult____h126028[24] ?
6'd32 :
(_theResult____h126028[23] ?
6'd33 :
(_theResult____h126028[22] ?
6'd34 :
(_theResult____h126028[21] ?
6'd35 :
(_theResult____h126028[20] ?
6'd36 :
(_theResult____h126028[19] ?
6'd37 :
(_theResult____h126028[18] ?
6'd38 :
(_theResult____h126028[17] ?
6'd39 :
(_theResult____h126028[16] ?
6'd40 :
(_theResult____h126028[15] ?
6'd41 :
(_theResult____h126028[14] ?
6'd42 :
(_theResult____h126028[13] ?
6'd43 :
(_theResult____h126028[12] ?
6'd44 :
(_theResult____h126028[11] ?
6'd45 :
(_theResult____h126028[10] ?
6'd46 :
(_theResult____h126028[9] ?
6'd47 :
(_theResult____h126028[8] ?
6'd48 :
(_theResult____h126028[7] ?
6'd49 :
(_theResult____h126028[6] ?
6'd50 :
(_theResult____h126028[5] ?
6'd51 :
(_theResult____h126028[4] ?
6'd52 :
(_theResult____h126028[3] ?
6'd53 :
(_theResult____h126028[2] ?
6'd54 :
(_theResult____h126028[1] ?
6'd55 :
(_theResult____h126028[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 =
(_theResult____h191843[56] ?
6'd0 :
(_theResult____h191843[55] ?
6'd1 :
(_theResult____h191843[54] ?
6'd2 :
(_theResult____h191843[53] ?
6'd3 :
(_theResult____h191843[52] ?
6'd4 :
(_theResult____h191843[51] ?
6'd5 :
(_theResult____h191843[50] ?
6'd6 :
(_theResult____h191843[49] ?
6'd7 :
(_theResult____h191843[48] ?
6'd8 :
(_theResult____h191843[47] ?
6'd9 :
(_theResult____h191843[46] ?
6'd10 :
(_theResult____h191843[45] ?
6'd11 :
(_theResult____h191843[44] ?
6'd12 :
(_theResult____h191843[43] ?
6'd13 :
(_theResult____h191843[42] ?
6'd14 :
(_theResult____h191843[41] ?
6'd15 :
(_theResult____h191843[40] ?
6'd16 :
(_theResult____h191843[39] ?
6'd17 :
(_theResult____h191843[38] ?
6'd18 :
(_theResult____h191843[37] ?
6'd19 :
(_theResult____h191843[36] ?
6'd20 :
(_theResult____h191843[35] ?
6'd21 :
(_theResult____h191843[34] ?
6'd22 :
(_theResult____h191843[33] ?
6'd23 :
(_theResult____h191843[32] ?
6'd24 :
(_theResult____h191843[31] ?
6'd25 :
(_theResult____h191843[30] ?
6'd26 :
(_theResult____h191843[29] ?
6'd27 :
(_theResult____h191843[28] ?
6'd28 :
(_theResult____h191843[27] ?
6'd29 :
(_theResult____h191843[26] ?
6'd30 :
(_theResult____h191843[25] ?
6'd31 :
(_theResult____h191843[24] ?
6'd32 :
(_theResult____h191843[23] ?
6'd33 :
(_theResult____h191843[22] ?
6'd34 :
(_theResult____h191843[21] ?
6'd35 :
(_theResult____h191843[20] ?
6'd36 :
(_theResult____h191843[19] ?
6'd37 :
(_theResult____h191843[18] ?
6'd38 :
(_theResult____h191843[17] ?
6'd39 :
(_theResult____h191843[16] ?
6'd40 :
(_theResult____h191843[15] ?
6'd41 :
(_theResult____h191843[14] ?
6'd42 :
(_theResult____h191843[13] ?
6'd43 :
(_theResult____h191843[12] ?
6'd44 :
(_theResult____h191843[11] ?
6'd45 :
(_theResult____h191843[10] ?
6'd46 :
(_theResult____h191843[9] ?
6'd47 :
(_theResult____h191843[8] ?
6'd48 :
(_theResult____h191843[7] ?
6'd49 :
(_theResult____h191843[6] ?
6'd50 :
(_theResult____h191843[5] ?
6'd51 :
(_theResult____h191843[4] ?
6'd52 :
(_theResult____h191843[3] ?
6'd53 :
(_theResult____h191843[2] ?
6'd54 :
(_theResult____h191843[1] ?
6'd55 :
(_theResult____h191843[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 =
(_theResult____h146240[56] ?
6'd0 :
(_theResult____h146240[55] ?
6'd1 :
(_theResult____h146240[54] ?
6'd2 :
(_theResult____h146240[53] ?
6'd3 :
(_theResult____h146240[52] ?
6'd4 :
(_theResult____h146240[51] ?
6'd5 :
(_theResult____h146240[50] ?
6'd6 :
(_theResult____h146240[49] ?
6'd7 :
(_theResult____h146240[48] ?
6'd8 :
(_theResult____h146240[47] ?
6'd9 :
(_theResult____h146240[46] ?
6'd10 :
(_theResult____h146240[45] ?
6'd11 :
(_theResult____h146240[44] ?
6'd12 :
(_theResult____h146240[43] ?
6'd13 :
(_theResult____h146240[42] ?
6'd14 :
(_theResult____h146240[41] ?
6'd15 :
(_theResult____h146240[40] ?
6'd16 :
(_theResult____h146240[39] ?
6'd17 :
(_theResult____h146240[38] ?
6'd18 :
(_theResult____h146240[37] ?
6'd19 :
(_theResult____h146240[36] ?
6'd20 :
(_theResult____h146240[35] ?
6'd21 :
(_theResult____h146240[34] ?
6'd22 :
(_theResult____h146240[33] ?
6'd23 :
(_theResult____h146240[32] ?
6'd24 :
(_theResult____h146240[31] ?
6'd25 :
(_theResult____h146240[30] ?
6'd26 :
(_theResult____h146240[29] ?
6'd27 :
(_theResult____h146240[28] ?
6'd28 :
(_theResult____h146240[27] ?
6'd29 :
(_theResult____h146240[26] ?
6'd30 :
(_theResult____h146240[25] ?
6'd31 :
(_theResult____h146240[24] ?
6'd32 :
(_theResult____h146240[23] ?
6'd33 :
(_theResult____h146240[22] ?
6'd34 :
(_theResult____h146240[21] ?
6'd35 :
(_theResult____h146240[20] ?
6'd36 :
(_theResult____h146240[19] ?
6'd37 :
(_theResult____h146240[18] ?
6'd38 :
(_theResult____h146240[17] ?
6'd39 :
(_theResult____h146240[16] ?
6'd40 :
(_theResult____h146240[15] ?
6'd41 :
(_theResult____h146240[14] ?
6'd42 :
(_theResult____h146240[13] ?
6'd43 :
(_theResult____h146240[12] ?
6'd44 :
(_theResult____h146240[11] ?
6'd45 :
(_theResult____h146240[10] ?
6'd46 :
(_theResult____h146240[9] ?
6'd47 :
(_theResult____h146240[8] ?
6'd48 :
(_theResult____h146240[7] ?
6'd49 :
(_theResult____h146240[6] ?
6'd50 :
(_theResult____h146240[5] ?
6'd51 :
(_theResult____h146240[4] ?
6'd52 :
(_theResult____h146240[3] ?
6'd53 :
(_theResult____h146240[2] ?
6'd54 :
(_theResult____h146240[1] ?
6'd55 :
(_theResult____h146240[0] ?
6'd56 :
6'd57))))))))))))))))))))))))))))))))))))))))))))))))))))))))) -
6'd1 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713 =
(guard__h126038 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h135390 :
_theResult___exp__h135916 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715 =
(guard__h126038 == 2'b0) ?
_theResult___fst_exp__h135390 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h135916 :
_theResult___fst_exp__h135390) ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260 =
(guard__h126038 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfdin__h135384[56:34] :
_theResult___sfd__h135917 ;
assign IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262 =
(guard__h126038 == 2'b0) ?
sfdin__h135384[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h135917 :
sfdin__h135384[56:34]) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992 =
(guard__h191853 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___fst_exp__h201334 :
_theResult___exp__h202063 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994 =
(guard__h191853 == 2'b0) ?
_theResult___fst_exp__h201334 :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___exp__h202063 :
_theResult___fst_exp__h201334) ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121 =
(guard__h191853 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
sfdin__h201328[56:5] :
_theResult___sfd__h202064 ;
assign IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123 =
(guard__h191853 == 2'b0) ?
sfdin__h201328[56:5] :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___sfd__h202064 :
sfdin__h201328[56:5]) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157 =
(guard__h146250 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h155731 :
_theResult___exp__h156257 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159 =
(guard__h146250 == 2'b0) ?
_theResult___fst_exp__h155731 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h156257 :
_theResult___fst_exp__h155731) ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306 =
(guard__h146250 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfdin__h155725[56:34] :
_theResult___sfd__h156258 ;
assign IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308 =
(guard__h146250 == 2'b0) ?
sfdin__h155725[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h156258 :
sfdin__h155725[56:34]) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667 =
(guard__h181312 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___fst_exp__h190506 :
_theResult___exp__h191161 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669 =
(guard__h181312 == 2'b0) ?
_theResult___fst_exp__h190506 :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___exp__h191161 :
_theResult___fst_exp__h190506) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061 =
(guard__h202175 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___fst_exp__h211398 :
_theResult___exp__h212078 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063 =
(guard__h202175 == 2'b0) ?
_theResult___fst_exp__h211398 :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___exp__h212078 :
_theResult___fst_exp__h211398) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094 =
(guard__h181312 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___snd__h190457[56:5] :
_theResult___sfd__h191162 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096 =
(guard__h181312 == 2'b0) ?
_theResult___snd__h190457[56:5] :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___sfd__h191162 :
_theResult___snd__h190457[56:5]) ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140 =
(guard__h202175 == 2'b0 ||
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___snd__h211344[56:5] :
_theResult___sfd__h212079 ;
assign IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142 =
(guard__h202175 == 2'b0) ?
_theResult___snd__h211344[56:5] :
((requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
_theResult___sfd__h212079 :
_theResult___snd__h211344[56:5]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401 =
(guard__h34468 == 2'b0) ?
8'd0 :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h34881 :
8'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427 =
(guard__h34995 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
x__h35010[7:0] :
_theResult___exp__h35434 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429 =
(guard__h34995 == 2'b0) ?
x__h35010[7:0] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h35434 :
x__h35010[7:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450 =
(guard__h34468 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h34458[31:9] :
_theResult___sfd__h34882 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452 =
(guard__h34468 == 2'b0) ?
sfd___3__h34458[31:9] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h34882 :
sfd___3__h34458[31:9]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468 =
(guard__h34995 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h34458[30:8] :
_theResult___sfd__h35435 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470 =
(guard__h34995 == 2'b0) ?
sfd___3__h34458[30:8] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h35435 :
sfd___3__h34458[30:8]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419 =
(guard__h69399 == 2'b0) ?
11'd0 :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h70015 :
11'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445 =
(guard__h70129 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
x__h70144[10:0] :
_theResult___exp__h70771 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447 =
(guard__h70129 == 2'b0) ?
x__h70144[10:0] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___exp__h70771 :
x__h70144[10:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468 =
(guard__h69399 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h69389[54:3] :
_theResult___sfd__h70016 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470 =
(guard__h69399 == 2'b0) ?
sfd___3__h69389[54:3] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h70016 :
sfd___3__h69389[54:3]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486 =
(guard__h70129 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
sfd___3__h69389[53:2] :
_theResult___sfd__h70772 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488 =
(guard__h70129 == 2'b0) ?
sfd___3__h69389[53:2] :
(requestR_BITS_191_TO_128__q1[31] ?
_theResult___sfd__h70772 :
sfd___3__h69389[53:2]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958 =
(guard__h95721 == 2'b0) ?
11'd0 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h96337 :
11'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984 =
(guard__h96451 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
x__h96466[10:0] :
_theResult___exp__h97093 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986 =
(guard__h96451 == 2'b0) ?
x__h96466[10:0] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h97093 :
x__h96466[10:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007 =
(guard__h95721 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[63:12] :
_theResult___sfd__h96338 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009 =
(guard__h95721 == 2'b0) ?
sfd___3__h15005[63:12] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h96338 :
sfd___3__h15005[63:12]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025 =
(guard__h96451 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[62:11] :
_theResult___sfd__h97094 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027 =
(guard__h96451 == 2'b0) ?
sfd___3__h15005[62:11] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h97094 :
sfd___3__h15005[62:11]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830 =
(guard__h136028 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h145309 :
_theResult___exp__h145761 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832 =
(guard__h136028 == 2'b0) ?
_theResult___fst_exp__h145309 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h145761 :
_theResult___fst_exp__h145309) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226 =
(guard__h156369 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___fst_exp__h165679 :
_theResult___exp__h166156 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228 =
(guard__h156369 == 2'b0) ?
_theResult___fst_exp__h165679 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h166156 :
_theResult___fst_exp__h165679) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279 =
(guard__h136028 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___snd__h145260[56:34] :
_theResult___sfd__h145762 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281 =
(guard__h136028 == 2'b0) ?
_theResult___snd__h145260[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h145762 :
_theResult___snd__h145260[56:34]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325 =
(guard__h156369 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
_theResult___snd__h165625[56:34] :
_theResult___sfd__h166157 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327 =
(guard__h156369 == 2'b0) ?
_theResult___snd__h165625[56:34] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h166157 :
_theResult___snd__h165625[56:34]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533 =
(guard__h15015 == 2'b0) ?
8'd0 :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h15431 :
8'd0) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559 =
(guard__h15545 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
x__h15560[7:0] :
_theResult___exp__h15984 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561 =
(guard__h15545 == 2'b0) ?
x__h15560[7:0] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___exp__h15984 :
x__h15560[7:0]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582 =
(guard__h15015 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[63:41] :
_theResult___sfd__h15432 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584 =
(guard__h15015 == 2'b0) ?
sfd___3__h15005[63:41] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h15432 :
sfd___3__h15005[63:41]) ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600 =
(guard__h15545 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
sfd___3__h15005[62:40] :
_theResult___sfd__h15985 ;
assign IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602 =
(guard__h15545 == 2'b0) ?
sfd___3__h15005[62:40] :
(requestR_BITS_191_TO_128__q1[63] ?
_theResult___sfd__h15985 :
sfd___3__h15005[62:40]) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318 =
sfd__h28849[31] ?
6'd0 :
(sfd__h28849[30] ?
6'd1 :
(sfd__h28849[29] ?
6'd2 :
(sfd__h28849[28] ?
6'd3 :
(sfd__h28849[27] ?
6'd4 :
(sfd__h28849[26] ?
6'd5 :
(sfd__h28849[25] ?
6'd6 :
(sfd__h28849[24] ?
6'd7 :
(sfd__h28849[23] ?
6'd8 :
(sfd__h28849[22] ?
6'd9 :
(sfd__h28849[21] ?
6'd10 :
(sfd__h28849[20] ?
6'd11 :
(sfd__h28849[19] ?
6'd12 :
(sfd__h28849[18] ?
6'd13 :
(sfd__h28849[17] ?
6'd14 :
(sfd__h28849[16] ?
6'd15 :
(sfd__h28849[15] ?
6'd16 :
(sfd__h28849[14] ?
6'd17 :
(sfd__h28849[13] ?
6'd18 :
(sfd__h28849[12] ?
6'd19 :
(sfd__h28849[11] ?
6'd20 :
(sfd__h28849[10] ?
6'd21 :
(sfd__h28849[9] ?
6'd22 :
(sfd__h28849[8] ?
6'd23 :
(sfd__h28849[7] ?
6'd24 :
(sfd__h28849[6] ?
6'd25 :
(sfd__h28849[5] ?
6'd26 :
(sfd__h28849[4] ?
6'd27 :
(sfd__h28849[3] ?
6'd28 :
(sfd__h28849[2] ?
6'd29 :
(sfd__h28849[1] ?
6'd30 :
(sfd__h28849[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1816 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745 :
((sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
64'd0 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1814) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1876 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
64'd0 :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847[19] ?
64'hFFFFFFFFFFFFFFFF :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1874) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1967 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904 :
((sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
32'd0 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1965) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2022 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
32'd0 :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993[19] ?
32'hFFFFFFFF :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d2020) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2108 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598[22] ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077) ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081 ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2106) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2109 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22]) ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2108 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2111 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22] &&
sV2_exp__h1597 == 8'd255 &&
sV2_sfd__h1598[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2109 } ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2112 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22]) ?
res__h49096 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2111 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2113 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22]) ?
res__h48859 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2112 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2123 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081 ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2122 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2125 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598[22]) ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077 ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2123) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2126 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22]) ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2125 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2128 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22] &&
sV2_exp__h1597 == 8'd255 &&
sV2_sfd__h1598[22]) ?
64'hFFFFFFFF7FC00000 :
{ 32'hFFFFFFFF,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2126 } ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2129 =
(sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22]) ?
res__h49096 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2128 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2130 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22]) ?
res__h48859 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2129 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2206 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
res___1__h57780 :
((sV1_exp__h1472 == 8'd0) ? res___1__h57799 : res__h57815) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2207 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
res___1__h57770 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2206 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339 =
sfd__h28849[31] ?
6'd0 :
(sfd__h28849[30] ?
6'd1 :
(sfd__h28849[29] ?
6'd2 :
(sfd__h28849[28] ?
6'd3 :
(sfd__h28849[27] ?
6'd4 :
(sfd__h28849[26] ?
6'd5 :
(sfd__h28849[25] ?
6'd6 :
(sfd__h28849[24] ?
6'd7 :
(sfd__h28849[23] ?
6'd8 :
(sfd__h28849[22] ?
6'd9 :
(sfd__h28849[21] ?
6'd10 :
(sfd__h28849[20] ?
6'd11 :
(sfd__h28849[19] ?
6'd12 :
(sfd__h28849[18] ?
6'd13 :
(sfd__h28849[17] ?
6'd14 :
(sfd__h28849[16] ?
6'd15 :
(sfd__h28849[15] ?
6'd16 :
(sfd__h28849[14] ?
6'd17 :
(sfd__h28849[13] ?
6'd18 :
(sfd__h28849[12] ?
6'd19 :
(sfd__h28849[11] ?
6'd20 :
(sfd__h28849[10] ?
6'd21 :
(sfd__h28849[9] ?
6'd22 :
(sfd__h28849[8] ?
6'd23 :
(sfd__h28849[7] ?
6'd24 :
(sfd__h28849[6] ?
6'd25 :
(sfd__h28849[5] ?
6'd26 :
(sfd__h28849[4] ?
6'd27 :
(sfd__h28849[3] ?
6'd28 :
(sfd__h28849[2] ?
6'd29 :
(sfd__h28849[1] ?
6'd30 :
(sfd__h28849[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 =
sfd__h3990[63] ?
7'd0 :
(sfd__h3990[62] ?
7'd1 :
(sfd__h3990[61] ?
7'd2 :
(sfd__h3990[60] ?
7'd3 :
(sfd__h3990[59] ?
7'd4 :
(sfd__h3990[58] ?
7'd5 :
(sfd__h3990[57] ?
7'd6 :
(sfd__h3990[56] ?
7'd7 :
(sfd__h3990[55] ?
7'd8 :
(sfd__h3990[54] ?
7'd9 :
(sfd__h3990[53] ?
7'd10 :
(sfd__h3990[52] ?
7'd11 :
(sfd__h3990[51] ?
7'd12 :
(sfd__h3990[50] ?
7'd13 :
(sfd__h3990[49] ?
7'd14 :
(sfd__h3990[48] ?
7'd15 :
(sfd__h3990[47] ?
7'd16 :
(sfd__h3990[46] ?
7'd17 :
(sfd__h3990[45] ?
7'd18 :
(sfd__h3990[44] ?
7'd19 :
(sfd__h3990[43] ?
7'd20 :
(sfd__h3990[42] ?
7'd21 :
(sfd__h3990[41] ?
7'd22 :
(sfd__h3990[40] ?
7'd23 :
(sfd__h3990[39] ?
7'd24 :
(sfd__h3990[38] ?
7'd25 :
(sfd__h3990[37] ?
7'd26 :
(sfd__h3990[36] ?
7'd27 :
(sfd__h3990[35] ?
7'd28 :
(sfd__h3990[34] ?
7'd29 :
(sfd__h3990[33] ?
7'd30 :
(sfd__h3990[32] ?
7'd31 :
(sfd__h3990[31] ?
7'd32 :
(sfd__h3990[30] ?
7'd33 :
(sfd__h3990[29] ?
7'd34 :
(sfd__h3990[28] ?
7'd35 :
(sfd__h3990[27] ?
7'd36 :
(sfd__h3990[26] ?
7'd37 :
(sfd__h3990[25] ?
7'd38 :
(sfd__h3990[24] ?
7'd39 :
(sfd__h3990[23] ?
7'd40 :
(sfd__h3990[22] ?
7'd41 :
(sfd__h3990[21] ?
7'd42 :
(sfd__h3990[20] ?
7'd43 :
(sfd__h3990[19] ?
7'd44 :
(sfd__h3990[18] ?
7'd45 :
(sfd__h3990[17] ?
7'd46 :
(sfd__h3990[16] ?
7'd47 :
(sfd__h3990[15] ?
7'd48 :
(sfd__h3990[14] ?
7'd49 :
(sfd__h3990[13] ?
7'd50 :
(sfd__h3990[12] ?
7'd51 :
(sfd__h3990[11] ?
7'd52 :
(sfd__h3990[10] ?
7'd53 :
(sfd__h3990[9] ?
7'd54 :
(sfd__h3990[8] ?
7'd55 :
(sfd__h3990[7] ?
7'd56 :
(sfd__h3990[6] ?
7'd57 :
(sfd__h3990[5] ?
7'd58 :
(sfd__h3990[4] ?
7'd59 :
(sfd__h3990[3] ?
7'd60 :
(sfd__h3990[2] ?
7'd61 :
(sfd__h3990[1] ?
7'd62 :
(sfd__h3990[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 =
((sV1_exp__h1472 == 8'd0) ?
(sV1_sfd__h1473[22] ?
6'd2 :
(sV1_sfd__h1473[21] ?
6'd3 :
(sV1_sfd__h1473[20] ?
6'd4 :
(sV1_sfd__h1473[19] ?
6'd5 :
(sV1_sfd__h1473[18] ?
6'd6 :
(sV1_sfd__h1473[17] ?
6'd7 :
(sV1_sfd__h1473[16] ?
6'd8 :
(sV1_sfd__h1473[15] ?
6'd9 :
(sV1_sfd__h1473[14] ?
6'd10 :
(sV1_sfd__h1473[13] ?
6'd11 :
(sV1_sfd__h1473[12] ?
6'd12 :
(sV1_sfd__h1473[11] ?
6'd13 :
(sV1_sfd__h1473[10] ?
6'd14 :
(sV1_sfd__h1473[9] ?
6'd15 :
(sV1_sfd__h1473[8] ?
6'd16 :
(sV1_sfd__h1473[7] ?
6'd17 :
(sV1_sfd__h1473[6] ?
6'd18 :
(sV1_sfd__h1473[5] ?
6'd19 :
(sV1_sfd__h1473[4] ?
6'd20 :
(sV1_sfd__h1473[3] ?
6'd21 :
(sV1_sfd__h1473[2] ?
6'd22 :
(sV1_sfd__h1473[1] ?
6'd23 :
(sV1_sfd__h1473[0] ?
6'd24 :
6'd57))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0) ?
_theResult___snd_fst_sfd__h169840 :
_theResult___fst_sfd__h212195 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5188 =
(sV1_exp__h1472 == 8'd0) ?
IF_NOT_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_ETC___d5169 :
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ?
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5186 :
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5189 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(sV1_exp__h1472 == 8'd255 || sV1_exp__h1472 == 8'd0) &&
sV1_sfd__h1473 == 23'd0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5188 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5224 =
(sV1_exp__h1472 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 &&
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[4] :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 &&
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[4] ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5227 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0) ?
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22] :
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5224 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5234 =
(sV1_exp__h1472 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 &&
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[3] :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 &&
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 &&
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[3] ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5248 =
(sV1_exp__h1472 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ||
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[2] :
!SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ||
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5246 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5260 =
(sV1_exp__h1472 == 8'd0) ?
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 &&
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ||
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[1]) :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 &&
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5258 ;
assign IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5272 =
(sV1_exp__h1472 == 8'd0) ?
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ||
!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 &&
_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203[0] :
!SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ||
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5270 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1439 =
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
!sfd__h28849[31] && !sfd__h28849[30] && !sfd__h28849[29] &&
!sfd__h28849[28] &&
!sfd__h28849[27] &&
!sfd__h28849[26] &&
!sfd__h28849[25] &&
!sfd__h28849[24] &&
!sfd__h28849[23] &&
!sfd__h28849[22] &&
!sfd__h28849[21] &&
!sfd__h28849[20] &&
!sfd__h28849[19] &&
!sfd__h28849[18] &&
!sfd__h28849[17] &&
!sfd__h28849[16] &&
!sfd__h28849[15] &&
!sfd__h28849[14] &&
!sfd__h28849[13] &&
!sfd__h28849[12] &&
!sfd__h28849[11] &&
!sfd__h28849[10] &&
!sfd__h28849[9] &&
!sfd__h28849[8] &&
!sfd__h28849[7] &&
!sfd__h28849[6] &&
!sfd__h28849[5] &&
!sfd__h28849[4] &&
!sfd__h28849[3] &&
!sfd__h28849[2] &&
!sfd__h28849[1] &&
!sfd__h28849[0]) ?
8'd0 :
_theResult___snd_fst_exp__h35543 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1520 =
(sfd__h28849[31] || sfd__h28849[30] || sfd__h28849[29] ||
sfd__h28849[28] ||
sfd__h28849[27] ||
sfd__h28849[26] ||
sfd__h28849[25] ||
sfd__h28849[24] ||
sfd__h28849[23] ||
sfd__h28849[22] ||
sfd__h28849[21] ||
sfd__h28849[20] ||
sfd__h28849[19] ||
sfd__h28849[18] ||
sfd__h28849[17] ||
sfd__h28849[16] ||
sfd__h28849[15] ||
sfd__h28849[14] ||
sfd__h28849[13] ||
sfd__h28849[12] ||
sfd__h28849[11] ||
sfd__h28849[10] ||
sfd__h28849[9] ||
sfd__h28849[8] ||
sfd__h28849[7] ||
sfd__h28849[6] ||
sfd__h28849[5] ||
sfd__h28849[4] ||
sfd__h28849[3] ||
sfd__h28849[2] ||
sfd__h28849[1] ||
sfd__h28849[0]) &&
(!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 &&
_theResult___fst_exp__h35534 == 8'd255 &&
_theResult___fst_sfd__h35535 == 23'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1523 =
(sfd__h28849[31] || sfd__h28849[30] || sfd__h28849[29] ||
sfd__h28849[28] ||
sfd__h28849[27] ||
sfd__h28849[26] ||
sfd__h28849[25] ||
sfd__h28849[24] ||
sfd__h28849[23] ||
sfd__h28849[22] ||
sfd__h28849[21] ||
sfd__h28849[20] ||
sfd__h28849[19] ||
sfd__h28849[18] ||
sfd__h28849[17] ||
sfd__h28849[16] ||
sfd__h28849[15] ||
sfd__h28849[14] ||
sfd__h28849[13] ||
sfd__h28849[12] ||
sfd__h28849[11] ||
sfd__h28849[10] ||
sfd__h28849[9] ||
sfd__h28849[8] ||
sfd__h28849[7] ||
sfd__h28849[6] ||
sfd__h28849[5] ||
sfd__h28849[4] ||
sfd__h28849[3] ||
sfd__h28849[2] ||
sfd__h28849[1] ||
sfd__h28849[0]) &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1532 =
(sfd__h28849[31] || sfd__h28849[30] || sfd__h28849[29] ||
sfd__h28849[28] ||
sfd__h28849[27] ||
sfd__h28849[26] ||
sfd__h28849[25] ||
sfd__h28849[24] ||
sfd__h28849[23] ||
sfd__h28849[22] ||
sfd__h28849[21] ||
sfd__h28849[20] ||
sfd__h28849[19] ||
sfd__h28849[18] ||
sfd__h28849[17] ||
sfd__h28849[16] ||
sfd__h28849[15] ||
sfd__h28849[14] ||
sfd__h28849[13] ||
sfd__h28849[12] ||
sfd__h28849[11] ||
sfd__h28849[10] ||
sfd__h28849[9] ||
sfd__h28849[8] ||
sfd__h28849[7] ||
sfd__h28849[6] ||
sfd__h28849[5] ||
sfd__h28849[4] ||
sfd__h28849[3] ||
sfd__h28849[2] ||
sfd__h28849[1] ||
sfd__h28849[0]) &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 &&
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1529 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574 =
requestR_BITS_191_TO_128__q1[31] ?
6'd0 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd1 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd31 :
6'd32))))))))))))))))))))))))))))))) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748 =
sV1_exp__h1472 - 8'd127 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
-b__h43158 :
b__h43158 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1774 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h43091 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[24] :
guard__h43091 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h43091 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88] &&
guard__h43091 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h43869 == 2'b10) ?
x__h44058[25] :
guard__h43869 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h43869 != 2'd0 :
requestR[194:192] == 3'h1 && x__h44058[88] &&
guard__h43869 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h45193 == 2'b10) ?
x__h45414[25] :
guard__h45193 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h45193 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1878 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd0 :
((sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1876) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868 &&
x__h45414[88:25] == 64'hFFFFFFFFFFFFFFFF) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1896 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890 } ==
5'd0 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
32'h80000000 :
32'h7FFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
-b__h46021 :
b__h46021 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1925 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h45954 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[24] :
guard__h45954 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h45954 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56] &&
guard__h45954 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h46508 == 2'b10) ?
x__h46697[25] :
guard__h46508 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h46508 != 2'd0 :
requestR[194:192] == 3'h1 && x__h46697[56] &&
guard__h46508 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h47594 == 2'b10) ?
x__h47815[25] :
guard__h47594 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h47594 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2024 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
32'd0 :
((sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0) ?
32'hFFFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2022) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014 &&
x__h47815[56:25] == 32'hFFFFFFFF) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2043 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037 } ==
5'd0 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22] &&
sV2_exp__h1597 == 8'd255 &&
sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2077 =
sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] &&
sV2_exp__h1597 == 8'd0 &&
sV2_sfd__h1598 == 23'd0 &&
(requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2081 =
sV2_exp__h1597 == 8'd0 && sV2_sfd__h1598 == 23'd0 &&
requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31] &&
sV1_exp__h1472 == 8'd0 &&
sV1_sfd__h1473 == 23'd0 &&
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 =
sV1_exp__h1472 < sV2_exp__h1597 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 =
sV1_exp__h1472 == sV2_exp__h1597 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092 =
sV1_sfd__h1473 < sV2_sfd__h1598 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 =
sV1_exp__h1472 <= sV2_exp__h1597 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097 =
sV1_sfd__h1473 <= sV2_sfd__h1598 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115 =
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22] ||
sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0 &&
!sV2_sfd__h1598[22] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22] ||
sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598[22] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2167 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097) &&
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171 =
sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0 &&
sV2_exp__h1597 == 8'd0 &&
sV2_sfd__h1598 == 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31]) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2169 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2496 =
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ||
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345) ?
52'd0 :
_theResult___snd_fst_sfd__h70875 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555 =
requestR_BITS_191_TO_128__q1[31] ?
6'd0 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd1 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd31 :
6'd55))))))))))))))))))))))))))))))) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2680 =
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560) ?
52'd0 :
_theResult___snd_fst_sfd__h81820 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719 =
requestR_BITS_191_TO_128__q1[63] ? 32'h80000000 : 32'h7FFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731 =
requestR_BITS_191_TO_128__q1[63] ? -b__h82525 : b__h82525 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2748 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h82458 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[53] :
guard__h82458 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h82458 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85] &&
guard__h82458 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h83012 == 2'b10) ?
x__h83201[54] :
guard__h83012 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h83012 != 2'd0 :
requestR[194:192] == 3'h1 && x__h83201[85] &&
guard__h83012 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2790 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'd0 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2788) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h84098 == 2'b10) ?
x__h84319[54] :
guard__h84098 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h84098 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2851 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'd0 :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822[23] ?
32'hFFFFFFFF :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2849) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2996 =
(requestR[191:128] == 64'd0 ||
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0]) ?
11'd0 :
_theResult___snd_fst_exp__h97202 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3045 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 &&
_theResult___fst_exp__h97193 == 11'd2047 &&
_theResult___fst_sfd__h97194 == 52'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3048 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3057 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 &&
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d3054 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220 =
requestR_BITS_191_TO_128__q1[63] ?
64'h8000000000000000 :
64'h7FFFFFFFFFFFFFFF ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224 =
requestR_BITS_191_TO_128__q1[63] ? -b__h110422 : b__h110422 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3241 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h110355 == 2'b10) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[53] :
guard__h110355 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h110355 != 2'd0 :
requestR[194:192] == 3'h1 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117] &&
guard__h110355 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h111133 == 2'b10) ?
x__h111322[54] :
guard__h111133 == 2'b11) :
((requestR[194:192] == 3'h3) ?
guard__h111133 != 2'd0 :
requestR[194:192] == 3'h1 && x__h111322[117] &&
guard__h111133 != 2'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3283 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'd0 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3281) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
((guard__h112440 == 2'b10) ?
x__h112661[54] :
guard__h112440 == 2'b11) :
requestR[194:192] == 3'h3 && guard__h112440 != 2'd0 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3337 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'd0 :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308[23] ?
64'hFFFFFFFFFFFFFFFF :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3335) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_191_TO_128__q1[30:0] :
31'h7FC00000 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 =
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(requestR_BITS_191_TO_128__q1[51] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[50] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[49] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[48] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[47] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[46] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[45] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[44] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[43] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[42] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[41] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[40] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[39] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[38] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[37] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[36] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[35] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[34] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[33] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[32] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[31] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd31 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd32 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd33 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd34 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd35 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd36 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd37 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd38 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd39 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd40 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd41 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd42 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd43 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd44 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd45 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd46 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd47 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd48 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd49 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd50 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd51 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd52 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd53 :
6'd57)))))))))))))))))))))))))))))))))))))))))))))))))))) :
6'd1) -
6'd1 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) ?
_theResult___snd_fst_sfd__h117207 :
_theResult___fst_sfd__h166273 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4378 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ?
IF_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_21_ETC___d4358 :
requestR_BITS_191_TO_128__q1[63]) :
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ?
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4376 :
requestR_BITS_191_TO_128__q1[63]) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4429 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4411 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 &&
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[4] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4440 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4436 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 &&
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 &&
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[3] ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4456 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4448 :
!SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ||
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4454 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4469 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4463 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 &&
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4467 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4482 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4476 :
!SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ||
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4480 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4617 =
sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0] ||
!_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5010 =
sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0] ||
!_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326 =
requestR_BITS_191_TO_128__q1[63] ?
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 &&
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318 :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5333 =
(requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51] ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302) ?
requestR[191:128] :
(IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306 ?
requestR[127:64] :
res__h217300) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5348 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302 ?
requestR[127:64] :
(IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306 ?
requestR[191:128] :
res__h221886) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5426 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
res___1__h230314 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
res___1__h230333 :
res__h230349) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d571 =
(requestR[191:128] == 64'd0 ||
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0]) ?
8'd0 :
_theResult___snd_fst_exp__h16093 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d684 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 &&
_theResult___fst_exp__h16084 == 8'd255 &&
_theResult___fst_sfd__h16085 == 23'd0) ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d687 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d696 =
(sfd__h3990[63] || sfd__h3990[62] || sfd__h3990[61] ||
sfd__h3990[60] ||
sfd__h3990[59] ||
sfd__h3990[58] ||
sfd__h3990[57] ||
sfd__h3990[56] ||
sfd__h3990[55] ||
sfd__h3990[54] ||
sfd__h3990[53] ||
sfd__h3990[52] ||
sfd__h3990[51] ||
sfd__h3990[50] ||
sfd__h3990[49] ||
sfd__h3990[48] ||
sfd__h3990[47] ||
sfd__h3990[46] ||
sfd__h3990[45] ||
sfd__h3990[44] ||
sfd__h3990[43] ||
sfd__h3990[42] ||
sfd__h3990[41] ||
sfd__h3990[40] ||
sfd__h3990[39] ||
sfd__h3990[38] ||
sfd__h3990[37] ||
sfd__h3990[36] ||
sfd__h3990[35] ||
sfd__h3990[34] ||
sfd__h3990[33] ||
sfd__h3990[32] ||
sfd__h3990[31] ||
sfd__h3990[30] ||
sfd__h3990[29] ||
sfd__h3990[28] ||
sfd__h3990[27] ||
sfd__h3990[26] ||
sfd__h3990[25] ||
sfd__h3990[24] ||
sfd__h3990[23] ||
sfd__h3990[22] ||
sfd__h3990[21] ||
sfd__h3990[20] ||
sfd__h3990[19] ||
sfd__h3990[18] ||
sfd__h3990[17] ||
sfd__h3990[16] ||
sfd__h3990[15] ||
sfd__h3990[14] ||
sfd__h3990[13] ||
sfd__h3990[12] ||
sfd__h3990[11] ||
sfd__h3990[10] ||
sfd__h3990[9] ||
sfd__h3990[8] ||
sfd__h3990[7] ||
sfd__h3990[6] ||
sfd__h3990[5] ||
sfd__h3990[4] ||
sfd__h3990[3] ||
sfd__h3990[2] ||
sfd__h3990[1] ||
sfd__h3990[0]) &&
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 &&
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 &&
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d693 ;
assign IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 =
requestR_BITS_191_TO_128__q1[63] ?
7'd0 :
(requestR_BITS_191_TO_128__q1[62] ?
7'd1 :
(requestR_BITS_191_TO_128__q1[61] ?
7'd2 :
(requestR_BITS_191_TO_128__q1[60] ?
7'd3 :
(requestR_BITS_191_TO_128__q1[59] ?
7'd4 :
(requestR_BITS_191_TO_128__q1[58] ?
7'd5 :
(requestR_BITS_191_TO_128__q1[57] ?
7'd6 :
(requestR_BITS_191_TO_128__q1[56] ?
7'd7 :
(requestR_BITS_191_TO_128__q1[55] ?
7'd8 :
(requestR_BITS_191_TO_128__q1[54] ?
7'd9 :
(requestR_BITS_191_TO_128__q1[53] ?
7'd10 :
(requestR_BITS_191_TO_128__q1[52] ?
7'd11 :
(requestR_BITS_191_TO_128__q1[51] ?
7'd12 :
(requestR_BITS_191_TO_128__q1[50] ?
7'd13 :
(requestR_BITS_191_TO_128__q1[49] ?
7'd14 :
(requestR_BITS_191_TO_128__q1[48] ?
7'd15 :
(requestR_BITS_191_TO_128__q1[47] ?
7'd16 :
(requestR_BITS_191_TO_128__q1[46] ?
7'd17 :
(requestR_BITS_191_TO_128__q1[45] ?
7'd18 :
(requestR_BITS_191_TO_128__q1[44] ?
7'd19 :
(requestR_BITS_191_TO_128__q1[43] ?
7'd20 :
(requestR_BITS_191_TO_128__q1[42] ?
7'd21 :
(requestR_BITS_191_TO_128__q1[41] ?
7'd22 :
(requestR_BITS_191_TO_128__q1[40] ?
7'd23 :
(requestR_BITS_191_TO_128__q1[39] ?
7'd24 :
(requestR_BITS_191_TO_128__q1[38] ?
7'd25 :
(requestR_BITS_191_TO_128__q1[37] ?
7'd26 :
(requestR_BITS_191_TO_128__q1[36] ?
7'd27 :
(requestR_BITS_191_TO_128__q1[35] ?
7'd28 :
(requestR_BITS_191_TO_128__q1[34] ?
7'd29 :
(requestR_BITS_191_TO_128__q1[33] ?
7'd30 :
(requestR_BITS_191_TO_128__q1[32] ?
7'd31 :
(requestR_BITS_191_TO_128__q1[31] ?
7'd32 :
(requestR_BITS_191_TO_128__q1[30] ?
7'd33 :
(requestR_BITS_191_TO_128__q1[29] ?
7'd34 :
(requestR_BITS_191_TO_128__q1[28] ?
7'd35 :
(requestR_BITS_191_TO_128__q1[27] ?
7'd36 :
(requestR_BITS_191_TO_128__q1[26] ?
7'd37 :
(requestR_BITS_191_TO_128__q1[25] ?
7'd38 :
(requestR_BITS_191_TO_128__q1[24] ?
7'd39 :
(requestR_BITS_191_TO_128__q1[23] ?
7'd40 :
(requestR_BITS_191_TO_128__q1[22] ?
7'd41 :
(requestR_BITS_191_TO_128__q1[21] ?
7'd42 :
(requestR_BITS_191_TO_128__q1[20] ?
7'd43 :
(requestR_BITS_191_TO_128__q1[19] ?
7'd44 :
(requestR_BITS_191_TO_128__q1[18] ?
7'd45 :
(requestR_BITS_191_TO_128__q1[17] ?
7'd46 :
(requestR_BITS_191_TO_128__q1[16] ?
7'd47 :
(requestR_BITS_191_TO_128__q1[15] ?
7'd48 :
(requestR_BITS_191_TO_128__q1[14] ?
7'd49 :
(requestR_BITS_191_TO_128__q1[13] ?
7'd50 :
(requestR_BITS_191_TO_128__q1[12] ?
7'd51 :
(requestR_BITS_191_TO_128__q1[11] ?
7'd52 :
(requestR_BITS_191_TO_128__q1[10] ?
7'd53 :
(requestR_BITS_191_TO_128__q1[9] ?
7'd54 :
(requestR_BITS_191_TO_128__q1[8] ?
7'd55 :
(requestR_BITS_191_TO_128__q1[7] ?
7'd56 :
(requestR_BITS_191_TO_128__q1[6] ?
7'd57 :
(requestR_BITS_191_TO_128__q1[5] ?
7'd58 :
(requestR_BITS_191_TO_128__q1[4] ?
7'd59 :
(requestR_BITS_191_TO_128__q1[3] ?
7'd60 :
(requestR_BITS_191_TO_128__q1[2] ?
7'd61 :
(requestR_BITS_191_TO_128__q1[1] ?
7'd62 :
(requestR_BITS_191_TO_128__q1[0] ?
7'd63 :
7'd64))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))))) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1812 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806 ?
((x__h44058[88:25] == 64'h7FFFFFFFFFFFFFFF) ?
x__h44058[88:25] :
x__h44058[88:25] + 64'd1) :
x__h44058[88:25]) :
64'd0 ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1814 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048513) ?
((_theResult_____2__h43093[64:63] == 2'b11) ?
_theResult_____2__h43093[63:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745) :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783[19] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1745 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1812) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1837 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048513) ?
_theResult_____2__h43093[64:63] == 2'b11 &&
guard__h43091 != 2'd0 :
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 ||
guard__h43869 != 2'd0) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1874 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1868 ?
((x__h45414[88:25] == 64'hFFFFFFFFFFFFFFFF) ?
x__h45414[88:25] :
x__h45414[88:25] + 64'd1) :
x__h45414[88:25]) :
64'd0 ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1963 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957 ?
((x__h46697[56:25] == 32'h7FFFFFFF) ?
x__h46697[56:25] :
x__h46697[56:25] + 32'd1) :
x__h46697[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1965 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048545) ?
((_theResult_____2__h45956[32:31] == 2'b11) ?
_theResult_____2__h45956[31:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904) :
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934[19] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1904 :
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1963) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1983 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048545) ?
_theResult_____2__h45956[32:31] == 2'b11 &&
guard__h45954 != 2'd0 :
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 ||
guard__h46508 != 2'd0) ;
assign IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d2020 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2014 ?
((x__h47815[56:25] == 32'hFFFFFFFF) ?
x__h47815[56:25] :
x__h47815[56:25] + 32'd1) :
x__h47815[56:25]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2786 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780 ?
((x__h83201[85:54] == 32'h7FFFFFFF) ?
x__h83201[85:54] :
x__h83201[85:54] + 32'd1) :
x__h83201[85:54]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2788 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777185) ?
((_theResult_____2__h82460[32:31] == 2'b11) ?
_theResult_____2__h82460[31:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719) :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757[23] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2719 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2786) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2812 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777185) ?
_theResult_____2__h82460[32:31] == 2'b11 &&
guard__h82458 != 2'd0 :
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 ||
guard__h83012 != 2'd0) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2849 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843 ?
((x__h84319[85:54] == 32'hFFFFFFFF) ?
x__h84319[85:54] :
x__h84319[85:54] + 32'd1) :
x__h84319[85:54]) :
32'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3279 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273 ?
((x__h111322[117:54] == 64'h7FFFFFFFFFFFFFFF) ?
x__h111322[117:54] :
x__h111322[117:54] + 64'd1) :
x__h111322[117:54]) :
64'd0 ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3281 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777153) ?
((_theResult_____2__h110357[64:63] == 2'b11) ?
_theResult_____2__h110357[63:0] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220) :
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250[23] ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3220 :
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3279) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3298 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777153) ?
_theResult_____2__h110357[64:63] == 2'b11 &&
guard__h110355 != 2'd0 :
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 ||
guard__h111133 != 2'd0) ;
assign IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3335 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 ?
(IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329 ?
((x__h112661[117:54] == 64'hFFFFFFFFFFFFFFFF) ?
x__h112661[117:54] :
x__h112661[117:54] + 64'd1) :
x__h112661[117:54]) :
64'd0 ;
assign IF_NOT_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_B_ETC___d2399 =
(!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ||
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345) ?
requestR_BITS_191_TO_128__q1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2398 ;
assign IF_NOT_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_ETC___d5169 =
(!_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ||
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ||
_theResult___fst_exp__h190506 == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166) ;
assign IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2106 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 ?
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 ;
assign IF_NOT_IF_IF_requestR_3_BIT_214_4_THEN_request_ETC___d2122 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 :
{ requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign IF_NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2101 =
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092 :
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 &&
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007 =
((SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] ==
11'd0) ?
12'd3074 :
{ SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156[10],
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156 }) -
12'd3074 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5186 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
((_theResult___fst_exp__h201334 == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168)) :
((_theResult___fst_exp__h211398 == 11'd2047) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170)) ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5246 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[2] :
_theResult___fst_exp__h212179 == 11'd2047 &&
_theResult___fst_sfd__h212180 == 52'd0 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5258 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[1] :
_theResult___fst_exp__h211398 == 11'd0 &&
guard__h202175 != 2'b0 ;
assign IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5270 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220[0] :
_theResult___fst_exp__h211398 != 11'd2047 &&
guard__h202175 != 2'b0 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172 =
((SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] ==
8'd0) ?
9'd386 :
{ SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124[7],
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124 }) -
9'd386 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4376 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
((_theResult___fst_exp__h155731 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148)) :
((_theResult___fst_exp__h165679 == 8'd255) ?
requestR_BITS_191_TO_128__q1[63] :
((requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149 :
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150)) ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4454 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[2] :
_theResult___fst_exp__h166257 == 8'd255 &&
_theResult___fst_sfd__h166258 == 23'd0 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4467 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[1] :
_theResult___fst_exp__h165679 == 8'd0 &&
guard__h156369 != 2'b0 ;
assign IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4480 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425[0] :
_theResult___fst_exp__h165679 != 8'd255 &&
guard__h156369 != 2'b0 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1165 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 &&
_theResult___fst_exp__h28360 == 8'd255 &&
_theResult___fst_sfd__h28361 == 23'd0) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1168 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1177 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 &&
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1174 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1709 =
(requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 &&
_theResult___fst_exp__h42448 == 8'd255 &&
_theResult___fst_sfd__h42449 == 23'd0) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1712 =
(requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1721 =
(requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d1718 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] &&
(requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) ||
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) &&
IF_NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2101 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2169 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31]) &&
((requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) ?
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2166 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2167) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722 =
requestR_BITS_191_TO_128__q1[62:52] - 11'd1023 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2843 &&
x__h84319[85:54] == 32'hFFFFFFFF) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2872 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866 } ==
5'd0 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3199 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
(!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 &&
_theResult___fst_exp__h109716 == 11'd2047 &&
_theResult___fst_sfd__h109717 == 52'd0) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3202 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3211 =
(requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_191_TO_128__q1[62] ||
requestR_BITS_191_TO_128__q1[61] ||
requestR_BITS_191_TO_128__q1[60] ||
requestR_BITS_191_TO_128__q1[59] ||
requestR_BITS_191_TO_128__q1[58] ||
requestR_BITS_191_TO_128__q1[57] ||
requestR_BITS_191_TO_128__q1[56] ||
requestR_BITS_191_TO_128__q1[55] ||
requestR_BITS_191_TO_128__q1[54] ||
requestR_BITS_191_TO_128__q1[53] ||
requestR_BITS_191_TO_128__q1[52] ||
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_191_TO_128__q1[50] ||
requestR_BITS_191_TO_128__q1[49] ||
requestR_BITS_191_TO_128__q1[48] ||
requestR_BITS_191_TO_128__q1[47] ||
requestR_BITS_191_TO_128__q1[46] ||
requestR_BITS_191_TO_128__q1[45] ||
requestR_BITS_191_TO_128__q1[44] ||
requestR_BITS_191_TO_128__q1[43] ||
requestR_BITS_191_TO_128__q1[42] ||
requestR_BITS_191_TO_128__q1[41] ||
requestR_BITS_191_TO_128__q1[40] ||
requestR_BITS_191_TO_128__q1[39] ||
requestR_BITS_191_TO_128__q1[38] ||
requestR_BITS_191_TO_128__q1[37] ||
requestR_BITS_191_TO_128__q1[36] ||
requestR_BITS_191_TO_128__q1[35] ||
requestR_BITS_191_TO_128__q1[34] ||
requestR_BITS_191_TO_128__q1[33] ||
requestR_BITS_191_TO_128__q1[32] ||
requestR_BITS_191_TO_128__q1[31] ||
requestR_BITS_191_TO_128__q1[30] ||
requestR_BITS_191_TO_128__q1[29] ||
requestR_BITS_191_TO_128__q1[28] ||
requestR_BITS_191_TO_128__q1[27] ||
requestR_BITS_191_TO_128__q1[26] ||
requestR_BITS_191_TO_128__q1[25] ||
requestR_BITS_191_TO_128__q1[24] ||
requestR_BITS_191_TO_128__q1[23] ||
requestR_BITS_191_TO_128__q1[22] ||
requestR_BITS_191_TO_128__q1[21] ||
requestR_BITS_191_TO_128__q1[20] ||
requestR_BITS_191_TO_128__q1[19] ||
requestR_BITS_191_TO_128__q1[18] ||
requestR_BITS_191_TO_128__q1[17] ||
requestR_BITS_191_TO_128__q1[16] ||
requestR_BITS_191_TO_128__q1[15] ||
requestR_BITS_191_TO_128__q1[14] ||
requestR_BITS_191_TO_128__q1[13] ||
requestR_BITS_191_TO_128__q1[12] ||
requestR_BITS_191_TO_128__q1[11] ||
requestR_BITS_191_TO_128__q1[10] ||
requestR_BITS_191_TO_128__q1[9] ||
requestR_BITS_191_TO_128__q1[8] ||
requestR_BITS_191_TO_128__q1[7] ||
requestR_BITS_191_TO_128__q1[6] ||
requestR_BITS_191_TO_128__q1[5] ||
requestR_BITS_191_TO_128__q1[4] ||
requestR_BITS_191_TO_128__q1[3] ||
requestR_BITS_191_TO_128__q1[2] ||
requestR_BITS_191_TO_128__q1[1] ||
requestR_BITS_191_TO_128__q1[0]) &&
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 &&
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 &&
IF_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d3208 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3329 &&
x__h112661[117:54] == 64'hFFFFFFFFFFFFFFFF) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3357 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351 } ==
5'd0 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346 ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 =
{ requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31],
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_127_TO_64__q3[30:0] :
31'h7FC00000 } ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5302 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 &&
requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd0 &&
requestR_BITS_127_TO_64__q3[51:0] == 52'd0 &&
!requestR_BITS_127_TO_64__q3[63] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5306 =
requestR_BITS_127_TO_64__q3[62:52] == 11'd0 &&
requestR_BITS_127_TO_64__q3[51:0] == 52'd0 &&
requestR_BITS_127_TO_64__q3[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 &&
!requestR_BITS_191_TO_128__q1[63] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 =
requestR_BITS_191_TO_128__q1[62:52] <=
requestR_BITS_127_TO_64__q3[62:52] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 =
requestR_BITS_191_TO_128__q1[62:52] ==
requestR_BITS_127_TO_64__q3[62:52] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318 =
requestR_BITS_191_TO_128__q1[51:0] <=
requestR_BITS_127_TO_64__q3[51:0] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 =
requestR_BITS_191_TO_128__q1[62:52] <
requestR_BITS_127_TO_64__q3[62:52] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323 =
requestR_BITS_191_TO_128__q1[51:0] <
requestR_BITS_127_TO_64__q3[51:0] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51] ||
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51] ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5373 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318) &&
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323) ;
assign IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378 =
requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd0 &&
requestR_BITS_127_TO_64__q3[51:0] == 52'd0 ||
(!requestR_BITS_191_TO_128__q1[63] ||
requestR_BITS_127_TO_64__q3[63]) &&
(requestR_BITS_191_TO_128__q1[63] ||
!requestR_BITS_127_TO_64__q3[63]) &&
(requestR_BITS_191_TO_128__q1[63] ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5373 :
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5374) ;
assign IF_sfd___30336_BIT_1_THEN_2_ELSE_0__q85 =
sfd___3__h80336[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___30336_BIT_2_THEN_2_ELSE_0__q84 =
sfd___3__h80336[2] ? 2'd2 : 2'd0 ;
assign IF_sfd___31374_BIT_7_THEN_2_ELSE_0__q56 =
sfd___3__h41374[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___31374_BIT_8_THEN_2_ELSE_0__q55 =
sfd___3__h41374[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___34458_BIT_7_THEN_2_ELSE_0__q42 =
sfd___3__h34458[7] ? 2'd2 : 2'd0 ;
assign IF_sfd___34458_BIT_8_THEN_2_ELSE_0__q41 =
sfd___3__h34458[8] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_10_THEN_2_ELSE_0__q12 =
sfd___3__h15005[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_11_THEN_2_ELSE_0__q11 =
sfd___3__h15005[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_39_THEN_2_ELSE_0__q10 =
sfd___3__h15005[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___35005_BIT_40_THEN_2_ELSE_0__q9 =
sfd___3__h15005[40] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_10_THEN_2_ELSE_0__q28 =
sfd___3__h27286[10] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_11_THEN_2_ELSE_0__q27 =
sfd___3__h27286[11] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_39_THEN_2_ELSE_0__q26 =
sfd___3__h27286[39] ? 2'd2 : 2'd0 ;
assign IF_sfd___37286_BIT_40_THEN_2_ELSE_0__q25 =
sfd___3__h27286[40] ? 2'd2 : 2'd0 ;
assign IF_sfd___39389_BIT_1_THEN_2_ELSE_0__q71 =
sfd___3__h69389[1] ? 2'd2 : 2'd0 ;
assign IF_sfd___39389_BIT_2_THEN_2_ELSE_0__q70 =
sfd___3__h69389[2] ? 2'd2 : 2'd0 ;
assign IF_sfdin01328_BIT_4_THEN_2_ELSE_0__q155 =
sfdin__h201328[4] ? 2'd2 : 2'd0 ;
assign IF_sfdin35384_BIT_33_THEN_2_ELSE_0__q118 =
sfdin__h135384[33] ? 2'd2 : 2'd0 ;
assign IF_sfdin55725_BIT_33_THEN_2_ELSE_0__q123 =
sfdin__h155725[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd11344_BIT_4_THEN_2_ELSE_0__q158 =
_theResult___snd__h211344[4] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd45260_BIT_33_THEN_2_ELSE_0__q120 =
_theResult___snd__h145260[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd65625_BIT_33_THEN_2_ELSE_0__q126 =
_theResult___snd__h165625[33] ? 2'd2 : 2'd0 ;
assign IF_theResult___snd90457_BIT_4_THEN_2_ELSE_0__q152 =
_theResult___snd__h190457[4] ? 2'd2 : 2'd0 ;
assign IF_x11322_BIT_53_THEN_2_ELSE_0__q115 = x__h111322[53] ? 2'd2 : 2'd0 ;
assign IF_x12661_BIT_53_THEN_2_ELSE_0__q116 = x__h112661[53] ? 2'd2 : 2'd0 ;
assign IF_x3201_BIT_53_THEN_2_ELSE_0__q95 = x__h83201[53] ? 2'd2 : 2'd0 ;
assign IF_x4058_BIT_24_THEN_2_ELSE_0__q66 = x__h44058[24] ? 2'd2 : 2'd0 ;
assign IF_x4319_BIT_53_THEN_2_ELSE_0__q96 = x__h84319[53] ? 2'd2 : 2'd0 ;
assign IF_x5414_BIT_24_THEN_2_ELSE_0__q67 = x__h45414[24] ? 2'd2 : 2'd0 ;
assign IF_x6697_BIT_24_THEN_2_ELSE_0__q68 = x__h46697[24] ? 2'd2 : 2'd0 ;
assign IF_x7815_BIT_24_THEN_2_ELSE_0__q69 = x__h47815[24] ? 2'd2 : 2'd0 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 =
-{ {12{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748[7]}},
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748 } ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 +
20'd64 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782 -
20'd2 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783 ^
20'h80000) <=
20'd524352 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1782 -
20'd1 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847 ^
20'h80000) <=
20'd524352 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 +
20'd32 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933 -
20'd2 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993 =
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1933 -
20'd1 ;
assign NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 =
(NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993 ^
20'h80000) <=
20'd524320 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 =
-{ {13{IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722[10]}},
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722 } ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 +
24'd32 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756 -
24'd2 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757 ^
24'h800000) <=
24'd8388640 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2756 -
24'd1 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822 ^
24'h800000) <=
24'd8388640 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 +
24'd64 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249 -
24'd2 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250 ^
24'h800000) <=
24'd8388672 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308 =
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3249 -
24'd1 ;
assign NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 =
(NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308 ^
24'h800000) <=
24'd8388672 ;
assign NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4448 =
!_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ||
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[2] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[2]) ;
assign NOT_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_2_ETC___d4476 =
!_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ||
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[0] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[0]) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326 =
!sfd__h28849[31] && !sfd__h28849[30] && !sfd__h28849[29] &&
!sfd__h28849[28] &&
!sfd__h28849[27] &&
!sfd__h28849[26] &&
!sfd__h28849[25] &&
!sfd__h28849[24] &&
!sfd__h28849[23] &&
!sfd__h28849[22] &&
!sfd__h28849[21] &&
!sfd__h28849[20] &&
!sfd__h28849[19] &&
!sfd__h28849[18] &&
!sfd__h28849[17] &&
!sfd__h28849[16] &&
!sfd__h28849[15] &&
!sfd__h28849[14] &&
!sfd__h28849[13] &&
!sfd__h28849[12] &&
!sfd__h28849[11] &&
!sfd__h28849[10] &&
!sfd__h28849[9] &&
!sfd__h28849[8] &&
!sfd__h28849[7] &&
!sfd__h28849[6] &&
!sfd__h28849[5] &&
!sfd__h28849[4] &&
!sfd__h28849[3] &&
!sfd__h28849[2] &&
!sfd__h28849[1] &&
!sfd__h28849[0] ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 ||
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1826 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
((NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048513) ?
_theResult_____2__h43093[64:63] != 2'b11 :
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1785 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1806 &&
x__h44058[88:25] == 64'h7FFFFFFFFFFFFFFF) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1849 ||
guard__h45193 != 2'd0) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1975 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
((NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1750 ==
20'd1048545) ?
_theResult_____2__h45956[32:31] != 2'b11 :
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934[19] ||
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1936 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1957 &&
x__h46697[56:25] == 32'h7FFFFFFF) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993[19] &&
(!NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1995 ||
guard__h47594 != 2'd0) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2104 =
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0 ||
sV2_exp__h1597 != 8'd0 ||
sV2_sfd__h1598 != 23'd0) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 =
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV2_exp__h1597 != 8'd255 || sV2_sfd__h1598 == 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2104 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2166 =
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2090 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2092) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2095 &&
(!IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2091 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2097) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2172 =
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV2_exp__h1597 != 8'd255 || sV2_sfd__h1598 == 23'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2192 =
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV2_exp__h1597 != 8'd255 || sV2_sfd__h1598 == 23'd0) &&
(IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2103 ||
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2171) ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887 =
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0] ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 ||
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 ;
assign NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449 =
!sfd__h3990[63] && !sfd__h3990[62] && !sfd__h3990[61] &&
!sfd__h3990[60] &&
!sfd__h3990[59] &&
!sfd__h3990[58] &&
!sfd__h3990[57] &&
!sfd__h3990[56] &&
!sfd__h3990[55] &&
!sfd__h3990[54] &&
!sfd__h3990[53] &&
!sfd__h3990[52] &&
!sfd__h3990[51] &&
!sfd__h3990[50] &&
!sfd__h3990[49] &&
!sfd__h3990[48] &&
!sfd__h3990[47] &&
!sfd__h3990[46] &&
!sfd__h3990[45] &&
!sfd__h3990[44] &&
!sfd__h3990[43] &&
!sfd__h3990[42] &&
!sfd__h3990[41] &&
!sfd__h3990[40] &&
!sfd__h3990[39] &&
!sfd__h3990[38] &&
!sfd__h3990[37] &&
!sfd__h3990[36] &&
!sfd__h3990[35] &&
!sfd__h3990[34] &&
!sfd__h3990[33] &&
!sfd__h3990[32] &&
!sfd__h3990[31] &&
!sfd__h3990[30] &&
!sfd__h3990[29] &&
!sfd__h3990[28] &&
!sfd__h3990[27] &&
!sfd__h3990[26] &&
!sfd__h3990[25] &&
!sfd__h3990[24] &&
!sfd__h3990[23] &&
!sfd__h3990[22] &&
!sfd__h3990[21] &&
!sfd__h3990[20] &&
!sfd__h3990[19] &&
!sfd__h3990[18] &&
!sfd__h3990[17] &&
!sfd__h3990[16] &&
!sfd__h3990[15] &&
!sfd__h3990[14] &&
!sfd__h3990[13] &&
!sfd__h3990[12] &&
!sfd__h3990[11] &&
!sfd__h3990[10] &&
!sfd__h3990[9] &&
!sfd__h3990[8] &&
!sfd__h3990[7] &&
!sfd__h3990[6] &&
!sfd__h3990[5] &&
!sfd__h3990[4] &&
!sfd__h3990[3] &&
!sfd__h3990[2] &&
!sfd__h3990[1] &&
!sfd__h3990[0] ||
!_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 ||
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1059 =
!requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_191_TO_128__q1[62] &&
!requestR_BITS_191_TO_128__q1[61] &&
!requestR_BITS_191_TO_128__q1[60] &&
!requestR_BITS_191_TO_128__q1[59] &&
!requestR_BITS_191_TO_128__q1[58] &&
!requestR_BITS_191_TO_128__q1[57] &&
!requestR_BITS_191_TO_128__q1[56] &&
!requestR_BITS_191_TO_128__q1[55] &&
!requestR_BITS_191_TO_128__q1[54] &&
!requestR_BITS_191_TO_128__q1[53] &&
!requestR_BITS_191_TO_128__q1[52] &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 ||
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1666 =
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 ||
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2801 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
((NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777185) ?
_theResult_____2__h82460[32:31] != 2'b11 :
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2759 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2780 &&
x__h83201[85:54] == 32'h7FFFFFFF) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2824 ||
guard__h84098 != 2'd0) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3156 =
!requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_191_TO_128__q1[62] &&
!requestR_BITS_191_TO_128__q1[61] &&
!requestR_BITS_191_TO_128__q1[60] &&
!requestR_BITS_191_TO_128__q1[59] &&
!requestR_BITS_191_TO_128__q1[58] &&
!requestR_BITS_191_TO_128__q1[57] &&
!requestR_BITS_191_TO_128__q1[56] &&
!requestR_BITS_191_TO_128__q1[55] &&
!requestR_BITS_191_TO_128__q1[54] &&
!requestR_BITS_191_TO_128__q1[53] &&
!requestR_BITS_191_TO_128__q1[52] &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 ||
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3290 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
((NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2724 ==
24'd16777153) ?
_theResult_____2__h110357[64:63] != 2'b11 :
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250[23] ||
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3252 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3273 &&
x__h111322[117:54] == 64'h7FFFFFFFFFFFFFFF) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308[23] &&
(!NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3310 ||
guard__h112440 != 2'd0) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_127_TO_64__q3[62:52] != 11'd2047 ||
requestR_BITS_127_TO_64__q3[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_127_TO_64__q3[62:52] != 11'd0 ||
requestR_BITS_127_TO_64__q3[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_127_TO_64__q3[63] ||
(requestR_BITS_191_TO_128__q1[63] ||
!requestR_BITS_127_TO_64__q3[63]) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5374 =
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5322 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5323) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5315 &&
(!IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5317 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5318) ;
assign NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5399 =
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_127_TO_64__q3[62:52] != 11'd2047 ||
requestR_BITS_127_TO_64__q3[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[63] &&
!requestR_BITS_127_TO_64__q3[63] ||
(requestR_BITS_191_TO_128__q1[63] ||
!requestR_BITS_127_TO_64__q3[63]) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5326 ||
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378) ;
assign NOT_verbosity_ULE_1_6___d27 = verbosity > 4'd1 ;
assign NOT_verbosity_ULE_2_01___d702 = verbosity > 4'd2 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 =
{ {4{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748[7]}},
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1748 } ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 =
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 ^
12'h800) <=
12'd3071 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 =
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 ^
12'h800) <
12'd1026 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 +
12'd1023 ;
assign SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q156 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] -
11'd1023 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722[10],
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2722 } ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 =
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 ^
12'h800) <=
12'd2175 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 =
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 ^
12'h800) <
12'd1922 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 +
12'd127 ;
assign SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q124 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] -
8'd127 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656 =
({ 3'd0,
IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396 =
{ 3'd0,
_theResult___fst_exp__h135390 == 8'd0 &&
(sfdin__h135384[56:34] == 23'd0 || guard__h126038 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h136017 == 8'd255 &&
_theResult___fst_sfd__h136018 == 23'd0,
1'd0,
_theResult___fst_exp__h135390 != 8'd255 &&
guard__h126038 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935 =
({ 6'd0,
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 } ^
12'h800) <=
12'd2048 ;
assign _0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d5220 =
{ 3'd0,
_theResult___fst_exp__h201334 == 11'd0 &&
(sfdin__h201328[56:5] == 52'd0 || guard__h191853 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h202164 == 11'd2047 &&
_theResult___fst_sfd__h202165 == 52'd0,
1'd0,
_theResult___fst_exp__h201334 != 11'd2047 &&
guard__h191853 != 2'b0 } ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100 =
({ 3'd0,
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 } ^
9'h100) <=
9'd256 ;
assign _0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4425 =
{ 3'd0,
_theResult___fst_exp__h155731 == 8'd0 &&
(sfdin__h155725[56:34] == 23'd0 || guard__h146250 != 2'b0),
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h156358 == 8'd255 &&
_theResult___fst_sfd__h156359 == 23'd0,
1'd0,
_theResult___fst_exp__h155731 != 8'd255 &&
guard__h146250 != 2'b0 } ;
assign _0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d4615 =
({ 6'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ^
12'h800) <=
12'd2944 ;
assign _0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5008 =
({ 6'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ^
12'h800) <=
(IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007 ^
12'h800) ;
assign _0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d5203 =
{ 3'd0,
_theResult___fst_exp__h190506 == 11'd0 &&
guard__h181312 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h191262 == 11'd2047 &&
_theResult___fst_sfd__h191263 == 52'd0,
1'd0,
_theResult___fst_exp__h190506 != 11'd2047 &&
guard__h181312 != 2'b0 } ;
assign _0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778 =
({ 3'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ^
9'h100) <=
9'd384 ;
assign _0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173 =
({ 3'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ^
9'h100) <=
(IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172 ^
9'h100) ;
assign _0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408 =
{ 3'd0,
_theResult___fst_exp__h145309 == 8'd0 &&
guard__h136028 != 2'b0,
1'd0 } |
{ 2'd0,
_theResult___fst_exp__h145862 == 8'd255 &&
_theResult___fst_sfd__h145863 == 23'd0,
1'd0,
_theResult___fst_exp__h145309 != 8'd255 &&
guard__h136028 != 2'b0 } ;
assign _0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691 =
b__h46021 >>
_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 ;
assign _0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858 =
sfd__h117253 >>
_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 ;
assign _1_CONCAT_DONTCARE_CONCAT_IF_requestR_3_BIT_214_ETC___d97 =
{ 33'h1AAAAAAAA,
requestR_BITS_63_TO_0__q8[63:32] == 32'hFFFFFFFF &&
requestR_BITS_63_TO_0__q8[31],
(requestR_BITS_63_TO_0__q8[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_63_TO_0__q8[30:0] :
31'h7FC00000 } ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420 =
12'd3074 -
{ 6'd0,
requestR_BITS_191_TO_128__q1[51] ?
6'd0 :
(requestR_BITS_191_TO_128__q1[50] ?
6'd1 :
(requestR_BITS_191_TO_128__q1[49] ?
6'd2 :
(requestR_BITS_191_TO_128__q1[48] ?
6'd3 :
(requestR_BITS_191_TO_128__q1[47] ?
6'd4 :
(requestR_BITS_191_TO_128__q1[46] ?
6'd5 :
(requestR_BITS_191_TO_128__q1[45] ?
6'd6 :
(requestR_BITS_191_TO_128__q1[44] ?
6'd7 :
(requestR_BITS_191_TO_128__q1[43] ?
6'd8 :
(requestR_BITS_191_TO_128__q1[42] ?
6'd9 :
(requestR_BITS_191_TO_128__q1[41] ?
6'd10 :
(requestR_BITS_191_TO_128__q1[40] ?
6'd11 :
(requestR_BITS_191_TO_128__q1[39] ?
6'd12 :
(requestR_BITS_191_TO_128__q1[38] ?
6'd13 :
(requestR_BITS_191_TO_128__q1[37] ?
6'd14 :
(requestR_BITS_191_TO_128__q1[36] ?
6'd15 :
(requestR_BITS_191_TO_128__q1[35] ?
6'd16 :
(requestR_BITS_191_TO_128__q1[34] ?
6'd17 :
(requestR_BITS_191_TO_128__q1[33] ?
6'd18 :
(requestR_BITS_191_TO_128__q1[32] ?
6'd19 :
(requestR_BITS_191_TO_128__q1[31] ?
6'd20 :
(requestR_BITS_191_TO_128__q1[30] ?
6'd21 :
(requestR_BITS_191_TO_128__q1[29] ?
6'd22 :
(requestR_BITS_191_TO_128__q1[28] ?
6'd23 :
(requestR_BITS_191_TO_128__q1[27] ?
6'd24 :
(requestR_BITS_191_TO_128__q1[26] ?
6'd25 :
(requestR_BITS_191_TO_128__q1[25] ?
6'd26 :
(requestR_BITS_191_TO_128__q1[24] ?
6'd27 :
(requestR_BITS_191_TO_128__q1[23] ?
6'd28 :
(requestR_BITS_191_TO_128__q1[22] ?
6'd29 :
(requestR_BITS_191_TO_128__q1[21] ?
6'd30 :
(requestR_BITS_191_TO_128__q1[20] ?
6'd31 :
(requestR_BITS_191_TO_128__q1[19] ?
6'd32 :
(requestR_BITS_191_TO_128__q1[18] ?
6'd33 :
(requestR_BITS_191_TO_128__q1[17] ?
6'd34 :
(requestR_BITS_191_TO_128__q1[16] ?
6'd35 :
(requestR_BITS_191_TO_128__q1[15] ?
6'd36 :
(requestR_BITS_191_TO_128__q1[14] ?
6'd37 :
(requestR_BITS_191_TO_128__q1[13] ?
6'd38 :
(requestR_BITS_191_TO_128__q1[12] ?
6'd39 :
(requestR_BITS_191_TO_128__q1[11] ?
6'd40 :
(requestR_BITS_191_TO_128__q1[10] ?
6'd41 :
(requestR_BITS_191_TO_128__q1[9] ?
6'd42 :
(requestR_BITS_191_TO_128__q1[8] ?
6'd43 :
(requestR_BITS_191_TO_128__q1[7] ?
6'd44 :
(requestR_BITS_191_TO_128__q1[6] ?
6'd45 :
(requestR_BITS_191_TO_128__q1[5] ?
6'd46 :
(requestR_BITS_191_TO_128__q1[4] ?
6'd47 :
(requestR_BITS_191_TO_128__q1[3] ?
6'd48 :
(requestR_BITS_191_TO_128__q1[2] ?
6'd49 :
(requestR_BITS_191_TO_128__q1[1] ?
6'd50 :
(requestR_BITS_191_TO_128__q1[0] ?
6'd51 :
6'd52))))))))))))))))))))))))))))))))))))))))))))))))))) } ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 =
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420 ^
12'h800) <=
12'd2175 ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 =
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3420 ^
12'h800) <
12'd1922 ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4411 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 &&
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[4] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[4]) ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4436 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 &&
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[3] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[3]) ;
assign _3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d4463 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 &&
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d4396[1] :
_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4408[1]) ;
assign _3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 =
12'd3074 -
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4684 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 =
(9'd32 -
{ 3'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 =
(12'd32 -
{ 6'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 =
(_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 ^
12'h800) <
12'd1026 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 =
(9'd32 -
{ 3'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574 }) -
9'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 ^
9'h100) <=
9'd383 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 ^
9'h100) <
9'd107 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 ^
9'h100) <
9'd130 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 =
(12'd32 -
{ 6'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555 }) -
12'd1 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 ^
12'h800) <=
12'd3071 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 ^
12'h800) <
12'd974 ;
assign _32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 =
(_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541 =
12'd3970 -
{ 7'd0,
sV1_sfd__h1473[22] ?
5'd0 :
(sV1_sfd__h1473[21] ?
5'd1 :
(sV1_sfd__h1473[20] ?
5'd2 :
(sV1_sfd__h1473[19] ?
5'd3 :
(sV1_sfd__h1473[18] ?
5'd4 :
(sV1_sfd__h1473[17] ?
5'd5 :
(sV1_sfd__h1473[16] ?
5'd6 :
(sV1_sfd__h1473[15] ?
5'd7 :
(sV1_sfd__h1473[14] ?
5'd8 :
(sV1_sfd__h1473[13] ?
5'd9 :
(sV1_sfd__h1473[12] ?
5'd10 :
(sV1_sfd__h1473[11] ?
5'd11 :
(sV1_sfd__h1473[10] ?
5'd12 :
(sV1_sfd__h1473[9] ?
5'd13 :
(sV1_sfd__h1473[8] ?
5'd14 :
(sV1_sfd__h1473[7] ?
5'd15 :
(sV1_sfd__h1473[6] ?
5'd16 :
(sV1_sfd__h1473[5] ?
5'd17 :
(sV1_sfd__h1473[4] ?
5'd18 :
(sV1_sfd__h1473[3] ?
5'd19 :
(sV1_sfd__h1473[2] ?
5'd20 :
(sV1_sfd__h1473[1] ?
5'd21 :
(sV1_sfd__h1473[0] ?
5'd22 :
5'd23)))))))))))))))))))))) } ;
assign _3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 =
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541 ^
12'h800) <=
12'd3071 ;
assign _3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 =
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4541 ^
12'h800) <
12'd1026 ;
assign _3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 =
12'd3970 -
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3851 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 =
(12'd64 -
{ 5'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 =
(9'd64 -
{ 2'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 =
(_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 ^
9'h100) <
9'd130 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 =
(12'd64 -
{ 5'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 }) -
12'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 ^
12'h800) <=
12'd3071 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 ^
12'h800) <
12'd974 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 ^
12'h800) <
12'd1026 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 =
(9'd64 -
{ 2'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 }) -
9'd1 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 ^
9'h100) <=
9'd383 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 ^
9'h100) <
9'd107 ;
assign _64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 =
(_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 ^
9'h100) <
9'd130 ;
assign _theResult_____2__h110357 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3241 ?
out1___1__h111073 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117:53] ;
assign _theResult_____2__h43093 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1774 ?
out1___1__h43809 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88:24] ;
assign _theResult_____2__h45956 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1925 ?
out1___1__h46448 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56:24] ;
assign _theResult_____2__h82460 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2748 ?
out1___1__h82952 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85:53] ;
assign _theResult____h126028 =
(value__h82527 == 54'd0) ? sfd__h117253 : 57'd1 ;
assign _theResult____h146240 =
((_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 ^
12'h800) <
12'd2105) ?
result__h146853 :
_theResult____h126028 ;
assign _theResult____h191843 =
((_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 ^
12'h800) <
12'd2105) ?
result__h192456 :
((value__h43160 == 25'd0) ? b__h46021 : 57'd1) ;
assign _theResult___exp__h108862 =
(sfd__h108263[53] || sfd__h108263[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h109617 =
sfd__h109005[53] ?
((x__h108990[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h109755) :
((x__h108990[10:0] == 11'd0 && sfd__h109005[53:52] == 2'b01) ?
11'd1 :
x__h108990[10:0]) ;
assign _theResult___exp__h135916 =
sfd__h135482[24] ?
((_theResult___fst_exp__h135390 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166288) :
((_theResult___fst_exp__h135390 == 8'd0 &&
sfd__h135482[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h135390) ;
assign _theResult___exp__h145761 =
sfd__h145327[24] ?
((_theResult___fst_exp__h145309 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166312) :
((_theResult___fst_exp__h145309 == 8'd0 &&
sfd__h145327[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h145309) ;
assign _theResult___exp__h15431 =
(sfd__h15032[24] || sfd__h15032[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h156257 =
sfd__h155823[24] ?
((_theResult___fst_exp__h155731 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166342) :
((_theResult___fst_exp__h155731 == 8'd0 &&
sfd__h155823[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h155731) ;
assign _theResult___exp__h15984 =
sfd__h15575[24] ?
((x__h15560[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h16127) :
((x__h15560[7:0] == 8'd0 && sfd__h15575[24:23] == 2'b01) ?
8'd1 :
x__h15560[7:0]) ;
assign _theResult___exp__h166156 =
sfd__h165698[24] ?
((_theResult___fst_exp__h165679 == 8'd254) ?
8'd255 :
din_inc___2_exp__h166366) :
((_theResult___fst_exp__h165679 == 8'd0 &&
sfd__h165698[24:23] == 2'b01) ?
8'd1 :
_theResult___fst_exp__h165679) ;
assign _theResult___exp__h191161 =
sfd__h190524[53] ?
((_theResult___fst_exp__h190506 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h212214) :
((_theResult___fst_exp__h190506 == 11'd0 &&
sfd__h190524[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h190506) ;
assign _theResult___exp__h202063 =
sfd__h201426[53] ?
((_theResult___fst_exp__h201334 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h212244) :
((_theResult___fst_exp__h201334 == 11'd0 &&
sfd__h201426[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h201334) ;
assign _theResult___exp__h212078 =
sfd__h211417[53] ?
((_theResult___fst_exp__h211398 == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h212268) :
((_theResult___fst_exp__h211398 == 11'd0 &&
sfd__h211417[53:52] == 2'b01) ?
11'd1 :
_theResult___fst_exp__h211398) ;
assign _theResult___exp__h27709 =
(sfd__h27313[24] || sfd__h27313[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h28261 =
sfd__h27852[24] ?
((x__h27837[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h28399) :
((x__h27837[7:0] == 8'd0 && sfd__h27852[24:23] == 2'b01) ?
8'd1 :
x__h27837[7:0]) ;
assign _theResult___exp__h34881 =
(sfd__h34485[24] || sfd__h34485[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h35434 =
sfd__h35025[24] ?
((x__h35010[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h35577) :
((x__h35010[7:0] == 8'd0 && sfd__h35025[24:23] == 2'b01) ?
8'd1 :
x__h35010[7:0]) ;
assign _theResult___exp__h41797 =
(sfd__h41401[24] || sfd__h41401[24:23] == 2'b01) ? 8'd1 : 8'd0 ;
assign _theResult___exp__h42349 =
sfd__h41940[24] ?
((x__h41925[7:0] == 8'd254) ?
8'd255 :
din_inc___2_exp__h42487) :
((x__h41925[7:0] == 8'd0 && sfd__h41940[24:23] == 2'b01) ?
8'd1 :
x__h41925[7:0]) ;
assign _theResult___exp__h70015 =
(sfd__h69416[53] || sfd__h69416[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h70771 =
sfd__h70159[53] ?
((x__h70144[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h70914) :
((x__h70144[10:0] == 11'd0 && sfd__h70159[53:52] == 2'b01) ?
11'd1 :
x__h70144[10:0]) ;
assign _theResult___exp__h80962 =
(sfd__h80363[53] || sfd__h80363[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h81717 =
sfd__h81105[53] ?
((x__h81090[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h81855) :
((x__h81090[10:0] == 11'd0 && sfd__h81105[53:52] == 2'b01) ?
11'd1 :
x__h81090[10:0]) ;
assign _theResult___exp__h96337 =
(sfd__h95738[53] || sfd__h95738[53:52] == 2'b01) ?
11'd1 :
11'd0 ;
assign _theResult___exp__h97093 =
sfd__h96481[53] ?
((x__h96466[10:0] == 11'd2046) ?
11'd2047 :
din_inc___2_exp__h97236) :
((x__h96466[10:0] == 11'd0 && sfd__h96481[53:52] == 2'b01) ?
11'd1 :
x__h96466[10:0]) ;
assign _theResult___fst_exp__h108958 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 ;
assign _theResult___fst_exp__h109713 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 ;
assign _theResult___fst_exp__h109716 =
(x__h108990[10:0] == 11'd2047) ?
x__h108990[10:0] :
_theResult___fst_exp__h109713 ;
assign _theResult___fst_exp__h126010 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
8'd255 :
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 ;
assign _theResult___fst_exp__h135390 =
_theResult____h126028[56] ?
8'd2 :
_theResult___fst_exp__h135464 ;
assign _theResult___fst_exp__h135455 =
8'd0 -
{ 2'd0,
IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 } ;
assign _theResult___fst_exp__h135461 =
(!_theResult____h126028[56] && !_theResult____h126028[55] &&
!_theResult____h126028[54] &&
!_theResult____h126028[53] &&
!_theResult____h126028[52] &&
!_theResult____h126028[51] &&
!_theResult____h126028[50] &&
!_theResult____h126028[49] &&
!_theResult____h126028[48] &&
!_theResult____h126028[47] &&
!_theResult____h126028[46] &&
!_theResult____h126028[45] &&
!_theResult____h126028[44] &&
!_theResult____h126028[43] &&
!_theResult____h126028[42] &&
!_theResult____h126028[41] &&
!_theResult____h126028[40] &&
!_theResult____h126028[39] &&
!_theResult____h126028[38] &&
!_theResult____h126028[37] &&
!_theResult____h126028[36] &&
!_theResult____h126028[35] &&
!_theResult____h126028[34] &&
!_theResult____h126028[33] &&
!_theResult____h126028[32] &&
!_theResult____h126028[31] &&
!_theResult____h126028[30] &&
!_theResult____h126028[29] &&
!_theResult____h126028[28] &&
!_theResult____h126028[27] &&
!_theResult____h126028[26] &&
!_theResult____h126028[25] &&
!_theResult____h126028[24] &&
!_theResult____h126028[23] &&
!_theResult____h126028[22] &&
!_theResult____h126028[21] &&
!_theResult____h126028[20] &&
!_theResult____h126028[19] &&
!_theResult____h126028[18] &&
!_theResult____h126028[17] &&
!_theResult____h126028[16] &&
!_theResult____h126028[15] &&
!_theResult____h126028[14] &&
!_theResult____h126028[13] &&
!_theResult____h126028[12] &&
!_theResult____h126028[11] &&
!_theResult____h126028[10] &&
!_theResult____h126028[9] &&
!_theResult____h126028[8] &&
!_theResult____h126028[7] &&
!_theResult____h126028[6] &&
!_theResult____h126028[5] &&
!_theResult____h126028[4] &&
!_theResult____h126028[3] &&
!_theResult____h126028[2] &&
!_theResult____h126028[1] &&
!_theResult____h126028[0] ||
!_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BI_ETC___d3656) ?
8'd0 :
_theResult___fst_exp__h135455 ;
assign _theResult___fst_exp__h135464 =
(!_theResult____h126028[56] && _theResult____h126028[55]) ?
8'd1 :
_theResult___fst_exp__h135461 ;
assign _theResult___fst_exp__h136014 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 ;
assign _theResult___fst_exp__h136017 =
(_theResult___fst_exp__h135390 == 8'd255) ?
_theResult___fst_exp__h135390 :
_theResult___fst_exp__h136014 ;
assign _theResult___fst_exp__h145300 =
8'd129 -
{ 2'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ;
assign _theResult___fst_exp__h145306 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3778) ?
8'd0 :
_theResult___fst_exp__h145300 ;
assign _theResult___fst_exp__h145309 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___fst_exp__h145306 :
8'd129 ;
assign _theResult___fst_exp__h145859 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 ;
assign _theResult___fst_exp__h145862 =
(_theResult___fst_exp__h145309 == 8'd255) ?
_theResult___fst_exp__h145309 :
_theResult___fst_exp__h145859 ;
assign _theResult___fst_exp__h15528 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 ;
assign _theResult___fst_exp__h155731 =
_theResult____h146240[56] ?
8'd2 :
_theResult___fst_exp__h155805 ;
assign _theResult___fst_exp__h155796 =
8'd0 -
{ 2'd0,
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 } ;
assign _theResult___fst_exp__h155802 =
(!_theResult____h146240[56] && !_theResult____h146240[55] &&
!_theResult____h146240[54] &&
!_theResult____h146240[53] &&
!_theResult____h146240[52] &&
!_theResult____h146240[51] &&
!_theResult____h146240[50] &&
!_theResult____h146240[49] &&
!_theResult____h146240[48] &&
!_theResult____h146240[47] &&
!_theResult____h146240[46] &&
!_theResult____h146240[45] &&
!_theResult____h146240[44] &&
!_theResult____h146240[43] &&
!_theResult____h146240[42] &&
!_theResult____h146240[41] &&
!_theResult____h146240[40] &&
!_theResult____h146240[39] &&
!_theResult____h146240[38] &&
!_theResult____h146240[37] &&
!_theResult____h146240[36] &&
!_theResult____h146240[35] &&
!_theResult____h146240[34] &&
!_theResult____h146240[33] &&
!_theResult____h146240[32] &&
!_theResult____h146240[31] &&
!_theResult____h146240[30] &&
!_theResult____h146240[29] &&
!_theResult____h146240[28] &&
!_theResult____h146240[27] &&
!_theResult____h146240[26] &&
!_theResult____h146240[25] &&
!_theResult____h146240[24] &&
!_theResult____h146240[23] &&
!_theResult____h146240[22] &&
!_theResult____h146240[21] &&
!_theResult____h146240[20] &&
!_theResult____h146240[19] &&
!_theResult____h146240[18] &&
!_theResult____h146240[17] &&
!_theResult____h146240[16] &&
!_theResult____h146240[15] &&
!_theResult____h146240[14] &&
!_theResult____h146240[13] &&
!_theResult____h146240[12] &&
!_theResult____h146240[11] &&
!_theResult____h146240[10] &&
!_theResult____h146240[9] &&
!_theResult____h146240[8] &&
!_theResult____h146240[7] &&
!_theResult____h146240[6] &&
!_theResult____h146240[5] &&
!_theResult____h146240[4] &&
!_theResult____h146240[3] &&
!_theResult____h146240[2] &&
!_theResult____h146240[1] &&
!_theResult____h146240[0] ||
!_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR_3_B_ETC___d4100) ?
8'd0 :
_theResult___fst_exp__h155796 ;
assign _theResult___fst_exp__h155805 =
(!_theResult____h146240[56] && _theResult____h146240[55]) ?
8'd1 :
_theResult___fst_exp__h155802 ;
assign _theResult___fst_exp__h156355 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 ;
assign _theResult___fst_exp__h156358 =
(_theResult___fst_exp__h155731 == 8'd255) ?
_theResult___fst_exp__h155731 :
_theResult___fst_exp__h156355 ;
assign _theResult___fst_exp__h16081 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 ;
assign _theResult___fst_exp__h16084 =
(x__h15560[7:0] == 8'd255) ?
x__h15560[7:0] :
_theResult___fst_exp__h16081 ;
assign _theResult___fst_exp__h165631 =
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] ==
8'd0) ?
8'd1 :
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] ;
assign _theResult___fst_exp__h165670 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC__q121[7:0] -
{ 2'd0,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 } ;
assign _theResult___fst_exp__h165676 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0] ||
!_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4173) ?
8'd0 :
_theResult___fst_exp__h165670 ;
assign _theResult___fst_exp__h165679 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___fst_exp__h165676 :
_theResult___fst_exp__h165631 ;
assign _theResult___fst_exp__h166254 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 ;
assign _theResult___fst_exp__h166257 =
(_theResult___fst_exp__h165679 == 8'd255) ?
_theResult___fst_exp__h165679 :
_theResult___fst_exp__h166254 ;
assign _theResult___fst_exp__h166266 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ?
_theResult___snd_fst_exp__h145865 :
_theResult___fst_exp__h126010) :
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ?
_theResult___snd_fst_exp__h166260 :
_theResult___fst_exp__h126010) ;
assign _theResult___fst_exp__h166269 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
8'd0 :
_theResult___fst_exp__h166266 ;
assign _theResult___fst_exp__h174200 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
11'd2047 :
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 ;
assign _theResult___fst_exp__h190497 =
11'd897 -
{ 5'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ;
assign _theResult___fst_exp__h190503 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4617 ?
11'd0 :
_theResult___fst_exp__h190497 ;
assign _theResult___fst_exp__h190506 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___fst_exp__h190503 :
11'd897 ;
assign _theResult___fst_exp__h191259 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 ;
assign _theResult___fst_exp__h191262 =
(_theResult___fst_exp__h190506 == 11'd2047) ?
_theResult___fst_exp__h190506 :
_theResult___fst_exp__h191259 ;
assign _theResult___fst_exp__h201334 =
_theResult____h191843[56] ?
11'd2 :
_theResult___fst_exp__h201408 ;
assign _theResult___fst_exp__h201399 =
11'd0 -
{ 5'd0,
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 } ;
assign _theResult___fst_exp__h201405 =
(!_theResult____h191843[56] && !_theResult____h191843[55] &&
!_theResult____h191843[54] &&
!_theResult____h191843[53] &&
!_theResult____h191843[52] &&
!_theResult____h191843[51] &&
!_theResult____h191843[50] &&
!_theResult____h191843[49] &&
!_theResult____h191843[48] &&
!_theResult____h191843[47] &&
!_theResult____h191843[46] &&
!_theResult____h191843[45] &&
!_theResult____h191843[44] &&
!_theResult____h191843[43] &&
!_theResult____h191843[42] &&
!_theResult____h191843[41] &&
!_theResult____h191843[40] &&
!_theResult____h191843[39] &&
!_theResult____h191843[38] &&
!_theResult____h191843[37] &&
!_theResult____h191843[36] &&
!_theResult____h191843[35] &&
!_theResult____h191843[34] &&
!_theResult____h191843[33] &&
!_theResult____h191843[32] &&
!_theResult____h191843[31] &&
!_theResult____h191843[30] &&
!_theResult____h191843[29] &&
!_theResult____h191843[28] &&
!_theResult____h191843[27] &&
!_theResult____h191843[26] &&
!_theResult____h191843[25] &&
!_theResult____h191843[24] &&
!_theResult____h191843[23] &&
!_theResult____h191843[22] &&
!_theResult____h191843[21] &&
!_theResult____h191843[20] &&
!_theResult____h191843[19] &&
!_theResult____h191843[18] &&
!_theResult____h191843[17] &&
!_theResult____h191843[16] &&
!_theResult____h191843[15] &&
!_theResult____h191843[14] &&
!_theResult____h191843[13] &&
!_theResult____h191843[12] &&
!_theResult____h191843[11] &&
!_theResult____h191843[10] &&
!_theResult____h191843[9] &&
!_theResult____h191843[8] &&
!_theResult____h191843[7] &&
!_theResult____h191843[6] &&
!_theResult____h191843[5] &&
!_theResult____h191843[4] &&
!_theResult____h191843[3] &&
!_theResult____h191843[2] &&
!_theResult____h191843[1] &&
!_theResult____h191843[0] ||
!_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_requestR__ETC___d4935) ?
11'd0 :
_theResult___fst_exp__h201399 ;
assign _theResult___fst_exp__h201408 =
(!_theResult____h191843[56] && _theResult____h191843[55]) ?
11'd1 :
_theResult___fst_exp__h201405 ;
assign _theResult___fst_exp__h202161 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 ;
assign _theResult___fst_exp__h202164 =
(_theResult___fst_exp__h201334 == 11'd2047) ?
_theResult___fst_exp__h201334 :
_theResult___fst_exp__h202161 ;
assign _theResult___fst_exp__h211350 =
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] ==
11'd0) ?
11'd1 :
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] ;
assign _theResult___fst_exp__h211389 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC__q153[10:0] -
{ 5'd0,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 } ;
assign _theResult___fst_exp__h211395 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5010 ?
11'd0 :
_theResult___fst_exp__h211389 ;
assign _theResult___fst_exp__h211398 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___fst_exp__h211395 :
_theResult___fst_exp__h211350 ;
assign _theResult___fst_exp__h212176 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 ;
assign _theResult___fst_exp__h212179 =
(_theResult___fst_exp__h211398 == 11'd2047) ?
_theResult___fst_exp__h211398 :
_theResult___fst_exp__h212176 ;
assign _theResult___fst_exp__h212188 =
(sV1_exp__h1472 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ?
_theResult___snd_fst_exp__h191265 :
_theResult___fst_exp__h174200) :
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ?
_theResult___snd_fst_exp__h212182 :
_theResult___fst_exp__h174200) ;
assign _theResult___fst_exp__h212191 =
(sV1_exp__h1472 == 8'd0 && sV1_sfd__h1473 == 23'd0) ?
11'd0 :
_theResult___fst_exp__h212188 ;
assign _theResult___fst_exp__h27805 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 ;
assign _theResult___fst_exp__h28357 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 ;
assign _theResult___fst_exp__h28360 =
(x__h27837[7:0] == 8'd255) ?
x__h27837[7:0] :
_theResult___fst_exp__h28357 ;
assign _theResult___fst_exp__h34978 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 ;
assign _theResult___fst_exp__h35531 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 ;
assign _theResult___fst_exp__h35534 =
(x__h35010[7:0] == 8'd255) ?
x__h35010[7:0] :
_theResult___fst_exp__h35531 ;
assign _theResult___fst_exp__h41893 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 ;
assign _theResult___fst_exp__h42445 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 ;
assign _theResult___fst_exp__h42448 =
(x__h41925[7:0] == 8'd255) ?
x__h41925[7:0] :
_theResult___fst_exp__h42445 ;
assign _theResult___fst_exp__h70112 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 ;
assign _theResult___fst_exp__h70868 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 ;
assign _theResult___fst_exp__h70871 =
(x__h70144[10:0] == 11'd2047) ?
x__h70144[10:0] :
_theResult___fst_exp__h70868 ;
assign _theResult___fst_exp__h81058 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 :
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 ;
assign _theResult___fst_exp__h81813 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 ;
assign _theResult___fst_exp__h81816 =
(x__h81090[10:0] == 11'd2047) ?
x__h81090[10:0] :
_theResult___fst_exp__h81813 ;
assign _theResult___fst_exp__h96434 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 ;
assign _theResult___fst_exp__h97190 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 ;
assign _theResult___fst_exp__h97193 =
(x__h96466[10:0] == 11'd2047) ?
x__h96466[10:0] :
_theResult___fst_exp__h97190 ;
assign _theResult___fst_sfd__h108959 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 ;
assign _theResult___fst_sfd__h109714 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 ;
assign _theResult___fst_sfd__h109717 =
(x__h108990[10:0] == 11'd2047) ?
sfd___3__h27286[62:11] :
_theResult___fst_sfd__h109714 ;
assign _theResult___fst_sfd__h113549 =
{ 1'd1, requestR_BITS_191_TO_128__q1[50:0] } ;
assign _theResult___fst_sfd__h126011 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
23'd0 :
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 ;
assign _theResult___fst_sfd__h136015 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 ;
assign _theResult___fst_sfd__h136018 =
(_theResult___fst_exp__h135390 == 8'd255) ?
sfdin__h135384[56:34] :
_theResult___fst_sfd__h136015 ;
assign _theResult___fst_sfd__h145860 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 ;
assign _theResult___fst_sfd__h145863 =
(_theResult___fst_exp__h145309 == 8'd255) ?
_theResult___snd__h145260[56:34] :
_theResult___fst_sfd__h145860 ;
assign _theResult___fst_sfd__h15529 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 ;
assign _theResult___fst_sfd__h156356 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 ;
assign _theResult___fst_sfd__h156359 =
(_theResult___fst_exp__h155731 == 8'd255) ?
sfdin__h155725[56:34] :
_theResult___fst_sfd__h156356 ;
assign _theResult___fst_sfd__h16082 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 ;
assign _theResult___fst_sfd__h16085 =
(x__h15560[7:0] == 8'd255) ?
sfd___3__h15005[62:40] :
_theResult___fst_sfd__h16082 ;
assign _theResult___fst_sfd__h166255 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 ;
assign _theResult___fst_sfd__h166258 =
(_theResult___fst_exp__h165679 == 8'd255) ?
_theResult___snd__h165625[56:34] :
_theResult___fst_sfd__h166255 ;
assign _theResult___fst_sfd__h166267 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
(_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3421 ?
_theResult___snd_fst_sfd__h145866 :
_theResult___fst_sfd__h126011) :
(SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3852 ?
_theResult___snd_fst_sfd__h166261 :
_theResult___fst_sfd__h126011) ;
assign _theResult___fst_sfd__h166273 =
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd0) &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
23'd0 :
_theResult___fst_sfd__h166267 ;
assign _theResult___fst_sfd__h168212 = { 1'd1, sV1_sfd__h1473[21:0] } ;
assign _theResult___fst_sfd__h174201 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3) ?
52'd0 :
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 ;
assign _theResult___fst_sfd__h191260 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 ;
assign _theResult___fst_sfd__h191263 =
(_theResult___fst_exp__h190506 == 11'd2047) ?
_theResult___snd__h190457[56:5] :
_theResult___fst_sfd__h191260 ;
assign _theResult___fst_sfd__h202162 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 ;
assign _theResult___fst_sfd__h202165 =
(_theResult___fst_exp__h201334 == 11'd2047) ?
sfdin__h201328[56:5] :
_theResult___fst_sfd__h202162 ;
assign _theResult___fst_sfd__h212177 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 ;
assign _theResult___fst_sfd__h212180 =
(_theResult___fst_exp__h211398 == 11'd2047) ?
_theResult___snd__h211344[56:5] :
_theResult___fst_sfd__h212177 ;
assign _theResult___fst_sfd__h212189 =
(sV1_exp__h1472 == 8'd0) ?
(_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4542 ?
_theResult___snd_fst_sfd__h191266 :
_theResult___fst_sfd__h174201) :
(SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4685 ?
_theResult___snd_fst_sfd__h212183 :
_theResult___fst_sfd__h174201) ;
assign _theResult___fst_sfd__h212195 =
((sV1_exp__h1472 == 8'd255 || sV1_exp__h1472 == 8'd0) &&
sV1_sfd__h1473 == 23'd0) ?
52'd0 :
_theResult___fst_sfd__h212189 ;
assign _theResult___fst_sfd__h27806 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 ;
assign _theResult___fst_sfd__h28358 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 ;
assign _theResult___fst_sfd__h28361 =
(x__h27837[7:0] == 8'd255) ?
sfd___3__h27286[62:40] :
_theResult___fst_sfd__h28358 ;
assign _theResult___fst_sfd__h34979 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 ;
assign _theResult___fst_sfd__h35532 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 ;
assign _theResult___fst_sfd__h35535 =
(x__h35010[7:0] == 8'd255) ?
sfd___3__h34458[30:8] :
_theResult___fst_sfd__h35532 ;
assign _theResult___fst_sfd__h41894 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 ;
assign _theResult___fst_sfd__h42446 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 ;
assign _theResult___fst_sfd__h42449 =
(x__h41925[7:0] == 8'd255) ?
sfd___3__h41374[30:8] :
_theResult___fst_sfd__h42446 ;
assign _theResult___fst_sfd__h70113 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 ;
assign _theResult___fst_sfd__h70869 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 ;
assign _theResult___fst_sfd__h70872 =
(x__h70144[10:0] == 11'd2047) ?
sfd___3__h69389[53:2] :
_theResult___fst_sfd__h70869 ;
assign _theResult___fst_sfd__h81059 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 ;
assign _theResult___fst_sfd__h81814 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 ;
assign _theResult___fst_sfd__h81817 =
(x__h81090[10:0] == 11'd2047) ?
sfd___3__h80336[53:2] :
_theResult___fst_sfd__h81814 ;
assign _theResult___fst_sfd__h96435 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 ;
assign _theResult___fst_sfd__h97191 =
(requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4) ?
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 ;
assign _theResult___fst_sfd__h97194 =
(x__h96466[10:0] == 11'd2047) ?
sfd___3__h15005[62:11] :
_theResult___fst_sfd__h97191 ;
assign _theResult___sfd__h108863 =
sfd__h108263[53] ? sfd__h108263[52:1] : sfd__h108263[51:0] ;
assign _theResult___sfd__h109618 =
sfd__h109005[53] ?
((x__h108990[10:0] == 11'd2046) ? 52'd0 : sfd__h109005[52:1]) :
sfd__h109005[51:0] ;
assign _theResult___sfd__h135917 =
sfd__h135482[24] ?
((_theResult___fst_exp__h135390 == 8'd254) ?
23'd0 :
sfd__h135482[23:1]) :
sfd__h135482[22:0] ;
assign _theResult___sfd__h145762 =
sfd__h145327[24] ?
((_theResult___fst_exp__h145309 == 8'd254) ?
23'd0 :
sfd__h145327[23:1]) :
sfd__h145327[22:0] ;
assign _theResult___sfd__h15432 =
sfd__h15032[24] ? sfd__h15032[23:1] : sfd__h15032[22:0] ;
assign _theResult___sfd__h156258 =
sfd__h155823[24] ?
((_theResult___fst_exp__h155731 == 8'd254) ?
23'd0 :
sfd__h155823[23:1]) :
sfd__h155823[22:0] ;
assign _theResult___sfd__h15985 =
sfd__h15575[24] ?
((x__h15560[7:0] == 8'd254) ? 23'd0 : sfd__h15575[23:1]) :
sfd__h15575[22:0] ;
assign _theResult___sfd__h166157 =
sfd__h165698[24] ?
((_theResult___fst_exp__h165679 == 8'd254) ?
23'd0 :
sfd__h165698[23:1]) :
sfd__h165698[22:0] ;
assign _theResult___sfd__h191162 =
sfd__h190524[53] ?
((_theResult___fst_exp__h190506 == 11'd2046) ?
52'd0 :
sfd__h190524[52:1]) :
sfd__h190524[51:0] ;
assign _theResult___sfd__h202064 =
sfd__h201426[53] ?
((_theResult___fst_exp__h201334 == 11'd2046) ?
52'd0 :
sfd__h201426[52:1]) :
sfd__h201426[51:0] ;
assign _theResult___sfd__h212079 =
sfd__h211417[53] ?
((_theResult___fst_exp__h211398 == 11'd2046) ?
52'd0 :
sfd__h211417[52:1]) :
sfd__h211417[51:0] ;
assign _theResult___sfd__h27710 =
sfd__h27313[24] ? sfd__h27313[23:1] : sfd__h27313[22:0] ;
assign _theResult___sfd__h28262 =
sfd__h27852[24] ?
((x__h27837[7:0] == 8'd254) ? 23'd0 : sfd__h27852[23:1]) :
sfd__h27852[22:0] ;
assign _theResult___sfd__h34882 =
sfd__h34485[24] ? sfd__h34485[23:1] : sfd__h34485[22:0] ;
assign _theResult___sfd__h35435 =
sfd__h35025[24] ?
((x__h35010[7:0] == 8'd254) ? 23'd0 : sfd__h35025[23:1]) :
sfd__h35025[22:0] ;
assign _theResult___sfd__h41798 =
sfd__h41401[24] ? sfd__h41401[23:1] : sfd__h41401[22:0] ;
assign _theResult___sfd__h42350 =
sfd__h41940[24] ?
((x__h41925[7:0] == 8'd254) ? 23'd0 : sfd__h41940[23:1]) :
sfd__h41940[22:0] ;
assign _theResult___sfd__h70016 =
sfd__h69416[53] ? sfd__h69416[52:1] : sfd__h69416[51:0] ;
assign _theResult___sfd__h70772 =
sfd__h70159[53] ?
((x__h70144[10:0] == 11'd2046) ? 52'd0 : sfd__h70159[52:1]) :
sfd__h70159[51:0] ;
assign _theResult___sfd__h80963 =
sfd__h80363[53] ? sfd__h80363[52:1] : sfd__h80363[51:0] ;
assign _theResult___sfd__h81718 =
sfd__h81105[53] ?
((x__h81090[10:0] == 11'd2046) ? 52'd0 : sfd__h81105[52:1]) :
sfd__h81105[51:0] ;
assign _theResult___sfd__h96338 =
sfd__h95738[53] ? sfd__h95738[52:1] : sfd__h95738[51:0] ;
assign _theResult___sfd__h97094 =
sfd__h96481[53] ?
((x__h96466[10:0] == 11'd2046) ? 52'd0 : sfd__h96481[52:1]) :
sfd__h96481[51:0] ;
assign _theResult___snd__h135401 = { _theResult____h126028[55:0], 1'd0 } ;
assign _theResult___snd__h135412 =
(!_theResult____h126028[56] && _theResult____h126028[55]) ?
_theResult___snd__h135414 :
_theResult___snd__h135424 ;
assign _theResult___snd__h135414 = { _theResult____h126028[54:0], 2'd0 } ;
assign _theResult___snd__h135424 =
(!_theResult____h126028[56] && !_theResult____h126028[55] &&
!_theResult____h126028[54] &&
!_theResult____h126028[53] &&
!_theResult____h126028[52] &&
!_theResult____h126028[51] &&
!_theResult____h126028[50] &&
!_theResult____h126028[49] &&
!_theResult____h126028[48] &&
!_theResult____h126028[47] &&
!_theResult____h126028[46] &&
!_theResult____h126028[45] &&
!_theResult____h126028[44] &&
!_theResult____h126028[43] &&
!_theResult____h126028[42] &&
!_theResult____h126028[41] &&
!_theResult____h126028[40] &&
!_theResult____h126028[39] &&
!_theResult____h126028[38] &&
!_theResult____h126028[37] &&
!_theResult____h126028[36] &&
!_theResult____h126028[35] &&
!_theResult____h126028[34] &&
!_theResult____h126028[33] &&
!_theResult____h126028[32] &&
!_theResult____h126028[31] &&
!_theResult____h126028[30] &&
!_theResult____h126028[29] &&
!_theResult____h126028[28] &&
!_theResult____h126028[27] &&
!_theResult____h126028[26] &&
!_theResult____h126028[25] &&
!_theResult____h126028[24] &&
!_theResult____h126028[23] &&
!_theResult____h126028[22] &&
!_theResult____h126028[21] &&
!_theResult____h126028[20] &&
!_theResult____h126028[19] &&
!_theResult____h126028[18] &&
!_theResult____h126028[17] &&
!_theResult____h126028[16] &&
!_theResult____h126028[15] &&
!_theResult____h126028[14] &&
!_theResult____h126028[13] &&
!_theResult____h126028[12] &&
!_theResult____h126028[11] &&
!_theResult____h126028[10] &&
!_theResult____h126028[9] &&
!_theResult____h126028[8] &&
!_theResult____h126028[7] &&
!_theResult____h126028[6] &&
!_theResult____h126028[5] &&
!_theResult____h126028[4] &&
!_theResult____h126028[3] &&
!_theResult____h126028[2] &&
!_theResult____h126028[1] &&
!_theResult____h126028[0]) ?
_theResult____h126028 :
_theResult___snd__h135430 ;
assign _theResult___snd__h135430 =
{ IF_0_CONCAT_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_ETC__q117[54:0],
2'd0 } ;
assign _theResult___snd__h135453 =
_theResult____h126028 <<
IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_T_ETC___d3654 ;
assign _theResult___snd__h145260 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___snd__h145269 :
_theResult___snd__h145262 ;
assign _theResult___snd__h145262 =
{ requestR_BITS_191_TO_128__q1[51:0], 5'd0 } ;
assign _theResult___snd__h145269 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0]) ?
sfd__h117253 :
_theResult___snd__h145275 ;
assign _theResult___snd__h145275 =
{ IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q119[54:0],
2'd0 } ;
assign _theResult___snd__h145298 =
sfd__h117253 <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3776 ;
assign _theResult___snd__h155742 = { _theResult____h146240[55:0], 1'd0 } ;
assign _theResult___snd__h155753 =
(!_theResult____h146240[56] && _theResult____h146240[55]) ?
_theResult___snd__h155755 :
_theResult___snd__h155765 ;
assign _theResult___snd__h155755 = { _theResult____h146240[54:0], 2'd0 } ;
assign _theResult___snd__h155765 =
(!_theResult____h146240[56] && !_theResult____h146240[55] &&
!_theResult____h146240[54] &&
!_theResult____h146240[53] &&
!_theResult____h146240[52] &&
!_theResult____h146240[51] &&
!_theResult____h146240[50] &&
!_theResult____h146240[49] &&
!_theResult____h146240[48] &&
!_theResult____h146240[47] &&
!_theResult____h146240[46] &&
!_theResult____h146240[45] &&
!_theResult____h146240[44] &&
!_theResult____h146240[43] &&
!_theResult____h146240[42] &&
!_theResult____h146240[41] &&
!_theResult____h146240[40] &&
!_theResult____h146240[39] &&
!_theResult____h146240[38] &&
!_theResult____h146240[37] &&
!_theResult____h146240[36] &&
!_theResult____h146240[35] &&
!_theResult____h146240[34] &&
!_theResult____h146240[33] &&
!_theResult____h146240[32] &&
!_theResult____h146240[31] &&
!_theResult____h146240[30] &&
!_theResult____h146240[29] &&
!_theResult____h146240[28] &&
!_theResult____h146240[27] &&
!_theResult____h146240[26] &&
!_theResult____h146240[25] &&
!_theResult____h146240[24] &&
!_theResult____h146240[23] &&
!_theResult____h146240[22] &&
!_theResult____h146240[21] &&
!_theResult____h146240[20] &&
!_theResult____h146240[19] &&
!_theResult____h146240[18] &&
!_theResult____h146240[17] &&
!_theResult____h146240[16] &&
!_theResult____h146240[15] &&
!_theResult____h146240[14] &&
!_theResult____h146240[13] &&
!_theResult____h146240[12] &&
!_theResult____h146240[11] &&
!_theResult____h146240[10] &&
!_theResult____h146240[9] &&
!_theResult____h146240[8] &&
!_theResult____h146240[7] &&
!_theResult____h146240[6] &&
!_theResult____h146240[5] &&
!_theResult____h146240[4] &&
!_theResult____h146240[3] &&
!_theResult____h146240[2] &&
!_theResult____h146240[1] &&
!_theResult____h146240[0]) ?
_theResult____h146240 :
_theResult___snd__h155771 ;
assign _theResult___snd__h155771 =
{ IF_0_CONCAT_IF_IF_3970_MINUS_SEXT_IF_requestR__ETC__q122[54:0],
2'd0 } ;
assign _theResult___snd__h155794 =
_theResult____h146240 <<
IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4__ETC___d4098 ;
assign _theResult___snd__h165625 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0) ?
_theResult___snd__h165639 :
_theResult___snd__h145262 ;
assign _theResult___snd__h165639 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd0 &&
!requestR_BITS_191_TO_128__q1[51] &&
!requestR_BITS_191_TO_128__q1[50] &&
!requestR_BITS_191_TO_128__q1[49] &&
!requestR_BITS_191_TO_128__q1[48] &&
!requestR_BITS_191_TO_128__q1[47] &&
!requestR_BITS_191_TO_128__q1[46] &&
!requestR_BITS_191_TO_128__q1[45] &&
!requestR_BITS_191_TO_128__q1[44] &&
!requestR_BITS_191_TO_128__q1[43] &&
!requestR_BITS_191_TO_128__q1[42] &&
!requestR_BITS_191_TO_128__q1[41] &&
!requestR_BITS_191_TO_128__q1[40] &&
!requestR_BITS_191_TO_128__q1[39] &&
!requestR_BITS_191_TO_128__q1[38] &&
!requestR_BITS_191_TO_128__q1[37] &&
!requestR_BITS_191_TO_128__q1[36] &&
!requestR_BITS_191_TO_128__q1[35] &&
!requestR_BITS_191_TO_128__q1[34] &&
!requestR_BITS_191_TO_128__q1[33] &&
!requestR_BITS_191_TO_128__q1[32] &&
!requestR_BITS_191_TO_128__q1[31] &&
!requestR_BITS_191_TO_128__q1[30] &&
!requestR_BITS_191_TO_128__q1[29] &&
!requestR_BITS_191_TO_128__q1[28] &&
!requestR_BITS_191_TO_128__q1[27] &&
!requestR_BITS_191_TO_128__q1[26] &&
!requestR_BITS_191_TO_128__q1[25] &&
!requestR_BITS_191_TO_128__q1[24] &&
!requestR_BITS_191_TO_128__q1[23] &&
!requestR_BITS_191_TO_128__q1[22] &&
!requestR_BITS_191_TO_128__q1[21] &&
!requestR_BITS_191_TO_128__q1[20] &&
!requestR_BITS_191_TO_128__q1[19] &&
!requestR_BITS_191_TO_128__q1[18] &&
!requestR_BITS_191_TO_128__q1[17] &&
!requestR_BITS_191_TO_128__q1[16] &&
!requestR_BITS_191_TO_128__q1[15] &&
!requestR_BITS_191_TO_128__q1[14] &&
!requestR_BITS_191_TO_128__q1[13] &&
!requestR_BITS_191_TO_128__q1[12] &&
!requestR_BITS_191_TO_128__q1[11] &&
!requestR_BITS_191_TO_128__q1[10] &&
!requestR_BITS_191_TO_128__q1[9] &&
!requestR_BITS_191_TO_128__q1[8] &&
!requestR_BITS_191_TO_128__q1[7] &&
!requestR_BITS_191_TO_128__q1[6] &&
!requestR_BITS_191_TO_128__q1[5] &&
!requestR_BITS_191_TO_128__q1[4] &&
!requestR_BITS_191_TO_128__q1[3] &&
!requestR_BITS_191_TO_128__q1[2] &&
!requestR_BITS_191_TO_128__q1[1] &&
!requestR_BITS_191_TO_128__q1[0]) ?
sfd__h117253 :
_theResult___snd__h165645 ;
assign _theResult___snd__h165645 =
{ IF_0_CONCAT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC__q125[54:0],
2'd0 } ;
assign _theResult___snd__h165663 =
sfd__h117253 <<
IF_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4172 ;
assign _theResult___snd__h190457 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___snd__h190466 :
_theResult___snd__h190459 ;
assign _theResult___snd__h190459 = { sV1_sfd__h1473, 34'd0 } ;
assign _theResult___snd__h190466 =
(sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0]) ?
b__h46021 :
_theResult___snd__h190472 ;
assign _theResult___snd__h190472 =
{ IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q151[54:0],
2'd0 } ;
assign _theResult___snd__h190495 =
b__h46021 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d4613 ;
assign _theResult___snd__h201345 = { _theResult____h191843[55:0], 1'd0 } ;
assign _theResult___snd__h201356 =
(!_theResult____h191843[56] && _theResult____h191843[55]) ?
_theResult___snd__h201358 :
_theResult___snd__h201368 ;
assign _theResult___snd__h201358 = { _theResult____h191843[54:0], 2'd0 } ;
assign _theResult___snd__h201368 =
(!_theResult____h191843[56] && !_theResult____h191843[55] &&
!_theResult____h191843[54] &&
!_theResult____h191843[53] &&
!_theResult____h191843[52] &&
!_theResult____h191843[51] &&
!_theResult____h191843[50] &&
!_theResult____h191843[49] &&
!_theResult____h191843[48] &&
!_theResult____h191843[47] &&
!_theResult____h191843[46] &&
!_theResult____h191843[45] &&
!_theResult____h191843[44] &&
!_theResult____h191843[43] &&
!_theResult____h191843[42] &&
!_theResult____h191843[41] &&
!_theResult____h191843[40] &&
!_theResult____h191843[39] &&
!_theResult____h191843[38] &&
!_theResult____h191843[37] &&
!_theResult____h191843[36] &&
!_theResult____h191843[35] &&
!_theResult____h191843[34] &&
!_theResult____h191843[33] &&
!_theResult____h191843[32] &&
!_theResult____h191843[31] &&
!_theResult____h191843[30] &&
!_theResult____h191843[29] &&
!_theResult____h191843[28] &&
!_theResult____h191843[27] &&
!_theResult____h191843[26] &&
!_theResult____h191843[25] &&
!_theResult____h191843[24] &&
!_theResult____h191843[23] &&
!_theResult____h191843[22] &&
!_theResult____h191843[21] &&
!_theResult____h191843[20] &&
!_theResult____h191843[19] &&
!_theResult____h191843[18] &&
!_theResult____h191843[17] &&
!_theResult____h191843[16] &&
!_theResult____h191843[15] &&
!_theResult____h191843[14] &&
!_theResult____h191843[13] &&
!_theResult____h191843[12] &&
!_theResult____h191843[11] &&
!_theResult____h191843[10] &&
!_theResult____h191843[9] &&
!_theResult____h191843[8] &&
!_theResult____h191843[7] &&
!_theResult____h191843[6] &&
!_theResult____h191843[5] &&
!_theResult____h191843[4] &&
!_theResult____h191843[3] &&
!_theResult____h191843[2] &&
!_theResult____h191843[1] &&
!_theResult____h191843[0]) ?
_theResult____h191843 :
_theResult___snd__h201374 ;
assign _theResult___snd__h201374 =
{ IF_0_CONCAT_IF_IF_3074_MINUS_SEXT_IF_IF_reques_ETC__q154[54:0],
2'd0 } ;
assign _theResult___snd__h201397 =
_theResult____h191843 <<
IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_ETC___d4933 ;
assign _theResult___snd__h211344 =
(sV1_exp__h1472 == 8'd0) ?
_theResult___snd__h211358 :
_theResult___snd__h190459 ;
assign _theResult___snd__h211358 =
(sV1_exp__h1472 == 8'd0 && !sV1_sfd__h1473[22] &&
!sV1_sfd__h1473[21] &&
!sV1_sfd__h1473[20] &&
!sV1_sfd__h1473[19] &&
!sV1_sfd__h1473[18] &&
!sV1_sfd__h1473[17] &&
!sV1_sfd__h1473[16] &&
!sV1_sfd__h1473[15] &&
!sV1_sfd__h1473[14] &&
!sV1_sfd__h1473[13] &&
!sV1_sfd__h1473[12] &&
!sV1_sfd__h1473[11] &&
!sV1_sfd__h1473[10] &&
!sV1_sfd__h1473[9] &&
!sV1_sfd__h1473[8] &&
!sV1_sfd__h1473[7] &&
!sV1_sfd__h1473[6] &&
!sV1_sfd__h1473[5] &&
!sV1_sfd__h1473[4] &&
!sV1_sfd__h1473[3] &&
!sV1_sfd__h1473[2] &&
!sV1_sfd__h1473[1] &&
!sV1_sfd__h1473[0]) ?
b__h46021 :
_theResult___snd__h211364 ;
assign _theResult___snd__h211364 =
{ IF_0_CONCAT_IF_IF_IF_requestR_3_BIT_214_4_THEN_ETC__q157[54:0],
2'd0 } ;
assign _theResult___snd__h211382 =
b__h46021 <<
IF_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reques_ETC___d5007 ;
assign _theResult___snd_fst_exp__h109719 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 ?
_theResult___fst_exp__h108958 :
_theResult___fst_exp__h109716 ;
assign _theResult___snd_fst_exp__h109722 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3070 ?
11'd0 :
_theResult___snd_fst_exp__h109719 ;
assign _theResult___snd_fst_exp__h109725 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3069 ?
_theResult___snd_fst_exp__h109722 :
11'd2047 ;
assign _theResult___snd_fst_exp__h145865 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_theResult___fst_exp__h136017 :
_theResult___fst_exp__h145862 ;
assign _theResult___snd_fst_exp__h16087 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
_theResult___fst_exp__h15528 :
_theResult___fst_exp__h16084 ;
assign _theResult___snd_fst_exp__h16090 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d447 ?
8'd0 :
_theResult___snd_fst_exp__h16087 ;
assign _theResult___snd_fst_exp__h16093 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d445 ?
_theResult___snd_fst_exp__h16090 :
8'd255 ;
assign _theResult___snd_fst_exp__h166260 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_theResult___fst_exp__h156358 :
_theResult___fst_exp__h166257 ;
assign _theResult___snd_fst_exp__h191265 =
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ?
11'd0 :
_theResult___fst_exp__h191262 ;
assign _theResult___snd_fst_exp__h212182 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_theResult___fst_exp__h202164 :
_theResult___fst_exp__h212179 ;
assign _theResult___snd_fst_exp__h28363 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 ?
_theResult___fst_exp__h27805 :
_theResult___fst_exp__h28360 ;
assign _theResult___snd_fst_exp__h28366 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d971 ?
8'd0 :
_theResult___snd_fst_exp__h28363 ;
assign _theResult___snd_fst_exp__h28369 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d970 ?
_theResult___snd_fst_exp__h28366 :
8'd255 ;
assign _theResult___snd_fst_exp__h35537 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
_theResult___fst_exp__h34978 :
_theResult___fst_exp__h35534 ;
assign _theResult___snd_fst_exp__h35540 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1324 ?
8'd0 :
_theResult___snd_fst_exp__h35537 ;
assign _theResult___snd_fst_exp__h35543 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1322 ?
_theResult___snd_fst_exp__h35540 :
8'd255 ;
assign _theResult___snd_fst_exp__h42451 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 ?
_theResult___fst_exp__h41893 :
_theResult___fst_exp__h42448 ;
assign _theResult___snd_fst_exp__h42454 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1579 ?
8'd0 :
_theResult___snd_fst_exp__h42451 ;
assign _theResult___snd_fst_exp__h42457 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1578 ?
_theResult___snd_fst_exp__h42454 :
8'd255 ;
assign _theResult___snd_fst_exp__h70874 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
_theResult___fst_exp__h70112 :
_theResult___fst_exp__h70871 ;
assign _theResult___snd_fst_exp__h70877 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 ?
11'd0 :
_theResult___snd_fst_exp__h70874 ;
assign _theResult___snd_fst_exp__h70880 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ?
_theResult___snd_fst_exp__h70877 :
11'd2047 ;
assign _theResult___snd_fst_exp__h81819 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 ?
_theResult___fst_exp__h81058 :
_theResult___fst_exp__h81816 ;
assign _theResult___snd_fst_exp__h81822 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 ?
11'd0 :
_theResult___snd_fst_exp__h81819 ;
assign _theResult___snd_fst_exp__h81825 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 ?
_theResult___snd_fst_exp__h81822 :
11'd2047 ;
assign _theResult___snd_fst_exp__h97196 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
_theResult___fst_exp__h96434 :
_theResult___fst_exp__h97193 ;
assign _theResult___snd_fst_exp__h97199 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2885 ?
11'd0 :
_theResult___snd_fst_exp__h97196 ;
assign _theResult___snd_fst_exp__h97202 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2883 ?
_theResult___snd_fst_exp__h97199 :
11'd2047 ;
assign _theResult___snd_fst_sfd__h109720 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3071 ?
_theResult___fst_sfd__h108959 :
_theResult___fst_sfd__h109717 ;
assign _theResult___snd_fst_sfd__h117207 =
(value__h113092[51:29] == 23'd0) ?
23'd2097152 :
value__h113092[51:29] ;
assign _theResult___snd_fst_sfd__h145866 =
_3074_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_ETC___d3422 ?
_theResult___fst_sfd__h136018 :
_theResult___fst_sfd__h145863 ;
assign _theResult___snd_fst_sfd__h16088 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d450 ?
_theResult___fst_sfd__h15529 :
_theResult___fst_sfd__h16085 ;
assign _theResult___snd_fst_sfd__h166261 =
SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_3_B_ETC___d3853 ?
_theResult___fst_sfd__h156359 :
_theResult___fst_sfd__h166258 ;
assign _theResult___snd_fst_sfd__h169840 =
(value__h167957 == 23'd0) ?
52'h4000000000000 :
out___1_sfd__h167954 ;
assign _theResult___snd_fst_sfd__h191266 =
_3970_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_21_ETC___d4543 ?
52'd0 :
_theResult___fst_sfd__h191263 ;
assign _theResult___snd_fst_sfd__h212183 =
SEXT_IF_IF_requestR_3_BIT_214_4_THEN_requestR__ETC___d4686 ?
_theResult___fst_sfd__h202165 :
_theResult___fst_sfd__h212180 ;
assign _theResult___snd_fst_sfd__h28364 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d972 ?
_theResult___fst_sfd__h27806 :
_theResult___fst_sfd__h28361 ;
assign _theResult___snd_fst_sfd__h35538 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1327 ?
_theResult___fst_sfd__h34979 :
_theResult___fst_sfd__h35535 ;
assign _theResult___snd_fst_sfd__h42452 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1580 ?
_theResult___fst_sfd__h41894 :
_theResult___fst_sfd__h42449 ;
assign _theResult___snd_fst_sfd__h70875 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 ?
_theResult___fst_sfd__h70113 :
_theResult___fst_sfd__h70872 ;
assign _theResult___snd_fst_sfd__h81820 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 ?
_theResult___fst_sfd__h81059 :
_theResult___fst_sfd__h81817 ;
assign _theResult___snd_fst_sfd__h97197 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2888 ?
_theResult___fst_sfd__h96435 :
_theResult___fst_sfd__h97194 ;
assign b__h110422 = { value__h82527, 64'd0 } ;
assign b__h43158 = { value__h43160, 64'd0 } ;
assign b__h46021 = { value__h43160, 32'd0 } ;
assign b__h82525 = { value__h82527, 32'd0 } ;
assign din_inc___2_exp__h109755 = x__h108990[10:0] + 11'd1 ;
assign din_inc___2_exp__h16127 = x__h15560[7:0] + 8'd1 ;
assign din_inc___2_exp__h166288 = _theResult___fst_exp__h135390 + 8'd1 ;
assign din_inc___2_exp__h166312 = _theResult___fst_exp__h145309 + 8'd1 ;
assign din_inc___2_exp__h166342 = _theResult___fst_exp__h155731 + 8'd1 ;
assign din_inc___2_exp__h166366 = _theResult___fst_exp__h165679 + 8'd1 ;
assign din_inc___2_exp__h212214 = _theResult___fst_exp__h190506 + 11'd1 ;
assign din_inc___2_exp__h212244 = _theResult___fst_exp__h201334 + 11'd1 ;
assign din_inc___2_exp__h212268 = _theResult___fst_exp__h211398 + 11'd1 ;
assign din_inc___2_exp__h28399 = x__h27837[7:0] + 8'd1 ;
assign din_inc___2_exp__h35577 = x__h35010[7:0] + 8'd1 ;
assign din_inc___2_exp__h42487 = x__h41925[7:0] + 8'd1 ;
assign din_inc___2_exp__h70914 = x__h70144[10:0] + 11'd1 ;
assign din_inc___2_exp__h81855 = x__h81090[10:0] + 11'd1 ;
assign din_inc___2_exp__h97236 = x__h96466[10:0] + 11'd1 ;
assign fcsr__h3933 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d684,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d687,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d696 } ;
assign guard__h108246 =
{ IF_sfd___37286_BIT_11_THEN_2_ELSE_0__q27[1],
{ sfd___3__h27286[10:0], 52'd0 } != 63'd0 } ;
assign guard__h108975 =
{ IF_sfd___37286_BIT_10_THEN_2_ELSE_0__q28[1],
{ sfd___3__h27286[9:0], 53'd0 } != 63'd0 } ;
assign guard__h110355 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[52],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[51:0],
65'd0 } !=
117'd0 } ;
assign guard__h111133 =
{ IF_x11322_BIT_53_THEN_2_ELSE_0__q115[1],
{ x__h111322[52:0], 64'd0 } != 117'd0 } ;
assign guard__h112440 =
{ IF_x12661_BIT_53_THEN_2_ELSE_0__q116[1],
{ x__h112661[52:0], 64'd0 } != 117'd0 } ;
assign guard__h126038 =
{ IF_sfdin35384_BIT_33_THEN_2_ELSE_0__q118[1],
{ sfdin__h135384[32:0], 23'd0 } != 56'd0 } ;
assign guard__h136028 =
{ IF_theResult___snd45260_BIT_33_THEN_2_ELSE_0__q120[1],
{ _theResult___snd__h145260[32:0], 23'd0 } != 56'd0 } ;
assign guard__h146250 =
{ IF_sfdin55725_BIT_33_THEN_2_ELSE_0__q123[1],
{ sfdin__h155725[32:0], 23'd0 } != 56'd0 } ;
assign guard__h146848 = x__h146948 != 57'd0 ;
assign guard__h15015 =
{ IF_sfd___35005_BIT_40_THEN_2_ELSE_0__q9[1],
{ sfd___3__h15005[39:0], 23'd0 } != 63'd0 } ;
assign guard__h15545 =
{ IF_sfd___35005_BIT_39_THEN_2_ELSE_0__q10[1],
{ sfd___3__h15005[38:0], 24'd0 } != 63'd0 } ;
assign guard__h156369 =
{ IF_theResult___snd65625_BIT_33_THEN_2_ELSE_0__q126[1],
{ _theResult___snd__h165625[32:0], 23'd0 } != 56'd0 } ;
assign guard__h181312 =
{ IF_theResult___snd90457_BIT_4_THEN_2_ELSE_0__q152[1],
{ _theResult___snd__h190457[3:0], 52'd0 } != 56'd0 } ;
assign guard__h191853 =
{ IF_sfdin01328_BIT_4_THEN_2_ELSE_0__q155[1],
{ sfdin__h201328[3:0], 52'd0 } != 56'd0 } ;
assign guard__h192451 = x__h192551 != 57'd0 ;
assign guard__h202175 =
{ IF_theResult___snd11344_BIT_4_THEN_2_ELSE_0__q158[1],
{ _theResult___snd__h211344[3:0], 52'd0 } != 56'd0 } ;
assign guard__h27296 =
{ IF_sfd___37286_BIT_40_THEN_2_ELSE_0__q25[1],
{ sfd___3__h27286[39:0], 23'd0 } != 63'd0 } ;
assign guard__h27822 =
{ IF_sfd___37286_BIT_39_THEN_2_ELSE_0__q26[1],
{ sfd___3__h27286[38:0], 24'd0 } != 63'd0 } ;
assign guard__h34468 =
{ IF_sfd___34458_BIT_8_THEN_2_ELSE_0__q41[1],
{ sfd___3__h34458[7:0], 23'd0 } != 31'd0 } ;
assign guard__h34995 =
{ IF_sfd___34458_BIT_7_THEN_2_ELSE_0__q42[1],
{ sfd___3__h34458[6:0], 24'd0 } != 31'd0 } ;
assign guard__h41384 =
{ IF_sfd___31374_BIT_8_THEN_2_ELSE_0__q55[1],
{ sfd___3__h41374[7:0], 23'd0 } != 31'd0 } ;
assign guard__h41910 =
{ IF_sfd___31374_BIT_7_THEN_2_ELSE_0__q56[1],
{ sfd___3__h41374[6:0], 24'd0 } != 31'd0 } ;
assign guard__h43091 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[23],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[22:0],
65'd0 } !=
88'd0 } ;
assign guard__h43869 =
{ IF_x4058_BIT_24_THEN_2_ELSE_0__q66[1],
{ x__h44058[23:0], 64'd0 } != 88'd0 } ;
assign guard__h45193 =
{ IF_x5414_BIT_24_THEN_2_ELSE_0__q67[1],
{ x__h45414[23:0], 64'd0 } != 88'd0 } ;
assign guard__h45954 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[23],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[22:0],
33'd0 } !=
56'd0 } ;
assign guard__h46508 =
{ IF_x6697_BIT_24_THEN_2_ELSE_0__q68[1],
{ x__h46697[23:0], 32'd0 } != 56'd0 } ;
assign guard__h47594 =
{ IF_x7815_BIT_24_THEN_2_ELSE_0__q69[1],
{ x__h47815[23:0], 32'd0 } != 56'd0 } ;
assign guard__h69399 =
{ IF_sfd___39389_BIT_2_THEN_2_ELSE_0__q70[1],
{ sfd___3__h69389[1:0], 52'd0 } != 54'd0 } ;
assign guard__h70129 =
{ IF_sfd___39389_BIT_1_THEN_2_ELSE_0__q71[1],
{ sfd___3__h69389[0], 53'd0 } != 54'd0 } ;
assign guard__h80346 =
{ IF_sfd___30336_BIT_2_THEN_2_ELSE_0__q84[1],
{ sfd___3__h80336[1:0], 52'd0 } != 54'd0 } ;
assign guard__h81075 =
{ IF_sfd___30336_BIT_1_THEN_2_ELSE_0__q85[1],
{ sfd___3__h80336[0], 53'd0 } != 54'd0 } ;
assign guard__h82458 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[52],
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[51:0],
33'd0 } !=
85'd0 } ;
assign guard__h83012 =
{ IF_x3201_BIT_53_THEN_2_ELSE_0__q95[1],
{ x__h83201[52:0], 32'd0 } != 85'd0 } ;
assign guard__h84098 =
{ IF_x4319_BIT_53_THEN_2_ELSE_0__q96[1],
{ x__h84319[52:0], 32'd0 } != 85'd0 } ;
assign guard__h95721 =
{ IF_sfd___35005_BIT_11_THEN_2_ELSE_0__q11[1],
{ sfd___3__h15005[10:0], 52'd0 } != 63'd0 } ;
assign guard__h96451 =
{ IF_sfd___35005_BIT_10_THEN_2_ELSE_0__q12[1],
{ sfd___3__h15005[9:0], 53'd0 } != 63'd0 } ;
assign out1___1__h111073 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117:53] +
65'd1 ;
assign out1___1__h43809 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88:24] +
65'd1 ;
assign out1___1__h46448 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56:24] +
33'd1 ;
assign out1___1__h82952 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85:53] +
33'd1 ;
assign out___1_sfd__h167954 = { value__h167957, 29'd0 } ;
assign out_exp__h108865 =
sfd___3__h27286[12] ? _theResult___exp__h108862 : 11'd0 ;
assign out_exp__h109620 =
sfd___3__h27286[11] ?
_theResult___exp__h109617 :
x__h108990[10:0] ;
assign out_exp__h135919 =
sfdin__h135384[34] ?
_theResult___exp__h135916 :
_theResult___fst_exp__h135390 ;
assign out_exp__h145764 =
_theResult___snd__h145260[34] ?
_theResult___exp__h145761 :
_theResult___fst_exp__h145309 ;
assign out_exp__h15434 =
sfd___3__h15005[41] ? _theResult___exp__h15431 : 8'd0 ;
assign out_exp__h156260 =
sfdin__h155725[34] ?
_theResult___exp__h156257 :
_theResult___fst_exp__h155731 ;
assign out_exp__h15987 =
sfd___3__h15005[40] ? _theResult___exp__h15984 : x__h15560[7:0] ;
assign out_exp__h166159 =
_theResult___snd__h165625[34] ?
_theResult___exp__h166156 :
_theResult___fst_exp__h165679 ;
assign out_exp__h191164 =
_theResult___snd__h190457[5] ?
_theResult___exp__h191161 :
_theResult___fst_exp__h190506 ;
assign out_exp__h202066 =
sfdin__h201328[5] ?
_theResult___exp__h202063 :
_theResult___fst_exp__h201334 ;
assign out_exp__h212081 =
_theResult___snd__h211344[5] ?
_theResult___exp__h212078 :
_theResult___fst_exp__h211398 ;
assign out_exp__h27712 =
sfd___3__h27286[41] ? _theResult___exp__h27709 : 8'd0 ;
assign out_exp__h28264 =
sfd___3__h27286[40] ? _theResult___exp__h28261 : x__h27837[7:0] ;
assign out_exp__h34884 =
sfd___3__h34458[9] ? _theResult___exp__h34881 : 8'd0 ;
assign out_exp__h35437 =
sfd___3__h34458[8] ? _theResult___exp__h35434 : x__h35010[7:0] ;
assign out_exp__h41800 =
sfd___3__h41374[9] ? _theResult___exp__h41797 : 8'd0 ;
assign out_exp__h42352 =
sfd___3__h41374[8] ? _theResult___exp__h42349 : x__h41925[7:0] ;
assign out_exp__h70018 =
sfd___3__h69389[3] ? _theResult___exp__h70015 : 11'd0 ;
assign out_exp__h70774 =
sfd___3__h69389[2] ? _theResult___exp__h70771 : x__h70144[10:0] ;
assign out_exp__h80965 =
sfd___3__h80336[3] ? _theResult___exp__h80962 : 11'd0 ;
assign out_exp__h81720 =
sfd___3__h80336[2] ? _theResult___exp__h81717 : x__h81090[10:0] ;
assign out_exp__h96340 =
sfd___3__h15005[12] ? _theResult___exp__h96337 : 11'd0 ;
assign out_exp__h97096 =
sfd___3__h15005[11] ?
_theResult___exp__h97093 :
x__h96466[10:0] ;
assign out_sfd__h108866 =
sfd___3__h27286[12] ?
_theResult___sfd__h108863 :
sfd___3__h27286[63:12] ;
assign out_sfd__h109621 =
sfd___3__h27286[11] ?
_theResult___sfd__h109618 :
sfd___3__h27286[62:11] ;
assign out_sfd__h135920 =
sfdin__h135384[34] ?
_theResult___sfd__h135917 :
sfdin__h135384[56:34] ;
assign out_sfd__h145765 =
_theResult___snd__h145260[34] ?
_theResult___sfd__h145762 :
_theResult___snd__h145260[56:34] ;
assign out_sfd__h15435 =
sfd___3__h15005[41] ?
_theResult___sfd__h15432 :
sfd___3__h15005[63:41] ;
assign out_sfd__h156261 =
sfdin__h155725[34] ?
_theResult___sfd__h156258 :
sfdin__h155725[56:34] ;
assign out_sfd__h15988 =
sfd___3__h15005[40] ?
_theResult___sfd__h15985 :
sfd___3__h15005[62:40] ;
assign out_sfd__h166160 =
_theResult___snd__h165625[34] ?
_theResult___sfd__h166157 :
_theResult___snd__h165625[56:34] ;
assign out_sfd__h191165 =
_theResult___snd__h190457[5] ?
_theResult___sfd__h191162 :
_theResult___snd__h190457[56:5] ;
assign out_sfd__h202067 =
sfdin__h201328[5] ?
_theResult___sfd__h202064 :
sfdin__h201328[56:5] ;
assign out_sfd__h212082 =
_theResult___snd__h211344[5] ?
_theResult___sfd__h212079 :
_theResult___snd__h211344[56:5] ;
assign out_sfd__h27713 =
sfd___3__h27286[41] ?
_theResult___sfd__h27710 :
sfd___3__h27286[63:41] ;
assign out_sfd__h28265 =
sfd___3__h27286[40] ?
_theResult___sfd__h28262 :
sfd___3__h27286[62:40] ;
assign out_sfd__h34885 =
sfd___3__h34458[9] ?
_theResult___sfd__h34882 :
sfd___3__h34458[31:9] ;
assign out_sfd__h35438 =
sfd___3__h34458[8] ?
_theResult___sfd__h35435 :
sfd___3__h34458[30:8] ;
assign out_sfd__h41801 =
sfd___3__h41374[9] ?
_theResult___sfd__h41798 :
sfd___3__h41374[31:9] ;
assign out_sfd__h42353 =
sfd___3__h41374[8] ?
_theResult___sfd__h42350 :
sfd___3__h41374[30:8] ;
assign out_sfd__h70019 =
sfd___3__h69389[3] ?
_theResult___sfd__h70016 :
sfd___3__h69389[54:3] ;
assign out_sfd__h70775 =
sfd___3__h69389[2] ?
_theResult___sfd__h70772 :
sfd___3__h69389[53:2] ;
assign out_sfd__h80966 =
sfd___3__h80336[3] ?
_theResult___sfd__h80963 :
sfd___3__h80336[54:3] ;
assign out_sfd__h81721 =
sfd___3__h80336[2] ?
_theResult___sfd__h81718 :
sfd___3__h80336[53:2] ;
assign out_sfd__h96341 =
sfd___3__h15005[12] ?
_theResult___sfd__h96338 :
sfd___3__h15005[63:12] ;
assign out_sfd__h97097 =
sfd___3__h15005[11] ?
_theResult___sfd__h97094 :
sfd___3__h15005[62:11] ;
assign requestR_BITS_127_TO_64__q3 = requestR[127:64] ;
assign requestR_BITS_191_TO_128_BITS_31_TO_0__q2 =
requestR_BITS_191_TO_128__q1[31:0] ;
assign requestR_BITS_191_TO_128__q1 = requestR[191:128] ;
assign requestR_BITS_206_TO_200__q177 = requestR[206:200] ;
assign requestR_BITS_63_TO_0__q8 = requestR[63:0] ;
assign res___1__h229866 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51]) ?
64'd512 :
64'd256 ;
assign res___1__h230304 =
requestR_BITS_191_TO_128__q1[63] ? 64'd1 : 64'd128 ;
assign res___1__h230314 =
requestR_BITS_191_TO_128__q1[63] ? 64'd8 : 64'd16 ;
assign res___1__h230333 =
requestR_BITS_191_TO_128__q1[63] ? 64'd4 : 64'd32 ;
assign res___1__h57534 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473[22]) ?
64'd512 :
64'd256 ;
assign res___1__h57770 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd1 :
64'd128 ;
assign res___1__h57780 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd8 :
64'd16 ;
assign res___1__h57799 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd4 :
64'd32 ;
assign res__h166745 = { 32'hFFFFFFFF, x__h166751 } ;
assign res__h212818 =
{ IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5189,
x__h167898,
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153 } ;
assign res__h217300 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 ?
requestR[191:128] :
requestR[127:64] ;
assign res__h221886 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 ?
requestR[127:64] :
requestR[191:128] ;
assign res__h224628 =
((requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_127_TO_64__q3[62:52] != 11'd2047 ||
requestR_BITS_127_TO_64__q3[51:0] == 52'd0) &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5378) ?
64'd1 :
64'd0 ;
assign res__h227363 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5330 ?
64'd1 :
64'd0 ;
assign res__h229280 =
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d5399 ?
64'd1 :
64'd0 ;
assign res__h230349 = requestR_BITS_191_TO_128__q1[63] ? 64'd2 : 64'd64 ;
assign res__h230541 = { 32'hFFFFFFFF, fpu$server_core_response_get[36:5] } ;
assign res__h3932 = { 32'hFFFFFFFF, x__h3975 } ;
assign res__h48859 =
{ 32'hFFFFFFFF,
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d48 } ;
assign res__h49096 =
{ 32'hFFFFFFFF,
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign res__h54627 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2172 ?
64'd1 :
64'd0 ;
assign res__h56150 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2105 ?
64'd1 :
64'd0 ;
assign res__h57259 =
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2192 ?
64'd1 :
64'd0 ;
assign res__h57815 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
64'd2 :
64'd64 ;
assign result__h146853 =
{ _0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858[56:1],
_0b0_CONCAT_NOT_IF_requestR_3_BIT_214_4_THEN_re_ETC___d3858[0] |
guard__h146848 } ;
assign result__h192456 =
{ _0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691[56:1],
_0b0_CONCAT_NOT_IF_IF_requestR_3_BIT_214_4_THEN_ETC___d4691[0] |
guard__h192451 } ;
assign sV1_exp__h1472 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_191_TO_128__q1[30:23] :
8'd255 ;
assign sV1_sfd__h1473 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_191_TO_128__q1[22:0] :
23'd4194304 ;
assign sV2_exp__h1597 =
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_127_TO_64__q3[30:23] :
8'd255 ;
assign sV2_sfd__h1598 =
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF) ?
requestR_BITS_127_TO_64__q3[22:0] :
23'd4194304 ;
assign sfd___3__h15005 =
sfd__h3990 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d441 ;
assign sfd___3__h27286 =
requestR[191:128] <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d966 ;
assign sfd___3__h34458 =
sfd__h28849 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1318 ;
assign sfd___3__h41374 =
requestR_BITS_191_TO_128__q1[31:0] <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1574 ;
assign sfd___3__h69389 =
sfd__h60177 <<
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2339 ;
assign sfd___3__h80336 =
sfd__h71373 <<
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2555 ;
assign sfd__h108263 = { 2'd0, sfd___3__h27286[63:12] } + 54'd1 ;
assign sfd__h109005 =
{ 1'b0, x__h108990[10:0] != 11'd0, sfd___3__h27286[62:11] } +
54'd1 ;
assign sfd__h117253 = { value__h82527, 3'd0 } ;
assign sfd__h135482 =
{ 1'b0,
_theResult___fst_exp__h135390 != 8'd0,
sfdin__h135384[56:34] } +
25'd1 ;
assign sfd__h145327 =
{ 1'b0,
_theResult___fst_exp__h145309 != 8'd0,
_theResult___snd__h145260[56:34] } +
25'd1 ;
assign sfd__h15032 = { 2'd0, sfd___3__h15005[63:41] } + 25'd1 ;
assign sfd__h15575 =
{ 1'b0, x__h15560[7:0] != 8'd0, sfd___3__h15005[62:40] } +
25'd1 ;
assign sfd__h155823 =
{ 1'b0,
_theResult___fst_exp__h155731 != 8'd0,
sfdin__h155725[56:34] } +
25'd1 ;
assign sfd__h165698 =
{ 1'b0,
_theResult___fst_exp__h165679 != 8'd0,
_theResult___snd__h165625[56:34] } +
25'd1 ;
assign sfd__h190524 =
{ 1'b0,
_theResult___fst_exp__h190506 != 11'd0,
_theResult___snd__h190457[56:5] } +
54'd1 ;
assign sfd__h201426 =
{ 1'b0,
_theResult___fst_exp__h201334 != 11'd0,
sfdin__h201328[56:5] } +
54'd1 ;
assign sfd__h211417 =
{ 1'b0,
_theResult___fst_exp__h211398 != 11'd0,
_theResult___snd__h211344[56:5] } +
54'd1 ;
assign sfd__h27313 = { 2'd0, sfd___3__h27286[63:41] } + 25'd1 ;
assign sfd__h27852 =
{ 1'b0, x__h27837[7:0] != 8'd0, sfd___3__h27286[62:40] } +
25'd1 ;
assign sfd__h28849 =
requestR_BITS_191_TO_128__q1[31] ?
-requestR_BITS_191_TO_128__q1[31:0] :
requestR_BITS_191_TO_128__q1[31:0] ;
assign sfd__h34485 = { 2'd0, sfd___3__h34458[31:9] } + 25'd1 ;
assign sfd__h35025 =
{ 1'b0, x__h35010[7:0] != 8'd0, sfd___3__h34458[30:8] } + 25'd1 ;
assign sfd__h3990 =
requestR_BITS_191_TO_128__q1[63] ?
-requestR[191:128] :
requestR[191:128] ;
assign sfd__h41401 = { 2'd0, sfd___3__h41374[31:9] } + 25'd1 ;
assign sfd__h41940 =
{ 1'b0, x__h41925[7:0] != 8'd0, sfd___3__h41374[30:8] } + 25'd1 ;
assign sfd__h60177 = { sfd__h28849, 23'd0 } ;
assign sfd__h69416 = { 2'd0, sfd___3__h69389[54:3] } + 54'd1 ;
assign sfd__h70159 =
{ 1'b0, x__h70144[10:0] != 11'd0, sfd___3__h69389[53:2] } +
54'd1 ;
assign sfd__h71373 = { requestR_BITS_191_TO_128__q1[31:0], 23'd0 } ;
assign sfd__h80363 = { 2'd0, sfd___3__h80336[54:3] } + 54'd1 ;
assign sfd__h81105 =
{ 1'b0, x__h81090[10:0] != 11'd0, sfd___3__h80336[53:2] } +
54'd1 ;
assign sfd__h95738 = { 2'd0, sfd___3__h15005[63:12] } + 54'd1 ;
assign sfd__h96481 =
{ 1'b0, x__h96466[10:0] != 11'd0, sfd___3__h15005[62:11] } +
54'd1 ;
assign sfdin__h135384 =
_theResult____h126028[56] ?
_theResult___snd__h135401 :
_theResult___snd__h135412 ;
assign sfdin__h155725 =
_theResult____h146240[56] ?
_theResult___snd__h155742 :
_theResult___snd__h155753 ;
assign sfdin__h201328 =
_theResult____h191843[56] ?
_theResult___snd__h201345 :
_theResult___snd__h201356 ;
assign value__h113092 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51]) ?
_theResult___fst_sfd__h113549 :
requestR_BITS_191_TO_128__q1[51:0] ;
assign value__h167957 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 &&
!sV1_sfd__h1473[22]) ?
_theResult___fst_sfd__h168212 :
sV1_sfd__h1473 ;
assign value__h43160 = { 1'b0, sV1_exp__h1472 != 8'd0, sV1_sfd__h1473 } ;
assign value__h82527 =
{ 1'b0,
requestR_BITS_191_TO_128__q1[62:52] != 11'd0,
requestR_BITS_191_TO_128__q1[51:0] } ;
assign x__h108990 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d3068 +
12'd1023 ;
assign x__h109855 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3199,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3202,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3211 } ;
assign x__h110179 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'h7FFFFFFFFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3283 ;
assign x__h111322 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224 >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250 |
~(118'h3FFFFFFFFFFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3250) &
{118{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3224[117]}} ;
assign x__h111943 =
{ requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3290,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d3298 } ;
assign x__h112240 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
(requestR_BITS_191_TO_128__q1[63] ?
64'd0 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
64'hFFFFFFFFFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3337)) ;
assign x__h112661 =
{ requestR_BITS_191_TO_128__q1[62:52] != 11'd0,
requestR_BITS_191_TO_128__q1[51:0],
65'd0 } >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3308 ;
assign x__h112739 =
{ requestR_BITS_191_TO_128__q1[63] ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3357 :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d3346,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3351 } ;
assign x__h113022 =
(x__h113032 == 8'd255 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338[22]) ?
64'hFFFFFFFF7FC00000 :
res__h166745 ;
assign x__h113032 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047) ?
8'd255 :
_theResult___fst_exp__h166269 ;
assign x__h146948 = sfd__h117253 << x__h146981 ;
assign x__h146981 =
12'd57 -
_3970_MINUS_SEXT_IF_requestR_3_BIT_214_4_THEN_r_ETC___d3854 ;
assign x__h15560 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d444 +
9'd127 ;
assign x__h166751 =
{ (requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd0) &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
requestR_BITS_191_TO_128__q1[63] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4378,
x__h113032,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4338 } ;
assign x__h166866 =
{ (requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) ?
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51] :
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4429,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4440,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4456,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4469,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4482 } ;
assign x__h16727 =
{ 33'h1FFFFFFFE,
(requestR[191:128] == 64'd0) ?
8'd0 :
_theResult___snd_fst_exp__h28369,
(requestR[191:128] == 64'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1059) ?
23'd0 :
_theResult___snd_fst_sfd__h28364 } ;
assign x__h167888 =
(x__h167898 == 11'd2047 &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5153[51]) ?
64'h7FF8000000000000 :
res__h212818 ;
assign x__h167898 =
(sV1_exp__h1472 == 8'd255) ?
11'd2047 :
_theResult___fst_exp__h212191 ;
assign x__h192551 = b__h46021 << x__h192584 ;
assign x__h192584 =
12'd57 -
_3074_MINUS_SEXT_IF_IF_requestR_3_BIT_214_4_THE_ETC___d4687 ;
assign x__h212920 =
{ IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5227,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5234,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5248,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5260,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d5272 } ;
assign x__h213882 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294 ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
((requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51]) ?
requestR[191:128] :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51]) ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5333)))) ;
assign x__h217430 =
{ IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5339,
4'd0 } ;
assign x__h218468 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5294 ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 &&
!requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
((requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0 &&
!requestR_BITS_127_TO_64__q3[51]) ?
requestR[191:128] :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51] &&
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51]) ?
64'h7FF8000000000000 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51]) ?
requestR[127:64] :
((requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51]) ?
requestR[191:128] :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5348))))) ;
assign x__h222950 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 ?
64'd0 :
res__h224628 ;
assign x__h225685 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 ?
64'd0 :
res__h227363 ;
assign x__h227382 =
{ requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_127_TO_64__q3[62:52] == 11'd2047 &&
requestR_BITS_127_TO_64__q3[51:0] != 52'd0,
4'd0 } ;
assign x__h227602 =
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d5363 ?
64'd0 :
res__h229280 ;
assign x__h229846 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) ?
res___1__h229866 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
res___1__h230304 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5426) ;
assign x__h230460 =
fpu$server_core_response_get[69] ?
((fpu$server_core_response_get[35:28] == 8'd255 &&
fpu$server_core_response_get[27:5] != 23'd0) ?
64'hFFFFFFFF7FC00000 :
res__h230541) :
((fpu$server_core_response_get[67:57] == 11'd2047 &&
fpu$server_core_response_get[56:5] != 52'd0) ?
64'h7FF8000000000000 :
fpu$server_core_response_get[68:5]) ;
assign x__h27837 =
_64_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d969 +
9'd127 ;
assign x__h28503 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1165,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1168,
requestR[191:128] != 64'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1177 } ;
assign x__h28828 = { 32'hFFFFFFFF, x__h28834 } ;
assign x__h28834 =
{ requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
(NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326 ?
requestR_BITS_191_TO_128__q1[31] :
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d1379),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1439,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1326) ?
23'd0 :
_theResult___snd_fst_sfd__h35538 } ;
assign x__h3429 = { 32'hFFFFFFFF, x__h3436 } ;
assign x__h3436 =
{ requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign x__h35010 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d1321 +
9'd127 ;
assign x__h35703 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1520,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1523,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1532 } ;
assign x__h36028 =
{ 33'h1FFFFFFFE,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0) ?
8'd0 :
_theResult___snd_fst_exp__h42457,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d1666) ?
23'd0 :
_theResult___snd_fst_sfd__h42452 } ;
assign x__h3605 = { 32'hFFFFFFFF, x__h3612 } ;
assign x__h3612 =
{ requestR_BITS_127_TO_64__q3[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_127_TO_64__q3[31],
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign x__h3778 = { 32'hFFFFFFFF, x__h3785 } ;
assign x__h3785 =
{ (requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) !=
(requestR_BITS_127_TO_64__q3[63:32] == 32'hFFFFFFFF &&
requestR_BITS_127_TO_64__q3[31]),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d37 } ;
assign x__h3975 =
{ requestR[191:128] != 64'd0 &&
(NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449 ?
requestR_BITS_191_TO_128__q1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d511),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d571,
(requestR[191:128] == 64'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d449) ?
23'd0 :
_theResult___snd_fst_sfd__h16088 } ;
assign x__h41925 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d1577 +
9'd127 ;
assign x__h42591 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1709,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1712,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d1721 } ;
assign x__h42915 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
64'h7FFFFFFFFFFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1816 ;
assign x__h44058 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757 >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783 |
~(89'h1FFFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1783) &
{89{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1757[88]}} ;
assign x__h44696 =
{ sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1826,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1837 } ;
assign x__h44993 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
64'hFFFFFFFFFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1878 ;
assign x__h45414 =
{ sV1_exp__h1472 != 8'd0, sV1_sfd__h1473, 65'd0 } >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1847 ;
assign x__h45492 =
{ (requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1896 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1885,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1890 } ;
assign x__h45775 = { {32{x__h45778[31]}}, x__h45778 } ;
assign x__h45778 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
32'h7FFFFFFF :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d1967 ;
assign x__h46697 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908 >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934 |
~(57'h1FFFFFFFFFFFFFF >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1934) &
{57{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1908[56]}} ;
assign x__h47094 =
{ sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 == 23'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d1975,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
(sV1_exp__h1472 != 8'd0 || sV1_sfd__h1473 != 23'd0) &&
IF_NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_re_ETC___d1983 } ;
assign x__h47391 = { {32{x__h47394[31]}}, x__h47394 } ;
assign x__h47394 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
(requestR_BITS_191_TO_128__q1[63:32] != 32'hFFFFFFFF ||
!requestR_BITS_191_TO_128__q1[31]) &&
sV1_exp__h1472 == 8'd255 &&
sV1_sfd__h1473 == 23'd0) ?
32'hFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2024 ;
assign x__h47815 =
{ sV1_exp__h1472 != 8'd0, sV1_sfd__h1473, 33'd0 } >>
NEG_SEXT_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d1993 ;
assign x__h47893 =
{ (requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2043 :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2032,
3'd0,
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 == 23'd0) &&
(sV1_exp__h1472 != 8'd255 || sV1_sfd__h1473 != 23'd0) &&
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2037 } ;
assign x__h48180 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067 ?
64'hFFFFFFFF7FC00000 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2113 ;
assign x__h50220 =
{ IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2115,
4'd0 } ;
assign x__h50854 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2067 ?
64'hFFFFFFFF7FC00000 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2130 ;
assign x__h53419 = { 32'hFFFFFFFF, requestR_BITS_191_TO_128__q1[31:0] } ;
assign x__h53579 =
{ {32{requestR_BITS_191_TO_128_BITS_31_TO_0__q2[31]}},
requestR_BITS_191_TO_128_BITS_31_TO_0__q2 } ;
assign x__h53757 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 ?
64'd0 :
res__h54627 ;
assign x__h55280 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 ?
64'd0 :
res__h56150 ;
assign x__h56169 =
{ sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0 ||
sV2_exp__h1597 == 8'd255 && sV2_sfd__h1598 != 23'd0,
4'd0 } ;
assign x__h56389 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2156 ?
64'd0 :
res__h57259 ;
assign x__h57514 =
(sV1_exp__h1472 == 8'd255 && sV1_sfd__h1473 != 23'd0) ?
res___1__h57534 :
IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3__ETC___d2207 ;
assign x__h59668 =
{ requestR_BITS_127_TO_64__q3[63],
requestR_BITS_191_TO_128__q1[62:0] } ;
assign x__h59829 =
{ !requestR_BITS_127_TO_64__q3[63],
requestR_BITS_191_TO_128__q1[62:0] } ;
assign x__h59992 =
{ requestR_BITS_191_TO_128__q1[63] !=
requestR_BITS_127_TO_64__q3[63],
requestR_BITS_191_TO_128__q1[62:0] } ;
assign x__h60162 =
{ requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
IF_NOT_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_B_ETC___d2399,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h70880,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2496 } ;
assign x__h70144 =
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2342 +
12'd1023 ;
assign x__h71036 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 ||
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2347 &&
_theResult___fst_exp__h70871 == 11'd2047 &&
_theResult___fst_sfd__h70872 == 52'd0),
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2343 &&
!_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2345 &&
IF_32_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2513 } ;
assign x__h71361 =
{ 1'd0,
(requestR_BITS_191_TO_128__q1[31:0] == 32'd0) ?
11'd0 :
_theResult___snd_fst_exp__h81825,
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2680 } ;
assign x__h81090 =
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2558 +
12'd1023 ;
assign x__h81955 =
{ 2'd0,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
(!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 ||
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2561 &&
_theResult___fst_exp__h81816 == 11'd2047 &&
_theResult___fst_sfd__h81817 == 52'd0),
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560,
requestR_BITS_191_TO_128__q1[31:0] != 32'd0 &&
_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2559 &&
!_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214_4_T_ETC___d2560 &&
IF_32_MINUS_0_CONCAT_IF_IF_requestR_3_BIT_214__ETC___d2697 } ;
assign x__h82279 = { {32{x__h82282[31]}}, x__h82282 } ;
assign x__h82282 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'h7FFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2790 ;
assign x__h83201 =
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731 >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757 |
~(86'h3FFFFFFFFFFFFFFFFFFFFF >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2757) &
{86{IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2731[85]}} ;
assign x__h83598 =
{ requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2801,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd0 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
IF_NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d2812 } ;
assign x__h83895 = { {32{x__h83898[31]}}, x__h83898 } ;
assign x__h83898 =
(requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] != 52'd0 ||
!requestR_BITS_191_TO_128__q1[63] &&
requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'hFFFFFFFF :
(requestR_BITS_191_TO_128__q1[63] ?
32'd0 :
((requestR_BITS_191_TO_128__q1[62:52] == 11'd2047 &&
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) ?
32'hFFFFFFFF :
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2851)) ;
assign x__h84319 =
{ requestR_BITS_191_TO_128__q1[62:52] != 11'd0,
requestR_BITS_191_TO_128__q1[51:0],
33'd0 } >>
NEG_SEXT_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2822 ;
assign x__h84397 =
{ requestR_BITS_191_TO_128__q1[63] ?
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2872 :
IF_requestR_3_BIT_214_4_THEN_requestR_3_BITS_1_ETC___d2861,
3'd0,
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] == 52'd0) &&
(requestR_BITS_191_TO_128__q1[62:52] != 11'd2047 ||
requestR_BITS_191_TO_128__q1[51:0] != 52'd0) &&
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d2866 } ;
assign x__h84681 =
{ requestR[191:128] != 64'd0 &&
(NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887 ?
requestR_BITS_191_TO_128__q1[63] :
IF_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_2_ETC___d2937),
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2996,
(requestR[191:128] == 64'd0 ||
NOT_IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_ETC___d2887) ?
52'd0 :
_theResult___snd_fst_sfd__h97197 } ;
assign x__h96466 =
_64_MINUS_0_CONCAT_IF_IF_IF_requestR_3_BIT_214__ETC___d2882 +
12'd1023 ;
assign x__h97358 =
{ 2'd0,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3045,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3048,
requestR[191:128] != 64'd0 &&
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3057 } ;
assign x__h97683 =
{ 1'd0,
(requestR[191:128] == 64'd0) ?
11'd0 :
_theResult___snd_fst_exp__h109725,
(requestR[191:128] == 64'd0 ||
NOT_IF_requestR_3_BIT_214_4_THEN_requestR_3_BI_ETC___d3156) ?
52'd0 :
_theResult___snd_fst_sfd__h109720 } ;
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 = 8'd254;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 =
requestR_BITS_191_TO_128__q1[63] ? 8'd255 : 8'd254;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 =
requestR_BITS_191_TO_128__q1[63] ? 8'd254 : 8'd255;
default: CASE_requestR_BITS_194_TO_192_0x1_254_0x2_IF_r_ETC__q4 = 8'd0;
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 =
23'd8388607;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 =
requestR_BITS_191_TO_128__q1[63] ? 23'd0 : 23'd8388607;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 =
requestR_BITS_191_TO_128__q1[63] ? 23'd8388607 : 23'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_8388607_0x2__ETC__q5 = 23'd0;
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 = 11'd2046;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
11'd2047 :
11'd2046;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
11'd2046 :
11'd2047;
default: CASE_requestR_BITS_194_TO_192_0x1_2046_0x2_IF__ETC__q6 = 11'd0;
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1)
begin
case (requestR[194:192])
3'h1:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 =
52'hFFFFFFFFFFFFF;
3'h2:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
52'd0 :
52'hFFFFFFFFFFFFF;
3'h3:
CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 =
(requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31]) ?
52'hFFFFFFFFFFFFF :
52'd0;
default: CASE_requestR_BITS_194_TO_192_0x1_450359962737_ETC__q7 = 52'd0;
endcase
end
always@(requestR)
begin
case (requestR[194:192])
3'h0:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 =
requestR[194:192];
3'h1: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd4;
3'h2: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd3;
3'h3: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd2;
3'h4: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 = 3'd1;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d61 =
3'd0;
endcase
end
always@(guard__h15015 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h15015)
2'b0, 2'b01, 2'b10:
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard5015_0b0_requestR_BITS_191_TO_128_BI_ETC__q13 =
guard__h15015 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h15015)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14 =
(guard__h15015 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h15015 == 2'b01 || guard__h15015 == 2'b10 ||
guard__h15015 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q14 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h15545 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h15545)
2'b0, 2'b01, 2'b10:
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard5545_0b0_requestR_BITS_191_TO_128_BI_ETC__q15 =
guard__h15545 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h15545)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16 =
(guard__h15545 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h15545 == 2'b01 || guard__h15545 == 2'b10 ||
guard__h15545 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q16 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h15015 or _theResult___exp__h15431)
begin
case (guard__h15015)
2'b0: CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17 =
_theResult___exp__h15431;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533 or
guard__h15015 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h15431 or
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d533;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
(guard__h15015 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
8'd0 :
_theResult___exp__h15431;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
CASE_guard5015_0b0_0_0b1_theResult___exp5431_0_ETC__q17;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d536 =
8'd0;
endcase
end
always@(guard__h15015 or out_exp__h15434 or _theResult___exp__h15431)
begin
case (guard__h15015)
2'b0, 2'b01:
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 = 8'd0;
2'b10:
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 =
out_exp__h15434;
2'b11:
CASE_guard5015_0b0_0_0b1_0_0b10_out_exp5434_0b_ETC__q18 =
_theResult___exp__h15431;
endcase
end
always@(guard__h15545 or x__h15560 or _theResult___exp__h15984)
begin
case (guard__h15545)
2'b0:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19 =
x__h15560[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19 =
_theResult___exp__h15984;
endcase
end
always@(requestR or
x__h15560 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559 or
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
x__h15560[7:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d561;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d559;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_theRe_ETC__q19;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d565 =
8'd0;
endcase
end
always@(guard__h15545 or
x__h15560 or out_exp__h15987 or _theResult___exp__h15984)
begin
case (guard__h15545)
2'b0, 2'b01:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 =
x__h15560[7:0];
2'b10:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 =
out_exp__h15987;
2'b11:
CASE_guard5545_0b0_x5560_BITS_7_TO_0_0b1_x5560_ETC__q20 =
_theResult___exp__h15984;
endcase
end
always@(guard__h15015 or sfd___3__h15005 or _theResult___sfd__h15432)
begin
case (guard__h15015)
2'b0:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21 =
sfd___3__h15005[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21 =
_theResult___sfd__h15432;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582 or
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
sfd___3__h15005[63:41];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d584;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d582;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q21;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d588 =
23'd0;
endcase
end
always@(guard__h15015 or
sfd___3__h15005 or out_sfd__h15435 or _theResult___sfd__h15432)
begin
case (guard__h15015)
2'b0, 2'b01:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 =
sfd___3__h15005[63:41];
2'b10:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 =
out_sfd__h15435;
2'b11:
CASE_guard5015_0b0_sfd___35005_BITS_63_TO_41_0_ETC__q22 =
_theResult___sfd__h15432;
endcase
end
always@(guard__h15545 or sfd___3__h15005 or _theResult___sfd__h15985)
begin
case (guard__h15545)
2'b0:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23 =
sfd___3__h15005[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23 =
_theResult___sfd__h15985;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600 or
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
sfd___3__h15005[62:40];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d602;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d600;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q23;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d606 =
23'd0;
endcase
end
always@(guard__h15545 or
sfd___3__h15005 or out_sfd__h15988 or _theResult___sfd__h15985)
begin
case (guard__h15545)
2'b0, 2'b01:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 =
sfd___3__h15005[62:40];
2'b10:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 =
out_sfd__h15988;
2'b11:
CASE_guard5545_0b0_sfd___35005_BITS_62_TO_40_0_ETC__q24 =
_theResult___sfd__h15985;
endcase
end
always@(guard__h27296 or out_exp__h27712 or _theResult___exp__h27709)
begin
case (guard__h27296)
2'b0, 2'b01:
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 = 8'd0;
2'b10:
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 =
out_exp__h27712;
2'b11:
CASE_guard7296_0b0_0_0b1_0_0b10_out_exp7712_0b_ETC__q29 =
_theResult___exp__h27709;
endcase
end
always@(guard__h27296 or _theResult___exp__h27709)
begin
case (guard__h27296)
2'b0: CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30 =
_theResult___exp__h27709;
endcase
end
always@(requestR or
guard__h27296 or
_theResult___exp__h27709 or
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 =
(guard__h27296 == 2'b0) ? 8'd0 : _theResult___exp__h27709;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 =
CASE_guard7296_0b0_0_0b1_theResult___exp7709_0_ETC__q30;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard7296_ETC__q31 = 8'd0;
endcase
end
always@(guard__h108246 or out_exp__h108865 or _theResult___exp__h108862)
begin
case (guard__h108246)
2'b0, 2'b01:
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 = 11'd0;
2'b10:
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 =
out_exp__h108865;
2'b11:
CASE_guard08246_0b0_0_0b1_0_0b10_out_exp08865__ETC__q32 =
_theResult___exp__h108862;
endcase
end
always@(guard__h108246 or _theResult___exp__h108862)
begin
case (guard__h108246)
2'b0: CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33 =
_theResult___exp__h108862;
endcase
end
always@(requestR or
guard__h108246 or
_theResult___exp__h108862 or
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 =
(guard__h108246 == 2'b0) ? 11'd0 : _theResult___exp__h108862;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 =
CASE_guard08246_0b0_0_0b1_theResult___exp08862_ETC__q33;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard0824_ETC__q34 =
11'd0;
endcase
end
always@(guard__h27822 or x__h27837 or _theResult___exp__h28261)
begin
case (guard__h27822)
2'b0:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35 =
x__h27837[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35 =
_theResult___exp__h28261;
endcase
end
always@(requestR or
x__h27837 or
guard__h27822 or
_theResult___exp__h28261 or
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
x__h27837[7:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
(guard__h27822 == 2'b0) ?
x__h27837[7:0] :
_theResult___exp__h28261;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_theRe_ETC__q35;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1050 =
8'd0;
endcase
end
always@(guard__h27822 or
x__h27837 or out_exp__h28264 or _theResult___exp__h28261)
begin
case (guard__h27822)
2'b0, 2'b01:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 =
x__h27837[7:0];
2'b10:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 =
out_exp__h28264;
2'b11:
CASE_guard7822_0b0_x7837_BITS_7_TO_0_0b1_x7837_ETC__q36 =
_theResult___exp__h28261;
endcase
end
always@(guard__h27822 or sfd___3__h27286 or _theResult___sfd__h28262)
begin
case (guard__h27822)
2'b0:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37 =
sfd___3__h27286[62:40];
2'b01, 2'b10, 2'b11:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37 =
_theResult___sfd__h28262;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h27822 or
_theResult___sfd__h28262 or
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
sfd___3__h27286[62:40];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
(guard__h27822 == 2'b0) ?
sfd___3__h27286[62:40] :
_theResult___sfd__h28262;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q37;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1088 =
23'd0;
endcase
end
always@(guard__h27822 or
sfd___3__h27286 or out_sfd__h28265 or _theResult___sfd__h28262)
begin
case (guard__h27822)
2'b0, 2'b01:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 =
sfd___3__h27286[62:40];
2'b10:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 =
out_sfd__h28265;
2'b11:
CASE_guard7822_0b0_sfd___37286_BITS_62_TO_40_0_ETC__q38 =
_theResult___sfd__h28262;
endcase
end
always@(guard__h27296 or sfd___3__h27286 or _theResult___sfd__h27710)
begin
case (guard__h27296)
2'b0:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39 =
sfd___3__h27286[63:41];
2'b01, 2'b10, 2'b11:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39 =
_theResult___sfd__h27710;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h27296 or
_theResult___sfd__h27710 or
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
sfd___3__h27286[63:41];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
(guard__h27296 == 2'b0) ?
sfd___3__h27286[63:41] :
_theResult___sfd__h27710;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q39;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1073 =
23'd0;
endcase
end
always@(guard__h27296 or
sfd___3__h27286 or out_sfd__h27713 or _theResult___sfd__h27710)
begin
case (guard__h27296)
2'b0, 2'b01:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 =
sfd___3__h27286[63:41];
2'b10:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 =
out_sfd__h27713;
2'b11:
CASE_guard7296_0b0_sfd___37286_BITS_63_TO_41_0_ETC__q40 =
_theResult___sfd__h27710;
endcase
end
always@(guard__h34468 or _theResult___exp__h34881)
begin
case (guard__h34468)
2'b0: CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43 =
_theResult___exp__h34881;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401 or
guard__h34468 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h34881 or
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1401;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
(guard__h34468 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
8'd0 :
_theResult___exp__h34881;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
CASE_guard4468_0b0_0_0b1_theResult___exp4881_0_ETC__q43;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1404 =
8'd0;
endcase
end
always@(guard__h34468 or out_exp__h34884 or _theResult___exp__h34881)
begin
case (guard__h34468)
2'b0, 2'b01:
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 = 8'd0;
2'b10:
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 =
out_exp__h34884;
2'b11:
CASE_guard4468_0b0_0_0b1_0_0b10_out_exp4884_0b_ETC__q44 =
_theResult___exp__h34881;
endcase
end
always@(guard__h34468 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h34468)
2'b0, 2'b01, 2'b10:
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard4468_0b0_requestR_BITS_191_TO_128_BI_ETC__q45 =
guard__h34468 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h34468)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46 =
(guard__h34468 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h34468 == 2'b01 || guard__h34468 == 2'b10 ||
guard__h34468 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q46 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h34995 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h34995)
2'b0, 2'b01, 2'b10:
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard4995_0b0_requestR_BITS_191_TO_128_BI_ETC__q47 =
guard__h34995 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h34995)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48 =
(guard__h34995 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h34995 == 2'b01 || guard__h34995 == 2'b10 ||
guard__h34995 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q48 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h34995 or x__h35010 or _theResult___exp__h35434)
begin
case (guard__h34995)
2'b0:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49 =
x__h35010[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49 =
_theResult___exp__h35434;
endcase
end
always@(requestR or
x__h35010 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427 or
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
x__h35010[7:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1429;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1427;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_theRe_ETC__q49;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1433 =
8'd0;
endcase
end
always@(guard__h34995 or
x__h35010 or out_exp__h35437 or _theResult___exp__h35434)
begin
case (guard__h34995)
2'b0, 2'b01:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 =
x__h35010[7:0];
2'b10:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 =
out_exp__h35437;
2'b11:
CASE_guard4995_0b0_x5010_BITS_7_TO_0_0b1_x5010_ETC__q50 =
_theResult___exp__h35434;
endcase
end
always@(guard__h34468 or sfd___3__h34458 or _theResult___sfd__h34882)
begin
case (guard__h34468)
2'b0:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51 =
sfd___3__h34458[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51 =
_theResult___sfd__h34882;
endcase
end
always@(requestR or
sfd___3__h34458 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450 or
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
sfd___3__h34458[31:9];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1452;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1450;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q51;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1456 =
23'd0;
endcase
end
always@(guard__h34468 or
sfd___3__h34458 or out_sfd__h34885 or _theResult___sfd__h34882)
begin
case (guard__h34468)
2'b0, 2'b01:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 =
sfd___3__h34458[31:9];
2'b10:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 =
out_sfd__h34885;
2'b11:
CASE_guard4468_0b0_sfd___34458_BITS_31_TO_9_0b_ETC__q52 =
_theResult___sfd__h34882;
endcase
end
always@(guard__h34995 or sfd___3__h34458 or _theResult___sfd__h35435)
begin
case (guard__h34995)
2'b0:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53 =
sfd___3__h34458[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53 =
_theResult___sfd__h35435;
endcase
end
always@(requestR or
sfd___3__h34458 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468 or
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
sfd___3__h34458[30:8];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1470;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d1468;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q53;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1474 =
23'd0;
endcase
end
always@(guard__h34995 or
sfd___3__h34458 or out_sfd__h35438 or _theResult___sfd__h35435)
begin
case (guard__h34995)
2'b0, 2'b01:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 =
sfd___3__h34458[30:8];
2'b10:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 =
out_sfd__h35438;
2'b11:
CASE_guard4995_0b0_sfd___34458_BITS_30_TO_8_0b_ETC__q54 =
_theResult___sfd__h35435;
endcase
end
always@(guard__h41384 or out_exp__h41800 or _theResult___exp__h41797)
begin
case (guard__h41384)
2'b0, 2'b01:
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 = 8'd0;
2'b10:
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 =
out_exp__h41800;
2'b11:
CASE_guard1384_0b0_0_0b1_0_0b10_out_exp1800_0b_ETC__q57 =
_theResult___exp__h41797;
endcase
end
always@(guard__h41384 or _theResult___exp__h41797)
begin
case (guard__h41384)
2'b0: CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58 = 8'd0;
2'b01, 2'b10, 2'b11:
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58 =
_theResult___exp__h41797;
endcase
end
always@(requestR or
guard__h41384 or
_theResult___exp__h41797 or
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 =
(guard__h41384 == 2'b0) ? 8'd0 : _theResult___exp__h41797;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 =
CASE_guard1384_0b0_0_0b1_theResult___exp1797_0_ETC__q58;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard1384_ETC__q59 = 8'd0;
endcase
end
always@(guard__h41910 or x__h41925 or _theResult___exp__h42349)
begin
case (guard__h41910)
2'b0:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60 =
x__h41925[7:0];
2'b01, 2'b10, 2'b11:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60 =
_theResult___exp__h42349;
endcase
end
always@(requestR or
x__h41925 or
guard__h41910 or
_theResult___exp__h42349 or
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
x__h41925[7:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
(guard__h41910 == 2'b0) ?
x__h41925[7:0] :
_theResult___exp__h42349;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_theRe_ETC__q60;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1657 =
8'd0;
endcase
end
always@(guard__h41910 or
x__h41925 or out_exp__h42352 or _theResult___exp__h42349)
begin
case (guard__h41910)
2'b0, 2'b01:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 =
x__h41925[7:0];
2'b10:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 =
out_exp__h42352;
2'b11:
CASE_guard1910_0b0_x1925_BITS_7_TO_0_0b1_x1925_ETC__q61 =
_theResult___exp__h42349;
endcase
end
always@(guard__h41910 or sfd___3__h41374 or _theResult___sfd__h42350)
begin
case (guard__h41910)
2'b0:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62 =
sfd___3__h41374[30:8];
2'b01, 2'b10, 2'b11:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62 =
_theResult___sfd__h42350;
endcase
end
always@(requestR or
sfd___3__h41374 or
guard__h41910 or
_theResult___sfd__h42350 or
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
sfd___3__h41374[30:8];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
(guard__h41910 == 2'b0) ?
sfd___3__h41374[30:8] :
_theResult___sfd__h42350;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q62;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1695 =
23'd0;
endcase
end
always@(guard__h41910 or
sfd___3__h41374 or out_sfd__h42353 or _theResult___sfd__h42350)
begin
case (guard__h41910)
2'b0, 2'b01:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 =
sfd___3__h41374[30:8];
2'b10:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 =
out_sfd__h42353;
2'b11:
CASE_guard1910_0b0_sfd___31374_BITS_30_TO_8_0b_ETC__q63 =
_theResult___sfd__h42350;
endcase
end
always@(guard__h41384 or sfd___3__h41374 or _theResult___sfd__h41798)
begin
case (guard__h41384)
2'b0:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64 =
sfd___3__h41374[31:9];
2'b01, 2'b10, 2'b11:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64 =
_theResult___sfd__h41798;
endcase
end
always@(requestR or
sfd___3__h41374 or
guard__h41384 or
_theResult___sfd__h41798 or
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
sfd___3__h41374[31:9];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
(guard__h41384 == 2'b0) ?
sfd___3__h41374[31:9] :
_theResult___sfd__h41798;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q64;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d1680 =
23'd0;
endcase
end
always@(guard__h41384 or
sfd___3__h41374 or out_sfd__h41801 or _theResult___sfd__h41798)
begin
case (guard__h41384)
2'b0, 2'b01:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 =
sfd___3__h41374[31:9];
2'b10:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 =
out_sfd__h41801;
2'b11:
CASE_guard1384_0b0_sfd___31374_BITS_31_TO_9_0b_ETC__q65 =
_theResult___sfd__h41798;
endcase
end
always@(guard__h69399 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h69399)
2'b0, 2'b01, 2'b10:
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard9399_0b0_requestR_BITS_191_TO_128_BI_ETC__q72 =
guard__h69399 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h69399)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73 =
(guard__h69399 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h69399 == 2'b01 || guard__h69399 == 2'b10 ||
guard__h69399 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q73 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h70129 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h70129)
2'b0, 2'b01, 2'b10:
CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74 =
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard0129_0b0_requestR_BITS_191_TO_128_BI_ETC__q74 =
guard__h70129 == 2'b11 && requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h70129)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75 =
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75 =
(guard__h70129 == 2'b0) ?
requestR_BITS_191_TO_128__q1[31] :
(guard__h70129 == 2'b01 || guard__h70129 == 2'b10 ||
guard__h70129 == 2'b11) &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q75 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h70129 or x__h70144 or _theResult___exp__h70771)
begin
case (guard__h70129)
2'b0:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76 =
x__h70144[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76 =
_theResult___exp__h70771;
endcase
end
always@(requestR or
x__h70144 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445 or
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
x__h70144[10:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2447;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2445;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_theR_ETC__q76;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2451 =
11'd0;
endcase
end
always@(guard__h70129 or
x__h70144 or out_exp__h70774 or _theResult___exp__h70771)
begin
case (guard__h70129)
2'b0, 2'b01:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 =
x__h70144[10:0];
2'b10:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 =
out_exp__h70774;
2'b11:
CASE_guard0129_0b0_x0144_BITS_10_TO_0_0b1_x014_ETC__q77 =
_theResult___exp__h70771;
endcase
end
always@(guard__h70129 or sfd___3__h69389 or _theResult___sfd__h70772)
begin
case (guard__h70129)
2'b0:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78 =
sfd___3__h69389[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78 =
_theResult___sfd__h70772;
endcase
end
always@(requestR or
sfd___3__h69389 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486 or
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
sfd___3__h69389[53:2];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2488;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2486;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q78;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2492 =
52'd0;
endcase
end
always@(guard__h70129 or
sfd___3__h69389 or out_sfd__h70775 or _theResult___sfd__h70772)
begin
case (guard__h70129)
2'b0, 2'b01:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 =
sfd___3__h69389[53:2];
2'b10:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 =
out_sfd__h70775;
2'b11:
CASE_guard0129_0b0_sfd___39389_BITS_53_TO_2_0b_ETC__q79 =
_theResult___sfd__h70772;
endcase
end
always@(guard__h69399 or _theResult___exp__h70015)
begin
case (guard__h69399)
2'b0: CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80 =
_theResult___exp__h70015;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419 or
guard__h69399 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h70015 or
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2419;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
(guard__h69399 == 2'b0 || requestR_BITS_191_TO_128__q1[31]) ?
11'd0 :
_theResult___exp__h70015;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
CASE_guard9399_0b0_0_0b1_theResult___exp0015_0_ETC__q80;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2422 =
11'd0;
endcase
end
always@(guard__h69399 or out_exp__h70018 or _theResult___exp__h70015)
begin
case (guard__h69399)
2'b0, 2'b01:
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 = 11'd0;
2'b10:
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 =
out_exp__h70018;
2'b11:
CASE_guard9399_0b0_0_0b1_0_0b10_out_exp0018_0b_ETC__q81 =
_theResult___exp__h70015;
endcase
end
always@(guard__h69399 or sfd___3__h69389 or _theResult___sfd__h70016)
begin
case (guard__h69399)
2'b0:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82 =
sfd___3__h69389[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82 =
_theResult___sfd__h70016;
endcase
end
always@(requestR or
sfd___3__h69389 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468 or
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
sfd___3__h69389[54:3];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2470;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2468;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q82;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2474 =
52'd0;
endcase
end
always@(guard__h69399 or
sfd___3__h69389 or out_sfd__h70019 or _theResult___sfd__h70016)
begin
case (guard__h69399)
2'b0, 2'b01:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 =
sfd___3__h69389[54:3];
2'b10:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 =
out_sfd__h70019;
2'b11:
CASE_guard9399_0b0_sfd___39389_BITS_54_TO_3_0b_ETC__q83 =
_theResult___sfd__h70016;
endcase
end
always@(guard__h80346 or out_exp__h80965 or _theResult___exp__h80962)
begin
case (guard__h80346)
2'b0, 2'b01:
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 = 11'd0;
2'b10:
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 =
out_exp__h80965;
2'b11:
CASE_guard0346_0b0_0_0b1_0_0b10_out_exp0965_0b_ETC__q86 =
_theResult___exp__h80962;
endcase
end
always@(guard__h80346 or _theResult___exp__h80962)
begin
case (guard__h80346)
2'b0: CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87 =
_theResult___exp__h80962;
endcase
end
always@(requestR or
guard__h80346 or
_theResult___exp__h80962 or
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87)
begin
case (requestR[194:192])
3'h3:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 =
(guard__h80346 == 2'b0) ? 11'd0 : _theResult___exp__h80962;
3'h4:
CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 =
CASE_guard0346_0b0_0_0b1_theResult___exp0962_0_ETC__q87;
default: CASE_requestR_BITS_194_TO_192_0x3_IF_guard0346_ETC__q88 =
11'd0;
endcase
end
always@(guard__h81075 or x__h81090 or _theResult___exp__h81717)
begin
case (guard__h81075)
2'b0:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89 =
x__h81090[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89 =
_theResult___exp__h81717;
endcase
end
always@(requestR or
x__h81090 or
guard__h81075 or
_theResult___exp__h81717 or
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
x__h81090[10:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
(guard__h81075 == 2'b0) ?
x__h81090[10:0] :
_theResult___exp__h81717;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_theR_ETC__q89;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2639 =
11'd0;
endcase
end
always@(guard__h81075 or
x__h81090 or out_exp__h81720 or _theResult___exp__h81717)
begin
case (guard__h81075)
2'b0, 2'b01:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 =
x__h81090[10:0];
2'b10:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 =
out_exp__h81720;
2'b11:
CASE_guard1075_0b0_x1090_BITS_10_TO_0_0b1_x109_ETC__q90 =
_theResult___exp__h81717;
endcase
end
always@(guard__h81075 or sfd___3__h80336 or _theResult___sfd__h81718)
begin
case (guard__h81075)
2'b0:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91 =
sfd___3__h80336[53:2];
2'b01, 2'b10, 2'b11:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91 =
_theResult___sfd__h81718;
endcase
end
always@(requestR or
sfd___3__h80336 or
guard__h81075 or
_theResult___sfd__h81718 or
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
sfd___3__h80336[53:2];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
(guard__h81075 == 2'b0) ?
sfd___3__h80336[53:2] :
_theResult___sfd__h81718;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q91;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2676 =
52'd0;
endcase
end
always@(guard__h81075 or
sfd___3__h80336 or out_sfd__h81721 or _theResult___sfd__h81718)
begin
case (guard__h81075)
2'b0, 2'b01:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 =
sfd___3__h80336[53:2];
2'b10:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 =
out_sfd__h81721;
2'b11:
CASE_guard1075_0b0_sfd___30336_BITS_53_TO_2_0b_ETC__q92 =
_theResult___sfd__h81718;
endcase
end
always@(guard__h80346 or sfd___3__h80336 or _theResult___sfd__h80963)
begin
case (guard__h80346)
2'b0:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93 =
sfd___3__h80336[54:3];
2'b01, 2'b10, 2'b11:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93 =
_theResult___sfd__h80963;
endcase
end
always@(requestR or
sfd___3__h80336 or
guard__h80346 or
_theResult___sfd__h80963 or
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
sfd___3__h80336[54:3];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
(guard__h80346 == 2'b0) ?
sfd___3__h80336[54:3] :
_theResult___sfd__h80963;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q93;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2661 =
52'd0;
endcase
end
always@(guard__h80346 or
sfd___3__h80336 or out_sfd__h80966 or _theResult___sfd__h80963)
begin
case (guard__h80346)
2'b0, 2'b01:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 =
sfd___3__h80336[54:3];
2'b10:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 =
out_sfd__h80966;
2'b11:
CASE_guard0346_0b0_sfd___30336_BITS_54_TO_3_0b_ETC__q94 =
_theResult___sfd__h80963;
endcase
end
always@(guard__h95721 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h95721)
2'b0, 2'b01, 2'b10:
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard5721_0b0_requestR_BITS_191_TO_128_BI_ETC__q97 =
guard__h95721 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h95721)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98 =
(guard__h95721 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h95721 == 2'b01 || guard__h95721 == 2'b10 ||
guard__h95721 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q98 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h96451 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h96451)
2'b0, 2'b01, 2'b10:
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard6451_0b0_requestR_BITS_191_TO_128_BI_ETC__q99 =
guard__h96451 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h96451)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100 =
(guard__h96451 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h96451 == 2'b01 || guard__h96451 == 2'b10 ||
guard__h96451 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q100 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h96451 or x__h96466 or _theResult___exp__h97093)
begin
case (guard__h96451)
2'b0:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101 =
x__h96466[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101 =
_theResult___exp__h97093;
endcase
end
always@(requestR or
x__h96466 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984 or
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
x__h96466[10:0];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2986;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2984;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_theR_ETC__q101;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2990 =
11'd0;
endcase
end
always@(guard__h96451 or
x__h96466 or out_exp__h97096 or _theResult___exp__h97093)
begin
case (guard__h96451)
2'b0, 2'b01:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 =
x__h96466[10:0];
2'b10:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 =
out_exp__h97096;
2'b11:
CASE_guard6451_0b0_x6466_BITS_10_TO_0_0b1_x646_ETC__q102 =
_theResult___exp__h97093;
endcase
end
always@(guard__h96451 or sfd___3__h15005 or _theResult___sfd__h97094)
begin
case (guard__h96451)
2'b0:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103 =
sfd___3__h15005[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103 =
_theResult___sfd__h97094;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025 or
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
sfd___3__h15005[62:11];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3027;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3025;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q103;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3031 =
52'd0;
endcase
end
always@(guard__h96451 or
sfd___3__h15005 or out_sfd__h97097 or _theResult___sfd__h97094)
begin
case (guard__h96451)
2'b0, 2'b01:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 =
sfd___3__h15005[62:11];
2'b10:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 =
out_sfd__h97097;
2'b11:
CASE_guard6451_0b0_sfd___35005_BITS_62_TO_11_0_ETC__q104 =
_theResult___sfd__h97094;
endcase
end
always@(guard__h95721 or _theResult___exp__h96337)
begin
case (guard__h95721)
2'b0: CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105 = 11'd0;
2'b01, 2'b10, 2'b11:
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105 =
_theResult___exp__h96337;
endcase
end
always@(requestR or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958 or
guard__h95721 or
requestR_BITS_191_TO_128__q1 or
_theResult___exp__h96337 or
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105)
begin
case (requestR[194:192])
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d2958;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
(guard__h95721 == 2'b0 || requestR_BITS_191_TO_128__q1[63]) ?
11'd0 :
_theResult___exp__h96337;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
CASE_guard5721_0b0_0_0b1_theResult___exp6337_0_ETC__q105;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d2961 =
11'd0;
endcase
end
always@(guard__h95721 or out_exp__h96340 or _theResult___exp__h96337)
begin
case (guard__h95721)
2'b0, 2'b01:
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 = 11'd0;
2'b10:
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 =
out_exp__h96340;
2'b11:
CASE_guard5721_0b0_0_0b1_0_0b10_out_exp6340_0b_ETC__q106 =
_theResult___exp__h96337;
endcase
end
always@(guard__h95721 or sfd___3__h15005 or _theResult___sfd__h96338)
begin
case (guard__h95721)
2'b0:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107 =
sfd___3__h15005[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107 =
_theResult___sfd__h96338;
endcase
end
always@(requestR or
sfd___3__h15005 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007 or
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
sfd___3__h15005[63:12];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3009;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3007;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q107;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3013 =
52'd0;
endcase
end
always@(guard__h95721 or
sfd___3__h15005 or out_sfd__h96341 or _theResult___sfd__h96338)
begin
case (guard__h95721)
2'b0, 2'b01:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 =
sfd___3__h15005[63:12];
2'b10:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 =
out_sfd__h96341;
2'b11:
CASE_guard5721_0b0_sfd___35005_BITS_63_TO_12_0_ETC__q108 =
_theResult___sfd__h96338;
endcase
end
always@(guard__h108975 or x__h108990 or _theResult___exp__h109617)
begin
case (guard__h108975)
2'b0:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109 =
x__h108990[10:0];
2'b01, 2'b10, 2'b11:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109 =
_theResult___exp__h109617;
endcase
end
always@(requestR or
x__h108990 or
guard__h108975 or
_theResult___exp__h109617 or
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
x__h108990[10:0];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
(guard__h108975 == 2'b0) ?
x__h108990[10:0] :
_theResult___exp__h109617;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_th_ETC__q109;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3147 =
11'd0;
endcase
end
always@(guard__h108975 or
x__h108990 or out_exp__h109620 or _theResult___exp__h109617)
begin
case (guard__h108975)
2'b0, 2'b01:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 =
x__h108990[10:0];
2'b10:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 =
out_exp__h109620;
2'b11:
CASE_guard08975_0b0_x08990_BITS_10_TO_0_0b1_x0_ETC__q110 =
_theResult___exp__h109617;
endcase
end
always@(guard__h108975 or sfd___3__h27286 or _theResult___sfd__h109618)
begin
case (guard__h108975)
2'b0:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111 =
sfd___3__h27286[62:11];
2'b01, 2'b10, 2'b11:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111 =
_theResult___sfd__h109618;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h108975 or
_theResult___sfd__h109618 or
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
sfd___3__h27286[62:11];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
(guard__h108975 == 2'b0) ?
sfd___3__h27286[62:11] :
_theResult___sfd__h109618;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q111;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3185 =
52'd0;
endcase
end
always@(guard__h108975 or
sfd___3__h27286 or out_sfd__h109621 or _theResult___sfd__h109618)
begin
case (guard__h108975)
2'b0, 2'b01:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 =
sfd___3__h27286[62:11];
2'b10:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 =
out_sfd__h109621;
2'b11:
CASE_guard08975_0b0_sfd___37286_BITS_62_TO_11__ETC__q112 =
_theResult___sfd__h109618;
endcase
end
always@(guard__h108246 or sfd___3__h27286 or _theResult___sfd__h108863)
begin
case (guard__h108246)
2'b0:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113 =
sfd___3__h27286[63:12];
2'b01, 2'b10, 2'b11:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113 =
_theResult___sfd__h108863;
endcase
end
always@(requestR or
sfd___3__h27286 or
guard__h108246 or
_theResult___sfd__h108863 or
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113)
begin
case (requestR[194:192])
3'h1, 3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
sfd___3__h27286[63:12];
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
(guard__h108246 == 2'b0) ?
sfd___3__h27286[63:12] :
_theResult___sfd__h108863;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q113;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3170 =
52'd0;
endcase
end
always@(guard__h108246 or
sfd___3__h27286 or out_sfd__h108866 or _theResult___sfd__h108863)
begin
case (guard__h108246)
2'b0, 2'b01:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 =
sfd___3__h27286[63:12];
2'b10:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 =
out_sfd__h108866;
2'b11:
CASE_guard08246_0b0_sfd___37286_BITS_63_TO_12__ETC__q114 =
_theResult___sfd__h108863;
endcase
end
always@(guard__h126038 or
_theResult___fst_exp__h135390 or _theResult___exp__h135916)
begin
case (guard__h126038)
2'b0:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127 =
_theResult___fst_exp__h135390;
2'b01, 2'b10, 2'b11:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127 =
_theResult___exp__h135916;
endcase
end
always@(requestR or
_theResult___fst_exp__h135390 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713 or
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
_theResult___fst_exp__h135390;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3715;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d3713;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q127;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3719 =
8'd0;
endcase
end
always@(guard__h126038 or
_theResult___fst_exp__h135390 or
out_exp__h135919 or _theResult___exp__h135916)
begin
case (guard__h126038)
2'b0, 2'b01:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 =
_theResult___fst_exp__h135390;
2'b10:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 =
out_exp__h135919;
2'b11:
CASE_guard26038_0b0_theResult___fst_exp35390_0_ETC__q128 =
_theResult___exp__h135916;
endcase
end
always@(guard__h136028 or
_theResult___fst_exp__h145309 or _theResult___exp__h145761)
begin
case (guard__h136028)
2'b0:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129 =
_theResult___fst_exp__h145309;
2'b01, 2'b10, 2'b11:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129 =
_theResult___exp__h145761;
endcase
end
always@(requestR or
_theResult___fst_exp__h145309 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830 or
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
_theResult___fst_exp__h145309;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3832;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d3830;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q129;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d3836 =
8'd0;
endcase
end
always@(guard__h136028 or
_theResult___fst_exp__h145309 or
out_exp__h145764 or _theResult___exp__h145761)
begin
case (guard__h136028)
2'b0, 2'b01:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 =
_theResult___fst_exp__h145309;
2'b10:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 =
out_exp__h145764;
2'b11:
CASE_guard36028_0b0_theResult___fst_exp45309_0_ETC__q130 =
_theResult___exp__h145761;
endcase
end
always@(guard__h146250 or
_theResult___fst_exp__h155731 or _theResult___exp__h156257)
begin
case (guard__h146250)
2'b0:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131 =
_theResult___fst_exp__h155731;
2'b01, 2'b10, 2'b11:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131 =
_theResult___exp__h156257;
endcase
end
always@(requestR or
_theResult___fst_exp__h155731 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157 or
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
_theResult___fst_exp__h155731;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4159;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4157;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q131;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4163 =
8'd0;
endcase
end
always@(guard__h146250 or
_theResult___fst_exp__h155731 or
out_exp__h156260 or _theResult___exp__h156257)
begin
case (guard__h146250)
2'b0, 2'b01:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 =
_theResult___fst_exp__h155731;
2'b10:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 =
out_exp__h156260;
2'b11:
CASE_guard46250_0b0_theResult___fst_exp55731_0_ETC__q132 =
_theResult___exp__h156257;
endcase
end
always@(guard__h156369 or
_theResult___fst_exp__h165679 or _theResult___exp__h166156)
begin
case (guard__h156369)
2'b0:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133 =
_theResult___fst_exp__h165679;
2'b01, 2'b10, 2'b11:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133 =
_theResult___exp__h166156;
endcase
end
always@(requestR or
_theResult___fst_exp__h165679 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226 or
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
_theResult___fst_exp__h165679;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4228;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4226;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q133;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4232 =
8'd0;
endcase
end
always@(guard__h156369 or
_theResult___fst_exp__h165679 or
out_exp__h166159 or _theResult___exp__h166156)
begin
case (guard__h156369)
2'b0, 2'b01:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 =
_theResult___fst_exp__h165679;
2'b10:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 =
out_exp__h166159;
2'b11:
CASE_guard56369_0b0_theResult___fst_exp65679_0_ETC__q134 =
_theResult___exp__h166156;
endcase
end
always@(guard__h126038 or sfdin__h135384 or _theResult___sfd__h135917)
begin
case (guard__h126038)
2'b0:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135 =
sfdin__h135384[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135 =
_theResult___sfd__h135917;
endcase
end
always@(requestR or
sfdin__h135384 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262 or
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260 or
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
sfdin__h135384[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4262;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
IF_IF_IF_IF_0b0_CONCAT_NOT_IF_requestR_3_BIT_2_ETC___d4260;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q135;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4266 =
23'd0;
endcase
end
always@(guard__h126038 or
sfdin__h135384 or out_sfd__h135920 or _theResult___sfd__h135917)
begin
case (guard__h126038)
2'b0, 2'b01:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 =
sfdin__h135384[56:34];
2'b10:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 =
out_sfd__h135920;
2'b11:
CASE_guard26038_0b0_sfdin35384_BITS_56_TO_34_0_ETC__q136 =
_theResult___sfd__h135917;
endcase
end
always@(guard__h136028 or
_theResult___snd__h145260 or _theResult___sfd__h145762)
begin
case (guard__h136028)
2'b0:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137 =
_theResult___snd__h145260[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137 =
_theResult___sfd__h145762;
endcase
end
always@(requestR or
_theResult___snd__h145260 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279 or
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
_theResult___snd__h145260[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4281;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4279;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q137;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4285 =
23'd0;
endcase
end
always@(guard__h136028 or
_theResult___snd__h145260 or
out_sfd__h145765 or _theResult___sfd__h145762)
begin
case (guard__h136028)
2'b0, 2'b01:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 =
_theResult___snd__h145260[56:34];
2'b10:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 =
out_sfd__h145765;
2'b11:
CASE_guard36028_0b0_theResult___snd45260_BITS__ETC__q138 =
_theResult___sfd__h145762;
endcase
end
always@(guard__h146250 or sfdin__h155725 or _theResult___sfd__h156258)
begin
case (guard__h146250)
2'b0:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139 =
sfdin__h155725[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139 =
_theResult___sfd__h156258;
endcase
end
always@(requestR or
sfdin__h155725 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308 or
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306 or
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
sfdin__h155725[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4308;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
IF_IF_IF_IF_3970_MINUS_SEXT_IF_requestR_3_BIT__ETC___d4306;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q139;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4312 =
23'd0;
endcase
end
always@(guard__h146250 or
sfdin__h155725 or out_sfd__h156261 or _theResult___sfd__h156258)
begin
case (guard__h146250)
2'b0, 2'b01:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 =
sfdin__h155725[56:34];
2'b10:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 =
out_sfd__h156261;
2'b11:
CASE_guard46250_0b0_sfdin55725_BITS_56_TO_34_0_ETC__q140 =
_theResult___sfd__h156258;
endcase
end
always@(guard__h156369 or
_theResult___snd__h165625 or _theResult___sfd__h166157)
begin
case (guard__h156369)
2'b0:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141 =
_theResult___snd__h165625[56:34];
2'b01, 2'b10, 2'b11:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141 =
_theResult___sfd__h166157;
endcase
end
always@(requestR or
_theResult___snd__h165625 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327 or
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325 or
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
_theResult___snd__h165625[56:34];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4327;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_requestR_ETC___d4325;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q141;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4331 =
23'd0;
endcase
end
always@(guard__h156369 or
_theResult___snd__h165625 or
out_sfd__h166160 or _theResult___sfd__h166157)
begin
case (guard__h156369)
2'b0, 2'b01:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 =
_theResult___snd__h165625[56:34];
2'b10:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 =
out_sfd__h166160;
2'b11:
CASE_guard56369_0b0_theResult___snd65625_BITS__ETC__q142 =
_theResult___sfd__h166157;
endcase
end
always@(guard__h126038 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h126038)
2'b0, 2'b01, 2'b10:
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard26038_0b0_requestR_BITS_191_TO_128_B_ETC__q143 =
guard__h126038 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h126038)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144 =
(guard__h126038 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h126038 == 2'b01 || guard__h126038 == 2'b10 ||
guard__h126038 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q144 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h136028 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h136028)
2'b0, 2'b01, 2'b10:
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard36028_0b0_requestR_BITS_191_TO_128_B_ETC__q145 =
guard__h136028 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h136028)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146 =
(guard__h136028 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h136028 == 2'b01 || guard__h136028 == 2'b10 ||
guard__h136028 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q146 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h146250 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h146250)
2'b0, 2'b01, 2'b10:
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard46250_0b0_requestR_BITS_191_TO_128_B_ETC__q147 =
guard__h146250 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h146250)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148 =
(guard__h146250 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h146250 == 2'b01 || guard__h146250 == 2'b10 ||
guard__h146250 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q148 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h156369 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h156369)
2'b0, 2'b01, 2'b10:
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149 =
requestR_BITS_191_TO_128__q1[63];
2'd3:
CASE_guard56369_0b0_requestR_BITS_191_TO_128_B_ETC__q149 =
guard__h156369 == 2'b11 && requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h156369)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150 =
requestR_BITS_191_TO_128__q1[63];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150 =
(guard__h156369 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63] :
(guard__h156369 == 2'b01 || guard__h156369 == 2'b10 ||
guard__h156369 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q150 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63];
endcase
end
always@(guard__h181312 or
_theResult___fst_exp__h190506 or _theResult___exp__h191161)
begin
case (guard__h181312)
2'b0:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159 =
_theResult___fst_exp__h190506;
2'b01, 2'b10, 2'b11:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159 =
_theResult___exp__h191161;
endcase
end
always@(requestR or
_theResult___fst_exp__h190506 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667 or
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
_theResult___fst_exp__h190506;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4669;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d4667;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q159;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4673 =
11'd0;
endcase
end
always@(guard__h181312 or
_theResult___fst_exp__h190506 or
out_exp__h191164 or _theResult___exp__h191161)
begin
case (guard__h181312)
2'b0, 2'b01:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 =
_theResult___fst_exp__h190506;
2'b10:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 =
out_exp__h191164;
2'b11:
CASE_guard81312_0b0_theResult___fst_exp90506_0_ETC__q160 =
_theResult___exp__h191161;
endcase
end
always@(guard__h191853 or
_theResult___fst_exp__h201334 or _theResult___exp__h202063)
begin
case (guard__h191853)
2'b0:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161 =
_theResult___fst_exp__h201334;
2'b01, 2'b10, 2'b11:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161 =
_theResult___exp__h202063;
endcase
end
always@(requestR or
_theResult___fst_exp__h201334 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992 or
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
_theResult___fst_exp__h201334;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4994;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d4992;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q161;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d4998 =
11'd0;
endcase
end
always@(guard__h191853 or
_theResult___fst_exp__h201334 or
out_exp__h202066 or _theResult___exp__h202063)
begin
case (guard__h191853)
2'b0, 2'b01:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 =
_theResult___fst_exp__h201334;
2'b10:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 =
out_exp__h202066;
2'b11:
CASE_guard91853_0b0_theResult___fst_exp01334_0_ETC__q162 =
_theResult___exp__h202063;
endcase
end
always@(guard__h202175 or
_theResult___fst_exp__h211398 or _theResult___exp__h212078)
begin
case (guard__h202175)
2'b0:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163 =
_theResult___fst_exp__h211398;
2'b01, 2'b10, 2'b11:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163 =
_theResult___exp__h212078;
endcase
end
always@(requestR or
_theResult___fst_exp__h211398 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061 or
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
_theResult___fst_exp__h211398;
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5063;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5061;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q163;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5067 =
11'd0;
endcase
end
always@(guard__h202175 or
_theResult___fst_exp__h211398 or
out_exp__h212081 or _theResult___exp__h212078)
begin
case (guard__h202175)
2'b0, 2'b01:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 =
_theResult___fst_exp__h211398;
2'b10:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 =
out_exp__h212081;
2'b11:
CASE_guard02175_0b0_theResult___fst_exp11398_0_ETC__q164 =
_theResult___exp__h212078;
endcase
end
always@(guard__h181312 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h181312)
2'b0, 2'b01, 2'b10:
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard81312_0b0_requestR_BITS_191_TO_128_B_ETC__q165 =
guard__h181312 == 2'b11 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h181312)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166 =
(guard__h181312 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
(guard__h181312 == 2'b01 || guard__h181312 == 2'b10 ||
guard__h181312 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q166 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h191853 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h191853)
2'b0, 2'b01, 2'b10:
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard91853_0b0_requestR_BITS_191_TO_128_B_ETC__q167 =
guard__h191853 == 2'b11 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h191853)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168 =
(guard__h191853 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
(guard__h191853 == 2'b01 || guard__h191853 == 2'b10 ||
guard__h191853 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q168 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h202175 or requestR_BITS_191_TO_128__q1)
begin
case (guard__h202175)
2'b0, 2'b01, 2'b10:
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
2'd3:
CASE_guard02175_0b0_requestR_BITS_191_TO_128_B_ETC__q169 =
guard__h202175 == 2'b11 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(requestR or requestR_BITS_191_TO_128__q1 or guard__h202175)
begin
case (requestR[194:192])
3'h2, 3'h3:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170 =
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
3'h4:
CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170 =
(guard__h202175 == 2'b0) ?
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31] :
(guard__h202175 == 2'b01 || guard__h202175 == 2'b10 ||
guard__h202175 == 2'b11) &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
default: CASE_requestR_BITS_194_TO_192_0x2_requestR_BIT_ETC__q170 =
requestR[194:192] == 3'h1 &&
requestR_BITS_191_TO_128__q1[63:32] == 32'hFFFFFFFF &&
requestR_BITS_191_TO_128__q1[31];
endcase
end
always@(guard__h181312 or
_theResult___snd__h190457 or _theResult___sfd__h191162)
begin
case (guard__h181312)
2'b0:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171 =
_theResult___snd__h190457[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171 =
_theResult___sfd__h191162;
endcase
end
always@(requestR or
_theResult___snd__h190457 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094 or
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
_theResult___snd__h190457[56:5];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5096;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5094;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q171;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5100 =
52'd0;
endcase
end
always@(guard__h181312 or
_theResult___snd__h190457 or
out_sfd__h191165 or _theResult___sfd__h191162)
begin
case (guard__h181312)
2'b0, 2'b01:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 =
_theResult___snd__h190457[56:5];
2'b10:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 =
out_sfd__h191165;
2'b11:
CASE_guard81312_0b0_theResult___snd90457_BITS__ETC__q172 =
_theResult___sfd__h191162;
endcase
end
always@(guard__h191853 or sfdin__h201328 or _theResult___sfd__h202064)
begin
case (guard__h191853)
2'b0:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173 =
sfdin__h201328[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173 =
_theResult___sfd__h202064;
endcase
end
always@(requestR or
sfdin__h201328 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123 or
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121 or
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
sfdin__h201328[56:5];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5123;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
IF_IF_IF_IF_3074_MINUS_SEXT_IF_IF_requestR_3_B_ETC___d5121;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q173;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5127 =
52'd0;
endcase
end
always@(guard__h191853 or
sfdin__h201328 or out_sfd__h202067 or _theResult___sfd__h202064)
begin
case (guard__h191853)
2'b0, 2'b01:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 =
sfdin__h201328[56:5];
2'b10:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 =
out_sfd__h202067;
2'b11:
CASE_guard91853_0b0_sfdin01328_BITS_56_TO_5_0b_ETC__q174 =
_theResult___sfd__h202064;
endcase
end
always@(guard__h202175 or
_theResult___snd__h211344 or _theResult___sfd__h212079)
begin
case (guard__h202175)
2'b0:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175 =
_theResult___snd__h211344[56:5];
2'b01, 2'b10, 2'b11:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175 =
_theResult___sfd__h212079;
endcase
end
always@(requestR or
_theResult___snd__h211344 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142 or
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140 or
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175)
begin
case (requestR[194:192])
3'h1:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
_theResult___snd__h211344[56:5];
3'h2:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5142;
3'h3:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
IF_IF_IF_IF_IF_requestR_3_BIT_214_4_THEN_reque_ETC___d5140;
3'h4:
IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q175;
default: IF_IF_requestR_3_BIT_214_4_THEN_requestR_3_BIT_ETC___d5146 =
52'd0;
endcase
end
always@(guard__h202175 or
_theResult___snd__h211344 or
out_sfd__h212082 or _theResult___sfd__h212079)
begin
case (guard__h202175)
2'b0, 2'b01:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 =
_theResult___snd__h211344[56:5];
2'b10:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 =
out_sfd__h212082;
2'b11:
CASE_guard02175_0b0_theResult___snd11344_BITS__ETC__q176 =
_theResult___sfd__h212079;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
stateR <= `BSV_ASSIGNMENT_DELAY 2'd0;
end
else
begin
if (stateR$EN) stateR <= `BSV_ASSIGNMENT_DELAY stateR$D_IN;
end
if (requestR$EN) requestR <= `BSV_ASSIGNMENT_DELAY requestR$D_IN;
if (resultR$EN) resultR <= `BSV_ASSIGNMENT_DELAY resultR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
requestR = 215'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
resultR = 70'h2AAAAAAAAAAAAAAAAA;
stateR = 2'h2;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h1224 = $stime;
#0;
end
v__h1218 = v__h1224 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFADD: ", v__h1218);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h1777 = $stime;
#0;
end
v__h1771 = v__h1777 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSUB: ", v__h1771);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h1966 = $stime;
#0;
end
v__h1960 = v__h1966 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMUL: ", v__h1960);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2168 = $stime;
#0;
end
v__h2162 = v__h2168 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMADD_S ", v__h2162);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2418 = $stime;
#0;
end
v__h2412 = v__h2418 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMSUB_S ", v__h2412);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2593 = $stime;
#0;
end
v__h2587 = v__h2593 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMADD_S ", v__h2587);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2768 = $stime;
#0;
end
v__h2762 = v__h2768 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMSUB_S ", v__h2762);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h2950 = $stime;
#0;
end
v__h2944 = v__h2950 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFDIV_S ", v__h2944);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3139 = $stime;
#0;
end
v__h3133 = v__h3139 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSQRT_S ", v__h3133);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3337 = $stime;
#0;
end
v__h3331 = v__h3337 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJ_S ", v__h3331);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3520 = $stime;
#0;
end
v__h3514 = v__h3520 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJN_S ", v__h3514);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h3693 = $stime;
#0;
end
v__h3687 = v__h3693 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJX_S ", v__h3687);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_1_6___d27)
begin
v__h3882 = $stime;
#0;
end
v__h3876 = v__h3882 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_L ", v__h3876);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702)
$write("v1 = %08x, rmd = ", requestR[191:128]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
(requestR[194:192] == 3'h0 ||
requestR[194:192] != 3'h1 && requestR[194:192] != 3'h2 &&
requestR[194:192] != 3'h3 &&
requestR[194:192] != 3'h4))
$write("<Round Mode: Nearest Even>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h4)
$write("<Round Mode: Nearest Away From Zero>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h3)
$write("<Round Mode: +Infinity>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h2)
$write("<Round Mode: -Infinity>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702 &&
requestR[194:192] == 3'h1)
$write("<Round Mode: Zero>");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_L && NOT_verbosity_ULE_2_01___d702)
$display(" Result: (%08x, %05b)", res__h3932, fcsr__h3933);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_LU && NOT_verbosity_ULE_1_6___d27)
begin
v__h16640 = $stime;
#0;
end
v__h16634 = v__h16640 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_LU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_LU ", v__h16634);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_W && NOT_verbosity_ULE_1_6___d27)
begin
v__h28741 = $stime;
#0;
end
v__h28735 = v__h28741 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_W && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_W ", v__h28735);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_WU && NOT_verbosity_ULE_1_6___d27)
begin
v__h35941 = $stime;
#0;
end
v__h35935 = v__h35941 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_WU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_WU ", v__h35935);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h42829 = $stime;
#0;
end
v__h42823 = v__h42829 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_L_S ", v__h42823);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h44905 = $stime;
#0;
end
v__h44899 = v__h44905 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_LU_S ", v__h44899);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h45689 = $stime;
#0;
end
v__h45683 = v__h45689 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_W_S ", v__h45683);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h47303 = $stime;
#0;
end
v__h47297 = v__h47303 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_WU_S ", v__h47297);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h48090 = $stime;
#0;
end
v__h48084 = v__h48090 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMIN_S ", v__h48084);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h50764 = $stime;
#0;
end
v__h50758 = v__h50764 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMAX_S ", v__h50758);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_W_X && NOT_verbosity_ULE_1_6___d27)
begin
v__h53335 = $stime;
#0;
end
v__h53329 = v__h53335 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_W_X && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_W_X ", v__h53329);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_W && NOT_verbosity_ULE_1_6___d27)
begin
v__h53495 = $stime;
#0;
end
v__h53489 = v__h53495 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_W && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_X_W ", v__h53489);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h53671 = $stime;
#0;
end
v__h53665 = v__h53671 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFEQ_S ", v__h53665);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h55194 = $stime;
#0;
end
v__h55188 = v__h55194 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLT_S ", v__h55188);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h56303 = $stime;
#0;
end
v__h56297 = v__h56303 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLE_S ", v__h56297);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h57430 = $stime;
#0;
end
v__h57424 = v__h57430 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCLASS_S ", v__h57424);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h57911 = $stime;
#0;
end
v__h57905 = v__h57911 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFADD_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFADD_D ", v__h57905);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58124 = $stime;
#0;
end
v__h58118 = v__h58124 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSUB_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSUB_D ", v__h58118);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58311 = $stime;
#0;
end
v__h58305 = v__h58311 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMUL_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMUL_D ", v__h58305);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58491 = $stime;
#0;
end
v__h58485 = v__h58491 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMADD_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMADD_D ", v__h58485);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58676 = $stime;
#0;
end
v__h58670 = v__h58676 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMSUB_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMSUB_D ", v__h58670);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h58848 = $stime;
#0;
end
v__h58842 = v__h58848 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMADD_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMADD_D ", v__h58842);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59020 = $stime;
#0;
end
v__h59014 = v__h59020 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFNMSUB_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFNMSUB_D ", v__h59014);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59199 = $stime;
#0;
end
v__h59193 = v__h59199 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFDIV_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFDIV_D ", v__h59193);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59386 = $stime;
#0;
end
v__h59380 = v__h59386 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSQRT_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSQRT_D ", v__h59380);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59583 = $stime;
#0;
end
v__h59577 = v__h59583 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJ_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJ_D ", v__h59577);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59744 = $stime;
#0;
end
v__h59738 = v__h59744 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJN_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJN_D ", v__h59738);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h59907 = $stime;
#0;
end
v__h59901 = v__h59907 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFSGNJX_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFSGNJX_D ", v__h59901);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_W && NOT_verbosity_ULE_1_6___d27)
begin
v__h60075 = $stime;
#0;
end
v__h60069 = v__h60075 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_W && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_W ", v__h60069);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_WU && NOT_verbosity_ULE_1_6___d27)
begin
v__h71274 = $stime;
#0;
end
v__h71268 = v__h71274 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_WU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_WU ", v__h71268);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h82193 = $stime;
#0;
end
v__h82187 = v__h82193 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_W_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_W_D ", v__h82187);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h83807 = $stime;
#0;
end
v__h83801 = v__h83807 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_WU_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_WU_D ", v__h83801);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_L && NOT_verbosity_ULE_1_6___d27)
begin
v__h84594 = $stime;
#0;
end
v__h84588 = v__h84594 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_L && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_L ", v__h84588);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_LU && NOT_verbosity_ULE_1_6___d27)
begin
v__h97596 = $stime;
#0;
end
v__h97590 = v__h97596 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_LU && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_LU ", v__h97590);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h110093 = $stime;
#0;
end
v__h110087 = v__h110093 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_L_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_L_D ", v__h110087);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h112152 = $stime;
#0;
end
v__h112146 = v__h112152 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_LU_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_LU_D ", v__h112146);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h112936 = $stime;
#0;
end
v__h112930 = v__h112936 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_S_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_S_D ", v__h112930);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_S && NOT_verbosity_ULE_1_6___d27)
begin
v__h167802 = $stime;
#0;
end
v__h167796 = v__h167802 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCVT_D_S && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCVT_D_S ", v__h167796);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h213792 = $stime;
#0;
end
v__h213786 = v__h213792 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMIN_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMIN_D ", v__h213786);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h218378 = $stime;
#0;
end
v__h218372 = v__h218378 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMAX_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMAX_D ", v__h218372);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h222864 = $stime;
#0;
end
v__h222858 = v__h222864 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFEQ_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFEQ_D ", v__h222858);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h225599 = $stime;
#0;
end
v__h225593 = v__h225599 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLT_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLT_D ", v__h225593);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h227516 = $stime;
#0;
end
v__h227510 = v__h227516 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFLE_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFLE_D ", v__h227510);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_D_X && NOT_verbosity_ULE_1_6___d27)
begin
v__h229453 = $stime;
#0;
end
v__h229447 = v__h229453 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_D_X && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_D_X ", v__h229447);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h229605 = $stime;
#0;
end
v__h229599 = v__h229605 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFMV_X_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFMV_X_D ", v__h229599);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_D && NOT_verbosity_ULE_1_6___d27)
begin
v__h229762 = $stime;
#0;
end
v__h229756 = v__h229762 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_doFCLASS_D && NOT_verbosity_ULE_1_6___d27)
$display("%0d: FBox_Core.doFCLASS_D ", v__h229756);
end
// synopsys translate_on
endmodule // mkFBox_Core
|
// (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 0
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2014.3" *)
(* CHECK_LICENSE_TYPE = "processing_system7_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "processing_system7_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2014.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=0,x_ipLanguage=VERILOG,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=48,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=32,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=true,C_PACKAGE_NAME=clg400}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module processing_system7_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
FCLK_CLK0,
FCLK_CLK3,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *)
output wire ENET0_PTP_DELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *)
output wire ENET0_PTP_DELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *)
output wire ENET0_PTP_PDELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *)
output wire ENET0_PTP_PDELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *)
output wire ENET0_PTP_PDELAY_RESP_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *)
output wire ENET0_PTP_PDELAY_RESP_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *)
output wire ENET0_PTP_SYNC_FRAME_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *)
output wire ENET0_PTP_SYNC_FRAME_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *)
output wire ENET0_SOF_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *)
output wire ENET0_SOF_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_I" *)
input wire [47 : 0] GPIO_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_O" *)
output wire [47 : 0] GPIO_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:gpio:1.0 GPIO_0 TRI_T" *)
output wire [47 : 0] GPIO_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *)
input wire I2C0_SDA_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *)
output wire I2C0_SDA_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *)
output wire I2C0_SDA_T;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *)
input wire I2C0_SCL_I;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *)
output wire I2C0_SCL_O;
(* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *)
output wire I2C0_SCL_T;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_1 PORT_INDCTL" *)
output wire [1 : 0] USB1_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_1 VBUS_PWRSELECT" *)
output wire USB1_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_1 VBUS_PWRFAULT" *)
input wire USB1_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARVALID" *)
output wire M_AXI_GP1_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWVALID" *)
output wire M_AXI_GP1_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BREADY" *)
output wire M_AXI_GP1_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RREADY" *)
output wire M_AXI_GP1_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WLAST" *)
output wire M_AXI_GP1_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WVALID" *)
output wire M_AXI_GP1_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARID" *)
output wire [11 : 0] M_AXI_GP1_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWID" *)
output wire [11 : 0] M_AXI_GP1_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WID" *)
output wire [11 : 0] M_AXI_GP1_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARBURST" *)
output wire [1 : 0] M_AXI_GP1_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARLOCK" *)
output wire [1 : 0] M_AXI_GP1_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARSIZE" *)
output wire [2 : 0] M_AXI_GP1_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWBURST" *)
output wire [1 : 0] M_AXI_GP1_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWLOCK" *)
output wire [1 : 0] M_AXI_GP1_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWSIZE" *)
output wire [2 : 0] M_AXI_GP1_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARPROT" *)
output wire [2 : 0] M_AXI_GP1_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWPROT" *)
output wire [2 : 0] M_AXI_GP1_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARADDR" *)
output wire [31 : 0] M_AXI_GP1_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWADDR" *)
output wire [31 : 0] M_AXI_GP1_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WDATA" *)
output wire [31 : 0] M_AXI_GP1_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARCACHE" *)
output wire [3 : 0] M_AXI_GP1_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARLEN" *)
output wire [3 : 0] M_AXI_GP1_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARQOS" *)
output wire [3 : 0] M_AXI_GP1_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWCACHE" *)
output wire [3 : 0] M_AXI_GP1_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWLEN" *)
output wire [3 : 0] M_AXI_GP1_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWQOS" *)
output wire [3 : 0] M_AXI_GP1_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WSTRB" *)
output wire [3 : 0] M_AXI_GP1_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP1_ACLK CLK" *)
input wire M_AXI_GP1_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 ARREADY" *)
input wire M_AXI_GP1_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 AWREADY" *)
input wire M_AXI_GP1_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BVALID" *)
input wire M_AXI_GP1_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RLAST" *)
input wire M_AXI_GP1_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RVALID" *)
input wire M_AXI_GP1_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 WREADY" *)
input wire M_AXI_GP1_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BID" *)
input wire [11 : 0] M_AXI_GP1_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RID" *)
input wire [11 : 0] M_AXI_GP1_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 BRESP" *)
input wire [1 : 0] M_AXI_GP1_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RRESP" *)
input wire [1 : 0] M_AXI_GP1_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP1 RDATA" *)
input wire [31 : 0] M_AXI_GP1_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARREADY" *)
output wire S_AXI_HP1_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWREADY" *)
output wire S_AXI_HP1_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 BVALID" *)
output wire S_AXI_HP1_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RLAST" *)
output wire S_AXI_HP1_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RVALID" *)
output wire S_AXI_HP1_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WREADY" *)
output wire S_AXI_HP1_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 BRESP" *)
output wire [1 : 0] S_AXI_HP1_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RRESP" *)
output wire [1 : 0] S_AXI_HP1_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 BID" *)
output wire [5 : 0] S_AXI_HP1_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RID" *)
output wire [5 : 0] S_AXI_HP1_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RDATA" *)
output wire [63 : 0] S_AXI_HP1_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL RCOUNT" *)
output wire [7 : 0] S_AXI_HP1_RCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL WCOUNT" *)
output wire [7 : 0] S_AXI_HP1_WCOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL RACOUNT" *)
output wire [2 : 0] S_AXI_HP1_RACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL WACOUNT" *)
output wire [5 : 0] S_AXI_HP1_WACOUNT;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP1_ACLK CLK" *)
input wire S_AXI_HP1_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARVALID" *)
input wire S_AXI_HP1_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWVALID" *)
input wire S_AXI_HP1_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 BREADY" *)
input wire S_AXI_HP1_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL RDISSUECAPEN" *)
input wire S_AXI_HP1_RDISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 RREADY" *)
input wire S_AXI_HP1_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WLAST" *)
input wire S_AXI_HP1_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP1_FIFO_CTRL WRISSUECAPEN" *)
input wire S_AXI_HP1_WRISSUECAP1_EN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WVALID" *)
input wire S_AXI_HP1_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARBURST" *)
input wire [1 : 0] S_AXI_HP1_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARLOCK" *)
input wire [1 : 0] S_AXI_HP1_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARSIZE" *)
input wire [2 : 0] S_AXI_HP1_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWBURST" *)
input wire [1 : 0] S_AXI_HP1_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWLOCK" *)
input wire [1 : 0] S_AXI_HP1_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWSIZE" *)
input wire [2 : 0] S_AXI_HP1_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARPROT" *)
input wire [2 : 0] S_AXI_HP1_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWPROT" *)
input wire [2 : 0] S_AXI_HP1_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARADDR" *)
input wire [31 : 0] S_AXI_HP1_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWADDR" *)
input wire [31 : 0] S_AXI_HP1_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARCACHE" *)
input wire [3 : 0] S_AXI_HP1_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARLEN" *)
input wire [3 : 0] S_AXI_HP1_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARQOS" *)
input wire [3 : 0] S_AXI_HP1_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWCACHE" *)
input wire [3 : 0] S_AXI_HP1_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWLEN" *)
input wire [3 : 0] S_AXI_HP1_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWQOS" *)
input wire [3 : 0] S_AXI_HP1_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 ARID" *)
input wire [5 : 0] S_AXI_HP1_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 AWID" *)
input wire [5 : 0] S_AXI_HP1_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WID" *)
input wire [5 : 0] S_AXI_HP1_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WDATA" *)
input wire [63 : 0] S_AXI_HP1_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP1 WSTRB" *)
input wire [7 : 0] S_AXI_HP1_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK3 CLK" *)
output wire FCLK_CLK3;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(48),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(32),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("true"),
.C_PACKAGE_NAME("clg400")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),
.ENET0_SOF_RX(ENET0_SOF_RX),
.ENET0_SOF_TX(ENET0_SOF_TX),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(GPIO_I),
.GPIO_O(GPIO_O),
.GPIO_T(GPIO_T),
.I2C0_SDA_I(I2C0_SDA_I),
.I2C0_SDA_O(I2C0_SDA_O),
.I2C0_SDA_T(I2C0_SDA_T),
.I2C0_SCL_I(I2C0_SCL_I),
.I2C0_SCL_O(I2C0_SCL_O),
.I2C0_SCL_T(I2C0_SCL_T),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(),
.TTC0_WAVE1_OUT(),
.TTC0_WAVE2_OUT(),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(USB1_PORT_INDCTL),
.USB1_VBUS_PWRSELECT(USB1_VBUS_PWRSELECT),
.USB1_VBUS_PWRFAULT(USB1_VBUS_PWRFAULT),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(),
.M_AXI_GP0_AWVALID(),
.M_AXI_GP0_BREADY(),
.M_AXI_GP0_RREADY(),
.M_AXI_GP0_WLAST(),
.M_AXI_GP0_WVALID(),
.M_AXI_GP0_ARID(),
.M_AXI_GP0_AWID(),
.M_AXI_GP0_WID(),
.M_AXI_GP0_ARBURST(),
.M_AXI_GP0_ARLOCK(),
.M_AXI_GP0_ARSIZE(),
.M_AXI_GP0_AWBURST(),
.M_AXI_GP0_AWLOCK(),
.M_AXI_GP0_AWSIZE(),
.M_AXI_GP0_ARPROT(),
.M_AXI_GP0_AWPROT(),
.M_AXI_GP0_ARADDR(),
.M_AXI_GP0_AWADDR(),
.M_AXI_GP0_WDATA(),
.M_AXI_GP0_ARCACHE(),
.M_AXI_GP0_ARLEN(),
.M_AXI_GP0_ARQOS(),
.M_AXI_GP0_AWCACHE(),
.M_AXI_GP0_AWLEN(),
.M_AXI_GP0_AWQOS(),
.M_AXI_GP0_WSTRB(),
.M_AXI_GP0_ACLK(1'B0),
.M_AXI_GP0_ARREADY(1'B0),
.M_AXI_GP0_AWREADY(1'B0),
.M_AXI_GP0_BVALID(1'B0),
.M_AXI_GP0_RLAST(1'B0),
.M_AXI_GP0_RVALID(1'B0),
.M_AXI_GP0_WREADY(1'B0),
.M_AXI_GP0_BID(12'B0),
.M_AXI_GP0_RID(12'B0),
.M_AXI_GP0_BRESP(2'B0),
.M_AXI_GP0_RRESP(2'B0),
.M_AXI_GP0_RDATA(32'B0),
.M_AXI_GP1_ARVALID(M_AXI_GP1_ARVALID),
.M_AXI_GP1_AWVALID(M_AXI_GP1_AWVALID),
.M_AXI_GP1_BREADY(M_AXI_GP1_BREADY),
.M_AXI_GP1_RREADY(M_AXI_GP1_RREADY),
.M_AXI_GP1_WLAST(M_AXI_GP1_WLAST),
.M_AXI_GP1_WVALID(M_AXI_GP1_WVALID),
.M_AXI_GP1_ARID(M_AXI_GP1_ARID),
.M_AXI_GP1_AWID(M_AXI_GP1_AWID),
.M_AXI_GP1_WID(M_AXI_GP1_WID),
.M_AXI_GP1_ARBURST(M_AXI_GP1_ARBURST),
.M_AXI_GP1_ARLOCK(M_AXI_GP1_ARLOCK),
.M_AXI_GP1_ARSIZE(M_AXI_GP1_ARSIZE),
.M_AXI_GP1_AWBURST(M_AXI_GP1_AWBURST),
.M_AXI_GP1_AWLOCK(M_AXI_GP1_AWLOCK),
.M_AXI_GP1_AWSIZE(M_AXI_GP1_AWSIZE),
.M_AXI_GP1_ARPROT(M_AXI_GP1_ARPROT),
.M_AXI_GP1_AWPROT(M_AXI_GP1_AWPROT),
.M_AXI_GP1_ARADDR(M_AXI_GP1_ARADDR),
.M_AXI_GP1_AWADDR(M_AXI_GP1_AWADDR),
.M_AXI_GP1_WDATA(M_AXI_GP1_WDATA),
.M_AXI_GP1_ARCACHE(M_AXI_GP1_ARCACHE),
.M_AXI_GP1_ARLEN(M_AXI_GP1_ARLEN),
.M_AXI_GP1_ARQOS(M_AXI_GP1_ARQOS),
.M_AXI_GP1_AWCACHE(M_AXI_GP1_AWCACHE),
.M_AXI_GP1_AWLEN(M_AXI_GP1_AWLEN),
.M_AXI_GP1_AWQOS(M_AXI_GP1_AWQOS),
.M_AXI_GP1_WSTRB(M_AXI_GP1_WSTRB),
.M_AXI_GP1_ACLK(M_AXI_GP1_ACLK),
.M_AXI_GP1_ARREADY(M_AXI_GP1_ARREADY),
.M_AXI_GP1_AWREADY(M_AXI_GP1_AWREADY),
.M_AXI_GP1_BVALID(M_AXI_GP1_BVALID),
.M_AXI_GP1_RLAST(M_AXI_GP1_RLAST),
.M_AXI_GP1_RVALID(M_AXI_GP1_RVALID),
.M_AXI_GP1_WREADY(M_AXI_GP1_WREADY),
.M_AXI_GP1_BID(M_AXI_GP1_BID),
.M_AXI_GP1_RID(M_AXI_GP1_RID),
.M_AXI_GP1_BRESP(M_AXI_GP1_BRESP),
.M_AXI_GP1_RRESP(M_AXI_GP1_RRESP),
.M_AXI_GP1_RDATA(M_AXI_GP1_RDATA),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(32'B0),
.S_AXI_HP0_WSTRB(4'B0),
.S_AXI_HP1_ARREADY(S_AXI_HP1_ARREADY),
.S_AXI_HP1_AWREADY(S_AXI_HP1_AWREADY),
.S_AXI_HP1_BVALID(S_AXI_HP1_BVALID),
.S_AXI_HP1_RLAST(S_AXI_HP1_RLAST),
.S_AXI_HP1_RVALID(S_AXI_HP1_RVALID),
.S_AXI_HP1_WREADY(S_AXI_HP1_WREADY),
.S_AXI_HP1_BRESP(S_AXI_HP1_BRESP),
.S_AXI_HP1_RRESP(S_AXI_HP1_RRESP),
.S_AXI_HP1_BID(S_AXI_HP1_BID),
.S_AXI_HP1_RID(S_AXI_HP1_RID),
.S_AXI_HP1_RDATA(S_AXI_HP1_RDATA),
.S_AXI_HP1_RCOUNT(S_AXI_HP1_RCOUNT),
.S_AXI_HP1_WCOUNT(S_AXI_HP1_WCOUNT),
.S_AXI_HP1_RACOUNT(S_AXI_HP1_RACOUNT),
.S_AXI_HP1_WACOUNT(S_AXI_HP1_WACOUNT),
.S_AXI_HP1_ACLK(S_AXI_HP1_ACLK),
.S_AXI_HP1_ARVALID(S_AXI_HP1_ARVALID),
.S_AXI_HP1_AWVALID(S_AXI_HP1_AWVALID),
.S_AXI_HP1_BREADY(S_AXI_HP1_BREADY),
.S_AXI_HP1_RDISSUECAP1_EN(S_AXI_HP1_RDISSUECAP1_EN),
.S_AXI_HP1_RREADY(S_AXI_HP1_RREADY),
.S_AXI_HP1_WLAST(S_AXI_HP1_WLAST),
.S_AXI_HP1_WRISSUECAP1_EN(S_AXI_HP1_WRISSUECAP1_EN),
.S_AXI_HP1_WVALID(S_AXI_HP1_WVALID),
.S_AXI_HP1_ARBURST(S_AXI_HP1_ARBURST),
.S_AXI_HP1_ARLOCK(S_AXI_HP1_ARLOCK),
.S_AXI_HP1_ARSIZE(S_AXI_HP1_ARSIZE),
.S_AXI_HP1_AWBURST(S_AXI_HP1_AWBURST),
.S_AXI_HP1_AWLOCK(S_AXI_HP1_AWLOCK),
.S_AXI_HP1_AWSIZE(S_AXI_HP1_AWSIZE),
.S_AXI_HP1_ARPROT(S_AXI_HP1_ARPROT),
.S_AXI_HP1_AWPROT(S_AXI_HP1_AWPROT),
.S_AXI_HP1_ARADDR(S_AXI_HP1_ARADDR),
.S_AXI_HP1_AWADDR(S_AXI_HP1_AWADDR),
.S_AXI_HP1_ARCACHE(S_AXI_HP1_ARCACHE),
.S_AXI_HP1_ARLEN(S_AXI_HP1_ARLEN),
.S_AXI_HP1_ARQOS(S_AXI_HP1_ARQOS),
.S_AXI_HP1_AWCACHE(S_AXI_HP1_AWCACHE),
.S_AXI_HP1_AWLEN(S_AXI_HP1_AWLEN),
.S_AXI_HP1_AWQOS(S_AXI_HP1_AWQOS),
.S_AXI_HP1_ARID(S_AXI_HP1_ARID),
.S_AXI_HP1_AWID(S_AXI_HP1_AWID),
.S_AXI_HP1_WID(S_AXI_HP1_WID),
.S_AXI_HP1_WDATA(S_AXI_HP1_WDATA),
.S_AXI_HP1_WSTRB(S_AXI_HP1_WSTRB),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(FCLK_CLK3),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_ibs_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_ibs_rom.dat", ram0);
$readmemh("./Loop_loop_height_ibs_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_ibs(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_ibs_rom Loop_loop_height_ibs_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
`default_nettype none
module plle2_test
(
input wire CLK,
input wire RST,
output wire CLKFBOUT,
input wire CLKFBIN,
input wire I_PWRDWN,
input wire I_CLKINSEL,
output wire O_LOCKED,
output wire [5:0] O_CNT
);
// "INTERNAL" - PLL's internal feedback
// "BUF" - Feedback through a BUFG
// "EXTERNAL" - Feedback external to the FPGA chip (use CLKFB* ports)
parameter FEEDBACK = "INTERNAL";
// ============================================================================
// Input clock divider (to get different clkins)
wire clk100;
reg clk50;
assign clk100 = CLK;
always @(posedge clk100)
clk50 <= !clk50;
wire clk50_bufg;
BUFG bufgctrl (.I(clk50), .O(clk50_bufg));
// ============================================================================
// The PLL
wire clk_fb_o;
wire clk_fb_i;
wire [5:0] clk;
wire [5:0] gclk;
PLLE2_ADV #
(
.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.CLKIN1_PERIOD (20.0), // 50MHz
.CLKIN2_PERIOD (10.0), // 100MHz
/*
.CLKFBOUT_MULT (16),
.CLKFBOUT_PHASE (0.0),
.CLKOUT0_DIVIDE (16),
.CLKOUT0_DUTY_CYCLE (0.53125),
.CLKOUT0_PHASE (45.0),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_DUTY_CYCLE (0.5),
.CLKOUT1_PHASE (90.0),
.CLKOUT2_DIVIDE (48),
.CLKOUT2_DUTY_CYCLE (0.5),
.CLKOUT2_PHASE (135.0),
.CLKOUT3_DIVIDE (64),
.CLKOUT3_DUTY_CYCLE (0.5),
.CLKOUT3_PHASE (-45.0),
.CLKOUT4_DIVIDE (80),
.CLKOUT4_DUTY_CYCLE (0.5),
.CLKOUT4_PHASE (-90.0),
.CLKOUT5_DIVIDE (96),
.CLKOUT5_DUTY_CYCLE (0.5),
.CLKOUT5_PHASE (-135.0),
*/
.CLKFBOUT_MULT (16),
.CLKFBOUT_PHASE (0),
.CLKOUT0_DIVIDE (16),
.CLKOUT0_DUTY_CYCLE (53125),
.CLKOUT0_PHASE (45000),
.CLKOUT1_DIVIDE (32),
.CLKOUT1_DUTY_CYCLE (50000),
.CLKOUT1_PHASE (90000),
.CLKOUT2_DIVIDE (48),
.CLKOUT2_DUTY_CYCLE (50000),
.CLKOUT2_PHASE (135000),
.CLKOUT3_DIVIDE (64),
.CLKOUT3_DUTY_CYCLE (50000),
.CLKOUT3_PHASE (-45000),
.CLKOUT4_DIVIDE (80),
.CLKOUT4_DUTY_CYCLE (50000),
.CLKOUT4_PHASE (-90000),
.CLKOUT5_DIVIDE (96),
.CLKOUT5_DUTY_CYCLE (50000),
.CLKOUT5_PHASE (-135000),
.STARTUP_WAIT ("FALSE")
)
pll
(
.CLKIN1 (clk50_bufg),
.CLKIN2 (clk100),
.CLKINSEL (I_CLKINSEL),
.RST (RST),
.PWRDWN (I_PWRDWN),
.LOCKED (O_LOCKED),
.CLKFBIN (clk_fb_i),
.CLKFBOUT (clk_fb_o),
.CLKOUT0 (clk[0]),
.CLKOUT1 (clk[1]),
.CLKOUT2 (clk[2]),
.CLKOUT3 (clk[3]),
.CLKOUT4 (clk[4]),
.CLKOUT5 (clk[5])
);
generate if (FEEDBACK == "INTERNAL") begin
assign clk_fb_i = clk_fb_o;
end else if (FEEDBACK == "BUFG") begin
BUFG clk_fb_buf (.I(clk_fb_o), .O(clk_fb_i));
end else if (FEEDBACK == "EXTERNAL") begin
assign CLKFBOUT = clk_fb_o;
assign clk_fb_i = CLKFBIN;
end endgenerate
// ============================================================================
// Counters
wire rst = RST || !O_LOCKED;
genvar i;
generate for (i=0; i<6; i=i+1) begin
BUFG bufg(.I(clk[i]), .O(gclk[i]));
reg [23:0] counter;
always @(posedge gclk[i] or posedge rst)
if (rst) counter <= 0;
else counter <= counter + 1;
assign O_CNT[i] = counter[21];
end endgenerate
endmodule
|
/*
** -----------------------------------------------------------------------------**
** irq_smart.v
**
** making a simgle interrupt that combines frame sync and compressor done
** waiting for the latest of the 2
**
** Copyright (C) 2008-2010 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.wpage0_inc
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
// control bits:
// [1:0] : 3 - enable waiting for frame sync if compressor done comes earlier
// 2 - disable waiting F.S. (should be disabled for single-frame acquisitions where no frame sync will follow the first frame)
// 1, 0 - don't change F.S. waiting
// [3:2] : 3 - wait for DMA FIFO to be transferred to the system before generating interrupt
// 2 - don't wait for the DMA FIFO to be emptied
// 1, 0 - don't change DMA FIFO waiting
// [15] ; reset requests (mostly fro simulation
// NOTE: now if wait_fs is off, IRQ will be on either FS or done (may be twice)
module irq_smart (sclk, // @negedge
wen, // sync to address and d[0:15]
di, // [15:0] data in, only [3:0] are currently used
frame_sync, // frame sync, single pulse @ negedge sclk
is_compressing, // @posedge clk, needs re-sync
compressor_done, // single pulse @ negedge sclk - compressor finished (some data is still in DMA FIFO)
fifo_empty, // DMA FIFO empty (no gaps between compressor_done and !fifo_empty)
irq); // single cycle $ negedge sclk output to be used as IRQ source
input sclk;
input wen;
input [15:0] di;
input frame_sync; // frame sync, single pulse @ negedge sclk
input is_compressing; // @posedge clk, needs re-sync
input compressor_done; // single pulse @ negedge sclk - compressor finished (some data is still in DMA FIFO)
input fifo_empty; // DMA FIFO empty (no gaps between compressor_done and !fifo_empty)
output irq; // single cycle $ negedge sclk output to be used as IRQ source
reg [2:0] is_compressing_s;
reg is_finishing=0; /// no gap with is_compressing_s[2]
reg was_finishing;
// together they provide number of frames currently being processed (0/1/2)
reg wait_frame_sync;
reg wait_fifo;
reg compressor_fifo_done; // single cycle - compressor and and fifo done (next after done if !wait_fifo)
reg done_request = 0;
reg irq;
reg rst;
wire will_postpone_fs;
wire end_postpone_fs;
wire finished;
reg fs_postponed;
wire will_delay_done_irq;
reg delaying_done_irq;
assign will_postpone_fs=wait_frame_sync && (is_compressing_s[2] || is_finishing) ;
assign finished=was_finishing && ! is_finishing;
assign end_postpone_fs=finished || frame_sync;
assign will_delay_done_irq=wait_frame_sync && (finished && !fs_postponed);
always @ (negedge sclk) begin
//control interface
if (wen & di[1]) wait_frame_sync <= di[0];
if (wen & di[3]) wait_fifo <= di[2];
rst <=wen & di[15];
// process frame sync postponed - wait for the compression to finish if it was started during previous frame
fs_postponed <= !rst && ((will_postpone_fs && frame_sync) || (fs_postponed && !end_postpone_fs));
delaying_done_irq <= !rst && (will_delay_done_irq || (delaying_done_irq && !frame_sync));
is_compressing_s[2:0]<={is_compressing_s[1:0],is_compressing} ; // re-sync from posedge xclk to negedge clk
done_request <= !rst && (compressor_done || (done_request && !compressor_fifo_done));
compressor_fifo_done <= done_request && (!wait_fifo || fifo_empty) && !compressor_fifo_done;
is_finishing <= !rst && ((is_compressing_s[2] && !is_compressing_s[1]) ||
(is_finishing && !compressor_fifo_done));
was_finishing <= is_finishing;
irq <= !rst && ((frame_sync && (!will_postpone_fs || delaying_done_irq)) ||
(fs_postponed && end_postpone_fs) || // will include frame_sync if compression did not finish
(!will_delay_done_irq && finished));
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XNOR3_TB_V
`define SKY130_FD_SC_LP__XNOR3_TB_V
/**
* xnor3: 3-input exclusive NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xnor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__xnor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__XNOR3_TB_V
|
`timescale 1ns/1ps
module pipelineCPU(clk,button,din,switch,led,digi,dout);
input clk;
input button;
input din;
input [7:0] switch;
output [7:0] led;
output [11:0] digi;
output dout;
wire reset = ~button;
wire slow_clk;
watchmaker #(4) slow_watch(slow_clk,clk);
//assign slow_clk = clk;
wire datahazard;
wire [2:0] PCSrc;
wire ALUOut;
wire [31:0] ConBA;
wire [25:0] JT;
wire [31:0] DatabusA;
wire [31:0] DatabusB;
wire [31:0] daout;
wire [31:0] dbout;
wire [31:0] PC;
wire [31:0] PCplusin;
wire [31:0] PCplusout;
wire [31:0] PCplusout1;
wire [31:0] instructionin;
wire [31:0] instructionout;
wire IRQ;
wire IRQout;
wire [1:0] RegDst;
wire RegWr;
wire ALUSrc1;
wire ALUSrc2;
wire [5:0] ALUFun;
wire Sign;
wire MemWr;
wire MemRd;
wire [1:0] MemtoReg;
wire EXTOp;
wire LUOp;
wire [5:0] OpCode;
wire [4:0] WriteReg;
wire [31:0] WriteData;
wire [31:0] immout;
wire IDEXMemRd;
wire flushIDEX;
wire [1:0] RegDstn;
wire RegWrn;
wire ALUSrc1n;
wire ALUSrc2n;
wire [5:0] ALUFunn;
wire Signn;
wire MemWrn;
wire MemRdn;
wire [1:0] MemtoRegn;
wire [1:0] IDEXRegDst;
wire [1:0] EXMEMRegDst;
wire [1:0] MEMWBRegDst;
wire IDEXRegWr;
wire IDEXALUSrc1;
wire IDEXALUSrc2;
wire [5:0] IDEXALUFun;
wire IDEXSign;
wire IDEXMemWr;
wire EXMEMMemWr;
wire EXMEMMemRd;
wire [1:0] IDEXMemtoReg;
wire [1:0] EXMEMMemtoReg;
wire [1:0] MEMWBMemtoReg;
wire [4:0] IDEXshamt;
wire [4:0] IDEXRs;
wire [4:0] IDEXRt;
wire [4:0] IDEXRd;
wire [31:0] DatabusAout;
wire [31:0] DatabusBout;
wire [31:0] imm;
wire [31:0] IDEXPCplus;
wire [31:0] EXMEMPCplus;
wire [31:0] MEMWBPCplus;
wire [4:0] EXMEMRt;
wire [4:0] EXMEMRd;
wire [4:0] MEMWBRt;
wire [4:0] MEMWBRd;
wire EXMEMRegWr;
wire MEMWBRegWr;
wire [1:0] forwardA;
wire [1:0] forwardB;
wire [1:0] forward1;
wire [1:0] forward2;
wire [31:0] EXMEMALUresult;
wire [31:0] MEMWBALUresult;
wire [31:0] DataA;
wire [31:0] DataB;
wire [31:0] DataAin;
wire [31:0] DataBin;
wire [31:0] ALUresult;
wire [31:0] EXMEMDatawrite;
wire [31:0] RAMrdata;
wire [31:0] RAMrdata1;
wire [31:0] RAMrdata2;
wire [31:0] RAMrdataout;
programcounter PC1(slow_clk,reset,datahazard,PCSrc,ALUOut,ConBA,JT,daout,PC,PCplusin);
ROM rom1(PC,instructionin);
IFIDreg IFIDreg1(slow_clk,ALUOut,PCSrc,IRQ,datahazard,instructionin,PCplusin,instructionout,PCplusout,IRQout);
controlunit ctrl1(instructionout,IRQout,PC[31],PCplusout,PCplusout1,PCSrc,RegDst,RegWr,ALUSrc1,ALUSrc2,ALUFun,Sign,MemWr,MemRd,MemtoReg,EXTOp,LUOp,JT,OpCode);
RegFile regfile1(reset,slow_clk,instructionout[25:21],DatabusA,instructionout[20:16],DatabusB,MEMWBRegWr,WriteReg,WriteData);
branchcheck bc1(OpCode,daout,dbout,ALUOut);
signextend signextend1(instructionout[15:0],PCplusout,EXTOp,LUOp,ConBA,immout);
hazardcheck hc1(instructionout[25:21],instructionout[20:16],IDEXRt,EXMEMRt,IDEXMemRd,EXMEMMemRd,datahazard,flushIDEX);
flushMUX fMUX1(flushIDEX,RegDst,RegWr,ALUSrc1,ALUSrc2,ALUFun,Sign,MemWr,MemRd,MemtoReg,RegDstn,RegWrn,ALUSrc1n,ALUSrc2n,ALUFunn,Signn,MemWrn,MemRdn,MemtoRegn);
IDEXreg IDEXreg1(slow_clk,instructionout,datahazard,daout,dbout,immout,PCplusout1,RegDstn,RegWrn,ALUSrc1n,ALUSrc2n,ALUFunn,Signn,MemWrn,MemRdn,MemtoRegn,
IDEXRegDst,IDEXRegWr,IDEXALUSrc1,IDEXALUSrc2,IDEXALUFun,IDEXSign,IDEXMemWr,IDEXMemRd,IDEXMemtoReg,IDEXshamt,IDEXRs,IDEXRt,IDEXRd,DatabusAout,DatabusBout,imm,IDEXPCplus);
forwardunit fu1(instructionout[25:21],instructionout[20:16],IDEXRs,IDEXRt,IDEXRd,EXMEMRd,MEMWBRd,
IDEXRegWr,EXMEMRegWr,MEMWBRegWr,forwardA,forwardB,forward1,forward2);
databusMUX DA(forward1,DatabusA,ALUresult,EXMEMALUresult,WriteData,daout);
databusMUX DB(forward2,DatabusB,ALUresult,EXMEMALUresult,WriteData,dbout);
forwardMUX FA(forwardA,DatabusAout,WriteData,EXMEMALUresult,DataA);
forwardMUX FB(forwardB,DatabusBout,WriteData,EXMEMALUresult,DataB);
ALUSrcMUX ALA(IDEXALUSrc1,DataA,{27'h0,IDEXshamt},DataAin);
ALUSrcMUX ALB(IDEXALUSrc2,DataB,imm,DataBin);
ALU ALU1(DataAin,DataBin,IDEXALUFun,IDEXSign,ALUresult);//refer to the book
EXMEMreg EXMEMreg1(slow_clk,IDEXRt,IDEXRd,IDEXPCplus,ALUresult,DataB,IDEXRegDst,IDEXRegWr,IDEXMemWr,IDEXMemRd,IDEXMemtoReg,
EXMEMRt,EXMEMRd,EXMEMPCplus,EXMEMALUresult,EXMEMDatawrite,EXMEMRegDst,EXMEMRegWr,EXMEMMemWr,EXMEMMemRd,EXMEMMemtoReg);
DataMem RAM1(reset,slow_clk,EXMEMMemRd,EXMEMMemWr,EXMEMALUresult,EXMEMDatawrite,RAMrdata1);
Peripheral peripheral(reset,clk,slow_clk,EXMEMMemRd,EXMEMMemWr,EXMEMALUresult,EXMEMDatawrite,RAMrdata2,led,switch,digi,IRQ,din,dout);
assign RAMrdata = (EXMEMALUresult[31:28] == 4'b0100) ? RAMrdata2 : RAMrdata1;
MEMWBreg MEMWBreg1(slow_clk,EXMEMRt,EXMEMRd,EXMEMPCplus,RAMrdata,EXMEMALUresult,EXMEMRegDst,EXMEMRegWr,EXMEMMemtoReg,
MEMWBRt,MEMWBRd,MEMWBPCplus,RAMrdataout,MEMWBALUresult,MEMWBRegDst,MEMWBRegWr,MEMWBMemtoReg);
MemtoRegMUX MtR(MEMWBMemtoReg,MEMWBALUresult,RAMrdataout,MEMWBPCplus,WriteData);
RegDstMUX RD(MEMWBRegDst,MEMWBRd,MEMWBRt,WriteReg);
endmodule
|
`define SMV
`include "routingBlock.v"
/*
* File: routingBlock_tb.v
* Test bench for routingblock.v
* Includes assertions for verification
*/
module main();
// Inputs to DUT
reg [8*32:0] inputState;
reg [2:0] inputSelect;
// Outputs of DUT
wire [31:0] result;
wire configInvalid;
routingBlock routingBlock_t(.inputState(inputState),
.inputSelect(inputSelect),
.out(result),
.configInvalid(configInvalid),
.NUM_INPUTS(8),
.NUM_INPUTS_LOG_2(3));
endmodule // main
/* ********* SMV Assertions *********
//SMV-Assertions
# Properties select_0, select_1, .., select_7, select_def:
# Assert when inputSelect = X, the Xth 32-bit block of inputState is returned.
# Note that this assumes INPUT_WIDTH = 32 in routingBlock.
# Note this only checks for 0 <= X < 8. If NUM_INPUTS is set to something higher than 8, more checks would need to be added.
\select_0 : assert G((\inputSelect = 0) -> (\result = \inputState [((32*1)-1)..(32*0)]));
\select_1 : assert G((\inputSelect = 1) -> (\result = \inputState [((32*2)-1)..(32*1)]));
\select_2 : assert G((\inputSelect = 2) -> (\result = \inputState [((32*3)-1)..(32*2)]));
\select_3 : assert G((\inputSelect = 3) -> (\result = \inputState [((32*4)-1)..(32*3)]));
\select_4 : assert G((\inputSelect = 4) -> (\result = \inputState [((32*5)-1)..(32*4)]));
\select_5 : assert G((\inputSelect = 5) -> (\result = \inputState [((32*6)-1)..(32*5)]));
\select_6 : assert G((\inputSelect = 6) -> (\result = \inputState [((32*7)-1)..(32*6)]));
\select_7 : assert G((\inputSelect = 7) -> (\result = \inputState [((32*8)-1)..(32*7)]));
\select_def : assert G((\inputSelect > 7) -> (\result = 0));
# Properties select_inv, select_val:
# Assert configInvalid is set iff inputSelect is outside the range [0,7]
# Note if NUM_INPUTS is changed, the checked range would need to be adjusted.
\select_inv : assert G(((\inputSelect < 0) || (\inputSelect > 7)) -> \configInvalid );
\select_val : assert G((\inputSelect < 8) -> ~\configInvalid );
//SMV-Assertions
*/ |
/*
* Copyright (c) 2011-2014 Travis Geiselbrecht
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files
* (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
`timescale 1ns/1ns
module testbench(
input clk
);
parameter AWIDTH = 16;
reg [31:0] count;
initial
count = 0;
always @(posedge clk)
count <= count + 1;
always @(count)
begin
if (count == 100)
$finish;
end
reg rst;
wire [29:0] memaddr;
wire [31:0] rmemdata;
wire [31:0] wmemdata;
wire mem_oe;
wire mem_we;
cpu cpu0(
.clk(clk),
.rst(rst),
.mem_re(mem_oe),
.mem_we(mem_we),
.memaddr(memaddr),
.rmemdata(rmemdata),
.wmemdata(wmemdata)
);
rom rom0(
.clk(clk),
.re(mem_oe),
.we(mem_we),
.addr(memaddr),
.rdata(rmemdata),
.wdata(wmemdata)
);
/* hold the cpu in reset for a few clocks */
always @(count)
if (count < 10)
rst = 1;
else
rst = 0;
endmodule
module rom(
input clk,
input re,
input we,
input [29:0] addr,
output reg [31:0] rdata,
input [31:0] wdata
);
reg [31:0] rom [0:255];
initial begin
$readmemh("../test2.asm.hex", rom);
end
always @(posedge clk) begin
rdata <= rom[addr];
if (we)
rom[addr] <= wdata;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_BLACKBOX_V
`define SKY130_FD_SC_LS__EDFXTP_BLACKBOX_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK,
D ,
DE
);
output Q ;
input CLK;
input D ;
input DE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__BUFLP_PP_BLACKBOX_V
/**
* buflp: Buffer, Low Power.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__buflp (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_PP_BLACKBOX_V
|
module controlTransmitter (Complete, NullString, NullDataChar, Generated, LoadString, CompareString, LoadNextChar, GenerateData, SendData, Reset, clk);
input Complete, NullString, NullDataChar, clk, Reset, Generated;
output reg LoadString, CompareString, LoadNextChar, GenerateData, SendData;
reg [2:0] current_state;
reg [2:0] next_state;
parameter Standby=3'b000, LoadingString=3'b001, ComparingString=3'b010, LoadingChar=3'b011;
parameter GeneratingData=3'b100, SendingData=3'b101;
always @(Complete, NullString, NullDataChar, current_state, Reset, Generated)begin
if (Reset)begin
next_state <= Standby;
LoadString<=0;
CompareString<=0;
LoadNextChar<=0;
GenerateData<=0;
SendData<=0;
end
else begin
case (current_state)
Standby: begin
if (Complete==1'b0) begin
LoadString<=0;
CompareString<=0;
LoadNextChar<=0;
GenerateData<=0;
SendData<=0;
next_state <= Standby;
end
else begin
next_state <= LoadingString;
LoadString<=0;
CompareString<=0;
LoadNextChar<=0;
GenerateData<=0;
SendData<=0;
end
end
LoadingString: begin
LoadString<=1;
CompareString<=0;
LoadNextChar<=0;
GenerateData<=0;
SendData<=0;
next_state<=ComparingString;
end
ComparingString: begin
LoadString<=0;
CompareString<=1;
LoadNextChar<=0;
GenerateData<=0;
SendData<=0;
if (NullString==1'b1)next_state<=Standby;
else next_state<=LoadingChar;
end
LoadingChar: begin
LoadString<=0;
CompareString<=0;
LoadNextChar<=1;
GenerateData<=0;
SendData<=0;
next_state<=GeneratingData;
end
GeneratingData: begin
LoadString<=0;
CompareString<=0;
LoadNextChar<=0;
GenerateData<=1;
SendData<=0;
if (Generated)next_state <= SendingData;
else next_state <= GeneratingData;
end
SendingData: begin
LoadString<=0;
CompareString<=0;
LoadNextChar<=0;
GenerateData<=0;
SendData<=1;
if (NullDataChar == 1)next_state <= ComparingString;
else next_state <= SendingData;
end
default: begin
LoadString<=0;
CompareString<=0;
LoadNextChar<=0;
GenerateData<=0;
SendData<=0;
next_state <= Standby;
end
endcase
end
end
always @(negedge clk) begin
current_state <= next_state;
end
endmodule
|
/*
Copyright (C) {2014} {Ganesh Ajjanagadde} <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
///////////////////////////////////////////////////////////////////////////////////////////////////
// pixels_kept: Calculates the percentage of pixels lost, given the
// coordinates of the four points of the quadrilateral.
// The module is a pure combinational logic module
// The area formula is given by a standard determinant expansion, and may be
// derived easily.
// Alternatively, it is easily available on the web
///////////////////////////////////////////////////////////////////////////////////////////////////
module pixels_kept(input[9:0] x1,
input[8:0] y1,
input[9:0] x2,
input[8:0] y2,
input[9:0] x3,
input[8:0] y3,
input[9:0] x4,
input[8:0] y4,
output wire[6:0] percent_kept); // percent_kept ranges from 0 to 100, a 7 bit number
wire signed[10:0] sx1, sx2, sx3, sx4;
wire signed[9:0] sy1, sy2, sy3, sy4;
wire signed[10:0] d_x1_x3, d_x2_x4;
wire signed[9:0] d_y1_y3, d_y2_y4;
wire signed[20:0] prod0, prod1;
wire signed[20:0] prod;
wire signed[20:0] abs_prod;
wire[20:0] unsigned_prod;
wire[13:0] shift_prod_7;
wire[11:0] shift_prod_9;
wire[9:0] shift_prod_11;
wire[14:0] sum_shift_prod;
// sign extensions
assign sx1 = {1'b0, x1};
assign sx2 = {1'b0, x2};
assign sx3 = {1'b0, x3};
assign sx4 = {1'b0, x4};
assign sy1 = {1'b0, y1};
assign sy2 = {1'b0, y2};
assign sy3 = {1'b0, y3};
assign sy4 = {1'b0, y4};
// difference terms
assign d_x1_x3 = sx1 - sx3;
assign d_x2_x4 = sx2 - sx4;
assign d_y1_y3 = sy1 - sy3;
assign d_y2_y4 = sy2 - sy4;
// multipliers
assign prod0 = d_x1_x3 * d_y2_y4;
assign prod1 = d_y1_y3 * d_x2_x4;
// final area calculation
assign prod = prod0 - prod1; // this is twice the area
// but first, we need to take its absolute value
assign abs_prod = (prod < 0) ? -prod : prod;
assign unsigned_prod = abs_prod;
// to compute the percentage of pixels covered, here is the calculation
// we want (100*A)/(640*480), or A/(64*48)
// what we have is temp=2*A
// thus, we need temp/(128*48) = temp/(6144) = temp/(2^11 * 3) = (temp >> 11) / 3
// to avoid the division by 3, we approximate 3 ~= 21/64 (accurate to
// within 1%)
// thus, we want ((temp >> 11)*21) >> 6
// but mult by 21 is same as mult by (16 + 4 + 1)
// thus, our final calculation is ((temp >> 7) + (temp >> 9) + (temp >> 11))>>6
assign shift_prod_7 = unsigned_prod >> 7;
assign shift_prod_9 = unsigned_prod >> 9;
assign shift_prod_11 = unsigned_prod >> 11;
assign sum_shift_prod = shift_prod_7 + shift_prod_9 + shift_prod_11;
assign percent_kept = sum_shift_prod >> 6;
endmodule
|
module note_mono_harray(clk, rst, note_on, note_off, note, out_note, out_gate);
//inputs outputs
input wire clk, rst, note_on, note_off;
input wire [6:0] note;
output wire [6:0] out_note;
output reg out_gate;
initial out_gate <= 0;
reg [6:0] t_out_note;
initial t_out_note <= 7'd0;
assign out_note = t_out_note;//(out_gate) ? t_out_note : 7'd0;
reg [127:0] keys;
initial keys <= 128'd0;
reg [6:0] bit_ptr;
//state list
parameter READY = 1'd0;
parameter BUSY = 1'd1;
reg state;
initial state <= READY;
always @(posedge clk) begin
if (rst) begin
out_gate <= 0;
t_out_note <= 7'd0;
keys <= 128'd0;
state <= READY;
end else if (state==READY) begin
if (note_on) begin
keys[note] <= 1;
bit_ptr <= 7'd127;
state <= BUSY;
end else if (note_off) begin
keys[note] <= 0;
bit_ptr <= 7'd127;
state <= BUSY;
end
end else if (state==BUSY) begin
if (note_on||note_off) begin //если в процессе работы еще что-то пришло
if (note_on) begin
keys[note] <= 1;
end else if (note_off) begin
keys[note] <= 0;
end
bit_ptr <= 7'd127;
end else if (bit_ptr==7'd0) begin //не нашли ни одной установленной ноты
out_gate <= 0;
state <= READY;
end else if (keys[bit_ptr]== 1'b1) begin //нашли установленый бит - заканчиваем поиск
out_gate <= 1;
t_out_note <= bit_ptr;
state <= READY;
end else begin
bit_ptr <= bit_ptr - 1'b1;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR2B_1_V
`define SKY130_FD_SC_MS__OR2B_1_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or2b_1 (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__or2b_1 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR2B_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
`define SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V
/**
* probec_p: Virtual current probe point.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__probec_p (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBEC_P_FUNCTIONAL_V |
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone master mem bus
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//wishbone slave 0 signals
wire mem0_we_o;
wire mem0_cyc_o;
wire [31:0] mem0_dat_o;
wire mem0_stb_o;
wire [3:0] mem0_sel_o;
wire mem0_ack_i;
wire [31:0] mem0_dat_i;
wire [31:0] mem0_adr_o;
wire mem0_int_i;
wire sdram_clk;
wire sdram_cke;
wire sdram_cs_n;
wire sdram_ras;
wire sdram_cas;
wire sdram_we;
wire [11:0] sdram_addr;
wire [1:0] sdram_bank;
wire [15:0] sdram_data;
wire [1:0] sdram_data_mask;
wire sdram_ready;
reg [15:0] sdram_in_data;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire camera_mem_o_stb;
wire camera_mem_o_cyc;
wire camera_mem_o_we;
wire [3:0] camera_mem_o_sel;
wire [31:0] camera_mem_o_dat;
wire [31:0] camera_mem_o_adr;
wire [31:0] camera_mem_i_dat;
wire camera_mem_i_ack;
wire camera_mem_i_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_cam_rst;
wire w_flash;
wire w_cam_in_clk;
wire w_pix_clk;
wire w_flash_strobe;
wire w_vsync;
wire w_hsync;
wire [7:0] w_pix_data;
wire start;
assign w_wbs0_int = 0;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
wb_sf_camera s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.mem_o_cyc (camera_mem_o_cyc ),
.mem_o_stb (camera_mem_o_stb ),
.mem_o_we (camera_mem_o_we ),
.mem_i_ack (camera_mem_i_ack ),
.mem_o_sel (camera_mem_o_sel ),
.mem_o_adr (camera_mem_o_adr ),
.mem_o_dat (camera_mem_o_dat ),
.mem_i_dat (camera_mem_i_dat ),
.mem_i_int (camera_mem_i_int ),
.o_cam_rst (w_cam_rst ),
.o_flash (w_flash ),
.o_cam_in_clk (w_cam_in_clk ),
.i_pix_clk (w_pix_clk ),
.i_flash_strobe (w_flash_strobe ),
.i_vsync (w_vsync ),
.i_hsync (w_hsync ),
.i_pix_data (w_pix_data )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
mt48lc4m16
//#(
// tdevice_TRCD = 10
//)
ram (
.A11 (sdram_addr[11]),
.A10 (sdram_addr[10]),
.A9 (sdram_addr[9]),
.A8 (sdram_addr[8]),
.A7 (sdram_addr[7]),
.A6 (sdram_addr[6]),
.A5 (sdram_addr[5]),
.A4 (sdram_addr[4]),
.A3 (sdram_addr[3]),
.A2 (sdram_addr[2]),
.A1 (sdram_addr[1]),
.A0 (sdram_addr[0]),
.DQ15 (sdram_data[15]),
.DQ14 (sdram_data[14]),
.DQ13 (sdram_data[13]),
.DQ12 (sdram_data[12]),
.DQ11 (sdram_data[11]),
.DQ10 (sdram_data[10]),
.DQ9 (sdram_data[9]),
.DQ8 (sdram_data[8]),
.DQ7 (sdram_data[7]),
.DQ6 (sdram_data[6]),
.DQ5 (sdram_data[5]),
.DQ4 (sdram_data[4]),
.DQ3 (sdram_data[3]),
.DQ2 (sdram_data[2]),
.DQ1 (sdram_data[1]),
.DQ0 (sdram_data[0]),
.BA0 (sdram_bank[0]),
.BA1 (sdram_bank[1]),
.DQMH (sdram_data_mask[1]),
.DQML (sdram_data_mask[0]),
.CLK (sdram_clk),
.CKE (sdram_cke),
.WENeg (sdram_we),
.RASNeg (sdram_ras),
.CSNeg (sdram_cs_n),
.CASNeg (sdram_cas)
);
//mem 0
wb_sdram m0 (
.clk(clk),
.rst(rst),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int ),
.o_sdram_clk (sdram_clk ),
.o_sdram_cke (sdram_cke ),
.o_sdram_cs_n (sdram_cs_n ),
.o_sdram_ras (sdram_ras ),
.o_sdram_cas (sdram_cas ),
.o_sdram_we (sdram_we ),
.o_sdram_addr (sdram_addr ),
.o_sdram_bank (sdram_bank ),
.io_sdram_data (sdram_data ),
.o_sdram_data_mask (sdram_data_mask ),
.o_sdram_ready (sdram_ready )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (rst ),
//masters
.i_m0_we (camera_mem_o_we ),
.i_m0_stb (camera_mem_o_stb ),
.i_m0_cyc (camera_mem_o_cyc ),
.i_m0_sel (camera_mem_o_sel ),
.i_m0_dat (camera_mem_o_dat ),
.i_m0_adr (camera_mem_o_adr ),
.o_m0_dat (camera_mem_i_dat ),
.o_m0_ack (camera_mem_i_ack ),
.o_m0_int (camera_mem_i_int ),
.i_m1_we (w_sm0_i_wbs_we ),
.i_m1_stb (w_sm0_i_wbs_stb ),
.i_m1_cyc (w_sm0_i_wbs_cyc ),
.i_m1_sel (w_sm0_i_wbs_sel ),
.i_m1_dat (w_sm0_i_wbs_dat ),
.i_m1_adr (w_sm0_i_wbs_adr ),
.o_m1_dat (w_sm0_o_wbs_dat ),
.o_m1_ack (w_sm0_o_wbs_ack ),
.o_m1_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
sim_camera cam (
.i_cam_in_clk (w_cam_in_clk ),
.i_cam_rst (w_cam_rst ),
.i_flash (w_flash ),
.o_pix_clk (w_pix_clk ),
.o_flash_strobe (w_flash_strobe ),
.o_vsync (w_vsync ),
.o_hsync (w_hsync ),
.o_pix_data (w_pix_data )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = sdram_ready;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
$display ("");
end
else begin
$display ("Error unrecognized line: %h" % ch);
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
$display ("Sleep for %h Clock cycles", r_in_data_count);
`SLEEP_CLK(r_in_data_count);
$display ("Sleep Finished");
end
else begin
$display ("Error: read_count = %h != 4", read_count);
$display ("Character: %h", ch);
end
end
else begin
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
$display ("Execute Command");
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
$display ("TB: reading a new double word: %h", r_in_data);
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
$display ("Command Finished");
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
$display ("TB: finished command");
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
else begin
$display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data);
$display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count);
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
$display ("TB: Ping Response Good");
end
else begin
$display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
$display ("In Write Response");
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
$display ("TB: Write Response Good");
end
else begin
$display ("TB: Write Response Bad (Malformed response: %h)", w_out_status);
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
$display ("TB: Read Response Good");
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
$display ("TB: Read Response Bad (Malformed response: %h)", w_out_status);
state <= FINISHED;
end
$display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data);
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
$display ("TB: Read a 32bit data packet");
$display ("TB: \tRead Data: %h", w_out_data);
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
$display ("Execute Command is low");
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
$display("TB: Output Handler Recieved interrupt");
$display("TB:\tcommand: %h", w_out_status);
$display("TB:\taddress: %h", w_out_address);
$display("TB:\tdata: %h", w_out_data);
end
end//not reset
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue Jun 06 02:48:32 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.v
// Design : system_ov7670_controller_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_ov7670_controller_0_0,ov7670_controller,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "ov7670_controller,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_ov7670_controller_0_0
(clk,
resend,
config_finished,
sioc,
siod,
reset,
pwdn,
xclk);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input resend;
output config_finished;
output sioc;
inout siod;
(* x_interface_info = "xilinx.com:signal:reset:1.0 reset RST" *) output reset;
output pwdn;
output xclk;
wire \<const0> ;
wire \<const1> ;
wire clk;
wire config_finished;
wire resend;
wire sioc;
wire siod;
assign pwdn = \<const0> ;
assign reset = \<const1> ;
GND GND
(.G(\<const0> ));
system_ov7670_controller_0_0_ov7670_controller U0
(.clk(clk),
.config_finished(config_finished),
.resend(resend),
.sioc(sioc),
.siod(siod));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "i2c_sender" *)
module system_ov7670_controller_0_0_i2c_sender
(E,
sioc,
p_0_in,
\busy_sr_reg[1]_0 ,
siod,
\busy_sr_reg[31]_0 ,
clk,
p_1_in,
DOADO,
\busy_sr_reg[31]_1 );
output [0:0]E;
output sioc;
output p_0_in;
output \busy_sr_reg[1]_0 ;
output siod;
input \busy_sr_reg[31]_0 ;
input clk;
input [0:0]p_1_in;
input [15:0]DOADO;
input [0:0]\busy_sr_reg[31]_1 ;
wire [15:0]DOADO;
wire [0:0]E;
wire busy_sr0;
wire \busy_sr[0]_i_3_n_0 ;
wire \busy_sr[0]_i_5_n_0 ;
wire \busy_sr[10]_i_1_n_0 ;
wire \busy_sr[11]_i_1_n_0 ;
wire \busy_sr[12]_i_1_n_0 ;
wire \busy_sr[13]_i_1_n_0 ;
wire \busy_sr[14]_i_1_n_0 ;
wire \busy_sr[15]_i_1_n_0 ;
wire \busy_sr[16]_i_1_n_0 ;
wire \busy_sr[17]_i_1_n_0 ;
wire \busy_sr[18]_i_1_n_0 ;
wire \busy_sr[19]_i_1_n_0 ;
wire \busy_sr[1]_i_1_n_0 ;
wire \busy_sr[20]_i_1_n_0 ;
wire \busy_sr[21]_i_1_n_0 ;
wire \busy_sr[22]_i_1_n_0 ;
wire \busy_sr[23]_i_1_n_0 ;
wire \busy_sr[24]_i_1_n_0 ;
wire \busy_sr[25]_i_1_n_0 ;
wire \busy_sr[26]_i_1_n_0 ;
wire \busy_sr[27]_i_1_n_0 ;
wire \busy_sr[28]_i_1_n_0 ;
wire \busy_sr[29]_i_1_n_0 ;
wire \busy_sr[2]_i_1_n_0 ;
wire \busy_sr[30]_i_1_n_0 ;
wire \busy_sr[31]_i_1_n_0 ;
wire \busy_sr[31]_i_2_n_0 ;
wire \busy_sr[3]_i_1_n_0 ;
wire \busy_sr[4]_i_1_n_0 ;
wire \busy_sr[5]_i_1_n_0 ;
wire \busy_sr[6]_i_1_n_0 ;
wire \busy_sr[7]_i_1_n_0 ;
wire \busy_sr[8]_i_1_n_0 ;
wire \busy_sr[9]_i_1_n_0 ;
wire \busy_sr_reg[1]_0 ;
wire \busy_sr_reg[31]_0 ;
wire [0:0]\busy_sr_reg[31]_1 ;
wire \busy_sr_reg_n_0_[0] ;
wire \busy_sr_reg_n_0_[10] ;
wire \busy_sr_reg_n_0_[11] ;
wire \busy_sr_reg_n_0_[12] ;
wire \busy_sr_reg_n_0_[13] ;
wire \busy_sr_reg_n_0_[14] ;
wire \busy_sr_reg_n_0_[15] ;
wire \busy_sr_reg_n_0_[16] ;
wire \busy_sr_reg_n_0_[17] ;
wire \busy_sr_reg_n_0_[18] ;
wire \busy_sr_reg_n_0_[1] ;
wire \busy_sr_reg_n_0_[21] ;
wire \busy_sr_reg_n_0_[22] ;
wire \busy_sr_reg_n_0_[23] ;
wire \busy_sr_reg_n_0_[24] ;
wire \busy_sr_reg_n_0_[25] ;
wire \busy_sr_reg_n_0_[26] ;
wire \busy_sr_reg_n_0_[27] ;
wire \busy_sr_reg_n_0_[28] ;
wire \busy_sr_reg_n_0_[29] ;
wire \busy_sr_reg_n_0_[2] ;
wire \busy_sr_reg_n_0_[30] ;
wire \busy_sr_reg_n_0_[3] ;
wire \busy_sr_reg_n_0_[4] ;
wire \busy_sr_reg_n_0_[5] ;
wire \busy_sr_reg_n_0_[6] ;
wire \busy_sr_reg_n_0_[7] ;
wire \busy_sr_reg_n_0_[8] ;
wire \busy_sr_reg_n_0_[9] ;
wire clk;
wire \data_sr[10]_i_1_n_0 ;
wire \data_sr[12]_i_1_n_0 ;
wire \data_sr[13]_i_1_n_0 ;
wire \data_sr[14]_i_1_n_0 ;
wire \data_sr[15]_i_1_n_0 ;
wire \data_sr[16]_i_1_n_0 ;
wire \data_sr[17]_i_1_n_0 ;
wire \data_sr[18]_i_1_n_0 ;
wire \data_sr[19]_i_1_n_0 ;
wire \data_sr[22]_i_1_n_0 ;
wire \data_sr[27]_i_1_n_0 ;
wire \data_sr[30]_i_1_n_0 ;
wire \data_sr[31]_i_1_n_0 ;
wire \data_sr[31]_i_2_n_0 ;
wire \data_sr[3]_i_1_n_0 ;
wire \data_sr[4]_i_1_n_0 ;
wire \data_sr[5]_i_1_n_0 ;
wire \data_sr[6]_i_1_n_0 ;
wire \data_sr[7]_i_1_n_0 ;
wire \data_sr[8]_i_1_n_0 ;
wire \data_sr[9]_i_1_n_0 ;
wire \data_sr_reg_n_0_[10] ;
wire \data_sr_reg_n_0_[11] ;
wire \data_sr_reg_n_0_[12] ;
wire \data_sr_reg_n_0_[13] ;
wire \data_sr_reg_n_0_[14] ;
wire \data_sr_reg_n_0_[15] ;
wire \data_sr_reg_n_0_[16] ;
wire \data_sr_reg_n_0_[17] ;
wire \data_sr_reg_n_0_[18] ;
wire \data_sr_reg_n_0_[19] ;
wire \data_sr_reg_n_0_[1] ;
wire \data_sr_reg_n_0_[20] ;
wire \data_sr_reg_n_0_[21] ;
wire \data_sr_reg_n_0_[22] ;
wire \data_sr_reg_n_0_[23] ;
wire \data_sr_reg_n_0_[24] ;
wire \data_sr_reg_n_0_[25] ;
wire \data_sr_reg_n_0_[26] ;
wire \data_sr_reg_n_0_[27] ;
wire \data_sr_reg_n_0_[28] ;
wire \data_sr_reg_n_0_[29] ;
wire \data_sr_reg_n_0_[2] ;
wire \data_sr_reg_n_0_[30] ;
wire \data_sr_reg_n_0_[31] ;
wire \data_sr_reg_n_0_[3] ;
wire \data_sr_reg_n_0_[4] ;
wire \data_sr_reg_n_0_[5] ;
wire \data_sr_reg_n_0_[6] ;
wire \data_sr_reg_n_0_[7] ;
wire \data_sr_reg_n_0_[8] ;
wire \data_sr_reg_n_0_[9] ;
wire [7:6]divider_reg__0;
wire [5:0]divider_reg__1;
wire p_0_in;
wire [7:0]p_0_in__0;
wire [0:0]p_1_in;
wire [1:0]p_1_in_0;
wire sioc;
wire sioc_i_1_n_0;
wire sioc_i_2_n_0;
wire sioc_i_3_n_0;
wire sioc_i_4_n_0;
wire sioc_i_5_n_0;
wire siod;
wire siod_INST_0_i_1_n_0;
LUT6 #(
.INIT(64'h4000FFFF40004000))
\busy_sr[0]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.I2(divider_reg__0[7]),
.I3(p_0_in),
.I4(\busy_sr_reg[1]_0 ),
.I5(p_1_in),
.O(busy_sr0));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\busy_sr[0]_i_3
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(\busy_sr[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\busy_sr[0]_i_4
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[3]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(\busy_sr[0]_i_5_n_0 ),
.O(\busy_sr_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hFFFE))
\busy_sr[0]_i_5
(.I0(divider_reg__1[5]),
.I1(divider_reg__1[4]),
.I2(divider_reg__0[7]),
.I3(divider_reg__0[6]),
.O(\busy_sr[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[10]_i_1
(.I0(\busy_sr_reg_n_0_[9] ),
.I1(p_0_in),
.O(\busy_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[11]_i_1
(.I0(\busy_sr_reg_n_0_[10] ),
.I1(p_0_in),
.O(\busy_sr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[12]_i_1
(.I0(\busy_sr_reg_n_0_[11] ),
.I1(p_0_in),
.O(\busy_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[13]_i_1
(.I0(\busy_sr_reg_n_0_[12] ),
.I1(p_0_in),
.O(\busy_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[14]_i_1
(.I0(\busy_sr_reg_n_0_[13] ),
.I1(p_0_in),
.O(\busy_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[15]_i_1
(.I0(\busy_sr_reg_n_0_[14] ),
.I1(p_0_in),
.O(\busy_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[16]_i_1
(.I0(\busy_sr_reg_n_0_[15] ),
.I1(p_0_in),
.O(\busy_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[17]_i_1
(.I0(\busy_sr_reg_n_0_[16] ),
.I1(p_0_in),
.O(\busy_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[18]_i_1
(.I0(\busy_sr_reg_n_0_[17] ),
.I1(p_0_in),
.O(\busy_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[19]_i_1
(.I0(\busy_sr_reg_n_0_[18] ),
.I1(p_0_in),
.O(\busy_sr[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[1]_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(p_0_in),
.O(\busy_sr[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[20]_i_1
(.I0(p_1_in_0[0]),
.I1(p_0_in),
.O(\busy_sr[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[21]_i_1
(.I0(p_1_in_0[1]),
.I1(p_0_in),
.O(\busy_sr[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[22]_i_1
(.I0(\busy_sr_reg_n_0_[21] ),
.I1(p_0_in),
.O(\busy_sr[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[23]_i_1
(.I0(\busy_sr_reg_n_0_[22] ),
.I1(p_0_in),
.O(\busy_sr[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[24]_i_1
(.I0(\busy_sr_reg_n_0_[23] ),
.I1(p_0_in),
.O(\busy_sr[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[25]_i_1
(.I0(\busy_sr_reg_n_0_[24] ),
.I1(p_0_in),
.O(\busy_sr[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[26]_i_1
(.I0(\busy_sr_reg_n_0_[25] ),
.I1(p_0_in),
.O(\busy_sr[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[27]_i_1
(.I0(\busy_sr_reg_n_0_[26] ),
.I1(p_0_in),
.O(\busy_sr[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[28]_i_1
(.I0(\busy_sr_reg_n_0_[27] ),
.I1(p_0_in),
.O(\busy_sr[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[29]_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(p_0_in),
.O(\busy_sr[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[2]_i_1
(.I0(\busy_sr_reg_n_0_[1] ),
.I1(p_0_in),
.O(\busy_sr[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[30]_i_1
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(p_0_in),
.O(\busy_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'h22222222A2222222))
\busy_sr[31]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.I3(divider_reg__0[7]),
.I4(divider_reg__0[6]),
.I5(\busy_sr[0]_i_3_n_0 ),
.O(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[31]_i_2
(.I0(p_0_in),
.I1(\busy_sr_reg_n_0_[30] ),
.O(\busy_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[3]_i_1
(.I0(\busy_sr_reg_n_0_[2] ),
.I1(p_0_in),
.O(\busy_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[4]_i_1
(.I0(\busy_sr_reg_n_0_[3] ),
.I1(p_0_in),
.O(\busy_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[5]_i_1
(.I0(\busy_sr_reg_n_0_[4] ),
.I1(p_0_in),
.O(\busy_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[6]_i_1
(.I0(\busy_sr_reg_n_0_[5] ),
.I1(p_0_in),
.O(\busy_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[7]_i_1
(.I0(\busy_sr_reg_n_0_[6] ),
.I1(p_0_in),
.O(\busy_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[8]_i_1
(.I0(\busy_sr_reg_n_0_[7] ),
.I1(p_0_in),
.O(\busy_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h8))
\busy_sr[9]_i_1
(.I0(\busy_sr_reg_n_0_[8] ),
.I1(p_0_in),
.O(\busy_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\busy_sr_reg[0]
(.C(clk),
.CE(busy_sr0),
.D(p_1_in),
.Q(\busy_sr_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[10]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[10] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[11]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[11] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[12]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[12] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[13]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[13] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[14]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[14] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[15]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[15] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[16]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[16] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[17]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[17] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[18]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[18] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[19]_i_1_n_0 ),
.Q(p_1_in_0[0]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[1]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[1] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[20]_i_1_n_0 ),
.Q(p_1_in_0[1]),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[21]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[21] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[22]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[22]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[22] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[23]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[23] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[24]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[24] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[25]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[25] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[26]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[26] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[27]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[27]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[27] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[28]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[28] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[29]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[29] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[2]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[2] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[30]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[30] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[31]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[31]_i_2_n_0 ),
.Q(p_0_in),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[3]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[3] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[4]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[4] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[5]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[5] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[6]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[6] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[7]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[7] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[8]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[8] ),
.S(\busy_sr[31]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\busy_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\busy_sr[9]_i_1_n_0 ),
.Q(\busy_sr_reg_n_0_[9] ),
.S(\busy_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[10]_i_1
(.I0(\data_sr_reg_n_0_[9] ),
.I1(p_0_in),
.I2(DOADO[7]),
.O(\data_sr[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[12]_i_1
(.I0(\data_sr_reg_n_0_[11] ),
.I1(p_0_in),
.I2(DOADO[8]),
.O(\data_sr[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[13]_i_1
(.I0(\data_sr_reg_n_0_[12] ),
.I1(p_0_in),
.I2(DOADO[9]),
.O(\data_sr[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[14]_i_1
(.I0(\data_sr_reg_n_0_[13] ),
.I1(p_0_in),
.I2(DOADO[10]),
.O(\data_sr[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[15]_i_1
(.I0(\data_sr_reg_n_0_[14] ),
.I1(p_0_in),
.I2(DOADO[11]),
.O(\data_sr[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[16]_i_1
(.I0(\data_sr_reg_n_0_[15] ),
.I1(p_0_in),
.I2(DOADO[12]),
.O(\data_sr[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[17]_i_1
(.I0(\data_sr_reg_n_0_[16] ),
.I1(p_0_in),
.I2(DOADO[13]),
.O(\data_sr[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[18]_i_1
(.I0(\data_sr_reg_n_0_[17] ),
.I1(p_0_in),
.I2(DOADO[14]),
.O(\data_sr[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[19]_i_1
(.I0(\data_sr_reg_n_0_[18] ),
.I1(p_0_in),
.I2(DOADO[15]),
.O(\data_sr[19]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[22]_i_1
(.I0(\data_sr_reg_n_0_[22] ),
.I1(\data_sr_reg_n_0_[21] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[22]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[27]_i_1
(.I0(\data_sr_reg_n_0_[27] ),
.I1(\data_sr_reg_n_0_[26] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[27]_i_1_n_0 ));
LUT3 #(
.INIT(8'h02))
\data_sr[30]_i_1
(.I0(p_1_in),
.I1(\busy_sr_reg[1]_0 ),
.I2(p_0_in),
.O(\data_sr[30]_i_1_n_0 ));
LUT6 #(
.INIT(64'hCFCFCFCFAACAAAAA))
\data_sr[31]_i_1
(.I0(\data_sr_reg_n_0_[31] ),
.I1(\data_sr_reg_n_0_[30] ),
.I2(p_0_in),
.I3(\data_sr[31]_i_2_n_0 ),
.I4(divider_reg__0[7]),
.I5(\busy_sr_reg[31]_0 ),
.O(\data_sr[31]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'hB))
\data_sr[31]_i_2
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(\data_sr[31]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[3]_i_1
(.I0(\data_sr_reg_n_0_[2] ),
.I1(p_0_in),
.I2(DOADO[0]),
.O(\data_sr[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[4]_i_1
(.I0(\data_sr_reg_n_0_[3] ),
.I1(p_0_in),
.I2(DOADO[1]),
.O(\data_sr[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[5]_i_1
(.I0(\data_sr_reg_n_0_[4] ),
.I1(p_0_in),
.I2(DOADO[2]),
.O(\data_sr[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[6]_i_1
(.I0(\data_sr_reg_n_0_[5] ),
.I1(p_0_in),
.I2(DOADO[3]),
.O(\data_sr[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[7]_i_1
(.I0(\data_sr_reg_n_0_[6] ),
.I1(p_0_in),
.I2(DOADO[4]),
.O(\data_sr[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[8]_i_1
(.I0(\data_sr_reg_n_0_[7] ),
.I1(p_0_in),
.I2(DOADO[5]),
.O(\data_sr[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\data_sr[9]_i_1
(.I0(\data_sr_reg_n_0_[8] ),
.I1(p_0_in),
.I2(DOADO[6]),
.O(\data_sr[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[10]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[10]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[10] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[11]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[10] ),
.Q(\data_sr_reg_n_0_[11] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[12]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[12]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[12] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[13]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[13]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[13] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[14]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[14]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[14] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[15]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[15]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[15] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[16]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[16]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[16] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[17]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[17]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[17] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[18]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[18]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[18] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[19]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[19]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[19] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[1]
(.C(clk),
.CE(busy_sr0),
.D(p_0_in),
.Q(\data_sr_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[20]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[19] ),
.Q(\data_sr_reg_n_0_[20] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[21]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[20] ),
.Q(\data_sr_reg_n_0_[21] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[22]
(.C(clk),
.CE(1'b1),
.D(\data_sr[22]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[22] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[23]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[22] ),
.Q(\data_sr_reg_n_0_[23] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[24]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[23] ),
.Q(\data_sr_reg_n_0_[24] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[25]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[24] ),
.Q(\data_sr_reg_n_0_[25] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[26]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[25] ),
.Q(\data_sr_reg_n_0_[26] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[27]
(.C(clk),
.CE(1'b1),
.D(\data_sr[27]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[27] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[28]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[27] ),
.Q(\data_sr_reg_n_0_[28] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[29]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[28] ),
.Q(\data_sr_reg_n_0_[29] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[2]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[1] ),
.Q(\data_sr_reg_n_0_[2] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[30]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr_reg_n_0_[29] ),
.Q(\data_sr_reg_n_0_[30] ),
.R(\data_sr[30]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\data_sr_reg[31]
(.C(clk),
.CE(1'b1),
.D(\data_sr[31]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[31] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[3]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[3]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[4]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[4]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[5]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[5]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[6]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[6]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[7]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[7]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[8]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[8]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\data_sr_reg[9]
(.C(clk),
.CE(busy_sr0),
.D(\data_sr[9]_i_1_n_0 ),
.Q(\data_sr_reg_n_0_[9] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT1 #(
.INIT(2'h1))
\divider[0]_i_1
(.I0(divider_reg__1[0]),
.O(p_0_in__0[0]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h6))
\divider[1]_i_1
(.I0(divider_reg__1[0]),
.I1(divider_reg__1[1]),
.O(p_0_in__0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\divider[2]_i_1
(.I0(divider_reg__1[1]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[2]),
.O(p_0_in__0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\divider[3]_i_1
(.I0(divider_reg__1[2]),
.I1(divider_reg__1[0]),
.I2(divider_reg__1[1]),
.I3(divider_reg__1[3]),
.O(p_0_in__0[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h7FFF8000))
\divider[4]_i_1
(.I0(divider_reg__1[3]),
.I1(divider_reg__1[1]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[2]),
.I4(divider_reg__1[4]),
.O(p_0_in__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\divider[5]_i_1
(.I0(divider_reg__1[4]),
.I1(divider_reg__1[2]),
.I2(divider_reg__1[0]),
.I3(divider_reg__1[1]),
.I4(divider_reg__1[3]),
.I5(divider_reg__1[5]),
.O(p_0_in__0[5]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h9))
\divider[6]_i_1
(.I0(\busy_sr[0]_i_3_n_0 ),
.I1(divider_reg__0[6]),
.O(p_0_in__0[6]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hD2))
\divider[7]_i_2
(.I0(divider_reg__0[6]),
.I1(\busy_sr[0]_i_3_n_0 ),
.I2(divider_reg__0[7]),
.O(p_0_in__0[7]));
FDRE #(
.INIT(1'b1))
\divider_reg[0]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[0]),
.Q(divider_reg__1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[1]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[1]),
.Q(divider_reg__1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[2]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[2]),
.Q(divider_reg__1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[3]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[3]),
.Q(divider_reg__1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[4]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[4]),
.Q(divider_reg__1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[5]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[5]),
.Q(divider_reg__1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[6]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[6]),
.Q(divider_reg__0[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\divider_reg[7]
(.C(clk),
.CE(\busy_sr_reg[31]_1 ),
.D(p_0_in__0[7]),
.Q(divider_reg__0[7]),
.R(1'b0));
LUT6 #(
.INIT(64'hFCFCFFF8FFFFFFFF))
sioc_i_1
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(sioc_i_2_n_0),
.I2(sioc_i_3_n_0),
.I3(\busy_sr_reg_n_0_[1] ),
.I4(sioc_i_4_n_0),
.I5(p_0_in),
.O(sioc_i_1_n_0));
LUT2 #(
.INIT(4'h6))
sioc_i_2
(.I0(divider_reg__0[6]),
.I1(divider_reg__0[7]),
.O(sioc_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hA222))
sioc_i_3
(.I0(sioc_i_5_n_0),
.I1(\busy_sr_reg_n_0_[30] ),
.I2(divider_reg__0[6]),
.I3(p_0_in),
.O(sioc_i_3_n_0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7FFF))
sioc_i_4
(.I0(\busy_sr_reg_n_0_[29] ),
.I1(\busy_sr_reg_n_0_[2] ),
.I2(p_0_in),
.I3(\busy_sr_reg_n_0_[30] ),
.O(sioc_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
sioc_i_5
(.I0(\busy_sr_reg_n_0_[0] ),
.I1(\busy_sr_reg_n_0_[1] ),
.I2(\busy_sr_reg_n_0_[29] ),
.I3(\busy_sr_reg_n_0_[2] ),
.O(sioc_i_5_n_0));
FDRE sioc_reg
(.C(clk),
.CE(1'b1),
.D(sioc_i_1_n_0),
.Q(sioc),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
siod_INST_0
(.I0(\data_sr_reg_n_0_[31] ),
.I1(siod_INST_0_i_1_n_0),
.O(siod));
LUT6 #(
.INIT(64'hB0BBB0BB0000B0BB))
siod_INST_0_i_1
(.I0(\busy_sr_reg_n_0_[28] ),
.I1(\busy_sr_reg_n_0_[29] ),
.I2(p_1_in_0[0]),
.I3(p_1_in_0[1]),
.I4(\busy_sr_reg_n_0_[11] ),
.I5(\busy_sr_reg_n_0_[10] ),
.O(siod_INST_0_i_1_n_0));
FDRE taken_reg
(.C(clk),
.CE(1'b1),
.D(\busy_sr_reg[31]_0 ),
.Q(E),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "ov7670_controller" *)
module system_ov7670_controller_0_0_ov7670_controller
(config_finished,
siod,
sioc,
resend,
clk);
output config_finished;
output siod;
output sioc;
input resend;
input clk;
wire Inst_i2c_sender_n_3;
wire Inst_ov7670_registers_n_16;
wire Inst_ov7670_registers_n_18;
wire clk;
wire config_finished;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire sioc;
wire siod;
wire [15:0]sreg_reg;
wire taken;
system_ov7670_controller_0_0_i2c_sender Inst_i2c_sender
(.DOADO(sreg_reg),
.E(taken),
.\busy_sr_reg[1]_0 (Inst_i2c_sender_n_3),
.\busy_sr_reg[31]_0 (Inst_ov7670_registers_n_18),
.\busy_sr_reg[31]_1 (Inst_ov7670_registers_n_16),
.clk(clk),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.sioc(sioc),
.siod(siod));
system_ov7670_controller_0_0_ov7670_registers Inst_ov7670_registers
(.DOADO(sreg_reg),
.E(taken),
.clk(clk),
.config_finished(config_finished),
.\divider_reg[2] (Inst_i2c_sender_n_3),
.\divider_reg[7] (Inst_ov7670_registers_n_16),
.p_0_in(p_0_in),
.p_1_in(p_1_in),
.resend(resend),
.taken_reg(Inst_ov7670_registers_n_18));
endmodule
(* ORIG_REF_NAME = "ov7670_registers" *)
module system_ov7670_controller_0_0_ov7670_registers
(DOADO,
\divider_reg[7] ,
config_finished,
taken_reg,
p_1_in,
clk,
\divider_reg[2] ,
p_0_in,
resend,
E);
output [15:0]DOADO;
output [0:0]\divider_reg[7] ;
output config_finished;
output taken_reg;
output [0:0]p_1_in;
input clk;
input \divider_reg[2] ;
input p_0_in;
input resend;
input [0:0]E;
wire [15:0]DOADO;
wire [0:0]E;
wire [7:0]address;
wire [7:0]address_reg__0;
wire \address_rep[0]_i_1_n_0 ;
wire \address_rep[1]_i_1_n_0 ;
wire \address_rep[2]_i_1_n_0 ;
wire \address_rep[3]_i_1_n_0 ;
wire \address_rep[4]_i_1_n_0 ;
wire \address_rep[5]_i_1_n_0 ;
wire \address_rep[6]_i_1_n_0 ;
wire \address_rep[7]_i_1_n_0 ;
wire \address_rep[7]_i_2_n_0 ;
wire clk;
wire config_finished;
wire config_finished_INST_0_i_1_n_0;
wire config_finished_INST_0_i_2_n_0;
wire config_finished_INST_0_i_3_n_0;
wire config_finished_INST_0_i_4_n_0;
wire \divider_reg[2] ;
wire [0:0]\divider_reg[7] ;
wire p_0_in;
wire [0:0]p_1_in;
wire resend;
wire taken_reg;
wire [15:0]NLW_sreg_reg_DOBDO_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPADOP_UNCONNECTED;
wire [1:0]NLW_sreg_reg_DOPBDOP_UNCONNECTED;
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address_reg__0[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address_reg__0[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address_reg__0[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address_reg__0[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address_reg__0[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address_reg__0[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address_reg__0[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address_reg__0[7]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[0]
(.C(clk),
.CE(E),
.D(\address_rep[0]_i_1_n_0 ),
.Q(address[0]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[1]
(.C(clk),
.CE(E),
.D(\address_rep[1]_i_1_n_0 ),
.Q(address[1]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[2]
(.C(clk),
.CE(E),
.D(\address_rep[2]_i_1_n_0 ),
.Q(address[2]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[3]
(.C(clk),
.CE(E),
.D(\address_rep[3]_i_1_n_0 ),
.Q(address[3]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[4]
(.C(clk),
.CE(E),
.D(\address_rep[4]_i_1_n_0 ),
.Q(address[4]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[5]
(.C(clk),
.CE(E),
.D(\address_rep[5]_i_1_n_0 ),
.Q(address[5]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[6]
(.C(clk),
.CE(E),
.D(\address_rep[6]_i_1_n_0 ),
.Q(address[6]),
.R(resend));
(* equivalent_register_removal = "no" *)
FDRE #(
.INIT(1'b0))
\address_reg_rep[7]
(.C(clk),
.CE(E),
.D(\address_rep[7]_i_1_n_0 ),
.Q(address[7]),
.R(resend));
LUT1 #(
.INIT(2'h1))
\address_rep[0]_i_1
(.I0(address_reg__0[0]),
.O(\address_rep[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h6))
\address_rep[1]_i_1
(.I0(address_reg__0[0]),
.I1(address_reg__0[1]),
.O(\address_rep[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'h78))
\address_rep[2]_i_1
(.I0(address_reg__0[1]),
.I1(address_reg__0[0]),
.I2(address_reg__0[2]),
.O(\address_rep[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'h7F80))
\address_rep[3]_i_1
(.I0(address_reg__0[2]),
.I1(address_reg__0[0]),
.I2(address_reg__0[1]),
.I3(address_reg__0[3]),
.O(\address_rep[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h7FFF8000))
\address_rep[4]_i_1
(.I0(address_reg__0[3]),
.I1(address_reg__0[1]),
.I2(address_reg__0[0]),
.I3(address_reg__0[2]),
.I4(address_reg__0[4]),
.O(\address_rep[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\address_rep[5]_i_1
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'h9))
\address_rep[6]_i_1
(.I0(\address_rep[7]_i_2_n_0 ),
.I1(address_reg__0[6]),
.O(\address_rep[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hD2))
\address_rep[7]_i_1
(.I0(address_reg__0[6]),
.I1(\address_rep[7]_i_2_n_0 ),
.I2(address_reg__0[7]),
.O(\address_rep[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\address_rep[7]_i_2
(.I0(address_reg__0[4]),
.I1(address_reg__0[2]),
.I2(address_reg__0[0]),
.I3(address_reg__0[1]),
.I4(address_reg__0[3]),
.I5(address_reg__0[5]),
.O(\address_rep[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT5 #(
.INIT(32'h0000FFFE))
\busy_sr[0]_i_2
(.I0(config_finished_INST_0_i_4_n_0),
.I1(config_finished_INST_0_i_3_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_1_n_0),
.I4(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h0001))
config_finished_INST_0
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.O(config_finished));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_1
(.I0(DOADO[5]),
.I1(DOADO[4]),
.I2(DOADO[7]),
.I3(DOADO[6]),
.O(config_finished_INST_0_i_1_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_2
(.I0(DOADO[1]),
.I1(DOADO[0]),
.I2(DOADO[3]),
.I3(DOADO[2]),
.O(config_finished_INST_0_i_2_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_3
(.I0(DOADO[13]),
.I1(DOADO[12]),
.I2(DOADO[15]),
.I3(DOADO[14]),
.O(config_finished_INST_0_i_3_n_0));
LUT4 #(
.INIT(16'h7FFF))
config_finished_INST_0_i_4
(.I0(DOADO[9]),
.I1(DOADO[8]),
.I2(DOADO[11]),
.I3(DOADO[10]),
.O(config_finished_INST_0_i_4_n_0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\divider[7]_i_1
(.I0(config_finished_INST_0_i_1_n_0),
.I1(config_finished_INST_0_i_2_n_0),
.I2(config_finished_INST_0_i_3_n_0),
.I3(config_finished_INST_0_i_4_n_0),
.I4(\divider_reg[2] ),
.I5(p_0_in),
.O(\divider_reg[7] ));
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* \MEM.PORTA.DATA_BIT_LAYOUT = "p0_d16" *)
(* METHODOLOGY_DRC_VIOS = "{SYNTH-6 {cell *THIS*}}" *)
(* RTL_RAM_BITS = "4096" *)
(* RTL_RAM_NAME = "U0/Inst_ov7670_registers/sreg" *)
(* bram_addr_begin = "0" *)
(* bram_addr_end = "1023" *)
(* bram_slice_begin = "0" *)
(* bram_slice_end = "15" *)
RAMB18E1 #(
.DOA_REG(0),
.DOB_REG(0),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h53295217510C50344F4014383A04401004008C003E000C001100120412801280),
.INIT_01(256'h229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440),
.INIT_02(256'h90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907),
.INIT_03(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100),
.INIT_04(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_05(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_06(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_07(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_08(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_09(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0A(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0B(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0C(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0D(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0E(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_0F(256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(0),
.RSTREG_PRIORITY_A("RSTREG"),
.RSTREG_PRIORITY_B("RSTREG"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(0))
sreg_reg
(.ADDRARDADDR({1'b0,1'b0,address,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CLKARDCLK(clk),
.CLKBWRCLK(1'b0),
.DIADI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIBDI({1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b1,1'b1}),
.DOADO(DOADO),
.DOBDO(NLW_sreg_reg_DOBDO_UNCONNECTED[15:0]),
.DOPADOP(NLW_sreg_reg_DOPADOP_UNCONNECTED[1:0]),
.DOPBDOP(NLW_sreg_reg_DOPBDOP_UNCONNECTED[1:0]),
.ENARDEN(1'b1),
.ENBWREN(1'b0),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({1'b0,1'b0}),
.WEBWE({1'b0,1'b0,1'b0,1'b0}));
LUT6 #(
.INIT(64'h0000000055555554))
taken_i_1
(.I0(p_0_in),
.I1(config_finished_INST_0_i_1_n_0),
.I2(config_finished_INST_0_i_2_n_0),
.I3(config_finished_INST_0_i_3_n_0),
.I4(config_finished_INST_0_i_4_n_0),
.I5(\divider_reg[2] ),
.O(taken_reg));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09:24:59 10/24/2009
// Design Name:
// Module Name: FONT5_9Chan
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
//
// Note: the XIL_PAR_ALLOW_LVDS_LOC_OVERRIDE environment variable was set to
// true to allow MAP to complete. It complained that about 5 of the ch1
// data bits were connected backwards to the differential inputs, and would
// have the wrong polarity. The env. var. overode this error
//
//////////////////////////////////////////////////////////////////////////////////
module FONT5_base_xlnx(
input clk357_n,
input clk357_p,
input clk40_s,
input ch1_drdy_n,
input ch2_drdy_n,
input ch3_drdy_n,
input ch1_drdy_p,
input ch2_drdy_p,
input ch3_drdy_p,
input signed [12:0] ch1_data_in_n,
input signed [12:0] ch2_data_in_n,
input signed [12:0] ch3_data_in_n,
input signed [12:0] ch1_data_in_p,
input signed [12:0] ch2_data_in_p,
input signed [12:0] ch3_data_in_p,
input ch4_drdy_n,
input ch5_drdy_n,
input ch6_drdy_n,
input ch4_drdy_p,
input ch5_drdy_p,
input ch6_drdy_p,
input signed [12:0] ch4_data_in_n,
input signed [12:0] ch5_data_in_n,
input signed [12:0] ch6_data_in_n,
input signed [12:0] ch4_data_in_p,
input signed [12:0] ch5_data_in_p,
input signed [12:0] ch6_data_in_p,
input ch7_drdy_n,
input ch8_drdy_n,
input ch9_drdy_n,
input ch7_drdy_p,
input ch8_drdy_p,
input ch9_drdy_p,
input signed [12:0] ch7_data_in_n,
input signed [12:0] ch8_data_in_n,
input signed [12:0] ch9_data_in_n,
input signed [12:0] ch7_data_in_p,
input signed [12:0] ch8_data_in_p,
input signed [12:0] ch9_data_in_p,
input rs232_in,
//output amp_trig,
//output amp_trig2,
output adc_powerdown,
output adc1_clk_n,
output adc1_clk_p,
output adc2_clk_n,
output adc2_clk_p,
output adc3_clk_n,
output adc3_clk_p,
output signed [12:0] dac1_out,
output dac1_clk,
output signed [12:0] dac2_out,
output dac2_clk,
// output [12:0] dac3_out,
// output dac3_clk,
// output [12:0] dac4_out,
// output dac4_clk,
output rs232_out,
output led0_out,
output led1_out,
output led2_out,
output trim_cs_ld,
output trim_sck,
output trim_sdi,
output diginput1A,
output diginput1B,
input diginput1,
output diginput2A,
output diginput2B,
input diginput2,
//output auxOutA,
//output auxOutB
output auxOutA1,
output auxOutB1,
output auxOutA2,
output auxOutB2,
(* PULLUP = "TRUE" *) input FONT5_detect,
output DirectIO2,
input auxInA,
output auxOutC
//inout DirectIO1
//input FONT5_detect
//diginput2_loopback
);
//`include "H:\Firmware\FONT5_base\sources\verilog\definitions.vh"
//wire signed [12:0] dac1_out, dac2_out;
//wire dac1_clk, dac2_clk;
//assign dac3_out = dac1_out;
//assign dac4_out = dac2_out;
//assign dac3_clk = dac1_clk;
//assign dac4_clk = dac2_clk;
//`define FASTCLK_INT
//`define CLK357_PLL
supply0 gnd;
supply1 vcc;
//signal declarations for slow clock (on-board oscillator)
wire clk40_ibufg, clk200, clk40_dcm, dcm200_locked, clk40_blk, idelayctrl_rdy;
//(* clock_buffer = "BUFG" *) wire clk40;
wire clk40;
//signal declarations for fast clock (external)
//(* clock_buffer = "BUFG" *) wire clk357_delayed;
//wire clk357_delayed;
wire clk357_ibufg, clk357_bufg, clk357_delayed;
`ifdef CLK357_PLL
wire pll_clk357_fb, pll_clk357_locked, clk357_pll;
`endif
//(* clock_buffer = "BUFG" *) wire clk357_pll;
wire clk357_idelay_ce, clk357_idelay_rst, idelay_rst;
//(* clock_buffer = "BUFGMUX" *) wire clk357;
wire clk357;
wire ch1_drdy, ch2_drdy, ch3_drdy, ch4_drdy, ch5_drdy, ch6_drdy, ch7_drdy, ch8_drdy, ch9_drdy;
wire delay_calc_strb1, delay_calc_strb2, delay_calc_strb3, delay_trig1, delay_trig2, delay_trig3, adc1_drdy_delay_ce, adc2_drdy_delay_ce, adc3_drdy_delay_ce;
wire ch1_drdy_out, ch2_drdy_out, ch3_drdy_out, ch4_drdy_out, ch5_drdy_out, ch6_drdy_out, ch7_drdy_out, ch8_drdy_out, ch9_drdy_out;
wire adc1_clk_delay_ce, adc2_clk_delay_ce, adc3_clk_delay_ce;
wire adc1_data_delay_ce, adc2_data_delay_ce, adc3_data_delay_ce;
wire adc1_clk, adc2_clk, adc3_clk;
wire signed [12:0] ch1_data_in, ch2_data_in, ch3_data_in, ch4_data_in, ch5_data_in, ch6_data_in, ch7_data_in, ch8_data_in, ch9_data_in;
wire signed [12:0] ch1_data_in_del, ch2_data_in_del, ch3_data_in_del, ch4_data_in_del, ch5_data_in_del, ch6_data_in_del, ch7_data_in_del, ch8_data_in_del, ch9_data_in_del;
wire IDDR1_Q1, IDDR1_Q2, IDDR2_Q1, IDDR2_Q2, IDDR3_Q1, IDDR3_Q2;
//Detect board variant and configure AUX_OUTS
//wire auxOutA, auxOutB;
//assign auxOutA1 = (FONT5_detect) ? auxOutA : 1'bz;
//assign auxOutB1 = (FONT5_detect) ? auxOutB : 1'bz;
//assign auxOutA2 = (FONT5_detect) ? 1'bz : ~auxOutA; // NB: auxOuts on FONT5A boards use inverting buffers
//assign auxOutB2 = (FONT5_detect) ? 1'bz : ~auxOutB; // NB: auxOuts on FONT5A boards use inverting buffers
//assign auxOutA2 = auxOutA;
//assign auxOutB2 = auxOutB;
//DCM config reset
wire config_rst;
DCM_config_rst ConfigRst1(clk40_ibufg, config_rst);
//wire clk40_bufg;
IBUFG #(
.IOSTANDARD("DEFAULT")
) IBUFG_clk40 (
.O(clk40_ibufg), // Clock buffer output
.I(clk40_s) // Clock buffer input (connect directly to top-level port)
);
//DCM for 200 MHz
DCM1 DCM200 (
.CLKIN_IN(clk40_ibufg),
//.RST_IN(dcm200_rst),
.RST_IN(config_rst),
.CLKFX_OUT(clk200),
//.CLKIN_IBUFG_OUT(clk40_ibufg),
.CLK0_OUT(clk40_dcm),
.LOCKED_OUT(dcm200_locked)
);
//assign clk40_ibufg = clk40_bufg;
// %%%%%%%%%%%%%%% 40MHz INPUT - 200MHz gen - IDELAYCTRL %%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// **** Input buffer for 40Mz on-board oscillator ****
// Note the clk40_ibufg clocks the reset logic since it is present during DCM reset,
// and the UART & Decoder for the same reason
BUFGCE BUFGCE_DCM_CLK40 (
.O(clk40),
.CE(~clk40_blk),
.I(clk40_dcm)
);
//assign clk40 = (clk40_blk) ? 1'b0 : clk40_dcm;
// **** IDELAYCTRL instantiation ****
// Single instantiation template for all IODELAYS
IDELAYCTRL IDELAYCTRL1 (
.RDY(idelayctrl_rdy),
.REFCLK(clk200),
.RST(~dcm200_locked)
);
// %%%%%%%%%%%%%%%%%%%%%%%%%%%% 357MHz INPUT %%%%%%%%%%%%%%%%%%%%%%%%%%%%
// %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
wire fastClk_ext;
`ifdef FASTCLK_INT
wire fastClk_int, dcm360_locked;
//(* clock_buffer = "BUFG" *) wire fastClk_ext;
//Internal clock DCM
DCM2 DCM360(
.CLKIN_IN(clk40_ibufg),
//.RST_IN(dcm200_rst),
.RST_IN(config_rst),
.CLKFX_OUT(fastClk_int),
.CLK0_OUT(),
.LOCKED_OUT(dcm360_locked)
);
// **** Differential input buffer for the master 357MHz clock ****
/*IBUFGDS #(
.DIFF_TERM("TRUE"),
.IOSTANDARD("DEFAULT")
) IBUFGDS_CLK357 (
.O(clk357_ibufg),
.I(clk357_p),
.IB(clk357_n)
);*/
`endif
IBUFDS #( //changed to IBUFDS - 16/3/15
.DIFF_TERM("TRUE"),
.IOSTANDARD("DEFAULT")
) IBUFGDS_CLK357 (
.O(clk357_ibufg),
.I(clk357_p),
.IB(clk357_n)
);
`ifdef CLK357_PLL
wire dcm200_rst;
//Instance pll_clkSwitch
//wire fastClk_sel, clkSwitch_out, pll_rst;
//pll_clkSwitch clkSwitch1(clk40, fastClk_sel, clkSwitch_out, pll_rst); //Custom-VCD on fastClk_sel
// **** PLL for master 357MHz clock ****
// Configured as a jitter filter (low bandwidth, internal feedback)
// VCO frequency 2*357MHz
// Output via global clock buffer as required
PLL_BASE #(
.BANDWIDTH("LOW"), //Better jitter filter performance (V5 user guide)
.CLKFBOUT_MULT(2),
.CLKFBOUT_PHASE(0.0),
.CLKIN_PERIOD(2.8), // ns
.CLKOUT0_DIVIDE(2),
.CLKOUT0_DUTY_CYCLE(0.5),
.CLKOUT0_PHASE(0.0),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.5),
.CLKOUT1_PHASE(0.0),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.5),
.CLKOUT2_PHASE(0.0),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.5),
.CLKOUT3_PHASE(0.0),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.5),
.CLKOUT4_PHASE(0.0),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.5),
.CLKOUT5_PHASE(0.0),
.COMPENSATION("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE(1),
.REF_JITTER(0.100) // Input reference jitter *LEFT AT DEFAULT*
) PLL_CLK357 (
.CLKFBOUT(pll_clk357_fb), // Internal feedback signal
.CLKOUT0(clk357_pll),
//.CLKOUT0(fastClk_ext),
.CLKOUT1(),
.CLKOUT2(),
.CLKOUT3(),
.CLKOUT4(),
.CLKOUT5(),
.LOCKED(pll_clk357_locked),
.CLKFBIN(pll_clk357_fb), // Internal feedback signal
//.CLKIN(clk357_ibufg),
.CLKIN(clk357_bufg),
//.CLKIN(clk357_delayed),
.RST(dcm200_rst)
);
// PLL_ADV: Phase-Lock Loop Clock Circuit
// Virtex-5
// Xilinx HDL Language Template, version 14.7
/* PLL_ADV #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(2), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN1_PERIOD(2.800), // Clock period (ns) of input clock on CLKIN1
.CLKIN2_PERIOD(2.778), // Clock period (ns) of input clock on CLKIN2
.CLKOUT0_DIVIDE(1), // Division factor for CLKOUT0 (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(1), // Division factor for CLKOUT1 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(1), // Division factor for CLKOUT2 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(1), // Division factor for CLKOUT3 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(0.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(1), // Division factor for CLKOUT4 (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(1), // Division factor for CLKOUT5 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(0.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
// "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL",
// "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.EN_REL("FALSE"), // Enable release (PMCD mode only)
.PLL_PMCD_MODE("FALSE"), // PMCD Mode, TRUE/FASLE
.REF_JITTER(0.100), // Input reference jitter (0.000 to 0.999 UI%)
.RST_DEASSERT_CLK("CLKIN1") // In PMCD mode, clock to synchronize RST release
) PLL_ADV_inst (
.CLKFBDCM(), // Output feedback signal used when PLL feeds a DCM
.CLKFBOUT(pll_clk357_fb), // General output feedback signal
.CLKOUT0(clk357_pll), // One of six general clock output signals
.CLKOUT1(), // One of six general clock output signals
.CLKOUT2(), // One of six general clock output signals
.CLKOUT3(), // One of six general clock output signals
.CLKOUT4(), // One of six general clock output signals
.CLKOUT5(), // One of six general clock output signals
.CLKOUTDCM0(), // One of six clock outputs to connect to the DCM
.CLKOUTDCM1(), // One of six clock outputs to connect to the DCM
.CLKOUTDCM2(), // One of six clock outputs to connect to the DCM
.CLKOUTDCM3(), // One of six clock outputs to connect to the DCM
.CLKOUTDCM4(), // One of six clock outputs to connect to the DCM
.CLKOUTDCM5(), // One of six clock outputs to connect to the DCM
.DO(), // Dynamic reconfig data output (16-bits)
.DRDY(), // Dynamic reconfig ready output
.LOCKED(pll_clk357_locked), // Active high PLL lock signal
.CLKFBIN(pll_clk357_fb), // Clock feedback input
.CLKIN1(clk357_ibufg), // Primary clock input
.CLKIN2(fastClk_int), // Secondary clock input
.CLKINSEL(clkSwitch_out), // Selects '1' = CLKIN1, '0' = CLKIN2
.DADDR(), // Dynamic reconfig address input (5-bits)
.DCLK(), // Dynamic reconfig clock input
.DEN(), // Dynamic reconfig enable input
.DI(), // Dynamic reconfig data input (16-bits)
.DWE(), // Dynamic reconfig write enable input
.REL(), // Clock release input (PMCD mode only)
.RST(pll_rst | dcm200_rst) // Asynchronous PLL reset
);*/
BUFG BUFG_PLL_CLK357 (
.O(clk357_bufg),
//.I(clk357_pll)
.I(clk357_delayed)
);
`else
assign clk357_bufg = clk357_delayed;
`endif
// **** IDELAY for the master 357MHz clock ****
IODELAY # (
//.DELAY_SRC("DATAIN"),
.DELAY_SRC("I"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(0),
.ODELAY_VALUE(0),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("CLOCK")
) IODELAY_MASTER_CLK357 (
//.DATAOUT(clk357_bufg),
//.DATAOUT(fastClk_ext),
.DATAOUT(clk357_delayed),
.C(clk40),
.CE(clk357_idelay_ce),
//.DATAIN(clk357_bufg),
//.DATAIN(clk357_pll),
//.IDATAIN(clk357_ibufg),
//.IDATAIN(gnd), // Must be grounded
.IDATAIN(clk357_ibufg), // Must be grounded
.INC(1'b1), // Always increment
.ODATAIN(gnd), // Must be grounded
.RST(clk357_idelay_rst | idelay_rst), //Reset when modifying delay or as part of full reset
.T(vcc) // 1==INPUT/INTERNAL 0==OUTPUT
);
// **** Final global clock buffer for 357MHz distribution ****
/*BUFG BUFG_CLK357 (
.O(fastClk_ext),
//.O(clk357),
//.I(clk357_delayed)
.I(clk357_pll)
);
*/
`ifdef CLK357_PLL
wire clkPLL_sel;
BUFGMUX_CTRL BUFG_CLK357 (
.O(fastClk_ext), // Clock MUX output
.I0(clk357_pll), // Clock0 input
//.I0(clk357_delayed), // Clock0 input
.I1(clk357_bufg), // Clock1 input
.S(clkPLL_sel) // Clock select input
//.S(1'b0) // Clock select input
);
`else
BUFG BUFG_CLK357 (
.O(fastClk_ext),
.I(clk357_bufg)
);
`endif
`ifdef FASTCLK_INT
wire fastClk_sel;
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
.O(clk357), // Clock MUX output
.I0(fastClk_ext), // Clock0 input
//.I0(clk357_delayed), // Clock0 input
.I1(fastClk_int), // Clock1 input
.S(fastClk_sel) // Clock select input
);
`else
assign clk357 = fastClk_ext;
`endif
//assign clk357 = (fastClk_sel) ? fastClk_int : fastClk_ext;
//Instantiate IBUFDS and IODELAYs for the incoming DATA, DRDY, and ADC clocks
`include "DRDY_IBUFDS_inst.v"
`include "DRDY_IDELAY_inst.v"
IODELAY # (
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(0),
.ODELAY_VALUE(0),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("CLOCK")
) adc1_clk_odelay (
.DATAOUT(adc1_clk),
.C(clk40),
.CE(adc1_clk_delay_ce),
.DATAIN(clk357),
.IDATAIN(gnd), // Must be grounded
.INC(1'b1), // Always increment
.ODATAIN(gnd), // Must be grounded
.RST(delay_calc_strb1 | delay_trig1),
.T(vcc) // 1==INPUT/INTERNAL 0==OUTPUT
);
IODELAY # (
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(0),
.ODELAY_VALUE(0),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("CLOCK")
) adc2_clk_odelay (
.DATAOUT(adc2_clk),
.C(clk40),
.CE(adc2_clk_delay_ce),
.DATAIN(clk357),
.IDATAIN(gnd), // Must be grounded
.INC(1'b1), // Always increment
.ODATAIN(gnd), // Must be grounded
.RST(delay_calc_strb2 | delay_trig2),
.T(vcc) // 1==INPUT/INTERNAL 0==OUTPUT
);
IODELAY # (
.DELAY_SRC("DATAIN"),
.HIGH_PERFORMANCE_MODE("TRUE"),
.IDELAY_TYPE("VARIABLE"),
.IDELAY_VALUE(0),
.ODELAY_VALUE(0),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("CLOCK")
) adc3_clk_odelay (
.DATAOUT(adc3_clk),
.C(clk40),
.CE(adc3_clk_delay_ce),
.DATAIN(clk357),
.IDATAIN(gnd), // Must be grounded
.INC(1'b1), // Always increment
.ODATAIN(gnd), // Must be grounded
.RST(delay_calc_strb3 | delay_trig3),
.T(vcc) // 1==INPUT/INTERNAL 0==OUTPUT
);
`include "DATA_IBUFDS_inst.v"
`include "DATA_IODELAY_inst.v"
//wire adc1_clk_buf;
//assign adc1_clk_buf = adc1_clk & pad_support;
wire run;
// **** Differential output buffers for ADC group clocks ****
OBUFDS #(
//.IOSTANDARD("DEFAULT")
.IOSTANDARD("LVPECL_25")
) OBUFDS_ADC1 (
.O(adc1_clk_p),
.OB(adc1_clk_n),
.I(adc1_clk & run)
//.I(adc1_clk)
);
OBUFDS #(
//.IOSTANDARD("DEFAULT")
.IOSTANDARD("LVPECL_25")
) OBUFDS_ADC2 (
.O(adc2_clk_p),
.OB(adc2_clk_n),
.I(adc2_clk & run)
//.I(adc2_clk)
);
OBUFDS #(
//.IOSTANDARD("DEFAULT")
.IOSTANDARD("LVPECL_25")
) OBUFDS_ADC3 (
.O(adc3_clk_p),
.OB(adc3_clk_n),
.I(adc3_clk & run)
//.I(adc3_clk)
);
wire drdy1 = ch1_drdy_out; //to keep with the logical names for changing this dynamically
wire drdy2 = ch4_drdy_out;
wire drdy3 = ch7_drdy_out;
wire iddr_ce;
//wire dcm200_rst;
// Instantiate the double data input in the IOB
/*
IDDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("ASYNC")
) DRDY_IDDR1 (
.Q1(IDDR1_Q1),
.Q2(IDDR1_Q2),
.C(clk357),
.CE(1'b1),
.D(drdy1),
.R(dcm200_rst),
.S(1'b0)
);
IDDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("ASYNC")
) DRDY_IDDR2 (
.Q1(IDDR2_Q1),
.Q2(IDDR2_Q2),
.C(clk357),
.CE(1'b1),
.D(drdy2),
.R(dcm200_rst),
.S(1'b0)
);
IDDR #(
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("ASYNC")
) DRDY_IDDR3 (
.Q1(IDDR3_Q1),
.Q2(IDDR3_Q2),
.C(clk357),
.CE(1'b1),
.D(drdy3),
.R(dcm200_rst),
.S(1'b0)
);
*/
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("SYNC")
) DRDY_IDDR1 (
.Q1(IDDR1_Q1),
.Q2(IDDR1_Q2),
.C(clk357),
.CE(iddr_ce),
.D(drdy1),
.R(gnd),
.S(gnd)
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("SYNC")
) DRDY_IDDR2 (
.Q1(IDDR2_Q1),
.Q2(IDDR2_Q2),
.C(clk357),
.CE(iddr_ce),
.D(drdy2),
.R(gnd),
.S(gnd)
);
IDDR #(
.DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.SRTYPE("SYNC")
) DRDY_IDDR3 (
.Q1(IDDR3_Q1),
.Q2(IDDR3_Q2),
.C(clk357),
.CE(iddr_ce),
.D(drdy3),
.R(gnd),
.S(gnd)
);
//Instance the auxOut selection module
wire auxOutA, auxOutB;
auxOut_select auxOut_select(clk357, FONT5_detect, auxOutA, auxOutB, auxOutA1, auxOutB1, auxOutA2, auxOutB2);
//Instantiate the top level module
FONT5_base FONT5_base_top (
.clk357(clk357),
.clk40(clk40),
.clk40_ibufg(clk40_ibufg),
.ch1_data_in_del(ch1_data_in_del),
.ch2_data_in_del(ch2_data_in_del),
.ch3_data_in_del(ch3_data_in_del),
.ch4_data_in_del(ch4_data_in_del),
.ch5_data_in_del(ch5_data_in_del),
.ch6_data_in_del(ch6_data_in_del),
.ch7_data_in_del(ch7_data_in_del),
.ch8_data_in_del(ch8_data_in_del),
.ch9_data_in_del(ch9_data_in_del),
.rs232_in(rs232_in),
//.amp_trig(amp_trig),
//.amp_trig2(amp_trig2),
.adc_powerdown(adc_powerdown),
.iddr_ce(iddr_ce),
//.dcm200_rst(dcm200_rst), //output to xlnx
.dac1_out(dac1_out),
.dac1_clk(dac1_clk),
.dac2_out(dac2_out),
.dac2_clk(dac2_clk),
// .dac3_out(dac3_out),
// .dac3_clk(dac3_clk),
// .dac4_out(dac4_out),
// .dac4_clk(dac4_clk),
.rs232_out(rs232_out),
.led0_out(led0_out),
.led1_out(led1_out),
.led2_out(led2_out),
.trim_cs_ld(trim_cs_ld),
.trim_sck(trim_sck),
.trim_sdi(trim_sdi),
.diginput1A(diginput1A),
.diginput1B(diginput1B),
.diginput1(diginput1),
.diginput2A(diginput2A),
.diginput2B(diginput2B),
.diginput2(diginput2),
.auxOutA(auxOutA),
.auxOutB(auxOutB),
//.diginput2_loopback(diginput2_loopback),
.dcm200_locked(dcm200_locked), //input to top
.clk_blk(clk40_blk), //output to xlnx
.idelayctrl_rdy(idelayctrl_rdy), //input to top
.clk357_idelay_ce(clk357_idelay_ce), //output to xlnx
.clk357_idelay_rst(clk357_idelay_rst), //output to xlnx
.idelay_rst(idelay_rst), //output to xlnx
`ifdef FASTCLK_INT
.dcm360_locked(dcm360_locked), //input to top
.fastClk_sel(fastClk_sel), //output to xlnx
`endif
`ifdef CLK357_PLL
.dcm200_rst(dcm200_rst), //output to xlnx
.pll_clk357_locked(pll_clk357_locked), //input to top
.clkPLL_sel_a(clkPLL_sel), // output to xlnx
`endif
.run(run), //output to xlnx
.delay_calc_strb1(delay_calc_strb1), //output to xlnx from ADC_block
.delay_calc_strb2(delay_calc_strb2), //output to xlnx from ADC_block
.delay_calc_strb3(delay_calc_strb3), //output to xlnx from ADC_block
.delay_trig1(delay_trig1), //output to xlnx from top (UART decoder)
.delay_trig2(delay_trig2), //output to xlnx from top (UART decoder)
.delay_trig3(delay_trig3), //output to xlnx from top (UART decoder)
.adc1_drdy_delay_ce(adc1_drdy_delay_ce), //output to xlnx from ADC_block
.adc2_drdy_delay_ce(adc2_drdy_delay_ce), //output to xlnx from ADC_block
.adc3_drdy_delay_ce(adc3_drdy_delay_ce), //output to xlnx from ADC_block
.adc1_clk_delay_ce(adc1_clk_delay_ce), //output to xlnx from ADC_block
.adc2_clk_delay_ce(adc2_clk_delay_ce), //output to xlnx from ADC_block
.adc3_clk_delay_ce(adc3_clk_delay_ce), //output to xlnx from ADC_block
.adc1_data_delay_ce(adc1_data_delay_ce), //output to xlnx from ADC_block
.adc2_data_delay_ce(adc2_data_delay_ce), //output to xlnx from ADC_block
.adc3_data_delay_ce(adc3_data_delay_ce), //output to xlnx from ADC_block
.IDDR1_Q1(IDDR1_Q1), //input to top (to Alignment monitors via ADC block)
.IDDR1_Q2(IDDR1_Q2), //input to top (to Alignment monitors via ADC block)
.IDDR2_Q1(IDDR2_Q1), //input to top (to Alignment monitors via ADC block)
.IDDR2_Q2(IDDR2_Q2), //input to top (to Alignment monitors via ADC block)
.IDDR3_Q1(IDDR3_Q1), //input to top (to Alignment monitors via ADC block)
.IDDR3_Q2(IDDR3_Q2), //input to top (to Alignment monitors via ADC block)
//.DirectIO1(DirectIO1)
.DirIOB(DirectIO2),
.auxInA(auxInA),
.auxOutC(auxOutC)
);
endmodule |
module rx(
clk,
reset_,
sample,
rx,
rx_enable,
rxdata);
input clk;
input reset_;
input sample; // Pulse at "sample rate" (16x baud frequency)
input rx; // Serial RX data from FTDI USB chip
output rx_enable; // Set high for one clock when rxdata is ready
output [7:0] rxdata; // Deserialized byte received
wire rx_stop;
wire rx_enable;
reg [2:0] state;
reg [3:0] sample_cnt;
reg [3:0] rxpos;
reg [7:0] rxdata;
// Indicates rxdata is ready (when STOP bit has finished being sampled)
assign rx_enable = state == ST_RXSTOP && rx_stop;
// End of stop bit; either when sample count saturates, or rx goes to
// 0 at least halfway through the expected sample period
assign rx_stop = sample_cnt == 4'hf || (!rx && sample_cnt > 4'h8);
// End of bit period
assign sample_done = sample_cnt == 4'hf;
// Moment when data is sampled; halfway through bit period
assign sample_en = sample_cnt == 4'h8;
parameter ST_IDLE = 2'd0;
parameter ST_RXSTART = 2'd1;
parameter ST_RXDATA = 2'd2;
parameter ST_RXSTOP = 2'd3;
// State machine
always@ (posedge clk or negedge reset_)
if (!reset_)
state <= ST_IDLE;
else if (state == ST_IDLE && !rx)
state <= ST_RXSTART;
else if (state == ST_RXSTART && sample && sample_done)
state <= ST_RXDATA;
else if (state == ST_RXDATA && rxpos == 4'd8 && sample_done)
state <= ST_RXSTOP;
else if (state == ST_RXSTOP && rx_stop)
state <= ST_IDLE;
// Sample counter
always@ (posedge clk or negedge reset_)
if (!reset_)
sample_cnt <= 4'h0;
else if (sample && state == ST_IDLE)
sample_cnt <= 4'h0;
else if (sample && (state == ST_RXSTART && (!rx || sample_cnt != 4'h0)))
sample_cnt <= sample_cnt + 4'h1;
else if (sample && state == ST_RXSTART && sample_done)
sample_cnt <= 4'h0;
else if (sample && (state == ST_RXDATA || state == ST_RXSTOP))
sample_cnt <= sample_cnt + 4'h1;
// Rx data bit position (which bit in the byte are we sampling)
always@ (posedge clk or negedge reset_)
if (!reset_)
rxpos <= 4'h0;
else if (sample && state == ST_RXSTART)
rxpos <= 4'h0;
else if (sample && state == ST_RXDATA && sample_en)
rxpos <= rxpos + 4'h1;
// Deserialized data
always@ (posedge clk or negedge reset_)
if (!reset_)
rxdata <= 8'h0;
else if (sample && sample_en)
rxdata[rxpos[2:0]] <= rx;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_wishbone.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "ethmac_defines.v"
`include "timescale.v"
module eth_wishbone
(
// WISHBONE common
WB_CLK_I, WB_DAT_I, WB_DAT_O,
// WISHBONE slave
WB_ADR_I, WB_WE_I, WB_ACK_O,
BDCs,
Reset,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
PerPacketPad,
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort,
RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood,
AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched,
CarrierSenseLost
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
`ifdef WISHBONE_DEBUG
,
dbg_dat0
`endif
);
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
output [31:0] WB_DAT_O; // WISHBONE data output
// WISHBONE slave
input [9:2] WB_ADR_I; // WISHBONE address input
input WB_WE_I; // WISHBONE write enable input
input [3:0] BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
// WISHBONE master
output [29:0] m_wb_adr_o; //
output [3:0] m_wb_sel_o; //
output m_wb_we_o; //
output [31:0] m_wb_dat_o; //
output m_wb_cyc_o; //
output m_wb_stb_o; //
input [31:0] m_wb_dat_i; //
input m_wb_ack_i; //
input m_wb_err_i; //
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
`ifdef BURST_4BEAT
output reg [1:0] m_wb_bte_o; // Burst Type Extension
`else
output [1:0] m_wb_bte_o; // Burst Type Extension
`endif
reg [2:0] m_wb_cti_o; // Cycle Type Identifier
`endif
input Reset; // Reset signal
// Rx Status signals
input InvalidSymbol; // Invalid symbol was received during
// reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving
// frame
input ShortFrame; // Frame shorter then the minimum size
// (r_MinFL) was received while small
// packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than
// r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are
// good
input AddressMiss; // When a packet is received AddressMiss
// status is written to the Rx BD
input r_RxFlow;
input r_PassAll;
input ReceivedPauseFrm;
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value +
// 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered
// before sucessfully sent)
output RstDeferLatched;
input CarrierSenseLost; // Carrier Sense was lost during the
// frame transmission
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
output TxStartFrm; // Transmit packet start frame
output TxEndFrm; // Transmit packet end frame
output [7:0] TxData; // Transmit packet data byte
output TxUnderRun; // Transmit packet under-run
output PerPacketCrcEn; // Per packet crc enable
output PerPacketPad; // Per packet pading
// Rx
input MRxClk; // Receive clock (from PHY)
input [7:0] RxData; // Received data byte (from PHY)
input RxValid; //
input RxStartFrm; //
input RxEndFrm; //
input RxAbort; // This signal is set when address doesn't
// match.
output RxStatusWriteLatched_sync2;
//Register
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Receive buffer descriptor number
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
`ifdef WISHBONE_DEBUG
output [31:0] dbg_dat0;
`endif
reg TxB_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
reg TxStartFrm;
reg TxEndFrm;
reg [7:0] TxData;
reg TxUnderRun;
reg TxUnderRun_wb;
reg TxBDRead;
wire TxStatusWrite;
reg [1:0] TxValidBytesLatched;
reg [15:0] TxLength;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
reg [14:13] RxStatus;
reg TxStartFrm_wb;
reg TxRetry_wb;
reg TxAbort_wb;
reg TxDone_wb;
reg TxDone_wb_q;
reg TxAbort_wb_q;
reg TxRetry_wb_q;
reg TxRetryPacket;
reg TxRetryPacket_NotCleared;
reg TxDonePacket;
reg TxDonePacket_NotCleared;
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxBDOK/* synthesis syn_allow_retiming=0*/;
reg TxBDReady;
reg RxBDRead ;
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
reg LastWord;
reg ReadTxDataFromFifo_tck;
reg BlockingTxStatusWrite;
reg BlockingTxBDRead;
reg Flop;
reg [7:1] TxBDAddress;
reg [7:1] RxBDAddress;
reg TxRetrySync1;
reg TxAbortSync1;
reg TxDoneSync1;
reg TxAbort_q;
reg TxRetry_q;
reg TxUsedData_q;
reg [31:0] RxDataLatched2;
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
reg [1:0] RxValidBytes;
reg [1:0] RxByteCnt;
reg LastByteIn;
reg ShiftWillEnd;
reg WriteRxDataToFifo;
reg [15:0] LatchedRxLength;
reg RxAbortLatched;
reg ShiftEnded;
reg RxOverrun;
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
wire [31:0] RxBDDataIn; // Rx BD data in
wire [31:0] TxBDDataIn; // Tx BD data in
reg TxEndFrm_wb;
wire TxRetryPulse;
wire TxDonePulse;
wire TxAbortPulse;
wire StartRxBDRead;
wire StartTxBDRead;
wire TxIRQEn;
wire WrapTxStatusBit;
wire RxIRQEn;
wire WrapRxStatusBit;
wire [1:0] TxValidBytes;
wire [7:1] TempTxBDAddress;
wire [7:1] TempRxBDAddress;
wire RxStatusWrite;
wire RxBufferFull;
wire RxBufferAlmostEmpty;
wire RxBufferEmpty;
reg WB_ACK_O;
wire [8:0] RxStatusIn;
reg [8:0] RxStatusInLatched;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg TxEn, TxEn_q /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg r_TxEn_q;
reg r_RxEn_q;
wire ram_ce;
wire [3:0] ram_we;
wire ram_oe;
reg [7:0] ram_addr;
reg [31:0] ram_di;
wire [31:0] ram_do;
wire StartTxPointerRead;
reg TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
wire StartRxPointerRead;
reg RxPointerRead/* synthesis syn_allow_retiming=0*/;
// RX shift ending signals
reg ShiftEnded_rck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
reg ShiftEndedSync_c1;
reg ShiftEndedSync_c2;
wire StartShiftWillEnd;
// Pulse for wishbone side having finished writing back
reg rx_wb_writeback_finished;
// Indicator of last set of writes from the Wishbone master coming up
reg rx_wb_last_writes;
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
wire TxFifoClear;
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/;
reg tx_burst_en;
reg rx_burst_en;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
wire ReadTxDataFromMemory_2;
wire tx_burst;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
reg ReadTxDataFromMemory/* synthesis syn_allow_retiming=0*/;
wire WriteRxDataToMemory;
reg WriteRxDataToMemory_r ;
reg MasterWbTX;
reg MasterWbRX;
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
wire TxLengthEq0;
wire TxLengthLt4;
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
`ifdef ETH_WISHBONE_B3
`ifndef BURST_4BEAT
assign m_wb_bte_o = 2'b00; // Linear burst
`endif
`endif
assign m_wb_stb_o = m_wb_cyc_o;
always @ (posedge WB_CLK_I)
begin
WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
assign WB_DAT_O = ram_do;
// Generic synchronous single-port RAM interface
eth_spram_256x32
#(1) // Write enable width
bd_ram
(
.clk (WB_CLK_I),
.rst (Reset),
.ce (ram_ce),
.we (ram_we[0]),
.oe (ram_oe),
.addr (ram_addr),
.di (ram_di),
.dato (ram_do)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign ram_ce = 1'b1;
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) |
{4{(TxStatusWrite | RxStatusWrite)}};
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q &
(TxBDRead | TxPointerRead) | RxEn & RxEn_q &
(RxBDRead | RxPointerRead);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEn_needed <= 1'b0;
else
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
TxEn_needed <= 1'b1;
else
if(TxPointerRead & TxEn & TxEn_q)
TxEn_needed <= 1'b0;
end
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn <= 1'b1;
RxEn <= 1'b0;
TxEn <= 1'b0;
ram_addr <= 8'h0;
ram_di <= 32'h0;
BDRead <= 1'b0;
BDWrite <= 0;
end
else
begin
// Switching between three stages depends on enable signals
/* verilator lint_off CASEINCOMPLETE */ // JB
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
WbEn <= 1'b0;
RxEn <= 1'b1; // wb access stage and r_RxEn is enabled
TxEn <= 1'b0;
ram_addr <= {RxBDAddress, RxPointerRead};
ram_di <= RxBDDataIn;
end
5'b100_01 :
begin
WbEn <= 1'b0;
RxEn <= 1'b0;
TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but
// r_TxEn is enabled
ram_addr <= {TxBDAddress, TxPointerRead};
ram_di <= TxBDDataIn;
end
5'b010_00, 5'b010_10 :
begin
WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled
RxEn <= 1'b0;
TxEn <= 1'b0;
ram_addr <= WB_ADR_I[9:2];
ram_di <= WB_DAT_I;
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
BDRead <= (|BDCs) & ~WB_WE_I;
end
5'b010_01, 5'b010_11 :
begin
WbEn <= 1'b0;
RxEn <= 1'b0;
TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled
ram_addr <= {TxBDAddress, TxPointerRead};
ram_di <= TxBDDataIn;
end
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
begin
WbEn <= 1'b1; // TxEn access stage (we always go to wb
// access stage)
RxEn <= 1'b0;
TxEn <= 1'b0;
ram_addr <= WB_ADR_I[9:2];
ram_di <= WB_DAT_I;
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
BDRead <= (|BDCs) & ~WB_WE_I;
end
5'b100_00 :
begin
WbEn <= 1'b0; // WbEn access stage and there is no need
// for other stages. WbEn needs to be
// switched off for a bit
end
5'b000_00 :
begin
WbEn <= 1'b1; // Idle state. We go to WbEn access stage.
RxEn <= 1'b0;
TxEn <= 1'b0;
ram_addr <= WB_ADR_I[9:2];
ram_di <= WB_DAT_I;
BDWrite <= BDCs[3:0] & {4{WB_WE_I}};
BDRead <= (|BDCs) & ~WB_WE_I;
end
endcase //case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed})
/* verilator lint_on CASEINCOMPLETE */
end
end
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn_q <= 1'b0;
RxEn_q <= 1'b0;
TxEn_q <= 1'b0;
r_TxEn_q <= 1'b0;
r_RxEn_q <= 1'b0;
end
else
begin
WbEn_q <= WbEn;
RxEn_q <= RxEn;
TxEn_q <= TxEn;
r_TxEn_q <= r_TxEn;
r_RxEn_q <= r_RxEn;
end
end
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Flop <= 1'b0;
else
if(TxDone | TxAbort | TxRetry_q)
Flop <= 1'b0;
else
if(TxUsedData)
Flop <= ~Flop;
end
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDReady <= 1'b0;
else
if(TxEn & TxEn_q & TxBDRead)
// TxBDReady is sampled only once at the beginning.
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4);
else
// Only packets larger then 4 bytes are transmitted.
if(ResetTxBDReady)
TxBDReady <= 1'b0;
end
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) &
~BlockingTxBDRead & ~TxBDReady;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDRead <= 1'b1;
else
if(StartTxBDRead)
TxBDRead <= 1'b1;
else
if(TxBDReady)
TxBDRead <= 1'b0;
end
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerRead <= 1'b0;
else
if(StartTxPointerRead)
TxPointerRead <= 1'b1;
else
if(TxEn_q)
TxPointerRead <= 1'b0;
end
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared)&
TxEn & TxEn_q & ~BlockingTxStatusWrite;
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite <= 1'b0;
else
if(~TxDone_wb & ~TxAbort_wb)
BlockingTxStatusWrite <= 1'b0;
else
if(TxStatusWrite)
BlockingTxStatusWrite <= 1'b1;
end
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
reg BlockingTxStatusWrite_sync3;
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync1 <= 1'b0;
else
BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync2 <= 1'b0;
else
BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync3 <= 1'b0;
else
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2;
end
assign RstDeferLatched = BlockingTxStatusWrite_sync2 &
~BlockingTxStatusWrite_sync3;
// TxBDRead state is activated only once.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxBDRead <= 1'b0;
else
if(StartTxBDRead)
BlockingTxBDRead <= 1'b1;
else
if(~StartTxBDRead & ~TxBDReady)
BlockingTxBDRead <= 1'b0;
end
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time
// signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <= 4'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <= ram_do[14:11];
end
// Register WriteRxDataToMemory in Wishbone clock domain
// so it doesn't get out of sync with burst capability indication signals
always @(posedge WB_CLK_I or posedge Reset)
if (Reset)
WriteRxDataToMemory_r <= 0;
else
WriteRxDataToMemory_r <= WriteRxDataToMemory;
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxLength <= 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxLength <= ram_do[31:16];
else
if(MasterWbTX & m_wb_ack_i)
begin
if(TxLengthLt4)
TxLength <= 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <= TxLength - 16'd4; // Length is subtracted at
// the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <= TxLength - 16'd3; // Length is subtracted
// at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <= TxLength - 16'd2; // Length is subtracted
// at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <= TxLength - 16'd1; // Length is subtracted
// at the data request
end
end
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <= 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <= ram_do[31:16];
end
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
reg cyc_cleared;
reg IncrTxPointer;
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are
// latched because TxPointerMSB is only used for word-aligned accesses.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerMSB <= 30'h0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerMSB <= ram_do[31:2];
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
// TxPointer is word-aligned
TxPointerMSB <= TxPointerMSB + 1;
end
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are
// performed, valid data does not necesserly start at byte 0 (could be byte
// 0, 1, 2 or 3). This signals are used for proper selection of the start
// byte (TxData and TxByteCnt) are set by this two bits.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB[1:0] <= 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB[1:0] <= ram_do[1:0];
end
// Latching 2 MSB bits of the buffer descriptor.
// After the read access, TxLength needs to be decremented for the number of
// the valid bytes (1 to 4 bytes are valid in the first word). After the
// first read all bytes are valid so this two bits are reset to zero.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB_rst[1:0] <= 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB_rst[1:0] <= ram_do[1:0];
else
// After first access pointer is word alligned
if(MasterWbTX & m_wb_ack_i)
TxPointerLSB_rst[1:0] <= 0;
end
reg [3:0] RxByteSel;
wire MasterAccessFinished;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingIncrementTxPointer <= 0;
else
if(MasterAccessFinished)
BlockingIncrementTxPointer <= 0;
else
if(IncrTxPointer)
BlockingIncrementTxPointer <= 1'b1;
end
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromMemory <= 1'b0;
else
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
ReadTxDataFromMemory <= 1'b0;
else
if(SetReadTxDataFromMemory)
ReadTxDataFromMemory <= 1'b1;
end
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory &
~BlockReadTxDataFromMemory | (|tx_burst_cnt);
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockReadTxDataFromMemory <= 1'b0;
else
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX &
(~cyc_cleared) & (!(TxAbortPacket_NotCleared |
TxRetryPacket_NotCleared)))
BlockReadTxDataFromMemory <= 1'b1;
else
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket |
TxRetryPacket)
BlockReadTxDataFromMemory <= 1'b0;
end
`define TX_BURST_EN_CONDITION ({1'b0,txfifo_cnt}<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)))
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
MasterWbTX <= 1'b0;
MasterWbRX <= 1'b0;
m_wb_adr_o <= 30'h0;
m_wb_cyc_o <= 1'b0;
m_wb_we_o <= 1'b0;
m_wb_sel_o <= 4'h0;
cyc_cleared<= 1'b0;
tx_burst_cnt<= 0;
rx_burst_cnt<= 0;
IncrTxPointer<= 1'b0;
tx_burst_en<= 1'b1;
rx_burst_en<= 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <= 3'b0;
`ifdef BURST_4BEAT
m_wb_bte_o <= 2'b00;
`endif
`endif
end
else
begin
// Switching between two stages depends on enable signals
casez ({MasterWbTX,
MasterWbRX,
ReadTxDataFromMemory_2,
WriteRxDataToMemory_r,
MasterAccessFinished,
cyc_cleared,
tx_burst,
rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1?_10_1?, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1?_01_1?: // Clear (previously MW) and MRB needed
begin
MasterWbTX <= 1'b1; // tx burst
MasterWbRX <= 1'b0;
m_wb_cyc_o <= 1'b1;
m_wb_we_o <= 1'b0;
m_wb_sel_o <= 4'hf;
cyc_cleared<= 1'b0;
IncrTxPointer<= 1'b1;
tx_burst_cnt <= tx_burst_cnt+3'h1;
if(tx_burst_cnt==0)
m_wb_adr_o <= TxPointerMSB;
else
m_wb_adr_o <= m_wb_adr_o + 1;
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
tx_burst_en<= 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <= 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <= 3'b010;
`ifdef BURST_4BEAT
m_wb_bte_o <= 2'b01;
`endif
`endif
end
end // case: 8'b00_10_00_10,...
`ifdef ETH_RX_BURST_EN
8'b00_?1_00_?1, // Idle and MWB needed
8'b01_?1_10_?1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_?1_01_?1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <= 1'b0; // rx burst
MasterWbRX <= 1'b1;
m_wb_cyc_o <= 1'b1;
m_wb_we_o <= 1'b1;
m_wb_sel_o <= RxByteSel;
IncrTxPointer<= 1'b0;
cyc_cleared<= 1'b0;
rx_burst_cnt <= rx_burst_cnt+3'd1;
if(rx_burst_cnt==0)
m_wb_adr_o <= RxPointerMSB;
else
m_wb_adr_o <= m_wb_adr_o + 1;
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
rx_burst_en<= 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <= 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
`ifdef BURST_4BEAT
m_wb_cti_o <= 3'b010;
m_wb_bte_o <= 2'b01;
`endif
`endif
end
end // case: 8'b00_x1_00_x1,...
`endif // `ifdef ETH_RX_BURST_EN
8'b00_?1_00_?0 ,//idle and MW is needed (data write to rx buffer)
8'b01_?1_00_?0 :// Sometimes gets caught changing states - JB
begin
MasterWbTX <= 1'b0;
MasterWbRX <= !RxBufferEmpty;
m_wb_adr_o <= RxPointerMSB;
m_wb_cyc_o <= !RxBufferEmpty;
m_wb_we_o <= !RxBufferEmpty;
m_wb_sel_o <= RxByteSel;
IncrTxPointer<= 1'b0;
`ifdef ETH_WISHBONE_B3
`ifdef ETH_RX_BURST_EN
`ifdef BURST_4BEAT
if ((RxPointerMSB[3:2]==2'b00) & !RxBufferEmpty &
enough_data_in_rxfifo_for_burst & !m_wb_cyc_o)
// Added "& !_m_wb_cyc_o" here to stop burst signals
// going high during a transfer
begin
rx_burst_en<= 1'b1;
m_wb_cti_o <= 3'b010;
m_wb_bte_o <= 2'b01;
rx_burst_cnt<= 1;
end
`endif
`endif
`endif // `ifdef ETH_WISHBONE_B3
end
8'b00_10_00_00 : // idle and MR is needed (data read from tx
// buffer)
begin
MasterWbTX <= 1'b1;
MasterWbRX <= 1'b0;
m_wb_adr_o <= TxPointerMSB;
m_wb_cyc_o <= 1'b1;
m_wb_we_o <= 1'b0;
m_wb_sel_o <= 4'hf;
IncrTxPointer<= 1'b1;
`ifdef BURST_4BEAT
// Attempt ethernet bugfix, start bursts later
if ((TxPointerMSB[3:2]==2'b00) && `TX_BURST_EN_CONDITION)
begin
`ifdef TX_BURST_EN_VERBOSE
$display("(%t)(%m): %b enabling tx_burst_en",$time,
{MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
WriteRxDataToMemory,MasterAccessFinished,
cyc_cleared,tx_burst,rx_burst});
`endif
tx_burst_en<= 1'b1;
tx_burst_cnt <= 3'h1;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <= 3'b010;
m_wb_bte_o <= 2'b01;
`endif
end
`endif
end
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer)
8'b01_1?_01_0? :// MW and MR is needed (data read from tx
// buffer)
begin
MasterWbTX <= 1'b1; // Only switch to TX here
// when not end of RX
MasterWbRX <= 1'b0;
m_wb_adr_o <= TxPointerMSB;
m_wb_cyc_o <= 1'b1;
m_wb_we_o <= 1'b0;
m_wb_sel_o <= 4'hf;
cyc_cleared<= 1'b0;
IncrTxPointer<= 1'b1;
`ifdef BURST_4BEAT
if ((TxPointerMSB[3:2]==2'b00) & `TX_BURST_EN_CONDITION)
begin
`ifdef TX_BURST_EN_VERBOSE
$display("(%t)(%m): %b enabling tx_burst_en",$time,
{MasterWbTX,MasterWbRX,
ReadTxDataFromMemory_2,
WriteRxDataToMemory,
MasterAccessFinished,
cyc_cleared,
tx_burst,
rx_burst});
`endif
tx_burst_en<= 1'b1;
tx_burst_cnt <= 3'h1;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <= 3'b010;
m_wb_bte_o <= 2'b01;
`endif
end
`endif
end
8'b01_01_01_00,// MW and MW needed (data write to rx buffer)
8'b10_?1_01_?0 ://MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <= 1'b0;
MasterWbRX <= !RxBufferEmpty;
rx_burst_cnt<= 0;
m_wb_adr_o <= RxPointerMSB;
m_wb_cyc_o <= !RxBufferEmpty;
m_wb_we_o <= !RxBufferEmpty;
m_wb_sel_o <= RxByteSel;
`ifdef ETH_WISHBONE_B3
`ifdef ETH_RX_BURST_EN
`ifdef BURST_4BEAT
if ((RxPointerMSB[3:2]==2'b00) &
enough_data_in_rxfifo_for_burst & !RxBufferEmpty)
//enough_data_in_rxfifo_for_burst_plus1)
begin
rx_burst_en<= 1'b1;
m_wb_cti_o <= 3'b010;
m_wb_bte_o <= 2'b01;
rx_burst_cnt<= 1;
end
`endif
`endif // `ifdef ETH_RX_BURST_EN
`endif // `ifdef ETH_WISHBONE_B3
cyc_cleared<= 1'b0;
IncrTxPointer<= 1'b0;
end
8'b01_01_10_00,// MW and MW needed (cycle is cleared between
// previous and next access)
8'b01_1?_10_?0,// MW and MW or MR or MRB needed (cycle is
// cleared between previous and next access)
8'b10_10_10_00,// MR and MR needed (cycle is cleared between
// previous and next access)
8'b10_?1_10_0? :// MR and MR or MW or MWB (cycle is cleared
// between previous and next access)
begin
m_wb_cyc_o <= 1'b0;// whatever and master read or write is
// needed. We need to clear m_wb_cyc_o
// before next access is started
cyc_cleared<= 1'b1;
IncrTxPointer<= 1'b0;
tx_burst_cnt<= 0;
`ifdef BURST_4BEAT
// Caused a bug!
// if (TxPointerMSB[3:2]==2'b00)
//tx_burst_en<= `TX_BURST_EN_CONDITION;
// Set this to 0 here
tx_burst_en<= 0;
`endif
rx_burst_cnt<= 0;
`ifdef ETH_WISHBONE_B3
m_wb_bte_o <= 2'b00;
m_wb_cti_o <= 3'b0;
`endif
end
8'b??_00_10_00,// whatever and no master read or write is needed
// (ack or err comes finishing previous access)
8'b??_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <= 1'b0;
MasterWbRX <= 1'b0;
m_wb_cyc_o <= 1'b0;
cyc_cleared<= 1'b0;
IncrTxPointer<= 1'b0;
rx_burst_cnt<= 0;
m_wb_bte_o <= 2'b00;
m_wb_cti_o <= 3'b0;
end
8'b00_00_00_00: // whatever and no master read or write is
// needed (ack or err comes finishing previous
// access)
begin
tx_burst_cnt<= 0;
`ifdef BURST_4BEAT
// This caused tx_burst to remain set between
// transmits, and sometimes we would burst immediately
// and maybe get the wrong data because the offset of
// the buffer pointer wasn't 16-byte aligned.
//if (TxPointerMSB[3:2]==2'b00)
// tx_burst_en<= `TX_BURST_EN_CONDITION;
// Fix for transmit problems... maybe - jb
if(TxEn & TxEn_q & TxPointerRead & (ram_do[3:0]===4'h0))
begin
`ifdef TX_BURST_EN_VERBOSE
$display("(%t)(%m): %b enabling tx_burst_en",$time,
{MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2,
WriteRxDataToMemory,MasterAccessFinished,
cyc_cleared,tx_burst,rx_burst});
`endif
tx_burst_en<= `TX_BURST_EN_CONDITION;
end
else
tx_burst_en<= 0;
`endif
end
default: // Don't touch
begin
MasterWbTX <= MasterWbTX;
MasterWbRX <= MasterWbRX;
m_wb_cyc_o <= m_wb_cyc_o;
m_wb_sel_o <= m_wb_sel_o;
IncrTxPointer<= IncrTxPointer;
end
endcase
end
end
assign TxFifoClear = (TxAbortPacket | TxRetryPacket | StartTxPointerRead);
eth_fifo
#(
`ETH_TX_FIFO_DATA_WIDTH,
`ETH_TX_FIFO_DEPTH,
`ETH_TX_FIFO_CNT_WIDTH
)
tx_fifo
(
.data_in(m_wb_dat_i),
.data_out(TxData_wb),
.clk(WB_CLK_I),
.reset(Reset),
.write(MasterWbTX & m_wb_ack_i),
.read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
.clear(TxFifoClear),
.full(TxBufferFull),
.almost_full(TxBufferAlmostFull),
.almost_empty(TxBufferAlmostEmpty),
.empty(TxBufferEmpty),
.cnt(txfifo_cnt)
);
// Start: Generation of the TxStartFrm_wb which is then synchronized to the
// MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_wb <= 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferAlmostFull | TxBufferFull| TxLengthEq0))
TxStartFrm_wb <= 1'b1;
else
if(TxStartFrm_syncb2)
TxStartFrm_wb <= 1'b0;
end
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's
// blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
StartOccured <= 1'b0;
else
if(TxStartFrm_wb)
StartOccured <= 1'b1;
else
if(ResetTxBDReady)
StartOccured <= 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync1 <= 1'b0;
else
TxStartFrm_sync1 <= TxStartFrm_wb;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync2 <= 1'b0;
else
TxStartFrm_sync2 <= TxStartFrm_sync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb1 <= 1'b0;
else
TxStartFrm_syncb1 <= TxStartFrm_sync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb2 <= 1'b0;
else
TxStartFrm_syncb2 <= TxStartFrm_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm <= 1'b0;
else
if(TxStartFrm_sync2)
TxStartFrm <= 1'b1;
else
if(TxUsedData_q | ~TxStartFrm_sync2 &
(TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
TxStartFrm <= 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the
// MTxClk
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEndFrm_wb <= 1'b0;
else
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
TxEndFrm_wb <= 1'b1;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxEndFrm_wb <= 1'b0;
end
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
reg LatchValidBytes;
reg LatchValidBytes_q;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes <= 1'b0;
else
if(TxLengthLt4 & TxBDReady)
LatchValidBytes <= 1'b1;
else
LatchValidBytes <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes_q <= 1'b0;
else
LatchValidBytes_q <= LatchValidBytes;
end
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxValidBytesLatched <= 2'h0;
else
if(LatchValidBytes & ~LatchValidBytes_q)
TxValidBytesLatched <= TxValidBytes;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxValidBytesLatched <= 2'h0;
end
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13];
assign PerPacketPad = TxStatus[12];
assign PerPacketCrcEn = TxStatus[11];
assign RxIRQEn = RxStatus[14];
assign WrapRxStatusBit = RxStatus[13];
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
{7{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address)
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDAddress <= 7'h0;
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <= 7'h0;
else if (TxStatusWrite)
TxBDAddress <= TempTxBDAddress;
end
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <= 7'h0;
else if(r_RxEn & (~r_RxEn_q))
RxBDAddress <= r_TxBDNum[6:0];
else if(RxStatusWrite)
RxBDAddress <= TempRxBDAddress;
end
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0],
RetryLimit, LateCollLatched, DeferLatched,
CarrierSenseLost};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0,
RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0,
TxStatusInLatched};
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
TxAbort_q <= 1'b0;
TxRetry_q <= 1'b0;
TxUsedData_q <= 1'b0;
end
else
begin
TxAbort_q <= TxAbort;
TxRetry_q <= TxRetry;
TxUsedData_q <= TxUsedData;
end
end
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
TxDone_wb_q <= 1'b0;
TxAbort_wb_q <= 1'b0;
TxRetry_wb_q <= 1'b0;
end
else
begin
TxDone_wb_q <= TxDone_wb;
TxAbort_wb_q <= TxAbort_wb;
TxRetry_wb_q <= TxRetry_wb;
end
end
reg TxAbortPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket <= 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished &
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) &
(~TxAbortPacketBlocked))
TxAbortPacket <= 1'b1;
else
TxAbortPacket <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket_NotCleared <= 1'b0;
else
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
TxAbortPacket_NotCleared <= 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX &
MasterAccessFinished & (~TxAbortPacketBlocked) | TxAbort_wb &
(~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket_NotCleared <= 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacketBlocked <= 1'b0;
else
if(!TxAbort_wb & TxAbort_wb_q)
TxAbortPacketBlocked <= 1'b0;
else
if(TxAbortPacket)
TxAbortPacketBlocked <= 1'b1;
end
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket <= 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
!TxRetryPacketBlocked)
TxRetryPacket <= 1'b1;
else
TxRetryPacket <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket_NotCleared <= 1'b0;
else
if(StartTxBDRead)
TxRetryPacket_NotCleared <= 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX &
!TxRetryPacketBlocked)
TxRetryPacket_NotCleared <= 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacketBlocked <= 1'b0;
else
if(!TxRetry_wb & TxRetry_wb_q)
TxRetryPacketBlocked <= 1'b0;
else
if(TxRetryPacket)
TxRetryPacketBlocked <= 1'b1;
end
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket <= 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished &
!TxDonePacketBlocked | TxDone_wb & !MasterWbTX &
!TxDonePacketBlocked)
TxDonePacket <= 1'b1;
else
TxDonePacket <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket_NotCleared <= 1'b0;
else
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
TxDonePacket_NotCleared <= 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished
& (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX
& (~TxDonePacketBlocked))
TxDonePacket_NotCleared <= 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacketBlocked <= 1'b0;
else
if(!TxDone_wb & TxDone_wb_q)
TxDonePacketBlocked <= 1'b0;
else
if(TxDonePacket)
TxDonePacketBlocked <= 1'b1;
end
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LastWord <= 1'b0;
else
if((TxEndFrm | TxAbort | TxRetry) & Flop)
LastWord <= 1'b0;
else
if(TxUsedData & Flop & TxByteCnt == 2'h3)
LastWord <= TxEndFrm_wb;
end
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxEndFrm <= 1'b0;
else
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
TxEndFrm <= 1'b0;
else
if(Flop & LastWord)
begin
case (TxValidBytesLatched) // synopsys parallel_case
1 : TxEndFrm <= TxByteCnt == 2'h0;
2 : TxEndFrm <= TxByteCnt == 2'h1;
3 : TxEndFrm <= TxByteCnt == 2'h2;
0 : TxEndFrm <= TxByteCnt == 2'h3;
default : TxEndFrm <= 1'b0;
endcase
end
end
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxData <= 0;
else
if(TxStartFrm_sync2 & ~TxStartFrm)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering
2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering
2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering
endcase
else
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
TxData <= TxData_wb[31:24];// Big Endian Byte Ordering
else
if(TxUsedData & Flop)
begin
case(TxByteCnt) // synopsys parallel_case
// Big Endian Byte Ordering
0 : TxData <= TxDataLatched[31:24];
1 : TxData <= TxDataLatched[23:16];
2 : TxData <= TxDataLatched[15:8];
3 : TxData <= TxDataLatched[7:0];
endcase
end
end
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDataLatched[31:0] <= 32'h0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop &
TxByteCnt == 2'h0)
TxDataLatched[31:0] <= TxData_wb[31:0];
end
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun_wb <= 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <= 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <= 1'b1;
end
reg TxUnderRun_sync1;
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun_sync1 <= 1'b0;
else
if(TxUnderRun_wb)
TxUnderRun_sync1 <= 1'b1;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun_sync1 <= 1'b0;
end
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <= 1'b0;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun <= 1'b0;
else
if(TxUnderRun_sync1)
TxUnderRun <= 1'b1;
end
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxByteCnt <= 2'h0;
else
if(TxAbort_q | TxRetry_q)
TxByteCnt <= 2'h0;
else
if(TxStartFrm & ~TxUsedData)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxByteCnt <= 2'h1;
2'h1 : TxByteCnt <= 2'h2;
2'h2 : TxByteCnt <= 2'h3;
2'h3 : TxByteCnt <= 2'h0;
endcase
else
if(TxUsedData & Flop)
TxByteCnt <= TxByteCnt + 1'b1;
end
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
reg ReadTxDataFromFifo_syncb3;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_tck <= 1'b0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop &
TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop &
TxByteCnt == 2'h0)
ReadTxDataFromFifo_tck <= 1'b1;
else
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
ReadTxDataFromFifo_tck <= 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync1 <= 1'b0;
else
ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync2 <= 1'b0;
else
ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb1 <= 1'b0;
else
ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb2 <= 1'b0;
else
ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb3 <= 1'b0;
else
ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync3 <= 1'b0;
else
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2;
end
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 &
~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization
// to the WB_CLK_I
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetrySync1 <= 1'b0;
else
TxRetrySync1 <= TxRetry;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetry_wb <= 1'b0;
else
TxRetry_wb <= TxRetrySync1;
end
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDoneSync1 <= 1'b0;
else
TxDoneSync1 <= TxDone;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDone_wb <= 1'b0;
else
TxDone_wb <= TxDoneSync1;
end
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortSync1 <= 1'b0;
else
TxAbortSync1 <= TxAbort;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbort_wb <= 1'b0;
else
TxAbort_wb <= TxAbortSync1;
end
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 |
r_RxEn & ~r_RxEn_q;
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDRead <= 1'b0;
else
if(StartRxBDRead)
RxBDRead <= 1'b1;
else
if(RxBDReady)
RxBDRead <= 1'b0;
end
// Reading of the next receive buffer descriptor starts after reception
// status is written to the previous one.
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDReady <= 1'b0;
else
if(RxPointerRead)
RxBDReady <= 1'b0;
else
if(RxEn & RxEn_q & RxBDRead)
// RxBDReady is sampled only once at the beginning
RxBDReady <= ram_do[15];
end // always @ (posedge WB_CLK_I or posedge Reset)
// Indicate we just read the RX buffer descriptor and that RxBDReady is
// valid.
reg rx_just_read_bd;
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_just_read_bd <= 0;
else if (rx_just_read_bd)
rx_just_read_bd <= 0;
else
rx_just_read_bd <= (RxEn & RxEn_q & RxBDRead);
// Signal to indicate we've checked and the RxBD we want to use is not free
reg rx_waiting_for_bd_to_become_free/*syn_allow_retiming=0; syn_keep=1; syn_preserve=1*/;
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_waiting_for_bd_to_become_free <= 0;
else if (rx_just_read_bd & !RxBDReady)
// Assert if we read the BD and it's not cool
rx_waiting_for_bd_to_become_free <= 1;
else if (RxBDOK)
rx_waiting_for_bd_to_become_free <= 0;
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time
// signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatus <= 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatus <= ram_do[14:13];
end
// RxBDOK generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDOK <= 1'b0;
else
if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 |
~r_RxEn & r_RxEn_q)
RxBDOK <= 1'b0;
else
if(RxBDReady)
RxBDOK <= 1'b1;
end
// Reading Rx BD pointer
assign StartRxPointerRead = RxBDRead & RxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerRead <= 1'b0;
else
if(StartRxPointerRead)
RxPointerRead <= 1'b1;
else
if(RxEn & RxEn_q)
RxPointerRead <= 1'b0;
end
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerMSB <= 30'h0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerMSB <= ram_do[31:2];
else
if(MasterWbRX & m_wb_ack_i)
// Word access (always word access. m_wb_sel_o are used for
// selecting bytes)
RxPointerMSB <= RxPointerMSB + 1;
end
//Latching last addresses from buffer descriptor (used as byte-half-word
// indicator);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerLSB_rst[1:0] <= 0;
else
if(MasterWbRX & m_wb_ack_i)
// After first write all RxByteSel are active
RxPointerLSB_rst[1:0] <= 0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerLSB_rst[1:0] <= ram_do[1:0];
end
always @ (RxPointerLSB_rst)
begin
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
2'h0 : RxByteSel[3:0] = 4'hf;
2'h1 : RxByteSel[3:0] = 4'h7;
2'h2 : RxByteSel[3:0] = 4'h3;
2'h3 : RxByteSel[3:0] = 4'h1;
endcase
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxEn_needed <= 1'b0;
else
if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q)
RxEn_needed <= 1'b1;
else
if(RxPointerRead & RxEn & RxEn_q)
RxEn_needed <= 1'b0;
end
// Reception status is written back to the buffer descriptor after the end
// of frame is detected.
assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q;
reg RxEnableWindow;
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LastByteIn <= 1'b0;
else
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
LastByteIn <= 1'b0;
else
if(RxValid /*& RxReady*/& RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
LastByteIn <= 1'b1;
end
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) &
RxEnableWindow;
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftWillEnd <= 1'b0;
else
if(ShiftEnded_rck | RxAbort)
ShiftWillEnd <= 1'b0;
else
if(StartShiftWillEnd)
ShiftWillEnd <= 1'b1;
end
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxByteCnt <= 2'h0;
else
if(ShiftEnded_rck | RxAbort)
RxByteCnt <= 2'h0;
else
if(RxValid & RxStartFrm /*& RxReady*/)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxByteCnt <= 2'h1;
2'h1 : RxByteCnt <= 2'h2;
2'h2 : RxByteCnt <= 2'h3;
2'h3 : RxByteCnt <= 2'h0;
endcase
else
if(RxValid & RxEnableWindow /*& RxReady*/ | LastByteIn)
RxByteCnt <= RxByteCnt + 1;
end
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxValidBytes <= 2'h1;
else
if(RxValid & RxStartFrm)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxValidBytes <= 2'h1;
2'h1 : RxValidBytes <= 2'h2;
2'h2 : RxValidBytes <= 2'h3;
2'h3 : RxValidBytes <= 2'h0;
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <= RxValidBytes + 1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched1 <= 24'h0;
else
if(RxValid /*& RxReady*/ & ~LastByteIn)
if(RxStartFrm)
begin
case(RxPointerLSB_rst) // synopsys parallel_case
// Big Endian Byte Ordering
2'h0: RxDataLatched1[31:24] <= RxData;
2'h1: RxDataLatched1[23:16] <= RxData;
2'h2: RxDataLatched1[15:8] <= RxData;
2'h3: RxDataLatched1 <= RxDataLatched1;
endcase
end
else if (RxEnableWindow)
begin
case(RxByteCnt) // synopsys parallel_case
// Big Endian Byte Ordering
2'h0: RxDataLatched1[31:24] <= RxData;
2'h1: RxDataLatched1[23:16] <= RxData;
2'h2: RxDataLatched1[15:8] <= RxData;
2'h3: RxDataLatched1 <= RxDataLatched1;
endcase
end
end
wire SetWriteRxDataToFifo;
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched2 <= 32'h0;
else
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
// Big Endian Byte Ordering
RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
else
if(SetWriteRxDataToFifo & ShiftWillEnd)
case(RxValidBytes) // synopsys parallel_case
// Big Endian Byte Ordering
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData};
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0};
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0};
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0};
endcase
end
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
reg WriteRxDataToFifoSync3;
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & ~RxStartFrm &
RxEnableWindow & (&RxByteCnt))
/*| (RxValid & RxStartFrm &
(&RxPointerLSB_rst)) */
|(ShiftWillEnd & LastByteIn & (&RxByteCnt));
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
WriteRxDataToFifo <= 1'b0;
else
if(SetWriteRxDataToFifo & ~RxAbort)
WriteRxDataToFifo <= 1'b1;
else
if(WriteRxDataToFifoSync2 | RxAbort)
WriteRxDataToFifo <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync1 <= 1'b0;
else
if(WriteRxDataToFifo)
WriteRxDataToFifoSync1 <= 1'b1;
else
WriteRxDataToFifoSync1 <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync2 <= 1'b0;
else
WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync3 <= 1'b0;
else
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2;
end
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 &
~WriteRxDataToFifoSync3;
// Receive fifo selection register - JB
reg [3:0] rx_shift_ended_wb_shr;
reg rx_ethside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
reg rx_wbside_fifo_sel /* synthesis syn_allow_retiming=0; syn_noprune=1; syn_keep=1 */;
// Shift in this - our detection of end of data RX
always @(posedge WB_CLK_I)
rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0],
ShiftEndedSync1 & ~ShiftEndedSync2};
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_ethside_fifo_sel <= 0;
else
if(rx_shift_ended_wb_shr[3:2] == 2'b01)
// Switch over whenever we've finished receiving last frame's data
rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel;
// Wishbone side looks at other FIFO when we write back the status of this
// received frame
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_wbside_fifo_sel <= 0;
else
if(rx_wb_writeback_finished & RxEn & RxEn_q)
// Switch over whenever we've finished receiving last frame's data
rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel;
reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxStartFrm <= 0;
else
if(RxStartFrm & ~SyncRxStartFrm_q)
LatchedRxStartFrm <= 1;
else
if(SyncRxStartFrm_q)
LatchedRxStartFrm <= 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm <= 0;
else
if(LatchedRxStartFrm)
SyncRxStartFrm <= 1;
else
SyncRxStartFrm <= 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q <= 0;
else
SyncRxStartFrm_q <= SyncRxStartFrm;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q2 <= 0;
else
SyncRxStartFrm_q2 <= SyncRxStartFrm_q;
end
wire rx_startfrm_wb;
assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
assign RxFifoReset = rx_startfrm_wb;
wire [31:0] rx_fifo0_data_out;
wire rx_fifo0_write;
wire rx_fifo0_read;
wire rx_fifo0_clear;
wire rx_fifo0_full;
wire rx_fifo0_afull;
wire rx_fifo0_empty;
wire rx_fifo0_aempty;
wire [31:0] rx_fifo1_data_out;
wire rx_fifo1_write;
wire rx_fifo1_read;
wire rx_fifo1_clear;
wire rx_fifo1_full;
wire rx_fifo1_afull;
wire rx_fifo1_empty;
wire rx_fifo1_aempty;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt;
// RX FIFO buffer 0 controls
assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
~rx_fifo0_full;
assign rx_fifo0_read = (!rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
~rx_fifo0_empty;
assign rx_fifo0_clear = (!rx_ethside_fifo_sel) & RxFifoReset;
// RX FIFO buffer 1 controls
assign rx_fifo1_write = (rx_ethside_fifo_sel) & WriteRxDataToFifo_wb &
~rx_fifo1_full;
assign rx_fifo1_read = (rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i &
~rx_fifo1_empty;
assign rx_fifo1_clear = (rx_ethside_fifo_sel) & RxFifoReset;
eth_fifo #(
`ETH_RX_FIFO_DATA_WIDTH,
`ETH_RX_FIFO_DEPTH,
`ETH_RX_FIFO_CNT_WIDTH
)
rx_fifo0 (
.clk (WB_CLK_I ),
.reset (Reset ),
// Inputs
.data_in (RxDataLatched2 ),
.write (rx_fifo0_write ),
.read (rx_fifo0_read ),
.clear (rx_fifo0_clear ),
// Outputs
.data_out (rx_fifo0_data_out),
.full (rx_fifo0_full ),
.almost_full (),
.almost_empty (rx_fifo0_aempty ),
.empty (rx_fifo0_empty ),
.cnt (rx_fifo0_cnt )
);
eth_fifo #(
`ETH_RX_FIFO_DATA_WIDTH,
`ETH_RX_FIFO_DEPTH,
`ETH_RX_FIFO_CNT_WIDTH
)
rx_fifo1 (
.clk (WB_CLK_I ),
.reset (Reset ),
// Inputs
.data_in (RxDataLatched2 ),
.write (rx_fifo1_write ),
.read (rx_fifo1_read ),
.clear (rx_fifo1_clear ),
// Outputs
.data_out (rx_fifo1_data_out),
.full (rx_fifo1_full ),
.almost_full (),
.almost_empty (rx_fifo1_aempty ),
.empty (rx_fifo1_empty ),
.cnt (rx_fifo1_cnt )
);
assign m_wb_dat_o = rx_wbside_fifo_sel ?
rx_fifo1_data_out : rx_fifo0_data_out;
assign rxfifo_cnt = rx_wbside_fifo_sel ?
rx_fifo1_cnt : rx_fifo0_cnt;
assign RxBufferAlmostEmpty = rx_wbside_fifo_sel ?
rx_fifo1_aempty : rx_fifo0_aempty;
assign RxBufferEmpty = rx_wbside_fifo_sel ?
rx_fifo1_empty : rx_fifo0_empty;
assign RxBufferFull = rx_wbside_fifo_sel ?
rx_fifo1_full : rx_fifo0_full;
wire write_rx_data_to_memory_wait;
assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead;
wire write_rx_data_to_memory_go;
`ifdef ETH_RX_BURST_EN
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH);
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1);
// While receiving, don't flog the bus too hard, only write out when
// we can burst. But when finishing keep going until we've emptied the fifo
assign write_rx_data_to_memory_go
= RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ?
(rxfifo_cnt>(`ETH_BURST_LENGTH) + 2) | (|rx_burst_cnt) : ~RxBufferEmpty;
`else
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
assign write_rx_data_to_memory_go = ~RxBufferEmpty;
`endif // !`ifdef ETH_RX_BURST_EN
assign WriteRxDataToMemory = write_rx_data_to_memory_go &
!write_rx_data_to_memory_wait;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEnded_rck <= 1'b0;
else
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
ShiftEnded_rck <= 1'b1;
else
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
ShiftEnded_rck <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync1 <= 1'b0;
else
ShiftEndedSync1 <= ShiftEnded_rck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync2 <= 1'b0;
else
ShiftEndedSync2 <= ShiftEndedSync1;
end
// indicate end of wishbone RX is coming up
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_wb_last_writes <= 1'b0;
else if (!rx_wb_last_writes)
rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2;
else if (rx_wb_writeback_finished & RxEn & RxEn_q)
rx_wb_last_writes <= 0;
// Pulse indicating last of RX data has been written out
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
rx_wb_writeback_finished <= 0;
else if (rx_wb_writeback_finished & RxEn & RxEn_q)
rx_wb_writeback_finished <= 0;
else
rx_wb_writeback_finished <= rx_wb_last_writes & RxBufferEmpty &
!WriteRxDataToFifo_wb;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c1 <= 1'b0;
else
ShiftEndedSync_c1 <= ShiftEndedSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c2 <= 1'b0;
else
ShiftEndedSync_c2 <= ShiftEndedSync_c1;
end
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxEnableWindow <= 1'b0;
else
if(RxStartFrm)
RxEnableWindow <= 1'b1;
else
if(RxEndFrm | RxAbort)
RxEnableWindow <= 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync1 <= 1'b0;
else
RxAbortSync1 <= RxAbortLatched;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync2 <= 1'b0;
else
RxAbortSync2 <= RxAbortSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync3 <= 1'b0;
else
RxAbortSync3 <= RxAbortSync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync4 <= 1'b0;
else
RxAbortSync4 <= RxAbortSync3;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb1 <= 1'b0;
else
RxAbortSyncb1 <= RxAbortSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb2 <= 1'b0;
else
RxAbortSyncb2 <= RxAbortSyncb1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortLatched <= 1'b0;
else
if(RxAbortSyncb2)
RxAbortLatched <= 1'b0;
else
if(RxAbort)
RxAbortLatched <= 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxLength[15:0] <= 16'h0;
else
if(LoadRxStatus)
LatchedRxLength[15:0] <= RxLength[15:0];
end
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <= 'h0;
else
if(LoadRxStatus)
RxStatusInLatched <= RxStatusIn;
end
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxOverrun <= 1'b0;
else
if(RxStatusWrite)
RxOverrun <= 1'b0;
else
if(RxBufferFull & WriteRxDataToFifo_wb)
RxOverrun <= 1'b1;
end
wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
wire RxError;
// ShortFrame (RxStatusInLatched[2]) can not set an error because short
// frames are aborted when signal r_RecSmall is set to 0 in MODER register.
// AddressMiss is identifying that a frame was received because of the
// promiscous mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
reg RxStatusWriteLatched;
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb2;
// Latching and synchronizing RxStatusWrite signal. This signal is used for
// clearing the ReceivedPauseFrm signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <= 1'b0;
else
if(RxStatusWriteLatched_syncb2)
RxStatusWriteLatched <= 1'b0;
else
if(RxStatusWrite)
RxStatusWriteLatched <= 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_sync1 <= 1'b0;
RxStatusWriteLatched_sync2 <= 1'b0;
end
else
begin
RxStatusWriteLatched_sync1 <= RxStatusWriteLatched;
RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1;
end
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_syncb1 <= 1'b0;
RxStatusWriteLatched_syncb2 <= 1'b0;
end
else
begin
RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2;
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1;
end
end
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxB_IRQ <= 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxB_IRQ <= ~TxError;
else
TxB_IRQ <= 1'b0;
end
// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxE_IRQ <= 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxE_IRQ <= TxError;
else
TxE_IRQ <= 1'b0;
end
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxB_IRQ <= 1'b0;
else
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood &
(~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxB_IRQ <= (~RxError);
else
RxB_IRQ <= 1'b0;
end
// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxE_IRQ <= 1'b0;
else
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm
& r_PassAll & (~r_RxFlow)))
RxE_IRQ <= RxError;
else
RxE_IRQ <= 1'b0;
end
// Set this high when we started receiving another packet while the wishbone
// side was still writing out the last one. This makes sure we check at the
// right time if the next buffer descriptor is free.
reg rxstartfrm_occurred;
always @ (posedge WB_CLK_I)
if (Reset)
rxstartfrm_occurred <= 0;
else if (rx_just_read_bd)
rxstartfrm_occurred <= 0;
else if (((rx_ethside_fifo_sel != rx_wbside_fifo_sel) | StartRxBDRead |
RxBDRead) & rx_startfrm_wb)
rxstartfrm_occurred <= 1;
reg busy_wb;
always @ (posedge WB_CLK_I or posedge Reset)
if(Reset)
busy_wb <= 0;
else if (busy_wb)
busy_wb <= 0;
else if
// Indicate busy if either:
// a) RX is idle and we get a start frame and current BD indicates not
// ready.
// b) RX is already receiving another packet and we got a startframe,
// indicated by rx_startfrm_occurred, and we then read the BD and
// it says it's not ready.
// This actually may not work since it's in the MII RX clock domain.
((rx_ethside_fifo_sel == rx_wbside_fifo_sel) &
((rxstartfrm_occurred & rx_just_read_bd & ~RxBDReady) |
(!rxstartfrm_occurred & !StartRxBDRead & !RxBDRead & rx_startfrm_wb &
rx_waiting_for_bd_to_become_free))
)
busy_wb <= 1;
assign Busy_IRQ = busy_wb;
always @(posedge Busy_IRQ)
$display("(%t)(%m) Ethernet MAC BUSY signal asserted", $time);
// Assign the debug output
`ifdef WISHBONE_DEBUG
// Top byte, burst progress counters
assign dbg_dat0[31] = 0;
assign dbg_dat0[30:28] = rx_burst_cnt;
assign dbg_dat0[27] = 0;
assign dbg_dat0[26:24] = tx_burst_cnt;
// Third byte
assign dbg_dat0[23] = 0;
assign dbg_dat0[22] = 0;
assign dbg_dat0[21] = rx_burst;
assign dbg_dat0[20] = rx_burst_en;
assign dbg_dat0[19] = 0;
assign dbg_dat0[18] = 0;
assign dbg_dat0[17] = tx_burst;
assign dbg_dat0[16] = tx_burst_en;
// Second byte - TxBDAddress - or TX BD address pointer
assign dbg_dat0[15:8] = { 1'b0, TxBDAddress};
// Bottom byte - FSM controlling vector
assign dbg_dat0[7:0] = {MasterWbTX,MasterWbRX,
ReadTxDataFromMemory_2,WriteRxDataToMemory,
MasterAccessFinished,cyc_cleared,
tx_burst,rx_burst};
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EDFXBP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__EDFXBP_BEHAVIORAL_PP_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__edfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire CLK_delayed;
wire mux_out ;
wire awake ;
wire cond0 ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( DE_delayed === 1'b1 ) );
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EDFXBP_BEHAVIORAL_PP_V |
/* Model for xilinx async fifo*/
module fifo_async_104x32
(/*AUTOARG*/
// Outputs
full, prog_full, dout, empty, valid,
// Inputs
rst, wr_clk, rd_clk, wr_en, din, rd_en
);
parameter DW = 104;//104 wide
parameter DEPTH = 16; //
// almost_full,
// wr_rst, rd_rst,
//##########
//# RESET/CLOCK
//##########
input wr_rst; //asynchronous reset
input rd_rst; //asynchronous reset
input wr_clk; //write clock
input rd_clk; //read clock
//##########
//# FIFO WRITE
//##########
input wr_en;
input [DW-1:0] din;
output full;
output prog_full;
output almost_full;
//###########
//# FIFO READ
//###########
input rd_en;
output [DW-1:0] dout;
output empty;
output valid;
input rst;
defparam fifo_model.DW=104;
defparam fifo_model.DEPTH=32;
fifo_async_model fifo_model (/*AUTOINST*/
// Outputs
.full (full),
.prog_full (prog_full),
//.almost_full (almost_full),
.dout (dout[DW-1:0]),
.empty (empty),
.valid (valid),
// Inputs
.rst (rst),
//.wr_rst (wr_rst),
//.rd_rst (rd_rst),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
endmodule // fifo_async
// Local Variables:
// verilog-library-directories:("." "../../memory/hdl")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211A_FUNCTIONAL_PP_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_t
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_t.v,v 1.6 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: ent_t.v,v $
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_t
//
// No user `defines in this module
module ent_t
//
// Generated Module inst_t
//
(
sig_i_a,
sig_i_a2,
sig_i_ae,
sig_o_a,
sig_o_a2,
sig_o_ae
);
// Generated Module Inputs:
input sig_i_a;
input sig_i_a2;
input [6:0] sig_i_ae;
// Generated Module Outputs:
output sig_o_a;
output sig_o_a2;
output [7:0] sig_o_ae;
// Generated Wires:
wire sig_i_a;
wire sig_i_a2;
wire [6:0] sig_i_ae;
wire sig_o_a;
wire sig_o_a2;
wire [7:0] sig_o_ae;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire sig_01;
wire sig_03;
wire sig_04;
wire [3:0] sig_05;
wire [3:0] sig_06;
wire [5:0] sig_07;
wire [8:2] sig_08;
// __I_OUT_OPEN wire [4:0] sig_13; // __W_BAD_BRANCH
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
ent_a inst_a (
.p_mix_sig_01_go(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.p_mix_sig_03_go(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.p_mix_sig_04_gi(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.p_mix_sig_05_2_1_go(sig_05[2:1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.p_mix_sig_06_gi(sig_06), // Conflicting definition (X2)
.p_mix_sig_i_ae_gi(sig_i_ae), // Input Bus
.p_mix_sig_o_ae_go(sig_o_ae), // Output Bus
.port_i_a(sig_i_a), // Input Port
.port_o_a(sig_o_a), // Output Port
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08), // VHDL intermediate needed (port name)
.sig_13(), // Create internal signal name
.sig_i_a2(sig_i_a2), // Input Port
.sig_o_a2(sig_o_a2) // Output Port
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
ent_b inst_b (
.port_b_1(sig_01), // Use internally test1Will create p_mix_sig_1_go port
.port_b_3(sig_03), // Interhierachy link, will create p_mix_sig_3_go
.port_b_4(sig_04), // Interhierachy link, will create p_mix_sig_4_gi
.port_b_5_1(sig_05[2]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_5_2(sig_05[1]), // Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
.port_b_6i(sig_06), // Conflicting definition (X2)
.port_b_6o(sig_06), // Conflicting definition (X2)
.sig_07(sig_07), // Conflicting definition, IN false!
.sig_08(sig_08) // VHDL intermediate needed (port name)
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of ent_t
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFINV_16_V
`define SKY130_FD_SC_LP__BUFINV_16_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_16 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufinv_16 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFINV_16_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_2_V
`define SKY130_FD_SC_LP__NOR2_2_V
/**
* nor2: 2-input NOR.
*
* Verilog wrapper for nor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_2_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:03:27 10/03/2014
// Design Name:
// Module Name: topmodule
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module divider(
reset,
out,
clk
);
output out;
input clk;
input reset;
parameter divisor1 = 5;
parameter divisor2 = 2;
reg[31:0] cnt1;
reg result;
wire EN;
wire compare1,compare2;
// counter
always@(posedge clk or negedge reset)
begin
if(reset == 0)
cnt1 <= 0;
else if(cnt1 == divisor1)
cnt1 <= 1;
else
cnt1 <= cnt1 + 1;
end
//comparatorA for posedge
assign compare1 = (cnt1 == 5) ? 1 : 0;
//comparatorB for nevedge
assign compare2 = (cnt1 == divisor2) ? 1 : 0;
assign EN = compare1 | compare2;
// D-type flip-flop output
// posedge clk && (compareA || compareB) ???
always@(posedge clk or negedge reset)
begin
if(reset == 0)
result <= 0;
else if(EN)
result <= !result;
// do nothing
end
assign out = result;
endmodule
|
/*
-- ============================================================================
-- FILE NAME : mem_ctrl.v
-- DESCRIPTION : ¥á¥â¥ê¥¢¥¯¥»¥¹ÖÆÓù¥æ¥Ë¥Ã¥È
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
`include "bus.h"
/********** ¥â¥¸¥å©`¥ë **********/
module mem_ctrl (
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire [`MemOpBus] ex_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] ex_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`WordDataBus] ex_out, // IÀí½Y¹û
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] addr, // ¥¢¥É¥ì¥¹
output reg as_, // ¥¢¥É¥ì¥¹Óп
output reg rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û **********/
output reg [`WordDataBus] out , // ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û
output reg miss_align // ¥ß¥¹¥¢¥é¥¤¥ó
);
/********** ÄÚ²¿ÐźŠ**********/
wire [`ByteOffsetBus] offset; // ¥ª¥Õ¥»¥Ã¥È
/********** ³öÁ¦¤Î¥¢¥µ¥¤¥ó **********/
assign wr_data = ex_mem_wr_data; // ø¤Þz¤ß¥Ç©`¥¿
assign addr = ex_out[`WordAddrLoc]; // ¥¢¥É¥ì¥¹
assign offset = ex_out[`ByteOffsetLoc]; // ¥ª¥Õ¥»¥Ã¥È
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¤ÎÖÆÓù **********/
always @(*) begin
/* ¥Ç¥Õ¥©¥ë¥È */
miss_align = `DISABLE;
out = `WORD_DATA_W'h0;
as_ = `DISABLE_;
rw = `READ;
/* ¥á¥â¥ê¥¢¥¯¥»¥¹ */
if (ex_en == `ENABLE) begin
case (ex_mem_op)
`MEM_OP_LDW : begin // ¥ï©`¥ÉÕi¤ß³ö¤·
/* ¥Ð¥¤¥È¥ª¥Õ¥»¥Ã¥È¤Î¥Á¥§¥Ã¥¯ */
if (offset == `BYTE_OFFSET_WORD) begin // ¥¢¥é¥¤¥ó
out = rd_data;
as_ = `ENABLE_;
end else begin // ¥ß¥¹¥¢¥é¥¤¥ó
miss_align = `ENABLE;
end
end
`MEM_OP_STW : begin // ¥ï©`¥Éø¤Þz¤ß
/* ¥Ð¥¤¥È¥ª¥Õ¥»¥Ã¥È¤Î¥Á¥§¥Ã¥¯ */
if (offset == `BYTE_OFFSET_WORD) begin // ¥¢¥é¥¤¥ó
rw = `WRITE;
as_ = `ENABLE_;
end else begin // ¥ß¥¹¥¢¥é¥¤¥ó
miss_align = `ENABLE;
end
end
default : begin // ¥á¥â¥ê¥¢¥¯¥»¥¹¤Ê¤·
out = ex_out;
end
endcase
end
end
endmodule
|
/*
File: ewrapper_io_tx_slow.v
This file is part of the Parallella Project .
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module ewrapper_io_tx_slow
(/*AUTOARG*/
// Outputs
DATA_OUT_TO_PINS_P, DATA_OUT_TO_PINS_N, LCLK_OUT_TO_PINS_P,
LCLK_OUT_TO_PINS_N,
// Inputs
CLK_IN, CLK_IN_90, CLK_DIV_IN, CLK_RESET, IO_RESET, elink_disable,
DATA_OUT_FROM_DEVICE
);
//###########
//# INPUTS
//###########
(* dont_touch = "true" *) input CLK_IN; // Fast clock input from PLL/MMCM
(* dont_touch = "true" *) input CLK_IN_90; // Fast clock input with 90deg phase shift
input CLK_DIV_IN; // Slow clock input from PLL/MMCM
input CLK_RESET;
input IO_RESET;
input elink_disable;
input [71:0] DATA_OUT_FROM_DEVICE;
//#############
//# OUTPUTS
//#############
output [8:0] DATA_OUT_TO_PINS_P;
output [8:0] DATA_OUT_TO_PINS_N;
output LCLK_OUT_TO_PINS_P;
output LCLK_OUT_TO_PINS_N;
//############
//# REGS
//############
reg [1:0] clk_cnt;
reg tx_coreclock_del_45;
reg tx_coreclock_del_135;
reg [8:0] clk_even_reg;
reg [8:0] clk_odd_reg;
reg [71:0] tx_in_sync;
reg tx_pedge_first;
reg [3:0] cycle_sel;
//############
//# WIRES
//############
wire txo_lclk;
wire txo_lclk90;
wire tx_coreclock;
wire reset;
wire [8:0] clk_even;
wire [8:0] clk0_even;
wire [8:0] clk1_even;
wire [8:0] clk2_even;
wire [8:0] clk3_even;
wire [8:0] clk_odd;
wire [8:0] clk0_odd;
wire [8:0] clk1_odd;
wire [8:0] clk2_odd;
wire [8:0] clk3_odd;
wire [71:0] tx_in;
wire [8:0] tx_out;
wire tx_lclk_out;
wire [8:0] DATA_OUT_TO_PINS_P;
wire [8:0] DATA_OUT_TO_PINS_N;
wire LCLK_OUT_TO_PINS_P;
wire LCLK_OUT_TO_PINS_N;
// Inversions for E16/E64 migration
`ifdef TARGET_E16
wire elink_invert = 1'b0;
`elsif TARGET_E64
wire elink_invert = 1'b1;
`endif
/*AUTOINPUT*/
/*AUTOWIRE*/
assign reset = IO_RESET;
assign tx_in[71:0] = DATA_OUT_FROM_DEVICE[71:0];
assign txo_lclk = CLK_IN;
assign txo_lclk90 = CLK_IN_90;
assign tx_coreclock = CLK_DIV_IN;
//#################################################
//# Synchronize incoming data to fast clock domain
//#################################################
always @ (posedge txo_lclk)
if(tx_pedge_first)
tx_in_sync <= elink_invert ? ~tx_in : tx_in;
//################################
//# Output Buffers Instantiation
//################################
OBUFTDS #(.IOSTANDARD (`IOSTD_ELINK))
obufds_inst [8:0]
(.O (DATA_OUT_TO_PINS_P),
.OB (DATA_OUT_TO_PINS_N),
.I (tx_out),
.T ({1'b0, {8{elink_disable}}})); // Frame is always enabled
OBUFDS #(.IOSTANDARD (`IOSTD_ELINK))
obufds_lclk_inst
(.O (LCLK_OUT_TO_PINS_P),
.OB (LCLK_OUT_TO_PINS_N),
.I (tx_lclk_out));
//#############################
//# ODDR instantiation
//#############################
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_inst [8:0]
(
.Q (tx_out),
.C (txo_lclk),
.CE (1'b1),
.D1 (clk_even_reg),
.D2 (clk_odd_reg),
.R (reset),
.S (1'b0));
ODDR #(
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT (1'b0),
.SRTYPE ("ASYNC"))
oddr_lclk_inst
(
.Q (tx_lclk_out),
.C (txo_lclk90),
.CE (1'b1),
.D1 (~elink_invert & ~elink_disable),
.D2 (elink_invert & ~elink_disable),
.R (CLK_RESET),
.S (1'b0));
//########################
//# Data Serialization
//########################
always @ (posedge txo_lclk) begin
clk_even_reg[8:0] <= clk_even[8:0];
clk_odd_reg[8:0] <= clk_odd[8:0];
end
mux4 #(18) mux4
(// Outputs
.out ({clk_even[8:0],clk_odd[8:0]}),
// Inputs
.in0 ({clk0_even[8:0],clk0_odd[8:0]}),
.sel0 (cycle_sel[0]),
.in1 ({clk1_even[8:0],clk1_odd[8:0]}),
.sel1 (cycle_sel[1]),
.in2 ({clk2_even[8:0],clk2_odd[8:0]}),
.sel2 (cycle_sel[2]),
.in3 ({clk3_even[8:0],clk3_odd[8:0]}),
.sel3 (cycle_sel[3]));
//#################################
//# Serialization Cycle Counter
//#################################
always @ (posedge txo_lclk) begin
tx_pedge_first <= tx_coreclock_del_45 & tx_coreclock_del_135;
cycle_sel[0] <= tx_pedge_first;
cycle_sel[3:1] <= cycle_sel[2:0];
end
//################################################################
//# Posedge Detection of the Slow Clock in the Fast Clock Domain
//################################################################
always @ (negedge txo_lclk) begin
tx_coreclock_del_45 <= tx_coreclock;
tx_coreclock_del_135 <= tx_coreclock_del_45;
end
//##################################
//# Data Alignment Channel-to-Byte
//##################################
assign clk0_even[8:0] ={tx_in_sync[71],tx_in_sync[63],tx_in_sync[55],
tx_in_sync[47],tx_in_sync[39],tx_in_sync[31],
tx_in_sync[23],tx_in_sync[15],tx_in_sync[7]};
assign clk0_odd[8:0] ={tx_in_sync[70],tx_in_sync[62],tx_in_sync[54],
tx_in_sync[46],tx_in_sync[38],tx_in_sync[30],
tx_in_sync[22],tx_in_sync[14],tx_in_sync[6]};
assign clk1_even[8:0] ={tx_in_sync[69],tx_in_sync[61],tx_in_sync[53],
tx_in_sync[45],tx_in_sync[37],tx_in_sync[29],
tx_in_sync[21],tx_in_sync[13],tx_in_sync[5]};
assign clk1_odd[8:0] ={tx_in_sync[68],tx_in_sync[60],tx_in_sync[52],
tx_in_sync[44],tx_in_sync[36],tx_in_sync[28],
tx_in_sync[20],tx_in_sync[12],tx_in_sync[4]};
assign clk2_even[8:0] ={tx_in_sync[67],tx_in_sync[59],tx_in_sync[51],
tx_in_sync[43],tx_in_sync[35],tx_in_sync[27],
tx_in_sync[19],tx_in_sync[11],tx_in_sync[3]};
assign clk2_odd[8:0] ={tx_in_sync[66],tx_in_sync[58],tx_in_sync[50],
tx_in_sync[42],tx_in_sync[34],tx_in_sync[26],
tx_in_sync[18],tx_in_sync[10],tx_in_sync[2]};
assign clk3_even[8:0] ={tx_in_sync[65],tx_in_sync[57],tx_in_sync[49],
tx_in_sync[41],tx_in_sync[33],tx_in_sync[25],
tx_in_sync[17],tx_in_sync[9], tx_in_sync[1]};
assign clk3_odd[8:0] ={tx_in_sync[64],tx_in_sync[56],tx_in_sync[48],
tx_in_sync[40],tx_in_sync[32],tx_in_sync[24],
tx_in_sync[16],tx_in_sync[8], tx_in_sync[0]};
endmodule // ewrapper_io_tx_slow
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.4
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1ns/1ps
module ANN_dadd_64ns_64ns_64_5_full_dsp
#(parameter
ID = 6,
NUM_STAGE = 5,
din0_WIDTH = 64,
din1_WIDTH = 64,
dout_WIDTH = 64
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [63:0] a_tdata;
wire b_tvalid;
wire [63:0] b_tdata;
wire r_tvalid;
wire [63:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
ANN_ap_dadd_3_full_dsp_64 ANN_ap_dadd_3_full_dsp_64_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1==='bx ? 'b0 : din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1==='bx ? 'b0 : din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
module memory_epp(
input wire mclk,
input wire epp_astb,
input wire epp_dstb,
input wire epp_wr,
output reg epp_wait,
inout wire[7:0] epp_data,
input wire[7:6] status,
input wire[31:0] address,
output wire[31:0] dout,
input wire[31:0] din,
output reg complete,
input wire complete_clr
);
// Host is Little-Endian (LSB, ..., MSB).
wire[7:0] address_array[0:3];
assign address_array[0] = address[7:0];
assign address_array[1] = address[15:8];
assign address_array[2] = address[23:16];
assign address_array[3] = address[31:24];
wire[7:0] din_array[0:3];
assign din_array[0] = din[7:0];
assign din_array[1] = din[15:8];
assign din_array[2] = din[23:16];
assign din_array[3] = din[31:24];
reg[7:0] dout_array[0:3];
assign dout[31:0] = {dout_array[3], dout_array[2], dout_array[1], dout_array[0]};
reg[7:0] epp_data_reg;
assign epp_data = epp_data_reg;
parameter max_index = 3;
reg[2:0] index = 0;
parameter epp_reg_status = 8'd0;
parameter epp_reg_mem_addr = 8'd1;
parameter epp_reg_mem_data = 8'd2;
reg[7:0] epp_address = 0;
parameter epp_state_idle = 3'b000;
parameter epp_state_data_read = 3'b001;
parameter epp_state_data_write = 3'b010;
parameter epp_state_addr_read = 3'b011;
parameter epp_state_addr_write = 3'b100;
reg[2:0] epp_state = epp_state_idle;
// EPP Controller Asserts "Complete" After:
// - Host reads 4 bytes from mem_data register
// - Host writes 4 bytes to mem_data register
// - Host writes value 1 to command register
// EPP Controller Transparently Allows:
// - Read of command register
// - Read of memory adress
always @ (posedge mclk) begin
if(complete_clr == 1) begin
complete <= 0;
end else begin
case(epp_state)
epp_state_addr_read: begin
epp_wait <= 1;
epp_data_reg <= epp_address;
if(epp_astb == 1) begin
epp_state <= epp_state_idle;
end
end
epp_state_addr_write: begin
epp_wait <= 1;
epp_address <= epp_data;
index <= 0;
if(epp_astb == 1) begin
epp_state <= epp_state_idle;
end
end
epp_state_data_read: begin
epp_wait <= 1;
case(epp_address)
epp_reg_status:
epp_data_reg <= {status, 6'b0};
epp_reg_mem_addr:
epp_data_reg <= address_array[index];
epp_reg_mem_data:
epp_data_reg <= din_array[index];
default:
epp_data_reg <= 0;
endcase
if(epp_dstb == 1) begin
if(epp_address == epp_reg_mem_data && index == max_index) begin
complete <= 1;
end
index <= index + 1;
epp_state <= epp_state_idle;
end
end
epp_state_data_write: begin
epp_wait <= 1;
if(epp_address == epp_reg_mem_data) begin
dout_array[index] <= epp_data;
end
if(epp_dstb == 1) begin
if(epp_address == epp_reg_mem_data && index == max_index) begin
complete <= 1;
end
index <= index + 1;
epp_state <= epp_state_idle;
end
end
default: begin
if(epp_astb == 0) begin
if(epp_wr == 0) begin
epp_state <= epp_state_addr_write;
end else begin
epp_state <= epp_state_addr_read;
end
end else if(epp_dstb == 0) begin
if(epp_wr == 0) begin
epp_state <= epp_state_data_write;
end else begin
epp_state <= epp_state_data_read;
end
end
epp_wait <= 0; // Asserted
epp_data_reg <= 8'bZZZZZZZZ;
end
endcase
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's generate PC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// PC, interface to IC. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_genpc.v,v $
// Revision 1.10 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.9 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.7.4.3 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.7.4.2 2003/12/04 23:44:31 lampret
// Static exception prefix.
//
// Revision 1.7.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.7 2003/04/20 22:23:57 lampret
// No functional change. Only added customization for exception vectors.
//
// Revision 1.6 2002/03/29 15:16:55 lampret
// Some of the warnings fixed.
//
// Revision 1.5 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/20 18:46:15 simons
// Break point bug fixed
//
// Revision 1.9 2001/11/18 09:58:28 lampret
// Fixed some l.trap typos.
//
// Revision 1.8 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.1 2001/08/09 13:39:33 lampret
// Major clean-up.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_genpc(
// Clock and reset
clk, rst,
// External i/f to IC
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_rty_i, icpu_adr_i,
// Internal i/f
branch_op, except_type, except_prefix,
branch_addrofs, lr_restor, flag, taken, except_start,
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
genpc_freeze, genpc_stop_prefetch, no_more_dslot
);
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External i/f to IC
//
output [31:0] icpu_adr_o;
output icpu_cycstb_o;
output [3:0] icpu_sel_o;
output [3:0] icpu_tag_o;
input icpu_rty_i;
input [31:0] icpu_adr_i;
//
// Internal i/f
//
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
input except_prefix;
input [31:2] branch_addrofs;
input [31:0] lr_restor;
input flag;
output taken;
input except_start;
input [31:2] binsn_addr;
input [31:0] epcr;
input [31:0] spr_dat_i;
input spr_pc_we;
input genpc_refetch;
input genpc_stop_prefetch;
input genpc_freeze;
input no_more_dslot;
//
// Internal wires and regs
//
reg [31:2] pcreg;
reg [31:0] pc;
reg taken; /* Set to in case of jump or taken branch */
reg genpc_refetch_r;
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
//
// Control access to IC subsystem
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
//assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
//assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
//
// genpc_freeze_r
//
always @(posedge clk or posedge rst)
if (rst)
genpc_refetch_r <= #1 1'b0;
else if (genpc_refetch)
genpc_refetch_r <= #1 1'b1;
else
genpc_refetch_r <= #1 1'b0;
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
{2'b00, `OR1200_BRANCHOP_NOP}: begin
pc = {pcreg + 30'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
pc = {branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
pc = lr_restor;
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_BF}:
if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
pc = {pcreg + 30'd1, 2'b0};
taken = 1'b0;
end
{2'b00, `OR1200_BRANCHOP_BNF}:
if (flag) begin
pc = {pcreg + 30'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
taken = 1'b0;
end
else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
pc = {binsn_addr + branch_addrofs, 2'b0};
taken = 1'b1;
end
{2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
pc = epcr;
taken = 1'b1;
end
{2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
taken = 1'b1;
end
default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
pc = spr_dat_i;
taken = 1'b0;
end
endcase
end
//
// PC register
//
always @(posedge clk or posedge rst)
if (rst)
// pcreg <= #1 30'd63;
pcreg <= #1 ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
else if (spr_pc_we)
pcreg <= #1 spr_dat_i[31:2];
else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
pcreg <= #1 pc[31:2];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / 16K-Bit Data and 2K-Bit Parity Dual Port Block RAM
// /___/ /\ Filename : RAMB36SDP.v
// \ \ / \ Timestamp : Thu Jul 13 03:59:04 PST 2009
// \___\/\___\
//
// Revision:
// 07/13/09 - Initial version.
// End Revision
`timescale 1 ps/1 ps
module RAMB36SDP (DBITERR, DO, DOP, ECCPARITY, SBITERR,
DI, DIP, RDADDR, RDCLK, RDEN, REGCE, SSR, WE, WRADDR, WRCLK, WREN);
parameter integer DO_REG = 0;
parameter EN_ECC_READ = "FALSE";
parameter EN_ECC_SCRUB = "FALSE";
parameter EN_ECC_WRITE = "FALSE";
parameter [71:0] INIT = 72'h0;
parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter INIT_FILE = "NONE";
parameter SIM_COLLISION_CHECK = "ALL";
parameter SIM_MODE = "SAFE";
parameter [71:0] SRVAL = 72'h0;
localparam SETUP_ALL = 1000;
localparam SETUP_READ_FIRST = 3000;
output DBITERR;
output SBITERR;
output [63:0] DO;
output [7:0] DOP;
output [7:0] ECCPARITY;
input RDCLK;
input RDEN;
input REGCE;
input SSR;
input WRCLK;
input WREN;
input [8:0] WRADDR;
input [8:0] RDADDR;
input [63:0] DI;
input [7:0] DIP;
input [7:0] WE;
wire ssr_ram_wire;
wire ssr_reg_wire;
assign ssr_ram_wire = (DO_REG == 1) ? 1'b0 : SSR;
assign ssr_reg_wire = (DO_REG == 1) ? SSR : 1'b0;
RAMB36E1 #(.DOA_REG(DO_REG), .INIT_A({INIT[67:64], INIT[31:0]}), .INIT_B({INIT[71:68], INIT[63:32]}), .EN_ECC_READ(EN_ECC_READ), .EN_ECC_WRITE(EN_ECC_WRITE), .INIT_FILE(INIT_FILE), .RAM_MODE("SDP"), .SRVAL_A({SRVAL[67:64], SRVAL[31:0]}), .SRVAL_B({SRVAL[71:68], SRVAL[63:32]}), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST"), .READ_WIDTH_A(72), .READ_WIDTH_B(72), .WRITE_WIDTH_A(72), .WRITE_WIDTH_B(72), .SIM_COLLISION_CHECK(SIM_COLLISION_CHECK), .SIM_DEVICE("VIRTEX6"), .RSTREG_PRIORITY_A("REGCE"), .RSTREG_PRIORITY_B("REGCE"), .INIT_00(INIT_00), .INIT_01(INIT_01), .INIT_02(INIT_02), .INIT_03(INIT_03), .INIT_04(INIT_04), .INIT_05(INIT_05), .INIT_06(INIT_06), .INIT_07(INIT_07), .INIT_08(INIT_08), .INIT_09(INIT_09), .INIT_0A(INIT_0A), .INIT_0B(INIT_0B), .INIT_0C(INIT_0C), .INIT_0D(INIT_0D), .INIT_0E(INIT_0E), .INIT_0F(INIT_0F), .INIT_10(INIT_10), .INIT_11(INIT_11), .INIT_12(INIT_12), .INIT_13(INIT_13), .INIT_14(INIT_14), .INIT_15(INIT_15), .INIT_16(INIT_16), .INIT_17(INIT_17), .INIT_18(INIT_18), .INIT_19(INIT_19), .INIT_1A(INIT_1A), .INIT_1B(INIT_1B), .INIT_1C(INIT_1C), .INIT_1D(INIT_1D), .INIT_1E(INIT_1E), .INIT_1F(INIT_1F), .INIT_20(INIT_20), .INIT_21(INIT_21), .INIT_22(INIT_22), .INIT_23(INIT_23), .INIT_24(INIT_24), .INIT_25(INIT_25), .INIT_26(INIT_26), .INIT_27(INIT_27), .INIT_28(INIT_28), .INIT_29(INIT_29), .INIT_2A(INIT_2A), .INIT_2B(INIT_2B), .INIT_2C(INIT_2C), .INIT_2D(INIT_2D), .INIT_2E(INIT_2E), .INIT_2F(INIT_2F), .INIT_30(INIT_30), .INIT_31(INIT_31), .INIT_32(INIT_32), .INIT_33(INIT_33), .INIT_34(INIT_34), .INIT_35(INIT_35), .INIT_36(INIT_36), .INIT_37(INIT_37), .INIT_38(INIT_38), .INIT_39(INIT_39), .INIT_3A(INIT_3A), .INIT_3B(INIT_3B), .INIT_3C(INIT_3C), .INIT_3D(INIT_3D), .INIT_3E(INIT_3E), .INIT_3F(INIT_3F), .INIT_40(INIT_40), .INIT_41(INIT_41), .INIT_42(INIT_42), .INIT_43(INIT_43), .INIT_44(INIT_44), .INIT_45(INIT_45), .INIT_46(INIT_46), .INIT_47(INIT_47), .INIT_48(INIT_48), .INIT_49(INIT_49), .INIT_4A(INIT_4A), .INIT_4B(INIT_4B), .INIT_4C(INIT_4C), .INIT_4D(INIT_4D), .INIT_4E(INIT_4E), .INIT_4F(INIT_4F), .INIT_50(INIT_50), .INIT_51(INIT_51), .INIT_52(INIT_52), .INIT_53(INIT_53), .INIT_55(INIT_55), .INIT_56(INIT_56), .INIT_57(INIT_57), .INIT_58(INIT_58), .INIT_59(INIT_59), .INIT_5A(INIT_5A), .INIT_5B(INIT_5B), .INIT_5C(INIT_5C), .INIT_5D(INIT_5D), .INIT_5E(INIT_5E), .INIT_5F(INIT_5F), .INIT_60(INIT_60), .INIT_61(INIT_61), .INIT_62(INIT_62), .INIT_63(INIT_63), .INIT_64(INIT_64), .INIT_65(INIT_65), .INIT_66(INIT_66), .INIT_67(INIT_67), .INIT_68(INIT_68), .INIT_69(INIT_69), .INIT_6A(INIT_6A), .INIT_6B(INIT_6B), .INIT_6C(INIT_6C), .INIT_6D(INIT_6D), .INIT_6E(INIT_6E), .INIT_6F(INIT_6F), .INIT_70(INIT_70), .INIT_71(INIT_71), .INIT_72(INIT_72), .INIT_73(INIT_73), .INIT_74(INIT_74), .INIT_75(INIT_75), .INIT_76(INIT_76), .INIT_77(INIT_77), .INIT_78(INIT_78), .INIT_79(INIT_79), .INIT_7A(INIT_7A), .INIT_7B(INIT_7B), .INIT_7C(INIT_7C), .INIT_7D(INIT_7D), .INIT_7E(INIT_7E), .INIT_7F(INIT_7F), .INITP_00(INITP_00), .INITP_01(INITP_01), .INITP_02(INITP_02), .INITP_03(INITP_03), .INITP_04(INITP_04), .INITP_05(INITP_05), .INITP_06(INITP_06), .INITP_07(INITP_07), .INITP_08(INITP_08), .INITP_09(INITP_09), .INITP_0A(INITP_0A), .INITP_0B(INITP_0B), .INITP_0C(INITP_0C), .INITP_0D(INITP_0D), .INITP_0E(INITP_0E), .INITP_0F(INITP_0F)) R1 (.CASCADEOUTA(), .CASCADEOUTB(), .DBITERR(DBITERR), .SBITERR(SBITERR), .DOADO(DO[31:0]), .DOBDO(DO[63:32]), .DOPADOP(DOP[3:0]), .DOPBDOP(DOP[7:4]), .ECCPARITY(ECCPARITY), .RDADDRECC(), .ADDRARDADDR({1'b1, RDADDR, 1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .ADDRBWRADDR({1'b1,WRADDR,1'b1,1'b1,1'b1,1'b1,1'b1,1'b1}), .CASCADEINA(1'b0), .CASCADEINB(1'b0), .CLKARDCLK(RDCLK), .CLKBWRCLK(WRCLK), .DIADI(DI[31:0]), .DIBDI(DI[63:32]), .DIPADIP(DIP[3:0]), .DIPBDIP(DIP[7:4]), .ENARDEN(RDEN), .ENBWREN(WREN), .INJECTDBITERR(1'b0), .INJECTSBITERR(1'b0), .REGCEAREGCE(REGCE), .REGCEB(REGCE), .RSTRAMARSTRAM(ssr_ram_wire), .RSTRAMB(ssr_ram_wire), .RSTREGARSTREG(ssr_reg_wire), .RSTREGB(ssr_reg_wire), .WEA(4'b0), .WEBWE(WE));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:25:45 06/10/2015
// Design Name:
// Module Name: Top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Top(
input clk_50M,
//input btn,
input rst_n,
input RegNumPlus,
//vga
output hsync,
output vsync,
output vga_r,
output vga_g,
output vga_b,
//lcd
output lcd_rs,
output lcd_rw,
output lcd_e,
output[3:0] lcd_d,
output flash_ce,
//keyboard
input PS2C,
input PS2D,
//Serial Port
input RxD,
output TxD
);
wire clk;
assign clk = clk_50M;
/*
pbdebounce pb1 (
.clk(clk_50M),
.button(btn),
.pbreg(clk)
);*/
//RegNumControl
reg[4:0] RegNum;
pbdebounce pb2 (
.clk(clk_50M),
.button(RegNumPlus),
.pbreg(rnp)
);
always@(posedge rnp) begin
RegNum <= RegNum + 1;
end
//MainBoard
wire[31:0] RegData,ProgramCounter,IR;
wire[31:0] ExtraOut;
MainBoard mb(
//clk
.clk(clk),
.clk_50M(clk_50M),
//for debug
.RegNum(RegNum),
.RegData(RegData),
.ProgramCounter(ProgramCounter),
.IR(IR),
.ExtraOut(ExtraOut),
//vag
.hsync(hsync),
.vsync(vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b),
//keyboard
.PS2C(PS2C),
.PS2D(PS2D),
//Serial Port
.RxD(RxD),
.TxD(TxD)
);
//LCD_Display
wire[127:0] num128;
assign num128 = {
ProgramCounter | {3'h0,RegNum,24'h0},
RegData,
ExtraOut,
IR
};
LCD_dis lcd (
.clk(clk_50M),
.num(num128),
.reset(rst_n),
.lcd_rs(lcd_rs),
.lcd_rw(lcd_rw),
.lcd_e(lcd_e),
.lcd_d(lcd_d),
.flash_ce(flash_ce)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_ddr_6sig_x2_async.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_ddr_6sig_x2_async(ps_select_i_l ,testmode_l_i_l ,
test_mode_i_l ,testmode_l_i_r ,test_mode_i_r ,serial_out ,serial_in
,afo ,pad_clk_so ,async_pad_0 ,async_pad_1 ,afi ,vrefcode_i_l ,
vrefcode_i_r ,dq_pad ,io_dram_data_in ,io_dram_data_in_hi ,data_neg
,data_pos ,dqs_pad ,ps_select_i_r ,bso ,ctl_data_0 ,pad_clk_si ,
bypass_enable_i_l ,vdd_h ,strobe_i_r ,lpf_code_i_r ,
burst_length_four_i_r ,dram_io_ptr_clk_inv_i_r ,
dram_io_pad_enable_i_r ,dram_io_drive_enable_i_r ,rst_l_i_r , arst_l_i_r,
pad_pos_cnt_i_r ,pad_neg_cnt_i_r ,dram_io_channel_disabled_i_r ,
dram_io_drive_data_i_r ,cbu_i_r ,cbd_i_r ,se_i_r ,mode_ctrl_i_r ,
shift_dr_i_r ,clock_dr_i_r ,hiz_n_i_r ,update_dr_i_r ,strobe_i_l ,
lpf_code_i_l ,burst_length_four_i_l ,dram_io_ptr_clk_inv_i_l ,
dram_io_pad_enable_i_l ,dram_io_drive_enable_i_l ,ctl_data_1 ,
rst_l_i_l , arst_l_i_l, pad_pos_cnt_i_l ,pad_neg_cnt_i_l ,
dram_io_channel_disabled_i_l ,dram_io_drive_data_i_l ,cbu_i_l ,
cbd_i_l ,se_i_l ,mode_ctrl_i_l ,shift_dr_i_l ,clock_dr_i_l ,
hiz_n_i_l ,update_dr_i_l ,rclk ,bypass_enable_i_r ,bsi );
output [7:0] serial_out ;
output [7:0] afi ;
output [7:0] io_dram_data_in ;
output [7:0] io_dram_data_in_hi ;
input [7:0] serial_in ;
input [7:0] afo ;
input [7:0] vrefcode_i_l ;
input [7:0] vrefcode_i_r ;
input [7:0] data_neg ;
input [7:0] data_pos ;
input [4:0] lpf_code_i_r ;
input [1:0] dram_io_ptr_clk_inv_i_r ;
input [1:0] pad_pos_cnt_i_r ;
input [1:0] pad_neg_cnt_i_r ;
input [8:1] cbu_i_r ;
input [8:1] cbd_i_r ;
input [4:0] lpf_code_i_l ;
input [1:0] dram_io_ptr_clk_inv_i_l ;
input [1:0] pad_pos_cnt_i_l ;
input [1:0] pad_neg_cnt_i_l ;
input [8:1] cbu_i_l ;
input [8:1] cbd_i_l ;
inout [7:0] dq_pad ;
inout [1:0] dqs_pad ;
output pad_clk_so ;
output bso ;
input ps_select_i_l ;
input testmode_l_i_l ;
input test_mode_i_l ;
input testmode_l_i_r ;
input test_mode_i_r ;
input ps_select_i_r ;
input ctl_data_0 ;
input pad_clk_si ;
input bypass_enable_i_l ;
input vdd_h ;
input strobe_i_r ;
input burst_length_four_i_r ;
input dram_io_pad_enable_i_r ;
input dram_io_drive_enable_i_r ;
input rst_l_i_r ;
input arst_l_i_r ;
input dram_io_channel_disabled_i_r ;
input dram_io_drive_data_i_r ;
input se_i_r ;
input mode_ctrl_i_r ;
input shift_dr_i_r ;
input clock_dr_i_r ;
input hiz_n_i_r ;
input update_dr_i_r ;
input strobe_i_l ;
input burst_length_four_i_l ;
input dram_io_pad_enable_i_l ;
input dram_io_drive_enable_i_l ;
input ctl_data_1 ;
input rst_l_i_l ;
input arst_l_i_l ;
input dram_io_channel_disabled_i_l ;
input dram_io_drive_data_i_l ;
input se_i_l ;
input mode_ctrl_i_l ;
input shift_dr_i_l ;
input clock_dr_i_l ;
input hiz_n_i_l ;
input update_dr_i_l ;
input rclk ;
input bypass_enable_i_r ;
input bsi ;
inout async_pad_0 ;
inout async_pad_1 ;
wire clk_out0 ;
wire clk_out1 ;
wire dll_s0 ;
wire dll_s1 ;
wire bs0 ;
wire strobe0 ;
wire strobe1 ;
wire dl_clk_in0 ;
wire dl_clk_in1 ;
wire pad_clk_s0 ;
wire dl_clk_out0 ;
wire dl_clk_out1 ;
bw_io_ddr_6sig_async ddr_6sig0 (
.serial_out ({serial_out[3:0] } ),
.serial_in ({serial_in[3:0] } ),
.vrefcode ({vrefcode_i_l } ),
.io_dram_data_in_hi ({io_dram_data_in_hi[3:0] } ),
.afo ({afo[3:0] } ),
.afi ({afi[3:0] } ),
.dram_io_ptr_clk_inv ({dram_io_ptr_clk_inv_i_l } ),
.dq_pad ({dq_pad[3:0] } ),
.io_dram_data_in ({io_dram_data_in[3:0] } ),
.data_pos ({data_pos[3:0] } ),
.data_neg ({data_neg[3:0] } ),
.pad_neg_cnt ({pad_neg_cnt_i_l } ),
.pad_pos_cnt ({pad_pos_cnt_i_l } ),
.cbu ({cbu_i_l } ),
.cbd ({cbd_i_l } ),
.testmode_l (testmode_l_i_l ),
.test_mode (test_mode_i_l ),
.async_pad (async_pad_0 ),
.clk_out (clk_out0 ),
.mode_ctrl (mode_ctrl_i_l ),
.pad_clk_si (pad_clk_si ),
.rclk (rclk ),
.pad_clk_so (dll_s0 ),
.bypass_enable (bypass_enable_i_l ),
.ps_select (ps_select_i_l ),
.dqs_pad (dqs_pad[0] ),
.clk_sel (dl_clk_in0 ),
.vdd_h (vdd_h ),
.se (se_i_l ),
.bso (bs0 ),
.bsi (bsi ),
.hiz_n (hiz_n_i_l ),
.clock_dr (clock_dr_i_l ),
.shift_dr (shift_dr_i_l ),
.data (ctl_data_0 ),
.dram_io_drive_data (dram_io_drive_data_i_l ),
.dram_io_channel_disabled (dram_io_channel_disabled_i_l ),
.update_dr (update_dr_i_l ),
.rst_l (rst_l_i_l ),
.arst_l (arst_l_i_l ),
.dram_io_pad_enable (dram_io_pad_enable_i_l ),
.dram_io_drive_enable (dram_io_drive_enable_i_l ),
.dqs_read (dl_clk_out0 ),
.burst_length_four (burst_length_four_i_l ) );
bw_io_ddr_6sig_async ddr_6sig1 (
.serial_out ({serial_out[7:4] } ),
.serial_in ({serial_in[7:4] } ),
.vrefcode ({vrefcode_i_r } ),
.io_dram_data_in_hi ({io_dram_data_in_hi[7:4] } ),
.afo ({afo[7:4] } ),
.afi ({afi[7:4] } ),
.dram_io_ptr_clk_inv ({dram_io_ptr_clk_inv_i_r } ),
.dq_pad ({dq_pad[7:4] } ),
.io_dram_data_in ({io_dram_data_in[7:4] } ),
.data_pos ({data_pos[7:4] } ),
.data_neg ({data_neg[7:4] } ),
.pad_neg_cnt ({pad_neg_cnt_i_r } ),
.pad_pos_cnt ({pad_pos_cnt_i_r } ),
.cbu ({cbu_i_r } ),
.cbd ({cbd_i_r } ),
.testmode_l (testmode_l_i_r ),
.test_mode (test_mode_i_r ),
.async_pad (async_pad_1 ),
.clk_out (clk_out1 ),
.mode_ctrl (mode_ctrl_i_r ),
.pad_clk_si (pad_clk_s0 ),
.rclk (rclk ),
.pad_clk_so (dll_s1 ),
.bypass_enable (bypass_enable_i_r ),
.ps_select (ps_select_i_r ),
.dqs_pad (dqs_pad[1] ),
.clk_sel (dl_clk_in1 ),
.vdd_h (vdd_h ),
.se (se_i_r ),
.bso (bso ),
.bsi (bs0 ),
.hiz_n (hiz_n_i_r ),
.clock_dr (clock_dr_i_r ),
.shift_dr (shift_dr_i_r ),
.data (ctl_data_1 ),
.dram_io_drive_data (dram_io_drive_data_i_r ),
.dram_io_channel_disabled (dram_io_channel_disabled_i_r ),
.update_dr (update_dr_i_r ),
.rst_l (rst_l_i_r ),
.arst_l (arst_l_i_r ),
.dram_io_pad_enable (dram_io_pad_enable_i_r ),
.dram_io_drive_enable (dram_io_drive_enable_i_r ),
.dqs_read (dl_clk_out1 ),
.burst_length_four (burst_length_four_i_r ) );
bw_ioslave_dl io_slave_dl0 (
.lpf_out ({lpf_code_i_l } ),
.dqs_in (dl_clk_in0 ),
.si (dll_s0 ),
.se (se_i_l ),
.strobe (strobe0 ),
.so (pad_clk_s0 ),
.dqs_out (dl_clk_out0 ) );
bw_ioslave_dl io_slave_dl1 (
.lpf_out ({lpf_code_i_r } ),
.dqs_in (dl_clk_in1 ),
.si (dll_s1 ),
.se (se_i_r ),
.strobe (strobe1 ),
.so (pad_clk_so ),
.dqs_out (dl_clk_out1 ) );
bw_io_ddr_testmux testmux0 (
.strobe_out (strobe0 ),
.clk (clk_out0 ),
.testmode_l (testmode_l_i_l ),
.strobe (strobe_i_l ) );
bw_io_ddr_testmux testmux1 (
.strobe_out (strobe1 ),
.clk (clk_out1 ),
.testmode_l (testmode_l_i_r ),
.strobe (strobe_i_r ) );
endmodule
|
//****************************************************************************************************
//*---------------Copyright (c) 2016 C-L-G.FPGA1988.lichangbeiju. All rights reserved-----------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : if_reg.v
//Project Name : azpr_soc
//Description : the digital top of the chip.
//Github Address : github.com/C-L-G/azpr_soc/trunk/ic/digital/rtl/if_reg.v
//License : Apache-2.0
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 2016-11-22 17:00
//First Author : lichangbeiju
//Last Modify : 2016-11-23 14:20
//Last Author : lichangbeiju
//Version Number : 12 commits
//****************************************************************************************************
//Change History(latest change first)
//yyyy.mm.dd - Author - Your log of change
//****************************************************************************************************
//2016.12.08 - lichangbeiju - Change the include.
//2016.11.29 - lichangbeiju - Change the xx_ to xx_n.
//2016.11.23 - lichangbeiju - Change the coding style.
//2016.11.22 - lichangbeiju - Add io port.
//****************************************************************************************************
//File Include : system header file
`include "../sys_include.h"
`include "isa.h"
`include "cpu.h"
module if_reg (
input wire clk ,//clock
input wire reset ,//async reset
input wire [`WordDataBus] insn ,//read inst
input wire stall ,//delay
input wire flush ,//refresh
input wire [`WordAddrBus] new_pc ,//new program count
input wire br_taken,//branch taken
input wire [`WordAddrBus] br_addr ,//branch dest address
output reg [`WordAddrBus] if_pc ,//program count
output reg [`WordDataBus] if_insn ,//inst
output reg if_en //pipeline data valid flag
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 2.1 the output reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.2 the internal reg
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 2.x the test logic
//------------------------------------------------------------------------------------------------
//************************************************************************************************
// 3.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the pipeline register
//------------------------------------------------------------------------------------------------
always @(posedge clk or `RESET_EDGE reset) begin : PIPELINE_REG
//asynchronous reset
if (reset == `RESET_ENABLE) begin
if_pc <= #1 `RESET_VECTOR;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else begin
//update the pipeline reg
if (stall == `DISABLE) begin
if (flush == `ENABLE) begin //refresh the pipeline and pc
if_pc <= #1 new_pc;
if_insn <= #1 `ISA_NOP;
if_en <= #1 `DISABLE;
end else if (br_taken == `ENABLE) begin //branch taken and pc = br_addr
if_pc <= #1 br_addr;
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end else begin
if_pc <= #1 if_pc + 1'd1; //pc = next address[+1]
if_insn <= #1 insn;
if_en <= #1 `ENABLE;
end
end
end
end
//************************************************************************************************
// 4.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the clk generate module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Module
//****************************************************************************************************
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module oq_regs_eval_full
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH),
parameter MAX_PKT = 2048/CTRL_WIDTH, // allow for 2K bytes,
parameter MIN_PKT = 60/CTRL_WIDTH + 1,
parameter PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT)
)
(
// --- Inputs from dst update ---
input dst_update,
input [NUM_OQ_WIDTH-1:0] dst_oq,
input [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] dst_num_pkts_in_q,
input dst_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] dst_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] dst_num_words_left,
input dst_num_words_left_done,
// --- Inputs from src update ---
input src_update,
input [NUM_OQ_WIDTH-1:0] src_oq,
input [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q,
input [PKTS_IN_RAM_WIDTH-1:0] src_num_pkts_in_q,
input src_num_pkts_in_q_done,
input [SRAM_ADDR_WIDTH-1:0] src_oq_full_thresh,
input [SRAM_ADDR_WIDTH-1:0] src_num_words_left,
input src_num_words_left_done,
// --- Clear the flag ---
input initialize,
input [NUM_OQ_WIDTH-1:0] initialize_oq,
output [NUM_OUTPUT_QUEUES-1:0] full,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
// ------------- Wires/reg ------------------
reg [NUM_OUTPUT_QUEUES-1:0] full_pkts_in_q;
reg [NUM_OUTPUT_QUEUES-1:0] full_words_left;
wire src_full_pkts_in_q;
reg src_full_pkts_in_q_held;
wire dst_full_pkts_in_q;
wire src_full_words_left;
reg src_full_words_left_held;
wire dst_full_words_left;
reg dst_update_d1;
reg src_update_d1;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_max_pkts_in_q_held;
reg [PKTS_IN_RAM_WIDTH-1:0] dst_oq_full_thresh_held;
reg [PKTS_IN_RAM_WIDTH-1:0] src_oq_full_thresh_held;
reg [NUM_OQ_WIDTH-1:0] dst_oq_held;
reg [NUM_OQ_WIDTH-1:0] src_oq_held;
reg src_num_pkts_in_q_done_held;
reg src_num_words_left_done_held;
// ------------- Logic ------------------
assign full = full_pkts_in_q | full_words_left;
assign src_full_pkts_in_q = src_num_pkts_in_q >= src_max_pkts_in_q_held &&
src_max_pkts_in_q_held != 0;
assign dst_full_pkts_in_q = dst_num_pkts_in_q >= dst_max_pkts_in_q_held &&
dst_max_pkts_in_q_held != 0;
assign src_full_words_left = src_num_words_left <= src_oq_full_thresh_held ||
src_num_words_left < 2 * MAX_PKT;
assign dst_full_words_left = dst_num_words_left <= dst_oq_full_thresh_held ||
dst_num_words_left < 2 * MAX_PKT;
always @(posedge clk)
begin
dst_update_d1 <= dst_update;
src_update_d1 <= src_update;
if (reset) begin
full_pkts_in_q <= 'h0;
full_words_left <= 'h0;
end
else begin
if (dst_update) begin
dst_oq_held <= dst_oq;
end
if (src_update) begin
src_oq_held <= src_oq;
end
// Latch the maximums the cycle immediately following the update
// notifications. The update notifications are linked to the read
// ports of the appropriate registers so the read value will always
// be returned in the next cycle.
if (dst_update_d1) begin
dst_max_pkts_in_q_held <= dst_max_pkts_in_q;
dst_oq_full_thresh_held <= dst_oq_full_thresh;
end
if (src_update_d1) begin
src_max_pkts_in_q_held <= src_max_pkts_in_q;
src_oq_full_thresh_held <= src_oq_full_thresh;
end
// Update the full status giving preference to stores over removes
// since we don't want to accidentally try adding to a full queue
// Number of packets in queue
if (dst_num_pkts_in_q_done) begin
full_pkts_in_q[dst_oq_held] <= dst_full_pkts_in_q;
src_num_pkts_in_q_done_held <= src_num_pkts_in_q_done;
src_full_pkts_in_q_held <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q;
end
else if (src_num_pkts_in_q_done_held) begin
full_pkts_in_q[src_oq_held] <= src_full_pkts_in_q_held;
end
else if (initialize) begin
full_pkts_in_q[initialize_oq] <= 1'b0;
end
// Number of words left:
if (dst_num_words_left_done) begin
full_words_left[dst_oq_held] <= dst_full_words_left;
src_num_words_left_done_held <= src_num_words_left_done;
src_full_words_left_held <= src_full_words_left;
end
else if (src_num_words_left_done) begin
full_words_left[src_oq_held] <= src_full_words_left;
end
else if (src_num_words_left_done_held) begin
full_words_left[src_oq_held] <= src_full_words_left_held;
end
else if (initialize) begin
full_words_left[initialize_oq] <= 1'b0;
end
end
end
endmodule // oq_regs_eval_full
|
/*
Framebuffer Format
scrIs320=0 //640x240, 4x4x1 in 32 bits
scrIs320=1 //320x240, 4x4x2 in 64 bits
32-bit blocks:
00pp-pppp pppp-pppp pppp-pppp pppp-pppp
4x4x2, prior colors, UL pixel is ColorA
01pp-pppp pppp-pppp pppp-pppp pppp-pppp
4x4x2, prior colors, UL pixel is ColorB
10yy-yzzz uuvv-wwxx pppp-pppp pppp-pppp
4x4x1, YUV pair, ColorA=yuv, ColorB=zwx
11yy-yydd dduu-uvvv pppp-pppp pppp-pppp
4x4x1, YUVD centroid
64-bit blocks:
00pp-pppp pppp-pppp pppp-pppp pppp-pppp
Reserved
01pp-pppp pppp-pppp pppp-pppp pppp-pppp
Reserved
10yy-yyyy yzzz-zzzz uuuu-vvvv wwww-xxxx
4x4x2, YUV pair, ColorA=yuv, ColorB=zwx
11uu-uuuu uvvv-vvvv yyyy-yyyy dddd-dddd
4x4x2, YUVD centroid
A0_A000_XXXX: VRAM/Ctrl
0000..7FFF: First 32kB
8000..9FFF: Last 8kB
FF00..FFFF: Registers
*/
module ModFbCc(clock, reset,
pixPosX, pixPosY, pixCy, pixCu, pixCv,
pixCellIx, cellData1, cellData2);
// busAddr, busData, busOE, busWR, busHold);
/* verilator lint_off UNUSED */
input clock;
input reset;
input[9:0] pixPosX;
input[9:0] pixPosY;
output[7:0] pixCy;
output[7:0] pixCu;
output[7:0] pixCv;
output[13:0] pixCellIx;
input[31:0] cellData1;
input[31:0] cellData2;
reg[9:0] tPixPosX;
reg[9:0] tPixPosY;
reg[7:0] tPixCy;
reg[7:0] tPixCu;
reg[7:0] tPixCv;
reg[7:0] tPixNextCy;
reg[7:0] tPixNextCu;
reg[7:0] tPixNextCv;
reg[13:0] tPixCellX; //base cell X
reg[13:0] tPixCellY; //base cell Y
reg[13:0] tPixCellIx; //base cell index
reg[3:0] tPixCellFx; //base cell index
reg[13:0] tPixCellNextIx; //base cell index
reg[3:0] tPixCellNextFx; //base cell index
reg scrIs320; //use 320x240 (vs 640x240)
reg scrIsCell64; //cells are 64-bit
reg scrCellNoRead;
reg[31:0] tCell;
reg[31:0] tCell1;
reg[31:0] tCell2;
reg[31:0] tNextCell1;
reg[31:0] tNextCell2;
reg[9:0] tCellCy;
reg[9:0] tCellDy;
reg[9:0] tCellCu;
reg[9:0] tCellCv;
reg[9:0] tCellMCy;
reg[9:0] tCellNCy;
reg[9:0] tCellMCu;
reg[9:0] tCellNCu;
reg[9:0] tCellMCv;
reg[9:0] tCellNCv;
reg[9:0] tCellNextMCy;
reg[9:0] tCellNextNCy;
reg[9:0] tCellNextMCu;
reg[9:0] tCellNextNCu;
reg[9:0] tCellNextMCv;
reg[9:0] tCellNextNCv;
reg[7:0] tCellCy0;
reg[7:0] tCellCu0;
reg[7:0] tCellCv0;
reg[7:0] tCellCy1;
reg[7:0] tCellCu1;
reg[7:0] tCellCv1;
reg[7:0] tCellCy2;
reg[7:0] tCellCu2;
reg[7:0] tCellCv2;
reg[7:0] tCellCy3;
reg[7:0] tCellCu3;
reg[7:0] tCellCv3;
reg[1:0] tCellBit;
reg[1:0] tCellNextBit;
reg[31:0] tCellBits;
reg[31:0] tCellNextBits;
reg tCellUse32;
reg tCellNextUse32;
assign pixCellIx = tPixCellIx;
assign pixCy = tPixCy;
assign pixCu = tPixCu;
assign pixCv = tPixCv;
always @ (clock)
begin
scrIs320 = 1;
scrIsCell64 = 0;
// scrIs320 = scrCell2[2047][0];
// scrIs320 = scrCell2[11'h7C0][0];
tCellCy=0;
tCellDy=0;
tCellCu=0;
tCellCv=0;
tCellNextMCy=tCellMCy;
tCellNextNCy=tCellNCy;
tCellNextMCu=tCellMCu;
tCellNextNCu=tCellNCy;
tCellNextMCv=tCellMCv;
tCellNextNCv=tCellNCv;
tCellNextBits=0;
tCellNextBit=0;
tCellNextUse32=0;
tPixCellX=0;
tPixCellY=0;
if(scrIs320)
begin
tPixCellX[6:0] = tPixPosX[9:3];
tPixCellY[6:0] = tPixPosY[8:2];
tPixCellNextFx[1:0] = tPixPosX[2:1];
tPixCellNextFx[3:2] = tPixPosY[1:0];
if(scrIsCell64)
tPixCellNextIx = tPixCellY*160 + tPixCellX*2;
else
tPixCellNextIx = tPixCellY*80 + tPixCellX;
end
else
begin
tPixCellX[7:0] = tPixPosX[9:2];
tPixCellY[6:0] = tPixPosY[8:2];
tPixCellNextFx[1:0] = tPixPosX[1:0];
tPixCellNextFx[3:2] = tPixPosY[1:0];
tPixCellNextIx = tPixCellY*160 + tPixCellX;
end
// if(scrIs320)
if(scrIsCell64)
begin
case(tCell1[31:30])
2: begin
tCellNextMCy[7:1]=tCell1[29:23];
tCellNextNCy[7:1]=tCell1[22:16];
tCellNextMCy[0]=tCell1[29];
tCellNextNCy[0]=tCell1[22];
tCellNextMCu[7:4]=tCell1[15:12];
tCellNextMCv[7:4]=tCell1[11: 8];
tCellNextNCu[7:4]=tCell1[ 7: 4];
tCellNextNCv[7:4]=tCell1[ 3: 0];
tCellNextMCu[3:0]=0;
tCellNextMCv[3:0]=0;
tCellNextNCu[3:0]=0;
tCellNextNCv[3:0]=0;
tCellNextBits = tCell2;
tCellNextUse32 = 1;
end
3: begin
tCellCy[7:0]=tCell1[15: 8];
tCellDy[7:0]=tCell1[ 7: 0];
tCellCu[7:1]=tCell1[29:23];
tCellCv[7:1]=tCell1[22:16];
tCellCu[0]=0;
tCellCv[0]=0;
tCellNextMCy=tCellCy-(tCellDy>>1);
tCellNextNCy=tCellMCy+tCellDy;
tCellNextMCu=tCellCu;
tCellNextNCu=tCellCu;
tCellNextMCv=tCellCv;
tCellNextNCv=tCellCv;
tCellNextBits = tCell2;
tCellNextUse32 = 1;
end
endcase
end
else
begin
tCell = tPixCellIx[0] ? tCell2 : tCell1;
case(tCell[31:30])
0: begin
tCellNextBits[31:0] = tCell[31:0];
tCellNextUse32=1;
end
1: begin
tCellNextBits[31:0] = tCell[31:0];
tCellNextUse32=1;
end
2: begin
tCellNextMCy[7:5]=tCell[29:27];
tCellNextNCy[7:5]=tCell[26:24];
tCellNextMCy[4:2]=tCell[29:27];
tCellNextNCy[4:2]=tCell[26:24];
tCellNextMCy[1:0]=tCell[29:28];
tCellNextNCy[1:0]=tCell[26:25];
tCellNextMCu[7:6]=tCell[23:22];
tCellNextMCv[7:6]=tCell[21:20];
tCellNextNCu[7:6]=tCell[19:18];
tCellNextNCv[7:6]=tCell[17:16];
tCellNextMCu[5:0]=0;
tCellNextMCv[5:0]=0;
tCellNextNCu[5:0]=0;
tCellNextNCv[5:0]=0;
tCellNextBits[15:0] = tCell[15:0];
end
3: begin
tCellCy[7:4]=tCell[29:26];
tCellCy[3:0]=tCell[29:26];
tCellDy[7:4]=tCell[25:22];
tCellDy[3:0]=tCell[25:22];
tCellCu[7:5]=tCell[21:19];
tCellCv[7:5]=tCell[18:16];
tCellCu[4:0]=0;
tCellCv[4:0]=0;
tCellNextMCy=tCellCy-(tCellDy>>1);
tCellNextNCy=tCellMCy+tCellDy;
tCellNextMCu=tCellCu;
tCellNextNCu=tCellCu;
tCellNextMCv=tCellCv;
tCellNextNCv=tCellCv;
tCellNextBits[15:0] = tCell[15:0];
end
endcase
end
// tCellNextMCy=128;
// tCellNextNCy=128;
// tCellNextMCu=0;
// tCellNextNCu=255;
// tCellNextMCv=0;
// tCellNextNCv=255;
if(tCellUse32)
begin
case(tPixCellFx)
0: tCellNextBit=tCellBits[31:30];
1: tCellNextBit=tCellBits[29:28];
2: tCellNextBit=tCellBits[27:26];
3: tCellNextBit=tCellBits[25:24];
4: tCellNextBit=tCellBits[23:22];
5: tCellNextBit=tCellBits[21:20];
6: tCellNextBit=tCellBits[19:18];
7: tCellNextBit=tCellBits[17:16];
8: tCellNextBit=tCellBits[15:14];
9: tCellNextBit=tCellBits[13:12];
10: tCellNextBit=tCellBits[11:10];
11: tCellNextBit=tCellBits[ 9: 8];
12: tCellNextBit=tCellBits[ 7: 6];
13: tCellNextBit=tCellBits[ 5: 4];
14: tCellNextBit=tCellBits[ 3: 2];
15: tCellNextBit=tCellBits[ 1: 0];
endcase
end
else
begin
tCellNextBit[1]=0;
case(tPixCellFx)
0: tCellNextBit[0]=tCellBits[15];
1: tCellNextBit[0]=tCellBits[14];
2: tCellNextBit[0]=tCellBits[13];
3: tCellNextBit[0]=tCellBits[12];
4: tCellNextBit[0]=tCellBits[11];
5: tCellNextBit[0]=tCellBits[10];
6: tCellNextBit[0]=tCellBits[ 9];
7: tCellNextBit[0]=tCellBits[ 8];
8: tCellNextBit[0]=tCellBits[ 7];
9: tCellNextBit[0]=tCellBits[ 6];
10: tCellNextBit[0]=tCellBits[ 5];
11: tCellNextBit[0]=tCellBits[ 5];
12: tCellNextBit[0]=tCellBits[ 3];
13: tCellNextBit[0]=tCellBits[ 2];
14: tCellNextBit[0]=tCellBits[ 1];
15: tCellNextBit[0]=tCellBits[ 0];
endcase
end
tPixNextCy = 0;
tPixNextCu = 0;
tPixNextCv = 0;
// tCellCy0 = tCellLastNCy[7:0];
// tCellCu0 = tCellLastNCu[7:0];
// tCellCv0 = tCellLastNCv[7:0];
// tCellCy1 = tCellLastMCy[7:0];
// tCellCu1 = tCellLastMCu[7:0];
// tCellCv1 = tCellLastMCv[7:0];
if(tCellNCy[9])
tCellCy0 = 0;
else if(tCellNCy[8])
tCellCy0 = 255;
else
tCellCy0 = tCellNCy[7:0];
if(tCellNCu[9])
tCellCu0 = 0;
else if(tCellNCu[8])
tCellCu0 = 255;
else
tCellCu0 = tCellNCu[7:0];
if(tCellNCv[9])
tCellCv0 = 0;
else if(tCellNCv[8])
tCellCv0 = 255;
else
tCellCv0 = tCellNCv[7:0];
if(tCellMCy[9])
tCellCy1 = 0;
else if(tCellMCy[8])
tCellCy1 = 255;
else
tCellCy1 = tCellMCy[7:0];
if(tCellMCu[9])
tCellCu1 = 0;
else if(tCellMCu[8])
tCellCu1 = 255;
else
tCellCu1 = tCellMCu[7:0];
if(tCellMCv[9])
tCellCv1 = 0;
else if(tCellMCv[8])
tCellCv1 = 255;
else
tCellCv1 = tCellMCv[7:0];
tCellCy2=(tCellCy0>>1)+(tCellCy0>>2)+(tCellCy1>>2);
tCellCu2=(tCellCu0>>1)+(tCellCu0>>2)+(tCellCu1>>2);
tCellCv2=(tCellCv0>>1)+(tCellCv0>>2)+(tCellCv1>>2);
tCellCy3=(tCellCy1>>1)+(tCellCy1>>2)+(tCellCy0>>2);
tCellCu3=(tCellCu1>>1)+(tCellCu1>>2)+(tCellCu0>>2);
tCellCv3=(tCellCv1>>1)+(tCellCv1>>2)+(tCellCv0>>2);
if(tCellBit[1])
begin
if(tCellBit[0])
begin
tPixNextCy = tCellCy2;
tPixNextCu = tCellCu2;
tPixNextCv = tCellCv2;
end
else
begin
tPixNextCy = tCellCy3;
tPixNextCu = tCellCu3;
tPixNextCv = tCellCv3;
end
end
else
begin
if(tCellBit[0])
begin
tPixNextCy = tCellCy0;
tPixNextCu = tCellCu0;
tPixNextCv = tCellCv0;
end
else
begin
tPixNextCy = tCellCy1;
tPixNextCu = tCellCu1;
tPixNextCv = tCellCv1;
end
end
// tPixNextCy = 128;
// tPixNextCu = 0;
// tPixNextCv = 0;
end
always @ (posedge clock)
begin
tPixPosX <= pixPosX;
tPixPosY <= pixPosY;
tPixCellIx <= tPixCellNextIx;
tPixCellFx <= tPixCellNextFx;
tCell1 <= cellData1;
tCell2 <= cellData2;
tCellMCy <= tCellNextMCy;
tCellNCy <= tCellNextNCy;
tCellMCu <= tCellNextMCu;
tCellNCu <= tCellNextNCu;
tCellMCv <= tCellNextMCv;
tCellNCv <= tCellNextNCv;
tCellBits <= tCellNextBits;
tCellBit <= tCellNextBit;
tCellUse32 <= tCellNextUse32;
tPixCy <= tPixNextCy;
tPixCu <= tPixNextCu;
tPixCv <= tPixNextCv;
end
endmodule
|
//****************************************************************************************************
//*----------------Copyright (c) 2016 C-L-G.FPGA1988.Roger Wang. All rights reserved------------------
//
// -- It to be define --
// -- ... --
// -- ... --
// -- ... --
//****************************************************************************************************
//File Information
//****************************************************************************************************
//File Name : clk_gen_module.v
//Project Name : gt0000
//Description : The system auxiliary module.
//Github Address : https://github.com/C-L-G/gt0000/trunk/ic/digital/rtl/clk_gen_module/clk_gen_module.v
//License : CPL
//****************************************************************************************************
//Version Information
//****************************************************************************************************
//Create Date : 29-08-2016 17:00(1th Fri,July,2016)
//First Author : Roger Wang
//Modify Date : 29-08-2016 14:20(1th Sun,July,2016)
//Last Author : Roger Wang
//Version Number : 001
//Last Commit : 29-08-2016 14:30(1th Sun,July,2016)
//****************************************************************************************************
//Change History(latest change first)
//dd.mm.yyyy - Author - Your log of change
//****************************************************************************************************
//02.09.2016 - Roger Wang - Move the div logic from gen top to this module.
//*---------------------------------------------------------------------------------------------------
`timescale 1ns/1ps
module clk_div_module(
src_clk ,//01 In
div_rst_n ,//01 In
div_clk_0 ,//01 Out
div_clk_1 //01 Out
);
//************************************************************************************************
// 1.Parameter and constant define
//************************************************************************************************
//************************************************************************************************
// 2.input and output declaration
//************************************************************************************************
input src_clk ;//the clk = 200MHz
input div_rst_n ;//the reset signal : low active
output div_clk_0 ;//the div 2 clock = 100MHz
output div_clk_1 ;//the div 4 clock = 50MHz
//************************************************************************************************
// 3.Register and wire declaration
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 3.1 the system led module wire
//------------------------------------------------------------------------------------------------
reg [01:00] clk_div_cnt ;//led count
//************************************************************************************************
// 4.Main code
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 4.1 the system led module assignment
//------------------------------------------------------------------------------------------------
always @(posedge src_clk or negedge div_rst_n) begin : DIV_CNT_ADD
if(!div_rst_n)
begin
`ifndef SYNTHESIS
$display("The initial value of clk div count is 0.");
`endif
clk_div_cnt <= 'd0;
end
else
begin
clk_div_cnt <= clk_div_cnt + 1'b1;
end
end
assign div_clk_0 = clk_div_cnt[0];
assign div_clk_1 = clk_div_cnt[1];
//************************************************************************************************
// 5.Sub module instantiation
//************************************************************************************************
//------------------------------------------------------------------------------------------------
// 5.1 the xxx module
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 5.2 the xxx module
//------------------------------------------------------------------------------------------------
//------------------------------------------------------------------------------------------------
// 5.3 the xxx module
//------------------------------------------------------------------------------------------------
endmodule
//****************************************************************************************************
//End of Mopdule
//****************************************************************************************************
|
`timescale 1 ns / 1 ps
//////////////////////////////////////////////////////////////////////////////////
// Company: AGH UST
// Engineer: Wojciech Gredel, Hubert Górowski
//
// Create Date:
// Design Name:
// Module Name: MarioScore24x1
// Project Name: DOS_Mario
// Target Devices: Basys3
// Tool versions: Vivado 2016.1
// Description:
// This is the engine module, it controlls:
// *Mario movement
// *Mario lives
// *Background movement
// *Hitting the blocks
//
//
// Dependencies:
//
// Revision:
// Revision 0.01 - Module created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module GameEngine
(
input wire clk,
input wire game_clk,
input wire rst,
input wire L_ALT,
input wire R_ALT,
input wire L_CTRL,
input wire R_CTRL,
input wire SPACE,
input wire L_SHIFT,
input wire R_SHIFT,
input wire ESC,
input wire D_ARROW,
input wire L_ARROW,
input wire R_ARROW,
input wire blocking_in,
input wire [5:0] block_in,
input wire stage_restarted,
output reg [7:0] block_xpos,
output reg [3:0] block_ypos,
output reg [9:0] bcgr_xpos,
output reg [7:0] plane_xpos,
output reg [5:0] plane_xpos_ofs,
output reg [9:0] player_xpos,
output reg [8:0] player_ypos,
output reg player_dir,
output reg monster_1_dir,
output reg [1:0] player_speed,
output reg gameover,
output reg [5:0] write_block,
output reg block_we,
output reg restartgame,
output reg [3:0] player_life,
output reg [11:0] player_points,
output reg [3:0] lvl_number
);
always @(posedge clk) begin
lvl_number <=1 ;
end
reg gameover_nxt;
reg restartgame_nxt;
reg player_xpos_restarted;
reg player_ypos_restarted;
reg bcgr_restarted;
reg board_restarted;
reg player_xpos_restarted_nxt;
reg player_ypos_restarted_nxt;
reg bcgr_restarted_nxt;
reg board_restarted_nxt;
//************************
//State Machine for player
//************************
reg [3:0] player_life_nxt;
reg [1:0] player_hor_state;
reg [1:0] player_ver_state;
reg [1:0] player_hor_state_nxt;
reg [1:0] player_ver_state_nxt;
reg [7:0] jump_height;
reg [7:0] jump_height_nxt;
reg [9:0] player_xpos_nxt;
reg [8:0] player_ypos_nxt;
reg player_dir_nxt;
reg [1:0] player_speed_nxt;
localparam PL_STOP = 2'b00;
localparam PL_RIGHT = 2'b01;
localparam PL_LEFT = 2'b10;
localparam PL_JUMP = 2'b01;
localparam PL_FALL = 2'b10;
localparam DIR_RIGHT = 1'b0;
localparam DIR_LEFT = 1'b1;
localparam PL_STAND = 2'b00;
localparam PL_WALK = 2'b01;
localparam PL_RUN = 2'b10;
localparam PLAYER_WIDTH = 40;
localparam PLAYER_XPOS_MAX = 480;
localparam PLAYER_XPOS_MIN = 120;
localparam PLAYER_YPOS_MAX = 480;
//Speed
always @* begin
if(L_ARROW || R_ARROW) begin
if(L_CTRL || R_CTRL)
player_speed_nxt = PL_RUN;
else
player_speed_nxt = PL_WALK;
end
else
player_speed_nxt = PL_STAND;
end
//Lifes
always @(posedge clk or posedge rst) begin
if(rst) begin
player_life <= 3;
gameover <= 0;
restartgame <= 0;
end
else begin
player_life <= player_life_nxt;
gameover <= gameover_nxt;
restartgame <= restartgame_nxt;
end
end
reg [11:0] player_points_nxt;
reg [11:0] player_points_latched;
reg [11:0] player_points_latched_nxt;
//Points
always @(posedge clk or posedge rst) begin
if(rst) begin
player_points <= 0;
player_points_latched <= 0;
end
else begin
player_points <= player_points_nxt;//player_points_nxt;
player_points_latched <= player_points_latched_nxt;
end
end
always @* begin
if((new_point) && (player_points_latched == player_points)) begin
player_points_nxt = player_points + 1;
player_points_latched_nxt = player_points_latched;
end
else begin
player_points_nxt = player_points;
if(new_point)
player_points_latched_nxt = player_points_latched;
else
player_points_latched_nxt = player_points;
end
end
//loosing lifes, gameover
always @* begin
if(gameover) begin
restartgame_nxt = 1;
player_life_nxt = 0;
gameover_nxt = 1;
end
else if(restartgame) begin
if((player_xpos_restarted) && (player_ypos_restarted) && (board_restarted) && (bcgr_restarted) && (stage_restarted)) begin
restartgame_nxt = 0;
player_life_nxt = player_life;
gameover_nxt = gameover;
end
else begin
restartgame_nxt = 1;
player_life_nxt = player_life;
gameover_nxt = gameover;
end
end
else if(player_ypos == 0) begin
if(player_life == 1) begin
gameover_nxt = 1;
player_life_nxt = 0;
restartgame_nxt = 1;
end
else begin
player_life_nxt = player_life - 1;
gameover_nxt = 0;
restartgame_nxt = 1;
end
end
else begin
gameover_nxt = 0;
player_life_nxt = player_life;
restartgame_nxt = 0;
end
end
//Player horizontal movement
always @* begin
if(restartgame) begin
player_xpos_nxt = 120;
player_hor_state_nxt= 0;
player_dir_nxt = 0;
player_xpos_restarted_nxt = 1;
end
else begin
player_xpos_restarted_nxt = 0;
case(player_hor_state)
PL_STOP: begin
if(L_ARROW) begin
if(blocking[1]) player_hor_state_nxt = PL_STOP;
else player_hor_state_nxt = PL_LEFT;
end
else if(R_ARROW) begin
if(blocking[0]) player_hor_state_nxt = PL_STOP;
else player_hor_state_nxt = PL_RIGHT;
end
else begin
player_hor_state_nxt = PL_STOP;
end
player_xpos_nxt = player_xpos;
player_dir_nxt = player_dir;
end
PL_RIGHT: begin
if(L_ARROW) begin
if(blocking[1]) player_hor_state_nxt = PL_STOP;
else player_hor_state_nxt = PL_LEFT;
end
else if(R_ARROW) begin
if(blocking[0]) player_hor_state_nxt = PL_STOP;
else player_hor_state_nxt = PL_RIGHT;
end
else begin
player_hor_state_nxt = PL_STOP;
end
if(((player_xpos) < PLAYER_XPOS_MAX)&&(blocking[0]==0)) begin
player_xpos_nxt = player_xpos + 1;
player_dir_nxt = DIR_RIGHT;
end
else begin
player_xpos_nxt = player_xpos;
player_dir_nxt = DIR_RIGHT;
end
end
PL_LEFT: begin
if(L_ARROW) begin
if(blocking[1]) player_hor_state_nxt = PL_STOP;
else player_hor_state_nxt = PL_LEFT;
end
else if(R_ARROW) begin
if(blocking[0]) player_hor_state_nxt = PL_STOP;
else player_hor_state_nxt = PL_RIGHT;
end
else begin
player_hor_state_nxt = PL_STOP;
end
if(((player_xpos) > PLAYER_XPOS_MIN)&&(blocking[1] == 0)) begin
player_xpos_nxt = player_xpos - 1;
player_dir_nxt = DIR_LEFT;
end
else begin
player_xpos_nxt = player_xpos;
player_dir_nxt = DIR_LEFT;
end
end
default: begin
player_hor_state_nxt = PL_STOP;
player_xpos_nxt = player_xpos;
player_dir_nxt = player_dir;
end
endcase
end
end
//Player vertical movement
always @* begin
if(restartgame) begin
player_ypos_nxt = 100;
player_ver_state_nxt= 0;
jump_height_nxt = 0;
player_ypos_restarted_nxt = 1;
end
else begin
player_ypos_restarted_nxt = 0;
case(player_ver_state)
PL_STOP: begin
if(L_ALT || R_ALT) begin
if(blocking[2])
player_ver_state_nxt = PL_STOP;
else
player_ver_state_nxt = PL_JUMP;
end
else if(blocking[3] == 0)
player_ver_state_nxt = PL_FALL;
else
player_ver_state_nxt = PL_STOP;
player_ypos_nxt = player_ypos;
jump_height_nxt = 0;
end
PL_JUMP: begin
if((jump_height < 200) && (blocking[2] == 0)) begin
player_ver_state_nxt = PL_JUMP;
jump_height_nxt = jump_height + 1;
if(player_ypos == PLAYER_YPOS_MAX)
player_ypos_nxt = player_ypos;
else
player_ypos_nxt = player_ypos + 1;
end
else begin
player_ver_state_nxt = PL_FALL;
jump_height_nxt = jump_height;
player_ypos_nxt = player_ypos;
end
end
PL_FALL: begin
if((blocking[3] == 0)) begin
player_ver_state_nxt = PL_FALL;
jump_height_nxt = jump_height - 1;
player_ypos_nxt = player_ypos - 1;
end
else begin
player_ver_state_nxt = PL_STOP;
jump_height_nxt = jump_height;
player_ypos_nxt = player_ypos;
end
end
default: begin
player_ver_state_nxt = PL_STOP;
jump_height_nxt = jump_height;
player_ypos_nxt = player_ypos;
end
endcase
end
end
always @(posedge game_clk or posedge rst) begin
if(rst) begin
player_ypos <= 100;
player_ver_state<= 0;
jump_height <= 0;
player_ypos_restarted <= 0;
end
else begin
player_ypos <= player_ypos_nxt;
player_ver_state<= player_ver_state_nxt;
jump_height <= jump_height_nxt;
player_ypos_restarted <= player_ypos_restarted_nxt;
end
end
reg [1:0] clk_hor_divider;
always @(posedge game_clk or posedge rst) begin
if(rst) begin
player_xpos_restarted <= 0;
player_xpos <= 120;
player_hor_state<= 0;
player_dir <= 0;
clk_hor_divider <= 2'b00;
end
else begin
if((clk_hor_divider == 2'b01)&&(player_speed == PL_RUN)) begin
player_xpos <= player_xpos_nxt;
player_hor_state<= player_hor_state_nxt;
player_dir <= player_dir_nxt;
clk_hor_divider <= 2'b10;
player_xpos_restarted <= 0;
end
else if(clk_hor_divider == 2'b11) begin
player_xpos <= player_xpos_nxt;
player_hor_state<= player_hor_state_nxt;
player_dir <= player_dir_nxt;
clk_hor_divider <= 2'b00;
player_xpos_restarted <= player_xpos_restarted_nxt;
end
else
clk_hor_divider <= clk_hor_divider + 1;
end
end
always @(posedge game_clk or posedge rst) begin
if(rst)
player_speed <= PL_STOP;
else
if(clk_hor_divider == 2'b11)
player_speed <= player_speed_nxt;
end
//********************************
// End of State Machine for player
//********************************
//************************************************
// State Machine for board and background movement (uses player states because depends on player movement)
//************************************************
reg [9:0] bcgr_xpos_nxt;
localparam XRES = 640;
always @* begin
if(restartgame) begin
bcgr_xpos_nxt = 0;
bcgr_restarted_nxt = 1;
end
else begin
bcgr_restarted_nxt = 0;
case(player_hor_state)
PL_STOP:
bcgr_xpos_nxt = bcgr_xpos;
PL_RIGHT:
if((player_xpos == PLAYER_XPOS_MAX)&&((plane_xpos_ofs != MAX_OFFSET)||(plane_xpos != BOARD_END)))
bcgr_xpos_nxt = (bcgr_xpos + 2*player_speed) % (XRES - 1);
else
bcgr_xpos_nxt = bcgr_xpos;
PL_LEFT:
if((player_xpos == PLAYER_XPOS_MIN)&&((plane_xpos_ofs != 0)||(plane_xpos != 0)))
if(bcgr_xpos < 2*player_speed)
bcgr_xpos_nxt = ((XRES-1) + bcgr_xpos - 2*player_speed);
else
bcgr_xpos_nxt = bcgr_xpos - 2*player_speed;
else
bcgr_xpos_nxt = bcgr_xpos;
default:
bcgr_xpos_nxt = bcgr_xpos;
endcase
end
end
reg [7:0] plane_xpos_nxt;
reg [5:0] plane_xpos_ofs_nxt;
localparam MAX_OFFSET = 39;
localparam BOARD_END = 163;
always @* begin
if(restartgame) begin
plane_xpos_ofs_nxt = 0;
plane_xpos_nxt = 0;
board_restarted_nxt = 1;
end
else begin
board_restarted_nxt = 0;
case(player_hor_state)
PL_STOP: begin
plane_xpos_ofs_nxt = plane_xpos_ofs;
plane_xpos_nxt = plane_xpos;
end
PL_RIGHT:
if(player_xpos == PLAYER_XPOS_MAX) begin
if(blocking[0] == 0) begin
if(plane_xpos_ofs == MAX_OFFSET) begin
if(plane_xpos == BOARD_END) begin
plane_xpos_ofs_nxt = MAX_OFFSET;
plane_xpos_nxt = BOARD_END;
end
else begin
plane_xpos_ofs_nxt = 0;
plane_xpos_nxt = plane_xpos + 1;
end
end
else begin
plane_xpos_ofs_nxt = plane_xpos_ofs + 1;
plane_xpos_nxt = plane_xpos;
end
end
else begin
plane_xpos_ofs_nxt = plane_xpos_ofs;
plane_xpos_nxt = plane_xpos;
end
end
else begin
plane_xpos_ofs_nxt = plane_xpos_ofs;
plane_xpos_nxt = plane_xpos;
end
PL_LEFT: begin
if(player_xpos == PLAYER_XPOS_MIN) begin
if(blocking[1] == 0) begin
if(plane_xpos_ofs == 0) begin
if(plane_xpos == 0) begin
plane_xpos_ofs_nxt = 0;
plane_xpos_nxt = 0;
end
else begin
plane_xpos_ofs_nxt = MAX_OFFSET;
plane_xpos_nxt = plane_xpos - 1;
end
end
else begin
plane_xpos_ofs_nxt = plane_xpos_ofs - 1;
plane_xpos_nxt = plane_xpos;
end
end
else begin
plane_xpos_ofs_nxt = plane_xpos_ofs;
plane_xpos_nxt = plane_xpos;
end
end
else begin
plane_xpos_ofs_nxt = plane_xpos_ofs;
plane_xpos_nxt = plane_xpos;
end
end
default: begin
plane_xpos_ofs_nxt = plane_xpos_ofs;
plane_xpos_nxt = plane_xpos;
end
endcase
end
end
always @(posedge game_clk or posedge rst) begin
if(rst) begin
plane_xpos_ofs <= 0;
plane_xpos <= 0;
board_restarted <= 0;
end
else begin
if((clk_hor_divider == 2'b01)&&(player_speed == PL_RUN)) begin
plane_xpos_ofs <= plane_xpos_ofs_nxt;
plane_xpos <= plane_xpos_nxt;
board_restarted <= 0;
end
else if(clk_hor_divider == 2'b11) begin
plane_xpos_ofs <= plane_xpos_ofs_nxt;
plane_xpos <= plane_xpos_nxt;
board_restarted <= board_restarted_nxt;
end
end
end
always @(posedge game_clk or posedge rst) begin
if(rst) begin
bcgr_xpos <= 0;
bcgr_restarted <= 0;
end
else begin
if(clk_hor_divider == 2'b11) begin
bcgr_xpos <= bcgr_xpos_nxt;
bcgr_restarted <= bcgr_restarted_nxt;
end
end
end
//**********************************************
// End of State Machine for board and background
//**********************************************
//**********************************************************
// Logic for blocking the player and checking special blocks
//**********************************************************
reg [7:0] block_xpos_nxt;
reg [3:0] block_ypos_nxt;
reg [3:0] blocking;//D:U:L:R
reg [3:0] blocking_nxt;
reg [47:0] modi_block; //DL:DR:UL:UR:LD:LU:RD:RU
reg [47:0] modi_block_nxt;
reg [3:0] blocking_state;
reg [3:0] blocking_state_nxt;
reg [1:0] special;
reg [1:0] special_nxt;
reg [5:0] write_block_nxt;
reg block_we_nxt;
reg [1:0] writing_phase;
reg [1:0] writing_phase_nxt;
reg position_changed;
reg position_changed_nxt;
localparam SPECIAL = 2'b01;
localparam BLOCKING = 2'b00;
localparam MOD_BLOCK = 2'b11;
localparam PREPARE = 4'b0000;
localparam START = 4'b0001;
localparam DOWN_L = 4'b0010;
localparam DOWN_R = 4'b0011;
localparam UP_L = 4'b0100;
localparam UP_R = 4'b0101;
localparam LEFT_D = 4'b0110;
localparam LEFT_U = 4'b0111;
localparam RIGHT_D = 4'b1000;
localparam RIGHT_U = 4'b1001;
//position changed
reg [7:0] old_plane_xpos;
reg [5:0] old_plane_xpos_ofs;
reg [9:0] old_player_xpos;
reg [8:0] old_player_ypos;
reg [7:0] old_plane_xpos_nxt;
reg [5:0] old_plane_xpos_ofs_nxt;
reg [9:0] old_player_xpos_nxt;
reg [8:0] old_player_ypos_nxt;
reg position_changed1;
reg position_changed1_nxt;
always @* begin
old_plane_xpos_nxt = plane_xpos;
old_plane_xpos_ofs_nxt = plane_xpos_ofs;
old_player_xpos_nxt = player_xpos;
old_player_ypos_nxt = player_ypos;
if((old_plane_xpos != plane_xpos) || (old_plane_xpos_ofs != plane_xpos_ofs) || (old_player_xpos != player_xpos) || (old_player_ypos != player_ypos))
position_changed1_nxt = 1;
else
position_changed1_nxt = 0;
end
always @(posedge clk or posedge rst) begin
if(rst) begin
old_plane_xpos <= 0;
old_plane_xpos_ofs <= 0;
old_player_xpos <= 0;
old_player_ypos <= 0;
position_changed1 <= 0;
end
else begin
position_changed1 <= position_changed1_nxt;
old_plane_xpos <= old_plane_xpos_nxt;
old_plane_xpos_ofs <= old_plane_xpos_ofs_nxt;
old_player_xpos <= old_player_xpos_nxt;
old_player_ypos <= old_player_ypos_nxt;
end
end
//rest of blocking
always @(posedge clk or posedge rst) begin
if(rst) begin
special <= 0;
blocking_state <= PREPARE;
block_ypos <= 0;
block_xpos <= 0;
blocking <= 4'b1000;
modi_block <= 0;
write_block <= 0;
writing_phase <= 2'b00;
old_block <=0 ;
position_changed <= 0;
end
else begin
modi_block <= modi_block_nxt;
special <= special_nxt;
blocking_state <= blocking_state_nxt;
block_xpos <= block_xpos_nxt;
block_ypos <= block_ypos_nxt;
blocking <= blocking_nxt;
write_block <= write_block_nxt;
writing_phase <= writing_phase_nxt;
old_block <= old_block_nxt;
position_changed <= position_changed_nxt;
end
end
//And here we are, the code below does the job, it really does
always @* begin
if(position_changed) begin
case(special)
BLOCKING: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 0;
writing_phase_nxt = 2'b00;
write_block_nxt = 0;
block_we = 0;
old_block_nxt = 0;
modi_block_nxt = modi_block;
case(blocking_state)
PREPARE: begin
blocking_state_nxt = START;
block_xpos_nxt = plane_xpos + (player_xpos + plane_xpos_ofs)/40;
block_ypos_nxt = player_ypos/40;
blocking_nxt = blocking;
special_nxt = BLOCKING;
end
START: begin
blocking_state_nxt = DOWN_L;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos - 1;
blocking_nxt = blocking;
special_nxt = BLOCKING;
end
DOWN_L: begin
special_nxt = BLOCKING;
if((player_xpos + plane_xpos_ofs)%40 == 0) begin
blocking_state_nxt = UP_L;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos + 2;
end
else begin
block_xpos_nxt = block_xpos + 1;
block_ypos_nxt = block_ypos;
blocking_state_nxt = DOWN_R;
end
if(player_ypos % 40 == 0)
blocking_nxt[3] = blocking_in;
else
blocking_nxt[3] = 0;
blocking_nxt[2] = blocking[2];
blocking_nxt[1] = blocking[1];
blocking_nxt[0] = blocking[0];
end
DOWN_R: begin
special_nxt = BLOCKING;
blocking_state_nxt = UP_L;
block_xpos_nxt = block_xpos - 1;
block_ypos_nxt = block_ypos + 2;
if(player_ypos % 40 == 0)
blocking_nxt[3] = (blocking_in || blocking[3]);
else
blocking_nxt[3] = 0;
blocking_nxt[2] = blocking[2];
blocking_nxt[1] = blocking[1];
blocking_nxt[0] = blocking[0];
end
UP_L: begin
special_nxt = BLOCKING;
if((player_xpos + plane_xpos_ofs)%40 == 0) begin
blocking_state_nxt = LEFT_D;
block_xpos_nxt = block_xpos - 1;
block_ypos_nxt = block_ypos - 1;
end
else begin
block_xpos_nxt = block_xpos + 1;
blocking_state_nxt = UP_R;
block_ypos_nxt = block_ypos;
end
blocking_nxt[3] = blocking[3];
if(player_ypos % 40 == 0)
blocking_nxt[2] = blocking_in;
else
blocking_nxt[2] = 0;
blocking_nxt[1] = blocking[1];
blocking_nxt[0] = blocking[0];
end
UP_R: begin
special_nxt = BLOCKING;
blocking_state_nxt = LEFT_D;
block_xpos_nxt = block_xpos - 2;
block_ypos_nxt = block_ypos - 1;
blocking_nxt[3] = blocking[3];
if(player_ypos % 40 == 0)
blocking_nxt[2] = (blocking_in || blocking[2]);
else
blocking_nxt[2] = 0;
blocking_nxt[1] = blocking[1];
blocking_nxt[0] = blocking[0];
end
LEFT_D: begin
special_nxt = BLOCKING;
if(player_ypos % 40 == 0) begin
blocking_state_nxt = RIGHT_D;
block_xpos_nxt = block_xpos + 2;
block_ypos_nxt = block_ypos;
end
else begin
blocking_state_nxt = LEFT_U;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos + 1;
end
blocking_nxt[3] = blocking[3];
blocking_nxt[2] = blocking[2];
if((player_xpos + plane_xpos_ofs) % 40 == 0)
blocking_nxt[1] = blocking_in;
else
blocking_nxt[1] = 0;
blocking_nxt[0] = blocking[0];
end
LEFT_U: begin
special_nxt = BLOCKING;
blocking_state_nxt = RIGHT_D;
block_xpos_nxt = block_xpos + 2;
block_ypos_nxt = block_ypos - 1;
blocking_nxt[3] = blocking[3];
blocking_nxt[2] = blocking[2];
if((player_xpos + plane_xpos_ofs) % 40 == 0)
blocking_nxt[1] = (blocking_in || blocking[1]);
else
blocking_nxt[1] = 0;
blocking_nxt[0] = blocking[0];
end
RIGHT_D: begin
if(player_ypos % 40 == 0) begin
blocking_state_nxt = PREPARE;
special_nxt = SPECIAL;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
end
else begin
special_nxt = BLOCKING;
blocking_state_nxt = RIGHT_U;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos + 1;
end
blocking_nxt[3] = blocking[3];
blocking_nxt[2] = blocking[2];
blocking_nxt[1] = blocking[1];
if((player_xpos + plane_xpos_ofs) % 40 == 0)
blocking_nxt[0] = blocking_in;
else
blocking_nxt[0] = 0;
end
RIGHT_U: begin
special_nxt = SPECIAL;
blocking_state_nxt = PREPARE;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
blocking_nxt[3] = blocking[3];
blocking_nxt[2] = blocking[2];
blocking_nxt[1] = blocking[1];
if((player_xpos + plane_xpos_ofs) % 40 == 0)
blocking_nxt[0] = (blocking_in || blocking[0]);
else
blocking_nxt[0] = 0;
end
default: begin
blocking_state_nxt = PREPARE;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
blocking_nxt = blocking;
special_nxt = BLOCKING;
end
endcase
end
SPECIAL: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 0;
writing_phase_nxt = 2'b00;
block_we = 0;
old_block_nxt = 0;
write_block_nxt = 0;
case(blocking_state)
PREPARE: begin
blocking_state_nxt = START;
block_xpos_nxt = plane_xpos + (player_xpos + plane_xpos_ofs)/40;
block_ypos_nxt = player_ypos/40;
blocking_nxt = blocking;
special_nxt = SPECIAL;
modi_block_nxt = 0;
end
START: begin
blocking_state_nxt = DOWN_L;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos - 1;
blocking_nxt = blocking;
special_nxt = SPECIAL;
modi_block_nxt = 0;
end
DOWN_L: begin
special_nxt = SPECIAL;
blocking_nxt = blocking;
if((player_xpos + plane_xpos_ofs)%40 == 0) begin
blocking_state_nxt = UP_L;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos + 2;
end
else begin
block_xpos_nxt = block_xpos + 1;
blocking_state_nxt = DOWN_R;
block_ypos_nxt = block_ypos;
end
if(player_ypos % 40 == 0)
modi_block_nxt[47:42] = block_in;
else
modi_block_nxt[47:42] = 0;
modi_block_nxt[41:0] = 0;
end
DOWN_R: begin
special_nxt = SPECIAL;
blocking_nxt = blocking;
blocking_state_nxt = UP_L;
block_xpos_nxt = block_xpos - 1;
block_ypos_nxt = block_ypos + 2;
if(player_ypos % 40 == 0)
modi_block_nxt[41:36] = block_in;
else
modi_block_nxt[41:36] = 0;
modi_block_nxt[47:42] = modi_block[47:42];
modi_block_nxt[35:0] = 0;
end
UP_L: begin
special_nxt = SPECIAL;
blocking_nxt = blocking;
if((player_xpos + plane_xpos_ofs)%40 == 0) begin
blocking_state_nxt = LEFT_D;
block_xpos_nxt = block_xpos - 1;
block_ypos_nxt = block_ypos - 1;
end
else begin
block_xpos_nxt = block_xpos + 1;
blocking_state_nxt = UP_R;
block_ypos_nxt = block_ypos;
end
if(player_ypos % 40 == 0)
modi_block_nxt[35:30] = block_in;
else
modi_block_nxt[35:30] = 0;
modi_block_nxt[47:36] = modi_block[47:36];
modi_block_nxt[29:0] = 0;
end
UP_R: begin
special_nxt = SPECIAL;
blocking_nxt = blocking;
blocking_state_nxt = LEFT_D;
block_xpos_nxt = block_xpos - 2;
block_ypos_nxt = block_ypos - 1;
if(player_ypos % 40 == 0)
modi_block_nxt[29:24] = block_in;
else
modi_block_nxt[29:24] = 0;
modi_block_nxt[47:30] = modi_block[47:30];
modi_block_nxt[23:0] = 0;
end
LEFT_D: begin
special_nxt = SPECIAL;
blocking_nxt = blocking;
if(player_ypos % 40 == 0) begin
blocking_state_nxt = RIGHT_D;
block_xpos_nxt = block_xpos + 2;
block_ypos_nxt = block_ypos;
end
else begin
blocking_state_nxt = LEFT_U;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos + 1;
end
if((player_xpos + plane_xpos_ofs) % 40 == 0)
modi_block_nxt[23:18] = block_in;
else
modi_block_nxt[23:18] = 0;
modi_block_nxt[47:24] = modi_block[47:24];
modi_block_nxt[17:0] = 0;
end
LEFT_U: begin
special_nxt = SPECIAL;
blocking_nxt = blocking;
blocking_state_nxt = RIGHT_D;
block_xpos_nxt = block_xpos + 2;
block_ypos_nxt = block_ypos - 1;
if((player_xpos + plane_xpos_ofs) % 40 == 0)
modi_block_nxt[17:12] = block_in;
else
modi_block_nxt[17:12] = 0;
modi_block_nxt[47:18] = modi_block[47:18];
modi_block_nxt[11:0] = 0;
end
RIGHT_D: begin
blocking_nxt = blocking;
if(player_ypos % 40 == 0) begin
blocking_state_nxt = PREPARE;
special_nxt = MOD_BLOCK;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
end
else begin
special_nxt = SPECIAL;
blocking_state_nxt = RIGHT_U;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos + 1;
end
if((player_xpos + plane_xpos_ofs) % 40 == 0)
modi_block_nxt[11:6] = block_in;
else
modi_block_nxt[11:6] = 0;
modi_block_nxt[47:12] = modi_block[47:12];
modi_block_nxt[5:0] = 0;
end
RIGHT_U: begin
blocking_nxt = blocking;
blocking_state_nxt = PREPARE;
special_nxt = MOD_BLOCK;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
if((player_xpos + plane_xpos_ofs) % 40 == 0)
modi_block_nxt[5:0] = block_in;
else
modi_block_nxt[5:0] = block_in;
modi_block_nxt[47:6] = modi_block[47:6];
end
default: begin
special_nxt = BLOCKING;
blocking_state_nxt = PREPARE;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
end
endcase
end
MOD_BLOCK: begin
case(blocking_state)
PREPARE: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 0;
blocking_state_nxt = START;
block_xpos_nxt = plane_xpos + (player_xpos + plane_xpos_ofs)/40;
block_ypos_nxt = player_ypos/40;
blocking_nxt = blocking;
special_nxt = MOD_BLOCK;
modi_block_nxt = modi_block;
writing_phase_nxt = 2'b00;
old_block_nxt = 0;
block_we = 0;
write_block_nxt = 0;
end
START: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 0;
blocking_state_nxt = DOWN_L;
block_xpos_nxt = block_xpos;
block_ypos_nxt = block_ypos - 1;
blocking_nxt = blocking;
special_nxt = MOD_BLOCK;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
old_block_nxt = modi_block[47:42];
writing_phase_nxt = 2'b00;
block_we = 0;
end
DOWN_L: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 0;
special_nxt = MOD_BLOCK;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[47:42];
end
2'b01: begin
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[47:42];
end
2'b11: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos + 1;
blocking_state_nxt = DOWN_R;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[41:36];
end
default: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
DOWN_R: begin
left_right_block = 1;
position_changed_nxt = position_changed;
up_direction = 0;
special_nxt = MOD_BLOCK;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[41:36];
end
2'b01: begin
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[41:36];
end
2'b11: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos - 1;
blocking_state_nxt = UP_L;
block_ypos_nxt = block_ypos + 2;
old_block_nxt = modi_block[35:30];
end
default: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
UP_L: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 1;
special_nxt = MOD_BLOCK;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[35:30];
end
2'b01: begin
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[35:30];
end
2'b11: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos + 1;
blocking_state_nxt = UP_R;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[29:24];
end
default: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
UP_R: begin
left_right_block = 1;
position_changed_nxt = position_changed;
up_direction = 1;
special_nxt = MOD_BLOCK;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[29:24];
end
2'b01: begin
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[29:24];
end
2'b11: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos - 2;
blocking_state_nxt = LEFT_D;
block_ypos_nxt = block_ypos - 1;
old_block_nxt = modi_block[23:18];
end
default: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
LEFT_D: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 0;
special_nxt = MOD_BLOCK;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[23:18];
end
2'b01: begin
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[23:18];
end
2'b11: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos;
blocking_state_nxt = LEFT_U;
block_ypos_nxt = block_ypos + 1;
old_block_nxt = modi_block[17:12];
end
default: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
LEFT_U: begin
left_right_block = 0;
position_changed_nxt = position_changed;
up_direction = 0;
special_nxt = MOD_BLOCK;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[17:12];
end
2'b01: begin
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[17:12];
end
2'b11: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos + 2;
blocking_state_nxt = RIGHT_D;
block_ypos_nxt = block_ypos - 1;
old_block_nxt = modi_block[11:6];
end
default: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
RIGHT_D: begin
left_right_block = 1;
position_changed_nxt = position_changed;
up_direction = 0;
special_nxt = MOD_BLOCK;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[11:6];
end
2'b01: begin
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[11:6];
end
2'b11: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos;
blocking_state_nxt = RIGHT_U;
block_ypos_nxt = block_ypos + 1;
old_block_nxt = modi_block[5:0];
end
default: begin
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
RIGHT_U: begin
left_right_block = 1;
position_changed_nxt = 0;
up_direction = 0;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
write_block_nxt = new_block;
case(writing_phase)
2'b00: begin
special_nxt = MOD_BLOCK;
writing_phase_nxt = 2'b01;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[5:0];
end
2'b01: begin
special_nxt = MOD_BLOCK;
writing_phase_nxt = 2'b11;
block_we = new_block_we;
block_xpos_nxt = block_xpos;
blocking_state_nxt = blocking_state;
block_ypos_nxt = block_ypos;
old_block_nxt = modi_block[5:0];
end
2'b11: begin
special_nxt = BLOCKING;
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = block_xpos;
blocking_state_nxt = PREPARE;
block_ypos_nxt = block_ypos;
old_block_nxt = old_block;
end
default: begin
special_nxt = BLOCKING;
writing_phase_nxt = 2'b00;
block_we = 0;
block_xpos_nxt = 0;
blocking_state_nxt = PREPARE;
block_ypos_nxt = 0;
old_block_nxt = 0;
end
endcase
end
default: begin
left_right_block = 0;
position_changed_nxt = 0;
up_direction = 0;
write_block_nxt = 0;
special_nxt = BLOCKING;
blocking_state_nxt = PREPARE;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
blocking_nxt = blocking;
modi_block_nxt = modi_block;
writing_phase_nxt = 2'b00;
old_block_nxt = 0;
block_we = 0;
end
endcase
end
default: begin
left_right_block = 0;
position_changed_nxt = 0;
up_direction = 0;
write_block_nxt = 0;
block_we = 0;
modi_block_nxt = modi_block;
special_nxt = BLOCKING;
blocking_state_nxt = PREPARE;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
blocking_nxt = blocking;
writing_phase_nxt = 2'b00;
old_block_nxt = 0;
end
endcase
end
else begin
if(position_changed1)
position_changed_nxt = 1;
else
position_changed_nxt = 0;
left_right_block = 0;
up_direction = 0;
write_block_nxt = 0;
block_we = 0;
modi_block_nxt = modi_block;
special_nxt = BLOCKING;
blocking_state_nxt = PREPARE;
block_xpos_nxt = 0;
block_ypos_nxt = 0;
blocking_nxt = blocking;
writing_phase_nxt = 2'b00;
old_block_nxt = 0;
end
end
//*************************************
// End of logic for blocking the player
//*************************************
//Breaking the locks and getting points
wire [5:0] new_block;
reg [5:0] old_block, old_block_nxt;
reg up_direction, left_right_block;
new_block my_new_block(
.block_in(old_block),
.up_direction(up_direction),
.direction(left_right_block),
.block_out(new_block),
.relative_xpos(player_xpos + plane_xpos_ofs),
.relative_ypos(player_ypos),
.write_enable(new_block_we),
.new_point(new_point)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "image_processing_2d_design_auto_pc_2,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "image_processing_2d_design_auto_pc_2,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDT\
H=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_auto_pc_2 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A41OI_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A41OI_PP_SYMBOL_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a41oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input A4 ,
input B1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A41OI_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ui_top.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// Top level of simple user interface.
`timescale 1 ps / 1 ps
module ui_top #
(
parameter TCQ = 100,
parameter APP_DATA_WIDTH = 256,
parameter APP_MASK_WIDTH = 32,
parameter BANK_WIDTH = 3,
parameter COL_WIDTH = 12,
parameter CWL = 5,
parameter DATA_BUF_ADDR_WIDTH = 5,
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
parameter ORDERING = "NORM",
parameter nCK_PER_CLK = 2,
parameter RANKS = 4,
parameter REG_CTRL = "ON", // "ON" for registered DIMM
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"
)
(/*AUTOARG*/
// Outputs
wr_data_mask, wr_data, use_addr, size, row, raw_not_ecc, rank,
hi_priority, data_buf_addr, col, cmd, bank, app_wdf_rdy, app_rdy,
app_rd_data_valid, app_rd_data_end, app_rd_data,
app_ecc_multiple_err, correct_en,
// Inputs
wr_data_offset, wr_data_en, wr_data_addr, rst, rd_data_offset,
rd_data_end, rd_data_en, rd_data_addr, rd_data, ecc_multiple, clk,
app_wdf_wren, app_wdf_mask, app_wdf_end, app_wdf_data, app_sz,
app_raw_not_ecc, app_hi_pri, app_en, app_cmd, app_addr, accept_ns,
accept, app_correct_en
);
input accept;
localparam ADDR_WIDTH = RANK_WIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
// Add a cycle to CWL for the register in RDIMM devices
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
input app_correct_en;
output wire correct_en;
assign correct_en = app_correct_en;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input accept_ns; // To ui_cmd0 of ui_cmd.v
input [ADDR_WIDTH-1:0] app_addr; // To ui_cmd0 of ui_cmd.v
input [2:0] app_cmd; // To ui_cmd0 of ui_cmd.v
input app_en; // To ui_cmd0 of ui_cmd.v
input app_hi_pri; // To ui_cmd0 of ui_cmd.v
input [2*nCK_PER_CLK-1:0] app_raw_not_ecc; // To ui_wr_data0 of ui_wr_data.v
input app_sz; // To ui_cmd0 of ui_cmd.v
input [APP_DATA_WIDTH-1:0] app_wdf_data; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_end; // To ui_wr_data0 of ui_wr_data.v
input [APP_MASK_WIDTH-1:0] app_wdf_mask; // To ui_wr_data0 of ui_wr_data.v
input app_wdf_wren; // To ui_wr_data0 of ui_wr_data.v
input clk; // To ui_cmd0 of ui_cmd.v, ...
input [2*nCK_PER_CLK-1:0] ecc_multiple; // To ui_rd_data0 of ui_rd_data.v
input [APP_DATA_WIDTH-1:0] rd_data; // To ui_rd_data0 of ui_rd_data.v
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr; // To ui_rd_data0 of ui_rd_data.v
input rd_data_en; // To ui_rd_data0 of ui_rd_data.v
input rd_data_end; // To ui_rd_data0 of ui_rd_data.v
input rd_data_offset; // To ui_rd_data0 of ui_rd_data.v
input rst; // To ui_cmd0 of ui_cmd.v, ...
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr; // To ui_wr_data0 of ui_wr_data.v
input wr_data_en; // To ui_wr_data0 of ui_wr_data.v
input wr_data_offset; // To ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [2*nCK_PER_CLK-1:0] app_ecc_multiple_err; // From ui_rd_data0 of ui_rd_data.v
output [APP_DATA_WIDTH-1:0] app_rd_data; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_end; // From ui_rd_data0 of ui_rd_data.v
output app_rd_data_valid; // From ui_rd_data0 of ui_rd_data.v
output app_rdy; // From ui_cmd0 of ui_cmd.v
output app_wdf_rdy; // From ui_wr_data0 of ui_wr_data.v
output [BANK_WIDTH-1:0] bank; // From ui_cmd0 of ui_cmd.v
output [2:0] cmd; // From ui_cmd0 of ui_cmd.v
output [COL_WIDTH-1:0] col; // From ui_cmd0 of ui_cmd.v
output [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;// From ui_cmd0 of ui_cmd.v
output hi_priority; // From ui_cmd0 of ui_cmd.v
output [RANK_WIDTH-1:0] rank; // From ui_cmd0 of ui_cmd.v
output [2*nCK_PER_CLK-1:0] raw_not_ecc; // From ui_wr_data0 of ui_wr_data.v
output [ROW_WIDTH-1:0] row; // From ui_cmd0 of ui_cmd.v
output size; // From ui_cmd0 of ui_cmd.v
output use_addr; // From ui_cmd0 of ui_cmd.v
output [APP_DATA_WIDTH-1:0] wr_data; // From ui_wr_data0 of ui_wr_data.v
output [APP_MASK_WIDTH-1:0] wr_data_mask; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] ram_init_addr; // From ui_rd_data0 of ui_rd_data.v
wire ram_init_done_r; // From ui_rd_data0 of ui_rd_data.v
wire rd_accepted; // From ui_cmd0 of ui_cmd.v
wire rd_buf_full; // From ui_rd_data0 of ui_rd_data.v
wire [DATA_BUF_ADDR_WIDTH-1:0]rd_data_buf_addr_r;// From ui_rd_data0 of ui_rd_data.v
wire wr_accepted; // From ui_cmd0 of ui_cmd.v
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_buf_addr;// From ui_wr_data0 of ui_wr_data.v
wire wr_req_16; // From ui_wr_data0 of ui_wr_data.v
// End of automatics
// In the UI, the read and write buffers are allowed to be asymmetric to
// to maximize read performance, but the MC's native interface requires
// symmetry, so we zero-fill the write pointer
generate
if(DATA_BUF_ADDR_WIDTH > 4) begin
assign wr_data_buf_addr[DATA_BUF_ADDR_WIDTH-1:4] = 0;
end
endgenerate
ui_cmd #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.ADDR_WIDTH (ADDR_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.RANKS (RANKS),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER))
ui_cmd0
(/*AUTOINST*/
// Outputs
.app_rdy (app_rdy),
.use_addr (use_addr),
.rank (rank[RANK_WIDTH-1:0]),
.bank (bank[BANK_WIDTH-1:0]),
.row (row[ROW_WIDTH-1:0]),
.col (col[COL_WIDTH-1:0]),
.size (size),
.cmd (cmd[2:0]),
.hi_priority (hi_priority),
.rd_accepted (rd_accepted),
.wr_accepted (wr_accepted),
.data_buf_addr (data_buf_addr),
// Inputs
.rst (rst),
.clk (clk),
.accept_ns (accept_ns),
.rd_buf_full (rd_buf_full),
.wr_req_16 (wr_req_16),
.app_addr (app_addr[ADDR_WIDTH-1:0]),
.app_cmd (app_cmd[2:0]),
.app_sz (app_sz),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.wr_data_buf_addr (wr_data_buf_addr),
.rd_data_buf_addr_r (rd_data_buf_addr_r));
ui_wr_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.CWL (CWL_M))
ui_wr_data0
(/*AUTOINST*/
// Outputs
.app_wdf_rdy (app_wdf_rdy),
.wr_req_16 (wr_req_16),
.wr_data_buf_addr (wr_data_buf_addr[3:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1:0]),
// Inputs
.rst (rst),
.clk (clk),
.app_wdf_data (app_wdf_data[APP_DATA_WIDTH-1:0]),
.app_wdf_mask (app_wdf_mask[APP_MASK_WIDTH-1:0]),
.app_raw_not_ecc (app_raw_not_ecc[2*nCK_PER_CLK-1:0]),
.app_wdf_wren (app_wdf_wren),
.app_wdf_end (app_wdf_end),
.wr_data_offset (wr_data_offset),
.wr_data_addr (wr_data_addr[3:0]),
.wr_data_en (wr_data_en),
.wr_accepted (wr_accepted),
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr));
ui_rd_data #
(/*AUTOINSTPARAM*/
// Parameters
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.ECC (ECC),
.ORDERING (ORDERING))
ui_rd_data0
(/*AUTOINST*/
// Outputs
.ram_init_done_r (ram_init_done_r),
.ram_init_addr (ram_init_addr),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data[APP_DATA_WIDTH-1:0]),
.app_ecc_multiple_err (app_ecc_multiple_err[2*nCK_PER_CLK-1:0]),
.rd_buf_full (rd_buf_full),
.rd_data_buf_addr_r (rd_data_buf_addr_r),
// Inputs
.rst (rst),
.clk (clk),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple[3:0]),
.rd_accepted (rd_accepted));
endmodule // ui_top
// Local Variables:
// verilog-library-directories:("." "../mc")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21A_SYMBOL_V
`define SKY130_FD_SC_HS__O21A_SYMBOL_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21a (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21A_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__O21AI_FUNCTIONAL_PP_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o21ai (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , B1, or0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21AI_FUNCTIONAL_PP_V |
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 10/10/2009
// Modified: 3/20/2012
//
// Counter based debounce circuit originally written for EC551 (back
// in the day) and then modified (i.e. chagned entirely) into 3 always
// block format. This debouncer generates a signal that goes high for
// 1 clock cycle after the clock sees an asserted value on the button
// line. This action is then disabled until the counter hits a
// specified count value that is determined by the clock frequency and
// desired debounce frequency. An alternative implementation would not
// use a counter, but would use the shift register approach, looking
// for repeated matches (say 5) on the button line.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module button_debounce
(
input clk, // clock
input reset_n, // asynchronous reset
input button, // bouncy button
output reg debounce // debounced 1-cycle signal
);
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
// These parameters are specified such that you can choose any power
// of 2 frequency for a debouncer between 1 Hz and
// CLK_FREQUENCY. Note, that this will throw errors if you choose a
// non power of 2 frequency (i.e. count_value evaluates to some
// number / 3 which isn't interpreted as a logical right shift). I'm
// assuming this will not work for DEBOUNCE_HZ values less than 1,
// however, I'm uncertain of the value of a debouncer for fractional
// hertz button presses.
localparam
COUNT_VALUE = CLK_FREQUENCY / DEBOUNCE_HZ,
WAIT = 0,
FIRE = 1,
COUNT = 2;
reg [1:0] state, next_state;
reg [25:0] count;
always @ (posedge clk or negedge reset_n)
state <= (!reset_n) ? WAIT : next_state;
always @ (posedge clk or negedge reset_n) begin
if (!reset_n) begin
debounce <= 0;
count <= 0;
end
else begin
debounce <= 0;
count <= 0;
case (state)
WAIT: begin
end
FIRE: begin
debounce <= 1;
end
COUNT: begin
count <= count + 1;
end
endcase
end
end
always @ * begin
case (state)
WAIT: next_state = (button) ? FIRE : state;
FIRE: next_state = COUNT;
COUNT: next_state = (count > COUNT_VALUE - 1) ? WAIT : state;
default: next_state = WAIT;
endcase
end
endmodule
|
// soc_system_mm_interconnect_3.v
// This file was auto-generated from altera_merlin_interconnect_wrapper_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 13.1 162 at 2014.12.19.15:55:02
`timescale 1 ps / 1 ps
module soc_system_mm_interconnect_3 (
input wire [11:0] hps_0_h2f_lw_axi_master_awid, // hps_0_h2f_lw_axi_master.awid
input wire [20:0] hps_0_h2f_lw_axi_master_awaddr, // .awaddr
input wire [3:0] hps_0_h2f_lw_axi_master_awlen, // .awlen
input wire [2:0] hps_0_h2f_lw_axi_master_awsize, // .awsize
input wire [1:0] hps_0_h2f_lw_axi_master_awburst, // .awburst
input wire [1:0] hps_0_h2f_lw_axi_master_awlock, // .awlock
input wire [3:0] hps_0_h2f_lw_axi_master_awcache, // .awcache
input wire [2:0] hps_0_h2f_lw_axi_master_awprot, // .awprot
input wire hps_0_h2f_lw_axi_master_awvalid, // .awvalid
output wire hps_0_h2f_lw_axi_master_awready, // .awready
input wire [11:0] hps_0_h2f_lw_axi_master_wid, // .wid
input wire [31:0] hps_0_h2f_lw_axi_master_wdata, // .wdata
input wire [3:0] hps_0_h2f_lw_axi_master_wstrb, // .wstrb
input wire hps_0_h2f_lw_axi_master_wlast, // .wlast
input wire hps_0_h2f_lw_axi_master_wvalid, // .wvalid
output wire hps_0_h2f_lw_axi_master_wready, // .wready
output wire [11:0] hps_0_h2f_lw_axi_master_bid, // .bid
output wire [1:0] hps_0_h2f_lw_axi_master_bresp, // .bresp
output wire hps_0_h2f_lw_axi_master_bvalid, // .bvalid
input wire hps_0_h2f_lw_axi_master_bready, // .bready
input wire [11:0] hps_0_h2f_lw_axi_master_arid, // .arid
input wire [20:0] hps_0_h2f_lw_axi_master_araddr, // .araddr
input wire [3:0] hps_0_h2f_lw_axi_master_arlen, // .arlen
input wire [2:0] hps_0_h2f_lw_axi_master_arsize, // .arsize
input wire [1:0] hps_0_h2f_lw_axi_master_arburst, // .arburst
input wire [1:0] hps_0_h2f_lw_axi_master_arlock, // .arlock
input wire [3:0] hps_0_h2f_lw_axi_master_arcache, // .arcache
input wire [2:0] hps_0_h2f_lw_axi_master_arprot, // .arprot
input wire hps_0_h2f_lw_axi_master_arvalid, // .arvalid
output wire hps_0_h2f_lw_axi_master_arready, // .arready
output wire [11:0] hps_0_h2f_lw_axi_master_rid, // .rid
output wire [31:0] hps_0_h2f_lw_axi_master_rdata, // .rdata
output wire [1:0] hps_0_h2f_lw_axi_master_rresp, // .rresp
output wire hps_0_h2f_lw_axi_master_rlast, // .rlast
output wire hps_0_h2f_lw_axi_master_rvalid, // .rvalid
input wire hps_0_h2f_lw_axi_master_rready, // .rready
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire system_pll_outclk0_clk, // system_pll_outclk0.clk
input wire fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset, // fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset.reset
input wire hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset, // hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset.reset
output wire [7:0] fifo_bridge_cpuM_cpus0_s1_address, // fifo_bridge_cpuM_cpus0_s1.address
output wire fifo_bridge_cpuM_cpus0_s1_write, // .write
output wire fifo_bridge_cpuM_cpus0_s1_read, // .read
input wire [31:0] fifo_bridge_cpuM_cpus0_s1_readdata, // .readdata
output wire [31:0] fifo_bridge_cpuM_cpus0_s1_writedata, // .writedata
output wire [7:0] fifo_bridge_cpuM_cpus1_s1_address, // fifo_bridge_cpuM_cpus1_s1.address
output wire fifo_bridge_cpuM_cpus1_s1_write, // .write
output wire fifo_bridge_cpuM_cpus1_s1_read, // .read
input wire [31:0] fifo_bridge_cpuM_cpus1_s1_readdata, // .readdata
output wire [31:0] fifo_bridge_cpuM_cpus1_s1_writedata // .writedata
);
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // fifo_bridge_cpuM_cpus0_s1_translator:uav_waitrequest -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> fifo_bridge_cpuM_cpus0_s1_translator:uav_burstcount
wire [31:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> fifo_bridge_cpuM_cpus0_s1_translator:uav_writedata
wire [20:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_address -> fifo_bridge_cpuM_cpus0_s1_translator:uav_address
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_write -> fifo_bridge_cpuM_cpus0_s1_translator:uav_write
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> fifo_bridge_cpuM_cpus0_s1_translator:uav_lock
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_read -> fifo_bridge_cpuM_cpus0_s1_translator:uav_read
wire [31:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // fifo_bridge_cpuM_cpus0_s1_translator:uav_readdata -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // fifo_bridge_cpuM_cpus0_s1_translator:uav_readdatavalid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fifo_bridge_cpuM_cpus0_s1_translator:uav_debugaccess
wire [3:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> fifo_bridge_cpuM_cpus0_s1_translator:uav_byteenable
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [112:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [112:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [33:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // fifo_bridge_cpuM_cpus1_s1_translator:uav_waitrequest -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> fifo_bridge_cpuM_cpus1_s1_translator:uav_burstcount
wire [31:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> fifo_bridge_cpuM_cpus1_s1_translator:uav_writedata
wire [20:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_address -> fifo_bridge_cpuM_cpus1_s1_translator:uav_address
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_write -> fifo_bridge_cpuM_cpus1_s1_translator:uav_write
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_lock -> fifo_bridge_cpuM_cpus1_s1_translator:uav_lock
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_read -> fifo_bridge_cpuM_cpus1_s1_translator:uav_read
wire [31:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // fifo_bridge_cpuM_cpus1_s1_translator:uav_readdata -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // fifo_bridge_cpuM_cpus1_s1_translator:uav_readdatavalid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> fifo_bridge_cpuM_cpus1_s1_translator:uav_debugaccess
wire [3:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> fifo_bridge_cpuM_cpus1_s1_translator:uav_byteenable
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [112:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [112:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [33:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_endofpacket -> addr_router:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_write_cp_valid; // hps_0_h2f_lw_axi_master_agent:write_cp_valid -> addr_router:sink_valid
wire hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:write_cp_startofpacket -> addr_router:sink_startofpacket
wire [111:0] hps_0_h2f_lw_axi_master_agent_write_cp_data; // hps_0_h2f_lw_axi_master_agent:write_cp_data -> addr_router:sink_data
wire hps_0_h2f_lw_axi_master_agent_write_cp_ready; // addr_router:sink_ready -> hps_0_h2f_lw_axi_master_agent:write_cp_ready
wire hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_endofpacket -> addr_router_001:sink_endofpacket
wire hps_0_h2f_lw_axi_master_agent_read_cp_valid; // hps_0_h2f_lw_axi_master_agent:read_cp_valid -> addr_router_001:sink_valid
wire hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket; // hps_0_h2f_lw_axi_master_agent:read_cp_startofpacket -> addr_router_001:sink_startofpacket
wire [111:0] hps_0_h2f_lw_axi_master_agent_read_cp_data; // hps_0_h2f_lw_axi_master_agent:read_cp_data -> addr_router_001:sink_data
wire hps_0_h2f_lw_axi_master_agent_read_cp_ready; // addr_router_001:sink_ready -> hps_0_h2f_lw_axi_master_agent:read_cp_ready
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [111:0] fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [111:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [1:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [111:0] fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> rsp_xbar_demux_001:sink_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [111:0] id_router_001_src_data; // id_router_001:src_data -> rsp_xbar_demux_001:sink_data
wire [1:0] id_router_001_src_channel; // id_router_001:src_channel -> rsp_xbar_demux_001:sink_channel
wire id_router_001_src_ready; // rsp_xbar_demux_001:sink_ready -> id_router_001:src_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> limiter:cmd_sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> limiter:cmd_sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> limiter:cmd_sink_startofpacket
wire [111:0] addr_router_src_data; // addr_router:src_data -> limiter:cmd_sink_data
wire [1:0] addr_router_src_channel; // addr_router:src_channel -> limiter:cmd_sink_channel
wire addr_router_src_ready; // limiter:cmd_sink_ready -> addr_router:src_ready
wire limiter_cmd_src_endofpacket; // limiter:cmd_src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire limiter_cmd_src_startofpacket; // limiter:cmd_src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [111:0] limiter_cmd_src_data; // limiter:cmd_src_data -> cmd_xbar_demux:sink_data
wire [1:0] limiter_cmd_src_channel; // limiter:cmd_src_channel -> cmd_xbar_demux:sink_channel
wire limiter_cmd_src_ready; // cmd_xbar_demux:sink_ready -> limiter:cmd_src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> limiter:rsp_sink_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> limiter:rsp_sink_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> limiter:rsp_sink_startofpacket
wire [111:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> limiter:rsp_sink_data
wire [1:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> limiter:rsp_sink_channel
wire rsp_xbar_mux_src_ready; // limiter:rsp_sink_ready -> rsp_xbar_mux:src_ready
wire limiter_rsp_src_endofpacket; // limiter:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_endofpacket
wire limiter_rsp_src_valid; // limiter:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:write_rp_valid
wire limiter_rsp_src_startofpacket; // limiter:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:write_rp_startofpacket
wire [111:0] limiter_rsp_src_data; // limiter:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:write_rp_data
wire [1:0] limiter_rsp_src_channel; // limiter:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:write_rp_channel
wire limiter_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:write_rp_ready -> limiter:rsp_src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> limiter_001:cmd_sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> limiter_001:cmd_sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> limiter_001:cmd_sink_startofpacket
wire [111:0] addr_router_001_src_data; // addr_router_001:src_data -> limiter_001:cmd_sink_data
wire [1:0] addr_router_001_src_channel; // addr_router_001:src_channel -> limiter_001:cmd_sink_channel
wire addr_router_001_src_ready; // limiter_001:cmd_sink_ready -> addr_router_001:src_ready
wire limiter_001_cmd_src_endofpacket; // limiter_001:cmd_src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire limiter_001_cmd_src_startofpacket; // limiter_001:cmd_src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [111:0] limiter_001_cmd_src_data; // limiter_001:cmd_src_data -> cmd_xbar_demux_001:sink_data
wire [1:0] limiter_001_cmd_src_channel; // limiter_001:cmd_src_channel -> cmd_xbar_demux_001:sink_channel
wire limiter_001_cmd_src_ready; // cmd_xbar_demux_001:sink_ready -> limiter_001:cmd_src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> limiter_001:rsp_sink_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> limiter_001:rsp_sink_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> limiter_001:rsp_sink_startofpacket
wire [111:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> limiter_001:rsp_sink_data
wire [1:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> limiter_001:rsp_sink_channel
wire rsp_xbar_mux_001_src_ready; // limiter_001:rsp_sink_ready -> rsp_xbar_mux_001:src_ready
wire limiter_001_rsp_src_endofpacket; // limiter_001:rsp_src_endofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_endofpacket
wire limiter_001_rsp_src_valid; // limiter_001:rsp_src_valid -> hps_0_h2f_lw_axi_master_agent:read_rp_valid
wire limiter_001_rsp_src_startofpacket; // limiter_001:rsp_src_startofpacket -> hps_0_h2f_lw_axi_master_agent:read_rp_startofpacket
wire [111:0] limiter_001_rsp_src_data; // limiter_001:rsp_src_data -> hps_0_h2f_lw_axi_master_agent:read_rp_data
wire [1:0] limiter_001_rsp_src_channel; // limiter_001:rsp_src_channel -> hps_0_h2f_lw_axi_master_agent:read_rp_channel
wire limiter_001_rsp_src_ready; // hps_0_h2f_lw_axi_master_agent:read_rp_ready -> limiter_001:rsp_src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> burst_adapter:sink0_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> burst_adapter:sink0_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> burst_adapter:sink0_startofpacket
wire [111:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> burst_adapter:sink0_data
wire [1:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> burst_adapter:sink0_channel
wire cmd_xbar_mux_src_ready; // burst_adapter:sink0_ready -> cmd_xbar_mux:src_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [111:0] burst_adapter_source0_data; // burst_adapter:source0_data -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [1:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> fifo_bridge_cpuM_cpus0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> burst_adapter_001:sink0_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> burst_adapter_001:sink0_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> burst_adapter_001:sink0_startofpacket
wire [111:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> burst_adapter_001:sink0_data
wire [1:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> burst_adapter_001:sink0_channel
wire cmd_xbar_mux_001_src_ready; // burst_adapter_001:sink0_ready -> cmd_xbar_mux_001:src_ready
wire burst_adapter_001_source0_endofpacket; // burst_adapter_001:source0_endofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_001_source0_valid; // burst_adapter_001:source0_valid -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_001_source0_startofpacket; // burst_adapter_001:source0_startofpacket -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [111:0] burst_adapter_001_source0_data; // burst_adapter_001:source0_data -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_001_source0_ready; // fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
wire [1:0] burst_adapter_001_source0_channel; // burst_adapter_001:source0_channel -> fifo_bridge_cpuM_cpus1_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> crosser:in_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> crosser:in_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> crosser:in_startofpacket
wire [111:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> crosser:in_data
wire [1:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> crosser:in_channel
wire cmd_xbar_demux_src0_ready; // crosser:in_ready -> cmd_xbar_demux:src0_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_xbar_mux:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [111:0] crosser_out_data; // crosser:out_data -> cmd_xbar_mux:sink0_data
wire [1:0] crosser_out_channel; // crosser:out_channel -> cmd_xbar_mux:sink0_channel
wire crosser_out_ready; // cmd_xbar_mux:sink0_ready -> crosser:out_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> crosser_001:in_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> crosser_001:in_startofpacket
wire [111:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> crosser_001:in_data
wire [1:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> crosser_001:in_channel
wire cmd_xbar_demux_src1_ready; // crosser_001:in_ready -> cmd_xbar_demux:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_xbar_mux_001:sink0_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [111:0] crosser_001_out_data; // crosser_001:out_data -> cmd_xbar_mux_001:sink0_data
wire [1:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_xbar_mux_001:sink0_channel
wire crosser_001_out_ready; // cmd_xbar_mux_001:sink0_ready -> crosser_001:out_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> crosser_002:in_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> crosser_002:in_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> crosser_002:in_startofpacket
wire [111:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> crosser_002:in_data
wire [1:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> crosser_002:in_channel
wire cmd_xbar_demux_001_src0_ready; // crosser_002:in_ready -> cmd_xbar_demux_001:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> cmd_xbar_mux:sink1_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [111:0] crosser_002_out_data; // crosser_002:out_data -> cmd_xbar_mux:sink1_data
wire [1:0] crosser_002_out_channel; // crosser_002:out_channel -> cmd_xbar_mux:sink1_channel
wire crosser_002_out_ready; // cmd_xbar_mux:sink1_ready -> crosser_002:out_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> crosser_003:in_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> crosser_003:in_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> crosser_003:in_startofpacket
wire [111:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> crosser_003:in_data
wire [1:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> crosser_003:in_channel
wire cmd_xbar_demux_001_src1_ready; // crosser_003:in_ready -> cmd_xbar_demux_001:src1_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> cmd_xbar_mux_001:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [111:0] crosser_003_out_data; // crosser_003:out_data -> cmd_xbar_mux_001:sink1_data
wire [1:0] crosser_003_out_channel; // crosser_003:out_channel -> cmd_xbar_mux_001:sink1_channel
wire crosser_003_out_ready; // cmd_xbar_mux_001:sink1_ready -> crosser_003:out_ready
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> crosser_004:in_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> crosser_004:in_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> crosser_004:in_startofpacket
wire [111:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> crosser_004:in_data
wire [1:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> crosser_004:in_channel
wire rsp_xbar_demux_src0_ready; // crosser_004:in_ready -> rsp_xbar_demux:src0_ready
wire crosser_004_out_endofpacket; // crosser_004:out_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire crosser_004_out_valid; // crosser_004:out_valid -> rsp_xbar_mux:sink0_valid
wire crosser_004_out_startofpacket; // crosser_004:out_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [111:0] crosser_004_out_data; // crosser_004:out_data -> rsp_xbar_mux:sink0_data
wire [1:0] crosser_004_out_channel; // crosser_004:out_channel -> rsp_xbar_mux:sink0_channel
wire crosser_004_out_ready; // rsp_xbar_mux:sink0_ready -> crosser_004:out_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> crosser_005:in_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> crosser_005:in_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> crosser_005:in_startofpacket
wire [111:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> crosser_005:in_data
wire [1:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> crosser_005:in_channel
wire rsp_xbar_demux_src1_ready; // crosser_005:in_ready -> rsp_xbar_demux:src1_ready
wire crosser_005_out_endofpacket; // crosser_005:out_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire crosser_005_out_valid; // crosser_005:out_valid -> rsp_xbar_mux_001:sink0_valid
wire crosser_005_out_startofpacket; // crosser_005:out_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [111:0] crosser_005_out_data; // crosser_005:out_data -> rsp_xbar_mux_001:sink0_data
wire [1:0] crosser_005_out_channel; // crosser_005:out_channel -> rsp_xbar_mux_001:sink0_channel
wire crosser_005_out_ready; // rsp_xbar_mux_001:sink0_ready -> crosser_005:out_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> crosser_006:in_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> crosser_006:in_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> crosser_006:in_startofpacket
wire [111:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> crosser_006:in_data
wire [1:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> crosser_006:in_channel
wire rsp_xbar_demux_001_src0_ready; // crosser_006:in_ready -> rsp_xbar_demux_001:src0_ready
wire crosser_006_out_endofpacket; // crosser_006:out_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire crosser_006_out_valid; // crosser_006:out_valid -> rsp_xbar_mux:sink1_valid
wire crosser_006_out_startofpacket; // crosser_006:out_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [111:0] crosser_006_out_data; // crosser_006:out_data -> rsp_xbar_mux:sink1_data
wire [1:0] crosser_006_out_channel; // crosser_006:out_channel -> rsp_xbar_mux:sink1_channel
wire crosser_006_out_ready; // rsp_xbar_mux:sink1_ready -> crosser_006:out_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> crosser_007:in_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> crosser_007:in_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> crosser_007:in_startofpacket
wire [111:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> crosser_007:in_data
wire [1:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> crosser_007:in_channel
wire rsp_xbar_demux_001_src1_ready; // crosser_007:in_ready -> rsp_xbar_demux_001:src1_ready
wire crosser_007_out_endofpacket; // crosser_007:out_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire crosser_007_out_valid; // crosser_007:out_valid -> rsp_xbar_mux_001:sink1_valid
wire crosser_007_out_startofpacket; // crosser_007:out_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [111:0] crosser_007_out_data; // crosser_007:out_data -> rsp_xbar_mux_001:sink1_data
wire [1:0] crosser_007_out_channel; // crosser_007:out_channel -> rsp_xbar_mux_001:sink1_channel
wire crosser_007_out_ready; // rsp_xbar_mux_001:sink1_ready -> crosser_007:out_ready
wire [1:0] limiter_cmd_valid_data; // limiter:cmd_src_valid -> cmd_xbar_demux:sink_valid
wire [1:0] limiter_001_cmd_valid_data; // limiter_001:cmd_src_valid -> cmd_xbar_demux_001:sink_valid
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) fifo_bridge_cpum_cpus0_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (fifo_bridge_cpuM_cpus0_s1_address), // avalon_anti_slave_0.address
.av_write (fifo_bridge_cpuM_cpus0_s1_write), // .write
.av_read (fifo_bridge_cpuM_cpus0_s1_read), // .read
.av_readdata (fifo_bridge_cpuM_cpus0_s1_readdata), // .readdata
.av_writedata (fifo_bridge_cpuM_cpus0_s1_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (21),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) fifo_bridge_cpum_cpus1_s1_translator (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (fifo_bridge_cpuM_cpus1_s1_address), // avalon_anti_slave_0.address
.av_write (fifo_bridge_cpuM_cpus1_s1_write), // .write
.av_read (fifo_bridge_cpuM_cpus1_s1_read), // .read
.av_readdata (fifo_bridge_cpuM_cpus1_s1_readdata), // .readdata
.av_writedata (fifo_bridge_cpuM_cpus1_s1_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_axi_master_ni #(
.ID_WIDTH (12),
.ADDR_WIDTH (21),
.RDATA_WIDTH (32),
.WDATA_WIDTH (32),
.ADDR_USER_WIDTH (1),
.DATA_USER_WIDTH (1),
.AXI_BURST_LENGTH_WIDTH (4),
.AXI_LOCK_WIDTH (2),
.AXI_VERSION ("AXI3"),
.WRITE_ISSUING_CAPABILITY (8),
.READ_ISSUING_CAPABILITY (8),
.PKT_BEGIN_BURST (84),
.PKT_CACHE_H (106),
.PKT_CACHE_L (103),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_RESPONSE_STATUS_L (107),
.PKT_RESPONSE_STATUS_H (108),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_EXCLUSIVE (62),
.PKT_TRANS_LOCK (61),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_THREAD_ID_H (99),
.PKT_THREAD_ID_L (88),
.PKT_QOS_L (85),
.PKT_QOS_H (85),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.ID (0)
) hps_0_h2f_lw_axi_master_agent (
.aclk (clk_0_clk_clk), // clk.clk
.aresetn (~hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset_n
.write_cp_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // write_cp.valid
.write_cp_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.write_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.write_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.write_cp_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // .ready
.write_rp_valid (limiter_rsp_src_valid), // write_rp.valid
.write_rp_data (limiter_rsp_src_data), // .data
.write_rp_channel (limiter_rsp_src_channel), // .channel
.write_rp_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.write_rp_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.write_rp_ready (limiter_rsp_src_ready), // .ready
.read_cp_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // read_cp.valid
.read_cp_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.read_cp_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.read_cp_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.read_cp_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // .ready
.read_rp_valid (limiter_001_rsp_src_valid), // read_rp.valid
.read_rp_data (limiter_001_rsp_src_data), // .data
.read_rp_channel (limiter_001_rsp_src_channel), // .channel
.read_rp_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.read_rp_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.read_rp_ready (limiter_001_rsp_src_ready), // .ready
.awid (hps_0_h2f_lw_axi_master_awid), // altera_axi_slave.awid
.awaddr (hps_0_h2f_lw_axi_master_awaddr), // .awaddr
.awlen (hps_0_h2f_lw_axi_master_awlen), // .awlen
.awsize (hps_0_h2f_lw_axi_master_awsize), // .awsize
.awburst (hps_0_h2f_lw_axi_master_awburst), // .awburst
.awlock (hps_0_h2f_lw_axi_master_awlock), // .awlock
.awcache (hps_0_h2f_lw_axi_master_awcache), // .awcache
.awprot (hps_0_h2f_lw_axi_master_awprot), // .awprot
.awvalid (hps_0_h2f_lw_axi_master_awvalid), // .awvalid
.awready (hps_0_h2f_lw_axi_master_awready), // .awready
.wid (hps_0_h2f_lw_axi_master_wid), // .wid
.wdata (hps_0_h2f_lw_axi_master_wdata), // .wdata
.wstrb (hps_0_h2f_lw_axi_master_wstrb), // .wstrb
.wlast (hps_0_h2f_lw_axi_master_wlast), // .wlast
.wvalid (hps_0_h2f_lw_axi_master_wvalid), // .wvalid
.wready (hps_0_h2f_lw_axi_master_wready), // .wready
.bid (hps_0_h2f_lw_axi_master_bid), // .bid
.bresp (hps_0_h2f_lw_axi_master_bresp), // .bresp
.bvalid (hps_0_h2f_lw_axi_master_bvalid), // .bvalid
.bready (hps_0_h2f_lw_axi_master_bready), // .bready
.arid (hps_0_h2f_lw_axi_master_arid), // .arid
.araddr (hps_0_h2f_lw_axi_master_araddr), // .araddr
.arlen (hps_0_h2f_lw_axi_master_arlen), // .arlen
.arsize (hps_0_h2f_lw_axi_master_arsize), // .arsize
.arburst (hps_0_h2f_lw_axi_master_arburst), // .arburst
.arlock (hps_0_h2f_lw_axi_master_arlock), // .arlock
.arcache (hps_0_h2f_lw_axi_master_arcache), // .arcache
.arprot (hps_0_h2f_lw_axi_master_arprot), // .arprot
.arvalid (hps_0_h2f_lw_axi_master_arvalid), // .arvalid
.arready (hps_0_h2f_lw_axi_master_arready), // .arready
.rid (hps_0_h2f_lw_axi_master_rid), // .rid
.rdata (hps_0_h2f_lw_axi_master_rdata), // .rdata
.rresp (hps_0_h2f_lw_axi_master_rresp), // .rresp
.rlast (hps_0_h2f_lw_axi_master_rlast), // .rlast
.rvalid (hps_0_h2f_lw_axi_master_rvalid), // .rvalid
.rready (hps_0_h2f_lw_axi_master_rready), // .rready
.awuser (1'b0), // (terminated)
.aruser (1'b0), // (terminated)
.awqos (4'b0000), // (terminated)
.arqos (4'b0000), // (terminated)
.awregion (4'b0000), // (terminated)
.arregion (4'b0000), // (terminated)
.wuser (8'b00000000), // (terminated)
.ruser (), // (terminated)
.buser () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_RESPONSE_STATUS_H (108),
.PKT_RESPONSE_STATUS_L (107),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.ST_CHANNEL_W (2),
.ST_DATA_W (112),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (113),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.PKT_TRANS_LOCK (61),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_PROTECTION_H (102),
.PKT_PROTECTION_L (100),
.PKT_RESPONSE_STATUS_H (108),
.PKT_RESPONSE_STATUS_L (107),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (109),
.PKT_ORI_BURST_SIZE_H (111),
.ST_CHANNEL_W (2),
.ST_DATA_W (112),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_001_source0_ready), // cp.ready
.cp_valid (burst_adapter_001_source0_valid), // .valid
.cp_data (burst_adapter_001_source0_data), // .data
.cp_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_001_source0_channel), // .channel
.rf_sink_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (113),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
soc_system_mm_interconnect_3_addr_router addr_router (
.sink_ready (hps_0_h2f_lw_axi_master_agent_write_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_write_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_write_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_write_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_addr_router addr_router_001 (
.sink_ready (hps_0_h2f_lw_axi_master_agent_read_cp_ready), // sink.ready
.sink_valid (hps_0_h2f_lw_axi_master_agent_read_cp_valid), // .valid
.sink_data (hps_0_h2f_lw_axi_master_agent_read_cp_data), // .data
.sink_startofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_startofpacket), // .startofpacket
.sink_endofpacket (hps_0_h2f_lw_axi_master_agent_read_cp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_id_router id_router (
.sink_ready (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (fifo_bridge_cpum_cpus0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_id_router id_router_001 (
.sink_ready (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (fifo_bridge_cpum_cpus1_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_src_valid), // .valid
.cmd_sink_data (addr_router_src_data), // .data
.cmd_sink_channel (addr_router_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_cmd_src_data), // .data
.cmd_src_channel (limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_rsp_src_valid), // .valid
.rsp_src_data (limiter_rsp_src_data), // .data
.rsp_src_channel (limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (87),
.PKT_DEST_ID_L (87),
.PKT_SRC_ID_H (86),
.PKT_SRC_ID_L (86),
.PKT_TRANS_POSTED (58),
.PKT_TRANS_WRITE (59),
.MAX_OUTSTANDING_RESPONSES (7),
.PIPELINED (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.VALID_WIDTH (2),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.REORDER (0)
) limiter_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (addr_router_001_src_ready), // cmd_sink.ready
.cmd_sink_valid (addr_router_001_src_valid), // .valid
.cmd_sink_data (addr_router_001_src_data), // .data
.cmd_sink_channel (addr_router_001_src_channel), // .channel
.cmd_sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.cmd_src_ready (limiter_001_cmd_src_ready), // cmd_src.ready
.cmd_src_data (limiter_001_cmd_src_data), // .data
.cmd_src_channel (limiter_001_cmd_src_channel), // .channel
.cmd_src_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_xbar_mux_001_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_xbar_mux_001_src_valid), // .valid
.rsp_sink_channel (rsp_xbar_mux_001_src_channel), // .channel
.rsp_sink_data (rsp_xbar_mux_001_src_data), // .data
.rsp_sink_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rsp_src_ready (limiter_001_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (limiter_001_rsp_src_valid), // .valid
.rsp_src_data (limiter_001_rsp_src_data), // .data
.rsp_src_channel (limiter_001_rsp_src_channel), // .channel
.rsp_src_startofpacket (limiter_001_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (limiter_001_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (limiter_001_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_src_data), // .data
.sink0_channel (cmd_xbar_mux_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (56),
.PKT_ADDR_L (36),
.PKT_BEGIN_BURST (84),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (63),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (70),
.PKT_TRANS_COMPRESSED_READ (57),
.PKT_TRANS_WRITE (59),
.PKT_TRANS_READ (60),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (1),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (112),
.ST_CHANNEL_W (2),
.OUT_BYTE_CNT_H (65),
.OUT_BURSTWRAP_H (76),
.COMPRESSED_READ_SUPPORT (1),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (0),
.BURSTWRAP_CONST_VALUE (0)
) burst_adapter_001 (
.clk (system_pll_outclk0_clk), // cr0.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_xbar_mux_001_src_valid), // sink0.valid
.sink0_data (cmd_xbar_mux_001_src_data), // .data
.sink0_channel (cmd_xbar_mux_001_src_channel), // .channel
.sink0_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_mux_001_src_ready), // .ready
.source0_valid (burst_adapter_001_source0_valid), // source0.valid
.source0_data (burst_adapter_001_source0_data), // .data
.source0_channel (burst_adapter_001_source0_channel), // .channel
.source0_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_001_source0_ready) // .ready
);
soc_system_mm_interconnect_3_cmd_xbar_demux cmd_xbar_demux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_cmd_src_ready), // sink.ready
.sink_channel (limiter_cmd_src_channel), // .channel
.sink_data (limiter_cmd_src_data), // .data
.sink_startofpacket (limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_cmd_xbar_demux cmd_xbar_demux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (limiter_001_cmd_src_ready), // sink.ready
.sink_channel (limiter_001_cmd_src_channel), // .channel
.sink_data (limiter_001_cmd_src_data), // .data
.sink_startofpacket (limiter_001_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (limiter_001_cmd_src_endofpacket), // .endofpacket
.sink_valid (limiter_001_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_cmd_xbar_mux cmd_xbar_mux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (crosser_002_out_ready), // sink1.ready
.sink1_valid (crosser_002_out_valid), // .valid
.sink1_channel (crosser_002_out_channel), // .channel
.sink1_data (crosser_002_out_data), // .data
.sink1_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_002_out_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_001_out_ready), // sink0.ready
.sink0_valid (crosser_001_out_valid), // .valid
.sink0_channel (crosser_001_out_channel), // .channel
.sink0_data (crosser_001_out_data), // .data
.sink0_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_demux rsp_xbar_demux (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (system_pll_outclk0_clk), // clk.clk
.reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (id_router_001_src_ready), // sink.ready
.sink_channel (id_router_001_src_channel), // .channel
.sink_data (id_router_001_src_data), // .data
.sink_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.sink_valid (id_router_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_mux rsp_xbar_mux (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (crosser_004_out_ready), // sink0.ready
.sink0_valid (crosser_004_out_valid), // .valid
.sink0_channel (crosser_004_out_channel), // .channel
.sink0_data (crosser_004_out_data), // .data
.sink0_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.sink1_ready (crosser_006_out_ready), // sink1.ready
.sink1_valid (crosser_006_out_valid), // .valid
.sink1_channel (crosser_006_out_channel), // .channel
.sink1_data (crosser_006_out_data), // .data
.sink1_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_006_out_endofpacket) // .endofpacket
);
soc_system_mm_interconnect_3_rsp_xbar_mux rsp_xbar_mux_001 (
.clk (clk_0_clk_clk), // clk.clk
.reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_005_out_ready), // sink0.ready
.sink0_valid (crosser_005_out_valid), // .valid
.sink0_channel (crosser_005_out_channel), // .channel
.sink0_data (crosser_005_out_data), // .data
.sink0_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.sink1_ready (crosser_007_out_ready), // sink1.ready
.sink1_valid (crosser_007_out_valid), // .valid
.sink1_channel (crosser_007_out_channel), // .channel
.sink1_data (crosser_007_out_data), // .data
.sink1_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_007_out_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_src0_ready), // in.ready
.in_valid (cmd_xbar_demux_src0_valid), // .valid
.in_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_src0_channel), // .channel
.in_data (cmd_xbar_demux_src0_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_src1_ready), // in.ready
.in_valid (cmd_xbar_demux_src1_valid), // .valid
.in_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_src1_channel), // .channel
.in_data (cmd_xbar_demux_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_001_src0_ready), // in.ready
.in_valid (cmd_xbar_demux_001_src0_valid), // .valid
.in_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_001_src0_channel), // .channel
.in_data (cmd_xbar_demux_001_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (system_pll_outclk0_clk), // out_clk.clk
.out_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_001_src1_ready), // in.ready
.in_valid (cmd_xbar_demux_001_src1_valid), // .valid
.in_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_001_src1_channel), // .channel
.in_data (cmd_xbar_demux_001_src1_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_004 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_src0_ready), // in.ready
.in_valid (rsp_xbar_demux_src0_valid), // .valid
.in_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_src0_channel), // .channel
.in_data (rsp_xbar_demux_src0_data), // .data
.out_ready (crosser_004_out_ready), // out.ready
.out_valid (crosser_004_out_valid), // .valid
.out_startofpacket (crosser_004_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_004_out_endofpacket), // .endofpacket
.out_channel (crosser_004_out_channel), // .channel
.out_data (crosser_004_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_005 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_src1_ready), // in.ready
.in_valid (rsp_xbar_demux_src1_valid), // .valid
.in_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_src1_channel), // .channel
.in_data (rsp_xbar_demux_src1_data), // .data
.out_ready (crosser_005_out_ready), // out.ready
.out_valid (crosser_005_out_valid), // .valid
.out_startofpacket (crosser_005_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_005_out_endofpacket), // .endofpacket
.out_channel (crosser_005_out_channel), // .channel
.out_data (crosser_005_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_006 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_001_src0_ready), // in.ready
.in_valid (rsp_xbar_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_001_src0_channel), // .channel
.in_data (rsp_xbar_demux_001_src0_data), // .data
.out_ready (crosser_006_out_ready), // out.ready
.out_valid (crosser_006_out_valid), // .valid
.out_startofpacket (crosser_006_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_006_out_endofpacket), // .endofpacket
.out_channel (crosser_006_out_channel), // .channel
.out_data (crosser_006_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (112),
.BITS_PER_SYMBOL (112),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (2),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_007 (
.in_clk (system_pll_outclk0_clk), // in_clk.clk
.in_reset (fifo_bridge_cpuM_cpus0_clock_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_001_src1_ready), // in.ready
.in_valid (rsp_xbar_demux_001_src1_valid), // .valid
.in_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_001_src1_channel), // .channel
.in_data (rsp_xbar_demux_001_src1_data), // .data
.out_ready (crosser_007_out_ready), // out.ready
.out_valid (crosser_007_out_valid), // .valid
.out_startofpacket (crosser_007_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_007_out_endofpacket), // .endofpacket
.out_channel (crosser_007_out_channel), // .channel
.out_data (crosser_007_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_14_top,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_us_0,axi_dwidth_converter_v2_1_14_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_us_0,axi_dwidth_converter_v2_1_14_top,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_M_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=16,C\
_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_us_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_14_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(32),
.C_S_AXI_DATA_WIDTH(32),
.C_M_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(16),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// File: fifoStatus.v
// Generated by MyHDL 0.10
// Date: Mon Aug 27 20:11:12 2018
`timescale 1ns/10ps
module fifoStatus (
wr,
rd,
fifo_we,
fifo_rd,
wptr,
rptr,
fifo_full,
fifo_empty,
fifo_threshold,
fifo_overflow,
fifo_underflow,
clk,
rst_n
);
// Input:
// wr(bool): write signal
// rd(bool): read signal
// fifo_we(bool): write enable signal
// fifo_rd(bool): read enable signal
// wptr(5bit): write pointer
// rptr(5bit): read pointer
// clk(bool): clock
// rst_n(bool): reset
//
// Ouput:
// fifo_full(bool): signal indicating the fifo memory is full
// fifo_empty(bool):signal indicating the fifo memory is empty
// fifo_threshold(bool): signal indicating that the fifo is about to overflow
// fifo_overflow(bool): signal indicating that the fifo rptr has overflowed
// fifo_underflow(bool): signal indicating that the fifo wptr has underflowed
input wr;
input rd;
input fifo_we;
input fifo_rd;
input [4:0] wptr;
input [4:0] rptr;
output fifo_full;
wire fifo_full;
output fifo_empty;
wire fifo_empty;
output fifo_threshold;
wire fifo_threshold;
output fifo_overflow;
wire fifo_overflow;
output fifo_underflow;
wire fifo_underflow;
input clk;
input rst_n;
reg underflow_set = 0;
reg signed [4:0] pointer_result = 0;
reg pointer_equal = 0;
reg overflow_set = 0;
reg fifo_underflow_i = 0;
reg fifo_threshold_i = 0;
reg fifo_overflow_i = 0;
reg fifo_full_i = 0;
reg fifo_empty_i = 0;
reg fbit_comp = 0;
always @(rd, wr, fifo_full_i, rptr, wptr, fifo_empty_i) begin: FIFOSTATUS_LOGIC1
fbit_comp = (wptr[4] ^ rptr[4]);
if (($signed({1'b0, wptr[3-1:0]}) - rptr[3-1:0])) begin
pointer_equal = 0;
end
else begin
pointer_equal = 1;
end
pointer_result = (wptr[4-1:0] - rptr[4-1:0]);
overflow_set = (fifo_full_i & wr);
underflow_set = (fifo_empty_i & rd);
end
always @(fbit_comp, pointer_equal, pointer_result) begin: FIFOSTATUS_LOGIC2
fifo_full_i = (fbit_comp & pointer_equal);
fifo_empty_i = ((!fbit_comp) & pointer_equal);
if ((pointer_result[4] || pointer_result[3])) begin
fifo_threshold_i = 1;
end
else begin
fifo_threshold_i = 0;
end
end
always @(posedge clk, negedge rst_n) begin: FIFOSTATUS_OVERFLOWCONTROL
if (rst_n) begin
fifo_overflow_i <= 0;
end
else if (((overflow_set == 1) && (fifo_rd == 0))) begin
fifo_overflow_i <= 1;
end
else if (fifo_rd) begin
fifo_overflow_i <= 0;
end
else begin
fifo_overflow_i <= fifo_overflow_i;
end
end
always @(posedge clk, negedge rst_n) begin: FIFOSTATUS_UNDERFLOWCONTROL
if (rst_n) begin
fifo_underflow_i <= 0;
end
else if (((underflow_set == 1) && (fifo_we == 0))) begin
fifo_underflow_i <= 1;
end
else if (fifo_we) begin
fifo_underflow_i <= 0;
end
else begin
fifo_underflow_i <= fifo_underflow_i;
end
end
assign fifo_full = fifo_full_i;
assign fifo_empty = fifo_empty_i;
assign fifo_threshold = fifo_threshold_i;
assign fifo_overflow = fifo_overflow_i;
assign fifo_underflow = fifo_underflow_i;
endmodule
|
module memory(
// input
i_clk, i_reset_n,
i_address, i_write, i_read, i_writedata,
// output
o_readdata, o_waitrequest
);
input wire i_clk;
input wire i_reset_n;
input wire [17:0] i_address;
input wire i_write;
input wire i_read;
input wire [35:0] i_writedata;
output wire [35:0] o_readdata;
output wire o_waitrequest;
reg [35:0] mem[0:'o40000-1];
wire addrok = i_address[17:14] == 0;
wire [13:0] addr = i_address[13:0];
wire [35:0] memword = addrok ? mem[addr] : 0;
always @(posedge i_clk or negedge i_reset_n) begin
if(~i_reset_n) begin
end else begin
if(i_write & addrok) begin
mem[addr] <= i_writedata;
end
end
end
assign o_readdata = i_read ? memword : 0;
assign o_waitrequest = 0;
endmodule
module dlymemory(
// input
i_clk, i_reset_n,
i_address, i_write, i_read, i_writedata,
// output
o_readdata, o_waitrequest
);
input wire i_clk;
input wire i_reset_n;
input wire [17:0] i_address;
input wire i_write;
input wire i_read;
input wire [35:0] i_writedata;
output wire [35:0] o_readdata;
output wire o_waitrequest;
reg [35:0] mem[0:'o40000-1];
wire addrok = i_address[17:14] == 0;
wire [13:0] addr = i_address[13:0];
wire [35:0] memword = addrok ? mem[addr] : 0;
wire write_edge, read_edge;
reg [3:0] dly;
wire ready = dly == 0;
edgedet e0(i_clk, i_reset_n, i_write, write_edge);
edgedet e1(i_clk, i_reset_n, i_read, read_edge);
always @(posedge i_clk or negedge i_reset_n) begin
if(~i_reset_n) begin
dly <= 4;
end else begin
if(i_write & ready & addrok) begin
mem[addr] <= i_writedata;
end
if(~(i_write | i_read))
dly <= 4;
else if(dly)
dly <= dly - 1;
end
end
assign o_readdata = i_read ? memword : 0;
assign o_waitrequest = ~ready;
endmodule
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Wed Nov 28 10:36:26 EST 2012
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wtiS0_SThreadBusy O 1 reg
// wtiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 32 reg
// wsiM0_MByteEn O 4 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// adx_csb O 1 reg
// adx_sdo O 1 reg
// adx_funct O 1 const
// adc0_oe O 1 const
// adc0_resetp O 1 reg
// adc0_sen O 1 reg
// adc0_sdata O 1 reg
// adc1_oe O 1 const
// adc1_resetp O 1 reg
// adc1_sen O 1 reg
// adc1_sdata O 1 reg
// CLK_adx_sclk O 1 clock
// CLK_GATE_adx_sclk O 1 const
// CLK_adx_sclkn O 1 clock
// CLK_GATE_adx_sclkn O 1 const
// CLK_adc0_sclk O 1 clock
// CLK_GATE_adc0_sclk O 1 const
// CLK_adc0_sclkn O 1 clock
// CLK_GATE_adc0_sclkn O 1 const
// CLK_adc1_sclk O 1 clock
// CLK_GATE_adc1_sclk O 1 const
// CLK_adc1_sclkn O 1 clock
// CLK_GATE_adc1_sclkn O 1 const
// CLK_adcSdrClk O 1 clock
// CLK_GATE_adcSdrClk O 1 const
// RST_N_adx_srst O 1 reset
// RST_N_adc0_rst O 1 reset
// RST_N_adc1_rst O 1 reset
// RST_N_adcSdrRst O 1 reset
// CLK_sys0_clk I 1 clock
// RST_N_sys0_rst I 1 reset
// CLK_adc_clk I 1 clock
// CLK_adc0_clk I 1 clock
// CLK_adc1_clk I 1 clock
// RST_N_adcx_rst I 1 unused
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wtiS0_req I 67 reg
// adx_sdi_arg I 1 reg
// adx_status_arg I 1 unused
// adc0_ddp_arg I 7
// adc0_ddn_arg I 7
// adc0_sdout_arg I 1 reg
// adc1_ddp_arg I 7
// adc1_ddn_arg I 7
// adc1_sdout_arg I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkADCWorker(CLK_sys0_clk,
RST_N_sys0_rst,
CLK_adc_clk,
CLK_adc0_clk,
CLK_adc1_clk,
RST_N_adcx_rst,
wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wtiS0_req,
wtiS0_SThreadBusy,
wtiS0_SReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
adx_csb,
adx_sdo,
adx_sdi_arg,
adx_funct,
adx_status_arg,
adc0_oe,
adc0_ddp_arg,
adc0_ddn_arg,
adc0_resetp,
adc0_sen,
adc0_sdata,
adc0_sdout_arg,
adc1_oe,
adc1_ddp_arg,
adc1_ddn_arg,
adc1_resetp,
adc1_sen,
adc1_sdata,
adc1_sdout_arg,
CLK_adx_sclk,
CLK_GATE_adx_sclk,
CLK_adx_sclkn,
CLK_GATE_adx_sclkn,
CLK_adc0_sclk,
CLK_GATE_adc0_sclk,
CLK_adc0_sclkn,
CLK_GATE_adc0_sclkn,
CLK_adc1_sclk,
CLK_GATE_adc1_sclk,
CLK_adc1_sclkn,
CLK_GATE_adc1_sclkn,
CLK_adcSdrClk,
CLK_GATE_adcSdrClk,
RST_N_adx_srst,
RST_N_adc0_rst,
RST_N_adc1_rst,
RST_N_adcSdrRst);
parameter [0 : 0] hasDebugLogic = 1'b0;
input CLK_sys0_clk;
input RST_N_sys0_rst;
input CLK_adc_clk;
input CLK_adc0_clk;
input CLK_adc1_clk;
input RST_N_adcx_rst;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wtiS0_put
input [66 : 0] wtiS0_req;
// value method wtiS0_sThreadBusy
output wtiS0_SThreadBusy;
// value method wtiS0_sReset_n
output wtiS0_SReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [31 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [3 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method adx_adx_csb
output adx_csb;
// value method adx_adx_sdo
output adx_sdo;
// action method adx_adx_sdi
input adx_sdi_arg;
// value method adx_adx_funct
output adx_funct;
// action method adx_adx_status
input adx_status_arg;
// value method adc0_oe
output adc0_oe;
// action method adc0_ddp
input [6 : 0] adc0_ddp_arg;
// action method adc0_ddn
input [6 : 0] adc0_ddn_arg;
// value method adc0_resetp
output adc0_resetp;
// value method adc0_sen
output adc0_sen;
// value method adc0_sdata
output adc0_sdata;
// action method adc0_sdout
input adc0_sdout_arg;
// value method adc1_oe
output adc1_oe;
// action method adc1_ddp
input [6 : 0] adc1_ddp_arg;
// action method adc1_ddn
input [6 : 0] adc1_ddn_arg;
// value method adc1_resetp
output adc1_resetp;
// value method adc1_sen
output adc1_sen;
// value method adc1_sdata
output adc1_sdata;
// action method adc1_sdout
input adc1_sdout_arg;
// oscillator and gates for output clock CLK_adx_sclk
output CLK_adx_sclk;
output CLK_GATE_adx_sclk;
// oscillator and gates for output clock CLK_adx_sclkn
output CLK_adx_sclkn;
output CLK_GATE_adx_sclkn;
// oscillator and gates for output clock CLK_adc0_sclk
output CLK_adc0_sclk;
output CLK_GATE_adc0_sclk;
// oscillator and gates for output clock CLK_adc0_sclkn
output CLK_adc0_sclkn;
output CLK_GATE_adc0_sclkn;
// oscillator and gates for output clock CLK_adc1_sclk
output CLK_adc1_sclk;
output CLK_GATE_adc1_sclk;
// oscillator and gates for output clock CLK_adc1_sclkn
output CLK_adc1_sclkn;
output CLK_GATE_adc1_sclkn;
// oscillator and gates for output clock CLK_adcSdrClk
output CLK_adcSdrClk;
output CLK_GATE_adcSdrClk;
// output resets
output RST_N_adx_srst;
output RST_N_adc0_rst;
output RST_N_adc1_rst;
output RST_N_adcSdrRst;
// signals for module outputs
wire [31 : 0] wciS0_SData, wsiM0_MData;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [3 : 0] wsiM0_MByteEn;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire CLK_GATE_adc0_sclk,
CLK_GATE_adc0_sclkn,
CLK_GATE_adc1_sclk,
CLK_GATE_adc1_sclkn,
CLK_GATE_adcSdrClk,
CLK_GATE_adx_sclk,
CLK_GATE_adx_sclkn,
CLK_adc0_sclk,
CLK_adc0_sclkn,
CLK_adc1_sclk,
CLK_adc1_sclkn,
CLK_adcSdrClk,
CLK_adx_sclk,
CLK_adx_sclkn,
RST_N_adc0_rst,
RST_N_adc1_rst,
RST_N_adcSdrRst,
RST_N_adx_srst,
adc0_oe,
adc0_resetp,
adc0_sdata,
adc0_sen,
adc1_oe,
adc1_resetp,
adc1_sdata,
adc1_sen,
adx_csb,
adx_funct,
adx_sdo,
wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wtiS0_SReset_n,
wtiS0_SThreadBusy;
// inlined wires
wire [95 : 0] wsiM_extStatusW$wget;
wire [71 : 0] wci_wslv_wciReq$wget;
wire [66 : 0] wti_wtiReq$wget;
wire [63 : 0] adcCore0_colGate_nowW$wget,
adcCore0_nowW$wget,
adcCore1_colGate_nowW$wget,
adcCore1_nowW$wget;
wire [60 : 0] wsiM_reqFifo_x_wire$wget;
wire [38 : 0] adcCore0_sampF_wDataIn$wget,
adcCore0_sampF_wDataOut$wget,
adcCore1_sampF_wDataIn$wget,
adcCore1_sampF_wDataOut$wget;
wire [33 : 0] wci_wslv_respF_x_wire$wget;
wire [31 : 0] adcCore0_colGate_sampDataW$wget,
adcCore1_colGate_sampDataW$wget,
wci_wci_Es_mAddr_w$wget,
wci_wci_Es_mData_w$wget;
wire [17 : 0] fcAdc_grayCounter_wdCounterCrossing$wget;
wire [15 : 0] adcCore0_colGate_maxBurstLenW$wget,
adcCore1_colGate_maxBurstLenW$wget;
wire [10 : 0] adcCore0_sampF_rRdPtr_wdCounterCrossing$wget,
adcCore0_sampF_rWrPtr_wdCounterCrossing$wget,
adcCore1_sampF_rRdPtr_wdCounterCrossing$wget,
adcCore1_sampF_rWrPtr_wdCounterCrossing$wget;
wire [3 : 0] wci_wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_wci_Es_mCmd_w$wget, wci_wslv_wEdge$wget;
wire [1 : 0] adcCore0_ddrC_psCmdReg_1$wget, adcCore1_ddrC_psCmdReg_1$wget;
wire adcCore0_acquireDReg_1$wget,
adcCore0_acquireDReg_1$whas,
adcCore0_adcRst_1$wget,
adcCore0_adcRst_1$whas,
adcCore0_averageDReg_1$wget,
adcCore0_averageDReg_1$whas,
adcCore0_colGate_average_dw$wget,
adcCore0_colGate_average_dw$whas,
adcCore0_colGate_collectPW$whas,
adcCore0_colGate_enaSyncPW$whas,
adcCore0_colGate_enaTimestampPW$whas,
adcCore0_colGate_maxBurstLenW$whas,
adcCore0_colGate_nowW$whas,
adcCore0_colGate_operatePW$whas,
adcCore0_colGate_sampActive_1$wget,
adcCore0_colGate_sampActive_1$whas,
adcCore0_colGate_sampDataW$whas,
adcCore0_ddrC_psCmdReg_1$whas,
adcCore0_iseqFsm_abort$wget,
adcCore0_iseqFsm_abort$whas,
adcCore0_iseqFsm_start_reg_1_1$wget,
adcCore0_iseqFsm_start_reg_1_1$whas,
adcCore0_iseqFsm_start_wire$wget,
adcCore0_iseqFsm_start_wire$whas,
adcCore0_iseqFsm_state_fired_1$wget,
adcCore0_iseqFsm_state_fired_1$whas,
adcCore0_iseqFsm_state_overlap_pw$whas,
adcCore0_iseqFsm_state_set_pw$whas,
adcCore0_nowW$whas,
adcCore0_operateDReg_1$wget,
adcCore0_operateDReg_1$whas,
adcCore0_sampF_pwDequeue$whas,
adcCore0_sampF_pwEnqueue$whas,
adcCore0_sampF_rRdPtr_pwDecrement$whas,
adcCore0_sampF_rRdPtr_pwIncrement$whas,
adcCore0_sampF_rWrPtr_pwDecrement$whas,
adcCore0_sampF_rWrPtr_pwIncrement$whas,
adcCore0_sampF_wDataIn$whas,
adcCore0_sampF_wDataOut$whas,
adcCore0_spiI_cGate_1$wget,
adcCore0_spiI_cGate_1$whas,
adcCore0_spiI_csbR_1$wget,
adcCore0_spiI_csbR_1$whas,
adcCore0_spiI_doResp_1$wget,
adcCore0_spiI_doResp_1$whas,
adcCore0_spiI_reqF_dClear_pw$whas,
adcCore0_spiI_reqF_deq_happened$whas,
adcCore0_spiI_reqF_deq_pw$whas,
adcCore0_spiI_reqF_enq_pw$whas,
adcCore0_spiI_reqF_sClear_pw$whas,
adcCore0_spiI_respF_dClear_pw$whas,
adcCore0_spiI_respF_deq_happened$whas,
adcCore0_spiI_respF_deq_pw$whas,
adcCore0_spiI_respF_enq_pw$whas,
adcCore0_spiI_respF_sClear_pw$whas,
adcCore0_spiI_sdiWs$wget,
adcCore0_spiI_sdoR_1$wget,
adcCore0_spiI_sdoR_1$whas,
adcCore1_acquireDReg_1$wget,
adcCore1_acquireDReg_1$whas,
adcCore1_adcRst_1$wget,
adcCore1_adcRst_1$whas,
adcCore1_averageDReg_1$wget,
adcCore1_averageDReg_1$whas,
adcCore1_colGate_average_dw$wget,
adcCore1_colGate_average_dw$whas,
adcCore1_colGate_collectPW$whas,
adcCore1_colGate_enaSyncPW$whas,
adcCore1_colGate_enaTimestampPW$whas,
adcCore1_colGate_maxBurstLenW$whas,
adcCore1_colGate_nowW$whas,
adcCore1_colGate_operatePW$whas,
adcCore1_colGate_sampActive_1$wget,
adcCore1_colGate_sampActive_1$whas,
adcCore1_colGate_sampDataW$whas,
adcCore1_ddrC_psCmdReg_1$whas,
adcCore1_iseqFsm_abort$wget,
adcCore1_iseqFsm_abort$whas,
adcCore1_iseqFsm_start_reg_1_1$wget,
adcCore1_iseqFsm_start_reg_1_1$whas,
adcCore1_iseqFsm_start_wire$wget,
adcCore1_iseqFsm_start_wire$whas,
adcCore1_iseqFsm_state_fired_1$wget,
adcCore1_iseqFsm_state_fired_1$whas,
adcCore1_iseqFsm_state_overlap_pw$whas,
adcCore1_iseqFsm_state_set_pw$whas,
adcCore1_nowW$whas,
adcCore1_operateDReg_1$wget,
adcCore1_operateDReg_1$whas,
adcCore1_sampF_pwDequeue$whas,
adcCore1_sampF_pwEnqueue$whas,
adcCore1_sampF_rRdPtr_pwDecrement$whas,
adcCore1_sampF_rRdPtr_pwIncrement$whas,
adcCore1_sampF_rWrPtr_pwDecrement$whas,
adcCore1_sampF_rWrPtr_pwIncrement$whas,
adcCore1_sampF_wDataIn$whas,
adcCore1_sampF_wDataOut$whas,
adcCore1_spiI_cGate_1$wget,
adcCore1_spiI_cGate_1$whas,
adcCore1_spiI_csbR_1$wget,
adcCore1_spiI_csbR_1$whas,
adcCore1_spiI_doResp_1$wget,
adcCore1_spiI_doResp_1$whas,
adcCore1_spiI_reqF_dClear_pw$whas,
adcCore1_spiI_reqF_deq_happened$whas,
adcCore1_spiI_reqF_deq_pw$whas,
adcCore1_spiI_reqF_enq_pw$whas,
adcCore1_spiI_reqF_sClear_pw$whas,
adcCore1_spiI_respF_dClear_pw$whas,
adcCore1_spiI_respF_deq_happened$whas,
adcCore1_spiI_respF_deq_pw$whas,
adcCore1_spiI_respF_enq_pw$whas,
adcCore1_spiI_respF_sClear_pw$whas,
adcCore1_spiI_sdiWs$wget,
adcCore1_spiI_sdoR_1$wget,
adcCore1_spiI_sdoR_1$whas,
fcAdc_grayCounter_pwDecrement$whas,
fcAdc_grayCounter_pwIncrement$whas,
fcAdc_pulseAction_1$wget,
fcAdc_pulseAction_1$whas,
oneKHz_decAction$whas,
oneKHz_incAction$whas,
spiClk_iseqFsm_abort$wget,
spiClk_iseqFsm_abort$whas,
spiClk_iseqFsm_start_reg_1_1$wget,
spiClk_iseqFsm_start_reg_1_1$whas,
spiClk_iseqFsm_start_wire$wget,
spiClk_iseqFsm_start_wire$whas,
spiClk_iseqFsm_state_fired_1$wget,
spiClk_iseqFsm_state_fired_1$whas,
spiClk_iseqFsm_state_overlap_pw$whas,
spiClk_iseqFsm_state_set_pw$whas,
spiClk_spiI_cGate_1$wget,
spiClk_spiI_cGate_1$whas,
spiClk_spiI_csbR_1$wget,
spiClk_spiI_csbR_1$whas,
spiClk_spiI_doResp_1$wget,
spiClk_spiI_doResp_1$whas,
spiClk_spiI_reqF_dClear_pw$whas,
spiClk_spiI_reqF_deq_happened$whas,
spiClk_spiI_reqF_deq_pw$whas,
spiClk_spiI_reqF_enq_pw$whas,
spiClk_spiI_reqF_sClear_pw$whas,
spiClk_spiI_respF_dClear_pw$whas,
spiClk_spiI_respF_deq_happened$whas,
spiClk_spiI_respF_deq_pw$whas,
spiClk_spiI_respF_enq_pw$whas,
spiClk_spiI_respF_sClear_pw$whas,
spiClk_spiI_sdiWs$wget,
spiClk_spiI_sdoR_1$wget,
spiClk_spiI_sdoR_1$whas,
wci_wci_Es_mAddrSpace_w$wget,
wci_wci_Es_mAddrSpace_w$whas,
wci_wci_Es_mAddr_w$whas,
wci_wci_Es_mByteEn_w$whas,
wci_wci_Es_mCmd_w$whas,
wci_wci_Es_mData_w$whas,
wci_wslv_ctlAckReg_1$wget,
wci_wslv_ctlAckReg_1$whas,
wci_wslv_reqF_r_clr$whas,
wci_wslv_reqF_r_deq$whas,
wci_wslv_reqF_r_enq$whas,
wci_wslv_respF_dequeueing$whas,
wci_wslv_respF_enqueueing$whas,
wci_wslv_respF_x_wire$whas,
wci_wslv_sFlagReg_1$wget,
wci_wslv_sFlagReg_1$whas,
wci_wslv_sThreadBusy_pw$whas,
wci_wslv_wEdge$whas,
wci_wslv_wciReq$whas,
wci_wslv_wci_cfrd_pw$whas,
wci_wslv_wci_cfwr_pw$whas,
wci_wslv_wci_ctrl_pw$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wti_operateD_1$wget,
wti_operateD_1$whas,
wti_wtiReq$whas;
// register adcControl
reg [31 : 0] adcControl;
wire [31 : 0] adcControl$D_IN;
wire adcControl$EN;
// register adcCore0_acquireDReg
reg adcCore0_acquireDReg;
wire adcCore0_acquireDReg$D_IN, adcCore0_acquireDReg$EN;
// register adcCore0_adcRst
reg adcCore0_adcRst;
wire adcCore0_adcRst$D_IN, adcCore0_adcRst$EN;
// register adcCore0_averageDReg
reg adcCore0_averageDReg;
wire adcCore0_averageDReg$D_IN, adcCore0_averageDReg$EN;
// register adcCore0_colGate_avgEven
reg [17 : 0] adcCore0_colGate_avgEven;
wire [17 : 0] adcCore0_colGate_avgEven$D_IN;
wire adcCore0_colGate_avgEven$EN;
// register adcCore0_colGate_avgOdd
reg [17 : 0] adcCore0_colGate_avgOdd;
wire [17 : 0] adcCore0_colGate_avgOdd$D_IN;
wire adcCore0_colGate_avgOdd$EN;
// register adcCore0_colGate_avgPhase
reg [1 : 0] adcCore0_colGate_avgPhase;
wire [1 : 0] adcCore0_colGate_avgPhase$D_IN;
wire adcCore0_colGate_avgPhase$EN;
// register adcCore0_colGate_collectD
reg adcCore0_colGate_collectD;
wire adcCore0_colGate_collectD$D_IN, adcCore0_colGate_collectD$EN;
// register adcCore0_colGate_dropCount
reg [31 : 0] adcCore0_colGate_dropCount;
wire [31 : 0] adcCore0_colGate_dropCount$D_IN;
wire adcCore0_colGate_dropCount$EN;
// register adcCore0_colGate_dwellFails
reg [31 : 0] adcCore0_colGate_dwellFails;
wire [31 : 0] adcCore0_colGate_dwellFails$D_IN;
wire adcCore0_colGate_dwellFails$EN;
// register adcCore0_colGate_dwellStarts
reg [31 : 0] adcCore0_colGate_dwellStarts;
wire [31 : 0] adcCore0_colGate_dwellStarts$D_IN;
wire adcCore0_colGate_dwellStarts$EN;
// register adcCore0_colGate_ovrRecover
reg [3 : 0] adcCore0_colGate_ovrRecover;
reg [3 : 0] adcCore0_colGate_ovrRecover$D_IN;
wire adcCore0_colGate_ovrRecover$EN;
// register adcCore0_colGate_sampActive
reg adcCore0_colGate_sampActive;
wire adcCore0_colGate_sampActive$D_IN, adcCore0_colGate_sampActive$EN;
// register adcCore0_colGate_sampActiveD
reg adcCore0_colGate_sampActiveD;
wire adcCore0_colGate_sampActiveD$D_IN, adcCore0_colGate_sampActiveD$EN;
// register adcCore0_colGate_sampCount
reg [31 : 0] adcCore0_colGate_sampCount;
wire [31 : 0] adcCore0_colGate_sampCount$D_IN;
wire adcCore0_colGate_sampCount$EN;
// register adcCore0_colGate_sampDataWD
reg [31 : 0] adcCore0_colGate_sampDataWD;
wire [31 : 0] adcCore0_colGate_sampDataWD$D_IN;
wire adcCore0_colGate_sampDataWD$EN;
// register adcCore0_colGate_syncMesg
reg [1 : 0] adcCore0_colGate_syncMesg;
wire [1 : 0] adcCore0_colGate_syncMesg$D_IN;
wire adcCore0_colGate_syncMesg$EN;
// register adcCore0_colGate_timeMesg
reg [2 : 0] adcCore0_colGate_timeMesg;
wire [2 : 0] adcCore0_colGate_timeMesg$D_IN;
wire adcCore0_colGate_timeMesg$EN;
// register adcCore0_colGate_uprollCnt
reg [15 : 0] adcCore0_colGate_uprollCnt;
wire [15 : 0] adcCore0_colGate_uprollCnt$D_IN;
wire adcCore0_colGate_uprollCnt$EN;
// register adcCore0_ddrC_psCmdReg
reg [1 : 0] adcCore0_ddrC_psCmdReg;
wire [1 : 0] adcCore0_ddrC_psCmdReg$D_IN;
wire adcCore0_ddrC_psCmdReg$EN;
// register adcCore0_iseqFsm_jj_delay_count
reg [12 : 0] adcCore0_iseqFsm_jj_delay_count;
wire [12 : 0] adcCore0_iseqFsm_jj_delay_count$D_IN;
wire adcCore0_iseqFsm_jj_delay_count$EN;
// register adcCore0_iseqFsm_start_reg
reg adcCore0_iseqFsm_start_reg;
wire adcCore0_iseqFsm_start_reg$D_IN, adcCore0_iseqFsm_start_reg$EN;
// register adcCore0_iseqFsm_start_reg_1
reg adcCore0_iseqFsm_start_reg_1;
wire adcCore0_iseqFsm_start_reg_1$D_IN, adcCore0_iseqFsm_start_reg_1$EN;
// register adcCore0_iseqFsm_state_can_overlap
reg adcCore0_iseqFsm_state_can_overlap;
wire adcCore0_iseqFsm_state_can_overlap$D_IN,
adcCore0_iseqFsm_state_can_overlap$EN;
// register adcCore0_iseqFsm_state_fired
reg adcCore0_iseqFsm_state_fired;
wire adcCore0_iseqFsm_state_fired$D_IN, adcCore0_iseqFsm_state_fired$EN;
// register adcCore0_iseqFsm_state_mkFSMstate
reg [3 : 0] adcCore0_iseqFsm_state_mkFSMstate;
reg [3 : 0] adcCore0_iseqFsm_state_mkFSMstate$D_IN;
wire adcCore0_iseqFsm_state_mkFSMstate$EN;
// register adcCore0_operateDReg
reg adcCore0_operateDReg;
wire adcCore0_operateDReg$D_IN, adcCore0_operateDReg$EN;
// register adcCore0_readMode
reg adcCore0_readMode;
wire adcCore0_readMode$D_IN, adcCore0_readMode$EN;
// register adcCore0_samp
reg [31 : 0] adcCore0_samp;
wire [31 : 0] adcCore0_samp$D_IN;
wire adcCore0_samp$EN;
// register adcCore0_sampF_rRdPtr_rdCounter
reg [10 : 0] adcCore0_sampF_rRdPtr_rdCounter;
wire [10 : 0] adcCore0_sampF_rRdPtr_rdCounter$D_IN;
wire adcCore0_sampF_rRdPtr_rdCounter$EN;
// register adcCore0_sampF_rRdPtr_rdCounterPre
reg [10 : 0] adcCore0_sampF_rRdPtr_rdCounterPre;
wire [10 : 0] adcCore0_sampF_rRdPtr_rdCounterPre$D_IN;
wire adcCore0_sampF_rRdPtr_rdCounterPre$EN;
// register adcCore0_sampF_rRdPtr_rsCounter
reg [10 : 0] adcCore0_sampF_rRdPtr_rsCounter;
wire [10 : 0] adcCore0_sampF_rRdPtr_rsCounter$D_IN;
wire adcCore0_sampF_rRdPtr_rsCounter$EN;
// register adcCore0_sampF_rWrPtr_rdCounter
reg [10 : 0] adcCore0_sampF_rWrPtr_rdCounter;
wire [10 : 0] adcCore0_sampF_rWrPtr_rdCounter$D_IN;
wire adcCore0_sampF_rWrPtr_rdCounter$EN;
// register adcCore0_sampF_rWrPtr_rdCounterPre
reg [10 : 0] adcCore0_sampF_rWrPtr_rdCounterPre;
wire [10 : 0] adcCore0_sampF_rWrPtr_rdCounterPre$D_IN;
wire adcCore0_sampF_rWrPtr_rdCounterPre$EN;
// register adcCore0_sampF_rWrPtr_rsCounter
reg [10 : 0] adcCore0_sampF_rWrPtr_rsCounter;
wire [10 : 0] adcCore0_sampF_rWrPtr_rsCounter$D_IN;
wire adcCore0_sampF_rWrPtr_rsCounter$EN;
// register adcCore0_spiI_cGate
reg adcCore0_spiI_cGate;
wire adcCore0_spiI_cGate$D_IN, adcCore0_spiI_cGate$EN;
// register adcCore0_spiI_cap
reg adcCore0_spiI_cap;
wire adcCore0_spiI_cap$D_IN, adcCore0_spiI_cap$EN;
// register adcCore0_spiI_cap_1
reg adcCore0_spiI_cap_1;
wire adcCore0_spiI_cap_1$D_IN, adcCore0_spiI_cap_1$EN;
// register adcCore0_spiI_cap_2
reg adcCore0_spiI_cap_2;
wire adcCore0_spiI_cap_2$D_IN, adcCore0_spiI_cap_2$EN;
// register adcCore0_spiI_cap_3
reg adcCore0_spiI_cap_3;
wire adcCore0_spiI_cap_3$D_IN, adcCore0_spiI_cap_3$EN;
// register adcCore0_spiI_cap_4
reg adcCore0_spiI_cap_4;
wire adcCore0_spiI_cap_4$D_IN, adcCore0_spiI_cap_4$EN;
// register adcCore0_spiI_cap_5
reg adcCore0_spiI_cap_5;
wire adcCore0_spiI_cap_5$D_IN, adcCore0_spiI_cap_5$EN;
// register adcCore0_spiI_cap_6
reg adcCore0_spiI_cap_6;
wire adcCore0_spiI_cap_6$D_IN, adcCore0_spiI_cap_6$EN;
// register adcCore0_spiI_cap_7
reg adcCore0_spiI_cap_7;
wire adcCore0_spiI_cap_7$D_IN, adcCore0_spiI_cap_7$EN;
// register adcCore0_spiI_csbR
reg adcCore0_spiI_csbR;
wire adcCore0_spiI_csbR$D_IN, adcCore0_spiI_csbR$EN;
// register adcCore0_spiI_dPos
reg [2 : 0] adcCore0_spiI_dPos;
wire [2 : 0] adcCore0_spiI_dPos$D_IN;
wire adcCore0_spiI_dPos$EN;
// register adcCore0_spiI_doResp
reg adcCore0_spiI_doResp;
wire adcCore0_spiI_doResp$D_IN, adcCore0_spiI_doResp$EN;
// register adcCore0_spiI_iPos
reg [3 : 0] adcCore0_spiI_iPos;
wire [3 : 0] adcCore0_spiI_iPos$D_IN;
wire adcCore0_spiI_iPos$EN;
// register adcCore0_spiI_reqF_head_wrapped
reg adcCore0_spiI_reqF_head_wrapped;
wire adcCore0_spiI_reqF_head_wrapped$D_IN,
adcCore0_spiI_reqF_head_wrapped$EN;
// register adcCore0_spiI_reqF_tail_wrapped
reg adcCore0_spiI_reqF_tail_wrapped;
wire adcCore0_spiI_reqF_tail_wrapped$D_IN,
adcCore0_spiI_reqF_tail_wrapped$EN;
// register adcCore0_spiI_reqS
reg [16 : 0] adcCore0_spiI_reqS;
reg [16 : 0] adcCore0_spiI_reqS$D_IN;
wire adcCore0_spiI_reqS$EN;
// register adcCore0_spiI_respF_head_wrapped
reg adcCore0_spiI_respF_head_wrapped;
wire adcCore0_spiI_respF_head_wrapped$D_IN,
adcCore0_spiI_respF_head_wrapped$EN;
// register adcCore0_spiI_respF_tail_wrapped
reg adcCore0_spiI_respF_tail_wrapped;
wire adcCore0_spiI_respF_tail_wrapped$D_IN,
adcCore0_spiI_respF_tail_wrapped$EN;
// register adcCore0_spiI_respS
reg [7 : 0] adcCore0_spiI_respS;
wire [7 : 0] adcCore0_spiI_respS$D_IN;
wire adcCore0_spiI_respS$EN;
// register adcCore0_spiI_sdiP
reg adcCore0_spiI_sdiP;
wire adcCore0_spiI_sdiP$D_IN, adcCore0_spiI_sdiP$EN;
// register adcCore0_spiI_sdoR
reg adcCore0_spiI_sdoR;
wire adcCore0_spiI_sdoR$D_IN, adcCore0_spiI_sdoR$EN;
// register adcCore0_spiI_xmt_d
reg adcCore0_spiI_xmt_d;
wire adcCore0_spiI_xmt_d$D_IN, adcCore0_spiI_xmt_d$EN;
// register adcCore0_spiI_xmt_i
reg adcCore0_spiI_xmt_i;
wire adcCore0_spiI_xmt_i$D_IN, adcCore0_spiI_xmt_i$EN;
// register adcCore1_acquireDReg
reg adcCore1_acquireDReg;
wire adcCore1_acquireDReg$D_IN, adcCore1_acquireDReg$EN;
// register adcCore1_adcRst
reg adcCore1_adcRst;
wire adcCore1_adcRst$D_IN, adcCore1_adcRst$EN;
// register adcCore1_averageDReg
reg adcCore1_averageDReg;
wire adcCore1_averageDReg$D_IN, adcCore1_averageDReg$EN;
// register adcCore1_colGate_avgEven
reg [17 : 0] adcCore1_colGate_avgEven;
wire [17 : 0] adcCore1_colGate_avgEven$D_IN;
wire adcCore1_colGate_avgEven$EN;
// register adcCore1_colGate_avgOdd
reg [17 : 0] adcCore1_colGate_avgOdd;
wire [17 : 0] adcCore1_colGate_avgOdd$D_IN;
wire adcCore1_colGate_avgOdd$EN;
// register adcCore1_colGate_avgPhase
reg [1 : 0] adcCore1_colGate_avgPhase;
wire [1 : 0] adcCore1_colGate_avgPhase$D_IN;
wire adcCore1_colGate_avgPhase$EN;
// register adcCore1_colGate_collectD
reg adcCore1_colGate_collectD;
wire adcCore1_colGate_collectD$D_IN, adcCore1_colGate_collectD$EN;
// register adcCore1_colGate_dropCount
reg [31 : 0] adcCore1_colGate_dropCount;
wire [31 : 0] adcCore1_colGate_dropCount$D_IN;
wire adcCore1_colGate_dropCount$EN;
// register adcCore1_colGate_dwellFails
reg [31 : 0] adcCore1_colGate_dwellFails;
wire [31 : 0] adcCore1_colGate_dwellFails$D_IN;
wire adcCore1_colGate_dwellFails$EN;
// register adcCore1_colGate_dwellStarts
reg [31 : 0] adcCore1_colGate_dwellStarts;
wire [31 : 0] adcCore1_colGate_dwellStarts$D_IN;
wire adcCore1_colGate_dwellStarts$EN;
// register adcCore1_colGate_ovrRecover
reg [3 : 0] adcCore1_colGate_ovrRecover;
reg [3 : 0] adcCore1_colGate_ovrRecover$D_IN;
wire adcCore1_colGate_ovrRecover$EN;
// register adcCore1_colGate_sampActive
reg adcCore1_colGate_sampActive;
wire adcCore1_colGate_sampActive$D_IN, adcCore1_colGate_sampActive$EN;
// register adcCore1_colGate_sampActiveD
reg adcCore1_colGate_sampActiveD;
wire adcCore1_colGate_sampActiveD$D_IN, adcCore1_colGate_sampActiveD$EN;
// register adcCore1_colGate_sampCount
reg [31 : 0] adcCore1_colGate_sampCount;
wire [31 : 0] adcCore1_colGate_sampCount$D_IN;
wire adcCore1_colGate_sampCount$EN;
// register adcCore1_colGate_sampDataWD
reg [31 : 0] adcCore1_colGate_sampDataWD;
wire [31 : 0] adcCore1_colGate_sampDataWD$D_IN;
wire adcCore1_colGate_sampDataWD$EN;
// register adcCore1_colGate_syncMesg
reg [1 : 0] adcCore1_colGate_syncMesg;
wire [1 : 0] adcCore1_colGate_syncMesg$D_IN;
wire adcCore1_colGate_syncMesg$EN;
// register adcCore1_colGate_timeMesg
reg [2 : 0] adcCore1_colGate_timeMesg;
wire [2 : 0] adcCore1_colGate_timeMesg$D_IN;
wire adcCore1_colGate_timeMesg$EN;
// register adcCore1_colGate_uprollCnt
reg [15 : 0] adcCore1_colGate_uprollCnt;
wire [15 : 0] adcCore1_colGate_uprollCnt$D_IN;
wire adcCore1_colGate_uprollCnt$EN;
// register adcCore1_ddrC_psCmdReg
reg [1 : 0] adcCore1_ddrC_psCmdReg;
wire [1 : 0] adcCore1_ddrC_psCmdReg$D_IN;
wire adcCore1_ddrC_psCmdReg$EN;
// register adcCore1_iseqFsm_jj_delay_count
reg [12 : 0] adcCore1_iseqFsm_jj_delay_count;
wire [12 : 0] adcCore1_iseqFsm_jj_delay_count$D_IN;
wire adcCore1_iseqFsm_jj_delay_count$EN;
// register adcCore1_iseqFsm_start_reg
reg adcCore1_iseqFsm_start_reg;
wire adcCore1_iseqFsm_start_reg$D_IN, adcCore1_iseqFsm_start_reg$EN;
// register adcCore1_iseqFsm_start_reg_1
reg adcCore1_iseqFsm_start_reg_1;
wire adcCore1_iseqFsm_start_reg_1$D_IN, adcCore1_iseqFsm_start_reg_1$EN;
// register adcCore1_iseqFsm_state_can_overlap
reg adcCore1_iseqFsm_state_can_overlap;
wire adcCore1_iseqFsm_state_can_overlap$D_IN,
adcCore1_iseqFsm_state_can_overlap$EN;
// register adcCore1_iseqFsm_state_fired
reg adcCore1_iseqFsm_state_fired;
wire adcCore1_iseqFsm_state_fired$D_IN, adcCore1_iseqFsm_state_fired$EN;
// register adcCore1_iseqFsm_state_mkFSMstate
reg [3 : 0] adcCore1_iseqFsm_state_mkFSMstate;
reg [3 : 0] adcCore1_iseqFsm_state_mkFSMstate$D_IN;
wire adcCore1_iseqFsm_state_mkFSMstate$EN;
// register adcCore1_operateDReg
reg adcCore1_operateDReg;
wire adcCore1_operateDReg$D_IN, adcCore1_operateDReg$EN;
// register adcCore1_readMode
reg adcCore1_readMode;
wire adcCore1_readMode$D_IN, adcCore1_readMode$EN;
// register adcCore1_samp
reg [31 : 0] adcCore1_samp;
wire [31 : 0] adcCore1_samp$D_IN;
wire adcCore1_samp$EN;
// register adcCore1_sampF_rRdPtr_rdCounter
reg [10 : 0] adcCore1_sampF_rRdPtr_rdCounter;
wire [10 : 0] adcCore1_sampF_rRdPtr_rdCounter$D_IN;
wire adcCore1_sampF_rRdPtr_rdCounter$EN;
// register adcCore1_sampF_rRdPtr_rdCounterPre
reg [10 : 0] adcCore1_sampF_rRdPtr_rdCounterPre;
wire [10 : 0] adcCore1_sampF_rRdPtr_rdCounterPre$D_IN;
wire adcCore1_sampF_rRdPtr_rdCounterPre$EN;
// register adcCore1_sampF_rRdPtr_rsCounter
reg [10 : 0] adcCore1_sampF_rRdPtr_rsCounter;
wire [10 : 0] adcCore1_sampF_rRdPtr_rsCounter$D_IN;
wire adcCore1_sampF_rRdPtr_rsCounter$EN;
// register adcCore1_sampF_rWrPtr_rdCounter
reg [10 : 0] adcCore1_sampF_rWrPtr_rdCounter;
wire [10 : 0] adcCore1_sampF_rWrPtr_rdCounter$D_IN;
wire adcCore1_sampF_rWrPtr_rdCounter$EN;
// register adcCore1_sampF_rWrPtr_rdCounterPre
reg [10 : 0] adcCore1_sampF_rWrPtr_rdCounterPre;
wire [10 : 0] adcCore1_sampF_rWrPtr_rdCounterPre$D_IN;
wire adcCore1_sampF_rWrPtr_rdCounterPre$EN;
// register adcCore1_sampF_rWrPtr_rsCounter
reg [10 : 0] adcCore1_sampF_rWrPtr_rsCounter;
wire [10 : 0] adcCore1_sampF_rWrPtr_rsCounter$D_IN;
wire adcCore1_sampF_rWrPtr_rsCounter$EN;
// register adcCore1_spiI_cGate
reg adcCore1_spiI_cGate;
wire adcCore1_spiI_cGate$D_IN, adcCore1_spiI_cGate$EN;
// register adcCore1_spiI_cap
reg adcCore1_spiI_cap;
wire adcCore1_spiI_cap$D_IN, adcCore1_spiI_cap$EN;
// register adcCore1_spiI_cap_1
reg adcCore1_spiI_cap_1;
wire adcCore1_spiI_cap_1$D_IN, adcCore1_spiI_cap_1$EN;
// register adcCore1_spiI_cap_2
reg adcCore1_spiI_cap_2;
wire adcCore1_spiI_cap_2$D_IN, adcCore1_spiI_cap_2$EN;
// register adcCore1_spiI_cap_3
reg adcCore1_spiI_cap_3;
wire adcCore1_spiI_cap_3$D_IN, adcCore1_spiI_cap_3$EN;
// register adcCore1_spiI_cap_4
reg adcCore1_spiI_cap_4;
wire adcCore1_spiI_cap_4$D_IN, adcCore1_spiI_cap_4$EN;
// register adcCore1_spiI_cap_5
reg adcCore1_spiI_cap_5;
wire adcCore1_spiI_cap_5$D_IN, adcCore1_spiI_cap_5$EN;
// register adcCore1_spiI_cap_6
reg adcCore1_spiI_cap_6;
wire adcCore1_spiI_cap_6$D_IN, adcCore1_spiI_cap_6$EN;
// register adcCore1_spiI_cap_7
reg adcCore1_spiI_cap_7;
wire adcCore1_spiI_cap_7$D_IN, adcCore1_spiI_cap_7$EN;
// register adcCore1_spiI_csbR
reg adcCore1_spiI_csbR;
wire adcCore1_spiI_csbR$D_IN, adcCore1_spiI_csbR$EN;
// register adcCore1_spiI_dPos
reg [2 : 0] adcCore1_spiI_dPos;
wire [2 : 0] adcCore1_spiI_dPos$D_IN;
wire adcCore1_spiI_dPos$EN;
// register adcCore1_spiI_doResp
reg adcCore1_spiI_doResp;
wire adcCore1_spiI_doResp$D_IN, adcCore1_spiI_doResp$EN;
// register adcCore1_spiI_iPos
reg [3 : 0] adcCore1_spiI_iPos;
wire [3 : 0] adcCore1_spiI_iPos$D_IN;
wire adcCore1_spiI_iPos$EN;
// register adcCore1_spiI_reqF_head_wrapped
reg adcCore1_spiI_reqF_head_wrapped;
wire adcCore1_spiI_reqF_head_wrapped$D_IN,
adcCore1_spiI_reqF_head_wrapped$EN;
// register adcCore1_spiI_reqF_tail_wrapped
reg adcCore1_spiI_reqF_tail_wrapped;
wire adcCore1_spiI_reqF_tail_wrapped$D_IN,
adcCore1_spiI_reqF_tail_wrapped$EN;
// register adcCore1_spiI_reqS
reg [16 : 0] adcCore1_spiI_reqS;
reg [16 : 0] adcCore1_spiI_reqS$D_IN;
wire adcCore1_spiI_reqS$EN;
// register adcCore1_spiI_respF_head_wrapped
reg adcCore1_spiI_respF_head_wrapped;
wire adcCore1_spiI_respF_head_wrapped$D_IN,
adcCore1_spiI_respF_head_wrapped$EN;
// register adcCore1_spiI_respF_tail_wrapped
reg adcCore1_spiI_respF_tail_wrapped;
wire adcCore1_spiI_respF_tail_wrapped$D_IN,
adcCore1_spiI_respF_tail_wrapped$EN;
// register adcCore1_spiI_respS
reg [7 : 0] adcCore1_spiI_respS;
wire [7 : 0] adcCore1_spiI_respS$D_IN;
wire adcCore1_spiI_respS$EN;
// register adcCore1_spiI_sdiP
reg adcCore1_spiI_sdiP;
wire adcCore1_spiI_sdiP$D_IN, adcCore1_spiI_sdiP$EN;
// register adcCore1_spiI_sdoR
reg adcCore1_spiI_sdoR;
wire adcCore1_spiI_sdoR$D_IN, adcCore1_spiI_sdoR$EN;
// register adcCore1_spiI_xmt_d
reg adcCore1_spiI_xmt_d;
wire adcCore1_spiI_xmt_d$D_IN, adcCore1_spiI_xmt_d$EN;
// register adcCore1_spiI_xmt_i
reg adcCore1_spiI_xmt_i;
wire adcCore1_spiI_xmt_i$D_IN, adcCore1_spiI_xmt_i$EN;
// register adcIdc_doResetCount
reg [3 : 0] adcIdc_doResetCount;
wire [3 : 0] adcIdc_doResetCount$D_IN;
wire adcIdc_doResetCount$EN;
// register adcIdc_preResetCount
reg [3 : 0] adcIdc_preResetCount;
wire [3 : 0] adcIdc_preResetCount$D_IN;
wire adcIdc_preResetCount$EN;
// register fcAdc_countNow
reg [17 : 0] fcAdc_countNow;
wire [17 : 0] fcAdc_countNow$D_IN;
wire fcAdc_countNow$EN;
// register fcAdc_countPast
reg [17 : 0] fcAdc_countPast;
wire [17 : 0] fcAdc_countPast$D_IN;
wire fcAdc_countPast$EN;
// register fcAdc_frequency
reg [17 : 0] fcAdc_frequency;
wire [17 : 0] fcAdc_frequency$D_IN;
wire fcAdc_frequency$EN;
// register fcAdc_grayCounter_rdCounter
reg [17 : 0] fcAdc_grayCounter_rdCounter;
wire [17 : 0] fcAdc_grayCounter_rdCounter$D_IN;
wire fcAdc_grayCounter_rdCounter$EN;
// register fcAdc_grayCounter_rdCounterPre
reg [17 : 0] fcAdc_grayCounter_rdCounterPre;
wire [17 : 0] fcAdc_grayCounter_rdCounterPre$D_IN;
wire fcAdc_grayCounter_rdCounterPre$EN;
// register fcAdc_grayCounter_rsCounter
reg [17 : 0] fcAdc_grayCounter_rsCounter;
wire [17 : 0] fcAdc_grayCounter_rsCounter$D_IN;
wire fcAdc_grayCounter_rsCounter$EN;
// register fcAdc_pulseAction
reg fcAdc_pulseAction;
wire fcAdc_pulseAction$D_IN, fcAdc_pulseAction$EN;
// register fcAdc_sampleCount
reg [15 : 0] fcAdc_sampleCount;
wire [15 : 0] fcAdc_sampleCount$D_IN;
wire fcAdc_sampleCount$EN;
// register initOpInFlight
reg initOpInFlight;
wire initOpInFlight$D_IN, initOpInFlight$EN;
// register lastOverflowMesg
reg [31 : 0] lastOverflowMesg;
wire [31 : 0] lastOverflowMesg$D_IN;
wire lastOverflowMesg$EN;
// register maxMesgLength
reg [31 : 0] maxMesgLength;
wire [31 : 0] maxMesgLength$D_IN;
wire maxMesgLength$EN;
// register mesgCount
reg [31 : 0] mesgCount;
wire [31 : 0] mesgCount$D_IN;
wire mesgCount$EN;
// register oneKHz_value
reg [17 : 0] oneKHz_value;
wire [17 : 0] oneKHz_value$D_IN;
wire oneKHz_value$EN;
// register overflowCountD
reg [31 : 0] overflowCountD;
wire [31 : 0] overflowCountD$D_IN;
wire overflowCountD$EN;
// register sFlagState
reg sFlagState;
wire sFlagState$D_IN, sFlagState$EN;
// register spiClk_iState
reg [3 : 0] spiClk_iState;
wire [3 : 0] spiClk_iState$D_IN;
wire spiClk_iState$EN;
// register spiClk_iseqFsm_start_reg
reg spiClk_iseqFsm_start_reg;
wire spiClk_iseqFsm_start_reg$D_IN, spiClk_iseqFsm_start_reg$EN;
// register spiClk_iseqFsm_start_reg_1
reg spiClk_iseqFsm_start_reg_1;
wire spiClk_iseqFsm_start_reg_1$D_IN, spiClk_iseqFsm_start_reg_1$EN;
// register spiClk_iseqFsm_state_can_overlap
reg spiClk_iseqFsm_state_can_overlap;
wire spiClk_iseqFsm_state_can_overlap$D_IN,
spiClk_iseqFsm_state_can_overlap$EN;
// register spiClk_iseqFsm_state_fired
reg spiClk_iseqFsm_state_fired;
wire spiClk_iseqFsm_state_fired$D_IN, spiClk_iseqFsm_state_fired$EN;
// register spiClk_iseqFsm_state_mkFSMstate
reg [3 : 0] spiClk_iseqFsm_state_mkFSMstate;
reg [3 : 0] spiClk_iseqFsm_state_mkFSMstate$D_IN;
wire spiClk_iseqFsm_state_mkFSMstate$EN;
// register spiClk_spiI_cGate
reg spiClk_spiI_cGate;
wire spiClk_spiI_cGate$D_IN, spiClk_spiI_cGate$EN;
// register spiClk_spiI_cap
reg spiClk_spiI_cap;
wire spiClk_spiI_cap$D_IN, spiClk_spiI_cap$EN;
// register spiClk_spiI_cap_1
reg spiClk_spiI_cap_1;
wire spiClk_spiI_cap_1$D_IN, spiClk_spiI_cap_1$EN;
// register spiClk_spiI_cap_2
reg spiClk_spiI_cap_2;
wire spiClk_spiI_cap_2$D_IN, spiClk_spiI_cap_2$EN;
// register spiClk_spiI_cap_3
reg spiClk_spiI_cap_3;
wire spiClk_spiI_cap_3$D_IN, spiClk_spiI_cap_3$EN;
// register spiClk_spiI_cap_4
reg spiClk_spiI_cap_4;
wire spiClk_spiI_cap_4$D_IN, spiClk_spiI_cap_4$EN;
// register spiClk_spiI_cap_5
reg spiClk_spiI_cap_5;
wire spiClk_spiI_cap_5$D_IN, spiClk_spiI_cap_5$EN;
// register spiClk_spiI_cap_6
reg spiClk_spiI_cap_6;
wire spiClk_spiI_cap_6$D_IN, spiClk_spiI_cap_6$EN;
// register spiClk_spiI_cap_7
reg spiClk_spiI_cap_7;
wire spiClk_spiI_cap_7$D_IN, spiClk_spiI_cap_7$EN;
// register spiClk_spiI_csbR
reg spiClk_spiI_csbR;
wire spiClk_spiI_csbR$D_IN, spiClk_spiI_csbR$EN;
// register spiClk_spiI_dPos
reg [2 : 0] spiClk_spiI_dPos;
wire [2 : 0] spiClk_spiI_dPos$D_IN;
wire spiClk_spiI_dPos$EN;
// register spiClk_spiI_doResp
reg spiClk_spiI_doResp;
wire spiClk_spiI_doResp$D_IN, spiClk_spiI_doResp$EN;
// register spiClk_spiI_iPos
reg [3 : 0] spiClk_spiI_iPos;
wire [3 : 0] spiClk_spiI_iPos$D_IN;
wire spiClk_spiI_iPos$EN;
// register spiClk_spiI_reqF_head_wrapped
reg spiClk_spiI_reqF_head_wrapped;
wire spiClk_spiI_reqF_head_wrapped$D_IN, spiClk_spiI_reqF_head_wrapped$EN;
// register spiClk_spiI_reqF_tail_wrapped
reg spiClk_spiI_reqF_tail_wrapped;
wire spiClk_spiI_reqF_tail_wrapped$D_IN, spiClk_spiI_reqF_tail_wrapped$EN;
// register spiClk_spiI_reqS
reg [16 : 0] spiClk_spiI_reqS;
reg [16 : 0] spiClk_spiI_reqS$D_IN;
wire spiClk_spiI_reqS$EN;
// register spiClk_spiI_respF_head_wrapped
reg spiClk_spiI_respF_head_wrapped;
wire spiClk_spiI_respF_head_wrapped$D_IN, spiClk_spiI_respF_head_wrapped$EN;
// register spiClk_spiI_respF_tail_wrapped
reg spiClk_spiI_respF_tail_wrapped;
wire spiClk_spiI_respF_tail_wrapped$D_IN, spiClk_spiI_respF_tail_wrapped$EN;
// register spiClk_spiI_respS
reg [7 : 0] spiClk_spiI_respS;
wire [7 : 0] spiClk_spiI_respS$D_IN;
wire spiClk_spiI_respS$EN;
// register spiClk_spiI_sdiP
reg spiClk_spiI_sdiP;
wire spiClk_spiI_sdiP$D_IN, spiClk_spiI_sdiP$EN;
// register spiClk_spiI_sdoR
reg spiClk_spiI_sdoR;
wire spiClk_spiI_sdoR$D_IN, spiClk_spiI_sdoR$EN;
// register spiClk_spiI_xmt_d
reg spiClk_spiI_xmt_d;
wire spiClk_spiI_xmt_d$D_IN, spiClk_spiI_xmt_d$EN;
// register spiClk_spiI_xmt_i
reg spiClk_spiI_xmt_i;
wire spiClk_spiI_xmt_i$D_IN, spiClk_spiI_xmt_i$EN;
// register spiResp
reg [7 : 0] spiResp;
reg [7 : 0] spiResp$D_IN;
wire spiResp$EN;
// register splitReadInFlight
reg splitReadInFlight;
wire splitReadInFlight$D_IN, splitReadInFlight$EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge$D_IN;
wire wci_wslv_cEdge$EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState$D_IN;
wire wci_wslv_cState$EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState$D_IN;
wire wci_wslv_nState$EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg$D_IN;
wire wci_wslv_reqF_countReg$EN;
// register wci_wslv_respF_c_r
reg [1 : 0] wci_wslv_respF_c_r;
wire [1 : 0] wci_wslv_respF_c_r$D_IN;
wire wci_wslv_respF_c_r$EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0$D_IN;
wire wci_wslv_respF_q_0$EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1$D_IN;
wire wci_wslv_respF_q_1$EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wti_isReset_isInReset
reg wti_isReset_isInReset;
wire wti_isReset_isInReset$D_IN, wti_isReset_isInReset$EN;
// register wti_nowReq
reg [66 : 0] wti_nowReq;
wire [66 : 0] wti_nowReq$D_IN;
wire wti_nowReq$EN;
// register wti_operateD
reg wti_operateD;
wire wti_operateD$D_IN, wti_operateD$EN;
// ports of submodule adcCore0_acquireD
wire adcCore0_acquireD$dD_OUT,
adcCore0_acquireD$sD_IN,
adcCore0_acquireD$sEN,
adcCore0_acquireD$sRDY;
// ports of submodule adcCore0_averageD
wire adcCore0_averageD$dD_OUT,
adcCore0_averageD$sD_IN,
adcCore0_averageD$sEN,
adcCore0_averageD$sRDY;
// ports of submodule adcCore0_colGate_sampF
reg [38 : 0] adcCore0_colGate_sampF$D_IN;
wire [38 : 0] adcCore0_colGate_sampF$D_OUT;
wire adcCore0_colGate_sampF$CLR,
adcCore0_colGate_sampF$DEQ,
adcCore0_colGate_sampF$EMPTY_N,
adcCore0_colGate_sampF$ENQ,
adcCore0_colGate_sampF$FULL_N;
// ports of submodule adcCore0_ddrC_ddrV
wire [13 : 0] adcCore0_ddrC_ddrV$sdrData0, adcCore0_ddrC_ddrV$sdrData1;
wire [6 : 0] adcCore0_ddrC_ddrV$ddrDataN, adcCore0_ddrC_ddrV$ddrDataP;
wire adcCore0_ddrC_ddrV$psEna,
adcCore0_ddrC_ddrV$psInc,
adcCore0_ddrC_ddrV$sdrClk;
// ports of submodule adcCore0_maxBurstLengthR
wire [15 : 0] adcCore0_maxBurstLengthR$dD_OUT,
adcCore0_maxBurstLengthR$sD_IN;
wire adcCore0_maxBurstLengthR$sEN, adcCore0_maxBurstLengthR$sRDY;
// ports of submodule adcCore0_operateD
wire adcCore0_operateD$dD_OUT,
adcCore0_operateD$sD_IN,
adcCore0_operateD$sEN,
adcCore0_operateD$sRDY;
// ports of submodule adcCore0_reqF
wire [16 : 0] adcCore0_reqF$D_IN, adcCore0_reqF$D_OUT;
wire adcCore0_reqF$CLR,
adcCore0_reqF$DEQ,
adcCore0_reqF$EMPTY_N,
adcCore0_reqF$ENQ,
adcCore0_reqF$FULL_N;
// ports of submodule adcCore0_sampCC
wire [31 : 0] adcCore0_sampCC$dD_OUT, adcCore0_sampCC$sD_IN;
wire adcCore0_sampCC$sEN, adcCore0_sampCC$sRDY;
// ports of submodule adcCore0_sampF_memory
wire [38 : 0] adcCore0_sampF_memory$DIA,
adcCore0_sampF_memory$DIB,
adcCore0_sampF_memory$DOB;
wire [9 : 0] adcCore0_sampF_memory$ADDRA, adcCore0_sampF_memory$ADDRB;
wire adcCore0_sampF_memory$ENA,
adcCore0_sampF_memory$ENB,
adcCore0_sampF_memory$WEA,
adcCore0_sampF_memory$WEB;
// ports of submodule adcCore0_sdrRst
wire adcCore0_sdrRst$OUT_RST;
// ports of submodule adcCore0_spiI_cd
wire adcCore0_spiI_cd$CLK_OUT, adcCore0_spiI_cd$PREEDGE;
// ports of submodule adcCore0_spiI_cinv
wire adcCore0_spiI_cinv$CLK_OUT;
// ports of submodule adcCore0_spiI_reqF_dCombinedReset
wire adcCore0_spiI_reqF_dCombinedReset$RST_OUT;
// ports of submodule adcCore0_spiI_reqF_dCrossedsReset
wire adcCore0_spiI_reqF_dCrossedsReset$OUT_RST;
// ports of submodule adcCore0_spiI_reqF_dInReset
wire adcCore0_spiI_reqF_dInReset$VAL;
// ports of submodule adcCore0_spiI_reqF_sCombinedReset
wire adcCore0_spiI_reqF_sCombinedReset$RST_OUT;
// ports of submodule adcCore0_spiI_reqF_sCrosseddReset
wire adcCore0_spiI_reqF_sCrosseddReset$OUT_RST;
// ports of submodule adcCore0_spiI_reqF_sInReset
wire adcCore0_spiI_reqF_sInReset$VAL;
// ports of submodule adcCore0_spiI_respF_dCombinedReset
wire adcCore0_spiI_respF_dCombinedReset$RST_OUT;
// ports of submodule adcCore0_spiI_respF_dCrossedsReset
wire adcCore0_spiI_respF_dCrossedsReset$OUT_RST;
// ports of submodule adcCore0_spiI_respF_dInReset
wire adcCore0_spiI_respF_dInReset$VAL;
// ports of submodule adcCore0_spiI_respF_sCombinedReset
wire adcCore0_spiI_respF_sCombinedReset$RST_OUT;
// ports of submodule adcCore0_spiI_respF_sCrosseddReset
wire adcCore0_spiI_respF_sCrosseddReset$OUT_RST;
// ports of submodule adcCore0_spiI_respF_sInReset
wire adcCore0_spiI_respF_sInReset$VAL;
// ports of submodule adcCore0_spiI_slowReset
wire adcCore0_spiI_slowReset$OUT_RST;
// ports of submodule adcCore0_statsCC
wire [127 : 0] adcCore0_statsCC$dD_OUT, adcCore0_statsCC$sD_IN;
wire adcCore0_statsCC$sEN, adcCore0_statsCC$sRDY;
// ports of submodule adcCore1_acquireD
wire adcCore1_acquireD$dD_OUT,
adcCore1_acquireD$sD_IN,
adcCore1_acquireD$sEN,
adcCore1_acquireD$sRDY;
// ports of submodule adcCore1_averageD
wire adcCore1_averageD$dD_OUT,
adcCore1_averageD$sD_IN,
adcCore1_averageD$sEN,
adcCore1_averageD$sRDY;
// ports of submodule adcCore1_colGate_sampF
reg [38 : 0] adcCore1_colGate_sampF$D_IN;
wire [38 : 0] adcCore1_colGate_sampF$D_OUT;
wire adcCore1_colGate_sampF$CLR,
adcCore1_colGate_sampF$DEQ,
adcCore1_colGate_sampF$EMPTY_N,
adcCore1_colGate_sampF$ENQ,
adcCore1_colGate_sampF$FULL_N;
// ports of submodule adcCore1_ddrC_ddrV
wire [13 : 0] adcCore1_ddrC_ddrV$sdrData0, adcCore1_ddrC_ddrV$sdrData1;
wire [6 : 0] adcCore1_ddrC_ddrV$ddrDataN, adcCore1_ddrC_ddrV$ddrDataP;
wire adcCore1_ddrC_ddrV$psEna,
adcCore1_ddrC_ddrV$psInc,
adcCore1_ddrC_ddrV$sdrClk;
// ports of submodule adcCore1_maxBurstLengthR
wire [15 : 0] adcCore1_maxBurstLengthR$dD_OUT,
adcCore1_maxBurstLengthR$sD_IN;
wire adcCore1_maxBurstLengthR$sEN;
// ports of submodule adcCore1_operateD
wire adcCore1_operateD$dD_OUT,
adcCore1_operateD$sD_IN,
adcCore1_operateD$sEN,
adcCore1_operateD$sRDY;
// ports of submodule adcCore1_reqF
wire [16 : 0] adcCore1_reqF$D_IN, adcCore1_reqF$D_OUT;
wire adcCore1_reqF$CLR,
adcCore1_reqF$DEQ,
adcCore1_reqF$EMPTY_N,
adcCore1_reqF$ENQ,
adcCore1_reqF$FULL_N;
// ports of submodule adcCore1_sampCC
wire [31 : 0] adcCore1_sampCC$dD_OUT, adcCore1_sampCC$sD_IN;
wire adcCore1_sampCC$sEN, adcCore1_sampCC$sRDY;
// ports of submodule adcCore1_sampF_memory
wire [38 : 0] adcCore1_sampF_memory$DIA,
adcCore1_sampF_memory$DIB,
adcCore1_sampF_memory$DOB;
wire [9 : 0] adcCore1_sampF_memory$ADDRA, adcCore1_sampF_memory$ADDRB;
wire adcCore1_sampF_memory$ENA,
adcCore1_sampF_memory$ENB,
adcCore1_sampF_memory$WEA,
adcCore1_sampF_memory$WEB;
// ports of submodule adcCore1_sdrRst
wire adcCore1_sdrRst$OUT_RST;
// ports of submodule adcCore1_spiI_cd
wire adcCore1_spiI_cd$CLK_OUT, adcCore1_spiI_cd$PREEDGE;
// ports of submodule adcCore1_spiI_cinv
wire adcCore1_spiI_cinv$CLK_OUT;
// ports of submodule adcCore1_spiI_reqF_dCombinedReset
wire adcCore1_spiI_reqF_dCombinedReset$RST_OUT;
// ports of submodule adcCore1_spiI_reqF_dCrossedsReset
wire adcCore1_spiI_reqF_dCrossedsReset$OUT_RST;
// ports of submodule adcCore1_spiI_reqF_dInReset
wire adcCore1_spiI_reqF_dInReset$VAL;
// ports of submodule adcCore1_spiI_reqF_sCombinedReset
wire adcCore1_spiI_reqF_sCombinedReset$RST_OUT;
// ports of submodule adcCore1_spiI_reqF_sCrosseddReset
wire adcCore1_spiI_reqF_sCrosseddReset$OUT_RST;
// ports of submodule adcCore1_spiI_reqF_sInReset
wire adcCore1_spiI_reqF_sInReset$VAL;
// ports of submodule adcCore1_spiI_respF_dCombinedReset
wire adcCore1_spiI_respF_dCombinedReset$RST_OUT;
// ports of submodule adcCore1_spiI_respF_dCrossedsReset
wire adcCore1_spiI_respF_dCrossedsReset$OUT_RST;
// ports of submodule adcCore1_spiI_respF_dInReset
wire adcCore1_spiI_respF_dInReset$VAL;
// ports of submodule adcCore1_spiI_respF_sCombinedReset
wire adcCore1_spiI_respF_sCombinedReset$RST_OUT;
// ports of submodule adcCore1_spiI_respF_sCrosseddReset
wire adcCore1_spiI_respF_sCrosseddReset$OUT_RST;
// ports of submodule adcCore1_spiI_respF_sInReset
wire adcCore1_spiI_respF_sInReset$VAL;
// ports of submodule adcCore1_spiI_slowReset
wire adcCore1_spiI_slowReset$OUT_RST;
// ports of submodule adcCore1_statsCC
wire [127 : 0] adcCore1_statsCC$sD_IN;
wire adcCore1_statsCC$sEN, adcCore1_statsCC$sRDY;
// ports of submodule adcIdc
wire adcIdc$RDY;
// ports of submodule adcIdcRdyBit
wire adcIdcRdyBit$dD_OUT, adcIdcRdyBit$sD_IN, adcIdcRdyBit$sEN;
// ports of submodule adcIdc_idcRst
wire adcIdc_idcRst$ASSERT_IN, adcIdc_idcRst$OUT_RST;
// ports of submodule adcIdc_resetP
wire adcIdc_resetP$RESET_OUT;
// ports of submodule fcAdc_testRst
wire fcAdc_testRst$OUT_RST;
// ports of submodule spiClk_spiI_cd
wire spiClk_spiI_cd$CLK_OUT, spiClk_spiI_cd$PREEDGE;
// ports of submodule spiClk_spiI_cinv
wire spiClk_spiI_cinv$CLK_OUT;
// ports of submodule spiClk_spiI_reqF_dCombinedReset
wire spiClk_spiI_reqF_dCombinedReset$RST_OUT;
// ports of submodule spiClk_spiI_reqF_dCrossedsReset
wire spiClk_spiI_reqF_dCrossedsReset$OUT_RST;
// ports of submodule spiClk_spiI_reqF_dInReset
wire spiClk_spiI_reqF_dInReset$VAL;
// ports of submodule spiClk_spiI_reqF_sCombinedReset
wire spiClk_spiI_reqF_sCombinedReset$RST_OUT;
// ports of submodule spiClk_spiI_reqF_sCrosseddReset
wire spiClk_spiI_reqF_sCrosseddReset$OUT_RST;
// ports of submodule spiClk_spiI_reqF_sInReset
wire spiClk_spiI_reqF_sInReset$VAL;
// ports of submodule spiClk_spiI_respF_dCombinedReset
wire spiClk_spiI_respF_dCombinedReset$RST_OUT;
// ports of submodule spiClk_spiI_respF_dCrossedsReset
wire spiClk_spiI_respF_dCrossedsReset$OUT_RST;
// ports of submodule spiClk_spiI_respF_dInReset
wire spiClk_spiI_respF_dInReset$VAL;
// ports of submodule spiClk_spiI_respF_sCombinedReset
wire spiClk_spiI_respF_sCombinedReset$RST_OUT;
// ports of submodule spiClk_spiI_respF_sCrosseddReset
wire spiClk_spiI_respF_sCrosseddReset$OUT_RST;
// ports of submodule spiClk_spiI_respF_sInReset
wire spiClk_spiI_respF_sInReset$VAL;
// ports of submodule spiClk_spiI_slowReset
wire spiClk_spiI_slowReset$OUT_RST;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT;
wire wci_wslv_reqF$CLR,
wci_wslv_reqF$DEQ,
wci_wslv_reqF$EMPTY_N,
wci_wslv_reqF$ENQ;
// rule scheduling signals
wire CAN_FIRE_RL_get_adc0_resp,
CAN_FIRE_RL_get_adc1_resp,
CAN_FIRE_RL_get_adx_resp,
CAN_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_adcCore0_advance_spi_request,
WILL_FIRE_RL_adcCore0_colGate_capture_collect,
WILL_FIRE_RL_adcCore0_colGate_count_dropped_samples,
WILL_FIRE_RL_adcCore0_colGate_count_dwells,
WILL_FIRE_RL_adcCore0_colGate_form_avg4_sample,
WILL_FIRE_RL_adcCore0_colGate_overrun_recovery,
WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg,
WILL_FIRE_RL_adcCore0_colGate_send_timestamp_mesg,
WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12,
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9,
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9,
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9,
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9,
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9,
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9,
WILL_FIRE_RL_adcCore0_iseqFsm_action_np,
WILL_FIRE_RL_adcCore0_iseqFsm_fsm_start,
WILL_FIRE_RL_adcCore0_iseqFsm_idle_l115c3,
WILL_FIRE_RL_adcCore0_spiI_reqF_deq_update_head,
WILL_FIRE_RL_adcCore0_spiI_reqF_enq_update_tail,
WILL_FIRE_RL_adcCore0_spiI_respF_deq_update_head,
WILL_FIRE_RL_adcCore0_spiI_respF_enq_update_tail,
WILL_FIRE_RL_adcCore0_spiI_send_d,
WILL_FIRE_RL_adcCore0_spiI_send_i,
WILL_FIRE_RL_adcCore0_spiI_start_cs,
WILL_FIRE_RL_adcCore1_advance_spi_request,
WILL_FIRE_RL_adcCore1_colGate_capture_collect,
WILL_FIRE_RL_adcCore1_colGate_count_dropped_samples,
WILL_FIRE_RL_adcCore1_colGate_count_dwells,
WILL_FIRE_RL_adcCore1_colGate_form_avg4_sample,
WILL_FIRE_RL_adcCore1_colGate_overrun_recovery,
WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg,
WILL_FIRE_RL_adcCore1_colGate_send_timestamp_mesg,
WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12,
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9,
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9,
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9,
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9,
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9,
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9,
WILL_FIRE_RL_adcCore1_iseqFsm_action_np,
WILL_FIRE_RL_adcCore1_iseqFsm_fsm_start,
WILL_FIRE_RL_adcCore1_iseqFsm_idle_l115c3,
WILL_FIRE_RL_adcCore1_spiI_reqF_deq_update_head,
WILL_FIRE_RL_adcCore1_spiI_reqF_enq_update_tail,
WILL_FIRE_RL_adcCore1_spiI_respF_deq_update_head,
WILL_FIRE_RL_adcCore1_spiI_respF_enq_update_tail,
WILL_FIRE_RL_adcCore1_spiI_send_d,
WILL_FIRE_RL_adcCore1_spiI_send_i,
WILL_FIRE_RL_adcCore1_spiI_start_cs,
WILL_FIRE_RL_doMessage,
WILL_FIRE_RL_get_adc1_resp,
WILL_FIRE_RL_init_complete_ok,
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9,
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9,
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9,
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9,
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9,
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9,
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9,
WILL_FIRE_RL_spiClk_iseqFsm_fsm_start,
WILL_FIRE_RL_spiClk_iseqFsm_idle_l43c3,
WILL_FIRE_RL_spiClk_spiI_reqF_deq_update_head,
WILL_FIRE_RL_spiClk_spiI_reqF_enq_update_tail,
WILL_FIRE_RL_spiClk_spiI_respF_deq_update_head,
WILL_FIRE_RL_spiClk_spiI_respF_enq_update_tail,
WILL_FIRE_RL_spiClk_spiI_send_d,
WILL_FIRE_RL_spiClk_spiI_send_i,
WILL_FIRE_RL_spiClk_spiI_start_cs,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1,
MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
wire [38 : 0] MUX_adcCore0_colGate_sampF$enq_1__VAL_1,
MUX_adcCore0_colGate_sampF$enq_1__VAL_2,
MUX_adcCore0_colGate_sampF$enq_1__VAL_3,
MUX_adcCore1_colGate_sampF$enq_1__VAL_1,
MUX_adcCore1_colGate_sampF$enq_1__VAL_2,
MUX_adcCore1_colGate_sampF$enq_1__VAL_3;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
MUX_wci_wslv_respF_q_1$write_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_4,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_5;
wire [31 : 0] MUX_adcCore0_colGate_dropCount$write_1__VAL_1,
MUX_adcCore0_colGate_dwellFails$write_1__VAL_1,
MUX_adcCore0_colGate_dwellStarts$write_1__VAL_1,
MUX_adcCore0_colGate_sampCount$write_1__VAL_1,
MUX_adcCore1_colGate_dropCount$write_1__VAL_1,
MUX_adcCore1_colGate_dwellFails$write_1__VAL_1,
MUX_adcCore1_colGate_dwellStarts$write_1__VAL_1,
MUX_adcCore1_colGate_sampCount$write_1__VAL_1;
wire [17 : 0] MUX_fcAdc_grayCounter_rsCounter$write_1__VAL_1,
MUX_oneKHz_value$write_1__VAL_1;
wire [16 : 0] MUX_adcCore0_reqF$enq_1__VAL_1,
MUX_adcCore0_reqF$enq_1__VAL_2,
MUX_adcCore0_spiI_reqS$write_1__VAL_1,
MUX_adcCore1_spiI_reqS$write_1__VAL_1;
wire [15 : 0] MUX_adcCore0_colGate_uprollCnt$write_1__VAL_2,
MUX_adcCore1_colGate_uprollCnt$write_1__VAL_2;
wire [12 : 0] MUX_adcCore0_iseqFsm_jj_delay_count$write_1__VAL_1,
MUX_adcCore1_iseqFsm_jj_delay_count$write_1__VAL_1;
wire [10 : 0] MUX_adcCore0_sampF_rRdPtr_rsCounter$write_1__VAL_1,
MUX_adcCore0_sampF_rWrPtr_rsCounter$write_1__VAL_1,
MUX_adcCore1_sampF_rWrPtr_rsCounter$write_1__VAL_1;
wire [3 : 0] MUX_adcCore0_colGate_ovrRecover$write_1__VAL_2,
MUX_adcCore0_spiI_iPos$write_1__VAL_1,
MUX_adcCore1_colGate_ovrRecover$write_1__VAL_2,
MUX_adcCore1_spiI_iPos$write_1__VAL_1,
MUX_spiClk_spiI_iPos$write_1__VAL_1;
wire [2 : 0] MUX_adcCore0_colGate_timeMesg$write_1__VAL_1,
MUX_adcCore0_spiI_dPos$write_1__VAL_1,
MUX_adcCore1_colGate_timeMesg$write_1__VAL_1,
MUX_adcCore1_spiI_dPos$write_1__VAL_1,
MUX_spiClk_spiI_dPos$write_1__VAL_1;
wire [1 : 0] MUX_adcCore0_colGate_syncMesg$write_1__VAL_1,
MUX_adcCore1_colGate_syncMesg$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_adcCore0_colGate_dwellFails$write_1__SEL_1,
MUX_adcCore0_colGate_sampF$enq_1__SEL_1,
MUX_adcCore0_reqF$enq_1__SEL_1,
MUX_adcCore0_spiI_sdoR_1$wset_1__VAL_1,
MUX_adcCore0_spiI_sdoR_1$wset_1__VAL_2,
MUX_adcCore0_spiI_xmt_d$write_1__SEL_2,
MUX_adcCore1_colGate_dwellFails$write_1__SEL_1,
MUX_adcCore1_colGate_sampF$enq_1__SEL_1,
MUX_adcCore1_reqF$enq_1__SEL_1,
MUX_adcCore1_spiI_sdoR_1$wset_1__VAL_1,
MUX_adcCore1_spiI_sdoR_1$wset_1__VAL_2,
MUX_adcCore1_spiI_xmt_d$write_1__SEL_2,
MUX_spiClk_spiI_reqS$write_1__SEL_1,
MUX_spiClk_spiI_reqS$write_1__SEL_2,
MUX_spiClk_spiI_sdoR_1$wset_1__VAL_1,
MUX_spiClk_spiI_sdoR_1$wset_1__VAL_2,
MUX_spiClk_spiI_xmt_d$write_1__SEL_2,
MUX_splitReadInFlight$write_1__PSEL_1,
MUX_splitReadInFlight$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1,
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2,
MUX_wci_wslv_respF_x_wire$wset_1__SEL_1,
MUX_wci_wslv_respF_x_wire$wset_1__SEL_2,
MUX_wci_wslv_respF_x_wire$wset_1__SEL_3,
MUX_wci_wslv_respF_x_wire$wset_1__SEL_4,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
MUX_wsiM_reqFifo_q_1$write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h130298, v__h131387, v__h3700, v__h3875, v__h4019;
reg [31 : 0] IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092,
x1_data__h35585,
x1_data__h81295;
reg CASE_adcCore0_colGate_avgPhase_0b1_0_1_1_1_2_1_ETC__q4,
CASE_adcCore1_colGate_avgPhase_0b1_0_1_1_1_2_1_ETC__q5,
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_NOT_wci_ETC__q3;
wire [63 : 0] wti_nowReq_BITS_63_TO_0__q1;
wire [31 : 0] IF_adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_ETC___d2461,
IF_adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_ETC___d2462,
IF_adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_ETC___d2458,
IF_adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_ETC___d2459,
IF_adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_3_ETC___d2467,
IF_adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_3_ETC___d2468,
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d2454,
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d2455,
adcStatusLs__h130971,
avgDataBW__h35898,
avgDataBW__h81608,
d_data__h35985,
d_data__h81695,
rdat__h131371,
rdat__h131450,
rdat__h131531,
rdat__h131557;
wire [17 : 0] x__h36250,
x__h36260,
x__h36326,
x__h36400,
x__h36410,
x__h7511,
x__h81960,
x__h81970,
x__h82036,
x__h82110,
x__h82120,
y__h36411,
y__h36413,
y__h82121,
y__h82123,
y__h8916;
wire [11 : 0] x_burstLength__h128706;
wire [10 : 0] adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216,
x__h38579,
x__h40881,
x__h44308,
x__h84289,
x_dReadBin__h42694,
x_dReadBin__h88404,
x_sReadBin__h42691,
y__h39466,
y__h41768,
y__h85176;
wire [9 : 0] x2__h44277, x2__h89987;
wire [7 : 0] adcCore0_spiI_reqS_BITS_15_TO_8__q6,
adcCore0_spiI_reqS_BITS_7_TO_0__q7,
adcCore1_spiI_reqS_BITS_15_TO_8__q9,
adcCore1_spiI_reqS_BITS_7_TO_0__q8,
spiClk_spiI_reqS_BITS_15_TO_8__q2,
spiClk_spiI_reqS_BITS_7_TO_0__q10;
wire IF_spiClk_spiI_iPos_89_EQ_15_90_THEN_NOT_spiCl_ETC___d401,
IF_wci_wslv_reqF_first__5_BITS_43_TO_42_943_EQ_ETC___d1970,
IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1968,
IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d2447,
NOT_adcCore0_sampF_rRdPtr_rsCounter_59_EQ_adcC_ETC___d1909,
NOT_adcCore0_spiI_reqF_head_wrapped__read__82__ETC___d1025,
NOT_adcCore1_spiI_reqF_head_wrapped__read__629_ETC___d1672,
NOT_spiClk_spiI_reqF_head_wrapped__read__39_EQ_ETC___d382,
adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d590,
adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d601,
adcCore0_colGate_sampF_RDY_first__04_AND_NOT_a_ETC___d961,
adcCore0_colGate_uprollCnt_04_EQ_adcCore0_colG_ETC___d2230,
adcCore0_iseqFsm_abort_whas__080_AND_adcCore0__ETC___d1152,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2169,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2170,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2171,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2172,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2173,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2174,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2175,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2178,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2200,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_XO_ETC___d2328,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2150,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2161,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2162,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2163,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2164,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2165,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2166,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2167,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2168,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2231,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_XO_ETC___d2327,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2142,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2143,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2144,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2145,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2146,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2148,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2155,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2156,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2157,
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130,
adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1237,
adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1248,
adcCore1_colGate_sampF_RDY_first__551_AND_NOT__ETC___d1608,
adcCore1_colGate_uprollCnt_251_EQ_adcCore1_col_ETC___d2234,
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d1799,
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d2103,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2194,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2195,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2196,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2197,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2198,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2203,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2204,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2205,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2215,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2187,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2188,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2189,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2190,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2191,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2192,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2193,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2199,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2202,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_344__ETC___d2338,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2179,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2180,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2181,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2182,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2183,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2184,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2185,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2186,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2201,
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2132,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2133,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2134,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2135,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2136,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2137,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2138,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2139,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2140,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2141,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2147,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2149,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2151,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2152,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2153,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2154,
fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d2326,
initOpInFlight_041_AND_adcCore0_iseqFsm_abort__ETC___d2110,
spiClk_iseqFsm_abort_whas__53_AND_spiClk_iseqF_ETC___d513,
spiClk_spiI_iPos_89_EQ_14_92_OR_spiClk_spiI_iP_ETC___d400,
spiClk_spiI_iPos_89_ULE_12___d2220,
spiClk_spiI_iPos_89_ULT_7___d2219,
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402,
x__h17146,
z__h39510,
z__h39517,
z__h39524,
z__h39531,
z__h39538,
z__h39545,
z__h39552,
z__h39559,
z__h39566,
z__h41812,
z__h41819,
z__h41826,
z__h41833,
z__h41840,
z__h41847,
z__h41854,
z__h41861,
z__h41868,
z__h7531,
z__h7538,
z__h7545,
z__h7552,
z__h7559,
z__h7566,
z__h7573,
z__h7580,
z__h7587,
z__h7594,
z__h7601,
z__h7608,
z__h7615,
z__h7622,
z__h7629,
z__h7636,
z__h85220,
z__h85227,
z__h85234,
z__h85241,
z__h85248,
z__h85255,
z__h85262,
z__h85269,
z__h85276;
// oscillator and gates for output clock CLK_adx_sclk
assign CLK_adx_sclk = spiClk_spiI_cd$CLK_OUT ;
assign CLK_GATE_adx_sclk = 1'b1 ;
// oscillator and gates for output clock CLK_adx_sclkn
assign CLK_adx_sclkn = spiClk_spiI_cinv$CLK_OUT ;
assign CLK_GATE_adx_sclkn = 1'b1 ;
// oscillator and gates for output clock CLK_adc0_sclk
assign CLK_adc0_sclk = adcCore0_spiI_cd$CLK_OUT ;
assign CLK_GATE_adc0_sclk = 1'b1 ;
// oscillator and gates for output clock CLK_adc0_sclkn
assign CLK_adc0_sclkn = adcCore0_spiI_cinv$CLK_OUT ;
assign CLK_GATE_adc0_sclkn = 1'b1 ;
// oscillator and gates for output clock CLK_adc1_sclk
assign CLK_adc1_sclk = adcCore1_spiI_cd$CLK_OUT ;
assign CLK_GATE_adc1_sclk = 1'b1 ;
// oscillator and gates for output clock CLK_adc1_sclkn
assign CLK_adc1_sclkn = adcCore1_spiI_cinv$CLK_OUT ;
assign CLK_GATE_adc1_sclkn = 1'b1 ;
// oscillator and gates for output clock CLK_adcSdrClk
assign CLK_adcSdrClk = adcCore0_ddrC_ddrV$sdrClk ;
assign CLK_GATE_adcSdrClk = 1'b1 ;
// output resets
assign RST_N_adx_srst = spiClk_spiI_slowReset$OUT_RST ;
assign RST_N_adc0_rst = adcCore0_spiI_slowReset$OUT_RST ;
assign RST_N_adc1_rst = adcCore1_spiI_slowReset$OUT_RST ;
assign RST_N_adcSdrRst = adcCore0_sdrRst$OUT_RST ;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wtiS0_sThreadBusy
assign wtiS0_SThreadBusy = wti_isReset_isInReset ;
// value method wtiS0_sReset_n
assign wtiS0_SReset_n = !wti_isReset_isInReset && wti_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// value method adx_adx_csb
assign adx_csb = spiClk_spiI_csbR ;
// value method adx_adx_sdo
assign adx_sdo = spiClk_spiI_sdoR ;
// value method adx_adx_funct
assign adx_funct = 1'b1 ;
// value method adc0_oe
assign adc0_oe = 1'd1 ;
// value method adc0_resetp
assign adc0_resetp = adcCore0_adcRst ;
// value method adc0_sen
assign adc0_sen = adcCore0_spiI_csbR ;
// value method adc0_sdata
assign adc0_sdata = adcCore0_spiI_sdoR ;
// value method adc1_oe
assign adc1_oe = 1'd1 ;
// value method adc1_resetp
assign adc1_resetp = adcCore1_adcRst ;
// value method adc1_sen
assign adc1_sen = adcCore1_spiI_csbR ;
// value method adc1_sdata
assign adc1_sdata = adcCore1_spiI_sdoR ;
// submodule adcCore0_acquireD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore0_acquireD(.sCLK(wciS0_Clk),
.dCLK(adcCore0_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore0_acquireD$sD_IN),
.sEN(adcCore0_acquireD$sEN),
.dD_OUT(adcCore0_acquireD$dD_OUT),
.sRDY(adcCore0_acquireD$sRDY));
// submodule adcCore0_averageD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore0_averageD(.sCLK(wciS0_Clk),
.dCLK(adcCore0_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore0_averageD$sD_IN),
.sEN(adcCore0_averageD$sEN),
.dD_OUT(adcCore0_averageD$dD_OUT),
.sRDY(adcCore0_averageD$sRDY));
// submodule adcCore0_colGate_sampF
arSRLFIFOD #(.width(32'd39),
.l2depth(32'd4)) adcCore0_colGate_sampF(.CLK(adcCore0_ddrC_ddrV$sdrClk),
.RST_N(adcCore0_sdrRst$OUT_RST),
.D_IN(adcCore0_colGate_sampF$D_IN),
.ENQ(adcCore0_colGate_sampF$ENQ),
.DEQ(adcCore0_colGate_sampF$DEQ),
.CLR(adcCore0_colGate_sampF$CLR),
.D_OUT(adcCore0_colGate_sampF$D_OUT),
.FULL_N(adcCore0_colGate_sampF$FULL_N),
.EMPTY_N(adcCore0_colGate_sampF$EMPTY_N));
// submodule adcCore0_ddrC_ddrV
ddrInput2 adcCore0_ddrC_ddrV(.psClk(wciS0_Clk),
.psRstN(wciS0_MReset_n),
.ddrClk(CLK_adc0_clk),
.ddrDataN(adcCore0_ddrC_ddrV$ddrDataN),
.ddrDataP(adcCore0_ddrC_ddrV$ddrDataP),
.psEna(adcCore0_ddrC_ddrV$psEna),
.psInc(adcCore0_ddrC_ddrV$psInc),
.sdrData0(adcCore0_ddrC_ddrV$sdrData0),
.sdrData1(adcCore0_ddrC_ddrV$sdrData1),
.sdrClk(adcCore0_ddrC_ddrV$sdrClk));
// submodule adcCore0_maxBurstLengthR
SyncRegister #(.width(32'd16),
.init(16'd0)) adcCore0_maxBurstLengthR(.sCLK(wciS0_Clk),
.dCLK(adcCore0_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore0_maxBurstLengthR$sD_IN),
.sEN(adcCore0_maxBurstLengthR$sEN),
.dD_OUT(adcCore0_maxBurstLengthR$dD_OUT),
.sRDY(adcCore0_maxBurstLengthR$sRDY));
// submodule adcCore0_operateD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore0_operateD(.sCLK(wciS0_Clk),
.dCLK(adcCore0_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore0_operateD$sD_IN),
.sEN(adcCore0_operateD$sEN),
.dD_OUT(adcCore0_operateD$dD_OUT),
.sRDY(adcCore0_operateD$sRDY));
// submodule adcCore0_reqF
FIFO2 #(.width(32'd17), .guarded(32'd1)) adcCore0_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(adcCore0_reqF$D_IN),
.ENQ(adcCore0_reqF$ENQ),
.DEQ(adcCore0_reqF$DEQ),
.CLR(adcCore0_reqF$CLR),
.D_OUT(adcCore0_reqF$D_OUT),
.FULL_N(adcCore0_reqF$FULL_N),
.EMPTY_N(adcCore0_reqF$EMPTY_N));
// submodule adcCore0_sampCC
SyncRegister #(.width(32'd32),
.init(32'd0)) adcCore0_sampCC(.sCLK(adcCore0_ddrC_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(adcCore0_sdrRst$OUT_RST),
.sD_IN(adcCore0_sampCC$sD_IN),
.sEN(adcCore0_sampCC$sEN),
.dD_OUT(adcCore0_sampCC$dD_OUT),
.sRDY(adcCore0_sampCC$sRDY));
// submodule adcCore0_sampF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd39),
.MEMSIZE(11'd1024)) adcCore0_sampF_memory(.CLKA(adcCore0_ddrC_ddrV$sdrClk),
.CLKB(wciS0_Clk),
.ADDRA(adcCore0_sampF_memory$ADDRA),
.ADDRB(adcCore0_sampF_memory$ADDRB),
.DIA(adcCore0_sampF_memory$DIA),
.DIB(adcCore0_sampF_memory$DIB),
.WEA(adcCore0_sampF_memory$WEA),
.WEB(adcCore0_sampF_memory$WEB),
.ENA(adcCore0_sampF_memory$ENA),
.ENB(adcCore0_sampF_memory$ENB),
.DOA(),
.DOB(adcCore0_sampF_memory$DOB));
// submodule adcCore0_sdrRst
SyncResetA #(.RSTDELAY(32'd1)) adcCore0_sdrRst(.CLK(adcCore0_ddrC_ddrV$sdrClk),
.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore0_sdrRst$OUT_RST));
// submodule adcCore0_spiI_cd
ClockDiv #(.width(32'd3),
.lower(32'd0),
.upper(32'd7),
.offset(32'd0)) adcCore0_spiI_cd(.CLK_IN(wciS0_Clk),
.RST(wciS0_MReset_n),
.PREEDGE(adcCore0_spiI_cd$PREEDGE),
.CLK_OUT(adcCore0_spiI_cd$CLK_OUT));
// submodule adcCore0_spiI_cinv
ClockInverter adcCore0_spiI_cinv(.CLK_IN(adcCore0_spiI_cd$CLK_OUT),
.PREEDGE(),
.CLK_OUT(adcCore0_spiI_cinv$CLK_OUT));
// submodule adcCore0_spiI_reqF_dCombinedReset
ResetEither adcCore0_spiI_reqF_dCombinedReset(.A_RST(adcCore0_spiI_slowReset$OUT_RST),
.B_RST(adcCore0_spiI_reqF_dCrossedsReset$OUT_RST),
.RST_OUT(adcCore0_spiI_reqF_dCombinedReset$RST_OUT));
// submodule adcCore0_spiI_reqF_dCrossedsReset
SyncReset0 adcCore0_spiI_reqF_dCrossedsReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore0_spiI_reqF_dCrossedsReset$OUT_RST));
// submodule adcCore0_spiI_reqF_dInReset
ResetToBool adcCore0_spiI_reqF_dInReset(.RST(adcCore0_spiI_reqF_dCombinedReset$RST_OUT),
.VAL(adcCore0_spiI_reqF_dInReset$VAL));
// submodule adcCore0_spiI_reqF_sCombinedReset
ResetEither adcCore0_spiI_reqF_sCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(adcCore0_spiI_reqF_sCrosseddReset$OUT_RST),
.RST_OUT(adcCore0_spiI_reqF_sCombinedReset$RST_OUT));
// submodule adcCore0_spiI_reqF_sCrosseddReset
SyncReset0 adcCore0_spiI_reqF_sCrosseddReset(.IN_RST(adcCore0_spiI_slowReset$OUT_RST),
.OUT_RST(adcCore0_spiI_reqF_sCrosseddReset$OUT_RST));
// submodule adcCore0_spiI_reqF_sInReset
ResetToBool adcCore0_spiI_reqF_sInReset(.RST(adcCore0_spiI_reqF_sCombinedReset$RST_OUT),
.VAL(adcCore0_spiI_reqF_sInReset$VAL));
// submodule adcCore0_spiI_respF_dCombinedReset
ResetEither adcCore0_spiI_respF_dCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(adcCore0_spiI_respF_dCrossedsReset$OUT_RST),
.RST_OUT(adcCore0_spiI_respF_dCombinedReset$RST_OUT));
// submodule adcCore0_spiI_respF_dCrossedsReset
SyncReset0 adcCore0_spiI_respF_dCrossedsReset(.IN_RST(adcCore0_spiI_slowReset$OUT_RST),
.OUT_RST(adcCore0_spiI_respF_dCrossedsReset$OUT_RST));
// submodule adcCore0_spiI_respF_dInReset
ResetToBool adcCore0_spiI_respF_dInReset(.RST(adcCore0_spiI_respF_dCombinedReset$RST_OUT),
.VAL(adcCore0_spiI_respF_dInReset$VAL));
// submodule adcCore0_spiI_respF_sCombinedReset
ResetEither adcCore0_spiI_respF_sCombinedReset(.A_RST(adcCore0_spiI_slowReset$OUT_RST),
.B_RST(adcCore0_spiI_respF_sCrosseddReset$OUT_RST),
.RST_OUT(adcCore0_spiI_respF_sCombinedReset$RST_OUT));
// submodule adcCore0_spiI_respF_sCrosseddReset
SyncReset0 adcCore0_spiI_respF_sCrosseddReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore0_spiI_respF_sCrosseddReset$OUT_RST));
// submodule adcCore0_spiI_respF_sInReset
ResetToBool adcCore0_spiI_respF_sInReset(.RST(adcCore0_spiI_respF_sCombinedReset$RST_OUT),
.VAL(adcCore0_spiI_respF_sInReset$VAL));
// submodule adcCore0_spiI_slowReset
SyncResetA #(.RSTDELAY(32'd1)) adcCore0_spiI_slowReset(.CLK(adcCore0_spiI_cd$CLK_OUT),
.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore0_spiI_slowReset$OUT_RST));
// submodule adcCore0_statsCC
SyncRegister #(.width(32'd128),
.init(128'd0)) adcCore0_statsCC(.sCLK(adcCore0_ddrC_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(adcCore0_sdrRst$OUT_RST),
.sD_IN(adcCore0_statsCC$sD_IN),
.sEN(adcCore0_statsCC$sEN),
.dD_OUT(adcCore0_statsCC$dD_OUT),
.sRDY(adcCore0_statsCC$sRDY));
// submodule adcCore1_acquireD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore1_acquireD(.sCLK(wciS0_Clk),
.dCLK(adcCore1_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore1_acquireD$sD_IN),
.sEN(adcCore1_acquireD$sEN),
.dD_OUT(adcCore1_acquireD$dD_OUT),
.sRDY(adcCore1_acquireD$sRDY));
// submodule adcCore1_averageD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore1_averageD(.sCLK(wciS0_Clk),
.dCLK(adcCore1_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore1_averageD$sD_IN),
.sEN(adcCore1_averageD$sEN),
.dD_OUT(adcCore1_averageD$dD_OUT),
.sRDY(adcCore1_averageD$sRDY));
// submodule adcCore1_colGate_sampF
arSRLFIFOD #(.width(32'd39),
.l2depth(32'd4)) adcCore1_colGate_sampF(.CLK(adcCore1_ddrC_ddrV$sdrClk),
.RST_N(adcCore1_sdrRst$OUT_RST),
.D_IN(adcCore1_colGate_sampF$D_IN),
.ENQ(adcCore1_colGate_sampF$ENQ),
.DEQ(adcCore1_colGate_sampF$DEQ),
.CLR(adcCore1_colGate_sampF$CLR),
.D_OUT(adcCore1_colGate_sampF$D_OUT),
.FULL_N(adcCore1_colGate_sampF$FULL_N),
.EMPTY_N(adcCore1_colGate_sampF$EMPTY_N));
// submodule adcCore1_ddrC_ddrV
ddrInput2 adcCore1_ddrC_ddrV(.psClk(wciS0_Clk),
.psRstN(wciS0_MReset_n),
.ddrClk(CLK_adc1_clk),
.ddrDataN(adcCore1_ddrC_ddrV$ddrDataN),
.ddrDataP(adcCore1_ddrC_ddrV$ddrDataP),
.psEna(adcCore1_ddrC_ddrV$psEna),
.psInc(adcCore1_ddrC_ddrV$psInc),
.sdrData0(adcCore1_ddrC_ddrV$sdrData0),
.sdrData1(adcCore1_ddrC_ddrV$sdrData1),
.sdrClk(adcCore1_ddrC_ddrV$sdrClk));
// submodule adcCore1_maxBurstLengthR
SyncRegister #(.width(32'd16),
.init(16'd0)) adcCore1_maxBurstLengthR(.sCLK(wciS0_Clk),
.dCLK(adcCore1_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore1_maxBurstLengthR$sD_IN),
.sEN(adcCore1_maxBurstLengthR$sEN),
.dD_OUT(adcCore1_maxBurstLengthR$dD_OUT),
.sRDY());
// submodule adcCore1_operateD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore1_operateD(.sCLK(wciS0_Clk),
.dCLK(adcCore1_ddrC_ddrV$sdrClk),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore1_operateD$sD_IN),
.sEN(adcCore1_operateD$sEN),
.dD_OUT(adcCore1_operateD$dD_OUT),
.sRDY(adcCore1_operateD$sRDY));
// submodule adcCore1_reqF
FIFO2 #(.width(32'd17), .guarded(32'd1)) adcCore1_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(adcCore1_reqF$D_IN),
.ENQ(adcCore1_reqF$ENQ),
.DEQ(adcCore1_reqF$DEQ),
.CLR(adcCore1_reqF$CLR),
.D_OUT(adcCore1_reqF$D_OUT),
.FULL_N(adcCore1_reqF$FULL_N),
.EMPTY_N(adcCore1_reqF$EMPTY_N));
// submodule adcCore1_sampCC
SyncRegister #(.width(32'd32),
.init(32'd0)) adcCore1_sampCC(.sCLK(adcCore1_ddrC_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(adcCore1_sdrRst$OUT_RST),
.sD_IN(adcCore1_sampCC$sD_IN),
.sEN(adcCore1_sampCC$sEN),
.dD_OUT(adcCore1_sampCC$dD_OUT),
.sRDY(adcCore1_sampCC$sRDY));
// submodule adcCore1_sampF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd39),
.MEMSIZE(11'd1024)) adcCore1_sampF_memory(.CLKA(adcCore1_ddrC_ddrV$sdrClk),
.CLKB(wciS0_Clk),
.ADDRA(adcCore1_sampF_memory$ADDRA),
.ADDRB(adcCore1_sampF_memory$ADDRB),
.DIA(adcCore1_sampF_memory$DIA),
.DIB(adcCore1_sampF_memory$DIB),
.WEA(adcCore1_sampF_memory$WEA),
.WEB(adcCore1_sampF_memory$WEB),
.ENA(adcCore1_sampF_memory$ENA),
.ENB(adcCore1_sampF_memory$ENB),
.DOA(),
.DOB(adcCore1_sampF_memory$DOB));
// submodule adcCore1_sdrRst
SyncResetA #(.RSTDELAY(32'd1)) adcCore1_sdrRst(.CLK(adcCore1_ddrC_ddrV$sdrClk),
.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore1_sdrRst$OUT_RST));
// submodule adcCore1_spiI_cd
ClockDiv #(.width(32'd3),
.lower(32'd0),
.upper(32'd7),
.offset(32'd0)) adcCore1_spiI_cd(.CLK_IN(wciS0_Clk),
.RST(wciS0_MReset_n),
.PREEDGE(adcCore1_spiI_cd$PREEDGE),
.CLK_OUT(adcCore1_spiI_cd$CLK_OUT));
// submodule adcCore1_spiI_cinv
ClockInverter adcCore1_spiI_cinv(.CLK_IN(adcCore1_spiI_cd$CLK_OUT),
.PREEDGE(),
.CLK_OUT(adcCore1_spiI_cinv$CLK_OUT));
// submodule adcCore1_spiI_reqF_dCombinedReset
ResetEither adcCore1_spiI_reqF_dCombinedReset(.A_RST(adcCore1_spiI_slowReset$OUT_RST),
.B_RST(adcCore1_spiI_reqF_dCrossedsReset$OUT_RST),
.RST_OUT(adcCore1_spiI_reqF_dCombinedReset$RST_OUT));
// submodule adcCore1_spiI_reqF_dCrossedsReset
SyncReset0 adcCore1_spiI_reqF_dCrossedsReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore1_spiI_reqF_dCrossedsReset$OUT_RST));
// submodule adcCore1_spiI_reqF_dInReset
ResetToBool adcCore1_spiI_reqF_dInReset(.RST(adcCore1_spiI_reqF_dCombinedReset$RST_OUT),
.VAL(adcCore1_spiI_reqF_dInReset$VAL));
// submodule adcCore1_spiI_reqF_sCombinedReset
ResetEither adcCore1_spiI_reqF_sCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(adcCore1_spiI_reqF_sCrosseddReset$OUT_RST),
.RST_OUT(adcCore1_spiI_reqF_sCombinedReset$RST_OUT));
// submodule adcCore1_spiI_reqF_sCrosseddReset
SyncReset0 adcCore1_spiI_reqF_sCrosseddReset(.IN_RST(adcCore1_spiI_slowReset$OUT_RST),
.OUT_RST(adcCore1_spiI_reqF_sCrosseddReset$OUT_RST));
// submodule adcCore1_spiI_reqF_sInReset
ResetToBool adcCore1_spiI_reqF_sInReset(.RST(adcCore1_spiI_reqF_sCombinedReset$RST_OUT),
.VAL(adcCore1_spiI_reqF_sInReset$VAL));
// submodule adcCore1_spiI_respF_dCombinedReset
ResetEither adcCore1_spiI_respF_dCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(adcCore1_spiI_respF_dCrossedsReset$OUT_RST),
.RST_OUT(adcCore1_spiI_respF_dCombinedReset$RST_OUT));
// submodule adcCore1_spiI_respF_dCrossedsReset
SyncReset0 adcCore1_spiI_respF_dCrossedsReset(.IN_RST(adcCore1_spiI_slowReset$OUT_RST),
.OUT_RST(adcCore1_spiI_respF_dCrossedsReset$OUT_RST));
// submodule adcCore1_spiI_respF_dInReset
ResetToBool adcCore1_spiI_respF_dInReset(.RST(adcCore1_spiI_respF_dCombinedReset$RST_OUT),
.VAL(adcCore1_spiI_respF_dInReset$VAL));
// submodule adcCore1_spiI_respF_sCombinedReset
ResetEither adcCore1_spiI_respF_sCombinedReset(.A_RST(adcCore1_spiI_slowReset$OUT_RST),
.B_RST(adcCore1_spiI_respF_sCrosseddReset$OUT_RST),
.RST_OUT(adcCore1_spiI_respF_sCombinedReset$RST_OUT));
// submodule adcCore1_spiI_respF_sCrosseddReset
SyncReset0 adcCore1_spiI_respF_sCrosseddReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore1_spiI_respF_sCrosseddReset$OUT_RST));
// submodule adcCore1_spiI_respF_sInReset
ResetToBool adcCore1_spiI_respF_sInReset(.RST(adcCore1_spiI_respF_sCombinedReset$RST_OUT),
.VAL(adcCore1_spiI_respF_sInReset$VAL));
// submodule adcCore1_spiI_slowReset
SyncResetA #(.RSTDELAY(32'd1)) adcCore1_spiI_slowReset(.CLK(adcCore1_spiI_cd$CLK_OUT),
.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore1_spiI_slowReset$OUT_RST));
// submodule adcCore1_statsCC
SyncRegister #(.width(32'd128),
.init(128'd0)) adcCore1_statsCC(.sCLK(adcCore1_ddrC_ddrV$sdrClk),
.dCLK(wciS0_Clk),
.sRST(adcCore1_sdrRst$OUT_RST),
.sD_IN(adcCore1_statsCC$sD_IN),
.sEN(adcCore1_statsCC$sEN),
.dD_OUT(),
.sRDY(adcCore1_statsCC$sRDY));
// submodule adcIdc
IDELAYCTRL_GRP #(.IODELAY_GRP("IODELAY_ADC")) adcIdc(.REFCLK(CLK_sys0_clk),
.RST(adcIdc_resetP$RESET_OUT),
.RDY(adcIdc$RDY));
// submodule adcIdcRdyBit
SyncBit #(.init(1'd0)) adcIdcRdyBit(.sCLK(CLK_sys0_clk),
.dCLK(wciS0_Clk),
.sRST(RST_N_sys0_rst),
.sD_IN(adcIdcRdyBit$sD_IN),
.sEN(adcIdcRdyBit$sEN),
.dD_OUT(adcIdcRdyBit$dD_OUT));
// submodule adcIdc_idcRst
MakeResetA #(.RSTDELAY(32'd1),
.init(1'd0)) adcIdc_idcRst(.CLK(CLK_sys0_clk),
.RST(RST_N_sys0_rst),
.DST_CLK(CLK_sys0_clk),
.ASSERT_IN(adcIdc_idcRst$ASSERT_IN),
.ASSERT_OUT(),
.OUT_RST(adcIdc_idcRst$OUT_RST));
// submodule adcIdc_resetP
ResetInverter adcIdc_resetP(.RESET_IN(adcIdc_idcRst$OUT_RST),
.RESET_OUT(adcIdc_resetP$RESET_OUT));
// submodule fcAdc_testRst
SyncResetA #(.RSTDELAY(32'd1)) fcAdc_testRst(.CLK(CLK_adc_clk),
.IN_RST(wciS0_MReset_n),
.OUT_RST(fcAdc_testRst$OUT_RST));
// submodule spiClk_spiI_cd
ClockDiv #(.width(32'd3),
.lower(32'd0),
.upper(32'd7),
.offset(32'd0)) spiClk_spiI_cd(.CLK_IN(wciS0_Clk),
.RST(wciS0_MReset_n),
.PREEDGE(spiClk_spiI_cd$PREEDGE),
.CLK_OUT(spiClk_spiI_cd$CLK_OUT));
// submodule spiClk_spiI_cinv
ClockInverter spiClk_spiI_cinv(.CLK_IN(spiClk_spiI_cd$CLK_OUT),
.PREEDGE(),
.CLK_OUT(spiClk_spiI_cinv$CLK_OUT));
// submodule spiClk_spiI_reqF_dCombinedReset
ResetEither spiClk_spiI_reqF_dCombinedReset(.A_RST(spiClk_spiI_slowReset$OUT_RST),
.B_RST(spiClk_spiI_reqF_dCrossedsReset$OUT_RST),
.RST_OUT(spiClk_spiI_reqF_dCombinedReset$RST_OUT));
// submodule spiClk_spiI_reqF_dCrossedsReset
SyncReset0 spiClk_spiI_reqF_dCrossedsReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(spiClk_spiI_reqF_dCrossedsReset$OUT_RST));
// submodule spiClk_spiI_reqF_dInReset
ResetToBool spiClk_spiI_reqF_dInReset(.RST(spiClk_spiI_reqF_dCombinedReset$RST_OUT),
.VAL(spiClk_spiI_reqF_dInReset$VAL));
// submodule spiClk_spiI_reqF_sCombinedReset
ResetEither spiClk_spiI_reqF_sCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(spiClk_spiI_reqF_sCrosseddReset$OUT_RST),
.RST_OUT(spiClk_spiI_reqF_sCombinedReset$RST_OUT));
// submodule spiClk_spiI_reqF_sCrosseddReset
SyncReset0 spiClk_spiI_reqF_sCrosseddReset(.IN_RST(spiClk_spiI_slowReset$OUT_RST),
.OUT_RST(spiClk_spiI_reqF_sCrosseddReset$OUT_RST));
// submodule spiClk_spiI_reqF_sInReset
ResetToBool spiClk_spiI_reqF_sInReset(.RST(spiClk_spiI_reqF_sCombinedReset$RST_OUT),
.VAL(spiClk_spiI_reqF_sInReset$VAL));
// submodule spiClk_spiI_respF_dCombinedReset
ResetEither spiClk_spiI_respF_dCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(spiClk_spiI_respF_dCrossedsReset$OUT_RST),
.RST_OUT(spiClk_spiI_respF_dCombinedReset$RST_OUT));
// submodule spiClk_spiI_respF_dCrossedsReset
SyncReset0 spiClk_spiI_respF_dCrossedsReset(.IN_RST(spiClk_spiI_slowReset$OUT_RST),
.OUT_RST(spiClk_spiI_respF_dCrossedsReset$OUT_RST));
// submodule spiClk_spiI_respF_dInReset
ResetToBool spiClk_spiI_respF_dInReset(.RST(spiClk_spiI_respF_dCombinedReset$RST_OUT),
.VAL(spiClk_spiI_respF_dInReset$VAL));
// submodule spiClk_spiI_respF_sCombinedReset
ResetEither spiClk_spiI_respF_sCombinedReset(.A_RST(spiClk_spiI_slowReset$OUT_RST),
.B_RST(spiClk_spiI_respF_sCrosseddReset$OUT_RST),
.RST_OUT(spiClk_spiI_respF_sCombinedReset$RST_OUT));
// submodule spiClk_spiI_respF_sCrosseddReset
SyncReset0 spiClk_spiI_respF_sCrosseddReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(spiClk_spiI_respF_sCrosseddReset$OUT_RST));
// submodule spiClk_spiI_respF_sInReset
ResetToBool spiClk_spiI_respF_sInReset(.RST(spiClk_spiI_respF_sCombinedReset$RST_OUT),
.VAL(spiClk_spiI_respF_sInReset$VAL));
// submodule spiClk_spiI_slowReset
SyncResetA #(.RSTDELAY(32'd1)) spiClk_spiI_slowReset(.CLK(spiClk_spiI_cd$CLK_OUT),
.IN_RST(wciS0_MReset_n),
.OUT_RST(spiClk_spiI_slowReset$OUT_RST));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF$D_IN),
.ENQ(wci_wslv_reqF$ENQ),
.DEQ(wci_wslv_reqF$DEQ),
.CLR(wci_wslv_reqF$CLR),
.D_OUT(wci_wslv_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF$EMPTY_N));
// rule RL_get_adx_resp
assign CAN_FIRE_RL_get_adx_resp =
spiClk_spiI_respF_head_wrapped !=
spiClk_spiI_respF_tail_wrapped &&
!spiClk_spiI_respF_dInReset$VAL &&
spiClk_spiI_cd$PREEDGE &&
(!splitReadInFlight || wci_wslv_respF_c_r != 2'd2) ;
// rule RL_get_adc0_resp
assign CAN_FIRE_RL_get_adc0_resp =
adcCore0_spiI_respF_head_wrapped !=
adcCore0_spiI_respF_tail_wrapped &&
!adcCore0_spiI_respF_dInReset$VAL &&
adcCore0_spiI_cd$PREEDGE &&
(!splitReadInFlight || wci_wslv_respF_c_r != 2'd2) ;
// rule RL_get_adc1_resp
assign CAN_FIRE_RL_get_adc1_resp =
adcCore1_spiI_respF_head_wrapped !=
adcCore1_spiI_respF_tail_wrapped &&
!adcCore1_spiI_respF_dInReset$VAL &&
adcCore1_spiI_cd$PREEDGE &&
(!splitReadInFlight || wci_wslv_respF_c_r != 2'd2) ;
assign WILL_FIRE_RL_get_adc1_resp =
CAN_FIRE_RL_get_adc1_resp &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
IF_wci_wslv_reqF_first__5_BITS_43_TO_42_943_EQ_ETC___d1970 &&
wci_wslv_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_spiClk_spiI_start_cs
assign WILL_FIRE_RL_spiClk_spiI_start_cs =
NOT_spiClk_spiI_reqF_head_wrapped__read__39_EQ_ETC___d382 &&
!spiClk_spiI_xmt_i &&
!spiClk_spiI_xmt_d ;
// rule RL_spiClk_spiI_send_d
assign WILL_FIRE_RL_spiClk_spiI_send_d =
NOT_spiClk_spiI_reqF_head_wrapped__read__39_EQ_ETC___d382 &&
!spiClk_spiI_reqF_dInReset$VAL &&
spiClk_spiI_xmt_d ;
// rule RL_spiClk_spiI_send_i
assign WILL_FIRE_RL_spiClk_spiI_send_i =
IF_spiClk_spiI_iPos_89_EQ_15_90_THEN_NOT_spiCl_ETC___d401 &&
spiClk_spiI_xmt_i ;
// rule RL_spiClk_spiI_reqF_deq_update_head
assign WILL_FIRE_RL_spiClk_spiI_reqF_deq_update_head =
!spiClk_spiI_reqF_dInReset$VAL &&
MUX_spiClk_spiI_xmt_d$write_1__SEL_2 ;
// rule RL_spiClk_spiI_respF_enq_update_tail
assign WILL_FIRE_RL_spiClk_spiI_respF_enq_update_tail =
!spiClk_spiI_respF_sInReset$VAL &&
spiClk_spiI_respF_enq_pw$whas ;
// rule RL_spiClk_spiI_respF_deq_update_head
assign WILL_FIRE_RL_spiClk_spiI_respF_deq_update_head =
!spiClk_spiI_respF_dInReset$VAL &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 ;
// rule RL_spiClk_iseqFsm_action_l45c9
assign WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 &&
spiClk_iseqFsm_state_mkFSMstate == 4'd1 &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_cfwr ;
// rule RL_spiClk_iseqFsm_action_l46c9
assign WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 &&
spiClk_iseqFsm_state_mkFSMstate == 4'd2 &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_cfwr ;
// rule RL_spiClk_iseqFsm_action_l47c9
assign WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 &&
spiClk_iseqFsm_state_mkFSMstate == 4'd3 &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_cfwr ;
// rule RL_spiClk_iseqFsm_action_l48c9
assign WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 &&
spiClk_iseqFsm_state_mkFSMstate == 4'd4 &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_cfwr ;
// rule RL_spiClk_iseqFsm_action_l49c9
assign WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 &&
spiClk_iseqFsm_state_mkFSMstate == 4'd5 &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_cfwr ;
// rule RL_spiClk_iseqFsm_action_l50c9
assign WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 &&
spiClk_iseqFsm_state_mkFSMstate == 4'd6 &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_cfwr ;
// rule RL_adcCore0_advance_spi_request
assign WILL_FIRE_RL_adcCore0_advance_spi_request =
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 &&
adcCore0_reqF$EMPTY_N &&
adcCore0_iseqFsm_abort_whas__080_AND_adcCore0__ETC___d1152 &&
!adcCore0_iseqFsm_start_reg ;
// rule RL_adcCore0_colGate_send_timestamp_mesg
assign WILL_FIRE_RL_adcCore0_colGate_send_timestamp_mesg =
adcCore0_colGate_sampF$FULL_N && adcCore0_operateD$dD_OUT &&
adcCore0_colGate_timeMesg != 3'd0 ;
// rule RL_adcCore0_colGate_send_sync_mesg
assign WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg =
adcCore0_colGate_sampF$FULL_N && adcCore0_operateD$dD_OUT &&
adcCore0_colGate_syncMesg != 2'd0 &&
adcCore0_colGate_timeMesg == 3'd0 ;
// rule RL_adcCore0_colGate_capture_collect
assign WILL_FIRE_RL_adcCore0_colGate_capture_collect =
adcCore0_colGate_sampF$FULL_N &&
adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d601 ;
// rule RL_adcCore0_colGate_form_avg4_sample
assign WILL_FIRE_RL_adcCore0_colGate_form_avg4_sample =
CASE_adcCore0_colGate_avgPhase_0b1_0_1_1_1_2_1_ETC__q4 &&
adcCore0_operateD$dD_OUT ;
// rule RL_adcCore0_colGate_overrun_recovery
assign WILL_FIRE_RL_adcCore0_colGate_overrun_recovery =
(adcCore0_colGate_ovrRecover != 4'd15 ||
adcCore0_colGate_sampF$FULL_N) &&
adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d590 &&
adcCore0_colGate_ovrRecover != 4'd0 &&
!WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg ;
// rule RL_adcCore0_colGate_count_dropped_samples
assign WILL_FIRE_RL_adcCore0_colGate_count_dropped_samples =
adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d590 &&
adcCore0_colGate_sampActive &&
!adcCore0_colGate_sampF$FULL_N &&
!WILL_FIRE_RL_adcCore0_colGate_overrun_recovery ;
// rule RL_adcCore0_colGate_count_dwells
assign WILL_FIRE_RL_adcCore0_colGate_count_dwells =
adcCore0_operateD$dD_OUT && adcCore0_acquireD$dD_OUT &&
!adcCore0_colGate_collectD ;
// rule RL_adcCore0_spiI_start_cs
assign WILL_FIRE_RL_adcCore0_spiI_start_cs =
NOT_adcCore0_spiI_reqF_head_wrapped__read__82__ETC___d1025 &&
!adcCore0_spiI_xmt_i &&
!adcCore0_spiI_xmt_d ;
// rule RL_adcCore0_spiI_send_d
assign WILL_FIRE_RL_adcCore0_spiI_send_d =
NOT_adcCore0_spiI_reqF_head_wrapped__read__82__ETC___d1025 &&
!adcCore0_spiI_reqF_dInReset$VAL &&
adcCore0_spiI_xmt_d ;
// rule RL_adcCore0_spiI_send_i
assign WILL_FIRE_RL_adcCore0_spiI_send_i =
NOT_adcCore0_spiI_reqF_head_wrapped__read__82__ETC___d1025 &&
!adcCore0_spiI_reqF_dInReset$VAL &&
adcCore0_spiI_xmt_i ;
// rule RL_adcCore0_spiI_reqF_deq_update_head
assign WILL_FIRE_RL_adcCore0_spiI_reqF_deq_update_head =
!adcCore0_spiI_reqF_dInReset$VAL &&
MUX_adcCore0_spiI_xmt_d$write_1__SEL_2 ;
// rule RL_adcCore0_spiI_respF_enq_update_tail
assign WILL_FIRE_RL_adcCore0_spiI_respF_enq_update_tail =
!adcCore0_spiI_respF_sInReset$VAL &&
adcCore0_spiI_respF_enq_pw$whas ;
// rule RL_adcCore0_spiI_respF_deq_update_head
assign WILL_FIRE_RL_adcCore0_spiI_respF_deq_update_head =
!adcCore0_spiI_respF_dInReset$VAL &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 ;
// rule RL_adcCore0_iseqFsm_action_np
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_np =
!adcCore0_iseqFsm_jj_delay_count[12] &&
(adcCore0_iseqFsm_state_mkFSMstate == 4'd3 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_adcCore0_iseqFsm_action_l119c9
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 =
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 &&
adcCore0_iseqFsm_jj_delay_count[12] &&
(adcCore0_iseqFsm_state_mkFSMstate == 4'd3 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_adcCore0_iseqFsm_action_l120c9
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 =
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 &&
adcCore0_iseqFsm_state_mkFSMstate == 4'd5 ;
// rule RL_adcCore0_iseqFsm_action_l121c9
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 =
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 &&
adcCore0_iseqFsm_state_mkFSMstate == 4'd6 ;
// rule RL_adcCore0_iseqFsm_action_l122c9
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 =
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 &&
adcCore0_iseqFsm_state_mkFSMstate == 4'd7 ;
// rule RL_adcCore0_iseqFsm_action_l123c9
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 =
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 &&
adcCore0_iseqFsm_state_mkFSMstate == 4'd8 ;
// rule RL_adcCore0_iseqFsm_action_l124c9
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9 =
adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 &&
adcCore0_iseqFsm_state_mkFSMstate == 4'd9 ;
// rule RL_adcCore0_spiI_reqF_enq_update_tail
assign WILL_FIRE_RL_adcCore0_spiI_reqF_enq_update_tail =
!adcCore0_spiI_reqF_sInReset$VAL &&
adcCore0_spiI_reqF_enq_pw$whas ;
// rule RL_adcCore1_advance_spi_request
assign WILL_FIRE_RL_adcCore1_advance_spi_request =
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 &&
adcCore1_reqF$EMPTY_N &&
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d1799 &&
!adcCore1_iseqFsm_start_reg ;
// rule RL_adcCore1_colGate_send_timestamp_mesg
assign WILL_FIRE_RL_adcCore1_colGate_send_timestamp_mesg =
adcCore1_colGate_sampF$FULL_N &&
adcCore1_colGate_timeMesg != 3'h6 &&
adcCore1_colGate_timeMesg != 3'h5 &&
adcCore1_operateD$dD_OUT &&
adcCore1_colGate_timeMesg != 3'd0 ;
// rule RL_adcCore1_colGate_send_sync_mesg
assign WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg =
adcCore1_colGate_sampF$FULL_N && adcCore1_operateD$dD_OUT &&
adcCore1_colGate_syncMesg != 2'd0 &&
adcCore1_colGate_timeMesg == 3'd0 ;
// rule RL_adcCore1_colGate_capture_collect
assign WILL_FIRE_RL_adcCore1_colGate_capture_collect =
adcCore1_colGate_sampF$FULL_N &&
adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1248 ;
// rule RL_adcCore1_colGate_form_avg4_sample
assign WILL_FIRE_RL_adcCore1_colGate_form_avg4_sample =
CASE_adcCore1_colGate_avgPhase_0b1_0_1_1_1_2_1_ETC__q5 &&
adcCore1_operateD$dD_OUT ;
// rule RL_adcCore1_colGate_overrun_recovery
assign WILL_FIRE_RL_adcCore1_colGate_overrun_recovery =
(adcCore1_colGate_ovrRecover != 4'd15 ||
adcCore1_colGate_sampF$FULL_N) &&
adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1237 &&
adcCore1_colGate_ovrRecover != 4'd0 &&
!WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg ;
// rule RL_adcCore1_colGate_count_dropped_samples
assign WILL_FIRE_RL_adcCore1_colGate_count_dropped_samples =
adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1237 &&
adcCore1_colGate_sampActive &&
!adcCore1_colGate_sampF$FULL_N &&
!WILL_FIRE_RL_adcCore1_colGate_overrun_recovery ;
// rule RL_adcCore1_colGate_count_dwells
assign WILL_FIRE_RL_adcCore1_colGate_count_dwells =
adcCore1_operateD$dD_OUT && adcCore1_acquireD$dD_OUT &&
!adcCore1_colGate_collectD ;
// rule RL_adcCore1_spiI_start_cs
assign WILL_FIRE_RL_adcCore1_spiI_start_cs =
NOT_adcCore1_spiI_reqF_head_wrapped__read__629_ETC___d1672 &&
!adcCore1_spiI_xmt_i &&
!adcCore1_spiI_xmt_d ;
// rule RL_adcCore1_spiI_send_d
assign WILL_FIRE_RL_adcCore1_spiI_send_d =
NOT_adcCore1_spiI_reqF_head_wrapped__read__629_ETC___d1672 &&
!adcCore1_spiI_reqF_dInReset$VAL &&
adcCore1_spiI_xmt_d ;
// rule RL_adcCore1_spiI_send_i
assign WILL_FIRE_RL_adcCore1_spiI_send_i =
NOT_adcCore1_spiI_reqF_head_wrapped__read__629_ETC___d1672 &&
!adcCore1_spiI_reqF_dInReset$VAL &&
adcCore1_spiI_xmt_i ;
// rule RL_adcCore1_spiI_reqF_deq_update_head
assign WILL_FIRE_RL_adcCore1_spiI_reqF_deq_update_head =
!adcCore1_spiI_reqF_dInReset$VAL &&
MUX_adcCore1_spiI_xmt_d$write_1__SEL_2 ;
// rule RL_adcCore1_spiI_respF_enq_update_tail
assign WILL_FIRE_RL_adcCore1_spiI_respF_enq_update_tail =
!adcCore1_spiI_respF_sInReset$VAL &&
adcCore1_spiI_respF_enq_pw$whas ;
// rule RL_adcCore1_spiI_respF_deq_update_head
assign WILL_FIRE_RL_adcCore1_spiI_respF_deq_update_head =
!adcCore1_spiI_respF_dInReset$VAL && WILL_FIRE_RL_get_adc1_resp ;
// rule RL_adcCore1_iseqFsm_action_np
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_np =
!adcCore1_iseqFsm_jj_delay_count[12] &&
(adcCore1_iseqFsm_state_mkFSMstate == 4'd3 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_adcCore1_iseqFsm_action_l119c9
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 =
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 &&
adcCore1_iseqFsm_jj_delay_count[12] &&
(adcCore1_iseqFsm_state_mkFSMstate == 4'd3 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_adcCore1_iseqFsm_action_l120c9
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 =
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 &&
adcCore1_iseqFsm_state_mkFSMstate == 4'd5 ;
// rule RL_adcCore1_iseqFsm_action_l121c9
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 =
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 &&
adcCore1_iseqFsm_state_mkFSMstate == 4'd6 ;
// rule RL_adcCore1_iseqFsm_action_l122c9
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 =
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 &&
adcCore1_iseqFsm_state_mkFSMstate == 4'd7 ;
// rule RL_adcCore1_iseqFsm_action_l123c9
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 =
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 &&
adcCore1_iseqFsm_state_mkFSMstate == 4'd8 ;
// rule RL_adcCore1_iseqFsm_action_l124c9
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9 =
adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 &&
adcCore1_iseqFsm_state_mkFSMstate == 4'd9 ;
// rule RL_adcCore1_spiI_reqF_enq_update_tail
assign WILL_FIRE_RL_adcCore1_spiI_reqF_enq_update_tail =
!adcCore1_spiI_reqF_sInReset$VAL &&
adcCore1_spiI_reqF_enq_pw$whas ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_wslv_reqF$EMPTY_N &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 ||
IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d2447) &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b01 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b10 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b11 ||
wci_wslv_respF_c_r != 2'd2) &&
wci_wslv_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_doMessage
assign WILL_FIRE_RL_doMessage =
wsiM_reqFifo_c_r != 2'd2 &&
NOT_adcCore0_sampF_rRdPtr_rsCounter_59_EQ_adcC_ETC___d1909 &&
wci_wslv_cState == 3'd2 ;
// rule RL_init_complete_ok
assign WILL_FIRE_RL_init_complete_ok =
initOpInFlight_041_AND_adcCore0_iseqFsm_abort__ETC___d2110 &&
spiClk_iseqFsm_abort_whas__53_AND_spiClk_iseqF_ETC___d513 &&
!spiClk_iseqFsm_start_reg ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
adcCore0_iseqFsm_abort_whas__080_AND_adcCore0__ETC___d1152 &&
!adcCore0_iseqFsm_start_reg &&
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d2103 &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
((wci_wslv_respF_c_r == 2'd0) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_enqueueing$whas &&
!(wci_wslv_respF_c_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
((wci_wslv_respF_c_r == 2'd1) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_c_r != 2'd0 &&
wci_wslv_respF_enqueueing$whas ;
// rule RL_spiClk_iseqFsm_fsm_start
assign WILL_FIRE_RL_spiClk_iseqFsm_fsm_start =
spiClk_iseqFsm_abort_whas__53_AND_spiClk_iseqF_ETC___d513 &&
spiClk_iseqFsm_start_reg ;
// rule RL_spiClk_iseqFsm_action_l44c9
assign WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 &&
spiClk_iseqFsm_start_wire$whas &&
(spiClk_iseqFsm_state_mkFSMstate == 4'd0 ||
spiClk_iseqFsm_state_mkFSMstate == 4'd7) &&
!WILL_FIRE_RL_wci_cfrd &&
!WILL_FIRE_RL_wci_cfwr ;
// rule RL_spiClk_spiI_reqF_enq_update_tail
assign WILL_FIRE_RL_spiClk_spiI_reqF_enq_update_tail =
!spiClk_spiI_reqF_sInReset$VAL && spiClk_spiI_reqF_enq_pw$whas ;
// rule RL_spiClk_iseqFsm_idle_l43c3
assign WILL_FIRE_RL_spiClk_iseqFsm_idle_l43c3 =
!spiClk_iseqFsm_start_wire$whas &&
spiClk_iseqFsm_state_mkFSMstate == 4'd7 ;
// rule RL_adcCore0_iseqFsm_fsm_start
assign WILL_FIRE_RL_adcCore0_iseqFsm_fsm_start =
adcCore0_iseqFsm_abort_whas__080_AND_adcCore0__ETC___d1152 &&
adcCore0_iseqFsm_start_reg ;
// rule RL_adcCore0_iseqFsm_action_l116c12
assign WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12 =
adcCore0_iseqFsm_start_wire$whas &&
(adcCore0_iseqFsm_state_mkFSMstate == 4'd0 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd10) ;
// rule RL_adcCore0_iseqFsm_idle_l115c3
assign WILL_FIRE_RL_adcCore0_iseqFsm_idle_l115c3 =
!adcCore0_iseqFsm_start_wire$whas &&
adcCore0_iseqFsm_state_mkFSMstate == 4'd10 ;
// rule RL_adcCore1_iseqFsm_fsm_start
assign WILL_FIRE_RL_adcCore1_iseqFsm_fsm_start =
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d1799 &&
adcCore1_iseqFsm_start_reg ;
// rule RL_adcCore1_iseqFsm_action_l116c12
assign WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12 =
adcCore1_iseqFsm_start_wire$whas &&
(adcCore1_iseqFsm_state_mkFSMstate == 4'd0 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd10) ;
// rule RL_adcCore1_iseqFsm_idle_l115c3
assign WILL_FIRE_RL_adcCore1_iseqFsm_idle_l115c3 =
!adcCore1_iseqFsm_start_wire$whas &&
adcCore1_iseqFsm_state_mkFSMstate == 4'd10 ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
WILL_FIRE_RL_doMessage :
wsiM_reqFifo_c_r != 2'd1 || WILL_FIRE_RL_doMessage) &&
WILL_FIRE_RL_doMessage &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !WILL_FIRE_RL_doMessage ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
WILL_FIRE_RL_doMessage :
wsiM_reqFifo_c_r != 2'd2 || WILL_FIRE_RL_doMessage) &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
WILL_FIRE_RL_doMessage ;
// inputs to muxes for submodule ports
assign MUX_adcCore0_colGate_dwellFails$write_1__SEL_1 =
WILL_FIRE_RL_adcCore0_colGate_count_dropped_samples &&
adcCore0_colGate_ovrRecover == 4'd0 ;
assign MUX_adcCore0_colGate_sampF$enq_1__SEL_1 =
WILL_FIRE_RL_adcCore0_colGate_overrun_recovery &&
adcCore0_colGate_ovrRecover == 4'd15 ;
assign MUX_adcCore0_reqF$enq_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h28 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b01) ;
assign MUX_adcCore0_spiI_xmt_d$write_1__SEL_2 =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd0 ;
assign MUX_adcCore1_colGate_dwellFails$write_1__SEL_1 =
WILL_FIRE_RL_adcCore1_colGate_count_dropped_samples &&
adcCore1_colGate_ovrRecover == 4'd0 ;
assign MUX_adcCore1_colGate_sampF$enq_1__SEL_1 =
WILL_FIRE_RL_adcCore1_colGate_overrun_recovery &&
adcCore1_colGate_ovrRecover == 4'd15 ;
assign MUX_adcCore1_reqF$enq_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h2C ||
wci_wslv_reqF$D_OUT[43:42] == 2'b10) ;
assign MUX_adcCore1_spiI_xmt_d$write_1__SEL_2 =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd0 ;
assign MUX_spiClk_spiI_reqS$write_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h24 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b11) ;
assign MUX_spiClk_spiI_reqS$write_1__SEL_2 =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b11 ;
assign MUX_spiClk_spiI_xmt_d$write_1__SEL_2 =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd0 ;
assign MUX_splitReadInFlight$write_1__PSEL_1 =
WILL_FIRE_RL_get_adc1_resp ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 ;
assign MUX_splitReadInFlight$write_1__SEL_1 =
MUX_splitReadInFlight$write_1__PSEL_1 && splitReadInFlight ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ;
assign MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 =
CAN_FIRE_RL_get_adx_resp &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 =
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 && splitReadInFlight ;
assign MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 =
CAN_FIRE_RL_get_adc0_resp &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 && splitReadInFlight ;
assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 =
WILL_FIRE_RL_get_adc1_resp && splitReadInFlight ;
assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_4 =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b0 ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_adcCore0_colGate_dropCount$write_1__VAL_1 =
adcCore0_colGate_dropCount + 32'd1 ;
assign MUX_adcCore0_colGate_dwellFails$write_1__VAL_1 =
adcCore0_colGate_dwellFails + 32'd1 ;
assign MUX_adcCore0_colGate_dwellStarts$write_1__VAL_1 =
adcCore0_colGate_dwellStarts + 32'd1 ;
assign MUX_adcCore0_colGate_ovrRecover$write_1__VAL_2 =
adcCore0_colGate_ovrRecover - 4'd1 ;
assign MUX_adcCore0_colGate_sampCount$write_1__VAL_1 =
adcCore0_colGate_sampCount + 32'd1 ;
assign MUX_adcCore0_colGate_sampF$enq_1__VAL_1 =
{ 7'd31, adcCore0_colGate_sampDataWD } ;
assign MUX_adcCore0_colGate_sampF$enq_1__VAL_2 =
{ 2'd2,
adcCore0_colGate_timeMesg == 3'h1,
4'd15,
x1_data__h35585 } ;
assign MUX_adcCore0_colGate_sampF$enq_1__VAL_3 =
{ 2'd0,
adcCore0_colGate_uprollCnt_04_EQ_adcCore0_colG_ETC___d2230,
4'd15,
d_data__h35985 } ;
assign MUX_adcCore0_colGate_syncMesg$write_1__VAL_1 =
adcCore0_colGate_syncMesg - 2'd1 ;
assign MUX_adcCore0_colGate_timeMesg$write_1__VAL_1 =
adcCore0_colGate_timeMesg - 3'd1 ;
assign MUX_adcCore0_colGate_uprollCnt$write_1__VAL_2 =
adcCore0_colGate_uprollCnt_04_EQ_adcCore0_colG_ETC___d2230 ?
16'd0 :
adcCore0_colGate_uprollCnt + 16'd1 ;
assign MUX_adcCore0_iseqFsm_jj_delay_count$write_1__VAL_1 =
{ adcCore0_iseqFsm_jj_delay_count[11:0], 1'd0 } ;
assign MUX_adcCore0_reqF$enq_1__VAL_1 =
{ wci_wslv_reqF$D_OUT[43:42] == 2'b0 && wci_wslv_reqF$D_OUT[31],
(wci_wslv_reqF$D_OUT[43:42] == 2'b0) ?
wci_wslv_reqF$D_OUT[15:0] :
{ wci_wslv_reqF$D_OUT[41:34], wci_wslv_reqF$D_OUT[7:0] } } ;
assign MUX_adcCore0_reqF$enq_1__VAL_2 =
{ 1'd1, wci_wslv_reqF$D_OUT[41:34], 8'd0 } ;
assign MUX_adcCore0_sampF_rRdPtr_rsCounter$write_1__VAL_1 =
(~adcCore0_sampF_rRdPtr_rsCounter[IF_adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_ETC___d2461[3:0]]) ?
adcCore0_sampF_rRdPtr_rsCounter | x__h40881 :
adcCore0_sampF_rRdPtr_rsCounter & y__h41768 ;
assign MUX_adcCore0_sampF_rWrPtr_rsCounter$write_1__VAL_1 =
(~adcCore0_sampF_rWrPtr_rsCounter[IF_adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_ETC___d2458[3:0]]) ?
adcCore0_sampF_rWrPtr_rsCounter | x__h38579 :
adcCore0_sampF_rWrPtr_rsCounter & y__h39466 ;
assign MUX_adcCore0_spiI_dPos$write_1__VAL_1 =
(adcCore0_spiI_dPos == 3'd0) ?
adcCore0_spiI_dPos :
adcCore0_spiI_dPos - 3'd1 ;
assign MUX_adcCore0_spiI_iPos$write_1__VAL_1 =
(adcCore0_spiI_iPos == 4'd0) ?
adcCore0_spiI_iPos :
adcCore0_spiI_iPos - 4'd1 ;
assign MUX_adcCore0_spiI_reqS$write_1__VAL_1 =
(adcCore0_reqF$D_OUT[16] && !adcCore0_readMode) ?
17'd1 :
((!adcCore0_reqF$D_OUT[16] && adcCore0_readMode) ?
17'd0 :
adcCore0_reqF$D_OUT) ;
assign MUX_adcCore0_spiI_sdoR_1$wset_1__VAL_1 =
adcCore0_spiI_reqS_BITS_15_TO_8__q6[adcCore0_spiI_iPos[2:0]] ;
assign MUX_adcCore0_spiI_sdoR_1$wset_1__VAL_2 =
adcCore0_spiI_reqS_BITS_7_TO_0__q7[adcCore0_spiI_dPos] ;
assign MUX_adcCore1_colGate_dropCount$write_1__VAL_1 =
adcCore1_colGate_dropCount + 32'd1 ;
assign MUX_adcCore1_colGate_dwellFails$write_1__VAL_1 =
adcCore1_colGate_dwellFails + 32'd1 ;
assign MUX_adcCore1_colGate_dwellStarts$write_1__VAL_1 =
adcCore1_colGate_dwellStarts + 32'd1 ;
assign MUX_adcCore1_colGate_ovrRecover$write_1__VAL_2 =
adcCore1_colGate_ovrRecover - 4'd1 ;
assign MUX_adcCore1_colGate_sampCount$write_1__VAL_1 =
adcCore1_colGate_sampCount + 32'd1 ;
assign MUX_adcCore1_colGate_sampF$enq_1__VAL_1 =
{ 7'd31, adcCore1_colGate_sampDataWD } ;
assign MUX_adcCore1_colGate_sampF$enq_1__VAL_2 =
{ 2'd2,
adcCore1_colGate_timeMesg == 3'h1,
4'd15,
x1_data__h81295 } ;
assign MUX_adcCore1_colGate_sampF$enq_1__VAL_3 =
{ 2'd0,
adcCore1_colGate_uprollCnt_251_EQ_adcCore1_col_ETC___d2234,
4'd15,
d_data__h81695 } ;
assign MUX_adcCore1_colGate_syncMesg$write_1__VAL_1 =
adcCore1_colGate_syncMesg - 2'd1 ;
assign MUX_adcCore1_colGate_timeMesg$write_1__VAL_1 =
adcCore1_colGate_timeMesg - 3'd1 ;
assign MUX_adcCore1_colGate_uprollCnt$write_1__VAL_2 =
adcCore1_colGate_uprollCnt_251_EQ_adcCore1_col_ETC___d2234 ?
16'd0 :
adcCore1_colGate_uprollCnt + 16'd1 ;
assign MUX_adcCore1_iseqFsm_jj_delay_count$write_1__VAL_1 =
{ adcCore1_iseqFsm_jj_delay_count[11:0], 1'd0 } ;
assign MUX_adcCore1_sampF_rWrPtr_rsCounter$write_1__VAL_1 =
(~adcCore1_sampF_rWrPtr_rsCounter[IF_adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_3_ETC___d2467[3:0]]) ?
adcCore1_sampF_rWrPtr_rsCounter | x__h84289 :
adcCore1_sampF_rWrPtr_rsCounter & y__h85176 ;
assign MUX_adcCore1_spiI_dPos$write_1__VAL_1 =
(adcCore1_spiI_dPos == 3'd0) ?
adcCore1_spiI_dPos :
adcCore1_spiI_dPos - 3'd1 ;
assign MUX_adcCore1_spiI_iPos$write_1__VAL_1 =
(adcCore1_spiI_iPos == 4'd0) ?
adcCore1_spiI_iPos :
adcCore1_spiI_iPos - 4'd1 ;
assign MUX_adcCore1_spiI_reqS$write_1__VAL_1 =
(adcCore1_reqF$D_OUT[16] && !adcCore1_readMode) ?
17'd1 :
((!adcCore1_reqF$D_OUT[16] && adcCore1_readMode) ?
17'd0 :
adcCore1_reqF$D_OUT) ;
assign MUX_adcCore1_spiI_sdoR_1$wset_1__VAL_1 =
adcCore1_spiI_reqS_BITS_15_TO_8__q9[adcCore1_spiI_iPos[2:0]] ;
assign MUX_adcCore1_spiI_sdoR_1$wset_1__VAL_2 =
adcCore1_spiI_reqS_BITS_7_TO_0__q8[adcCore1_spiI_dPos] ;
assign MUX_fcAdc_grayCounter_rsCounter$write_1__VAL_1 =
(~fcAdc_grayCounter_rsCounter[IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d2455[4:0]]) ?
fcAdc_grayCounter_rsCounter | x__h7511 :
fcAdc_grayCounter_rsCounter & y__h8916 ;
assign MUX_oneKHz_value$write_1__VAL_1 =
(oneKHz_value == 18'd124999) ? 18'd0 : oneKHz_value + 18'd1 ;
assign MUX_spiClk_spiI_dPos$write_1__VAL_1 =
(spiClk_spiI_dPos == 3'd0) ?
spiClk_spiI_dPos :
spiClk_spiI_dPos - 3'd1 ;
assign MUX_spiClk_spiI_iPos$write_1__VAL_1 =
(spiClk_spiI_iPos == 4'd0) ?
spiClk_spiI_iPos :
spiClk_spiI_iPos - 4'd1 ;
assign MUX_spiClk_spiI_sdoR_1$wset_1__VAL_1 =
(spiClk_spiI_iPos == 4'd15) ?
spiClk_spiI_reqS[16] :
spiClk_spiI_iPos != 4'd14 && spiClk_spiI_iPos != 4'd13 &&
(spiClk_spiI_iPos_89_ULT_7___d2219 ||
!spiClk_spiI_iPos_89_ULE_12___d2220) &&
x__h17146 ;
assign MUX_spiClk_spiI_sdoR_1$wset_1__VAL_2 =
spiClk_spiI_reqS_BITS_7_TO_0__q10[spiClk_spiI_dPos] ;
assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ;
assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd1) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or
MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or
MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 or
MUX_wci_wslv_respF_x_wire$wset_1__SEL_4 or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_4 or
WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_5 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_x_wire$wset_1__SEL_1:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1;
MUX_wci_wslv_respF_x_wire$wset_1__SEL_2:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
MUX_wci_wslv_respF_x_wire$wset_1__SEL_3:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3;
MUX_wci_wslv_respF_x_wire$wset_1__SEL_4:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_4;
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_5;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd2) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 =
{ 26'd16777216, spiClk_spiI_respS } ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 =
{ 26'd16777216, adcCore0_spiI_respS } ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 =
{ 26'd16777216, adcCore1_spiI_respS } ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_4 = { 2'd1, rdat__h131371 } ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_5 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 :
61'h00000AAAAAAAAA00 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 =
{ 3'd1,
adcCore0_sampF_memory$DOB[36],
1'd0,
x_burstLength__h128706,
adcCore0_sampF_memory$DOB[31:0],
10'd960,
adcCore0_sampF_memory$DOB[38:37] } ;
// inlined wires
assign wci_wslv_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq$whas = 1'd1 ;
assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_2 ;
assign wci_wslv_respF_x_wire$whas =
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 && splitReadInFlight ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 && splitReadInFlight ||
WILL_FIRE_RL_get_adc1_resp && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b0 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1$wget = 1'd1 ;
assign wci_wslv_sFlagReg_1$whas = sFlagState ;
assign wci_wslv_ctlAckReg_1$wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1$whas =
WILL_FIRE_RL_init_complete_ok || WILL_FIRE_RL_wci_ctrl_OrE ||
WILL_FIRE_RL_wci_ctrl_IsO ;
assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_wci_Es_mData_w$wget = wciS0_MData ;
assign wci_wci_Es_mData_w$whas = 1'd1 ;
assign fcAdc_pulseAction_1$wget = 1'd1 ;
assign fcAdc_pulseAction_1$whas = oneKHz_value == 18'd124999 ;
assign spiClk_spiI_cGate_1$wget = 1'd1 ;
assign spiClk_spiI_cGate_1$whas =
WILL_FIRE_RL_spiClk_spiI_send_i ||
WILL_FIRE_RL_spiClk_spiI_send_d ;
assign spiClk_spiI_sdoR_1$wget =
WILL_FIRE_RL_spiClk_spiI_send_i ?
MUX_spiClk_spiI_sdoR_1$wset_1__VAL_1 :
MUX_spiClk_spiI_sdoR_1$wset_1__VAL_2 ;
assign spiClk_spiI_sdoR_1$whas =
WILL_FIRE_RL_spiClk_spiI_send_d ||
WILL_FIRE_RL_spiClk_spiI_send_i ;
assign spiClk_spiI_csbR_1$wget = 1'b0 ;
assign spiClk_spiI_csbR_1$whas = spiClk_spiI_cGate_1$whas ;
assign spiClk_spiI_doResp_1$wget = spiClk_spiI_reqS[16] ;
assign spiClk_spiI_doResp_1$whas = MUX_spiClk_spiI_xmt_d$write_1__SEL_2 ;
assign spiClk_iseqFsm_start_wire$wget = 1'd1 ;
assign spiClk_iseqFsm_start_wire$whas =
WILL_FIRE_RL_spiClk_iseqFsm_fsm_start ||
spiClk_iseqFsm_start_reg_1 && !spiClk_iseqFsm_state_fired ;
assign spiClk_iseqFsm_start_reg_1_1$wget = 1'd1 ;
assign spiClk_iseqFsm_start_reg_1_1$whas = spiClk_iseqFsm_start_wire$whas ;
assign spiClk_iseqFsm_abort$wget = 1'b0 ;
assign spiClk_iseqFsm_abort$whas = 1'b0 ;
assign spiClk_iseqFsm_state_fired_1$wget = 1'd1 ;
assign spiClk_iseqFsm_state_fired_1$whas =
spiClk_iseqFsm_state_set_pw$whas ;
assign adcCore0_ddrC_psCmdReg_1$wget = wci_wslv_reqF$D_OUT[1:0] ;
assign adcCore0_ddrC_psCmdReg_1$whas =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h48 ;
assign adcCore0_colGate_average_dw$wget = 1'd1 ;
assign adcCore0_colGate_average_dw$whas = adcCore0_averageD$dD_OUT ;
assign adcCore0_colGate_sampActive_1$wget = 1'd1 ;
assign adcCore0_colGate_sampActive_1$whas = 1'd1 ;
assign adcCore0_colGate_nowW$wget = wti_nowReq[63:0] ;
assign adcCore0_colGate_nowW$whas = 1'd1 ;
assign adcCore0_colGate_maxBurstLenW$wget =
adcCore0_maxBurstLengthR$dD_OUT ;
assign adcCore0_colGate_maxBurstLenW$whas = 1'd1 ;
assign adcCore0_colGate_sampDataW$wget = adcCore0_samp ;
assign adcCore0_colGate_sampDataW$whas = 1'd1 ;
assign adcCore0_operateDReg_1$wget = 1'd1 ;
assign adcCore0_operateDReg_1$whas = wci_wslv_cState == 3'd2 ;
assign adcCore0_acquireDReg_1$wget = 1'd1 ;
assign adcCore0_acquireDReg_1$whas =
wci_wslv_cState == 3'd2 && !adcControl[0] &&
(!adcControl[3] || overflowCountD == 32'd0) ;
assign adcCore0_averageDReg_1$wget = 1'd1 ;
assign adcCore0_averageDReg_1$whas =
wci_wslv_cState == 3'd2 && adcControl[4] ;
assign adcCore0_sampF_wDataIn$wget = adcCore0_colGate_sampF$D_OUT ;
assign adcCore0_sampF_wDataIn$whas = adcCore0_sampF_pwEnqueue$whas ;
assign adcCore0_sampF_wDataOut$wget = adcCore0_sampF_memory$DOB ;
assign adcCore0_sampF_wDataOut$whas = 1'd1 ;
assign adcCore0_nowW$wget = wti_nowReq[63:0] ;
assign adcCore0_nowW$whas = 1'd1 ;
assign adcCore0_spiI_cGate_1$wget = 1'd1 ;
assign adcCore0_spiI_cGate_1$whas =
WILL_FIRE_RL_adcCore0_spiI_send_i ||
WILL_FIRE_RL_adcCore0_spiI_send_d ;
assign adcCore0_spiI_sdoR_1$wget =
WILL_FIRE_RL_adcCore0_spiI_send_i ?
MUX_adcCore0_spiI_sdoR_1$wset_1__VAL_1 :
MUX_adcCore0_spiI_sdoR_1$wset_1__VAL_2 ;
assign adcCore0_spiI_sdoR_1$whas = adcCore0_spiI_cGate_1$whas ;
assign adcCore0_spiI_csbR_1$wget = 1'b0 ;
assign adcCore0_spiI_csbR_1$whas = adcCore0_spiI_cGate_1$whas ;
assign adcCore0_spiI_doResp_1$wget = adcCore0_spiI_reqS[16] ;
assign adcCore0_spiI_doResp_1$whas =
MUX_adcCore0_spiI_xmt_d$write_1__SEL_2 ;
assign adcCore0_adcRst_1$wget = 1'd1 ;
assign adcCore0_adcRst_1$whas =
adcCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12 ;
assign adcCore0_iseqFsm_start_wire$wget = 1'd1 ;
assign adcCore0_iseqFsm_start_wire$whas =
WILL_FIRE_RL_adcCore0_iseqFsm_fsm_start ||
adcCore0_iseqFsm_start_reg_1 && !adcCore0_iseqFsm_state_fired ;
assign adcCore0_iseqFsm_start_reg_1_1$wget = 1'd1 ;
assign adcCore0_iseqFsm_start_reg_1_1$whas =
adcCore0_iseqFsm_start_wire$whas ;
assign adcCore0_iseqFsm_abort$wget = 1'b0 ;
assign adcCore0_iseqFsm_abort$whas = 1'b0 ;
assign adcCore0_iseqFsm_state_fired_1$wget = 1'd1 ;
assign adcCore0_iseqFsm_state_fired_1$whas =
adcCore0_iseqFsm_state_set_pw$whas ;
assign adcCore1_ddrC_psCmdReg_1$wget = wci_wslv_reqF$D_OUT[1:0] ;
assign adcCore1_ddrC_psCmdReg_1$whas =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h4C ;
assign adcCore1_colGate_average_dw$wget = 1'd1 ;
assign adcCore1_colGate_average_dw$whas = adcCore1_averageD$dD_OUT ;
assign adcCore1_colGate_sampActive_1$wget = 1'd1 ;
assign adcCore1_colGate_sampActive_1$whas = 1'd1 ;
assign adcCore1_colGate_nowW$wget = 64'h0 ;
assign adcCore1_colGate_nowW$whas = 1'b0 ;
assign adcCore1_colGate_maxBurstLenW$wget =
adcCore1_maxBurstLengthR$dD_OUT ;
assign adcCore1_colGate_maxBurstLenW$whas = 1'd1 ;
assign adcCore1_colGate_sampDataW$wget = adcCore1_samp ;
assign adcCore1_colGate_sampDataW$whas = 1'd1 ;
assign adcCore1_operateDReg_1$wget = 1'b0 ;
assign adcCore1_operateDReg_1$whas = 1'b0 ;
assign adcCore1_acquireDReg_1$wget = 1'b0 ;
assign adcCore1_acquireDReg_1$whas = 1'b0 ;
assign adcCore1_averageDReg_1$wget = 1'b0 ;
assign adcCore1_averageDReg_1$whas = 1'b0 ;
assign adcCore1_sampF_wDataIn$wget = adcCore1_colGate_sampF$D_OUT ;
assign adcCore1_sampF_wDataIn$whas = adcCore1_sampF_pwEnqueue$whas ;
assign adcCore1_sampF_wDataOut$wget = adcCore1_sampF_memory$DOB ;
assign adcCore1_sampF_wDataOut$whas = 1'd1 ;
assign adcCore1_nowW$wget = 64'h0 ;
assign adcCore1_nowW$whas = 1'b0 ;
assign adcCore1_spiI_cGate_1$wget = 1'd1 ;
assign adcCore1_spiI_cGate_1$whas =
WILL_FIRE_RL_adcCore1_spiI_send_i ||
WILL_FIRE_RL_adcCore1_spiI_send_d ;
assign adcCore1_spiI_sdoR_1$wget =
WILL_FIRE_RL_adcCore1_spiI_send_i ?
MUX_adcCore1_spiI_sdoR_1$wset_1__VAL_1 :
MUX_adcCore1_spiI_sdoR_1$wset_1__VAL_2 ;
assign adcCore1_spiI_sdoR_1$whas = adcCore1_spiI_cGate_1$whas ;
assign adcCore1_spiI_csbR_1$wget = 1'b0 ;
assign adcCore1_spiI_csbR_1$whas = adcCore1_spiI_cGate_1$whas ;
assign adcCore1_spiI_doResp_1$wget = adcCore1_spiI_reqS[16] ;
assign adcCore1_spiI_doResp_1$whas =
MUX_adcCore1_spiI_xmt_d$write_1__SEL_2 ;
assign adcCore1_adcRst_1$wget = 1'd1 ;
assign adcCore1_adcRst_1$whas =
adcCore1_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12 ;
assign adcCore1_iseqFsm_start_wire$wget = 1'd1 ;
assign adcCore1_iseqFsm_start_wire$whas =
WILL_FIRE_RL_adcCore1_iseqFsm_fsm_start ||
adcCore1_iseqFsm_start_reg_1 && !adcCore1_iseqFsm_state_fired ;
assign adcCore1_iseqFsm_start_reg_1_1$wget = 1'd1 ;
assign adcCore1_iseqFsm_start_reg_1_1$whas =
adcCore1_iseqFsm_start_wire$whas ;
assign adcCore1_iseqFsm_abort$wget = 1'b0 ;
assign adcCore1_iseqFsm_abort$whas = 1'b0 ;
assign adcCore1_iseqFsm_state_fired_1$wget = 1'd1 ;
assign adcCore1_iseqFsm_state_fired_1$whas =
adcCore1_iseqFsm_state_set_pw$whas ;
assign wti_wtiReq$wget = 67'h0 ;
assign wti_wtiReq$whas = 1'b0 ;
assign wti_operateD_1$wget = 1'b0 ;
assign wti_operateD_1$whas = 1'b0 ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_1$write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire$whas = WILL_FIRE_RL_doMessage ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr$whas = 1'b0 ;
assign wci_wslv_respF_enqueueing$whas =
(WILL_FIRE_RL_get_adc1_resp ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1) &&
splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b0 ||
WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw$whas =
wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign fcAdc_grayCounter_pwIncrement$whas = 1'd1 ;
assign fcAdc_grayCounter_pwDecrement$whas = 1'b0 ;
assign oneKHz_incAction$whas = 1'd1 ;
assign oneKHz_decAction$whas = 1'b0 ;
assign spiClk_spiI_reqF_enq_pw$whas =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h24 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b11) ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b11 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 ;
assign spiClk_spiI_reqF_deq_pw$whas = MUX_spiClk_spiI_xmt_d$write_1__SEL_2 ;
assign spiClk_spiI_reqF_sClear_pw$whas = 1'b0 ;
assign spiClk_spiI_reqF_dClear_pw$whas = 1'b0 ;
assign spiClk_spiI_reqF_deq_happened$whas = 1'b0 ;
assign spiClk_spiI_respF_enq_pw$whas =
spiClk_spiI_respF_head_wrapped ==
spiClk_spiI_respF_tail_wrapped &&
!spiClk_spiI_respF_sInReset$VAL &&
spiClk_spiI_doResp ;
assign spiClk_spiI_respF_deq_pw$whas =
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 ;
assign spiClk_spiI_respF_sClear_pw$whas = 1'b0 ;
assign spiClk_spiI_respF_dClear_pw$whas = 1'b0 ;
assign spiClk_spiI_respF_deq_happened$whas = 1'b0 ;
assign spiClk_iseqFsm_state_set_pw$whas =
WILL_FIRE_RL_spiClk_iseqFsm_idle_l43c3 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 ;
assign spiClk_iseqFsm_state_overlap_pw$whas = 1'b0 ;
assign adcCore0_colGate_operatePW$whas = adcCore0_operateD$dD_OUT ;
assign adcCore0_colGate_collectPW$whas = adcCore0_acquireD$dD_OUT ;
assign adcCore0_colGate_enaSyncPW$whas = 1'b0 ;
assign adcCore0_colGate_enaTimestampPW$whas = 1'b0 ;
assign adcCore0_sampF_rWrPtr_pwIncrement$whas =
adcCore0_sampF_pwEnqueue$whas ;
assign adcCore0_sampF_rWrPtr_pwDecrement$whas = 1'b0 ;
assign adcCore0_sampF_rRdPtr_pwIncrement$whas =
adcCore0_sampF_pwDequeue$whas ;
assign adcCore0_sampF_rRdPtr_pwDecrement$whas = 1'b0 ;
assign adcCore0_sampF_pwDequeue$whas =
NOT_adcCore0_sampF_rRdPtr_rsCounter_59_EQ_adcC_ETC___d1909 &&
wci_wslv_cState != 3'd2 ||
WILL_FIRE_RL_doMessage ;
assign adcCore0_sampF_pwEnqueue$whas =
adcCore0_colGate_sampF$EMPTY_N &&
adcCore0_colGate_sampF_RDY_first__04_AND_NOT_a_ETC___d961 ;
assign adcCore0_spiI_reqF_enq_pw$whas =
WILL_FIRE_RL_adcCore0_advance_spi_request ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ;
assign adcCore0_spiI_reqF_deq_pw$whas =
MUX_adcCore0_spiI_xmt_d$write_1__SEL_2 ;
assign adcCore0_spiI_reqF_sClear_pw$whas = 1'b0 ;
assign adcCore0_spiI_reqF_dClear_pw$whas = 1'b0 ;
assign adcCore0_spiI_reqF_deq_happened$whas = 1'b0 ;
assign adcCore0_spiI_respF_enq_pw$whas =
adcCore0_spiI_respF_head_wrapped ==
adcCore0_spiI_respF_tail_wrapped &&
!adcCore0_spiI_respF_sInReset$VAL &&
adcCore0_spiI_doResp ;
assign adcCore0_spiI_respF_deq_pw$whas =
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 ;
assign adcCore0_spiI_respF_sClear_pw$whas = 1'b0 ;
assign adcCore0_spiI_respF_dClear_pw$whas = 1'b0 ;
assign adcCore0_spiI_respF_deq_happened$whas = 1'b0 ;
assign adcCore0_iseqFsm_state_set_pw$whas =
WILL_FIRE_RL_adcCore0_iseqFsm_idle_l115c3 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_np ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd2 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12 ;
assign adcCore0_iseqFsm_state_overlap_pw$whas = 1'b0 ;
assign adcCore1_colGate_operatePW$whas = adcCore1_operateD$dD_OUT ;
assign adcCore1_colGate_collectPW$whas = adcCore1_acquireD$dD_OUT ;
assign adcCore1_colGate_enaSyncPW$whas = 1'b0 ;
assign adcCore1_colGate_enaTimestampPW$whas = 1'b0 ;
assign adcCore1_sampF_rWrPtr_pwIncrement$whas =
adcCore1_sampF_pwEnqueue$whas ;
assign adcCore1_sampF_rWrPtr_pwDecrement$whas = 1'b0 ;
assign adcCore1_sampF_rRdPtr_pwIncrement$whas = 1'b0 ;
assign adcCore1_sampF_rRdPtr_pwDecrement$whas = 1'b0 ;
assign adcCore1_sampF_pwDequeue$whas = 1'b0 ;
assign adcCore1_sampF_pwEnqueue$whas =
adcCore1_colGate_sampF$EMPTY_N &&
adcCore1_colGate_sampF_RDY_first__551_AND_NOT__ETC___d1608 ;
assign adcCore1_spiI_reqF_enq_pw$whas =
WILL_FIRE_RL_adcCore1_advance_spi_request ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ;
assign adcCore1_spiI_reqF_deq_pw$whas =
MUX_adcCore1_spiI_xmt_d$write_1__SEL_2 ;
assign adcCore1_spiI_reqF_sClear_pw$whas = 1'b0 ;
assign adcCore1_spiI_reqF_dClear_pw$whas = 1'b0 ;
assign adcCore1_spiI_reqF_deq_happened$whas = 1'b0 ;
assign adcCore1_spiI_respF_enq_pw$whas =
adcCore1_spiI_respF_head_wrapped ==
adcCore1_spiI_respF_tail_wrapped &&
!adcCore1_spiI_respF_sInReset$VAL &&
adcCore1_spiI_doResp ;
assign adcCore1_spiI_respF_deq_pw$whas = WILL_FIRE_RL_get_adc1_resp ;
assign adcCore1_spiI_respF_sClear_pw$whas = 1'b0 ;
assign adcCore1_spiI_respF_dClear_pw$whas = 1'b0 ;
assign adcCore1_spiI_respF_deq_happened$whas = 1'b0 ;
assign adcCore1_iseqFsm_state_set_pw$whas =
WILL_FIRE_RL_adcCore1_iseqFsm_idle_l115c3 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_np ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd2 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12 ;
assign adcCore1_iseqFsm_state_overlap_pw$whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing$whas = WILL_FIRE_RL_doMessage ;
assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign fcAdc_grayCounter_wdCounterCrossing$wget =
fcAdc_grayCounter_rsCounter ;
assign spiClk_spiI_sdiWs$wget = spiClk_spiI_sdiP ;
assign adcCore0_sampF_rWrPtr_wdCounterCrossing$wget =
adcCore0_sampF_rWrPtr_rsCounter ;
assign adcCore0_sampF_rRdPtr_wdCounterCrossing$wget =
adcCore0_sampF_rRdPtr_rsCounter ;
assign adcCore0_spiI_sdiWs$wget = adcCore0_spiI_sdiP ;
assign adcCore1_sampF_rWrPtr_wdCounterCrossing$wget =
adcCore1_sampF_rWrPtr_rsCounter ;
assign adcCore1_sampF_rRdPtr_wdCounterCrossing$wget =
adcCore1_sampF_rRdPtr_rsCounter ;
assign adcCore1_spiI_sdiWs$wget = adcCore1_spiI_sdiP ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register adcControl
assign adcControl$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign adcControl$EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h0C ;
// register adcCore0_acquireDReg
assign adcCore0_acquireDReg$D_IN = adcCore0_acquireDReg_1$whas ;
assign adcCore0_acquireDReg$EN = 1'd1 ;
// register adcCore0_adcRst
assign adcCore0_adcRst$D_IN = adcCore0_adcRst_1$whas ;
assign adcCore0_adcRst$EN = 1'd1 ;
// register adcCore0_averageDReg
assign adcCore0_averageDReg$D_IN = adcCore0_averageDReg_1$whas ;
assign adcCore0_averageDReg$EN = 1'd1 ;
// register adcCore0_colGate_avgEven
assign adcCore0_colGate_avgEven$D_IN =
(adcCore0_colGate_avgPhase == 2'd0) ? x__h36326 : x__h36250 ;
assign adcCore0_colGate_avgEven$EN =
WILL_FIRE_RL_adcCore0_colGate_form_avg4_sample &&
(adcCore0_colGate_avgPhase == 2'd0 ||
adcCore0_colGate_avgPhase == 2'd1) ;
// register adcCore0_colGate_avgOdd
assign adcCore0_colGate_avgOdd$D_IN =
(adcCore0_colGate_avgPhase == 2'd2) ? x__h36326 : x__h36400 ;
assign adcCore0_colGate_avgOdd$EN =
WILL_FIRE_RL_adcCore0_colGate_form_avg4_sample &&
(adcCore0_colGate_avgPhase == 2'd2 ||
adcCore0_colGate_avgPhase == 2'd3) ;
// register adcCore0_colGate_avgPhase
assign adcCore0_colGate_avgPhase$D_IN = adcCore0_colGate_avgPhase + 2'd1 ;
assign adcCore0_colGate_avgPhase$EN =
WILL_FIRE_RL_adcCore0_colGate_form_avg4_sample ;
// register adcCore0_colGate_collectD
assign adcCore0_colGate_collectD$D_IN =
adcCore0_operateD$dD_OUT && adcCore0_acquireD$dD_OUT ;
assign adcCore0_colGate_collectD$EN = 1'b1 ;
// register adcCore0_colGate_dropCount
assign adcCore0_colGate_dropCount$D_IN =
WILL_FIRE_RL_adcCore0_colGate_count_dropped_samples ?
MUX_adcCore0_colGate_dropCount$write_1__VAL_1 :
32'd0 ;
assign adcCore0_colGate_dropCount$EN =
WILL_FIRE_RL_adcCore0_colGate_count_dropped_samples ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_colGate_dwellFails
assign adcCore0_colGate_dwellFails$D_IN =
MUX_adcCore0_colGate_dwellFails$write_1__SEL_1 ?
MUX_adcCore0_colGate_dwellFails$write_1__VAL_1 :
32'd0 ;
assign adcCore0_colGate_dwellFails$EN =
WILL_FIRE_RL_adcCore0_colGate_count_dropped_samples &&
adcCore0_colGate_ovrRecover == 4'd0 ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_colGate_dwellStarts
assign adcCore0_colGate_dwellStarts$D_IN =
WILL_FIRE_RL_adcCore0_colGate_count_dwells ?
MUX_adcCore0_colGate_dwellStarts$write_1__VAL_1 :
32'd0 ;
assign adcCore0_colGate_dwellStarts$EN =
WILL_FIRE_RL_adcCore0_colGate_count_dwells ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_colGate_ovrRecover
always@(MUX_adcCore0_colGate_dwellFails$write_1__SEL_1 or
WILL_FIRE_RL_adcCore0_colGate_overrun_recovery or
MUX_adcCore0_colGate_ovrRecover$write_1__VAL_2 or
adcCore0_operateD$dD_OUT)
begin
case (1'b1) // synopsys parallel_case
MUX_adcCore0_colGate_dwellFails$write_1__SEL_1:
adcCore0_colGate_ovrRecover$D_IN = 4'd15;
WILL_FIRE_RL_adcCore0_colGate_overrun_recovery:
adcCore0_colGate_ovrRecover$D_IN =
MUX_adcCore0_colGate_ovrRecover$write_1__VAL_2;
!adcCore0_operateD$dD_OUT: adcCore0_colGate_ovrRecover$D_IN = 4'd0;
default: adcCore0_colGate_ovrRecover$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign adcCore0_colGate_ovrRecover$EN =
WILL_FIRE_RL_adcCore0_colGate_count_dropped_samples &&
adcCore0_colGate_ovrRecover == 4'd0 ||
WILL_FIRE_RL_adcCore0_colGate_overrun_recovery ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_colGate_sampActive
assign adcCore0_colGate_sampActive$D_IN = 1'b1 ;
assign adcCore0_colGate_sampActive$EN = 1'd1 ;
// register adcCore0_colGate_sampActiveD
assign adcCore0_colGate_sampActiveD$D_IN =
adcCore0_operateD$dD_OUT && adcCore0_colGate_sampActive ;
assign adcCore0_colGate_sampActiveD$EN = 1'b1 ;
// register adcCore0_colGate_sampCount
assign adcCore0_colGate_sampCount$D_IN =
WILL_FIRE_RL_adcCore0_colGate_capture_collect ?
MUX_adcCore0_colGate_sampCount$write_1__VAL_1 :
32'd0 ;
assign adcCore0_colGate_sampCount$EN =
WILL_FIRE_RL_adcCore0_colGate_capture_collect ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_colGate_sampDataWD
assign adcCore0_colGate_sampDataWD$D_IN = adcCore0_samp ;
assign adcCore0_colGate_sampDataWD$EN =
MUX_adcCore0_colGate_dwellFails$write_1__SEL_1 ;
// register adcCore0_colGate_syncMesg
assign adcCore0_colGate_syncMesg$D_IN =
WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg ?
MUX_adcCore0_colGate_syncMesg$write_1__VAL_1 :
2'd0 ;
assign adcCore0_colGate_syncMesg$EN =
WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_colGate_timeMesg
assign adcCore0_colGate_timeMesg$D_IN =
WILL_FIRE_RL_adcCore0_colGate_send_timestamp_mesg ?
MUX_adcCore0_colGate_timeMesg$write_1__VAL_1 :
3'd0 ;
assign adcCore0_colGate_timeMesg$EN =
WILL_FIRE_RL_adcCore0_colGate_send_timestamp_mesg ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_colGate_uprollCnt
assign adcCore0_colGate_uprollCnt$D_IN =
WILL_FIRE_RL_adcCore0_colGate_capture_collect ?
MUX_adcCore0_colGate_uprollCnt$write_1__VAL_2 :
16'd0 ;
assign adcCore0_colGate_uprollCnt$EN =
WILL_FIRE_RL_adcCore0_colGate_overrun_recovery &&
adcCore0_colGate_ovrRecover == 4'd15 ||
WILL_FIRE_RL_adcCore0_colGate_capture_collect ||
!adcCore0_operateD$dD_OUT ;
// register adcCore0_ddrC_psCmdReg
assign adcCore0_ddrC_psCmdReg$D_IN =
adcCore0_ddrC_psCmdReg_1$whas ? wci_wslv_reqF$D_OUT[1:0] : 2'd0 ;
assign adcCore0_ddrC_psCmdReg$EN = 1'd1 ;
// register adcCore0_iseqFsm_jj_delay_count
assign adcCore0_iseqFsm_jj_delay_count$D_IN =
WILL_FIRE_RL_adcCore0_iseqFsm_action_np ?
MUX_adcCore0_iseqFsm_jj_delay_count$write_1__VAL_1 :
13'd1 ;
assign adcCore0_iseqFsm_jj_delay_count$EN =
WILL_FIRE_RL_adcCore0_iseqFsm_action_np ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd2 ;
// register adcCore0_iseqFsm_start_reg
assign adcCore0_iseqFsm_start_reg$D_IN =
!WILL_FIRE_RL_adcCore0_iseqFsm_fsm_start ;
assign adcCore0_iseqFsm_start_reg$EN =
WILL_FIRE_RL_adcCore0_iseqFsm_fsm_start ||
WILL_FIRE_RL_wci_ctrl_EiI ;
// register adcCore0_iseqFsm_start_reg_1
assign adcCore0_iseqFsm_start_reg_1$D_IN =
adcCore0_iseqFsm_start_wire$whas ;
assign adcCore0_iseqFsm_start_reg_1$EN = 1'd1 ;
// register adcCore0_iseqFsm_state_can_overlap
assign adcCore0_iseqFsm_state_can_overlap$D_IN =
adcCore0_iseqFsm_state_set_pw$whas ||
adcCore0_iseqFsm_state_can_overlap ;
assign adcCore0_iseqFsm_state_can_overlap$EN = 1'd1 ;
// register adcCore0_iseqFsm_state_fired
assign adcCore0_iseqFsm_state_fired$D_IN =
adcCore0_iseqFsm_state_set_pw$whas ;
assign adcCore0_iseqFsm_state_fired$EN = 1'd1 ;
// register adcCore0_iseqFsm_state_mkFSMstate
always@(WILL_FIRE_RL_adcCore0_iseqFsm_idle_l115c3 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12 or
adcCore0_iseqFsm_state_mkFSMstate or
WILL_FIRE_RL_adcCore0_iseqFsm_action_np or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_adcCore0_iseqFsm_idle_l115c3:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd0;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd1;
adcCore0_iseqFsm_state_mkFSMstate == 4'd1:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd2;
adcCore0_iseqFsm_state_mkFSMstate == 4'd2:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd3;
WILL_FIRE_RL_adcCore0_iseqFsm_action_np:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd4;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd7;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd8;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd9;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9:
adcCore0_iseqFsm_state_mkFSMstate$D_IN = 4'd10;
default: adcCore0_iseqFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign adcCore0_iseqFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_adcCore0_iseqFsm_idle_l115c3 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9 ;
// register adcCore0_operateDReg
assign adcCore0_operateDReg$D_IN = wci_wslv_cState == 3'd2 ;
assign adcCore0_operateDReg$EN = 1'd1 ;
// register adcCore0_readMode
assign adcCore0_readMode$D_IN =
adcCore0_reqF$D_OUT[16] && !adcCore0_readMode ;
assign adcCore0_readMode$EN =
WILL_FIRE_RL_adcCore0_advance_spi_request &&
(adcCore0_reqF$D_OUT[16] && !adcCore0_readMode ||
!adcCore0_reqF$D_OUT[16] && adcCore0_readMode) ;
// register adcCore0_samp
assign adcCore0_samp$D_IN =
{ adcCore0_ddrC_ddrV$sdrData1,
2'h0,
adcCore0_ddrC_ddrV$sdrData0,
2'h0 } ;
assign adcCore0_samp$EN = 1'd1 ;
// register adcCore0_sampF_rRdPtr_rdCounter
assign adcCore0_sampF_rRdPtr_rdCounter$D_IN =
adcCore0_sampF_rRdPtr_rdCounterPre ;
assign adcCore0_sampF_rRdPtr_rdCounter$EN = 1'd1 ;
// register adcCore0_sampF_rRdPtr_rdCounterPre
assign adcCore0_sampF_rRdPtr_rdCounterPre$D_IN =
adcCore0_sampF_rRdPtr_rsCounter ;
assign adcCore0_sampF_rRdPtr_rdCounterPre$EN = 1'd1 ;
// register adcCore0_sampF_rRdPtr_rsCounter
assign adcCore0_sampF_rRdPtr_rsCounter$D_IN =
MUX_adcCore0_sampF_rRdPtr_rsCounter$write_1__VAL_1 ;
assign adcCore0_sampF_rRdPtr_rsCounter$EN = adcCore0_sampF_pwDequeue$whas ;
// register adcCore0_sampF_rWrPtr_rdCounter
assign adcCore0_sampF_rWrPtr_rdCounter$D_IN =
adcCore0_sampF_rWrPtr_rdCounterPre ;
assign adcCore0_sampF_rWrPtr_rdCounter$EN = 1'd1 ;
// register adcCore0_sampF_rWrPtr_rdCounterPre
assign adcCore0_sampF_rWrPtr_rdCounterPre$D_IN =
adcCore0_sampF_rWrPtr_rsCounter ;
assign adcCore0_sampF_rWrPtr_rdCounterPre$EN = 1'd1 ;
// register adcCore0_sampF_rWrPtr_rsCounter
assign adcCore0_sampF_rWrPtr_rsCounter$D_IN =
MUX_adcCore0_sampF_rWrPtr_rsCounter$write_1__VAL_1 ;
assign adcCore0_sampF_rWrPtr_rsCounter$EN = adcCore0_sampF_pwEnqueue$whas ;
// register adcCore0_spiI_cGate
assign adcCore0_spiI_cGate$D_IN = adcCore0_spiI_cGate_1$whas ;
assign adcCore0_spiI_cGate$EN = 1'd1 ;
// register adcCore0_spiI_cap
assign adcCore0_spiI_cap$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap$EN = MUX_adcCore0_spiI_xmt_d$write_1__SEL_2 ;
// register adcCore0_spiI_cap_1
assign adcCore0_spiI_cap_1$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap_1$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd1 ;
// register adcCore0_spiI_cap_2
assign adcCore0_spiI_cap_2$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap_2$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd2 ;
// register adcCore0_spiI_cap_3
assign adcCore0_spiI_cap_3$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap_3$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd3 ;
// register adcCore0_spiI_cap_4
assign adcCore0_spiI_cap_4$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap_4$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd4 ;
// register adcCore0_spiI_cap_5
assign adcCore0_spiI_cap_5$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap_5$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd5 ;
// register adcCore0_spiI_cap_6
assign adcCore0_spiI_cap_6$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap_6$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd6 ;
// register adcCore0_spiI_cap_7
assign adcCore0_spiI_cap_7$D_IN = adcCore0_spiI_sdiP ;
assign adcCore0_spiI_cap_7$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d && adcCore0_spiI_dPos == 3'd7 ;
// register adcCore0_spiI_csbR
assign adcCore0_spiI_csbR$D_IN = !adcCore0_spiI_cGate_1$whas ;
assign adcCore0_spiI_csbR$EN = 1'd1 ;
// register adcCore0_spiI_dPos
assign adcCore0_spiI_dPos$D_IN =
WILL_FIRE_RL_adcCore0_spiI_send_d ?
MUX_adcCore0_spiI_dPos$write_1__VAL_1 :
3'h7 ;
assign adcCore0_spiI_dPos$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d ||
WILL_FIRE_RL_adcCore0_spiI_start_cs ;
// register adcCore0_spiI_doResp
assign adcCore0_spiI_doResp$D_IN =
MUX_adcCore0_spiI_xmt_d$write_1__SEL_2 &&
adcCore0_spiI_reqS[16] ;
assign adcCore0_spiI_doResp$EN = 1'd1 ;
// register adcCore0_spiI_iPos
assign adcCore0_spiI_iPos$D_IN =
WILL_FIRE_RL_adcCore0_spiI_send_i ?
MUX_adcCore0_spiI_iPos$write_1__VAL_1 :
4'h7 ;
assign adcCore0_spiI_iPos$EN =
WILL_FIRE_RL_adcCore0_spiI_send_i ||
WILL_FIRE_RL_adcCore0_spiI_start_cs ;
// register adcCore0_spiI_reqF_head_wrapped
assign adcCore0_spiI_reqF_head_wrapped$D_IN =
WILL_FIRE_RL_adcCore0_spiI_reqF_deq_update_head &&
!adcCore0_spiI_reqF_head_wrapped ;
assign adcCore0_spiI_reqF_head_wrapped$EN =
WILL_FIRE_RL_adcCore0_spiI_reqF_deq_update_head ||
adcCore0_spiI_reqF_dInReset$VAL ;
// register adcCore0_spiI_reqF_tail_wrapped
assign adcCore0_spiI_reqF_tail_wrapped$D_IN =
WILL_FIRE_RL_adcCore0_spiI_reqF_enq_update_tail &&
!adcCore0_spiI_reqF_tail_wrapped ;
assign adcCore0_spiI_reqF_tail_wrapped$EN =
WILL_FIRE_RL_adcCore0_spiI_reqF_enq_update_tail ||
adcCore0_spiI_reqF_sInReset$VAL ;
// register adcCore0_spiI_reqS
always@(WILL_FIRE_RL_adcCore0_advance_spi_request or
MUX_adcCore0_spiI_reqS$write_1__VAL_1 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 or
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_adcCore0_advance_spi_request:
adcCore0_spiI_reqS$D_IN = MUX_adcCore0_spiI_reqS$write_1__VAL_1;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9:
adcCore0_spiI_reqS$D_IN = 17'd20486;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9:
adcCore0_spiI_reqS$D_IN = 17'd20788;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9:
adcCore0_spiI_reqS$D_IN = 17'd21010;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9:
adcCore0_spiI_reqS$D_IN = 17'd21568;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9:
adcCore0_spiI_reqS$D_IN = 17'd21776;
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9:
adcCore0_spiI_reqS$D_IN = 17'd25092;
default: adcCore0_spiI_reqS$D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign adcCore0_spiI_reqS$EN =
WILL_FIRE_RL_adcCore0_advance_spi_request ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9 ;
// register adcCore0_spiI_respF_head_wrapped
assign adcCore0_spiI_respF_head_wrapped$D_IN =
WILL_FIRE_RL_adcCore0_spiI_respF_deq_update_head &&
!adcCore0_spiI_respF_head_wrapped ;
assign adcCore0_spiI_respF_head_wrapped$EN =
WILL_FIRE_RL_adcCore0_spiI_respF_deq_update_head ||
adcCore0_spiI_respF_dInReset$VAL ;
// register adcCore0_spiI_respF_tail_wrapped
assign adcCore0_spiI_respF_tail_wrapped$D_IN =
WILL_FIRE_RL_adcCore0_spiI_respF_enq_update_tail &&
!adcCore0_spiI_respF_tail_wrapped ;
assign adcCore0_spiI_respF_tail_wrapped$EN =
WILL_FIRE_RL_adcCore0_spiI_respF_enq_update_tail ||
adcCore0_spiI_respF_sInReset$VAL ;
// register adcCore0_spiI_respS
assign adcCore0_spiI_respS$D_IN =
{ adcCore0_spiI_cap_6,
adcCore0_spiI_cap_5,
adcCore0_spiI_cap_4,
adcCore0_spiI_cap_3,
adcCore0_spiI_cap_2,
adcCore0_spiI_cap_1,
adcCore0_spiI_cap,
adcCore0_spiI_sdiP } ;
assign adcCore0_spiI_respS$EN = adcCore0_spiI_respF_enq_pw$whas ;
// register adcCore0_spiI_sdiP
assign adcCore0_spiI_sdiP$D_IN = adc0_sdout_arg ;
assign adcCore0_spiI_sdiP$EN = 1'd1 ;
// register adcCore0_spiI_sdoR
assign adcCore0_spiI_sdoR$D_IN =
adcCore0_spiI_cGate_1$whas && adcCore0_spiI_sdoR_1$wget ;
assign adcCore0_spiI_sdoR$EN = 1'd1 ;
// register adcCore0_spiI_xmt_d
assign adcCore0_spiI_xmt_d$D_IN =
WILL_FIRE_RL_adcCore0_spiI_send_i && adcCore0_spiI_iPos == 4'd0 ;
assign adcCore0_spiI_xmt_d$EN =
WILL_FIRE_RL_adcCore0_spiI_send_d &&
adcCore0_spiI_dPos == 3'd0 ||
WILL_FIRE_RL_adcCore0_spiI_send_i ;
// register adcCore0_spiI_xmt_i
assign adcCore0_spiI_xmt_i$D_IN =
!WILL_FIRE_RL_adcCore0_spiI_send_i ||
adcCore0_spiI_iPos != 4'd0 ;
assign adcCore0_spiI_xmt_i$EN =
WILL_FIRE_RL_adcCore0_spiI_send_i ||
WILL_FIRE_RL_adcCore0_spiI_start_cs ;
// register adcCore1_acquireDReg
assign adcCore1_acquireDReg$D_IN = 1'b0 ;
assign adcCore1_acquireDReg$EN = 1'd1 ;
// register adcCore1_adcRst
assign adcCore1_adcRst$D_IN = adcCore1_adcRst_1$whas ;
assign adcCore1_adcRst$EN = 1'd1 ;
// register adcCore1_averageDReg
assign adcCore1_averageDReg$D_IN = 1'b0 ;
assign adcCore1_averageDReg$EN = 1'd1 ;
// register adcCore1_colGate_avgEven
assign adcCore1_colGate_avgEven$D_IN =
(adcCore1_colGate_avgPhase == 2'd0) ? x__h82036 : x__h81960 ;
assign adcCore1_colGate_avgEven$EN =
WILL_FIRE_RL_adcCore1_colGate_form_avg4_sample &&
(adcCore1_colGate_avgPhase == 2'd0 ||
adcCore1_colGate_avgPhase == 2'd1) ;
// register adcCore1_colGate_avgOdd
assign adcCore1_colGate_avgOdd$D_IN =
(adcCore1_colGate_avgPhase == 2'd2) ? x__h82036 : x__h82110 ;
assign adcCore1_colGate_avgOdd$EN =
WILL_FIRE_RL_adcCore1_colGate_form_avg4_sample &&
(adcCore1_colGate_avgPhase == 2'd2 ||
adcCore1_colGate_avgPhase == 2'd3) ;
// register adcCore1_colGate_avgPhase
assign adcCore1_colGate_avgPhase$D_IN = adcCore1_colGate_avgPhase + 2'd1 ;
assign adcCore1_colGate_avgPhase$EN =
WILL_FIRE_RL_adcCore1_colGate_form_avg4_sample ;
// register adcCore1_colGate_collectD
assign adcCore1_colGate_collectD$D_IN =
adcCore1_operateD$dD_OUT && adcCore1_acquireD$dD_OUT ;
assign adcCore1_colGate_collectD$EN = 1'b1 ;
// register adcCore1_colGate_dropCount
assign adcCore1_colGate_dropCount$D_IN =
WILL_FIRE_RL_adcCore1_colGate_count_dropped_samples ?
MUX_adcCore1_colGate_dropCount$write_1__VAL_1 :
32'd0 ;
assign adcCore1_colGate_dropCount$EN =
WILL_FIRE_RL_adcCore1_colGate_count_dropped_samples ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_colGate_dwellFails
assign adcCore1_colGate_dwellFails$D_IN =
MUX_adcCore1_colGate_dwellFails$write_1__SEL_1 ?
MUX_adcCore1_colGate_dwellFails$write_1__VAL_1 :
32'd0 ;
assign adcCore1_colGate_dwellFails$EN =
WILL_FIRE_RL_adcCore1_colGate_count_dropped_samples &&
adcCore1_colGate_ovrRecover == 4'd0 ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_colGate_dwellStarts
assign adcCore1_colGate_dwellStarts$D_IN =
WILL_FIRE_RL_adcCore1_colGate_count_dwells ?
MUX_adcCore1_colGate_dwellStarts$write_1__VAL_1 :
32'd0 ;
assign adcCore1_colGate_dwellStarts$EN =
WILL_FIRE_RL_adcCore1_colGate_count_dwells ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_colGate_ovrRecover
always@(MUX_adcCore1_colGate_dwellFails$write_1__SEL_1 or
WILL_FIRE_RL_adcCore1_colGate_overrun_recovery or
MUX_adcCore1_colGate_ovrRecover$write_1__VAL_2 or
adcCore1_operateD$dD_OUT)
begin
case (1'b1) // synopsys parallel_case
MUX_adcCore1_colGate_dwellFails$write_1__SEL_1:
adcCore1_colGate_ovrRecover$D_IN = 4'd15;
WILL_FIRE_RL_adcCore1_colGate_overrun_recovery:
adcCore1_colGate_ovrRecover$D_IN =
MUX_adcCore1_colGate_ovrRecover$write_1__VAL_2;
!adcCore1_operateD$dD_OUT: adcCore1_colGate_ovrRecover$D_IN = 4'd0;
default: adcCore1_colGate_ovrRecover$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign adcCore1_colGate_ovrRecover$EN =
WILL_FIRE_RL_adcCore1_colGate_count_dropped_samples &&
adcCore1_colGate_ovrRecover == 4'd0 ||
WILL_FIRE_RL_adcCore1_colGate_overrun_recovery ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_colGate_sampActive
assign adcCore1_colGate_sampActive$D_IN = 1'b1 ;
assign adcCore1_colGate_sampActive$EN = 1'd1 ;
// register adcCore1_colGate_sampActiveD
assign adcCore1_colGate_sampActiveD$D_IN =
adcCore1_operateD$dD_OUT && adcCore1_colGate_sampActive ;
assign adcCore1_colGate_sampActiveD$EN = 1'b1 ;
// register adcCore1_colGate_sampCount
assign adcCore1_colGate_sampCount$D_IN =
WILL_FIRE_RL_adcCore1_colGate_capture_collect ?
MUX_adcCore1_colGate_sampCount$write_1__VAL_1 :
32'd0 ;
assign adcCore1_colGate_sampCount$EN =
WILL_FIRE_RL_adcCore1_colGate_capture_collect ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_colGate_sampDataWD
assign adcCore1_colGate_sampDataWD$D_IN = adcCore1_samp ;
assign adcCore1_colGate_sampDataWD$EN =
MUX_adcCore1_colGate_dwellFails$write_1__SEL_1 ;
// register adcCore1_colGate_syncMesg
assign adcCore1_colGate_syncMesg$D_IN =
WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg ?
MUX_adcCore1_colGate_syncMesg$write_1__VAL_1 :
2'd0 ;
assign adcCore1_colGate_syncMesg$EN =
WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_colGate_timeMesg
assign adcCore1_colGate_timeMesg$D_IN =
WILL_FIRE_RL_adcCore1_colGate_send_timestamp_mesg ?
MUX_adcCore1_colGate_timeMesg$write_1__VAL_1 :
3'd0 ;
assign adcCore1_colGate_timeMesg$EN =
WILL_FIRE_RL_adcCore1_colGate_send_timestamp_mesg ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_colGate_uprollCnt
assign adcCore1_colGate_uprollCnt$D_IN =
WILL_FIRE_RL_adcCore1_colGate_capture_collect ?
MUX_adcCore1_colGate_uprollCnt$write_1__VAL_2 :
16'd0 ;
assign adcCore1_colGate_uprollCnt$EN =
WILL_FIRE_RL_adcCore1_colGate_overrun_recovery &&
adcCore1_colGate_ovrRecover == 4'd15 ||
WILL_FIRE_RL_adcCore1_colGate_capture_collect ||
!adcCore1_operateD$dD_OUT ;
// register adcCore1_ddrC_psCmdReg
assign adcCore1_ddrC_psCmdReg$D_IN =
adcCore1_ddrC_psCmdReg_1$whas ? wci_wslv_reqF$D_OUT[1:0] : 2'd0 ;
assign adcCore1_ddrC_psCmdReg$EN = 1'd1 ;
// register adcCore1_iseqFsm_jj_delay_count
assign adcCore1_iseqFsm_jj_delay_count$D_IN =
WILL_FIRE_RL_adcCore1_iseqFsm_action_np ?
MUX_adcCore1_iseqFsm_jj_delay_count$write_1__VAL_1 :
13'd1 ;
assign adcCore1_iseqFsm_jj_delay_count$EN =
WILL_FIRE_RL_adcCore1_iseqFsm_action_np ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd2 ;
// register adcCore1_iseqFsm_start_reg
assign adcCore1_iseqFsm_start_reg$D_IN =
!WILL_FIRE_RL_adcCore1_iseqFsm_fsm_start ;
assign adcCore1_iseqFsm_start_reg$EN =
WILL_FIRE_RL_adcCore1_iseqFsm_fsm_start ||
WILL_FIRE_RL_wci_ctrl_EiI ;
// register adcCore1_iseqFsm_start_reg_1
assign adcCore1_iseqFsm_start_reg_1$D_IN =
adcCore1_iseqFsm_start_wire$whas ;
assign adcCore1_iseqFsm_start_reg_1$EN = 1'd1 ;
// register adcCore1_iseqFsm_state_can_overlap
assign adcCore1_iseqFsm_state_can_overlap$D_IN =
adcCore1_iseqFsm_state_set_pw$whas ||
adcCore1_iseqFsm_state_can_overlap ;
assign adcCore1_iseqFsm_state_can_overlap$EN = 1'd1 ;
// register adcCore1_iseqFsm_state_fired
assign adcCore1_iseqFsm_state_fired$D_IN =
adcCore1_iseqFsm_state_set_pw$whas ;
assign adcCore1_iseqFsm_state_fired$EN = 1'd1 ;
// register adcCore1_iseqFsm_state_mkFSMstate
always@(WILL_FIRE_RL_adcCore1_iseqFsm_idle_l115c3 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12 or
adcCore1_iseqFsm_state_mkFSMstate or
WILL_FIRE_RL_adcCore1_iseqFsm_action_np or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_adcCore1_iseqFsm_idle_l115c3:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd0;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd1;
adcCore1_iseqFsm_state_mkFSMstate == 4'd1:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd2;
adcCore1_iseqFsm_state_mkFSMstate == 4'd2:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd3;
WILL_FIRE_RL_adcCore1_iseqFsm_action_np:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd4;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd7;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd8;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd9;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9:
adcCore1_iseqFsm_state_mkFSMstate$D_IN = 4'd10;
default: adcCore1_iseqFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign adcCore1_iseqFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_adcCore1_iseqFsm_idle_l115c3 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd1 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9 ;
// register adcCore1_operateDReg
assign adcCore1_operateDReg$D_IN = 1'b0 ;
assign adcCore1_operateDReg$EN = 1'd1 ;
// register adcCore1_readMode
assign adcCore1_readMode$D_IN =
adcCore1_reqF$D_OUT[16] && !adcCore1_readMode ;
assign adcCore1_readMode$EN =
WILL_FIRE_RL_adcCore1_advance_spi_request &&
(adcCore1_reqF$D_OUT[16] && !adcCore1_readMode ||
!adcCore1_reqF$D_OUT[16] && adcCore1_readMode) ;
// register adcCore1_samp
assign adcCore1_samp$D_IN =
{ adcCore1_ddrC_ddrV$sdrData1,
2'h0,
adcCore1_ddrC_ddrV$sdrData0,
2'h0 } ;
assign adcCore1_samp$EN = 1'd1 ;
// register adcCore1_sampF_rRdPtr_rdCounter
assign adcCore1_sampF_rRdPtr_rdCounter$D_IN =
adcCore1_sampF_rRdPtr_rdCounterPre ;
assign adcCore1_sampF_rRdPtr_rdCounter$EN = 1'd1 ;
// register adcCore1_sampF_rRdPtr_rdCounterPre
assign adcCore1_sampF_rRdPtr_rdCounterPre$D_IN =
adcCore1_sampF_rRdPtr_rsCounter ;
assign adcCore1_sampF_rRdPtr_rdCounterPre$EN = 1'd1 ;
// register adcCore1_sampF_rRdPtr_rsCounter
assign adcCore1_sampF_rRdPtr_rsCounter$D_IN =
11'b01010101010 /* unspecified value */ ;
assign adcCore1_sampF_rRdPtr_rsCounter$EN = 1'b0 ;
// register adcCore1_sampF_rWrPtr_rdCounter
assign adcCore1_sampF_rWrPtr_rdCounter$D_IN =
adcCore1_sampF_rWrPtr_rdCounterPre ;
assign adcCore1_sampF_rWrPtr_rdCounter$EN = 1'd1 ;
// register adcCore1_sampF_rWrPtr_rdCounterPre
assign adcCore1_sampF_rWrPtr_rdCounterPre$D_IN =
adcCore1_sampF_rWrPtr_rsCounter ;
assign adcCore1_sampF_rWrPtr_rdCounterPre$EN = 1'd1 ;
// register adcCore1_sampF_rWrPtr_rsCounter
assign adcCore1_sampF_rWrPtr_rsCounter$D_IN =
MUX_adcCore1_sampF_rWrPtr_rsCounter$write_1__VAL_1 ;
assign adcCore1_sampF_rWrPtr_rsCounter$EN = adcCore1_sampF_pwEnqueue$whas ;
// register adcCore1_spiI_cGate
assign adcCore1_spiI_cGate$D_IN = adcCore1_spiI_cGate_1$whas ;
assign adcCore1_spiI_cGate$EN = 1'd1 ;
// register adcCore1_spiI_cap
assign adcCore1_spiI_cap$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap$EN = MUX_adcCore1_spiI_xmt_d$write_1__SEL_2 ;
// register adcCore1_spiI_cap_1
assign adcCore1_spiI_cap_1$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap_1$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd1 ;
// register adcCore1_spiI_cap_2
assign adcCore1_spiI_cap_2$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap_2$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd2 ;
// register adcCore1_spiI_cap_3
assign adcCore1_spiI_cap_3$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap_3$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd3 ;
// register adcCore1_spiI_cap_4
assign adcCore1_spiI_cap_4$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap_4$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd4 ;
// register adcCore1_spiI_cap_5
assign adcCore1_spiI_cap_5$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap_5$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd5 ;
// register adcCore1_spiI_cap_6
assign adcCore1_spiI_cap_6$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap_6$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd6 ;
// register adcCore1_spiI_cap_7
assign adcCore1_spiI_cap_7$D_IN = adcCore1_spiI_sdiP ;
assign adcCore1_spiI_cap_7$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d && adcCore1_spiI_dPos == 3'd7 ;
// register adcCore1_spiI_csbR
assign adcCore1_spiI_csbR$D_IN = !adcCore1_spiI_cGate_1$whas ;
assign adcCore1_spiI_csbR$EN = 1'd1 ;
// register adcCore1_spiI_dPos
assign adcCore1_spiI_dPos$D_IN =
WILL_FIRE_RL_adcCore1_spiI_send_d ?
MUX_adcCore1_spiI_dPos$write_1__VAL_1 :
3'h7 ;
assign adcCore1_spiI_dPos$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d ||
WILL_FIRE_RL_adcCore1_spiI_start_cs ;
// register adcCore1_spiI_doResp
assign adcCore1_spiI_doResp$D_IN =
MUX_adcCore1_spiI_xmt_d$write_1__SEL_2 &&
adcCore1_spiI_reqS[16] ;
assign adcCore1_spiI_doResp$EN = 1'd1 ;
// register adcCore1_spiI_iPos
assign adcCore1_spiI_iPos$D_IN =
WILL_FIRE_RL_adcCore1_spiI_send_i ?
MUX_adcCore1_spiI_iPos$write_1__VAL_1 :
4'h7 ;
assign adcCore1_spiI_iPos$EN =
WILL_FIRE_RL_adcCore1_spiI_send_i ||
WILL_FIRE_RL_adcCore1_spiI_start_cs ;
// register adcCore1_spiI_reqF_head_wrapped
assign adcCore1_spiI_reqF_head_wrapped$D_IN =
WILL_FIRE_RL_adcCore1_spiI_reqF_deq_update_head &&
!adcCore1_spiI_reqF_head_wrapped ;
assign adcCore1_spiI_reqF_head_wrapped$EN =
WILL_FIRE_RL_adcCore1_spiI_reqF_deq_update_head ||
adcCore1_spiI_reqF_dInReset$VAL ;
// register adcCore1_spiI_reqF_tail_wrapped
assign adcCore1_spiI_reqF_tail_wrapped$D_IN =
WILL_FIRE_RL_adcCore1_spiI_reqF_enq_update_tail &&
!adcCore1_spiI_reqF_tail_wrapped ;
assign adcCore1_spiI_reqF_tail_wrapped$EN =
WILL_FIRE_RL_adcCore1_spiI_reqF_enq_update_tail ||
adcCore1_spiI_reqF_sInReset$VAL ;
// register adcCore1_spiI_reqS
always@(WILL_FIRE_RL_adcCore1_advance_spi_request or
MUX_adcCore1_spiI_reqS$write_1__VAL_1 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 or
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_adcCore1_advance_spi_request:
adcCore1_spiI_reqS$D_IN = MUX_adcCore1_spiI_reqS$write_1__VAL_1;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9:
adcCore1_spiI_reqS$D_IN = 17'd20486;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9:
adcCore1_spiI_reqS$D_IN = 17'd20788;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9:
adcCore1_spiI_reqS$D_IN = 17'd21010;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9:
adcCore1_spiI_reqS$D_IN = 17'd21568;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9:
adcCore1_spiI_reqS$D_IN = 17'd21776;
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9:
adcCore1_spiI_reqS$D_IN = 17'd25092;
default: adcCore1_spiI_reqS$D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign adcCore1_spiI_reqS$EN =
WILL_FIRE_RL_adcCore1_advance_spi_request ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9 ;
// register adcCore1_spiI_respF_head_wrapped
assign adcCore1_spiI_respF_head_wrapped$D_IN =
WILL_FIRE_RL_adcCore1_spiI_respF_deq_update_head &&
!adcCore1_spiI_respF_head_wrapped ;
assign adcCore1_spiI_respF_head_wrapped$EN =
WILL_FIRE_RL_adcCore1_spiI_respF_deq_update_head ||
adcCore1_spiI_respF_dInReset$VAL ;
// register adcCore1_spiI_respF_tail_wrapped
assign adcCore1_spiI_respF_tail_wrapped$D_IN =
WILL_FIRE_RL_adcCore1_spiI_respF_enq_update_tail &&
!adcCore1_spiI_respF_tail_wrapped ;
assign adcCore1_spiI_respF_tail_wrapped$EN =
WILL_FIRE_RL_adcCore1_spiI_respF_enq_update_tail ||
adcCore1_spiI_respF_sInReset$VAL ;
// register adcCore1_spiI_respS
assign adcCore1_spiI_respS$D_IN =
{ adcCore1_spiI_cap_6,
adcCore1_spiI_cap_5,
adcCore1_spiI_cap_4,
adcCore1_spiI_cap_3,
adcCore1_spiI_cap_2,
adcCore1_spiI_cap_1,
adcCore1_spiI_cap,
adcCore1_spiI_sdiP } ;
assign adcCore1_spiI_respS$EN = adcCore1_spiI_respF_enq_pw$whas ;
// register adcCore1_spiI_sdiP
assign adcCore1_spiI_sdiP$D_IN = adc1_sdout_arg ;
assign adcCore1_spiI_sdiP$EN = 1'd1 ;
// register adcCore1_spiI_sdoR
assign adcCore1_spiI_sdoR$D_IN =
adcCore1_spiI_cGate_1$whas && adcCore1_spiI_sdoR_1$wget ;
assign adcCore1_spiI_sdoR$EN = 1'd1 ;
// register adcCore1_spiI_xmt_d
assign adcCore1_spiI_xmt_d$D_IN =
WILL_FIRE_RL_adcCore1_spiI_send_i && adcCore1_spiI_iPos == 4'd0 ;
assign adcCore1_spiI_xmt_d$EN =
WILL_FIRE_RL_adcCore1_spiI_send_d &&
adcCore1_spiI_dPos == 3'd0 ||
WILL_FIRE_RL_adcCore1_spiI_send_i ;
// register adcCore1_spiI_xmt_i
assign adcCore1_spiI_xmt_i$D_IN =
!WILL_FIRE_RL_adcCore1_spiI_send_i ||
adcCore1_spiI_iPos != 4'd0 ;
assign adcCore1_spiI_xmt_i$EN =
WILL_FIRE_RL_adcCore1_spiI_send_i ||
WILL_FIRE_RL_adcCore1_spiI_start_cs ;
// register adcIdc_doResetCount
assign adcIdc_doResetCount$D_IN =
(adcIdc_doResetCount == 4'hF) ?
adcIdc_doResetCount :
adcIdc_doResetCount + 4'd1 ;
assign adcIdc_doResetCount$EN = adcIdc_preResetCount == 4'hF ;
// register adcIdc_preResetCount
assign adcIdc_preResetCount$D_IN =
(adcIdc_preResetCount == 4'hF) ?
adcIdc_preResetCount :
adcIdc_preResetCount + 4'd1 ;
assign adcIdc_preResetCount$EN = 1'd1 ;
// register fcAdc_countNow
assign fcAdc_countNow$D_IN =
{ fcAdc_grayCounter_rdCounter[17],
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2132,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2151,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2133,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2134,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2149,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2135,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2136,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2137,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2153,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2152,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2154,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2138,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2139,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2141,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2147,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2140,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2140 ^
fcAdc_grayCounter_rdCounter[0] } ;
assign fcAdc_countNow$EN = fcAdc_pulseAction ;
// register fcAdc_countPast
assign fcAdc_countPast$D_IN = fcAdc_countNow ;
assign fcAdc_countPast$EN = fcAdc_pulseAction ;
// register fcAdc_frequency
assign fcAdc_frequency$D_IN = fcAdc_countNow - fcAdc_countPast ;
assign fcAdc_frequency$EN = fcAdc_pulseAction ;
// register fcAdc_grayCounter_rdCounter
assign fcAdc_grayCounter_rdCounter$D_IN = fcAdc_grayCounter_rdCounterPre ;
assign fcAdc_grayCounter_rdCounter$EN = 1'd1 ;
// register fcAdc_grayCounter_rdCounterPre
assign fcAdc_grayCounter_rdCounterPre$D_IN = fcAdc_grayCounter_rsCounter ;
assign fcAdc_grayCounter_rdCounterPre$EN = 1'd1 ;
// register fcAdc_grayCounter_rsCounter
assign fcAdc_grayCounter_rsCounter$D_IN =
MUX_fcAdc_grayCounter_rsCounter$write_1__VAL_1 ;
assign fcAdc_grayCounter_rsCounter$EN = 1'b1 ;
// register fcAdc_pulseAction
assign fcAdc_pulseAction$D_IN = oneKHz_value == 18'd124999 ;
assign fcAdc_pulseAction$EN = 1'd1 ;
// register fcAdc_sampleCount
assign fcAdc_sampleCount$D_IN = fcAdc_sampleCount + 16'd1 ;
assign fcAdc_sampleCount$EN = fcAdc_pulseAction ;
// register initOpInFlight
assign initOpInFlight$D_IN = WILL_FIRE_RL_wci_ctrl_EiI ;
assign initOpInFlight$EN =
WILL_FIRE_RL_init_complete_ok || WILL_FIRE_RL_wci_ctrl_EiI ;
// register lastOverflowMesg
assign lastOverflowMesg$D_IN = mesgCount ;
assign lastOverflowMesg$EN =
wci_wslv_cState == 3'd2 &&
overflowCountD != adcCore0_statsCC$dD_OUT[31:0] ;
// register maxMesgLength
assign maxMesgLength$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign maxMesgLength$EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h08 ;
// register mesgCount
assign mesgCount$D_IN = mesgCount + 32'd1 ;
assign mesgCount$EN =
WILL_FIRE_RL_doMessage && adcCore0_sampF_memory$DOB[36] ;
// register oneKHz_value
assign oneKHz_value$D_IN = MUX_oneKHz_value$write_1__VAL_1 ;
assign oneKHz_value$EN = 1'b1 ;
// register overflowCountD
assign overflowCountD$D_IN = adcCore0_statsCC$dD_OUT[31:0] ;
assign overflowCountD$EN = wci_wslv_cState == 3'd2 ;
// register sFlagState
assign sFlagState$D_IN = 1'b0 ;
assign sFlagState$EN = 1'b0 ;
// register spiClk_iState
assign spiClk_iState$D_IN = 4'h0 ;
assign spiClk_iState$EN = 1'b0 ;
// register spiClk_iseqFsm_start_reg
assign spiClk_iseqFsm_start_reg$D_IN =
!WILL_FIRE_RL_spiClk_iseqFsm_fsm_start ;
assign spiClk_iseqFsm_start_reg$EN =
WILL_FIRE_RL_spiClk_iseqFsm_fsm_start ||
WILL_FIRE_RL_wci_ctrl_EiI ;
// register spiClk_iseqFsm_start_reg_1
assign spiClk_iseqFsm_start_reg_1$D_IN = spiClk_iseqFsm_start_wire$whas ;
assign spiClk_iseqFsm_start_reg_1$EN = 1'd1 ;
// register spiClk_iseqFsm_state_can_overlap
assign spiClk_iseqFsm_state_can_overlap$D_IN =
spiClk_iseqFsm_state_set_pw$whas ||
spiClk_iseqFsm_state_can_overlap ;
assign spiClk_iseqFsm_state_can_overlap$EN = 1'd1 ;
// register spiClk_iseqFsm_state_fired
assign spiClk_iseqFsm_state_fired$D_IN = spiClk_iseqFsm_state_set_pw$whas ;
assign spiClk_iseqFsm_state_fired$EN = 1'd1 ;
// register spiClk_iseqFsm_state_mkFSMstate
always@(WILL_FIRE_RL_spiClk_iseqFsm_idle_l43c3 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_spiClk_iseqFsm_idle_l43c3:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd0;
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd1;
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd2;
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd3;
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd4;
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9:
spiClk_iseqFsm_state_mkFSMstate$D_IN = 4'd7;
default: spiClk_iseqFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign spiClk_iseqFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_spiClk_iseqFsm_idle_l43c3 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9 ;
// register spiClk_spiI_cGate
assign spiClk_spiI_cGate$D_IN = spiClk_spiI_cGate_1$whas ;
assign spiClk_spiI_cGate$EN = 1'd1 ;
// register spiClk_spiI_cap
assign spiClk_spiI_cap$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap$EN = MUX_spiClk_spiI_xmt_d$write_1__SEL_2 ;
// register spiClk_spiI_cap_1
assign spiClk_spiI_cap_1$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap_1$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd1 ;
// register spiClk_spiI_cap_2
assign spiClk_spiI_cap_2$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap_2$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd2 ;
// register spiClk_spiI_cap_3
assign spiClk_spiI_cap_3$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap_3$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd3 ;
// register spiClk_spiI_cap_4
assign spiClk_spiI_cap_4$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap_4$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd4 ;
// register spiClk_spiI_cap_5
assign spiClk_spiI_cap_5$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap_5$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd5 ;
// register spiClk_spiI_cap_6
assign spiClk_spiI_cap_6$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap_6$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd6 ;
// register spiClk_spiI_cap_7
assign spiClk_spiI_cap_7$D_IN = spiClk_spiI_sdiP ;
assign spiClk_spiI_cap_7$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd7 ;
// register spiClk_spiI_csbR
assign spiClk_spiI_csbR$D_IN = !spiClk_spiI_cGate_1$whas ;
assign spiClk_spiI_csbR$EN = 1'd1 ;
// register spiClk_spiI_dPos
assign spiClk_spiI_dPos$D_IN =
WILL_FIRE_RL_spiClk_spiI_send_d ?
MUX_spiClk_spiI_dPos$write_1__VAL_1 :
3'h7 ;
assign spiClk_spiI_dPos$EN =
WILL_FIRE_RL_spiClk_spiI_send_d ||
WILL_FIRE_RL_spiClk_spiI_start_cs ;
// register spiClk_spiI_doResp
assign spiClk_spiI_doResp$D_IN =
MUX_spiClk_spiI_xmt_d$write_1__SEL_2 && spiClk_spiI_reqS[16] ;
assign spiClk_spiI_doResp$EN = 1'd1 ;
// register spiClk_spiI_iPos
assign spiClk_spiI_iPos$D_IN =
WILL_FIRE_RL_spiClk_spiI_send_i ?
MUX_spiClk_spiI_iPos$write_1__VAL_1 :
4'hF ;
assign spiClk_spiI_iPos$EN =
WILL_FIRE_RL_spiClk_spiI_send_i ||
WILL_FIRE_RL_spiClk_spiI_start_cs ;
// register spiClk_spiI_reqF_head_wrapped
assign spiClk_spiI_reqF_head_wrapped$D_IN =
WILL_FIRE_RL_spiClk_spiI_reqF_deq_update_head &&
!spiClk_spiI_reqF_head_wrapped ;
assign spiClk_spiI_reqF_head_wrapped$EN =
WILL_FIRE_RL_spiClk_spiI_reqF_deq_update_head ||
spiClk_spiI_reqF_dInReset$VAL ;
// register spiClk_spiI_reqF_tail_wrapped
assign spiClk_spiI_reqF_tail_wrapped$D_IN =
WILL_FIRE_RL_spiClk_spiI_reqF_enq_update_tail &&
!spiClk_spiI_reqF_tail_wrapped ;
assign spiClk_spiI_reqF_tail_wrapped$EN =
WILL_FIRE_RL_spiClk_spiI_reqF_enq_update_tail ||
spiClk_spiI_reqF_sInReset$VAL ;
// register spiClk_spiI_reqS
always@(MUX_spiClk_spiI_reqS$write_1__SEL_1 or
MUX_adcCore0_reqF$enq_1__VAL_1 or
MUX_spiClk_spiI_reqS$write_1__SEL_2 or
MUX_adcCore0_reqF$enq_1__VAL_2 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 or
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9)
begin
case (1'b1) // synopsys parallel_case
MUX_spiClk_spiI_reqS$write_1__SEL_1:
spiClk_spiI_reqS$D_IN = MUX_adcCore0_reqF$enq_1__VAL_1;
MUX_spiClk_spiI_reqS$write_1__SEL_2:
spiClk_spiI_reqS$D_IN = MUX_adcCore0_reqF$enq_1__VAL_2;
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9:
spiClk_spiI_reqS$D_IN = 17'd17666;
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9:
spiClk_spiI_reqS$D_IN = 17'd19328;
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9:
spiClk_spiI_reqS$D_IN = 17'd19840;
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9:
spiClk_spiI_reqS$D_IN = 17'd20352;
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9:
spiClk_spiI_reqS$D_IN = 17'd20864;
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9:
spiClk_spiI_reqS$D_IN = 17'd21376;
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9:
spiClk_spiI_reqS$D_IN = 17'd23041;
default: spiClk_spiI_reqS$D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign spiClk_spiI_reqS$EN =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h24 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b11) ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b11 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9 ;
// register spiClk_spiI_respF_head_wrapped
assign spiClk_spiI_respF_head_wrapped$D_IN =
WILL_FIRE_RL_spiClk_spiI_respF_deq_update_head &&
!spiClk_spiI_respF_head_wrapped ;
assign spiClk_spiI_respF_head_wrapped$EN =
WILL_FIRE_RL_spiClk_spiI_respF_deq_update_head ||
spiClk_spiI_respF_dInReset$VAL ;
// register spiClk_spiI_respF_tail_wrapped
assign spiClk_spiI_respF_tail_wrapped$D_IN =
WILL_FIRE_RL_spiClk_spiI_respF_enq_update_tail &&
!spiClk_spiI_respF_tail_wrapped ;
assign spiClk_spiI_respF_tail_wrapped$EN =
WILL_FIRE_RL_spiClk_spiI_respF_enq_update_tail ||
spiClk_spiI_respF_sInReset$VAL ;
// register spiClk_spiI_respS
assign spiClk_spiI_respS$D_IN =
{ spiClk_spiI_cap_6,
spiClk_spiI_cap_5,
spiClk_spiI_cap_4,
spiClk_spiI_cap_3,
spiClk_spiI_cap_2,
spiClk_spiI_cap_1,
spiClk_spiI_cap,
spiClk_spiI_sdiP } ;
assign spiClk_spiI_respS$EN = spiClk_spiI_respF_enq_pw$whas ;
// register spiClk_spiI_sdiP
assign spiClk_spiI_sdiP$D_IN = adx_sdi_arg ;
assign spiClk_spiI_sdiP$EN = 1'd1 ;
// register spiClk_spiI_sdoR
assign spiClk_spiI_sdoR$D_IN =
spiClk_spiI_sdoR_1$whas && spiClk_spiI_sdoR_1$wget ;
assign spiClk_spiI_sdoR$EN = 1'd1 ;
// register spiClk_spiI_xmt_d
assign spiClk_spiI_xmt_d$D_IN =
WILL_FIRE_RL_spiClk_spiI_send_i && spiClk_spiI_iPos == 4'd0 ;
assign spiClk_spiI_xmt_d$EN =
WILL_FIRE_RL_spiClk_spiI_send_d && spiClk_spiI_dPos == 3'd0 ||
WILL_FIRE_RL_spiClk_spiI_send_i ;
// register spiClk_spiI_xmt_i
assign spiClk_spiI_xmt_i$D_IN =
!WILL_FIRE_RL_spiClk_spiI_send_i || spiClk_spiI_iPos != 4'd0 ;
assign spiClk_spiI_xmt_i$EN =
WILL_FIRE_RL_spiClk_spiI_send_i ||
WILL_FIRE_RL_spiClk_spiI_start_cs ;
// register spiResp
always@(MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 or
spiClk_spiI_respS or
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 or
adcCore0_spiI_respS or
WILL_FIRE_RL_get_adc1_resp or adcCore1_spiI_respS)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1:
spiResp$D_IN = spiClk_spiI_respS;
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2:
spiResp$D_IN = adcCore0_spiI_respS;
WILL_FIRE_RL_get_adc1_resp: spiResp$D_IN = adcCore1_spiI_respS;
default: spiResp$D_IN = 8'b10101010 /* unspecified value */ ;
endcase
end
assign spiResp$EN =
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 ||
WILL_FIRE_RL_get_adc1_resp ;
// register splitReadInFlight
assign splitReadInFlight$D_IN = !MUX_splitReadInFlight$write_1__SEL_1 ;
assign splitReadInFlight$EN =
(WILL_FIRE_RL_get_adc1_resp ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 ||
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1) &&
splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b01 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b10 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b11) ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState$D_IN = wci_wslv_nState ;
assign wci_wslv_cState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ;
assign wci_wslv_ctlAckReg$EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
assign wci_wslv_illegalEdge$EN =
MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF$D_OUT)
begin
case (wci_wslv_reqF$D_OUT[36:34])
3'd0: wci_wslv_nState$D_IN = 3'd1;
3'd1: wci_wslv_nState$D_IN = 3'd2;
3'd2: wci_wslv_nState$D_IN = 3'd3;
default: wci_wslv_nState$D_IN = 3'd0;
endcase
end
assign wci_wslv_nState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg$D_IN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg$EN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq$whas ;
// register wci_wslv_respF_c_r
assign wci_wslv_respF_c_r$D_IN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ?
MUX_wci_wslv_respF_c_r$write_1__VAL_1 :
MUX_wci_wslv_respF_c_r$write_1__VAL_2 ;
assign wci_wslv_respF_c_r$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_0
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
MUX_wci_wslv_respF_q_0$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
MUX_wci_wslv_respF_q_0$write_1__SEL_2:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_1$write_1__VAL_1 or
MUX_wci_wslv_respF_q_1$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1;
MUX_wci_wslv_respF_q_1$write_1__SEL_2:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg$D_IN = sFlagState ;
assign wci_wslv_sFlagReg$EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[57]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset$D_IN = 1'd0 ;
assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_0
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wti_isReset_isInReset
assign wti_isReset_isInReset$D_IN = 1'd0 ;
assign wti_isReset_isInReset$EN = wti_isReset_isInReset ;
// register wti_nowReq
assign wti_nowReq$D_IN = wtiS0_req ;
assign wti_nowReq$EN = 1'd1 ;
// register wti_operateD
assign wti_operateD$D_IN = 1'b1 ;
assign wti_operateD$EN = 1'd1 ;
// submodule adcCore0_acquireD
assign adcCore0_acquireD$sD_IN = adcCore0_acquireDReg ;
assign adcCore0_acquireD$sEN =
adcCore0_operateD$sRDY && adcCore0_acquireD$sRDY &&
adcCore0_averageD$sRDY ;
// submodule adcCore0_averageD
assign adcCore0_averageD$sD_IN = adcCore0_averageDReg ;
assign adcCore0_averageD$sEN =
adcCore0_operateD$sRDY && adcCore0_acquireD$sRDY &&
adcCore0_averageD$sRDY ;
// submodule adcCore0_colGate_sampF
always@(MUX_adcCore0_colGate_sampF$enq_1__SEL_1 or
MUX_adcCore0_colGate_sampF$enq_1__VAL_1 or
WILL_FIRE_RL_adcCore0_colGate_send_timestamp_mesg or
MUX_adcCore0_colGate_sampF$enq_1__VAL_2 or
WILL_FIRE_RL_adcCore0_colGate_capture_collect or
MUX_adcCore0_colGate_sampF$enq_1__VAL_3 or
WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg)
begin
case (1'b1) // synopsys parallel_case
MUX_adcCore0_colGate_sampF$enq_1__SEL_1:
adcCore0_colGate_sampF$D_IN =
MUX_adcCore0_colGate_sampF$enq_1__VAL_1;
WILL_FIRE_RL_adcCore0_colGate_send_timestamp_mesg:
adcCore0_colGate_sampF$D_IN =
MUX_adcCore0_colGate_sampF$enq_1__VAL_2;
WILL_FIRE_RL_adcCore0_colGate_capture_collect:
adcCore0_colGate_sampF$D_IN =
MUX_adcCore0_colGate_sampF$enq_1__VAL_3;
WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg:
adcCore0_colGate_sampF$D_IN = 39'h3000000000;
default: adcCore0_colGate_sampF$D_IN =
39'h2AAAAAAAAA /* unspecified value */ ;
endcase
end
assign adcCore0_colGate_sampF$ENQ =
WILL_FIRE_RL_adcCore0_colGate_overrun_recovery &&
adcCore0_colGate_ovrRecover == 4'd15 ||
WILL_FIRE_RL_adcCore0_colGate_send_timestamp_mesg ||
WILL_FIRE_RL_adcCore0_colGate_capture_collect ||
WILL_FIRE_RL_adcCore0_colGate_send_sync_mesg ;
assign adcCore0_colGate_sampF$DEQ = adcCore0_sampF_pwEnqueue$whas ;
assign adcCore0_colGate_sampF$CLR = !adcCore0_operateD$dD_OUT ;
// submodule adcCore0_ddrC_ddrV
assign adcCore0_ddrC_ddrV$ddrDataN = adc0_ddn_arg ;
assign adcCore0_ddrC_ddrV$ddrDataP = adc0_ddp_arg ;
assign adcCore0_ddrC_ddrV$psEna = adcCore0_ddrC_psCmdReg[0] ;
assign adcCore0_ddrC_ddrV$psInc = adcCore0_ddrC_psCmdReg[1] ;
// submodule adcCore0_maxBurstLengthR
assign adcCore0_maxBurstLengthR$sD_IN = maxMesgLength[17:2] ;
assign adcCore0_maxBurstLengthR$sEN = adcCore0_maxBurstLengthR$sRDY ;
// submodule adcCore0_operateD
assign adcCore0_operateD$sD_IN = adcCore0_operateDReg ;
assign adcCore0_operateD$sEN =
adcCore0_operateD$sRDY && adcCore0_acquireD$sRDY &&
adcCore0_averageD$sRDY ;
// submodule adcCore0_reqF
assign adcCore0_reqF$D_IN =
MUX_adcCore0_reqF$enq_1__SEL_1 ?
MUX_adcCore0_reqF$enq_1__VAL_1 :
MUX_adcCore0_reqF$enq_1__VAL_2 ;
assign adcCore0_reqF$ENQ =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h28 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b01) ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b01 ;
assign adcCore0_reqF$DEQ =
WILL_FIRE_RL_adcCore0_advance_spi_request &&
(!adcCore0_reqF$D_OUT[16] || adcCore0_readMode) &&
(adcCore0_reqF$D_OUT[16] || !adcCore0_readMode) ;
assign adcCore0_reqF$CLR = 1'b0 ;
// submodule adcCore0_sampCC
assign adcCore0_sampCC$sD_IN = adcCore0_samp ;
assign adcCore0_sampCC$sEN = adcCore0_sampCC$sRDY ;
// submodule adcCore0_sampF_memory
assign adcCore0_sampF_memory$ADDRA =
{ adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2157,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2142,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2155,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2143,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2144,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2148,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2145,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2146,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2156,
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2156 ^
adcCore0_sampF_rWrPtr_rsCounter[0] } ;
assign adcCore0_sampF_memory$ADDRB =
adcCore0_sampF_pwDequeue$whas ? x__h44308[9:0] : x2__h44277 ;
assign adcCore0_sampF_memory$DIA =
{ adcCore0_sampF_pwEnqueue$whas ?
adcCore0_colGate_sampF$D_OUT[38:37] :
2'd0,
adcCore0_sampF_pwEnqueue$whas &&
adcCore0_colGate_sampF$D_OUT[36],
adcCore0_sampF_pwEnqueue$whas ?
adcCore0_colGate_sampF$D_OUT[35:0] :
36'd0 } ;
assign adcCore0_sampF_memory$DIB = 39'h2AAAAAAAAA /* unspecified value */ ;
assign adcCore0_sampF_memory$WEA = adcCore0_sampF_pwEnqueue$whas ;
assign adcCore0_sampF_memory$WEB = 1'd0 ;
assign adcCore0_sampF_memory$ENA = 1'd1 ;
assign adcCore0_sampF_memory$ENB = 1'd1 ;
// submodule adcCore0_statsCC
assign adcCore0_statsCC$sD_IN =
{ adcCore0_colGate_dropCount,
adcCore0_colGate_sampCount,
adcCore0_colGate_dwellStarts,
adcCore0_colGate_dwellFails } ;
assign adcCore0_statsCC$sEN = adcCore0_statsCC$sRDY ;
// submodule adcCore1_acquireD
assign adcCore1_acquireD$sD_IN = adcCore1_acquireDReg ;
assign adcCore1_acquireD$sEN =
adcCore1_operateD$sRDY && adcCore1_acquireD$sRDY &&
adcCore1_averageD$sRDY ;
// submodule adcCore1_averageD
assign adcCore1_averageD$sD_IN = adcCore1_averageDReg ;
assign adcCore1_averageD$sEN =
adcCore1_operateD$sRDY && adcCore1_acquireD$sRDY &&
adcCore1_averageD$sRDY ;
// submodule adcCore1_colGate_sampF
always@(MUX_adcCore1_colGate_sampF$enq_1__SEL_1 or
MUX_adcCore1_colGate_sampF$enq_1__VAL_1 or
WILL_FIRE_RL_adcCore1_colGate_send_timestamp_mesg or
MUX_adcCore1_colGate_sampF$enq_1__VAL_2 or
WILL_FIRE_RL_adcCore1_colGate_capture_collect or
MUX_adcCore1_colGate_sampF$enq_1__VAL_3 or
WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg)
begin
case (1'b1) // synopsys parallel_case
MUX_adcCore1_colGate_sampF$enq_1__SEL_1:
adcCore1_colGate_sampF$D_IN =
MUX_adcCore1_colGate_sampF$enq_1__VAL_1;
WILL_FIRE_RL_adcCore1_colGate_send_timestamp_mesg:
adcCore1_colGate_sampF$D_IN =
MUX_adcCore1_colGate_sampF$enq_1__VAL_2;
WILL_FIRE_RL_adcCore1_colGate_capture_collect:
adcCore1_colGate_sampF$D_IN =
MUX_adcCore1_colGate_sampF$enq_1__VAL_3;
WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg:
adcCore1_colGate_sampF$D_IN = 39'h3000000000;
default: adcCore1_colGate_sampF$D_IN =
39'h2AAAAAAAAA /* unspecified value */ ;
endcase
end
assign adcCore1_colGate_sampF$ENQ =
WILL_FIRE_RL_adcCore1_colGate_overrun_recovery &&
adcCore1_colGate_ovrRecover == 4'd15 ||
WILL_FIRE_RL_adcCore1_colGate_send_timestamp_mesg ||
WILL_FIRE_RL_adcCore1_colGate_capture_collect ||
WILL_FIRE_RL_adcCore1_colGate_send_sync_mesg ;
assign adcCore1_colGate_sampF$DEQ = adcCore1_sampF_pwEnqueue$whas ;
assign adcCore1_colGate_sampF$CLR = !adcCore1_operateD$dD_OUT ;
// submodule adcCore1_ddrC_ddrV
assign adcCore1_ddrC_ddrV$ddrDataN = adc1_ddn_arg ;
assign adcCore1_ddrC_ddrV$ddrDataP = adc1_ddp_arg ;
assign adcCore1_ddrC_ddrV$psEna = adcCore1_ddrC_psCmdReg[0] ;
assign adcCore1_ddrC_ddrV$psInc = adcCore1_ddrC_psCmdReg[1] ;
// submodule adcCore1_maxBurstLengthR
assign adcCore1_maxBurstLengthR$sD_IN = 16'h0 ;
assign adcCore1_maxBurstLengthR$sEN = 1'b0 ;
// submodule adcCore1_operateD
assign adcCore1_operateD$sD_IN = adcCore1_operateDReg ;
assign adcCore1_operateD$sEN =
adcCore1_operateD$sRDY && adcCore1_acquireD$sRDY &&
adcCore1_averageD$sRDY ;
// submodule adcCore1_reqF
assign adcCore1_reqF$D_IN =
MUX_adcCore1_reqF$enq_1__SEL_1 ?
MUX_adcCore0_reqF$enq_1__VAL_1 :
MUX_adcCore0_reqF$enq_1__VAL_2 ;
assign adcCore1_reqF$ENQ =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h2C ||
wci_wslv_reqF$D_OUT[43:42] == 2'b10) ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b10 ;
assign adcCore1_reqF$DEQ =
WILL_FIRE_RL_adcCore1_advance_spi_request &&
(!adcCore1_reqF$D_OUT[16] || adcCore1_readMode) &&
(adcCore1_reqF$D_OUT[16] || !adcCore1_readMode) ;
assign adcCore1_reqF$CLR = 1'b0 ;
// submodule adcCore1_sampCC
assign adcCore1_sampCC$sD_IN = adcCore1_samp ;
assign adcCore1_sampCC$sEN = adcCore1_sampCC$sRDY ;
// submodule adcCore1_sampF_memory
assign adcCore1_sampF_memory$ADDRA =
{ adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2180,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2179,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2201,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2181,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2182,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2183,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2184,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2186,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2185,
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2185 ^
adcCore1_sampF_rWrPtr_rsCounter[0] } ;
assign adcCore1_sampF_memory$ADDRB = x2__h89987 ;
assign adcCore1_sampF_memory$DIA =
{ adcCore1_sampF_pwEnqueue$whas ?
adcCore1_colGate_sampF$D_OUT[38:37] :
2'd0,
adcCore1_sampF_pwEnqueue$whas &&
adcCore1_colGate_sampF$D_OUT[36],
adcCore1_sampF_pwEnqueue$whas ?
adcCore1_colGate_sampF$D_OUT[35:0] :
36'd0 } ;
assign adcCore1_sampF_memory$DIB = 39'h2AAAAAAAAA /* unspecified value */ ;
assign adcCore1_sampF_memory$WEA = adcCore1_sampF_pwEnqueue$whas ;
assign adcCore1_sampF_memory$WEB = 1'd0 ;
assign adcCore1_sampF_memory$ENA = 1'd1 ;
assign adcCore1_sampF_memory$ENB = 1'd1 ;
// submodule adcCore1_statsCC
assign adcCore1_statsCC$sD_IN =
{ adcCore1_colGate_dropCount,
adcCore1_colGate_sampCount,
adcCore1_colGate_dwellStarts,
adcCore1_colGate_dwellFails } ;
assign adcCore1_statsCC$sEN = adcCore1_statsCC$sRDY ;
// submodule adcIdcRdyBit
assign adcIdcRdyBit$sD_IN = adcIdc$RDY ;
assign adcIdcRdyBit$sEN = 1'd1 ;
// submodule adcIdc_idcRst
assign adcIdc_idcRst$ASSERT_IN =
adcIdc_preResetCount == 4'hF && adcIdc_doResetCount != 4'hF ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ;
assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ;
assign wci_wslv_reqF$CLR = 1'b0 ;
// remaining internal signals
assign IF_adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_ETC___d2461 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_XO_ETC___d2328 ?
IF_adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_ETC___d2462 :
32'd0 ;
assign IF_adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_ETC___d2462 =
(adcCore0_sampF_rRdPtr_rsCounter[0] ||
adcCore0_sampF_rRdPtr_rsCounter[1] ||
adcCore0_sampF_rRdPtr_rsCounter[2] ||
adcCore0_sampF_rRdPtr_rsCounter[3] ||
adcCore0_sampF_rRdPtr_rsCounter[4] ||
adcCore0_sampF_rRdPtr_rsCounter[5] ||
adcCore0_sampF_rRdPtr_rsCounter[6] ||
adcCore0_sampF_rRdPtr_rsCounter[7] ||
adcCore0_sampF_rRdPtr_rsCounter[8] ||
adcCore0_sampF_rRdPtr_rsCounter[9]) ?
(adcCore0_sampF_rRdPtr_rsCounter[0] ?
32'd1 :
(adcCore0_sampF_rRdPtr_rsCounter[1] ?
32'd2 :
(adcCore0_sampF_rRdPtr_rsCounter[2] ?
32'd3 :
(adcCore0_sampF_rRdPtr_rsCounter[3] ?
32'd4 :
(adcCore0_sampF_rRdPtr_rsCounter[4] ?
32'd5 :
(adcCore0_sampF_rRdPtr_rsCounter[5] ?
32'd6 :
(adcCore0_sampF_rRdPtr_rsCounter[6] ?
32'd7 :
(adcCore0_sampF_rRdPtr_rsCounter[7] ?
32'd8 :
(adcCore0_sampF_rRdPtr_rsCounter[8] ?
32'd9 :
(adcCore0_sampF_rRdPtr_rsCounter[9] ?
32'd10 :
(adcCore0_sampF_rRdPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_ETC___d2458 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_XO_ETC___d2327 ?
IF_adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_ETC___d2459 :
32'd0 ;
assign IF_adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_ETC___d2459 =
(adcCore0_sampF_rWrPtr_rsCounter[0] ||
adcCore0_sampF_rWrPtr_rsCounter[1] ||
adcCore0_sampF_rWrPtr_rsCounter[2] ||
adcCore0_sampF_rWrPtr_rsCounter[3] ||
adcCore0_sampF_rWrPtr_rsCounter[4] ||
adcCore0_sampF_rWrPtr_rsCounter[5] ||
adcCore0_sampF_rWrPtr_rsCounter[6] ||
adcCore0_sampF_rWrPtr_rsCounter[7] ||
adcCore0_sampF_rWrPtr_rsCounter[8] ||
adcCore0_sampF_rWrPtr_rsCounter[9]) ?
(adcCore0_sampF_rWrPtr_rsCounter[0] ?
32'd1 :
(adcCore0_sampF_rWrPtr_rsCounter[1] ?
32'd2 :
(adcCore0_sampF_rWrPtr_rsCounter[2] ?
32'd3 :
(adcCore0_sampF_rWrPtr_rsCounter[3] ?
32'd4 :
(adcCore0_sampF_rWrPtr_rsCounter[4] ?
32'd5 :
(adcCore0_sampF_rWrPtr_rsCounter[5] ?
32'd6 :
(adcCore0_sampF_rWrPtr_rsCounter[6] ?
32'd7 :
(adcCore0_sampF_rWrPtr_rsCounter[7] ?
32'd8 :
(adcCore0_sampF_rWrPtr_rsCounter[8] ?
32'd9 :
(adcCore0_sampF_rWrPtr_rsCounter[9] ?
32'd10 :
(adcCore0_sampF_rWrPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_3_ETC___d2467 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_344__ETC___d2338 ?
IF_adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_3_ETC___d2468 :
32'd0 ;
assign IF_adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_3_ETC___d2468 =
(adcCore1_sampF_rWrPtr_rsCounter[0] ||
adcCore1_sampF_rWrPtr_rsCounter[1] ||
adcCore1_sampF_rWrPtr_rsCounter[2] ||
adcCore1_sampF_rWrPtr_rsCounter[3] ||
adcCore1_sampF_rWrPtr_rsCounter[4] ||
adcCore1_sampF_rWrPtr_rsCounter[5] ||
adcCore1_sampF_rWrPtr_rsCounter[6] ||
adcCore1_sampF_rWrPtr_rsCounter[7] ||
adcCore1_sampF_rWrPtr_rsCounter[8] ||
adcCore1_sampF_rWrPtr_rsCounter[9]) ?
(adcCore1_sampF_rWrPtr_rsCounter[0] ?
32'd1 :
(adcCore1_sampF_rWrPtr_rsCounter[1] ?
32'd2 :
(adcCore1_sampF_rWrPtr_rsCounter[2] ?
32'd3 :
(adcCore1_sampF_rWrPtr_rsCounter[3] ?
32'd4 :
(adcCore1_sampF_rWrPtr_rsCounter[4] ?
32'd5 :
(adcCore1_sampF_rWrPtr_rsCounter[5] ?
32'd6 :
(adcCore1_sampF_rWrPtr_rsCounter[6] ?
32'd7 :
(adcCore1_sampF_rWrPtr_rsCounter[7] ?
32'd8 :
(adcCore1_sampF_rWrPtr_rsCounter[8] ?
32'd9 :
(adcCore1_sampF_rWrPtr_rsCounter[9] ?
32'd10 :
(adcCore1_sampF_rWrPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d2454 =
(fcAdc_grayCounter_rsCounter[0] ||
fcAdc_grayCounter_rsCounter[1] ||
fcAdc_grayCounter_rsCounter[2] ||
fcAdc_grayCounter_rsCounter[3] ||
fcAdc_grayCounter_rsCounter[4] ||
fcAdc_grayCounter_rsCounter[5] ||
fcAdc_grayCounter_rsCounter[6] ||
fcAdc_grayCounter_rsCounter[7] ||
fcAdc_grayCounter_rsCounter[8] ||
fcAdc_grayCounter_rsCounter[9] ||
fcAdc_grayCounter_rsCounter[10] ||
fcAdc_grayCounter_rsCounter[11] ||
fcAdc_grayCounter_rsCounter[12] ||
fcAdc_grayCounter_rsCounter[13] ||
fcAdc_grayCounter_rsCounter[14] ||
fcAdc_grayCounter_rsCounter[15] ||
fcAdc_grayCounter_rsCounter[16]) ?
(fcAdc_grayCounter_rsCounter[0] ?
32'd1 :
(fcAdc_grayCounter_rsCounter[1] ?
32'd2 :
(fcAdc_grayCounter_rsCounter[2] ?
32'd3 :
(fcAdc_grayCounter_rsCounter[3] ?
32'd4 :
(fcAdc_grayCounter_rsCounter[4] ?
32'd5 :
(fcAdc_grayCounter_rsCounter[5] ?
32'd6 :
(fcAdc_grayCounter_rsCounter[6] ?
32'd7 :
(fcAdc_grayCounter_rsCounter[7] ?
32'd8 :
(fcAdc_grayCounter_rsCounter[8] ?
32'd9 :
(fcAdc_grayCounter_rsCounter[9] ?
32'd10 :
(fcAdc_grayCounter_rsCounter[10] ?
32'd11 :
(fcAdc_grayCounter_rsCounter[11] ?
32'd12 :
(fcAdc_grayCounter_rsCounter[12] ?
32'd13 :
(fcAdc_grayCounter_rsCounter[13] ?
32'd14 :
(fcAdc_grayCounter_rsCounter[14] ?
32'd15 :
(fcAdc_grayCounter_rsCounter[15] ?
32'd16 :
(fcAdc_grayCounter_rsCounter[16] ?
32'd17 :
(fcAdc_grayCounter_rsCounter[17] ?
32'd18 :
32'd19)))))))))))))))))) :
32'd17 ;
assign IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d2455 =
fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d2326 ?
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d2454 :
32'd0 ;
assign IF_spiClk_spiI_iPos_89_EQ_15_90_THEN_NOT_spiCl_ETC___d401 =
(spiClk_spiI_iPos == 4'd15) ?
NOT_spiClk_spiI_reqF_head_wrapped__read__39_EQ_ETC___d382 &&
!spiClk_spiI_reqF_dInReset$VAL :
spiClk_spiI_iPos_89_EQ_14_92_OR_spiClk_spiI_iP_ETC___d400 ;
assign IF_wci_wslv_reqF_first__5_BITS_43_TO_42_943_EQ_ETC___d1970 =
(wci_wslv_reqF$D_OUT[43:42] == 2'b0) ?
wci_wslv_reqF$D_OUT[39:32] == 8'h08 ||
wci_wslv_reqF$D_OUT[39:32] == 8'h0C ||
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_NOT_wci_ETC__q3 :
IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d2447 ;
assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1968 =
(wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[43:42] == 2'b10) ?
adcCore1_reqF$FULL_N :
!wci_wslv_reqF$EMPTY_N ||
wci_wslv_reqF$D_OUT[43:42] != 2'b11 ||
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 ;
assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d2447 =
(wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[43:42] == 2'b01) ?
adcCore0_reqF$FULL_N :
IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1968 ;
assign NOT_adcCore0_sampF_rRdPtr_rsCounter_59_EQ_adcC_ETC___d1909 =
adcCore0_sampF_rRdPtr_rsCounter !=
adcCore0_sampF_rWrPtr_rdCounter ;
assign NOT_adcCore0_spiI_reqF_head_wrapped__read__82__ETC___d1025 =
adcCore0_spiI_reqF_head_wrapped !=
adcCore0_spiI_reqF_tail_wrapped ;
assign NOT_adcCore1_spiI_reqF_head_wrapped__read__629_ETC___d1672 =
adcCore1_spiI_reqF_head_wrapped !=
adcCore1_spiI_reqF_tail_wrapped ;
assign NOT_spiClk_spiI_reqF_head_wrapped__read__39_EQ_ETC___d382 =
spiClk_spiI_reqF_head_wrapped != spiClk_spiI_reqF_tail_wrapped ;
assign adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d590 =
adcCore0_operateD$dD_OUT && adcCore0_colGate_timeMesg == 3'd0 &&
adcCore0_acquireD$dD_OUT &&
adcCore0_colGate_collectD ;
assign adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d601 =
adcCore0_colGate_operatePW_whas__35_AND_adcCor_ETC___d590 &&
adcCore0_colGate_syncMesg == 2'd0 &&
adcCore0_colGate_ovrRecover == 4'd0 &&
(!adcCore0_averageD$dD_OUT ||
adcCore0_colGate_avgPhase == 2'd0) ;
assign adcCore0_colGate_sampF_RDY_first__04_AND_NOT_a_ETC___d961 =
adcCore0_colGate_sampF$EMPTY_N &&
adcCore0_sampF_rWrPtr_rsCounter !=
{ adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[10],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[10] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[9],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[9] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[8],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[8] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[7],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[7] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[6],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[6] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[5],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[5] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[4],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[4] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[3],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[3] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[2],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[2] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[1],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[1] ^
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176[0] } ;
assign adcCore0_colGate_uprollCnt_04_EQ_adcCore0_colG_ETC___d2230 =
adcCore0_colGate_uprollCnt ==
adcCore0_maxBurstLengthR$dD_OUT - 16'd1 ;
assign adcCore0_iseqFsm_abort_whas__080_AND_adcCore0__ETC___d1152 =
(adcCore0_iseqFsm_state_mkFSMstate == 4'd0 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd10) &&
(!adcCore0_iseqFsm_start_reg_1 || adcCore0_iseqFsm_state_fired) ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_C_ETC___d2176 =
x_dReadBin__h42694 + 11'd512 ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2169 =
adcCore0_sampF_rRdPtr_rdCounter[10] ^
adcCore0_sampF_rRdPtr_rdCounter[9] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2170 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2169 ^
adcCore0_sampF_rRdPtr_rdCounter[8] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2171 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2170 ^
adcCore0_sampF_rRdPtr_rdCounter[7] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2172 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2171 ^
adcCore0_sampF_rRdPtr_rdCounter[6] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2173 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2172 ^
adcCore0_sampF_rRdPtr_rdCounter[5] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2174 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2200 ^
adcCore0_sampF_rRdPtr_rdCounter[2] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2175 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2173 ^
adcCore0_sampF_rRdPtr_rdCounter[4] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2178 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2174 ^
adcCore0_sampF_rRdPtr_rdCounter[1] ;
assign adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2200 =
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2175 ^
adcCore0_sampF_rRdPtr_rdCounter[3] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_XO_ETC___d2328 =
z__h41868 ^ adcCore0_sampF_rRdPtr_rsCounter[10] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2150 =
adcCore0_sampF_rRdPtr_rsCounter[10] ^
adcCore0_sampF_rRdPtr_rsCounter[9] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2161 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2150 ^
adcCore0_sampF_rRdPtr_rsCounter[8] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2162 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2161 ^
adcCore0_sampF_rRdPtr_rsCounter[7] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2163 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2162 ^
adcCore0_sampF_rRdPtr_rsCounter[6] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2164 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2163 ^
adcCore0_sampF_rRdPtr_rsCounter[5] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2165 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2164 ^
adcCore0_sampF_rRdPtr_rsCounter[4] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2166 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2165 ^
adcCore0_sampF_rRdPtr_rsCounter[3] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2167 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2166 ^
adcCore0_sampF_rRdPtr_rsCounter[2] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2168 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2167 ^
adcCore0_sampF_rRdPtr_rsCounter[1] ;
assign adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2231 =
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2168 ^
adcCore0_sampF_rRdPtr_rsCounter[0] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_XO_ETC___d2327 =
z__h39566 ^ adcCore0_sampF_rWrPtr_rsCounter[10] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2142 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2157 ^
adcCore0_sampF_rWrPtr_rsCounter[8] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2143 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2155 ^
adcCore0_sampF_rWrPtr_rsCounter[6] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2144 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2143 ^
adcCore0_sampF_rWrPtr_rsCounter[5] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2145 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2148 ^
adcCore0_sampF_rWrPtr_rsCounter[3] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2146 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2145 ^
adcCore0_sampF_rWrPtr_rsCounter[2] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2148 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2144 ^
adcCore0_sampF_rWrPtr_rsCounter[4] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2155 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2142 ^
adcCore0_sampF_rWrPtr_rsCounter[7] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2156 =
adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2146 ^
adcCore0_sampF_rWrPtr_rsCounter[1] ;
assign adcCore0_sampF_rWrPtr_rsCounter_90_BIT_10_16_X_ETC___d2157 =
adcCore0_sampF_rWrPtr_rsCounter[10] ^
adcCore0_sampF_rWrPtr_rsCounter[9] ;
assign adcCore0_spiI_reqF_head_wrapped_crossed__74_EQ_ETC___d1130 =
adcCore0_spiI_reqF_head_wrapped ==
adcCore0_spiI_reqF_tail_wrapped &&
!adcCore0_spiI_reqF_sInReset$VAL &&
adcCore0_spiI_cd$PREEDGE ;
assign adcCore0_spiI_reqS_BITS_15_TO_8__q6 = adcCore0_spiI_reqS[15:8] ;
assign adcCore0_spiI_reqS_BITS_7_TO_0__q7 = adcCore0_spiI_reqS[7:0] ;
assign adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1237 =
adcCore1_operateD$dD_OUT && adcCore1_colGate_timeMesg == 3'd0 &&
adcCore1_acquireD$dD_OUT &&
adcCore1_colGate_collectD ;
assign adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1248 =
adcCore1_colGate_operatePW_whas__182_AND_adcCo_ETC___d1237 &&
adcCore1_colGate_syncMesg == 2'd0 &&
adcCore1_colGate_ovrRecover == 4'd0 &&
(!adcCore1_averageD$dD_OUT ||
adcCore1_colGate_avgPhase == 2'd0) ;
assign adcCore1_colGate_sampF_RDY_first__551_AND_NOT__ETC___d1608 =
adcCore1_colGate_sampF$EMPTY_N &&
adcCore1_sampF_rWrPtr_rsCounter !=
{ adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[10],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[10] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[9],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[9] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[8],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[8] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[7],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[7] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[6],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[6] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[5],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[5] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[4],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[4] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[3],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[3] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[2],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[2] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[1],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[1] ^
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216[0] } ;
assign adcCore1_colGate_uprollCnt_251_EQ_adcCore1_col_ETC___d2234 =
adcCore1_colGate_uprollCnt ==
adcCore1_maxBurstLengthR$dD_OUT - 16'd1 ;
assign adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d1799 =
(adcCore1_iseqFsm_state_mkFSMstate == 4'd0 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd10) &&
(!adcCore1_iseqFsm_start_reg_1 || adcCore1_iseqFsm_state_fired) ;
assign adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d2103 =
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d1799 &&
!adcCore1_iseqFsm_start_reg &&
spiClk_iseqFsm_abort_whas__53_AND_spiClk_iseqF_ETC___d513 &&
!spiClk_iseqFsm_start_reg &&
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2194 =
adcCore1_sampF_rRdPtr_rdCounter[10] ^
adcCore1_sampF_rRdPtr_rdCounter[9] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2195 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2194 ^
adcCore1_sampF_rRdPtr_rdCounter[8] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2196 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2195 ^
adcCore1_sampF_rRdPtr_rdCounter[7] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2197 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2203 ^
adcCore1_sampF_rRdPtr_rdCounter[4] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2198 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2196 ^
adcCore1_sampF_rRdPtr_rdCounter[6] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2203 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2198 ^
adcCore1_sampF_rRdPtr_rdCounter[5] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2204 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2197 ^
adcCore1_sampF_rRdPtr_rdCounter[3] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2205 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2204 ^
adcCore1_sampF_rRdPtr_rdCounter[2] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2215 =
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2205 ^
adcCore1_sampF_rRdPtr_rdCounter[1] ;
assign adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2216 =
x_dReadBin__h88404 + 11'd512 ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2187 =
adcCore1_sampF_rRdPtr_rsCounter[10] ^
adcCore1_sampF_rRdPtr_rsCounter[9] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2188 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2187 ^
adcCore1_sampF_rRdPtr_rsCounter[8] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2189 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2188 ^
adcCore1_sampF_rRdPtr_rsCounter[7] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2190 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2189 ^
adcCore1_sampF_rRdPtr_rsCounter[6] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2191 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2190 ^
adcCore1_sampF_rRdPtr_rsCounter[5] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2192 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2191 ^
adcCore1_sampF_rRdPtr_rsCounter[4] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2193 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2202 ^
adcCore1_sampF_rRdPtr_rsCounter[2] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2199 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2193 ^
adcCore1_sampF_rRdPtr_rsCounter[1] ;
assign adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2202 =
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2192 ^
adcCore1_sampF_rRdPtr_rsCounter[3] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_344__ETC___d2338 =
z__h85276 ^ adcCore1_sampF_rWrPtr_rsCounter[10] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2179 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2180 ^
adcCore1_sampF_rWrPtr_rsCounter[8] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2180 =
adcCore1_sampF_rWrPtr_rsCounter[10] ^
adcCore1_sampF_rWrPtr_rsCounter[9] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2181 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2201 ^
adcCore1_sampF_rWrPtr_rsCounter[6] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2182 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2181 ^
adcCore1_sampF_rWrPtr_rsCounter[5] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2183 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2182 ^
adcCore1_sampF_rWrPtr_rsCounter[4] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2184 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2183 ^
adcCore1_sampF_rWrPtr_rsCounter[3] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2185 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2186 ^
adcCore1_sampF_rWrPtr_rsCounter[1] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2186 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2184 ^
adcCore1_sampF_rWrPtr_rsCounter[2] ;
assign adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2201 =
adcCore1_sampF_rWrPtr_rsCounter_337_BIT_10_363_ETC___d2179 ^
adcCore1_sampF_rWrPtr_rsCounter[7] ;
assign adcCore1_spiI_reqF_head_wrapped_crossed__621_E_ETC___d1777 =
adcCore1_spiI_reqF_head_wrapped ==
adcCore1_spiI_reqF_tail_wrapped &&
!adcCore1_spiI_reqF_sInReset$VAL &&
adcCore1_spiI_cd$PREEDGE ;
assign adcCore1_spiI_reqS_BITS_15_TO_8__q9 = adcCore1_spiI_reqS[15:8] ;
assign adcCore1_spiI_reqS_BITS_7_TO_0__q8 = adcCore1_spiI_reqS[7:0] ;
assign adcStatusLs__h130971 =
{ 26'd0,
adcIdcRdyBit$dD_OUT,
splitReadInFlight,
initOpInFlight,
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d1799 &&
!adcCore1_iseqFsm_start_reg,
adcCore0_iseqFsm_abort_whas__080_AND_adcCore0__ETC___d1152 &&
!adcCore0_iseqFsm_start_reg,
spiClk_iseqFsm_abort_whas__53_AND_spiClk_iseqF_ETC___d513 &&
!spiClk_iseqFsm_start_reg } ;
assign avgDataBW__h35898 =
{ adcCore0_colGate_avgOdd[17:2],
adcCore0_colGate_avgEven[17:2] } ;
assign avgDataBW__h81608 =
{ adcCore1_colGate_avgOdd[17:2],
adcCore1_colGate_avgEven[17:2] } ;
assign d_data__h35985 =
adcCore0_averageD$dD_OUT ? avgDataBW__h35898 : adcCore0_samp ;
assign d_data__h81695 =
adcCore1_averageD$dD_OUT ? avgDataBW__h81608 : adcCore1_samp ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2132 =
fcAdc_grayCounter_rdCounter[17] ^
fcAdc_grayCounter_rdCounter[16] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2133 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2151 ^
fcAdc_grayCounter_rdCounter[14] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2134 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2133 ^
fcAdc_grayCounter_rdCounter[13] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2135 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2149 ^
fcAdc_grayCounter_rdCounter[11] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2136 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2135 ^
fcAdc_grayCounter_rdCounter[10] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2137 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2136 ^
fcAdc_grayCounter_rdCounter[9] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2138 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2154 ^
fcAdc_grayCounter_rdCounter[5] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2139 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2138 ^
fcAdc_grayCounter_rdCounter[4] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2140 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2147 ^
fcAdc_grayCounter_rdCounter[1] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2141 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2139 ^
fcAdc_grayCounter_rdCounter[3] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2147 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2141 ^
fcAdc_grayCounter_rdCounter[2] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2149 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2134 ^
fcAdc_grayCounter_rdCounter[12] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2151 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2132 ^
fcAdc_grayCounter_rdCounter[15] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2152 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2153 ^
fcAdc_grayCounter_rdCounter[7] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2153 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2137 ^
fcAdc_grayCounter_rdCounter[8] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2154 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d2152 ^
fcAdc_grayCounter_rdCounter[6] ;
assign fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d2326 =
z__h7636 ^ fcAdc_grayCounter_rsCounter[17] ;
assign initOpInFlight_041_AND_adcCore0_iseqFsm_abort__ETC___d2110 =
initOpInFlight &&
adcCore0_iseqFsm_abort_whas__080_AND_adcCore0__ETC___d1152 &&
!adcCore0_iseqFsm_start_reg &&
adcCore1_iseqFsm_abort_whas__727_AND_adcCore1__ETC___d1799 &&
!adcCore1_iseqFsm_start_reg ;
assign rdat__h131371 =
(wci_wslv_reqF$D_OUT[43:42] == 2'b0) ?
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 :
32'd0 ;
assign rdat__h131450 = { 24'd0, wsiM_statusR } ;
assign rdat__h131531 = { 14'd0, fcAdc_frequency } ;
assign rdat__h131557 = { 24'd0, spiResp } ;
assign spiClk_iseqFsm_abort_whas__53_AND_spiClk_iseqF_ETC___d513 =
(spiClk_iseqFsm_state_mkFSMstate == 4'd0 ||
spiClk_iseqFsm_state_mkFSMstate == 4'd7) &&
(!spiClk_iseqFsm_start_reg_1 || spiClk_iseqFsm_state_fired) ;
assign spiClk_spiI_iPos_89_EQ_14_92_OR_spiClk_spiI_iP_ETC___d400 =
spiClk_spiI_iPos == 4'd14 || spiClk_spiI_iPos == 4'd13 ||
!spiClk_spiI_iPos_89_ULT_7___d2219 &&
spiClk_spiI_iPos_89_ULE_12___d2220 ||
NOT_spiClk_spiI_reqF_head_wrapped__read__39_EQ_ETC___d382 &&
!spiClk_spiI_reqF_dInReset$VAL ;
assign spiClk_spiI_iPos_89_ULE_12___d2220 = spiClk_spiI_iPos <= 4'd12 ;
assign spiClk_spiI_iPos_89_ULT_7___d2219 = spiClk_spiI_iPos < 4'd7 ;
assign spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 =
spiClk_spiI_reqF_head_wrapped == spiClk_spiI_reqF_tail_wrapped &&
!spiClk_spiI_reqF_sInReset$VAL &&
spiClk_spiI_cd$PREEDGE ;
assign spiClk_spiI_reqS_BITS_15_TO_8__q2 = spiClk_spiI_reqS[15:8] ;
assign spiClk_spiI_reqS_BITS_7_TO_0__q10 = spiClk_spiI_reqS[7:0] ;
assign wti_nowReq_BITS_63_TO_0__q1 = wti_nowReq[63:0] ;
assign x2__h44277 =
{ adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2150,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2161,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2162,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2163,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2164,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2165,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2166,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2167,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2168,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2231 } ;
assign x2__h89987 =
{ adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2187,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2188,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2189,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2190,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2191,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2192,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2202,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2193,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2199,
adcCore1_sampF_rRdPtr_rsCounter_406_BIT_10_432_ETC___d2199 ^
adcCore1_sampF_rRdPtr_rsCounter[0] } ;
assign x__h17146 =
spiClk_spiI_reqS_BITS_15_TO_8__q2[spiClk_spiI_iPos[2:0]] ;
assign x__h36250 = x__h36260 + y__h36411 ;
assign x__h36260 = adcCore0_colGate_avgEven + y__h36413 ;
assign x__h36326 = y__h36413 + y__h36411 ;
assign x__h36400 = x__h36410 + y__h36411 ;
assign x__h36410 = adcCore0_colGate_avgOdd + y__h36413 ;
assign x__h38579 =
11'd1 <<
IF_adcCore0_sampF_rWrPtr_rsCounter_90_BIT_0_97_ETC___d2458 ;
assign x__h40881 =
11'd1 <<
IF_adcCore0_sampF_rRdPtr_rsCounter_59_BIT_0_66_ETC___d2461 ;
assign x__h44308 = x_sReadBin__h42691 + 11'd1 ;
assign x__h7511 =
18'd1 <<
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d2455 ;
assign x__h81960 = x__h81970 + y__h82121 ;
assign x__h81970 = adcCore1_colGate_avgEven + y__h82123 ;
assign x__h82036 = y__h82123 + y__h82121 ;
assign x__h82110 = x__h82120 + y__h82121 ;
assign x__h82120 = adcCore1_colGate_avgOdd + y__h82123 ;
assign x__h84289 =
11'd1 <<
IF_adcCore1_sampF_rWrPtr_rsCounter_337_BIT_0_3_ETC___d2467 ;
assign x_burstLength__h128706 =
adcCore0_sampF_memory$DOB[36] ? 12'd1 : 12'd4095 ;
assign x_dReadBin__h42694 =
{ adcCore0_sampF_rRdPtr_rdCounter[10],
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2169,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2170,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2171,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2172,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2173,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2175,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2200,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2174,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2178,
adcCore0_sampF_rRdPtr_rdCounter_05_BIT_10_06_X_ETC___d2178 ^
adcCore0_sampF_rRdPtr_rdCounter[0] } ;
assign x_dReadBin__h88404 =
{ adcCore1_sampF_rRdPtr_rdCounter[10],
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2194,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2195,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2196,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2198,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2203,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2197,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2204,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2205,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2215,
adcCore1_sampF_rRdPtr_rdCounter_552_BIT_10_553_ETC___d2215 ^
adcCore1_sampF_rRdPtr_rdCounter[0] } ;
assign x_sReadBin__h42691 =
{ adcCore0_sampF_rRdPtr_rsCounter[10],
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2150,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2161,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2162,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2163,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2164,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2165,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2166,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2167,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2168,
adcCore0_sampF_rRdPtr_rsCounter_59_BIT_10_85_X_ETC___d2231 } ;
assign y__h36411 = { 2'd0, adcCore0_samp[15:0] } ;
assign y__h36413 = { 2'd0, adcCore0_samp[31:16] } ;
assign y__h39466 = ~x__h38579 ;
assign y__h41768 = ~x__h40881 ;
assign y__h82121 = { 2'd0, adcCore1_samp[15:0] } ;
assign y__h82123 = { 2'd0, adcCore1_samp[31:16] } ;
assign y__h85176 = ~x__h84289 ;
assign y__h8916 = ~x__h7511 ;
assign z__h39510 =
adcCore0_sampF_rWrPtr_rsCounter[0] ^
adcCore0_sampF_rWrPtr_rsCounter[1] ;
assign z__h39517 = z__h39510 ^ adcCore0_sampF_rWrPtr_rsCounter[2] ;
assign z__h39524 = z__h39517 ^ adcCore0_sampF_rWrPtr_rsCounter[3] ;
assign z__h39531 = z__h39524 ^ adcCore0_sampF_rWrPtr_rsCounter[4] ;
assign z__h39538 = z__h39531 ^ adcCore0_sampF_rWrPtr_rsCounter[5] ;
assign z__h39545 = z__h39538 ^ adcCore0_sampF_rWrPtr_rsCounter[6] ;
assign z__h39552 = z__h39545 ^ adcCore0_sampF_rWrPtr_rsCounter[7] ;
assign z__h39559 = z__h39552 ^ adcCore0_sampF_rWrPtr_rsCounter[8] ;
assign z__h39566 = z__h39559 ^ adcCore0_sampF_rWrPtr_rsCounter[9] ;
assign z__h41812 =
adcCore0_sampF_rRdPtr_rsCounter[0] ^
adcCore0_sampF_rRdPtr_rsCounter[1] ;
assign z__h41819 = z__h41812 ^ adcCore0_sampF_rRdPtr_rsCounter[2] ;
assign z__h41826 = z__h41819 ^ adcCore0_sampF_rRdPtr_rsCounter[3] ;
assign z__h41833 = z__h41826 ^ adcCore0_sampF_rRdPtr_rsCounter[4] ;
assign z__h41840 = z__h41833 ^ adcCore0_sampF_rRdPtr_rsCounter[5] ;
assign z__h41847 = z__h41840 ^ adcCore0_sampF_rRdPtr_rsCounter[6] ;
assign z__h41854 = z__h41847 ^ adcCore0_sampF_rRdPtr_rsCounter[7] ;
assign z__h41861 = z__h41854 ^ adcCore0_sampF_rRdPtr_rsCounter[8] ;
assign z__h41868 = z__h41861 ^ adcCore0_sampF_rRdPtr_rsCounter[9] ;
assign z__h7531 =
fcAdc_grayCounter_rsCounter[0] ^ fcAdc_grayCounter_rsCounter[1] ;
assign z__h7538 = z__h7531 ^ fcAdc_grayCounter_rsCounter[2] ;
assign z__h7545 = z__h7538 ^ fcAdc_grayCounter_rsCounter[3] ;
assign z__h7552 = z__h7545 ^ fcAdc_grayCounter_rsCounter[4] ;
assign z__h7559 = z__h7552 ^ fcAdc_grayCounter_rsCounter[5] ;
assign z__h7566 = z__h7559 ^ fcAdc_grayCounter_rsCounter[6] ;
assign z__h7573 = z__h7566 ^ fcAdc_grayCounter_rsCounter[7] ;
assign z__h7580 = z__h7573 ^ fcAdc_grayCounter_rsCounter[8] ;
assign z__h7587 = z__h7580 ^ fcAdc_grayCounter_rsCounter[9] ;
assign z__h7594 = z__h7587 ^ fcAdc_grayCounter_rsCounter[10] ;
assign z__h7601 = z__h7594 ^ fcAdc_grayCounter_rsCounter[11] ;
assign z__h7608 = z__h7601 ^ fcAdc_grayCounter_rsCounter[12] ;
assign z__h7615 = z__h7608 ^ fcAdc_grayCounter_rsCounter[13] ;
assign z__h7622 = z__h7615 ^ fcAdc_grayCounter_rsCounter[14] ;
assign z__h7629 = z__h7622 ^ fcAdc_grayCounter_rsCounter[15] ;
assign z__h7636 = z__h7629 ^ fcAdc_grayCounter_rsCounter[16] ;
assign z__h85220 =
adcCore1_sampF_rWrPtr_rsCounter[0] ^
adcCore1_sampF_rWrPtr_rsCounter[1] ;
assign z__h85227 = z__h85220 ^ adcCore1_sampF_rWrPtr_rsCounter[2] ;
assign z__h85234 = z__h85227 ^ adcCore1_sampF_rWrPtr_rsCounter[3] ;
assign z__h85241 = z__h85234 ^ adcCore1_sampF_rWrPtr_rsCounter[4] ;
assign z__h85248 = z__h85241 ^ adcCore1_sampF_rWrPtr_rsCounter[5] ;
assign z__h85255 = z__h85248 ^ adcCore1_sampF_rWrPtr_rsCounter[6] ;
assign z__h85262 = z__h85255 ^ adcCore1_sampF_rWrPtr_rsCounter[7] ;
assign z__h85269 = z__h85262 ^ adcCore1_sampF_rWrPtr_rsCounter[8] ;
assign z__h85276 = z__h85269 ^ adcCore1_sampF_rWrPtr_rsCounter[9] ;
always@(adcCore0_colGate_timeMesg or
adcCore0_colGate_dwellFails or
adcCore0_colGate_dwellStarts or
adcCore0_colGate_sampCount or
adcCore0_colGate_dropCount or wti_nowReq_BITS_63_TO_0__q1)
begin
case (adcCore0_colGate_timeMesg)
3'h1: x1_data__h35585 = adcCore0_colGate_dwellStarts;
3'h3: x1_data__h35585 = adcCore0_colGate_sampCount;
3'h4: x1_data__h35585 = adcCore0_colGate_dropCount;
3'h5: x1_data__h35585 = wti_nowReq_BITS_63_TO_0__q1[31:0];
3'h6: x1_data__h35585 = wti_nowReq_BITS_63_TO_0__q1[63:32];
default: x1_data__h35585 = adcCore0_colGate_dwellFails;
endcase
end
always@(adcCore1_colGate_timeMesg or
adcCore1_colGate_dwellFails or
adcCore1_colGate_dwellStarts or
adcCore1_colGate_sampCount or adcCore1_colGate_dropCount)
begin
case (adcCore1_colGate_timeMesg)
3'h1: x1_data__h81295 = adcCore1_colGate_dwellStarts;
3'h3: x1_data__h81295 = adcCore1_colGate_sampCount;
3'h4: x1_data__h81295 = adcCore1_colGate_dropCount;
3'h5, 3'h6: x1_data__h81295 = 32'b0;
default: x1_data__h81295 = adcCore1_colGate_dwellFails;
endcase
end
always@(wci_wslv_reqF$D_OUT or
adcCore1_reqF$FULL_N or
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402 or
adcCore0_reqF$FULL_N)
begin
case (wci_wslv_reqF$D_OUT[39:32])
8'h24:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_NOT_wci_ETC__q3 =
spiClk_spiI_reqF_head_wrapped_crossed__31_EQ_s_ETC___d2402;
8'h28:
CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_NOT_wci_ETC__q3 =
adcCore0_reqF$FULL_N;
default: CASE_wci_wslv_reqFD_OUT_BITS_39_TO_32_NOT_wci_ETC__q3 =
wci_wslv_reqF$D_OUT[39:32] != 8'h2C ||
adcCore1_reqF$FULL_N;
endcase
end
always@(adcCore0_colGate_avgPhase)
begin
case (adcCore0_colGate_avgPhase)
2'd0, 2'd1, 2'd2, 2'd3:
CASE_adcCore0_colGate_avgPhase_0b1_0_1_1_1_2_1_ETC__q4 = 1'd1;
endcase
end
always@(adcCore1_colGate_avgPhase)
begin
case (adcCore1_colGate_avgPhase)
2'd0, 2'd1, 2'd2, 2'd3:
CASE_adcCore1_colGate_avgPhase_0b1_0_1_1_1_2_1_ETC__q5 = 1'd1;
endcase
end
always@(wci_wslv_reqF$D_OUT or
rdat__h131450 or
adcStatusLs__h130971 or
maxMesgLength or
adcControl or
rdat__h131531 or
adcCore0_statsCC$dD_OUT or
adcCore0_sampCC$dD_OUT or
adcCore1_sampCC$dD_OUT or
rdat__h131557 or
mesgCount or
lastOverflowMesg or wsiM_extStatusW$wget or overflowCountD)
begin
case (wci_wslv_reqF$D_OUT[39:32])
8'h0:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
rdat__h131450;
8'h04:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcStatusLs__h130971;
8'h08:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
maxMesgLength;
8'h0C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcControl;
8'h14:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
rdat__h131531;
8'h18:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcCore0_statsCC$dD_OUT[95:64];
8'h1C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcCore0_sampCC$dD_OUT;
8'h20:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcCore1_sampCC$dD_OUT;
8'h30:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
rdat__h131557;
8'h34:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
mesgCount;
8'h3C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcCore0_statsCC$dD_OUT[63:32];
8'h40:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcCore0_statsCC$dD_OUT[31:0];
8'h44:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
lastOverflowMesg;
8'h50:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
wsiM_extStatusW$wget[95:64];
8'h54:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
wsiM_extStatusW$wget[63:32];
8'h58:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
wsiM_extStatusW$wget[31:0];
8'h5C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
adcCore0_statsCC$dD_OUT[127:96];
8'h60:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
overflowCountD;
default: IF_wci_wslv_reqF_first__5_BITS_39_TO_32_945_EQ_ETC___d2092 =
32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
adcControl <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore0_acquireDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_adcRst <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_averageDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_ddrC_psCmdReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore0_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 13'd1;
adcCore0_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
adcCore0_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
adcCore0_operateDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_readMode <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_acquireDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_adcRst <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_averageDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_ddrC_psCmdReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore1_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 13'd1;
adcCore1_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
adcCore1_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
adcCore1_operateDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_readMode <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
fcAdc_countNow <= `BSV_ASSIGNMENT_DELAY 18'd262143;
fcAdc_countPast <= `BSV_ASSIGNMENT_DELAY 18'd262143;
fcAdc_frequency <= `BSV_ASSIGNMENT_DELAY 18'd262143;
fcAdc_pulseAction <= `BSV_ASSIGNMENT_DELAY 1'd0;
fcAdc_sampleCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
initOpInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
lastOverflowMesg <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
maxMesgLength <= `BSV_ASSIGNMENT_DELAY 32'd1024;
mesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
oneKHz_value <= `BSV_ASSIGNMENT_DELAY 18'd0;
overflowCountD <= `BSV_ASSIGNMENT_DELAY 32'd0;
sFlagState <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_iState <= `BSV_ASSIGNMENT_DELAY 4'd0;
spiClk_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
spiClk_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
spiClk_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiResp <= `BSV_ASSIGNMENT_DELAY 8'd255;
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (adcControl$EN)
adcControl <= `BSV_ASSIGNMENT_DELAY adcControl$D_IN;
if (adcCore0_acquireDReg$EN)
adcCore0_acquireDReg <= `BSV_ASSIGNMENT_DELAY
adcCore0_acquireDReg$D_IN;
if (adcCore0_adcRst$EN)
adcCore0_adcRst <= `BSV_ASSIGNMENT_DELAY adcCore0_adcRst$D_IN;
if (adcCore0_averageDReg$EN)
adcCore0_averageDReg <= `BSV_ASSIGNMENT_DELAY
adcCore0_averageDReg$D_IN;
if (adcCore0_ddrC_psCmdReg$EN)
adcCore0_ddrC_psCmdReg <= `BSV_ASSIGNMENT_DELAY
adcCore0_ddrC_psCmdReg$D_IN;
if (adcCore0_iseqFsm_jj_delay_count$EN)
adcCore0_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY
adcCore0_iseqFsm_jj_delay_count$D_IN;
if (adcCore0_iseqFsm_start_reg$EN)
adcCore0_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY
adcCore0_iseqFsm_start_reg$D_IN;
if (adcCore0_iseqFsm_start_reg_1$EN)
adcCore0_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
adcCore0_iseqFsm_start_reg_1$D_IN;
if (adcCore0_iseqFsm_state_can_overlap$EN)
adcCore0_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
adcCore0_iseqFsm_state_can_overlap$D_IN;
if (adcCore0_iseqFsm_state_fired$EN)
adcCore0_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY
adcCore0_iseqFsm_state_fired$D_IN;
if (adcCore0_iseqFsm_state_mkFSMstate$EN)
adcCore0_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
adcCore0_iseqFsm_state_mkFSMstate$D_IN;
if (adcCore0_operateDReg$EN)
adcCore0_operateDReg <= `BSV_ASSIGNMENT_DELAY
adcCore0_operateDReg$D_IN;
if (adcCore0_readMode$EN)
adcCore0_readMode <= `BSV_ASSIGNMENT_DELAY adcCore0_readMode$D_IN;
if (adcCore0_spiI_reqF_tail_wrapped$EN)
adcCore0_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_reqF_tail_wrapped$D_IN;
if (adcCore0_spiI_respF_head_wrapped$EN)
adcCore0_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_respF_head_wrapped$D_IN;
if (adcCore1_acquireDReg$EN)
adcCore1_acquireDReg <= `BSV_ASSIGNMENT_DELAY
adcCore1_acquireDReg$D_IN;
if (adcCore1_adcRst$EN)
adcCore1_adcRst <= `BSV_ASSIGNMENT_DELAY adcCore1_adcRst$D_IN;
if (adcCore1_averageDReg$EN)
adcCore1_averageDReg <= `BSV_ASSIGNMENT_DELAY
adcCore1_averageDReg$D_IN;
if (adcCore1_ddrC_psCmdReg$EN)
adcCore1_ddrC_psCmdReg <= `BSV_ASSIGNMENT_DELAY
adcCore1_ddrC_psCmdReg$D_IN;
if (adcCore1_iseqFsm_jj_delay_count$EN)
adcCore1_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY
adcCore1_iseqFsm_jj_delay_count$D_IN;
if (adcCore1_iseqFsm_start_reg$EN)
adcCore1_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY
adcCore1_iseqFsm_start_reg$D_IN;
if (adcCore1_iseqFsm_start_reg_1$EN)
adcCore1_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
adcCore1_iseqFsm_start_reg_1$D_IN;
if (adcCore1_iseqFsm_state_can_overlap$EN)
adcCore1_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
adcCore1_iseqFsm_state_can_overlap$D_IN;
if (adcCore1_iseqFsm_state_fired$EN)
adcCore1_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY
adcCore1_iseqFsm_state_fired$D_IN;
if (adcCore1_iseqFsm_state_mkFSMstate$EN)
adcCore1_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
adcCore1_iseqFsm_state_mkFSMstate$D_IN;
if (adcCore1_operateDReg$EN)
adcCore1_operateDReg <= `BSV_ASSIGNMENT_DELAY
adcCore1_operateDReg$D_IN;
if (adcCore1_readMode$EN)
adcCore1_readMode <= `BSV_ASSIGNMENT_DELAY adcCore1_readMode$D_IN;
if (adcCore1_spiI_reqF_tail_wrapped$EN)
adcCore1_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_reqF_tail_wrapped$D_IN;
if (adcCore1_spiI_respF_head_wrapped$EN)
adcCore1_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_respF_head_wrapped$D_IN;
if (fcAdc_countNow$EN)
fcAdc_countNow <= `BSV_ASSIGNMENT_DELAY fcAdc_countNow$D_IN;
if (fcAdc_countPast$EN)
fcAdc_countPast <= `BSV_ASSIGNMENT_DELAY fcAdc_countPast$D_IN;
if (fcAdc_frequency$EN)
fcAdc_frequency <= `BSV_ASSIGNMENT_DELAY fcAdc_frequency$D_IN;
if (fcAdc_pulseAction$EN)
fcAdc_pulseAction <= `BSV_ASSIGNMENT_DELAY fcAdc_pulseAction$D_IN;
if (fcAdc_sampleCount$EN)
fcAdc_sampleCount <= `BSV_ASSIGNMENT_DELAY fcAdc_sampleCount$D_IN;
if (initOpInFlight$EN)
initOpInFlight <= `BSV_ASSIGNMENT_DELAY initOpInFlight$D_IN;
if (lastOverflowMesg$EN)
lastOverflowMesg <= `BSV_ASSIGNMENT_DELAY lastOverflowMesg$D_IN;
if (maxMesgLength$EN)
maxMesgLength <= `BSV_ASSIGNMENT_DELAY maxMesgLength$D_IN;
if (mesgCount$EN) mesgCount <= `BSV_ASSIGNMENT_DELAY mesgCount$D_IN;
if (oneKHz_value$EN)
oneKHz_value <= `BSV_ASSIGNMENT_DELAY oneKHz_value$D_IN;
if (overflowCountD$EN)
overflowCountD <= `BSV_ASSIGNMENT_DELAY overflowCountD$D_IN;
if (sFlagState$EN)
sFlagState <= `BSV_ASSIGNMENT_DELAY sFlagState$D_IN;
if (spiClk_iState$EN)
spiClk_iState <= `BSV_ASSIGNMENT_DELAY spiClk_iState$D_IN;
if (spiClk_iseqFsm_start_reg$EN)
spiClk_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY
spiClk_iseqFsm_start_reg$D_IN;
if (spiClk_iseqFsm_start_reg_1$EN)
spiClk_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
spiClk_iseqFsm_start_reg_1$D_IN;
if (spiClk_iseqFsm_state_can_overlap$EN)
spiClk_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
spiClk_iseqFsm_state_can_overlap$D_IN;
if (spiClk_iseqFsm_state_fired$EN)
spiClk_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY
spiClk_iseqFsm_state_fired$D_IN;
if (spiClk_iseqFsm_state_mkFSMstate$EN)
spiClk_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
spiClk_iseqFsm_state_mkFSMstate$D_IN;
if (spiClk_spiI_reqF_tail_wrapped$EN)
spiClk_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
spiClk_spiI_reqF_tail_wrapped$D_IN;
if (spiClk_spiI_respF_head_wrapped$EN)
spiClk_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
spiClk_spiI_respF_head_wrapped$D_IN;
if (spiResp$EN) spiResp <= `BSV_ASSIGNMENT_DELAY spiResp$D_IN;
if (splitReadInFlight$EN)
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN;
if (wci_wslv_cEdge$EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN;
if (wci_wslv_cState$EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN;
if (wci_wslv_ctlAckReg$EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN;
if (wci_wslv_ctlOpActive$EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive$D_IN;
if (wci_wslv_illegalEdge$EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge$D_IN;
if (wci_wslv_nState$EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN;
if (wci_wslv_reqF_countReg$EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg$D_IN;
if (wci_wslv_respF_c_r$EN)
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN;
if (wci_wslv_respF_q_0$EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN;
if (wci_wslv_respF_q_1$EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN;
if (wci_wslv_sFlagReg$EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN;
if (wci_wslv_sThreadBusy_d$EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
end
if (adcCore0_spiI_reqS$EN)
adcCore0_spiI_reqS <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_reqS$D_IN;
if (adcCore1_spiI_reqS$EN)
adcCore1_spiI_reqS <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_reqS$D_IN;
if (spiClk_spiI_reqS$EN)
spiClk_spiI_reqS <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_reqS$D_IN;
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
end
always@(posedge CLK_sys0_clk)
begin
if (RST_N_sys0_rst == `BSV_RESET_VALUE)
begin
adcIdc_doResetCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
adcIdc_preResetCount <= `BSV_ASSIGNMENT_DELAY 4'd0;
end
else
begin
if (adcIdc_doResetCount$EN)
adcIdc_doResetCount <= `BSV_ASSIGNMENT_DELAY
adcIdc_doResetCount$D_IN;
if (adcIdc_preResetCount$EN)
adcIdc_preResetCount <= `BSV_ASSIGNMENT_DELAY
adcIdc_preResetCount$D_IN;
end
end
always@(posedge spiClk_spiI_cd$CLK_OUT)
begin
if (spiClk_spiI_slowReset$OUT_RST == `BSV_RESET_VALUE)
begin
spiClk_spiI_cGate <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_spiI_csbR <= `BSV_ASSIGNMENT_DELAY 1'b1;
spiClk_spiI_doResp <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY 1'b0;
spiClk_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiClk_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (spiClk_spiI_cGate$EN)
spiClk_spiI_cGate <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cGate$D_IN;
if (spiClk_spiI_csbR$EN)
spiClk_spiI_csbR <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_csbR$D_IN;
if (spiClk_spiI_doResp$EN)
spiClk_spiI_doResp <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_doResp$D_IN;
if (spiClk_spiI_reqF_head_wrapped$EN)
spiClk_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
spiClk_spiI_reqF_head_wrapped$D_IN;
if (spiClk_spiI_respF_tail_wrapped$EN)
spiClk_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
spiClk_spiI_respF_tail_wrapped$D_IN;
if (spiClk_spiI_sdoR$EN)
spiClk_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_sdoR$D_IN;
if (spiClk_spiI_xmt_d$EN)
spiClk_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_xmt_d$D_IN;
if (spiClk_spiI_xmt_i$EN)
spiClk_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_xmt_i$D_IN;
end
if (spiClk_spiI_cap$EN)
spiClk_spiI_cap <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap$D_IN;
if (spiClk_spiI_cap_1$EN)
spiClk_spiI_cap_1 <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap_1$D_IN;
if (spiClk_spiI_cap_2$EN)
spiClk_spiI_cap_2 <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap_2$D_IN;
if (spiClk_spiI_cap_3$EN)
spiClk_spiI_cap_3 <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap_3$D_IN;
if (spiClk_spiI_cap_4$EN)
spiClk_spiI_cap_4 <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap_4$D_IN;
if (spiClk_spiI_cap_5$EN)
spiClk_spiI_cap_5 <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap_5$D_IN;
if (spiClk_spiI_cap_6$EN)
spiClk_spiI_cap_6 <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap_6$D_IN;
if (spiClk_spiI_cap_7$EN)
spiClk_spiI_cap_7 <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_cap_7$D_IN;
if (spiClk_spiI_dPos$EN)
spiClk_spiI_dPos <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_dPos$D_IN;
if (spiClk_spiI_iPos$EN)
spiClk_spiI_iPos <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_iPos$D_IN;
if (spiClk_spiI_respS$EN)
spiClk_spiI_respS <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_respS$D_IN;
end
always@(posedge spiClk_spiI_cinv$CLK_OUT)
begin
if (spiClk_spiI_sdiP$EN)
spiClk_spiI_sdiP <= `BSV_ASSIGNMENT_DELAY spiClk_spiI_sdiP$D_IN;
end
always@(posedge adcCore0_ddrC_ddrV$sdrClk)
begin
if (adcCore0_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore0_colGate_avgEven <= `BSV_ASSIGNMENT_DELAY 18'd0;
adcCore0_colGate_avgOdd <= `BSV_ASSIGNMENT_DELAY 18'd0;
adcCore0_colGate_avgPhase <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore0_colGate_collectD <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_colGate_dropCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore0_colGate_dwellFails <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore0_colGate_dwellStarts <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore0_colGate_ovrRecover <= `BSV_ASSIGNMENT_DELAY 4'd0;
adcCore0_colGate_sampActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_colGate_sampActiveD <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_colGate_sampCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore0_colGate_syncMesg <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore0_colGate_timeMesg <= `BSV_ASSIGNMENT_DELAY 3'd0;
adcCore0_colGate_uprollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
wti_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wti_operateD <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (adcCore0_colGate_avgEven$EN)
adcCore0_colGate_avgEven <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_avgEven$D_IN;
if (adcCore0_colGate_avgOdd$EN)
adcCore0_colGate_avgOdd <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_avgOdd$D_IN;
if (adcCore0_colGate_avgPhase$EN)
adcCore0_colGate_avgPhase <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_avgPhase$D_IN;
if (adcCore0_colGate_collectD$EN)
adcCore0_colGate_collectD <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_collectD$D_IN;
if (adcCore0_colGate_dropCount$EN)
adcCore0_colGate_dropCount <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_dropCount$D_IN;
if (adcCore0_colGate_dwellFails$EN)
adcCore0_colGate_dwellFails <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_dwellFails$D_IN;
if (adcCore0_colGate_dwellStarts$EN)
adcCore0_colGate_dwellStarts <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_dwellStarts$D_IN;
if (adcCore0_colGate_ovrRecover$EN)
adcCore0_colGate_ovrRecover <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_ovrRecover$D_IN;
if (adcCore0_colGate_sampActive$EN)
adcCore0_colGate_sampActive <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_sampActive$D_IN;
if (adcCore0_colGate_sampActiveD$EN)
adcCore0_colGate_sampActiveD <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_sampActiveD$D_IN;
if (adcCore0_colGate_sampCount$EN)
adcCore0_colGate_sampCount <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_sampCount$D_IN;
if (adcCore0_colGate_syncMesg$EN)
adcCore0_colGate_syncMesg <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_syncMesg$D_IN;
if (adcCore0_colGate_timeMesg$EN)
adcCore0_colGate_timeMesg <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_timeMesg$D_IN;
if (adcCore0_colGate_uprollCnt$EN)
adcCore0_colGate_uprollCnt <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_uprollCnt$D_IN;
if (wti_nowReq$EN)
wti_nowReq <= `BSV_ASSIGNMENT_DELAY wti_nowReq$D_IN;
if (wti_operateD$EN)
wti_operateD <= `BSV_ASSIGNMENT_DELAY wti_operateD$D_IN;
end
if (adcCore0_colGate_sampDataWD$EN)
adcCore0_colGate_sampDataWD <= `BSV_ASSIGNMENT_DELAY
adcCore0_colGate_sampDataWD$D_IN;
if (adcCore0_samp$EN)
adcCore0_samp <= `BSV_ASSIGNMENT_DELAY adcCore0_samp$D_IN;
end
always@(posedge adcCore0_spiI_cd$CLK_OUT)
begin
if (adcCore0_spiI_slowReset$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore0_spiI_cGate <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_spiI_csbR <= `BSV_ASSIGNMENT_DELAY 1'b1;
adcCore0_spiI_doResp <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY 1'b0;
adcCore0_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore0_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (adcCore0_spiI_cGate$EN)
adcCore0_spiI_cGate <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_cGate$D_IN;
if (adcCore0_spiI_csbR$EN)
adcCore0_spiI_csbR <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_csbR$D_IN;
if (adcCore0_spiI_doResp$EN)
adcCore0_spiI_doResp <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_doResp$D_IN;
if (adcCore0_spiI_reqF_head_wrapped$EN)
adcCore0_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_reqF_head_wrapped$D_IN;
if (adcCore0_spiI_respF_tail_wrapped$EN)
adcCore0_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_respF_tail_wrapped$D_IN;
if (adcCore0_spiI_sdoR$EN)
adcCore0_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_sdoR$D_IN;
if (adcCore0_spiI_xmt_d$EN)
adcCore0_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_xmt_d$D_IN;
if (adcCore0_spiI_xmt_i$EN)
adcCore0_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY
adcCore0_spiI_xmt_i$D_IN;
end
if (adcCore0_spiI_cap$EN)
adcCore0_spiI_cap <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap$D_IN;
if (adcCore0_spiI_cap_1$EN)
adcCore0_spiI_cap_1 <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap_1$D_IN;
if (adcCore0_spiI_cap_2$EN)
adcCore0_spiI_cap_2 <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap_2$D_IN;
if (adcCore0_spiI_cap_3$EN)
adcCore0_spiI_cap_3 <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap_3$D_IN;
if (adcCore0_spiI_cap_4$EN)
adcCore0_spiI_cap_4 <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap_4$D_IN;
if (adcCore0_spiI_cap_5$EN)
adcCore0_spiI_cap_5 <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap_5$D_IN;
if (adcCore0_spiI_cap_6$EN)
adcCore0_spiI_cap_6 <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap_6$D_IN;
if (adcCore0_spiI_cap_7$EN)
adcCore0_spiI_cap_7 <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_cap_7$D_IN;
if (adcCore0_spiI_dPos$EN)
adcCore0_spiI_dPos <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_dPos$D_IN;
if (adcCore0_spiI_iPos$EN)
adcCore0_spiI_iPos <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_iPos$D_IN;
if (adcCore0_spiI_respS$EN)
adcCore0_spiI_respS <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_respS$D_IN;
end
always@(posedge adcCore0_spiI_cinv$CLK_OUT)
begin
if (adcCore0_spiI_sdiP$EN)
adcCore0_spiI_sdiP <= `BSV_ASSIGNMENT_DELAY adcCore0_spiI_sdiP$D_IN;
end
always@(posedge adcCore1_ddrC_ddrV$sdrClk)
begin
if (adcCore1_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore1_colGate_avgEven <= `BSV_ASSIGNMENT_DELAY 18'd0;
adcCore1_colGate_avgOdd <= `BSV_ASSIGNMENT_DELAY 18'd0;
adcCore1_colGate_avgPhase <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore1_colGate_collectD <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_colGate_dropCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore1_colGate_dwellFails <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore1_colGate_dwellStarts <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore1_colGate_ovrRecover <= `BSV_ASSIGNMENT_DELAY 4'd0;
adcCore1_colGate_sampActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_colGate_sampActiveD <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_colGate_sampCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore1_colGate_syncMesg <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore1_colGate_timeMesg <= `BSV_ASSIGNMENT_DELAY 3'd0;
adcCore1_colGate_uprollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
end
else
begin
if (adcCore1_colGate_avgEven$EN)
adcCore1_colGate_avgEven <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_avgEven$D_IN;
if (adcCore1_colGate_avgOdd$EN)
adcCore1_colGate_avgOdd <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_avgOdd$D_IN;
if (adcCore1_colGate_avgPhase$EN)
adcCore1_colGate_avgPhase <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_avgPhase$D_IN;
if (adcCore1_colGate_collectD$EN)
adcCore1_colGate_collectD <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_collectD$D_IN;
if (adcCore1_colGate_dropCount$EN)
adcCore1_colGate_dropCount <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_dropCount$D_IN;
if (adcCore1_colGate_dwellFails$EN)
adcCore1_colGate_dwellFails <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_dwellFails$D_IN;
if (adcCore1_colGate_dwellStarts$EN)
adcCore1_colGate_dwellStarts <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_dwellStarts$D_IN;
if (adcCore1_colGate_ovrRecover$EN)
adcCore1_colGate_ovrRecover <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_ovrRecover$D_IN;
if (adcCore1_colGate_sampActive$EN)
adcCore1_colGate_sampActive <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_sampActive$D_IN;
if (adcCore1_colGate_sampActiveD$EN)
adcCore1_colGate_sampActiveD <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_sampActiveD$D_IN;
if (adcCore1_colGate_sampCount$EN)
adcCore1_colGate_sampCount <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_sampCount$D_IN;
if (adcCore1_colGate_syncMesg$EN)
adcCore1_colGate_syncMesg <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_syncMesg$D_IN;
if (adcCore1_colGate_timeMesg$EN)
adcCore1_colGate_timeMesg <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_timeMesg$D_IN;
if (adcCore1_colGate_uprollCnt$EN)
adcCore1_colGate_uprollCnt <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_uprollCnt$D_IN;
end
if (adcCore1_colGate_sampDataWD$EN)
adcCore1_colGate_sampDataWD <= `BSV_ASSIGNMENT_DELAY
adcCore1_colGate_sampDataWD$D_IN;
if (adcCore1_samp$EN)
adcCore1_samp <= `BSV_ASSIGNMENT_DELAY adcCore1_samp$D_IN;
end
always@(posedge adcCore1_spiI_cd$CLK_OUT)
begin
if (adcCore1_spiI_slowReset$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore1_spiI_cGate <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_spiI_csbR <= `BSV_ASSIGNMENT_DELAY 1'b1;
adcCore1_spiI_doResp <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY 1'b0;
adcCore1_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore1_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (adcCore1_spiI_cGate$EN)
adcCore1_spiI_cGate <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_cGate$D_IN;
if (adcCore1_spiI_csbR$EN)
adcCore1_spiI_csbR <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_csbR$D_IN;
if (adcCore1_spiI_doResp$EN)
adcCore1_spiI_doResp <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_doResp$D_IN;
if (adcCore1_spiI_reqF_head_wrapped$EN)
adcCore1_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_reqF_head_wrapped$D_IN;
if (adcCore1_spiI_respF_tail_wrapped$EN)
adcCore1_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_respF_tail_wrapped$D_IN;
if (adcCore1_spiI_sdoR$EN)
adcCore1_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_sdoR$D_IN;
if (adcCore1_spiI_xmt_d$EN)
adcCore1_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_xmt_d$D_IN;
if (adcCore1_spiI_xmt_i$EN)
adcCore1_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY
adcCore1_spiI_xmt_i$D_IN;
end
if (adcCore1_spiI_cap$EN)
adcCore1_spiI_cap <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap$D_IN;
if (adcCore1_spiI_cap_1$EN)
adcCore1_spiI_cap_1 <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap_1$D_IN;
if (adcCore1_spiI_cap_2$EN)
adcCore1_spiI_cap_2 <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap_2$D_IN;
if (adcCore1_spiI_cap_3$EN)
adcCore1_spiI_cap_3 <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap_3$D_IN;
if (adcCore1_spiI_cap_4$EN)
adcCore1_spiI_cap_4 <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap_4$D_IN;
if (adcCore1_spiI_cap_5$EN)
adcCore1_spiI_cap_5 <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap_5$D_IN;
if (adcCore1_spiI_cap_6$EN)
adcCore1_spiI_cap_6 <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap_6$D_IN;
if (adcCore1_spiI_cap_7$EN)
adcCore1_spiI_cap_7 <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_cap_7$D_IN;
if (adcCore1_spiI_dPos$EN)
adcCore1_spiI_dPos <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_dPos$D_IN;
if (adcCore1_spiI_iPos$EN)
adcCore1_spiI_iPos <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_iPos$D_IN;
if (adcCore1_spiI_respS$EN)
adcCore1_spiI_respS <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_respS$D_IN;
end
always@(posedge adcCore1_spiI_cinv$CLK_OUT)
begin
if (adcCore1_spiI_sdiP$EN)
adcCore1_spiI_sdiP <= `BSV_ASSIGNMENT_DELAY adcCore1_spiI_sdiP$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
adcCore0_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore0_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore0_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore1_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore1_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore1_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
fcAdc_grayCounter_rdCounter <= `BSV_ASSIGNMENT_DELAY 18'd0;
fcAdc_grayCounter_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 18'd0;
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (adcCore0_sampF_rRdPtr_rsCounter$EN)
adcCore0_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
adcCore0_sampF_rRdPtr_rsCounter$D_IN;
if (adcCore0_sampF_rWrPtr_rdCounter$EN)
adcCore0_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
adcCore0_sampF_rWrPtr_rdCounter$D_IN;
if (adcCore0_sampF_rWrPtr_rdCounterPre$EN)
adcCore0_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
adcCore0_sampF_rWrPtr_rdCounterPre$D_IN;
if (adcCore1_sampF_rRdPtr_rsCounter$EN)
adcCore1_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
adcCore1_sampF_rRdPtr_rsCounter$D_IN;
if (adcCore1_sampF_rWrPtr_rdCounter$EN)
adcCore1_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
adcCore1_sampF_rWrPtr_rdCounter$D_IN;
if (adcCore1_sampF_rWrPtr_rdCounterPre$EN)
adcCore1_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
adcCore1_sampF_rWrPtr_rdCounterPre$D_IN;
if (fcAdc_grayCounter_rdCounter$EN)
fcAdc_grayCounter_rdCounter <= `BSV_ASSIGNMENT_DELAY
fcAdc_grayCounter_rdCounter$D_IN;
if (fcAdc_grayCounter_rdCounterPre$EN)
fcAdc_grayCounter_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
fcAdc_grayCounter_rdCounterPre$D_IN;
if (wci_wslv_isReset_isInReset$EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset$D_IN;
if (wsiM_isReset_isInReset$EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset$D_IN;
end
always@(posedge CLK_adc_clk or `BSV_RESET_EDGE fcAdc_testRst$OUT_RST)
if (fcAdc_testRst$OUT_RST == `BSV_RESET_VALUE)
begin
fcAdc_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY 18'd0;
end
else
begin
if (fcAdc_grayCounter_rsCounter$EN)
fcAdc_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY
fcAdc_grayCounter_rsCounter$D_IN;
end
always@(posedge adcCore0_ddrC_ddrV$sdrClk or
`BSV_RESET_EDGE adcCore0_sdrRst$OUT_RST)
if (adcCore0_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore0_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore0_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore0_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (adcCore0_sampF_rRdPtr_rdCounter$EN)
adcCore0_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
adcCore0_sampF_rRdPtr_rdCounter$D_IN;
if (adcCore0_sampF_rRdPtr_rdCounterPre$EN)
adcCore0_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
adcCore0_sampF_rRdPtr_rdCounterPre$D_IN;
if (adcCore0_sampF_rWrPtr_rsCounter$EN)
adcCore0_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
adcCore0_sampF_rWrPtr_rsCounter$D_IN;
if (wti_isReset_isInReset$EN)
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wti_isReset_isInReset$D_IN;
end
always@(posedge adcCore1_ddrC_ddrV$sdrClk or
`BSV_RESET_EDGE adcCore1_sdrRst$OUT_RST)
if (adcCore1_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore1_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore1_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore1_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
end
else
begin
if (adcCore1_sampF_rRdPtr_rdCounter$EN)
adcCore1_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
adcCore1_sampF_rRdPtr_rdCounter$D_IN;
if (adcCore1_sampF_rRdPtr_rdCounterPre$EN)
adcCore1_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
adcCore1_sampF_rRdPtr_rdCounterPre$D_IN;
if (adcCore1_sampF_rWrPtr_rsCounter$EN)
adcCore1_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
adcCore1_sampF_rWrPtr_rsCounter$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
adcControl = 32'hAAAAAAAA;
adcCore0_acquireDReg = 1'h0;
adcCore0_adcRst = 1'h0;
adcCore0_averageDReg = 1'h0;
adcCore0_colGate_avgEven = 18'h2AAAA;
adcCore0_colGate_avgOdd = 18'h2AAAA;
adcCore0_colGate_avgPhase = 2'h2;
adcCore0_colGate_collectD = 1'h0;
adcCore0_colGate_dropCount = 32'hAAAAAAAA;
adcCore0_colGate_dwellFails = 32'hAAAAAAAA;
adcCore0_colGate_dwellStarts = 32'hAAAAAAAA;
adcCore0_colGate_ovrRecover = 4'hA;
adcCore0_colGate_sampActive = 1'h0;
adcCore0_colGate_sampActiveD = 1'h0;
adcCore0_colGate_sampCount = 32'hAAAAAAAA;
adcCore0_colGate_sampDataWD = 32'hAAAAAAAA;
adcCore0_colGate_syncMesg = 2'h2;
adcCore0_colGate_timeMesg = 3'h2;
adcCore0_colGate_uprollCnt = 16'hAAAA;
adcCore0_ddrC_psCmdReg = 2'h2;
adcCore0_iseqFsm_jj_delay_count = 13'h0AAA;
adcCore0_iseqFsm_start_reg = 1'h0;
adcCore0_iseqFsm_start_reg_1 = 1'h0;
adcCore0_iseqFsm_state_can_overlap = 1'h0;
adcCore0_iseqFsm_state_fired = 1'h0;
adcCore0_iseqFsm_state_mkFSMstate = 4'hA;
adcCore0_operateDReg = 1'h0;
adcCore0_readMode = 1'h0;
adcCore0_samp = 32'hAAAAAAAA;
adcCore0_sampF_rRdPtr_rdCounter = 11'h2AA;
adcCore0_sampF_rRdPtr_rdCounterPre = 11'h2AA;
adcCore0_sampF_rRdPtr_rsCounter = 11'h2AA;
adcCore0_sampF_rWrPtr_rdCounter = 11'h2AA;
adcCore0_sampF_rWrPtr_rdCounterPre = 11'h2AA;
adcCore0_sampF_rWrPtr_rsCounter = 11'h2AA;
adcCore0_spiI_cGate = 1'h0;
adcCore0_spiI_cap = 1'h0;
adcCore0_spiI_cap_1 = 1'h0;
adcCore0_spiI_cap_2 = 1'h0;
adcCore0_spiI_cap_3 = 1'h0;
adcCore0_spiI_cap_4 = 1'h0;
adcCore0_spiI_cap_5 = 1'h0;
adcCore0_spiI_cap_6 = 1'h0;
adcCore0_spiI_cap_7 = 1'h0;
adcCore0_spiI_csbR = 1'h0;
adcCore0_spiI_dPos = 3'h2;
adcCore0_spiI_doResp = 1'h0;
adcCore0_spiI_iPos = 4'hA;
adcCore0_spiI_reqF_head_wrapped = 1'h0;
adcCore0_spiI_reqF_tail_wrapped = 1'h0;
adcCore0_spiI_reqS = 17'h0AAAA;
adcCore0_spiI_respF_head_wrapped = 1'h0;
adcCore0_spiI_respF_tail_wrapped = 1'h0;
adcCore0_spiI_respS = 8'hAA;
adcCore0_spiI_sdiP = 1'h0;
adcCore0_spiI_sdoR = 1'h0;
adcCore0_spiI_xmt_d = 1'h0;
adcCore0_spiI_xmt_i = 1'h0;
adcCore1_acquireDReg = 1'h0;
adcCore1_adcRst = 1'h0;
adcCore1_averageDReg = 1'h0;
adcCore1_colGate_avgEven = 18'h2AAAA;
adcCore1_colGate_avgOdd = 18'h2AAAA;
adcCore1_colGate_avgPhase = 2'h2;
adcCore1_colGate_collectD = 1'h0;
adcCore1_colGate_dropCount = 32'hAAAAAAAA;
adcCore1_colGate_dwellFails = 32'hAAAAAAAA;
adcCore1_colGate_dwellStarts = 32'hAAAAAAAA;
adcCore1_colGate_ovrRecover = 4'hA;
adcCore1_colGate_sampActive = 1'h0;
adcCore1_colGate_sampActiveD = 1'h0;
adcCore1_colGate_sampCount = 32'hAAAAAAAA;
adcCore1_colGate_sampDataWD = 32'hAAAAAAAA;
adcCore1_colGate_syncMesg = 2'h2;
adcCore1_colGate_timeMesg = 3'h2;
adcCore1_colGate_uprollCnt = 16'hAAAA;
adcCore1_ddrC_psCmdReg = 2'h2;
adcCore1_iseqFsm_jj_delay_count = 13'h0AAA;
adcCore1_iseqFsm_start_reg = 1'h0;
adcCore1_iseqFsm_start_reg_1 = 1'h0;
adcCore1_iseqFsm_state_can_overlap = 1'h0;
adcCore1_iseqFsm_state_fired = 1'h0;
adcCore1_iseqFsm_state_mkFSMstate = 4'hA;
adcCore1_operateDReg = 1'h0;
adcCore1_readMode = 1'h0;
adcCore1_samp = 32'hAAAAAAAA;
adcCore1_sampF_rRdPtr_rdCounter = 11'h2AA;
adcCore1_sampF_rRdPtr_rdCounterPre = 11'h2AA;
adcCore1_sampF_rRdPtr_rsCounter = 11'h2AA;
adcCore1_sampF_rWrPtr_rdCounter = 11'h2AA;
adcCore1_sampF_rWrPtr_rdCounterPre = 11'h2AA;
adcCore1_sampF_rWrPtr_rsCounter = 11'h2AA;
adcCore1_spiI_cGate = 1'h0;
adcCore1_spiI_cap = 1'h0;
adcCore1_spiI_cap_1 = 1'h0;
adcCore1_spiI_cap_2 = 1'h0;
adcCore1_spiI_cap_3 = 1'h0;
adcCore1_spiI_cap_4 = 1'h0;
adcCore1_spiI_cap_5 = 1'h0;
adcCore1_spiI_cap_6 = 1'h0;
adcCore1_spiI_cap_7 = 1'h0;
adcCore1_spiI_csbR = 1'h0;
adcCore1_spiI_dPos = 3'h2;
adcCore1_spiI_doResp = 1'h0;
adcCore1_spiI_iPos = 4'hA;
adcCore1_spiI_reqF_head_wrapped = 1'h0;
adcCore1_spiI_reqF_tail_wrapped = 1'h0;
adcCore1_spiI_reqS = 17'h0AAAA;
adcCore1_spiI_respF_head_wrapped = 1'h0;
adcCore1_spiI_respF_tail_wrapped = 1'h0;
adcCore1_spiI_respS = 8'hAA;
adcCore1_spiI_sdiP = 1'h0;
adcCore1_spiI_sdoR = 1'h0;
adcCore1_spiI_xmt_d = 1'h0;
adcCore1_spiI_xmt_i = 1'h0;
adcIdc_doResetCount = 4'hA;
adcIdc_preResetCount = 4'hA;
fcAdc_countNow = 18'h2AAAA;
fcAdc_countPast = 18'h2AAAA;
fcAdc_frequency = 18'h2AAAA;
fcAdc_grayCounter_rdCounter = 18'h2AAAA;
fcAdc_grayCounter_rdCounterPre = 18'h2AAAA;
fcAdc_grayCounter_rsCounter = 18'h2AAAA;
fcAdc_pulseAction = 1'h0;
fcAdc_sampleCount = 16'hAAAA;
initOpInFlight = 1'h0;
lastOverflowMesg = 32'hAAAAAAAA;
maxMesgLength = 32'hAAAAAAAA;
mesgCount = 32'hAAAAAAAA;
oneKHz_value = 18'h2AAAA;
overflowCountD = 32'hAAAAAAAA;
sFlagState = 1'h0;
spiClk_iState = 4'hA;
spiClk_iseqFsm_start_reg = 1'h0;
spiClk_iseqFsm_start_reg_1 = 1'h0;
spiClk_iseqFsm_state_can_overlap = 1'h0;
spiClk_iseqFsm_state_fired = 1'h0;
spiClk_iseqFsm_state_mkFSMstate = 4'hA;
spiClk_spiI_cGate = 1'h0;
spiClk_spiI_cap = 1'h0;
spiClk_spiI_cap_1 = 1'h0;
spiClk_spiI_cap_2 = 1'h0;
spiClk_spiI_cap_3 = 1'h0;
spiClk_spiI_cap_4 = 1'h0;
spiClk_spiI_cap_5 = 1'h0;
spiClk_spiI_cap_6 = 1'h0;
spiClk_spiI_cap_7 = 1'h0;
spiClk_spiI_csbR = 1'h0;
spiClk_spiI_dPos = 3'h2;
spiClk_spiI_doResp = 1'h0;
spiClk_spiI_iPos = 4'hA;
spiClk_spiI_reqF_head_wrapped = 1'h0;
spiClk_spiI_reqF_tail_wrapped = 1'h0;
spiClk_spiI_reqS = 17'h0AAAA;
spiClk_spiI_respF_head_wrapped = 1'h0;
spiClk_spiI_respF_tail_wrapped = 1'h0;
spiClk_spiI_respS = 8'hAA;
spiClk_spiI_sdiP = 1'h0;
spiClk_spiI_sdoR = 1'h0;
spiClk_spiI_xmt_d = 1'h0;
spiClk_spiI_xmt_i = 1'h0;
spiResp = 8'hAA;
splitReadInFlight = 1'h0;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_c_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wti_isReset_isInReset = 1'h0;
wti_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wti_operateD = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 &&
WILL_FIRE_RL_get_adc1_resp)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 88: (R0001)\n Mutually exclusive rules (from the ME sets [RL_get_adx_resp] and\n [RL_get_adc1_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1 &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 88: (R0001)\n Mutually exclusive rules (from the ME sets [RL_get_adx_resp] and\n [RL_get_adc0_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2 &&
WILL_FIRE_RL_get_adc1_resp)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 102: (R0001)\n Mutually exclusive rules (from the ME sets [RL_get_adc0_resp] and\n [RL_get_adc1_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h130298 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h130298,
wci_wslv_reqF$D_OUT[63:32],
wci_wslv_reqF$D_OUT[67:64],
wci_wslv_reqF$D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3700 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3700,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_get_adc1_resp)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_get_adc1_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_get_adc0_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_get_adx_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_get_adc1_resp)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 74: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_get_adc1_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_OrE &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 74: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_get_adc0_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_OrE &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 74: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_get_adx_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 &&
(WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9))
$display("Error: \"bsv/dev/AD9512.bsv\", line 45, column 9: (R0001)\n Mutually exclusive rules (from the ME sets [RL_spiClk_iseqFsm_action_l45c9]\n and [RL_spiClk_iseqFsm_action_l46c9, RL_spiClk_iseqFsm_action_l47c9,\n RL_spiClk_iseqFsm_action_l48c9, RL_spiClk_iseqFsm_action_l49c9,\n RL_spiClk_iseqFsm_action_l50c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 &&
(WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9))
$display("Error: \"bsv/dev/AD9512.bsv\", line 46, column 9: (R0001)\n Mutually exclusive rules (from the ME sets [RL_spiClk_iseqFsm_action_l46c9]\n and [RL_spiClk_iseqFsm_action_l47c9, RL_spiClk_iseqFsm_action_l48c9,\n RL_spiClk_iseqFsm_action_l49c9, RL_spiClk_iseqFsm_action_l50c9] ) fired in\n the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 &&
(WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9))
$display("Error: \"bsv/dev/AD9512.bsv\", line 47, column 9: (R0001)\n Mutually exclusive rules (from the ME sets [RL_spiClk_iseqFsm_action_l47c9]\n and [RL_spiClk_iseqFsm_action_l48c9, RL_spiClk_iseqFsm_action_l49c9,\n RL_spiClk_iseqFsm_action_l50c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 &&
(WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9))
$display("Error: \"bsv/dev/AD9512.bsv\", line 48, column 9: (R0001)\n Mutually exclusive rules (from the ME sets [RL_spiClk_iseqFsm_action_l48c9]\n and [RL_spiClk_iseqFsm_action_l49c9, RL_spiClk_iseqFsm_action_l50c9] ) fired\n in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 &&
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9)
$display("Error: \"bsv/dev/AD9512.bsv\", line 49, column 9: (R0001)\n Mutually exclusive rules (from the ME sets [RL_spiClk_iseqFsm_action_l49c9]\n and [RL_spiClk_iseqFsm_action_l50c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (adcCore0_iseqFsm_state_mkFSMstate == 4'd1 &&
(adcCore0_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 117, column 12: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_l117c12] and\n [RL_adcCore0_iseqFsm_action_d_init_np, RL_adcCore0_iseqFsm_action_np,\n RL_adcCore0_iseqFsm_action_l119c9, RL_adcCore0_iseqFsm_action_l120c9,\n RL_adcCore0_iseqFsm_action_l121c9, RL_adcCore0_iseqFsm_action_l122c9,\n RL_adcCore0_iseqFsm_action_l123c9, RL_adcCore0_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (adcCore0_iseqFsm_state_mkFSMstate == 4'd2 &&
(WILL_FIRE_RL_adcCore0_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_d_init_np] and [RL_adcCore0_iseqFsm_action_np,\n RL_adcCore0_iseqFsm_action_l119c9, RL_adcCore0_iseqFsm_action_l120c9,\n RL_adcCore0_iseqFsm_action_l121c9, RL_adcCore0_iseqFsm_action_l122c9,\n RL_adcCore0_iseqFsm_action_l123c9, RL_adcCore0_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore0_iseqFsm_action_np &&
(WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_adcCore0_iseqFsm_action_np]\n and [RL_adcCore0_iseqFsm_action_l119c9, RL_adcCore0_iseqFsm_action_l120c9,\n RL_adcCore0_iseqFsm_action_l121c9, RL_adcCore0_iseqFsm_action_l122c9,\n RL_adcCore0_iseqFsm_action_l123c9, RL_adcCore0_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 &&
(WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 119, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_l119c9] and [RL_adcCore0_iseqFsm_action_l120c9,\n RL_adcCore0_iseqFsm_action_l121c9, RL_adcCore0_iseqFsm_action_l122c9,\n RL_adcCore0_iseqFsm_action_l123c9, RL_adcCore0_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 &&
(WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 120, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_l120c9] and [RL_adcCore0_iseqFsm_action_l121c9,\n RL_adcCore0_iseqFsm_action_l122c9, RL_adcCore0_iseqFsm_action_l123c9,\n RL_adcCore0_iseqFsm_action_l124c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 &&
(WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 121, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_l121c9] and [RL_adcCore0_iseqFsm_action_l122c9,\n RL_adcCore0_iseqFsm_action_l123c9, RL_adcCore0_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 &&
(WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 122, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_l122c9] and [RL_adcCore0_iseqFsm_action_l123c9,\n RL_adcCore0_iseqFsm_action_l124c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 &&
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9)
$display("Error: \"bsv/dev/TI6149.bsv\", line 123, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_l123c9] and [RL_adcCore0_iseqFsm_action_l124c9]\n ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (adcCore1_iseqFsm_state_mkFSMstate == 4'd1 &&
(adcCore1_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 117, column 12: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_l117c12] and\n [RL_adcCore1_iseqFsm_action_d_init_np, RL_adcCore1_iseqFsm_action_np,\n RL_adcCore1_iseqFsm_action_l119c9, RL_adcCore1_iseqFsm_action_l120c9,\n RL_adcCore1_iseqFsm_action_l121c9, RL_adcCore1_iseqFsm_action_l122c9,\n RL_adcCore1_iseqFsm_action_l123c9, RL_adcCore1_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (adcCore1_iseqFsm_state_mkFSMstate == 4'd2 &&
(WILL_FIRE_RL_adcCore1_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_d_init_np] and [RL_adcCore1_iseqFsm_action_np,\n RL_adcCore1_iseqFsm_action_l119c9, RL_adcCore1_iseqFsm_action_l120c9,\n RL_adcCore1_iseqFsm_action_l121c9, RL_adcCore1_iseqFsm_action_l122c9,\n RL_adcCore1_iseqFsm_action_l123c9, RL_adcCore1_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore1_iseqFsm_action_np &&
(WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_adcCore1_iseqFsm_action_np]\n and [RL_adcCore1_iseqFsm_action_l119c9, RL_adcCore1_iseqFsm_action_l120c9,\n RL_adcCore1_iseqFsm_action_l121c9, RL_adcCore1_iseqFsm_action_l122c9,\n RL_adcCore1_iseqFsm_action_l123c9, RL_adcCore1_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 &&
(WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 119, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_l119c9] and [RL_adcCore1_iseqFsm_action_l120c9,\n RL_adcCore1_iseqFsm_action_l121c9, RL_adcCore1_iseqFsm_action_l122c9,\n RL_adcCore1_iseqFsm_action_l123c9, RL_adcCore1_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 &&
(WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 120, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_l120c9] and [RL_adcCore1_iseqFsm_action_l121c9,\n RL_adcCore1_iseqFsm_action_l122c9, RL_adcCore1_iseqFsm_action_l123c9,\n RL_adcCore1_iseqFsm_action_l124c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 &&
(WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 121, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_l121c9] and [RL_adcCore1_iseqFsm_action_l122c9,\n RL_adcCore1_iseqFsm_action_l123c9, RL_adcCore1_iseqFsm_action_l124c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 &&
(WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 122, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_l122c9] and [RL_adcCore1_iseqFsm_action_l123c9,\n RL_adcCore1_iseqFsm_action_l124c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 &&
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9)
$display("Error: \"bsv/dev/TI6149.bsv\", line 123, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_l123c9] and [RL_adcCore1_iseqFsm_action_l124c9]\n ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h131387 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h131387,
wci_wslv_reqF$D_OUT[63:32],
wci_wslv_reqF$D_OUT[67:64],
rdat__h131371);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_get_adc1_resp)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_get_adc1_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_get_adc0_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_get_adx_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_get_adc1_resp)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_get_adc1_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_get_adc0_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_get_adx_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_get_adc1_resp)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_get_adc1_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_2)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_get_adc0_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI &&
MUX_wci_wslv_respF_x_wire$wset_1__PSEL_1)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_get_adx_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/ADCWorker.bsv\", line 125, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h4019 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4019,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3875 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3875,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_spiClk_iseqFsm_action_l44c9 &&
(WILL_FIRE_RL_spiClk_iseqFsm_action_l45c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l46c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l47c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l48c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l49c9 ||
WILL_FIRE_RL_spiClk_iseqFsm_action_l50c9))
$display("Error: \"bsv/dev/AD9512.bsv\", line 44, column 9: (R0001)\n Mutually exclusive rules (from the ME sets [RL_spiClk_iseqFsm_action_l44c9]\n and [RL_spiClk_iseqFsm_action_l45c9, RL_spiClk_iseqFsm_action_l46c9,\n RL_spiClk_iseqFsm_action_l47c9, RL_spiClk_iseqFsm_action_l48c9,\n RL_spiClk_iseqFsm_action_l49c9, RL_spiClk_iseqFsm_action_l50c9] ) fired in\n the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore0_iseqFsm_action_l116c12 &&
(adcCore0_iseqFsm_state_mkFSMstate == 4'd1 ||
adcCore0_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore0_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 116, column 12: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore0_iseqFsm_action_l116c12] and\n [RL_adcCore0_iseqFsm_action_l117c12, RL_adcCore0_iseqFsm_action_d_init_np,\n RL_adcCore0_iseqFsm_action_np, RL_adcCore0_iseqFsm_action_l119c9,\n RL_adcCore0_iseqFsm_action_l120c9, RL_adcCore0_iseqFsm_action_l121c9,\n RL_adcCore0_iseqFsm_action_l122c9, RL_adcCore0_iseqFsm_action_l123c9,\n RL_adcCore0_iseqFsm_action_l124c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore1_iseqFsm_action_l116c12 &&
(adcCore1_iseqFsm_state_mkFSMstate == 4'd1 ||
adcCore1_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l119c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l120c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l121c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l122c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l123c9 ||
WILL_FIRE_RL_adcCore1_iseqFsm_action_l124c9))
$display("Error: \"bsv/dev/TI6149.bsv\", line 116, column 12: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore1_iseqFsm_action_l116c12] and\n [RL_adcCore1_iseqFsm_action_l117c12, RL_adcCore1_iseqFsm_action_d_init_np,\n RL_adcCore1_iseqFsm_action_np, RL_adcCore1_iseqFsm_action_l119c9,\n RL_adcCore1_iseqFsm_action_l120c9, RL_adcCore1_iseqFsm_action_l121c9,\n RL_adcCore1_iseqFsm_action_l122c9, RL_adcCore1_iseqFsm_action_l123c9,\n RL_adcCore1_iseqFsm_action_l124c9] ) fired in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkADCWorker
|
/*
-- ============================================================================
-- FILE NAME : mem_stage.v
-- DESCRIPTION : MEM¥¹¥Æ©`¥¸
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito ÐÂÒ×÷³É
-- ============================================================================
*/
/********** ¹²Í¨¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "nettype.h"
`include "global_config.h"
`include "stddef.h"
/********** e¥Ø¥Ã¥À¥Õ¥¡¥¤¥ë **********/
`include "isa.h"
`include "cpu.h"
/********** ¥â¥¸¥å©`¥ë **********/
module mem_stage (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
input wire clk, // ¥¯¥í¥Ã¥¯
input wire reset, // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
input wire stall, // ¥¹¥È©`¥ë
input wire flush, // ¥Õ¥é¥Ã¥·¥å
output wire busy, // ¥Ó¥¸©`ÐźÅ
/********** ¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
output wire [`WordDataBus] fwd_data, // ¥Õ¥©¥ï©`¥Ç¥£¥ó¥°¥Ç©`¥¿
/********** SPM¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] spm_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
output wire [`WordAddrBus] spm_addr, // ¥¢¥É¥ì¥¹
output wire spm_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire spm_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] spm_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
input wire [`WordDataBus] bus_rd_data, // Õi¤ß³ö¤·¥Ç©`¥¿
input wire bus_rdy_, // ¥ì¥Ç¥£
input wire bus_grnt_, // ¥Ð¥¹¥°¥é¥ó¥È
output wire bus_req_, // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
output wire [`WordAddrBus] bus_addr, // ¥¢¥É¥ì¥¹
output wire bus_as_, // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
output wire bus_rw, // Õi¤ß£¯ø¤
output wire [`WordDataBus] bus_wr_data, // ø¤Þz¤ß¥Ç©`¥¿
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
input wire [`WordAddrBus] ex_pc, // ¥×¥í¥°¥é¥à¥«¥¦¥ó¥¿
input wire ex_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
input wire ex_br_flag, // ·Ö᪥ե饰
input wire [`MemOpBus] ex_mem_op, // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`WordDataBus] ex_mem_wr_data, // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
input wire [`CtrlOpBus] ex_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
input wire [`RegAddrBus] ex_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
input wire ex_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
input wire [`IsaExpBus] ex_exp_code, // ÀýÍ⥳©`¥É
input wire [`WordDataBus] ex_out, // IÀí½Y¹û
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
output wire [`WordAddrBus] mem_pc, // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
output wire mem_en, // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
output wire mem_br_flag, // ·Ö᪥ե饰
output wire [`CtrlOpBus] mem_ctrl_op, // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
output wire [`RegAddrBus] mem_dst_addr, // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
output wire mem_gpr_we_, // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
output wire [`IsaExpBus] mem_exp_code, // ÀýÍ⥳©`¥É
output wire [`WordDataBus] mem_out // IÀí½Y¹û
);
/********** ÄÚ²¿ÐźŠ**********/
wire [`WordDataBus] rd_data; // Õi¤ß³ö¤·¥Ç©`¥¿
wire [`WordAddrBus] addr; // ¥¢¥É¥ì¥¹
wire as_; // ¥¢¥É¥ì¥¹Óп
wire rw; // Õi¤ß£¯ø¤
wire [`WordDataBus] wr_data; // ø¤Þz¤ß¥Ç©`¥¿
wire [`WordDataBus] out; // ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û
wire miss_align; // ¥ß¥¹¥¢¥é¥¤¥ó
/********** ½Y¹û¤Î¥Õ¥©¥ï©`¥Ç¥£¥ó¥° **********/
assign fwd_data = out;
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹ÖÆÓù¥æ¥Ë¥Ã¥È **********/
mem_ctrl mem_ctrl (
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_mem_op (ex_mem_op), // ¥á¥â¥ê¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_mem_wr_data (ex_mem_wr_data), // ¥á¥â¥êø¤Þz¤ß¥Ç©`¥¿
.ex_out (ex_out), // IÀí½Y¹û
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.rd_data (rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.addr (addr), // ¥¢¥É¥ì¥¹
.as_ (as_), // ¥¢¥É¥ì¥¹Óп
.rw (rw), // Õi¤ß£¯ø¤
.wr_data (wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û **********/
.out (out), // ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û
.miss_align (miss_align) // ¥ß¥¹¥¢¥é¥¤¥ó
);
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
bus_if bus_if (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥åÐźÅ
.busy (busy), // ¥Ó¥¸©`ÐźÅ
/********** CPU¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.addr (addr), // ¥¢¥É¥ì¥¹
.as_ (as_), // ¥¢¥É¥ì¥¹Óп
.rw (rw), // Õi¤ß£¯ø¤
.wr_data (wr_data), // ø¤Þz¤ß¥Ç©`¥¿
.rd_data (rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
/********** ¥¹¥¯¥é¥Ã¥Á¥Ñ¥Ã¥É¥á¥â¥ê¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.spm_rd_data (spm_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.spm_addr (spm_addr), // ¥¢¥É¥ì¥¹
.spm_as_ (spm_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.spm_rw (spm_rw), // Õi¤ß£¯ø¤
.spm_wr_data (spm_wr_data), // ø¤Þz¤ß¥Ç©`¥¿
/********** ¥Ð¥¹¥¤¥ó¥¿¥Õ¥§©`¥¹ **********/
.bus_rd_data (bus_rd_data), // Õi¤ß³ö¤·¥Ç©`¥¿
.bus_rdy_ (bus_rdy_), // ¥ì¥Ç¥£
.bus_grnt_ (bus_grnt_), // ¥Ð¥¹¥°¥é¥ó¥È
.bus_req_ (bus_req_), // ¥Ð¥¹¥ê¥¯¥¨¥¹¥È
.bus_addr (bus_addr), // ¥¢¥É¥ì¥¹
.bus_as_ (bus_as_), // ¥¢¥É¥ì¥¹¥¹¥È¥í©`¥Ö
.bus_rw (bus_rw), // Õi¤ß£¯ø¤
.bus_wr_data (bus_wr_data) // ø¤Þz¤ß¥Ç©`¥¿
);
/********** MEM¥¹¥Æ©`¥¸¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
mem_reg mem_reg (
/********** ¥¯¥í¥Ã¥¯ & ¥ê¥»¥Ã¥È **********/
.clk (clk), // ¥¯¥í¥Ã¥¯
.reset (reset), // ·ÇͬÆڥꥻ¥Ã¥È
/********** ¥á¥â¥ê¥¢¥¯¥»¥¹½Y¹û **********/
.out (out), // ½Y¹û
.miss_align (miss_align), // ¥ß¥¹¥¢¥é¥¤¥ó
/********** ¥Ñ¥¤¥×¥é¥¤¥óÖÆÓùÐźŠ**********/
.stall (stall), // ¥¹¥È©`¥ë
.flush (flush), // ¥Õ¥é¥Ã¥·¥å
/********** EX/MEM¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.ex_pc (ex_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.ex_en (ex_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.ex_br_flag (ex_br_flag), // ·Ö᪥ե饰
.ex_ctrl_op (ex_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.ex_dst_addr (ex_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.ex_gpr_we_ (ex_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.ex_exp_code (ex_exp_code), // ÀýÍ⥳©`¥É
/********** MEM/WB¥Ñ¥¤¥×¥é¥¤¥ó¥ì¥¸¥¹¥¿ **********/
.mem_pc (mem_pc), // ¥×¥í¥°¥é¥ó¥«¥¦¥ó¥¿
.mem_en (mem_en), // ¥Ñ¥¤¥×¥é¥¤¥ó¥Ç©`¥¿¤ÎÓп
.mem_br_flag (mem_br_flag), // ·Ö᪥ե饰
.mem_ctrl_op (mem_ctrl_op), // ÖÆÓù¥ì¥¸¥¹¥¿¥ª¥Ú¥ì©`¥·¥ç¥ó
.mem_dst_addr (mem_dst_addr), // øÓå쥸¥¹¥¿ø¤Þz¤ß¥¢¥É¥ì¥¹
.mem_gpr_we_ (mem_gpr_we_), // øÓå쥸¥¹¥¿ø¤Þz¤ßÓп
.mem_exp_code (mem_exp_code), // ÀýÍ⥳©`¥É
.mem_out (mem_out) // IÀí½Y¹û
);
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2015.1
// Copyright (C) 2015 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="tri_intersect,hls_ip_2015_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=463,HLS_SYN_TPT=none,HLS_SYN_MEM=32,HLS_SYN_DSP=127,HLS_SYN_FF=20827,HLS_SYN_LUT=27149}" *)
module tri_intersect (
ap_clk,
ap_rst_n,
ins_TDATA,
ins_TVALID,
ins_TREADY,
ins_TKEEP,
ins_TSTRB,
ins_TUSER,
ins_TLAST,
ins_TID,
ins_TDEST,
outs_TDATA,
outs_TVALID,
outs_TREADY,
outs_TKEEP,
outs_TSTRB,
outs_TUSER,
outs_TLAST,
outs_TID,
outs_TDEST
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 362'b1;
parameter ap_ST_st2_fsm_1 = 362'b10;
parameter ap_ST_st3_fsm_2 = 362'b100;
parameter ap_ST_st4_fsm_3 = 362'b1000;
parameter ap_ST_st5_fsm_4 = 362'b10000;
parameter ap_ST_st6_fsm_5 = 362'b100000;
parameter ap_ST_st7_fsm_6 = 362'b1000000;
parameter ap_ST_st8_fsm_7 = 362'b10000000;
parameter ap_ST_st9_fsm_8 = 362'b100000000;
parameter ap_ST_st10_fsm_9 = 362'b1000000000;
parameter ap_ST_st11_fsm_10 = 362'b10000000000;
parameter ap_ST_st12_fsm_11 = 362'b100000000000;
parameter ap_ST_st13_fsm_12 = 362'b1000000000000;
parameter ap_ST_st14_fsm_13 = 362'b10000000000000;
parameter ap_ST_st15_fsm_14 = 362'b100000000000000;
parameter ap_ST_st16_fsm_15 = 362'b1000000000000000;
parameter ap_ST_st17_fsm_16 = 362'b10000000000000000;
parameter ap_ST_st18_fsm_17 = 362'b100000000000000000;
parameter ap_ST_st19_fsm_18 = 362'b1000000000000000000;
parameter ap_ST_st20_fsm_19 = 362'b10000000000000000000;
parameter ap_ST_st21_fsm_20 = 362'b100000000000000000000;
parameter ap_ST_st22_fsm_21 = 362'b1000000000000000000000;
parameter ap_ST_st23_fsm_22 = 362'b10000000000000000000000;
parameter ap_ST_st24_fsm_23 = 362'b100000000000000000000000;
parameter ap_ST_st25_fsm_24 = 362'b1000000000000000000000000;
parameter ap_ST_st26_fsm_25 = 362'b10000000000000000000000000;
parameter ap_ST_st27_fsm_26 = 362'b100000000000000000000000000;
parameter ap_ST_st28_fsm_27 = 362'b1000000000000000000000000000;
parameter ap_ST_st29_fsm_28 = 362'b10000000000000000000000000000;
parameter ap_ST_st30_fsm_29 = 362'b100000000000000000000000000000;
parameter ap_ST_st31_fsm_30 = 362'b1000000000000000000000000000000;
parameter ap_ST_st32_fsm_31 = 362'b10000000000000000000000000000000;
parameter ap_ST_st33_fsm_32 = 362'b100000000000000000000000000000000;
parameter ap_ST_st34_fsm_33 = 362'b1000000000000000000000000000000000;
parameter ap_ST_st35_fsm_34 = 362'b10000000000000000000000000000000000;
parameter ap_ST_st36_fsm_35 = 362'b100000000000000000000000000000000000;
parameter ap_ST_st37_fsm_36 = 362'b1000000000000000000000000000000000000;
parameter ap_ST_st38_fsm_37 = 362'b10000000000000000000000000000000000000;
parameter ap_ST_st39_fsm_38 = 362'b100000000000000000000000000000000000000;
parameter ap_ST_st40_fsm_39 = 362'b1000000000000000000000000000000000000000;
parameter ap_ST_st41_fsm_40 = 362'b10000000000000000000000000000000000000000;
parameter ap_ST_st42_fsm_41 = 362'b100000000000000000000000000000000000000000;
parameter ap_ST_st43_fsm_42 = 362'b1000000000000000000000000000000000000000000;
parameter ap_ST_st44_fsm_43 = 362'b10000000000000000000000000000000000000000000;
parameter ap_ST_st45_fsm_44 = 362'b100000000000000000000000000000000000000000000;
parameter ap_ST_st46_fsm_45 = 362'b1000000000000000000000000000000000000000000000;
parameter ap_ST_st47_fsm_46 = 362'b10000000000000000000000000000000000000000000000;
parameter ap_ST_st48_fsm_47 = 362'b100000000000000000000000000000000000000000000000;
parameter ap_ST_st49_fsm_48 = 362'b1000000000000000000000000000000000000000000000000;
parameter ap_ST_st50_fsm_49 = 362'b10000000000000000000000000000000000000000000000000;
parameter ap_ST_st51_fsm_50 = 362'b100000000000000000000000000000000000000000000000000;
parameter ap_ST_st52_fsm_51 = 362'b1000000000000000000000000000000000000000000000000000;
parameter ap_ST_st53_fsm_52 = 362'b10000000000000000000000000000000000000000000000000000;
parameter ap_ST_st54_fsm_53 = 362'b100000000000000000000000000000000000000000000000000000;
parameter ap_ST_st55_fsm_54 = 362'b1000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st56_fsm_55 = 362'b10000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st57_fsm_56 = 362'b100000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st58_fsm_57 = 362'b1000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st59_fsm_58 = 362'b10000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st60_fsm_59 = 362'b100000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st61_fsm_60 = 362'b1000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st62_fsm_61 = 362'b10000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st63_fsm_62 = 362'b100000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st64_fsm_63 = 362'b1000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st65_fsm_64 = 362'b10000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st66_fsm_65 = 362'b100000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st67_fsm_66 = 362'b1000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st68_fsm_67 = 362'b10000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st69_fsm_68 = 362'b100000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st70_fsm_69 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st71_fsm_70 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st72_fsm_71 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st73_fsm_72 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st74_fsm_73 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st75_fsm_74 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st76_fsm_75 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st77_fsm_76 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st78_fsm_77 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st79_fsm_78 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st80_fsm_79 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st81_fsm_80 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st82_fsm_81 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st83_fsm_82 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st84_fsm_83 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st85_fsm_84 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st86_fsm_85 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st87_fsm_86 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st88_fsm_87 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st89_fsm_88 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st90_fsm_89 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st91_fsm_90 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st92_fsm_91 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st93_fsm_92 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st94_fsm_93 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st95_fsm_94 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st96_fsm_95 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st97_fsm_96 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st98_fsm_97 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st99_fsm_98 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st100_fsm_99 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st101_fsm_100 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st102_fsm_101 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st103_fsm_102 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st104_fsm_103 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st105_fsm_104 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st106_fsm_105 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st107_fsm_106 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st108_fsm_107 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st109_fsm_108 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st110_fsm_109 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st111_fsm_110 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st112_fsm_111 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st113_fsm_112 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st114_fsm_113 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st115_fsm_114 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st116_fsm_115 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st117_fsm_116 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st118_fsm_117 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st119_fsm_118 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st120_fsm_119 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st121_fsm_120 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st122_fsm_121 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st123_fsm_122 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st124_fsm_123 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st125_fsm_124 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st126_fsm_125 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st127_fsm_126 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st128_fsm_127 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st129_fsm_128 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st130_fsm_129 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st131_fsm_130 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st132_fsm_131 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st133_fsm_132 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st134_fsm_133 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st135_fsm_134 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st136_fsm_135 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st137_fsm_136 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st138_fsm_137 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st139_fsm_138 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st140_fsm_139 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st141_fsm_140 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st142_fsm_141 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st143_fsm_142 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st144_fsm_143 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st145_fsm_144 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st146_fsm_145 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st147_fsm_146 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st148_fsm_147 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st149_fsm_148 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st150_fsm_149 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st151_fsm_150 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st152_fsm_151 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st153_fsm_152 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st154_fsm_153 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st155_fsm_154 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st156_fsm_155 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st157_fsm_156 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st158_fsm_157 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st159_fsm_158 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st160_fsm_159 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st161_fsm_160 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st162_fsm_161 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st163_fsm_162 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st164_fsm_163 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st165_fsm_164 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st166_fsm_165 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st167_fsm_166 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st168_fsm_167 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st169_fsm_168 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st170_fsm_169 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st171_fsm_170 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st172_fsm_171 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st173_fsm_172 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st174_fsm_173 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st175_fsm_174 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st176_fsm_175 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st177_fsm_176 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st178_fsm_177 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st179_fsm_178 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st180_fsm_179 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st181_fsm_180 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st182_fsm_181 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st183_fsm_182 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st184_fsm_183 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st185_fsm_184 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st186_fsm_185 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st187_fsm_186 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st188_fsm_187 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st189_fsm_188 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st190_fsm_189 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st191_fsm_190 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st192_fsm_191 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st193_fsm_192 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st194_fsm_193 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st195_fsm_194 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st196_fsm_195 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st197_fsm_196 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st198_fsm_197 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st199_fsm_198 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st200_fsm_199 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st201_fsm_200 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st202_fsm_201 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st203_fsm_202 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st204_fsm_203 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st205_fsm_204 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st206_fsm_205 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st207_fsm_206 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st208_fsm_207 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st209_fsm_208 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st210_fsm_209 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st211_fsm_210 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st212_fsm_211 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st213_fsm_212 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st214_fsm_213 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st215_fsm_214 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st216_fsm_215 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st217_fsm_216 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st218_fsm_217 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st219_fsm_218 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st220_fsm_219 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st221_fsm_220 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st222_fsm_221 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st223_fsm_222 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st224_fsm_223 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st225_fsm_224 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st226_fsm_225 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st227_fsm_226 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st228_fsm_227 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st229_fsm_228 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st230_fsm_229 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st231_fsm_230 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st232_fsm_231 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st233_fsm_232 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st234_fsm_233 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st235_fsm_234 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st236_fsm_235 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st237_fsm_236 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st238_fsm_237 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st239_fsm_238 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st240_fsm_239 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st241_fsm_240 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st242_fsm_241 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st243_fsm_242 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st244_fsm_243 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st245_fsm_244 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st246_fsm_245 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st247_fsm_246 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st248_fsm_247 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st249_fsm_248 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st250_fsm_249 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st251_fsm_250 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st252_fsm_251 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st253_fsm_252 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st254_fsm_253 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st255_fsm_254 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st256_fsm_255 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st257_fsm_256 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st258_fsm_257 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st259_fsm_258 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st260_fsm_259 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st261_fsm_260 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st262_fsm_261 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st263_fsm_262 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st264_fsm_263 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st265_fsm_264 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st266_fsm_265 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st267_fsm_266 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st268_fsm_267 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st269_fsm_268 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st270_fsm_269 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st271_fsm_270 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st272_fsm_271 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st273_fsm_272 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st274_fsm_273 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st275_fsm_274 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st276_fsm_275 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st277_fsm_276 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st278_fsm_277 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st279_fsm_278 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st280_fsm_279 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st281_fsm_280 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st282_fsm_281 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st283_fsm_282 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st284_fsm_283 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st285_fsm_284 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st286_fsm_285 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st287_fsm_286 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st288_fsm_287 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st289_fsm_288 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st290_fsm_289 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st291_fsm_290 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st292_fsm_291 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st293_fsm_292 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st294_fsm_293 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st295_fsm_294 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st296_fsm_295 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st297_fsm_296 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st298_fsm_297 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st299_fsm_298 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st300_fsm_299 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_pp0_stg0_fsm_300 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st385_fsm_301 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st386_fsm_302 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st387_fsm_303 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st388_fsm_304 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st389_fsm_305 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st390_fsm_306 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st391_fsm_307 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st392_fsm_308 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st393_fsm_309 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st394_fsm_310 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st395_fsm_311 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st396_fsm_312 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st397_fsm_313 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st398_fsm_314 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st399_fsm_315 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st400_fsm_316 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st401_fsm_317 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st402_fsm_318 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st403_fsm_319 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st404_fsm_320 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st405_fsm_321 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st406_fsm_322 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st407_fsm_323 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st408_fsm_324 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st409_fsm_325 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st410_fsm_326 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st411_fsm_327 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st412_fsm_328 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st413_fsm_329 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st414_fsm_330 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st415_fsm_331 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st416_fsm_332 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st417_fsm_333 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st418_fsm_334 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st419_fsm_335 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st420_fsm_336 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st421_fsm_337 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st422_fsm_338 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st423_fsm_339 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st424_fsm_340 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st425_fsm_341 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st426_fsm_342 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st427_fsm_343 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st428_fsm_344 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st429_fsm_345 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st430_fsm_346 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st431_fsm_347 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st432_fsm_348 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st433_fsm_349 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st434_fsm_350 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st435_fsm_351 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st436_fsm_352 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st437_fsm_353 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st438_fsm_354 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st439_fsm_355 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st440_fsm_356 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st441_fsm_357 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st442_fsm_358 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st443_fsm_359 = 362'b100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st444_fsm_360 = 362'b1000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_ST_st445_fsm_361 = 362'b10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_true = 1'b1;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_48 = 32'b1001000;
parameter ap_const_lv32_4B = 32'b1001011;
parameter ap_const_lv32_5A = 32'b1011010;
parameter ap_const_lv32_69 = 32'b1101001;
parameter ap_const_lv32_78 = 32'b1111000;
parameter ap_const_lv32_87 = 32'b10000111;
parameter ap_const_lv32_96 = 32'b10010110;
parameter ap_const_lv32_A5 = 32'b10100101;
parameter ap_const_lv32_B4 = 32'b10110100;
parameter ap_const_lv32_C3 = 32'b11000011;
parameter ap_const_lv32_D2 = 32'b11010010;
parameter ap_const_lv32_E1 = 32'b11100001;
parameter ap_const_lv32_F0 = 32'b11110000;
parameter ap_const_lv32_FF = 32'b11111111;
parameter ap_const_lv32_10E = 32'b100001110;
parameter ap_const_lv32_11D = 32'b100011101;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_49 = 32'b1001001;
parameter ap_const_lv32_4C = 32'b1001100;
parameter ap_const_lv32_5B = 32'b1011011;
parameter ap_const_lv32_6A = 32'b1101010;
parameter ap_const_lv32_79 = 32'b1111001;
parameter ap_const_lv32_88 = 32'b10001000;
parameter ap_const_lv32_97 = 32'b10010111;
parameter ap_const_lv32_A6 = 32'b10100110;
parameter ap_const_lv32_B5 = 32'b10110101;
parameter ap_const_lv32_C4 = 32'b11000100;
parameter ap_const_lv32_D3 = 32'b11010011;
parameter ap_const_lv32_E2 = 32'b11100010;
parameter ap_const_lv32_F1 = 32'b11110001;
parameter ap_const_lv32_100 = 32'b100000000;
parameter ap_const_lv32_10F = 32'b100001111;
parameter ap_const_lv32_11E = 32'b100011110;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_4D = 32'b1001101;
parameter ap_const_lv32_5C = 32'b1011100;
parameter ap_const_lv32_6B = 32'b1101011;
parameter ap_const_lv32_7A = 32'b1111010;
parameter ap_const_lv32_89 = 32'b10001001;
parameter ap_const_lv32_98 = 32'b10011000;
parameter ap_const_lv32_A7 = 32'b10100111;
parameter ap_const_lv32_B6 = 32'b10110110;
parameter ap_const_lv32_C5 = 32'b11000101;
parameter ap_const_lv32_D4 = 32'b11010100;
parameter ap_const_lv32_E3 = 32'b11100011;
parameter ap_const_lv32_F2 = 32'b11110010;
parameter ap_const_lv32_101 = 32'b100000001;
parameter ap_const_lv32_110 = 32'b100010000;
parameter ap_const_lv32_11F = 32'b100011111;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_4E = 32'b1001110;
parameter ap_const_lv32_5D = 32'b1011101;
parameter ap_const_lv32_6C = 32'b1101100;
parameter ap_const_lv32_7B = 32'b1111011;
parameter ap_const_lv32_8A = 32'b10001010;
parameter ap_const_lv32_99 = 32'b10011001;
parameter ap_const_lv32_A8 = 32'b10101000;
parameter ap_const_lv32_B7 = 32'b10110111;
parameter ap_const_lv32_C6 = 32'b11000110;
parameter ap_const_lv32_D5 = 32'b11010101;
parameter ap_const_lv32_E4 = 32'b11100100;
parameter ap_const_lv32_F3 = 32'b11110011;
parameter ap_const_lv32_102 = 32'b100000010;
parameter ap_const_lv32_111 = 32'b100010001;
parameter ap_const_lv32_120 = 32'b100100000;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_4F = 32'b1001111;
parameter ap_const_lv32_5E = 32'b1011110;
parameter ap_const_lv32_6D = 32'b1101101;
parameter ap_const_lv32_7C = 32'b1111100;
parameter ap_const_lv32_8B = 32'b10001011;
parameter ap_const_lv32_9A = 32'b10011010;
parameter ap_const_lv32_A9 = 32'b10101001;
parameter ap_const_lv32_B8 = 32'b10111000;
parameter ap_const_lv32_C7 = 32'b11000111;
parameter ap_const_lv32_D6 = 32'b11010110;
parameter ap_const_lv32_E5 = 32'b11100101;
parameter ap_const_lv32_F4 = 32'b11110100;
parameter ap_const_lv32_103 = 32'b100000011;
parameter ap_const_lv32_112 = 32'b100010010;
parameter ap_const_lv32_121 = 32'b100100001;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv32_50 = 32'b1010000;
parameter ap_const_lv32_5F = 32'b1011111;
parameter ap_const_lv32_6E = 32'b1101110;
parameter ap_const_lv32_7D = 32'b1111101;
parameter ap_const_lv32_8C = 32'b10001100;
parameter ap_const_lv32_9B = 32'b10011011;
parameter ap_const_lv32_AA = 32'b10101010;
parameter ap_const_lv32_B9 = 32'b10111001;
parameter ap_const_lv32_C8 = 32'b11001000;
parameter ap_const_lv32_D7 = 32'b11010111;
parameter ap_const_lv32_E6 = 32'b11100110;
parameter ap_const_lv32_F5 = 32'b11110101;
parameter ap_const_lv32_104 = 32'b100000100;
parameter ap_const_lv32_113 = 32'b100010011;
parameter ap_const_lv32_122 = 32'b100100010;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_51 = 32'b1010001;
parameter ap_const_lv32_60 = 32'b1100000;
parameter ap_const_lv32_6F = 32'b1101111;
parameter ap_const_lv32_7E = 32'b1111110;
parameter ap_const_lv32_8D = 32'b10001101;
parameter ap_const_lv32_9C = 32'b10011100;
parameter ap_const_lv32_AB = 32'b10101011;
parameter ap_const_lv32_BA = 32'b10111010;
parameter ap_const_lv32_C9 = 32'b11001001;
parameter ap_const_lv32_D8 = 32'b11011000;
parameter ap_const_lv32_E7 = 32'b11100111;
parameter ap_const_lv32_F6 = 32'b11110110;
parameter ap_const_lv32_105 = 32'b100000101;
parameter ap_const_lv32_114 = 32'b100010100;
parameter ap_const_lv32_123 = 32'b100100011;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv32_52 = 32'b1010010;
parameter ap_const_lv32_61 = 32'b1100001;
parameter ap_const_lv32_70 = 32'b1110000;
parameter ap_const_lv32_7F = 32'b1111111;
parameter ap_const_lv32_8E = 32'b10001110;
parameter ap_const_lv32_9D = 32'b10011101;
parameter ap_const_lv32_AC = 32'b10101100;
parameter ap_const_lv32_BB = 32'b10111011;
parameter ap_const_lv32_CA = 32'b11001010;
parameter ap_const_lv32_D9 = 32'b11011001;
parameter ap_const_lv32_E8 = 32'b11101000;
parameter ap_const_lv32_F7 = 32'b11110111;
parameter ap_const_lv32_106 = 32'b100000110;
parameter ap_const_lv32_115 = 32'b100010101;
parameter ap_const_lv32_124 = 32'b100100100;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv32_53 = 32'b1010011;
parameter ap_const_lv32_62 = 32'b1100010;
parameter ap_const_lv32_71 = 32'b1110001;
parameter ap_const_lv32_80 = 32'b10000000;
parameter ap_const_lv32_8F = 32'b10001111;
parameter ap_const_lv32_9E = 32'b10011110;
parameter ap_const_lv32_AD = 32'b10101101;
parameter ap_const_lv32_BC = 32'b10111100;
parameter ap_const_lv32_CB = 32'b11001011;
parameter ap_const_lv32_DA = 32'b11011010;
parameter ap_const_lv32_E9 = 32'b11101001;
parameter ap_const_lv32_F8 = 32'b11111000;
parameter ap_const_lv32_107 = 32'b100000111;
parameter ap_const_lv32_116 = 32'b100010110;
parameter ap_const_lv32_125 = 32'b100100101;
parameter ap_const_lv32_9 = 32'b1001;
parameter ap_const_lv32_54 = 32'b1010100;
parameter ap_const_lv32_63 = 32'b1100011;
parameter ap_const_lv32_72 = 32'b1110010;
parameter ap_const_lv32_81 = 32'b10000001;
parameter ap_const_lv32_90 = 32'b10010000;
parameter ap_const_lv32_9F = 32'b10011111;
parameter ap_const_lv32_AE = 32'b10101110;
parameter ap_const_lv32_BD = 32'b10111101;
parameter ap_const_lv32_CC = 32'b11001100;
parameter ap_const_lv32_DB = 32'b11011011;
parameter ap_const_lv32_EA = 32'b11101010;
parameter ap_const_lv32_F9 = 32'b11111001;
parameter ap_const_lv32_108 = 32'b100001000;
parameter ap_const_lv32_117 = 32'b100010111;
parameter ap_const_lv32_126 = 32'b100100110;
parameter ap_const_lv32_A = 32'b1010;
parameter ap_const_lv32_55 = 32'b1010101;
parameter ap_const_lv32_64 = 32'b1100100;
parameter ap_const_lv32_73 = 32'b1110011;
parameter ap_const_lv32_82 = 32'b10000010;
parameter ap_const_lv32_91 = 32'b10010001;
parameter ap_const_lv32_A0 = 32'b10100000;
parameter ap_const_lv32_AF = 32'b10101111;
parameter ap_const_lv32_BE = 32'b10111110;
parameter ap_const_lv32_CD = 32'b11001101;
parameter ap_const_lv32_DC = 32'b11011100;
parameter ap_const_lv32_EB = 32'b11101011;
parameter ap_const_lv32_FA = 32'b11111010;
parameter ap_const_lv32_109 = 32'b100001001;
parameter ap_const_lv32_118 = 32'b100011000;
parameter ap_const_lv32_127 = 32'b100100111;
parameter ap_const_lv32_B = 32'b1011;
parameter ap_const_lv32_56 = 32'b1010110;
parameter ap_const_lv32_65 = 32'b1100101;
parameter ap_const_lv32_74 = 32'b1110100;
parameter ap_const_lv32_83 = 32'b10000011;
parameter ap_const_lv32_92 = 32'b10010010;
parameter ap_const_lv32_A1 = 32'b10100001;
parameter ap_const_lv32_B0 = 32'b10110000;
parameter ap_const_lv32_BF = 32'b10111111;
parameter ap_const_lv32_CE = 32'b11001110;
parameter ap_const_lv32_DD = 32'b11011101;
parameter ap_const_lv32_EC = 32'b11101100;
parameter ap_const_lv32_FB = 32'b11111011;
parameter ap_const_lv32_10A = 32'b100001010;
parameter ap_const_lv32_119 = 32'b100011001;
parameter ap_const_lv32_128 = 32'b100101000;
parameter ap_const_lv32_C = 32'b1100;
parameter ap_const_lv32_57 = 32'b1010111;
parameter ap_const_lv32_66 = 32'b1100110;
parameter ap_const_lv32_75 = 32'b1110101;
parameter ap_const_lv32_84 = 32'b10000100;
parameter ap_const_lv32_93 = 32'b10010011;
parameter ap_const_lv32_A2 = 32'b10100010;
parameter ap_const_lv32_B1 = 32'b10110001;
parameter ap_const_lv32_C0 = 32'b11000000;
parameter ap_const_lv32_CF = 32'b11001111;
parameter ap_const_lv32_DE = 32'b11011110;
parameter ap_const_lv32_ED = 32'b11101101;
parameter ap_const_lv32_FC = 32'b11111100;
parameter ap_const_lv32_10B = 32'b100001011;
parameter ap_const_lv32_11A = 32'b100011010;
parameter ap_const_lv32_129 = 32'b100101001;
parameter ap_const_lv32_D = 32'b1101;
parameter ap_const_lv32_58 = 32'b1011000;
parameter ap_const_lv32_67 = 32'b1100111;
parameter ap_const_lv32_76 = 32'b1110110;
parameter ap_const_lv32_85 = 32'b10000101;
parameter ap_const_lv32_94 = 32'b10010100;
parameter ap_const_lv32_A3 = 32'b10100011;
parameter ap_const_lv32_B2 = 32'b10110010;
parameter ap_const_lv32_C1 = 32'b11000001;
parameter ap_const_lv32_D0 = 32'b11010000;
parameter ap_const_lv32_DF = 32'b11011111;
parameter ap_const_lv32_EE = 32'b11101110;
parameter ap_const_lv32_FD = 32'b11111101;
parameter ap_const_lv32_10C = 32'b100001100;
parameter ap_const_lv32_11B = 32'b100011011;
parameter ap_const_lv32_12A = 32'b100101010;
parameter ap_const_lv32_47 = 32'b1000111;
parameter ap_const_lv32_12C = 32'b100101100;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_12E = 32'b100101110;
parameter ap_const_lv32_131 = 32'b100110001;
parameter ap_const_lv32_134 = 32'b100110100;
parameter ap_const_lv32_137 = 32'b100110111;
parameter ap_const_lv32_13A = 32'b100111010;
parameter ap_const_lv32_13D = 32'b100111101;
parameter ap_const_lv32_140 = 32'b101000000;
parameter ap_const_lv32_143 = 32'b101000011;
parameter ap_const_lv32_146 = 32'b101000110;
parameter ap_const_lv32_149 = 32'b101001001;
parameter ap_const_lv32_14C = 32'b101001100;
parameter ap_const_lv32_14F = 32'b101001111;
parameter ap_const_lv32_152 = 32'b101010010;
parameter ap_const_lv32_155 = 32'b101010101;
parameter ap_const_lv32_158 = 32'b101011000;
parameter ap_const_lv32_15B = 32'b101011011;
parameter ap_const_lv32_15E = 32'b101011110;
parameter ap_const_lv32_161 = 32'b101100001;
parameter ap_const_lv32_164 = 32'b101100100;
parameter ap_const_lv32_167 = 32'b101100111;
parameter ap_const_lv32_E = 32'b1110;
parameter ap_const_lv32_F = 32'b1111;
parameter ap_const_lv32_10 = 32'b10000;
parameter ap_const_lv32_11 = 32'b10001;
parameter ap_const_lv32_12 = 32'b10010;
parameter ap_const_lv32_13 = 32'b10011;
parameter ap_const_lv32_14 = 32'b10100;
parameter ap_const_lv32_15 = 32'b10101;
parameter ap_const_lv32_16 = 32'b10110;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv32_18 = 32'b11000;
parameter ap_const_lv32_19 = 32'b11001;
parameter ap_const_lv32_1A = 32'b11010;
parameter ap_const_lv32_1B = 32'b11011;
parameter ap_const_lv32_1C = 32'b11100;
parameter ap_const_lv32_1D = 32'b11101;
parameter ap_const_lv32_1E = 32'b11110;
parameter ap_const_lv32_1F = 32'b11111;
parameter ap_const_lv32_20 = 32'b100000;
parameter ap_const_lv32_21 = 32'b100001;
parameter ap_const_lv32_22 = 32'b100010;
parameter ap_const_lv32_23 = 32'b100011;
parameter ap_const_lv32_24 = 32'b100100;
parameter ap_const_lv32_25 = 32'b100101;
parameter ap_const_lv32_26 = 32'b100110;
parameter ap_const_lv32_27 = 32'b100111;
parameter ap_const_lv32_28 = 32'b101000;
parameter ap_const_lv32_29 = 32'b101001;
parameter ap_const_lv32_2A = 32'b101010;
parameter ap_const_lv32_2B = 32'b101011;
parameter ap_const_lv32_2C = 32'b101100;
parameter ap_const_lv32_2D = 32'b101101;
parameter ap_const_lv32_2E = 32'b101110;
parameter ap_const_lv32_2F = 32'b101111;
parameter ap_const_lv32_30 = 32'b110000;
parameter ap_const_lv32_31 = 32'b110001;
parameter ap_const_lv32_32 = 32'b110010;
parameter ap_const_lv32_33 = 32'b110011;
parameter ap_const_lv32_34 = 32'b110100;
parameter ap_const_lv32_35 = 32'b110101;
parameter ap_const_lv32_36 = 32'b110110;
parameter ap_const_lv32_37 = 32'b110111;
parameter ap_const_lv32_38 = 32'b111000;
parameter ap_const_lv32_39 = 32'b111001;
parameter ap_const_lv32_3A = 32'b111010;
parameter ap_const_lv32_3B = 32'b111011;
parameter ap_const_lv32_3C = 32'b111100;
parameter ap_const_lv32_3D = 32'b111101;
parameter ap_const_lv32_3E = 32'b111110;
parameter ap_const_lv32_3F = 32'b111111;
parameter ap_const_lv32_40 = 32'b1000000;
parameter ap_const_lv32_41 = 32'b1000001;
parameter ap_const_lv32_42 = 32'b1000010;
parameter ap_const_lv32_43 = 32'b1000011;
parameter ap_const_lv32_44 = 32'b1000100;
parameter ap_const_lv32_45 = 32'b1000101;
parameter ap_const_lv32_46 = 32'b1000110;
parameter ap_const_lv32_4A = 32'b1001010;
parameter ap_const_lv32_59 = 32'b1011001;
parameter ap_const_lv32_68 = 32'b1101000;
parameter ap_const_lv32_77 = 32'b1110111;
parameter ap_const_lv32_86 = 32'b10000110;
parameter ap_const_lv32_95 = 32'b10010101;
parameter ap_const_lv32_A4 = 32'b10100100;
parameter ap_const_lv32_B3 = 32'b10110011;
parameter ap_const_lv32_C2 = 32'b11000010;
parameter ap_const_lv32_D1 = 32'b11010001;
parameter ap_const_lv32_E0 = 32'b11100000;
parameter ap_const_lv32_EF = 32'b11101111;
parameter ap_const_lv32_12B = 32'b100101011;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv64_10 = 64'b10000;
parameter ap_const_lv64_12 = 64'b10010;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_2 = 64'b10;
parameter ap_const_lv64_4 = 64'b100;
parameter ap_const_lv64_11 = 64'b10001;
parameter ap_const_lv64_13 = 64'b10011;
parameter ap_const_lv64_1 = 64'b1;
parameter ap_const_lv64_3 = 64'b11;
parameter ap_const_lv64_5 = 64'b101;
parameter ap_const_lv64_6 = 64'b110;
parameter ap_const_lv64_7 = 64'b111;
parameter ap_const_lv64_8 = 64'b1000;
parameter ap_const_lv64_9 = 64'b1001;
parameter ap_const_lv64_A = 64'b1010;
parameter ap_const_lv64_B = 64'b1011;
parameter ap_const_lv64_C = 64'b1100;
parameter ap_const_lv64_D = 64'b1101;
parameter ap_const_lv64_E = 64'b1110;
parameter ap_const_lv64_F = 64'b1111;
parameter ap_const_lv32_FE = 32'b11111110;
parameter ap_const_lv32_10D = 32'b100001101;
parameter ap_const_lv32_11C = 32'b100011100;
parameter ap_const_lv32_12F = 32'b100101111;
parameter ap_const_lv32_130 = 32'b100110000;
parameter ap_const_lv32_132 = 32'b100110010;
parameter ap_const_lv32_133 = 32'b100110011;
parameter ap_const_lv32_135 = 32'b100110101;
parameter ap_const_lv32_136 = 32'b100110110;
parameter ap_const_lv32_138 = 32'b100111000;
parameter ap_const_lv32_139 = 32'b100111001;
parameter ap_const_lv32_13B = 32'b100111011;
parameter ap_const_lv32_13C = 32'b100111100;
parameter ap_const_lv32_13E = 32'b100111110;
parameter ap_const_lv32_13F = 32'b100111111;
parameter ap_const_lv32_141 = 32'b101000001;
parameter ap_const_lv32_142 = 32'b101000010;
parameter ap_const_lv32_144 = 32'b101000100;
parameter ap_const_lv32_145 = 32'b101000101;
parameter ap_const_lv32_147 = 32'b101000111;
parameter ap_const_lv32_148 = 32'b101001000;
parameter ap_const_lv32_14A = 32'b101001010;
parameter ap_const_lv32_14B = 32'b101001011;
parameter ap_const_lv32_14D = 32'b101001101;
parameter ap_const_lv32_14E = 32'b101001110;
parameter ap_const_lv32_150 = 32'b101010000;
parameter ap_const_lv32_151 = 32'b101010001;
parameter ap_const_lv32_153 = 32'b101010011;
parameter ap_const_lv32_154 = 32'b101010100;
parameter ap_const_lv32_156 = 32'b101010110;
parameter ap_const_lv32_157 = 32'b101010111;
parameter ap_const_lv32_159 = 32'b101011001;
parameter ap_const_lv32_15A = 32'b101011010;
parameter ap_const_lv32_15C = 32'b101011100;
parameter ap_const_lv32_15D = 32'b101011101;
parameter ap_const_lv32_15F = 32'b101011111;
parameter ap_const_lv32_160 = 32'b101100000;
parameter ap_const_lv32_162 = 32'b101100010;
parameter ap_const_lv32_163 = 32'b101100011;
parameter ap_const_lv32_165 = 32'b101100101;
parameter ap_const_lv32_166 = 32'b101100110;
parameter ap_const_lv32_168 = 32'b101101000;
parameter ap_const_lv32_169 = 32'b101101001;
parameter ap_const_lv32_12D = 32'b100101101;
parameter ap_const_lv32_3F800000 = 32'b111111100000000000000000000000;
parameter ap_const_lv32_1E0 = 32'b111100000;
parameter ap_const_lv32_1FF = 32'b111111111;
parameter ap_const_lv32_200 = 32'b1000000000;
parameter ap_const_lv32_21F = 32'b1000011111;
parameter ap_const_lv32_220 = 32'b1000100000;
parameter ap_const_lv32_23F = 32'b1000111111;
parameter ap_const_lv576_lc_1 = 576'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv32_1DF = 32'b111011111;
parameter ap_const_lv5_14 = 5'b10100;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv32_17F = 32'b101111111;
parameter ap_const_lv32_180 = 32'b110000000;
parameter ap_const_lv32_19F = 32'b110011111;
parameter ap_const_lv32_1A0 = 32'b110100000;
parameter ap_const_lv32_1BF = 32'b110111111;
parameter ap_const_lv32_1C0 = 32'b111000000;
parameter ap_const_lv32_80000000 = 32'b10000000000000000000000000000000;
input ap_clk;
input ap_rst_n;
input [31:0] ins_TDATA;
input ins_TVALID;
output ins_TREADY;
input [3:0] ins_TKEEP;
input [3:0] ins_TSTRB;
input [0:0] ins_TUSER;
input [0:0] ins_TLAST;
input [0:0] ins_TID;
input [0:0] ins_TDEST;
output [31:0] outs_TDATA;
output outs_TVALID;
input outs_TREADY;
output [3:0] outs_TKEEP;
output [3:0] outs_TSTRB;
output [0:0] outs_TUSER;
output [0:0] outs_TLAST;
output [0:0] outs_TID;
output [0:0] outs_TDEST;
reg ins_TREADY;
reg[31:0] outs_TDATA;
reg outs_TVALID;
reg[0:0] outs_TLAST;
reg ap_rst_n_inv;
reg [4:0] i1_reg_418;
reg [31:0] reg_669;
(* fsm_encoding = "none" *) reg [361:0] ap_CS_fsm = 362'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_399;
reg ap_sig_cseq_ST_st73_fsm_72;
reg ap_sig_bdd_410;
reg ap_sig_cseq_ST_st76_fsm_75;
reg ap_sig_bdd_419;
reg ap_sig_cseq_ST_st91_fsm_90;
reg ap_sig_bdd_428;
reg ap_sig_cseq_ST_st106_fsm_105;
reg ap_sig_bdd_437;
reg ap_sig_cseq_ST_st121_fsm_120;
reg ap_sig_bdd_446;
reg ap_sig_cseq_ST_st136_fsm_135;
reg ap_sig_bdd_455;
reg ap_sig_cseq_ST_st151_fsm_150;
reg ap_sig_bdd_464;
reg ap_sig_cseq_ST_st166_fsm_165;
reg ap_sig_bdd_473;
reg ap_sig_cseq_ST_st181_fsm_180;
reg ap_sig_bdd_482;
reg ap_sig_cseq_ST_st196_fsm_195;
reg ap_sig_bdd_491;
reg ap_sig_cseq_ST_st211_fsm_210;
reg ap_sig_bdd_500;
reg ap_sig_cseq_ST_st226_fsm_225;
reg ap_sig_bdd_509;
reg ap_sig_cseq_ST_st241_fsm_240;
reg ap_sig_bdd_518;
reg ap_sig_cseq_ST_st256_fsm_255;
reg ap_sig_bdd_527;
reg ap_sig_cseq_ST_st271_fsm_270;
reg ap_sig_bdd_536;
reg ap_sig_cseq_ST_st286_fsm_285;
reg ap_sig_bdd_545;
reg [31:0] reg_673;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_555;
reg ap_sig_cseq_ST_st74_fsm_73;
reg ap_sig_bdd_563;
reg ap_sig_cseq_ST_st77_fsm_76;
reg ap_sig_bdd_572;
reg ap_sig_cseq_ST_st92_fsm_91;
reg ap_sig_bdd_581;
reg ap_sig_cseq_ST_st107_fsm_106;
reg ap_sig_bdd_590;
reg ap_sig_cseq_ST_st122_fsm_121;
reg ap_sig_bdd_599;
reg ap_sig_cseq_ST_st137_fsm_136;
reg ap_sig_bdd_608;
reg ap_sig_cseq_ST_st152_fsm_151;
reg ap_sig_bdd_617;
reg ap_sig_cseq_ST_st167_fsm_166;
reg ap_sig_bdd_626;
reg ap_sig_cseq_ST_st182_fsm_181;
reg ap_sig_bdd_635;
reg ap_sig_cseq_ST_st197_fsm_196;
reg ap_sig_bdd_644;
reg ap_sig_cseq_ST_st212_fsm_211;
reg ap_sig_bdd_653;
reg ap_sig_cseq_ST_st227_fsm_226;
reg ap_sig_bdd_662;
reg ap_sig_cseq_ST_st242_fsm_241;
reg ap_sig_bdd_671;
reg ap_sig_cseq_ST_st257_fsm_256;
reg ap_sig_bdd_680;
reg ap_sig_cseq_ST_st272_fsm_271;
reg ap_sig_bdd_689;
reg ap_sig_cseq_ST_st287_fsm_286;
reg ap_sig_bdd_698;
reg [31:0] reg_677;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_708;
reg ap_sig_cseq_ST_st78_fsm_77;
reg ap_sig_bdd_716;
reg ap_sig_cseq_ST_st93_fsm_92;
reg ap_sig_bdd_725;
reg ap_sig_cseq_ST_st108_fsm_107;
reg ap_sig_bdd_734;
reg ap_sig_cseq_ST_st123_fsm_122;
reg ap_sig_bdd_743;
reg ap_sig_cseq_ST_st138_fsm_137;
reg ap_sig_bdd_752;
reg ap_sig_cseq_ST_st153_fsm_152;
reg ap_sig_bdd_761;
reg ap_sig_cseq_ST_st168_fsm_167;
reg ap_sig_bdd_770;
reg ap_sig_cseq_ST_st183_fsm_182;
reg ap_sig_bdd_779;
reg ap_sig_cseq_ST_st198_fsm_197;
reg ap_sig_bdd_788;
reg ap_sig_cseq_ST_st213_fsm_212;
reg ap_sig_bdd_797;
reg ap_sig_cseq_ST_st228_fsm_227;
reg ap_sig_bdd_806;
reg ap_sig_cseq_ST_st243_fsm_242;
reg ap_sig_bdd_815;
reg ap_sig_cseq_ST_st258_fsm_257;
reg ap_sig_bdd_824;
reg ap_sig_cseq_ST_st273_fsm_272;
reg ap_sig_bdd_833;
reg ap_sig_cseq_ST_st288_fsm_287;
reg ap_sig_bdd_842;
reg [31:0] reg_681;
reg ap_sig_cseq_ST_st4_fsm_3;
reg ap_sig_bdd_852;
reg ap_sig_cseq_ST_st79_fsm_78;
reg ap_sig_bdd_860;
reg ap_sig_cseq_ST_st94_fsm_93;
reg ap_sig_bdd_869;
reg ap_sig_cseq_ST_st109_fsm_108;
reg ap_sig_bdd_878;
reg ap_sig_cseq_ST_st124_fsm_123;
reg ap_sig_bdd_887;
reg ap_sig_cseq_ST_st139_fsm_138;
reg ap_sig_bdd_896;
reg ap_sig_cseq_ST_st154_fsm_153;
reg ap_sig_bdd_905;
reg ap_sig_cseq_ST_st169_fsm_168;
reg ap_sig_bdd_914;
reg ap_sig_cseq_ST_st184_fsm_183;
reg ap_sig_bdd_923;
reg ap_sig_cseq_ST_st199_fsm_198;
reg ap_sig_bdd_932;
reg ap_sig_cseq_ST_st214_fsm_213;
reg ap_sig_bdd_941;
reg ap_sig_cseq_ST_st229_fsm_228;
reg ap_sig_bdd_950;
reg ap_sig_cseq_ST_st244_fsm_243;
reg ap_sig_bdd_959;
reg ap_sig_cseq_ST_st259_fsm_258;
reg ap_sig_bdd_968;
reg ap_sig_cseq_ST_st274_fsm_273;
reg ap_sig_bdd_977;
reg ap_sig_cseq_ST_st289_fsm_288;
reg ap_sig_bdd_986;
reg [31:0] reg_685;
reg ap_sig_cseq_ST_st5_fsm_4;
reg ap_sig_bdd_996;
reg ap_sig_cseq_ST_st80_fsm_79;
reg ap_sig_bdd_1004;
reg ap_sig_cseq_ST_st95_fsm_94;
reg ap_sig_bdd_1013;
reg ap_sig_cseq_ST_st110_fsm_109;
reg ap_sig_bdd_1022;
reg ap_sig_cseq_ST_st125_fsm_124;
reg ap_sig_bdd_1031;
reg ap_sig_cseq_ST_st140_fsm_139;
reg ap_sig_bdd_1040;
reg ap_sig_cseq_ST_st155_fsm_154;
reg ap_sig_bdd_1049;
reg ap_sig_cseq_ST_st170_fsm_169;
reg ap_sig_bdd_1058;
reg ap_sig_cseq_ST_st185_fsm_184;
reg ap_sig_bdd_1067;
reg ap_sig_cseq_ST_st200_fsm_199;
reg ap_sig_bdd_1076;
reg ap_sig_cseq_ST_st215_fsm_214;
reg ap_sig_bdd_1085;
reg ap_sig_cseq_ST_st230_fsm_229;
reg ap_sig_bdd_1094;
reg ap_sig_cseq_ST_st245_fsm_244;
reg ap_sig_bdd_1103;
reg ap_sig_cseq_ST_st260_fsm_259;
reg ap_sig_bdd_1112;
reg ap_sig_cseq_ST_st275_fsm_274;
reg ap_sig_bdd_1121;
reg ap_sig_cseq_ST_st290_fsm_289;
reg ap_sig_bdd_1130;
reg [31:0] reg_689;
reg ap_sig_cseq_ST_st6_fsm_5;
reg ap_sig_bdd_1140;
reg ap_sig_cseq_ST_st81_fsm_80;
reg ap_sig_bdd_1148;
reg ap_sig_cseq_ST_st96_fsm_95;
reg ap_sig_bdd_1157;
reg ap_sig_cseq_ST_st111_fsm_110;
reg ap_sig_bdd_1166;
reg ap_sig_cseq_ST_st126_fsm_125;
reg ap_sig_bdd_1175;
reg ap_sig_cseq_ST_st141_fsm_140;
reg ap_sig_bdd_1184;
reg ap_sig_cseq_ST_st156_fsm_155;
reg ap_sig_bdd_1193;
reg ap_sig_cseq_ST_st171_fsm_170;
reg ap_sig_bdd_1202;
reg ap_sig_cseq_ST_st186_fsm_185;
reg ap_sig_bdd_1211;
reg ap_sig_cseq_ST_st201_fsm_200;
reg ap_sig_bdd_1220;
reg ap_sig_cseq_ST_st216_fsm_215;
reg ap_sig_bdd_1229;
reg ap_sig_cseq_ST_st231_fsm_230;
reg ap_sig_bdd_1238;
reg ap_sig_cseq_ST_st246_fsm_245;
reg ap_sig_bdd_1247;
reg ap_sig_cseq_ST_st261_fsm_260;
reg ap_sig_bdd_1256;
reg ap_sig_cseq_ST_st276_fsm_275;
reg ap_sig_bdd_1265;
reg ap_sig_cseq_ST_st291_fsm_290;
reg ap_sig_bdd_1274;
reg [31:0] reg_693;
reg ap_sig_cseq_ST_st7_fsm_6;
reg ap_sig_bdd_1284;
reg ap_sig_cseq_ST_st82_fsm_81;
reg ap_sig_bdd_1292;
reg ap_sig_cseq_ST_st97_fsm_96;
reg ap_sig_bdd_1301;
reg ap_sig_cseq_ST_st112_fsm_111;
reg ap_sig_bdd_1310;
reg ap_sig_cseq_ST_st127_fsm_126;
reg ap_sig_bdd_1319;
reg ap_sig_cseq_ST_st142_fsm_141;
reg ap_sig_bdd_1328;
reg ap_sig_cseq_ST_st157_fsm_156;
reg ap_sig_bdd_1337;
reg ap_sig_cseq_ST_st172_fsm_171;
reg ap_sig_bdd_1346;
reg ap_sig_cseq_ST_st187_fsm_186;
reg ap_sig_bdd_1355;
reg ap_sig_cseq_ST_st202_fsm_201;
reg ap_sig_bdd_1364;
reg ap_sig_cseq_ST_st217_fsm_216;
reg ap_sig_bdd_1373;
reg ap_sig_cseq_ST_st232_fsm_231;
reg ap_sig_bdd_1382;
reg ap_sig_cseq_ST_st247_fsm_246;
reg ap_sig_bdd_1391;
reg ap_sig_cseq_ST_st262_fsm_261;
reg ap_sig_bdd_1400;
reg ap_sig_cseq_ST_st277_fsm_276;
reg ap_sig_bdd_1409;
reg ap_sig_cseq_ST_st292_fsm_291;
reg ap_sig_bdd_1418;
reg [31:0] reg_697;
reg ap_sig_cseq_ST_st8_fsm_7;
reg ap_sig_bdd_1428;
reg ap_sig_cseq_ST_st83_fsm_82;
reg ap_sig_bdd_1436;
reg ap_sig_cseq_ST_st98_fsm_97;
reg ap_sig_bdd_1445;
reg ap_sig_cseq_ST_st113_fsm_112;
reg ap_sig_bdd_1454;
reg ap_sig_cseq_ST_st128_fsm_127;
reg ap_sig_bdd_1463;
reg ap_sig_cseq_ST_st143_fsm_142;
reg ap_sig_bdd_1472;
reg ap_sig_cseq_ST_st158_fsm_157;
reg ap_sig_bdd_1481;
reg ap_sig_cseq_ST_st173_fsm_172;
reg ap_sig_bdd_1490;
reg ap_sig_cseq_ST_st188_fsm_187;
reg ap_sig_bdd_1499;
reg ap_sig_cseq_ST_st203_fsm_202;
reg ap_sig_bdd_1508;
reg ap_sig_cseq_ST_st218_fsm_217;
reg ap_sig_bdd_1517;
reg ap_sig_cseq_ST_st233_fsm_232;
reg ap_sig_bdd_1526;
reg ap_sig_cseq_ST_st248_fsm_247;
reg ap_sig_bdd_1535;
reg ap_sig_cseq_ST_st263_fsm_262;
reg ap_sig_bdd_1544;
reg ap_sig_cseq_ST_st278_fsm_277;
reg ap_sig_bdd_1553;
reg ap_sig_cseq_ST_st293_fsm_292;
reg ap_sig_bdd_1562;
reg [31:0] reg_701;
reg ap_sig_cseq_ST_st9_fsm_8;
reg ap_sig_bdd_1572;
reg ap_sig_cseq_ST_st84_fsm_83;
reg ap_sig_bdd_1580;
reg ap_sig_cseq_ST_st99_fsm_98;
reg ap_sig_bdd_1589;
reg ap_sig_cseq_ST_st114_fsm_113;
reg ap_sig_bdd_1598;
reg ap_sig_cseq_ST_st129_fsm_128;
reg ap_sig_bdd_1607;
reg ap_sig_cseq_ST_st144_fsm_143;
reg ap_sig_bdd_1616;
reg ap_sig_cseq_ST_st159_fsm_158;
reg ap_sig_bdd_1625;
reg ap_sig_cseq_ST_st174_fsm_173;
reg ap_sig_bdd_1634;
reg ap_sig_cseq_ST_st189_fsm_188;
reg ap_sig_bdd_1643;
reg ap_sig_cseq_ST_st204_fsm_203;
reg ap_sig_bdd_1652;
reg ap_sig_cseq_ST_st219_fsm_218;
reg ap_sig_bdd_1661;
reg ap_sig_cseq_ST_st234_fsm_233;
reg ap_sig_bdd_1670;
reg ap_sig_cseq_ST_st249_fsm_248;
reg ap_sig_bdd_1679;
reg ap_sig_cseq_ST_st264_fsm_263;
reg ap_sig_bdd_1688;
reg ap_sig_cseq_ST_st279_fsm_278;
reg ap_sig_bdd_1697;
reg ap_sig_cseq_ST_st294_fsm_293;
reg ap_sig_bdd_1706;
reg [31:0] reg_705;
reg ap_sig_cseq_ST_st10_fsm_9;
reg ap_sig_bdd_1716;
reg ap_sig_cseq_ST_st85_fsm_84;
reg ap_sig_bdd_1724;
reg ap_sig_cseq_ST_st100_fsm_99;
reg ap_sig_bdd_1733;
reg ap_sig_cseq_ST_st115_fsm_114;
reg ap_sig_bdd_1742;
reg ap_sig_cseq_ST_st130_fsm_129;
reg ap_sig_bdd_1751;
reg ap_sig_cseq_ST_st145_fsm_144;
reg ap_sig_bdd_1760;
reg ap_sig_cseq_ST_st160_fsm_159;
reg ap_sig_bdd_1769;
reg ap_sig_cseq_ST_st175_fsm_174;
reg ap_sig_bdd_1778;
reg ap_sig_cseq_ST_st190_fsm_189;
reg ap_sig_bdd_1787;
reg ap_sig_cseq_ST_st205_fsm_204;
reg ap_sig_bdd_1796;
reg ap_sig_cseq_ST_st220_fsm_219;
reg ap_sig_bdd_1805;
reg ap_sig_cseq_ST_st235_fsm_234;
reg ap_sig_bdd_1814;
reg ap_sig_cseq_ST_st250_fsm_249;
reg ap_sig_bdd_1823;
reg ap_sig_cseq_ST_st265_fsm_264;
reg ap_sig_bdd_1832;
reg ap_sig_cseq_ST_st280_fsm_279;
reg ap_sig_bdd_1841;
reg ap_sig_cseq_ST_st295_fsm_294;
reg ap_sig_bdd_1850;
reg [31:0] reg_709;
reg ap_sig_cseq_ST_st11_fsm_10;
reg ap_sig_bdd_1860;
reg ap_sig_cseq_ST_st86_fsm_85;
reg ap_sig_bdd_1868;
reg ap_sig_cseq_ST_st101_fsm_100;
reg ap_sig_bdd_1877;
reg ap_sig_cseq_ST_st116_fsm_115;
reg ap_sig_bdd_1886;
reg ap_sig_cseq_ST_st131_fsm_130;
reg ap_sig_bdd_1895;
reg ap_sig_cseq_ST_st146_fsm_145;
reg ap_sig_bdd_1904;
reg ap_sig_cseq_ST_st161_fsm_160;
reg ap_sig_bdd_1913;
reg ap_sig_cseq_ST_st176_fsm_175;
reg ap_sig_bdd_1922;
reg ap_sig_cseq_ST_st191_fsm_190;
reg ap_sig_bdd_1931;
reg ap_sig_cseq_ST_st206_fsm_205;
reg ap_sig_bdd_1940;
reg ap_sig_cseq_ST_st221_fsm_220;
reg ap_sig_bdd_1949;
reg ap_sig_cseq_ST_st236_fsm_235;
reg ap_sig_bdd_1958;
reg ap_sig_cseq_ST_st251_fsm_250;
reg ap_sig_bdd_1967;
reg ap_sig_cseq_ST_st266_fsm_265;
reg ap_sig_bdd_1976;
reg ap_sig_cseq_ST_st281_fsm_280;
reg ap_sig_bdd_1985;
reg ap_sig_cseq_ST_st296_fsm_295;
reg ap_sig_bdd_1994;
reg [31:0] reg_713;
reg ap_sig_cseq_ST_st12_fsm_11;
reg ap_sig_bdd_2004;
reg ap_sig_cseq_ST_st87_fsm_86;
reg ap_sig_bdd_2012;
reg ap_sig_cseq_ST_st102_fsm_101;
reg ap_sig_bdd_2021;
reg ap_sig_cseq_ST_st117_fsm_116;
reg ap_sig_bdd_2030;
reg ap_sig_cseq_ST_st132_fsm_131;
reg ap_sig_bdd_2039;
reg ap_sig_cseq_ST_st147_fsm_146;
reg ap_sig_bdd_2048;
reg ap_sig_cseq_ST_st162_fsm_161;
reg ap_sig_bdd_2057;
reg ap_sig_cseq_ST_st177_fsm_176;
reg ap_sig_bdd_2066;
reg ap_sig_cseq_ST_st192_fsm_191;
reg ap_sig_bdd_2075;
reg ap_sig_cseq_ST_st207_fsm_206;
reg ap_sig_bdd_2084;
reg ap_sig_cseq_ST_st222_fsm_221;
reg ap_sig_bdd_2093;
reg ap_sig_cseq_ST_st237_fsm_236;
reg ap_sig_bdd_2102;
reg ap_sig_cseq_ST_st252_fsm_251;
reg ap_sig_bdd_2111;
reg ap_sig_cseq_ST_st267_fsm_266;
reg ap_sig_bdd_2120;
reg ap_sig_cseq_ST_st282_fsm_281;
reg ap_sig_bdd_2129;
reg ap_sig_cseq_ST_st297_fsm_296;
reg ap_sig_bdd_2138;
reg [31:0] reg_717;
reg ap_sig_cseq_ST_st13_fsm_12;
reg ap_sig_bdd_2148;
reg ap_sig_cseq_ST_st88_fsm_87;
reg ap_sig_bdd_2156;
reg ap_sig_cseq_ST_st103_fsm_102;
reg ap_sig_bdd_2165;
reg ap_sig_cseq_ST_st118_fsm_117;
reg ap_sig_bdd_2174;
reg ap_sig_cseq_ST_st133_fsm_132;
reg ap_sig_bdd_2183;
reg ap_sig_cseq_ST_st148_fsm_147;
reg ap_sig_bdd_2192;
reg ap_sig_cseq_ST_st163_fsm_162;
reg ap_sig_bdd_2201;
reg ap_sig_cseq_ST_st178_fsm_177;
reg ap_sig_bdd_2210;
reg ap_sig_cseq_ST_st193_fsm_192;
reg ap_sig_bdd_2219;
reg ap_sig_cseq_ST_st208_fsm_207;
reg ap_sig_bdd_2228;
reg ap_sig_cseq_ST_st223_fsm_222;
reg ap_sig_bdd_2237;
reg ap_sig_cseq_ST_st238_fsm_237;
reg ap_sig_bdd_2246;
reg ap_sig_cseq_ST_st253_fsm_252;
reg ap_sig_bdd_2255;
reg ap_sig_cseq_ST_st268_fsm_267;
reg ap_sig_bdd_2264;
reg ap_sig_cseq_ST_st283_fsm_282;
reg ap_sig_bdd_2273;
reg ap_sig_cseq_ST_st298_fsm_297;
reg ap_sig_bdd_2282;
reg [31:0] reg_721;
reg ap_sig_cseq_ST_st14_fsm_13;
reg ap_sig_bdd_2292;
reg ap_sig_cseq_ST_st89_fsm_88;
reg ap_sig_bdd_2300;
reg ap_sig_cseq_ST_st104_fsm_103;
reg ap_sig_bdd_2309;
reg ap_sig_cseq_ST_st119_fsm_118;
reg ap_sig_bdd_2318;
reg ap_sig_cseq_ST_st134_fsm_133;
reg ap_sig_bdd_2327;
reg ap_sig_cseq_ST_st149_fsm_148;
reg ap_sig_bdd_2336;
reg ap_sig_cseq_ST_st164_fsm_163;
reg ap_sig_bdd_2345;
reg ap_sig_cseq_ST_st179_fsm_178;
reg ap_sig_bdd_2354;
reg ap_sig_cseq_ST_st194_fsm_193;
reg ap_sig_bdd_2363;
reg ap_sig_cseq_ST_st209_fsm_208;
reg ap_sig_bdd_2372;
reg ap_sig_cseq_ST_st224_fsm_223;
reg ap_sig_bdd_2381;
reg ap_sig_cseq_ST_st239_fsm_238;
reg ap_sig_bdd_2390;
reg ap_sig_cseq_ST_st254_fsm_253;
reg ap_sig_bdd_2399;
reg ap_sig_cseq_ST_st269_fsm_268;
reg ap_sig_bdd_2408;
reg ap_sig_cseq_ST_st284_fsm_283;
reg ap_sig_bdd_2417;
reg ap_sig_cseq_ST_st299_fsm_298;
reg ap_sig_bdd_2426;
wire [575:0] data_array_q0;
reg [575:0] reg_725;
reg ap_sig_cseq_ST_st72_fsm_71;
reg ap_sig_bdd_2437;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it2;
reg ap_reg_ppiten_pp0_it0 = 1'b0;
reg ap_reg_ppiten_pp0_it1 = 1'b0;
reg ap_reg_ppiten_pp0_it2 = 1'b0;
reg ap_reg_ppiten_pp0_it3 = 1'b0;
reg ap_reg_ppiten_pp0_it4 = 1'b0;
reg ap_reg_ppiten_pp0_it5 = 1'b0;
reg ap_reg_ppiten_pp0_it6 = 1'b0;
reg ap_reg_ppiten_pp0_it7 = 1'b0;
reg ap_reg_ppiten_pp0_it8 = 1'b0;
reg ap_reg_ppiten_pp0_it9 = 1'b0;
reg ap_reg_ppiten_pp0_it10 = 1'b0;
reg ap_reg_ppiten_pp0_it11 = 1'b0;
reg ap_reg_ppiten_pp0_it12 = 1'b0;
reg ap_reg_ppiten_pp0_it13 = 1'b0;
reg ap_reg_ppiten_pp0_it14 = 1'b0;
reg ap_reg_ppiten_pp0_it15 = 1'b0;
reg ap_reg_ppiten_pp0_it16 = 1'b0;
reg ap_reg_ppiten_pp0_it17 = 1'b0;
reg ap_reg_ppiten_pp0_it18 = 1'b0;
reg ap_reg_ppiten_pp0_it19 = 1'b0;
reg ap_reg_ppiten_pp0_it20 = 1'b0;
reg ap_reg_ppiten_pp0_it21 = 1'b0;
reg ap_reg_ppiten_pp0_it22 = 1'b0;
reg ap_reg_ppiten_pp0_it23 = 1'b0;
reg ap_reg_ppiten_pp0_it24 = 1'b0;
reg ap_reg_ppiten_pp0_it25 = 1'b0;
reg ap_reg_ppiten_pp0_it26 = 1'b0;
reg ap_reg_ppiten_pp0_it27 = 1'b0;
reg ap_reg_ppiten_pp0_it28 = 1'b0;
reg ap_reg_ppiten_pp0_it29 = 1'b0;
reg ap_reg_ppiten_pp0_it30 = 1'b0;
reg ap_reg_ppiten_pp0_it31 = 1'b0;
reg ap_reg_ppiten_pp0_it32 = 1'b0;
reg ap_reg_ppiten_pp0_it33 = 1'b0;
reg ap_reg_ppiten_pp0_it34 = 1'b0;
reg ap_reg_ppiten_pp0_it35 = 1'b0;
reg ap_reg_ppiten_pp0_it36 = 1'b0;
reg ap_reg_ppiten_pp0_it37 = 1'b0;
reg ap_reg_ppiten_pp0_it38 = 1'b0;
reg ap_reg_ppiten_pp0_it39 = 1'b0;
reg ap_reg_ppiten_pp0_it40 = 1'b0;
reg ap_reg_ppiten_pp0_it41 = 1'b0;
reg ap_reg_ppiten_pp0_it42 = 1'b0;
reg ap_reg_ppiten_pp0_it43 = 1'b0;
reg ap_reg_ppiten_pp0_it44 = 1'b0;
reg ap_reg_ppiten_pp0_it45 = 1'b0;
reg ap_reg_ppiten_pp0_it46 = 1'b0;
reg ap_reg_ppiten_pp0_it47 = 1'b0;
reg ap_reg_ppiten_pp0_it48 = 1'b0;
reg ap_reg_ppiten_pp0_it49 = 1'b0;
reg ap_reg_ppiten_pp0_it50 = 1'b0;
reg ap_reg_ppiten_pp0_it51 = 1'b0;
reg ap_reg_ppiten_pp0_it52 = 1'b0;
reg ap_reg_ppiten_pp0_it53 = 1'b0;
reg ap_reg_ppiten_pp0_it54 = 1'b0;
reg ap_reg_ppiten_pp0_it55 = 1'b0;
reg ap_reg_ppiten_pp0_it56 = 1'b0;
reg ap_reg_ppiten_pp0_it57 = 1'b0;
reg ap_reg_ppiten_pp0_it58 = 1'b0;
reg ap_reg_ppiten_pp0_it59 = 1'b0;
reg ap_reg_ppiten_pp0_it60 = 1'b0;
reg ap_reg_ppiten_pp0_it61 = 1'b0;
reg ap_reg_ppiten_pp0_it62 = 1'b0;
reg ap_reg_ppiten_pp0_it63 = 1'b0;
reg ap_reg_ppiten_pp0_it64 = 1'b0;
reg ap_reg_ppiten_pp0_it65 = 1'b0;
reg ap_reg_ppiten_pp0_it66 = 1'b0;
reg ap_reg_ppiten_pp0_it67 = 1'b0;
reg ap_reg_ppiten_pp0_it68 = 1'b0;
reg ap_reg_ppiten_pp0_it69 = 1'b0;
reg ap_reg_ppiten_pp0_it70 = 1'b0;
reg ap_reg_ppiten_pp0_it71 = 1'b0;
reg ap_reg_ppiten_pp0_it72 = 1'b0;
reg ap_reg_ppiten_pp0_it73 = 1'b0;
reg ap_reg_ppiten_pp0_it74 = 1'b0;
reg ap_reg_ppiten_pp0_it75 = 1'b0;
reg ap_reg_ppiten_pp0_it76 = 1'b0;
reg ap_reg_ppiten_pp0_it77 = 1'b0;
reg ap_reg_ppiten_pp0_it78 = 1'b0;
reg ap_reg_ppiten_pp0_it79 = 1'b0;
reg ap_reg_ppiten_pp0_it80 = 1'b0;
reg ap_reg_ppiten_pp0_it81 = 1'b0;
reg ap_reg_ppiten_pp0_it82 = 1'b0;
reg ap_reg_ppiten_pp0_it83 = 1'b0;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it3;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it4;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it5;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it6;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it7;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it8;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it9;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it10;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it11;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it12;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it13;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it14;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it15;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it16;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it17;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it18;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it19;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it20;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it21;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it22;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it23;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it24;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it25;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it26;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it27;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it28;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it29;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it30;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it31;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it32;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it33;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it34;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it35;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it36;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it37;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it38;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it39;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it40;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it41;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it42;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it43;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it44;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it45;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it46;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it47;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it48;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it49;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it50;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it51;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it52;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it53;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it54;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it55;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it56;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it57;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it58;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it59;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it60;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it61;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it62;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it63;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it64;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it65;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it66;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it67;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it68;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it69;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it70;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it71;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it72;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it73;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it74;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it75;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it76;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it77;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it78;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it79;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it80;
reg [575:0] ap_reg_ppstg_reg_725_pp0_it81;
reg ap_sig_cseq_ST_pp0_stg0_fsm_300;
reg ap_sig_bdd_2694;
reg [0:0] exitcond2_reg_3854;
reg [31:0] reg_729;
reg ap_sig_cseq_ST_st386_fsm_302;
reg ap_sig_bdd_2708;
reg ap_sig_ioackin_outs_TREADY;
reg ap_sig_cseq_ST_st389_fsm_305;
reg ap_sig_bdd_2719;
reg ap_sig_cseq_ST_st392_fsm_308;
reg ap_sig_bdd_2728;
reg ap_sig_cseq_ST_st395_fsm_311;
reg ap_sig_bdd_2737;
reg ap_sig_cseq_ST_st398_fsm_314;
reg ap_sig_bdd_2746;
reg ap_sig_cseq_ST_st401_fsm_317;
reg ap_sig_bdd_2755;
reg ap_sig_cseq_ST_st404_fsm_320;
reg ap_sig_bdd_2764;
reg ap_sig_cseq_ST_st407_fsm_323;
reg ap_sig_bdd_2773;
reg ap_sig_cseq_ST_st410_fsm_326;
reg ap_sig_bdd_2782;
reg ap_sig_cseq_ST_st413_fsm_329;
reg ap_sig_bdd_2791;
reg ap_sig_cseq_ST_st416_fsm_332;
reg ap_sig_bdd_2800;
reg ap_sig_cseq_ST_st419_fsm_335;
reg ap_sig_bdd_2809;
reg ap_sig_cseq_ST_st422_fsm_338;
reg ap_sig_bdd_2818;
reg ap_sig_cseq_ST_st425_fsm_341;
reg ap_sig_bdd_2827;
reg ap_sig_cseq_ST_st428_fsm_344;
reg ap_sig_bdd_2836;
reg ap_sig_cseq_ST_st431_fsm_347;
reg ap_sig_bdd_2845;
reg ap_sig_cseq_ST_st434_fsm_350;
reg ap_sig_bdd_2854;
reg ap_sig_cseq_ST_st437_fsm_353;
reg ap_sig_bdd_2863;
reg ap_sig_cseq_ST_st440_fsm_356;
reg ap_sig_bdd_2872;
reg ap_sig_cseq_ST_st443_fsm_359;
reg ap_sig_bdd_2881;
reg [31:0] reg_733;
reg [31:0] ins_data_val14_reg_3415;
reg ap_sig_cseq_ST_st15_fsm_14;
reg ap_sig_bdd_2893;
reg [31:0] ins_data_val15_reg_3420;
reg ap_sig_cseq_ST_st16_fsm_15;
reg ap_sig_bdd_2902;
reg [31:0] ins_data_val16_reg_3425;
reg ap_sig_cseq_ST_st17_fsm_16;
reg ap_sig_bdd_2911;
reg [31:0] ins_data_val17_reg_3430;
reg ap_sig_cseq_ST_st18_fsm_17;
reg ap_sig_bdd_2920;
reg [31:0] ins_data_val18_reg_3435;
reg ap_sig_cseq_ST_st19_fsm_18;
reg ap_sig_bdd_2929;
reg [31:0] ins_data_val19_reg_3440;
reg ap_sig_cseq_ST_st20_fsm_19;
reg ap_sig_bdd_2938;
reg [31:0] ins_data_val20_reg_3445;
reg ap_sig_cseq_ST_st21_fsm_20;
reg ap_sig_bdd_2947;
reg [31:0] ins_data_val21_reg_3450;
reg ap_sig_cseq_ST_st22_fsm_21;
reg ap_sig_bdd_2956;
reg [31:0] ins_data_val22_reg_3455;
reg ap_sig_cseq_ST_st23_fsm_22;
reg ap_sig_bdd_2965;
reg [31:0] ins_data_val23_reg_3460;
reg ap_sig_cseq_ST_st24_fsm_23;
reg ap_sig_bdd_2974;
reg [31:0] ins_data_val24_reg_3465;
reg ap_sig_cseq_ST_st25_fsm_24;
reg ap_sig_bdd_2983;
reg [31:0] ins_data_val25_reg_3470;
reg ap_sig_cseq_ST_st26_fsm_25;
reg ap_sig_bdd_2992;
reg [31:0] ins_data_val26_reg_3475;
reg ap_sig_cseq_ST_st27_fsm_26;
reg ap_sig_bdd_3001;
reg [31:0] ins_data_val27_reg_3480;
reg ap_sig_cseq_ST_st28_fsm_27;
reg ap_sig_bdd_3010;
reg [31:0] ins_data_val28_reg_3485;
reg ap_sig_cseq_ST_st29_fsm_28;
reg ap_sig_bdd_3019;
reg [31:0] ins_data_val29_reg_3490;
reg ap_sig_cseq_ST_st30_fsm_29;
reg ap_sig_bdd_3028;
reg [31:0] ins_data_val30_reg_3495;
reg ap_sig_cseq_ST_st31_fsm_30;
reg ap_sig_bdd_3037;
reg [31:0] ins_data_val31_reg_3500;
reg ap_sig_cseq_ST_st32_fsm_31;
reg ap_sig_bdd_3046;
reg [31:0] ins_data_val32_reg_3505;
reg ap_sig_cseq_ST_st33_fsm_32;
reg ap_sig_bdd_3055;
reg [31:0] ins_data_val33_reg_3510;
reg ap_sig_cseq_ST_st34_fsm_33;
reg ap_sig_bdd_3064;
reg [31:0] ins_data_val34_reg_3515;
reg ap_sig_cseq_ST_st35_fsm_34;
reg ap_sig_bdd_3073;
reg [31:0] ins_data_val35_reg_3520;
reg ap_sig_cseq_ST_st36_fsm_35;
reg ap_sig_bdd_3082;
reg [31:0] ins_data_val36_reg_3525;
reg ap_sig_cseq_ST_st37_fsm_36;
reg ap_sig_bdd_3091;
reg [31:0] ins_data_val37_reg_3530;
reg ap_sig_cseq_ST_st38_fsm_37;
reg ap_sig_bdd_3100;
reg [31:0] ins_data_val38_reg_3535;
reg ap_sig_cseq_ST_st39_fsm_38;
reg ap_sig_bdd_3109;
reg [31:0] ins_data_val39_reg_3540;
reg ap_sig_cseq_ST_st40_fsm_39;
reg ap_sig_bdd_3118;
reg [31:0] ins_data_val40_reg_3545;
reg ap_sig_cseq_ST_st41_fsm_40;
reg ap_sig_bdd_3127;
reg [31:0] ins_data_val41_reg_3550;
reg ap_sig_cseq_ST_st42_fsm_41;
reg ap_sig_bdd_3136;
reg [31:0] ins_data_val42_reg_3555;
reg ap_sig_cseq_ST_st43_fsm_42;
reg ap_sig_bdd_3145;
reg [31:0] ins_data_val43_reg_3560;
reg ap_sig_cseq_ST_st44_fsm_43;
reg ap_sig_bdd_3154;
reg [31:0] ins_data_val44_reg_3565;
reg ap_sig_cseq_ST_st45_fsm_44;
reg ap_sig_bdd_3163;
reg [31:0] ins_data_val45_reg_3570;
reg ap_sig_cseq_ST_st46_fsm_45;
reg ap_sig_bdd_3172;
reg [31:0] ins_data_val46_reg_3575;
reg ap_sig_cseq_ST_st47_fsm_46;
reg ap_sig_bdd_3181;
reg [31:0] ins_data_val47_reg_3580;
reg ap_sig_cseq_ST_st48_fsm_47;
reg ap_sig_bdd_3190;
reg [31:0] ins_data_val48_reg_3585;
reg ap_sig_cseq_ST_st49_fsm_48;
reg ap_sig_bdd_3199;
reg [31:0] ins_data_val49_reg_3590;
reg ap_sig_cseq_ST_st50_fsm_49;
reg ap_sig_bdd_3208;
reg [31:0] ins_data_val50_reg_3595;
reg ap_sig_cseq_ST_st51_fsm_50;
reg ap_sig_bdd_3217;
reg [31:0] ins_data_val51_reg_3600;
reg ap_sig_cseq_ST_st52_fsm_51;
reg ap_sig_bdd_3226;
reg [31:0] ins_data_val52_reg_3605;
reg ap_sig_cseq_ST_st53_fsm_52;
reg ap_sig_bdd_3235;
reg [31:0] ins_data_val53_reg_3610;
reg ap_sig_cseq_ST_st54_fsm_53;
reg ap_sig_bdd_3244;
reg [31:0] ins_data_val54_reg_3615;
reg ap_sig_cseq_ST_st55_fsm_54;
reg ap_sig_bdd_3253;
reg [31:0] ins_data_val55_reg_3620;
reg ap_sig_cseq_ST_st56_fsm_55;
reg ap_sig_bdd_3262;
reg [31:0] ins_data_val56_reg_3625;
reg ap_sig_cseq_ST_st57_fsm_56;
reg ap_sig_bdd_3271;
reg [31:0] ins_data_val57_reg_3630;
reg ap_sig_cseq_ST_st58_fsm_57;
reg ap_sig_bdd_3280;
reg [31:0] ins_data_val58_reg_3635;
reg ap_sig_cseq_ST_st59_fsm_58;
reg ap_sig_bdd_3289;
reg [31:0] ins_data_val59_reg_3640;
reg ap_sig_cseq_ST_st60_fsm_59;
reg ap_sig_bdd_3298;
reg [31:0] ins_data_val60_reg_3645;
reg ap_sig_cseq_ST_st61_fsm_60;
reg ap_sig_bdd_3307;
reg [31:0] ins_data_val61_reg_3650;
reg ap_sig_cseq_ST_st62_fsm_61;
reg ap_sig_bdd_3316;
reg [31:0] ins_data_val62_reg_3655;
reg ap_sig_cseq_ST_st63_fsm_62;
reg ap_sig_bdd_3325;
reg [31:0] ins_data_val63_reg_3660;
reg ap_sig_cseq_ST_st64_fsm_63;
reg ap_sig_bdd_3334;
reg [31:0] ins_data_val64_reg_3665;
reg ap_sig_cseq_ST_st65_fsm_64;
reg ap_sig_bdd_3343;
reg [31:0] ins_data_val65_reg_3670;
reg ap_sig_cseq_ST_st66_fsm_65;
reg ap_sig_bdd_3352;
reg [31:0] ins_data_val66_reg_3675;
reg ap_sig_cseq_ST_st67_fsm_66;
reg ap_sig_bdd_3361;
reg [31:0] ins_data_val67_reg_3680;
reg ap_sig_cseq_ST_st68_fsm_67;
reg ap_sig_bdd_3370;
reg [31:0] ins_data_val68_reg_3685;
reg ap_sig_cseq_ST_st69_fsm_68;
reg ap_sig_bdd_3379;
reg [31:0] ins_data_val69_reg_3690;
reg ap_sig_cseq_ST_st70_fsm_69;
reg ap_sig_bdd_3388;
reg [31:0] ins_data_val70_reg_3695;
reg ap_sig_cseq_ST_st71_fsm_70;
reg ap_sig_bdd_3397;
wire [4:0] data_array_addr_16_gep_fu_244_p3;
reg [4:0] data_array_addr_16_reg_3700;
reg [31:0] ins_data_val71_reg_3706;
wire [4:0] data_array_addr_18_gep_fu_256_p3;
reg [4:0] data_array_addr_18_reg_3711;
wire [4:0] data_array_addr_gep_fu_264_p3;
reg [4:0] data_array_addr_reg_3717;
reg [575:0] data_array_load_2_reg_3722;
wire [4:0] data_array_addr_2_gep_fu_272_p3;
reg [4:0] data_array_addr_2_reg_3727;
wire [4:0] data_array_addr_4_gep_fu_280_p3;
reg [4:0] data_array_addr_4_reg_3732;
reg ap_sig_cseq_ST_st75_fsm_74;
reg ap_sig_bdd_3417;
wire [4:0] data_array_addr_17_gep_fu_288_p3;
reg [4:0] data_array_addr_17_reg_3737;
reg [575:0] data_array_load_1_reg_3743;
wire [4:0] data_array_addr_19_gep_fu_296_p3;
reg [4:0] data_array_addr_19_reg_3748;
wire [4:0] data_array_addr_1_gep_fu_304_p3;
reg [4:0] data_array_addr_1_reg_3754;
reg [575:0] data_array_load_3_reg_3759;
wire [4:0] data_array_addr_3_gep_fu_312_p3;
reg [4:0] data_array_addr_3_reg_3764;
wire [4:0] data_array_addr_5_gep_fu_320_p3;
reg [4:0] data_array_addr_5_reg_3769;
reg ap_sig_cseq_ST_st90_fsm_89;
reg ap_sig_bdd_3437;
wire [4:0] data_array_addr_6_gep_fu_328_p3;
reg [4:0] data_array_addr_6_reg_3774;
reg ap_sig_cseq_ST_st105_fsm_104;
reg ap_sig_bdd_3447;
wire [4:0] data_array_addr_7_gep_fu_336_p3;
reg [4:0] data_array_addr_7_reg_3779;
reg ap_sig_cseq_ST_st120_fsm_119;
reg ap_sig_bdd_3457;
wire [4:0] data_array_addr_8_gep_fu_344_p3;
reg [4:0] data_array_addr_8_reg_3784;
reg ap_sig_cseq_ST_st135_fsm_134;
reg ap_sig_bdd_3467;
wire [4:0] data_array_addr_9_gep_fu_352_p3;
reg [4:0] data_array_addr_9_reg_3789;
reg ap_sig_cseq_ST_st150_fsm_149;
reg ap_sig_bdd_3477;
wire [4:0] data_array_addr_10_gep_fu_360_p3;
reg [4:0] data_array_addr_10_reg_3794;
reg ap_sig_cseq_ST_st165_fsm_164;
reg ap_sig_bdd_3487;
wire [4:0] data_array_addr_11_gep_fu_368_p3;
reg [4:0] data_array_addr_11_reg_3799;
reg ap_sig_cseq_ST_st180_fsm_179;
reg ap_sig_bdd_3497;
wire [4:0] data_array_addr_12_gep_fu_376_p3;
reg [4:0] data_array_addr_12_reg_3804;
reg ap_sig_cseq_ST_st195_fsm_194;
reg ap_sig_bdd_3507;
wire [4:0] data_array_addr_13_gep_fu_384_p3;
reg [4:0] data_array_addr_13_reg_3809;
reg ap_sig_cseq_ST_st210_fsm_209;
reg ap_sig_bdd_3517;
wire [4:0] data_array_addr_14_gep_fu_392_p3;
reg [4:0] data_array_addr_14_reg_3814;
reg ap_sig_cseq_ST_st225_fsm_224;
reg ap_sig_bdd_3527;
wire [4:0] data_array_addr_15_gep_fu_400_p3;
reg [4:0] data_array_addr_15_reg_3819;
reg ap_sig_cseq_ST_st240_fsm_239;
reg ap_sig_bdd_3537;
reg [3:0] ins_keep_V_val_reg_3824;
reg ap_sig_cseq_ST_st300_fsm_299;
reg ap_sig_bdd_3547;
reg [3:0] ins_strb_V_val_reg_3829;
reg [0:0] ins_user_V_val_reg_3834;
reg [0:0] ins_last_V_val_reg_3839;
reg [0:0] ins_id_V_val_reg_3844;
reg [0:0] ins_dest_V_val_reg_3849;
wire [0:0] exitcond2_fu_2840_p2;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it1;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it2;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it3;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it4;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it5;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it6;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it7;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it8;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it9;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it10;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it11;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it12;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it13;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it14;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it15;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it16;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it17;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it18;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it19;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it20;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it21;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it22;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it23;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it24;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it25;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it26;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it27;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it28;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it29;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it30;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it31;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it32;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it33;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it34;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it35;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it36;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it37;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it38;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it39;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it40;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it41;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it42;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it43;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it44;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it45;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it46;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it47;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it48;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it49;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it50;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it51;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it52;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it53;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it54;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it55;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it56;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it57;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it58;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it59;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it60;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it61;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it62;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it63;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it64;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it65;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it66;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it67;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it68;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it69;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it70;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it71;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it72;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it73;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it74;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it75;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it76;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it77;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it78;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it79;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it80;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it81;
reg [0:0] ap_reg_ppstg_exitcond2_reg_3854_pp0_it82;
wire [4:0] i_fu_2846_p2;
reg [4:0] data_array_addr_20_reg_3863;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81;
reg [4:0] ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82;
wire [31:0] tmp_22_fu_2857_p1;
reg [31:0] tmp_22_reg_3869;
reg [31:0] v0y_assign_new_reg_3874;
reg [31:0] v0z_assign_new_reg_3879;
reg [31:0] v1x_assign_new_reg_3884;
reg [31:0] v1y_assign_new_reg_3889;
reg [31:0] v1z_assign_new_reg_3894;
reg [31:0] v2x_assign_new_reg_3899;
reg [31:0] v2y_assign_new_reg_3904;
reg [31:0] v2z_assign_new_reg_3909;
reg [31:0] rdx_assign_new_reg_3914;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9;
reg [31:0] ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10;
reg [31:0] rdy_assign_new_reg_3919;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9;
reg [31:0] ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10;
reg [31:0] rdz_assign_new_reg_3924;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9;
reg [31:0] ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10;
reg [31:0] rex_assign_new_reg_3929;
reg [31:0] rey_assign_new_reg_3934;
reg [31:0] rez_assign_new_reg_3939;
wire [31:0] v0x_assign4_fu_3001_p1;
wire [31:0] v0y_assign_fu_3007_p1;
wire [31:0] v0z_assign_fu_3013_p1;
wire [31:0] grp_fu_430_p2;
reg [31:0] a_reg_4010;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it11;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it12;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it13;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it14;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it15;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it16;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it17;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it18;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it19;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it20;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it21;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it22;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it23;
reg [31:0] ap_reg_ppstg_a_reg_4010_pp0_it24;
wire [31:0] grp_fu_434_p2;
reg [31:0] b_reg_4017;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it11;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it12;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it13;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it14;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it15;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it16;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it17;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it18;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it19;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it20;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it21;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it22;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it23;
reg [31:0] ap_reg_ppstg_b_reg_4017_pp0_it24;
wire [31:0] grp_fu_438_p2;
reg [31:0] c_reg_4024;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it11;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it12;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it13;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it14;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it15;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it16;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it17;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it18;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it19;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it20;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it21;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it22;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it23;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it24;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it25;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it26;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it27;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it28;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it29;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it30;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it31;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it32;
reg [31:0] ap_reg_ppstg_c_reg_4024_pp0_it33;
wire [31:0] grp_fu_442_p2;
reg [31:0] d_reg_4031;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it11;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it12;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it13;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it14;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it15;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it16;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it17;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it18;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it19;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it20;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it21;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it22;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it23;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it24;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it25;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it26;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it27;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it28;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it29;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it30;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it31;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it32;
reg [31:0] ap_reg_ppstg_d_reg_4031_pp0_it33;
wire [31:0] grp_fu_446_p2;
reg [31:0] e_reg_4038;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it11;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it12;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it13;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it14;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it15;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it16;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it17;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it18;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it19;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it20;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it21;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it22;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it23;
reg [31:0] ap_reg_ppstg_e_reg_4038_pp0_it24;
wire [31:0] grp_fu_450_p2;
reg [31:0] f_reg_4045;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it11;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it12;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it13;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it14;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it15;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it16;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it17;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it18;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it19;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it20;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it21;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it22;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it23;
reg [31:0] ap_reg_ppstg_f_reg_4045_pp0_it24;
wire [31:0] grp_fu_454_p2;
reg [31:0] j_reg_4052;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it11;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it12;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it13;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it14;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it15;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it16;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it17;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it18;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it19;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it20;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it21;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it22;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it23;
reg [31:0] ap_reg_ppstg_j_reg_4052_pp0_it24;
wire [31:0] grp_fu_458_p2;
reg [31:0] k_reg_4059;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it11;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it12;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it13;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it14;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it15;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it16;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it17;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it18;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it19;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it20;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it21;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it22;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it23;
reg [31:0] ap_reg_ppstg_k_reg_4059_pp0_it24;
wire [31:0] grp_fu_462_p2;
reg [31:0] l_reg_4066;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it11;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it12;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it13;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it14;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it15;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it16;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it17;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it18;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it19;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it20;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it21;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it22;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it23;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it24;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it25;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it26;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it27;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it28;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it29;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it30;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it31;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it32;
reg [31:0] ap_reg_ppstg_l_reg_4066_pp0_it33;
wire [31:0] g_fu_3055_p1;
reg [31:0] g_reg_4073;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it12;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it13;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it14;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it15;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it16;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it17;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it18;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it19;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it20;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it21;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it22;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it23;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it24;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it25;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it26;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it27;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it28;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it29;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it30;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it31;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it32;
reg [31:0] ap_reg_ppstg_g_reg_4073_pp0_it33;
wire [31:0] h_fu_3059_p1;
reg [31:0] h_reg_4080;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it12;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it13;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it14;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it15;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it16;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it17;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it18;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it19;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it20;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it21;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it22;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it23;
reg [31:0] ap_reg_ppstg_h_reg_4080_pp0_it24;
wire [31:0] i_1_fu_3063_p1;
reg [31:0] i_1_reg_4087;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it12;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it13;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it14;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it15;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it16;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it17;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it18;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it19;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it20;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it21;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it22;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it23;
reg [31:0] ap_reg_ppstg_i_1_reg_4087_pp0_it24;
wire [31:0] grp_fu_522_p2;
reg [31:0] tmp_i_reg_4094;
wire [31:0] grp_fu_526_p2;
reg [31:0] tmp_i_311_reg_4099;
wire [31:0] grp_fu_530_p2;
reg [31:0] tmp_3_i_reg_4104;
wire [31:0] grp_fu_534_p2;
reg [31:0] tmp_4_i_reg_4109;
wire [31:0] grp_fu_538_p2;
reg [31:0] tmp_12_i_reg_4114;
wire [31:0] grp_fu_542_p2;
reg [31:0] tmp_13_i_reg_4119;
wire [31:0] grp_fu_546_p2;
reg [31:0] tmp_16_i_reg_4124;
wire [31:0] grp_fu_550_p2;
reg [31:0] tmp_17_i_reg_4129;
wire [31:0] grp_fu_466_p2;
reg [31:0] tmp_1_i_reg_4134;
wire [31:0] grp_fu_470_p2;
reg [31:0] tmp_5_i_reg_4140;
wire [31:0] grp_fu_554_p2;
reg [31:0] tmp_8_i_reg_4146;
wire [31:0] grp_fu_558_p2;
reg [31:0] tmp_9_i_reg_4151;
wire [31:0] grp_fu_474_p2;
reg [31:0] tmp_14_i_reg_4156;
wire [31:0] grp_fu_478_p2;
reg [31:0] tmp_18_i_reg_4162;
wire [31:0] grp_fu_562_p2;
reg [31:0] tmp_21_i_reg_4168;
wire [31:0] grp_fu_566_p2;
reg [31:0] tmp_22_i_reg_4173;
wire [31:0] grp_fu_570_p2;
reg [31:0] tmp_2_i_reg_4178;
wire [31:0] grp_fu_574_p2;
reg [31:0] tmp_6_i_reg_4183;
wire [31:0] grp_fu_578_p2;
reg [31:0] tmp_15_i_reg_4188;
wire [31:0] grp_fu_582_p2;
reg [31:0] tmp_19_i_reg_4193;
wire [31:0] grp_fu_586_p2;
reg [31:0] tmp_27_i_reg_4198;
wire [31:0] grp_fu_590_p2;
reg [31:0] tmp_28_i_reg_4203;
wire [31:0] grp_fu_594_p2;
reg [31:0] tmp_32_i_reg_4208;
wire [31:0] grp_fu_598_p2;
reg [31:0] tmp_33_i_reg_4213;
wire [31:0] grp_fu_482_p2;
reg [31:0] tmp_10_i_reg_4218;
wire [31:0] grp_fu_486_p2;
reg [31:0] tmp_23_i_reg_4224;
wire [31:0] grp_fu_490_p2;
reg [31:0] tmp_7_i_reg_4230;
wire [31:0] grp_fu_602_p2;
reg [31:0] tmp_11_i_reg_4235;
wire [31:0] grp_fu_494_p2;
reg [31:0] tmp_20_i_reg_4240;
wire [31:0] grp_fu_606_p2;
reg [31:0] tmp_24_i_reg_4245;
wire [31:0] grp_fu_498_p2;
reg [31:0] tmp_29_i_reg_4250;
wire [31:0] grp_fu_610_p2;
reg [31:0] tmp_30_i_reg_4255;
wire [31:0] grp_fu_502_p2;
reg [31:0] tmp_34_i_reg_4260;
wire [31:0] grp_fu_614_p2;
reg [31:0] tmp_35_i_reg_4265;
wire [31:0] grp_fu_506_p2;
reg [31:0] m_reg_4270;
wire [31:0] grp_fu_510_p2;
reg [31:0] tmp_25_i_reg_4275;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75;
reg [31:0] ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76;
wire [31:0] grp_fu_514_p2;
reg [31:0] tmp_31_i_reg_4280;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76;
reg [31:0] ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77;
wire [31:0] grp_fu_518_p2;
reg [31:0] tmp_36_i_reg_4285;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76;
reg [31:0] ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77;
wire [31:0] grp_fu_630_p2;
reg [31:0] im_reg_4290;
wire [31:0] tmp_61_neg_i_fu_3071_p2;
reg [31:0] tmp_61_neg_i_reg_4297;
wire [575:0] beta_addr_111281129_part_set_fu_3103_p5;
reg [575:0] beta_addr_111281129_part_set_reg_4307;
reg [4:0] data_array_address0;
reg data_array_ce0;
reg data_array_we0;
reg [575:0] data_array_d0;
reg [4:0] data_array_address1;
reg data_array_ce1;
reg data_array_we1;
wire [575:0] data_array_d1;
wire [575:0] data_array_q1;
wire [63:0] tmp_1_fu_2852_p1;
reg ap_sig_cseq_ST_st255_fsm_254;
reg ap_sig_bdd_5023;
reg ap_sig_cseq_ST_st270_fsm_269;
reg ap_sig_bdd_5046;
reg ap_sig_cseq_ST_st285_fsm_284;
reg ap_sig_bdd_5069;
wire [31:0] t_load_fu_3115_p1;
wire [31:0] gamma_load_fu_3120_p1;
reg ap_sig_cseq_ST_st387_fsm_303;
reg ap_sig_bdd_5096;
wire [31:0] beta_load_fu_3125_p1;
reg ap_sig_cseq_ST_st388_fsm_304;
reg ap_sig_bdd_5104;
wire [31:0] t_load_s_fu_3130_p1;
wire [31:0] gamma_load_s_fu_3135_p1;
reg ap_sig_cseq_ST_st390_fsm_306;
reg ap_sig_bdd_5113;
wire [31:0] beta_load_s_fu_3140_p1;
reg ap_sig_cseq_ST_st391_fsm_307;
reg ap_sig_bdd_5121;
wire [31:0] t_load_1_fu_3145_p1;
wire [31:0] gamma_load_1_fu_3150_p1;
reg ap_sig_cseq_ST_st393_fsm_309;
reg ap_sig_bdd_5130;
wire [31:0] beta_load_1_fu_3155_p1;
reg ap_sig_cseq_ST_st394_fsm_310;
reg ap_sig_bdd_5138;
wire [31:0] t_load_2_fu_3160_p1;
wire [31:0] gamma_load_2_fu_3165_p1;
reg ap_sig_cseq_ST_st396_fsm_312;
reg ap_sig_bdd_5147;
wire [31:0] beta_load_2_fu_3170_p1;
reg ap_sig_cseq_ST_st397_fsm_313;
reg ap_sig_bdd_5155;
wire [31:0] t_load_3_fu_3175_p1;
wire [31:0] gamma_load_3_fu_3180_p1;
reg ap_sig_cseq_ST_st399_fsm_315;
reg ap_sig_bdd_5164;
wire [31:0] beta_load_3_fu_3185_p1;
reg ap_sig_cseq_ST_st400_fsm_316;
reg ap_sig_bdd_5172;
wire [31:0] t_load_4_fu_3190_p1;
wire [31:0] gamma_load_4_fu_3195_p1;
reg ap_sig_cseq_ST_st402_fsm_318;
reg ap_sig_bdd_5181;
wire [31:0] beta_load_4_fu_3200_p1;
reg ap_sig_cseq_ST_st403_fsm_319;
reg ap_sig_bdd_5189;
wire [31:0] t_load_5_fu_3205_p1;
wire [31:0] gamma_load_5_fu_3210_p1;
reg ap_sig_cseq_ST_st405_fsm_321;
reg ap_sig_bdd_5198;
wire [31:0] beta_load_5_fu_3215_p1;
reg ap_sig_cseq_ST_st406_fsm_322;
reg ap_sig_bdd_5206;
wire [31:0] t_load_6_fu_3220_p1;
wire [31:0] gamma_load_6_fu_3225_p1;
reg ap_sig_cseq_ST_st408_fsm_324;
reg ap_sig_bdd_5215;
wire [31:0] beta_load_6_fu_3230_p1;
reg ap_sig_cseq_ST_st409_fsm_325;
reg ap_sig_bdd_5223;
wire [31:0] t_load_7_fu_3235_p1;
wire [31:0] gamma_load_7_fu_3240_p1;
reg ap_sig_cseq_ST_st411_fsm_327;
reg ap_sig_bdd_5232;
wire [31:0] beta_load_7_fu_3245_p1;
reg ap_sig_cseq_ST_st412_fsm_328;
reg ap_sig_bdd_5240;
wire [31:0] t_load_8_fu_3250_p1;
wire [31:0] gamma_load_8_fu_3255_p1;
reg ap_sig_cseq_ST_st414_fsm_330;
reg ap_sig_bdd_5249;
wire [31:0] beta_load_8_fu_3260_p1;
reg ap_sig_cseq_ST_st415_fsm_331;
reg ap_sig_bdd_5257;
wire [31:0] t_load_9_fu_3265_p1;
wire [31:0] gamma_load_9_fu_3270_p1;
reg ap_sig_cseq_ST_st417_fsm_333;
reg ap_sig_bdd_5266;
wire [31:0] beta_load_9_fu_3275_p1;
reg ap_sig_cseq_ST_st418_fsm_334;
reg ap_sig_bdd_5274;
wire [31:0] t_load_10_fu_3280_p1;
wire [31:0] gamma_load_10_fu_3285_p1;
reg ap_sig_cseq_ST_st420_fsm_336;
reg ap_sig_bdd_5283;
wire [31:0] beta_load_10_fu_3290_p1;
reg ap_sig_cseq_ST_st421_fsm_337;
reg ap_sig_bdd_5291;
wire [31:0] t_load_11_fu_3295_p1;
wire [31:0] gamma_load_11_fu_3300_p1;
reg ap_sig_cseq_ST_st423_fsm_339;
reg ap_sig_bdd_5300;
wire [31:0] beta_load_11_fu_3305_p1;
reg ap_sig_cseq_ST_st424_fsm_340;
reg ap_sig_bdd_5308;
wire [31:0] t_load_12_fu_3310_p1;
wire [31:0] gamma_load_12_fu_3315_p1;
reg ap_sig_cseq_ST_st426_fsm_342;
reg ap_sig_bdd_5317;
wire [31:0] beta_load_12_fu_3320_p1;
reg ap_sig_cseq_ST_st427_fsm_343;
reg ap_sig_bdd_5325;
wire [31:0] t_load_13_fu_3325_p1;
wire [31:0] gamma_load_13_fu_3330_p1;
reg ap_sig_cseq_ST_st429_fsm_345;
reg ap_sig_bdd_5334;
wire [31:0] beta_load_13_fu_3335_p1;
reg ap_sig_cseq_ST_st430_fsm_346;
reg ap_sig_bdd_5342;
wire [31:0] t_load_14_fu_3340_p1;
wire [31:0] gamma_load_14_fu_3345_p1;
reg ap_sig_cseq_ST_st432_fsm_348;
reg ap_sig_bdd_5351;
wire [31:0] beta_load_14_fu_3350_p1;
reg ap_sig_cseq_ST_st433_fsm_349;
reg ap_sig_bdd_5359;
wire [31:0] t_load_15_fu_3355_p1;
wire [31:0] gamma_load_15_fu_3360_p1;
reg ap_sig_cseq_ST_st435_fsm_351;
reg ap_sig_bdd_5368;
wire [31:0] beta_load_15_fu_3365_p1;
reg ap_sig_cseq_ST_st436_fsm_352;
reg ap_sig_bdd_5376;
wire [31:0] t_load_16_fu_3370_p1;
wire [31:0] gamma_load_16_fu_3375_p1;
reg ap_sig_cseq_ST_st438_fsm_354;
reg ap_sig_bdd_5385;
wire [31:0] beta_load_16_fu_3380_p1;
reg ap_sig_cseq_ST_st439_fsm_355;
reg ap_sig_bdd_5393;
wire [31:0] t_load_17_fu_3385_p1;
wire [31:0] gamma_load_17_fu_3390_p1;
reg ap_sig_cseq_ST_st441_fsm_357;
reg ap_sig_bdd_5402;
wire [31:0] beta_load_17_fu_3395_p1;
reg ap_sig_cseq_ST_st442_fsm_358;
reg ap_sig_bdd_5410;
wire [31:0] t_load_18_fu_3400_p1;
wire [31:0] gamma_load_18_fu_3405_p1;
reg ap_sig_cseq_ST_st444_fsm_360;
reg ap_sig_bdd_5419;
wire [31:0] beta_load_18_fu_3410_p1;
reg ap_sig_cseq_ST_st445_fsm_361;
reg ap_sig_bdd_5427;
reg ap_reg_ioackin_outs_TREADY = 1'b0;
wire [575:0] rez_addr959960_part_set_fu_830_p5;
wire [575:0] rez_addr_3953954_part_set_fu_922_p5;
wire [575:0] rez_addr_5947948_part_set_fu_1017_p5;
wire [575:0] rez_addr_1956957_part_set_fu_1109_p5;
wire [575:0] rez_addr_4950951_part_set_fu_1201_p5;
wire [575:0] rez_addr_6944945_part_set_fu_1308_p5;
wire [575:0] rez_addr_7941942_part_set_fu_1415_p5;
wire [575:0] rez_addr_8938939_part_set_fu_1522_p5;
wire [575:0] rez_addr_9935936_part_set_fu_1629_p5;
wire [575:0] rez_addr_10932933_part_set_fu_1736_p5;
wire [575:0] rez_addr_11929930_part_set_fu_1843_p5;
wire [575:0] rez_addr_12926927_part_set_fu_1950_p5;
wire [575:0] rez_addr_13923924_part_set_fu_2057_p5;
wire [575:0] rez_addr_14920921_part_set_fu_2164_p5;
wire [575:0] rez_addr_15917918_part_set_fu_2271_p5;
wire [575:0] rez_addr_16914915_part_set_fu_2378_p5;
wire [575:0] rez_addr_17911912_part_set_fu_2485_p5;
wire [575:0] rez_addr_18908909_part_set_fu_2592_p5;
wire [575:0] rez_addr_19905906_part_set_fu_2698_p5;
wire [575:0] rez_addr_20902903_part_set_fu_2828_p5;
reg ap_sig_cseq_ST_st385_fsm_301;
reg ap_sig_bdd_5902;
wire [31:0] grp_fu_430_p0;
wire [31:0] grp_fu_430_p1;
wire [31:0] grp_fu_434_p0;
wire [31:0] grp_fu_434_p1;
wire [31:0] grp_fu_438_p0;
wire [31:0] grp_fu_438_p1;
wire [31:0] grp_fu_442_p0;
wire [31:0] grp_fu_442_p1;
wire [31:0] grp_fu_446_p0;
wire [31:0] grp_fu_446_p1;
wire [31:0] grp_fu_450_p0;
wire [31:0] grp_fu_450_p1;
wire [31:0] grp_fu_454_p0;
wire [31:0] grp_fu_454_p1;
wire [31:0] grp_fu_458_p0;
wire [31:0] grp_fu_458_p1;
wire [31:0] grp_fu_462_p0;
wire [31:0] grp_fu_462_p1;
wire [31:0] grp_fu_466_p0;
wire [31:0] grp_fu_466_p1;
wire [31:0] grp_fu_470_p0;
wire [31:0] grp_fu_470_p1;
wire [31:0] grp_fu_474_p0;
wire [31:0] grp_fu_474_p1;
wire [31:0] grp_fu_478_p0;
wire [31:0] grp_fu_478_p1;
wire [31:0] grp_fu_482_p0;
wire [31:0] grp_fu_482_p1;
wire [31:0] grp_fu_486_p0;
wire [31:0] grp_fu_486_p1;
wire [31:0] grp_fu_490_p0;
wire [31:0] grp_fu_490_p1;
wire [31:0] grp_fu_494_p0;
wire [31:0] grp_fu_494_p1;
wire [31:0] grp_fu_498_p0;
wire [31:0] grp_fu_498_p1;
wire [31:0] grp_fu_502_p0;
wire [31:0] grp_fu_502_p1;
wire [31:0] grp_fu_506_p0;
wire [31:0] grp_fu_506_p1;
wire [31:0] grp_fu_510_p0;
wire [31:0] grp_fu_510_p1;
wire [31:0] grp_fu_514_p0;
wire [31:0] grp_fu_514_p1;
wire [31:0] grp_fu_518_p0;
wire [31:0] grp_fu_518_p1;
wire [31:0] grp_fu_522_p0;
wire [31:0] grp_fu_522_p1;
wire [31:0] grp_fu_526_p0;
wire [31:0] grp_fu_526_p1;
wire [31:0] grp_fu_530_p0;
wire [31:0] grp_fu_530_p1;
wire [31:0] grp_fu_534_p0;
wire [31:0] grp_fu_534_p1;
wire [31:0] grp_fu_538_p0;
wire [31:0] grp_fu_538_p1;
wire [31:0] grp_fu_542_p0;
wire [31:0] grp_fu_542_p1;
wire [31:0] grp_fu_546_p0;
wire [31:0] grp_fu_546_p1;
wire [31:0] grp_fu_550_p0;
wire [31:0] grp_fu_550_p1;
wire [31:0] grp_fu_554_p0;
wire [31:0] grp_fu_554_p1;
wire [31:0] grp_fu_558_p0;
wire [31:0] grp_fu_558_p1;
wire [31:0] grp_fu_562_p0;
wire [31:0] grp_fu_562_p1;
wire [31:0] grp_fu_566_p0;
wire [31:0] grp_fu_566_p1;
wire [31:0] grp_fu_570_p0;
wire [31:0] grp_fu_570_p1;
wire [31:0] grp_fu_574_p0;
wire [31:0] grp_fu_574_p1;
wire [31:0] grp_fu_578_p0;
wire [31:0] grp_fu_578_p1;
wire [31:0] grp_fu_582_p0;
wire [31:0] grp_fu_582_p1;
wire [31:0] grp_fu_586_p0;
wire [31:0] grp_fu_586_p1;
wire [31:0] grp_fu_590_p0;
wire [31:0] grp_fu_590_p1;
wire [31:0] grp_fu_594_p0;
wire [31:0] grp_fu_594_p1;
wire [31:0] grp_fu_598_p0;
wire [31:0] grp_fu_598_p1;
wire [31:0] grp_fu_602_p0;
wire [31:0] grp_fu_602_p1;
wire [31:0] grp_fu_606_p0;
wire [31:0] grp_fu_606_p1;
wire [31:0] grp_fu_610_p0;
wire [31:0] grp_fu_610_p1;
wire [31:0] grp_fu_614_p0;
wire [31:0] grp_fu_614_p1;
wire [31:0] grp_fu_618_p0;
wire [31:0] grp_fu_618_p1;
wire [31:0] grp_fu_622_p0;
wire [31:0] grp_fu_622_p1;
wire [31:0] grp_fu_626_p0;
wire [31:0] grp_fu_626_p1;
wire [31:0] grp_fu_630_p0;
wire [31:0] grp_fu_630_p1;
wire [31:0] ins_data_tmp_load_14_toint_fu_793_p1;
wire [31:0] ins_data_tmp_load_13_toint_fu_789_p1;
wire [31:0] ins_data_tmp_load_12_toint_fu_785_p1;
wire [31:0] ins_data_tmp_load_11_toint_fu_781_p1;
wire [31:0] ins_data_tmp_load_10_toint_fu_777_p1;
wire [31:0] ins_data_tmp_load_9_toint_fu_773_p1;
wire [31:0] ins_data_tmp_load_8_toint_fu_769_p1;
wire [31:0] ins_data_tmp_load_7_toint_fu_765_p1;
wire [31:0] ins_data_tmp_load_6_toint_fu_761_p1;
wire [31:0] ins_data_tmp_load_5_toint_fu_757_p1;
wire [31:0] ins_data_tmp_load_4_toint_fu_753_p1;
wire [31:0] ins_data_tmp_load_3_toint_fu_749_p1;
wire [31:0] ins_data_tmp_load_2_toint_fu_745_p1;
wire [31:0] ins_data_tmp_load_1_toint_fu_741_p1;
wire [31:0] ins_data_tmp_load_toint_fu_737_p1;
wire [479:0] tmp_fu_796_p16;
wire [31:0] ins_data_tmp_load_44_toint_fu_885_p1;
wire [31:0] ins_data_tmp_load_43_toint_fu_882_p1;
wire [31:0] ins_data_tmp_load_42_toint_fu_879_p1;
wire [31:0] ins_data_tmp_load_41_toint_fu_876_p1;
wire [31:0] ins_data_tmp_load_40_toint_fu_873_p1;
wire [31:0] ins_data_tmp_load_39_toint_fu_870_p1;
wire [31:0] ins_data_tmp_load_38_toint_fu_867_p1;
wire [31:0] ins_data_tmp_load_37_toint_fu_864_p1;
wire [31:0] ins_data_tmp_load_36_toint_fu_861_p1;
wire [31:0] ins_data_tmp_load_35_toint_fu_858_p1;
wire [31:0] ins_data_tmp_load_34_toint_fu_855_p1;
wire [31:0] ins_data_tmp_load_33_toint_fu_852_p1;
wire [31:0] ins_data_tmp_load_32_toint_fu_849_p1;
wire [31:0] ins_data_tmp_load_31_toint_fu_846_p1;
wire [31:0] ins_data_tmp_load_30_toint_fu_843_p1;
wire [479:0] tmp_3_fu_888_p16;
wire [31:0] ins_data_tmp_load_74_toint_fu_979_p1;
wire [31:0] ins_data_tmp_load_73_toint_fu_975_p1;
wire [31:0] ins_data_tmp_load_72_toint_fu_971_p1;
wire [31:0] ins_data_tmp_load_71_toint_fu_968_p1;
wire [31:0] ins_data_tmp_load_70_toint_fu_965_p1;
wire [31:0] ins_data_tmp_load_69_toint_fu_962_p1;
wire [31:0] ins_data_tmp_load_68_toint_fu_959_p1;
wire [31:0] ins_data_tmp_load_67_toint_fu_956_p1;
wire [31:0] ins_data_tmp_load_66_toint_fu_953_p1;
wire [31:0] ins_data_tmp_load_65_toint_fu_950_p1;
wire [31:0] ins_data_tmp_load_64_toint_fu_947_p1;
wire [31:0] ins_data_tmp_load_63_toint_fu_944_p1;
wire [31:0] ins_data_tmp_load_62_toint_fu_941_p1;
wire [31:0] ins_data_tmp_load_61_toint_fu_938_p1;
wire [31:0] ins_data_tmp_load_60_toint_fu_935_p1;
wire [479:0] tmp_5_fu_983_p16;
wire [31:0] ins_data_tmp_load_29_toint_fu_1072_p1;
wire [31:0] ins_data_tmp_load_28_toint_fu_1069_p1;
wire [31:0] ins_data_tmp_load_27_toint_fu_1066_p1;
wire [31:0] ins_data_tmp_load_26_toint_fu_1063_p1;
wire [31:0] ins_data_tmp_load_25_toint_fu_1060_p1;
wire [31:0] ins_data_tmp_load_24_toint_fu_1057_p1;
wire [31:0] ins_data_tmp_load_23_toint_fu_1054_p1;
wire [31:0] ins_data_tmp_load_22_toint_fu_1051_p1;
wire [31:0] ins_data_tmp_load_21_toint_fu_1048_p1;
wire [31:0] ins_data_tmp_load_20_toint_fu_1045_p1;
wire [31:0] ins_data_tmp_load_19_toint_fu_1042_p1;
wire [31:0] ins_data_tmp_load_18_toint_fu_1039_p1;
wire [31:0] ins_data_tmp_load_17_toint_fu_1036_p1;
wire [31:0] ins_data_tmp_load_16_toint_fu_1033_p1;
wire [31:0] ins_data_tmp_load_15_toint_fu_1030_p1;
wire [479:0] tmp_2_fu_1075_p16;
wire [31:0] ins_data_tmp_load_59_toint_fu_1164_p1;
wire [31:0] ins_data_tmp_load_58_toint_fu_1161_p1;
wire [31:0] ins_data_tmp_load_57_toint_fu_1158_p1;
wire [31:0] ins_data_tmp_load_56_toint_fu_1155_p1;
wire [31:0] ins_data_tmp_load_55_toint_fu_1152_p1;
wire [31:0] ins_data_tmp_load_54_toint_fu_1149_p1;
wire [31:0] ins_data_tmp_load_53_toint_fu_1146_p1;
wire [31:0] ins_data_tmp_load_52_toint_fu_1143_p1;
wire [31:0] ins_data_tmp_load_51_toint_fu_1140_p1;
wire [31:0] ins_data_tmp_load_50_toint_fu_1137_p1;
wire [31:0] ins_data_tmp_load_49_toint_fu_1134_p1;
wire [31:0] ins_data_tmp_load_48_toint_fu_1131_p1;
wire [31:0] ins_data_tmp_load_47_toint_fu_1128_p1;
wire [31:0] ins_data_tmp_load_46_toint_fu_1125_p1;
wire [31:0] ins_data_tmp_load_45_toint_fu_1122_p1;
wire [479:0] tmp_4_fu_1167_p16;
wire [31:0] ins_data_tmp_load_89_toint_fu_1270_p1;
wire [31:0] ins_data_tmp_load_88_toint_fu_1266_p1;
wire [31:0] ins_data_tmp_load_87_toint_fu_1262_p1;
wire [31:0] ins_data_tmp_load_86_toint_fu_1258_p1;
wire [31:0] ins_data_tmp_load_85_toint_fu_1254_p1;
wire [31:0] ins_data_tmp_load_84_toint_fu_1250_p1;
wire [31:0] ins_data_tmp_load_83_toint_fu_1246_p1;
wire [31:0] ins_data_tmp_load_82_toint_fu_1242_p1;
wire [31:0] ins_data_tmp_load_81_toint_fu_1238_p1;
wire [31:0] ins_data_tmp_load_80_toint_fu_1234_p1;
wire [31:0] ins_data_tmp_load_79_toint_fu_1230_p1;
wire [31:0] ins_data_tmp_load_78_toint_fu_1226_p1;
wire [31:0] ins_data_tmp_load_77_toint_fu_1222_p1;
wire [31:0] ins_data_tmp_load_76_toint_fu_1218_p1;
wire [31:0] ins_data_tmp_load_75_toint_fu_1214_p1;
wire [479:0] tmp_6_fu_1274_p16;
wire [31:0] ins_data_tmp_load_104_toint_fu_1377_p1;
wire [31:0] ins_data_tmp_load_103_toint_fu_1373_p1;
wire [31:0] ins_data_tmp_load_102_toint_fu_1369_p1;
wire [31:0] ins_data_tmp_load_101_toint_fu_1365_p1;
wire [31:0] ins_data_tmp_load_100_toint_fu_1361_p1;
wire [31:0] ins_data_tmp_load_99_toint_fu_1357_p1;
wire [31:0] ins_data_tmp_load_98_toint_fu_1353_p1;
wire [31:0] ins_data_tmp_load_97_toint_fu_1349_p1;
wire [31:0] ins_data_tmp_load_96_toint_fu_1345_p1;
wire [31:0] ins_data_tmp_load_95_toint_fu_1341_p1;
wire [31:0] ins_data_tmp_load_94_toint_fu_1337_p1;
wire [31:0] ins_data_tmp_load_93_toint_fu_1333_p1;
wire [31:0] ins_data_tmp_load_92_toint_fu_1329_p1;
wire [31:0] ins_data_tmp_load_91_toint_fu_1325_p1;
wire [31:0] ins_data_tmp_load_90_toint_fu_1321_p1;
wire [479:0] tmp_7_fu_1381_p16;
wire [31:0] ins_data_tmp_load_119_toint_fu_1484_p1;
wire [31:0] ins_data_tmp_load_118_toint_fu_1480_p1;
wire [31:0] ins_data_tmp_load_117_toint_fu_1476_p1;
wire [31:0] ins_data_tmp_load_116_toint_fu_1472_p1;
wire [31:0] ins_data_tmp_load_115_toint_fu_1468_p1;
wire [31:0] ins_data_tmp_load_114_toint_fu_1464_p1;
wire [31:0] ins_data_tmp_load_113_toint_fu_1460_p1;
wire [31:0] ins_data_tmp_load_112_toint_fu_1456_p1;
wire [31:0] ins_data_tmp_load_111_toint_fu_1452_p1;
wire [31:0] ins_data_tmp_load_110_toint_fu_1448_p1;
wire [31:0] ins_data_tmp_load_109_toint_fu_1444_p1;
wire [31:0] ins_data_tmp_load_108_toint_fu_1440_p1;
wire [31:0] ins_data_tmp_load_107_toint_fu_1436_p1;
wire [31:0] ins_data_tmp_load_106_toint_fu_1432_p1;
wire [31:0] ins_data_tmp_load_105_toint_fu_1428_p1;
wire [479:0] tmp_8_fu_1488_p16;
wire [31:0] ins_data_tmp_load_134_toint_fu_1591_p1;
wire [31:0] ins_data_tmp_load_133_toint_fu_1587_p1;
wire [31:0] ins_data_tmp_load_132_toint_fu_1583_p1;
wire [31:0] ins_data_tmp_load_131_toint_fu_1579_p1;
wire [31:0] ins_data_tmp_load_130_toint_fu_1575_p1;
wire [31:0] ins_data_tmp_load_129_toint_fu_1571_p1;
wire [31:0] ins_data_tmp_load_128_toint_fu_1567_p1;
wire [31:0] ins_data_tmp_load_127_toint_fu_1563_p1;
wire [31:0] ins_data_tmp_load_126_toint_fu_1559_p1;
wire [31:0] ins_data_tmp_load_125_toint_fu_1555_p1;
wire [31:0] ins_data_tmp_load_124_toint_fu_1551_p1;
wire [31:0] ins_data_tmp_load_123_toint_fu_1547_p1;
wire [31:0] ins_data_tmp_load_122_toint_fu_1543_p1;
wire [31:0] ins_data_tmp_load_121_toint_fu_1539_p1;
wire [31:0] ins_data_tmp_load_120_toint_fu_1535_p1;
wire [479:0] tmp_9_fu_1595_p16;
wire [31:0] ins_data_tmp_load_149_toint_fu_1698_p1;
wire [31:0] ins_data_tmp_load_148_toint_fu_1694_p1;
wire [31:0] ins_data_tmp_load_147_toint_fu_1690_p1;
wire [31:0] ins_data_tmp_load_146_toint_fu_1686_p1;
wire [31:0] ins_data_tmp_load_145_toint_fu_1682_p1;
wire [31:0] ins_data_tmp_load_144_toint_fu_1678_p1;
wire [31:0] ins_data_tmp_load_143_toint_fu_1674_p1;
wire [31:0] ins_data_tmp_load_142_toint_fu_1670_p1;
wire [31:0] ins_data_tmp_load_141_toint_fu_1666_p1;
wire [31:0] ins_data_tmp_load_140_toint_fu_1662_p1;
wire [31:0] ins_data_tmp_load_139_toint_fu_1658_p1;
wire [31:0] ins_data_tmp_load_138_toint_fu_1654_p1;
wire [31:0] ins_data_tmp_load_137_toint_fu_1650_p1;
wire [31:0] ins_data_tmp_load_136_toint_fu_1646_p1;
wire [31:0] ins_data_tmp_load_135_toint_fu_1642_p1;
wire [479:0] tmp_10_fu_1702_p16;
wire [31:0] ins_data_tmp_load_164_toint_fu_1805_p1;
wire [31:0] ins_data_tmp_load_163_toint_fu_1801_p1;
wire [31:0] ins_data_tmp_load_162_toint_fu_1797_p1;
wire [31:0] ins_data_tmp_load_161_toint_fu_1793_p1;
wire [31:0] ins_data_tmp_load_160_toint_fu_1789_p1;
wire [31:0] ins_data_tmp_load_159_toint_fu_1785_p1;
wire [31:0] ins_data_tmp_load_158_toint_fu_1781_p1;
wire [31:0] ins_data_tmp_load_157_toint_fu_1777_p1;
wire [31:0] ins_data_tmp_load_156_toint_fu_1773_p1;
wire [31:0] ins_data_tmp_load_155_toint_fu_1769_p1;
wire [31:0] ins_data_tmp_load_154_toint_fu_1765_p1;
wire [31:0] ins_data_tmp_load_153_toint_fu_1761_p1;
wire [31:0] ins_data_tmp_load_152_toint_fu_1757_p1;
wire [31:0] ins_data_tmp_load_151_toint_fu_1753_p1;
wire [31:0] ins_data_tmp_load_150_toint_fu_1749_p1;
wire [479:0] tmp_11_fu_1809_p16;
wire [31:0] ins_data_tmp_load_179_toint_fu_1912_p1;
wire [31:0] ins_data_tmp_load_178_toint_fu_1908_p1;
wire [31:0] ins_data_tmp_load_177_toint_fu_1904_p1;
wire [31:0] ins_data_tmp_load_176_toint_fu_1900_p1;
wire [31:0] ins_data_tmp_load_175_toint_fu_1896_p1;
wire [31:0] ins_data_tmp_load_174_toint_fu_1892_p1;
wire [31:0] ins_data_tmp_load_173_toint_fu_1888_p1;
wire [31:0] ins_data_tmp_load_172_toint_fu_1884_p1;
wire [31:0] ins_data_tmp_load_171_toint_fu_1880_p1;
wire [31:0] ins_data_tmp_load_170_toint_fu_1876_p1;
wire [31:0] ins_data_tmp_load_169_toint_fu_1872_p1;
wire [31:0] ins_data_tmp_load_168_toint_fu_1868_p1;
wire [31:0] ins_data_tmp_load_167_toint_fu_1864_p1;
wire [31:0] ins_data_tmp_load_166_toint_fu_1860_p1;
wire [31:0] ins_data_tmp_load_165_toint_fu_1856_p1;
wire [479:0] tmp_12_fu_1916_p16;
wire [31:0] ins_data_tmp_load_194_toint_fu_2019_p1;
wire [31:0] ins_data_tmp_load_193_toint_fu_2015_p1;
wire [31:0] ins_data_tmp_load_192_toint_fu_2011_p1;
wire [31:0] ins_data_tmp_load_191_toint_fu_2007_p1;
wire [31:0] ins_data_tmp_load_190_toint_fu_2003_p1;
wire [31:0] ins_data_tmp_load_189_toint_fu_1999_p1;
wire [31:0] ins_data_tmp_load_188_toint_fu_1995_p1;
wire [31:0] ins_data_tmp_load_187_toint_fu_1991_p1;
wire [31:0] ins_data_tmp_load_186_toint_fu_1987_p1;
wire [31:0] ins_data_tmp_load_185_toint_fu_1983_p1;
wire [31:0] ins_data_tmp_load_184_toint_fu_1979_p1;
wire [31:0] ins_data_tmp_load_183_toint_fu_1975_p1;
wire [31:0] ins_data_tmp_load_182_toint_fu_1971_p1;
wire [31:0] ins_data_tmp_load_181_toint_fu_1967_p1;
wire [31:0] ins_data_tmp_load_180_toint_fu_1963_p1;
wire [479:0] tmp_13_fu_2023_p16;
wire [31:0] ins_data_tmp_load_209_toint_fu_2126_p1;
wire [31:0] ins_data_tmp_load_208_toint_fu_2122_p1;
wire [31:0] ins_data_tmp_load_207_toint_fu_2118_p1;
wire [31:0] ins_data_tmp_load_206_toint_fu_2114_p1;
wire [31:0] ins_data_tmp_load_205_toint_fu_2110_p1;
wire [31:0] ins_data_tmp_load_204_toint_fu_2106_p1;
wire [31:0] ins_data_tmp_load_203_toint_fu_2102_p1;
wire [31:0] ins_data_tmp_load_202_toint_fu_2098_p1;
wire [31:0] ins_data_tmp_load_201_toint_fu_2094_p1;
wire [31:0] ins_data_tmp_load_200_toint_fu_2090_p1;
wire [31:0] ins_data_tmp_load_199_toint_fu_2086_p1;
wire [31:0] ins_data_tmp_load_198_toint_fu_2082_p1;
wire [31:0] ins_data_tmp_load_197_toint_fu_2078_p1;
wire [31:0] ins_data_tmp_load_196_toint_fu_2074_p1;
wire [31:0] ins_data_tmp_load_195_toint_fu_2070_p1;
wire [479:0] tmp_14_fu_2130_p16;
wire [31:0] ins_data_tmp_load_224_toint_fu_2233_p1;
wire [31:0] ins_data_tmp_load_223_toint_fu_2229_p1;
wire [31:0] ins_data_tmp_load_222_toint_fu_2225_p1;
wire [31:0] ins_data_tmp_load_221_toint_fu_2221_p1;
wire [31:0] ins_data_tmp_load_220_toint_fu_2217_p1;
wire [31:0] ins_data_tmp_load_219_toint_fu_2213_p1;
wire [31:0] ins_data_tmp_load_218_toint_fu_2209_p1;
wire [31:0] ins_data_tmp_load_217_toint_fu_2205_p1;
wire [31:0] ins_data_tmp_load_216_toint_fu_2201_p1;
wire [31:0] ins_data_tmp_load_215_toint_fu_2197_p1;
wire [31:0] ins_data_tmp_load_214_toint_fu_2193_p1;
wire [31:0] ins_data_tmp_load_213_toint_fu_2189_p1;
wire [31:0] ins_data_tmp_load_212_toint_fu_2185_p1;
wire [31:0] ins_data_tmp_load_211_toint_fu_2181_p1;
wire [31:0] ins_data_tmp_load_210_toint_fu_2177_p1;
wire [479:0] tmp_15_fu_2237_p16;
wire [31:0] ins_data_tmp_load_239_toint_fu_2340_p1;
wire [31:0] ins_data_tmp_load_238_toint_fu_2336_p1;
wire [31:0] ins_data_tmp_load_237_toint_fu_2332_p1;
wire [31:0] ins_data_tmp_load_236_toint_fu_2328_p1;
wire [31:0] ins_data_tmp_load_235_toint_fu_2324_p1;
wire [31:0] ins_data_tmp_load_234_toint_fu_2320_p1;
wire [31:0] ins_data_tmp_load_233_toint_fu_2316_p1;
wire [31:0] ins_data_tmp_load_232_toint_fu_2312_p1;
wire [31:0] ins_data_tmp_load_231_toint_fu_2308_p1;
wire [31:0] ins_data_tmp_load_230_toint_fu_2304_p1;
wire [31:0] ins_data_tmp_load_229_toint_fu_2300_p1;
wire [31:0] ins_data_tmp_load_228_toint_fu_2296_p1;
wire [31:0] ins_data_tmp_load_227_toint_fu_2292_p1;
wire [31:0] ins_data_tmp_load_226_toint_fu_2288_p1;
wire [31:0] ins_data_tmp_load_225_toint_fu_2284_p1;
wire [479:0] tmp_16_fu_2344_p16;
wire [31:0] ins_data_tmp_load_254_toint_fu_2447_p1;
wire [31:0] ins_data_tmp_load_253_toint_fu_2443_p1;
wire [31:0] ins_data_tmp_load_252_toint_fu_2439_p1;
wire [31:0] ins_data_tmp_load_251_toint_fu_2435_p1;
wire [31:0] ins_data_tmp_load_250_toint_fu_2431_p1;
wire [31:0] ins_data_tmp_load_249_toint_fu_2427_p1;
wire [31:0] ins_data_tmp_load_248_toint_fu_2423_p1;
wire [31:0] ins_data_tmp_load_247_toint_fu_2419_p1;
wire [31:0] ins_data_tmp_load_246_toint_fu_2415_p1;
wire [31:0] ins_data_tmp_load_245_toint_fu_2411_p1;
wire [31:0] ins_data_tmp_load_244_toint_fu_2407_p1;
wire [31:0] ins_data_tmp_load_243_toint_fu_2403_p1;
wire [31:0] ins_data_tmp_load_242_toint_fu_2399_p1;
wire [31:0] ins_data_tmp_load_241_toint_fu_2395_p1;
wire [31:0] ins_data_tmp_load_240_toint_fu_2391_p1;
wire [479:0] tmp_17_fu_2451_p16;
wire [31:0] ins_data_tmp_load_269_toint_fu_2554_p1;
wire [31:0] ins_data_tmp_load_268_toint_fu_2550_p1;
wire [31:0] ins_data_tmp_load_267_toint_fu_2546_p1;
wire [31:0] ins_data_tmp_load_266_toint_fu_2542_p1;
wire [31:0] ins_data_tmp_load_265_toint_fu_2538_p1;
wire [31:0] ins_data_tmp_load_264_toint_fu_2534_p1;
wire [31:0] ins_data_tmp_load_263_toint_fu_2530_p1;
wire [31:0] ins_data_tmp_load_262_toint_fu_2526_p1;
wire [31:0] ins_data_tmp_load_261_toint_fu_2522_p1;
wire [31:0] ins_data_tmp_load_260_toint_fu_2518_p1;
wire [31:0] ins_data_tmp_load_259_toint_fu_2514_p1;
wire [31:0] ins_data_tmp_load_258_toint_fu_2510_p1;
wire [31:0] ins_data_tmp_load_257_toint_fu_2506_p1;
wire [31:0] ins_data_tmp_load_256_toint_fu_2502_p1;
wire [31:0] ins_data_tmp_load_255_toint_fu_2498_p1;
wire [479:0] tmp_18_fu_2558_p16;
wire [31:0] ins_data_tmp_load_284_toint_fu_2660_p1;
wire [31:0] ins_data_tmp_load_283_toint_fu_2656_p1;
wire [31:0] ins_data_tmp_load_282_toint_fu_2652_p1;
wire [31:0] ins_data_tmp_load_281_toint_fu_2648_p1;
wire [31:0] ins_data_tmp_load_280_toint_fu_2644_p1;
wire [31:0] ins_data_tmp_load_279_toint_fu_2640_p1;
wire [31:0] ins_data_tmp_load_278_toint_fu_2636_p1;
wire [31:0] ins_data_tmp_load_277_toint_fu_2632_p1;
wire [31:0] ins_data_tmp_load_276_toint_fu_2628_p1;
wire [31:0] ins_data_tmp_load_275_toint_fu_2624_p1;
wire [31:0] ins_data_tmp_load_274_toint_fu_2620_p1;
wire [31:0] ins_data_tmp_load_273_toint_fu_2616_p1;
wire [31:0] ins_data_tmp_load_272_toint_fu_2612_p1;
wire [31:0] ins_data_tmp_load_271_toint_fu_2608_p1;
wire [31:0] ins_data_tmp_load_270_toint_fu_2604_p1;
wire [479:0] tmp_19_fu_2664_p16;
wire [31:0] ins_data_tmp_load_299_toint_fu_2790_p1;
wire [31:0] ins_data_tmp_load_298_toint_fu_2762_p1;
wire [31:0] ins_data_tmp_load_297_toint_fu_2758_p1;
wire [31:0] ins_data_tmp_load_296_toint_fu_2754_p1;
wire [31:0] ins_data_tmp_load_295_toint_fu_2750_p1;
wire [31:0] ins_data_tmp_load_294_toint_fu_2746_p1;
wire [31:0] ins_data_tmp_load_293_toint_fu_2742_p1;
wire [31:0] ins_data_tmp_load_292_toint_fu_2738_p1;
wire [31:0] ins_data_tmp_load_291_toint_fu_2734_p1;
wire [31:0] ins_data_tmp_load_290_toint_fu_2730_p1;
wire [31:0] ins_data_tmp_load_289_toint_fu_2726_p1;
wire [31:0] ins_data_tmp_load_288_toint_fu_2722_p1;
wire [31:0] ins_data_tmp_load_287_toint_fu_2718_p1;
wire [31:0] ins_data_tmp_load_286_toint_fu_2714_p1;
wire [31:0] ins_data_tmp_load_285_toint_fu_2710_p1;
wire [479:0] tmp_20_fu_2794_p16;
wire [31:0] tmp_61_to_int_i_fu_3068_p1;
wire [31:0] grp_fu_618_p2;
wire [31:0] grp_fu_622_p2;
wire [31:0] grp_fu_626_p2;
wire [31:0] beta_write_assign_toint_fu_3089_p1;
wire [31:0] gamma_write_assign_toint_fu_3085_p1;
wire [31:0] t_write_assign_toint_fu_3081_p1;
wire [95:0] tmp_21_fu_3093_p4;
wire [31:0] grp_fu_639_p4;
wire grp_fu_430_ce;
wire grp_fu_434_ce;
wire grp_fu_438_ce;
wire grp_fu_442_ce;
wire grp_fu_446_ce;
wire grp_fu_450_ce;
wire grp_fu_454_ce;
wire grp_fu_458_ce;
wire grp_fu_462_ce;
wire grp_fu_466_ce;
wire grp_fu_470_ce;
wire grp_fu_474_ce;
wire grp_fu_478_ce;
wire grp_fu_482_ce;
wire grp_fu_486_ce;
wire grp_fu_490_ce;
wire grp_fu_494_ce;
wire grp_fu_498_ce;
wire grp_fu_502_ce;
wire grp_fu_506_ce;
wire grp_fu_510_ce;
wire grp_fu_514_ce;
wire grp_fu_518_ce;
wire grp_fu_522_ce;
wire grp_fu_526_ce;
wire grp_fu_530_ce;
wire grp_fu_534_ce;
wire grp_fu_538_ce;
wire grp_fu_542_ce;
wire grp_fu_546_ce;
wire grp_fu_550_ce;
wire grp_fu_554_ce;
wire grp_fu_558_ce;
wire grp_fu_562_ce;
wire grp_fu_566_ce;
wire grp_fu_570_ce;
wire grp_fu_574_ce;
wire grp_fu_578_ce;
wire grp_fu_582_ce;
wire grp_fu_586_ce;
wire grp_fu_590_ce;
wire grp_fu_594_ce;
wire grp_fu_598_ce;
wire grp_fu_602_ce;
wire grp_fu_606_ce;
wire grp_fu_610_ce;
wire grp_fu_614_ce;
wire grp_fu_618_ce;
wire grp_fu_622_ce;
wire grp_fu_626_ce;
wire grp_fu_630_ce;
reg [361:0] ap_NS_fsm;
tri_intersect_data_array #(
.DataWidth( 576 ),
.AddressRange( 20 ),
.AddressWidth( 5 ))
data_array_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( data_array_address0 ),
.ce0( data_array_ce0 ),
.we0( data_array_we0 ),
.d0( data_array_d0 ),
.q0( data_array_q0 ),
.address1( data_array_address1 ),
.ce1( data_array_ce1 ),
.we1( data_array_we1 ),
.d1( data_array_d1 ),
.q1( data_array_q1 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U0(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_430_p0 ),
.din1( grp_fu_430_p1 ),
.ce( grp_fu_430_ce ),
.dout( grp_fu_430_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U1(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_434_p0 ),
.din1( grp_fu_434_p1 ),
.ce( grp_fu_434_ce ),
.dout( grp_fu_434_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U2(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_438_p0 ),
.din1( grp_fu_438_p1 ),
.ce( grp_fu_438_ce ),
.dout( grp_fu_438_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U3(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_442_p0 ),
.din1( grp_fu_442_p1 ),
.ce( grp_fu_442_ce ),
.dout( grp_fu_442_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U4(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_446_p0 ),
.din1( grp_fu_446_p1 ),
.ce( grp_fu_446_ce ),
.dout( grp_fu_446_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U5(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_450_p0 ),
.din1( grp_fu_450_p1 ),
.ce( grp_fu_450_ce ),
.dout( grp_fu_450_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U6(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_454_p0 ),
.din1( grp_fu_454_p1 ),
.ce( grp_fu_454_ce ),
.dout( grp_fu_454_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U7(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_458_p0 ),
.din1( grp_fu_458_p1 ),
.ce( grp_fu_458_ce ),
.dout( grp_fu_458_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U8(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_462_p0 ),
.din1( grp_fu_462_p1 ),
.ce( grp_fu_462_ce ),
.dout( grp_fu_462_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U9(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_466_p0 ),
.din1( grp_fu_466_p1 ),
.ce( grp_fu_466_ce ),
.dout( grp_fu_466_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U10(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_470_p0 ),
.din1( grp_fu_470_p1 ),
.ce( grp_fu_470_ce ),
.dout( grp_fu_470_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U11(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_474_p0 ),
.din1( grp_fu_474_p1 ),
.ce( grp_fu_474_ce ),
.dout( grp_fu_474_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U12(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_478_p0 ),
.din1( grp_fu_478_p1 ),
.ce( grp_fu_478_ce ),
.dout( grp_fu_478_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U13(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_482_p0 ),
.din1( grp_fu_482_p1 ),
.ce( grp_fu_482_ce ),
.dout( grp_fu_482_p2 )
);
tri_intersect_fsub_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fsub_32ns_32ns_32_9_full_dsp_U14(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_486_p0 ),
.din1( grp_fu_486_p1 ),
.ce( grp_fu_486_ce ),
.dout( grp_fu_486_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U15(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_490_p0 ),
.din1( grp_fu_490_p1 ),
.ce( grp_fu_490_ce ),
.dout( grp_fu_490_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U16(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_494_p0 ),
.din1( grp_fu_494_p1 ),
.ce( grp_fu_494_ce ),
.dout( grp_fu_494_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U17(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_498_p0 ),
.din1( grp_fu_498_p1 ),
.ce( grp_fu_498_ce ),
.dout( grp_fu_498_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U18(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_502_p0 ),
.din1( grp_fu_502_p1 ),
.ce( grp_fu_502_ce ),
.dout( grp_fu_502_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U19(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_506_p0 ),
.din1( grp_fu_506_p1 ),
.ce( grp_fu_506_ce ),
.dout( grp_fu_506_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U20(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_510_p0 ),
.din1( grp_fu_510_p1 ),
.ce( grp_fu_510_ce ),
.dout( grp_fu_510_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U21(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_514_p0 ),
.din1( grp_fu_514_p1 ),
.ce( grp_fu_514_ce ),
.dout( grp_fu_514_p2 )
);
tri_intersect_fadd_32ns_32ns_32_9_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 9 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fadd_32ns_32ns_32_9_full_dsp_U22(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_518_p0 ),
.din1( grp_fu_518_p1 ),
.ce( grp_fu_518_ce ),
.dout( grp_fu_518_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U23(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_522_p0 ),
.din1( grp_fu_522_p1 ),
.ce( grp_fu_522_ce ),
.dout( grp_fu_522_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U24(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_526_p0 ),
.din1( grp_fu_526_p1 ),
.ce( grp_fu_526_ce ),
.dout( grp_fu_526_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U25(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_530_p0 ),
.din1( grp_fu_530_p1 ),
.ce( grp_fu_530_ce ),
.dout( grp_fu_530_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U26(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_534_p0 ),
.din1( grp_fu_534_p1 ),
.ce( grp_fu_534_ce ),
.dout( grp_fu_534_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U27(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_538_p0 ),
.din1( grp_fu_538_p1 ),
.ce( grp_fu_538_ce ),
.dout( grp_fu_538_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U28(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_542_p0 ),
.din1( grp_fu_542_p1 ),
.ce( grp_fu_542_ce ),
.dout( grp_fu_542_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U29(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_546_p0 ),
.din1( grp_fu_546_p1 ),
.ce( grp_fu_546_ce ),
.dout( grp_fu_546_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U30(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_550_p0 ),
.din1( grp_fu_550_p1 ),
.ce( grp_fu_550_ce ),
.dout( grp_fu_550_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U31(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_554_p0 ),
.din1( grp_fu_554_p1 ),
.ce( grp_fu_554_ce ),
.dout( grp_fu_554_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U32(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_558_p0 ),
.din1( grp_fu_558_p1 ),
.ce( grp_fu_558_ce ),
.dout( grp_fu_558_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U33(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_562_p0 ),
.din1( grp_fu_562_p1 ),
.ce( grp_fu_562_ce ),
.dout( grp_fu_562_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U34(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_566_p0 ),
.din1( grp_fu_566_p1 ),
.ce( grp_fu_566_ce ),
.dout( grp_fu_566_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U35(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_570_p0 ),
.din1( grp_fu_570_p1 ),
.ce( grp_fu_570_ce ),
.dout( grp_fu_570_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U36(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_574_p0 ),
.din1( grp_fu_574_p1 ),
.ce( grp_fu_574_ce ),
.dout( grp_fu_574_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U37(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_578_p0 ),
.din1( grp_fu_578_p1 ),
.ce( grp_fu_578_ce ),
.dout( grp_fu_578_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U38(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_582_p0 ),
.din1( grp_fu_582_p1 ),
.ce( grp_fu_582_ce ),
.dout( grp_fu_582_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U39(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_586_p0 ),
.din1( grp_fu_586_p1 ),
.ce( grp_fu_586_ce ),
.dout( grp_fu_586_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U40(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_590_p0 ),
.din1( grp_fu_590_p1 ),
.ce( grp_fu_590_ce ),
.dout( grp_fu_590_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U41(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_594_p0 ),
.din1( grp_fu_594_p1 ),
.ce( grp_fu_594_ce ),
.dout( grp_fu_594_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U42(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_598_p0 ),
.din1( grp_fu_598_p1 ),
.ce( grp_fu_598_ce ),
.dout( grp_fu_598_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U43(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_602_p0 ),
.din1( grp_fu_602_p1 ),
.ce( grp_fu_602_ce ),
.dout( grp_fu_602_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U44(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_606_p0 ),
.din1( grp_fu_606_p1 ),
.ce( grp_fu_606_ce ),
.dout( grp_fu_606_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U45(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_610_p0 ),
.din1( grp_fu_610_p1 ),
.ce( grp_fu_610_ce ),
.dout( grp_fu_610_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U46(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_614_p0 ),
.din1( grp_fu_614_p1 ),
.ce( grp_fu_614_ce ),
.dout( grp_fu_614_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U47(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_618_p0 ),
.din1( grp_fu_618_p1 ),
.ce( grp_fu_618_ce ),
.dout( grp_fu_618_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U48(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_622_p0 ),
.din1( grp_fu_622_p1 ),
.ce( grp_fu_622_ce ),
.dout( grp_fu_622_p2 )
);
tri_intersect_fmul_32ns_32ns_32_5_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fmul_32ns_32ns_32_5_max_dsp_U49(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_626_p0 ),
.din1( grp_fu_626_p1 ),
.ce( grp_fu_626_ce ),
.dout( grp_fu_626_p2 )
);
tri_intersect_fdiv_32ns_32ns_32_30 #(
.ID( 1 ),
.NUM_STAGE( 30 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
tri_intersect_fdiv_32ns_32ns_32_30_U50(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_630_p0 ),
.din1( grp_fu_630_p1 ),
.ce( grp_fu_630_ce ),
.dout( grp_fu_630_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ioackin_outs_TREADY assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ioackin_outs_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
end else begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st386_fsm_302) & ~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st389_fsm_305)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st392_fsm_308)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st395_fsm_311)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st398_fsm_314)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st401_fsm_317)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st404_fsm_320)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st407_fsm_323)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st410_fsm_326)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st413_fsm_329)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st416_fsm_332)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st419_fsm_335)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st422_fsm_338)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st425_fsm_341)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st428_fsm_344)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st431_fsm_347)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st434_fsm_350)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st437_fsm_353)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st440_fsm_356)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st443_fsm_359)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st387_fsm_303)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st388_fsm_304)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st390_fsm_306)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st391_fsm_307)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st393_fsm_309)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st394_fsm_310)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st396_fsm_312)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st397_fsm_313)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st399_fsm_315)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st400_fsm_316)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st402_fsm_318)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st403_fsm_319)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st405_fsm_321)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st406_fsm_322)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st408_fsm_324)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st409_fsm_325)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st411_fsm_327)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st412_fsm_328)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st414_fsm_330)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st415_fsm_331)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st417_fsm_333)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st418_fsm_334)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st420_fsm_336)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st421_fsm_337)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st423_fsm_339)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st424_fsm_340)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st426_fsm_342)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st427_fsm_343)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st429_fsm_345)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st430_fsm_346)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st432_fsm_348)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st433_fsm_349)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st435_fsm_351)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st436_fsm_352)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st438_fsm_354)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st439_fsm_355)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st441_fsm_357)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st442_fsm_358)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st444_fsm_360)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st445_fsm_361)))) begin
ap_reg_ioackin_outs_TREADY <= ap_const_logic_0;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_st386_fsm_302) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st387_fsm_303) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st388_fsm_304) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st389_fsm_305) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st390_fsm_306) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st391_fsm_307) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st392_fsm_308) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st393_fsm_309) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st394_fsm_310) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st395_fsm_311) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st396_fsm_312) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st397_fsm_313) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st398_fsm_314) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st399_fsm_315) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st400_fsm_316) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st401_fsm_317) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st402_fsm_318) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st403_fsm_319) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st404_fsm_320) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st405_fsm_321) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st406_fsm_322) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st407_fsm_323) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st408_fsm_324) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st409_fsm_325) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st410_fsm_326) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st411_fsm_327) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st412_fsm_328) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st413_fsm_329) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st414_fsm_330) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st415_fsm_331) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st416_fsm_332) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st417_fsm_333) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st418_fsm_334) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st419_fsm_335) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st420_fsm_336) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st421_fsm_337) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st422_fsm_338) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st423_fsm_339) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st424_fsm_340) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st425_fsm_341) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st426_fsm_342) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st427_fsm_343) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st428_fsm_344) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st429_fsm_345) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st430_fsm_346) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st431_fsm_347) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st432_fsm_348) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st433_fsm_349) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st434_fsm_350) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st435_fsm_351) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st436_fsm_352) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st437_fsm_353) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st438_fsm_354) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st439_fsm_355) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st440_fsm_356) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st441_fsm_357) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st442_fsm_358) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st443_fsm_359) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st444_fsm_360) & (ap_const_logic_1 == outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st445_fsm_361) & (ap_const_logic_1 == outs_TREADY)))) begin
ap_reg_ioackin_outs_TREADY <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300) & ~(ap_const_lv1_0 == exitcond2_fu_2840_p2))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_0;
end else if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299))) begin
ap_reg_ppiten_pp0_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp0_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it1
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300) & (ap_const_lv1_0 == exitcond2_fu_2840_p2))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_1;
end else if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300) & ~(ap_const_lv1_0 == exitcond2_fu_2840_p2)))) begin
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp0_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it10
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end
end
/// ap_reg_ppiten_pp0_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it11
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end
end
/// ap_reg_ppiten_pp0_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it12
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it12 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it12 <= ap_reg_ppiten_pp0_it11;
end
end
/// ap_reg_ppiten_pp0_it13 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it13
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it13 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it13 <= ap_reg_ppiten_pp0_it12;
end
end
/// ap_reg_ppiten_pp0_it14 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it14
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it14 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it14 <= ap_reg_ppiten_pp0_it13;
end
end
/// ap_reg_ppiten_pp0_it15 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it15
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it15 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it15 <= ap_reg_ppiten_pp0_it14;
end
end
/// ap_reg_ppiten_pp0_it16 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it16
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it16 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it16 <= ap_reg_ppiten_pp0_it15;
end
end
/// ap_reg_ppiten_pp0_it17 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it17
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it17 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it17 <= ap_reg_ppiten_pp0_it16;
end
end
/// ap_reg_ppiten_pp0_it18 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it18
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it18 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it18 <= ap_reg_ppiten_pp0_it17;
end
end
/// ap_reg_ppiten_pp0_it19 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it19
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it19 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it19 <= ap_reg_ppiten_pp0_it18;
end
end
/// ap_reg_ppiten_pp0_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it2
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end
end
/// ap_reg_ppiten_pp0_it20 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it20
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it20 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it20 <= ap_reg_ppiten_pp0_it19;
end
end
/// ap_reg_ppiten_pp0_it21 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it21
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it21 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it21 <= ap_reg_ppiten_pp0_it20;
end
end
/// ap_reg_ppiten_pp0_it22 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it22
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it22 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it22 <= ap_reg_ppiten_pp0_it21;
end
end
/// ap_reg_ppiten_pp0_it23 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it23
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it23 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it23 <= ap_reg_ppiten_pp0_it22;
end
end
/// ap_reg_ppiten_pp0_it24 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it24
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it24 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it24 <= ap_reg_ppiten_pp0_it23;
end
end
/// ap_reg_ppiten_pp0_it25 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it25
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it25 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it25 <= ap_reg_ppiten_pp0_it24;
end
end
/// ap_reg_ppiten_pp0_it26 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it26
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it26 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it26 <= ap_reg_ppiten_pp0_it25;
end
end
/// ap_reg_ppiten_pp0_it27 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it27
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it27 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it27 <= ap_reg_ppiten_pp0_it26;
end
end
/// ap_reg_ppiten_pp0_it28 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it28
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it28 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it28 <= ap_reg_ppiten_pp0_it27;
end
end
/// ap_reg_ppiten_pp0_it29 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it29
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it29 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it29 <= ap_reg_ppiten_pp0_it28;
end
end
/// ap_reg_ppiten_pp0_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it3
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end
end
/// ap_reg_ppiten_pp0_it30 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it30
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it30 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it30 <= ap_reg_ppiten_pp0_it29;
end
end
/// ap_reg_ppiten_pp0_it31 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it31
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it31 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it31 <= ap_reg_ppiten_pp0_it30;
end
end
/// ap_reg_ppiten_pp0_it32 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it32
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it32 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it32 <= ap_reg_ppiten_pp0_it31;
end
end
/// ap_reg_ppiten_pp0_it33 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it33
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it33 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it33 <= ap_reg_ppiten_pp0_it32;
end
end
/// ap_reg_ppiten_pp0_it34 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it34
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it34 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it34 <= ap_reg_ppiten_pp0_it33;
end
end
/// ap_reg_ppiten_pp0_it35 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it35
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it35 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it35 <= ap_reg_ppiten_pp0_it34;
end
end
/// ap_reg_ppiten_pp0_it36 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it36
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it36 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it36 <= ap_reg_ppiten_pp0_it35;
end
end
/// ap_reg_ppiten_pp0_it37 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it37
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it37 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it37 <= ap_reg_ppiten_pp0_it36;
end
end
/// ap_reg_ppiten_pp0_it38 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it38
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it38 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it38 <= ap_reg_ppiten_pp0_it37;
end
end
/// ap_reg_ppiten_pp0_it39 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it39
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it39 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it39 <= ap_reg_ppiten_pp0_it38;
end
end
/// ap_reg_ppiten_pp0_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it4
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end
end
/// ap_reg_ppiten_pp0_it40 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it40
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it40 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it40 <= ap_reg_ppiten_pp0_it39;
end
end
/// ap_reg_ppiten_pp0_it41 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it41
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it41 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it41 <= ap_reg_ppiten_pp0_it40;
end
end
/// ap_reg_ppiten_pp0_it42 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it42
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it42 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it42 <= ap_reg_ppiten_pp0_it41;
end
end
/// ap_reg_ppiten_pp0_it43 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it43
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it43 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it43 <= ap_reg_ppiten_pp0_it42;
end
end
/// ap_reg_ppiten_pp0_it44 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it44
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it44 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it44 <= ap_reg_ppiten_pp0_it43;
end
end
/// ap_reg_ppiten_pp0_it45 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it45
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it45 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it45 <= ap_reg_ppiten_pp0_it44;
end
end
/// ap_reg_ppiten_pp0_it46 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it46
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it46 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it46 <= ap_reg_ppiten_pp0_it45;
end
end
/// ap_reg_ppiten_pp0_it47 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it47
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it47 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it47 <= ap_reg_ppiten_pp0_it46;
end
end
/// ap_reg_ppiten_pp0_it48 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it48
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it48 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it48 <= ap_reg_ppiten_pp0_it47;
end
end
/// ap_reg_ppiten_pp0_it49 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it49
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it49 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it49 <= ap_reg_ppiten_pp0_it48;
end
end
/// ap_reg_ppiten_pp0_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it5
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end
end
/// ap_reg_ppiten_pp0_it50 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it50
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it50 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it50 <= ap_reg_ppiten_pp0_it49;
end
end
/// ap_reg_ppiten_pp0_it51 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it51
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it51 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it51 <= ap_reg_ppiten_pp0_it50;
end
end
/// ap_reg_ppiten_pp0_it52 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it52
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it52 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it52 <= ap_reg_ppiten_pp0_it51;
end
end
/// ap_reg_ppiten_pp0_it53 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it53
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it53 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it53 <= ap_reg_ppiten_pp0_it52;
end
end
/// ap_reg_ppiten_pp0_it54 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it54
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it54 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it54 <= ap_reg_ppiten_pp0_it53;
end
end
/// ap_reg_ppiten_pp0_it55 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it55
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it55 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it55 <= ap_reg_ppiten_pp0_it54;
end
end
/// ap_reg_ppiten_pp0_it56 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it56
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it56 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it56 <= ap_reg_ppiten_pp0_it55;
end
end
/// ap_reg_ppiten_pp0_it57 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it57
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it57 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it57 <= ap_reg_ppiten_pp0_it56;
end
end
/// ap_reg_ppiten_pp0_it58 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it58
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it58 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it58 <= ap_reg_ppiten_pp0_it57;
end
end
/// ap_reg_ppiten_pp0_it59 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it59
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it59 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it59 <= ap_reg_ppiten_pp0_it58;
end
end
/// ap_reg_ppiten_pp0_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it6
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end
end
/// ap_reg_ppiten_pp0_it60 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it60
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it60 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it60 <= ap_reg_ppiten_pp0_it59;
end
end
/// ap_reg_ppiten_pp0_it61 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it61
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it61 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it61 <= ap_reg_ppiten_pp0_it60;
end
end
/// ap_reg_ppiten_pp0_it62 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it62
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it62 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it62 <= ap_reg_ppiten_pp0_it61;
end
end
/// ap_reg_ppiten_pp0_it63 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it63
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it63 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it63 <= ap_reg_ppiten_pp0_it62;
end
end
/// ap_reg_ppiten_pp0_it64 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it64
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it64 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it64 <= ap_reg_ppiten_pp0_it63;
end
end
/// ap_reg_ppiten_pp0_it65 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it65
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it65 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it65 <= ap_reg_ppiten_pp0_it64;
end
end
/// ap_reg_ppiten_pp0_it66 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it66
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it66 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it66 <= ap_reg_ppiten_pp0_it65;
end
end
/// ap_reg_ppiten_pp0_it67 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it67
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it67 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it67 <= ap_reg_ppiten_pp0_it66;
end
end
/// ap_reg_ppiten_pp0_it68 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it68
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it68 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it68 <= ap_reg_ppiten_pp0_it67;
end
end
/// ap_reg_ppiten_pp0_it69 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it69
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it69 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it69 <= ap_reg_ppiten_pp0_it68;
end
end
/// ap_reg_ppiten_pp0_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it7
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end
end
/// ap_reg_ppiten_pp0_it70 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it70
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it70 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it70 <= ap_reg_ppiten_pp0_it69;
end
end
/// ap_reg_ppiten_pp0_it71 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it71
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it71 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it71 <= ap_reg_ppiten_pp0_it70;
end
end
/// ap_reg_ppiten_pp0_it72 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it72
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it72 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it72 <= ap_reg_ppiten_pp0_it71;
end
end
/// ap_reg_ppiten_pp0_it73 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it73
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it73 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it73 <= ap_reg_ppiten_pp0_it72;
end
end
/// ap_reg_ppiten_pp0_it74 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it74
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it74 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it74 <= ap_reg_ppiten_pp0_it73;
end
end
/// ap_reg_ppiten_pp0_it75 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it75
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it75 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it75 <= ap_reg_ppiten_pp0_it74;
end
end
/// ap_reg_ppiten_pp0_it76 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it76
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it76 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it76 <= ap_reg_ppiten_pp0_it75;
end
end
/// ap_reg_ppiten_pp0_it77 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it77
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it77 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it77 <= ap_reg_ppiten_pp0_it76;
end
end
/// ap_reg_ppiten_pp0_it78 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it78
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it78 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it78 <= ap_reg_ppiten_pp0_it77;
end
end
/// ap_reg_ppiten_pp0_it79 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it79
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it79 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it79 <= ap_reg_ppiten_pp0_it78;
end
end
/// ap_reg_ppiten_pp0_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it8
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end
end
/// ap_reg_ppiten_pp0_it80 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it80
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it80 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it80 <= ap_reg_ppiten_pp0_it79;
end
end
/// ap_reg_ppiten_pp0_it81 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it81
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it81 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it81 <= ap_reg_ppiten_pp0_it80;
end
end
/// ap_reg_ppiten_pp0_it82 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it82
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it82 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it82 <= ap_reg_ppiten_pp0_it81;
end
end
/// ap_reg_ppiten_pp0_it83 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it83
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it83 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it83 <= ap_reg_ppiten_pp0_it82;
end
end
/// ap_reg_ppiten_pp0_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp0_it9
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
end else begin
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299))) begin
i1_reg_418 <= ap_const_lv5_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300) & (ap_const_lv1_0 == exitcond2_fu_2840_p2))) begin
i1_reg_418 <= i_fu_2846_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it9)) begin
a_reg_4010 <= grp_fu_430_p2;
b_reg_4017 <= grp_fu_434_p2;
c_reg_4024 <= grp_fu_438_p2;
d_reg_4031 <= grp_fu_442_p2;
e_reg_4038 <= grp_fu_446_p2;
f_reg_4045 <= grp_fu_450_p2;
j_reg_4052 <= grp_fu_454_p2;
k_reg_4059 <= grp_fu_458_p2;
l_reg_4066 <= grp_fu_462_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_true == ap_true)) begin
ap_reg_ppstg_a_reg_4010_pp0_it11 <= a_reg_4010;
ap_reg_ppstg_a_reg_4010_pp0_it12 <= ap_reg_ppstg_a_reg_4010_pp0_it11;
ap_reg_ppstg_a_reg_4010_pp0_it13 <= ap_reg_ppstg_a_reg_4010_pp0_it12;
ap_reg_ppstg_a_reg_4010_pp0_it14 <= ap_reg_ppstg_a_reg_4010_pp0_it13;
ap_reg_ppstg_a_reg_4010_pp0_it15 <= ap_reg_ppstg_a_reg_4010_pp0_it14;
ap_reg_ppstg_a_reg_4010_pp0_it16 <= ap_reg_ppstg_a_reg_4010_pp0_it15;
ap_reg_ppstg_a_reg_4010_pp0_it17 <= ap_reg_ppstg_a_reg_4010_pp0_it16;
ap_reg_ppstg_a_reg_4010_pp0_it18 <= ap_reg_ppstg_a_reg_4010_pp0_it17;
ap_reg_ppstg_a_reg_4010_pp0_it19 <= ap_reg_ppstg_a_reg_4010_pp0_it18;
ap_reg_ppstg_a_reg_4010_pp0_it20 <= ap_reg_ppstg_a_reg_4010_pp0_it19;
ap_reg_ppstg_a_reg_4010_pp0_it21 <= ap_reg_ppstg_a_reg_4010_pp0_it20;
ap_reg_ppstg_a_reg_4010_pp0_it22 <= ap_reg_ppstg_a_reg_4010_pp0_it21;
ap_reg_ppstg_a_reg_4010_pp0_it23 <= ap_reg_ppstg_a_reg_4010_pp0_it22;
ap_reg_ppstg_a_reg_4010_pp0_it24 <= ap_reg_ppstg_a_reg_4010_pp0_it23;
ap_reg_ppstg_b_reg_4017_pp0_it11 <= b_reg_4017;
ap_reg_ppstg_b_reg_4017_pp0_it12 <= ap_reg_ppstg_b_reg_4017_pp0_it11;
ap_reg_ppstg_b_reg_4017_pp0_it13 <= ap_reg_ppstg_b_reg_4017_pp0_it12;
ap_reg_ppstg_b_reg_4017_pp0_it14 <= ap_reg_ppstg_b_reg_4017_pp0_it13;
ap_reg_ppstg_b_reg_4017_pp0_it15 <= ap_reg_ppstg_b_reg_4017_pp0_it14;
ap_reg_ppstg_b_reg_4017_pp0_it16 <= ap_reg_ppstg_b_reg_4017_pp0_it15;
ap_reg_ppstg_b_reg_4017_pp0_it17 <= ap_reg_ppstg_b_reg_4017_pp0_it16;
ap_reg_ppstg_b_reg_4017_pp0_it18 <= ap_reg_ppstg_b_reg_4017_pp0_it17;
ap_reg_ppstg_b_reg_4017_pp0_it19 <= ap_reg_ppstg_b_reg_4017_pp0_it18;
ap_reg_ppstg_b_reg_4017_pp0_it20 <= ap_reg_ppstg_b_reg_4017_pp0_it19;
ap_reg_ppstg_b_reg_4017_pp0_it21 <= ap_reg_ppstg_b_reg_4017_pp0_it20;
ap_reg_ppstg_b_reg_4017_pp0_it22 <= ap_reg_ppstg_b_reg_4017_pp0_it21;
ap_reg_ppstg_b_reg_4017_pp0_it23 <= ap_reg_ppstg_b_reg_4017_pp0_it22;
ap_reg_ppstg_b_reg_4017_pp0_it24 <= ap_reg_ppstg_b_reg_4017_pp0_it23;
ap_reg_ppstg_c_reg_4024_pp0_it11 <= c_reg_4024;
ap_reg_ppstg_c_reg_4024_pp0_it12 <= ap_reg_ppstg_c_reg_4024_pp0_it11;
ap_reg_ppstg_c_reg_4024_pp0_it13 <= ap_reg_ppstg_c_reg_4024_pp0_it12;
ap_reg_ppstg_c_reg_4024_pp0_it14 <= ap_reg_ppstg_c_reg_4024_pp0_it13;
ap_reg_ppstg_c_reg_4024_pp0_it15 <= ap_reg_ppstg_c_reg_4024_pp0_it14;
ap_reg_ppstg_c_reg_4024_pp0_it16 <= ap_reg_ppstg_c_reg_4024_pp0_it15;
ap_reg_ppstg_c_reg_4024_pp0_it17 <= ap_reg_ppstg_c_reg_4024_pp0_it16;
ap_reg_ppstg_c_reg_4024_pp0_it18 <= ap_reg_ppstg_c_reg_4024_pp0_it17;
ap_reg_ppstg_c_reg_4024_pp0_it19 <= ap_reg_ppstg_c_reg_4024_pp0_it18;
ap_reg_ppstg_c_reg_4024_pp0_it20 <= ap_reg_ppstg_c_reg_4024_pp0_it19;
ap_reg_ppstg_c_reg_4024_pp0_it21 <= ap_reg_ppstg_c_reg_4024_pp0_it20;
ap_reg_ppstg_c_reg_4024_pp0_it22 <= ap_reg_ppstg_c_reg_4024_pp0_it21;
ap_reg_ppstg_c_reg_4024_pp0_it23 <= ap_reg_ppstg_c_reg_4024_pp0_it22;
ap_reg_ppstg_c_reg_4024_pp0_it24 <= ap_reg_ppstg_c_reg_4024_pp0_it23;
ap_reg_ppstg_c_reg_4024_pp0_it25 <= ap_reg_ppstg_c_reg_4024_pp0_it24;
ap_reg_ppstg_c_reg_4024_pp0_it26 <= ap_reg_ppstg_c_reg_4024_pp0_it25;
ap_reg_ppstg_c_reg_4024_pp0_it27 <= ap_reg_ppstg_c_reg_4024_pp0_it26;
ap_reg_ppstg_c_reg_4024_pp0_it28 <= ap_reg_ppstg_c_reg_4024_pp0_it27;
ap_reg_ppstg_c_reg_4024_pp0_it29 <= ap_reg_ppstg_c_reg_4024_pp0_it28;
ap_reg_ppstg_c_reg_4024_pp0_it30 <= ap_reg_ppstg_c_reg_4024_pp0_it29;
ap_reg_ppstg_c_reg_4024_pp0_it31 <= ap_reg_ppstg_c_reg_4024_pp0_it30;
ap_reg_ppstg_c_reg_4024_pp0_it32 <= ap_reg_ppstg_c_reg_4024_pp0_it31;
ap_reg_ppstg_c_reg_4024_pp0_it33 <= ap_reg_ppstg_c_reg_4024_pp0_it32;
ap_reg_ppstg_d_reg_4031_pp0_it11 <= d_reg_4031;
ap_reg_ppstg_d_reg_4031_pp0_it12 <= ap_reg_ppstg_d_reg_4031_pp0_it11;
ap_reg_ppstg_d_reg_4031_pp0_it13 <= ap_reg_ppstg_d_reg_4031_pp0_it12;
ap_reg_ppstg_d_reg_4031_pp0_it14 <= ap_reg_ppstg_d_reg_4031_pp0_it13;
ap_reg_ppstg_d_reg_4031_pp0_it15 <= ap_reg_ppstg_d_reg_4031_pp0_it14;
ap_reg_ppstg_d_reg_4031_pp0_it16 <= ap_reg_ppstg_d_reg_4031_pp0_it15;
ap_reg_ppstg_d_reg_4031_pp0_it17 <= ap_reg_ppstg_d_reg_4031_pp0_it16;
ap_reg_ppstg_d_reg_4031_pp0_it18 <= ap_reg_ppstg_d_reg_4031_pp0_it17;
ap_reg_ppstg_d_reg_4031_pp0_it19 <= ap_reg_ppstg_d_reg_4031_pp0_it18;
ap_reg_ppstg_d_reg_4031_pp0_it20 <= ap_reg_ppstg_d_reg_4031_pp0_it19;
ap_reg_ppstg_d_reg_4031_pp0_it21 <= ap_reg_ppstg_d_reg_4031_pp0_it20;
ap_reg_ppstg_d_reg_4031_pp0_it22 <= ap_reg_ppstg_d_reg_4031_pp0_it21;
ap_reg_ppstg_d_reg_4031_pp0_it23 <= ap_reg_ppstg_d_reg_4031_pp0_it22;
ap_reg_ppstg_d_reg_4031_pp0_it24 <= ap_reg_ppstg_d_reg_4031_pp0_it23;
ap_reg_ppstg_d_reg_4031_pp0_it25 <= ap_reg_ppstg_d_reg_4031_pp0_it24;
ap_reg_ppstg_d_reg_4031_pp0_it26 <= ap_reg_ppstg_d_reg_4031_pp0_it25;
ap_reg_ppstg_d_reg_4031_pp0_it27 <= ap_reg_ppstg_d_reg_4031_pp0_it26;
ap_reg_ppstg_d_reg_4031_pp0_it28 <= ap_reg_ppstg_d_reg_4031_pp0_it27;
ap_reg_ppstg_d_reg_4031_pp0_it29 <= ap_reg_ppstg_d_reg_4031_pp0_it28;
ap_reg_ppstg_d_reg_4031_pp0_it30 <= ap_reg_ppstg_d_reg_4031_pp0_it29;
ap_reg_ppstg_d_reg_4031_pp0_it31 <= ap_reg_ppstg_d_reg_4031_pp0_it30;
ap_reg_ppstg_d_reg_4031_pp0_it32 <= ap_reg_ppstg_d_reg_4031_pp0_it31;
ap_reg_ppstg_d_reg_4031_pp0_it33 <= ap_reg_ppstg_d_reg_4031_pp0_it32;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it10;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it11;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it12;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it13;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it14;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it15;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it16;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it17;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it18;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it19;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it20;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it21;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it22;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it23;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it24;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it25;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it26;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it27;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it28;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it2;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it29;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it30;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it31;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it32;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it33;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it34;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it35;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it36;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it37;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it38;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it3;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it39;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it40;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it41;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it42;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it43;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it44;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it45;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it46;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it47;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it48;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it4;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it49;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it50;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it51;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it52;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it53;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it54;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it55;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it56;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it57;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it58;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it5;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it59;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it60;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it61;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it62;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it63;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it64;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it65;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it66;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it67;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it68;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it6;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it69;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it70;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it71;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it72;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it73;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it74;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it75;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it76;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it77;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it78;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it7;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it79;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it80;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it81;
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it9 <= ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it8;
ap_reg_ppstg_e_reg_4038_pp0_it11 <= e_reg_4038;
ap_reg_ppstg_e_reg_4038_pp0_it12 <= ap_reg_ppstg_e_reg_4038_pp0_it11;
ap_reg_ppstg_e_reg_4038_pp0_it13 <= ap_reg_ppstg_e_reg_4038_pp0_it12;
ap_reg_ppstg_e_reg_4038_pp0_it14 <= ap_reg_ppstg_e_reg_4038_pp0_it13;
ap_reg_ppstg_e_reg_4038_pp0_it15 <= ap_reg_ppstg_e_reg_4038_pp0_it14;
ap_reg_ppstg_e_reg_4038_pp0_it16 <= ap_reg_ppstg_e_reg_4038_pp0_it15;
ap_reg_ppstg_e_reg_4038_pp0_it17 <= ap_reg_ppstg_e_reg_4038_pp0_it16;
ap_reg_ppstg_e_reg_4038_pp0_it18 <= ap_reg_ppstg_e_reg_4038_pp0_it17;
ap_reg_ppstg_e_reg_4038_pp0_it19 <= ap_reg_ppstg_e_reg_4038_pp0_it18;
ap_reg_ppstg_e_reg_4038_pp0_it20 <= ap_reg_ppstg_e_reg_4038_pp0_it19;
ap_reg_ppstg_e_reg_4038_pp0_it21 <= ap_reg_ppstg_e_reg_4038_pp0_it20;
ap_reg_ppstg_e_reg_4038_pp0_it22 <= ap_reg_ppstg_e_reg_4038_pp0_it21;
ap_reg_ppstg_e_reg_4038_pp0_it23 <= ap_reg_ppstg_e_reg_4038_pp0_it22;
ap_reg_ppstg_e_reg_4038_pp0_it24 <= ap_reg_ppstg_e_reg_4038_pp0_it23;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it10 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it9;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it11 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it10;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it12 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it11;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it13 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it12;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it14 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it13;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it15 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it14;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it16 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it15;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it17 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it16;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it18 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it17;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it19 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it18;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it2 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it1;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it20 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it19;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it21 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it20;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it22 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it21;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it23 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it22;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it24 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it23;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it25 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it24;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it26 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it25;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it27 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it26;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it28 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it27;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it29 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it28;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it3 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it2;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it30 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it29;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it31 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it30;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it32 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it31;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it33 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it32;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it34 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it33;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it35 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it34;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it36 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it35;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it37 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it36;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it38 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it37;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it39 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it38;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it4 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it3;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it40 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it39;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it41 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it40;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it42 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it41;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it43 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it42;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it44 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it43;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it45 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it44;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it46 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it45;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it47 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it46;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it48 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it47;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it49 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it48;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it5 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it4;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it50 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it49;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it51 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it50;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it52 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it51;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it53 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it52;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it54 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it53;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it55 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it54;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it56 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it55;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it57 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it56;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it58 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it57;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it59 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it58;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it6 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it5;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it60 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it59;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it61 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it60;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it62 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it61;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it63 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it62;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it64 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it63;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it65 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it64;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it66 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it65;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it67 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it66;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it68 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it67;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it69 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it68;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it7 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it6;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it70 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it69;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it71 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it70;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it72 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it71;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it73 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it72;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it74 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it73;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it75 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it74;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it76 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it75;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it77 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it76;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it78 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it77;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it79 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it78;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it8 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it7;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it80 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it79;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it81 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it80;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it82 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it81;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it9 <= ap_reg_ppstg_exitcond2_reg_3854_pp0_it8;
ap_reg_ppstg_f_reg_4045_pp0_it11 <= f_reg_4045;
ap_reg_ppstg_f_reg_4045_pp0_it12 <= ap_reg_ppstg_f_reg_4045_pp0_it11;
ap_reg_ppstg_f_reg_4045_pp0_it13 <= ap_reg_ppstg_f_reg_4045_pp0_it12;
ap_reg_ppstg_f_reg_4045_pp0_it14 <= ap_reg_ppstg_f_reg_4045_pp0_it13;
ap_reg_ppstg_f_reg_4045_pp0_it15 <= ap_reg_ppstg_f_reg_4045_pp0_it14;
ap_reg_ppstg_f_reg_4045_pp0_it16 <= ap_reg_ppstg_f_reg_4045_pp0_it15;
ap_reg_ppstg_f_reg_4045_pp0_it17 <= ap_reg_ppstg_f_reg_4045_pp0_it16;
ap_reg_ppstg_f_reg_4045_pp0_it18 <= ap_reg_ppstg_f_reg_4045_pp0_it17;
ap_reg_ppstg_f_reg_4045_pp0_it19 <= ap_reg_ppstg_f_reg_4045_pp0_it18;
ap_reg_ppstg_f_reg_4045_pp0_it20 <= ap_reg_ppstg_f_reg_4045_pp0_it19;
ap_reg_ppstg_f_reg_4045_pp0_it21 <= ap_reg_ppstg_f_reg_4045_pp0_it20;
ap_reg_ppstg_f_reg_4045_pp0_it22 <= ap_reg_ppstg_f_reg_4045_pp0_it21;
ap_reg_ppstg_f_reg_4045_pp0_it23 <= ap_reg_ppstg_f_reg_4045_pp0_it22;
ap_reg_ppstg_f_reg_4045_pp0_it24 <= ap_reg_ppstg_f_reg_4045_pp0_it23;
ap_reg_ppstg_g_reg_4073_pp0_it12 <= g_reg_4073;
ap_reg_ppstg_g_reg_4073_pp0_it13 <= ap_reg_ppstg_g_reg_4073_pp0_it12;
ap_reg_ppstg_g_reg_4073_pp0_it14 <= ap_reg_ppstg_g_reg_4073_pp0_it13;
ap_reg_ppstg_g_reg_4073_pp0_it15 <= ap_reg_ppstg_g_reg_4073_pp0_it14;
ap_reg_ppstg_g_reg_4073_pp0_it16 <= ap_reg_ppstg_g_reg_4073_pp0_it15;
ap_reg_ppstg_g_reg_4073_pp0_it17 <= ap_reg_ppstg_g_reg_4073_pp0_it16;
ap_reg_ppstg_g_reg_4073_pp0_it18 <= ap_reg_ppstg_g_reg_4073_pp0_it17;
ap_reg_ppstg_g_reg_4073_pp0_it19 <= ap_reg_ppstg_g_reg_4073_pp0_it18;
ap_reg_ppstg_g_reg_4073_pp0_it20 <= ap_reg_ppstg_g_reg_4073_pp0_it19;
ap_reg_ppstg_g_reg_4073_pp0_it21 <= ap_reg_ppstg_g_reg_4073_pp0_it20;
ap_reg_ppstg_g_reg_4073_pp0_it22 <= ap_reg_ppstg_g_reg_4073_pp0_it21;
ap_reg_ppstg_g_reg_4073_pp0_it23 <= ap_reg_ppstg_g_reg_4073_pp0_it22;
ap_reg_ppstg_g_reg_4073_pp0_it24 <= ap_reg_ppstg_g_reg_4073_pp0_it23;
ap_reg_ppstg_g_reg_4073_pp0_it25 <= ap_reg_ppstg_g_reg_4073_pp0_it24;
ap_reg_ppstg_g_reg_4073_pp0_it26 <= ap_reg_ppstg_g_reg_4073_pp0_it25;
ap_reg_ppstg_g_reg_4073_pp0_it27 <= ap_reg_ppstg_g_reg_4073_pp0_it26;
ap_reg_ppstg_g_reg_4073_pp0_it28 <= ap_reg_ppstg_g_reg_4073_pp0_it27;
ap_reg_ppstg_g_reg_4073_pp0_it29 <= ap_reg_ppstg_g_reg_4073_pp0_it28;
ap_reg_ppstg_g_reg_4073_pp0_it30 <= ap_reg_ppstg_g_reg_4073_pp0_it29;
ap_reg_ppstg_g_reg_4073_pp0_it31 <= ap_reg_ppstg_g_reg_4073_pp0_it30;
ap_reg_ppstg_g_reg_4073_pp0_it32 <= ap_reg_ppstg_g_reg_4073_pp0_it31;
ap_reg_ppstg_g_reg_4073_pp0_it33 <= ap_reg_ppstg_g_reg_4073_pp0_it32;
ap_reg_ppstg_h_reg_4080_pp0_it12 <= h_reg_4080;
ap_reg_ppstg_h_reg_4080_pp0_it13 <= ap_reg_ppstg_h_reg_4080_pp0_it12;
ap_reg_ppstg_h_reg_4080_pp0_it14 <= ap_reg_ppstg_h_reg_4080_pp0_it13;
ap_reg_ppstg_h_reg_4080_pp0_it15 <= ap_reg_ppstg_h_reg_4080_pp0_it14;
ap_reg_ppstg_h_reg_4080_pp0_it16 <= ap_reg_ppstg_h_reg_4080_pp0_it15;
ap_reg_ppstg_h_reg_4080_pp0_it17 <= ap_reg_ppstg_h_reg_4080_pp0_it16;
ap_reg_ppstg_h_reg_4080_pp0_it18 <= ap_reg_ppstg_h_reg_4080_pp0_it17;
ap_reg_ppstg_h_reg_4080_pp0_it19 <= ap_reg_ppstg_h_reg_4080_pp0_it18;
ap_reg_ppstg_h_reg_4080_pp0_it20 <= ap_reg_ppstg_h_reg_4080_pp0_it19;
ap_reg_ppstg_h_reg_4080_pp0_it21 <= ap_reg_ppstg_h_reg_4080_pp0_it20;
ap_reg_ppstg_h_reg_4080_pp0_it22 <= ap_reg_ppstg_h_reg_4080_pp0_it21;
ap_reg_ppstg_h_reg_4080_pp0_it23 <= ap_reg_ppstg_h_reg_4080_pp0_it22;
ap_reg_ppstg_h_reg_4080_pp0_it24 <= ap_reg_ppstg_h_reg_4080_pp0_it23;
ap_reg_ppstg_i_1_reg_4087_pp0_it12 <= i_1_reg_4087;
ap_reg_ppstg_i_1_reg_4087_pp0_it13 <= ap_reg_ppstg_i_1_reg_4087_pp0_it12;
ap_reg_ppstg_i_1_reg_4087_pp0_it14 <= ap_reg_ppstg_i_1_reg_4087_pp0_it13;
ap_reg_ppstg_i_1_reg_4087_pp0_it15 <= ap_reg_ppstg_i_1_reg_4087_pp0_it14;
ap_reg_ppstg_i_1_reg_4087_pp0_it16 <= ap_reg_ppstg_i_1_reg_4087_pp0_it15;
ap_reg_ppstg_i_1_reg_4087_pp0_it17 <= ap_reg_ppstg_i_1_reg_4087_pp0_it16;
ap_reg_ppstg_i_1_reg_4087_pp0_it18 <= ap_reg_ppstg_i_1_reg_4087_pp0_it17;
ap_reg_ppstg_i_1_reg_4087_pp0_it19 <= ap_reg_ppstg_i_1_reg_4087_pp0_it18;
ap_reg_ppstg_i_1_reg_4087_pp0_it20 <= ap_reg_ppstg_i_1_reg_4087_pp0_it19;
ap_reg_ppstg_i_1_reg_4087_pp0_it21 <= ap_reg_ppstg_i_1_reg_4087_pp0_it20;
ap_reg_ppstg_i_1_reg_4087_pp0_it22 <= ap_reg_ppstg_i_1_reg_4087_pp0_it21;
ap_reg_ppstg_i_1_reg_4087_pp0_it23 <= ap_reg_ppstg_i_1_reg_4087_pp0_it22;
ap_reg_ppstg_i_1_reg_4087_pp0_it24 <= ap_reg_ppstg_i_1_reg_4087_pp0_it23;
ap_reg_ppstg_j_reg_4052_pp0_it11 <= j_reg_4052;
ap_reg_ppstg_j_reg_4052_pp0_it12 <= ap_reg_ppstg_j_reg_4052_pp0_it11;
ap_reg_ppstg_j_reg_4052_pp0_it13 <= ap_reg_ppstg_j_reg_4052_pp0_it12;
ap_reg_ppstg_j_reg_4052_pp0_it14 <= ap_reg_ppstg_j_reg_4052_pp0_it13;
ap_reg_ppstg_j_reg_4052_pp0_it15 <= ap_reg_ppstg_j_reg_4052_pp0_it14;
ap_reg_ppstg_j_reg_4052_pp0_it16 <= ap_reg_ppstg_j_reg_4052_pp0_it15;
ap_reg_ppstg_j_reg_4052_pp0_it17 <= ap_reg_ppstg_j_reg_4052_pp0_it16;
ap_reg_ppstg_j_reg_4052_pp0_it18 <= ap_reg_ppstg_j_reg_4052_pp0_it17;
ap_reg_ppstg_j_reg_4052_pp0_it19 <= ap_reg_ppstg_j_reg_4052_pp0_it18;
ap_reg_ppstg_j_reg_4052_pp0_it20 <= ap_reg_ppstg_j_reg_4052_pp0_it19;
ap_reg_ppstg_j_reg_4052_pp0_it21 <= ap_reg_ppstg_j_reg_4052_pp0_it20;
ap_reg_ppstg_j_reg_4052_pp0_it22 <= ap_reg_ppstg_j_reg_4052_pp0_it21;
ap_reg_ppstg_j_reg_4052_pp0_it23 <= ap_reg_ppstg_j_reg_4052_pp0_it22;
ap_reg_ppstg_j_reg_4052_pp0_it24 <= ap_reg_ppstg_j_reg_4052_pp0_it23;
ap_reg_ppstg_k_reg_4059_pp0_it11 <= k_reg_4059;
ap_reg_ppstg_k_reg_4059_pp0_it12 <= ap_reg_ppstg_k_reg_4059_pp0_it11;
ap_reg_ppstg_k_reg_4059_pp0_it13 <= ap_reg_ppstg_k_reg_4059_pp0_it12;
ap_reg_ppstg_k_reg_4059_pp0_it14 <= ap_reg_ppstg_k_reg_4059_pp0_it13;
ap_reg_ppstg_k_reg_4059_pp0_it15 <= ap_reg_ppstg_k_reg_4059_pp0_it14;
ap_reg_ppstg_k_reg_4059_pp0_it16 <= ap_reg_ppstg_k_reg_4059_pp0_it15;
ap_reg_ppstg_k_reg_4059_pp0_it17 <= ap_reg_ppstg_k_reg_4059_pp0_it16;
ap_reg_ppstg_k_reg_4059_pp0_it18 <= ap_reg_ppstg_k_reg_4059_pp0_it17;
ap_reg_ppstg_k_reg_4059_pp0_it19 <= ap_reg_ppstg_k_reg_4059_pp0_it18;
ap_reg_ppstg_k_reg_4059_pp0_it20 <= ap_reg_ppstg_k_reg_4059_pp0_it19;
ap_reg_ppstg_k_reg_4059_pp0_it21 <= ap_reg_ppstg_k_reg_4059_pp0_it20;
ap_reg_ppstg_k_reg_4059_pp0_it22 <= ap_reg_ppstg_k_reg_4059_pp0_it21;
ap_reg_ppstg_k_reg_4059_pp0_it23 <= ap_reg_ppstg_k_reg_4059_pp0_it22;
ap_reg_ppstg_k_reg_4059_pp0_it24 <= ap_reg_ppstg_k_reg_4059_pp0_it23;
ap_reg_ppstg_l_reg_4066_pp0_it11 <= l_reg_4066;
ap_reg_ppstg_l_reg_4066_pp0_it12 <= ap_reg_ppstg_l_reg_4066_pp0_it11;
ap_reg_ppstg_l_reg_4066_pp0_it13 <= ap_reg_ppstg_l_reg_4066_pp0_it12;
ap_reg_ppstg_l_reg_4066_pp0_it14 <= ap_reg_ppstg_l_reg_4066_pp0_it13;
ap_reg_ppstg_l_reg_4066_pp0_it15 <= ap_reg_ppstg_l_reg_4066_pp0_it14;
ap_reg_ppstg_l_reg_4066_pp0_it16 <= ap_reg_ppstg_l_reg_4066_pp0_it15;
ap_reg_ppstg_l_reg_4066_pp0_it17 <= ap_reg_ppstg_l_reg_4066_pp0_it16;
ap_reg_ppstg_l_reg_4066_pp0_it18 <= ap_reg_ppstg_l_reg_4066_pp0_it17;
ap_reg_ppstg_l_reg_4066_pp0_it19 <= ap_reg_ppstg_l_reg_4066_pp0_it18;
ap_reg_ppstg_l_reg_4066_pp0_it20 <= ap_reg_ppstg_l_reg_4066_pp0_it19;
ap_reg_ppstg_l_reg_4066_pp0_it21 <= ap_reg_ppstg_l_reg_4066_pp0_it20;
ap_reg_ppstg_l_reg_4066_pp0_it22 <= ap_reg_ppstg_l_reg_4066_pp0_it21;
ap_reg_ppstg_l_reg_4066_pp0_it23 <= ap_reg_ppstg_l_reg_4066_pp0_it22;
ap_reg_ppstg_l_reg_4066_pp0_it24 <= ap_reg_ppstg_l_reg_4066_pp0_it23;
ap_reg_ppstg_l_reg_4066_pp0_it25 <= ap_reg_ppstg_l_reg_4066_pp0_it24;
ap_reg_ppstg_l_reg_4066_pp0_it26 <= ap_reg_ppstg_l_reg_4066_pp0_it25;
ap_reg_ppstg_l_reg_4066_pp0_it27 <= ap_reg_ppstg_l_reg_4066_pp0_it26;
ap_reg_ppstg_l_reg_4066_pp0_it28 <= ap_reg_ppstg_l_reg_4066_pp0_it27;
ap_reg_ppstg_l_reg_4066_pp0_it29 <= ap_reg_ppstg_l_reg_4066_pp0_it28;
ap_reg_ppstg_l_reg_4066_pp0_it30 <= ap_reg_ppstg_l_reg_4066_pp0_it29;
ap_reg_ppstg_l_reg_4066_pp0_it31 <= ap_reg_ppstg_l_reg_4066_pp0_it30;
ap_reg_ppstg_l_reg_4066_pp0_it32 <= ap_reg_ppstg_l_reg_4066_pp0_it31;
ap_reg_ppstg_l_reg_4066_pp0_it33 <= ap_reg_ppstg_l_reg_4066_pp0_it32;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2 <= rdx_assign_new_reg_3914;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it2;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it3;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it4;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it5;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it6;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it7;
ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it9 <= ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it8;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2 <= rdy_assign_new_reg_3919;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it2;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it3;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it4;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it5;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it6;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it7;
ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it9 <= ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it8;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2 <= rdz_assign_new_reg_3924;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it2;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it3;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it4;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it5;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it6;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it7;
ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it9 <= ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it8;
ap_reg_ppstg_reg_725_pp0_it10 <= ap_reg_ppstg_reg_725_pp0_it9;
ap_reg_ppstg_reg_725_pp0_it11 <= ap_reg_ppstg_reg_725_pp0_it10;
ap_reg_ppstg_reg_725_pp0_it12 <= ap_reg_ppstg_reg_725_pp0_it11;
ap_reg_ppstg_reg_725_pp0_it13 <= ap_reg_ppstg_reg_725_pp0_it12;
ap_reg_ppstg_reg_725_pp0_it14 <= ap_reg_ppstg_reg_725_pp0_it13;
ap_reg_ppstg_reg_725_pp0_it15 <= ap_reg_ppstg_reg_725_pp0_it14;
ap_reg_ppstg_reg_725_pp0_it16 <= ap_reg_ppstg_reg_725_pp0_it15;
ap_reg_ppstg_reg_725_pp0_it17 <= ap_reg_ppstg_reg_725_pp0_it16;
ap_reg_ppstg_reg_725_pp0_it18 <= ap_reg_ppstg_reg_725_pp0_it17;
ap_reg_ppstg_reg_725_pp0_it19 <= ap_reg_ppstg_reg_725_pp0_it18;
ap_reg_ppstg_reg_725_pp0_it2 <= reg_725;
ap_reg_ppstg_reg_725_pp0_it20 <= ap_reg_ppstg_reg_725_pp0_it19;
ap_reg_ppstg_reg_725_pp0_it21 <= ap_reg_ppstg_reg_725_pp0_it20;
ap_reg_ppstg_reg_725_pp0_it22 <= ap_reg_ppstg_reg_725_pp0_it21;
ap_reg_ppstg_reg_725_pp0_it23 <= ap_reg_ppstg_reg_725_pp0_it22;
ap_reg_ppstg_reg_725_pp0_it24 <= ap_reg_ppstg_reg_725_pp0_it23;
ap_reg_ppstg_reg_725_pp0_it25 <= ap_reg_ppstg_reg_725_pp0_it24;
ap_reg_ppstg_reg_725_pp0_it26 <= ap_reg_ppstg_reg_725_pp0_it25;
ap_reg_ppstg_reg_725_pp0_it27 <= ap_reg_ppstg_reg_725_pp0_it26;
ap_reg_ppstg_reg_725_pp0_it28 <= ap_reg_ppstg_reg_725_pp0_it27;
ap_reg_ppstg_reg_725_pp0_it29 <= ap_reg_ppstg_reg_725_pp0_it28;
ap_reg_ppstg_reg_725_pp0_it3 <= ap_reg_ppstg_reg_725_pp0_it2;
ap_reg_ppstg_reg_725_pp0_it30 <= ap_reg_ppstg_reg_725_pp0_it29;
ap_reg_ppstg_reg_725_pp0_it31 <= ap_reg_ppstg_reg_725_pp0_it30;
ap_reg_ppstg_reg_725_pp0_it32 <= ap_reg_ppstg_reg_725_pp0_it31;
ap_reg_ppstg_reg_725_pp0_it33 <= ap_reg_ppstg_reg_725_pp0_it32;
ap_reg_ppstg_reg_725_pp0_it34 <= ap_reg_ppstg_reg_725_pp0_it33;
ap_reg_ppstg_reg_725_pp0_it35 <= ap_reg_ppstg_reg_725_pp0_it34;
ap_reg_ppstg_reg_725_pp0_it36 <= ap_reg_ppstg_reg_725_pp0_it35;
ap_reg_ppstg_reg_725_pp0_it37 <= ap_reg_ppstg_reg_725_pp0_it36;
ap_reg_ppstg_reg_725_pp0_it38 <= ap_reg_ppstg_reg_725_pp0_it37;
ap_reg_ppstg_reg_725_pp0_it39 <= ap_reg_ppstg_reg_725_pp0_it38;
ap_reg_ppstg_reg_725_pp0_it4 <= ap_reg_ppstg_reg_725_pp0_it3;
ap_reg_ppstg_reg_725_pp0_it40 <= ap_reg_ppstg_reg_725_pp0_it39;
ap_reg_ppstg_reg_725_pp0_it41 <= ap_reg_ppstg_reg_725_pp0_it40;
ap_reg_ppstg_reg_725_pp0_it42 <= ap_reg_ppstg_reg_725_pp0_it41;
ap_reg_ppstg_reg_725_pp0_it43 <= ap_reg_ppstg_reg_725_pp0_it42;
ap_reg_ppstg_reg_725_pp0_it44 <= ap_reg_ppstg_reg_725_pp0_it43;
ap_reg_ppstg_reg_725_pp0_it45 <= ap_reg_ppstg_reg_725_pp0_it44;
ap_reg_ppstg_reg_725_pp0_it46 <= ap_reg_ppstg_reg_725_pp0_it45;
ap_reg_ppstg_reg_725_pp0_it47 <= ap_reg_ppstg_reg_725_pp0_it46;
ap_reg_ppstg_reg_725_pp0_it48 <= ap_reg_ppstg_reg_725_pp0_it47;
ap_reg_ppstg_reg_725_pp0_it49 <= ap_reg_ppstg_reg_725_pp0_it48;
ap_reg_ppstg_reg_725_pp0_it5 <= ap_reg_ppstg_reg_725_pp0_it4;
ap_reg_ppstg_reg_725_pp0_it50 <= ap_reg_ppstg_reg_725_pp0_it49;
ap_reg_ppstg_reg_725_pp0_it51 <= ap_reg_ppstg_reg_725_pp0_it50;
ap_reg_ppstg_reg_725_pp0_it52 <= ap_reg_ppstg_reg_725_pp0_it51;
ap_reg_ppstg_reg_725_pp0_it53 <= ap_reg_ppstg_reg_725_pp0_it52;
ap_reg_ppstg_reg_725_pp0_it54 <= ap_reg_ppstg_reg_725_pp0_it53;
ap_reg_ppstg_reg_725_pp0_it55 <= ap_reg_ppstg_reg_725_pp0_it54;
ap_reg_ppstg_reg_725_pp0_it56 <= ap_reg_ppstg_reg_725_pp0_it55;
ap_reg_ppstg_reg_725_pp0_it57 <= ap_reg_ppstg_reg_725_pp0_it56;
ap_reg_ppstg_reg_725_pp0_it58 <= ap_reg_ppstg_reg_725_pp0_it57;
ap_reg_ppstg_reg_725_pp0_it59 <= ap_reg_ppstg_reg_725_pp0_it58;
ap_reg_ppstg_reg_725_pp0_it6 <= ap_reg_ppstg_reg_725_pp0_it5;
ap_reg_ppstg_reg_725_pp0_it60 <= ap_reg_ppstg_reg_725_pp0_it59;
ap_reg_ppstg_reg_725_pp0_it61 <= ap_reg_ppstg_reg_725_pp0_it60;
ap_reg_ppstg_reg_725_pp0_it62 <= ap_reg_ppstg_reg_725_pp0_it61;
ap_reg_ppstg_reg_725_pp0_it63 <= ap_reg_ppstg_reg_725_pp0_it62;
ap_reg_ppstg_reg_725_pp0_it64 <= ap_reg_ppstg_reg_725_pp0_it63;
ap_reg_ppstg_reg_725_pp0_it65 <= ap_reg_ppstg_reg_725_pp0_it64;
ap_reg_ppstg_reg_725_pp0_it66 <= ap_reg_ppstg_reg_725_pp0_it65;
ap_reg_ppstg_reg_725_pp0_it67 <= ap_reg_ppstg_reg_725_pp0_it66;
ap_reg_ppstg_reg_725_pp0_it68 <= ap_reg_ppstg_reg_725_pp0_it67;
ap_reg_ppstg_reg_725_pp0_it69 <= ap_reg_ppstg_reg_725_pp0_it68;
ap_reg_ppstg_reg_725_pp0_it7 <= ap_reg_ppstg_reg_725_pp0_it6;
ap_reg_ppstg_reg_725_pp0_it70 <= ap_reg_ppstg_reg_725_pp0_it69;
ap_reg_ppstg_reg_725_pp0_it71 <= ap_reg_ppstg_reg_725_pp0_it70;
ap_reg_ppstg_reg_725_pp0_it72 <= ap_reg_ppstg_reg_725_pp0_it71;
ap_reg_ppstg_reg_725_pp0_it73 <= ap_reg_ppstg_reg_725_pp0_it72;
ap_reg_ppstg_reg_725_pp0_it74 <= ap_reg_ppstg_reg_725_pp0_it73;
ap_reg_ppstg_reg_725_pp0_it75 <= ap_reg_ppstg_reg_725_pp0_it74;
ap_reg_ppstg_reg_725_pp0_it76 <= ap_reg_ppstg_reg_725_pp0_it75;
ap_reg_ppstg_reg_725_pp0_it77 <= ap_reg_ppstg_reg_725_pp0_it76;
ap_reg_ppstg_reg_725_pp0_it78 <= ap_reg_ppstg_reg_725_pp0_it77;
ap_reg_ppstg_reg_725_pp0_it79 <= ap_reg_ppstg_reg_725_pp0_it78;
ap_reg_ppstg_reg_725_pp0_it8 <= ap_reg_ppstg_reg_725_pp0_it7;
ap_reg_ppstg_reg_725_pp0_it80 <= ap_reg_ppstg_reg_725_pp0_it79;
ap_reg_ppstg_reg_725_pp0_it81 <= ap_reg_ppstg_reg_725_pp0_it80;
ap_reg_ppstg_reg_725_pp0_it9 <= ap_reg_ppstg_reg_725_pp0_it8;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48 <= tmp_25_i_reg_4275;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it48;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it49;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it50;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it51;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it52;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it53;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it54;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it55;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it56;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it57;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it58;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it59;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it60;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it61;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it62;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it63;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it64;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it65;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it66;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it67;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it68;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it69;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it70;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it71;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it72;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it73;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it74;
ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76 <= ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48 <= tmp_31_i_reg_4280;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it48;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it49;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it50;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it51;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it52;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it53;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it54;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it55;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it56;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it57;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it58;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it59;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it60;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it61;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it62;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it63;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it64;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it65;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it66;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it67;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it68;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it69;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it70;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it71;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it72;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it73;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it74;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it75;
ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77 <= ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it76;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48 <= tmp_36_i_reg_4285;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it48;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it49;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it50;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it51;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it52;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it53;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it54;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it55;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it56;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it57;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it58;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it59;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it60;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it61;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it62;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it63;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it64;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it65;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it66;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it67;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it68;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it69;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it70;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it71;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it72;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it73;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it74;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it75;
ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77 <= ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it76;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300)) begin
ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it1 <= data_array_addr_20_reg_3863;
ap_reg_ppstg_exitcond2_reg_3854_pp0_it1 <= exitcond2_reg_3854;
exitcond2_reg_3854 <= exitcond2_fu_2840_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it81)) begin
beta_addr_111281129_part_set_reg_4307 <= beta_addr_111281129_part_set_fu_3103_p5;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300) & (ap_const_lv1_0 == exitcond2_fu_2840_p2))) begin
data_array_addr_20_reg_3863 <= tmp_1_fu_2852_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86))) begin
data_array_load_1_reg_3743 <= data_array_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st73_fsm_72))) begin
data_array_load_2_reg_3722 <= data_array_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87))) begin
data_array_load_3_reg_3759 <= data_array_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it10)) begin
g_reg_4073 <= g_fu_3055_p1;
h_reg_4080 <= h_fu_3059_p1;
i_1_reg_4087 <= i_1_fu_3063_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it76)) begin
im_reg_4290 <= grp_fu_630_p2;
tmp_61_neg_i_reg_4297 <= tmp_61_neg_i_fu_3071_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14))) begin
ins_data_val14_reg_3415 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15))) begin
ins_data_val15_reg_3420 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16))) begin
ins_data_val16_reg_3425 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17))) begin
ins_data_val17_reg_3430 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18))) begin
ins_data_val18_reg_3435 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_19))) begin
ins_data_val19_reg_3440 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st21_fsm_20))) begin
ins_data_val20_reg_3445 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st22_fsm_21))) begin
ins_data_val21_reg_3450 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st23_fsm_22))) begin
ins_data_val22_reg_3455 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st24_fsm_23))) begin
ins_data_val23_reg_3460 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st25_fsm_24))) begin
ins_data_val24_reg_3465 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st26_fsm_25))) begin
ins_data_val25_reg_3470 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st27_fsm_26))) begin
ins_data_val26_reg_3475 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st28_fsm_27))) begin
ins_data_val27_reg_3480 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st29_fsm_28))) begin
ins_data_val28_reg_3485 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st30_fsm_29))) begin
ins_data_val29_reg_3490 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st31_fsm_30))) begin
ins_data_val30_reg_3495 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st32_fsm_31))) begin
ins_data_val31_reg_3500 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st33_fsm_32))) begin
ins_data_val32_reg_3505 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st34_fsm_33))) begin
ins_data_val33_reg_3510 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st35_fsm_34))) begin
ins_data_val34_reg_3515 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st36_fsm_35))) begin
ins_data_val35_reg_3520 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st37_fsm_36))) begin
ins_data_val36_reg_3525 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st38_fsm_37))) begin
ins_data_val37_reg_3530 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st39_fsm_38))) begin
ins_data_val38_reg_3535 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st40_fsm_39))) begin
ins_data_val39_reg_3540 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st41_fsm_40))) begin
ins_data_val40_reg_3545 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st42_fsm_41))) begin
ins_data_val41_reg_3550 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st43_fsm_42))) begin
ins_data_val42_reg_3555 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st44_fsm_43))) begin
ins_data_val43_reg_3560 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st45_fsm_44))) begin
ins_data_val44_reg_3565 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st46_fsm_45))) begin
ins_data_val45_reg_3570 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st47_fsm_46))) begin
ins_data_val46_reg_3575 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st48_fsm_47))) begin
ins_data_val47_reg_3580 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st49_fsm_48))) begin
ins_data_val48_reg_3585 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st50_fsm_49))) begin
ins_data_val49_reg_3590 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st51_fsm_50))) begin
ins_data_val50_reg_3595 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st52_fsm_51))) begin
ins_data_val51_reg_3600 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st53_fsm_52))) begin
ins_data_val52_reg_3605 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st54_fsm_53))) begin
ins_data_val53_reg_3610 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st55_fsm_54))) begin
ins_data_val54_reg_3615 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st56_fsm_55))) begin
ins_data_val55_reg_3620 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st57_fsm_56))) begin
ins_data_val56_reg_3625 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st58_fsm_57))) begin
ins_data_val57_reg_3630 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st59_fsm_58))) begin
ins_data_val58_reg_3635 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st60_fsm_59))) begin
ins_data_val59_reg_3640 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st61_fsm_60))) begin
ins_data_val60_reg_3645 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st62_fsm_61))) begin
ins_data_val61_reg_3650 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st63_fsm_62))) begin
ins_data_val62_reg_3655 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st64_fsm_63))) begin
ins_data_val63_reg_3660 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st65_fsm_64))) begin
ins_data_val64_reg_3665 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st66_fsm_65))) begin
ins_data_val65_reg_3670 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st67_fsm_66))) begin
ins_data_val66_reg_3675 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st68_fsm_67))) begin
ins_data_val67_reg_3680 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st69_fsm_68))) begin
ins_data_val68_reg_3685 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st70_fsm_69))) begin
ins_data_val69_reg_3690 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st71_fsm_70))) begin
ins_data_val70_reg_3695 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st72_fsm_71))) begin
ins_data_val71_reg_3706 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299))) begin
ins_dest_V_val_reg_3849 <= ins_TDEST;
ins_id_V_val_reg_3844 <= ins_TID;
ins_keep_V_val_reg_3824 <= ins_TKEEP;
ins_last_V_val_reg_3839 <= ins_TLAST;
ins_strb_V_val_reg_3829 <= ins_TSTRB;
ins_user_V_val_reg_3834 <= ins_TUSER;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it46)) begin
m_reg_4270 <= grp_fu_506_p2;
tmp_25_i_reg_4275 <= grp_fu_510_p2;
tmp_31_i_reg_4280 <= grp_fu_514_p2;
tmp_36_i_reg_4285 <= grp_fu_518_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300) & (exitcond2_reg_3854 == ap_const_lv1_0))) begin
rdx_assign_new_reg_3914 <= {{data_array_q0[ap_const_lv32_13F : ap_const_lv32_120]}};
rdy_assign_new_reg_3919 <= {{data_array_q0[ap_const_lv32_15F : ap_const_lv32_140]}};
rdz_assign_new_reg_3924 <= {{data_array_q0[ap_const_lv32_17F : ap_const_lv32_160]}};
rex_assign_new_reg_3929 <= {{data_array_q0[ap_const_lv32_19F : ap_const_lv32_180]}};
rey_assign_new_reg_3934 <= {{data_array_q0[ap_const_lv32_1BF : ap_const_lv32_1A0]}};
rez_assign_new_reg_3939 <= {{data_array_q0[ap_const_lv32_1DF : ap_const_lv32_1C0]}};
tmp_22_reg_3869 <= tmp_22_fu_2857_p1;
v0y_assign_new_reg_3874 <= {{data_array_q0[ap_const_lv32_3F : ap_const_lv32_20]}};
v0z_assign_new_reg_3879 <= {{data_array_q0[ap_const_lv32_5F : ap_const_lv32_40]}};
v1x_assign_new_reg_3884 <= {{data_array_q0[ap_const_lv32_7F : ap_const_lv32_60]}};
v1y_assign_new_reg_3889 <= {{data_array_q0[ap_const_lv32_9F : ap_const_lv32_80]}};
v1z_assign_new_reg_3894 <= {{data_array_q0[ap_const_lv32_BF : ap_const_lv32_A0]}};
v2x_assign_new_reg_3899 <= {{data_array_q0[ap_const_lv32_DF : ap_const_lv32_C0]}};
v2y_assign_new_reg_3904 <= {{data_array_q0[ap_const_lv32_FF : ap_const_lv32_E0]}};
v2z_assign_new_reg_3909 <= {{data_array_q0[ap_const_lv32_11F : ap_const_lv32_100]}};
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ins_TVALID == ap_const_logic_0)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st73_fsm_72)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st76_fsm_75)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st91_fsm_90)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st106_fsm_105)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st121_fsm_120)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st136_fsm_135)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st151_fsm_150)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st181_fsm_180)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st196_fsm_195)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st211_fsm_210)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st226_fsm_225)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st241_fsm_240)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st256_fsm_255)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st271_fsm_270)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st286_fsm_285)))) begin
reg_669 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st74_fsm_73)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st92_fsm_91)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st107_fsm_106)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st137_fsm_136)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st152_fsm_151)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st167_fsm_166)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st182_fsm_181)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st197_fsm_196)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st212_fsm_211)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st227_fsm_226)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st242_fsm_241)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st257_fsm_256)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st272_fsm_271)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st287_fsm_286)))) begin
reg_673 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st108_fsm_107)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st123_fsm_122)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st138_fsm_137)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st153_fsm_152)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st168_fsm_167)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st183_fsm_182)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st198_fsm_197)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st213_fsm_212)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st228_fsm_227)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st243_fsm_242)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st258_fsm_257)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st273_fsm_272)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st288_fsm_287)))) begin
reg_677 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st94_fsm_93)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st109_fsm_108)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st124_fsm_123)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st154_fsm_153)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st169_fsm_168)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st184_fsm_183)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st199_fsm_198)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st214_fsm_213)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st229_fsm_228)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st244_fsm_243)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st259_fsm_258)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st274_fsm_273)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st289_fsm_288)))) begin
reg_681 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st95_fsm_94)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st110_fsm_109)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st125_fsm_124)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st140_fsm_139)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st155_fsm_154)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st170_fsm_169)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st185_fsm_184)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st200_fsm_199)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st215_fsm_214)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st230_fsm_229)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st245_fsm_244)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st260_fsm_259)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st275_fsm_274)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st290_fsm_289)))) begin
reg_685 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st96_fsm_95)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st111_fsm_110)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st126_fsm_125)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st141_fsm_140)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st171_fsm_170)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st186_fsm_185)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st201_fsm_200)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st216_fsm_215)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st231_fsm_230)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st246_fsm_245)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st261_fsm_260)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st276_fsm_275)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st291_fsm_290)))) begin
reg_689 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st82_fsm_81)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st97_fsm_96)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st112_fsm_111)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st127_fsm_126)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st142_fsm_141)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st157_fsm_156)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st172_fsm_171)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st187_fsm_186)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st202_fsm_201)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st217_fsm_216)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st232_fsm_231)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st247_fsm_246)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st262_fsm_261)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st277_fsm_276)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st292_fsm_291)))) begin
reg_693 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st83_fsm_82)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st98_fsm_97)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st113_fsm_112)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st128_fsm_127)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st143_fsm_142)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st158_fsm_157)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st173_fsm_172)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st188_fsm_187)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st203_fsm_202)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st218_fsm_217)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st233_fsm_232)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st248_fsm_247)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st263_fsm_262)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st278_fsm_277)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st293_fsm_292)))) begin
reg_697 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st84_fsm_83)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st99_fsm_98)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st114_fsm_113)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st129_fsm_128)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st144_fsm_143)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st159_fsm_158)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st174_fsm_173)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st189_fsm_188)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st204_fsm_203)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st219_fsm_218)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st234_fsm_233)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st249_fsm_248)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st264_fsm_263)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st279_fsm_278)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st294_fsm_293)))) begin
reg_701 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st85_fsm_84)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st100_fsm_99)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st130_fsm_129)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st145_fsm_144)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st160_fsm_159)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st175_fsm_174)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st190_fsm_189)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st205_fsm_204)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st220_fsm_219)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st235_fsm_234)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st250_fsm_249)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st265_fsm_264)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st280_fsm_279)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st295_fsm_294)))) begin
reg_705 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st86_fsm_85)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st101_fsm_100)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st116_fsm_115)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st131_fsm_130)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st146_fsm_145)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st161_fsm_160)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st176_fsm_175)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st191_fsm_190)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st206_fsm_205)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st221_fsm_220)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st236_fsm_235)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st251_fsm_250)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st266_fsm_265)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st281_fsm_280)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st296_fsm_295)))) begin
reg_709 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st102_fsm_101)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st132_fsm_131)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st147_fsm_146)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st162_fsm_161)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st177_fsm_176)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st192_fsm_191)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st207_fsm_206)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st222_fsm_221)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st237_fsm_236)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st252_fsm_251)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st267_fsm_266)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st282_fsm_281)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st297_fsm_296)))) begin
reg_713 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st103_fsm_102)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st118_fsm_117)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st133_fsm_132)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st163_fsm_162)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st178_fsm_177)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st193_fsm_192)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st208_fsm_207)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st223_fsm_222)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st238_fsm_237)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st253_fsm_252)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st268_fsm_267)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st283_fsm_282)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st298_fsm_297)))) begin
reg_717 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st89_fsm_88)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st104_fsm_103)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st119_fsm_118)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st134_fsm_133)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st164_fsm_163)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st179_fsm_178)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st194_fsm_193)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st209_fsm_208)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st224_fsm_223)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st239_fsm_238)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st254_fsm_253)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st269_fsm_268)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st284_fsm_283)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st299_fsm_298)))) begin
reg_721 <= ins_TDATA;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st72_fsm_71)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300) & (exitcond2_reg_3854 == ap_const_lv1_0)))) begin
reg_725 <= data_array_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st386_fsm_302) & ~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st389_fsm_305)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st392_fsm_308)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st395_fsm_311)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st398_fsm_314)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st401_fsm_317)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st404_fsm_320)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st407_fsm_323)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st410_fsm_326)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st413_fsm_329)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st416_fsm_332)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st419_fsm_335)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st422_fsm_338)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st425_fsm_341)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st428_fsm_344)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st431_fsm_347)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st434_fsm_350)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st437_fsm_353)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st440_fsm_356)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st443_fsm_359)))) begin
reg_729 <= {{data_array_q1[ap_const_lv32_21F : ap_const_lv32_200]}};
reg_733 <= {{data_array_q1[ap_const_lv32_23F : ap_const_lv32_220]}};
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it32)) begin
tmp_10_i_reg_4218 <= grp_fu_482_p2;
tmp_23_i_reg_4224 <= grp_fu_486_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it37)) begin
tmp_11_i_reg_4235 <= grp_fu_602_p2;
tmp_20_i_reg_4240 <= grp_fu_494_p2;
tmp_24_i_reg_4245 <= grp_fu_606_p2;
tmp_29_i_reg_4250 <= grp_fu_498_p2;
tmp_30_i_reg_4255 <= grp_fu_610_p2;
tmp_34_i_reg_4260 <= grp_fu_502_p2;
tmp_35_i_reg_4265 <= grp_fu_614_p2;
tmp_7_i_reg_4230 <= grp_fu_490_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it14)) begin
tmp_12_i_reg_4114 <= grp_fu_538_p2;
tmp_13_i_reg_4119 <= grp_fu_542_p2;
tmp_16_i_reg_4124 <= grp_fu_546_p2;
tmp_17_i_reg_4129 <= grp_fu_550_p2;
tmp_3_i_reg_4104 <= grp_fu_530_p2;
tmp_4_i_reg_4109 <= grp_fu_534_p2;
tmp_i_311_reg_4099 <= grp_fu_526_p2;
tmp_i_reg_4094 <= grp_fu_522_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it23)) begin
tmp_14_i_reg_4156 <= grp_fu_474_p2;
tmp_18_i_reg_4162 <= grp_fu_478_p2;
tmp_1_i_reg_4134 <= grp_fu_466_p2;
tmp_21_i_reg_4168 <= grp_fu_562_p2;
tmp_22_i_reg_4173 <= grp_fu_566_p2;
tmp_5_i_reg_4140 <= grp_fu_470_p2;
tmp_8_i_reg_4146 <= grp_fu_554_p2;
tmp_9_i_reg_4151 <= grp_fu_558_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it28)) begin
tmp_15_i_reg_4188 <= grp_fu_578_p2;
tmp_19_i_reg_4193 <= grp_fu_582_p2;
tmp_27_i_reg_4198 <= grp_fu_586_p2;
tmp_28_i_reg_4203 <= grp_fu_590_p2;
tmp_2_i_reg_4178 <= grp_fu_570_p2;
tmp_32_i_reg_4208 <= grp_fu_594_p2;
tmp_33_i_reg_4213 <= grp_fu_598_p2;
tmp_6_i_reg_4183 <= grp_fu_574_p2;
end
end
/// ap_sig_cseq_ST_pp0_stg0_fsm_300 assign process. ///
always @ (ap_sig_bdd_2694)
begin
if (ap_sig_bdd_2694) begin
ap_sig_cseq_ST_pp0_stg0_fsm_300 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp0_stg0_fsm_300 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st100_fsm_99 assign process. ///
always @ (ap_sig_bdd_1733)
begin
if (ap_sig_bdd_1733) begin
ap_sig_cseq_ST_st100_fsm_99 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st100_fsm_99 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st101_fsm_100 assign process. ///
always @ (ap_sig_bdd_1877)
begin
if (ap_sig_bdd_1877) begin
ap_sig_cseq_ST_st101_fsm_100 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st101_fsm_100 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st102_fsm_101 assign process. ///
always @ (ap_sig_bdd_2021)
begin
if (ap_sig_bdd_2021) begin
ap_sig_cseq_ST_st102_fsm_101 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st102_fsm_101 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st103_fsm_102 assign process. ///
always @ (ap_sig_bdd_2165)
begin
if (ap_sig_bdd_2165) begin
ap_sig_cseq_ST_st103_fsm_102 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st103_fsm_102 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st104_fsm_103 assign process. ///
always @ (ap_sig_bdd_2309)
begin
if (ap_sig_bdd_2309) begin
ap_sig_cseq_ST_st104_fsm_103 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st104_fsm_103 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st105_fsm_104 assign process. ///
always @ (ap_sig_bdd_3447)
begin
if (ap_sig_bdd_3447) begin
ap_sig_cseq_ST_st105_fsm_104 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st105_fsm_104 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st106_fsm_105 assign process. ///
always @ (ap_sig_bdd_437)
begin
if (ap_sig_bdd_437) begin
ap_sig_cseq_ST_st106_fsm_105 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st106_fsm_105 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st107_fsm_106 assign process. ///
always @ (ap_sig_bdd_590)
begin
if (ap_sig_bdd_590) begin
ap_sig_cseq_ST_st107_fsm_106 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st107_fsm_106 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st108_fsm_107 assign process. ///
always @ (ap_sig_bdd_734)
begin
if (ap_sig_bdd_734) begin
ap_sig_cseq_ST_st108_fsm_107 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st108_fsm_107 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st109_fsm_108 assign process. ///
always @ (ap_sig_bdd_878)
begin
if (ap_sig_bdd_878) begin
ap_sig_cseq_ST_st109_fsm_108 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st109_fsm_108 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st10_fsm_9 assign process. ///
always @ (ap_sig_bdd_1716)
begin
if (ap_sig_bdd_1716) begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st10_fsm_9 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st110_fsm_109 assign process. ///
always @ (ap_sig_bdd_1022)
begin
if (ap_sig_bdd_1022) begin
ap_sig_cseq_ST_st110_fsm_109 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st110_fsm_109 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st111_fsm_110 assign process. ///
always @ (ap_sig_bdd_1166)
begin
if (ap_sig_bdd_1166) begin
ap_sig_cseq_ST_st111_fsm_110 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st111_fsm_110 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st112_fsm_111 assign process. ///
always @ (ap_sig_bdd_1310)
begin
if (ap_sig_bdd_1310) begin
ap_sig_cseq_ST_st112_fsm_111 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st112_fsm_111 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st113_fsm_112 assign process. ///
always @ (ap_sig_bdd_1454)
begin
if (ap_sig_bdd_1454) begin
ap_sig_cseq_ST_st113_fsm_112 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st113_fsm_112 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st114_fsm_113 assign process. ///
always @ (ap_sig_bdd_1598)
begin
if (ap_sig_bdd_1598) begin
ap_sig_cseq_ST_st114_fsm_113 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st114_fsm_113 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st115_fsm_114 assign process. ///
always @ (ap_sig_bdd_1742)
begin
if (ap_sig_bdd_1742) begin
ap_sig_cseq_ST_st115_fsm_114 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st115_fsm_114 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st116_fsm_115 assign process. ///
always @ (ap_sig_bdd_1886)
begin
if (ap_sig_bdd_1886) begin
ap_sig_cseq_ST_st116_fsm_115 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st116_fsm_115 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st117_fsm_116 assign process. ///
always @ (ap_sig_bdd_2030)
begin
if (ap_sig_bdd_2030) begin
ap_sig_cseq_ST_st117_fsm_116 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st117_fsm_116 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st118_fsm_117 assign process. ///
always @ (ap_sig_bdd_2174)
begin
if (ap_sig_bdd_2174) begin
ap_sig_cseq_ST_st118_fsm_117 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st118_fsm_117 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st119_fsm_118 assign process. ///
always @ (ap_sig_bdd_2318)
begin
if (ap_sig_bdd_2318) begin
ap_sig_cseq_ST_st119_fsm_118 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st119_fsm_118 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st11_fsm_10 assign process. ///
always @ (ap_sig_bdd_1860)
begin
if (ap_sig_bdd_1860) begin
ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st11_fsm_10 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st120_fsm_119 assign process. ///
always @ (ap_sig_bdd_3457)
begin
if (ap_sig_bdd_3457) begin
ap_sig_cseq_ST_st120_fsm_119 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st120_fsm_119 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st121_fsm_120 assign process. ///
always @ (ap_sig_bdd_446)
begin
if (ap_sig_bdd_446) begin
ap_sig_cseq_ST_st121_fsm_120 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st121_fsm_120 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st122_fsm_121 assign process. ///
always @ (ap_sig_bdd_599)
begin
if (ap_sig_bdd_599) begin
ap_sig_cseq_ST_st122_fsm_121 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st122_fsm_121 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st123_fsm_122 assign process. ///
always @ (ap_sig_bdd_743)
begin
if (ap_sig_bdd_743) begin
ap_sig_cseq_ST_st123_fsm_122 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st123_fsm_122 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st124_fsm_123 assign process. ///
always @ (ap_sig_bdd_887)
begin
if (ap_sig_bdd_887) begin
ap_sig_cseq_ST_st124_fsm_123 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st124_fsm_123 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st125_fsm_124 assign process. ///
always @ (ap_sig_bdd_1031)
begin
if (ap_sig_bdd_1031) begin
ap_sig_cseq_ST_st125_fsm_124 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st125_fsm_124 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st126_fsm_125 assign process. ///
always @ (ap_sig_bdd_1175)
begin
if (ap_sig_bdd_1175) begin
ap_sig_cseq_ST_st126_fsm_125 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st126_fsm_125 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st127_fsm_126 assign process. ///
always @ (ap_sig_bdd_1319)
begin
if (ap_sig_bdd_1319) begin
ap_sig_cseq_ST_st127_fsm_126 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st127_fsm_126 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st128_fsm_127 assign process. ///
always @ (ap_sig_bdd_1463)
begin
if (ap_sig_bdd_1463) begin
ap_sig_cseq_ST_st128_fsm_127 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st128_fsm_127 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st129_fsm_128 assign process. ///
always @ (ap_sig_bdd_1607)
begin
if (ap_sig_bdd_1607) begin
ap_sig_cseq_ST_st129_fsm_128 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st129_fsm_128 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st12_fsm_11 assign process. ///
always @ (ap_sig_bdd_2004)
begin
if (ap_sig_bdd_2004) begin
ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st12_fsm_11 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st130_fsm_129 assign process. ///
always @ (ap_sig_bdd_1751)
begin
if (ap_sig_bdd_1751) begin
ap_sig_cseq_ST_st130_fsm_129 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st130_fsm_129 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st131_fsm_130 assign process. ///
always @ (ap_sig_bdd_1895)
begin
if (ap_sig_bdd_1895) begin
ap_sig_cseq_ST_st131_fsm_130 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st131_fsm_130 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st132_fsm_131 assign process. ///
always @ (ap_sig_bdd_2039)
begin
if (ap_sig_bdd_2039) begin
ap_sig_cseq_ST_st132_fsm_131 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st132_fsm_131 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st133_fsm_132 assign process. ///
always @ (ap_sig_bdd_2183)
begin
if (ap_sig_bdd_2183) begin
ap_sig_cseq_ST_st133_fsm_132 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st133_fsm_132 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st134_fsm_133 assign process. ///
always @ (ap_sig_bdd_2327)
begin
if (ap_sig_bdd_2327) begin
ap_sig_cseq_ST_st134_fsm_133 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st134_fsm_133 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st135_fsm_134 assign process. ///
always @ (ap_sig_bdd_3467)
begin
if (ap_sig_bdd_3467) begin
ap_sig_cseq_ST_st135_fsm_134 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st135_fsm_134 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st136_fsm_135 assign process. ///
always @ (ap_sig_bdd_455)
begin
if (ap_sig_bdd_455) begin
ap_sig_cseq_ST_st136_fsm_135 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st136_fsm_135 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st137_fsm_136 assign process. ///
always @ (ap_sig_bdd_608)
begin
if (ap_sig_bdd_608) begin
ap_sig_cseq_ST_st137_fsm_136 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st137_fsm_136 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st138_fsm_137 assign process. ///
always @ (ap_sig_bdd_752)
begin
if (ap_sig_bdd_752) begin
ap_sig_cseq_ST_st138_fsm_137 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st138_fsm_137 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st139_fsm_138 assign process. ///
always @ (ap_sig_bdd_896)
begin
if (ap_sig_bdd_896) begin
ap_sig_cseq_ST_st139_fsm_138 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st139_fsm_138 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st13_fsm_12 assign process. ///
always @ (ap_sig_bdd_2148)
begin
if (ap_sig_bdd_2148) begin
ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st13_fsm_12 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st140_fsm_139 assign process. ///
always @ (ap_sig_bdd_1040)
begin
if (ap_sig_bdd_1040) begin
ap_sig_cseq_ST_st140_fsm_139 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st140_fsm_139 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st141_fsm_140 assign process. ///
always @ (ap_sig_bdd_1184)
begin
if (ap_sig_bdd_1184) begin
ap_sig_cseq_ST_st141_fsm_140 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st141_fsm_140 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st142_fsm_141 assign process. ///
always @ (ap_sig_bdd_1328)
begin
if (ap_sig_bdd_1328) begin
ap_sig_cseq_ST_st142_fsm_141 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st142_fsm_141 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st143_fsm_142 assign process. ///
always @ (ap_sig_bdd_1472)
begin
if (ap_sig_bdd_1472) begin
ap_sig_cseq_ST_st143_fsm_142 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st143_fsm_142 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st144_fsm_143 assign process. ///
always @ (ap_sig_bdd_1616)
begin
if (ap_sig_bdd_1616) begin
ap_sig_cseq_ST_st144_fsm_143 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st144_fsm_143 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st145_fsm_144 assign process. ///
always @ (ap_sig_bdd_1760)
begin
if (ap_sig_bdd_1760) begin
ap_sig_cseq_ST_st145_fsm_144 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st145_fsm_144 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st146_fsm_145 assign process. ///
always @ (ap_sig_bdd_1904)
begin
if (ap_sig_bdd_1904) begin
ap_sig_cseq_ST_st146_fsm_145 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st146_fsm_145 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st147_fsm_146 assign process. ///
always @ (ap_sig_bdd_2048)
begin
if (ap_sig_bdd_2048) begin
ap_sig_cseq_ST_st147_fsm_146 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st147_fsm_146 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st148_fsm_147 assign process. ///
always @ (ap_sig_bdd_2192)
begin
if (ap_sig_bdd_2192) begin
ap_sig_cseq_ST_st148_fsm_147 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st148_fsm_147 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st149_fsm_148 assign process. ///
always @ (ap_sig_bdd_2336)
begin
if (ap_sig_bdd_2336) begin
ap_sig_cseq_ST_st149_fsm_148 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st149_fsm_148 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st14_fsm_13 assign process. ///
always @ (ap_sig_bdd_2292)
begin
if (ap_sig_bdd_2292) begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st14_fsm_13 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st150_fsm_149 assign process. ///
always @ (ap_sig_bdd_3477)
begin
if (ap_sig_bdd_3477) begin
ap_sig_cseq_ST_st150_fsm_149 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st150_fsm_149 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st151_fsm_150 assign process. ///
always @ (ap_sig_bdd_464)
begin
if (ap_sig_bdd_464) begin
ap_sig_cseq_ST_st151_fsm_150 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st151_fsm_150 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st152_fsm_151 assign process. ///
always @ (ap_sig_bdd_617)
begin
if (ap_sig_bdd_617) begin
ap_sig_cseq_ST_st152_fsm_151 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st152_fsm_151 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st153_fsm_152 assign process. ///
always @ (ap_sig_bdd_761)
begin
if (ap_sig_bdd_761) begin
ap_sig_cseq_ST_st153_fsm_152 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st153_fsm_152 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st154_fsm_153 assign process. ///
always @ (ap_sig_bdd_905)
begin
if (ap_sig_bdd_905) begin
ap_sig_cseq_ST_st154_fsm_153 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st154_fsm_153 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st155_fsm_154 assign process. ///
always @ (ap_sig_bdd_1049)
begin
if (ap_sig_bdd_1049) begin
ap_sig_cseq_ST_st155_fsm_154 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st155_fsm_154 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st156_fsm_155 assign process. ///
always @ (ap_sig_bdd_1193)
begin
if (ap_sig_bdd_1193) begin
ap_sig_cseq_ST_st156_fsm_155 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st156_fsm_155 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st157_fsm_156 assign process. ///
always @ (ap_sig_bdd_1337)
begin
if (ap_sig_bdd_1337) begin
ap_sig_cseq_ST_st157_fsm_156 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st157_fsm_156 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st158_fsm_157 assign process. ///
always @ (ap_sig_bdd_1481)
begin
if (ap_sig_bdd_1481) begin
ap_sig_cseq_ST_st158_fsm_157 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st158_fsm_157 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st159_fsm_158 assign process. ///
always @ (ap_sig_bdd_1625)
begin
if (ap_sig_bdd_1625) begin
ap_sig_cseq_ST_st159_fsm_158 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st159_fsm_158 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st15_fsm_14 assign process. ///
always @ (ap_sig_bdd_2893)
begin
if (ap_sig_bdd_2893) begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st15_fsm_14 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st160_fsm_159 assign process. ///
always @ (ap_sig_bdd_1769)
begin
if (ap_sig_bdd_1769) begin
ap_sig_cseq_ST_st160_fsm_159 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st160_fsm_159 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st161_fsm_160 assign process. ///
always @ (ap_sig_bdd_1913)
begin
if (ap_sig_bdd_1913) begin
ap_sig_cseq_ST_st161_fsm_160 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st161_fsm_160 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st162_fsm_161 assign process. ///
always @ (ap_sig_bdd_2057)
begin
if (ap_sig_bdd_2057) begin
ap_sig_cseq_ST_st162_fsm_161 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st162_fsm_161 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st163_fsm_162 assign process. ///
always @ (ap_sig_bdd_2201)
begin
if (ap_sig_bdd_2201) begin
ap_sig_cseq_ST_st163_fsm_162 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st163_fsm_162 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st164_fsm_163 assign process. ///
always @ (ap_sig_bdd_2345)
begin
if (ap_sig_bdd_2345) begin
ap_sig_cseq_ST_st164_fsm_163 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st164_fsm_163 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st165_fsm_164 assign process. ///
always @ (ap_sig_bdd_3487)
begin
if (ap_sig_bdd_3487) begin
ap_sig_cseq_ST_st165_fsm_164 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st165_fsm_164 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st166_fsm_165 assign process. ///
always @ (ap_sig_bdd_473)
begin
if (ap_sig_bdd_473) begin
ap_sig_cseq_ST_st166_fsm_165 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st166_fsm_165 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st167_fsm_166 assign process. ///
always @ (ap_sig_bdd_626)
begin
if (ap_sig_bdd_626) begin
ap_sig_cseq_ST_st167_fsm_166 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st167_fsm_166 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st168_fsm_167 assign process. ///
always @ (ap_sig_bdd_770)
begin
if (ap_sig_bdd_770) begin
ap_sig_cseq_ST_st168_fsm_167 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st168_fsm_167 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st169_fsm_168 assign process. ///
always @ (ap_sig_bdd_914)
begin
if (ap_sig_bdd_914) begin
ap_sig_cseq_ST_st169_fsm_168 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st169_fsm_168 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st16_fsm_15 assign process. ///
always @ (ap_sig_bdd_2902)
begin
if (ap_sig_bdd_2902) begin
ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st16_fsm_15 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st170_fsm_169 assign process. ///
always @ (ap_sig_bdd_1058)
begin
if (ap_sig_bdd_1058) begin
ap_sig_cseq_ST_st170_fsm_169 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st170_fsm_169 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st171_fsm_170 assign process. ///
always @ (ap_sig_bdd_1202)
begin
if (ap_sig_bdd_1202) begin
ap_sig_cseq_ST_st171_fsm_170 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st171_fsm_170 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st172_fsm_171 assign process. ///
always @ (ap_sig_bdd_1346)
begin
if (ap_sig_bdd_1346) begin
ap_sig_cseq_ST_st172_fsm_171 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st172_fsm_171 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st173_fsm_172 assign process. ///
always @ (ap_sig_bdd_1490)
begin
if (ap_sig_bdd_1490) begin
ap_sig_cseq_ST_st173_fsm_172 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st173_fsm_172 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st174_fsm_173 assign process. ///
always @ (ap_sig_bdd_1634)
begin
if (ap_sig_bdd_1634) begin
ap_sig_cseq_ST_st174_fsm_173 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st174_fsm_173 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st175_fsm_174 assign process. ///
always @ (ap_sig_bdd_1778)
begin
if (ap_sig_bdd_1778) begin
ap_sig_cseq_ST_st175_fsm_174 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st175_fsm_174 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st176_fsm_175 assign process. ///
always @ (ap_sig_bdd_1922)
begin
if (ap_sig_bdd_1922) begin
ap_sig_cseq_ST_st176_fsm_175 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st176_fsm_175 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st177_fsm_176 assign process. ///
always @ (ap_sig_bdd_2066)
begin
if (ap_sig_bdd_2066) begin
ap_sig_cseq_ST_st177_fsm_176 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st177_fsm_176 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st178_fsm_177 assign process. ///
always @ (ap_sig_bdd_2210)
begin
if (ap_sig_bdd_2210) begin
ap_sig_cseq_ST_st178_fsm_177 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st178_fsm_177 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st179_fsm_178 assign process. ///
always @ (ap_sig_bdd_2354)
begin
if (ap_sig_bdd_2354) begin
ap_sig_cseq_ST_st179_fsm_178 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st179_fsm_178 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st17_fsm_16 assign process. ///
always @ (ap_sig_bdd_2911)
begin
if (ap_sig_bdd_2911) begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st17_fsm_16 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st180_fsm_179 assign process. ///
always @ (ap_sig_bdd_3497)
begin
if (ap_sig_bdd_3497) begin
ap_sig_cseq_ST_st180_fsm_179 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st180_fsm_179 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st181_fsm_180 assign process. ///
always @ (ap_sig_bdd_482)
begin
if (ap_sig_bdd_482) begin
ap_sig_cseq_ST_st181_fsm_180 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st181_fsm_180 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st182_fsm_181 assign process. ///
always @ (ap_sig_bdd_635)
begin
if (ap_sig_bdd_635) begin
ap_sig_cseq_ST_st182_fsm_181 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st182_fsm_181 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st183_fsm_182 assign process. ///
always @ (ap_sig_bdd_779)
begin
if (ap_sig_bdd_779) begin
ap_sig_cseq_ST_st183_fsm_182 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st183_fsm_182 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st184_fsm_183 assign process. ///
always @ (ap_sig_bdd_923)
begin
if (ap_sig_bdd_923) begin
ap_sig_cseq_ST_st184_fsm_183 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st184_fsm_183 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st185_fsm_184 assign process. ///
always @ (ap_sig_bdd_1067)
begin
if (ap_sig_bdd_1067) begin
ap_sig_cseq_ST_st185_fsm_184 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st185_fsm_184 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st186_fsm_185 assign process. ///
always @ (ap_sig_bdd_1211)
begin
if (ap_sig_bdd_1211) begin
ap_sig_cseq_ST_st186_fsm_185 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st186_fsm_185 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st187_fsm_186 assign process. ///
always @ (ap_sig_bdd_1355)
begin
if (ap_sig_bdd_1355) begin
ap_sig_cseq_ST_st187_fsm_186 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st187_fsm_186 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st188_fsm_187 assign process. ///
always @ (ap_sig_bdd_1499)
begin
if (ap_sig_bdd_1499) begin
ap_sig_cseq_ST_st188_fsm_187 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st188_fsm_187 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st189_fsm_188 assign process. ///
always @ (ap_sig_bdd_1643)
begin
if (ap_sig_bdd_1643) begin
ap_sig_cseq_ST_st189_fsm_188 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st189_fsm_188 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st18_fsm_17 assign process. ///
always @ (ap_sig_bdd_2920)
begin
if (ap_sig_bdd_2920) begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st18_fsm_17 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st190_fsm_189 assign process. ///
always @ (ap_sig_bdd_1787)
begin
if (ap_sig_bdd_1787) begin
ap_sig_cseq_ST_st190_fsm_189 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st190_fsm_189 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st191_fsm_190 assign process. ///
always @ (ap_sig_bdd_1931)
begin
if (ap_sig_bdd_1931) begin
ap_sig_cseq_ST_st191_fsm_190 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st191_fsm_190 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st192_fsm_191 assign process. ///
always @ (ap_sig_bdd_2075)
begin
if (ap_sig_bdd_2075) begin
ap_sig_cseq_ST_st192_fsm_191 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st192_fsm_191 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st193_fsm_192 assign process. ///
always @ (ap_sig_bdd_2219)
begin
if (ap_sig_bdd_2219) begin
ap_sig_cseq_ST_st193_fsm_192 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st193_fsm_192 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st194_fsm_193 assign process. ///
always @ (ap_sig_bdd_2363)
begin
if (ap_sig_bdd_2363) begin
ap_sig_cseq_ST_st194_fsm_193 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st194_fsm_193 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st195_fsm_194 assign process. ///
always @ (ap_sig_bdd_3507)
begin
if (ap_sig_bdd_3507) begin
ap_sig_cseq_ST_st195_fsm_194 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st195_fsm_194 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st196_fsm_195 assign process. ///
always @ (ap_sig_bdd_491)
begin
if (ap_sig_bdd_491) begin
ap_sig_cseq_ST_st196_fsm_195 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st196_fsm_195 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st197_fsm_196 assign process. ///
always @ (ap_sig_bdd_644)
begin
if (ap_sig_bdd_644) begin
ap_sig_cseq_ST_st197_fsm_196 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st197_fsm_196 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st198_fsm_197 assign process. ///
always @ (ap_sig_bdd_788)
begin
if (ap_sig_bdd_788) begin
ap_sig_cseq_ST_st198_fsm_197 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st198_fsm_197 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st199_fsm_198 assign process. ///
always @ (ap_sig_bdd_932)
begin
if (ap_sig_bdd_932) begin
ap_sig_cseq_ST_st199_fsm_198 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st199_fsm_198 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st19_fsm_18 assign process. ///
always @ (ap_sig_bdd_2929)
begin
if (ap_sig_bdd_2929) begin
ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st19_fsm_18 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_399)
begin
if (ap_sig_bdd_399) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st200_fsm_199 assign process. ///
always @ (ap_sig_bdd_1076)
begin
if (ap_sig_bdd_1076) begin
ap_sig_cseq_ST_st200_fsm_199 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st200_fsm_199 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st201_fsm_200 assign process. ///
always @ (ap_sig_bdd_1220)
begin
if (ap_sig_bdd_1220) begin
ap_sig_cseq_ST_st201_fsm_200 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st201_fsm_200 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st202_fsm_201 assign process. ///
always @ (ap_sig_bdd_1364)
begin
if (ap_sig_bdd_1364) begin
ap_sig_cseq_ST_st202_fsm_201 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st202_fsm_201 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st203_fsm_202 assign process. ///
always @ (ap_sig_bdd_1508)
begin
if (ap_sig_bdd_1508) begin
ap_sig_cseq_ST_st203_fsm_202 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st203_fsm_202 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st204_fsm_203 assign process. ///
always @ (ap_sig_bdd_1652)
begin
if (ap_sig_bdd_1652) begin
ap_sig_cseq_ST_st204_fsm_203 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st204_fsm_203 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st205_fsm_204 assign process. ///
always @ (ap_sig_bdd_1796)
begin
if (ap_sig_bdd_1796) begin
ap_sig_cseq_ST_st205_fsm_204 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st205_fsm_204 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st206_fsm_205 assign process. ///
always @ (ap_sig_bdd_1940)
begin
if (ap_sig_bdd_1940) begin
ap_sig_cseq_ST_st206_fsm_205 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st206_fsm_205 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st207_fsm_206 assign process. ///
always @ (ap_sig_bdd_2084)
begin
if (ap_sig_bdd_2084) begin
ap_sig_cseq_ST_st207_fsm_206 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st207_fsm_206 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st208_fsm_207 assign process. ///
always @ (ap_sig_bdd_2228)
begin
if (ap_sig_bdd_2228) begin
ap_sig_cseq_ST_st208_fsm_207 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st208_fsm_207 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st209_fsm_208 assign process. ///
always @ (ap_sig_bdd_2372)
begin
if (ap_sig_bdd_2372) begin
ap_sig_cseq_ST_st209_fsm_208 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st209_fsm_208 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st20_fsm_19 assign process. ///
always @ (ap_sig_bdd_2938)
begin
if (ap_sig_bdd_2938) begin
ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st20_fsm_19 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st210_fsm_209 assign process. ///
always @ (ap_sig_bdd_3517)
begin
if (ap_sig_bdd_3517) begin
ap_sig_cseq_ST_st210_fsm_209 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st210_fsm_209 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st211_fsm_210 assign process. ///
always @ (ap_sig_bdd_500)
begin
if (ap_sig_bdd_500) begin
ap_sig_cseq_ST_st211_fsm_210 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st211_fsm_210 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st212_fsm_211 assign process. ///
always @ (ap_sig_bdd_653)
begin
if (ap_sig_bdd_653) begin
ap_sig_cseq_ST_st212_fsm_211 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st212_fsm_211 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st213_fsm_212 assign process. ///
always @ (ap_sig_bdd_797)
begin
if (ap_sig_bdd_797) begin
ap_sig_cseq_ST_st213_fsm_212 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st213_fsm_212 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st214_fsm_213 assign process. ///
always @ (ap_sig_bdd_941)
begin
if (ap_sig_bdd_941) begin
ap_sig_cseq_ST_st214_fsm_213 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st214_fsm_213 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st215_fsm_214 assign process. ///
always @ (ap_sig_bdd_1085)
begin
if (ap_sig_bdd_1085) begin
ap_sig_cseq_ST_st215_fsm_214 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st215_fsm_214 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st216_fsm_215 assign process. ///
always @ (ap_sig_bdd_1229)
begin
if (ap_sig_bdd_1229) begin
ap_sig_cseq_ST_st216_fsm_215 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st216_fsm_215 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st217_fsm_216 assign process. ///
always @ (ap_sig_bdd_1373)
begin
if (ap_sig_bdd_1373) begin
ap_sig_cseq_ST_st217_fsm_216 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st217_fsm_216 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st218_fsm_217 assign process. ///
always @ (ap_sig_bdd_1517)
begin
if (ap_sig_bdd_1517) begin
ap_sig_cseq_ST_st218_fsm_217 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st218_fsm_217 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st219_fsm_218 assign process. ///
always @ (ap_sig_bdd_1661)
begin
if (ap_sig_bdd_1661) begin
ap_sig_cseq_ST_st219_fsm_218 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st219_fsm_218 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st21_fsm_20 assign process. ///
always @ (ap_sig_bdd_2947)
begin
if (ap_sig_bdd_2947) begin
ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st21_fsm_20 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st220_fsm_219 assign process. ///
always @ (ap_sig_bdd_1805)
begin
if (ap_sig_bdd_1805) begin
ap_sig_cseq_ST_st220_fsm_219 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st220_fsm_219 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st221_fsm_220 assign process. ///
always @ (ap_sig_bdd_1949)
begin
if (ap_sig_bdd_1949) begin
ap_sig_cseq_ST_st221_fsm_220 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st221_fsm_220 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st222_fsm_221 assign process. ///
always @ (ap_sig_bdd_2093)
begin
if (ap_sig_bdd_2093) begin
ap_sig_cseq_ST_st222_fsm_221 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st222_fsm_221 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st223_fsm_222 assign process. ///
always @ (ap_sig_bdd_2237)
begin
if (ap_sig_bdd_2237) begin
ap_sig_cseq_ST_st223_fsm_222 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st223_fsm_222 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st224_fsm_223 assign process. ///
always @ (ap_sig_bdd_2381)
begin
if (ap_sig_bdd_2381) begin
ap_sig_cseq_ST_st224_fsm_223 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st224_fsm_223 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st225_fsm_224 assign process. ///
always @ (ap_sig_bdd_3527)
begin
if (ap_sig_bdd_3527) begin
ap_sig_cseq_ST_st225_fsm_224 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st225_fsm_224 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st226_fsm_225 assign process. ///
always @ (ap_sig_bdd_509)
begin
if (ap_sig_bdd_509) begin
ap_sig_cseq_ST_st226_fsm_225 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st226_fsm_225 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st227_fsm_226 assign process. ///
always @ (ap_sig_bdd_662)
begin
if (ap_sig_bdd_662) begin
ap_sig_cseq_ST_st227_fsm_226 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st227_fsm_226 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st228_fsm_227 assign process. ///
always @ (ap_sig_bdd_806)
begin
if (ap_sig_bdd_806) begin
ap_sig_cseq_ST_st228_fsm_227 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st228_fsm_227 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st229_fsm_228 assign process. ///
always @ (ap_sig_bdd_950)
begin
if (ap_sig_bdd_950) begin
ap_sig_cseq_ST_st229_fsm_228 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st229_fsm_228 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st22_fsm_21 assign process. ///
always @ (ap_sig_bdd_2956)
begin
if (ap_sig_bdd_2956) begin
ap_sig_cseq_ST_st22_fsm_21 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st22_fsm_21 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st230_fsm_229 assign process. ///
always @ (ap_sig_bdd_1094)
begin
if (ap_sig_bdd_1094) begin
ap_sig_cseq_ST_st230_fsm_229 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st230_fsm_229 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st231_fsm_230 assign process. ///
always @ (ap_sig_bdd_1238)
begin
if (ap_sig_bdd_1238) begin
ap_sig_cseq_ST_st231_fsm_230 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st231_fsm_230 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st232_fsm_231 assign process. ///
always @ (ap_sig_bdd_1382)
begin
if (ap_sig_bdd_1382) begin
ap_sig_cseq_ST_st232_fsm_231 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st232_fsm_231 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st233_fsm_232 assign process. ///
always @ (ap_sig_bdd_1526)
begin
if (ap_sig_bdd_1526) begin
ap_sig_cseq_ST_st233_fsm_232 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st233_fsm_232 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st234_fsm_233 assign process. ///
always @ (ap_sig_bdd_1670)
begin
if (ap_sig_bdd_1670) begin
ap_sig_cseq_ST_st234_fsm_233 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st234_fsm_233 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st235_fsm_234 assign process. ///
always @ (ap_sig_bdd_1814)
begin
if (ap_sig_bdd_1814) begin
ap_sig_cseq_ST_st235_fsm_234 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st235_fsm_234 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st236_fsm_235 assign process. ///
always @ (ap_sig_bdd_1958)
begin
if (ap_sig_bdd_1958) begin
ap_sig_cseq_ST_st236_fsm_235 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st236_fsm_235 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st237_fsm_236 assign process. ///
always @ (ap_sig_bdd_2102)
begin
if (ap_sig_bdd_2102) begin
ap_sig_cseq_ST_st237_fsm_236 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st237_fsm_236 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st238_fsm_237 assign process. ///
always @ (ap_sig_bdd_2246)
begin
if (ap_sig_bdd_2246) begin
ap_sig_cseq_ST_st238_fsm_237 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st238_fsm_237 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st239_fsm_238 assign process. ///
always @ (ap_sig_bdd_2390)
begin
if (ap_sig_bdd_2390) begin
ap_sig_cseq_ST_st239_fsm_238 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st239_fsm_238 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st23_fsm_22 assign process. ///
always @ (ap_sig_bdd_2965)
begin
if (ap_sig_bdd_2965) begin
ap_sig_cseq_ST_st23_fsm_22 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st23_fsm_22 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st240_fsm_239 assign process. ///
always @ (ap_sig_bdd_3537)
begin
if (ap_sig_bdd_3537) begin
ap_sig_cseq_ST_st240_fsm_239 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st240_fsm_239 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st241_fsm_240 assign process. ///
always @ (ap_sig_bdd_518)
begin
if (ap_sig_bdd_518) begin
ap_sig_cseq_ST_st241_fsm_240 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st241_fsm_240 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st242_fsm_241 assign process. ///
always @ (ap_sig_bdd_671)
begin
if (ap_sig_bdd_671) begin
ap_sig_cseq_ST_st242_fsm_241 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st242_fsm_241 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st243_fsm_242 assign process. ///
always @ (ap_sig_bdd_815)
begin
if (ap_sig_bdd_815) begin
ap_sig_cseq_ST_st243_fsm_242 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st243_fsm_242 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st244_fsm_243 assign process. ///
always @ (ap_sig_bdd_959)
begin
if (ap_sig_bdd_959) begin
ap_sig_cseq_ST_st244_fsm_243 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st244_fsm_243 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st245_fsm_244 assign process. ///
always @ (ap_sig_bdd_1103)
begin
if (ap_sig_bdd_1103) begin
ap_sig_cseq_ST_st245_fsm_244 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st245_fsm_244 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st246_fsm_245 assign process. ///
always @ (ap_sig_bdd_1247)
begin
if (ap_sig_bdd_1247) begin
ap_sig_cseq_ST_st246_fsm_245 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st246_fsm_245 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st247_fsm_246 assign process. ///
always @ (ap_sig_bdd_1391)
begin
if (ap_sig_bdd_1391) begin
ap_sig_cseq_ST_st247_fsm_246 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st247_fsm_246 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st248_fsm_247 assign process. ///
always @ (ap_sig_bdd_1535)
begin
if (ap_sig_bdd_1535) begin
ap_sig_cseq_ST_st248_fsm_247 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st248_fsm_247 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st249_fsm_248 assign process. ///
always @ (ap_sig_bdd_1679)
begin
if (ap_sig_bdd_1679) begin
ap_sig_cseq_ST_st249_fsm_248 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st249_fsm_248 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st24_fsm_23 assign process. ///
always @ (ap_sig_bdd_2974)
begin
if (ap_sig_bdd_2974) begin
ap_sig_cseq_ST_st24_fsm_23 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st24_fsm_23 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st250_fsm_249 assign process. ///
always @ (ap_sig_bdd_1823)
begin
if (ap_sig_bdd_1823) begin
ap_sig_cseq_ST_st250_fsm_249 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st250_fsm_249 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st251_fsm_250 assign process. ///
always @ (ap_sig_bdd_1967)
begin
if (ap_sig_bdd_1967) begin
ap_sig_cseq_ST_st251_fsm_250 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st251_fsm_250 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st252_fsm_251 assign process. ///
always @ (ap_sig_bdd_2111)
begin
if (ap_sig_bdd_2111) begin
ap_sig_cseq_ST_st252_fsm_251 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st252_fsm_251 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st253_fsm_252 assign process. ///
always @ (ap_sig_bdd_2255)
begin
if (ap_sig_bdd_2255) begin
ap_sig_cseq_ST_st253_fsm_252 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st253_fsm_252 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st254_fsm_253 assign process. ///
always @ (ap_sig_bdd_2399)
begin
if (ap_sig_bdd_2399) begin
ap_sig_cseq_ST_st254_fsm_253 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st254_fsm_253 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st255_fsm_254 assign process. ///
always @ (ap_sig_bdd_5023)
begin
if (ap_sig_bdd_5023) begin
ap_sig_cseq_ST_st255_fsm_254 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st255_fsm_254 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st256_fsm_255 assign process. ///
always @ (ap_sig_bdd_527)
begin
if (ap_sig_bdd_527) begin
ap_sig_cseq_ST_st256_fsm_255 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st256_fsm_255 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st257_fsm_256 assign process. ///
always @ (ap_sig_bdd_680)
begin
if (ap_sig_bdd_680) begin
ap_sig_cseq_ST_st257_fsm_256 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st257_fsm_256 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st258_fsm_257 assign process. ///
always @ (ap_sig_bdd_824)
begin
if (ap_sig_bdd_824) begin
ap_sig_cseq_ST_st258_fsm_257 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st258_fsm_257 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st259_fsm_258 assign process. ///
always @ (ap_sig_bdd_968)
begin
if (ap_sig_bdd_968) begin
ap_sig_cseq_ST_st259_fsm_258 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st259_fsm_258 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st25_fsm_24 assign process. ///
always @ (ap_sig_bdd_2983)
begin
if (ap_sig_bdd_2983) begin
ap_sig_cseq_ST_st25_fsm_24 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st25_fsm_24 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st260_fsm_259 assign process. ///
always @ (ap_sig_bdd_1112)
begin
if (ap_sig_bdd_1112) begin
ap_sig_cseq_ST_st260_fsm_259 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st260_fsm_259 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st261_fsm_260 assign process. ///
always @ (ap_sig_bdd_1256)
begin
if (ap_sig_bdd_1256) begin
ap_sig_cseq_ST_st261_fsm_260 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st261_fsm_260 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st262_fsm_261 assign process. ///
always @ (ap_sig_bdd_1400)
begin
if (ap_sig_bdd_1400) begin
ap_sig_cseq_ST_st262_fsm_261 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st262_fsm_261 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st263_fsm_262 assign process. ///
always @ (ap_sig_bdd_1544)
begin
if (ap_sig_bdd_1544) begin
ap_sig_cseq_ST_st263_fsm_262 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st263_fsm_262 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st264_fsm_263 assign process. ///
always @ (ap_sig_bdd_1688)
begin
if (ap_sig_bdd_1688) begin
ap_sig_cseq_ST_st264_fsm_263 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st264_fsm_263 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st265_fsm_264 assign process. ///
always @ (ap_sig_bdd_1832)
begin
if (ap_sig_bdd_1832) begin
ap_sig_cseq_ST_st265_fsm_264 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st265_fsm_264 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st266_fsm_265 assign process. ///
always @ (ap_sig_bdd_1976)
begin
if (ap_sig_bdd_1976) begin
ap_sig_cseq_ST_st266_fsm_265 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st266_fsm_265 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st267_fsm_266 assign process. ///
always @ (ap_sig_bdd_2120)
begin
if (ap_sig_bdd_2120) begin
ap_sig_cseq_ST_st267_fsm_266 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st267_fsm_266 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st268_fsm_267 assign process. ///
always @ (ap_sig_bdd_2264)
begin
if (ap_sig_bdd_2264) begin
ap_sig_cseq_ST_st268_fsm_267 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st268_fsm_267 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st269_fsm_268 assign process. ///
always @ (ap_sig_bdd_2408)
begin
if (ap_sig_bdd_2408) begin
ap_sig_cseq_ST_st269_fsm_268 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st269_fsm_268 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st26_fsm_25 assign process. ///
always @ (ap_sig_bdd_2992)
begin
if (ap_sig_bdd_2992) begin
ap_sig_cseq_ST_st26_fsm_25 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st26_fsm_25 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st270_fsm_269 assign process. ///
always @ (ap_sig_bdd_5046)
begin
if (ap_sig_bdd_5046) begin
ap_sig_cseq_ST_st270_fsm_269 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st270_fsm_269 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st271_fsm_270 assign process. ///
always @ (ap_sig_bdd_536)
begin
if (ap_sig_bdd_536) begin
ap_sig_cseq_ST_st271_fsm_270 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st271_fsm_270 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st272_fsm_271 assign process. ///
always @ (ap_sig_bdd_689)
begin
if (ap_sig_bdd_689) begin
ap_sig_cseq_ST_st272_fsm_271 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st272_fsm_271 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st273_fsm_272 assign process. ///
always @ (ap_sig_bdd_833)
begin
if (ap_sig_bdd_833) begin
ap_sig_cseq_ST_st273_fsm_272 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st273_fsm_272 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st274_fsm_273 assign process. ///
always @ (ap_sig_bdd_977)
begin
if (ap_sig_bdd_977) begin
ap_sig_cseq_ST_st274_fsm_273 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st274_fsm_273 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st275_fsm_274 assign process. ///
always @ (ap_sig_bdd_1121)
begin
if (ap_sig_bdd_1121) begin
ap_sig_cseq_ST_st275_fsm_274 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st275_fsm_274 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st276_fsm_275 assign process. ///
always @ (ap_sig_bdd_1265)
begin
if (ap_sig_bdd_1265) begin
ap_sig_cseq_ST_st276_fsm_275 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st276_fsm_275 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st277_fsm_276 assign process. ///
always @ (ap_sig_bdd_1409)
begin
if (ap_sig_bdd_1409) begin
ap_sig_cseq_ST_st277_fsm_276 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st277_fsm_276 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st278_fsm_277 assign process. ///
always @ (ap_sig_bdd_1553)
begin
if (ap_sig_bdd_1553) begin
ap_sig_cseq_ST_st278_fsm_277 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st278_fsm_277 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st279_fsm_278 assign process. ///
always @ (ap_sig_bdd_1697)
begin
if (ap_sig_bdd_1697) begin
ap_sig_cseq_ST_st279_fsm_278 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st279_fsm_278 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st27_fsm_26 assign process. ///
always @ (ap_sig_bdd_3001)
begin
if (ap_sig_bdd_3001) begin
ap_sig_cseq_ST_st27_fsm_26 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st27_fsm_26 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st280_fsm_279 assign process. ///
always @ (ap_sig_bdd_1841)
begin
if (ap_sig_bdd_1841) begin
ap_sig_cseq_ST_st280_fsm_279 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st280_fsm_279 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st281_fsm_280 assign process. ///
always @ (ap_sig_bdd_1985)
begin
if (ap_sig_bdd_1985) begin
ap_sig_cseq_ST_st281_fsm_280 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st281_fsm_280 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st282_fsm_281 assign process. ///
always @ (ap_sig_bdd_2129)
begin
if (ap_sig_bdd_2129) begin
ap_sig_cseq_ST_st282_fsm_281 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st282_fsm_281 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st283_fsm_282 assign process. ///
always @ (ap_sig_bdd_2273)
begin
if (ap_sig_bdd_2273) begin
ap_sig_cseq_ST_st283_fsm_282 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st283_fsm_282 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st284_fsm_283 assign process. ///
always @ (ap_sig_bdd_2417)
begin
if (ap_sig_bdd_2417) begin
ap_sig_cseq_ST_st284_fsm_283 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st284_fsm_283 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st285_fsm_284 assign process. ///
always @ (ap_sig_bdd_5069)
begin
if (ap_sig_bdd_5069) begin
ap_sig_cseq_ST_st285_fsm_284 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st285_fsm_284 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st286_fsm_285 assign process. ///
always @ (ap_sig_bdd_545)
begin
if (ap_sig_bdd_545) begin
ap_sig_cseq_ST_st286_fsm_285 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st286_fsm_285 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st287_fsm_286 assign process. ///
always @ (ap_sig_bdd_698)
begin
if (ap_sig_bdd_698) begin
ap_sig_cseq_ST_st287_fsm_286 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st287_fsm_286 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st288_fsm_287 assign process. ///
always @ (ap_sig_bdd_842)
begin
if (ap_sig_bdd_842) begin
ap_sig_cseq_ST_st288_fsm_287 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st288_fsm_287 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st289_fsm_288 assign process. ///
always @ (ap_sig_bdd_986)
begin
if (ap_sig_bdd_986) begin
ap_sig_cseq_ST_st289_fsm_288 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st289_fsm_288 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st28_fsm_27 assign process. ///
always @ (ap_sig_bdd_3010)
begin
if (ap_sig_bdd_3010) begin
ap_sig_cseq_ST_st28_fsm_27 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st28_fsm_27 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st290_fsm_289 assign process. ///
always @ (ap_sig_bdd_1130)
begin
if (ap_sig_bdd_1130) begin
ap_sig_cseq_ST_st290_fsm_289 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st290_fsm_289 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st291_fsm_290 assign process. ///
always @ (ap_sig_bdd_1274)
begin
if (ap_sig_bdd_1274) begin
ap_sig_cseq_ST_st291_fsm_290 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st291_fsm_290 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st292_fsm_291 assign process. ///
always @ (ap_sig_bdd_1418)
begin
if (ap_sig_bdd_1418) begin
ap_sig_cseq_ST_st292_fsm_291 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st292_fsm_291 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st293_fsm_292 assign process. ///
always @ (ap_sig_bdd_1562)
begin
if (ap_sig_bdd_1562) begin
ap_sig_cseq_ST_st293_fsm_292 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st293_fsm_292 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st294_fsm_293 assign process. ///
always @ (ap_sig_bdd_1706)
begin
if (ap_sig_bdd_1706) begin
ap_sig_cseq_ST_st294_fsm_293 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st294_fsm_293 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st295_fsm_294 assign process. ///
always @ (ap_sig_bdd_1850)
begin
if (ap_sig_bdd_1850) begin
ap_sig_cseq_ST_st295_fsm_294 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st295_fsm_294 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st296_fsm_295 assign process. ///
always @ (ap_sig_bdd_1994)
begin
if (ap_sig_bdd_1994) begin
ap_sig_cseq_ST_st296_fsm_295 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st296_fsm_295 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st297_fsm_296 assign process. ///
always @ (ap_sig_bdd_2138)
begin
if (ap_sig_bdd_2138) begin
ap_sig_cseq_ST_st297_fsm_296 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st297_fsm_296 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st298_fsm_297 assign process. ///
always @ (ap_sig_bdd_2282)
begin
if (ap_sig_bdd_2282) begin
ap_sig_cseq_ST_st298_fsm_297 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st298_fsm_297 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st299_fsm_298 assign process. ///
always @ (ap_sig_bdd_2426)
begin
if (ap_sig_bdd_2426) begin
ap_sig_cseq_ST_st299_fsm_298 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st299_fsm_298 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st29_fsm_28 assign process. ///
always @ (ap_sig_bdd_3019)
begin
if (ap_sig_bdd_3019) begin
ap_sig_cseq_ST_st29_fsm_28 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st29_fsm_28 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_555)
begin
if (ap_sig_bdd_555) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st300_fsm_299 assign process. ///
always @ (ap_sig_bdd_3547)
begin
if (ap_sig_bdd_3547) begin
ap_sig_cseq_ST_st300_fsm_299 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st300_fsm_299 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st30_fsm_29 assign process. ///
always @ (ap_sig_bdd_3028)
begin
if (ap_sig_bdd_3028) begin
ap_sig_cseq_ST_st30_fsm_29 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st30_fsm_29 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st31_fsm_30 assign process. ///
always @ (ap_sig_bdd_3037)
begin
if (ap_sig_bdd_3037) begin
ap_sig_cseq_ST_st31_fsm_30 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st31_fsm_30 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st32_fsm_31 assign process. ///
always @ (ap_sig_bdd_3046)
begin
if (ap_sig_bdd_3046) begin
ap_sig_cseq_ST_st32_fsm_31 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st32_fsm_31 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st33_fsm_32 assign process. ///
always @ (ap_sig_bdd_3055)
begin
if (ap_sig_bdd_3055) begin
ap_sig_cseq_ST_st33_fsm_32 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st33_fsm_32 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st34_fsm_33 assign process. ///
always @ (ap_sig_bdd_3064)
begin
if (ap_sig_bdd_3064) begin
ap_sig_cseq_ST_st34_fsm_33 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st34_fsm_33 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st35_fsm_34 assign process. ///
always @ (ap_sig_bdd_3073)
begin
if (ap_sig_bdd_3073) begin
ap_sig_cseq_ST_st35_fsm_34 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st35_fsm_34 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st36_fsm_35 assign process. ///
always @ (ap_sig_bdd_3082)
begin
if (ap_sig_bdd_3082) begin
ap_sig_cseq_ST_st36_fsm_35 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st36_fsm_35 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st37_fsm_36 assign process. ///
always @ (ap_sig_bdd_3091)
begin
if (ap_sig_bdd_3091) begin
ap_sig_cseq_ST_st37_fsm_36 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st37_fsm_36 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st385_fsm_301 assign process. ///
always @ (ap_sig_bdd_5902)
begin
if (ap_sig_bdd_5902) begin
ap_sig_cseq_ST_st385_fsm_301 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st385_fsm_301 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st386_fsm_302 assign process. ///
always @ (ap_sig_bdd_2708)
begin
if (ap_sig_bdd_2708) begin
ap_sig_cseq_ST_st386_fsm_302 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st386_fsm_302 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st387_fsm_303 assign process. ///
always @ (ap_sig_bdd_5096)
begin
if (ap_sig_bdd_5096) begin
ap_sig_cseq_ST_st387_fsm_303 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st387_fsm_303 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st388_fsm_304 assign process. ///
always @ (ap_sig_bdd_5104)
begin
if (ap_sig_bdd_5104) begin
ap_sig_cseq_ST_st388_fsm_304 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st388_fsm_304 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st389_fsm_305 assign process. ///
always @ (ap_sig_bdd_2719)
begin
if (ap_sig_bdd_2719) begin
ap_sig_cseq_ST_st389_fsm_305 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st389_fsm_305 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st38_fsm_37 assign process. ///
always @ (ap_sig_bdd_3100)
begin
if (ap_sig_bdd_3100) begin
ap_sig_cseq_ST_st38_fsm_37 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st38_fsm_37 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st390_fsm_306 assign process. ///
always @ (ap_sig_bdd_5113)
begin
if (ap_sig_bdd_5113) begin
ap_sig_cseq_ST_st390_fsm_306 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st390_fsm_306 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st391_fsm_307 assign process. ///
always @ (ap_sig_bdd_5121)
begin
if (ap_sig_bdd_5121) begin
ap_sig_cseq_ST_st391_fsm_307 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st391_fsm_307 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st392_fsm_308 assign process. ///
always @ (ap_sig_bdd_2728)
begin
if (ap_sig_bdd_2728) begin
ap_sig_cseq_ST_st392_fsm_308 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st392_fsm_308 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st393_fsm_309 assign process. ///
always @ (ap_sig_bdd_5130)
begin
if (ap_sig_bdd_5130) begin
ap_sig_cseq_ST_st393_fsm_309 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st393_fsm_309 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st394_fsm_310 assign process. ///
always @ (ap_sig_bdd_5138)
begin
if (ap_sig_bdd_5138) begin
ap_sig_cseq_ST_st394_fsm_310 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st394_fsm_310 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st395_fsm_311 assign process. ///
always @ (ap_sig_bdd_2737)
begin
if (ap_sig_bdd_2737) begin
ap_sig_cseq_ST_st395_fsm_311 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st395_fsm_311 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st396_fsm_312 assign process. ///
always @ (ap_sig_bdd_5147)
begin
if (ap_sig_bdd_5147) begin
ap_sig_cseq_ST_st396_fsm_312 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st396_fsm_312 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st397_fsm_313 assign process. ///
always @ (ap_sig_bdd_5155)
begin
if (ap_sig_bdd_5155) begin
ap_sig_cseq_ST_st397_fsm_313 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st397_fsm_313 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st398_fsm_314 assign process. ///
always @ (ap_sig_bdd_2746)
begin
if (ap_sig_bdd_2746) begin
ap_sig_cseq_ST_st398_fsm_314 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st398_fsm_314 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st399_fsm_315 assign process. ///
always @ (ap_sig_bdd_5164)
begin
if (ap_sig_bdd_5164) begin
ap_sig_cseq_ST_st399_fsm_315 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st399_fsm_315 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st39_fsm_38 assign process. ///
always @ (ap_sig_bdd_3109)
begin
if (ap_sig_bdd_3109) begin
ap_sig_cseq_ST_st39_fsm_38 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st39_fsm_38 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_708)
begin
if (ap_sig_bdd_708) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st400_fsm_316 assign process. ///
always @ (ap_sig_bdd_5172)
begin
if (ap_sig_bdd_5172) begin
ap_sig_cseq_ST_st400_fsm_316 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st400_fsm_316 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st401_fsm_317 assign process. ///
always @ (ap_sig_bdd_2755)
begin
if (ap_sig_bdd_2755) begin
ap_sig_cseq_ST_st401_fsm_317 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st401_fsm_317 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st402_fsm_318 assign process. ///
always @ (ap_sig_bdd_5181)
begin
if (ap_sig_bdd_5181) begin
ap_sig_cseq_ST_st402_fsm_318 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st402_fsm_318 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st403_fsm_319 assign process. ///
always @ (ap_sig_bdd_5189)
begin
if (ap_sig_bdd_5189) begin
ap_sig_cseq_ST_st403_fsm_319 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st403_fsm_319 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st404_fsm_320 assign process. ///
always @ (ap_sig_bdd_2764)
begin
if (ap_sig_bdd_2764) begin
ap_sig_cseq_ST_st404_fsm_320 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st404_fsm_320 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st405_fsm_321 assign process. ///
always @ (ap_sig_bdd_5198)
begin
if (ap_sig_bdd_5198) begin
ap_sig_cseq_ST_st405_fsm_321 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st405_fsm_321 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st406_fsm_322 assign process. ///
always @ (ap_sig_bdd_5206)
begin
if (ap_sig_bdd_5206) begin
ap_sig_cseq_ST_st406_fsm_322 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st406_fsm_322 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st407_fsm_323 assign process. ///
always @ (ap_sig_bdd_2773)
begin
if (ap_sig_bdd_2773) begin
ap_sig_cseq_ST_st407_fsm_323 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st407_fsm_323 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st408_fsm_324 assign process. ///
always @ (ap_sig_bdd_5215)
begin
if (ap_sig_bdd_5215) begin
ap_sig_cseq_ST_st408_fsm_324 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st408_fsm_324 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st409_fsm_325 assign process. ///
always @ (ap_sig_bdd_5223)
begin
if (ap_sig_bdd_5223) begin
ap_sig_cseq_ST_st409_fsm_325 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st409_fsm_325 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st40_fsm_39 assign process. ///
always @ (ap_sig_bdd_3118)
begin
if (ap_sig_bdd_3118) begin
ap_sig_cseq_ST_st40_fsm_39 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st40_fsm_39 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st410_fsm_326 assign process. ///
always @ (ap_sig_bdd_2782)
begin
if (ap_sig_bdd_2782) begin
ap_sig_cseq_ST_st410_fsm_326 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st410_fsm_326 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st411_fsm_327 assign process. ///
always @ (ap_sig_bdd_5232)
begin
if (ap_sig_bdd_5232) begin
ap_sig_cseq_ST_st411_fsm_327 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st411_fsm_327 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st412_fsm_328 assign process. ///
always @ (ap_sig_bdd_5240)
begin
if (ap_sig_bdd_5240) begin
ap_sig_cseq_ST_st412_fsm_328 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st412_fsm_328 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st413_fsm_329 assign process. ///
always @ (ap_sig_bdd_2791)
begin
if (ap_sig_bdd_2791) begin
ap_sig_cseq_ST_st413_fsm_329 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st413_fsm_329 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st414_fsm_330 assign process. ///
always @ (ap_sig_bdd_5249)
begin
if (ap_sig_bdd_5249) begin
ap_sig_cseq_ST_st414_fsm_330 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st414_fsm_330 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st415_fsm_331 assign process. ///
always @ (ap_sig_bdd_5257)
begin
if (ap_sig_bdd_5257) begin
ap_sig_cseq_ST_st415_fsm_331 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st415_fsm_331 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st416_fsm_332 assign process. ///
always @ (ap_sig_bdd_2800)
begin
if (ap_sig_bdd_2800) begin
ap_sig_cseq_ST_st416_fsm_332 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st416_fsm_332 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st417_fsm_333 assign process. ///
always @ (ap_sig_bdd_5266)
begin
if (ap_sig_bdd_5266) begin
ap_sig_cseq_ST_st417_fsm_333 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st417_fsm_333 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st418_fsm_334 assign process. ///
always @ (ap_sig_bdd_5274)
begin
if (ap_sig_bdd_5274) begin
ap_sig_cseq_ST_st418_fsm_334 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st418_fsm_334 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st419_fsm_335 assign process. ///
always @ (ap_sig_bdd_2809)
begin
if (ap_sig_bdd_2809) begin
ap_sig_cseq_ST_st419_fsm_335 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st419_fsm_335 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st41_fsm_40 assign process. ///
always @ (ap_sig_bdd_3127)
begin
if (ap_sig_bdd_3127) begin
ap_sig_cseq_ST_st41_fsm_40 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st41_fsm_40 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st420_fsm_336 assign process. ///
always @ (ap_sig_bdd_5283)
begin
if (ap_sig_bdd_5283) begin
ap_sig_cseq_ST_st420_fsm_336 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st420_fsm_336 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st421_fsm_337 assign process. ///
always @ (ap_sig_bdd_5291)
begin
if (ap_sig_bdd_5291) begin
ap_sig_cseq_ST_st421_fsm_337 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st421_fsm_337 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st422_fsm_338 assign process. ///
always @ (ap_sig_bdd_2818)
begin
if (ap_sig_bdd_2818) begin
ap_sig_cseq_ST_st422_fsm_338 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st422_fsm_338 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st423_fsm_339 assign process. ///
always @ (ap_sig_bdd_5300)
begin
if (ap_sig_bdd_5300) begin
ap_sig_cseq_ST_st423_fsm_339 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st423_fsm_339 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st424_fsm_340 assign process. ///
always @ (ap_sig_bdd_5308)
begin
if (ap_sig_bdd_5308) begin
ap_sig_cseq_ST_st424_fsm_340 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st424_fsm_340 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st425_fsm_341 assign process. ///
always @ (ap_sig_bdd_2827)
begin
if (ap_sig_bdd_2827) begin
ap_sig_cseq_ST_st425_fsm_341 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st425_fsm_341 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st426_fsm_342 assign process. ///
always @ (ap_sig_bdd_5317)
begin
if (ap_sig_bdd_5317) begin
ap_sig_cseq_ST_st426_fsm_342 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st426_fsm_342 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st427_fsm_343 assign process. ///
always @ (ap_sig_bdd_5325)
begin
if (ap_sig_bdd_5325) begin
ap_sig_cseq_ST_st427_fsm_343 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st427_fsm_343 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st428_fsm_344 assign process. ///
always @ (ap_sig_bdd_2836)
begin
if (ap_sig_bdd_2836) begin
ap_sig_cseq_ST_st428_fsm_344 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st428_fsm_344 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st429_fsm_345 assign process. ///
always @ (ap_sig_bdd_5334)
begin
if (ap_sig_bdd_5334) begin
ap_sig_cseq_ST_st429_fsm_345 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st429_fsm_345 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st42_fsm_41 assign process. ///
always @ (ap_sig_bdd_3136)
begin
if (ap_sig_bdd_3136) begin
ap_sig_cseq_ST_st42_fsm_41 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st42_fsm_41 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st430_fsm_346 assign process. ///
always @ (ap_sig_bdd_5342)
begin
if (ap_sig_bdd_5342) begin
ap_sig_cseq_ST_st430_fsm_346 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st430_fsm_346 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st431_fsm_347 assign process. ///
always @ (ap_sig_bdd_2845)
begin
if (ap_sig_bdd_2845) begin
ap_sig_cseq_ST_st431_fsm_347 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st431_fsm_347 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st432_fsm_348 assign process. ///
always @ (ap_sig_bdd_5351)
begin
if (ap_sig_bdd_5351) begin
ap_sig_cseq_ST_st432_fsm_348 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st432_fsm_348 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st433_fsm_349 assign process. ///
always @ (ap_sig_bdd_5359)
begin
if (ap_sig_bdd_5359) begin
ap_sig_cseq_ST_st433_fsm_349 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st433_fsm_349 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st434_fsm_350 assign process. ///
always @ (ap_sig_bdd_2854)
begin
if (ap_sig_bdd_2854) begin
ap_sig_cseq_ST_st434_fsm_350 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st434_fsm_350 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st435_fsm_351 assign process. ///
always @ (ap_sig_bdd_5368)
begin
if (ap_sig_bdd_5368) begin
ap_sig_cseq_ST_st435_fsm_351 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st435_fsm_351 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st436_fsm_352 assign process. ///
always @ (ap_sig_bdd_5376)
begin
if (ap_sig_bdd_5376) begin
ap_sig_cseq_ST_st436_fsm_352 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st436_fsm_352 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st437_fsm_353 assign process. ///
always @ (ap_sig_bdd_2863)
begin
if (ap_sig_bdd_2863) begin
ap_sig_cseq_ST_st437_fsm_353 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st437_fsm_353 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st438_fsm_354 assign process. ///
always @ (ap_sig_bdd_5385)
begin
if (ap_sig_bdd_5385) begin
ap_sig_cseq_ST_st438_fsm_354 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st438_fsm_354 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st439_fsm_355 assign process. ///
always @ (ap_sig_bdd_5393)
begin
if (ap_sig_bdd_5393) begin
ap_sig_cseq_ST_st439_fsm_355 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st439_fsm_355 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st43_fsm_42 assign process. ///
always @ (ap_sig_bdd_3145)
begin
if (ap_sig_bdd_3145) begin
ap_sig_cseq_ST_st43_fsm_42 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st43_fsm_42 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st440_fsm_356 assign process. ///
always @ (ap_sig_bdd_2872)
begin
if (ap_sig_bdd_2872) begin
ap_sig_cseq_ST_st440_fsm_356 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st440_fsm_356 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st441_fsm_357 assign process. ///
always @ (ap_sig_bdd_5402)
begin
if (ap_sig_bdd_5402) begin
ap_sig_cseq_ST_st441_fsm_357 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st441_fsm_357 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st442_fsm_358 assign process. ///
always @ (ap_sig_bdd_5410)
begin
if (ap_sig_bdd_5410) begin
ap_sig_cseq_ST_st442_fsm_358 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st442_fsm_358 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st443_fsm_359 assign process. ///
always @ (ap_sig_bdd_2881)
begin
if (ap_sig_bdd_2881) begin
ap_sig_cseq_ST_st443_fsm_359 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st443_fsm_359 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st444_fsm_360 assign process. ///
always @ (ap_sig_bdd_5419)
begin
if (ap_sig_bdd_5419) begin
ap_sig_cseq_ST_st444_fsm_360 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st444_fsm_360 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st445_fsm_361 assign process. ///
always @ (ap_sig_bdd_5427)
begin
if (ap_sig_bdd_5427) begin
ap_sig_cseq_ST_st445_fsm_361 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st445_fsm_361 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st44_fsm_43 assign process. ///
always @ (ap_sig_bdd_3154)
begin
if (ap_sig_bdd_3154) begin
ap_sig_cseq_ST_st44_fsm_43 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st44_fsm_43 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st45_fsm_44 assign process. ///
always @ (ap_sig_bdd_3163)
begin
if (ap_sig_bdd_3163) begin
ap_sig_cseq_ST_st45_fsm_44 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st45_fsm_44 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st46_fsm_45 assign process. ///
always @ (ap_sig_bdd_3172)
begin
if (ap_sig_bdd_3172) begin
ap_sig_cseq_ST_st46_fsm_45 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st46_fsm_45 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st47_fsm_46 assign process. ///
always @ (ap_sig_bdd_3181)
begin
if (ap_sig_bdd_3181) begin
ap_sig_cseq_ST_st47_fsm_46 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st47_fsm_46 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st48_fsm_47 assign process. ///
always @ (ap_sig_bdd_3190)
begin
if (ap_sig_bdd_3190) begin
ap_sig_cseq_ST_st48_fsm_47 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st48_fsm_47 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st49_fsm_48 assign process. ///
always @ (ap_sig_bdd_3199)
begin
if (ap_sig_bdd_3199) begin
ap_sig_cseq_ST_st49_fsm_48 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st49_fsm_48 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st4_fsm_3 assign process. ///
always @ (ap_sig_bdd_852)
begin
if (ap_sig_bdd_852) begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st4_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st50_fsm_49 assign process. ///
always @ (ap_sig_bdd_3208)
begin
if (ap_sig_bdd_3208) begin
ap_sig_cseq_ST_st50_fsm_49 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st50_fsm_49 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st51_fsm_50 assign process. ///
always @ (ap_sig_bdd_3217)
begin
if (ap_sig_bdd_3217) begin
ap_sig_cseq_ST_st51_fsm_50 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st51_fsm_50 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st52_fsm_51 assign process. ///
always @ (ap_sig_bdd_3226)
begin
if (ap_sig_bdd_3226) begin
ap_sig_cseq_ST_st52_fsm_51 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st52_fsm_51 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st53_fsm_52 assign process. ///
always @ (ap_sig_bdd_3235)
begin
if (ap_sig_bdd_3235) begin
ap_sig_cseq_ST_st53_fsm_52 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st53_fsm_52 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st54_fsm_53 assign process. ///
always @ (ap_sig_bdd_3244)
begin
if (ap_sig_bdd_3244) begin
ap_sig_cseq_ST_st54_fsm_53 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st54_fsm_53 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st55_fsm_54 assign process. ///
always @ (ap_sig_bdd_3253)
begin
if (ap_sig_bdd_3253) begin
ap_sig_cseq_ST_st55_fsm_54 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st55_fsm_54 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st56_fsm_55 assign process. ///
always @ (ap_sig_bdd_3262)
begin
if (ap_sig_bdd_3262) begin
ap_sig_cseq_ST_st56_fsm_55 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st56_fsm_55 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st57_fsm_56 assign process. ///
always @ (ap_sig_bdd_3271)
begin
if (ap_sig_bdd_3271) begin
ap_sig_cseq_ST_st57_fsm_56 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st57_fsm_56 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st58_fsm_57 assign process. ///
always @ (ap_sig_bdd_3280)
begin
if (ap_sig_bdd_3280) begin
ap_sig_cseq_ST_st58_fsm_57 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st58_fsm_57 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st59_fsm_58 assign process. ///
always @ (ap_sig_bdd_3289)
begin
if (ap_sig_bdd_3289) begin
ap_sig_cseq_ST_st59_fsm_58 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st59_fsm_58 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st5_fsm_4 assign process. ///
always @ (ap_sig_bdd_996)
begin
if (ap_sig_bdd_996) begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st5_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st60_fsm_59 assign process. ///
always @ (ap_sig_bdd_3298)
begin
if (ap_sig_bdd_3298) begin
ap_sig_cseq_ST_st60_fsm_59 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st60_fsm_59 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st61_fsm_60 assign process. ///
always @ (ap_sig_bdd_3307)
begin
if (ap_sig_bdd_3307) begin
ap_sig_cseq_ST_st61_fsm_60 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st61_fsm_60 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st62_fsm_61 assign process. ///
always @ (ap_sig_bdd_3316)
begin
if (ap_sig_bdd_3316) begin
ap_sig_cseq_ST_st62_fsm_61 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st62_fsm_61 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st63_fsm_62 assign process. ///
always @ (ap_sig_bdd_3325)
begin
if (ap_sig_bdd_3325) begin
ap_sig_cseq_ST_st63_fsm_62 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st63_fsm_62 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st64_fsm_63 assign process. ///
always @ (ap_sig_bdd_3334)
begin
if (ap_sig_bdd_3334) begin
ap_sig_cseq_ST_st64_fsm_63 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st64_fsm_63 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st65_fsm_64 assign process. ///
always @ (ap_sig_bdd_3343)
begin
if (ap_sig_bdd_3343) begin
ap_sig_cseq_ST_st65_fsm_64 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st65_fsm_64 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st66_fsm_65 assign process. ///
always @ (ap_sig_bdd_3352)
begin
if (ap_sig_bdd_3352) begin
ap_sig_cseq_ST_st66_fsm_65 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st66_fsm_65 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st67_fsm_66 assign process. ///
always @ (ap_sig_bdd_3361)
begin
if (ap_sig_bdd_3361) begin
ap_sig_cseq_ST_st67_fsm_66 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st67_fsm_66 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st68_fsm_67 assign process. ///
always @ (ap_sig_bdd_3370)
begin
if (ap_sig_bdd_3370) begin
ap_sig_cseq_ST_st68_fsm_67 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st68_fsm_67 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st69_fsm_68 assign process. ///
always @ (ap_sig_bdd_3379)
begin
if (ap_sig_bdd_3379) begin
ap_sig_cseq_ST_st69_fsm_68 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st69_fsm_68 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st6_fsm_5 assign process. ///
always @ (ap_sig_bdd_1140)
begin
if (ap_sig_bdd_1140) begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st6_fsm_5 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st70_fsm_69 assign process. ///
always @ (ap_sig_bdd_3388)
begin
if (ap_sig_bdd_3388) begin
ap_sig_cseq_ST_st70_fsm_69 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st70_fsm_69 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st71_fsm_70 assign process. ///
always @ (ap_sig_bdd_3397)
begin
if (ap_sig_bdd_3397) begin
ap_sig_cseq_ST_st71_fsm_70 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st71_fsm_70 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st72_fsm_71 assign process. ///
always @ (ap_sig_bdd_2437)
begin
if (ap_sig_bdd_2437) begin
ap_sig_cseq_ST_st72_fsm_71 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st72_fsm_71 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st73_fsm_72 assign process. ///
always @ (ap_sig_bdd_410)
begin
if (ap_sig_bdd_410) begin
ap_sig_cseq_ST_st73_fsm_72 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st73_fsm_72 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st74_fsm_73 assign process. ///
always @ (ap_sig_bdd_563)
begin
if (ap_sig_bdd_563) begin
ap_sig_cseq_ST_st74_fsm_73 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st74_fsm_73 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st75_fsm_74 assign process. ///
always @ (ap_sig_bdd_3417)
begin
if (ap_sig_bdd_3417) begin
ap_sig_cseq_ST_st75_fsm_74 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st75_fsm_74 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st76_fsm_75 assign process. ///
always @ (ap_sig_bdd_419)
begin
if (ap_sig_bdd_419) begin
ap_sig_cseq_ST_st76_fsm_75 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st76_fsm_75 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st77_fsm_76 assign process. ///
always @ (ap_sig_bdd_572)
begin
if (ap_sig_bdd_572) begin
ap_sig_cseq_ST_st77_fsm_76 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st77_fsm_76 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st78_fsm_77 assign process. ///
always @ (ap_sig_bdd_716)
begin
if (ap_sig_bdd_716) begin
ap_sig_cseq_ST_st78_fsm_77 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st78_fsm_77 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st79_fsm_78 assign process. ///
always @ (ap_sig_bdd_860)
begin
if (ap_sig_bdd_860) begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st79_fsm_78 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st7_fsm_6 assign process. ///
always @ (ap_sig_bdd_1284)
begin
if (ap_sig_bdd_1284) begin
ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st7_fsm_6 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st80_fsm_79 assign process. ///
always @ (ap_sig_bdd_1004)
begin
if (ap_sig_bdd_1004) begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st80_fsm_79 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st81_fsm_80 assign process. ///
always @ (ap_sig_bdd_1148)
begin
if (ap_sig_bdd_1148) begin
ap_sig_cseq_ST_st81_fsm_80 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st81_fsm_80 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st82_fsm_81 assign process. ///
always @ (ap_sig_bdd_1292)
begin
if (ap_sig_bdd_1292) begin
ap_sig_cseq_ST_st82_fsm_81 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st82_fsm_81 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st83_fsm_82 assign process. ///
always @ (ap_sig_bdd_1436)
begin
if (ap_sig_bdd_1436) begin
ap_sig_cseq_ST_st83_fsm_82 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st83_fsm_82 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st84_fsm_83 assign process. ///
always @ (ap_sig_bdd_1580)
begin
if (ap_sig_bdd_1580) begin
ap_sig_cseq_ST_st84_fsm_83 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st84_fsm_83 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st85_fsm_84 assign process. ///
always @ (ap_sig_bdd_1724)
begin
if (ap_sig_bdd_1724) begin
ap_sig_cseq_ST_st85_fsm_84 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st85_fsm_84 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st86_fsm_85 assign process. ///
always @ (ap_sig_bdd_1868)
begin
if (ap_sig_bdd_1868) begin
ap_sig_cseq_ST_st86_fsm_85 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st86_fsm_85 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st87_fsm_86 assign process. ///
always @ (ap_sig_bdd_2012)
begin
if (ap_sig_bdd_2012) begin
ap_sig_cseq_ST_st87_fsm_86 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st87_fsm_86 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st88_fsm_87 assign process. ///
always @ (ap_sig_bdd_2156)
begin
if (ap_sig_bdd_2156) begin
ap_sig_cseq_ST_st88_fsm_87 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st88_fsm_87 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st89_fsm_88 assign process. ///
always @ (ap_sig_bdd_2300)
begin
if (ap_sig_bdd_2300) begin
ap_sig_cseq_ST_st89_fsm_88 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st89_fsm_88 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st8_fsm_7 assign process. ///
always @ (ap_sig_bdd_1428)
begin
if (ap_sig_bdd_1428) begin
ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st8_fsm_7 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st90_fsm_89 assign process. ///
always @ (ap_sig_bdd_3437)
begin
if (ap_sig_bdd_3437) begin
ap_sig_cseq_ST_st90_fsm_89 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st90_fsm_89 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st91_fsm_90 assign process. ///
always @ (ap_sig_bdd_428)
begin
if (ap_sig_bdd_428) begin
ap_sig_cseq_ST_st91_fsm_90 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st91_fsm_90 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st92_fsm_91 assign process. ///
always @ (ap_sig_bdd_581)
begin
if (ap_sig_bdd_581) begin
ap_sig_cseq_ST_st92_fsm_91 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st92_fsm_91 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st93_fsm_92 assign process. ///
always @ (ap_sig_bdd_725)
begin
if (ap_sig_bdd_725) begin
ap_sig_cseq_ST_st93_fsm_92 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st93_fsm_92 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st94_fsm_93 assign process. ///
always @ (ap_sig_bdd_869)
begin
if (ap_sig_bdd_869) begin
ap_sig_cseq_ST_st94_fsm_93 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st94_fsm_93 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st95_fsm_94 assign process. ///
always @ (ap_sig_bdd_1013)
begin
if (ap_sig_bdd_1013) begin
ap_sig_cseq_ST_st95_fsm_94 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st95_fsm_94 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st96_fsm_95 assign process. ///
always @ (ap_sig_bdd_1157)
begin
if (ap_sig_bdd_1157) begin
ap_sig_cseq_ST_st96_fsm_95 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st96_fsm_95 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st97_fsm_96 assign process. ///
always @ (ap_sig_bdd_1301)
begin
if (ap_sig_bdd_1301) begin
ap_sig_cseq_ST_st97_fsm_96 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st97_fsm_96 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st98_fsm_97 assign process. ///
always @ (ap_sig_bdd_1445)
begin
if (ap_sig_bdd_1445) begin
ap_sig_cseq_ST_st98_fsm_97 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st98_fsm_97 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st99_fsm_98 assign process. ///
always @ (ap_sig_bdd_1589)
begin
if (ap_sig_bdd_1589) begin
ap_sig_cseq_ST_st99_fsm_98 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st99_fsm_98 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st9_fsm_8 assign process. ///
always @ (ap_sig_bdd_1572)
begin
if (ap_sig_bdd_1572) begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st9_fsm_8 = ap_const_logic_0;
end
end
/// ap_sig_ioackin_outs_TREADY assign process. ///
always @ (outs_TREADY or ap_reg_ioackin_outs_TREADY)
begin
if ((ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) begin
ap_sig_ioackin_outs_TREADY = outs_TREADY;
end else begin
ap_sig_ioackin_outs_TREADY = ap_const_logic_1;
end
end
/// data_array_address0 assign process. ///
always @ (ap_sig_cseq_ST_st73_fsm_72 or ap_sig_cseq_ST_st74_fsm_73 or ap_sig_cseq_ST_st86_fsm_85 or ap_sig_cseq_ST_st87_fsm_86 or ap_sig_cseq_ST_st88_fsm_87 or ap_sig_cseq_ST_st89_fsm_88 or ap_sig_cseq_ST_st72_fsm_71 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg0_fsm_300 or ap_sig_cseq_ST_st71_fsm_70 or data_array_addr_16_reg_3700 or data_array_addr_18_reg_3711 or ap_sig_cseq_ST_st75_fsm_74 or data_array_addr_17_reg_3737 or data_array_addr_19_reg_3748 or ap_sig_cseq_ST_st90_fsm_89 or ap_sig_cseq_ST_st105_fsm_104 or ap_sig_cseq_ST_st120_fsm_119 or ap_sig_cseq_ST_st135_fsm_134 or ap_sig_cseq_ST_st150_fsm_149 or ap_sig_cseq_ST_st165_fsm_164 or ap_sig_cseq_ST_st180_fsm_179 or ap_sig_cseq_ST_st195_fsm_194 or ap_sig_cseq_ST_st210_fsm_209 or ap_sig_cseq_ST_st225_fsm_224 or ap_sig_cseq_ST_st240_fsm_239 or ap_sig_cseq_ST_st300_fsm_299 or tmp_1_fu_2852_p1 or ap_sig_cseq_ST_st255_fsm_254 or ap_sig_cseq_ST_st270_fsm_269 or ap_sig_cseq_ST_st285_fsm_284)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299)) begin
data_array_address0 = data_array_addr_19_reg_3748;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st285_fsm_284)) begin
data_array_address0 = data_array_addr_18_reg_3711;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st270_fsm_269)) begin
data_array_address0 = data_array_addr_17_reg_3737;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st255_fsm_254)) begin
data_array_address0 = data_array_addr_16_reg_3700;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st240_fsm_239)) begin
data_array_address0 = ap_const_lv64_F;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st225_fsm_224)) begin
data_array_address0 = ap_const_lv64_E;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st210_fsm_209)) begin
data_array_address0 = ap_const_lv64_D;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st195_fsm_194)) begin
data_array_address0 = ap_const_lv64_C;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st180_fsm_179)) begin
data_array_address0 = ap_const_lv64_B;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164)) begin
data_array_address0 = ap_const_lv64_A;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st150_fsm_149)) begin
data_array_address0 = ap_const_lv64_9;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st135_fsm_134)) begin
data_array_address0 = ap_const_lv64_8;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119)) begin
data_array_address0 = ap_const_lv64_7;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st105_fsm_104)) begin
data_array_address0 = ap_const_lv64_6;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st90_fsm_89)) begin
data_array_address0 = ap_const_lv64_5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st89_fsm_88)) begin
data_array_address0 = ap_const_lv64_3;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) begin
data_array_address0 = ap_const_lv64_1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) begin
data_array_address0 = ap_const_lv64_4;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st74_fsm_73)) begin
data_array_address0 = ap_const_lv64_2;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st73_fsm_72)) begin
data_array_address0 = ap_const_lv64_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300))) begin
data_array_address0 = tmp_1_fu_2852_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)) begin
data_array_address0 = ap_const_lv64_13;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st86_fsm_85)) begin
data_array_address0 = ap_const_lv64_11;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st72_fsm_71)) begin
data_array_address0 = ap_const_lv64_12;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st71_fsm_70)) begin
data_array_address0 = ap_const_lv64_10;
end else begin
data_array_address0 = 'bx;
end
end
/// data_array_address1 assign process. ///
always @ (ap_reg_ppiten_pp0_it83 or data_array_addr_16_reg_3700 or data_array_addr_18_reg_3711 or data_array_addr_reg_3717 or data_array_addr_2_reg_3727 or data_array_addr_4_reg_3732 or data_array_addr_17_reg_3737 or data_array_addr_19_reg_3748 or data_array_addr_1_reg_3754 or data_array_addr_3_reg_3764 or data_array_addr_5_reg_3769 or data_array_addr_6_reg_3774 or data_array_addr_7_reg_3779 or data_array_addr_8_reg_3784 or data_array_addr_9_reg_3789 or data_array_addr_10_reg_3794 or data_array_addr_11_reg_3799 or data_array_addr_12_reg_3804 or data_array_addr_13_reg_3809 or data_array_addr_14_reg_3814 or data_array_addr_15_reg_3819 or ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82 or ap_sig_cseq_ST_st388_fsm_304 or ap_sig_cseq_ST_st391_fsm_307 or ap_sig_cseq_ST_st394_fsm_310 or ap_sig_cseq_ST_st397_fsm_313 or ap_sig_cseq_ST_st400_fsm_316 or ap_sig_cseq_ST_st403_fsm_319 or ap_sig_cseq_ST_st406_fsm_322 or ap_sig_cseq_ST_st409_fsm_325 or ap_sig_cseq_ST_st412_fsm_328 or ap_sig_cseq_ST_st415_fsm_331 or ap_sig_cseq_ST_st418_fsm_334 or ap_sig_cseq_ST_st421_fsm_337 or ap_sig_cseq_ST_st424_fsm_340 or ap_sig_cseq_ST_st427_fsm_343 or ap_sig_cseq_ST_st430_fsm_346 or ap_sig_cseq_ST_st433_fsm_349 or ap_sig_cseq_ST_st436_fsm_352 or ap_sig_cseq_ST_st439_fsm_355 or ap_sig_cseq_ST_st442_fsm_358 or ap_sig_cseq_ST_st385_fsm_301)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp0_it83)) begin
data_array_address1 = ap_reg_ppstg_data_array_addr_20_reg_3863_pp0_it82;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st442_fsm_358)) begin
data_array_address1 = data_array_addr_19_reg_3748;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st439_fsm_355)) begin
data_array_address1 = data_array_addr_18_reg_3711;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st436_fsm_352)) begin
data_array_address1 = data_array_addr_17_reg_3737;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st433_fsm_349)) begin
data_array_address1 = data_array_addr_16_reg_3700;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st430_fsm_346)) begin
data_array_address1 = data_array_addr_15_reg_3819;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st427_fsm_343)) begin
data_array_address1 = data_array_addr_14_reg_3814;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st424_fsm_340)) begin
data_array_address1 = data_array_addr_13_reg_3809;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st421_fsm_337)) begin
data_array_address1 = data_array_addr_12_reg_3804;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st418_fsm_334)) begin
data_array_address1 = data_array_addr_11_reg_3799;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st415_fsm_331)) begin
data_array_address1 = data_array_addr_10_reg_3794;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st412_fsm_328)) begin
data_array_address1 = data_array_addr_9_reg_3789;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st409_fsm_325)) begin
data_array_address1 = data_array_addr_8_reg_3784;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st406_fsm_322)) begin
data_array_address1 = data_array_addr_7_reg_3779;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st403_fsm_319)) begin
data_array_address1 = data_array_addr_6_reg_3774;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st400_fsm_316)) begin
data_array_address1 = data_array_addr_5_reg_3769;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st397_fsm_313)) begin
data_array_address1 = data_array_addr_4_reg_3732;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st394_fsm_310)) begin
data_array_address1 = data_array_addr_3_reg_3764;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st391_fsm_307)) begin
data_array_address1 = data_array_addr_2_reg_3727;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st388_fsm_304)) begin
data_array_address1 = data_array_addr_1_reg_3754;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st385_fsm_301)) begin
data_array_address1 = data_array_addr_reg_3717;
end else begin
data_array_address1 = 'bx;
end
end
/// data_array_ce0 assign process. ///
always @ (ins_TVALID or ap_sig_cseq_ST_st73_fsm_72 or ap_sig_cseq_ST_st74_fsm_73 or ap_sig_cseq_ST_st86_fsm_85 or ap_sig_cseq_ST_st87_fsm_86 or ap_sig_cseq_ST_st88_fsm_87 or ap_sig_cseq_ST_st89_fsm_88 or ap_sig_cseq_ST_st72_fsm_71 or ap_reg_ppiten_pp0_it0 or ap_sig_cseq_ST_pp0_stg0_fsm_300 or ap_sig_cseq_ST_st71_fsm_70 or ap_sig_cseq_ST_st75_fsm_74 or ap_sig_cseq_ST_st90_fsm_89 or ap_sig_cseq_ST_st105_fsm_104 or ap_sig_cseq_ST_st120_fsm_119 or ap_sig_cseq_ST_st135_fsm_134 or ap_sig_cseq_ST_st150_fsm_149 or ap_sig_cseq_ST_st165_fsm_164 or ap_sig_cseq_ST_st180_fsm_179 or ap_sig_cseq_ST_st195_fsm_194 or ap_sig_cseq_ST_st210_fsm_209 or ap_sig_cseq_ST_st225_fsm_224 or ap_sig_cseq_ST_st240_fsm_239 or ap_sig_cseq_ST_st300_fsm_299 or ap_sig_cseq_ST_st255_fsm_254 or ap_sig_cseq_ST_st270_fsm_269 or ap_sig_cseq_ST_st285_fsm_284)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st73_fsm_72)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st74_fsm_73)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st86_fsm_85)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st89_fsm_88)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st72_fsm_71)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st71_fsm_70)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st90_fsm_89)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st105_fsm_104)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st135_fsm_134)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st150_fsm_149)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st180_fsm_179)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st195_fsm_194)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st210_fsm_209)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st225_fsm_224)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st240_fsm_239)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299)) | ((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp0_stg0_fsm_300)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st255_fsm_254)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st270_fsm_269)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st285_fsm_284)))) begin
data_array_ce0 = ap_const_logic_1;
end else begin
data_array_ce0 = ap_const_logic_0;
end
end
/// data_array_ce1 assign process. ///
always @ (ap_reg_ppiten_pp0_it83 or ap_sig_ioackin_outs_TREADY or ap_sig_cseq_ST_st388_fsm_304 or ap_sig_cseq_ST_st391_fsm_307 or ap_sig_cseq_ST_st394_fsm_310 or ap_sig_cseq_ST_st397_fsm_313 or ap_sig_cseq_ST_st400_fsm_316 or ap_sig_cseq_ST_st403_fsm_319 or ap_sig_cseq_ST_st406_fsm_322 or ap_sig_cseq_ST_st409_fsm_325 or ap_sig_cseq_ST_st412_fsm_328 or ap_sig_cseq_ST_st415_fsm_331 or ap_sig_cseq_ST_st418_fsm_334 or ap_sig_cseq_ST_st421_fsm_337 or ap_sig_cseq_ST_st424_fsm_340 or ap_sig_cseq_ST_st427_fsm_343 or ap_sig_cseq_ST_st430_fsm_346 or ap_sig_cseq_ST_st433_fsm_349 or ap_sig_cseq_ST_st436_fsm_352 or ap_sig_cseq_ST_st439_fsm_355 or ap_sig_cseq_ST_st442_fsm_358 or ap_sig_cseq_ST_st385_fsm_301)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it83) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st388_fsm_304)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st391_fsm_307)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st394_fsm_310)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st397_fsm_313)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st400_fsm_316)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st403_fsm_319)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st406_fsm_322)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st409_fsm_325)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st412_fsm_328)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st415_fsm_331)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st418_fsm_334)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st421_fsm_337)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st424_fsm_340)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st427_fsm_343)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st430_fsm_346)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st433_fsm_349)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st436_fsm_352)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st439_fsm_355)) | (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY) & (ap_const_logic_1 == ap_sig_cseq_ST_st442_fsm_358)) | (ap_const_logic_1 == ap_sig_cseq_ST_st385_fsm_301))) begin
data_array_ce1 = ap_const_logic_1;
end else begin
data_array_ce1 = ap_const_logic_0;
end
end
/// data_array_d0 assign process. ///
always @ (ap_sig_cseq_ST_st73_fsm_72 or ap_sig_cseq_ST_st74_fsm_73 or ap_sig_cseq_ST_st88_fsm_87 or ap_sig_cseq_ST_st89_fsm_88 or ap_sig_cseq_ST_st75_fsm_74 or ap_sig_cseq_ST_st90_fsm_89 or ap_sig_cseq_ST_st105_fsm_104 or ap_sig_cseq_ST_st120_fsm_119 or ap_sig_cseq_ST_st135_fsm_134 or ap_sig_cseq_ST_st150_fsm_149 or ap_sig_cseq_ST_st165_fsm_164 or ap_sig_cseq_ST_st180_fsm_179 or ap_sig_cseq_ST_st195_fsm_194 or ap_sig_cseq_ST_st210_fsm_209 or ap_sig_cseq_ST_st225_fsm_224 or ap_sig_cseq_ST_st240_fsm_239 or ap_sig_cseq_ST_st300_fsm_299 or ap_sig_cseq_ST_st255_fsm_254 or ap_sig_cseq_ST_st270_fsm_269 or ap_sig_cseq_ST_st285_fsm_284 or rez_addr959960_part_set_fu_830_p5 or rez_addr_3953954_part_set_fu_922_p5 or rez_addr_5947948_part_set_fu_1017_p5 or rez_addr_1956957_part_set_fu_1109_p5 or rez_addr_4950951_part_set_fu_1201_p5 or rez_addr_6944945_part_set_fu_1308_p5 or rez_addr_7941942_part_set_fu_1415_p5 or rez_addr_8938939_part_set_fu_1522_p5 or rez_addr_9935936_part_set_fu_1629_p5 or rez_addr_10932933_part_set_fu_1736_p5 or rez_addr_11929930_part_set_fu_1843_p5 or rez_addr_12926927_part_set_fu_1950_p5 or rez_addr_13923924_part_set_fu_2057_p5 or rez_addr_14920921_part_set_fu_2164_p5 or rez_addr_15917918_part_set_fu_2271_p5 or rez_addr_16914915_part_set_fu_2378_p5 or rez_addr_17911912_part_set_fu_2485_p5 or rez_addr_18908909_part_set_fu_2592_p5 or rez_addr_19905906_part_set_fu_2698_p5 or rez_addr_20902903_part_set_fu_2828_p5)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299)) begin
data_array_d0 = rez_addr_20902903_part_set_fu_2828_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st285_fsm_284)) begin
data_array_d0 = rez_addr_19905906_part_set_fu_2698_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st270_fsm_269)) begin
data_array_d0 = rez_addr_18908909_part_set_fu_2592_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st255_fsm_254)) begin
data_array_d0 = rez_addr_17911912_part_set_fu_2485_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st240_fsm_239)) begin
data_array_d0 = rez_addr_16914915_part_set_fu_2378_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st225_fsm_224)) begin
data_array_d0 = rez_addr_15917918_part_set_fu_2271_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st210_fsm_209)) begin
data_array_d0 = rez_addr_14920921_part_set_fu_2164_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st195_fsm_194)) begin
data_array_d0 = rez_addr_13923924_part_set_fu_2057_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st180_fsm_179)) begin
data_array_d0 = rez_addr_12926927_part_set_fu_1950_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164)) begin
data_array_d0 = rez_addr_11929930_part_set_fu_1843_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st150_fsm_149)) begin
data_array_d0 = rez_addr_10932933_part_set_fu_1736_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st135_fsm_134)) begin
data_array_d0 = rez_addr_9935936_part_set_fu_1629_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119)) begin
data_array_d0 = rez_addr_8938939_part_set_fu_1522_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st105_fsm_104)) begin
data_array_d0 = rez_addr_7941942_part_set_fu_1415_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st90_fsm_89)) begin
data_array_d0 = rez_addr_6944945_part_set_fu_1308_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st89_fsm_88)) begin
data_array_d0 = rez_addr_4950951_part_set_fu_1201_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) begin
data_array_d0 = rez_addr_1956957_part_set_fu_1109_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) begin
data_array_d0 = rez_addr_5947948_part_set_fu_1017_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st74_fsm_73)) begin
data_array_d0 = rez_addr_3953954_part_set_fu_922_p5;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st73_fsm_72)) begin
data_array_d0 = rez_addr959960_part_set_fu_830_p5;
end else begin
data_array_d0 = 'bx;
end
end
/// data_array_we0 assign process. ///
always @ (ins_TVALID or ap_sig_cseq_ST_st73_fsm_72 or ap_sig_cseq_ST_st74_fsm_73 or ap_sig_cseq_ST_st88_fsm_87 or ap_sig_cseq_ST_st89_fsm_88 or ap_sig_cseq_ST_st75_fsm_74 or ap_sig_cseq_ST_st90_fsm_89 or ap_sig_cseq_ST_st105_fsm_104 or ap_sig_cseq_ST_st120_fsm_119 or ap_sig_cseq_ST_st135_fsm_134 or ap_sig_cseq_ST_st150_fsm_149 or ap_sig_cseq_ST_st165_fsm_164 or ap_sig_cseq_ST_st180_fsm_179 or ap_sig_cseq_ST_st195_fsm_194 or ap_sig_cseq_ST_st210_fsm_209 or ap_sig_cseq_ST_st225_fsm_224 or ap_sig_cseq_ST_st240_fsm_239 or ap_sig_cseq_ST_st300_fsm_299 or ap_sig_cseq_ST_st255_fsm_254 or ap_sig_cseq_ST_st270_fsm_269 or ap_sig_cseq_ST_st285_fsm_284)
begin
if (((~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st73_fsm_72)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st74_fsm_73)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st89_fsm_88)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st90_fsm_89)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st105_fsm_104)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st135_fsm_134)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st150_fsm_149)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st180_fsm_179)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st195_fsm_194)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st210_fsm_209)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st225_fsm_224)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st240_fsm_239)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st255_fsm_254)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st270_fsm_269)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st285_fsm_284)))) begin
data_array_we0 = ap_const_logic_1;
end else begin
data_array_we0 = ap_const_logic_0;
end
end
/// data_array_we1 assign process. ///
always @ (ap_reg_ppiten_pp0_it83 or ap_reg_ppstg_exitcond2_reg_3854_pp0_it82)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it83) & (ap_const_lv1_0 == ap_reg_ppstg_exitcond2_reg_3854_pp0_it82))) begin
data_array_we1 = ap_const_logic_1;
end else begin
data_array_we1 = ap_const_logic_0;
end
end
/// ins_TREADY assign process. ///
always @ (ins_TVALID or ap_sig_cseq_ST_st1_fsm_0 or ap_sig_cseq_ST_st73_fsm_72 or ap_sig_cseq_ST_st76_fsm_75 or ap_sig_cseq_ST_st91_fsm_90 or ap_sig_cseq_ST_st106_fsm_105 or ap_sig_cseq_ST_st121_fsm_120 or ap_sig_cseq_ST_st136_fsm_135 or ap_sig_cseq_ST_st151_fsm_150 or ap_sig_cseq_ST_st166_fsm_165 or ap_sig_cseq_ST_st181_fsm_180 or ap_sig_cseq_ST_st196_fsm_195 or ap_sig_cseq_ST_st211_fsm_210 or ap_sig_cseq_ST_st226_fsm_225 or ap_sig_cseq_ST_st241_fsm_240 or ap_sig_cseq_ST_st256_fsm_255 or ap_sig_cseq_ST_st271_fsm_270 or ap_sig_cseq_ST_st286_fsm_285 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_cseq_ST_st74_fsm_73 or ap_sig_cseq_ST_st77_fsm_76 or ap_sig_cseq_ST_st92_fsm_91 or ap_sig_cseq_ST_st107_fsm_106 or ap_sig_cseq_ST_st122_fsm_121 or ap_sig_cseq_ST_st137_fsm_136 or ap_sig_cseq_ST_st152_fsm_151 or ap_sig_cseq_ST_st167_fsm_166 or ap_sig_cseq_ST_st182_fsm_181 or ap_sig_cseq_ST_st197_fsm_196 or ap_sig_cseq_ST_st212_fsm_211 or ap_sig_cseq_ST_st227_fsm_226 or ap_sig_cseq_ST_st242_fsm_241 or ap_sig_cseq_ST_st257_fsm_256 or ap_sig_cseq_ST_st272_fsm_271 or ap_sig_cseq_ST_st287_fsm_286 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_cseq_ST_st78_fsm_77 or ap_sig_cseq_ST_st93_fsm_92 or ap_sig_cseq_ST_st108_fsm_107 or ap_sig_cseq_ST_st123_fsm_122 or ap_sig_cseq_ST_st138_fsm_137 or ap_sig_cseq_ST_st153_fsm_152 or ap_sig_cseq_ST_st168_fsm_167 or ap_sig_cseq_ST_st183_fsm_182 or ap_sig_cseq_ST_st198_fsm_197 or ap_sig_cseq_ST_st213_fsm_212 or ap_sig_cseq_ST_st228_fsm_227 or ap_sig_cseq_ST_st243_fsm_242 or ap_sig_cseq_ST_st258_fsm_257 or ap_sig_cseq_ST_st273_fsm_272 or ap_sig_cseq_ST_st288_fsm_287 or ap_sig_cseq_ST_st4_fsm_3 or ap_sig_cseq_ST_st79_fsm_78 or ap_sig_cseq_ST_st94_fsm_93 or ap_sig_cseq_ST_st109_fsm_108 or ap_sig_cseq_ST_st124_fsm_123 or ap_sig_cseq_ST_st139_fsm_138 or ap_sig_cseq_ST_st154_fsm_153 or ap_sig_cseq_ST_st169_fsm_168 or ap_sig_cseq_ST_st184_fsm_183 or ap_sig_cseq_ST_st199_fsm_198 or ap_sig_cseq_ST_st214_fsm_213 or ap_sig_cseq_ST_st229_fsm_228 or ap_sig_cseq_ST_st244_fsm_243 or ap_sig_cseq_ST_st259_fsm_258 or ap_sig_cseq_ST_st274_fsm_273 or ap_sig_cseq_ST_st289_fsm_288 or ap_sig_cseq_ST_st5_fsm_4 or ap_sig_cseq_ST_st80_fsm_79 or ap_sig_cseq_ST_st95_fsm_94 or ap_sig_cseq_ST_st110_fsm_109 or ap_sig_cseq_ST_st125_fsm_124 or ap_sig_cseq_ST_st140_fsm_139 or ap_sig_cseq_ST_st155_fsm_154 or ap_sig_cseq_ST_st170_fsm_169 or ap_sig_cseq_ST_st185_fsm_184 or ap_sig_cseq_ST_st200_fsm_199 or ap_sig_cseq_ST_st215_fsm_214 or ap_sig_cseq_ST_st230_fsm_229 or ap_sig_cseq_ST_st245_fsm_244 or ap_sig_cseq_ST_st260_fsm_259 or ap_sig_cseq_ST_st275_fsm_274 or ap_sig_cseq_ST_st290_fsm_289 or ap_sig_cseq_ST_st6_fsm_5 or ap_sig_cseq_ST_st81_fsm_80 or ap_sig_cseq_ST_st96_fsm_95 or ap_sig_cseq_ST_st111_fsm_110 or ap_sig_cseq_ST_st126_fsm_125 or ap_sig_cseq_ST_st141_fsm_140 or ap_sig_cseq_ST_st156_fsm_155 or ap_sig_cseq_ST_st171_fsm_170 or ap_sig_cseq_ST_st186_fsm_185 or ap_sig_cseq_ST_st201_fsm_200 or ap_sig_cseq_ST_st216_fsm_215 or ap_sig_cseq_ST_st231_fsm_230 or ap_sig_cseq_ST_st246_fsm_245 or ap_sig_cseq_ST_st261_fsm_260 or ap_sig_cseq_ST_st276_fsm_275 or ap_sig_cseq_ST_st291_fsm_290 or ap_sig_cseq_ST_st7_fsm_6 or ap_sig_cseq_ST_st82_fsm_81 or ap_sig_cseq_ST_st97_fsm_96 or ap_sig_cseq_ST_st112_fsm_111 or ap_sig_cseq_ST_st127_fsm_126 or ap_sig_cseq_ST_st142_fsm_141 or ap_sig_cseq_ST_st157_fsm_156 or ap_sig_cseq_ST_st172_fsm_171 or ap_sig_cseq_ST_st187_fsm_186 or ap_sig_cseq_ST_st202_fsm_201 or ap_sig_cseq_ST_st217_fsm_216 or ap_sig_cseq_ST_st232_fsm_231 or ap_sig_cseq_ST_st247_fsm_246 or ap_sig_cseq_ST_st262_fsm_261 or ap_sig_cseq_ST_st277_fsm_276 or ap_sig_cseq_ST_st292_fsm_291 or ap_sig_cseq_ST_st8_fsm_7 or ap_sig_cseq_ST_st83_fsm_82 or ap_sig_cseq_ST_st98_fsm_97 or ap_sig_cseq_ST_st113_fsm_112 or ap_sig_cseq_ST_st128_fsm_127 or ap_sig_cseq_ST_st143_fsm_142 or ap_sig_cseq_ST_st158_fsm_157 or ap_sig_cseq_ST_st173_fsm_172 or ap_sig_cseq_ST_st188_fsm_187 or ap_sig_cseq_ST_st203_fsm_202 or ap_sig_cseq_ST_st218_fsm_217 or ap_sig_cseq_ST_st233_fsm_232 or ap_sig_cseq_ST_st248_fsm_247 or ap_sig_cseq_ST_st263_fsm_262 or ap_sig_cseq_ST_st278_fsm_277 or ap_sig_cseq_ST_st293_fsm_292 or ap_sig_cseq_ST_st9_fsm_8 or ap_sig_cseq_ST_st84_fsm_83 or ap_sig_cseq_ST_st99_fsm_98 or ap_sig_cseq_ST_st114_fsm_113 or ap_sig_cseq_ST_st129_fsm_128 or ap_sig_cseq_ST_st144_fsm_143 or ap_sig_cseq_ST_st159_fsm_158 or ap_sig_cseq_ST_st174_fsm_173 or ap_sig_cseq_ST_st189_fsm_188 or ap_sig_cseq_ST_st204_fsm_203 or ap_sig_cseq_ST_st219_fsm_218 or ap_sig_cseq_ST_st234_fsm_233 or ap_sig_cseq_ST_st249_fsm_248 or ap_sig_cseq_ST_st264_fsm_263 or ap_sig_cseq_ST_st279_fsm_278 or ap_sig_cseq_ST_st294_fsm_293 or ap_sig_cseq_ST_st10_fsm_9 or ap_sig_cseq_ST_st85_fsm_84 or ap_sig_cseq_ST_st100_fsm_99 or ap_sig_cseq_ST_st115_fsm_114 or ap_sig_cseq_ST_st130_fsm_129 or ap_sig_cseq_ST_st145_fsm_144 or ap_sig_cseq_ST_st160_fsm_159 or ap_sig_cseq_ST_st175_fsm_174 or ap_sig_cseq_ST_st190_fsm_189 or ap_sig_cseq_ST_st205_fsm_204 or ap_sig_cseq_ST_st220_fsm_219 or ap_sig_cseq_ST_st235_fsm_234 or ap_sig_cseq_ST_st250_fsm_249 or ap_sig_cseq_ST_st265_fsm_264 or ap_sig_cseq_ST_st280_fsm_279 or ap_sig_cseq_ST_st295_fsm_294 or ap_sig_cseq_ST_st11_fsm_10 or ap_sig_cseq_ST_st86_fsm_85 or ap_sig_cseq_ST_st101_fsm_100 or ap_sig_cseq_ST_st116_fsm_115 or ap_sig_cseq_ST_st131_fsm_130 or ap_sig_cseq_ST_st146_fsm_145 or ap_sig_cseq_ST_st161_fsm_160 or ap_sig_cseq_ST_st176_fsm_175 or ap_sig_cseq_ST_st191_fsm_190 or ap_sig_cseq_ST_st206_fsm_205 or ap_sig_cseq_ST_st221_fsm_220 or ap_sig_cseq_ST_st236_fsm_235 or ap_sig_cseq_ST_st251_fsm_250 or ap_sig_cseq_ST_st266_fsm_265 or ap_sig_cseq_ST_st281_fsm_280 or ap_sig_cseq_ST_st296_fsm_295 or ap_sig_cseq_ST_st12_fsm_11 or ap_sig_cseq_ST_st87_fsm_86 or ap_sig_cseq_ST_st102_fsm_101 or ap_sig_cseq_ST_st117_fsm_116 or ap_sig_cseq_ST_st132_fsm_131 or ap_sig_cseq_ST_st147_fsm_146 or ap_sig_cseq_ST_st162_fsm_161 or ap_sig_cseq_ST_st177_fsm_176 or ap_sig_cseq_ST_st192_fsm_191 or ap_sig_cseq_ST_st207_fsm_206 or ap_sig_cseq_ST_st222_fsm_221 or ap_sig_cseq_ST_st237_fsm_236 or ap_sig_cseq_ST_st252_fsm_251 or ap_sig_cseq_ST_st267_fsm_266 or ap_sig_cseq_ST_st282_fsm_281 or ap_sig_cseq_ST_st297_fsm_296 or ap_sig_cseq_ST_st13_fsm_12 or ap_sig_cseq_ST_st88_fsm_87 or ap_sig_cseq_ST_st103_fsm_102 or ap_sig_cseq_ST_st118_fsm_117 or ap_sig_cseq_ST_st133_fsm_132 or ap_sig_cseq_ST_st148_fsm_147 or ap_sig_cseq_ST_st163_fsm_162 or ap_sig_cseq_ST_st178_fsm_177 or ap_sig_cseq_ST_st193_fsm_192 or ap_sig_cseq_ST_st208_fsm_207 or ap_sig_cseq_ST_st223_fsm_222 or ap_sig_cseq_ST_st238_fsm_237 or ap_sig_cseq_ST_st253_fsm_252 or ap_sig_cseq_ST_st268_fsm_267 or ap_sig_cseq_ST_st283_fsm_282 or ap_sig_cseq_ST_st298_fsm_297 or ap_sig_cseq_ST_st14_fsm_13 or ap_sig_cseq_ST_st89_fsm_88 or ap_sig_cseq_ST_st104_fsm_103 or ap_sig_cseq_ST_st119_fsm_118 or ap_sig_cseq_ST_st134_fsm_133 or ap_sig_cseq_ST_st149_fsm_148 or ap_sig_cseq_ST_st164_fsm_163 or ap_sig_cseq_ST_st179_fsm_178 or ap_sig_cseq_ST_st194_fsm_193 or ap_sig_cseq_ST_st209_fsm_208 or ap_sig_cseq_ST_st224_fsm_223 or ap_sig_cseq_ST_st239_fsm_238 or ap_sig_cseq_ST_st254_fsm_253 or ap_sig_cseq_ST_st269_fsm_268 or ap_sig_cseq_ST_st284_fsm_283 or ap_sig_cseq_ST_st299_fsm_298 or ap_sig_cseq_ST_st72_fsm_71 or ap_sig_cseq_ST_st15_fsm_14 or ap_sig_cseq_ST_st16_fsm_15 or ap_sig_cseq_ST_st17_fsm_16 or ap_sig_cseq_ST_st18_fsm_17 or ap_sig_cseq_ST_st19_fsm_18 or ap_sig_cseq_ST_st20_fsm_19 or ap_sig_cseq_ST_st21_fsm_20 or ap_sig_cseq_ST_st22_fsm_21 or ap_sig_cseq_ST_st23_fsm_22 or ap_sig_cseq_ST_st24_fsm_23 or ap_sig_cseq_ST_st25_fsm_24 or ap_sig_cseq_ST_st26_fsm_25 or ap_sig_cseq_ST_st27_fsm_26 or ap_sig_cseq_ST_st28_fsm_27 or ap_sig_cseq_ST_st29_fsm_28 or ap_sig_cseq_ST_st30_fsm_29 or ap_sig_cseq_ST_st31_fsm_30 or ap_sig_cseq_ST_st32_fsm_31 or ap_sig_cseq_ST_st33_fsm_32 or ap_sig_cseq_ST_st34_fsm_33 or ap_sig_cseq_ST_st35_fsm_34 or ap_sig_cseq_ST_st36_fsm_35 or ap_sig_cseq_ST_st37_fsm_36 or ap_sig_cseq_ST_st38_fsm_37 or ap_sig_cseq_ST_st39_fsm_38 or ap_sig_cseq_ST_st40_fsm_39 or ap_sig_cseq_ST_st41_fsm_40 or ap_sig_cseq_ST_st42_fsm_41 or ap_sig_cseq_ST_st43_fsm_42 or ap_sig_cseq_ST_st44_fsm_43 or ap_sig_cseq_ST_st45_fsm_44 or ap_sig_cseq_ST_st46_fsm_45 or ap_sig_cseq_ST_st47_fsm_46 or ap_sig_cseq_ST_st48_fsm_47 or ap_sig_cseq_ST_st49_fsm_48 or ap_sig_cseq_ST_st50_fsm_49 or ap_sig_cseq_ST_st51_fsm_50 or ap_sig_cseq_ST_st52_fsm_51 or ap_sig_cseq_ST_st53_fsm_52 or ap_sig_cseq_ST_st54_fsm_53 or ap_sig_cseq_ST_st55_fsm_54 or ap_sig_cseq_ST_st56_fsm_55 or ap_sig_cseq_ST_st57_fsm_56 or ap_sig_cseq_ST_st58_fsm_57 or ap_sig_cseq_ST_st59_fsm_58 or ap_sig_cseq_ST_st60_fsm_59 or ap_sig_cseq_ST_st61_fsm_60 or ap_sig_cseq_ST_st62_fsm_61 or ap_sig_cseq_ST_st63_fsm_62 or ap_sig_cseq_ST_st64_fsm_63 or ap_sig_cseq_ST_st65_fsm_64 or ap_sig_cseq_ST_st66_fsm_65 or ap_sig_cseq_ST_st67_fsm_66 or ap_sig_cseq_ST_st68_fsm_67 or ap_sig_cseq_ST_st69_fsm_68 or ap_sig_cseq_ST_st70_fsm_69 or ap_sig_cseq_ST_st71_fsm_70 or ap_sig_cseq_ST_st75_fsm_74 or ap_sig_cseq_ST_st90_fsm_89 or ap_sig_cseq_ST_st105_fsm_104 or ap_sig_cseq_ST_st120_fsm_119 or ap_sig_cseq_ST_st135_fsm_134 or ap_sig_cseq_ST_st150_fsm_149 or ap_sig_cseq_ST_st165_fsm_164 or ap_sig_cseq_ST_st180_fsm_179 or ap_sig_cseq_ST_st195_fsm_194 or ap_sig_cseq_ST_st210_fsm_209 or ap_sig_cseq_ST_st225_fsm_224 or ap_sig_cseq_ST_st240_fsm_239 or ap_sig_cseq_ST_st300_fsm_299 or ap_sig_cseq_ST_st255_fsm_254 or ap_sig_cseq_ST_st270_fsm_269 or ap_sig_cseq_ST_st285_fsm_284)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ins_TVALID == ap_const_logic_0)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st73_fsm_72)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st76_fsm_75)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st91_fsm_90)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st106_fsm_105)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st121_fsm_120)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st136_fsm_135)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st151_fsm_150)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st166_fsm_165)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st181_fsm_180)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st196_fsm_195)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st211_fsm_210)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st226_fsm_225)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st241_fsm_240)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st256_fsm_255)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st271_fsm_270)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st286_fsm_285)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st74_fsm_73)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st77_fsm_76)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st92_fsm_91)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st107_fsm_106)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st122_fsm_121)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st137_fsm_136)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st152_fsm_151)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st167_fsm_166)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st182_fsm_181)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st197_fsm_196)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st212_fsm_211)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st227_fsm_226)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st242_fsm_241)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st257_fsm_256)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st272_fsm_271)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st287_fsm_286)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st78_fsm_77)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st93_fsm_92)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st108_fsm_107)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st123_fsm_122)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st138_fsm_137)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st153_fsm_152)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st168_fsm_167)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st183_fsm_182)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st198_fsm_197)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st213_fsm_212)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st228_fsm_227)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st243_fsm_242)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st258_fsm_257)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st273_fsm_272)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st288_fsm_287)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st4_fsm_3)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st79_fsm_78)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st94_fsm_93)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st109_fsm_108)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st124_fsm_123)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st139_fsm_138)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st154_fsm_153)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st169_fsm_168)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st184_fsm_183)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st199_fsm_198)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st214_fsm_213)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st229_fsm_228)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st244_fsm_243)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st259_fsm_258)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st274_fsm_273)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st289_fsm_288)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st5_fsm_4)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st80_fsm_79)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st95_fsm_94)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st110_fsm_109)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st125_fsm_124)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st140_fsm_139)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st155_fsm_154)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st170_fsm_169)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st185_fsm_184)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st200_fsm_199)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st215_fsm_214)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st230_fsm_229)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st245_fsm_244)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st260_fsm_259)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st275_fsm_274)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st290_fsm_289)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st6_fsm_5)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st81_fsm_80)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st96_fsm_95)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st111_fsm_110)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st126_fsm_125)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st141_fsm_140)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st156_fsm_155)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st171_fsm_170)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st186_fsm_185)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st201_fsm_200)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st216_fsm_215)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st231_fsm_230)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st246_fsm_245)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st261_fsm_260)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st276_fsm_275)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st291_fsm_290)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st7_fsm_6)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st82_fsm_81)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st97_fsm_96)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st112_fsm_111)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st127_fsm_126)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st142_fsm_141)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st157_fsm_156)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st172_fsm_171)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st187_fsm_186)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st202_fsm_201)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st217_fsm_216)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st232_fsm_231)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st247_fsm_246)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st262_fsm_261)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st277_fsm_276)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st292_fsm_291)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st8_fsm_7)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st83_fsm_82)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st98_fsm_97)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st113_fsm_112)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st128_fsm_127)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st143_fsm_142)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st158_fsm_157)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st173_fsm_172)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st188_fsm_187)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st203_fsm_202)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st218_fsm_217)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st233_fsm_232)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st248_fsm_247)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st263_fsm_262)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st278_fsm_277)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st293_fsm_292)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st9_fsm_8)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st84_fsm_83)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st99_fsm_98)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st114_fsm_113)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st129_fsm_128)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st144_fsm_143)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st159_fsm_158)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st174_fsm_173)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st189_fsm_188)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st204_fsm_203)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st219_fsm_218)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st234_fsm_233)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st249_fsm_248)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st264_fsm_263)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st279_fsm_278)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st294_fsm_293)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st10_fsm_9)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st85_fsm_84)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st100_fsm_99)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st115_fsm_114)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st130_fsm_129)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st145_fsm_144)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st160_fsm_159)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st175_fsm_174)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st190_fsm_189)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st205_fsm_204)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st220_fsm_219)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st235_fsm_234)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st250_fsm_249)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st265_fsm_264)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st280_fsm_279)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st295_fsm_294)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st11_fsm_10)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st86_fsm_85)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st101_fsm_100)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st116_fsm_115)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st131_fsm_130)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st146_fsm_145)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st161_fsm_160)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st176_fsm_175)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st191_fsm_190)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st206_fsm_205)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st221_fsm_220)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st236_fsm_235)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st251_fsm_250)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st266_fsm_265)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st281_fsm_280)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st296_fsm_295)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st12_fsm_11)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st87_fsm_86)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st102_fsm_101)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st117_fsm_116)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st132_fsm_131)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st147_fsm_146)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st162_fsm_161)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st177_fsm_176)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st192_fsm_191)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st207_fsm_206)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st222_fsm_221)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st237_fsm_236)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st252_fsm_251)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st267_fsm_266)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st282_fsm_281)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st297_fsm_296)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st13_fsm_12)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st88_fsm_87)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st103_fsm_102)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st118_fsm_117)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st133_fsm_132)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st148_fsm_147)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st163_fsm_162)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st178_fsm_177)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st193_fsm_192)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st208_fsm_207)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st223_fsm_222)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st238_fsm_237)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st253_fsm_252)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st268_fsm_267)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st283_fsm_282)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st298_fsm_297)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st14_fsm_13)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st89_fsm_88)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st104_fsm_103)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st119_fsm_118)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st134_fsm_133)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st149_fsm_148)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st164_fsm_163)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st179_fsm_178)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st194_fsm_193)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st209_fsm_208)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st224_fsm_223)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st239_fsm_238)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st254_fsm_253)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st269_fsm_268)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st284_fsm_283)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st299_fsm_298)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st72_fsm_71)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st15_fsm_14)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st16_fsm_15)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st17_fsm_16)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st18_fsm_17)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st19_fsm_18)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st20_fsm_19)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st21_fsm_20)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st22_fsm_21)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st23_fsm_22)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st24_fsm_23)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st25_fsm_24)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st26_fsm_25)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st27_fsm_26)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st28_fsm_27)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st29_fsm_28)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st30_fsm_29)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st31_fsm_30)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st32_fsm_31)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st33_fsm_32)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st34_fsm_33)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st35_fsm_34)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st36_fsm_35)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st37_fsm_36)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st38_fsm_37)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st39_fsm_38)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st40_fsm_39)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st41_fsm_40)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st42_fsm_41)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st43_fsm_42)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st44_fsm_43)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st45_fsm_44)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st46_fsm_45)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st47_fsm_46)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st48_fsm_47)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st49_fsm_48)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st50_fsm_49)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st51_fsm_50)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st52_fsm_51)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st53_fsm_52)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st54_fsm_53)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st55_fsm_54)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st56_fsm_55)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st57_fsm_56)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st58_fsm_57)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st59_fsm_58)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st60_fsm_59)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st61_fsm_60)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st62_fsm_61)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st63_fsm_62)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st64_fsm_63)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st65_fsm_64)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st66_fsm_65)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st67_fsm_66)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st68_fsm_67)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st69_fsm_68)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st70_fsm_69)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st71_fsm_70)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st75_fsm_74)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st90_fsm_89)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st105_fsm_104)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st120_fsm_119)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st135_fsm_134)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st150_fsm_149)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st165_fsm_164)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st180_fsm_179)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st195_fsm_194)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st210_fsm_209)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st225_fsm_224)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st240_fsm_239)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st300_fsm_299)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st255_fsm_254)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st270_fsm_269)) | (~(ins_TVALID == ap_const_logic_0) & (ap_const_logic_1 == ap_sig_cseq_ST_st285_fsm_284)))) begin
ins_TREADY = ap_const_logic_1;
end else begin
ins_TREADY = ap_const_logic_0;
end
end
/// outs_TDATA assign process. ///
always @ (ap_sig_cseq_ST_st386_fsm_302 or ap_sig_cseq_ST_st389_fsm_305 or ap_sig_cseq_ST_st392_fsm_308 or ap_sig_cseq_ST_st395_fsm_311 or ap_sig_cseq_ST_st398_fsm_314 or ap_sig_cseq_ST_st401_fsm_317 or ap_sig_cseq_ST_st404_fsm_320 or ap_sig_cseq_ST_st407_fsm_323 or ap_sig_cseq_ST_st410_fsm_326 or ap_sig_cseq_ST_st413_fsm_329 or ap_sig_cseq_ST_st416_fsm_332 or ap_sig_cseq_ST_st419_fsm_335 or ap_sig_cseq_ST_st422_fsm_338 or ap_sig_cseq_ST_st425_fsm_341 or ap_sig_cseq_ST_st428_fsm_344 or ap_sig_cseq_ST_st431_fsm_347 or ap_sig_cseq_ST_st434_fsm_350 or ap_sig_cseq_ST_st437_fsm_353 or ap_sig_cseq_ST_st440_fsm_356 or ap_sig_cseq_ST_st443_fsm_359 or t_load_fu_3115_p1 or gamma_load_fu_3120_p1 or ap_sig_cseq_ST_st387_fsm_303 or beta_load_fu_3125_p1 or ap_sig_cseq_ST_st388_fsm_304 or t_load_s_fu_3130_p1 or gamma_load_s_fu_3135_p1 or ap_sig_cseq_ST_st390_fsm_306 or beta_load_s_fu_3140_p1 or ap_sig_cseq_ST_st391_fsm_307 or t_load_1_fu_3145_p1 or gamma_load_1_fu_3150_p1 or ap_sig_cseq_ST_st393_fsm_309 or beta_load_1_fu_3155_p1 or ap_sig_cseq_ST_st394_fsm_310 or t_load_2_fu_3160_p1 or gamma_load_2_fu_3165_p1 or ap_sig_cseq_ST_st396_fsm_312 or beta_load_2_fu_3170_p1 or ap_sig_cseq_ST_st397_fsm_313 or t_load_3_fu_3175_p1 or gamma_load_3_fu_3180_p1 or ap_sig_cseq_ST_st399_fsm_315 or beta_load_3_fu_3185_p1 or ap_sig_cseq_ST_st400_fsm_316 or t_load_4_fu_3190_p1 or gamma_load_4_fu_3195_p1 or ap_sig_cseq_ST_st402_fsm_318 or beta_load_4_fu_3200_p1 or ap_sig_cseq_ST_st403_fsm_319 or t_load_5_fu_3205_p1 or gamma_load_5_fu_3210_p1 or ap_sig_cseq_ST_st405_fsm_321 or beta_load_5_fu_3215_p1 or ap_sig_cseq_ST_st406_fsm_322 or t_load_6_fu_3220_p1 or gamma_load_6_fu_3225_p1 or ap_sig_cseq_ST_st408_fsm_324 or beta_load_6_fu_3230_p1 or ap_sig_cseq_ST_st409_fsm_325 or t_load_7_fu_3235_p1 or gamma_load_7_fu_3240_p1 or ap_sig_cseq_ST_st411_fsm_327 or beta_load_7_fu_3245_p1 or ap_sig_cseq_ST_st412_fsm_328 or t_load_8_fu_3250_p1 or gamma_load_8_fu_3255_p1 or ap_sig_cseq_ST_st414_fsm_330 or beta_load_8_fu_3260_p1 or ap_sig_cseq_ST_st415_fsm_331 or t_load_9_fu_3265_p1 or gamma_load_9_fu_3270_p1 or ap_sig_cseq_ST_st417_fsm_333 or beta_load_9_fu_3275_p1 or ap_sig_cseq_ST_st418_fsm_334 or t_load_10_fu_3280_p1 or gamma_load_10_fu_3285_p1 or ap_sig_cseq_ST_st420_fsm_336 or beta_load_10_fu_3290_p1 or ap_sig_cseq_ST_st421_fsm_337 or t_load_11_fu_3295_p1 or gamma_load_11_fu_3300_p1 or ap_sig_cseq_ST_st423_fsm_339 or beta_load_11_fu_3305_p1 or ap_sig_cseq_ST_st424_fsm_340 or t_load_12_fu_3310_p1 or gamma_load_12_fu_3315_p1 or ap_sig_cseq_ST_st426_fsm_342 or beta_load_12_fu_3320_p1 or ap_sig_cseq_ST_st427_fsm_343 or t_load_13_fu_3325_p1 or gamma_load_13_fu_3330_p1 or ap_sig_cseq_ST_st429_fsm_345 or beta_load_13_fu_3335_p1 or ap_sig_cseq_ST_st430_fsm_346 or t_load_14_fu_3340_p1 or gamma_load_14_fu_3345_p1 or ap_sig_cseq_ST_st432_fsm_348 or beta_load_14_fu_3350_p1 or ap_sig_cseq_ST_st433_fsm_349 or t_load_15_fu_3355_p1 or gamma_load_15_fu_3360_p1 or ap_sig_cseq_ST_st435_fsm_351 or beta_load_15_fu_3365_p1 or ap_sig_cseq_ST_st436_fsm_352 or t_load_16_fu_3370_p1 or gamma_load_16_fu_3375_p1 or ap_sig_cseq_ST_st438_fsm_354 or beta_load_16_fu_3380_p1 or ap_sig_cseq_ST_st439_fsm_355 or t_load_17_fu_3385_p1 or gamma_load_17_fu_3390_p1 or ap_sig_cseq_ST_st441_fsm_357 or beta_load_17_fu_3395_p1 or ap_sig_cseq_ST_st442_fsm_358 or t_load_18_fu_3400_p1 or gamma_load_18_fu_3405_p1 or ap_sig_cseq_ST_st444_fsm_360 or beta_load_18_fu_3410_p1 or ap_sig_cseq_ST_st445_fsm_361)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st445_fsm_361)) begin
outs_TDATA = beta_load_18_fu_3410_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st444_fsm_360)) begin
outs_TDATA = gamma_load_18_fu_3405_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st443_fsm_359)) begin
outs_TDATA = t_load_18_fu_3400_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st442_fsm_358)) begin
outs_TDATA = beta_load_17_fu_3395_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st441_fsm_357)) begin
outs_TDATA = gamma_load_17_fu_3390_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st440_fsm_356)) begin
outs_TDATA = t_load_17_fu_3385_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st439_fsm_355)) begin
outs_TDATA = beta_load_16_fu_3380_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st438_fsm_354)) begin
outs_TDATA = gamma_load_16_fu_3375_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st437_fsm_353)) begin
outs_TDATA = t_load_16_fu_3370_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st436_fsm_352)) begin
outs_TDATA = beta_load_15_fu_3365_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st435_fsm_351)) begin
outs_TDATA = gamma_load_15_fu_3360_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st434_fsm_350)) begin
outs_TDATA = t_load_15_fu_3355_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st433_fsm_349)) begin
outs_TDATA = beta_load_14_fu_3350_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st432_fsm_348)) begin
outs_TDATA = gamma_load_14_fu_3345_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st431_fsm_347)) begin
outs_TDATA = t_load_14_fu_3340_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st430_fsm_346)) begin
outs_TDATA = beta_load_13_fu_3335_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st429_fsm_345)) begin
outs_TDATA = gamma_load_13_fu_3330_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st428_fsm_344)) begin
outs_TDATA = t_load_13_fu_3325_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st427_fsm_343)) begin
outs_TDATA = beta_load_12_fu_3320_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st426_fsm_342)) begin
outs_TDATA = gamma_load_12_fu_3315_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st425_fsm_341)) begin
outs_TDATA = t_load_12_fu_3310_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st424_fsm_340)) begin
outs_TDATA = beta_load_11_fu_3305_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st423_fsm_339)) begin
outs_TDATA = gamma_load_11_fu_3300_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st422_fsm_338)) begin
outs_TDATA = t_load_11_fu_3295_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st421_fsm_337)) begin
outs_TDATA = beta_load_10_fu_3290_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st420_fsm_336)) begin
outs_TDATA = gamma_load_10_fu_3285_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st419_fsm_335)) begin
outs_TDATA = t_load_10_fu_3280_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st418_fsm_334)) begin
outs_TDATA = beta_load_9_fu_3275_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st417_fsm_333)) begin
outs_TDATA = gamma_load_9_fu_3270_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st416_fsm_332)) begin
outs_TDATA = t_load_9_fu_3265_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st415_fsm_331)) begin
outs_TDATA = beta_load_8_fu_3260_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st414_fsm_330)) begin
outs_TDATA = gamma_load_8_fu_3255_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st413_fsm_329)) begin
outs_TDATA = t_load_8_fu_3250_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st412_fsm_328)) begin
outs_TDATA = beta_load_7_fu_3245_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st411_fsm_327)) begin
outs_TDATA = gamma_load_7_fu_3240_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st410_fsm_326)) begin
outs_TDATA = t_load_7_fu_3235_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st409_fsm_325)) begin
outs_TDATA = beta_load_6_fu_3230_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st408_fsm_324)) begin
outs_TDATA = gamma_load_6_fu_3225_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st407_fsm_323)) begin
outs_TDATA = t_load_6_fu_3220_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st406_fsm_322)) begin
outs_TDATA = beta_load_5_fu_3215_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st405_fsm_321)) begin
outs_TDATA = gamma_load_5_fu_3210_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st404_fsm_320)) begin
outs_TDATA = t_load_5_fu_3205_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st403_fsm_319)) begin
outs_TDATA = beta_load_4_fu_3200_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st402_fsm_318)) begin
outs_TDATA = gamma_load_4_fu_3195_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st401_fsm_317)) begin
outs_TDATA = t_load_4_fu_3190_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st400_fsm_316)) begin
outs_TDATA = beta_load_3_fu_3185_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st399_fsm_315)) begin
outs_TDATA = gamma_load_3_fu_3180_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st398_fsm_314)) begin
outs_TDATA = t_load_3_fu_3175_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st397_fsm_313)) begin
outs_TDATA = beta_load_2_fu_3170_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st396_fsm_312)) begin
outs_TDATA = gamma_load_2_fu_3165_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st395_fsm_311)) begin
outs_TDATA = t_load_2_fu_3160_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st394_fsm_310)) begin
outs_TDATA = beta_load_1_fu_3155_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st393_fsm_309)) begin
outs_TDATA = gamma_load_1_fu_3150_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st392_fsm_308)) begin
outs_TDATA = t_load_1_fu_3145_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st391_fsm_307)) begin
outs_TDATA = beta_load_s_fu_3140_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st390_fsm_306)) begin
outs_TDATA = gamma_load_s_fu_3135_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st389_fsm_305)) begin
outs_TDATA = t_load_s_fu_3130_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st388_fsm_304)) begin
outs_TDATA = beta_load_fu_3125_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st387_fsm_303)) begin
outs_TDATA = gamma_load_fu_3120_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_st386_fsm_302)) begin
outs_TDATA = t_load_fu_3115_p1;
end else begin
outs_TDATA = 'bx;
end
end
/// outs_TLAST assign process. ///
always @ (ap_sig_cseq_ST_st386_fsm_302 or ap_sig_cseq_ST_st389_fsm_305 or ap_sig_cseq_ST_st392_fsm_308 or ap_sig_cseq_ST_st395_fsm_311 or ap_sig_cseq_ST_st398_fsm_314 or ap_sig_cseq_ST_st401_fsm_317 or ap_sig_cseq_ST_st404_fsm_320 or ap_sig_cseq_ST_st407_fsm_323 or ap_sig_cseq_ST_st410_fsm_326 or ap_sig_cseq_ST_st413_fsm_329 or ap_sig_cseq_ST_st416_fsm_332 or ap_sig_cseq_ST_st419_fsm_335 or ap_sig_cseq_ST_st422_fsm_338 or ap_sig_cseq_ST_st425_fsm_341 or ap_sig_cseq_ST_st428_fsm_344 or ap_sig_cseq_ST_st431_fsm_347 or ap_sig_cseq_ST_st434_fsm_350 or ap_sig_cseq_ST_st437_fsm_353 or ap_sig_cseq_ST_st440_fsm_356 or ap_sig_cseq_ST_st443_fsm_359 or ins_last_V_val_reg_3839 or ap_sig_cseq_ST_st387_fsm_303 or ap_sig_cseq_ST_st388_fsm_304 or ap_sig_cseq_ST_st390_fsm_306 or ap_sig_cseq_ST_st391_fsm_307 or ap_sig_cseq_ST_st393_fsm_309 or ap_sig_cseq_ST_st394_fsm_310 or ap_sig_cseq_ST_st396_fsm_312 or ap_sig_cseq_ST_st397_fsm_313 or ap_sig_cseq_ST_st399_fsm_315 or ap_sig_cseq_ST_st400_fsm_316 or ap_sig_cseq_ST_st402_fsm_318 or ap_sig_cseq_ST_st403_fsm_319 or ap_sig_cseq_ST_st405_fsm_321 or ap_sig_cseq_ST_st406_fsm_322 or ap_sig_cseq_ST_st408_fsm_324 or ap_sig_cseq_ST_st409_fsm_325 or ap_sig_cseq_ST_st411_fsm_327 or ap_sig_cseq_ST_st412_fsm_328 or ap_sig_cseq_ST_st414_fsm_330 or ap_sig_cseq_ST_st415_fsm_331 or ap_sig_cseq_ST_st417_fsm_333 or ap_sig_cseq_ST_st418_fsm_334 or ap_sig_cseq_ST_st420_fsm_336 or ap_sig_cseq_ST_st421_fsm_337 or ap_sig_cseq_ST_st423_fsm_339 or ap_sig_cseq_ST_st424_fsm_340 or ap_sig_cseq_ST_st426_fsm_342 or ap_sig_cseq_ST_st427_fsm_343 or ap_sig_cseq_ST_st429_fsm_345 or ap_sig_cseq_ST_st430_fsm_346 or ap_sig_cseq_ST_st432_fsm_348 or ap_sig_cseq_ST_st433_fsm_349 or ap_sig_cseq_ST_st435_fsm_351 or ap_sig_cseq_ST_st436_fsm_352 or ap_sig_cseq_ST_st438_fsm_354 or ap_sig_cseq_ST_st439_fsm_355 or ap_sig_cseq_ST_st441_fsm_357 or ap_sig_cseq_ST_st442_fsm_358 or ap_sig_cseq_ST_st444_fsm_360 or ap_sig_cseq_ST_st445_fsm_361)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st445_fsm_361)) begin
outs_TLAST = ins_last_V_val_reg_3839;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st386_fsm_302) | (ap_const_logic_1 == ap_sig_cseq_ST_st389_fsm_305) | (ap_const_logic_1 == ap_sig_cseq_ST_st392_fsm_308) | (ap_const_logic_1 == ap_sig_cseq_ST_st395_fsm_311) | (ap_const_logic_1 == ap_sig_cseq_ST_st398_fsm_314) | (ap_const_logic_1 == ap_sig_cseq_ST_st401_fsm_317) | (ap_const_logic_1 == ap_sig_cseq_ST_st404_fsm_320) | (ap_const_logic_1 == ap_sig_cseq_ST_st407_fsm_323) | (ap_const_logic_1 == ap_sig_cseq_ST_st410_fsm_326) | (ap_const_logic_1 == ap_sig_cseq_ST_st413_fsm_329) | (ap_const_logic_1 == ap_sig_cseq_ST_st416_fsm_332) | (ap_const_logic_1 == ap_sig_cseq_ST_st419_fsm_335) | (ap_const_logic_1 == ap_sig_cseq_ST_st422_fsm_338) | (ap_const_logic_1 == ap_sig_cseq_ST_st425_fsm_341) | (ap_const_logic_1 == ap_sig_cseq_ST_st428_fsm_344) | (ap_const_logic_1 == ap_sig_cseq_ST_st431_fsm_347) | (ap_const_logic_1 == ap_sig_cseq_ST_st434_fsm_350) | (ap_const_logic_1 == ap_sig_cseq_ST_st437_fsm_353) | (ap_const_logic_1 == ap_sig_cseq_ST_st440_fsm_356) | (ap_const_logic_1 == ap_sig_cseq_ST_st443_fsm_359) | (ap_const_logic_1 == ap_sig_cseq_ST_st387_fsm_303) | (ap_const_logic_1 == ap_sig_cseq_ST_st388_fsm_304) | (ap_const_logic_1 == ap_sig_cseq_ST_st390_fsm_306) | (ap_const_logic_1 == ap_sig_cseq_ST_st391_fsm_307) | (ap_const_logic_1 == ap_sig_cseq_ST_st393_fsm_309) | (ap_const_logic_1 == ap_sig_cseq_ST_st394_fsm_310) | (ap_const_logic_1 == ap_sig_cseq_ST_st396_fsm_312) | (ap_const_logic_1 == ap_sig_cseq_ST_st397_fsm_313) | (ap_const_logic_1 == ap_sig_cseq_ST_st399_fsm_315) | (ap_const_logic_1 == ap_sig_cseq_ST_st400_fsm_316) | (ap_const_logic_1 == ap_sig_cseq_ST_st402_fsm_318) | (ap_const_logic_1 == ap_sig_cseq_ST_st403_fsm_319) | (ap_const_logic_1 == ap_sig_cseq_ST_st405_fsm_321) | (ap_const_logic_1 == ap_sig_cseq_ST_st406_fsm_322) | (ap_const_logic_1 == ap_sig_cseq_ST_st408_fsm_324) | (ap_const_logic_1 == ap_sig_cseq_ST_st409_fsm_325) | (ap_const_logic_1 == ap_sig_cseq_ST_st411_fsm_327) | (ap_const_logic_1 == ap_sig_cseq_ST_st412_fsm_328) | (ap_const_logic_1 == ap_sig_cseq_ST_st414_fsm_330) | (ap_const_logic_1 == ap_sig_cseq_ST_st415_fsm_331) | (ap_const_logic_1 == ap_sig_cseq_ST_st417_fsm_333) | (ap_const_logic_1 == ap_sig_cseq_ST_st418_fsm_334) | (ap_const_logic_1 == ap_sig_cseq_ST_st420_fsm_336) | (ap_const_logic_1 == ap_sig_cseq_ST_st421_fsm_337) | (ap_const_logic_1 == ap_sig_cseq_ST_st423_fsm_339) | (ap_const_logic_1 == ap_sig_cseq_ST_st424_fsm_340) | (ap_const_logic_1 == ap_sig_cseq_ST_st426_fsm_342) | (ap_const_logic_1 == ap_sig_cseq_ST_st427_fsm_343) | (ap_const_logic_1 == ap_sig_cseq_ST_st429_fsm_345) | (ap_const_logic_1 == ap_sig_cseq_ST_st430_fsm_346) | (ap_const_logic_1 == ap_sig_cseq_ST_st432_fsm_348) | (ap_const_logic_1 == ap_sig_cseq_ST_st433_fsm_349) | (ap_const_logic_1 == ap_sig_cseq_ST_st435_fsm_351) | (ap_const_logic_1 == ap_sig_cseq_ST_st436_fsm_352) | (ap_const_logic_1 == ap_sig_cseq_ST_st438_fsm_354) | (ap_const_logic_1 == ap_sig_cseq_ST_st439_fsm_355) | (ap_const_logic_1 == ap_sig_cseq_ST_st441_fsm_357) | (ap_const_logic_1 == ap_sig_cseq_ST_st442_fsm_358) | (ap_const_logic_1 == ap_sig_cseq_ST_st444_fsm_360))) begin
outs_TLAST = ap_const_lv1_0;
end else begin
outs_TLAST = 'bx;
end
end
/// outs_TVALID assign process. ///
always @ (ap_sig_cseq_ST_st386_fsm_302 or ap_sig_cseq_ST_st389_fsm_305 or ap_sig_cseq_ST_st392_fsm_308 or ap_sig_cseq_ST_st395_fsm_311 or ap_sig_cseq_ST_st398_fsm_314 or ap_sig_cseq_ST_st401_fsm_317 or ap_sig_cseq_ST_st404_fsm_320 or ap_sig_cseq_ST_st407_fsm_323 or ap_sig_cseq_ST_st410_fsm_326 or ap_sig_cseq_ST_st413_fsm_329 or ap_sig_cseq_ST_st416_fsm_332 or ap_sig_cseq_ST_st419_fsm_335 or ap_sig_cseq_ST_st422_fsm_338 or ap_sig_cseq_ST_st425_fsm_341 or ap_sig_cseq_ST_st428_fsm_344 or ap_sig_cseq_ST_st431_fsm_347 or ap_sig_cseq_ST_st434_fsm_350 or ap_sig_cseq_ST_st437_fsm_353 or ap_sig_cseq_ST_st440_fsm_356 or ap_sig_cseq_ST_st443_fsm_359 or ap_sig_cseq_ST_st387_fsm_303 or ap_sig_cseq_ST_st388_fsm_304 or ap_sig_cseq_ST_st390_fsm_306 or ap_sig_cseq_ST_st391_fsm_307 or ap_sig_cseq_ST_st393_fsm_309 or ap_sig_cseq_ST_st394_fsm_310 or ap_sig_cseq_ST_st396_fsm_312 or ap_sig_cseq_ST_st397_fsm_313 or ap_sig_cseq_ST_st399_fsm_315 or ap_sig_cseq_ST_st400_fsm_316 or ap_sig_cseq_ST_st402_fsm_318 or ap_sig_cseq_ST_st403_fsm_319 or ap_sig_cseq_ST_st405_fsm_321 or ap_sig_cseq_ST_st406_fsm_322 or ap_sig_cseq_ST_st408_fsm_324 or ap_sig_cseq_ST_st409_fsm_325 or ap_sig_cseq_ST_st411_fsm_327 or ap_sig_cseq_ST_st412_fsm_328 or ap_sig_cseq_ST_st414_fsm_330 or ap_sig_cseq_ST_st415_fsm_331 or ap_sig_cseq_ST_st417_fsm_333 or ap_sig_cseq_ST_st418_fsm_334 or ap_sig_cseq_ST_st420_fsm_336 or ap_sig_cseq_ST_st421_fsm_337 or ap_sig_cseq_ST_st423_fsm_339 or ap_sig_cseq_ST_st424_fsm_340 or ap_sig_cseq_ST_st426_fsm_342 or ap_sig_cseq_ST_st427_fsm_343 or ap_sig_cseq_ST_st429_fsm_345 or ap_sig_cseq_ST_st430_fsm_346 or ap_sig_cseq_ST_st432_fsm_348 or ap_sig_cseq_ST_st433_fsm_349 or ap_sig_cseq_ST_st435_fsm_351 or ap_sig_cseq_ST_st436_fsm_352 or ap_sig_cseq_ST_st438_fsm_354 or ap_sig_cseq_ST_st439_fsm_355 or ap_sig_cseq_ST_st441_fsm_357 or ap_sig_cseq_ST_st442_fsm_358 or ap_sig_cseq_ST_st444_fsm_360 or ap_sig_cseq_ST_st445_fsm_361 or ap_reg_ioackin_outs_TREADY)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st386_fsm_302) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st387_fsm_303) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st388_fsm_304) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st389_fsm_305) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st390_fsm_306) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st391_fsm_307) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st392_fsm_308) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st393_fsm_309) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st394_fsm_310) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st395_fsm_311) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st396_fsm_312) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st397_fsm_313) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st398_fsm_314) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st399_fsm_315) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st400_fsm_316) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st401_fsm_317) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st402_fsm_318) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st403_fsm_319) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st404_fsm_320) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st405_fsm_321) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st406_fsm_322) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st407_fsm_323) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st408_fsm_324) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st409_fsm_325) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st410_fsm_326) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st411_fsm_327) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st412_fsm_328) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st413_fsm_329) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st414_fsm_330) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st415_fsm_331) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st416_fsm_332) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st417_fsm_333) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st418_fsm_334) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st419_fsm_335) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st420_fsm_336) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st421_fsm_337) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st422_fsm_338) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st423_fsm_339) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st424_fsm_340) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st425_fsm_341) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st426_fsm_342) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st427_fsm_343) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st428_fsm_344) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st429_fsm_345) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st430_fsm_346) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st431_fsm_347) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st432_fsm_348) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st433_fsm_349) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st434_fsm_350) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st435_fsm_351) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st436_fsm_352) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st437_fsm_353) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st438_fsm_354) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st439_fsm_355) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st440_fsm_356) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st441_fsm_357) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st442_fsm_358) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st443_fsm_359) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st444_fsm_360) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)) | ((ap_const_logic_1 == ap_sig_cseq_ST_st445_fsm_361) & (ap_const_logic_0 == ap_reg_ioackin_outs_TREADY)))) begin
outs_TVALID = ap_const_logic_1;
end else begin
outs_TVALID = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ins_TVALID or ap_CS_fsm or ap_reg_ppiten_pp0_it0 or ap_reg_ppiten_pp0_it1 or ap_reg_ppiten_pp0_it82 or ap_reg_ppiten_pp0_it83 or ap_sig_ioackin_outs_TREADY or exitcond2_fu_2840_p2)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_st4_fsm_3 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end else begin
ap_NS_fsm = ap_ST_st4_fsm_3;
end
end
ap_ST_st5_fsm_4 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end else begin
ap_NS_fsm = ap_ST_st5_fsm_4;
end
end
ap_ST_st6_fsm_5 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end else begin
ap_NS_fsm = ap_ST_st6_fsm_5;
end
end
ap_ST_st7_fsm_6 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end else begin
ap_NS_fsm = ap_ST_st7_fsm_6;
end
end
ap_ST_st8_fsm_7 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end else begin
ap_NS_fsm = ap_ST_st8_fsm_7;
end
end
ap_ST_st9_fsm_8 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end else begin
ap_NS_fsm = ap_ST_st9_fsm_8;
end
end
ap_ST_st10_fsm_9 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end else begin
ap_NS_fsm = ap_ST_st10_fsm_9;
end
end
ap_ST_st11_fsm_10 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st12_fsm_11;
end else begin
ap_NS_fsm = ap_ST_st11_fsm_10;
end
end
ap_ST_st12_fsm_11 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end else begin
ap_NS_fsm = ap_ST_st12_fsm_11;
end
end
ap_ST_st13_fsm_12 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end else begin
ap_NS_fsm = ap_ST_st13_fsm_12;
end
end
ap_ST_st14_fsm_13 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st15_fsm_14;
end else begin
ap_NS_fsm = ap_ST_st14_fsm_13;
end
end
ap_ST_st15_fsm_14 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st16_fsm_15;
end else begin
ap_NS_fsm = ap_ST_st15_fsm_14;
end
end
ap_ST_st16_fsm_15 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st17_fsm_16;
end else begin
ap_NS_fsm = ap_ST_st16_fsm_15;
end
end
ap_ST_st17_fsm_16 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end else begin
ap_NS_fsm = ap_ST_st17_fsm_16;
end
end
ap_ST_st18_fsm_17 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end else begin
ap_NS_fsm = ap_ST_st18_fsm_17;
end
end
ap_ST_st19_fsm_18 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end else begin
ap_NS_fsm = ap_ST_st19_fsm_18;
end
end
ap_ST_st20_fsm_19 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end else begin
ap_NS_fsm = ap_ST_st20_fsm_19;
end
end
ap_ST_st21_fsm_20 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st22_fsm_21;
end else begin
ap_NS_fsm = ap_ST_st21_fsm_20;
end
end
ap_ST_st22_fsm_21 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st23_fsm_22;
end else begin
ap_NS_fsm = ap_ST_st22_fsm_21;
end
end
ap_ST_st23_fsm_22 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end else begin
ap_NS_fsm = ap_ST_st23_fsm_22;
end
end
ap_ST_st24_fsm_23 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st25_fsm_24;
end else begin
ap_NS_fsm = ap_ST_st24_fsm_23;
end
end
ap_ST_st25_fsm_24 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end else begin
ap_NS_fsm = ap_ST_st25_fsm_24;
end
end
ap_ST_st26_fsm_25 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st27_fsm_26;
end else begin
ap_NS_fsm = ap_ST_st26_fsm_25;
end
end
ap_ST_st27_fsm_26 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st28_fsm_27;
end else begin
ap_NS_fsm = ap_ST_st27_fsm_26;
end
end
ap_ST_st28_fsm_27 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st29_fsm_28;
end else begin
ap_NS_fsm = ap_ST_st28_fsm_27;
end
end
ap_ST_st29_fsm_28 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st30_fsm_29;
end else begin
ap_NS_fsm = ap_ST_st29_fsm_28;
end
end
ap_ST_st30_fsm_29 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st31_fsm_30;
end else begin
ap_NS_fsm = ap_ST_st30_fsm_29;
end
end
ap_ST_st31_fsm_30 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st32_fsm_31;
end else begin
ap_NS_fsm = ap_ST_st31_fsm_30;
end
end
ap_ST_st32_fsm_31 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st33_fsm_32;
end else begin
ap_NS_fsm = ap_ST_st32_fsm_31;
end
end
ap_ST_st33_fsm_32 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st34_fsm_33;
end else begin
ap_NS_fsm = ap_ST_st33_fsm_32;
end
end
ap_ST_st34_fsm_33 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st35_fsm_34;
end else begin
ap_NS_fsm = ap_ST_st34_fsm_33;
end
end
ap_ST_st35_fsm_34 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st36_fsm_35;
end else begin
ap_NS_fsm = ap_ST_st35_fsm_34;
end
end
ap_ST_st36_fsm_35 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end else begin
ap_NS_fsm = ap_ST_st36_fsm_35;
end
end
ap_ST_st37_fsm_36 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st38_fsm_37;
end else begin
ap_NS_fsm = ap_ST_st37_fsm_36;
end
end
ap_ST_st38_fsm_37 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st39_fsm_38;
end else begin
ap_NS_fsm = ap_ST_st38_fsm_37;
end
end
ap_ST_st39_fsm_38 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st40_fsm_39;
end else begin
ap_NS_fsm = ap_ST_st39_fsm_38;
end
end
ap_ST_st40_fsm_39 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st41_fsm_40;
end else begin
ap_NS_fsm = ap_ST_st40_fsm_39;
end
end
ap_ST_st41_fsm_40 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end else begin
ap_NS_fsm = ap_ST_st41_fsm_40;
end
end
ap_ST_st42_fsm_41 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end else begin
ap_NS_fsm = ap_ST_st42_fsm_41;
end
end
ap_ST_st43_fsm_42 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end else begin
ap_NS_fsm = ap_ST_st43_fsm_42;
end
end
ap_ST_st44_fsm_43 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st45_fsm_44;
end else begin
ap_NS_fsm = ap_ST_st44_fsm_43;
end
end
ap_ST_st45_fsm_44 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st46_fsm_45;
end else begin
ap_NS_fsm = ap_ST_st45_fsm_44;
end
end
ap_ST_st46_fsm_45 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st47_fsm_46;
end else begin
ap_NS_fsm = ap_ST_st46_fsm_45;
end
end
ap_ST_st47_fsm_46 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st48_fsm_47;
end else begin
ap_NS_fsm = ap_ST_st47_fsm_46;
end
end
ap_ST_st48_fsm_47 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st49_fsm_48;
end else begin
ap_NS_fsm = ap_ST_st48_fsm_47;
end
end
ap_ST_st49_fsm_48 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st50_fsm_49;
end else begin
ap_NS_fsm = ap_ST_st49_fsm_48;
end
end
ap_ST_st50_fsm_49 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st51_fsm_50;
end else begin
ap_NS_fsm = ap_ST_st50_fsm_49;
end
end
ap_ST_st51_fsm_50 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st52_fsm_51;
end else begin
ap_NS_fsm = ap_ST_st51_fsm_50;
end
end
ap_ST_st52_fsm_51 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st53_fsm_52;
end else begin
ap_NS_fsm = ap_ST_st52_fsm_51;
end
end
ap_ST_st53_fsm_52 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st54_fsm_53;
end else begin
ap_NS_fsm = ap_ST_st53_fsm_52;
end
end
ap_ST_st54_fsm_53 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st55_fsm_54;
end else begin
ap_NS_fsm = ap_ST_st54_fsm_53;
end
end
ap_ST_st55_fsm_54 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st56_fsm_55;
end else begin
ap_NS_fsm = ap_ST_st55_fsm_54;
end
end
ap_ST_st56_fsm_55 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st57_fsm_56;
end else begin
ap_NS_fsm = ap_ST_st56_fsm_55;
end
end
ap_ST_st57_fsm_56 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st58_fsm_57;
end else begin
ap_NS_fsm = ap_ST_st57_fsm_56;
end
end
ap_ST_st58_fsm_57 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st59_fsm_58;
end else begin
ap_NS_fsm = ap_ST_st58_fsm_57;
end
end
ap_ST_st59_fsm_58 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st60_fsm_59;
end else begin
ap_NS_fsm = ap_ST_st59_fsm_58;
end
end
ap_ST_st60_fsm_59 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st61_fsm_60;
end else begin
ap_NS_fsm = ap_ST_st60_fsm_59;
end
end
ap_ST_st61_fsm_60 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st62_fsm_61;
end else begin
ap_NS_fsm = ap_ST_st61_fsm_60;
end
end
ap_ST_st62_fsm_61 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st63_fsm_62;
end else begin
ap_NS_fsm = ap_ST_st62_fsm_61;
end
end
ap_ST_st63_fsm_62 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st64_fsm_63;
end else begin
ap_NS_fsm = ap_ST_st63_fsm_62;
end
end
ap_ST_st64_fsm_63 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st65_fsm_64;
end else begin
ap_NS_fsm = ap_ST_st64_fsm_63;
end
end
ap_ST_st65_fsm_64 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st66_fsm_65;
end else begin
ap_NS_fsm = ap_ST_st65_fsm_64;
end
end
ap_ST_st66_fsm_65 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st67_fsm_66;
end else begin
ap_NS_fsm = ap_ST_st66_fsm_65;
end
end
ap_ST_st67_fsm_66 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st68_fsm_67;
end else begin
ap_NS_fsm = ap_ST_st67_fsm_66;
end
end
ap_ST_st68_fsm_67 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st69_fsm_68;
end else begin
ap_NS_fsm = ap_ST_st68_fsm_67;
end
end
ap_ST_st69_fsm_68 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st70_fsm_69;
end else begin
ap_NS_fsm = ap_ST_st69_fsm_68;
end
end
ap_ST_st70_fsm_69 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st71_fsm_70;
end else begin
ap_NS_fsm = ap_ST_st70_fsm_69;
end
end
ap_ST_st71_fsm_70 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st72_fsm_71;
end else begin
ap_NS_fsm = ap_ST_st71_fsm_70;
end
end
ap_ST_st72_fsm_71 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st73_fsm_72;
end else begin
ap_NS_fsm = ap_ST_st72_fsm_71;
end
end
ap_ST_st73_fsm_72 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st74_fsm_73;
end else begin
ap_NS_fsm = ap_ST_st73_fsm_72;
end
end
ap_ST_st74_fsm_73 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st75_fsm_74;
end else begin
ap_NS_fsm = ap_ST_st74_fsm_73;
end
end
ap_ST_st75_fsm_74 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st76_fsm_75;
end else begin
ap_NS_fsm = ap_ST_st75_fsm_74;
end
end
ap_ST_st76_fsm_75 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st77_fsm_76;
end else begin
ap_NS_fsm = ap_ST_st76_fsm_75;
end
end
ap_ST_st77_fsm_76 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st78_fsm_77;
end else begin
ap_NS_fsm = ap_ST_st77_fsm_76;
end
end
ap_ST_st78_fsm_77 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st79_fsm_78;
end else begin
ap_NS_fsm = ap_ST_st78_fsm_77;
end
end
ap_ST_st79_fsm_78 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st80_fsm_79;
end else begin
ap_NS_fsm = ap_ST_st79_fsm_78;
end
end
ap_ST_st80_fsm_79 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st81_fsm_80;
end else begin
ap_NS_fsm = ap_ST_st80_fsm_79;
end
end
ap_ST_st81_fsm_80 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st82_fsm_81;
end else begin
ap_NS_fsm = ap_ST_st81_fsm_80;
end
end
ap_ST_st82_fsm_81 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st83_fsm_82;
end else begin
ap_NS_fsm = ap_ST_st82_fsm_81;
end
end
ap_ST_st83_fsm_82 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st84_fsm_83;
end else begin
ap_NS_fsm = ap_ST_st83_fsm_82;
end
end
ap_ST_st84_fsm_83 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st85_fsm_84;
end else begin
ap_NS_fsm = ap_ST_st84_fsm_83;
end
end
ap_ST_st85_fsm_84 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st86_fsm_85;
end else begin
ap_NS_fsm = ap_ST_st85_fsm_84;
end
end
ap_ST_st86_fsm_85 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st87_fsm_86;
end else begin
ap_NS_fsm = ap_ST_st86_fsm_85;
end
end
ap_ST_st87_fsm_86 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st88_fsm_87;
end else begin
ap_NS_fsm = ap_ST_st87_fsm_86;
end
end
ap_ST_st88_fsm_87 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st89_fsm_88;
end else begin
ap_NS_fsm = ap_ST_st88_fsm_87;
end
end
ap_ST_st89_fsm_88 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st90_fsm_89;
end else begin
ap_NS_fsm = ap_ST_st89_fsm_88;
end
end
ap_ST_st90_fsm_89 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st91_fsm_90;
end else begin
ap_NS_fsm = ap_ST_st90_fsm_89;
end
end
ap_ST_st91_fsm_90 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st92_fsm_91;
end else begin
ap_NS_fsm = ap_ST_st91_fsm_90;
end
end
ap_ST_st92_fsm_91 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st93_fsm_92;
end else begin
ap_NS_fsm = ap_ST_st92_fsm_91;
end
end
ap_ST_st93_fsm_92 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st94_fsm_93;
end else begin
ap_NS_fsm = ap_ST_st93_fsm_92;
end
end
ap_ST_st94_fsm_93 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st95_fsm_94;
end else begin
ap_NS_fsm = ap_ST_st94_fsm_93;
end
end
ap_ST_st95_fsm_94 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st96_fsm_95;
end else begin
ap_NS_fsm = ap_ST_st95_fsm_94;
end
end
ap_ST_st96_fsm_95 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st97_fsm_96;
end else begin
ap_NS_fsm = ap_ST_st96_fsm_95;
end
end
ap_ST_st97_fsm_96 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st98_fsm_97;
end else begin
ap_NS_fsm = ap_ST_st97_fsm_96;
end
end
ap_ST_st98_fsm_97 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st99_fsm_98;
end else begin
ap_NS_fsm = ap_ST_st98_fsm_97;
end
end
ap_ST_st99_fsm_98 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st100_fsm_99;
end else begin
ap_NS_fsm = ap_ST_st99_fsm_98;
end
end
ap_ST_st100_fsm_99 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st101_fsm_100;
end else begin
ap_NS_fsm = ap_ST_st100_fsm_99;
end
end
ap_ST_st101_fsm_100 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st102_fsm_101;
end else begin
ap_NS_fsm = ap_ST_st101_fsm_100;
end
end
ap_ST_st102_fsm_101 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st103_fsm_102;
end else begin
ap_NS_fsm = ap_ST_st102_fsm_101;
end
end
ap_ST_st103_fsm_102 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st104_fsm_103;
end else begin
ap_NS_fsm = ap_ST_st103_fsm_102;
end
end
ap_ST_st104_fsm_103 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st105_fsm_104;
end else begin
ap_NS_fsm = ap_ST_st104_fsm_103;
end
end
ap_ST_st105_fsm_104 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st106_fsm_105;
end else begin
ap_NS_fsm = ap_ST_st105_fsm_104;
end
end
ap_ST_st106_fsm_105 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st107_fsm_106;
end else begin
ap_NS_fsm = ap_ST_st106_fsm_105;
end
end
ap_ST_st107_fsm_106 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st108_fsm_107;
end else begin
ap_NS_fsm = ap_ST_st107_fsm_106;
end
end
ap_ST_st108_fsm_107 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st109_fsm_108;
end else begin
ap_NS_fsm = ap_ST_st108_fsm_107;
end
end
ap_ST_st109_fsm_108 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st110_fsm_109;
end else begin
ap_NS_fsm = ap_ST_st109_fsm_108;
end
end
ap_ST_st110_fsm_109 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st111_fsm_110;
end else begin
ap_NS_fsm = ap_ST_st110_fsm_109;
end
end
ap_ST_st111_fsm_110 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st112_fsm_111;
end else begin
ap_NS_fsm = ap_ST_st111_fsm_110;
end
end
ap_ST_st112_fsm_111 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st113_fsm_112;
end else begin
ap_NS_fsm = ap_ST_st112_fsm_111;
end
end
ap_ST_st113_fsm_112 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st114_fsm_113;
end else begin
ap_NS_fsm = ap_ST_st113_fsm_112;
end
end
ap_ST_st114_fsm_113 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st115_fsm_114;
end else begin
ap_NS_fsm = ap_ST_st114_fsm_113;
end
end
ap_ST_st115_fsm_114 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st116_fsm_115;
end else begin
ap_NS_fsm = ap_ST_st115_fsm_114;
end
end
ap_ST_st116_fsm_115 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st117_fsm_116;
end else begin
ap_NS_fsm = ap_ST_st116_fsm_115;
end
end
ap_ST_st117_fsm_116 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st118_fsm_117;
end else begin
ap_NS_fsm = ap_ST_st117_fsm_116;
end
end
ap_ST_st118_fsm_117 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st119_fsm_118;
end else begin
ap_NS_fsm = ap_ST_st118_fsm_117;
end
end
ap_ST_st119_fsm_118 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st120_fsm_119;
end else begin
ap_NS_fsm = ap_ST_st119_fsm_118;
end
end
ap_ST_st120_fsm_119 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st121_fsm_120;
end else begin
ap_NS_fsm = ap_ST_st120_fsm_119;
end
end
ap_ST_st121_fsm_120 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st122_fsm_121;
end else begin
ap_NS_fsm = ap_ST_st121_fsm_120;
end
end
ap_ST_st122_fsm_121 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st123_fsm_122;
end else begin
ap_NS_fsm = ap_ST_st122_fsm_121;
end
end
ap_ST_st123_fsm_122 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st124_fsm_123;
end else begin
ap_NS_fsm = ap_ST_st123_fsm_122;
end
end
ap_ST_st124_fsm_123 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st125_fsm_124;
end else begin
ap_NS_fsm = ap_ST_st124_fsm_123;
end
end
ap_ST_st125_fsm_124 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st126_fsm_125;
end else begin
ap_NS_fsm = ap_ST_st125_fsm_124;
end
end
ap_ST_st126_fsm_125 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st127_fsm_126;
end else begin
ap_NS_fsm = ap_ST_st126_fsm_125;
end
end
ap_ST_st127_fsm_126 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st128_fsm_127;
end else begin
ap_NS_fsm = ap_ST_st127_fsm_126;
end
end
ap_ST_st128_fsm_127 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st129_fsm_128;
end else begin
ap_NS_fsm = ap_ST_st128_fsm_127;
end
end
ap_ST_st129_fsm_128 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st130_fsm_129;
end else begin
ap_NS_fsm = ap_ST_st129_fsm_128;
end
end
ap_ST_st130_fsm_129 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st131_fsm_130;
end else begin
ap_NS_fsm = ap_ST_st130_fsm_129;
end
end
ap_ST_st131_fsm_130 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st132_fsm_131;
end else begin
ap_NS_fsm = ap_ST_st131_fsm_130;
end
end
ap_ST_st132_fsm_131 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st133_fsm_132;
end else begin
ap_NS_fsm = ap_ST_st132_fsm_131;
end
end
ap_ST_st133_fsm_132 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st134_fsm_133;
end else begin
ap_NS_fsm = ap_ST_st133_fsm_132;
end
end
ap_ST_st134_fsm_133 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st135_fsm_134;
end else begin
ap_NS_fsm = ap_ST_st134_fsm_133;
end
end
ap_ST_st135_fsm_134 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st136_fsm_135;
end else begin
ap_NS_fsm = ap_ST_st135_fsm_134;
end
end
ap_ST_st136_fsm_135 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st137_fsm_136;
end else begin
ap_NS_fsm = ap_ST_st136_fsm_135;
end
end
ap_ST_st137_fsm_136 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st138_fsm_137;
end else begin
ap_NS_fsm = ap_ST_st137_fsm_136;
end
end
ap_ST_st138_fsm_137 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end else begin
ap_NS_fsm = ap_ST_st138_fsm_137;
end
end
ap_ST_st139_fsm_138 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st140_fsm_139;
end else begin
ap_NS_fsm = ap_ST_st139_fsm_138;
end
end
ap_ST_st140_fsm_139 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st141_fsm_140;
end else begin
ap_NS_fsm = ap_ST_st140_fsm_139;
end
end
ap_ST_st141_fsm_140 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st142_fsm_141;
end else begin
ap_NS_fsm = ap_ST_st141_fsm_140;
end
end
ap_ST_st142_fsm_141 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st143_fsm_142;
end else begin
ap_NS_fsm = ap_ST_st142_fsm_141;
end
end
ap_ST_st143_fsm_142 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st144_fsm_143;
end else begin
ap_NS_fsm = ap_ST_st143_fsm_142;
end
end
ap_ST_st144_fsm_143 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st145_fsm_144;
end else begin
ap_NS_fsm = ap_ST_st144_fsm_143;
end
end
ap_ST_st145_fsm_144 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st146_fsm_145;
end else begin
ap_NS_fsm = ap_ST_st145_fsm_144;
end
end
ap_ST_st146_fsm_145 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st147_fsm_146;
end else begin
ap_NS_fsm = ap_ST_st146_fsm_145;
end
end
ap_ST_st147_fsm_146 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st148_fsm_147;
end else begin
ap_NS_fsm = ap_ST_st147_fsm_146;
end
end
ap_ST_st148_fsm_147 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st149_fsm_148;
end else begin
ap_NS_fsm = ap_ST_st148_fsm_147;
end
end
ap_ST_st149_fsm_148 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st150_fsm_149;
end else begin
ap_NS_fsm = ap_ST_st149_fsm_148;
end
end
ap_ST_st150_fsm_149 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st151_fsm_150;
end else begin
ap_NS_fsm = ap_ST_st150_fsm_149;
end
end
ap_ST_st151_fsm_150 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st152_fsm_151;
end else begin
ap_NS_fsm = ap_ST_st151_fsm_150;
end
end
ap_ST_st152_fsm_151 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st153_fsm_152;
end else begin
ap_NS_fsm = ap_ST_st152_fsm_151;
end
end
ap_ST_st153_fsm_152 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st154_fsm_153;
end else begin
ap_NS_fsm = ap_ST_st153_fsm_152;
end
end
ap_ST_st154_fsm_153 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st155_fsm_154;
end else begin
ap_NS_fsm = ap_ST_st154_fsm_153;
end
end
ap_ST_st155_fsm_154 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st156_fsm_155;
end else begin
ap_NS_fsm = ap_ST_st155_fsm_154;
end
end
ap_ST_st156_fsm_155 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st157_fsm_156;
end else begin
ap_NS_fsm = ap_ST_st156_fsm_155;
end
end
ap_ST_st157_fsm_156 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st158_fsm_157;
end else begin
ap_NS_fsm = ap_ST_st157_fsm_156;
end
end
ap_ST_st158_fsm_157 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st159_fsm_158;
end else begin
ap_NS_fsm = ap_ST_st158_fsm_157;
end
end
ap_ST_st159_fsm_158 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st160_fsm_159;
end else begin
ap_NS_fsm = ap_ST_st159_fsm_158;
end
end
ap_ST_st160_fsm_159 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st161_fsm_160;
end else begin
ap_NS_fsm = ap_ST_st160_fsm_159;
end
end
ap_ST_st161_fsm_160 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st162_fsm_161;
end else begin
ap_NS_fsm = ap_ST_st161_fsm_160;
end
end
ap_ST_st162_fsm_161 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st163_fsm_162;
end else begin
ap_NS_fsm = ap_ST_st162_fsm_161;
end
end
ap_ST_st163_fsm_162 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st164_fsm_163;
end else begin
ap_NS_fsm = ap_ST_st163_fsm_162;
end
end
ap_ST_st164_fsm_163 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st165_fsm_164;
end else begin
ap_NS_fsm = ap_ST_st164_fsm_163;
end
end
ap_ST_st165_fsm_164 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st166_fsm_165;
end else begin
ap_NS_fsm = ap_ST_st165_fsm_164;
end
end
ap_ST_st166_fsm_165 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st167_fsm_166;
end else begin
ap_NS_fsm = ap_ST_st166_fsm_165;
end
end
ap_ST_st167_fsm_166 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st168_fsm_167;
end else begin
ap_NS_fsm = ap_ST_st167_fsm_166;
end
end
ap_ST_st168_fsm_167 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st169_fsm_168;
end else begin
ap_NS_fsm = ap_ST_st168_fsm_167;
end
end
ap_ST_st169_fsm_168 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st170_fsm_169;
end else begin
ap_NS_fsm = ap_ST_st169_fsm_168;
end
end
ap_ST_st170_fsm_169 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st171_fsm_170;
end else begin
ap_NS_fsm = ap_ST_st170_fsm_169;
end
end
ap_ST_st171_fsm_170 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st172_fsm_171;
end else begin
ap_NS_fsm = ap_ST_st171_fsm_170;
end
end
ap_ST_st172_fsm_171 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st173_fsm_172;
end else begin
ap_NS_fsm = ap_ST_st172_fsm_171;
end
end
ap_ST_st173_fsm_172 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st174_fsm_173;
end else begin
ap_NS_fsm = ap_ST_st173_fsm_172;
end
end
ap_ST_st174_fsm_173 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st175_fsm_174;
end else begin
ap_NS_fsm = ap_ST_st174_fsm_173;
end
end
ap_ST_st175_fsm_174 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st176_fsm_175;
end else begin
ap_NS_fsm = ap_ST_st175_fsm_174;
end
end
ap_ST_st176_fsm_175 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st177_fsm_176;
end else begin
ap_NS_fsm = ap_ST_st176_fsm_175;
end
end
ap_ST_st177_fsm_176 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st178_fsm_177;
end else begin
ap_NS_fsm = ap_ST_st177_fsm_176;
end
end
ap_ST_st178_fsm_177 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st179_fsm_178;
end else begin
ap_NS_fsm = ap_ST_st178_fsm_177;
end
end
ap_ST_st179_fsm_178 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st180_fsm_179;
end else begin
ap_NS_fsm = ap_ST_st179_fsm_178;
end
end
ap_ST_st180_fsm_179 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st181_fsm_180;
end else begin
ap_NS_fsm = ap_ST_st180_fsm_179;
end
end
ap_ST_st181_fsm_180 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st182_fsm_181;
end else begin
ap_NS_fsm = ap_ST_st181_fsm_180;
end
end
ap_ST_st182_fsm_181 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st183_fsm_182;
end else begin
ap_NS_fsm = ap_ST_st182_fsm_181;
end
end
ap_ST_st183_fsm_182 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st184_fsm_183;
end else begin
ap_NS_fsm = ap_ST_st183_fsm_182;
end
end
ap_ST_st184_fsm_183 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st185_fsm_184;
end else begin
ap_NS_fsm = ap_ST_st184_fsm_183;
end
end
ap_ST_st185_fsm_184 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st186_fsm_185;
end else begin
ap_NS_fsm = ap_ST_st185_fsm_184;
end
end
ap_ST_st186_fsm_185 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st187_fsm_186;
end else begin
ap_NS_fsm = ap_ST_st186_fsm_185;
end
end
ap_ST_st187_fsm_186 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st188_fsm_187;
end else begin
ap_NS_fsm = ap_ST_st187_fsm_186;
end
end
ap_ST_st188_fsm_187 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st189_fsm_188;
end else begin
ap_NS_fsm = ap_ST_st188_fsm_187;
end
end
ap_ST_st189_fsm_188 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st190_fsm_189;
end else begin
ap_NS_fsm = ap_ST_st189_fsm_188;
end
end
ap_ST_st190_fsm_189 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st191_fsm_190;
end else begin
ap_NS_fsm = ap_ST_st190_fsm_189;
end
end
ap_ST_st191_fsm_190 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st192_fsm_191;
end else begin
ap_NS_fsm = ap_ST_st191_fsm_190;
end
end
ap_ST_st192_fsm_191 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st193_fsm_192;
end else begin
ap_NS_fsm = ap_ST_st192_fsm_191;
end
end
ap_ST_st193_fsm_192 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st194_fsm_193;
end else begin
ap_NS_fsm = ap_ST_st193_fsm_192;
end
end
ap_ST_st194_fsm_193 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st195_fsm_194;
end else begin
ap_NS_fsm = ap_ST_st194_fsm_193;
end
end
ap_ST_st195_fsm_194 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st196_fsm_195;
end else begin
ap_NS_fsm = ap_ST_st195_fsm_194;
end
end
ap_ST_st196_fsm_195 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st197_fsm_196;
end else begin
ap_NS_fsm = ap_ST_st196_fsm_195;
end
end
ap_ST_st197_fsm_196 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st198_fsm_197;
end else begin
ap_NS_fsm = ap_ST_st197_fsm_196;
end
end
ap_ST_st198_fsm_197 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st199_fsm_198;
end else begin
ap_NS_fsm = ap_ST_st198_fsm_197;
end
end
ap_ST_st199_fsm_198 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st200_fsm_199;
end else begin
ap_NS_fsm = ap_ST_st199_fsm_198;
end
end
ap_ST_st200_fsm_199 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st201_fsm_200;
end else begin
ap_NS_fsm = ap_ST_st200_fsm_199;
end
end
ap_ST_st201_fsm_200 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st202_fsm_201;
end else begin
ap_NS_fsm = ap_ST_st201_fsm_200;
end
end
ap_ST_st202_fsm_201 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st203_fsm_202;
end else begin
ap_NS_fsm = ap_ST_st202_fsm_201;
end
end
ap_ST_st203_fsm_202 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st204_fsm_203;
end else begin
ap_NS_fsm = ap_ST_st203_fsm_202;
end
end
ap_ST_st204_fsm_203 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st205_fsm_204;
end else begin
ap_NS_fsm = ap_ST_st204_fsm_203;
end
end
ap_ST_st205_fsm_204 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st206_fsm_205;
end else begin
ap_NS_fsm = ap_ST_st205_fsm_204;
end
end
ap_ST_st206_fsm_205 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st207_fsm_206;
end else begin
ap_NS_fsm = ap_ST_st206_fsm_205;
end
end
ap_ST_st207_fsm_206 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st208_fsm_207;
end else begin
ap_NS_fsm = ap_ST_st207_fsm_206;
end
end
ap_ST_st208_fsm_207 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st209_fsm_208;
end else begin
ap_NS_fsm = ap_ST_st208_fsm_207;
end
end
ap_ST_st209_fsm_208 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st210_fsm_209;
end else begin
ap_NS_fsm = ap_ST_st209_fsm_208;
end
end
ap_ST_st210_fsm_209 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st211_fsm_210;
end else begin
ap_NS_fsm = ap_ST_st210_fsm_209;
end
end
ap_ST_st211_fsm_210 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st212_fsm_211;
end else begin
ap_NS_fsm = ap_ST_st211_fsm_210;
end
end
ap_ST_st212_fsm_211 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st213_fsm_212;
end else begin
ap_NS_fsm = ap_ST_st212_fsm_211;
end
end
ap_ST_st213_fsm_212 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st214_fsm_213;
end else begin
ap_NS_fsm = ap_ST_st213_fsm_212;
end
end
ap_ST_st214_fsm_213 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st215_fsm_214;
end else begin
ap_NS_fsm = ap_ST_st214_fsm_213;
end
end
ap_ST_st215_fsm_214 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st216_fsm_215;
end else begin
ap_NS_fsm = ap_ST_st215_fsm_214;
end
end
ap_ST_st216_fsm_215 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st217_fsm_216;
end else begin
ap_NS_fsm = ap_ST_st216_fsm_215;
end
end
ap_ST_st217_fsm_216 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st218_fsm_217;
end else begin
ap_NS_fsm = ap_ST_st217_fsm_216;
end
end
ap_ST_st218_fsm_217 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st219_fsm_218;
end else begin
ap_NS_fsm = ap_ST_st218_fsm_217;
end
end
ap_ST_st219_fsm_218 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st220_fsm_219;
end else begin
ap_NS_fsm = ap_ST_st219_fsm_218;
end
end
ap_ST_st220_fsm_219 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st221_fsm_220;
end else begin
ap_NS_fsm = ap_ST_st220_fsm_219;
end
end
ap_ST_st221_fsm_220 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st222_fsm_221;
end else begin
ap_NS_fsm = ap_ST_st221_fsm_220;
end
end
ap_ST_st222_fsm_221 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st223_fsm_222;
end else begin
ap_NS_fsm = ap_ST_st222_fsm_221;
end
end
ap_ST_st223_fsm_222 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st224_fsm_223;
end else begin
ap_NS_fsm = ap_ST_st223_fsm_222;
end
end
ap_ST_st224_fsm_223 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st225_fsm_224;
end else begin
ap_NS_fsm = ap_ST_st224_fsm_223;
end
end
ap_ST_st225_fsm_224 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st226_fsm_225;
end else begin
ap_NS_fsm = ap_ST_st225_fsm_224;
end
end
ap_ST_st226_fsm_225 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st227_fsm_226;
end else begin
ap_NS_fsm = ap_ST_st226_fsm_225;
end
end
ap_ST_st227_fsm_226 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st228_fsm_227;
end else begin
ap_NS_fsm = ap_ST_st227_fsm_226;
end
end
ap_ST_st228_fsm_227 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st229_fsm_228;
end else begin
ap_NS_fsm = ap_ST_st228_fsm_227;
end
end
ap_ST_st229_fsm_228 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st230_fsm_229;
end else begin
ap_NS_fsm = ap_ST_st229_fsm_228;
end
end
ap_ST_st230_fsm_229 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st231_fsm_230;
end else begin
ap_NS_fsm = ap_ST_st230_fsm_229;
end
end
ap_ST_st231_fsm_230 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st232_fsm_231;
end else begin
ap_NS_fsm = ap_ST_st231_fsm_230;
end
end
ap_ST_st232_fsm_231 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st233_fsm_232;
end else begin
ap_NS_fsm = ap_ST_st232_fsm_231;
end
end
ap_ST_st233_fsm_232 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st234_fsm_233;
end else begin
ap_NS_fsm = ap_ST_st233_fsm_232;
end
end
ap_ST_st234_fsm_233 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st235_fsm_234;
end else begin
ap_NS_fsm = ap_ST_st234_fsm_233;
end
end
ap_ST_st235_fsm_234 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st236_fsm_235;
end else begin
ap_NS_fsm = ap_ST_st235_fsm_234;
end
end
ap_ST_st236_fsm_235 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st237_fsm_236;
end else begin
ap_NS_fsm = ap_ST_st236_fsm_235;
end
end
ap_ST_st237_fsm_236 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st238_fsm_237;
end else begin
ap_NS_fsm = ap_ST_st237_fsm_236;
end
end
ap_ST_st238_fsm_237 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st239_fsm_238;
end else begin
ap_NS_fsm = ap_ST_st238_fsm_237;
end
end
ap_ST_st239_fsm_238 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st240_fsm_239;
end else begin
ap_NS_fsm = ap_ST_st239_fsm_238;
end
end
ap_ST_st240_fsm_239 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st241_fsm_240;
end else begin
ap_NS_fsm = ap_ST_st240_fsm_239;
end
end
ap_ST_st241_fsm_240 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st242_fsm_241;
end else begin
ap_NS_fsm = ap_ST_st241_fsm_240;
end
end
ap_ST_st242_fsm_241 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st243_fsm_242;
end else begin
ap_NS_fsm = ap_ST_st242_fsm_241;
end
end
ap_ST_st243_fsm_242 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st244_fsm_243;
end else begin
ap_NS_fsm = ap_ST_st243_fsm_242;
end
end
ap_ST_st244_fsm_243 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st245_fsm_244;
end else begin
ap_NS_fsm = ap_ST_st244_fsm_243;
end
end
ap_ST_st245_fsm_244 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st246_fsm_245;
end else begin
ap_NS_fsm = ap_ST_st245_fsm_244;
end
end
ap_ST_st246_fsm_245 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st247_fsm_246;
end else begin
ap_NS_fsm = ap_ST_st246_fsm_245;
end
end
ap_ST_st247_fsm_246 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st248_fsm_247;
end else begin
ap_NS_fsm = ap_ST_st247_fsm_246;
end
end
ap_ST_st248_fsm_247 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st249_fsm_248;
end else begin
ap_NS_fsm = ap_ST_st248_fsm_247;
end
end
ap_ST_st249_fsm_248 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st250_fsm_249;
end else begin
ap_NS_fsm = ap_ST_st249_fsm_248;
end
end
ap_ST_st250_fsm_249 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st251_fsm_250;
end else begin
ap_NS_fsm = ap_ST_st250_fsm_249;
end
end
ap_ST_st251_fsm_250 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st252_fsm_251;
end else begin
ap_NS_fsm = ap_ST_st251_fsm_250;
end
end
ap_ST_st252_fsm_251 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st253_fsm_252;
end else begin
ap_NS_fsm = ap_ST_st252_fsm_251;
end
end
ap_ST_st253_fsm_252 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st254_fsm_253;
end else begin
ap_NS_fsm = ap_ST_st253_fsm_252;
end
end
ap_ST_st254_fsm_253 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st255_fsm_254;
end else begin
ap_NS_fsm = ap_ST_st254_fsm_253;
end
end
ap_ST_st255_fsm_254 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st256_fsm_255;
end else begin
ap_NS_fsm = ap_ST_st255_fsm_254;
end
end
ap_ST_st256_fsm_255 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st257_fsm_256;
end else begin
ap_NS_fsm = ap_ST_st256_fsm_255;
end
end
ap_ST_st257_fsm_256 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st258_fsm_257;
end else begin
ap_NS_fsm = ap_ST_st257_fsm_256;
end
end
ap_ST_st258_fsm_257 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st259_fsm_258;
end else begin
ap_NS_fsm = ap_ST_st258_fsm_257;
end
end
ap_ST_st259_fsm_258 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st260_fsm_259;
end else begin
ap_NS_fsm = ap_ST_st259_fsm_258;
end
end
ap_ST_st260_fsm_259 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st261_fsm_260;
end else begin
ap_NS_fsm = ap_ST_st260_fsm_259;
end
end
ap_ST_st261_fsm_260 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st262_fsm_261;
end else begin
ap_NS_fsm = ap_ST_st261_fsm_260;
end
end
ap_ST_st262_fsm_261 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st263_fsm_262;
end else begin
ap_NS_fsm = ap_ST_st262_fsm_261;
end
end
ap_ST_st263_fsm_262 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st264_fsm_263;
end else begin
ap_NS_fsm = ap_ST_st263_fsm_262;
end
end
ap_ST_st264_fsm_263 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st265_fsm_264;
end else begin
ap_NS_fsm = ap_ST_st264_fsm_263;
end
end
ap_ST_st265_fsm_264 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st266_fsm_265;
end else begin
ap_NS_fsm = ap_ST_st265_fsm_264;
end
end
ap_ST_st266_fsm_265 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st267_fsm_266;
end else begin
ap_NS_fsm = ap_ST_st266_fsm_265;
end
end
ap_ST_st267_fsm_266 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st268_fsm_267;
end else begin
ap_NS_fsm = ap_ST_st267_fsm_266;
end
end
ap_ST_st268_fsm_267 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st269_fsm_268;
end else begin
ap_NS_fsm = ap_ST_st268_fsm_267;
end
end
ap_ST_st269_fsm_268 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st270_fsm_269;
end else begin
ap_NS_fsm = ap_ST_st269_fsm_268;
end
end
ap_ST_st270_fsm_269 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st271_fsm_270;
end else begin
ap_NS_fsm = ap_ST_st270_fsm_269;
end
end
ap_ST_st271_fsm_270 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st272_fsm_271;
end else begin
ap_NS_fsm = ap_ST_st271_fsm_270;
end
end
ap_ST_st272_fsm_271 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st273_fsm_272;
end else begin
ap_NS_fsm = ap_ST_st272_fsm_271;
end
end
ap_ST_st273_fsm_272 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st274_fsm_273;
end else begin
ap_NS_fsm = ap_ST_st273_fsm_272;
end
end
ap_ST_st274_fsm_273 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st275_fsm_274;
end else begin
ap_NS_fsm = ap_ST_st274_fsm_273;
end
end
ap_ST_st275_fsm_274 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st276_fsm_275;
end else begin
ap_NS_fsm = ap_ST_st275_fsm_274;
end
end
ap_ST_st276_fsm_275 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st277_fsm_276;
end else begin
ap_NS_fsm = ap_ST_st276_fsm_275;
end
end
ap_ST_st277_fsm_276 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st278_fsm_277;
end else begin
ap_NS_fsm = ap_ST_st277_fsm_276;
end
end
ap_ST_st278_fsm_277 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st279_fsm_278;
end else begin
ap_NS_fsm = ap_ST_st278_fsm_277;
end
end
ap_ST_st279_fsm_278 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st280_fsm_279;
end else begin
ap_NS_fsm = ap_ST_st279_fsm_278;
end
end
ap_ST_st280_fsm_279 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st281_fsm_280;
end else begin
ap_NS_fsm = ap_ST_st280_fsm_279;
end
end
ap_ST_st281_fsm_280 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st282_fsm_281;
end else begin
ap_NS_fsm = ap_ST_st281_fsm_280;
end
end
ap_ST_st282_fsm_281 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st283_fsm_282;
end else begin
ap_NS_fsm = ap_ST_st282_fsm_281;
end
end
ap_ST_st283_fsm_282 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st284_fsm_283;
end else begin
ap_NS_fsm = ap_ST_st283_fsm_282;
end
end
ap_ST_st284_fsm_283 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st285_fsm_284;
end else begin
ap_NS_fsm = ap_ST_st284_fsm_283;
end
end
ap_ST_st285_fsm_284 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st286_fsm_285;
end else begin
ap_NS_fsm = ap_ST_st285_fsm_284;
end
end
ap_ST_st286_fsm_285 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st287_fsm_286;
end else begin
ap_NS_fsm = ap_ST_st286_fsm_285;
end
end
ap_ST_st287_fsm_286 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st288_fsm_287;
end else begin
ap_NS_fsm = ap_ST_st287_fsm_286;
end
end
ap_ST_st288_fsm_287 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st289_fsm_288;
end else begin
ap_NS_fsm = ap_ST_st288_fsm_287;
end
end
ap_ST_st289_fsm_288 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st290_fsm_289;
end else begin
ap_NS_fsm = ap_ST_st289_fsm_288;
end
end
ap_ST_st290_fsm_289 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st291_fsm_290;
end else begin
ap_NS_fsm = ap_ST_st290_fsm_289;
end
end
ap_ST_st291_fsm_290 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st292_fsm_291;
end else begin
ap_NS_fsm = ap_ST_st291_fsm_290;
end
end
ap_ST_st292_fsm_291 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st293_fsm_292;
end else begin
ap_NS_fsm = ap_ST_st292_fsm_291;
end
end
ap_ST_st293_fsm_292 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st294_fsm_293;
end else begin
ap_NS_fsm = ap_ST_st293_fsm_292;
end
end
ap_ST_st294_fsm_293 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st295_fsm_294;
end else begin
ap_NS_fsm = ap_ST_st294_fsm_293;
end
end
ap_ST_st295_fsm_294 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st296_fsm_295;
end else begin
ap_NS_fsm = ap_ST_st295_fsm_294;
end
end
ap_ST_st296_fsm_295 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st297_fsm_296;
end else begin
ap_NS_fsm = ap_ST_st296_fsm_295;
end
end
ap_ST_st297_fsm_296 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st298_fsm_297;
end else begin
ap_NS_fsm = ap_ST_st297_fsm_296;
end
end
ap_ST_st298_fsm_297 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st299_fsm_298;
end else begin
ap_NS_fsm = ap_ST_st298_fsm_297;
end
end
ap_ST_st299_fsm_298 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st300_fsm_299;
end else begin
ap_NS_fsm = ap_ST_st299_fsm_298;
end
end
ap_ST_st300_fsm_299 :
begin
if (~(ins_TVALID == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_300;
end else begin
ap_NS_fsm = ap_ST_st300_fsm_299;
end
end
ap_ST_pp0_stg0_fsm_300 :
begin
if ((~((ap_const_logic_1 == ap_reg_ppiten_pp0_it83) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it82)) & ~((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == exitcond2_fu_2840_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1)))) begin
ap_NS_fsm = ap_ST_pp0_stg0_fsm_300;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp0_it0) & ~(ap_const_lv1_0 == exitcond2_fu_2840_p2) & ~(ap_const_logic_1 == ap_reg_ppiten_pp0_it1))) begin
ap_NS_fsm = ap_ST_st385_fsm_301;
end else begin
ap_NS_fsm = ap_ST_st385_fsm_301;
end
end
ap_ST_st385_fsm_301 :
begin
ap_NS_fsm = ap_ST_st386_fsm_302;
end
ap_ST_st386_fsm_302 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st387_fsm_303;
end else begin
ap_NS_fsm = ap_ST_st386_fsm_302;
end
end
ap_ST_st387_fsm_303 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st388_fsm_304;
end else begin
ap_NS_fsm = ap_ST_st387_fsm_303;
end
end
ap_ST_st388_fsm_304 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st389_fsm_305;
end else begin
ap_NS_fsm = ap_ST_st388_fsm_304;
end
end
ap_ST_st389_fsm_305 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st390_fsm_306;
end else begin
ap_NS_fsm = ap_ST_st389_fsm_305;
end
end
ap_ST_st390_fsm_306 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st391_fsm_307;
end else begin
ap_NS_fsm = ap_ST_st390_fsm_306;
end
end
ap_ST_st391_fsm_307 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st392_fsm_308;
end else begin
ap_NS_fsm = ap_ST_st391_fsm_307;
end
end
ap_ST_st392_fsm_308 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st393_fsm_309;
end else begin
ap_NS_fsm = ap_ST_st392_fsm_308;
end
end
ap_ST_st393_fsm_309 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st394_fsm_310;
end else begin
ap_NS_fsm = ap_ST_st393_fsm_309;
end
end
ap_ST_st394_fsm_310 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st395_fsm_311;
end else begin
ap_NS_fsm = ap_ST_st394_fsm_310;
end
end
ap_ST_st395_fsm_311 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st396_fsm_312;
end else begin
ap_NS_fsm = ap_ST_st395_fsm_311;
end
end
ap_ST_st396_fsm_312 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st397_fsm_313;
end else begin
ap_NS_fsm = ap_ST_st396_fsm_312;
end
end
ap_ST_st397_fsm_313 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st398_fsm_314;
end else begin
ap_NS_fsm = ap_ST_st397_fsm_313;
end
end
ap_ST_st398_fsm_314 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st399_fsm_315;
end else begin
ap_NS_fsm = ap_ST_st398_fsm_314;
end
end
ap_ST_st399_fsm_315 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st400_fsm_316;
end else begin
ap_NS_fsm = ap_ST_st399_fsm_315;
end
end
ap_ST_st400_fsm_316 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st401_fsm_317;
end else begin
ap_NS_fsm = ap_ST_st400_fsm_316;
end
end
ap_ST_st401_fsm_317 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st402_fsm_318;
end else begin
ap_NS_fsm = ap_ST_st401_fsm_317;
end
end
ap_ST_st402_fsm_318 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st403_fsm_319;
end else begin
ap_NS_fsm = ap_ST_st402_fsm_318;
end
end
ap_ST_st403_fsm_319 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st404_fsm_320;
end else begin
ap_NS_fsm = ap_ST_st403_fsm_319;
end
end
ap_ST_st404_fsm_320 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st405_fsm_321;
end else begin
ap_NS_fsm = ap_ST_st404_fsm_320;
end
end
ap_ST_st405_fsm_321 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st406_fsm_322;
end else begin
ap_NS_fsm = ap_ST_st405_fsm_321;
end
end
ap_ST_st406_fsm_322 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st407_fsm_323;
end else begin
ap_NS_fsm = ap_ST_st406_fsm_322;
end
end
ap_ST_st407_fsm_323 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st408_fsm_324;
end else begin
ap_NS_fsm = ap_ST_st407_fsm_323;
end
end
ap_ST_st408_fsm_324 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st409_fsm_325;
end else begin
ap_NS_fsm = ap_ST_st408_fsm_324;
end
end
ap_ST_st409_fsm_325 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st410_fsm_326;
end else begin
ap_NS_fsm = ap_ST_st409_fsm_325;
end
end
ap_ST_st410_fsm_326 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st411_fsm_327;
end else begin
ap_NS_fsm = ap_ST_st410_fsm_326;
end
end
ap_ST_st411_fsm_327 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st412_fsm_328;
end else begin
ap_NS_fsm = ap_ST_st411_fsm_327;
end
end
ap_ST_st412_fsm_328 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st413_fsm_329;
end else begin
ap_NS_fsm = ap_ST_st412_fsm_328;
end
end
ap_ST_st413_fsm_329 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st414_fsm_330;
end else begin
ap_NS_fsm = ap_ST_st413_fsm_329;
end
end
ap_ST_st414_fsm_330 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st415_fsm_331;
end else begin
ap_NS_fsm = ap_ST_st414_fsm_330;
end
end
ap_ST_st415_fsm_331 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st416_fsm_332;
end else begin
ap_NS_fsm = ap_ST_st415_fsm_331;
end
end
ap_ST_st416_fsm_332 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st417_fsm_333;
end else begin
ap_NS_fsm = ap_ST_st416_fsm_332;
end
end
ap_ST_st417_fsm_333 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st418_fsm_334;
end else begin
ap_NS_fsm = ap_ST_st417_fsm_333;
end
end
ap_ST_st418_fsm_334 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st419_fsm_335;
end else begin
ap_NS_fsm = ap_ST_st418_fsm_334;
end
end
ap_ST_st419_fsm_335 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st420_fsm_336;
end else begin
ap_NS_fsm = ap_ST_st419_fsm_335;
end
end
ap_ST_st420_fsm_336 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st421_fsm_337;
end else begin
ap_NS_fsm = ap_ST_st420_fsm_336;
end
end
ap_ST_st421_fsm_337 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st422_fsm_338;
end else begin
ap_NS_fsm = ap_ST_st421_fsm_337;
end
end
ap_ST_st422_fsm_338 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st423_fsm_339;
end else begin
ap_NS_fsm = ap_ST_st422_fsm_338;
end
end
ap_ST_st423_fsm_339 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st424_fsm_340;
end else begin
ap_NS_fsm = ap_ST_st423_fsm_339;
end
end
ap_ST_st424_fsm_340 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st425_fsm_341;
end else begin
ap_NS_fsm = ap_ST_st424_fsm_340;
end
end
ap_ST_st425_fsm_341 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st426_fsm_342;
end else begin
ap_NS_fsm = ap_ST_st425_fsm_341;
end
end
ap_ST_st426_fsm_342 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st427_fsm_343;
end else begin
ap_NS_fsm = ap_ST_st426_fsm_342;
end
end
ap_ST_st427_fsm_343 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st428_fsm_344;
end else begin
ap_NS_fsm = ap_ST_st427_fsm_343;
end
end
ap_ST_st428_fsm_344 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st429_fsm_345;
end else begin
ap_NS_fsm = ap_ST_st428_fsm_344;
end
end
ap_ST_st429_fsm_345 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st430_fsm_346;
end else begin
ap_NS_fsm = ap_ST_st429_fsm_345;
end
end
ap_ST_st430_fsm_346 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st431_fsm_347;
end else begin
ap_NS_fsm = ap_ST_st430_fsm_346;
end
end
ap_ST_st431_fsm_347 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st432_fsm_348;
end else begin
ap_NS_fsm = ap_ST_st431_fsm_347;
end
end
ap_ST_st432_fsm_348 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st433_fsm_349;
end else begin
ap_NS_fsm = ap_ST_st432_fsm_348;
end
end
ap_ST_st433_fsm_349 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st434_fsm_350;
end else begin
ap_NS_fsm = ap_ST_st433_fsm_349;
end
end
ap_ST_st434_fsm_350 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st435_fsm_351;
end else begin
ap_NS_fsm = ap_ST_st434_fsm_350;
end
end
ap_ST_st435_fsm_351 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st436_fsm_352;
end else begin
ap_NS_fsm = ap_ST_st435_fsm_351;
end
end
ap_ST_st436_fsm_352 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st437_fsm_353;
end else begin
ap_NS_fsm = ap_ST_st436_fsm_352;
end
end
ap_ST_st437_fsm_353 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st438_fsm_354;
end else begin
ap_NS_fsm = ap_ST_st437_fsm_353;
end
end
ap_ST_st438_fsm_354 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st439_fsm_355;
end else begin
ap_NS_fsm = ap_ST_st438_fsm_354;
end
end
ap_ST_st439_fsm_355 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st440_fsm_356;
end else begin
ap_NS_fsm = ap_ST_st439_fsm_355;
end
end
ap_ST_st440_fsm_356 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st441_fsm_357;
end else begin
ap_NS_fsm = ap_ST_st440_fsm_356;
end
end
ap_ST_st441_fsm_357 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st442_fsm_358;
end else begin
ap_NS_fsm = ap_ST_st441_fsm_357;
end
end
ap_ST_st442_fsm_358 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st443_fsm_359;
end else begin
ap_NS_fsm = ap_ST_st442_fsm_358;
end
end
ap_ST_st443_fsm_359 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st444_fsm_360;
end else begin
ap_NS_fsm = ap_ST_st443_fsm_359;
end
end
ap_ST_st444_fsm_360 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st445_fsm_361;
end else begin
ap_NS_fsm = ap_ST_st444_fsm_360;
end
end
ap_ST_st445_fsm_361 :
begin
if (~(ap_const_logic_0 == ap_sig_ioackin_outs_TREADY)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_st445_fsm_361;
end
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
/// ap_sig_bdd_1004 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1004 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4F]);
end
/// ap_sig_bdd_1013 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1013 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5E]);
end
/// ap_sig_bdd_1022 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1022 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6D]);
end
/// ap_sig_bdd_1031 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1031 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7C]);
end
/// ap_sig_bdd_1040 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1040 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8B]);
end
/// ap_sig_bdd_1049 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1049 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9A]);
end
/// ap_sig_bdd_1058 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1058 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A9]);
end
/// ap_sig_bdd_1067 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1067 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B8]);
end
/// ap_sig_bdd_1076 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1076 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C7]);
end
/// ap_sig_bdd_1085 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1085 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D6]);
end
/// ap_sig_bdd_1094 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1094 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E5]);
end
/// ap_sig_bdd_1103 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1103 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F4]);
end
/// ap_sig_bdd_1112 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1112 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_103]);
end
/// ap_sig_bdd_1121 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1121 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_112]);
end
/// ap_sig_bdd_1130 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1130 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_121]);
end
/// ap_sig_bdd_1140 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1140 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_1148 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1148 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_50]);
end
/// ap_sig_bdd_1157 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1157 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5F]);
end
/// ap_sig_bdd_1166 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1166 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6E]);
end
/// ap_sig_bdd_1175 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1175 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7D]);
end
/// ap_sig_bdd_1184 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1184 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8C]);
end
/// ap_sig_bdd_1193 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1193 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9B]);
end
/// ap_sig_bdd_1202 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1202 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_AA]);
end
/// ap_sig_bdd_1211 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1211 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B9]);
end
/// ap_sig_bdd_1220 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1220 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C8]);
end
/// ap_sig_bdd_1229 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1229 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D7]);
end
/// ap_sig_bdd_1238 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1238 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E6]);
end
/// ap_sig_bdd_1247 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1247 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F5]);
end
/// ap_sig_bdd_1256 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1256 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_104]);
end
/// ap_sig_bdd_1265 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1265 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_113]);
end
/// ap_sig_bdd_1274 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1274 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_122]);
end
/// ap_sig_bdd_1284 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1284 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_1292 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1292 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_51]);
end
/// ap_sig_bdd_1301 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1301 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_60]);
end
/// ap_sig_bdd_1310 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1310 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6F]);
end
/// ap_sig_bdd_1319 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1319 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7E]);
end
/// ap_sig_bdd_1328 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1328 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8D]);
end
/// ap_sig_bdd_1337 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1337 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9C]);
end
/// ap_sig_bdd_1346 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1346 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_AB]);
end
/// ap_sig_bdd_1355 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1355 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_BA]);
end
/// ap_sig_bdd_1364 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1364 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C9]);
end
/// ap_sig_bdd_1373 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1373 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D8]);
end
/// ap_sig_bdd_1382 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1382 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E7]);
end
/// ap_sig_bdd_1391 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1391 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F6]);
end
/// ap_sig_bdd_1400 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1400 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_105]);
end
/// ap_sig_bdd_1409 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1409 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_114]);
end
/// ap_sig_bdd_1418 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1418 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_123]);
end
/// ap_sig_bdd_1428 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1428 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end
/// ap_sig_bdd_1436 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1436 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_52]);
end
/// ap_sig_bdd_1445 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1445 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_61]);
end
/// ap_sig_bdd_1454 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1454 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_70]);
end
/// ap_sig_bdd_1463 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1463 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7F]);
end
/// ap_sig_bdd_1472 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1472 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8E]);
end
/// ap_sig_bdd_1481 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1481 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9D]);
end
/// ap_sig_bdd_1490 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1490 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_AC]);
end
/// ap_sig_bdd_1499 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1499 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_BB]);
end
/// ap_sig_bdd_1508 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1508 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_CA]);
end
/// ap_sig_bdd_1517 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1517 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D9]);
end
/// ap_sig_bdd_1526 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1526 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E8]);
end
/// ap_sig_bdd_1535 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1535 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F7]);
end
/// ap_sig_bdd_1544 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1544 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_106]);
end
/// ap_sig_bdd_1553 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1553 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_115]);
end
/// ap_sig_bdd_1562 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1562 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_124]);
end
/// ap_sig_bdd_1572 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1572 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8]);
end
/// ap_sig_bdd_1580 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1580 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_53]);
end
/// ap_sig_bdd_1589 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1589 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_62]);
end
/// ap_sig_bdd_1598 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1598 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_71]);
end
/// ap_sig_bdd_1607 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1607 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_80]);
end
/// ap_sig_bdd_1616 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1616 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8F]);
end
/// ap_sig_bdd_1625 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1625 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9E]);
end
/// ap_sig_bdd_1634 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1634 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_AD]);
end
/// ap_sig_bdd_1643 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1643 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_BC]);
end
/// ap_sig_bdd_1652 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1652 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_CB]);
end
/// ap_sig_bdd_1661 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1661 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_DA]);
end
/// ap_sig_bdd_1670 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1670 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E9]);
end
/// ap_sig_bdd_1679 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1679 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F8]);
end
/// ap_sig_bdd_1688 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1688 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_107]);
end
/// ap_sig_bdd_1697 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1697 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_116]);
end
/// ap_sig_bdd_1706 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1706 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_125]);
end
/// ap_sig_bdd_1716 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1716 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9]);
end
/// ap_sig_bdd_1724 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1724 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_54]);
end
/// ap_sig_bdd_1733 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1733 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_63]);
end
/// ap_sig_bdd_1742 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1742 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_72]);
end
/// ap_sig_bdd_1751 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1751 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_81]);
end
/// ap_sig_bdd_1760 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1760 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_90]);
end
/// ap_sig_bdd_1769 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1769 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9F]);
end
/// ap_sig_bdd_1778 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1778 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_AE]);
end
/// ap_sig_bdd_1787 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1787 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_BD]);
end
/// ap_sig_bdd_1796 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1796 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_CC]);
end
/// ap_sig_bdd_1805 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1805 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_DB]);
end
/// ap_sig_bdd_1814 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1814 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_EA]);
end
/// ap_sig_bdd_1823 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1823 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F9]);
end
/// ap_sig_bdd_1832 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1832 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_108]);
end
/// ap_sig_bdd_1841 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1841 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_117]);
end
/// ap_sig_bdd_1850 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1850 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_126]);
end
/// ap_sig_bdd_1860 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1860 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A]);
end
/// ap_sig_bdd_1868 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1868 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_55]);
end
/// ap_sig_bdd_1877 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1877 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_64]);
end
/// ap_sig_bdd_1886 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1886 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_73]);
end
/// ap_sig_bdd_1895 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1895 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_82]);
end
/// ap_sig_bdd_1904 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1904 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_91]);
end
/// ap_sig_bdd_1913 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1913 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A0]);
end
/// ap_sig_bdd_1922 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1922 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_AF]);
end
/// ap_sig_bdd_1931 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1931 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_BE]);
end
/// ap_sig_bdd_1940 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1940 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_CD]);
end
/// ap_sig_bdd_1949 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1949 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_DC]);
end
/// ap_sig_bdd_1958 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1958 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_EB]);
end
/// ap_sig_bdd_1967 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1967 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_FA]);
end
/// ap_sig_bdd_1976 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1976 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_109]);
end
/// ap_sig_bdd_1985 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1985 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_118]);
end
/// ap_sig_bdd_1994 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1994 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_127]);
end
/// ap_sig_bdd_2004 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2004 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B]);
end
/// ap_sig_bdd_2012 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2012 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_56]);
end
/// ap_sig_bdd_2021 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2021 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_65]);
end
/// ap_sig_bdd_2030 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2030 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_74]);
end
/// ap_sig_bdd_2039 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2039 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_83]);
end
/// ap_sig_bdd_2048 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2048 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_92]);
end
/// ap_sig_bdd_2057 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2057 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A1]);
end
/// ap_sig_bdd_2066 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2066 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B0]);
end
/// ap_sig_bdd_2075 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2075 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_BF]);
end
/// ap_sig_bdd_2084 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2084 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_CE]);
end
/// ap_sig_bdd_2093 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2093 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_DD]);
end
/// ap_sig_bdd_2102 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2102 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_EC]);
end
/// ap_sig_bdd_2111 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2111 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_FB]);
end
/// ap_sig_bdd_2120 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2120 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10A]);
end
/// ap_sig_bdd_2129 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2129 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_119]);
end
/// ap_sig_bdd_2138 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2138 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_128]);
end
/// ap_sig_bdd_2148 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2148 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C]);
end
/// ap_sig_bdd_2156 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2156 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_57]);
end
/// ap_sig_bdd_2165 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2165 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_66]);
end
/// ap_sig_bdd_2174 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2174 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_75]);
end
/// ap_sig_bdd_2183 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2183 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_84]);
end
/// ap_sig_bdd_2192 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2192 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_93]);
end
/// ap_sig_bdd_2201 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2201 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A2]);
end
/// ap_sig_bdd_2210 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2210 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B1]);
end
/// ap_sig_bdd_2219 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2219 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C0]);
end
/// ap_sig_bdd_2228 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2228 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_CF]);
end
/// ap_sig_bdd_2237 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2237 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_DE]);
end
/// ap_sig_bdd_2246 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2246 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_ED]);
end
/// ap_sig_bdd_2255 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2255 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_FC]);
end
/// ap_sig_bdd_2264 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2264 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10B]);
end
/// ap_sig_bdd_2273 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2273 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11A]);
end
/// ap_sig_bdd_2282 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2282 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_129]);
end
/// ap_sig_bdd_2292 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2292 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D]);
end
/// ap_sig_bdd_2300 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2300 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_58]);
end
/// ap_sig_bdd_2309 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2309 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_67]);
end
/// ap_sig_bdd_2318 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2318 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_76]);
end
/// ap_sig_bdd_2327 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2327 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_85]);
end
/// ap_sig_bdd_2336 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2336 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_94]);
end
/// ap_sig_bdd_2345 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2345 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A3]);
end
/// ap_sig_bdd_2354 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2354 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B2]);
end
/// ap_sig_bdd_2363 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2363 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C1]);
end
/// ap_sig_bdd_2372 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2372 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D0]);
end
/// ap_sig_bdd_2381 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2381 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_DF]);
end
/// ap_sig_bdd_2390 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2390 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_EE]);
end
/// ap_sig_bdd_2399 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2399 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_FD]);
end
/// ap_sig_bdd_2408 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2408 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10C]);
end
/// ap_sig_bdd_2417 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2417 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11B]);
end
/// ap_sig_bdd_2426 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2426 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12A]);
end
/// ap_sig_bdd_2437 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2437 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_47]);
end
/// ap_sig_bdd_2694 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2694 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12C]);
end
/// ap_sig_bdd_2708 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2708 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12E]);
end
/// ap_sig_bdd_2719 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2719 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_131]);
end
/// ap_sig_bdd_2728 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2728 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_134]);
end
/// ap_sig_bdd_2737 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2737 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_137]);
end
/// ap_sig_bdd_2746 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2746 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13A]);
end
/// ap_sig_bdd_2755 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2755 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13D]);
end
/// ap_sig_bdd_2764 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2764 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_140]);
end
/// ap_sig_bdd_2773 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2773 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_143]);
end
/// ap_sig_bdd_2782 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2782 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_146]);
end
/// ap_sig_bdd_2791 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2791 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_149]);
end
/// ap_sig_bdd_2800 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2800 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14C]);
end
/// ap_sig_bdd_2809 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2809 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14F]);
end
/// ap_sig_bdd_2818 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2818 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_152]);
end
/// ap_sig_bdd_2827 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2827 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_155]);
end
/// ap_sig_bdd_2836 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2836 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_158]);
end
/// ap_sig_bdd_2845 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2845 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_15B]);
end
/// ap_sig_bdd_2854 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2854 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_15E]);
end
/// ap_sig_bdd_2863 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2863 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_161]);
end
/// ap_sig_bdd_2872 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2872 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_164]);
end
/// ap_sig_bdd_2881 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2881 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_167]);
end
/// ap_sig_bdd_2893 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2893 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E]);
end
/// ap_sig_bdd_2902 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2902 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F]);
end
/// ap_sig_bdd_2911 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2911 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10]);
end
/// ap_sig_bdd_2920 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2920 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11]);
end
/// ap_sig_bdd_2929 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2929 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12]);
end
/// ap_sig_bdd_2938 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2938 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13]);
end
/// ap_sig_bdd_2947 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2947 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14]);
end
/// ap_sig_bdd_2956 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2956 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_15]);
end
/// ap_sig_bdd_2965 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2965 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_16]);
end
/// ap_sig_bdd_2974 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2974 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_17]);
end
/// ap_sig_bdd_2983 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2983 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_18]);
end
/// ap_sig_bdd_2992 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_2992 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_19]);
end
/// ap_sig_bdd_3001 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3001 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1A]);
end
/// ap_sig_bdd_3010 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3010 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1B]);
end
/// ap_sig_bdd_3019 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3019 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1C]);
end
/// ap_sig_bdd_3028 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3028 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1D]);
end
/// ap_sig_bdd_3037 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3037 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1E]);
end
/// ap_sig_bdd_3046 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3046 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1F]);
end
/// ap_sig_bdd_3055 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3055 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_20]);
end
/// ap_sig_bdd_3064 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3064 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_21]);
end
/// ap_sig_bdd_3073 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3073 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_22]);
end
/// ap_sig_bdd_3082 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3082 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_23]);
end
/// ap_sig_bdd_3091 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3091 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_24]);
end
/// ap_sig_bdd_3100 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3100 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_25]);
end
/// ap_sig_bdd_3109 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3109 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_26]);
end
/// ap_sig_bdd_3118 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3118 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_27]);
end
/// ap_sig_bdd_3127 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3127 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_28]);
end
/// ap_sig_bdd_3136 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3136 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_29]);
end
/// ap_sig_bdd_3145 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3145 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2A]);
end
/// ap_sig_bdd_3154 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3154 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2B]);
end
/// ap_sig_bdd_3163 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3163 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2C]);
end
/// ap_sig_bdd_3172 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3172 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2D]);
end
/// ap_sig_bdd_3181 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3181 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2E]);
end
/// ap_sig_bdd_3190 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3190 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2F]);
end
/// ap_sig_bdd_3199 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3199 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_30]);
end
/// ap_sig_bdd_3208 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3208 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_31]);
end
/// ap_sig_bdd_3217 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3217 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_32]);
end
/// ap_sig_bdd_3226 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3226 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_33]);
end
/// ap_sig_bdd_3235 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3235 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_34]);
end
/// ap_sig_bdd_3244 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3244 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_35]);
end
/// ap_sig_bdd_3253 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3253 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_36]);
end
/// ap_sig_bdd_3262 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3262 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_37]);
end
/// ap_sig_bdd_3271 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3271 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_38]);
end
/// ap_sig_bdd_3280 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3280 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_39]);
end
/// ap_sig_bdd_3289 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3289 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3A]);
end
/// ap_sig_bdd_3298 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3298 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3B]);
end
/// ap_sig_bdd_3307 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3307 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3C]);
end
/// ap_sig_bdd_3316 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3316 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3D]);
end
/// ap_sig_bdd_3325 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3325 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3E]);
end
/// ap_sig_bdd_3334 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3334 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3F]);
end
/// ap_sig_bdd_3343 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3343 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_40]);
end
/// ap_sig_bdd_3352 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3352 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_41]);
end
/// ap_sig_bdd_3361 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3361 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_42]);
end
/// ap_sig_bdd_3370 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3370 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_43]);
end
/// ap_sig_bdd_3379 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3379 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_44]);
end
/// ap_sig_bdd_3388 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3388 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_45]);
end
/// ap_sig_bdd_3397 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3397 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_46]);
end
/// ap_sig_bdd_3417 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3417 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4A]);
end
/// ap_sig_bdd_3437 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3437 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_59]);
end
/// ap_sig_bdd_3447 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3447 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_68]);
end
/// ap_sig_bdd_3457 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3457 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_77]);
end
/// ap_sig_bdd_3467 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3467 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_86]);
end
/// ap_sig_bdd_3477 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3477 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_95]);
end
/// ap_sig_bdd_3487 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3487 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A4]);
end
/// ap_sig_bdd_3497 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3497 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B3]);
end
/// ap_sig_bdd_3507 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3507 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C2]);
end
/// ap_sig_bdd_3517 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3517 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D1]);
end
/// ap_sig_bdd_3527 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3527 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E0]);
end
/// ap_sig_bdd_3537 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3537 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_EF]);
end
/// ap_sig_bdd_3547 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_3547 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12B]);
end
/// ap_sig_bdd_399 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_399 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_410 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_410 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_48]);
end
/// ap_sig_bdd_419 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_419 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4B]);
end
/// ap_sig_bdd_428 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_428 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5A]);
end
/// ap_sig_bdd_437 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_437 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_69]);
end
/// ap_sig_bdd_446 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_446 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_78]);
end
/// ap_sig_bdd_455 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_455 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_87]);
end
/// ap_sig_bdd_464 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_464 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_96]);
end
/// ap_sig_bdd_473 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_473 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A5]);
end
/// ap_sig_bdd_482 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_482 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B4]);
end
/// ap_sig_bdd_491 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_491 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C3]);
end
/// ap_sig_bdd_500 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_500 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D2]);
end
/// ap_sig_bdd_5023 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5023 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_FE]);
end
/// ap_sig_bdd_5046 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5046 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10D]);
end
/// ap_sig_bdd_5069 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5069 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11C]);
end
/// ap_sig_bdd_509 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_509 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E1]);
end
/// ap_sig_bdd_5096 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5096 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12F]);
end
/// ap_sig_bdd_5104 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5104 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_130]);
end
/// ap_sig_bdd_5113 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5113 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_132]);
end
/// ap_sig_bdd_5121 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5121 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_133]);
end
/// ap_sig_bdd_5130 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5130 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_135]);
end
/// ap_sig_bdd_5138 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5138 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_136]);
end
/// ap_sig_bdd_5147 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5147 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_138]);
end
/// ap_sig_bdd_5155 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5155 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_139]);
end
/// ap_sig_bdd_5164 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5164 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13B]);
end
/// ap_sig_bdd_5172 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5172 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13C]);
end
/// ap_sig_bdd_518 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_518 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F0]);
end
/// ap_sig_bdd_5181 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5181 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13E]);
end
/// ap_sig_bdd_5189 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5189 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_13F]);
end
/// ap_sig_bdd_5198 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5198 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_141]);
end
/// ap_sig_bdd_5206 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5206 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_142]);
end
/// ap_sig_bdd_5215 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5215 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_144]);
end
/// ap_sig_bdd_5223 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5223 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_145]);
end
/// ap_sig_bdd_5232 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5232 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_147]);
end
/// ap_sig_bdd_5240 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5240 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_148]);
end
/// ap_sig_bdd_5249 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5249 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14A]);
end
/// ap_sig_bdd_5257 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5257 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14B]);
end
/// ap_sig_bdd_5266 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5266 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14D]);
end
/// ap_sig_bdd_527 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_527 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_FF]);
end
/// ap_sig_bdd_5274 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5274 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_14E]);
end
/// ap_sig_bdd_5283 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5283 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_150]);
end
/// ap_sig_bdd_5291 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5291 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_151]);
end
/// ap_sig_bdd_5300 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5300 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_153]);
end
/// ap_sig_bdd_5308 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5308 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_154]);
end
/// ap_sig_bdd_5317 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5317 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_156]);
end
/// ap_sig_bdd_5325 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5325 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_157]);
end
/// ap_sig_bdd_5334 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5334 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_159]);
end
/// ap_sig_bdd_5342 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5342 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_15A]);
end
/// ap_sig_bdd_5351 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5351 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_15C]);
end
/// ap_sig_bdd_5359 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5359 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_15D]);
end
/// ap_sig_bdd_536 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_536 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10E]);
end
/// ap_sig_bdd_5368 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5368 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_15F]);
end
/// ap_sig_bdd_5376 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5376 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_160]);
end
/// ap_sig_bdd_5385 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5385 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_162]);
end
/// ap_sig_bdd_5393 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5393 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_163]);
end
/// ap_sig_bdd_5402 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5402 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_165]);
end
/// ap_sig_bdd_5410 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5410 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_166]);
end
/// ap_sig_bdd_5419 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5419 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_168]);
end
/// ap_sig_bdd_5427 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5427 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_169]);
end
/// ap_sig_bdd_545 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_545 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11D]);
end
/// ap_sig_bdd_555 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_555 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_563 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_563 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_49]);
end
/// ap_sig_bdd_572 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_572 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4C]);
end
/// ap_sig_bdd_581 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_581 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5B]);
end
/// ap_sig_bdd_590 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_590 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6A]);
end
/// ap_sig_bdd_5902 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_5902 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_12D]);
end
/// ap_sig_bdd_599 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_599 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_79]);
end
/// ap_sig_bdd_608 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_608 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_88]);
end
/// ap_sig_bdd_617 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_617 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_97]);
end
/// ap_sig_bdd_626 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_626 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A6]);
end
/// ap_sig_bdd_635 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_635 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B5]);
end
/// ap_sig_bdd_644 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_644 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C4]);
end
/// ap_sig_bdd_653 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_653 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D3]);
end
/// ap_sig_bdd_662 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_662 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E2]);
end
/// ap_sig_bdd_671 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_671 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F1]);
end
/// ap_sig_bdd_680 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_680 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_100]);
end
/// ap_sig_bdd_689 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_689 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_10F]);
end
/// ap_sig_bdd_698 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_698 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11E]);
end
/// ap_sig_bdd_708 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_708 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_716 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_716 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4D]);
end
/// ap_sig_bdd_725 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_725 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5C]);
end
/// ap_sig_bdd_734 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_734 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6B]);
end
/// ap_sig_bdd_743 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_743 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7A]);
end
/// ap_sig_bdd_752 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_752 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_89]);
end
/// ap_sig_bdd_761 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_761 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_98]);
end
/// ap_sig_bdd_770 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_770 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A7]);
end
/// ap_sig_bdd_779 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_779 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B6]);
end
/// ap_sig_bdd_788 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_788 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C5]);
end
/// ap_sig_bdd_797 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_797 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D4]);
end
/// ap_sig_bdd_806 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_806 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E3]);
end
/// ap_sig_bdd_815 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_815 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F2]);
end
/// ap_sig_bdd_824 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_824 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_101]);
end
/// ap_sig_bdd_833 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_833 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_110]);
end
/// ap_sig_bdd_842 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_842 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_11F]);
end
/// ap_sig_bdd_852 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_852 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_860 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_860 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4E]);
end
/// ap_sig_bdd_869 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_869 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5D]);
end
/// ap_sig_bdd_878 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_878 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6C]);
end
/// ap_sig_bdd_887 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_887 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7B]);
end
/// ap_sig_bdd_896 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_896 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8A]);
end
/// ap_sig_bdd_905 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_905 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_99]);
end
/// ap_sig_bdd_914 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_914 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_A8]);
end
/// ap_sig_bdd_923 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_923 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_B7]);
end
/// ap_sig_bdd_932 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_932 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_C6]);
end
/// ap_sig_bdd_941 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_941 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_D5]);
end
/// ap_sig_bdd_950 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_950 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_E4]);
end
/// ap_sig_bdd_959 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_959 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_F3]);
end
/// ap_sig_bdd_968 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_968 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_102]);
end
/// ap_sig_bdd_977 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_977 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_111]);
end
/// ap_sig_bdd_986 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_986 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_120]);
end
/// ap_sig_bdd_996 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_996 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
assign beta_addr_111281129_part_set_fu_3103_p5 = {{tmp_21_fu_3093_p4}, {ap_reg_ppstg_reg_725_pp0_it81[32'd479 : 32'd0]}};
assign beta_load_10_fu_3290_p1 = reg_733;
assign beta_load_11_fu_3305_p1 = reg_733;
assign beta_load_12_fu_3320_p1 = reg_733;
assign beta_load_13_fu_3335_p1 = reg_733;
assign beta_load_14_fu_3350_p1 = reg_733;
assign beta_load_15_fu_3365_p1 = reg_733;
assign beta_load_16_fu_3380_p1 = reg_733;
assign beta_load_17_fu_3395_p1 = reg_733;
assign beta_load_18_fu_3410_p1 = reg_733;
assign beta_load_1_fu_3155_p1 = reg_733;
assign beta_load_2_fu_3170_p1 = reg_733;
assign beta_load_3_fu_3185_p1 = reg_733;
assign beta_load_4_fu_3200_p1 = reg_733;
assign beta_load_5_fu_3215_p1 = reg_733;
assign beta_load_6_fu_3230_p1 = reg_733;
assign beta_load_7_fu_3245_p1 = reg_733;
assign beta_load_8_fu_3260_p1 = reg_733;
assign beta_load_9_fu_3275_p1 = reg_733;
assign beta_load_fu_3125_p1 = reg_733;
assign beta_load_s_fu_3140_p1 = reg_733;
assign beta_write_assign_toint_fu_3089_p1 = grp_fu_626_p2;
assign data_array_addr_10_gep_fu_360_p3 = ap_const_lv64_A;
assign data_array_addr_11_gep_fu_368_p3 = ap_const_lv64_B;
assign data_array_addr_12_gep_fu_376_p3 = ap_const_lv64_C;
assign data_array_addr_13_gep_fu_384_p3 = ap_const_lv64_D;
assign data_array_addr_14_gep_fu_392_p3 = ap_const_lv64_E;
assign data_array_addr_15_gep_fu_400_p3 = ap_const_lv64_F;
assign data_array_addr_16_gep_fu_244_p3 = ap_const_lv64_10;
assign data_array_addr_17_gep_fu_288_p3 = ap_const_lv64_11;
assign data_array_addr_18_gep_fu_256_p3 = ap_const_lv64_12;
assign data_array_addr_19_gep_fu_296_p3 = ap_const_lv64_13;
assign data_array_addr_1_gep_fu_304_p3 = ap_const_lv64_1;
assign data_array_addr_2_gep_fu_272_p3 = ap_const_lv64_2;
assign data_array_addr_3_gep_fu_312_p3 = ap_const_lv64_3;
assign data_array_addr_4_gep_fu_280_p3 = ap_const_lv64_4;
assign data_array_addr_5_gep_fu_320_p3 = ap_const_lv64_5;
assign data_array_addr_6_gep_fu_328_p3 = ap_const_lv64_6;
assign data_array_addr_7_gep_fu_336_p3 = ap_const_lv64_7;
assign data_array_addr_8_gep_fu_344_p3 = ap_const_lv64_8;
assign data_array_addr_9_gep_fu_352_p3 = ap_const_lv64_9;
assign data_array_addr_gep_fu_264_p3 = ap_const_lv64_0;
assign data_array_d1 = beta_addr_111281129_part_set_reg_4307;
assign exitcond2_fu_2840_p2 = (i1_reg_418 == ap_const_lv5_14? 1'b1: 1'b0);
assign g_fu_3055_p1 = ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10;
assign gamma_load_10_fu_3285_p1 = reg_729;
assign gamma_load_11_fu_3300_p1 = reg_729;
assign gamma_load_12_fu_3315_p1 = reg_729;
assign gamma_load_13_fu_3330_p1 = reg_729;
assign gamma_load_14_fu_3345_p1 = reg_729;
assign gamma_load_15_fu_3360_p1 = reg_729;
assign gamma_load_16_fu_3375_p1 = reg_729;
assign gamma_load_17_fu_3390_p1 = reg_729;
assign gamma_load_18_fu_3405_p1 = reg_729;
assign gamma_load_1_fu_3150_p1 = reg_729;
assign gamma_load_2_fu_3165_p1 = reg_729;
assign gamma_load_3_fu_3180_p1 = reg_729;
assign gamma_load_4_fu_3195_p1 = reg_729;
assign gamma_load_5_fu_3210_p1 = reg_729;
assign gamma_load_6_fu_3225_p1 = reg_729;
assign gamma_load_7_fu_3240_p1 = reg_729;
assign gamma_load_8_fu_3255_p1 = reg_729;
assign gamma_load_9_fu_3270_p1 = reg_729;
assign gamma_load_fu_3120_p1 = reg_729;
assign gamma_load_s_fu_3135_p1 = reg_729;
assign gamma_write_assign_toint_fu_3085_p1 = grp_fu_622_p2;
assign grp_fu_430_ce = ap_const_logic_1;
assign grp_fu_430_p0 = v0x_assign4_fu_3001_p1;
assign grp_fu_430_p1 = v1x_assign_new_reg_3884;
assign grp_fu_434_ce = ap_const_logic_1;
assign grp_fu_434_p0 = v0y_assign_fu_3007_p1;
assign grp_fu_434_p1 = v1y_assign_new_reg_3889;
assign grp_fu_438_ce = ap_const_logic_1;
assign grp_fu_438_p0 = v0z_assign_fu_3013_p1;
assign grp_fu_438_p1 = v1z_assign_new_reg_3894;
assign grp_fu_442_ce = ap_const_logic_1;
assign grp_fu_442_p0 = v0x_assign4_fu_3001_p1;
assign grp_fu_442_p1 = v2x_assign_new_reg_3899;
assign grp_fu_446_ce = ap_const_logic_1;
assign grp_fu_446_p0 = v0y_assign_fu_3007_p1;
assign grp_fu_446_p1 = v2y_assign_new_reg_3904;
assign grp_fu_450_ce = ap_const_logic_1;
assign grp_fu_450_p0 = v0z_assign_fu_3013_p1;
assign grp_fu_450_p1 = v2z_assign_new_reg_3909;
assign grp_fu_454_ce = ap_const_logic_1;
assign grp_fu_454_p0 = v0x_assign4_fu_3001_p1;
assign grp_fu_454_p1 = rex_assign_new_reg_3929;
assign grp_fu_458_ce = ap_const_logic_1;
assign grp_fu_458_p0 = v0y_assign_fu_3007_p1;
assign grp_fu_458_p1 = rey_assign_new_reg_3934;
assign grp_fu_462_ce = ap_const_logic_1;
assign grp_fu_462_p0 = v0z_assign_fu_3013_p1;
assign grp_fu_462_p1 = rez_assign_new_reg_3939;
assign grp_fu_466_ce = ap_const_logic_1;
assign grp_fu_466_p0 = tmp_i_reg_4094;
assign grp_fu_466_p1 = tmp_i_311_reg_4099;
assign grp_fu_470_ce = ap_const_logic_1;
assign grp_fu_470_p0 = tmp_3_i_reg_4104;
assign grp_fu_470_p1 = tmp_4_i_reg_4109;
assign grp_fu_474_ce = ap_const_logic_1;
assign grp_fu_474_p0 = tmp_12_i_reg_4114;
assign grp_fu_474_p1 = tmp_13_i_reg_4119;
assign grp_fu_478_ce = ap_const_logic_1;
assign grp_fu_478_p0 = tmp_16_i_reg_4124;
assign grp_fu_478_p1 = tmp_17_i_reg_4129;
assign grp_fu_482_ce = ap_const_logic_1;
assign grp_fu_482_p0 = tmp_8_i_reg_4146;
assign grp_fu_482_p1 = tmp_9_i_reg_4151;
assign grp_fu_486_ce = ap_const_logic_1;
assign grp_fu_486_p0 = tmp_21_i_reg_4168;
assign grp_fu_486_p1 = tmp_22_i_reg_4173;
assign grp_fu_490_ce = ap_const_logic_1;
assign grp_fu_490_p0 = tmp_2_i_reg_4178;
assign grp_fu_490_p1 = tmp_6_i_reg_4183;
assign grp_fu_494_ce = ap_const_logic_1;
assign grp_fu_494_p0 = tmp_15_i_reg_4188;
assign grp_fu_494_p1 = tmp_19_i_reg_4193;
assign grp_fu_498_ce = ap_const_logic_1;
assign grp_fu_498_p0 = tmp_27_i_reg_4198;
assign grp_fu_498_p1 = tmp_28_i_reg_4203;
assign grp_fu_502_ce = ap_const_logic_1;
assign grp_fu_502_p0 = tmp_32_i_reg_4208;
assign grp_fu_502_p1 = tmp_33_i_reg_4213;
assign grp_fu_506_ce = ap_const_logic_1;
assign grp_fu_506_p0 = tmp_7_i_reg_4230;
assign grp_fu_506_p1 = tmp_11_i_reg_4235;
assign grp_fu_510_ce = ap_const_logic_1;
assign grp_fu_510_p0 = tmp_20_i_reg_4240;
assign grp_fu_510_p1 = tmp_24_i_reg_4245;
assign grp_fu_514_ce = ap_const_logic_1;
assign grp_fu_514_p0 = tmp_29_i_reg_4250;
assign grp_fu_514_p1 = tmp_30_i_reg_4255;
assign grp_fu_518_ce = ap_const_logic_1;
assign grp_fu_518_p0 = tmp_34_i_reg_4260;
assign grp_fu_518_p1 = tmp_35_i_reg_4265;
assign grp_fu_522_ce = ap_const_logic_1;
assign grp_fu_522_p0 = e_reg_4038;
assign grp_fu_522_p1 = i_1_fu_3063_p1;
assign grp_fu_526_ce = ap_const_logic_1;
assign grp_fu_526_p0 = f_reg_4045;
assign grp_fu_526_p1 = ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10;
assign grp_fu_530_ce = ap_const_logic_1;
assign grp_fu_530_p0 = f_reg_4045;
assign grp_fu_530_p1 = ap_reg_ppstg_rdx_assign_new_reg_3914_pp0_it10;
assign grp_fu_534_ce = ap_const_logic_1;
assign grp_fu_534_p0 = d_reg_4031;
assign grp_fu_534_p1 = i_1_fu_3063_p1;
assign grp_fu_538_ce = ap_const_logic_1;
assign grp_fu_538_p0 = a_reg_4010;
assign grp_fu_538_p1 = k_reg_4059;
assign grp_fu_542_ce = ap_const_logic_1;
assign grp_fu_542_p0 = j_reg_4052;
assign grp_fu_542_p1 = b_reg_4017;
assign grp_fu_546_ce = ap_const_logic_1;
assign grp_fu_546_p0 = j_reg_4052;
assign grp_fu_546_p1 = c_reg_4024;
assign grp_fu_550_ce = ap_const_logic_1;
assign grp_fu_550_p0 = a_reg_4010;
assign grp_fu_550_p1 = l_reg_4066;
assign grp_fu_554_ce = ap_const_logic_1;
assign grp_fu_554_p0 = ap_reg_ppstg_d_reg_4031_pp0_it19;
assign grp_fu_554_p1 = ap_reg_ppstg_h_reg_4080_pp0_it19;
assign grp_fu_558_ce = ap_const_logic_1;
assign grp_fu_558_p0 = ap_reg_ppstg_e_reg_4038_pp0_it19;
assign grp_fu_558_p1 = ap_reg_ppstg_g_reg_4073_pp0_it19;
assign grp_fu_562_ce = ap_const_logic_1;
assign grp_fu_562_p0 = ap_reg_ppstg_b_reg_4017_pp0_it19;
assign grp_fu_562_p1 = ap_reg_ppstg_l_reg_4066_pp0_it19;
assign grp_fu_566_ce = ap_const_logic_1;
assign grp_fu_566_p0 = ap_reg_ppstg_k_reg_4059_pp0_it19;
assign grp_fu_566_p1 = ap_reg_ppstg_c_reg_4024_pp0_it19;
assign grp_fu_570_ce = ap_const_logic_1;
assign grp_fu_570_p0 = ap_reg_ppstg_a_reg_4010_pp0_it24;
assign grp_fu_570_p1 = tmp_1_i_reg_4134;
assign grp_fu_574_ce = ap_const_logic_1;
assign grp_fu_574_p0 = ap_reg_ppstg_b_reg_4017_pp0_it24;
assign grp_fu_574_p1 = tmp_5_i_reg_4140;
assign grp_fu_578_ce = ap_const_logic_1;
assign grp_fu_578_p0 = ap_reg_ppstg_f_reg_4045_pp0_it24;
assign grp_fu_578_p1 = tmp_14_i_reg_4156;
assign grp_fu_582_ce = ap_const_logic_1;
assign grp_fu_582_p0 = ap_reg_ppstg_e_reg_4038_pp0_it24;
assign grp_fu_582_p1 = tmp_18_i_reg_4162;
assign grp_fu_586_ce = ap_const_logic_1;
assign grp_fu_586_p0 = tmp_14_i_reg_4156;
assign grp_fu_586_p1 = ap_reg_ppstg_i_1_reg_4087_pp0_it24;
assign grp_fu_590_ce = ap_const_logic_1;
assign grp_fu_590_p0 = tmp_18_i_reg_4162;
assign grp_fu_590_p1 = ap_reg_ppstg_h_reg_4080_pp0_it24;
assign grp_fu_594_ce = ap_const_logic_1;
assign grp_fu_594_p0 = ap_reg_ppstg_j_reg_4052_pp0_it24;
assign grp_fu_594_p1 = tmp_1_i_reg_4134;
assign grp_fu_598_ce = ap_const_logic_1;
assign grp_fu_598_p0 = ap_reg_ppstg_k_reg_4059_pp0_it24;
assign grp_fu_598_p1 = tmp_5_i_reg_4140;
assign grp_fu_602_ce = ap_const_logic_1;
assign grp_fu_602_p0 = ap_reg_ppstg_c_reg_4024_pp0_it33;
assign grp_fu_602_p1 = tmp_10_i_reg_4218;
assign grp_fu_606_ce = ap_const_logic_1;
assign grp_fu_606_p0 = ap_reg_ppstg_d_reg_4031_pp0_it33;
assign grp_fu_606_p1 = tmp_23_i_reg_4224;
assign grp_fu_610_ce = ap_const_logic_1;
assign grp_fu_610_p0 = tmp_23_i_reg_4224;
assign grp_fu_610_p1 = ap_reg_ppstg_g_reg_4073_pp0_it33;
assign grp_fu_614_ce = ap_const_logic_1;
assign grp_fu_614_p0 = ap_reg_ppstg_l_reg_4066_pp0_it33;
assign grp_fu_614_p1 = tmp_10_i_reg_4218;
assign grp_fu_618_ce = ap_const_logic_1;
assign grp_fu_618_p0 = tmp_61_neg_i_reg_4297;
assign grp_fu_618_p1 = im_reg_4290;
assign grp_fu_622_ce = ap_const_logic_1;
assign grp_fu_622_p0 = ap_reg_ppstg_tmp_31_i_reg_4280_pp0_it77;
assign grp_fu_622_p1 = im_reg_4290;
assign grp_fu_626_ce = ap_const_logic_1;
assign grp_fu_626_p0 = ap_reg_ppstg_tmp_36_i_reg_4285_pp0_it77;
assign grp_fu_626_p1 = im_reg_4290;
assign grp_fu_630_ce = ap_const_logic_1;
assign grp_fu_630_p0 = ap_const_lv32_3F800000;
assign grp_fu_630_p1 = m_reg_4270;
assign grp_fu_639_p4 = {{data_array_q1[ap_const_lv32_1FF : ap_const_lv32_1E0]}};
assign h_fu_3059_p1 = ap_reg_ppstg_rdy_assign_new_reg_3919_pp0_it10;
assign i_1_fu_3063_p1 = ap_reg_ppstg_rdz_assign_new_reg_3924_pp0_it10;
assign i_fu_2846_p2 = (i1_reg_418 + ap_const_lv5_1);
assign ins_data_tmp_load_100_toint_fu_1361_p1 = reg_709;
assign ins_data_tmp_load_101_toint_fu_1365_p1 = reg_713;
assign ins_data_tmp_load_102_toint_fu_1369_p1 = reg_717;
assign ins_data_tmp_load_103_toint_fu_1373_p1 = reg_721;
assign ins_data_tmp_load_104_toint_fu_1377_p1 = ins_TDATA;
assign ins_data_tmp_load_105_toint_fu_1428_p1 = reg_669;
assign ins_data_tmp_load_106_toint_fu_1432_p1 = reg_673;
assign ins_data_tmp_load_107_toint_fu_1436_p1 = reg_677;
assign ins_data_tmp_load_108_toint_fu_1440_p1 = reg_681;
assign ins_data_tmp_load_109_toint_fu_1444_p1 = reg_685;
assign ins_data_tmp_load_10_toint_fu_777_p1 = reg_709;
assign ins_data_tmp_load_110_toint_fu_1448_p1 = reg_689;
assign ins_data_tmp_load_111_toint_fu_1452_p1 = reg_693;
assign ins_data_tmp_load_112_toint_fu_1456_p1 = reg_697;
assign ins_data_tmp_load_113_toint_fu_1460_p1 = reg_701;
assign ins_data_tmp_load_114_toint_fu_1464_p1 = reg_705;
assign ins_data_tmp_load_115_toint_fu_1468_p1 = reg_709;
assign ins_data_tmp_load_116_toint_fu_1472_p1 = reg_713;
assign ins_data_tmp_load_117_toint_fu_1476_p1 = reg_717;
assign ins_data_tmp_load_118_toint_fu_1480_p1 = reg_721;
assign ins_data_tmp_load_119_toint_fu_1484_p1 = ins_TDATA;
assign ins_data_tmp_load_11_toint_fu_781_p1 = reg_713;
assign ins_data_tmp_load_120_toint_fu_1535_p1 = reg_669;
assign ins_data_tmp_load_121_toint_fu_1539_p1 = reg_673;
assign ins_data_tmp_load_122_toint_fu_1543_p1 = reg_677;
assign ins_data_tmp_load_123_toint_fu_1547_p1 = reg_681;
assign ins_data_tmp_load_124_toint_fu_1551_p1 = reg_685;
assign ins_data_tmp_load_125_toint_fu_1555_p1 = reg_689;
assign ins_data_tmp_load_126_toint_fu_1559_p1 = reg_693;
assign ins_data_tmp_load_127_toint_fu_1563_p1 = reg_697;
assign ins_data_tmp_load_128_toint_fu_1567_p1 = reg_701;
assign ins_data_tmp_load_129_toint_fu_1571_p1 = reg_705;
assign ins_data_tmp_load_12_toint_fu_785_p1 = reg_717;
assign ins_data_tmp_load_130_toint_fu_1575_p1 = reg_709;
assign ins_data_tmp_load_131_toint_fu_1579_p1 = reg_713;
assign ins_data_tmp_load_132_toint_fu_1583_p1 = reg_717;
assign ins_data_tmp_load_133_toint_fu_1587_p1 = reg_721;
assign ins_data_tmp_load_134_toint_fu_1591_p1 = ins_TDATA;
assign ins_data_tmp_load_135_toint_fu_1642_p1 = reg_669;
assign ins_data_tmp_load_136_toint_fu_1646_p1 = reg_673;
assign ins_data_tmp_load_137_toint_fu_1650_p1 = reg_677;
assign ins_data_tmp_load_138_toint_fu_1654_p1 = reg_681;
assign ins_data_tmp_load_139_toint_fu_1658_p1 = reg_685;
assign ins_data_tmp_load_13_toint_fu_789_p1 = reg_721;
assign ins_data_tmp_load_140_toint_fu_1662_p1 = reg_689;
assign ins_data_tmp_load_141_toint_fu_1666_p1 = reg_693;
assign ins_data_tmp_load_142_toint_fu_1670_p1 = reg_697;
assign ins_data_tmp_load_143_toint_fu_1674_p1 = reg_701;
assign ins_data_tmp_load_144_toint_fu_1678_p1 = reg_705;
assign ins_data_tmp_load_145_toint_fu_1682_p1 = reg_709;
assign ins_data_tmp_load_146_toint_fu_1686_p1 = reg_713;
assign ins_data_tmp_load_147_toint_fu_1690_p1 = reg_717;
assign ins_data_tmp_load_148_toint_fu_1694_p1 = reg_721;
assign ins_data_tmp_load_149_toint_fu_1698_p1 = ins_TDATA;
assign ins_data_tmp_load_14_toint_fu_793_p1 = ins_data_val14_reg_3415;
assign ins_data_tmp_load_150_toint_fu_1749_p1 = reg_669;
assign ins_data_tmp_load_151_toint_fu_1753_p1 = reg_673;
assign ins_data_tmp_load_152_toint_fu_1757_p1 = reg_677;
assign ins_data_tmp_load_153_toint_fu_1761_p1 = reg_681;
assign ins_data_tmp_load_154_toint_fu_1765_p1 = reg_685;
assign ins_data_tmp_load_155_toint_fu_1769_p1 = reg_689;
assign ins_data_tmp_load_156_toint_fu_1773_p1 = reg_693;
assign ins_data_tmp_load_157_toint_fu_1777_p1 = reg_697;
assign ins_data_tmp_load_158_toint_fu_1781_p1 = reg_701;
assign ins_data_tmp_load_159_toint_fu_1785_p1 = reg_705;
assign ins_data_tmp_load_15_toint_fu_1030_p1 = ins_data_val15_reg_3420;
assign ins_data_tmp_load_160_toint_fu_1789_p1 = reg_709;
assign ins_data_tmp_load_161_toint_fu_1793_p1 = reg_713;
assign ins_data_tmp_load_162_toint_fu_1797_p1 = reg_717;
assign ins_data_tmp_load_163_toint_fu_1801_p1 = reg_721;
assign ins_data_tmp_load_164_toint_fu_1805_p1 = ins_TDATA;
assign ins_data_tmp_load_165_toint_fu_1856_p1 = reg_669;
assign ins_data_tmp_load_166_toint_fu_1860_p1 = reg_673;
assign ins_data_tmp_load_167_toint_fu_1864_p1 = reg_677;
assign ins_data_tmp_load_168_toint_fu_1868_p1 = reg_681;
assign ins_data_tmp_load_169_toint_fu_1872_p1 = reg_685;
assign ins_data_tmp_load_16_toint_fu_1033_p1 = ins_data_val16_reg_3425;
assign ins_data_tmp_load_170_toint_fu_1876_p1 = reg_689;
assign ins_data_tmp_load_171_toint_fu_1880_p1 = reg_693;
assign ins_data_tmp_load_172_toint_fu_1884_p1 = reg_697;
assign ins_data_tmp_load_173_toint_fu_1888_p1 = reg_701;
assign ins_data_tmp_load_174_toint_fu_1892_p1 = reg_705;
assign ins_data_tmp_load_175_toint_fu_1896_p1 = reg_709;
assign ins_data_tmp_load_176_toint_fu_1900_p1 = reg_713;
assign ins_data_tmp_load_177_toint_fu_1904_p1 = reg_717;
assign ins_data_tmp_load_178_toint_fu_1908_p1 = reg_721;
assign ins_data_tmp_load_179_toint_fu_1912_p1 = ins_TDATA;
assign ins_data_tmp_load_17_toint_fu_1036_p1 = ins_data_val17_reg_3430;
assign ins_data_tmp_load_180_toint_fu_1963_p1 = reg_669;
assign ins_data_tmp_load_181_toint_fu_1967_p1 = reg_673;
assign ins_data_tmp_load_182_toint_fu_1971_p1 = reg_677;
assign ins_data_tmp_load_183_toint_fu_1975_p1 = reg_681;
assign ins_data_tmp_load_184_toint_fu_1979_p1 = reg_685;
assign ins_data_tmp_load_185_toint_fu_1983_p1 = reg_689;
assign ins_data_tmp_load_186_toint_fu_1987_p1 = reg_693;
assign ins_data_tmp_load_187_toint_fu_1991_p1 = reg_697;
assign ins_data_tmp_load_188_toint_fu_1995_p1 = reg_701;
assign ins_data_tmp_load_189_toint_fu_1999_p1 = reg_705;
assign ins_data_tmp_load_18_toint_fu_1039_p1 = ins_data_val18_reg_3435;
assign ins_data_tmp_load_190_toint_fu_2003_p1 = reg_709;
assign ins_data_tmp_load_191_toint_fu_2007_p1 = reg_713;
assign ins_data_tmp_load_192_toint_fu_2011_p1 = reg_717;
assign ins_data_tmp_load_193_toint_fu_2015_p1 = reg_721;
assign ins_data_tmp_load_194_toint_fu_2019_p1 = ins_TDATA;
assign ins_data_tmp_load_195_toint_fu_2070_p1 = reg_669;
assign ins_data_tmp_load_196_toint_fu_2074_p1 = reg_673;
assign ins_data_tmp_load_197_toint_fu_2078_p1 = reg_677;
assign ins_data_tmp_load_198_toint_fu_2082_p1 = reg_681;
assign ins_data_tmp_load_199_toint_fu_2086_p1 = reg_685;
assign ins_data_tmp_load_19_toint_fu_1042_p1 = ins_data_val19_reg_3440;
assign ins_data_tmp_load_1_toint_fu_741_p1 = reg_673;
assign ins_data_tmp_load_200_toint_fu_2090_p1 = reg_689;
assign ins_data_tmp_load_201_toint_fu_2094_p1 = reg_693;
assign ins_data_tmp_load_202_toint_fu_2098_p1 = reg_697;
assign ins_data_tmp_load_203_toint_fu_2102_p1 = reg_701;
assign ins_data_tmp_load_204_toint_fu_2106_p1 = reg_705;
assign ins_data_tmp_load_205_toint_fu_2110_p1 = reg_709;
assign ins_data_tmp_load_206_toint_fu_2114_p1 = reg_713;
assign ins_data_tmp_load_207_toint_fu_2118_p1 = reg_717;
assign ins_data_tmp_load_208_toint_fu_2122_p1 = reg_721;
assign ins_data_tmp_load_209_toint_fu_2126_p1 = ins_TDATA;
assign ins_data_tmp_load_20_toint_fu_1045_p1 = ins_data_val20_reg_3445;
assign ins_data_tmp_load_210_toint_fu_2177_p1 = reg_669;
assign ins_data_tmp_load_211_toint_fu_2181_p1 = reg_673;
assign ins_data_tmp_load_212_toint_fu_2185_p1 = reg_677;
assign ins_data_tmp_load_213_toint_fu_2189_p1 = reg_681;
assign ins_data_tmp_load_214_toint_fu_2193_p1 = reg_685;
assign ins_data_tmp_load_215_toint_fu_2197_p1 = reg_689;
assign ins_data_tmp_load_216_toint_fu_2201_p1 = reg_693;
assign ins_data_tmp_load_217_toint_fu_2205_p1 = reg_697;
assign ins_data_tmp_load_218_toint_fu_2209_p1 = reg_701;
assign ins_data_tmp_load_219_toint_fu_2213_p1 = reg_705;
assign ins_data_tmp_load_21_toint_fu_1048_p1 = ins_data_val21_reg_3450;
assign ins_data_tmp_load_220_toint_fu_2217_p1 = reg_709;
assign ins_data_tmp_load_221_toint_fu_2221_p1 = reg_713;
assign ins_data_tmp_load_222_toint_fu_2225_p1 = reg_717;
assign ins_data_tmp_load_223_toint_fu_2229_p1 = reg_721;
assign ins_data_tmp_load_224_toint_fu_2233_p1 = ins_TDATA;
assign ins_data_tmp_load_225_toint_fu_2284_p1 = reg_669;
assign ins_data_tmp_load_226_toint_fu_2288_p1 = reg_673;
assign ins_data_tmp_load_227_toint_fu_2292_p1 = reg_677;
assign ins_data_tmp_load_228_toint_fu_2296_p1 = reg_681;
assign ins_data_tmp_load_229_toint_fu_2300_p1 = reg_685;
assign ins_data_tmp_load_22_toint_fu_1051_p1 = ins_data_val22_reg_3455;
assign ins_data_tmp_load_230_toint_fu_2304_p1 = reg_689;
assign ins_data_tmp_load_231_toint_fu_2308_p1 = reg_693;
assign ins_data_tmp_load_232_toint_fu_2312_p1 = reg_697;
assign ins_data_tmp_load_233_toint_fu_2316_p1 = reg_701;
assign ins_data_tmp_load_234_toint_fu_2320_p1 = reg_705;
assign ins_data_tmp_load_235_toint_fu_2324_p1 = reg_709;
assign ins_data_tmp_load_236_toint_fu_2328_p1 = reg_713;
assign ins_data_tmp_load_237_toint_fu_2332_p1 = reg_717;
assign ins_data_tmp_load_238_toint_fu_2336_p1 = reg_721;
assign ins_data_tmp_load_239_toint_fu_2340_p1 = ins_TDATA;
assign ins_data_tmp_load_23_toint_fu_1054_p1 = ins_data_val23_reg_3460;
assign ins_data_tmp_load_240_toint_fu_2391_p1 = reg_669;
assign ins_data_tmp_load_241_toint_fu_2395_p1 = reg_673;
assign ins_data_tmp_load_242_toint_fu_2399_p1 = reg_677;
assign ins_data_tmp_load_243_toint_fu_2403_p1 = reg_681;
assign ins_data_tmp_load_244_toint_fu_2407_p1 = reg_685;
assign ins_data_tmp_load_245_toint_fu_2411_p1 = reg_689;
assign ins_data_tmp_load_246_toint_fu_2415_p1 = reg_693;
assign ins_data_tmp_load_247_toint_fu_2419_p1 = reg_697;
assign ins_data_tmp_load_248_toint_fu_2423_p1 = reg_701;
assign ins_data_tmp_load_249_toint_fu_2427_p1 = reg_705;
assign ins_data_tmp_load_24_toint_fu_1057_p1 = ins_data_val24_reg_3465;
assign ins_data_tmp_load_250_toint_fu_2431_p1 = reg_709;
assign ins_data_tmp_load_251_toint_fu_2435_p1 = reg_713;
assign ins_data_tmp_load_252_toint_fu_2439_p1 = reg_717;
assign ins_data_tmp_load_253_toint_fu_2443_p1 = reg_721;
assign ins_data_tmp_load_254_toint_fu_2447_p1 = ins_TDATA;
assign ins_data_tmp_load_255_toint_fu_2498_p1 = reg_669;
assign ins_data_tmp_load_256_toint_fu_2502_p1 = reg_673;
assign ins_data_tmp_load_257_toint_fu_2506_p1 = reg_677;
assign ins_data_tmp_load_258_toint_fu_2510_p1 = reg_681;
assign ins_data_tmp_load_259_toint_fu_2514_p1 = reg_685;
assign ins_data_tmp_load_25_toint_fu_1060_p1 = ins_data_val25_reg_3470;
assign ins_data_tmp_load_260_toint_fu_2518_p1 = reg_689;
assign ins_data_tmp_load_261_toint_fu_2522_p1 = reg_693;
assign ins_data_tmp_load_262_toint_fu_2526_p1 = reg_697;
assign ins_data_tmp_load_263_toint_fu_2530_p1 = reg_701;
assign ins_data_tmp_load_264_toint_fu_2534_p1 = reg_705;
assign ins_data_tmp_load_265_toint_fu_2538_p1 = reg_709;
assign ins_data_tmp_load_266_toint_fu_2542_p1 = reg_713;
assign ins_data_tmp_load_267_toint_fu_2546_p1 = reg_717;
assign ins_data_tmp_load_268_toint_fu_2550_p1 = reg_721;
assign ins_data_tmp_load_269_toint_fu_2554_p1 = ins_TDATA;
assign ins_data_tmp_load_26_toint_fu_1063_p1 = ins_data_val26_reg_3475;
assign ins_data_tmp_load_270_toint_fu_2604_p1 = reg_669;
assign ins_data_tmp_load_271_toint_fu_2608_p1 = reg_673;
assign ins_data_tmp_load_272_toint_fu_2612_p1 = reg_677;
assign ins_data_tmp_load_273_toint_fu_2616_p1 = reg_681;
assign ins_data_tmp_load_274_toint_fu_2620_p1 = reg_685;
assign ins_data_tmp_load_275_toint_fu_2624_p1 = reg_689;
assign ins_data_tmp_load_276_toint_fu_2628_p1 = reg_693;
assign ins_data_tmp_load_277_toint_fu_2632_p1 = reg_697;
assign ins_data_tmp_load_278_toint_fu_2636_p1 = reg_701;
assign ins_data_tmp_load_279_toint_fu_2640_p1 = reg_705;
assign ins_data_tmp_load_27_toint_fu_1066_p1 = ins_data_val27_reg_3480;
assign ins_data_tmp_load_280_toint_fu_2644_p1 = reg_709;
assign ins_data_tmp_load_281_toint_fu_2648_p1 = reg_713;
assign ins_data_tmp_load_282_toint_fu_2652_p1 = reg_717;
assign ins_data_tmp_load_283_toint_fu_2656_p1 = reg_721;
assign ins_data_tmp_load_284_toint_fu_2660_p1 = ins_TDATA;
assign ins_data_tmp_load_285_toint_fu_2710_p1 = reg_669;
assign ins_data_tmp_load_286_toint_fu_2714_p1 = reg_673;
assign ins_data_tmp_load_287_toint_fu_2718_p1 = reg_677;
assign ins_data_tmp_load_288_toint_fu_2722_p1 = reg_681;
assign ins_data_tmp_load_289_toint_fu_2726_p1 = reg_685;
assign ins_data_tmp_load_28_toint_fu_1069_p1 = ins_data_val28_reg_3485;
assign ins_data_tmp_load_290_toint_fu_2730_p1 = reg_689;
assign ins_data_tmp_load_291_toint_fu_2734_p1 = reg_693;
assign ins_data_tmp_load_292_toint_fu_2738_p1 = reg_697;
assign ins_data_tmp_load_293_toint_fu_2742_p1 = reg_701;
assign ins_data_tmp_load_294_toint_fu_2746_p1 = reg_705;
assign ins_data_tmp_load_295_toint_fu_2750_p1 = reg_709;
assign ins_data_tmp_load_296_toint_fu_2754_p1 = reg_713;
assign ins_data_tmp_load_297_toint_fu_2758_p1 = reg_717;
assign ins_data_tmp_load_298_toint_fu_2762_p1 = reg_721;
assign ins_data_tmp_load_299_toint_fu_2790_p1 = ins_TDATA;
assign ins_data_tmp_load_29_toint_fu_1072_p1 = ins_data_val29_reg_3490;
assign ins_data_tmp_load_2_toint_fu_745_p1 = reg_677;
assign ins_data_tmp_load_30_toint_fu_843_p1 = ins_data_val30_reg_3495;
assign ins_data_tmp_load_31_toint_fu_846_p1 = ins_data_val31_reg_3500;
assign ins_data_tmp_load_32_toint_fu_849_p1 = ins_data_val32_reg_3505;
assign ins_data_tmp_load_33_toint_fu_852_p1 = ins_data_val33_reg_3510;
assign ins_data_tmp_load_34_toint_fu_855_p1 = ins_data_val34_reg_3515;
assign ins_data_tmp_load_35_toint_fu_858_p1 = ins_data_val35_reg_3520;
assign ins_data_tmp_load_36_toint_fu_861_p1 = ins_data_val36_reg_3525;
assign ins_data_tmp_load_37_toint_fu_864_p1 = ins_data_val37_reg_3530;
assign ins_data_tmp_load_38_toint_fu_867_p1 = ins_data_val38_reg_3535;
assign ins_data_tmp_load_39_toint_fu_870_p1 = ins_data_val39_reg_3540;
assign ins_data_tmp_load_3_toint_fu_749_p1 = reg_681;
assign ins_data_tmp_load_40_toint_fu_873_p1 = ins_data_val40_reg_3545;
assign ins_data_tmp_load_41_toint_fu_876_p1 = ins_data_val41_reg_3550;
assign ins_data_tmp_load_42_toint_fu_879_p1 = ins_data_val42_reg_3555;
assign ins_data_tmp_load_43_toint_fu_882_p1 = ins_data_val43_reg_3560;
assign ins_data_tmp_load_44_toint_fu_885_p1 = ins_data_val44_reg_3565;
assign ins_data_tmp_load_45_toint_fu_1122_p1 = ins_data_val45_reg_3570;
assign ins_data_tmp_load_46_toint_fu_1125_p1 = ins_data_val46_reg_3575;
assign ins_data_tmp_load_47_toint_fu_1128_p1 = ins_data_val47_reg_3580;
assign ins_data_tmp_load_48_toint_fu_1131_p1 = ins_data_val48_reg_3585;
assign ins_data_tmp_load_49_toint_fu_1134_p1 = ins_data_val49_reg_3590;
assign ins_data_tmp_load_4_toint_fu_753_p1 = reg_685;
assign ins_data_tmp_load_50_toint_fu_1137_p1 = ins_data_val50_reg_3595;
assign ins_data_tmp_load_51_toint_fu_1140_p1 = ins_data_val51_reg_3600;
assign ins_data_tmp_load_52_toint_fu_1143_p1 = ins_data_val52_reg_3605;
assign ins_data_tmp_load_53_toint_fu_1146_p1 = ins_data_val53_reg_3610;
assign ins_data_tmp_load_54_toint_fu_1149_p1 = ins_data_val54_reg_3615;
assign ins_data_tmp_load_55_toint_fu_1152_p1 = ins_data_val55_reg_3620;
assign ins_data_tmp_load_56_toint_fu_1155_p1 = ins_data_val56_reg_3625;
assign ins_data_tmp_load_57_toint_fu_1158_p1 = ins_data_val57_reg_3630;
assign ins_data_tmp_load_58_toint_fu_1161_p1 = ins_data_val58_reg_3635;
assign ins_data_tmp_load_59_toint_fu_1164_p1 = ins_data_val59_reg_3640;
assign ins_data_tmp_load_5_toint_fu_757_p1 = reg_689;
assign ins_data_tmp_load_60_toint_fu_935_p1 = ins_data_val60_reg_3645;
assign ins_data_tmp_load_61_toint_fu_938_p1 = ins_data_val61_reg_3650;
assign ins_data_tmp_load_62_toint_fu_941_p1 = ins_data_val62_reg_3655;
assign ins_data_tmp_load_63_toint_fu_944_p1 = ins_data_val63_reg_3660;
assign ins_data_tmp_load_64_toint_fu_947_p1 = ins_data_val64_reg_3665;
assign ins_data_tmp_load_65_toint_fu_950_p1 = ins_data_val65_reg_3670;
assign ins_data_tmp_load_66_toint_fu_953_p1 = ins_data_val66_reg_3675;
assign ins_data_tmp_load_67_toint_fu_956_p1 = ins_data_val67_reg_3680;
assign ins_data_tmp_load_68_toint_fu_959_p1 = ins_data_val68_reg_3685;
assign ins_data_tmp_load_69_toint_fu_962_p1 = ins_data_val69_reg_3690;
assign ins_data_tmp_load_6_toint_fu_761_p1 = reg_693;
assign ins_data_tmp_load_70_toint_fu_965_p1 = ins_data_val70_reg_3695;
assign ins_data_tmp_load_71_toint_fu_968_p1 = ins_data_val71_reg_3706;
assign ins_data_tmp_load_72_toint_fu_971_p1 = reg_669;
assign ins_data_tmp_load_73_toint_fu_975_p1 = reg_673;
assign ins_data_tmp_load_74_toint_fu_979_p1 = ins_TDATA;
assign ins_data_tmp_load_75_toint_fu_1214_p1 = reg_669;
assign ins_data_tmp_load_76_toint_fu_1218_p1 = reg_673;
assign ins_data_tmp_load_77_toint_fu_1222_p1 = reg_677;
assign ins_data_tmp_load_78_toint_fu_1226_p1 = reg_681;
assign ins_data_tmp_load_79_toint_fu_1230_p1 = reg_685;
assign ins_data_tmp_load_7_toint_fu_765_p1 = reg_697;
assign ins_data_tmp_load_80_toint_fu_1234_p1 = reg_689;
assign ins_data_tmp_load_81_toint_fu_1238_p1 = reg_693;
assign ins_data_tmp_load_82_toint_fu_1242_p1 = reg_697;
assign ins_data_tmp_load_83_toint_fu_1246_p1 = reg_701;
assign ins_data_tmp_load_84_toint_fu_1250_p1 = reg_705;
assign ins_data_tmp_load_85_toint_fu_1254_p1 = reg_709;
assign ins_data_tmp_load_86_toint_fu_1258_p1 = reg_713;
assign ins_data_tmp_load_87_toint_fu_1262_p1 = reg_717;
assign ins_data_tmp_load_88_toint_fu_1266_p1 = reg_721;
assign ins_data_tmp_load_89_toint_fu_1270_p1 = ins_TDATA;
assign ins_data_tmp_load_8_toint_fu_769_p1 = reg_701;
assign ins_data_tmp_load_90_toint_fu_1321_p1 = reg_669;
assign ins_data_tmp_load_91_toint_fu_1325_p1 = reg_673;
assign ins_data_tmp_load_92_toint_fu_1329_p1 = reg_677;
assign ins_data_tmp_load_93_toint_fu_1333_p1 = reg_681;
assign ins_data_tmp_load_94_toint_fu_1337_p1 = reg_685;
assign ins_data_tmp_load_95_toint_fu_1341_p1 = reg_689;
assign ins_data_tmp_load_96_toint_fu_1345_p1 = reg_693;
assign ins_data_tmp_load_97_toint_fu_1349_p1 = reg_697;
assign ins_data_tmp_load_98_toint_fu_1353_p1 = reg_701;
assign ins_data_tmp_load_99_toint_fu_1357_p1 = reg_705;
assign ins_data_tmp_load_9_toint_fu_773_p1 = reg_705;
assign ins_data_tmp_load_toint_fu_737_p1 = reg_669;
assign outs_TDEST = ins_dest_V_val_reg_3849;
assign outs_TID = ins_id_V_val_reg_3844;
assign outs_TKEEP = ins_keep_V_val_reg_3824;
assign outs_TSTRB = ins_strb_V_val_reg_3829;
assign outs_TUSER = ins_user_V_val_reg_3834;
assign rez_addr959960_part_set_fu_830_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_fu_796_p16}};
assign rez_addr_10932933_part_set_fu_1736_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_10_fu_1702_p16}};
assign rez_addr_11929930_part_set_fu_1843_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_11_fu_1809_p16}};
assign rez_addr_12926927_part_set_fu_1950_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_12_fu_1916_p16}};
assign rez_addr_13923924_part_set_fu_2057_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_13_fu_2023_p16}};
assign rez_addr_14920921_part_set_fu_2164_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_14_fu_2130_p16}};
assign rez_addr_15917918_part_set_fu_2271_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_15_fu_2237_p16}};
assign rez_addr_16914915_part_set_fu_2378_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_16_fu_2344_p16}};
assign rez_addr_17911912_part_set_fu_2485_p5 = {{reg_725[32'd575 : 32'd480]}, {tmp_17_fu_2451_p16}};
assign rez_addr_18908909_part_set_fu_2592_p5 = {{data_array_load_1_reg_3743[32'd575 : 32'd480]}, {tmp_18_fu_2558_p16}};
assign rez_addr_1956957_part_set_fu_1109_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_2_fu_1075_p16}};
assign rez_addr_19905906_part_set_fu_2698_p5 = {{data_array_load_2_reg_3722[32'd575 : 32'd480]}, {tmp_19_fu_2664_p16}};
assign rez_addr_20902903_part_set_fu_2828_p5 = {{data_array_load_3_reg_3759[32'd575 : 32'd480]}, {tmp_20_fu_2794_p16}};
assign rez_addr_3953954_part_set_fu_922_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_3_fu_888_p16}};
assign rez_addr_4950951_part_set_fu_1201_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_4_fu_1167_p16}};
assign rez_addr_5947948_part_set_fu_1017_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_5_fu_983_p16}};
assign rez_addr_6944945_part_set_fu_1308_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_6_fu_1274_p16}};
assign rez_addr_7941942_part_set_fu_1415_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_7_fu_1381_p16}};
assign rez_addr_8938939_part_set_fu_1522_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_8_fu_1488_p16}};
assign rez_addr_9935936_part_set_fu_1629_p5 = {{ap_const_lv576_lc_1[32'd575 : 32'd480]}, {tmp_9_fu_1595_p16}};
assign t_load_10_fu_3280_p1 = grp_fu_639_p4;
assign t_load_11_fu_3295_p1 = grp_fu_639_p4;
assign t_load_12_fu_3310_p1 = grp_fu_639_p4;
assign t_load_13_fu_3325_p1 = grp_fu_639_p4;
assign t_load_14_fu_3340_p1 = grp_fu_639_p4;
assign t_load_15_fu_3355_p1 = grp_fu_639_p4;
assign t_load_16_fu_3370_p1 = grp_fu_639_p4;
assign t_load_17_fu_3385_p1 = grp_fu_639_p4;
assign t_load_18_fu_3400_p1 = grp_fu_639_p4;
assign t_load_1_fu_3145_p1 = grp_fu_639_p4;
assign t_load_2_fu_3160_p1 = grp_fu_639_p4;
assign t_load_3_fu_3175_p1 = grp_fu_639_p4;
assign t_load_4_fu_3190_p1 = grp_fu_639_p4;
assign t_load_5_fu_3205_p1 = grp_fu_639_p4;
assign t_load_6_fu_3220_p1 = grp_fu_639_p4;
assign t_load_7_fu_3235_p1 = grp_fu_639_p4;
assign t_load_8_fu_3250_p1 = grp_fu_639_p4;
assign t_load_9_fu_3265_p1 = grp_fu_639_p4;
assign t_load_fu_3115_p1 = grp_fu_639_p4;
assign t_load_s_fu_3130_p1 = grp_fu_639_p4;
assign t_write_assign_toint_fu_3081_p1 = grp_fu_618_p2;
assign tmp_10_fu_1702_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_149_toint_fu_1698_p1}, {ins_data_tmp_load_148_toint_fu_1694_p1}}, {ins_data_tmp_load_147_toint_fu_1690_p1}}, {ins_data_tmp_load_146_toint_fu_1686_p1}}, {ins_data_tmp_load_145_toint_fu_1682_p1}}, {ins_data_tmp_load_144_toint_fu_1678_p1}}, {ins_data_tmp_load_143_toint_fu_1674_p1}}, {ins_data_tmp_load_142_toint_fu_1670_p1}}, {ins_data_tmp_load_141_toint_fu_1666_p1}}, {ins_data_tmp_load_140_toint_fu_1662_p1}}, {ins_data_tmp_load_139_toint_fu_1658_p1}}, {ins_data_tmp_load_138_toint_fu_1654_p1}}, {ins_data_tmp_load_137_toint_fu_1650_p1}}, {ins_data_tmp_load_136_toint_fu_1646_p1}}, {ins_data_tmp_load_135_toint_fu_1642_p1}};
assign tmp_11_fu_1809_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_164_toint_fu_1805_p1}, {ins_data_tmp_load_163_toint_fu_1801_p1}}, {ins_data_tmp_load_162_toint_fu_1797_p1}}, {ins_data_tmp_load_161_toint_fu_1793_p1}}, {ins_data_tmp_load_160_toint_fu_1789_p1}}, {ins_data_tmp_load_159_toint_fu_1785_p1}}, {ins_data_tmp_load_158_toint_fu_1781_p1}}, {ins_data_tmp_load_157_toint_fu_1777_p1}}, {ins_data_tmp_load_156_toint_fu_1773_p1}}, {ins_data_tmp_load_155_toint_fu_1769_p1}}, {ins_data_tmp_load_154_toint_fu_1765_p1}}, {ins_data_tmp_load_153_toint_fu_1761_p1}}, {ins_data_tmp_load_152_toint_fu_1757_p1}}, {ins_data_tmp_load_151_toint_fu_1753_p1}}, {ins_data_tmp_load_150_toint_fu_1749_p1}};
assign tmp_12_fu_1916_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_179_toint_fu_1912_p1}, {ins_data_tmp_load_178_toint_fu_1908_p1}}, {ins_data_tmp_load_177_toint_fu_1904_p1}}, {ins_data_tmp_load_176_toint_fu_1900_p1}}, {ins_data_tmp_load_175_toint_fu_1896_p1}}, {ins_data_tmp_load_174_toint_fu_1892_p1}}, {ins_data_tmp_load_173_toint_fu_1888_p1}}, {ins_data_tmp_load_172_toint_fu_1884_p1}}, {ins_data_tmp_load_171_toint_fu_1880_p1}}, {ins_data_tmp_load_170_toint_fu_1876_p1}}, {ins_data_tmp_load_169_toint_fu_1872_p1}}, {ins_data_tmp_load_168_toint_fu_1868_p1}}, {ins_data_tmp_load_167_toint_fu_1864_p1}}, {ins_data_tmp_load_166_toint_fu_1860_p1}}, {ins_data_tmp_load_165_toint_fu_1856_p1}};
assign tmp_13_fu_2023_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_194_toint_fu_2019_p1}, {ins_data_tmp_load_193_toint_fu_2015_p1}}, {ins_data_tmp_load_192_toint_fu_2011_p1}}, {ins_data_tmp_load_191_toint_fu_2007_p1}}, {ins_data_tmp_load_190_toint_fu_2003_p1}}, {ins_data_tmp_load_189_toint_fu_1999_p1}}, {ins_data_tmp_load_188_toint_fu_1995_p1}}, {ins_data_tmp_load_187_toint_fu_1991_p1}}, {ins_data_tmp_load_186_toint_fu_1987_p1}}, {ins_data_tmp_load_185_toint_fu_1983_p1}}, {ins_data_tmp_load_184_toint_fu_1979_p1}}, {ins_data_tmp_load_183_toint_fu_1975_p1}}, {ins_data_tmp_load_182_toint_fu_1971_p1}}, {ins_data_tmp_load_181_toint_fu_1967_p1}}, {ins_data_tmp_load_180_toint_fu_1963_p1}};
assign tmp_14_fu_2130_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_209_toint_fu_2126_p1}, {ins_data_tmp_load_208_toint_fu_2122_p1}}, {ins_data_tmp_load_207_toint_fu_2118_p1}}, {ins_data_tmp_load_206_toint_fu_2114_p1}}, {ins_data_tmp_load_205_toint_fu_2110_p1}}, {ins_data_tmp_load_204_toint_fu_2106_p1}}, {ins_data_tmp_load_203_toint_fu_2102_p1}}, {ins_data_tmp_load_202_toint_fu_2098_p1}}, {ins_data_tmp_load_201_toint_fu_2094_p1}}, {ins_data_tmp_load_200_toint_fu_2090_p1}}, {ins_data_tmp_load_199_toint_fu_2086_p1}}, {ins_data_tmp_load_198_toint_fu_2082_p1}}, {ins_data_tmp_load_197_toint_fu_2078_p1}}, {ins_data_tmp_load_196_toint_fu_2074_p1}}, {ins_data_tmp_load_195_toint_fu_2070_p1}};
assign tmp_15_fu_2237_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_224_toint_fu_2233_p1}, {ins_data_tmp_load_223_toint_fu_2229_p1}}, {ins_data_tmp_load_222_toint_fu_2225_p1}}, {ins_data_tmp_load_221_toint_fu_2221_p1}}, {ins_data_tmp_load_220_toint_fu_2217_p1}}, {ins_data_tmp_load_219_toint_fu_2213_p1}}, {ins_data_tmp_load_218_toint_fu_2209_p1}}, {ins_data_tmp_load_217_toint_fu_2205_p1}}, {ins_data_tmp_load_216_toint_fu_2201_p1}}, {ins_data_tmp_load_215_toint_fu_2197_p1}}, {ins_data_tmp_load_214_toint_fu_2193_p1}}, {ins_data_tmp_load_213_toint_fu_2189_p1}}, {ins_data_tmp_load_212_toint_fu_2185_p1}}, {ins_data_tmp_load_211_toint_fu_2181_p1}}, {ins_data_tmp_load_210_toint_fu_2177_p1}};
assign tmp_16_fu_2344_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_239_toint_fu_2340_p1}, {ins_data_tmp_load_238_toint_fu_2336_p1}}, {ins_data_tmp_load_237_toint_fu_2332_p1}}, {ins_data_tmp_load_236_toint_fu_2328_p1}}, {ins_data_tmp_load_235_toint_fu_2324_p1}}, {ins_data_tmp_load_234_toint_fu_2320_p1}}, {ins_data_tmp_load_233_toint_fu_2316_p1}}, {ins_data_tmp_load_232_toint_fu_2312_p1}}, {ins_data_tmp_load_231_toint_fu_2308_p1}}, {ins_data_tmp_load_230_toint_fu_2304_p1}}, {ins_data_tmp_load_229_toint_fu_2300_p1}}, {ins_data_tmp_load_228_toint_fu_2296_p1}}, {ins_data_tmp_load_227_toint_fu_2292_p1}}, {ins_data_tmp_load_226_toint_fu_2288_p1}}, {ins_data_tmp_load_225_toint_fu_2284_p1}};
assign tmp_17_fu_2451_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_254_toint_fu_2447_p1}, {ins_data_tmp_load_253_toint_fu_2443_p1}}, {ins_data_tmp_load_252_toint_fu_2439_p1}}, {ins_data_tmp_load_251_toint_fu_2435_p1}}, {ins_data_tmp_load_250_toint_fu_2431_p1}}, {ins_data_tmp_load_249_toint_fu_2427_p1}}, {ins_data_tmp_load_248_toint_fu_2423_p1}}, {ins_data_tmp_load_247_toint_fu_2419_p1}}, {ins_data_tmp_load_246_toint_fu_2415_p1}}, {ins_data_tmp_load_245_toint_fu_2411_p1}}, {ins_data_tmp_load_244_toint_fu_2407_p1}}, {ins_data_tmp_load_243_toint_fu_2403_p1}}, {ins_data_tmp_load_242_toint_fu_2399_p1}}, {ins_data_tmp_load_241_toint_fu_2395_p1}}, {ins_data_tmp_load_240_toint_fu_2391_p1}};
assign tmp_18_fu_2558_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_269_toint_fu_2554_p1}, {ins_data_tmp_load_268_toint_fu_2550_p1}}, {ins_data_tmp_load_267_toint_fu_2546_p1}}, {ins_data_tmp_load_266_toint_fu_2542_p1}}, {ins_data_tmp_load_265_toint_fu_2538_p1}}, {ins_data_tmp_load_264_toint_fu_2534_p1}}, {ins_data_tmp_load_263_toint_fu_2530_p1}}, {ins_data_tmp_load_262_toint_fu_2526_p1}}, {ins_data_tmp_load_261_toint_fu_2522_p1}}, {ins_data_tmp_load_260_toint_fu_2518_p1}}, {ins_data_tmp_load_259_toint_fu_2514_p1}}, {ins_data_tmp_load_258_toint_fu_2510_p1}}, {ins_data_tmp_load_257_toint_fu_2506_p1}}, {ins_data_tmp_load_256_toint_fu_2502_p1}}, {ins_data_tmp_load_255_toint_fu_2498_p1}};
assign tmp_19_fu_2664_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_284_toint_fu_2660_p1}, {ins_data_tmp_load_283_toint_fu_2656_p1}}, {ins_data_tmp_load_282_toint_fu_2652_p1}}, {ins_data_tmp_load_281_toint_fu_2648_p1}}, {ins_data_tmp_load_280_toint_fu_2644_p1}}, {ins_data_tmp_load_279_toint_fu_2640_p1}}, {ins_data_tmp_load_278_toint_fu_2636_p1}}, {ins_data_tmp_load_277_toint_fu_2632_p1}}, {ins_data_tmp_load_276_toint_fu_2628_p1}}, {ins_data_tmp_load_275_toint_fu_2624_p1}}, {ins_data_tmp_load_274_toint_fu_2620_p1}}, {ins_data_tmp_load_273_toint_fu_2616_p1}}, {ins_data_tmp_load_272_toint_fu_2612_p1}}, {ins_data_tmp_load_271_toint_fu_2608_p1}}, {ins_data_tmp_load_270_toint_fu_2604_p1}};
assign tmp_1_fu_2852_p1 = i1_reg_418;
assign tmp_20_fu_2794_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_299_toint_fu_2790_p1}, {ins_data_tmp_load_298_toint_fu_2762_p1}}, {ins_data_tmp_load_297_toint_fu_2758_p1}}, {ins_data_tmp_load_296_toint_fu_2754_p1}}, {ins_data_tmp_load_295_toint_fu_2750_p1}}, {ins_data_tmp_load_294_toint_fu_2746_p1}}, {ins_data_tmp_load_293_toint_fu_2742_p1}}, {ins_data_tmp_load_292_toint_fu_2738_p1}}, {ins_data_tmp_load_291_toint_fu_2734_p1}}, {ins_data_tmp_load_290_toint_fu_2730_p1}}, {ins_data_tmp_load_289_toint_fu_2726_p1}}, {ins_data_tmp_load_288_toint_fu_2722_p1}}, {ins_data_tmp_load_287_toint_fu_2718_p1}}, {ins_data_tmp_load_286_toint_fu_2714_p1}}, {ins_data_tmp_load_285_toint_fu_2710_p1}};
assign tmp_21_fu_3093_p4 = {{{beta_write_assign_toint_fu_3089_p1}, {gamma_write_assign_toint_fu_3085_p1}}, {t_write_assign_toint_fu_3081_p1}};
assign tmp_22_fu_2857_p1 = data_array_q0[31:0];
assign tmp_2_fu_1075_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_29_toint_fu_1072_p1}, {ins_data_tmp_load_28_toint_fu_1069_p1}}, {ins_data_tmp_load_27_toint_fu_1066_p1}}, {ins_data_tmp_load_26_toint_fu_1063_p1}}, {ins_data_tmp_load_25_toint_fu_1060_p1}}, {ins_data_tmp_load_24_toint_fu_1057_p1}}, {ins_data_tmp_load_23_toint_fu_1054_p1}}, {ins_data_tmp_load_22_toint_fu_1051_p1}}, {ins_data_tmp_load_21_toint_fu_1048_p1}}, {ins_data_tmp_load_20_toint_fu_1045_p1}}, {ins_data_tmp_load_19_toint_fu_1042_p1}}, {ins_data_tmp_load_18_toint_fu_1039_p1}}, {ins_data_tmp_load_17_toint_fu_1036_p1}}, {ins_data_tmp_load_16_toint_fu_1033_p1}}, {ins_data_tmp_load_15_toint_fu_1030_p1}};
assign tmp_3_fu_888_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_44_toint_fu_885_p1}, {ins_data_tmp_load_43_toint_fu_882_p1}}, {ins_data_tmp_load_42_toint_fu_879_p1}}, {ins_data_tmp_load_41_toint_fu_876_p1}}, {ins_data_tmp_load_40_toint_fu_873_p1}}, {ins_data_tmp_load_39_toint_fu_870_p1}}, {ins_data_tmp_load_38_toint_fu_867_p1}}, {ins_data_tmp_load_37_toint_fu_864_p1}}, {ins_data_tmp_load_36_toint_fu_861_p1}}, {ins_data_tmp_load_35_toint_fu_858_p1}}, {ins_data_tmp_load_34_toint_fu_855_p1}}, {ins_data_tmp_load_33_toint_fu_852_p1}}, {ins_data_tmp_load_32_toint_fu_849_p1}}, {ins_data_tmp_load_31_toint_fu_846_p1}}, {ins_data_tmp_load_30_toint_fu_843_p1}};
assign tmp_4_fu_1167_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_59_toint_fu_1164_p1}, {ins_data_tmp_load_58_toint_fu_1161_p1}}, {ins_data_tmp_load_57_toint_fu_1158_p1}}, {ins_data_tmp_load_56_toint_fu_1155_p1}}, {ins_data_tmp_load_55_toint_fu_1152_p1}}, {ins_data_tmp_load_54_toint_fu_1149_p1}}, {ins_data_tmp_load_53_toint_fu_1146_p1}}, {ins_data_tmp_load_52_toint_fu_1143_p1}}, {ins_data_tmp_load_51_toint_fu_1140_p1}}, {ins_data_tmp_load_50_toint_fu_1137_p1}}, {ins_data_tmp_load_49_toint_fu_1134_p1}}, {ins_data_tmp_load_48_toint_fu_1131_p1}}, {ins_data_tmp_load_47_toint_fu_1128_p1}}, {ins_data_tmp_load_46_toint_fu_1125_p1}}, {ins_data_tmp_load_45_toint_fu_1122_p1}};
assign tmp_5_fu_983_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_74_toint_fu_979_p1}, {ins_data_tmp_load_73_toint_fu_975_p1}}, {ins_data_tmp_load_72_toint_fu_971_p1}}, {ins_data_tmp_load_71_toint_fu_968_p1}}, {ins_data_tmp_load_70_toint_fu_965_p1}}, {ins_data_tmp_load_69_toint_fu_962_p1}}, {ins_data_tmp_load_68_toint_fu_959_p1}}, {ins_data_tmp_load_67_toint_fu_956_p1}}, {ins_data_tmp_load_66_toint_fu_953_p1}}, {ins_data_tmp_load_65_toint_fu_950_p1}}, {ins_data_tmp_load_64_toint_fu_947_p1}}, {ins_data_tmp_load_63_toint_fu_944_p1}}, {ins_data_tmp_load_62_toint_fu_941_p1}}, {ins_data_tmp_load_61_toint_fu_938_p1}}, {ins_data_tmp_load_60_toint_fu_935_p1}};
assign tmp_61_neg_i_fu_3071_p2 = (tmp_61_to_int_i_fu_3068_p1 ^ ap_const_lv32_80000000);
assign tmp_61_to_int_i_fu_3068_p1 = ap_reg_ppstg_tmp_25_i_reg_4275_pp0_it76;
assign tmp_6_fu_1274_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_89_toint_fu_1270_p1}, {ins_data_tmp_load_88_toint_fu_1266_p1}}, {ins_data_tmp_load_87_toint_fu_1262_p1}}, {ins_data_tmp_load_86_toint_fu_1258_p1}}, {ins_data_tmp_load_85_toint_fu_1254_p1}}, {ins_data_tmp_load_84_toint_fu_1250_p1}}, {ins_data_tmp_load_83_toint_fu_1246_p1}}, {ins_data_tmp_load_82_toint_fu_1242_p1}}, {ins_data_tmp_load_81_toint_fu_1238_p1}}, {ins_data_tmp_load_80_toint_fu_1234_p1}}, {ins_data_tmp_load_79_toint_fu_1230_p1}}, {ins_data_tmp_load_78_toint_fu_1226_p1}}, {ins_data_tmp_load_77_toint_fu_1222_p1}}, {ins_data_tmp_load_76_toint_fu_1218_p1}}, {ins_data_tmp_load_75_toint_fu_1214_p1}};
assign tmp_7_fu_1381_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_104_toint_fu_1377_p1}, {ins_data_tmp_load_103_toint_fu_1373_p1}}, {ins_data_tmp_load_102_toint_fu_1369_p1}}, {ins_data_tmp_load_101_toint_fu_1365_p1}}, {ins_data_tmp_load_100_toint_fu_1361_p1}}, {ins_data_tmp_load_99_toint_fu_1357_p1}}, {ins_data_tmp_load_98_toint_fu_1353_p1}}, {ins_data_tmp_load_97_toint_fu_1349_p1}}, {ins_data_tmp_load_96_toint_fu_1345_p1}}, {ins_data_tmp_load_95_toint_fu_1341_p1}}, {ins_data_tmp_load_94_toint_fu_1337_p1}}, {ins_data_tmp_load_93_toint_fu_1333_p1}}, {ins_data_tmp_load_92_toint_fu_1329_p1}}, {ins_data_tmp_load_91_toint_fu_1325_p1}}, {ins_data_tmp_load_90_toint_fu_1321_p1}};
assign tmp_8_fu_1488_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_119_toint_fu_1484_p1}, {ins_data_tmp_load_118_toint_fu_1480_p1}}, {ins_data_tmp_load_117_toint_fu_1476_p1}}, {ins_data_tmp_load_116_toint_fu_1472_p1}}, {ins_data_tmp_load_115_toint_fu_1468_p1}}, {ins_data_tmp_load_114_toint_fu_1464_p1}}, {ins_data_tmp_load_113_toint_fu_1460_p1}}, {ins_data_tmp_load_112_toint_fu_1456_p1}}, {ins_data_tmp_load_111_toint_fu_1452_p1}}, {ins_data_tmp_load_110_toint_fu_1448_p1}}, {ins_data_tmp_load_109_toint_fu_1444_p1}}, {ins_data_tmp_load_108_toint_fu_1440_p1}}, {ins_data_tmp_load_107_toint_fu_1436_p1}}, {ins_data_tmp_load_106_toint_fu_1432_p1}}, {ins_data_tmp_load_105_toint_fu_1428_p1}};
assign tmp_9_fu_1595_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_134_toint_fu_1591_p1}, {ins_data_tmp_load_133_toint_fu_1587_p1}}, {ins_data_tmp_load_132_toint_fu_1583_p1}}, {ins_data_tmp_load_131_toint_fu_1579_p1}}, {ins_data_tmp_load_130_toint_fu_1575_p1}}, {ins_data_tmp_load_129_toint_fu_1571_p1}}, {ins_data_tmp_load_128_toint_fu_1567_p1}}, {ins_data_tmp_load_127_toint_fu_1563_p1}}, {ins_data_tmp_load_126_toint_fu_1559_p1}}, {ins_data_tmp_load_125_toint_fu_1555_p1}}, {ins_data_tmp_load_124_toint_fu_1551_p1}}, {ins_data_tmp_load_123_toint_fu_1547_p1}}, {ins_data_tmp_load_122_toint_fu_1543_p1}}, {ins_data_tmp_load_121_toint_fu_1539_p1}}, {ins_data_tmp_load_120_toint_fu_1535_p1}};
assign tmp_fu_796_p16 = {{{{{{{{{{{{{{{ins_data_tmp_load_14_toint_fu_793_p1}, {ins_data_tmp_load_13_toint_fu_789_p1}}, {ins_data_tmp_load_12_toint_fu_785_p1}}, {ins_data_tmp_load_11_toint_fu_781_p1}}, {ins_data_tmp_load_10_toint_fu_777_p1}}, {ins_data_tmp_load_9_toint_fu_773_p1}}, {ins_data_tmp_load_8_toint_fu_769_p1}}, {ins_data_tmp_load_7_toint_fu_765_p1}}, {ins_data_tmp_load_6_toint_fu_761_p1}}, {ins_data_tmp_load_5_toint_fu_757_p1}}, {ins_data_tmp_load_4_toint_fu_753_p1}}, {ins_data_tmp_load_3_toint_fu_749_p1}}, {ins_data_tmp_load_2_toint_fu_745_p1}}, {ins_data_tmp_load_1_toint_fu_741_p1}}, {ins_data_tmp_load_toint_fu_737_p1}};
assign v0x_assign4_fu_3001_p1 = tmp_22_reg_3869;
assign v0y_assign_fu_3007_p1 = v0y_assign_new_reg_3874;
assign v0z_assign_fu_3013_p1 = v0z_assign_new_reg_3879;
always @ (posedge ap_clk)
begin
data_array_addr_16_reg_3700[4:0] <= 5'b10000;
data_array_addr_18_reg_3711[4:0] <= 5'b10010;
data_array_addr_reg_3717[4:0] <= 5'b00000;
data_array_addr_2_reg_3727[4:0] <= 5'b00010;
data_array_addr_4_reg_3732[4:0] <= 5'b00100;
data_array_addr_17_reg_3737[4:0] <= 5'b10001;
data_array_addr_19_reg_3748[4:0] <= 5'b10011;
data_array_addr_1_reg_3754[4:0] <= 5'b00001;
data_array_addr_3_reg_3764[4:0] <= 5'b00011;
data_array_addr_5_reg_3769[4:0] <= 5'b00101;
data_array_addr_6_reg_3774[4:0] <= 5'b00110;
data_array_addr_7_reg_3779[4:0] <= 5'b00111;
data_array_addr_8_reg_3784[4:0] <= 5'b01000;
data_array_addr_9_reg_3789[4:0] <= 5'b01001;
data_array_addr_10_reg_3794[4:0] <= 5'b01010;
data_array_addr_11_reg_3799[4:0] <= 5'b01011;
data_array_addr_12_reg_3804[4:0] <= 5'b01100;
data_array_addr_13_reg_3809[4:0] <= 5'b01101;
data_array_addr_14_reg_3814[4:0] <= 5'b01110;
data_array_addr_15_reg_3819[4:0] <= 5'b01111;
end
endmodule //tri_intersect
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__CLKBUF_PP_SYMBOL_V
`define SKY130_FD_SC_LS__CLKBUF_PP_SYMBOL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__clkbuf (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__CLKBUF_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPMET1_BLACKBOX_V
`define SKY130_FD_SC_LS__TAPMET1_BLACKBOX_V
/**
* tapmet1: Tap cell with isolated power and ground connections.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__tapmet1 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPMET1_BLACKBOX_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o31ai (
Y ,
A1,
A2,
A3,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31AI_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:14:04 10/01/2015
// Design Name:
// Module Name: freqdiv
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module freqdiv(
input clk,
input rst_n,
output clk_out,
input [1:0] select
);
reg [23:0]counter;
reg out_clk_reg;
reg [23:0]divider;
assign clk_out=out_clk_reg;
always@(posedge clk or negedge rst_n)
begin
if(~rst_n) begin
counter<=24'd0;
out_clk_reg<=1'b0;
end
else
begin
case(select)
2'b0:
begin
divider <= 24'd5;
end
2'b1:
begin
divider <= 24'd5999999;
end
2'b10:
begin
divider <= 24'd5999;
end
2'b11:
begin
divider <= 24'd5;
end
endcase
if(counter==divider)
begin
counter<=24'd000000;
out_clk_reg<=~out_clk_reg;
end
else
begin
counter<=counter+1;
end
end
end
endmodule |
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Data Up-Sizer
// Mirror data for simple accesses.
// Merge data for burst.
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// w_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_9_w_upsizer #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_S_AXI_DATA_WIDTH = 64,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 32,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_REGISTER = 0,
// Clock output data.
// Range: 0, 1
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con.)
parameter integer C_S_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on SI-side.
parameter integer C_M_AXI_BYTES_LOG = 3,
// Log2 of number of 32bit word on MI-side.
parameter integer C_RATIO = 2,
// Up-Sizing ratio for data.
parameter integer C_RATIO_LOG = 1
// Log2 of Up-Sizing ratio for data.
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_valid,
input wire cmd_fix,
input wire cmd_modified,
input wire cmd_complete_wrap,
input wire cmd_packed_wrap,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_first_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_next_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_last_word,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_offset,
input wire [C_M_AXI_BYTES_LOG-1:0] cmd_mask,
input wire [C_S_AXI_BYTES_LOG:0] cmd_step,
input wire [8-1:0] cmd_length,
output wire cmd_ready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for SI-side word lanes on MI-side.
genvar word_cnt;
// Generate variable for intra SI-word byte control (on MI-side) for always pack.
genvar byte_cnt;
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam integer C_NEVER_PACK = 0;
localparam integer C_DEFAULT_PACK = 1;
localparam integer C_ALWAYS_PACK = 2;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Sub-word handling.
wire sel_first_word;
wire first_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] current_word;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_adjusted;
wire [C_RATIO-1:0] current_word_idx;
wire last_beat;
wire last_word;
wire last_word_extra_carry;
wire [C_M_AXI_BYTES_LOG-1:0] cmd_step_i;
// Sub-word handling for the next cycle.
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] pre_next_word_1;
wire [C_M_AXI_BYTES_LOG-1:0] next_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] next_word;
// Burst length handling.
wire first_mi_word;
wire [8-1:0] length_counter_1;
reg [8-1:0] length_counter;
wire [8-1:0] next_length_counter;
// Handle wrap buffering.
wire store_in_wrap_buffer_enabled;
wire store_in_wrap_buffer;
wire ARESET_or_store_in_wrap_buffer;
wire use_wrap_buffer;
reg wrap_buffer_available;
// Detect start of MI word.
wire first_si_in_mi;
// Throttling help signals.
wire word_complete_next_wrap;
wire word_complete_next_wrap_qual;
wire word_complete_next_wrap_valid;
wire word_complete_next_wrap_pop;
wire word_complete_next_wrap_last;
wire word_complete_next_wrap_stall;
wire word_complete_last_word;
wire word_complete_rest;
wire word_complete_rest_qual;
wire word_complete_rest_valid;
wire word_complete_rest_pop;
wire word_complete_rest_last;
wire word_complete_rest_stall;
wire word_completed;
wire word_completed_qualified;
wire cmd_ready_i;
wire pop_si_data;
wire pop_mi_data_i;
wire pop_mi_data;
wire mi_stalling;
// Internal SI side control signals.
wire S_AXI_WREADY_I;
// Internal packed write data.
wire use_expander_data;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wdata_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wrap_qualifier; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_i; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_i; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_buffer;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_last_word_mux;
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_last_word_mux;
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_cmb; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer_q; // For RTL only
reg [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer_q; // For RTL only
wire [C_M_AXI_DATA_WIDTH-1:0] wdata_wrap_buffer;
wire [C_M_AXI_DATA_WIDTH/8-1:0] wstrb_wrap_buffer;
// Internal signals for MI-side.
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA_I;
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_cmb; // For FPGA only
wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_q; // For FPGA only
reg [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB_I;
wire M_AXI_WLAST_I;
wire M_AXI_WVALID_I;
wire M_AXI_WREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Handle interface handshaking:
//
// Data on the MI-side is available when data a complete word has been
// assembled from the data on SI-side (and potentially from any remainder in
// the wrap buffer).
// No data is produced on the MI-side when a unaligned packed wrap is
// encountered, instead it stored in the wrap buffer to be used when the
// last SI-side data beat is received.
//
// The command is popped from the command queue once the last beat on the
// SI-side has been ackowledged.
//
// The packing process is stalled when a new MI-side is completed but not
// yet acknowledged (by ready).
//
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_RATIO_LOG > 1 ) begin : USE_LARGE_UPSIZING
assign cmd_step_i = {{C_RATIO_LOG-1{1'b0}}, cmd_step};
end else begin : NO_LARGE_UPSIZING
assign cmd_step_i = cmd_step;
end
endgenerate
generate
if ( C_FAMILY == "rtl" ||
( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_RTL_WORD_COMPLETED
// Detect when MI-side word is completely assembled.
assign word_completed = ( cmd_fix ) |
( ~cmd_fix & ~cmd_complete_wrap & next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( ~cmd_fix & last_word ) |
( ~cmd_modified ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_completed_qualified = word_completed & cmd_valid & ~store_in_wrap_buffer_enabled;
// RTL equivalent of optimized partial extressions (address wrap for next word).
assign word_complete_next_wrap = ( ~cmd_fix & ~cmd_complete_wrap &
next_word == {C_M_AXI_BYTES_LOG{1'b0}} ) |
( C_PACKING_LEVEL == C_NEVER_PACK );
assign word_complete_next_wrap_qual = word_complete_next_wrap & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_next_wrap_valid = word_complete_next_wrap_qual & S_AXI_WVALID;
assign word_complete_next_wrap_pop = word_complete_next_wrap_valid & M_AXI_WREADY_I;
assign word_complete_next_wrap_last = word_complete_next_wrap_pop & M_AXI_WLAST_I;
assign word_complete_next_wrap_stall = word_complete_next_wrap_valid & ~M_AXI_WREADY_I;
// RTL equivalent of optimized partial extressions (last word and the remaining).
assign word_complete_last_word = last_word & ~cmd_fix;
assign word_complete_rest = word_complete_last_word | cmd_fix | ~cmd_modified;
assign word_complete_rest_qual = word_complete_rest & cmd_valid & ~store_in_wrap_buffer_enabled;
assign word_complete_rest_valid = word_complete_rest_qual & S_AXI_WVALID;
assign word_complete_rest_pop = word_complete_rest_valid & M_AXI_WREADY_I;
assign word_complete_rest_last = word_complete_rest_pop & M_AXI_WLAST_I;
assign word_complete_rest_stall = word_complete_rest_valid & ~M_AXI_WREADY_I;
end else begin : USE_FPGA_WORD_COMPLETED
wire next_word_wrap;
wire sel_word_complete_next_wrap;
wire sel_word_complete_next_wrap_qual;
wire sel_word_complete_next_wrap_stall;
wire sel_last_word;
wire sel_word_complete_rest;
wire sel_word_complete_rest_qual;
wire sel_word_complete_rest_stall;
// Optimize next word address wrap branch of expression.
//
generic_baseblocks_v2_1_0_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE({C_M_AXI_BYTES_LOG{1'b0}}),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) next_word_wrap_inst
(
.CIN(1'b1),
.S(sel_first_word),
.A(pre_next_word_1),
.B(cmd_next_word),
.COUT(next_word_wrap)
);
assign sel_word_complete_next_wrap = ~cmd_fix & ~cmd_complete_wrap;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_inst
(
.CIN(next_word_wrap),
.S(sel_word_complete_next_wrap),
.COUT(word_complete_next_wrap)
);
assign sel_word_complete_next_wrap_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_valid_inst
(
.CIN(word_complete_next_wrap),
.S(sel_word_complete_next_wrap_qual),
.COUT(word_complete_next_wrap_qual)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_qual_inst
(
.CIN(word_complete_next_wrap_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_next_wrap_valid)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_pop_inst
(
.CIN(word_complete_next_wrap_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_next_wrap_pop)
);
assign sel_word_complete_next_wrap_stall = ~M_AXI_WREADY_I;
generic_baseblocks_v2_1_0_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(word_complete_next_wrap_valid),
.I(sel_word_complete_next_wrap_stall),
.O(word_complete_next_wrap_stall)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_last_inst
(
.CIN(word_complete_next_wrap_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_next_wrap_last)
);
// Optimize last word and "rest" branch of expression.
//
assign sel_last_word = ~cmd_fix;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst_2
(
.CIN(last_word_extra_carry),
.S(sel_last_word),
.COUT(word_complete_last_word)
);
assign sel_word_complete_rest = cmd_fix | ~cmd_modified;
generic_baseblocks_v2_1_0_carry_or #
(
.C_FAMILY(C_FAMILY)
) pop_si_data_inst
(
.CIN(word_complete_last_word),
.S(sel_word_complete_rest),
.COUT(word_complete_rest)
);
assign sel_word_complete_rest_qual = cmd_valid & ~store_in_wrap_buffer_enabled;
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_valid_inst
(
.CIN(word_complete_rest),
.S(sel_word_complete_rest_qual),
.COUT(word_complete_rest_qual)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_qual_inst
(
.CIN(word_complete_rest_qual),
.S(S_AXI_WVALID),
.COUT(word_complete_rest_valid)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_pop_inst
(
.CIN(word_complete_rest_valid),
.S(M_AXI_WREADY_I),
.COUT(word_complete_rest_pop)
);
assign sel_word_complete_rest_stall = ~M_AXI_WREADY_I;
generic_baseblocks_v2_1_0_carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_stall_inst
(
.CIN(word_complete_rest_valid),
.I(sel_word_complete_rest_stall),
.O(word_complete_rest_stall)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_rest_last_inst
(
.CIN(word_complete_rest_pop),
.S(M_AXI_WLAST_I),
.COUT(word_complete_rest_last)
);
// Combine the two branches to generate the full signal.
assign word_completed = word_complete_next_wrap | word_complete_rest;
assign word_completed_qualified = word_complete_next_wrap_qual | word_complete_rest_qual;
end
endgenerate
// Pop word from SI-side.
assign S_AXI_WREADY_I = ~mi_stalling & cmd_valid;
assign S_AXI_WREADY = S_AXI_WREADY_I;
// Indicate when there is data available @ MI-side.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_M_WVALID
assign M_AXI_WVALID_I = S_AXI_WVALID & word_completed_qualified;
end else begin : USE_FPGA_M_WVALID
assign M_AXI_WVALID_I = ( word_complete_next_wrap_valid | word_complete_rest_valid);
end
endgenerate
// Get SI-side data.
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER_SI_POP
assign pop_si_data = S_AXI_WVALID & ~mi_stalling & cmd_valid;
end else begin : NO_REGISTER_SI_POP
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_SI
assign pop_si_data = S_AXI_WVALID & S_AXI_WREADY_I;
end else begin : USE_FPGA_POP_SI
assign pop_si_data = ~( word_complete_next_wrap_stall | word_complete_rest_stall ) &
cmd_valid & S_AXI_WVALID;
end
end
endgenerate
// Signal that the command is done (so that it can be poped from command queue).
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_CMD_READY
assign cmd_ready_i = cmd_valid & M_AXI_WLAST_I & pop_mi_data_i;
end else begin : USE_FPGA_CMD_READY
assign cmd_ready_i = ( word_complete_next_wrap_last | word_complete_rest_last);
end
endgenerate
assign cmd_ready = cmd_ready_i;
// Set last upsized word.
assign M_AXI_WLAST_I = S_AXI_WLAST;
/////////////////////////////////////////////////////////////////////////////
// Keep track of data extraction:
//
// Current address is taken form the command buffer for the first data beat
// to handle unaligned Write transactions. After this is the extraction
// address usually calculated from this point.
// FIX transactions uses the same word address for all data beats.
//
// Next word address is generated as current word plus the current step
// size, with masking to facilitate sub-sized wraping. The Mask is all ones
// for normal wraping, and less when sub-sized wraping is used.
//
// The calculated word addresses (current and next) is offseted by the
// current Offset. For sub-sized transaction the Offest points to the least
// significant address of the included data beats. (The least significant
// word is not necessarily the first data to be packed, consider WRAP).
// Offset is only used for sub-sized WRAP transcation that are Complete.
//
// First word is active during the first SI-side data beat.
//
// First MI is set while the entire first MI-side word is processed.
//
// The transaction length is taken from the command buffer combinatorialy
// during the First MI cycle. For each generated MI word it is decreased
// until Last beat is reached.
//
/////////////////////////////////////////////////////////////////////////////
// Select if the offset comes from command queue directly or
// from a counter while when extracting multiple SI words per MI word
assign sel_first_word = first_word | cmd_fix;
assign current_word = sel_first_word ? cmd_first_word :
current_word_1;
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_NEXT_WORD
// Calculate next word.
assign pre_next_word_i = ( next_word_i + cmd_step_i );
// Calculate next word.
assign next_word_i = sel_first_word ? cmd_next_word :
pre_next_word_1;
end else begin : USE_FPGA_NEXT_WORD
wire [C_M_AXI_BYTES_LOG-1:0] next_sel;
wire [C_M_AXI_BYTES_LOG:0] next_carry_local;
// Assign input to local vectors.
assign next_carry_local[0] = 1'b0;
// Instantiate one carry and per level.
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
LUT6_2 # (
.INIT(64'h5A5A_5A66_F0F0_F0CC)
) LUT6_2_inst (
.O6(next_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(next_word_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(cmd_step_i[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(cmd_next_word[bit_cnt]), // LUT input (1-bit)
.I3(first_word), // LUT input (1-bit)
.I4(cmd_fix), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY next_carry_inst
(
.O (next_carry_local[bit_cnt+1]),
.CI (next_carry_local[bit_cnt]),
.DI (cmd_step_i[bit_cnt]),
.S (next_sel[bit_cnt])
);
XORCY next_xorcy_inst
(
.O(pre_next_word_i[bit_cnt]),
.CI(next_carry_local[bit_cnt]),
.LI(next_sel[bit_cnt])
);
end // end for bit_cnt
end
endgenerate
// Calculate next word.
assign next_word = next_word_i & cmd_mask;
assign pre_next_word = pre_next_word_i & cmd_mask;
// Calculate the word address with offset.
assign current_word_adjusted = sel_first_word ? ( cmd_first_word | cmd_offset ) :
( current_word_1 | cmd_offset );
// Prepare next word address.
generate
if ( C_FAMILY == "rtl" || C_M_AXI_REGISTER ) begin : USE_RTL_CURR_WORD
reg [C_M_AXI_BYTES_LOG-1:0] current_word_q;
reg first_word_q;
reg [C_M_AXI_BYTES_LOG-1:0] pre_next_word_q;
always @ (posedge ACLK) begin
if (ARESET) begin
first_word_q <= 1'b1;
current_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
pre_next_word_q <= {C_M_AXI_BYTES_LOG{1'b0}};
end else begin
if ( pop_si_data ) begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_q <= 1'b1;
end else begin
first_word_q <= 1'b0;
end
current_word_q <= next_word;
pre_next_word_q <= pre_next_word;
end
end
end
assign first_word = first_word_q;
assign current_word_1 = current_word_q;
assign pre_next_word_1 = pre_next_word_q;
end else begin : USE_FPGA_CURR_WORD
reg first_word_cmb;
wire first_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] current_word_i;
wire [C_M_AXI_BYTES_LOG-1:0] local_pre_next_word_i;
always @ *
begin
if ( S_AXI_WLAST ) begin
// Prepare for next access.
first_word_cmb = 1'b1;
end else begin
first_word_cmb = 1'b0;
end
end
for (bit_cnt = 0; bit_cnt < C_M_AXI_BYTES_LOG ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_current_inst (
.O(current_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(next_word[bit_cnt]), // LUT input (1-bit)
.I1(current_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_current_inst (
.Q(current_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(current_word_i[bit_cnt]) // Data input
);
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_next_inst (
.O(local_pre_next_word_i[bit_cnt]), // 6-LUT output (1-bit)
.I0(pre_next_word[bit_cnt]), // LUT input (1-bit)
.I1(pre_next_word_1[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_next_inst (
.Q(pre_next_word_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(local_pre_next_word_i[bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_first_inst (
.O(first_word_i), // 6-LUT output (1-bit)
.I0(first_word_cmb), // LUT input (1-bit)
.I1(first_word), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(cmd_valid), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_first_inst (
.Q(first_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_word_i) // Data input
);
end
endgenerate
// Select command length or counted length.
always @ *
begin
if ( first_mi_word )
length_counter = cmd_length;
else
length_counter = length_counter_1;
end
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LENGTH
reg [8-1:0] length_counter_q;
reg first_mi_word_q;
// Calculate next length counter value.
assign next_length_counter = length_counter - 1'b1;
// Keep track of burst length.
always @ (posedge ACLK) begin
if (ARESET) begin
first_mi_word_q <= 1'b1;
length_counter_q <= 8'b0;
end else begin
if ( pop_mi_data_i ) begin
if ( M_AXI_WLAST_I ) begin
first_mi_word_q <= 1'b1;
end else begin
first_mi_word_q <= 1'b0;
end
length_counter_q <= next_length_counter;
end
end
end
assign first_mi_word = first_mi_word_q;
assign length_counter_1 = length_counter_q;
end else begin : USE_FPGA_LENGTH
wire [8-1:0] length_counter_i;
wire [8-1:0] length_counter_ii;
wire [8-1:0] length_sel;
wire [8-1:0] length_di;
wire [8:0] length_local_carry;
// Assign input to local vectors.
assign length_local_carry[0] = 1'b0;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6_2 # (
.INIT(64'h333C_555A_FFF0_FFF0)
) LUT6_length_inst (
.O6(length_sel[bit_cnt]), // 6/5-LUT output (1-bit)
.O5(length_di[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(cmd_length[bit_cnt]), // LUT input (1-bit)
.I2(1'b1), // LUT input (1-bit)
.I3(1'b1), // LUT input (1-bit)
.I4(first_mi_word), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
MUXCY carry_inst
(
.O (length_local_carry[bit_cnt+1]),
.CI (length_local_carry[bit_cnt]),
.DI (length_di[bit_cnt]),
.S (length_sel[bit_cnt])
);
XORCY xorcy_inst
(
.O(length_counter_ii[bit_cnt]),
.CI(length_local_carry[bit_cnt]),
.LI(length_sel[bit_cnt])
);
LUT4 # (
.INIT(16'hCCCA)
) LUT4_inst (
.O(length_counter_i[bit_cnt]), // 5-LUT output (1-bit)
.I0(length_counter_1[bit_cnt]), // LUT input (1-bit)
.I1(length_counter_ii[bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_length_inst (
.Q(length_counter_1[bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(length_counter_i[bit_cnt]) // Data input
);
end // end for bit_cnt
wire first_mi_word_i;
LUT6 # (
.INIT(64'hAAAC_AAAC_AAAC_AAAC)
) LUT6_first_mi_inst (
.O(first_mi_word_i), // 6-LUT output (1-bit)
.I0(M_AXI_WLAST_I), // LUT input (1-bit)
.I1(first_mi_word), // LUT input (1-bit)
.I2(word_complete_rest_pop), // LUT input (1-bit)
.I3(word_complete_next_wrap_pop), // LUT input (1-bit)
.I4(1'b1), // LUT input (1-bit)
.I5(1'b1) // LUT input (1-bit)
);
FDSE #(
.INIT(1'b1) // Initial value of register (1'b0 or 1'b1)
) FDSE_inst (
.Q(first_mi_word), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.S(ARESET), // Synchronous reset input
.D(first_mi_word_i) // Data input
);
end
endgenerate
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_LAST_WORD
// Detect last beat in a burst.
assign last_beat = ( length_counter == 8'b0 );
// Determine if this last word that shall be assembled into this MI-side word.
assign last_word = ( cmd_modified & last_beat & ( current_word == cmd_last_word ) );
end else begin : USE_FPGA_LAST_WORD
wire last_beat_curr_word;
generic_baseblocks_v2_1_0_comparator_sel_static #
(
.C_FAMILY(C_FAMILY),
.C_VALUE(8'b0),
.C_DATA_WIDTH(8)
) last_beat_inst
(
.CIN(1'b1),
.S(first_mi_word),
.A(length_counter_1),
.B(cmd_length),
.COUT(last_beat)
);
generic_baseblocks_v2_1_0_comparator_sel #
(
.C_FAMILY(C_FAMILY),
.C_DATA_WIDTH(C_M_AXI_BYTES_LOG)
) last_beat_curr_word_inst
(
.CIN(last_beat),
.S(sel_first_word),
.A(current_word_1),
.B(cmd_first_word),
.V(cmd_last_word),
.COUT(last_beat_curr_word)
);
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst
(
.CIN(last_beat_curr_word),
.S(cmd_modified),
.COUT(last_word)
);
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle wrap buffer:
//
// The wrap buffer is used to move data around in an unaligned WRAP
// transaction. SI-side data word(s) for an unaligned accesses are delay
// to be packed with with the tail of the transaction to make it a WRAP
// transaction that is aligned to native MI-side data with.
// For example: an 32bit to 64bit write upsizing @ 0x4 will delay the first
// word until the 0x0 data arrives in the last data beat. This will make the
// Upsized transaction be WRAP at 0x8 on the MI-side
// (was WRAP @ 0x4 on SI-side).
//
/////////////////////////////////////////////////////////////////////////////
// The unaligned SI-side words are pushed into the wrap buffer.
assign store_in_wrap_buffer_enabled = cmd_packed_wrap & ~wrap_buffer_available & cmd_valid;
assign store_in_wrap_buffer = store_in_wrap_buffer_enabled & S_AXI_WVALID;
assign ARESET_or_store_in_wrap_buffer = store_in_wrap_buffer | ARESET;
// The wrap buffer is used to complete last word.
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL_USE_WRAP
assign use_wrap_buffer = wrap_buffer_available & last_word;
end else begin : USE_FPGA_USE_WRAP
wire last_word_carry;
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst2
(
.CIN(last_word),
.S(1'b1),
.COUT(last_word_carry)
);
carry_and #
(
.C_FAMILY(C_FAMILY)
) last_word_inst3
(
.CIN(last_word_carry),
.S(1'b1),
.COUT(last_word_extra_carry)
);
carry_latch_and #
(
.C_FAMILY(C_FAMILY)
) word_complete_next_wrap_stall_inst
(
.CIN(last_word_carry),
.I(wrap_buffer_available),
.O(use_wrap_buffer)
);
end
endgenerate
// Wrap buffer becomes available when the unaligned wrap words has been taken care of.
always @ (posedge ACLK) begin
if (ARESET) begin
wrap_buffer_available <= 1'b0;
end else begin
if ( store_in_wrap_buffer & word_completed ) begin
wrap_buffer_available <= 1'b1;
end else if ( cmd_ready_i ) begin
wrap_buffer_available <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pack multiple data SI-side words into fewer MI-side data word.
// Data is only packed when modify is set. Granularity is SI-side word for
// the combinatorial data mux.
//
// Expander:
// WDATA is expanded to all SI-word lane on the MI-side.
// WSTRB is activted to the correct SI-word lane on the MI-side.
//
// Packer:
// The WDATA and WSTRB registers are always cleared before a new word is
// assembled.
// WDATA is (SI-side word granularity)
// * Combinatorial WDATA is used for current word line or when expanding.
// * All other is taken from registers.
// WSTRB is
// * Combinatorial for single data to matching word lane
// * Zero for single data to mismatched word lane
// * Register data when multiple data
//
// To support sub-sized packing during Always Pack is the combinatorial
// information packed with "or" instead of multiplexing.
//
/////////////////////////////////////////////////////////////////////////////
// Determine if expander data should be used.
assign use_expander_data = ~cmd_modified & cmd_valid;
// Registers and combinatorial data word mux.
generate
for (word_cnt = 0; word_cnt < C_RATIO ; word_cnt = word_cnt + 1) begin : WORD_LANE
// Generate select signal per SI-side word.
if ( C_RATIO == 1 ) begin : SINGLE_WORD
assign current_word_idx[word_cnt] = 1'b1;
end else begin : MULTIPLE_WORD
assign current_word_idx[word_cnt] = current_word_adjusted[C_M_AXI_BYTES_LOG-C_RATIO_LOG +: C_RATIO_LOG] == word_cnt;
end
if ( ( C_PACKING_LEVEL == C_NEVER_PACK ) ) begin : USE_EXPANDER
// Expander only functionality.
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = {C_S_AXI_DATA_WIDTH{1'b0}};
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end else begin
if ( pop_si_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end
end
end else begin : NO_REGISTER
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH +: C_S_AXI_DATA_WIDTH] = S_AXI_WDATA;
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = S_AXI_WSTRB;
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8 +: C_S_AXI_DATA_WIDTH/8] = {C_S_AXI_DATA_WIDTH/8{1'b0}};
end
end
end // end if C_M_AXI_REGISTER
end else begin : USE_ALWAYS_PACKER
// Packer functionality
for (byte_cnt = 0; byte_cnt < C_S_AXI_DATA_WIDTH / 8 ; byte_cnt = byte_cnt + 1) begin : BYTE_LANE
if ( C_FAMILY == "rtl" ) begin : USE_RTL_DATA
// Generate extended write data and strobe in wrap buffer.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
end else if ( pop_mi_data ) begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
end
if ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end else if ( use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b1;
end else if ( pop_mi_data ) begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end
end
end
end else begin : NO_REGISTER
// Generate extended write data and strobe.
always @ (posedge ACLK) begin
if (ARESET) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else begin
if ( pop_mi_data | store_in_wrap_buffer_enabled ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= 8'b0;
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= 1'b0;
end else if ( current_word_idx[word_cnt] & pop_si_data & S_AXI_WSTRB[byte_cnt] ) begin
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] <= S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] <= S_AXI_WSTRB[byte_cnt];
end
end
end
assign wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
assign wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_buffer_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
end // end if C_M_AXI_REGISTER
end else begin : USE_FPGA_DATA
always @ *
begin
if ( cmd_ready_i ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = 8'b0;
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = 1'b0;
end else if ( current_word_idx[word_cnt] & store_in_wrap_buffer & S_AXI_WSTRB[byte_cnt] ) begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt];
end else begin
wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wstrb_wrap_buffer_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] | use_expander_data ) & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] & pop_si_data & ~store_in_wrap_buffer_enabled;
assign wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = use_wrap_buffer & pop_si_data &
wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_data_inst (
.O(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WDATA_cmb[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'hF0F0_F0F0_CCCC_00AA)
) LUT6_strb_inst (
.O(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(S_AXI_WSTRB[byte_cnt]), // LUT input (1-bit)
.I3(pop_mi_data), // LUT input (1-bit)
.I4(wrap_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(M_AXI_WSTRB_cmb[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
always @ *
begin
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = M_AXI_WDATA_q[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8];
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = M_AXI_WSTRB_q[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1];
end
end else begin : NO_REGISTER
assign wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] & cmd_valid & S_AXI_WSTRB[byte_cnt];
assign wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] = current_word_idx[word_cnt] &
S_AXI_WSTRB[byte_cnt] &
cmd_valid & S_AXI_WVALID;
for (bit_cnt = 0; bit_cnt < 8 ; bit_cnt = bit_cnt + 1) begin : BIT_LANE
LUT6 # (
.INIT(64'hCCCA_CCCC_CCCC_CCCC)
) LUT6_data_inst (
.O(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // 6-LUT output (1-bit)
.I0(S_AXI_WDATA[byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I1(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(wdata_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I5(S_AXI_WVALID) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wdata_inst (
.Q(wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET), // Synchronous reset input
.D(wdata_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8+bit_cnt]) // Data input
);
end // end for bit_cnt
LUT6 # (
.INIT(64'h0000_0000_0000_AAAE)
) LUT6_strb_inst (
.O(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // 6-LUT output (1-bit)
.I0(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I1(wstrb_qualifier[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // LUT input (1-bit)
.I2(word_complete_rest_stall), // LUT input (1-bit)
.I3(word_complete_next_wrap_stall), // LUT input (1-bit)
.I4(word_complete_rest_pop), // LUT input (1-bit)
.I5(word_complete_next_wrap_pop) // LUT input (1-bit)
);
FDRE #(
.INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
) FDRE_wstrb_inst (
.Q(wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]), // Data output
.C(ACLK), // Clock input
.CE(1'b1), // Clock enable input
.R(ARESET_or_store_in_wrap_buffer), // Synchronous reset input
.D(wstrb_buffer_i[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]) // Data input
);
// Select packed or extended data.
always @ *
begin
// Multiplex data.
if ( ( current_word_idx[word_cnt] & S_AXI_WSTRB[byte_cnt] ) | use_expander_data ) begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] = S_AXI_WDATA[byte_cnt*8 +: 8];
end else begin
wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt]}} ) |
( wdata_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] & {8{use_wrap_buffer}} );
end
// Multiplex write strobe.
if ( current_word_idx[word_cnt] ) begin
// Combinatorial for last word to MI-side (only word for single).
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] = S_AXI_WSTRB[byte_cnt] |
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end else begin
// Use registered strobes. Registers are zero until valid data is written.
// I.e. zero when used for mismatched lanes while expanding.
wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt] ) |
( wstrb_wrap_buffer[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] & use_wrap_buffer );
end
end
// Merge previous with current data.
always @ *
begin
M_AXI_WSTRB_I[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] =
( wstrb_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH/8+byte_cnt +: 1] );
M_AXI_WDATA_I[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] =
( wdata_last_word_mux[word_cnt*C_S_AXI_DATA_WIDTH+byte_cnt*8 +: 8] );
end
end // end if C_M_AXI_REGISTER
end // end if C_FAMILY
end // end for byte_cnt
end // end if USE_ALWAYS_PACKER
end // end for word_cnt
endgenerate
/////////////////////////////////////////////////////////////////////////////
// MI-side output handling
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_M_AXI_REGISTER ) begin : USE_REGISTER
reg M_AXI_WLAST_q;
reg M_AXI_WVALID_q;
// Register MI-side Data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_WLAST_q <= 1'b0;
M_AXI_WVALID_q <= 1'b0;
end else begin
if ( M_AXI_WREADY_I ) begin
M_AXI_WLAST_q <= M_AXI_WLAST_I;
M_AXI_WVALID_q <= M_AXI_WVALID_I;
end
end
end
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_q;
assign M_AXI_WVALID = M_AXI_WVALID_q;
assign M_AXI_WREADY_I = ( M_AXI_WVALID_q & M_AXI_WREADY) | ~M_AXI_WVALID_q;
// Get MI-side data.
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
assign pop_mi_data = M_AXI_WVALID_q & M_AXI_WREADY_I;
// Detect when MI-side is stalling.
assign mi_stalling = ( M_AXI_WVALID_q & ~M_AXI_WREADY_I ) & ~store_in_wrap_buffer_enabled;
end else begin : NO_REGISTER
// Combinatorial MI-side Data.
assign M_AXI_WDATA = M_AXI_WDATA_I;
assign M_AXI_WSTRB = M_AXI_WSTRB_I;
assign M_AXI_WLAST = M_AXI_WLAST_I;
assign M_AXI_WVALID = M_AXI_WVALID_I;
assign M_AXI_WREADY_I = M_AXI_WREADY;
// Get MI-side data.
if ( C_FAMILY == "rtl" ) begin : USE_RTL_POP_MI
assign pop_mi_data_i = M_AXI_WVALID_I & M_AXI_WREADY_I;
end else begin : USE_FPGA_POP_MI
assign pop_mi_data_i = ( word_complete_next_wrap_pop | word_complete_rest_pop);
end
assign pop_mi_data = pop_mi_data_i;
// Detect when MI-side is stalling.
assign mi_stalling = word_completed_qualified & ~M_AXI_WREADY_I;
end
endgenerate
endmodule
|
Require Import Coq.Setoids.Setoid Coq.Classes.CMorphisms.
Require Export Lob.Notations Lob.LobsTheoremStatement Lob.LobsTheoremPreProof.
Require Import Template.Template.
Require Import Coq.Strings.String.
Require Import Coq.Program.Program.
Require Import Coq.PArith.BinPos.
Local Open Scope string_scope.
Local Open Scope positive_scope.
Require Export Lob.quote_term.
(*Require Export Lob.quote_has_type.*)
Require Export Lob.conversion.
Require Export Lob.conversion_quote.
Axiom proof_admitted : False.
Ltac admit' := case proof_admitted.
Notation "( x ; y )" := (existT _ x y).
Notation "x .1" := (projT1 x) (at level 3, format "x '.1'").
Notation "x .2" := (projT2 x) (at level 3, format "x '.2'").
Tactic Notation "unique" "pose" "proof" constr(defn) :=
let T := type of defn in
match goal with
| [ H : T |- _ ] => fail 1
| _ => pose proof defn
end.
(** Test if a tactic succeeds, but always roll-back the results *)
Tactic Notation "test" tactic3(tac) :=
try (first [ tac | fail 2 tac "does not succeed" ]; fail 0 tac "succeeds"; [](* test for [t] solved all goals *)).
(** [not tac] is equivalent to [fail tac "succeeds"] if [tac] succeeds, and is equivalent to [idtac] if [tac] fails *)
Tactic Notation "not" tactic3(tac) := try ((test tac); fail 1 tac "succeeds").
Module Type Contexts.
Axiom qbox : Ast.term.
Definition is_closed (x : Ast.term) : Type
:= forall k n, subst_n_name x k n Ast.nAnon = x.
Existing Class is_closed.
Axiom box_is_closed : is_closed qbox.
Axiom qquote : Ast.term.
Axiom qquote_is_closed : is_closed qquote.
End Contexts.
Module WithContext (Ctx : Contexts).
Module LC <: LobExtendedContext.
Definition Preterm := Ast.term.
Definition Context : Type := Context.
Delimit Scope context_scope with ctx.
Bind Scope context_scope with Context.
Definition empty_context : Context := DefaultContext.
Notation ε := empty_context.
Definition context_extend : Context -> Preterm -> Context
:= fun Γ T => context_extend Γ (CBinder Ast.nAnon T).
Notation "Γ ▻ x" := (context_extend Γ x).
Delimit Scope preterm_scope with preterm.
Bind Scope preterm_scope with Preterm.
Global Open Scope preterm_scope.
Definition box' (Γ : Context) (T : Preterm) : Type
:= { t : Preterm & has_type Γ t T }.
Definition box : Preterm -> Type
:= box' ε.
Delimit Scope well_typed_term_scope with wtt.
Bind Scope well_typed_term_scope with box'.
Bind Scope well_typed_term_scope with box.
Notation "□ T" := (box T).
Definition qbox : Preterm := Ctx.qbox.
Notation "‘□’" := qbox.
Definition tProd : Preterm -> Preterm -> Preterm
:= Ast.tProd Ast.nAnon.
Notation "x ‘→’ y" := (tProd x y) : preterm_scope.
Definition tApp : Preterm -> Preterm -> Preterm
:= fun f x => Ast.tApp f [x].
Notation "x ‘’ y" := (tApp x y) : preterm_scope.
Definition quote : Preterm -> Preterm
:= quote.
Notation "⌜ x ⌝" := (quote x).
Delimit Scope well_typed_term_scope with wtt.
Bind Scope well_typed_term_scope with box'.
Definition is_closed (x : Preterm) : Type
:= forall k n, subst_n_name x k n Ast.nAnon = x.
Existing Class is_closed.
Global Instance box_is_closed : is_closed ‘□’
:= Ctx.box_is_closed.
Global Instance tApp_is_closed : forall A' B', is_closed A' -> is_closed B' -> is_closed (A' ‘’ B').
Proof.
intros A' B' H0 H1 k n.
specialize (H0 k).
specialize (H1 k).
simpl; rewrite H0, H1; reflexivity.
Qed.
Global Instance tProd_is_closed : forall A' B', is_closed A' -> is_closed B' -> is_closed (A' ‘→’ B').
Proof.
intros A' B' H0 H1 k n.
specialize (H0 k).
specialize (H1 k).
simpl.
rewrite H0, H1; reflexivity.
Qed.
Global Instance quote_is_closed : forall A', is_closed (quote A').
Proof.
repeat intro; apply eq__quote_term__closed_helper.
Qed.
End LC.
Module PRP <: PretermReflectionPrimitives LC.
Definition qPreterm := term'.
Notation "‘Preterm’" := qPreterm : preterm_scope.
Global Instance has_type__quote {Γ A} : has_type _ (quote A) qPreterm
:= has_type__quote_term _ Γ.
Definition wttquote {Γ} A : LC.box' _ _
:= (quote A; @has_type__quote Γ _).
Notation "‘⌜ A ⌝’" := (wttquote A) : well_typed_term_scope.
Definition qquote : LC.Preterm
:= Ctx.qquote.
(*Proof.
let t := (eval cbv beta delta [qO qS qEmptyString qString qnAnon qAscii qnil qcons qmkdef qtInd qtFix qtCase qtUnknown qtRel qtConstruct qtEvar qtMeta qtVar qtApp qtConst qtSort qtCast qtProd inductive_quotable quote_ascii bool_quotable quote_bool (*quote_string quote_positive quote_nat*) ident_quotable quote_ident quote_name nat_quotable name_quotable quote quote_term sort_quotable cast_kind_quotable quote_sort qsSet qsProp qsType universe_quotable quote_inductive qmkInd] in quote_term) in
quote_term t (fun x => exact x).
Defined.*)
Notation "‘quote’" := qquote : preterm_scope.
End PRP.
Module PP <: PretermPrimitives LC.
Export LC PRP.
Definition tLambda : Preterm -> Preterm -> Preterm
:= Ast.tLambda Ast.nAnon.
Definition qtApp : Preterm
:= tLambda ‘Preterm’ (tLambda ‘Preterm’ (Ast.tApp qtApp [Ast.tRel 1; (Ast.tApp qcons [‘Preterm’; Ast.tRel 0; Ast.tApp qnil [‘Preterm’]])])).
Notation "‘App’" := qtApp : preterm_scope.
Definition qtProd : Preterm -> Preterm -> Preterm
:= fun A B => (qtProd ‘’ qnAnon ‘’ A ‘’ B)%preterm.
Notation "x ‘‘→’’ y" := (qtProd x y) : preterm_scope.
Definition tVar0 : Preterm
:= Ast.tRel 0.
Notation "‘VAR₀’" := tVar0.
Definition ttVar0 {Γ T} : box' (Γ ▻ T) T.
Proof.
refine (tVar0; _).
apply has_type_tRel_0.
Defined.
Notation "‘‘VAR₀’’" := ttVar0 : well_typed_term_scope.
End PP.
Module TR <: TypingRules LC PP.
Export LC PP.
Definition capture_avoiding_subst_0 : forall (in_term : Preterm)
(new_value : Preterm),
Preterm
:= fun in_term new_value
=> subst_n_name in_term new_value (Some 0%nat) Ast.nAnon.
Notation "x [ 0 ↦ y ]" := (capture_avoiding_subst_0 x y).
Global Arguments capture_avoiding_subst_0 !_ / _.
Definition convertible : Context -> Preterm -> Preterm -> Type
:= convertible.
Definition eq__subst__quote
: forall A x, capture_avoiding_subst_0 (quote A) x = quote A.
Proof.
intros; unfold quote, capture_avoiding_subst_0.
rewrite eq__quote_term__closed_helper; reflexivity.
Defined.
Definition box'_respectful : forall {Γ A B},
convertible Γ A B
-> box' Γ A
-> box' Γ B.
Proof.
intros Γ A B H [a Ha].
exists a.
eapply has_type_conv_subst; try eassumption; exact H.
Defined.
Global Instance convertible_refl : forall {Γ}, Reflexive (convertible Γ) := conv_refl.
Global Instance convertible_sym : forall {Γ}, Symmetric (convertible Γ) := conv_sym.
Global Instance convertible_trans : forall {Γ}, Transitive (convertible Γ) := conv_trans.
Definition convertible_beta_app_lambda
: forall Γ A f a,
convertible Γ (tApp (tLambda A f) a) (capture_avoiding_subst_0 f a).
Proof.
intros; eapply conv_beta.
Defined.
Definition convertible__capture_avoiding_subst_0__tApp
: forall Γ A B x,
convertible Γ ((A ‘’ B) [ 0 ↦ x ]) ((A [ 0 ↦ x ]) ‘’ (B [ 0 ↦ x ])).
Proof.
reflexivity.
Defined.
Definition convertible__capture_avoiding_subst_0__qtProd
: forall Γ A B x,
convertible Γ ((A ‘‘→’’ B) [ 0 ↦ x ]) ((A [ 0 ↦ x ]) ‘‘→’’ (B [ 0 ↦ x ])).
Proof.
reflexivity.
Defined.
Definition convertible__capture_avoiding_subst_0__tVar0
: forall Γ x,
convertible Γ (‘VAR₀’ [ 0 ↦ x ]) x.
Proof.
reflexivity.
Defined.
Global Instance tApp_Proper_convertible
: forall Γ,
Proper (convertible Γ ==> convertible Γ ==> convertible Γ) tApp.
Proof.
repeat intro; apply conv_tApp_respectful; assumption.
Defined.
Global Instance qtProd_Proper_convertible
: forall Γ,
Proper (convertible Γ ==> convertible Γ ==> convertible Γ) qtProd.
Proof.
repeat intro.
unfold qtProd.
apply tApp_Proper_convertible; [ | assumption ].
apply tApp_Proper_convertible; [ reflexivity | assumption ].
Defined.
Global Instance tProd_Proper_convertible
: forall Γ,
Proper (convertible Γ ==> eq ==> convertible Γ) tProd.
Proof.
repeat intro.
apply conv_tProd_respectful; [ assumption | subst; reflexivity ].
Defined.
Definition convertible__quote__qtProd
: forall Γ A B,
convertible Γ (⌜ A ‘→’ B ⌝) (⌜ A ⌝ ‘‘→’’ ⌜ B ⌝).
Proof.
repeat intro.
simpl.
unfold qtProd, tApp; simpl.
symmetry.
apply conv_tApp_cons2.
apply conv_tApp_cons2.
reflexivity.
Defined.
Definition convertible__qtApp__closed
: forall Γ x,
convertible Γ (‘App’ [ 0 ↦ x ]) (‘App’).
Proof.
reflexivity.
Defined.
Definition convertible__quote__closed
: forall Γ A x,
convertible Γ ((quote A) [ 0 ↦ x ]) (quote A).
Proof.
intros; rewrite eq__subst__quote.
reflexivity.
Defined.
Hint Resolve convertible__quote__closed : t_quote_db.
Definition convertible__quote__app
: forall Γ A B,
convertible Γ (⌜ A ‘’ B ⌝) ((‘App’ ‘’ ⌜ A ⌝) ‘’ ⌜ B ⌝).
Proof.
intros; simpl.
unfold tApp, qtApp, tLambda.
symmetry.
etransitivity.
{ apply conv_tApp_respectful; [ | reflexivity ].
apply conv_beta. }
simpl.
etransitivity; [ apply conv_beta | ].
simpl.
unfold capture_avoiding_subst_0.
rewrite eq__quote_term__closed_helper; reflexivity.
Defined.
End TR.
Module PreL' <: PreL LC PP.
Export LC PP.
Definition wttLambda_nd
{Γ : Context} {B' : Preterm}
: forall A' : Preterm, box' (Γ ▻ A') B' -> box' Γ (A' ‘→’ B').
Proof.
refine (fun A' body
=> (Ast.tLambda Ast.nAnon A' body.1;
_)).
apply has_type_tLambda.
exact body.2.
Defined.
Definition wttApp_1 {Γ : Context} {A' B' : Preterm}
: box' Γ (A' ‘→’ B')
-> forall x : box' Γ A',
box' Γ (subst_n_name B' x.1 (Some 0%nat) Ast.nAnon).
Proof.
refine (fun F x
=> (Ast.tApp F.1 [x.1];
_)).
eapply has_type_tApp.
{ exact F.2. }
{ exact x.2. }
Defined.
Definition wttApp_1_nd {Γ : Context} {A' B' : Preterm} {H : is_closed B'}
: box' Γ (A' ‘→’ B') -> box' Γ A' -> box' Γ B'.
Proof.
intros F x.
pose proof (wttApp_1 F x) as H'.
exists H'.1.
destruct H' as [Fx H']; simpl.
hnf in H.
rewrite H in H'.
apply H'.
Defined.
Notation "x ‘’ y" := (wttApp_1_nd x%wtt y%wtt) : well_typed_term_scope.
End PreL'.
Module Type DoublyQuotedThings.
Export TR LC PP PRP.
Axiom qbox_Ui : Ast.sort.
Axiom has_type_qbox
: has_type ε ‘□’ (term' ‘→’ Ast.tSort qbox_Ui).
Global Existing Instance has_type_qbox.
Axiom box_qtProd_dom_precompose
: forall {Γ} A B C,
(box' Γ (‘□’ ‘’ B) -> box' Γ (‘□’ ‘’ A))
-> box' Γ (‘□’ ‘’ (A ‘‘→’’ C))
-> box' Γ (‘□’ ‘’ (B ‘‘→’’ C)).
(** FIXME: This seems a bit fishy... *)
Axiom box_quote_app_quote
: forall Γ T,
box' Γ (‘□’
‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ (‘App’ ‘’ ⌜ ‘quote’ ⌝ ‘’ ⌜ T ⌝))))
-> box' Γ (‘□’ ‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ ⌜ ⌜ T ⌝ ⌝))).
Axiom box_quote_app_quote_inv
: forall Γ T,
box' Γ (‘□’ ‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ ⌜ ⌜ T ⌝ ⌝)))
-> box' Γ (‘□’
‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ (‘App’ ‘’ ⌜ ‘quote’ ⌝ ‘’ ⌜ T ⌝)))).
Axiom Quot : forall T, □ T -> □ (‘□’ ‘’ ⌜ T ⌝).
Section context.
Context (qX qL0 : Preterm).
Let Γ := (ε ▻ (‘□’
‘’ (tLambda ‘Preterm’
(‘App’ ‘’ ⌜ ‘□’ ⌝
‘’ (‘App’ ‘’ ‘VAR₀’ ‘’ (‘App’ ‘’ ⌜ ‘quote’ ⌝ ‘’ ‘VAR₀’))
‘‘→’’ ⌜ qX ⌝) ‘’ ⌜ qL0 ⌝))).
Axiom qQuote
: forall T,
let A := (‘□’ ‘’ T)%preterm in
box' Γ (A ‘→’ (‘□’ ‘’ (⌜ A ⌝))).
Axiom qbApp
: forall A' B',
box' Γ ((‘□’ ‘’ (A' ‘‘→’’ B')) ‘→’ (‘□’ ‘’ A') ‘→’ (‘□’ ‘’ B')).
End context.
End DoublyQuotedThings.
Module PRTR (DQT : DoublyQuotedThings) <: PretermReflectionTypingRules LC PP PRP TR.
Export LC PP PRP TR.
Include DQT.
Definition convertible__qquote__closed
: forall Γ x,
convertible Γ (‘quote’ [ 0 ↦ x ]) (‘quote’).
Proof.
unfold capture_avoiding_subst_0; intros.
rewrite Ctx.qquote_is_closed; reflexivity.
Defined.
End PRTR.
Local Ltac t_has_type' :=
idtac;
match goal with
| _ => progress simpl in *
| _ => exact _
| [ |- has_type _ (Ast.tLambda (Ast.nNamed _) _ _) _ ]
=> apply has_type_tLambda_unname
| [ |- has_type ?Γ (Ast.tApp ?f [?a]) ?B ]
=> refine (@has_type_tApp Γ f Ast.nAnon _ _ a _ _); shelve_unifiable
| [ |- has_type ?Γ (Ast.tLambda ?x ?A ?b) ?B ]
=> refine (has_type_tLambda _ _ _ _ _ _); shelve_unifiable
| [ |- has_type ?Γ (Ast.tProd ?x ?A ?B) ?T ]
=> refine (has_type_tProd _ _ _ _ _ _); shelve_unifiable
| [ |- has_type _ (quote_term _) (subst_n_name ?e _ _ _) ]
=> unify e term'
| [ |- has_type _ (Ast.tApp (Ast.tLambda _ _ _) [_]) _ ]
=> eapply has_type_conv_subst_term;
[
| symmetry; solve [ apply conv_beta ] ];
simpl subst_n_name
| _ => rewrite !eq__quote_term__closed_helper
| [ |- has_type ?Γ (Ast.tApp ?f [?a]) ?B ]
=> let A := fresh in
let B' := fresh in
evar (A : Ast.term);
evar (B' : Ast.term);
let H := fresh in
pose proof (@has_type_tApp Γ f Ast.nAnon A B' a) as H;
subst A B';
refine (_ (H _ _)); shelve_unifiable; clear H;
[ | repeat t_has_type' | ]; shelve_unifiable;
[ simpl; exact (fun x => x) | ]
| _ => exact _
| [ |- has_type ?Γ (Ast.tApp ?f [?a]) ?B ]
=> not is_evar B; eapply has_type_conv_subst; shelve_unifiable
| [ |- has_type (_ ▻▻ _) _ _ ]
=> apply wkg_rel_free; [ intros ? [?|]; reflexivity | intros ? [?|]; reflexivity | ]
| [ |- has_type _ _ _ ]
=> eapply has_type_conv_subst;
[ eapply has_type_tConstruct1_Lookup;
[ | | simpl; reflexivity ];
hnf; simpl; reflexivity
| ]
| [ |- convertible ?Γ ?k _ ] => unfold k
| [ |- convertible ?Γ (Ast.tConst ?n) _ ]
=> let H := fresh in
pose proof (@conv_delta_Lookup Γ n) as H;
unfold is_rel_free in H;
simpl in H;
apply (H (fun _ _ => eq_refl))
| [ |- conversion.convertible _ (Ast.tProd _ _ _) (Ast.tProd _ _ _) ]
=> apply conv_tProd_respectful
| _ => progress simpl
| [ |- has_type _ (Ast.tApp _ (_::_::_)%list) _ ]
=> apply has_type_tApp_split
| [ |- conversion.convertible _ (Ast.tProd _ _ _) (Ast.tProd _ _ _) ]
=> apply conv_tProd_respectful
| [ |- conversion.convertible _ ?x (subst_n_name ?e _ _ _) ]
=> is_evar e; not has_evar x; unify x e; simpl; reflexivity
| [ |- conversion.convertible _ (subst_n_name ?e _ _ _) ?x ]
=> is_evar e; not has_evar x; unify x e; simpl; reflexivity
| [ |- conversion.convertible _ ?x ?y ]
=> not has_evar x; not has_evar y; reflexivity
| [ |- conversion.convertible _ ?x ?y ]
=> not has_evar x; is_evar y; reflexivity
| [ |- conversion.convertible _ ?x (subst_n_name ?e _ _ _) ]
=> is_evar e; unify x e; simpl; reflexivity
| [ |- conversion.convertible _ (subst_n_name ?e _ _ _) ?x ]
=> is_evar e; unify x e; simpl; reflexivity
| _ => progress unfold LC.tProd
| [ |- conversion.convertible _ (Ast.tSort match ?e with _ => _ end) (Ast.tSort ?v) ]
=> is_evar e; unify e v; reflexivity
end.
Module LA (DQT : DoublyQuotedThings) <: PostL_Assumptions LC PP PRP TR.
Export TR LC PP PRP.
Include DQT.
Section context.
Context (qX qL0 : Preterm).
Let Γ := (ε ▻ (‘□’
‘’ (tLambda ‘Preterm’
(‘App’ ‘’ ⌜ ‘□’ ⌝
‘’ (‘App’ ‘’ ‘VAR₀’ ‘’ (‘App’ ‘’ ⌜ ‘quote’ ⌝ ‘’ ‘VAR₀’))
‘‘→’’ ⌜ qX ⌝) ‘’ ⌜ qL0 ⌝))).
Definition box'_weaken
: forall {A} {H : is_closed A}, box' ε A -> box' Γ A.
Proof.
simpl; intros A H bA.
refine (bump_rel_from bA.1 (Some 0%nat) Ast.nAnon tt; _).
apply is_rel_free_iff in H.
hnf in H.
rewrite <- (H (Some 0%nat)).
subst Γ.
eapply (wkg_1 (Δ := nil)); [ | exact bA.2 ].
unfold qtProd, qtApp, tApp, tLambda.
Time do 3 t_has_type'.
{ match goal with
| [ |- has_type ?Γ (Ast.tApp ?f [?a]) ?B ]
=> let A := fresh in
let B' := fresh in
evar (A : Ast.term);
evar (B' : Ast.term);
let H := fresh in
pose proof (@has_type_tApp Γ f Ast.nAnon A B' a) as H;
subst A B';
refine (_ (H _ _)); shelve_unifiable; clear H;
[ | | ]; shelve_unifiable;
[ simpl | | ]
end.
Focus 2.
{
{ match goal with
| [ |- has_type ?Γ (Ast.tApp ?f [?a]) ?B ]
=> let A := fresh in
let B' := fresh in
evar (A : Ast.term);
evar (B' : Ast.term);
let H := fresh in
pose proof (@has_type_tApp Γ f Ast.nAnon A B' a) as H;
subst A B';
refine (_ (H _ _)); shelve_unifiable; clear H;
[ | | ]; shelve_unifiable;
[ simpl | | ]
end.
Focus 2.
{ repeat t_has_type'. }
Unfocus.
{ Time do 5 t_has_type'. }
{ Time do 2 t_has_type'.
{ t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
t_has_type'.
Existing Class eq.
Hint Extern 1 (Some (CType ?x _) = Some (CType ?x _)) => reflexivity : typeclass_instances.
eapply has_type_tConstruct1_Lookup; simpl.
3:exact _.
simpl.
all:simpl; try exact _.
all:simpl; try exact _.
(*t_has_type'.
t_has_type'.
Global Existing Instance has_type__quote_term_1
refine (@has_type__quote_term _ [(_, _)]%list).
rewrite eq__quote_term__closed_helper.
{
all:admit. }
{
admit'.
(* refine ((fun Ui H => @wkg_1_nil nil Ast.nAnon _ _ _ Ui H bA.2) _ _); shelve_unifiable.
unfold qtProd, qtApp, tApp, tLambda.
t_has_type.*)*)
Admitted.
End context.
Definition App : forall {A' B'} {H : is_closed B'},
□ (A' ‘→’ B') -> □ A' -> □ B'.
Proof.
intros A' B' H AtoB A.
refine (AtoB.1 ‘’ A.1;
_ (has_type_tApp ε AtoB.1 Ast.nAnon A' B' A.1 AtoB.2 A.2)).
clear -H; abstract (hnf in H; rewrite H; intro; assumption).
Defined.
End LA.
Module Lob (LH : LobHypotheses LC) (DQT : DoublyQuotedThings) <: LobsTheorem LC LH.
Module PRTR' := PRTR DQT.
Module LA' := LA DQT.
Module Lob' := LobOfPreLob LC LH PP PreL' PRP TR PRTR' LA'.
Definition lob := Lob'.lob.
Print Assumptions lob.
End Lob.
End WithContext.
(*
Module DQT <: DoublyQuotedThings.
Export TR LC PP PRP PreL'.
Definition qbox_Ui' : Ast.universe := 1.
Definition qbox_Ui := Ast.sType qbox_Ui'.
(*Global Instance has_type_qPreterm {Γ}
: has_type Γ ‘Preterm’ (Ast.tSort (Ast.sType 1))
:= _.
Definition wttPreterm {Γ} : box' Γ (Ast.tSort (Ast.sType 1))
:= (‘Preterm’; has_type_qPreterm).
Notation "‘‘Preterm’’" := wttPreterm : well_typed_term_scope.*)
Global Instance has_type_qbox
: has_type ε ‘□’ (term' ‘→’ Ast.tSort qbox_Ui).
Proof.
unfold qbox, qbox_Ui.
repeat t_has_type; shelve_unifiable.
admit'.
Qed.
Axiom box_qtProd_dom_precompose
: forall {Γ} A B C,
(box' Γ (‘□’ ‘’ B) -> box' Γ (‘□’ ‘’ A))
-> box' Γ (‘□’ ‘’ (A ‘‘→’’ C))
-> box' Γ (‘□’ ‘’ (B ‘‘→’’ C)).
(** FIXME: This seems a bit fishy... *)
Axiom box_quote_app_quote
: forall Γ T,
box' Γ (‘□’
‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ (‘App’ ‘’ ⌜ ‘quote’ ⌝ ‘’ ⌜ T ⌝))))
-> box' Γ (‘□’ ‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ ⌜ ⌜ T ⌝ ⌝))).
Axiom box_quote_app_quote_inv
: forall Γ T,
box' Γ (‘□’ ‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ ⌜ ⌜ T ⌝ ⌝)))
-> box' Γ (‘□’
‘’ (‘App’ ‘’ ⌜‘□’ ⌝ ‘’ (‘App’ ‘’ ⌜T ⌝ ‘’ (‘App’ ‘’ ⌜ ‘quote’ ⌝ ‘’ ⌜ T ⌝)))).
Quote Definition has_type' := has_type nil.
Axiom has_type_has_type' : forall {Γ}, has_type Γ has_type' (‘Preterm’ ‘→’ ‘Preterm’ ‘→’ Ast.tSort (Ast.sType 3)).
Existing Instance has_type_has_type'.
Definition wtthas_type {Γ} : box' Γ _
:= (has_type'; has_type_has_type').
Notation "‘‘has_type’’" := wtthas_type : well_typed_term_scope.
(*Definition wttexistT {Γ U1 U2} : box' Γ _
:= (‘existT’; has_type_qexistT _ U1 U2).
Notation "‘‘existT’’" := wttexistT : well_typed_term_scope.*)
Local Ltac set_evars :=
repeat match goal with
| [ |- appcontext[?E] ] => is_evar E; let e := fresh in set (e := E)
end.
Local Ltac subst_body :=
repeat match goal with
| [ H := _ |- _ ] => subst H
end.
Local Ltac conv_rewrite
:= set_evars;
repeat match goal with
| [ |- convertible _ ?x ?x ] => reflexivity
| [ |- convertible _ (?x ‘’ _) (?x ‘’ _) ]
=> apply tApp_Proper_convertible; [ reflexivity | ]
| [ |- convertible _ (_ ‘‘→’’ _) (_ ‘‘→’’ _) ]
=> apply qtProd_Proper_convertible
| [ |- convertible _ (_ ‘→’ ?x) _ ]
=> apply tProd_Proper_convertible; [ | reflexivity ]
| _ => progress rewrite_strat repeat (topdown repeat (hints convdb))
(*| _ => progress rewrite ?convertible__capture_avoiding_subst_0__tApp, ?convertible__qtApp__closed, ?convertible__quote__closed, ?convertible__quote__app, ?convertible__capture_avoiding_subst_0__tVar0, ?convertible__qquote__closed, ?convertible__capture_avoiding_subst_0__qtProd, ?convertible__quote__qtProd, ?convertible_beta_app_lambda*)
end;
subst_body.
Local Notation "x ‘’ y" := (wttApp_1 x%wtt y%wtt) : well_typed_term_scope.
Definition Quot : forall T, □ T -> □ (‘□’ ‘’ ⌜ T ⌝).
Proof.
intros T bT.
unfold qbox.
eapply box'_respectful; cycle 1.
2:unfold tApp.
2:let RHS := match goal with |- ?R ?x ?y => constr:y end in
match RHS with
| context G[Ast.tApp (Ast.tLambda ?x ?A ?b) [?a]]
=> let G' := context G[subst_n_name b a (Some 0%nat) x] in
refine (@transitivity _ _ _ _ G' _ _ _); simpl
end;
repeat match goal with
| [ |- ?R (Ast.tApp _ _) (Ast.tApp _ _) ]
=> apply tApp_Proper
| [ |- ?R _ (Ast.tApp (Ast.tLambda _ _ _) _) ]
=> etransitivity; [ | symmetry; apply conv_beta ]
| [ |- ?R (Ast.tLambda ?n ?A _) (Ast.tLambda ?n ?A _) ]
=> apply tLambda_Proper1
| [ |- ?R ?x ?x ] => reflexivity
| [ |- (_ * _)%type ] => split
| [ |- True ] => constructor
| _ => progress simpl
end.
Timeout 5 refine (‘‘existT’’ ‘’ ‘‘Preterm’’ ‘’ (wttLambda_nd _ (‘‘has_type’’ ‘’ ‘‘VAR₀’’ ‘’ ‘⌜ T ⌝’)) ‘’ ‘⌜ bT.1 ⌝’ ‘’ (_ bT.2))%wtt; shelve_unifiable.
2:repeat match goal with
| [ |- ?R (Ast.tApp _ [_]) (Ast.tApp _ [_]) ]
=> apply tApp_Proper
| [ |- ?R (Ast.tApp _ nil) (Ast.tApp _ nil) ]
=> apply tApp_Proper
| [ |- ?R (Ast.tApp _ [_;_]) (Ast.tApp _ [_;_]) ]
=> apply tApp_Proper
| [ |- ?R (Ast.tApp _ [_;_;_]) (Ast.tApp _ [_;_;_]) ]
=> apply tApp_Proper
| [ |- ?R _ (Ast.tApp (Ast.tLambda _ _ _) _) ]
=> etransitivity; [ | symmetry; apply conv_beta ]
| [ |- ?R (Ast.tApp (Ast.tApp _ _) _) _ ]
=> apply conv_tApp_cons2
| [ |- ?R _ (Ast.tApp (Ast.tApp _ _) _) ]
=> symmetry; apply conv_tApp_cons2; symmetry
| [ |- ?R (Ast.tLambda ?n ?A _) (Ast.tLambda ?n ?A _) ]
=> apply tLambda_Proper1
| [ |- ?R _ (Ast.tLambda (Ast.nNamed _) _ _) ]
=> etransitivity; [ | symmetry; apply conv_tLambda_unname ]
| [ |- ?R ?x ?x ] => reflexivity
| [ |- (_ * _)%type ] => split
| [ |- True ] => constructor
| _ => progress simpl
| _ => progress unfold quote_term.quote, term_quotable
| _ => rewrite eq__quote_term__closed_helper
end.
{ simpl.
intro ht.
eapply box'_respectful.
{ let RHS := match goal with |- ?R ?x ?y => constr:y end in
match RHS with
| context G[Ast.tApp (Ast.tLambda ?x ?A ?b) [?a]]
=> let G' := context G[subst_n_name b a (Some 0%nat) x] in
refine (@transitivity _ _ _ _ G' _ _ _); simpl
end;
repeat match goal with
| [ |- ?R _ (Ast.tApp (Ast.tLambda _ _ _) _) ]
=> etransitivity; [ | symmetry; apply conv_beta ]
| [ |- ?R (Ast.tApp (Ast.tLambda _ _ _) _) _ ]
=> etransitivity; [ apply conv_beta | ]
| [ |- ?R (Ast.tLambda ?n ?A _) (Ast.tLambda ?n ?A _) ]
=> apply tLambda_Proper1
| [ |- ?R (Ast.tApp _ [_]) (Ast.tApp _ [_]) ]
=> apply tApp_Proper
| [ |- ?R (Ast.tApp _ nil) (Ast.tApp _ nil) ]
=> apply tApp_Proper
| [ |- ?R (Ast.tApp _ [_;_]) (Ast.tApp _ [_;_]) ]
=> apply tApp_Proper
| [ |- ?R (Ast.tApp _ [_;_;_]) (Ast.tApp _ [_;_;_]) ]
=> apply tApp_Proper
| [ |- ?R (Ast.tApp (Ast.tApp _ _) _) _ ]
=> apply conv_tApp_cons2
| [ |- ?R _ (Ast.tApp (Ast.tApp _ _) _) ]
=> symmetry; apply conv_tApp_cons2; symmetry
| [ |- ?R ?x ?x ] => reflexivity
| [ |- (_ * _)%type ] => split
| [ |- True ] => constructor
| _ => progress simpl
| _ => progress unfold quote_term.quote, term_quotable
| _ => rewrite eq__quote_term__closed_helper
end;
reflexivity. }
admit.
Admitted.
Section context.
Context (qX qL0 : Preterm).
Let Γ := (ε ▻ (‘□’
‘’ (tLambda ‘Preterm’
(‘App’ ‘’ ⌜ ‘□’ ⌝
‘’ (‘App’ ‘’ ‘VAR₀’ ‘’ (‘App’ ‘’ ⌜ ‘quote’ ⌝ ‘’ ‘VAR₀’))
‘‘→’’ ⌜ qX ⌝) ‘’ ⌜ qL0 ⌝))).
Axiom qQuote
: forall T,
let A := (‘□’ ‘’ T)%preterm in
box' Γ (A ‘→’ (‘□’ ‘’ (⌜ A ⌝))).
Axiom qbApp
: forall A' B',
box' Γ ((‘□’ ‘’ (A' ‘‘→’’ B')) ‘→’ (‘□’ ‘’ A') ‘→’ (‘□’ ‘’ B')).
End context.
End DQT.
Declare Module LH : LobHypotheses LC.
Module Lob <: LobsTheorem LC LH.
Module PRTR' := PRTR DQT.
Module LA' := LA DQT.
Module Lob' := LobOfPreLob LC LH PP PreL' PRP TR PRTR' LA'.
Definition lob := Lob'.lob.
Print Assumptions lob.
End Lob.
Print Assumptions Lob.lob.
*)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:45:15 09/30/2016
// Design Name:
// Module Name: painter_chooser
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module painter_chooser(
input [9:0] hc,
input [9:0] vc,
input [9:0] mouse_x,
input [8:0] mouse_y,
input [7:0] rgb_background,
input [7:0] line_code,
output reg [9:0] hpos,
output reg [8:0] vpos,
output reg [4:0] line_number,
output reg [7:0] rgb
);
parameter [7:0]hbp = 144; // Fin del "back-porch" horizontal
parameter [4:0]vbp = 31; // Fin del "back-porch" vertical
parameter [7:0]black = 8'b00000000;
parameter [7:0]lblue = 8'b00001011;
parameter [7:0]lred = 8'b10000000;
always @(*)
begin
vpos = {vc - vbp}[8:0];
hpos = hc - hbp;
line_number = 0;
rgb = rgb_background;
if( hpos >= mouse_x && hpos < (mouse_x + 8) // Inicio: dibuja mouse
&& vpos >= mouse_y && vpos < (mouse_y + 11))
begin
line_number = {vpos - mouse_y}[4:0];
if(line_code[hpos-mouse_x])
rgb = black;
end // Fin: dibuja mouse
end
endmodule
|
// The MLAB
// --------
// In addition to Logic Array Blocks (LABs) that contain ten Adaptive Logic
// Modules (ALMs, see alm_sim.v), the Cyclone V/10GX also contain
// Memory/Logic Array Blocks (MLABs) that can act as either ten ALMs, or utilise
// the memory the ALM uses to store the look-up table data for general usage,
// producing a 32 address by 20-bit block of memory. MLABs are spread out
// around the chip, so they can be placed near where they are needed, rather than
// being comparatively limited in placement for a deep but narrow memory such as
// the M10K memory block.
//
// MLABs are used mainly for shallow but wide memories, such as CPU register
// files (which have perhaps 32 registers that are comparatively wide (16/32-bit))
// or shift registers (by using the output of the Nth bit as input for the N+1th
// bit).
//
// Oddly, instead of providing a block 32 address by 20-bit cell, Quartus asks
// synthesis tools to build MLABs out of 32 address by 1-bit cells, and tries
// to put these cells in the same MLAB during cell placement. Because of this
// a MISTRAL_MLAB cell represents one of these 32 address by 1-bit cells, and
// 20 of them represent a physical MLAB.
//
// How the MLAB works
// ------------------
// MLABs are poorly documented, so the following information is based mainly
// on the simulation model and my knowledge of how memories like these work.
// Additionally, note that the ports of MISTRAL_MLAB are the ones auto-generated
// by the Yosys `memory_bram` pass, and it doesn't make sense to me to use
// `techmap` just for the sake of renaming the cell ports.
//
// The MLAB can be initialised to any value, but unfortunately Quartus only
// allows memory initialisation from a file. Since Yosys doesn't preserve input
// file information, or write the contents of an `initial` block to a file,
// Yosys can't currently initialise the MLAB in a way Quartus will accept.
//
// The MLAB takes in data from A1DATA at the rising edge of CLK1, and if A1EN
// is high, writes it to the address in A1ADDR. A1EN can therefore be used to
// conditionally write data to the MLAB.
//
// Simultaneously, the MLAB reads data from B1ADDR, and outputs it to B1DATA,
// asynchronous to CLK1 and ignoring A1EN. If a synchronous read is needed
// then the output can be fed to embedded flops. Presently, Yosys assumes
// Quartus will pack external flops into the MLAB, but this is an assumption
// that needs testing.
// The vendor sim model outputs 'x for a very short period (a few
// combinational delta cycles) after each write. This has been omitted from
// the following model because it's very difficult to trigger this in practice
// as clock cycles will be much longer than any potential blip of 'x, so the
// model can be treated as always returning a defined result.
(* abc9_box, lib_whitebox *)
module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA);
reg [31:0] mem = 32'b0;
// TODO: Cyclone 10 GX timings; the below timings are for Cyclone V
specify
$setup(A1ADDR, posedge CLK1, 86);
$setup(A1DATA, posedge CLK1, 86);
$setup(A1EN, posedge CLK1, 86);
(B1ADDR[0] => B1DATA) = 487;
(B1ADDR[1] => B1DATA) = 475;
(B1ADDR[2] => B1DATA) = 382;
(B1ADDR[3] => B1DATA) = 284;
(B1ADDR[4] => B1DATA) = 96;
endspecify
always @(posedge CLK1)
if (A1EN) mem[A1ADDR] <= A1DATA;
assign B1DATA = mem[B1ADDR];
endmodule
// The M10K
// --------
// TODO
module MISTRAL_M10K(CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 10;
parameter CFG_DBITS = 10;
input CLK1;
input [CFG_ABITS-1:0] A1ADDR, B1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input A1EN, B1EN;
output reg [CFG_DBITS-1:0] B1DATA;
reg [2**CFG_ABITS * CFG_DBITS - 1 : 0] mem = 0;
specify
$setup(A1ADDR, posedge CLK1, 0);
$setup(A1DATA, posedge CLK1, 0);
if (B1EN) (posedge CLK1 => (B1DATA : A1DATA)) = 0;
endspecify
always @(posedge CLK1) begin
if (A1EN)
mem[(A1ADDR + 1) * CFG_DBITS - 1 : A1ADDR * CFG_DBITS] <= A1DATA;
if (B1EN)
B1DATA <= mem[(B1ADDR + 1) * CFG_DBITS - 1 : B1ADDR * CFG_DBITS];
end
endmodule
|
`timescale 1ns/1ns
module spi_slave_rxq
(input c,
input cs, input sclk, input mosi,
output [7:0] rxd, output rxdv, output rxe);
wire [7:0] spi_rxd;
wire spi_rxdv, spi_rxe;
spi_slave_rx spi_slave_rx_inst
(.clk(c), .cs(cs), .sclk(sclk), .mosi(mosi),
.rxd(spi_rxd), .rxdv(spi_rxdv), .rxe(spi_rxe));
wire dfifo_rdreq, dfifo_empty;
wire [7:0] dfifo_q;
wire [7:0] dfifo_usedw;
scfifo #(.lpm_width(8),
.lpm_numwords(256),
.lpm_widthu(8),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) dfifo
(.clock(c),
.wrreq(spi_rxdv), .data(spi_rxd),
.rdreq(dfifo_rdreq), .q(dfifo_q),
.empty(dfifo_empty), .usedw(dfifo_usedw), .aclr(1'b0), .sclr(1'b0));
localparam SW = 3;
localparam ST_IDLE = 3'd0;
localparam ST_TX_HEADER = 3'd1;
localparam ST_DRAIN_FIFO = 3'd2;
localparam ST_DONE = 3'd3;
localparam CW = 4;
reg [SW+CW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_reg
(.c(c), .d(next_state), .rst(1'b0), .en(1'b1), .q(state));
assign rxdv = ctrl[0];
assign rxd = state == ST_TX_HEADER ? 8'h99 : dfifo_q;
assign rxe = rxdv & dfifo_usedw == 8'h1;
assign dfifo_rdreq = ctrl[1];
always @* begin
case (state)
ST_IDLE:
if (spi_rxe) ctrl = { ST_TX_HEADER , 4'b0000 };
else ctrl = { ST_IDLE , 4'b0000 };
ST_TX_HEADER: ctrl = { ST_DRAIN_FIFO, 4'b0001 };
ST_DRAIN_FIFO:
if (dfifo_usedw == 8'h1) ctrl = { ST_IDLE , 4'b0011 };
else ctrl = { ST_DRAIN_FIFO, 4'b0011 };
default: ctrl = { ST_IDLE , 4'b0000 };
endcase
end
endmodule
`ifdef test_spi_slave_rxq
module spi_slave_rxq_tb();
wire c;
sim_clk #(100) clk_inst(c);
localparam W = 8;
reg [W-1:0] master_txd;
wire [W-1:0] master_rxd;
reg master_txdv;
wire master_rxdv;
wire master_done, master_busy;
wire sclk, mosi, miso, cs;
spi_master #(.SCLK_DIV(50), .W(8)) spi_master_inst
(.c(c), .busy(master_busy), .done(master_done),
.txd(master_txd), .txdv(master_txdv),
.rxd(master_rxd), .rxdv(master_rxdv),
.sclk(sclk), .mosi(mosi), .miso(miso), .cs(cs));
wire [7:0] qrxd;
wire qrxdv, qrxe;
spi_slave_rxq dut
(.c(c), .cs(cs), .sclk(sclk), .mosi(mosi),
.rxd(qrxd), .rxdv(qrxdv), .rxe(qrxe));
initial begin
$dumpfile("spi_slave_rxq.lxt");
$dumpvars();
master_txd = 8'ha5;
master_txdv = 0;
#100
@(posedge c);
#1 master_txdv = 1;
@(posedge c);
#1 master_txd = 8'h7;
@(posedge c);
#1 master_txd = 8'h51;
@(posedge c);
#1 master_txdv = 0;
#40000
@(posedge c);
#1 master_txdv = 1;
@(posedge c);
#1 master_txdv = 0;
#40000
$finish;
end
endmodule
`endif
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sun.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sun (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "../sprites/sun.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../sprites/sun.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../sprites/sun.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sun_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: openMSP430_defines.v
//
// *Module Description:
// openMSP430 Configuration file
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
`define OMSP_NO_INCLUDE
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
//============================================================================
//============================================================================
// BASIC SYSTEM CONFIGURATION
//============================================================================
//============================================================================
//
// Note: the sum of program, data and peripheral memory spaces must not
// exceed 64 kB
//
// Program Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define PMEM_SIZE_CUSTOM
//`define PMEM_SIZE_59_KB
//`define PMEM_SIZE_55_KB
//`define PMEM_SIZE_54_KB
//`define PMEM_SIZE_51_KB
//`define PMEM_SIZE_48_KB
//`define PMEM_SIZE_41_KB
//`define PMEM_SIZE_32_KB
//`define PMEM_SIZE_24_KB
//`define PMEM_SIZE_16_KB
//`define PMEM_SIZE_12_KB
//`define PMEM_SIZE_8_KB
`define PMEM_SIZE_4_KB
//`define PMEM_SIZE_2_KB
//`define PMEM_SIZE_1_KB
// Data Memory Size:
// Uncomment the required memory size
//-------------------------------------------------------
//`define DMEM_SIZE_CUSTOM
//`define DMEM_SIZE_32_KB
//`define DMEM_SIZE_24_KB
//`define DMEM_SIZE_16_KB
//`define DMEM_SIZE_10_KB
//`define DMEM_SIZE_8_KB
//`define DMEM_SIZE_5_KB
//`define DMEM_SIZE_4_KB
//`define DMEM_SIZE_2p5_KB
//`define DMEM_SIZE_2_KB
`define DMEM_SIZE_1_KB
//`define DMEM_SIZE_512_B
//`define DMEM_SIZE_256_B
//`define DMEM_SIZE_128_B
// Include/Exclude Hardware Multiplier
`define MULTIPLIER
// Include/Exclude Serial Debug interface
`define DBG_EN
//============================================================================
//============================================================================
// ADVANCED SYSTEM CONFIGURATION (FOR EXPERIENCED USERS)
//============================================================================
//============================================================================
//-------------------------------------------------------
// Custom user version number
//-------------------------------------------------------
// This 5 bit field can be freely used in order to allow
// custom identification of the system through the debug
// interface.
// (see CPU_ID.USER_VERSION field in the documentation)
//-------------------------------------------------------
`define USER_VERSION 5'b00000
//-------------------------------------------------------
// Include/Exclude Watchdog timer
//-------------------------------------------------------
// When excluded, the following functionality will be
// lost:
// - Watchog (both interval and watchdog modes)
// - NMI interrupt edge selection
// - Possibility to generate a software PUC reset
//-------------------------------------------------------
`define WATCHDOG
//-------------------------------------------------------
// Include/Exclude DMA interface support
//-------------------------------------------------------
`define DMA_IF_EN
//-------------------------------------------------------
// Include/Exclude Non-Maskable-Interrupt support
//-------------------------------------------------------
`define NMI
//-------------------------------------------------------
// Number of available IRQs
//-------------------------------------------------------
// Indicates the number of interrupt vectors supported
// (16, 32 or 64).
//-------------------------------------------------------
`define IRQ_16
//`define IRQ_32
//`define IRQ_64
//-------------------------------------------------------
// Input synchronizers
//-------------------------------------------------------
// In some cases, the asynchronous input ports might
// already be synchronized externally.
// If an extensive CDC design review showed that this
// is really the case, the individual synchronizers
// can be disabled with the following defines.
//
// Notes:
// - all three signals are all sampled in the MCLK domain
//
// - the dbg_en signal reset the debug interface
// when 0. Therefore make sure it is glitch free.
//
//-------------------------------------------------------
`define SYNC_NMI
//`define SYNC_CPU_EN
//`define SYNC_DBG_EN
//-------------------------------------------------------
// Peripheral Memory Space:
//-------------------------------------------------------
// The original MSP430 architecture map the peripherals
// from 0x0000 to 0x01FF (i.e. 512B of the memory space).
// The following defines allow you to expand this space
// up to 32 kB (i.e. from 0x0000 to 0x7fff).
// As a consequence, the data memory mapping will be
// shifted up and a custom linker script will therefore
// be required by the GCC compiler.
//-------------------------------------------------------
//`define PER_SIZE_CUSTOM
//`define PER_SIZE_32_KB
//`define PER_SIZE_16_KB
//`define PER_SIZE_8_KB
//`define PER_SIZE_4_KB
//`define PER_SIZE_2_KB
//`define PER_SIZE_1_KB
`define PER_SIZE_512_B
//-------------------------------------------------------
// Defines the debugger CPU_CTL.RST_BRK_EN reset value
// (CPU break on PUC reset)
//-------------------------------------------------------
// When defined, the CPU will automatically break after
// a PUC occurrence by default. This is typically useful
// when the program memory can only be initialized through
// the serial debug interface.
//-------------------------------------------------------
`define DBG_RST_BRK_EN
//============================================================================
//============================================================================
// EXPERT SYSTEM CONFIGURATION ( !!!! EXPERTS ONLY !!!! )
//============================================================================
//============================================================================
//
// IMPORTANT NOTE: Please update following configuration options ONLY if
// you have a good reason to do so... and if you know what
// you are doing :-P
//
//============================================================================
//-------------------------------------------------------
// Select serial debug interface protocol
//-------------------------------------------------------
// DBG_UART -> Enable UART (8N1) debug interface
// DBG_I2C -> Enable I2C debug interface
//-------------------------------------------------------
`define DBG_UART
//`define DBG_I2C
//-------------------------------------------------------
// Enable the I2C broadcast address
//-------------------------------------------------------
// For multicore systems, a common I2C broadcast address
// can be given to all oMSP cores in order to
// synchronously RESET, START, STOP, or STEP all CPUs
// at once with a single I2C command.
// If you have a single openMSP430 in your system,
// this option can stay commented-out.
//-------------------------------------------------------
//`define DBG_I2C_BROADCAST
//-------------------------------------------------------
// Number of hardware breakpoint/watchpoint units
// (each unit contains two hardware addresses available
// for breakpoints or watchpoints):
// - DBG_HWBRK_0 -> Include hardware breakpoints unit 0
// - DBG_HWBRK_1 -> Include hardware breakpoints unit 1
// - DBG_HWBRK_2 -> Include hardware breakpoints unit 2
// - DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//-------------------------------------------------------
// Please keep in mind that hardware breakpoints only
// make sense whenever the program memory is not an SRAM
// (i.e. Flash/OTP/ROM/...) or when you are interested
// in data breakpoints.
//-------------------------------------------------------
//`define DBG_HWBRK_0
//`define DBG_HWBRK_1
//`define DBG_HWBRK_2
//`define DBG_HWBRK_3
//-------------------------------------------------------
// Enable/Disable the hardware breakpoint RANGE mode
//-------------------------------------------------------
// When enabled this feature allows the hardware breakpoint
// units to stop the cpu whenever an instruction or data
// access lays within an address range.
// Note that this feature is not supported by GDB.
//-------------------------------------------------------
//`define DBG_HWBRK_RANGE
//-------------------------------------------------------
// Custom Program/Data and Peripheral Memory Spaces
//-------------------------------------------------------
// The following values are valid only if the
// corresponding *_SIZE_CUSTOM defines are uncommented:
//
// - *_SIZE : size of the section in bytes.
// - *_AWIDTH : address port width, this value must allow
// to address all WORDS of the section
// (i.e. the *_SIZE divided by 2)
//-------------------------------------------------------
// Custom Program memory (enabled with PMEM_SIZE_CUSTOM)
`define PMEM_CUSTOM_AWIDTH 10
`define PMEM_CUSTOM_SIZE 2048
// Custom Data memory (enabled with DMEM_SIZE_CUSTOM)
`define DMEM_CUSTOM_AWIDTH 6
`define DMEM_CUSTOM_SIZE 128
// Custom Peripheral memory (enabled with PER_SIZE_CUSTOM)
`define PER_CUSTOM_AWIDTH 8
`define PER_CUSTOM_SIZE 512
//-------------------------------------------------------
// ASIC version
//-------------------------------------------------------
// When uncommented, this define will enable the
// ASIC system configuration section (see below) and
// will activate scan support for production test.
//
// WARNING: if you target an FPGA, leave this define
// commented.
//-------------------------------------------------------
//`define ASIC
//============================================================================
//============================================================================
// ASIC SYSTEM CONFIGURATION ( !!!! EXPERTS/PROFESSIONALS ONLY !!!! )
//============================================================================
//============================================================================
`ifdef ASIC
//===============================================================
// FINE GRAINED CLOCK GATING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the fine
// grained clock gating of all registers in the core.
//-------------------------------------------------------
`define CLOCK_GATING
//===============================================================
// ASIC CLOCKING
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the ASIC
// architectural clock gating as well as the advanced low
// power modes support (most common).
// Comment this out in order to get FPGA-like clocking.
//-------------------------------------------------------
`define ASIC_CLOCKING
`ifdef ASIC_CLOCKING
//===============================================================
// LFXT CLOCK DOMAIN
//===============================================================
//-------------------------------------------------------
// When uncommented, this define will enable the lfxt_clk
// clock domain.
// When commented out, the whole chip is clocked with dco_clk.
//-------------------------------------------------------
`define LFXT_DOMAIN
//===============================================================
// CLOCK MUXES
//===============================================================
//-------------------------------------------------------
// MCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELMx register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define MCLK_MUX
//-------------------------------------------------------
// SMCLK: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock MUX allowing the selection between
// DCO_CLK and LFXT_CLK with the BCSCTL2.SELS register.
// When commented, DCO_CLK is selected.
//-------------------------------------------------------
`define SMCLK_MUX
//-------------------------------------------------------
// WATCHDOG: Clock Mux
//-------------------------------------------------------
// When uncommented, this define will enable the
// Watchdog clock MUX allowing the selection between
// ACLK and SMCLK with the WDTCTL.WDTSSEL register.
// When commented out, ACLK is selected if the
// WATCHDOG_NOMUX_ACLK define is uncommented, SMCLK is
// selected otherwise.
//-------------------------------------------------------
`define WATCHDOG_MUX
//`define WATCHDOG_NOMUX_ACLK
//===============================================================
// CLOCK DIVIDERS
//===============================================================
//-------------------------------------------------------
// MCLK: Clock divider
//-------------------------------------------------------
// When uncommented, this define will enable the
// MCLK clock divider (/1/2/4/8)
//-------------------------------------------------------
`define MCLK_DIVIDER
//-------------------------------------------------------
// SMCLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// SMCLK clock divider
//-------------------------------------------------------
`define SMCLK_DIVIDER
//-------------------------------------------------------
// ACLK: Clock divider (/1/2/4/8)
//-------------------------------------------------------
// When uncommented, this define will enable the
// ACLK clock divider
//-------------------------------------------------------
`define ACLK_DIVIDER
//===============================================================
// LOW POWER MODES
//===============================================================
//-------------------------------------------------------
// LOW POWER MODE: CPUOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off MCLK in
// all low power modes: LPM0, LPM1, LPM2, LPM3, LPM4
//-------------------------------------------------------
`define CPUOFF_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG0
//-------------------------------------------------------
// When uncommented, this define will enable the
// DCO_ENABLE/WKUP port control (always 1 when commented).
// This allows to switch off the DCO oscillator in the
// following low power modes: LPM1, LPM3, LPM4
//-------------------------------------------------------
`define SCG0_EN
//-------------------------------------------------------
// LOW POWER MODE: SCG1
//-------------------------------------------------------
// When uncommented, this define will include the
// clock gate allowing to switch off SMCLK in
// the following low power modes: LPM2, LPM3, LPM4
//-------------------------------------------------------
`define SCG1_EN
//-------------------------------------------------------
// LOW POWER MODE: OSCOFF
//-------------------------------------------------------
// When uncommented, this define will include the
// LFXT_CLK clock gate and enable the LFXT_ENABLE/WKUP
// port control (always 1 when commented).
// This allows to switch off the low frequency oscillator
// in the following low power modes: LPM4
//-------------------------------------------------------
`define OSCOFF_EN
//-------------------------------------------------------
// SCAN REPAIR NEG-EDGE CLOCKED FLIP-FLOPS
//-------------------------------------------------------
// When uncommented, a scan mux will be infered to
// replace all inverted clocks with regular ones when
// in scan mode.
//
// Note: standard scan insertion tool can usually deal
// with mixed rising/falling edge FF... so there
// is usually no need to uncomment this.
//-------------------------------------------------------
//`define SCAN_REPAIR_INV_CLOCKS
`endif
`endif
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//
// PROGRAM, DATA & PERIPHERAL MEMORY CONFIGURATION
//==================================================
// Program Memory Size
`ifdef PMEM_SIZE_59_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 60416
`endif
`ifdef PMEM_SIZE_55_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 56320
`endif
`ifdef PMEM_SIZE_54_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 55296
`endif
`ifdef PMEM_SIZE_51_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 52224
`endif
`ifdef PMEM_SIZE_48_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 49152
`endif
`ifdef PMEM_SIZE_41_KB
`define PMEM_AWIDTH 15
`define PMEM_SIZE 41984
`endif
`ifdef PMEM_SIZE_32_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 32768
`endif
`ifdef PMEM_SIZE_24_KB
`define PMEM_AWIDTH 14
`define PMEM_SIZE 24576
`endif
`ifdef PMEM_SIZE_16_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 16384
`endif
`ifdef PMEM_SIZE_12_KB
`define PMEM_AWIDTH 13
`define PMEM_SIZE 12288
`endif
`ifdef PMEM_SIZE_8_KB
`define PMEM_AWIDTH 12
`define PMEM_SIZE 8192
`endif
`ifdef PMEM_SIZE_4_KB
`define PMEM_AWIDTH 11
`define PMEM_SIZE 4096
`endif
`ifdef PMEM_SIZE_2_KB
`define PMEM_AWIDTH 10
`define PMEM_SIZE 2048
`endif
`ifdef PMEM_SIZE_1_KB
`define PMEM_AWIDTH 9
`define PMEM_SIZE 1024
`endif
`ifdef PMEM_SIZE_CUSTOM
`define PMEM_AWIDTH `PMEM_CUSTOM_AWIDTH
`define PMEM_SIZE `PMEM_CUSTOM_SIZE
`endif
// Data Memory Size
`ifdef DMEM_SIZE_32_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 32768
`endif
`ifdef DMEM_SIZE_24_KB
`define DMEM_AWIDTH 14
`define DMEM_SIZE 24576
`endif
`ifdef DMEM_SIZE_16_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 16384
`endif
`ifdef DMEM_SIZE_10_KB
`define DMEM_AWIDTH 13
`define DMEM_SIZE 10240
`endif
`ifdef DMEM_SIZE_8_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 8192
`endif
`ifdef DMEM_SIZE_5_KB
`define DMEM_AWIDTH 12
`define DMEM_SIZE 5120
`endif
`ifdef DMEM_SIZE_4_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 4096
`endif
`ifdef DMEM_SIZE_2p5_KB
`define DMEM_AWIDTH 11
`define DMEM_SIZE 2560
`endif
`ifdef DMEM_SIZE_2_KB
`define DMEM_AWIDTH 10
`define DMEM_SIZE 2048
`endif
`ifdef DMEM_SIZE_1_KB
`define DMEM_AWIDTH 9
`define DMEM_SIZE 1024
`endif
`ifdef DMEM_SIZE_512_B
`define DMEM_AWIDTH 8
`define DMEM_SIZE 512
`endif
`ifdef DMEM_SIZE_256_B
`define DMEM_AWIDTH 7
`define DMEM_SIZE 256
`endif
`ifdef DMEM_SIZE_128_B
`define DMEM_AWIDTH 6
`define DMEM_SIZE 128
`endif
`ifdef DMEM_SIZE_CUSTOM
`define DMEM_AWIDTH `DMEM_CUSTOM_AWIDTH
`define DMEM_SIZE `DMEM_CUSTOM_SIZE
`endif
// Peripheral Memory Size
`ifdef PER_SIZE_32_KB
`define PER_AWIDTH 14
`define PER_SIZE 32768
`endif
`ifdef PER_SIZE_16_KB
`define PER_AWIDTH 13
`define PER_SIZE 16384
`endif
`ifdef PER_SIZE_8_KB
`define PER_AWIDTH 12
`define PER_SIZE 8192
`endif
`ifdef PER_SIZE_4_KB
`define PER_AWIDTH 11
`define PER_SIZE 4096
`endif
`ifdef PER_SIZE_2_KB
`define PER_AWIDTH 10
`define PER_SIZE 2048
`endif
`ifdef PER_SIZE_1_KB
`define PER_AWIDTH 9
`define PER_SIZE 1024
`endif
`ifdef PER_SIZE_512_B
`define PER_AWIDTH 8
`define PER_SIZE 512
`endif
`ifdef PER_SIZE_CUSTOM
`define PER_AWIDTH `PER_CUSTOM_AWIDTH
`define PER_SIZE `PER_CUSTOM_SIZE
`endif
// Data Memory Base Adresses
`define DMEM_BASE `PER_SIZE
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB `PMEM_AWIDTH-1
`define DMEM_MSB `DMEM_AWIDTH-1
`define PER_MSB `PER_AWIDTH-1
// Number of available IRQs
`ifdef IRQ_16
`define IRQ_NR 16
`endif
`ifdef IRQ_32
`define IRQ_NR 32
`define IRQ_NR_GE_32
`endif
`ifdef IRQ_64
`define IRQ_NR 64
`define IRQ_NR_GE_32
`endif
//
// STATES, REGISTER FIELDS, ...
//======================================
// Instructions type
`define INST_SO 0
`define INST_JMP 1
`define INST_TO 2
// Single-operand arithmetic
`define RRC 0
`define SWPB 1
`define RRA 2
`define SXT 3
`define PUSH 4
`define CALL 5
`define RETI 6
`define IRQ 7
// Conditional jump
`define JNE 0
`define JEQ 1
`define JNC 2
`define JC 3
`define JN 4
`define JGE 5
`define JL 6
`define JMP 7
// Two-operand arithmetic
`define MOV 0
`define ADD 1
`define ADDC 2
`define SUBC 3
`define SUB 4
`define CMP 5
`define DADD 6
`define BIT 7
`define BIC 8
`define BIS 9
`define XOR 10
`define AND 11
// Addressing modes
`define DIR 0
`define IDX 1
`define INDIR 2
`define INDIR_I 3
`define SYMB 4
`define IMM 5
`define ABS 6
`define CONST 7
// Instruction state machine
`define I_IRQ_FETCH 3'h0
`define I_IRQ_DONE 3'h1
`define I_DEC 3'h2
`define I_EXT1 3'h3
`define I_EXT2 3'h4
`define I_IDLE 3'h5
// Execution state machine
// (swapped E_IRQ_0 and E_IRQ_2 values to suppress glitch generation warning from lint tool)
`define E_IRQ_0 4'h2
`define E_IRQ_1 4'h1
`define E_IRQ_2 4'h0
`define E_IRQ_3 4'h3
`define E_IRQ_4 4'h4
`define E_SRC_AD 4'h5
`define E_SRC_RD 4'h6
`define E_SRC_WR 4'h7
`define E_DST_AD 4'h8
`define E_DST_RD 4'h9
`define E_DST_WR 4'hA
`define E_EXEC 4'hB
`define E_JUMP 4'hC
`define E_IDLE 4'hD
// ALU control signals
`define ALU_SRC_INV 0
`define ALU_INC 1
`define ALU_INC_C 2
`define ALU_ADD 3
`define ALU_AND 4
`define ALU_OR 5
`define ALU_XOR 6
`define ALU_DADD 7
`define ALU_STAT_7 8
`define ALU_STAT_F 9
`define ALU_SHIFT 10
`define EXEC_NO_WR 11
// Debug interface
`define DBG_UART_WR 18
`define DBG_UART_BW 17
`define DBG_UART_ADDR 16:11
// Debug interface CPU_CTL register
`define HALT 0
`define RUN 1
`define ISTEP 2
`define SW_BRK_EN 3
`define FRZ_BRK_EN 4
`define RST_BRK_EN 5
`define CPU_RST 6
// Debug interface CPU_STAT register
`define HALT_RUN 0
`define PUC_PND 1
`define SWBRK_PND 3
`define HWBRK0_PND 4
`define HWBRK1_PND 5
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE 1:0
`define BRK_EN 2
`define BRK_I_EN 3
`define BRK_RANGE 4
// Basic clock module: BCSCTL1 Control Register
`define DIVAx 5:4
`define DMA_CPUOFF 0
`define DMA_OSCOFF 1
`define DMA_SCG0 2
`define DMA_SCG1 3
// Basic clock module: BCSCTL2 Control Register
`define SELMx 7
`define DIVMx 5:4
`define SELS 3
`define DIVSx 2:1
// MCLK Clock gate
`ifdef CPUOFF_EN
`define MCLK_CGATE
`else
`ifdef MCLK_DIVIDER
`define MCLK_CGATE
`endif
`endif
// SMCLK Clock gate
`ifdef SCG1_EN
`define SMCLK_CGATE
`else
`ifdef SMCLK_DIVIDER
`define SMCLK_CGATE
`endif
`endif
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
// Debug interface: CPU version
// 1 - FPGA support only (Pre-BSD licence era)
// 2 - Add ASIC support
// 3 - Add DMA interface support
`define CPU_VERSION 3'h3
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
// Debug UART interface data rate
// In order to properly setup the UART debug interface, you
// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
// the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD 9600
//`define DBG_UART_BAUD 19200
//`define DBG_UART_BAUD 38400
//`define DBG_UART_BAUD 57600
//`define DBG_UART_BAUD 115200
//`define DBG_UART_BAUD 230400
//`define DBG_UART_BAUD 460800
//`define DBG_UART_BAUD 576000
//`define DBG_UART_BAUD 921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ 20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
// Debug interface input synchronizer
`define SYNC_DBG_UART_RXD
// Enable/Disable the hardware breakpoint RANGE mode
`ifdef DBG_HWBRK_RANGE
`define HWBRK_RANGE 1'b1
`else
`define HWBRK_RANGE 1'b0
`endif
// Counter width for the debug interface UART
`define DBG_UART_XFER_CNT_W 16
// Check configuration
`ifdef DBG_EN
`ifdef DBG_UART
`ifdef DBG_I2C
CONFIGURATION ERROR: I2C AND UART DEBUG INTERFACE ARE BOTH ENABLED
`endif
`else
`ifdef DBG_I2C
`else
CONFIGURATION ERROR: I2C OR UART DEBUG INTERFACE SHOULD BE ENABLED
`endif
`endif
`endif
//
// MULTIPLIER CONFIGURATION
//======================================
// If uncommented, the following define selects
// the 16x16 multiplier (1 cycle) instead of the
// default 16x8 multplier (2 cycles)
//`define MPY_16x16
//======================================
// CONFIGURATION CHECKS
//======================================
`ifdef IRQ_16
`ifdef IRQ_32
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef IRQ_32
`ifdef IRQ_64
CONFIGURATION ERROR: ONLY ONE OF THE IRQ NUMBER OPTION CAN BE SELECTED
`endif
`endif
`ifdef LFXT_DOMAIN
`else
`ifdef MCLK_MUX
CONFIGURATION ERROR: THE MCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef SMCLK_MUX
CONFIGURATION ERROR: THE SMCLK_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`ifdef WATCHDOG_MUX
CONFIGURATION ERROR: THE WATCHDOG_MUX CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`else
`ifdef WATCHDOG_NOMUX_ACLK
CONFIGURATION ERROR: THE WATCHDOG_NOMUX_ACLK CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
`ifdef OSCOFF_EN
CONFIGURATION ERROR: THE OSCOFF LOW POWER MODE CAN ONLY BE ENABLED IF THE LFXT_DOMAIN IS ENABLED AS WELL
`endif
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SDLXTP_1_V
`define SKY130_FD_SC_HVL__SDLXTP_1_V
/**
* sdlxtp: ????.
*
* Verilog wrapper for sdlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__sdlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlxtp_1 (
Q ,
D ,
SCD ,
SCE ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__sdlxtp_1 (
Q ,
D ,
SCD ,
SCE ,
GATE
);
output Q ;
input D ;
input SCD ;
input SCE ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__sdlxtp base (
.Q(Q),
.D(D),
.SCD(SCD),
.SCE(SCE),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SDLXTP_1_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_qpll_drp.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_qpll_drp.v
// Description : QPLL DRP Module for 7 Series Transceiver
// Version : 20.2
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- QPLL DRP Module ---------------------------------------------------
module pcie3_7x_0_qpll_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter LOAD_CNT_MAX = 2'd3, // Load max count
parameter INDEX_MAX = 3'd6 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_OVRD,
input DRP_GEN3,
input DRP_QPLLLOCK,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 7:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output DRP_QPLLRESET,
output [ 5:0] DRP_CRSCODE,
output [ 8:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg ovrd_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg qplllock_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 2:0] index = 3'd0;
reg mode = 1'd0;
reg [ 5:0] crscode = 6'd0;
//---------- Output Registers --------------------------
reg [ 7:0] addr = 8'd0;
reg [15:0] di = 16'd0;
reg done = 1'd0;
reg [ 8:0] fsm = 7'd1;
//---------- DRP Address -------------------------------
localparam ADDR_QPLL_FBDIV = 8'h36;
localparam ADDR_QPLL_CFG = 8'h32;
localparam ADDR_QPLL_LPF = 8'h31;
localparam ADDR_CRSCODE = 8'h88;
localparam ADDR_QPLL_COARSE_FREQ_OVRD = 8'h35;
localparam ADDR_QPLL_COARSE_FREQ_OVRD_EN = 8'h36;
localparam ADDR_QPLL_LOCK_CFG = 8'h34;
//---------- DRP Mask ----------------------------------
localparam MASK_QPLL_FBDIV = 16'b1111110000000000; // Unmask bit [ 9: 0]
localparam MASK_QPLL_CFG = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_QPLL_LPF = 16'b1000011111111111; // Unmask bit [14:11]
localparam MASK_QPLL_COARSE_FREQ_OVRD = 16'b0000001111111111; // Unmask bit [15:10]
localparam MASK_QPLL_COARSE_FREQ_OVRD_EN = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_QPLL_LOCK_CFG = 16'b1110011111111111; // Unmask bit [12:11]
//---------- DRP Data for Normal QPLLLOCK Mode ---------
localparam NORM_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam NORM_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000000000000000; // Normal QPLL lock
localparam NORM_QPLL_LOCK_CFG = 16'b0000000000000000; // Normal QPLL lock config
//---------- DRP Data for Optimize QPLLLOCK Mode -------
localparam OVRD_QPLL_COARSE_FREQ_OVRD = 16'b0000000000000000; // Coarse freq value
localparam OVRD_QPLL_COARSE_FREQ_OVRD_EN = 16'b0000100000000000; // Override QPLL lock
localparam OVRD_QPLL_LOCK_CFG = 16'b0000000000000000; // Override QPLL lock config
//---------- Select QPLL Feedback Divider --------------
// N = 100 for 100 MHz ref clk and 10Gb/s line rate
// N = 80 for 125 MHz ref clk and 10Gb/s line rate
// N = 40 for 250 MHz ref clk and 10Gb/s line rate
//------------------------------------------------------
// N = 80 for 100 MHz ref clk and 8Gb/s line rate
// N = 64 for 125 MHz ref clk and 8Gb/s line rate
// N = 32 for 250 MHz ref clk and 8Gb/s line rate
//------------------------------------------------------
localparam QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000100100000 :
(PCIE_REFCLK_FREQ == 0) && (PCIE_PLL_SEL == "QPLL") ? 16'b0000000101110000 :
(PCIE_REFCLK_FREQ == 2) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) && (PCIE_PLL_SEL == "CPLL") ? 16'b0000000011100000 : 16'b0000000100100000;
localparam GEN12_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000010000000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000100100000 : 16'b0000000101110000;
localparam GEN3_QPLL_FBDIV = (PCIE_REFCLK_FREQ == 2) ? 16'b0000000001100000 :
(PCIE_REFCLK_FREQ == 1) ? 16'b0000000011100000 : 16'b0000000100100000;
//---------- Select QPLL Configuration ---------------------------
// QPLL_CFG[6] = 0 for upper band
// = 1 for lower band
//----------------------------------------------------------------
localparam GEN12_QPLL_CFG = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000000 : 16'b0000000001000000;
localparam GEN3_QPLL_CFG = 16'b0000000001000000;
//---------- Select QPLL LPF -------------------------------------
localparam GEN12_QPLL_LPF = (PCIE_PLL_SEL == "QPLL") ? 16'b0_0100_00000000000 : 16'b0_1101_00000000000;
localparam GEN3_QPLL_LPF = 16'b0_1101_00000000000;
//---------- DRP Data ----------------------------------
wire [15:0] data_qpll_fbdiv;
wire [15:0] data_qpll_cfg;
wire [15:0] data_qpll_lpf;
wire [15:0] data_qpll_coarse_freq_ovrd;
wire [15:0] data_qpll_coarse_freq_ovrd_en;
wire [15:0] data_qpll_lock_cfg;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 9'b000000001;
localparam FSM_LOAD = 9'b000000010;
localparam FSM_READ = 9'b000000100;
localparam FSM_RRDY = 9'b000001000;
localparam FSM_WRITE = 9'b000010000;
localparam FSM_WRDY = 9'b000100000;
localparam FSM_DONE = 9'b001000000;
localparam FSM_QPLLRESET = 9'b010000000;
localparam FSM_QPLLLOCK = 9'b100000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= 1'd0;
gen3_reg1 <= 1'd0;
qplllock_reg1 <= 1'd0;
start_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= 1'd0;
gen3_reg2 <= 1'd0;
qplllock_reg2 <= 1'd0;
start_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
ovrd_reg1 <= DRP_OVRD;
gen3_reg1 <= DRP_GEN3;
qplllock_reg1 <= DRP_QPLLLOCK;
start_reg1 <= DRP_START;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
//---------- 2nd Stage FF --------------------------
ovrd_reg2 <= ovrd_reg1;
gen3_reg2 <= gen3_reg1;
qplllock_reg2 <= qplllock_reg1;
start_reg2 <= start_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_qpll_fbdiv = (gen3_reg2) ? GEN3_QPLL_FBDIV : GEN12_QPLL_FBDIV;
assign data_qpll_cfg = (gen3_reg2) ? GEN3_QPLL_CFG : GEN12_QPLL_CFG;
assign data_qpll_lpf = (gen3_reg2) ? GEN3_QPLL_LPF : GEN12_QPLL_LPF;
assign data_qpll_coarse_freq_ovrd = NORM_QPLL_COARSE_FREQ_OVRD;
assign data_qpll_coarse_freq_ovrd_en = (ovrd_reg2) ? OVRD_QPLL_COARSE_FREQ_OVRD_EN : NORM_QPLL_COARSE_FREQ_OVRD_EN;
assign data_qpll_lock_cfg = (ovrd_reg2) ? OVRD_QPLL_LOCK_CFG : NORM_QPLL_LOCK_CFG;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
else
begin
case (index)
//--------------------------------------------------
3'd0 :
begin
addr <= ADDR_QPLL_FBDIV;
di <= (do_reg2 & MASK_QPLL_FBDIV) | (mode ? data_qpll_fbdiv : QPLL_FBDIV);
crscode <= crscode;
end
//--------------------------------------------------
3'd1 :
begin
addr <= ADDR_QPLL_CFG;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_CFG) | data_qpll_cfg;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_cfg;
crscode <= crscode;
end
//--------------------------------------------------
3'd2 :
begin
addr <= ADDR_QPLL_LPF;
if (PCIE_GT_DEVICE == "GTX")
di <= (do_reg2 & MASK_QPLL_LPF) | data_qpll_lpf;
else
di <= (do_reg2 & 16'hFFFF) | data_qpll_lpf;
crscode <= crscode;
end
//--------------------------------------------------
3'd3 :
begin
addr <= ADDR_CRSCODE;
di <= do_reg2;
//---------- Latch CRS Code --------------------
if (ovrd_reg2)
crscode <= do_reg2[6:1];
else
crscode <= crscode;
end
//--------------------------------------------------
3'd4 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD) | {(crscode - 6'd1), data_qpll_coarse_freq_ovrd[9:0]};
crscode <= crscode;
end
//--------------------------------------------------
3'd5 :
begin
addr <= ADDR_QPLL_COARSE_FREQ_OVRD_EN;
di <= (do_reg2 & MASK_QPLL_COARSE_FREQ_OVRD_EN) | data_qpll_coarse_freq_ovrd_en;
crscode <= crscode;
end
//--------------------------------------------------
3'd6 :
begin
addr <= ADDR_QPLL_LOCK_CFG;
di <= (do_reg2 & MASK_QPLL_LOCK_CFG) | data_qpll_lock_cfg;
crscode <= crscode;
end
//--------------------------------------------------
default :
begin
addr <= 8'd0;
di <= 16'd0;
crscode <= 6'd0;
end
endcase
end
end
//---------- QPLL DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
else if ((gen3_reg2 != gen3_reg1) && (PCIE_PLL_SEL == "QPLL"))
begin
fsm <= FSM_LOAD;
index <= 3'd0;
mode <= 1'd1;
done <= 1'd0;
end
else
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= (rdy_reg2 ? FSM_WRITE : FSM_RRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= (rdy_reg2 ? FSM_DONE : FSM_WRDY);
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 3'd2)))
begin
fsm <= mode ? FSM_QPLLRESET : FSM_IDLE;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 3'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- QPLL Reset ----------------------------
FSM_QPLLRESET :
begin
fsm <= !qplllock_reg2 ? FSM_QPLLLOCK : FSM_QPLLRESET;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- QPLL Reset ----------------------------
FSM_QPLLLOCK :
begin
fsm <= qplllock_reg2 ? FSM_IDLE : FSM_QPLLLOCK;
index <= 3'd0;
mode <= mode;
done <= 1'd0;
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 3'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- QPLL DRP Output ---------------------------------------------------
assign DRP_ADDR = addr;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di;
assign DRP_WE = (fsm == FSM_WRITE); // || (fsm == FSM_WRDY);
assign DRP_DONE = done;
assign DRP_QPLLRESET = (fsm == FSM_QPLLRESET);
assign DRP_CRSCODE = crscode;
assign DRP_FSM = fsm;
endmodule
|
// (C) 2001-2016 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/16.1/ip/merlin/altera_reset_controller/altera_reset_controller.v#1 $
// $Revision: #1 $
// $Date: 2016/08/07 $
// $Author: swbranch $
// --------------------------------------
// Reset controller
//
// Combines all the input resets and synchronizes
// the result to the clk.
// ACDS13.1 - Added reset request as part of reset sequencing
// --------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_controller
#(
parameter NUM_RESET_INPUTS = 6,
parameter USE_RESET_REQUEST_IN0 = 0,
parameter USE_RESET_REQUEST_IN1 = 0,
parameter USE_RESET_REQUEST_IN2 = 0,
parameter USE_RESET_REQUEST_IN3 = 0,
parameter USE_RESET_REQUEST_IN4 = 0,
parameter USE_RESET_REQUEST_IN5 = 0,
parameter USE_RESET_REQUEST_IN6 = 0,
parameter USE_RESET_REQUEST_IN7 = 0,
parameter USE_RESET_REQUEST_IN8 = 0,
parameter USE_RESET_REQUEST_IN9 = 0,
parameter USE_RESET_REQUEST_IN10 = 0,
parameter USE_RESET_REQUEST_IN11 = 0,
parameter USE_RESET_REQUEST_IN12 = 0,
parameter USE_RESET_REQUEST_IN13 = 0,
parameter USE_RESET_REQUEST_IN14 = 0,
parameter USE_RESET_REQUEST_IN15 = 0,
parameter OUTPUT_RESET_SYNC_EDGES = "deassert",
parameter SYNC_DEPTH = 2,
parameter RESET_REQUEST_PRESENT = 0,
parameter RESET_REQ_WAIT_TIME = 3,
parameter MIN_RST_ASSERTION_TIME = 11,
parameter RESET_REQ_EARLY_DSRT_TIME = 4,
parameter ADAPT_RESET_REQUEST = 0
)
(
// --------------------------------------
// We support up to 16 reset inputs, for now
// --------------------------------------
input reset_in0,
input reset_in1,
input reset_in2,
input reset_in3,
input reset_in4,
input reset_in5,
input reset_in6,
input reset_in7,
input reset_in8,
input reset_in9,
input reset_in10,
input reset_in11,
input reset_in12,
input reset_in13,
input reset_in14,
input reset_in15,
input reset_req_in0,
input reset_req_in1,
input reset_req_in2,
input reset_req_in3,
input reset_req_in4,
input reset_req_in5,
input reset_req_in6,
input reset_req_in7,
input reset_req_in8,
input reset_req_in9,
input reset_req_in10,
input reset_req_in11,
input reset_req_in12,
input reset_req_in13,
input reset_req_in14,
input reset_req_in15,
input clk,
output reg reset_out,
output reg reset_req
);
// Always use async reset synchronizer if reset_req is used
localparam ASYNC_RESET = (OUTPUT_RESET_SYNC_EDGES == "deassert");
// --------------------------------------
// Local parameter to control the reset_req and reset_out timing when RESET_REQUEST_PRESENT==1
// --------------------------------------
localparam MIN_METASTABLE = 3;
localparam RSTREQ_ASRT_SYNC_TAP = MIN_METASTABLE + RESET_REQ_WAIT_TIME;
localparam LARGER = RESET_REQ_WAIT_TIME > RESET_REQ_EARLY_DSRT_TIME ? RESET_REQ_WAIT_TIME : RESET_REQ_EARLY_DSRT_TIME;
localparam ASSERTION_CHAIN_LENGTH = (MIN_METASTABLE > LARGER) ?
MIN_RST_ASSERTION_TIME + 1 :
(
(MIN_RST_ASSERTION_TIME > LARGER)?
MIN_RST_ASSERTION_TIME + (LARGER - MIN_METASTABLE + 1) + 1 :
MIN_RST_ASSERTION_TIME + RESET_REQ_EARLY_DSRT_TIME + RESET_REQ_WAIT_TIME - MIN_METASTABLE + 2
);
localparam RESET_REQ_DRST_TAP = RESET_REQ_EARLY_DSRT_TIME + 1;
// --------------------------------------
wire merged_reset;
wire merged_reset_req_in;
wire reset_out_pre;
wire reset_req_pre;
// Registers and Interconnect
(*preserve*) reg [RSTREQ_ASRT_SYNC_TAP: 0] altera_reset_synchronizer_int_chain;
reg [ASSERTION_CHAIN_LENGTH-1: 0] r_sync_rst_chain;
reg r_sync_rst;
reg r_early_rst;
// --------------------------------------
// "Or" all the input resets together
// --------------------------------------
assign merged_reset = (
reset_in0 |
reset_in1 |
reset_in2 |
reset_in3 |
reset_in4 |
reset_in5 |
reset_in6 |
reset_in7 |
reset_in8 |
reset_in9 |
reset_in10 |
reset_in11 |
reset_in12 |
reset_in13 |
reset_in14 |
reset_in15
);
assign merged_reset_req_in = (
( (USE_RESET_REQUEST_IN0 == 1) ? reset_req_in0 : 1'b0) |
( (USE_RESET_REQUEST_IN1 == 1) ? reset_req_in1 : 1'b0) |
( (USE_RESET_REQUEST_IN2 == 1) ? reset_req_in2 : 1'b0) |
( (USE_RESET_REQUEST_IN3 == 1) ? reset_req_in3 : 1'b0) |
( (USE_RESET_REQUEST_IN4 == 1) ? reset_req_in4 : 1'b0) |
( (USE_RESET_REQUEST_IN5 == 1) ? reset_req_in5 : 1'b0) |
( (USE_RESET_REQUEST_IN6 == 1) ? reset_req_in6 : 1'b0) |
( (USE_RESET_REQUEST_IN7 == 1) ? reset_req_in7 : 1'b0) |
( (USE_RESET_REQUEST_IN8 == 1) ? reset_req_in8 : 1'b0) |
( (USE_RESET_REQUEST_IN9 == 1) ? reset_req_in9 : 1'b0) |
( (USE_RESET_REQUEST_IN10 == 1) ? reset_req_in10 : 1'b0) |
( (USE_RESET_REQUEST_IN11 == 1) ? reset_req_in11 : 1'b0) |
( (USE_RESET_REQUEST_IN12 == 1) ? reset_req_in12 : 1'b0) |
( (USE_RESET_REQUEST_IN13 == 1) ? reset_req_in13 : 1'b0) |
( (USE_RESET_REQUEST_IN14 == 1) ? reset_req_in14 : 1'b0) |
( (USE_RESET_REQUEST_IN15 == 1) ? reset_req_in15 : 1'b0)
);
// --------------------------------------
// And if required, synchronize it to the required clock domain,
// with the correct synchronization type
// --------------------------------------
generate if (OUTPUT_RESET_SYNC_EDGES == "none" && (RESET_REQUEST_PRESENT==0)) begin
assign reset_out_pre = merged_reset;
assign reset_req_pre = merged_reset_req_in;
end else begin
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(RESET_REQUEST_PRESENT? 1'b1 : ASYNC_RESET)
)
alt_rst_sync_uq1
(
.clk (clk),
.reset_in (merged_reset),
.reset_out (reset_out_pre)
);
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH),
.ASYNC_RESET(0)
)
alt_rst_req_sync_uq1
(
.clk (clk),
.reset_in (merged_reset_req_in),
.reset_out (reset_req_pre)
);
end
endgenerate
generate if ( ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==0) )|
( (ADAPT_RESET_REQUEST == 1) && (OUTPUT_RESET_SYNC_EDGES != "deassert") ) ) begin
always @* begin
reset_out = reset_out_pre;
reset_req = reset_req_pre;
end
end else if ( (RESET_REQUEST_PRESENT == 0) && (ADAPT_RESET_REQUEST==1) ) begin
wire reset_out_pre2;
altera_reset_synchronizer
#(
.DEPTH (SYNC_DEPTH+1),
.ASYNC_RESET(0)
)
alt_rst_sync_uq2
(
.clk (clk),
.reset_in (reset_out_pre),
.reset_out (reset_out_pre2)
);
always @* begin
reset_out = reset_out_pre2;
reset_req = reset_req_pre;
end
end
else begin
// 3-FF Metastability Synchronizer
initial
begin
altera_reset_synchronizer_int_chain <= {RSTREQ_ASRT_SYNC_TAP{1'b1}};
end
always @(posedge clk)
begin
altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP:0] <=
{altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP-1:0], reset_out_pre};
end
// Synchronous reset pipe
initial
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
always @(posedge clk)
begin
if (altera_reset_synchronizer_int_chain[MIN_METASTABLE-1] == 1'b1)
begin
r_sync_rst_chain <= {ASSERTION_CHAIN_LENGTH{1'b1}};
end
else
begin
r_sync_rst_chain <= {1'b0, r_sync_rst_chain[ASSERTION_CHAIN_LENGTH-1:1]};
end
end
// Standard synchronous reset output. From 0-1, the transition lags the early output. For 1->0, the transition
// matches the early input.
always @(posedge clk)
begin
case ({altera_reset_synchronizer_int_chain[RSTREQ_ASRT_SYNC_TAP], r_sync_rst_chain[1], r_sync_rst})
3'b000: r_sync_rst <= 1'b0; // Not reset
3'b001: r_sync_rst <= 1'b0;
3'b010: r_sync_rst <= 1'b0;
3'b011: r_sync_rst <= 1'b1;
3'b100: r_sync_rst <= 1'b1;
3'b101: r_sync_rst <= 1'b1;
3'b110: r_sync_rst <= 1'b1;
3'b111: r_sync_rst <= 1'b1; // In Reset
default: r_sync_rst <= 1'b1;
endcase
case ({r_sync_rst_chain[1], r_sync_rst_chain[RESET_REQ_DRST_TAP] | reset_req_pre})
2'b00: r_early_rst <= 1'b0; // Not reset
2'b01: r_early_rst <= 1'b1; // Coming out of reset
2'b10: r_early_rst <= 1'b0; // Spurious reset - should not be possible via synchronous design.
2'b11: r_early_rst <= 1'b1; // Held in reset
default: r_early_rst <= 1'b1;
endcase
end
always @* begin
reset_out = r_sync_rst;
reset_req = r_early_rst;
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__TAPVGND2_FUNCTIONAL_V
`define SKY130_FD_SC_MS__TAPVGND2_FUNCTIONAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__tapvgnd2 ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__TAPVGND2_FUNCTIONAL_V |
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module localram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4 localram0(
.DO (data_out[3:0]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[3:0]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram0.INIT_00 = 256'hCA40C840C8404001C840C840C840CA40C840C840400409014DA0804000000203;
defparam localram0.INIT_01 = 256'h002000000C0002044200000400C1000040C81480884114808010C840C840C840;
defparam localram0.INIT_02 = 256'h41060C1208C2001C0008F001C0008C0704810C0000CC20000080CF0000040030;
defparam localram0.INIT_03 = 256'h00100004FF0000C00F000080854880000D040750001000C00808508880008008;
defparam localram0.INIT_04 = 256'h0000000001000000050010040F000000040040F410407AF4420000000000C005;
defparam localram0.INIT_05 = 256'h4101041041410041041441004104104104444444400000000000000000000000;
defparam localram0.INIT_06 = 256'h0000041041041041041041044101041041410404104141004104104104104104;
defparam localram0.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram1(
.DO (data_out[7:4]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[7:4]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram1.INIT_00 = 256'h3333222211110005666655554444333322221111009105000F20F00000000100;
defparam localram1.INIT_01 = 256'h0000000001000C011000000100F00000013323C0000220F00007666655554444;
defparam localram1.INIT_02 = 256'h20010020010000258010F0025801000D121201220021000000202F00000200B0;
defparam localram1.INIT_03 = 256'h00200002FF0000100F0000202202200000020C60110010D00202202020000000;
defparam localram1.INIT_04 = 256'h0000000600000020020020000F00000200000010000002F00000000200001002;
defparam localram1.INIT_05 = 256'h0010100100001100100000110010010010000000000000000000000000000000;
defparam localram1.INIT_06 = 256'h0000100100100100100100100010100100001010010000110010010010010010;
defparam localram1.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram2(
.DO (data_out[11:8]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[11:8]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram2.INIT_00 = 256'h000000000000000000000000000000000000000000F000000F80F08080800000;
defparam localram2.INIT_01 = 256'h002F0000000000800400000000F00F08000000F0000800F00000000000000000;
defparam localram2.INIT_02 = 256'h00000082000200050000000050000000000000004000400000000F0000000000;
defparam localram2.INIT_03 = 256'h008200000F0000000F0000000000000000000F00000000000000000000000400;
defparam localram2.INIT_04 = 256'h0000000000800000000084000F00000000100010100000E00400000000000000;
defparam localram2.INIT_05 = 256'h1118765432111DCBA987111321FEDC1111111111100000000000000000000000;
defparam localram2.INIT_06 = 256'h0000BA98765432111DCBA987111321FEDC1118765432111DCBA987111321FEDC;
defparam localram2.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram3(
.DO (data_out[15:12]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[15:12]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram3.INIT_00 = 256'h000000000000000000000000000000000000000000F000600F10101010100000;
defparam localram3.INIT_01 = 256'h001F0000001000000100000010F001010000F0F0000EF0F60700000000000000;
defparam localram3.INIT_02 = 256'h00000011000100102000000102000000000100001000100000010F0000001000;
defparam localram3.INIT_03 = 256'h001100010F0000010F0000010100000100000F00000000000010100000010100;
defparam localram3.INIT_04 = 256'h0000000000100001010011000F00000010000000000001F00100000010000101;
defparam localram3.INIT_05 = 256'h0002222222000111111100011100000000000000000000000000000000000000;
defparam localram3.INIT_06 = 256'h0000666666666600055555550005554444000444444400033333330003332222;
defparam localram3.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram4(
.DO (data_out[19:16]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[19:16]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram4.INIT_00 = 256'hEDCBA98765432100F9876543210FEDCBA987654321D000884050DD5544CC0000;
defparam localram4.INIT_01 = 256'h2222022022200223220220222022320200540ED00DE00EDA0BADF9876543210F;
defparam localram4.INIT_02 = 256'h2202020202220222232220222232000000220232202220220222220220222000;
defparam localram4.INIT_03 = 256'h0202022222320222220220232223202200020020222020020232302320222202;
defparam localram4.INIT_04 = 256'h0000000022320232220202022202202222202002202002232202202222023222;
defparam localram4.INIT_05 = 256'h1118765432111DCBA987111321FEDC1811111111100000000000000000000000;
defparam localram4.INIT_06 = 256'h0000BA98765432111DCBA987111321FEDC1118765432111DCBA987111321FEDC;
defparam localram4.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram5(
.DO (data_out[23:20]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[23:20]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram5.INIT_00 = 256'hAAAAAAAAAAAAAA00BBBBBBBBBBBAAAAAAAAAAAAAAAB000808688B1A080910000;
defparam localram5.INIT_01 = 256'hCC040880440C060CC008804400604040CCCCABB0EBBCABB9611BBBBBBBBBBBBA;
defparam localram5.INIT_02 = 256'hC0060C400CC0048600CC4048600CCC00CCC60CCC00CC00880440C40880440040;
defparam localram5.INIT_03 = 256'h08400C8640880440C40C60C0C60CC040040C0440CC40C0060C0C40CCC040C00C;
defparam localram5.INIT_04 = 256'h00000000600608408608400C840880440C40C00C40C0460CC008804406084086;
defparam localram5.INIT_05 = 256'h0002222222000111111100011100000A00000000000000000000000000000000;
defparam localram5.INIT_06 = 256'h0000666666666600055555550005554444000444444400033333330003332222;
defparam localram5.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram6(
.DO (data_out[27:24]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[27:24]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram6.INIT_00 = 256'hFFFFFFFFFFFFFF0CFFFFFFFFFFFFFFFFFFFFFFFFFF780C04440C7C4C4C7C0000;
defparam localram6.INIT_01 = 256'hFF000FF0C4CF044FF00FF0C4C044CCCCFFFF3F7037F33F703047FFFFFFFFFFFF;
defparam localram6.INIT_02 = 256'hF4040F000FF00C040CFF00C040CFFF08FFF00FFF00FF00FF0C4CF00FF0C4C000;
defparam localram6.INIT_03 = 256'h0F000FF04CFF0C4CF40FC0FCF0CFF0CC040F0480FF40F08C0FCF00FFF0CCF00F;
defparam localram6.INIT_04 = 256'h00000008C4CC0F4CF00F000FF00FF0C4CF40F08F40F0404FF00FF0C4CC0F4CF0;
defparam localram6.INIT_05 = 256'hA988765432A98DCBA987A98321FEDCA081111111100000000000000000000000;
defparam localram6.INIT_06 = 256'h0000BA98765432A98DCBA987A98321FEDCA988765432A98DCBA987A98321FEDC;
defparam localram6.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram7(
.DO (data_out[31:28]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[31:28]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram7.INIT_00 = 256'h8888888888888800AAAAAAAAAAAAAAAAAAAAAAAAAA200043210A333333330101;
defparam localram7.INIT_01 = 256'h8A0308A0833A0128A008A083301283A3AAAA0A2002800A240432888888888888;
defparam localram7.INIT_02 = 256'hA201080008A00802038A30802038AA00AAA0088A008A008A0833A308A0833010;
defparam localram7.INIT_03 = 256'h080008A0338A0833A208A083A038A083010801208A20800A083A0088A083A008;
defparam localram7.INIT_04 = 256'h00000000A23A0833A0080008A308A0833A20800A20801038A008A0833A0833A0;
defparam localram7.INIT_05 = 256'h3330000000222000000011100000000C00000000000000000000000000000000;
defparam localram7.INIT_06 = 256'h0000000000000088800000007770000000666000000055500000004440000000;
defparam localram7.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_PP_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkinv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_FUNCTIONAL_PP_V |
//////////////////////////////////////////////////////////////////
// //
// Top-level module instantiating the entire Amber 2 system. //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// This is the highest level synthesizable module in the //
// project. The ports in this module represent pins on the //
// FPGA. //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`define AMBER_A25_CORE
`include "system_config_defines.v"
module system
(
input brd_rst,
input brd_clk_n,
input brd_clk_p,
// UART 0 Interface
input i_uart0_rts,
output o_uart0_rx,
output o_uart0_cts,
input i_uart0_tx,
// Xilinx Spartan 6 MCB DDR3 Interface
inout [15:0] ddr3_dq,
output [12:0] ddr3_addr,
output [2:0] ddr3_ba,
output ddr3_ras_n,
output ddr3_cas_n,
output ddr3_we_n,
output ddr3_odt,
output ddr3_reset_n,
output ddr3_cke,
output [1:0] ddr3_dm,
inout [1:0] ddr3_dqs_p,
inout [1:0] ddr3_dqs_n,
output ddr3_ck_p,
output ddr3_ck_n,
`ifdef XILINX_SPARTAN6_FPGA
inout mcb3_rzq,
`endif
// Ethmac B100 MAC to PHY Interface
input mtx_clk_pad_i,
output [3:0] mtxd_pad_o,
output mtxen_pad_o,
output mtxerr_pad_o,
input mrx_clk_pad_i,
input [3:0] mrxd_pad_i,
input mrxdv_pad_i,
input mrxerr_pad_i,
input mcoll_pad_i,
input mcrs_pad_i,
inout md_pad_io,
output mdc_pad_o,
output phy_reset_n,
output [3:0] led
);
wire sys_clk; // System clock
wire sys_rst; // Active high reset, synchronous to sys_clk
wire clk_200; // 200MHz from board
// ======================================
// Xilinx MCB DDR3 Controller connections
// ======================================
`ifdef XILINX_SPARTAN6_FPGA
wire c3_p0_cmd_en;
wire [2:0] c3_p0_cmd_instr;
wire [29:0] c3_p0_cmd_byte_addr;
wire c3_p0_wr_en;
wire [15:0] c3_p0_wr_mask;
wire [127:0] c3_p0_wr_data;
wire [127:0] c3_p0_rd_data;
wire c3_p0_rd_empty;
wire c3_p0_cmd_full;
wire c3_p0_wr_full;
`endif
wire phy_init_done;
wire test_mem_ctrl;
wire system_rdy;
// ======================================
// Ethmac MII
// ======================================
wire md_pad_i;
wire md_pad_o;
wire md_padoe_o;
// ======================================
// Wishbone Buses
// ======================================
localparam WB_MASTERS = 2;
localparam WB_SLAVES = 9;
`ifdef AMBER_A25_CORE
localparam WB_DWIDTH = 128;
localparam WB_SWIDTH = 16;
`else
localparam WB_DWIDTH = 32;
localparam WB_SWIDTH = 4;
`endif
// Wishbone Master Buses
wire [31:0] m_wb_adr [WB_MASTERS-1:0];
wire [WB_SWIDTH-1:0] m_wb_sel [WB_MASTERS-1:0];
wire [WB_MASTERS-1:0] m_wb_we ;
wire [WB_DWIDTH-1:0] m_wb_dat_w [WB_MASTERS-1:0];
wire [WB_DWIDTH-1:0] m_wb_dat_r [WB_MASTERS-1:0];
wire [WB_MASTERS-1:0] m_wb_cyc ;
wire [WB_MASTERS-1:0] m_wb_stb ;
wire [WB_MASTERS-1:0] m_wb_ack ;
wire [WB_MASTERS-1:0] m_wb_err ;
// Wishbone Slave Buses
wire [31:0] s_wb_adr [WB_SLAVES-1:0];
wire [WB_SWIDTH-1:0] s_wb_sel [WB_SLAVES-1:0];
wire [WB_SLAVES-1:0] s_wb_we ;
wire [WB_DWIDTH-1:0] s_wb_dat_w [WB_SLAVES-1:0];
wire [WB_DWIDTH-1:0] s_wb_dat_r [WB_SLAVES-1:0];
wire [WB_SLAVES-1:0] s_wb_cyc ;
wire [WB_SLAVES-1:0] s_wb_stb ;
wire [WB_SLAVES-1:0] s_wb_ack ;
wire [WB_SLAVES-1:0] s_wb_err ;
wire [31:0] emm_wb_adr;
wire [3:0] emm_wb_sel;
wire emm_wb_we;
wire [31:0] emm_wb_rdat;
wire [31:0] emm_wb_wdat;
wire emm_wb_cyc;
wire emm_wb_stb;
wire emm_wb_ack;
wire emm_wb_err;
wire [31:0] ems_wb_adr;
wire [3:0] ems_wb_sel;
wire ems_wb_we;
wire [31:0] ems_wb_rdat;
wire [31:0] ems_wb_wdat;
wire ems_wb_cyc;
wire ems_wb_stb;
wire ems_wb_ack;
wire ems_wb_err;
// ======================================
// Interrupts
// ======================================
wire amber_irq;
wire amber_firq;
wire ethmac_int;
wire test_reg_irq;
wire test_reg_firq;
wire uart0_int;
wire uart1_int;
wire [2:0] timer_int;
// ======================================
// Clocks and Resets Module
// ======================================
clocks_resets u_clocks_resets (
.i_brd_rst ( brd_rst ),
.i_brd_clk_n ( brd_clk_n ),
.i_brd_clk_p ( brd_clk_p ),
.i_ddr_calib_done ( phy_init_done ),
.o_sys_rst ( sys_rst ),
.o_sys_clk ( sys_clk ),
.o_clk_200 ( clk_200 )
);
// -------------------------------------------------------------
// Instantiate Amber Processor Core
// -------------------------------------------------------------
//`ifdef AMBER_A25_CORE
a25_core u_amber (
//`else
//a23_core u_amber (
//`endif
.i_clk ( sys_clk ),
.i_irq ( amber_irq ),
.i_firq ( amber_firq ),
.i_system_rdy ( system_rdy ),
.o_wb_adr ( m_wb_adr [1] ),
.o_wb_sel ( m_wb_sel [1] ),
.o_wb_we ( m_wb_we [1] ),
.i_wb_dat ( m_wb_dat_r[1] ),
.o_wb_dat ( m_wb_dat_w[1] ),
.o_wb_cyc ( m_wb_cyc [1] ),
.o_wb_stb ( m_wb_stb [1] ),
.i_wb_ack ( m_wb_ack [1] ),
.i_wb_err ( m_wb_err [1] )
);
// -------------------------------------------------------------
// Instantiate B100 Ethernet MAC
// -------------------------------------------------------------
eth_top u_eth_top (
.wb_clk_i ( sys_clk ),
.wb_rst_i ( sys_rst ),
// WISHBONE slave
.wb_adr_i ( ems_wb_adr [11:2] ),
.wb_sel_i ( ems_wb_sel ),
.wb_we_i ( ems_wb_we ),
.wb_cyc_i ( ems_wb_cyc ),
.wb_stb_i ( ems_wb_stb ),
.wb_ack_o ( ems_wb_ack ),
.wb_dat_i ( ems_wb_wdat ),
.wb_dat_o ( ems_wb_rdat ),
.wb_err_o ( ems_wb_err ),
// WISHBONE master
.m_wb_adr_o ( emm_wb_adr ),
.m_wb_sel_o ( emm_wb_sel ),
.m_wb_we_o ( emm_wb_we ),
.m_wb_dat_i ( emm_wb_rdat ),
.m_wb_dat_o ( emm_wb_wdat ),
.m_wb_cyc_o ( emm_wb_cyc ),
.m_wb_stb_o ( emm_wb_stb ),
.m_wb_ack_i ( emm_wb_ack ),
.m_wb_err_i ( emm_wb_err ),
// MAC to PHY I/F
.mtx_clk_pad_i ( mtx_clk_pad_i ),
.mtxd_pad_o ( mtxd_pad_o ),
.mtxen_pad_o ( mtxen_pad_o ),
.mtxerr_pad_o ( mtxerr_pad_o ),
.mrx_clk_pad_i ( mrx_clk_pad_i ),
.mrxd_pad_i ( mrxd_pad_i ),
.mrxdv_pad_i ( mrxdv_pad_i ),
.mrxerr_pad_i ( mrxerr_pad_i ),
.mcoll_pad_i ( mcoll_pad_i ),
.mcrs_pad_i ( mcrs_pad_i ),
.md_pad_i ( md_pad_i ),
.mdc_pad_o ( mdc_pad_o ),
.md_pad_o ( md_pad_o ),
.md_padoe_o ( md_padoe_o ),
// Interrupt
.int_o ( ethmac_int )
);
// -------------------------------------------------------------
// Instantiate Ethernet Control Interface tri-state buffer
// -------------------------------------------------------------
`ifdef XILINX_FPGA
IOBUF u_iobuf (
`else
generic_iobuf u_iobuf (
`endif
.O ( md_pad_i ),
.IO ( md_pad_io ),
.I ( md_pad_o ),
// T is high for tri-state output
.T ( ~md_padoe_o )
);
// Ethernet MII PHY reset
// Halt core until system is ready
assign system_rdy = phy_init_done && !sys_rst;
// -------------------------------------------------------------
// Instantiate Boot Memory - 8KBytes of Embedded SRAM
// -------------------------------------------------------------
generate
if (WB_DWIDTH == 32) begin : boot_mem32
boot_mem32 u_boot_mem (
.i_wb_clk ( sys_clk ),
.i_wb_adr ( s_wb_adr [1] ),
.i_wb_sel ( s_wb_sel [1] ),
.i_wb_we ( s_wb_we [1] ),
.o_wb_dat ( s_wb_dat_r[1] ),
.i_wb_dat ( s_wb_dat_w[1] ),
.i_wb_cyc ( s_wb_cyc [1] ),
.i_wb_stb ( s_wb_stb [1] ),
.o_wb_ack ( s_wb_ack [1] ),
.o_wb_err ( s_wb_err [1] )
);
end
else begin : boot_mem128
boot_mem128 u_boot_mem (
.i_wb_clk ( sys_clk ),
.i_wb_adr ( s_wb_adr [1] ),
.i_wb_sel ( s_wb_sel [1] ),
.i_wb_we ( s_wb_we [1] ),
.o_wb_dat ( s_wb_dat_r[1] ),
.i_wb_dat ( s_wb_dat_w[1] ),
.i_wb_cyc ( s_wb_cyc [1] ),
.i_wb_stb ( s_wb_stb [1] ),
.o_wb_ack ( s_wb_ack [1] ),
.o_wb_err ( s_wb_err [1] )
);
end
endgenerate
// -------------------------------------------------------------
// Instantiate UART0
// -------------------------------------------------------------
uart #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_uart0 (
.i_clk ( sys_clk ),
.o_uart_int ( uart0_int ),
.i_uart_cts_n ( i_uart0_rts ),
.o_uart_txd ( o_uart0_rx ),
.o_uart_rts_n ( o_uart0_cts ),
.i_uart_rxd ( i_uart0_tx ),
.i_wb_adr ( s_wb_adr [3] ),
.i_wb_sel ( s_wb_sel [3] ),
.i_wb_we ( s_wb_we [3] ),
.o_wb_dat ( s_wb_dat_r[3] ),
.i_wb_dat ( s_wb_dat_w[3] ),
.i_wb_cyc ( s_wb_cyc [3] ),
.i_wb_stb ( s_wb_stb [3] ),
.o_wb_ack ( s_wb_ack [3] ),
.o_wb_err ( s_wb_err [3] )
);
// -------------------------------------------------------------
// Instantiate UART1
// -------------------------------------------------------------
uart #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_uart1 (
.i_clk ( sys_clk ),
.o_uart_int ( uart1_int ),
// These are not connected. ONly pins for 1 UART
// on my development board
.i_uart_cts_n ( 1'd1 ),
.o_uart_txd ( ),
.o_uart_rts_n ( ),
.i_uart_rxd ( 1'd1 ),
.i_wb_adr ( s_wb_adr [4] ),
.i_wb_sel ( s_wb_sel [4] ),
.i_wb_we ( s_wb_we [4] ),
.o_wb_dat ( s_wb_dat_r[4] ),
.i_wb_dat ( s_wb_dat_w[4] ),
.i_wb_cyc ( s_wb_cyc [4] ),
.i_wb_stb ( s_wb_stb [4] ),
.o_wb_ack ( s_wb_ack [4] ),
.o_wb_err ( s_wb_err [4] )
);
// -------------------------------------------------------------
// Instantiate Test Module
// - includes register used to terminate tests
// -------------------------------------------------------------
test_module #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_test_module (
.i_clk ( sys_clk ),
.o_irq ( test_reg_irq ),
.o_firq ( test_reg_firq ),
.o_mem_ctrl ( test_mem_ctrl ),
.i_wb_adr ( s_wb_adr [5] ),
.i_wb_sel ( s_wb_sel [5] ),
.i_wb_we ( s_wb_we [5] ),
.o_wb_dat ( s_wb_dat_r[5] ),
.i_wb_dat ( s_wb_dat_w[5] ),
.i_wb_cyc ( s_wb_cyc [5] ),
.i_wb_stb ( s_wb_stb [5] ),
.o_wb_ack ( s_wb_ack [5] ),
.o_wb_err ( s_wb_err [5] ),
.o_led ( led ),
.o_phy_rst_n ( phy_reset_n )
);
// -------------------------------------------------------------
// Instantiate Timer Module
// -------------------------------------------------------------
timer_module #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_timer_module (
.i_clk ( sys_clk ),
// Interrupt outputs
.o_timer_int ( timer_int ),
// Wishbone interface
.i_wb_adr ( s_wb_adr [6] ),
.i_wb_sel ( s_wb_sel [6] ),
.i_wb_we ( s_wb_we [6] ),
.o_wb_dat ( s_wb_dat_r[6] ),
.i_wb_dat ( s_wb_dat_w[6] ),
.i_wb_cyc ( s_wb_cyc [6] ),
.i_wb_stb ( s_wb_stb [6] ),
.o_wb_ack ( s_wb_ack [6] ),
.o_wb_err ( s_wb_err [6] )
);
// -------------------------------------------------------------
// Instantiate Interrupt Controller Module
// -------------------------------------------------------------
interrupt_controller #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_interrupt_controller (
.i_clk ( sys_clk ),
// Interrupt outputs
.o_irq ( amber_irq ),
.o_firq ( amber_firq ),
// Interrupt inputs
.i_uart0_int ( uart0_int ),
.i_uart1_int ( uart1_int ),
.i_ethmac_int ( ethmac_int ),
.i_test_reg_irq ( test_reg_irq ),
.i_test_reg_firq ( test_reg_firq ),
.i_tm_timer_int ( timer_int ),
// Wishbone interface
.i_wb_adr ( s_wb_adr [7] ),
.i_wb_sel ( s_wb_sel [7] ),
.i_wb_we ( s_wb_we [7] ),
.o_wb_dat ( s_wb_dat_r[7] ),
.i_wb_dat ( s_wb_dat_w[7] ),
.i_wb_cyc ( s_wb_cyc [7] ),
.i_wb_stb ( s_wb_stb [7] ),
.o_wb_ack ( s_wb_ack [7] ),
.o_wb_err ( s_wb_err [7] )
);
`ifndef XILINX_FPGA
// ======================================
// Instantiate non-synthesizable main memory model
// ======================================
assign phy_init_done = 1'd1;
// main_mem #(
// .WB_DWIDTH ( WB_DWIDTH ),
// .WB_SWIDTH ( WB_SWIDTH )
// )
// u_main_mem (
// .i_clk ( sys_clk ),
// .i_mem_ctrl ( test_mem_ctrl ),
// .i_wb_adr ( s_wb_adr [2] ),
// .i_wb_sel ( s_wb_sel [2] ),
// .i_wb_we ( s_wb_we [2] ),
// .o_wb_dat ( s_wb_dat_r[2] ),
// .i_wb_dat ( s_wb_dat_w[2] ),
// .i_wb_cyc ( s_wb_cyc [2] ),
// .i_wb_stb ( s_wb_stb [2] ),
// .o_wb_ack ( s_wb_ack [2] ),
// .o_wb_err ( s_wb_err [2] )
// );
edc_mod edc (
.edc_clk ( sys_clk ),
.edc_mem_ctrl ( test_mem_ctrl ),
.edc_wb_adr ( s_wb_adr [2] ),
.edc_wb_sel ( s_wb_sel [2] ),
.edc_wb_we ( s_wb_we [2] ),
.edc_wb_dat_r ( s_wb_dat_r[2] ),
.edc_wb_dat_w ( s_wb_dat_w[2] ),
.edc_wb_cyc ( s_wb_cyc [2] ),
.edc_wb_stb ( s_wb_stb [2] ),
.edc_wb_ack ( s_wb_ack [2] ),
.edc_wb_err ( s_wb_err [2] )
);
`endif
`ifdef XILINX_SPARTAN6_FPGA
// -------------------------------------------------------------
// Instantiate Wishbone to Xilinx Spartan-6 DDR3 Bridge
// -------------------------------------------------------------
// The clock crossing fifo for spartan-6 is build into the mcb
wb_xs6_ddr3_bridge #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_wb_xs6_ddr3_bridge(
.i_clk ( sys_clk ),
.o_cmd_en ( c3_p0_cmd_en ),
.o_cmd_instr ( c3_p0_cmd_instr ),
.o_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
.i_cmd_full ( c3_p0_cmd_full ),
.i_wr_full ( c3_p0_wr_full ),
.o_wr_en ( c3_p0_wr_en ),
.o_wr_mask ( c3_p0_wr_mask ),
.o_wr_data ( c3_p0_wr_data ),
.i_rd_data ( c3_p0_rd_data ),
.i_rd_empty ( c3_p0_rd_empty ),
.i_mem_ctrl ( test_mem_ctrl ),
.i_wb_adr ( s_wb_adr [2] ),
.i_wb_sel ( s_wb_sel [2] ),
.i_wb_we ( s_wb_we [2] ),
.o_wb_dat ( s_wb_dat_r[2] ),
.i_wb_dat ( s_wb_dat_w[2] ),
.i_wb_cyc ( s_wb_cyc [2] ),
.i_wb_stb ( s_wb_stb [2] ),
.o_wb_ack ( s_wb_ack [2] ),
.o_wb_err ( s_wb_err [2] )
);
// -------------------------------------------------------------
// Instantiate Xilinx Spartan-6 FPGA MCB-DDR3 Controller
// -------------------------------------------------------------
ddr3 u_ddr3 (
// DDR3 signals
.mcb3_dram_dq ( ddr3_dq ),
.mcb3_dram_a ( ddr3_addr ),
.mcb3_dram_ba ( ddr3_ba ),
.mcb3_dram_ras_n ( ddr3_ras_n ),
.mcb3_dram_cas_n ( ddr3_cas_n ),
.mcb3_dram_we_n ( ddr3_we_n ),
.mcb3_dram_odt ( ddr3_odt ),
.mcb3_dram_reset_n ( ddr3_reset_n ),
.mcb3_dram_cke ( ddr3_cke ),
.mcb3_dram_udm ( ddr3_dm[1] ),
.mcb3_dram_dm ( ddr3_dm[0] ),
.mcb3_rzq ( mcb3_rzq ),
.mcb3_dram_udqs ( ddr3_dqs_p[1] ),
.mcb3_dram_dqs ( ddr3_dqs_p[0] ),
.mcb3_dram_udqs_n ( ddr3_dqs_n[1] ),
.mcb3_dram_dqs_n ( ddr3_dqs_n[0] ),
.mcb3_dram_ck ( ddr3_ck_p ),
.mcb3_dram_ck_n ( ddr3_ck_n ),
.c3_sys_clk ( clk_200 ),
.c3_sys_rst_i ( brd_rst ), // active-high
.c3_clk0 ( ),
.c3_rst0 ( ),
.c3_calib_done ( phy_init_done ),
.c3_p0_cmd_clk ( sys_clk ),
.c3_p0_cmd_en ( c3_p0_cmd_en ),
.c3_p0_cmd_instr ( c3_p0_cmd_instr ),
.c3_p0_cmd_bl ( 6'd0 ),
.c3_p0_cmd_byte_addr ( c3_p0_cmd_byte_addr ),
.c3_p0_cmd_empty ( ),
.c3_p0_cmd_full ( c3_p0_cmd_full ),
.c3_p0_wr_clk ( sys_clk ),
.c3_p0_wr_en ( c3_p0_wr_en ),
.c3_p0_wr_mask ( c3_p0_wr_mask ),
.c3_p0_wr_data ( c3_p0_wr_data ),
.c3_p0_wr_full ( c3_p0_wr_full ),
.c3_p0_wr_empty ( ),
.c3_p0_wr_count ( ),
.c3_p0_wr_underrun ( ),
.c3_p0_wr_error ( ),
.c3_p0_rd_clk ( sys_clk ),
.c3_p0_rd_en ( 1'd1 ),
.c3_p0_rd_data ( c3_p0_rd_data ),
.c3_p0_rd_full ( ),
.c3_p0_rd_empty ( c3_p0_rd_empty ),
.c3_p0_rd_count ( ),
.c3_p0_rd_overflow ( ),
.c3_p0_rd_error ( )
);
`endif
// -------------------------------------------------------------
// Instantiate Wishbone Arbiter
// -------------------------------------------------------------
wishbone_arbiter #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_wishbone_arbiter (
.i_wb_clk ( sys_clk ),
// WISHBONE master 0 - Ethmac
.i_m0_wb_adr ( m_wb_adr [0] ),
.i_m0_wb_sel ( m_wb_sel [0] ),
.i_m0_wb_we ( m_wb_we [0] ),
.o_m0_wb_dat ( m_wb_dat_r [0] ),
.i_m0_wb_dat ( m_wb_dat_w [0] ),
.i_m0_wb_cyc ( m_wb_cyc [0] ),
.i_m0_wb_stb ( m_wb_stb [0] ),
.o_m0_wb_ack ( m_wb_ack [0] ),
.o_m0_wb_err ( m_wb_err [0] ),
// WISHBONE master 1 - Amber Processor
.i_m1_wb_adr ( m_wb_adr [1] ),
.i_m1_wb_sel ( m_wb_sel [1] ),
.i_m1_wb_we ( m_wb_we [1] ),
.o_m1_wb_dat ( m_wb_dat_r [1] ),
.i_m1_wb_dat ( m_wb_dat_w [1] ),
.i_m1_wb_cyc ( m_wb_cyc [1] ),
.i_m1_wb_stb ( m_wb_stb [1] ),
.o_m1_wb_ack ( m_wb_ack [1] ),
.o_m1_wb_err ( m_wb_err [1] ),
// WISHBONE slave 0 - Ethmac
.o_s0_wb_adr ( s_wb_adr [0] ),
.o_s0_wb_sel ( s_wb_sel [0] ),
.o_s0_wb_we ( s_wb_we [0] ),
.i_s0_wb_dat ( s_wb_dat_r [0] ),
.o_s0_wb_dat ( s_wb_dat_w [0] ),
.o_s0_wb_cyc ( s_wb_cyc [0] ),
.o_s0_wb_stb ( s_wb_stb [0] ),
.i_s0_wb_ack ( s_wb_ack [0] ),
.i_s0_wb_err ( s_wb_err [0] ),
// WISHBONE slave 1 - Boot Memory
.o_s1_wb_adr ( s_wb_adr [1] ),
.o_s1_wb_sel ( s_wb_sel [1] ),
.o_s1_wb_we ( s_wb_we [1] ),
.i_s1_wb_dat ( s_wb_dat_r [1] ),
.o_s1_wb_dat ( s_wb_dat_w [1] ),
.o_s1_wb_cyc ( s_wb_cyc [1] ),
.o_s1_wb_stb ( s_wb_stb [1] ),
.i_s1_wb_ack ( s_wb_ack [1] ),
.i_s1_wb_err ( s_wb_err [1] ),
// WISHBONE slave 2 - Main Memory
.o_s2_wb_adr ( s_wb_adr [2] ),
.o_s2_wb_sel ( s_wb_sel [2] ),
.o_s2_wb_we ( s_wb_we [2] ),
.i_s2_wb_dat ( s_wb_dat_r [2] ),
.o_s2_wb_dat ( s_wb_dat_w [2] ),
.o_s2_wb_cyc ( s_wb_cyc [2] ),
.o_s2_wb_stb ( s_wb_stb [2] ),
.i_s2_wb_ack ( s_wb_ack [2] ),
.i_s2_wb_err ( s_wb_err [2] ),
// WISHBONE slave 3 - UART 0
.o_s3_wb_adr ( s_wb_adr [3] ),
.o_s3_wb_sel ( s_wb_sel [3] ),
.o_s3_wb_we ( s_wb_we [3] ),
.i_s3_wb_dat ( s_wb_dat_r [3] ),
.o_s3_wb_dat ( s_wb_dat_w [3] ),
.o_s3_wb_cyc ( s_wb_cyc [3] ),
.o_s3_wb_stb ( s_wb_stb [3] ),
.i_s3_wb_ack ( s_wb_ack [3] ),
.i_s3_wb_err ( s_wb_err [3] ),
// WISHBONE slave 4 - UART 1
.o_s4_wb_adr ( s_wb_adr [4] ),
.o_s4_wb_sel ( s_wb_sel [4] ),
.o_s4_wb_we ( s_wb_we [4] ),
.i_s4_wb_dat ( s_wb_dat_r [4] ),
.o_s4_wb_dat ( s_wb_dat_w [4] ),
.o_s4_wb_cyc ( s_wb_cyc [4] ),
.o_s4_wb_stb ( s_wb_stb [4] ),
.i_s4_wb_ack ( s_wb_ack [4] ),
.i_s4_wb_err ( s_wb_err [4] ),
// WISHBONE slave 5 - Test Module
.o_s5_wb_adr ( s_wb_adr [5] ),
.o_s5_wb_sel ( s_wb_sel [5] ),
.o_s5_wb_we ( s_wb_we [5] ),
.i_s5_wb_dat ( s_wb_dat_r [5] ),
.o_s5_wb_dat ( s_wb_dat_w [5] ),
.o_s5_wb_cyc ( s_wb_cyc [5] ),
.o_s5_wb_stb ( s_wb_stb [5] ),
.i_s5_wb_ack ( s_wb_ack [5] ),
.i_s5_wb_err ( s_wb_err [5] ),
// WISHBONE slave 6 - Timer Module
.o_s6_wb_adr ( s_wb_adr [6] ),
.o_s6_wb_sel ( s_wb_sel [6] ),
.o_s6_wb_we ( s_wb_we [6] ),
.i_s6_wb_dat ( s_wb_dat_r [6] ),
.o_s6_wb_dat ( s_wb_dat_w [6] ),
.o_s6_wb_cyc ( s_wb_cyc [6] ),
.o_s6_wb_stb ( s_wb_stb [6] ),
.i_s6_wb_ack ( s_wb_ack [6] ),
.i_s6_wb_err ( s_wb_err [6] ),
// WISHBONE slave 7 - Interrupt Controller
.o_s7_wb_adr ( s_wb_adr [7] ),
.o_s7_wb_sel ( s_wb_sel [7] ),
.o_s7_wb_we ( s_wb_we [7] ),
.i_s7_wb_dat ( s_wb_dat_r [7] ),
.o_s7_wb_dat ( s_wb_dat_w [7] ),
.o_s7_wb_cyc ( s_wb_cyc [7] ),
.o_s7_wb_stb ( s_wb_stb [7] ),
.i_s7_wb_ack ( s_wb_ack [7] ),
.i_s7_wb_err ( s_wb_err [7] )
);
ethmac_wb #(
.WB_DWIDTH ( WB_DWIDTH ),
.WB_SWIDTH ( WB_SWIDTH )
)
u_ethmac_wb (
// Wishbone arbiter side
.o_m_wb_adr ( m_wb_adr [0] ),
.o_m_wb_sel ( m_wb_sel [0] ),
.o_m_wb_we ( m_wb_we [0] ),
.i_m_wb_rdat ( m_wb_dat_r [0] ),
.o_m_wb_wdat ( m_wb_dat_w [0] ),
.o_m_wb_cyc ( m_wb_cyc [0] ),
.o_m_wb_stb ( m_wb_stb [0] ),
.i_m_wb_ack ( m_wb_ack [0] ),
.i_m_wb_err ( m_wb_err [0] ),
// Wishbone arbiter side
.i_s_wb_adr ( s_wb_adr [0] ),
.i_s_wb_sel ( s_wb_sel [0] ),
.i_s_wb_we ( s_wb_we [0] ),
.i_s_wb_cyc ( s_wb_cyc [0] ),
.i_s_wb_stb ( s_wb_stb [0] ),
.o_s_wb_ack ( s_wb_ack [0] ),
.i_s_wb_wdat ( s_wb_dat_w [0] ),
.o_s_wb_rdat ( s_wb_dat_r [0] ),
.o_s_wb_err ( s_wb_err [0] ),
// Ethmac side
.i_m_wb_adr ( emm_wb_adr ),
.i_m_wb_sel ( emm_wb_sel ),
.i_m_wb_we ( emm_wb_we ),
.o_m_wb_rdat ( emm_wb_rdat ),
.i_m_wb_wdat ( emm_wb_wdat ),
.i_m_wb_cyc ( emm_wb_cyc ),
.i_m_wb_stb ( emm_wb_stb ),
.o_m_wb_ack ( emm_wb_ack ),
.o_m_wb_err ( emm_wb_err ),
// Ethmac side
.o_s_wb_adr ( ems_wb_adr ),
.o_s_wb_sel ( ems_wb_sel ),
.o_s_wb_we ( ems_wb_we ),
.i_s_wb_rdat ( ems_wb_rdat ),
.o_s_wb_wdat ( ems_wb_wdat ),
.o_s_wb_cyc ( ems_wb_cyc ),
.o_s_wb_stb ( ems_wb_stb ),
.i_s_wb_ack ( ems_wb_ack ),
.i_s_wb_err ( ems_wb_err )
);
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_decrement (clock, reset, enable, test_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 1;
parameter value = 1;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input [width-1:0] test_expr;
output [`OVL_FIRE_WIDTH-1:0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_DECREMENT";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_VERILOG
`include "./vlog95/assert_decrement_logic.v"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_SVA
`include "./sva05/assert_decrement_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`ifdef OVL_PSL
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`include "./psl05/assert_decrement_psl_logic.v"
`else
`endmodule // ovl_decrement
`endif
|
//-----------------------------------------------------------------------------
// Title : Block-level Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// Project : Virtex-6 Embedded Tri-Mode Ethernet MAC Wrapper
// File : v6_emac_v1_3_block.v
// Version : 1.3
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Description: This is the block-level wrapper for the Virtex-6 Embedded
// Tri-Mode Ethernet MAC. It is intended that this example design
// can be quickly adapted and downloaded onto an FPGA to provide
// a hardware test environment.
//
// The block-level wrapper:
//
// * instantiates appropriate PHY interface modules (GMII, MII,
// RGMII, SGMII or 1000BASE-X) as required per the user
// configuration;
//
// * instantiates some clocking and reset resources to operate
// the EMAC and its example design.
//
// Please refer to the Datasheet, Getting Started Guide, and
// the Virtex-6 Embedded Tri-Mode Ethernet MAC User Gude for
// further information.
//-----------------------------------------------------------------------------
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Module declaration for the block-level wrapper
//-----------------------------------------------------------------------------
module v6_emac_v1_3_block
(
// TX clock output
TX_CLK_OUT,
// TX clock input from BUFG
TX_CLK,
// Client receiver interface
EMACCLIENTRXD,
EMACCLIENTRXDVLD,
EMACCLIENTRXGOODFRAME,
EMACCLIENTRXBADFRAME,
EMACCLIENTRXFRAMEDROP,
EMACCLIENTRXSTATS,
EMACCLIENTRXSTATSVLD,
EMACCLIENTRXSTATSBYTEVLD,
// Client transmitter interface
CLIENTEMACTXD,
CLIENTEMACTXDVLD,
EMACCLIENTTXACK,
CLIENTEMACTXFIRSTBYTE,
CLIENTEMACTXUNDERRUN,
EMACCLIENTTXCOLLISION,
EMACCLIENTTXRETRANSMIT,
CLIENTEMACTXIFGDELAY,
EMACCLIENTTXSTATS,
EMACCLIENTTXSTATSVLD,
EMACCLIENTTXSTATSBYTEVLD,
// MAC control interface
CLIENTEMACPAUSEREQ,
CLIENTEMACPAUSEVAL,
// Receive-side PHY clock on regional buffer, to EMAC
PHY_RX_CLK,
// Clock signal
GTX_CLK,
// GMII interface
GMII_TXD,
GMII_TX_EN,
GMII_TX_ER,
GMII_TX_CLK,
GMII_RXD,
GMII_RX_DV,
GMII_RX_ER,
GMII_RX_CLK,
// MDIO interface
MDC,
MDIO_I,
MDIO_O,
MDIO_T,
// Host interface
HOSTCLK,
HOSTOPCODE,
HOSTREQ,
HOSTMIIMSEL,
HOSTADDR,
HOSTWRDATA,
HOSTMIIMRDY,
HOSTRDDATA,
// Asynchronous reset
RESET
);
//-----------------------------------------------------------------------------
// Port declarations
//-----------------------------------------------------------------------------
// TX clock output
output TX_CLK_OUT;
// TX clock input from BUFG
input TX_CLK;
// Client receiver interface
output [7:0] EMACCLIENTRXD;
output EMACCLIENTRXDVLD;
output EMACCLIENTRXGOODFRAME;
output EMACCLIENTRXBADFRAME;
output EMACCLIENTRXFRAMEDROP;
output [6:0] EMACCLIENTRXSTATS;
output EMACCLIENTRXSTATSVLD;
output EMACCLIENTRXSTATSBYTEVLD;
// Client transmitter interface
input [7:0] CLIENTEMACTXD;
input CLIENTEMACTXDVLD;
output EMACCLIENTTXACK;
input CLIENTEMACTXFIRSTBYTE;
input CLIENTEMACTXUNDERRUN;
output EMACCLIENTTXCOLLISION;
output EMACCLIENTTXRETRANSMIT;
input [7:0] CLIENTEMACTXIFGDELAY;
output EMACCLIENTTXSTATS;
output EMACCLIENTTXSTATSVLD;
output EMACCLIENTTXSTATSBYTEVLD;
// MAC control interface
input CLIENTEMACPAUSEREQ;
input [15:0] CLIENTEMACPAUSEVAL;
// Receive-side PHY clock on regional buffer, to EMAC
input PHY_RX_CLK;
// Clock signal
input GTX_CLK;
// GMII interface
output [7:0] GMII_TXD;
output GMII_TX_EN;
output GMII_TX_ER;
output GMII_TX_CLK;
input [7:0] GMII_RXD;
input GMII_RX_DV;
input GMII_RX_ER;
input GMII_RX_CLK;
// MDIO interface
output MDC;
input MDIO_I;
output MDIO_O;
output MDIO_T;
// Host interface
input HOSTCLK;
input [1:0] HOSTOPCODE;
input HOSTREQ;
input HOSTMIIMSEL;
input [9:0] HOSTADDR;
input [31:0] HOSTWRDATA;
output HOSTMIIMRDY;
output [31:0] HOSTRDDATA;
// Asynchronous reset
input RESET;
//-----------------------------------------------------------------------------
// Wire and register declarations
//-----------------------------------------------------------------------------
// Asynchronous reset signals
wire reset_ibuf_i;
wire reset_i;
// ASYNC_REG attribute added to simulate actual behavior under
// asynchronous operating conditions.
(* ASYNC_REG = "TRUE" *)
reg [3:0] reset_r;
// Client clocking signals
wire rx_client_clk_out_i;
wire rx_client_clk_in_i;
wire tx_client_clk_out_i;
wire tx_client_clk_in_i;
wire tx_gmii_mii_clk_out_i;
wire tx_gmii_mii_clk_in_i;
// Physical interface signals
wire gmii_tx_en_i;
wire gmii_tx_er_i;
wire [7:0] gmii_txd_i;
wire gmii_rx_dv_r;
wire gmii_rx_er_r;
wire [7:0] gmii_rxd_r;
wire gmii_rx_clk_i;
// 125MHz reference clock
wire gtx_clk_ibufg_i;
// MDIO signals
wire mdc_out_i;
wire mdio_in_i;
wire mdio_out_i;
wire mdio_tri_i;
//-----------------------------------------------------------------------------
// Main body of code
//-----------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Main reset circuitry
//-------------------------------------------------------------------------
assign reset_ibuf_i = RESET;
assign reset_i = reset_ibuf_i;
//-------------------------------------------------------------------------
// GMII circuitry for the physical interface
//-------------------------------------------------------------------------
gmii_if gmii (
.RESET (reset_i),
.GMII_TXD (GMII_TXD),
.GMII_TX_EN (GMII_TX_EN),
.GMII_TX_ER (GMII_TX_ER),
.GMII_TX_CLK (GMII_TX_CLK),
.GMII_RXD (GMII_RXD),
.GMII_RX_DV (GMII_RX_DV),
.GMII_RX_ER (GMII_RX_ER),
.TXD_FROM_MAC (gmii_txd_i),
.TX_EN_FROM_MAC (gmii_tx_en_i),
.TX_ER_FROM_MAC (gmii_tx_er_i),
.TX_CLK (tx_gmii_mii_clk_in_i),
.RXD_TO_MAC (gmii_rxd_r),
.RX_DV_TO_MAC (gmii_rx_dv_r),
.RX_ER_TO_MAC (gmii_rx_er_r),
.RX_CLK (GMII_RX_CLK)
);
// GTX reference clock
assign gtx_clk_ibufg_i = GTX_CLK;
// GMII PHY-side transmit clock
assign tx_gmii_mii_clk_in_i = TX_CLK;
// GMII PHY-side receive clock, regionally-buffered
assign gmii_rx_clk_i = PHY_RX_CLK;
// GMII client-side transmit clock
assign tx_client_clk_in_i = TX_CLK;
// GMII client-side receive clock
assign rx_client_clk_in_i = gmii_rx_clk_i;
// TX clock output
assign TX_CLK_OUT = tx_gmii_mii_clk_out_i;
//------------------------------------------------------------------------
// Instantiate the primitive-level EMAC wrapper (v6_emac_v1_3.v)
//------------------------------------------------------------------------
v6_emac_v1_3 v6_emac_v1_3_inst
(
// Client receiver interface
.EMACCLIENTRXCLIENTCLKOUT (rx_client_clk_out_i),
.CLIENTEMACRXCLIENTCLKIN (rx_client_clk_in_i),
.EMACCLIENTRXD (EMACCLIENTRXD),
.EMACCLIENTRXDVLD (EMACCLIENTRXDVLD),
.EMACCLIENTRXDVLDMSW (),
.EMACCLIENTRXGOODFRAME (EMACCLIENTRXGOODFRAME),
.EMACCLIENTRXBADFRAME (EMACCLIENTRXBADFRAME),
.EMACCLIENTRXFRAMEDROP (EMACCLIENTRXFRAMEDROP),
.EMACCLIENTRXSTATS (EMACCLIENTRXSTATS),
.EMACCLIENTRXSTATSVLD (EMACCLIENTRXSTATSVLD),
.EMACCLIENTRXSTATSBYTEVLD (EMACCLIENTRXSTATSBYTEVLD),
// Client transmitter interface
.EMACCLIENTTXCLIENTCLKOUT (tx_client_clk_out_i),
.CLIENTEMACTXCLIENTCLKIN (tx_client_clk_in_i),
.CLIENTEMACTXD (CLIENTEMACTXD),
.CLIENTEMACTXDVLD (CLIENTEMACTXDVLD),
.CLIENTEMACTXDVLDMSW (1'b0),
.EMACCLIENTTXACK (EMACCLIENTTXACK),
.CLIENTEMACTXFIRSTBYTE (CLIENTEMACTXFIRSTBYTE),
.CLIENTEMACTXUNDERRUN (CLIENTEMACTXUNDERRUN),
.EMACCLIENTTXCOLLISION (EMACCLIENTTXCOLLISION),
.EMACCLIENTTXRETRANSMIT (EMACCLIENTTXRETRANSMIT),
.CLIENTEMACTXIFGDELAY (CLIENTEMACTXIFGDELAY),
.EMACCLIENTTXSTATS (EMACCLIENTTXSTATS),
.EMACCLIENTTXSTATSVLD (EMACCLIENTTXSTATSVLD),
.EMACCLIENTTXSTATSBYTEVLD (EMACCLIENTTXSTATSBYTEVLD),
// MAC control interface
.CLIENTEMACPAUSEREQ (CLIENTEMACPAUSEREQ),
.CLIENTEMACPAUSEVAL (CLIENTEMACPAUSEVAL),
// Clock signals
.GTX_CLK (gtx_clk_ibufg_i),
.EMACPHYTXGMIIMIICLKOUT (tx_gmii_mii_clk_out_i),
.PHYEMACTXGMIIMIICLKIN (tx_gmii_mii_clk_in_i),
// GMII interface
.GMII_TXD (gmii_txd_i),
.GMII_TX_EN (gmii_tx_en_i),
.GMII_TX_ER (gmii_tx_er_i),
.GMII_RXD (gmii_rxd_r),
.GMII_RX_DV (gmii_rx_dv_r),
.GMII_RX_ER (gmii_rx_er_r),
.GMII_RX_CLK (gmii_rx_clk_i),
// MDIO interface
.MDC (mdc_out_i),
.MDIO_I (mdio_in_i),
.MDIO_O (mdio_out_i),
.MDIO_T (mdio_tri_i),
// Host interface
.HOSTCLK (HOSTCLK),
.HOSTOPCODE (HOSTOPCODE),
.HOSTREQ (HOSTREQ),
.HOSTMIIMSEL (HOSTMIIMSEL),
.HOSTADDR (HOSTADDR),
.HOSTWRDATA (HOSTWRDATA),
.HOSTMIIMRDY (HOSTMIIMRDY),
.HOSTRDDATA (HOSTRDDATA),
// MMCM lock indicator
.MMCM_LOCKED (1'b1),
// Asynchronous reset
.RESET (reset_i)
);
//--------------------------------------------------------------------
// MDIO interface
//--------------------------------------------------------------------
// This example keeps the mdio_in, mdio_out, mdio_tri signals as
// separate connections: these could be connected to an external
// Tri-state buffer. Alternatively they could be connected to a
// Tri-state buffer in a Xilinx IOB and an appropriate SelectIO
// standard chosen.
assign MDC = mdc_out_i;
assign mdio_in_i = MDIO_I;
assign MDIO_O = mdio_out_i;
assign MDIO_T = mdio_tri_i;
endmodule
|
module arbiter(rst, clk, push, d, full, q, stall, valid, almost_full);
parameter WIDTH = 8;
parameter PORTS = 8;
parameter FIFO_DEPTH = 32;
parameter ALMOST_FULL_THRESHOLD = 1;
parameter PORTS_ADDR_WIDTH = log2(PORTS-1);
parameter FIFO_DEPTH_ADDR_WIDTH = log2(FIFO_DEPTH-1);
input rst;
input clk;
input [0:PORTS-1]push;
input [WIDTH*PORTS-1:0] d;
output [0:PORTS-1]full;
output [WIDTH-1:0] q;
input stall;
output valid;
output [0:PORTS-1] almost_full;
//TODO: std_fifos
wire [0:PORTS-1]almost_empty;
reg [0:PORTS-1]pop;
wire [0:PORTS-1]empty;
wire [FIFO_DEPTH_ADDR_WIDTH:0] count[0:PORTS-1];
wire [WIDTH-1:0] fifo_q[0:PORTS-1];
reg [WIDTH-1:0]fifo_d[0:PORTS-1];
integer i, j;
always @* begin
for(i = 0; i < PORTS; i = i + 1) begin
for(j = 0; j < WIDTH; j = j + 1) begin
fifo_d[i][j] = d[(PORTS - i - 1) * WIDTH + j];
end
end
end
genvar lane;
generate
for(lane = 0; lane < PORTS; lane = lane + 1) begin: fifo_generate
std_fifo #(.DEPTH(FIFO_DEPTH), .WIDTH(WIDTH), .ALMOST_FULL_COUNT(ALMOST_FULL_THRESHOLD)) fifo(rst, clk, push[lane], pop[lane], fifo_d[lane], fifo_q[lane], full[lane], empty[lane], count[lane], almost_empty[lane], almost_full[lane]);
end
endgenerate
reg [PORTS_ADDR_WIDTH-1:0] processing, next_processing, prev_processing;
always @* begin
pop = 0;
next_processing = processing;
if(!empty[processing] && !stall)
pop[processing] = 1;
if(almost_empty[processing])
next_processing = processing + 1;
if(next_processing == PORTS)
next_processing = 0;
if(rst)
next_processing = 0;
end
always @(posedge clk) begin
processing <= next_processing;
prev_processing <= processing;
end
//TODO: stall
reg r_valid, r_valid2;
reg [WIDTH-1:0] r_q;
always @(posedge clk) begin
r_q = fifo_q[prev_processing];
r_valid <= |pop;
r_valid2 <= r_valid;
end
assign q = r_q;
assign valid = r_valid2;
always @(posedge clk) begin
//$display("empty: %H", empty);
end
`include "log2.vh"
endmodule
|
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
//include "registers.v"
module oq_regs_ctrl
#(
parameter SRAM_ADDR_WIDTH = 13,
parameter CTRL_WIDTH = 8,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_OQ_WIDTH = log2(NUM_OUTPUT_QUEUES),
parameter NUM_REGS_USED = 17,
parameter ADDR_WIDTH = log2(NUM_REGS_USED),
parameter MAX_PKT = 2048/CTRL_WIDTH, // allow for 2K bytes
parameter MIN_PKT = 60/CTRL_WIDTH + 1,
parameter PKTS_IN_RAM_WIDTH = log2((2**SRAM_ADDR_WIDTH)/MIN_PKT),
parameter PKT_LEN_WIDTH = 11,
parameter PKT_WORDS_WIDTH = PKT_LEN_WIDTH-log2(CTRL_WIDTH)
)
(
// --- interface to store/remove pkt
output reg [NUM_OUTPUT_QUEUES-1:0] enable,
// --- interface to oq_regs_host_iface
input reg_req,
input reg_rd_wr_L_held,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_held,
input [ADDR_WIDTH-1:0] addr,
input [NUM_OQ_WIDTH-1:0] q_addr,
output reg result_ready,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_result,
// --- Interface to full/empty generation logic
output reg initialize,
output reg [NUM_OQ_WIDTH-1:0] initialize_oq,
// --- Register interfaces
output reg [NUM_OQ_WIDTH-1:0] reg_addr,
output reg num_pkt_bytes_stored_reg_req,
input num_pkt_bytes_stored_reg_ack,
output reg num_pkt_bytes_stored_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_stored_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_stored_reg_rd_data,
output reg num_overhead_bytes_stored_reg_req,
input num_overhead_bytes_stored_reg_ack,
output reg num_overhead_bytes_stored_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_stored_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_stored_reg_rd_data,
output reg num_pkts_stored_reg_req,
input num_pkts_stored_reg_ack,
output reg num_pkts_stored_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_stored_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_stored_reg_rd_data,
output reg num_pkts_dropped_reg_req,
input num_pkts_dropped_reg_ack,
output reg num_pkts_dropped_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_dropped_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_dropped_reg_rd_data,
output reg num_pkt_bytes_removed_reg_req,
input num_pkt_bytes_removed_reg_ack,
output reg num_pkt_bytes_removed_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_removed_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_pkt_bytes_removed_reg_rd_data,
output reg num_overhead_bytes_removed_reg_req,
input num_overhead_bytes_removed_reg_ack,
output reg num_overhead_bytes_removed_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_removed_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_overhead_bytes_removed_reg_rd_data,
output reg num_pkts_removed_reg_req,
input num_pkts_removed_reg_ack,
output reg num_pkts_removed_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_removed_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_removed_reg_rd_data,
output reg oq_addr_hi_reg_req,
input oq_addr_hi_reg_ack,
output reg oq_addr_hi_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_hi_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_hi_reg_rd_data,
output reg oq_addr_lo_reg_req,
input oq_addr_lo_reg_ack,
output reg oq_addr_lo_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_lo_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_lo_reg_rd_data,
output reg oq_wr_addr_reg_req,
input oq_wr_addr_reg_ack,
output reg oq_wr_addr_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] oq_wr_addr_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] oq_wr_addr_reg_rd_data,
output reg oq_rd_addr_reg_req,
input oq_rd_addr_reg_ack,
output reg oq_rd_addr_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] oq_rd_addr_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] oq_rd_addr_reg_rd_data,
output reg max_pkts_in_q_reg_req,
input max_pkts_in_q_reg_ack,
output reg max_pkts_in_q_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] max_pkts_in_q_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] max_pkts_in_q_reg_rd_data,
output reg num_pkts_in_q_reg_req,
input num_pkts_in_q_reg_ack,
output reg num_pkts_in_q_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_in_q_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_pkts_in_q_reg_rd_data,
output reg num_words_left_reg_req,
input num_words_left_reg_ack,
output reg num_words_left_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_words_left_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_words_left_reg_rd_data,
output reg num_words_in_q_reg_req,
input num_words_in_q_reg_ack,
output reg num_words_in_q_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] num_words_in_q_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] num_words_in_q_reg_rd_data,
output reg oq_full_thresh_reg_req,
input oq_full_thresh_reg_ack,
output reg oq_full_thresh_reg_wr,
output reg [`CPCI_NF2_DATA_WIDTH-1:0] oq_full_thresh_reg_wr_data,
input [`CPCI_NF2_DATA_WIDTH-1:0] oq_full_thresh_reg_rd_data,
// --- Misc
input clk,
input reset
);
function integer log2;
input integer number;
begin
log2=0;
while(2**log2<number) begin
log2=log2+1;
end
end
endfunction // log2
// ------------- Internal parameters --------------
localparam ADDR_MAX = `OQ_DEFAULT_ADDR_HIGH(0, NUM_OUTPUT_QUEUES);
localparam ADDR_INC = `OQ_DEFAULT_ADDR_LOW(1, NUM_OUTPUT_QUEUES);
localparam WORDS_IN_Q = `OQ_DEFAULT_ADDR_HIGH(0, NUM_OUTPUT_QUEUES) -
`OQ_DEFAULT_ADDR_LOW(0, NUM_OUTPUT_QUEUES) + 1;
// States
localparam RESET = 0;
localparam NORMAL_OPERATION = 1;
localparam READ_HI_LO_ADDR = 2;
localparam CLEAR_COUNTERS = 3;
localparam INITIALIZE_PAUSE = 4;
// ------------- Wires/reg ------------------
// State variables
reg [2:0] state;
reg enable_held;
// Register initialization signals
reg [NUM_OQ_WIDTH-1:0] reg_cnt;
reg [SRAM_ADDR_WIDTH-1:0] addr_min;
reg [SRAM_ADDR_WIDTH-1:0] addr_max;
// Register request in progress
reg [`CPCI_NF2_DATA_WIDTH-1:0] reg_result_nxt;
reg reg_req_in_progress;
// Held versions of the low and high addresses (used to calculate the
// number of words in a queue)
reg [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_hi_reg_rd_data_held;
reg [`CPCI_NF2_DATA_WIDTH-1:0] oq_addr_lo_reg_rd_data_held;
// Have the various requests been acknowledged during an initialize output
// queue operation?
reg oq_addr_hi_reg_acked;
reg oq_addr_lo_reg_acked;
reg num_pkt_bytes_stored_reg_acked;
reg num_overhead_bytes_stored_reg_acked;
reg num_pkts_stored_reg_acked;
reg num_pkts_dropped_reg_acked;
reg num_pkt_bytes_removed_reg_acked;
reg num_overhead_bytes_removed_reg_acked;
reg num_pkts_removed_reg_acked;
reg num_pkts_in_q_reg_acked;
reg num_words_left_reg_acked;
reg num_words_in_q_reg_acked;
reg oq_wr_addr_reg_acked;
reg oq_rd_addr_reg_acked;
// Misc
wire want_initialize_oq;
wire result_ready_local;
wire req_all;
// -------------- Logic ----------------------
assign result_ready_local = num_pkt_bytes_stored_reg_ack ||
num_overhead_bytes_stored_reg_ack ||
num_pkts_stored_reg_ack ||
num_pkts_dropped_reg_ack ||
num_pkt_bytes_removed_reg_ack ||
num_overhead_bytes_removed_reg_ack ||
num_pkts_removed_reg_ack ||
oq_addr_hi_reg_ack ||
oq_addr_lo_reg_ack ||
oq_wr_addr_reg_ack ||
oq_rd_addr_reg_ack ||
max_pkts_in_q_reg_ack ||
num_pkts_in_q_reg_ack ||
num_words_left_reg_ack ||
num_words_in_q_reg_ack ||
oq_full_thresh_reg_ack;
assign want_initialize_oq = reg_data_held[`OQ_INITIALIZE_OQ_BIT_NUM];
// Main state machine
//
// Note: The logic to control the value sent to the registers (ie.
// _reg_req, _reg_wr and _wr_data) are in a separate always block.
always @(posedge clk)
begin
if (reset) begin
state <= RESET;
reg_cnt <= 'h0;
addr_min <= 0;
addr_max <= ADDR_MAX;
reg_req_in_progress <= 1'b0;
enable <= {NUM_OUTPUT_QUEUES{1'b0}};
enable_held <= 1'b0;
initialize <= 1'b0;
initialize_oq <= 'h0;
end
else begin
case (state)
RESET : begin
// Walk through the register one by one resetting the values
if (reg_cnt == NUM_OUTPUT_QUEUES - 1) begin
state <= NORMAL_OPERATION;
enable <= {NUM_OUTPUT_QUEUES{1'b1}};
end
else
reg_cnt <= reg_cnt + 'h1;
addr_min <= addr_min + ADDR_INC;
addr_max <= addr_max + ADDR_INC;
end // RESET
NORMAL_OPERATION : begin
if (reg_req && !reg_req_in_progress) begin
result_ready <= 1'b0;
// Handle access to the control register separately
if (addr == `OQ_QUEUE_CTRL) begin
// If this request is a write to the initialize bit then
// we need to go through the process of clearing the
// appropriate queue
reg_req_in_progress <= !reg_rd_wr_L_held && want_initialize_oq;
// Handle writes
if (!reg_rd_wr_L_held) begin
enable[q_addr] <= reg_data_held[`OQ_ENABLE_SEND_BIT_NUM] &&
!want_initialize_oq;
if (want_initialize_oq) begin
// Go into the initalization state
state <= READ_HI_LO_ADDR;
initialize <= 1'b1;
initialize_oq <= q_addr;
enable_held <= reg_data_held[`OQ_ENABLE_SEND_BIT_NUM];
oq_addr_hi_reg_acked <= 1'b0;
oq_addr_lo_reg_acked <= 1'b0;
end
end
// Set the result state appropriately
result_ready <= reg_rd_wr_L_held || !want_initialize_oq;
reg_result <= reg_result_nxt;
end
else begin
// Processing a normal register request.
// Record that a register request is in progress
reg_req_in_progress <= 1'b1;
end
end // if (reg_req && !reg_req_in_progress)
else if (reg_req_in_progress) begin
// Wait for a response to be ready
if (result_ready_local) begin
reg_req_in_progress <= 1'b0;
result_ready <= 1'b1;
reg_result <= reg_result_nxt;
end
else if (!reg_req) begin
// The host interface has obviously given up (oops)
reg_req_in_progress <= 1'b0;
end
end
else begin
result_ready <= 1'b0;
end
end
READ_HI_LO_ADDR : begin
// If both requests have been acked then go ahead and clear the
// various counters
if ((oq_addr_hi_reg_ack && oq_addr_lo_reg_ack) ||
(oq_addr_hi_reg_ack && !oq_addr_lo_reg_req) ||
(!oq_addr_hi_reg_req && oq_addr_lo_reg_ack)) begin
// Clear the request flags
state <= CLEAR_COUNTERS;
end
// Latch the hi and lo addresses when the come back so that we
// can calculate the number of words
if (oq_addr_hi_reg_ack) begin
oq_addr_hi_reg_rd_data_held <= oq_addr_hi_reg_rd_data;
end
if (oq_addr_lo_reg_ack) begin
oq_addr_lo_reg_rd_data_held <= oq_addr_lo_reg_rd_data;
end
initialize <= 1'b0;
num_pkt_bytes_stored_reg_acked <= 1'b0;
num_overhead_bytes_stored_reg_acked <= 1'b0;
num_pkts_stored_reg_acked <= 1'b0;
num_pkts_dropped_reg_acked <= 1'b0;
num_pkt_bytes_removed_reg_acked <= 1'b0;
num_overhead_bytes_removed_reg_acked <= 1'b0;
num_pkts_removed_reg_acked <= 1'b0;
num_pkts_in_q_reg_acked <= 1'b0;
num_words_left_reg_acked <= 1'b0;
num_words_in_q_reg_acked <= 1'b0;
oq_wr_addr_reg_acked <= 1'b0;
oq_rd_addr_reg_acked <= 1'b0;
oq_addr_hi_reg_acked <= oq_addr_hi_reg_ack || oq_addr_hi_reg_acked;
oq_addr_lo_reg_acked <= oq_addr_lo_reg_ack || oq_addr_lo_reg_acked;
end
CLEAR_COUNTERS : begin
// Wait for all the request signals to be cleared
if (!num_pkts_in_q_reg_req &&
!num_words_left_reg_req &&
!num_words_in_q_reg_req &&
!oq_wr_addr_reg_req &&
!oq_rd_addr_reg_req) begin
state <= INITIALIZE_PAUSE;
// Set the enable state to the value desired by the user
enable[initialize_oq] <= enable_held;
// Notify the register block that we're done
reg_req_in_progress <= 1'b0;
result_ready <= 1'b1;
reg_result <= reg_result_nxt;
end
num_pkt_bytes_stored_reg_acked <= num_pkt_bytes_stored_reg_ack ||
num_pkt_bytes_stored_reg_acked;
num_overhead_bytes_stored_reg_acked <= num_overhead_bytes_stored_reg_ack ||
num_overhead_bytes_stored_reg_acked;
num_pkts_stored_reg_acked <= num_pkts_stored_reg_ack ||
num_pkts_stored_reg_acked;
num_pkts_dropped_reg_acked <= num_pkts_dropped_reg_ack ||
num_pkts_dropped_reg_acked;
num_pkt_bytes_removed_reg_acked <= num_pkt_bytes_removed_reg_ack ||
num_pkt_bytes_removed_reg_acked;
num_overhead_bytes_removed_reg_acked <= num_overhead_bytes_removed_reg_ack ||
num_overhead_bytes_removed_reg_acked;
num_pkts_removed_reg_acked <= num_pkts_removed_reg_ack ||
num_pkts_removed_reg_acked;
num_pkts_in_q_reg_acked <= num_pkts_in_q_reg_ack ||
num_pkts_in_q_reg_acked;
num_words_left_reg_acked <= num_words_left_reg_ack ||
num_words_left_reg_acked;
num_words_in_q_reg_acked <= num_words_in_q_reg_ack ||
num_words_in_q_reg_acked;
oq_wr_addr_reg_acked <= oq_wr_addr_reg_ack ||
oq_wr_addr_reg_acked;
oq_rd_addr_reg_acked <= oq_rd_addr_reg_ack ||
oq_rd_addr_reg_acked;
end
INITIALIZE_PAUSE : begin
state <= NORMAL_OPERATION;
end
endcase
end
end
// Generate the register access signals
//
// Note: Main state machine is above
always @*
begin
// Set defaults
reg_addr = q_addr;
// By default we shouldn't be issuing requests
num_pkt_bytes_stored_reg_req = 1'b0;
num_overhead_bytes_stored_reg_req = 1'b0;
num_pkts_stored_reg_req = 1'b0;
num_pkts_dropped_reg_req = 1'b0;
num_pkt_bytes_removed_reg_req = 1'b0;
num_overhead_bytes_removed_reg_req = 1'b0;
num_pkts_removed_reg_req = 1'b0;
max_pkts_in_q_reg_req = 1'b0;
num_pkts_in_q_reg_req = 1'b0;
num_words_left_reg_req = 1'b0;
num_words_in_q_reg_req = 1'b0;
oq_addr_hi_reg_req = 1'b0;
oq_addr_lo_reg_req = 1'b0;
oq_wr_addr_reg_req = 1'b0;
oq_rd_addr_reg_req = 1'b0;
oq_full_thresh_reg_req = 1'b0;
// Write enable -- default is the write value from the host interface
// (except for read-only registers)
num_pkt_bytes_stored_reg_wr = !reg_rd_wr_L_held;
num_overhead_bytes_stored_reg_wr = !reg_rd_wr_L_held;
num_pkts_stored_reg_wr = !reg_rd_wr_L_held;
num_pkts_dropped_reg_wr = !reg_rd_wr_L_held;
num_pkt_bytes_removed_reg_wr = !reg_rd_wr_L_held;
num_overhead_bytes_removed_reg_wr = !reg_rd_wr_L_held;
num_pkts_removed_reg_wr = !reg_rd_wr_L_held;
oq_addr_hi_reg_wr = !reg_rd_wr_L_held;
oq_addr_lo_reg_wr = !reg_rd_wr_L_held;
oq_wr_addr_reg_wr = 1'b0;
oq_rd_addr_reg_wr = 1'b0;
max_pkts_in_q_reg_wr = !reg_rd_wr_L_held;
num_pkts_in_q_reg_wr = 1'b0;
num_words_left_reg_wr = 1'b0;
num_words_in_q_reg_wr = 1'b0;
oq_full_thresh_reg_wr = !reg_rd_wr_L_held;
// Write data
// Default to the data from the host_iface modules
num_pkt_bytes_stored_reg_wr_data = reg_data_held;
num_overhead_bytes_stored_reg_wr_data = reg_data_held;
num_pkts_stored_reg_wr_data = reg_data_held;
num_pkts_dropped_reg_wr_data = reg_data_held;
num_pkt_bytes_removed_reg_wr_data = reg_data_held;
num_overhead_bytes_removed_reg_wr_data = reg_data_held;
num_pkts_removed_reg_wr_data = reg_data_held;
oq_addr_hi_reg_wr_data = reg_data_held;
oq_addr_lo_reg_wr_data = reg_data_held;
oq_wr_addr_reg_wr_data = reg_data_held;
oq_rd_addr_reg_wr_data = reg_data_held;
max_pkts_in_q_reg_wr_data = reg_data_held;
num_pkts_in_q_reg_wr_data = reg_data_held;
num_words_left_reg_wr_data = reg_data_held;
num_words_in_q_reg_wr_data = reg_data_held;
oq_full_thresh_reg_wr_data = reg_data_held;
case (state)
RESET : begin
reg_addr = reg_cnt;
num_pkt_bytes_stored_reg_wr_data = 'h0;
num_overhead_bytes_stored_reg_wr_data = 'h0;
num_pkts_stored_reg_wr_data = 'h0;
num_pkts_dropped_reg_wr_data = 'h0;
num_pkt_bytes_removed_reg_wr_data = 'h0;
num_overhead_bytes_removed_reg_wr_data = 'h0;
num_pkts_removed_reg_wr_data = 'h0;
max_pkts_in_q_reg_wr_data = `OQ_DEFAULT_MAX_PKTS;
num_pkts_in_q_reg_wr_data = 1'b0;
num_words_left_reg_wr_data = WORDS_IN_Q;
num_words_in_q_reg_wr_data = 'h0;
oq_addr_hi_reg_wr_data = addr_max;
oq_addr_lo_reg_wr_data = addr_min;
oq_wr_addr_reg_wr_data = addr_min;
oq_rd_addr_reg_wr_data = addr_min;
oq_full_thresh_reg_wr_data = 'h0;
num_pkt_bytes_stored_reg_wr = 1'b1;
num_overhead_bytes_stored_reg_wr = 1'b1;
num_pkts_stored_reg_wr = 1'b1;
num_pkts_dropped_reg_wr = 1'b1;
num_pkt_bytes_removed_reg_wr = 1'b1;
num_overhead_bytes_removed_reg_wr = 1'b1;
num_pkts_removed_reg_wr = 1'b1;
max_pkts_in_q_reg_wr = 1'b1;
num_pkts_in_q_reg_wr = 1'b1;
num_words_left_reg_wr = 1'b1;
num_words_in_q_reg_wr = 1'b1;
oq_addr_hi_reg_wr = 1'b1;
oq_addr_lo_reg_wr = 1'b1;
oq_wr_addr_reg_wr = 1'b1;
oq_rd_addr_reg_wr = 1'b1;
oq_full_thresh_reg_wr = 1'b1;
num_pkt_bytes_stored_reg_req = 1'b1;
num_overhead_bytes_stored_reg_req = 1'b1;
num_pkts_stored_reg_req = 1'b1;
num_pkts_dropped_reg_req = 1'b1;
num_pkt_bytes_removed_reg_req = 1'b1;
num_overhead_bytes_removed_reg_req = 1'b1;
num_pkts_removed_reg_req = 1'b1;
max_pkts_in_q_reg_req = 1'b1;
num_pkts_in_q_reg_req = 1'b1;
num_words_left_reg_req = 1'b1;
num_words_in_q_reg_req = 1'b1;
oq_addr_hi_reg_req = 1'b1;
oq_addr_lo_reg_req = 1'b1;
oq_wr_addr_reg_req = 1'b1;
oq_rd_addr_reg_req = 1'b1;
oq_full_thresh_reg_req = 1'b1;
end // RESET
NORMAL_OPERATION : begin
// Wait for a response to be ready
if (!reg_req_in_progress || result_ready_local || !reg_req) begin
// Write enable
num_pkt_bytes_stored_reg_req = 1'b0;
num_overhead_bytes_stored_reg_req = 1'b0;
num_pkts_stored_reg_req = 1'b0;
num_pkts_dropped_reg_req = 1'b0;
num_pkt_bytes_removed_reg_req = 1'b0;
num_overhead_bytes_removed_reg_req = 1'b0;
num_pkts_removed_reg_req = 1'b0;
oq_addr_hi_reg_req = 1'b0;
oq_addr_lo_reg_req = 1'b0;
oq_wr_addr_reg_req = 1'b0;
oq_rd_addr_reg_req = 1'b0;
max_pkts_in_q_reg_req = 1'b0;
num_pkts_in_q_reg_req = 1'b0;
num_words_left_reg_req = 1'b0;
num_words_in_q_reg_req = 1'b0;
oq_full_thresh_reg_req = 1'b0;
end
else begin
// Default to the "default" values calculated assuming that we are
// writing based upon the address register
//
// Write enable
num_pkt_bytes_stored_reg_req = addr == `OQ_QUEUE_NUM_PKT_BYTES_STORED;
num_overhead_bytes_stored_reg_req = addr == `OQ_QUEUE_NUM_OVERHEAD_BYTES_STORED;
num_pkts_stored_reg_req = addr == `OQ_QUEUE_NUM_PKTS_STORED;
num_pkts_dropped_reg_req = addr == `OQ_QUEUE_NUM_PKTS_DROPPED;
num_pkt_bytes_removed_reg_req = addr == `OQ_QUEUE_NUM_PKT_BYTES_REMOVED;
num_overhead_bytes_removed_reg_req = addr == `OQ_QUEUE_NUM_OVERHEAD_BYTES_REMOVED;
num_pkts_removed_reg_req = addr == `OQ_QUEUE_NUM_PKTS_REMOVED;
oq_addr_hi_reg_req = addr == `OQ_QUEUE_ADDR_HI;
oq_addr_lo_reg_req = addr == `OQ_QUEUE_ADDR_LO;
oq_wr_addr_reg_req = addr == `OQ_QUEUE_WR_ADDR;
oq_rd_addr_reg_req = addr == `OQ_QUEUE_RD_ADDR;
max_pkts_in_q_reg_req = addr == `OQ_QUEUE_MAX_PKTS_IN_Q;
num_pkts_in_q_reg_req = addr == `OQ_QUEUE_NUM_PKTS_IN_Q;
num_words_left_reg_req = addr == `OQ_QUEUE_NUM_WORDS_LEFT;
num_words_in_q_reg_req = addr == `OQ_QUEUE_NUM_WORDS_IN_Q;
oq_full_thresh_reg_req = addr == `OQ_QUEUE_FULL_THRESH;
end
end
READ_HI_LO_ADDR : begin
// Read the lo/hi addresses to enable us to calculate the
// maximum queue occupancy
oq_addr_hi_reg_req = !oq_addr_hi_reg_acked && !oq_addr_hi_reg_ack;
oq_addr_lo_reg_req = !oq_addr_lo_reg_acked && !oq_addr_lo_reg_ack;
oq_addr_hi_reg_wr = 1'b0;
oq_addr_lo_reg_wr = 1'b0;
end
CLEAR_COUNTERS : begin
// Set the values to write
num_pkts_in_q_reg_wr_data = 1'b0;
num_words_left_reg_wr_data = oq_addr_hi_reg_rd_data_held - oq_addr_lo_reg_rd_data_held ;
num_words_in_q_reg_wr_data = 'h0;
oq_wr_addr_reg_wr_data = oq_addr_lo_reg_rd_data_held;
oq_rd_addr_reg_wr_data = oq_addr_lo_reg_rd_data_held;
num_pkt_bytes_stored_reg_wr_data = 'h0;
num_overhead_bytes_stored_reg_wr_data = 'h0;
num_pkts_stored_reg_wr_data = 'h0;
num_pkts_dropped_reg_wr_data = 'h0;
num_pkt_bytes_removed_reg_wr_data = 'h0;
num_overhead_bytes_removed_reg_wr_data = 'h0;
num_pkts_removed_reg_wr_data = 'h0;
// Set the write enable flags
num_pkts_in_q_reg_wr = 1'b1;
num_words_left_reg_wr = 1'b1;
num_words_in_q_reg_wr = 1'b1;
oq_wr_addr_reg_wr = 1'b1;
oq_rd_addr_reg_wr = 1'b1;
num_pkt_bytes_stored_reg_wr = 1'b1;
num_overhead_bytes_stored_reg_wr = 1'b1;
num_pkts_stored_reg_wr = 1'b1;
num_pkts_dropped_reg_wr = 1'b1;
num_pkt_bytes_removed_reg_wr = 1'b1;
num_overhead_bytes_removed_reg_wr= 1'b1;
num_pkts_removed_reg_wr = 1'b1;
num_pkts_in_q_reg_req = !num_pkts_in_q_reg_acked && !num_pkts_in_q_reg_ack;
num_words_left_reg_req = !num_words_left_reg_acked && !num_words_left_reg_ack;
num_words_in_q_reg_req = !num_words_in_q_reg_acked && !num_words_in_q_reg_ack;
oq_wr_addr_reg_req = !oq_wr_addr_reg_acked && !oq_wr_addr_reg_ack;
oq_rd_addr_reg_req = !oq_rd_addr_reg_acked && !oq_rd_addr_reg_ack;
num_pkt_bytes_stored_reg_req = !num_pkt_bytes_stored_reg_acked &&
!num_pkt_bytes_stored_reg_ack;
num_overhead_bytes_stored_reg_req = !num_overhead_bytes_stored_reg_acked &&
!num_overhead_bytes_stored_reg_ack;
num_pkts_stored_reg_req = !num_pkts_stored_reg_acked &&
!num_pkts_stored_reg_ack;
num_pkts_dropped_reg_req = !num_pkts_dropped_reg_acked &&
!num_pkts_dropped_reg_ack;
num_pkt_bytes_removed_reg_req = !num_pkt_bytes_removed_reg_acked &&
!num_pkt_bytes_removed_reg_ack;
num_overhead_bytes_removed_reg_req = !num_overhead_bytes_removed_reg_acked &&
!num_overhead_bytes_removed_reg_ack;
num_pkts_removed_reg_req = !num_pkts_removed_reg_acked &&
!num_pkts_removed_reg_ack;
end
endcase
end
// Generate the result of the request
always @*
begin
case (addr)
`OQ_QUEUE_CTRL : reg_result_nxt = enable[q_addr];
`OQ_QUEUE_NUM_PKT_BYTES_STORED : reg_result_nxt = num_pkt_bytes_stored_reg_rd_data;
`OQ_QUEUE_NUM_OVERHEAD_BYTES_STORED : reg_result_nxt = num_overhead_bytes_stored_reg_rd_data;
`OQ_QUEUE_NUM_PKTS_STORED : reg_result_nxt = num_pkts_stored_reg_rd_data;
`OQ_QUEUE_NUM_PKTS_DROPPED : reg_result_nxt = num_pkts_dropped_reg_rd_data;
`OQ_QUEUE_NUM_PKT_BYTES_REMOVED : reg_result_nxt = num_pkt_bytes_removed_reg_rd_data;
`OQ_QUEUE_NUM_OVERHEAD_BYTES_REMOVED : reg_result_nxt = num_overhead_bytes_removed_reg_rd_data;
`OQ_QUEUE_NUM_PKTS_REMOVED : reg_result_nxt = num_pkts_removed_reg_rd_data;
`OQ_QUEUE_ADDR_HI : reg_result_nxt = oq_addr_hi_reg_rd_data;
`OQ_QUEUE_ADDR_LO : reg_result_nxt = oq_addr_lo_reg_rd_data;
`OQ_QUEUE_WR_ADDR : reg_result_nxt = oq_wr_addr_reg_rd_data;
`OQ_QUEUE_RD_ADDR : reg_result_nxt = oq_rd_addr_reg_rd_data;
`OQ_QUEUE_MAX_PKTS_IN_Q : reg_result_nxt = max_pkts_in_q_reg_rd_data;
`OQ_QUEUE_NUM_PKTS_IN_Q : reg_result_nxt = num_pkts_in_q_reg_rd_data;
`OQ_QUEUE_NUM_WORDS_LEFT : reg_result_nxt = num_words_left_reg_rd_data;
`OQ_QUEUE_NUM_WORDS_IN_Q : reg_result_nxt = num_words_in_q_reg_rd_data;
`OQ_QUEUE_FULL_THRESH : reg_result_nxt = oq_full_thresh_reg_rd_data;
default : reg_result_nxt = 32'h dead_beef;
endcase
end
endmodule // oq_regs_ctrl
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pipe_drp.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_pipe_drp.v
// Description : PIPE DRP Module for 7 Series Transceiver
// Version : 20.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE DRP Module ---------------------------------------------------
module pcie3_7x_0_pipe_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 5'd21 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_GTXRESET,
input [ 1:0] DRP_RATE,
input DRP_X16X20_MODE,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 6:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg mode = 1'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 6:0] fsm = 7'd1;
//---------- DRP Address -------------------------------
// DRP access for *RXCDR_EIDLE includes
// - [11] RXCDR_HOLD_DURING_EIDLE
// - [12] RXCDR_FR_RESET_ON_EIDLE
// - [13] RXCDR_PH_RESET_ON_EIDLE
//------------------------------------------------------
localparam ADDR_PCS_RSVD_ATTR = 9'h06F;
localparam ADDR_TXOUT_DIV = 9'h088;
localparam ADDR_RXOUT_DIV = 9'h088;
localparam ADDR_TX_DATA_WIDTH = 9'h06B;
localparam ADDR_TX_INT_DATAWIDTH = 9'h06B;
localparam ADDR_RX_DATA_WIDTH = 9'h011;
localparam ADDR_RX_INT_DATAWIDTH = 9'h011;
localparam ADDR_TXBUF_EN = 9'h01C;
localparam ADDR_RXBUF_EN = 9'h09D;
localparam ADDR_TX_XCLK_SEL = 9'h059;
localparam ADDR_RX_XCLK_SEL = 9'h059;
localparam ADDR_CLK_CORRECT_USE = 9'h044;
localparam ADDR_TX_DRIVE_MODE = 9'h019;
localparam ADDR_RXCDR_EIDLE = 9'h0A7;
localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E;
localparam ADDR_PMA_RSV_A = 9'h099;
localparam ADDR_PMA_RSV_B = 9'h09A;
localparam ADDR_RXCDR_CFG_A = 9'h0A8;
localparam ADDR_RXCDR_CFG_B = 9'h0A9;
localparam ADDR_RXCDR_CFG_C = 9'h0AA;
localparam ADDR_RXCDR_CFG_D = 9'h0AB;
localparam ADDR_RXCDR_CFG_E = 9'h0AC;
localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only
//---------- DRP Mask ----------------------------------
localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1]
localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4]
localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4]
localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11]
localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only
localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1]
localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7]
localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0]
localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0]
localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ]
localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
//---------- DRP Data for PCIe Gen1 and Gen2 -----------
localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2
localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2
localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width
localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width
localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer
localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC
localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction
localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode
localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle
localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle
localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480
localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001
localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020
localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF
localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003
localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208
localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000
localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE
localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000
//---------- DRP Data for PCIe Gen3 --------------------
localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width
localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width
localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width
localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width
localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer
localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer
localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR
localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR
localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction
localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode
localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle
localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle
localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080
localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E
localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080
localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010
localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF
localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B
localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
//localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
//localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
//localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848
//localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000
//localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
//localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
//localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010
//localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
//localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//----------
localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848
localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000
localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010
localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----
localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_txout_div;
wire [15:0] data_rxout_div;
wire [15:0] data_tx_data_width;
wire [15:0] data_tx_int_datawidth;
wire [15:0] data_rx_data_width;
wire [15:0] data_rx_int_datawidth;
wire [15:0] data_txbuf_en;
wire [15:0] data_rxbuf_en;
wire [15:0] data_tx_xclk_sel;
wire [15:0] data_rx_xclk_sel;
wire [15:0] data_clk_correction_use;
wire [15:0] data_tx_drive_mode;
wire [15:0] data_rxcdr_eidle;
wire [15:0] data_rx_dfe_lpm_eidle;
wire [15:0] data_pma_rsv_a;
wire [15:0] data_pma_rsv_b;
wire [15:0] data_rxcdr_cfg_a;
wire [15:0] data_rxcdr_cfg_b;
wire [15:0] data_rxcdr_cfg_c;
wire [15:0] data_rxcdr_cfg_d;
wire [15:0] data_rxcdr_cfg_e;
wire [15:0] data_rxcdr_cfg_f;
wire [15:0] data_pcs_rsvd_attr_a;
wire [15:0] data_pcs_rsvd_attr_m_tx;
wire [15:0] data_pcs_rsvd_attr_m_rx;
wire [15:0] data_pcs_rsvd_attr_m;
wire [15:0] data_x16x20_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 7'b0000001;
localparam FSM_LOAD = 7'b0000010;
localparam FSM_READ = 7'b0000100;
localparam FSM_RRDY = 7'b0001000;
localparam FSM_WRITE = 7'b0010000;
localparam FSM_WRDY = 7'b0100000;
localparam FSM_DONE = 7'b1000000;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= 1'd0;
rate_reg1 <= 2'd0;
x16x20_mode_reg1 <= 1'd0;
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= 1'd0;
rate_reg2 <= 2'd0;
x16x20_mode_reg2 <= 1'd0;
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= DRP_GTXRESET;
rate_reg1 <= DRP_RATE;
x16x20_mode_reg1 <= DRP_X16X20_MODE;
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= gtxreset_reg1;
rate_reg2 <= rate_reg1;
x16x20_mode_reg2 <= x16x20_mode_reg1;
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV;
assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV;
assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH;
assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH;
assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN;
assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN;
assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL;
assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL;
assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE;
assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE;
assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE;
assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A;
assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
5'd0:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR :
x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) :
x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) :
((do_reg2 & MASK_TXOUT_DIV) | data_txout_div);
end
//--------------------------------------------------
5'd1:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) :
((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div);
end
//--------------------------------------------------
5'd2 :
begin
addr_reg <= ADDR_TX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
end
//--------------------------------------------------
5'd3 :
begin
addr_reg <= ADDR_TX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
end
//--------------------------------------------------
5'd4 :
begin
addr_reg <= ADDR_RX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
end
//--------------------------------------------------
5'd5 :
begin
addr_reg <= ADDR_RX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
end
//--------------------------------------------------
5'd6 :
begin
addr_reg <= ADDR_TXBUF_EN;
di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
end
//--------------------------------------------------
5'd7 :
begin
addr_reg <= ADDR_RXBUF_EN;
di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
end
//--------------------------------------------------
5'd8 :
begin
addr_reg <= ADDR_TX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
end
//--------------------------------------------------
5'd9 :
begin
addr_reg <= ADDR_RX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
end
//--------------------------------------------------
5'd10 :
begin
addr_reg <= ADDR_CLK_CORRECT_USE;
di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
end
//--------------------------------------------------
5'd11 :
begin
addr_reg <= ADDR_TX_DRIVE_MODE;
di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
end
//--------------------------------------------------
5'd12 :
begin
addr_reg <= ADDR_RXCDR_EIDLE;
di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
end
//--------------------------------------------------
5'd13 :
begin
addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
end
//--------------------------------------------------
5'd14 :
begin
addr_reg <= ADDR_PMA_RSV_A;
di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
end
//--------------------------------------------------
5'd15 :
begin
addr_reg <= ADDR_PMA_RSV_B;
di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
end
//--------------------------------------------------
5'd16 :
begin
addr_reg <= ADDR_RXCDR_CFG_A;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
end
//--------------------------------------------------
5'd17 :
begin
addr_reg <= ADDR_RXCDR_CFG_B;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
end
//--------------------------------------------------
5'd18 :
begin
addr_reg <= ADDR_RXCDR_CFG_C;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
end
//--------------------------------------------------
5'd19 :
begin
addr_reg <= ADDR_RXCDR_CFG_D;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
end
//--------------------------------------------------
5'd20 :
begin
addr_reg <= ADDR_RXCDR_CFG_E;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
end
//--------------------------------------------------
5'd21 :
begin
addr_reg <= ADDR_RXCDR_CFG_F;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
//---------- GTXRESET --------------------------
else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd1;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRTP_2_V
`define SKY130_FD_SC_HS__SDFRTP_2_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_2 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE ,
VPWR ,
VGND
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__sdfrtp_2 (
RESET_B,
CLK ,
D ,
Q ,
SCD ,
SCE
);
input RESET_B;
input CLK ;
input D ;
output Q ;
input SCD ;
input SCE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__sdfrtp base (
.RESET_B(RESET_B),
.CLK(CLK),
.D(D),
.Q(Q),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRBN_PP_BLACKBOX_V
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Physics Institute, University of Bonn
* ------------------------------------------------------------
*/
`include "utils/fifo_32_to_8.v"
`include "utils/generic_fifo.v"
`include "utils/rgmii_io.v"
`include "utils/rbcp_to_bus.v"
`include "utils/bus_to_ip.v"
`include "gpio/gpio_core.v"
`include "gpio/gpio.v"
module bdaq53_eth_throughput_test(
input wire RESET_N,
input wire clkin,
output wire [3:0] rgmii_txd,
output wire rgmii_tx_ctl,
output wire rgmii_txc,
input wire [3:0] rgmii_rxd,
input wire rgmii_rx_ctl,
input wire rgmii_rxc,
output wire mdio_phy_mdc,
inout wire mdio_phy_mdio,
output wire phy_rst_n,
output wire [7:0] LED
);
wire RST;
wire BUS_CLK_PLL, CLK125PLLTX, CLK125PLLTX90;
wire PLL_FEEDBACK, LOCKED;
PLLE2_BASE #(
.BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW
.CLKFBOUT_MULT(10), // Multiply value for all CLKOUT, (2-64)
.CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000).
.CLKIN1_PERIOD(10.000), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
.CLKOUT0_DIVIDE(7), // Divide amount for CLKOUT0 (1-128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT0_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT1_DIVIDE(4), // Divide amount for CLKOUT0 (1-128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT1_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT2_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT2_PHASE(0.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT3_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT3_PHASE(90.0), // Phase offset for CLKOUT0 (-360.000-360.000).
.CLKOUT4_DIVIDE(8), // Divide amount for CLKOUT0 (1-128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.001-0.999).
.CLKOUT4_PHASE(-5.625), // Phase offset for CLKOUT0 (-360.000-360.000).
//-65 -> 0?; - 45 -> 39; -25 -> 100; -5 -> 0;
.DIVCLK_DIVIDE(1), // Master division value, (1-56)
.REF_JITTER1(0.0), // Reference input jitter in UI, (0.000-0.999).
.STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE")
)
PLLE2_BASE_inst (
.CLKOUT0(BUS_CLK_PLL),
.CLKOUT1(),
.CLKOUT2(CLK125PLLTX),
.CLKOUT3(CLK125PLLTX90),
.CLKOUT4(),
.CLKOUT5(),
.CLKFBOUT(PLL_FEEDBACK),
.LOCKED(LOCKED),
.CLKIN1(clkin),
.PWRDWN(0),
.RST(!RESET_N),
.CLKFBIN(PLL_FEEDBACK)
);
wire BUS_CLK;
BUFG BUFG_inst_BUS_CKL (.O(BUS_CLK), .I(BUS_CLK_PLL) );
wire CLK125TX, CLK125TX90, CLK125RX;
BUFG BUFG_inst_CLK125TX ( .O(CLK125TX), .I(CLK125PLLTX) );
BUFG BUFG_inst_CLK125TX90 ( .O(CLK125TX90), .I(CLK125PLLTX90) );
BUFG BUFG_inst_CLK125RX ( .O(CLK125RX), .I(rgmii_rxc) );
assign RST = !RESET_N | !LOCKED;
wire gmii_tx_en;
wire [7:0] gmii_txd;
wire gmii_tx_er;
wire gmii_crs;
wire gmii_col;
wire gmii_rx_dv;
wire [7:0] gmii_rxd;
wire gmii_rx_er;
wire mdio_gem_i;
wire mdio_gem_o;
wire mdio_gem_t;
wire link_status;
wire [1:0] clock_speed;
wire duplex_status;
rgmii_io rgmii
(
.rgmii_txd(rgmii_txd),
.rgmii_tx_ctl(rgmii_tx_ctl),
.rgmii_txc(rgmii_txc),
.rgmii_rxd(rgmii_rxd),
.rgmii_rx_ctl(rgmii_rx_ctl),
.gmii_txd_int(gmii_txd), // Internal gmii_txd signal.
.gmii_tx_en_int(gmii_tx_en),
.gmii_tx_er_int(gmii_tx_er),
.gmii_col_int(gmii_col),
.gmii_crs_int(gmii_crs),
.gmii_rxd_reg(gmii_rxd), // RGMII double data rate data valid.
.gmii_rx_dv_reg(gmii_rx_dv), // gmii_rx_dv_ibuf registered in IOBs.
.gmii_rx_er_reg(gmii_rx_er), // gmii_rx_er_ibuf registered in IOBs.
.eth_link_status(link_status),
.eth_clock_speed(clock_speed),
.eth_duplex_status(duplex_status),
// Following are generated by DCMs
.tx_rgmii_clk_int(CLK125TX), // Internal RGMII transmitter clock.
.tx_rgmii_clk90_int(CLK125TX90), // Internal RGMII transmitter clock w/ 90 deg phase
.rx_rgmii_clk_int(CLK125RX), // Internal RGMII receiver clock
.reset(!phy_rst_n)
);
// Instantiate tri-state buffer for MDIO
IOBUF i_iobuf_mdio(
.O(mdio_gem_i),
.IO(mdio_phy_mdio),
.I(mdio_gem_o),
.T(mdio_gem_t)
);
wire TCP_CLOSE_REQ;
wire TCP_OPEN_ACK;
wire RBCP_ACT, RBCP_WE, RBCP_RE;
wire [7:0] RBCP_WD, RBCP_RD;
wire [31:0] RBCP_ADDR;
wire TCP_RX_WR;
wire TCP_TX_WR;
wire [7:0] TCP_RX_DATA;
wire [7:0] TCP_TX_DATA;
wire TCP_TX_FULL;
wire RBCP_ACK;
wire SiTCP_RST;
reg [10:0] TCP_RX_WC_11B;
WRAP_SiTCP_GMII_XC7K_32K sitcp(
.CLK(BUS_CLK) , // in : System Clock >129MHz
.RST(RST) , // in : System reset
// Configuration parameters
.FORCE_DEFAULTn(1'b0) , // in : Load default parameters
.EXT_IP_ADDR(32'hc0a80a10) , // in : IP address[31:0] //192.168.10.16
.EXT_TCP_PORT(16'd24) , // in : TCP port #[15:0]
.EXT_RBCP_PORT(16'd4660) , // in : RBCP port #[15:0]
.PHY_ADDR(5'd3) , // in : PHY-device MIF address[4:0]
// EEPROM
.EEPROM_CS() , // out : Chip select
.EEPROM_SK() , // out : Serial data clock
.EEPROM_DI() , // out : Serial write data
.EEPROM_DO(1'b0) , // in : Serial read data
// user data, initial values are stored in the EEPROM, 0xFFFF_FC3C-3F
.USR_REG_X3C() , // out : Stored at 0xFFFF_FF3C
.USR_REG_X3D() , // out : Stored at 0xFFFF_FF3D
.USR_REG_X3E() , // out : Stored at 0xFFFF_FF3E
.USR_REG_X3F() , // out : Stored at 0xFFFF_FF3F
// MII interface
.GMII_RSTn(phy_rst_n) , // out : PHY reset
.GMII_1000M(1'b1) , // in : GMII mode (0:MII, 1:GMII)
// TX
.GMII_TX_CLK(CLK125TX) , // in : Tx clock
.GMII_TX_EN(gmii_tx_en) , // out : Tx enable
.GMII_TXD(gmii_txd) , // out : Tx data[7:0]
.GMII_TX_ER(gmii_tx_er) , // out : TX error
// RX
.GMII_RX_CLK(CLK125RX) , // in : Rx clock
.GMII_RX_DV(gmii_rx_dv) , // in : Rx data valid
.GMII_RXD(gmii_rxd) , // in : Rx data[7:0]
.GMII_RX_ER(gmii_rx_er) , // in : Rx error
.GMII_CRS(gmii_crs) , // in : Carrier sense
.GMII_COL(gmii_col) , // in : Collision detected
// Management IF
.GMII_MDC(mdio_phy_mdc) , // out : Clock for MDIO
.GMII_MDIO_IN(mdio_gem_i) , // in : Data
.GMII_MDIO_OUT(mdio_gem_o) , // out : Data
.GMII_MDIO_OE(mdio_gem_t) , // out : MDIO output enable
// User I/F
.SiTCP_RST(SiTCP_RST) , // out : Reset for SiTCP and related circuits
// TCP connection control
.TCP_OPEN_REQ(1'b0) , // in : Reserved input, shoud be 0
.TCP_OPEN_ACK(TCP_OPEN_ACK) , // out : Acknowledge for open (=Socket busy)
.TCP_ERROR() , // out : TCP error, its active period is equal to MSL
.TCP_CLOSE_REQ(TCP_CLOSE_REQ) , // out : Connection close request
.TCP_CLOSE_ACK(TCP_CLOSE_REQ) , // in : Acknowledge for closing
// FIFO I/F
.TCP_RX_WC({5'b1,TCP_RX_WC_11B}) , // in : Rx FIFO write count[15:0] (Unused bits should be set 1)
.TCP_RX_WR(TCP_RX_WR) , // out : Write enable
.TCP_RX_DATA(TCP_RX_DATA) , // out : Write data[7:0]
.TCP_TX_FULL(TCP_TX_FULL) , // out : Almost full flag
.TCP_TX_WR(TCP_TX_WR) , // in : Write enable
.TCP_TX_DATA(TCP_TX_DATA) , // in : Write data[7:0]
// RBCP
.RBCP_ACT(RBCP_ACT) , // out : RBCP active
.RBCP_ADDR(RBCP_ADDR) , // out : Address[31:0]
.RBCP_WD(RBCP_WD) , // out : Data[7:0]
.RBCP_WE(RBCP_WE) , // out : Write enable
.RBCP_RE(RBCP_RE) , // out : Read enable
.RBCP_ACK(RBCP_ACK) , // in : Access acknowledge
.RBCP_RD(RBCP_RD) // in : Read data[7:0]
);
wire [31:0] BUS_ADD;
wire [31:0] BUS_DATA;
wire BUS_WR, BUS_RD, BUS_RST;
assign BUS_RST = SiTCP_RST;
rbcp_to_bus irbcp_to_bus(
.BUS_RST(BUS_RST),
.BUS_CLK(BUS_CLK),
.RBCP_ACT(RBCP_ACT),
.RBCP_ADDR(RBCP_ADDR),
.RBCP_WD(RBCP_WD),
.RBCP_WE(RBCP_WE),
.RBCP_RE(RBCP_RE),
.RBCP_ACK(RBCP_ACK),
.RBCP_RD(RBCP_RD),
.BUS_WR(BUS_WR),
.BUS_RD(BUS_RD),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA)
);
wire fifo_empty, fifo_full, fifo_write;
reg fifo_next;
wire [31:0] FIFO_DATA;
fifo_32_to_8 #(
.DEPTH(128*1024)
) i_data_fifo (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE(fifo_write),
.READ(TCP_TX_WR),
.DATA_IN(FIFO_DATA),
.FULL(fifo_full),
.EMPTY(fifo_empty),
.DATA_OUT(TCP_TX_DATA)
);
wire [7:0] GPIO;
bdaq53_eth_core i_bdaq53_eth_core(
.RESET_N(RESET_N),
// clocks from PLL
.BUS_CLK(BUS_CLK),
.PLL_LOCKED(1'b1),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READY(!fifo_full && fifo_next),
.FIFO_DATA(FIFO_DATA),
.FIFO_VALID(fifo_write),
.GPIO(GPIO)
);
assign TCP_TX_WR = !TCP_TX_FULL && !fifo_empty;
reg ETH_START_SENDING, ETH_START_SENDING_temp, ETH_START_SENDING_LOCK;
/* ------- Main FSM ------- */
always @(posedge BUS_CLK)
begin
// wait for start condition
ETH_START_SENDING <= GPIO[0]; //TCP_OPEN_ACK;
if(ETH_START_SENDING && !ETH_START_SENDING_temp)
ETH_START_SENDING_LOCK <= 1;
ETH_START_SENDING_temp <= ETH_START_SENDING;
// RX FIFO word counter
if(TCP_RX_WR) begin
TCP_RX_WC_11B <= TCP_RX_WC_11B + 1;
end
else begin
TCP_RX_WC_11B <= 11'd0;
end
// FIFO handshake
if(ETH_START_SENDING_LOCK)
fifo_next <= 1'b1;
else
fifo_next <= 1'b0;
// stop, if connection is closed by host
if(TCP_CLOSE_REQ || !GPIO[0]) begin
ETH_START_SENDING_LOCK <= 0;
end
end
assign LED = ~{ TCP_OPEN_ACK, TCP_CLOSE_REQ, TCP_RX_WR, TCP_TX_WR,
fifo_full, fifo_empty, fifo_write, TCP_TX_WR};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFBUF_BLACKBOX_V
`define SKY130_FD_SC_MS__BUFBUF_BLACKBOX_V
/**
* bufbuf: Double buffer.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufbuf (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFBUF_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : sim_tb_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/07 13:45:16 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level testbench for testing DDR3.
// Instantiates:
// 1. IP_TOP (top-level representing FPGA, contains core,
// clocking, built-in testbench/memory checker and other
// support structures)
// 2. DDR3 Memory
// 3. Miscellaneous clock generation and reset logic
// 4. For ECC ON case inserts error on LSB bit
// of data from DRAM to FPGA.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/100fs
module sim_tb_top;
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter SIMULATION = "TRUE";
parameter BEGIN_ADDRESS = 32'h00000000;
parameter END_ADDRESS = 32'h00000fff;
parameter PRBS_EADDR_MASK_POS = 32'hff000000;
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3;
// # of memory Bank Address bits.
parameter CK_WIDTH = 1;
// # of CK/CK# outputs to memory.
parameter COL_WIDTH = 10;
// # of memory Column Address bits.
parameter CS_WIDTH = 1;
// # of unique CS outputs to memory.
parameter nCS_PER_RANK = 1;
// # of unique CS outputs per rank for phy
parameter CKE_WIDTH = 1;
// # of CKE outputs to memory.
parameter DM_WIDTH = 2;
// # of DM (data mask)
parameter DQ_WIDTH = 16;
// # of DQ (data)
parameter DQS_WIDTH = 2;
parameter DQS_CNT_WIDTH = 1;
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8;
// # of DQ per DQS
parameter ECC = "OFF";
parameter RANKS = 1;
// # of Ranks.
parameter ODT_WIDTH = 1;
// # of ODT outputs to memory.
parameter ROW_WIDTH = 13;
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27;
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8";
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
//***************************************************************************
// The following parameters are multiplier and divisor factors for PLLE2.
// Based on the selected design frequency these parameters vary.
//***************************************************************************
parameter CLKIN_PERIOD = 4999;
// Input Clock Period
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIM_BYPASS_INIT_CAL = "FAST";
// # = "SIM_INIT_CAL_FULL" - Complete
// memory init &
// calibration sequence
// # = "SKIP" - Not supported
// # = "FAST" - Complete memory init & use
// abbreviated calib sequence
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter TCQ = 100;
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter RST_ACT_LOW = 1;
// =1 for active low reset,
// =0 for active high.
//***************************************************************************
// Referece clock frequency parameters
//***************************************************************************
parameter REFCLK_FREQ = 200.0;
// IODELAYCTRL reference clock frequency
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter tCK = 3333;
// memory tCK paramter.
// # = Clock Period in pS.
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
parameter C_S_AXI_ID_WIDTH = 4;
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_ADDR_WIDTH = 32;
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32;
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 1;
// Indicates whether to instatiate upsizer
// Range: 0, 1
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF";
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
//***************************************************************************
// Debug and Internal parameters
//***************************************************************************
parameter DRAM_TYPE = "DDR2";
//**************************************************************************//
// Local parameters Declarations
//**************************************************************************//
localparam real TPROP_DQS = 0.00;
// Delay for DQS signal during Write Operation
localparam real TPROP_DQS_RD = 0.00;
// Delay for DQS signal during Read Operation
localparam real TPROP_PCB_CTRL = 0.00;
// Delay for Address and Ctrl signals
localparam real TPROP_PCB_DATA = 0.00;
// Delay for data signal during Write operation
localparam real TPROP_PCB_DATA_RD = 0.00;
// Delay for data signal during Read operation
localparam MEMORY_WIDTH = 16;
localparam NUM_COMP = DQ_WIDTH/MEMORY_WIDTH;
localparam ECC_TEST = "OFF" ;
localparam ERR_INSERT = (ECC_TEST == "ON") ? "OFF" : ECC ;
localparam real REFCLK_PERIOD = (1000000.0/(2*REFCLK_FREQ));
localparam RESET_PERIOD = 200000; //in pSec
localparam real SYSCLK_PERIOD = tCK;
//**************************************************************************//
// Wire Declarations
//**************************************************************************//
reg sys_rst_n;
wire sys_rst;
reg sys_clk_i;
reg clk_ref_i;
wire ddr2_reset_n;
wire [DQ_WIDTH-1:0] ddr2_dq_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_fpga;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_fpga;
wire [ROW_WIDTH-1:0] ddr2_addr_fpga;
wire [BANK_WIDTH-1:0] ddr2_ba_fpga;
wire ddr2_ras_n_fpga;
wire ddr2_cas_n_fpga;
wire ddr2_we_n_fpga;
wire [CKE_WIDTH-1:0] ddr2_cke_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_p_fpga;
wire [CK_WIDTH-1:0] ddr2_ck_n_fpga;
wire init_calib_complete;
wire tg_compare_error;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_fpga;
wire [DM_WIDTH-1:0] ddr2_dm_fpga;
wire [ODT_WIDTH-1:0] ddr2_odt_fpga;
reg [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram_tmp;
reg [DM_WIDTH-1:0] ddr2_dm_sdram_tmp;
reg [ODT_WIDTH-1:0] ddr2_odt_sdram_tmp;
wire [DQ_WIDTH-1:0] ddr2_dq_sdram;
reg [ROW_WIDTH-1:0] ddr2_addr_sdram;
reg [BANK_WIDTH-1:0] ddr2_ba_sdram;
reg ddr2_ras_n_sdram;
reg ddr2_cas_n_sdram;
reg ddr2_we_n_sdram;
wire [(CS_WIDTH*nCS_PER_RANK)-1:0] ddr2_cs_n_sdram;
wire [ODT_WIDTH-1:0] ddr2_odt_sdram;
reg [CKE_WIDTH-1:0] ddr2_cke_sdram;
wire [DM_WIDTH-1:0] ddr2_dm_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_p_sdram;
wire [DQS_WIDTH-1:0] ddr2_dqs_n_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_p_sdram;
reg [CK_WIDTH-1:0] ddr2_ck_n_sdram;
//**************************************************************************//
//**************************************************************************//
// Reset Generation
//**************************************************************************//
initial begin
sys_rst_n = 1'b0;
#RESET_PERIOD
sys_rst_n = 1'b1;
end
assign sys_rst = RST_ACT_LOW ? sys_rst_n : ~sys_rst_n;
//**************************************************************************//
// Clock Generation
//**************************************************************************//
initial
sys_clk_i = 1'b0;
always
sys_clk_i = #(CLKIN_PERIOD/2.0) ~sys_clk_i;
initial
clk_ref_i = 1'b0;
always
clk_ref_i = #REFCLK_PERIOD ~clk_ref_i;
always @( * ) begin
ddr2_ck_p_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_p_fpga;
ddr2_ck_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ck_n_fpga;
ddr2_addr_sdram <= #(TPROP_PCB_CTRL) ddr2_addr_fpga;
ddr2_ba_sdram <= #(TPROP_PCB_CTRL) ddr2_ba_fpga;
ddr2_ras_n_sdram <= #(TPROP_PCB_CTRL) ddr2_ras_n_fpga;
ddr2_cas_n_sdram <= #(TPROP_PCB_CTRL) ddr2_cas_n_fpga;
ddr2_we_n_sdram <= #(TPROP_PCB_CTRL) ddr2_we_n_fpga;
ddr2_cke_sdram <= #(TPROP_PCB_CTRL) ddr2_cke_fpga;
end
always @( * )
ddr2_cs_n_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_cs_n_fpga;
assign ddr2_cs_n_sdram = ddr2_cs_n_sdram_tmp;
always @( * )
ddr2_dm_sdram_tmp <= #(TPROP_PCB_DATA) ddr2_dm_fpga;//DM signal generation
assign ddr2_dm_sdram = ddr2_dm_sdram_tmp;
always @( * )
ddr2_odt_sdram_tmp <= #(TPROP_PCB_CTRL) ddr2_odt_fpga;
assign ddr2_odt_sdram = ddr2_odt_sdram_tmp;
// Controlling the bi-directional BUS
genvar dqwd;
generate
for (dqwd = 1;dqwd < DQ_WIDTH;dqwd = dqwd+1) begin : dq_delay
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT ("OFF")
)
u_delay_dq
(
.A (ddr2_dq_fpga[dqwd]),
.B (ddr2_dq_sdram[dqwd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
// For ECC ON case error is inserted on LSB bit from DRAM to FPGA
WireDelay #
(
.Delay_g (TPROP_PCB_DATA),
.Delay_rd (TPROP_PCB_DATA_RD),
.ERR_INSERT (ERR_INSERT)
)
u_delay_dq_0
(
.A (ddr2_dq_fpga[0]),
.B (ddr2_dq_sdram[0]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
endgenerate
genvar dqswd;
generate
for (dqswd = 0;dqswd < DQS_WIDTH;dqswd = dqswd+1) begin : dqs_delay
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_p
(
.A (ddr2_dqs_p_fpga[dqswd]),
.B (ddr2_dqs_p_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
WireDelay #
(
.Delay_g (TPROP_DQS),
.Delay_rd (TPROP_DQS_RD),
.ERR_INSERT ("OFF")
)
u_delay_dqs_n
(
.A (ddr2_dqs_n_fpga[dqswd]),
.B (ddr2_dqs_n_sdram[dqswd]),
.reset (sys_rst_n),
.phy_init_done (init_calib_complete)
);
end
endgenerate
//===========================================================================
// FPGA Memory Controller
//===========================================================================
example_top #
(
.SIMULATION (SIMULATION),
.BEGIN_ADDRESS (BEGIN_ADDRESS),
.END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CS_WIDTH (CS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC_TEST (ECC_TEST),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH),
.BURST_MODE (BURST_MODE),
.TCQ (TCQ),
.C_S_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_S_AXI_SUPPORTS_NARROW_BURST (C_S_AXI_SUPPORTS_NARROW_BURST),
.DEBUG_PORT (DEBUG_PORT)
// .RST_ACT_LOW (RST_ACT_LOW)
)
u_ip_top
(
.ddr2_dq (ddr2_dq_fpga),
.ddr2_dqs_n (ddr2_dqs_n_fpga),
.ddr2_dqs_p (ddr2_dqs_p_fpga),
.ddr2_addr (ddr2_addr_fpga),
.ddr2_ba (ddr2_ba_fpga),
.ddr2_ras_n (ddr2_ras_n_fpga),
.ddr2_cas_n (ddr2_cas_n_fpga),
.ddr2_we_n (ddr2_we_n_fpga),
.ddr2_ck_p (ddr2_ck_p_fpga),
.ddr2_ck_n (ddr2_ck_n_fpga),
.ddr2_cke (ddr2_cke_fpga),
.ddr2_cs_n (ddr2_cs_n_fpga),
.ddr2_dm (ddr2_dm_fpga),
.ddr2_odt (ddr2_odt_fpga),
.sys_clk_i (sys_clk_i),
.clk_ref_i (clk_ref_i),
.init_calib_complete (init_calib_complete),
.tg_compare_error (tg_compare_error),
.sys_rst (sys_rst)
);
//**************************************************************************//
// Memory Models instantiations
//**************************************************************************//
genvar r,i;
generate
for (r = 0; r < CS_WIDTH; r = r + 1) begin: mem_rnk
if(DQ_WIDTH/16) begin: mem
for (i = 0; i < NUM_COMP; i = i + 1) begin: gen_mem
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs (ddr2_dm_sdram[(2*(i+1)-1):(2*i)]),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq (ddr2_dq_sdram[16*(i+1)-1:16*(i)]),
.dqs (ddr2_dqs_p_sdram[(2*(i+1)-1):(2*i)]),
.dqs_n (ddr2_dqs_n_sdram[(2*(i+1)-1):(2*i)]),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
if (DQ_WIDTH%16) begin: gen_mem_extrabits
ddr2_model u_comp_ddr2
(
.ck (ddr2_ck_p_sdram[0+(NUM_COMP*r)]),
.ck_n (ddr2_ck_n_sdram[0+(NUM_COMP*r)]),
.cke (ddr2_cke_sdram[0+(NUM_COMP*r)]),
.cs_n (ddr2_cs_n_sdram[0+(NUM_COMP*r)]),
.ras_n (ddr2_ras_n_sdram),
.cas_n (ddr2_cas_n_sdram),
.we_n (ddr2_we_n_sdram),
.dm_rdqs ({ddr2_dm_sdram[DM_WIDTH-1],ddr2_dm_sdram[DM_WIDTH-1]}),
.ba (ddr2_ba_sdram),
.addr (ddr2_addr_sdram),
.dq ({ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)],
ddr2_dq_sdram[DQ_WIDTH-1:(DQ_WIDTH-8)]}),
.dqs ({ddr2_dqs_p_sdram[DQS_WIDTH-1],
ddr2_dqs_p_sdram[DQS_WIDTH-1]}),
.dqs_n ({ddr2_dqs_n_sdram[DQS_WIDTH-1],
ddr2_dqs_n_sdram[DQS_WIDTH-1]}),
.rdqs_n (),
.odt (ddr2_odt_sdram[0+(NUM_COMP*r)])
);
end
end
endgenerate
//***************************************************************************
// Reporting the test case status
// Status reporting logic exists both in simulation test bench (sim_tb_top)
// and sim.do file for ModelSim. Any update in simulation run time or time out
// in this file need to be updated in sim.do file as well.
//***************************************************************************
initial
begin : Logging
fork
begin : calibration_done
wait (init_calib_complete);
$display("Calibration Done");
#50000000.0;
if (!tg_compare_error) begin
$display("TEST PASSED");
end
else begin
$display("TEST FAILED: DATA ERROR");
end
disable calib_not_done;
$finish;
end
begin : calib_not_done
if (SIM_BYPASS_INIT_CAL == "SIM_INIT_CAL_FULL")
#2500000000.0;
else
#1000000000.0;
if (!init_calib_complete) begin
$display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
end
disable calibration_done;
$finish;
end
join
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__MACRO_SPARECELL_SYMBOL_V
`define SKY130_FD_SC_HD__MACRO_SPARECELL_SYMBOL_V
/**
* macro_sparecell: Macro cell for metal-mask-only revisioning,
* containing inverter, 2-input NOR, 2-input NAND,
* and constant cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__macro_sparecell (
//# {{data|Data Signals}}
output LO
);
// Voltage supply signals
supply0 VGND;
supply0 VNB ;
supply1 VPB ;
supply1 VPWR;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__MACRO_SPARECELL_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_BLACKBOX_V
`define SKY130_FD_SC_MS__FILL_DIODE_BLACKBOX_V
/**
* fill_diode: Fill diode.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__fill_diode ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_BLACKBOX_V
|
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