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/*
- This is a material implementd for google summer of code 2017.
- I built this module to be more familiar with the design required, start edit, re-implement the whole thing
- The mentor feedback would really help me getting more and more clear vision about this project
--------------------------------------------------------------------------------------------------------------
Written by: Abdelrahman Elbehery
*/
module PWM_INTERFACE (
input CLK_IN, //Input clock [Faster than the PWM clocl]
input [7:0] PWM_DCycle, //The PWM duty cycle input [Coming from the i2c slave]
output reg PWM_OUT //module pulse width modulated output
);
//internal registers, signals and wire assignments are here
parameter [4:0] N = 31, K=1; //The division forumula is pwm_clk=(CLK_IN)/(K*2^n*2^8)
reg [31:0] clk_div =0; //clock division counter for the main clock
reg [7:0] pwm_clk =0; //the PWM clock counter
//code body goes here
always @ ( posedge CLK_IN ) begin
clk_div<=clk_div+K; //Increment the clock each cycle by K
end
always @ (posedge clk_div[N]) begin //Watch the change of the Nth bit
pwm_clk<=pwm_clk+1;
end
always @ ( * ) begin
if(pwm_clk<=PWM_DCycle & PWM_DCycle!=0)
PWM_OUT<=1;
else
PWM_OUT<=0;
end
endmodule // PWM_INTERFACE
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module timer_1 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_continuous;
wire control_interrupt_enable;
reg [ 3: 0] control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 31: 0] counter_load_value;
reg [ 31: 0] counter_snapshot;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 31: 0] internal_counter;
wire irq;
reg [ 15: 0] period_h_register;
wire period_h_wr_strobe;
reg [ 15: 0] period_l_register;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire snap_h_wr_strobe;
wire snap_l_wr_strobe;
wire [ 31: 0] snap_read_value;
wire snap_strobe;
wire start_strobe;
wire status_wr_strobe;
wire stop_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 32'hC34F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = {period_h_register,
period_l_register};
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = start_strobe;
assign do_stop_counter = (stop_strobe ) ||
(force_reload ) ||
(counter_is_zero && ~control_continuous );
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 2)}} & period_l_register) |
({16 {(address == 3)}} & period_h_register) |
({16 {(address == 4)}} & snap_read_value[15 : 0]) |
({16 {(address == 5)}} & snap_read_value[31 : 16]) |
({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_l_register <= 49999;
else if (period_l_wr_strobe)
period_l_register <= writedata;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
period_h_register <= 0;
else if (period_h_wr_strobe)
period_h_register <= writedata;
end
assign snap_l_wr_strobe = chipselect && ~write_n && (address == 4);
assign snap_h_wr_strobe = chipselect && ~write_n && (address == 5);
assign snap_strobe = snap_l_wr_strobe || snap_h_wr_strobe;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_snapshot <= 0;
else if (snap_strobe)
counter_snapshot <= internal_counter;
end
assign snap_read_value = counter_snapshot;
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[3 : 0];
end
assign stop_strobe = writedata[3] && control_wr_strobe;
assign start_strobe = writedata[2] && control_wr_strobe;
assign control_continuous = control_register[1];
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBN_BLACKBOX_V
`define SKY130_FD_SC_LP__DLRBN_BLACKBOX_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlrbn (
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBN_BLACKBOX_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface
`timescale 1ns/100ps
module axi_ad9467_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data,
adc_or,
// processor interface
adc_ddr_edgesel,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
// buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [ 7:0] adc_data_in_p;
input [ 7:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data;
output adc_or;
// processor interface
input adc_ddr_edgesel;
// delay control signals
input up_clk;
input [ 8:0] up_dld;
input [44:0] up_dwdata;
output [44:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg [ 7:0] adc_data_p = 'd0;
reg [ 7:0] adc_data_n = 'd0;
reg [ 7:0] adc_data_p_d = 'd0;
reg [ 7:0] adc_dmux_a = 'd0;
reg [ 7:0] adc_dmux_b = 'd0;
reg [15:0] adc_data = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or = 'd0;
// internal signals
wire [ 7:0] adc_data_p_s;
wire [ 7:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
// sample select (p/n) swap
always @(posedge adc_clk) begin
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_p_d <= adc_data_p;
adc_dmux_a <= (adc_ddr_edgesel == 1'b1) ? adc_data_n : adc_data_p;
adc_dmux_b <= (adc_ddr_edgesel == 1'b1) ? adc_data_p_d : adc_data_n;
adc_data[15] <= adc_dmux_b[7];
adc_data[14] <= adc_dmux_a[7];
adc_data[13] <= adc_dmux_b[6];
adc_data[12] <= adc_dmux_a[6];
adc_data[11] <= adc_dmux_b[5];
adc_data[10] <= adc_dmux_a[5];
adc_data[ 9] <= adc_dmux_b[4];
adc_data[ 8] <= adc_dmux_a[4];
adc_data[ 7] <= adc_dmux_b[3];
adc_data[ 6] <= adc_dmux_a[3];
adc_data[ 5] <= adc_dmux_b[2];
adc_data[ 4] <= adc_dmux_a[2];
adc_data[ 3] <= adc_dmux_b[1];
adc_data[ 2] <= adc_dmux_a[1];
adc_data[ 1] <= adc_dmux_b[0];
adc_data[ 0] <= adc_dmux_a[0];
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
if ((adc_or_p == 1'b1) || (adc_or_n == 1'b1)) begin
adc_or <= 1'b1;
end else begin
adc_or <= 1'b0;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[8]),
.up_dwdata (up_dwdata[44:40]),
.up_drdata (up_drdata[44:40]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__A211O_PP_BLACKBOX_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a211o (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_PP_BLACKBOX_V
|
//
// dsp.v -- character display interface
//
module dsp(clk, reset,
addr, en, wr, wt,
data_in, data_out,
hsync, vsync,
r, g, b);
// internal interface
input clk;
input reset;
input [13:2] addr;
input en;
input wr;
output wt;
input [15:0] data_in;
output [15:0] data_out;
// external interface
output hsync;
output vsync;
output [2:0] r;
output [2:0] g;
output [2:0] b;
reg state;
display display1(
.clk(clk),
.dsp_row(addr[13:9]),
.dsp_col(addr[8:2]),
.dsp_en(en),
.dsp_wr(wr),
.dsp_wr_data(data_in[15:0]),
.dsp_rd_data(data_out[15:0]),
.hsync(hsync),
.vsync(vsync),
.r(r[2:0]),
.g(g[2:0]),
.b(b[2:0])
);
always @(posedge clk) begin
if (reset == 1) begin
state <= 1'b0;
end else begin
case (state)
1'b0:
begin
if (en == 1 && wr == 0) begin
state <= 1'b1;
end
end
1'b1:
begin
state <= 1'b0;
end
endcase
end
end
assign wt = (en == 1 && wr == 0 && state == 1'b0) ? 1 : 0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NOR3_FUNCTIONAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3_FUNCTIONAL_V |
// issue 1698
module sub_mod
(
input [8+4-1:0][7:0] add_left,
input [8-4-1:0][7:0] substract_left,
input [8*4-1:0][7:0] multiply_left,
input [8/4-1:0][7:0] divide_left
input [7:0][8+4-1:0] add_right,
input [7:0][8-4-1:0] substract_right,
input [7:0][8*4-1:0] multiply_right,
input [7:0][8/4-1:0] divide_right,
);
endmodule : sub_mod
module top_mod
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [8+4-1:0] [7:0] add_left, // To sub_mod_i of sub_mod.v
input [7:0] [11:0] add_right, // To sub_mod_i of sub_mod.v
input [8/4-1:0] [7:0] divide_left, // To sub_mod_i of sub_mod.v
input [7:0] [1:0] divide_right, // To sub_mod_i of sub_mod.v
input [8*4-1:0] [7:0] multiply_left, // To sub_mod_i of sub_mod.v
input [7:0] [31:0] multiply_right, // To sub_mod_i of sub_mod.v
input [8-4-1:0] [7:0] substract_left, // To sub_mod_i of sub_mod.v
input [7:0] [3:0] substract_right // To sub_mod_i of sub_mod.v
// End of automatics
);
sub_mod sub_mod_i
(/*AUTOINST*/
// Inputs
.add_left (add_left/*[8+4-1:0][7:0]*/),
.substract_left (substract_left/*[8-4-1:0][7:0]*/),
.multiply_left (multiply_left/*[8*4-1:0][7:0]*/),
.divide_left (divide_left/*[8/4-1:0][7:0]*/),
.add_right (add_right/*[7:0][8+4-1:0]*/),
.substract_right (substract_right/*[7:0][8-4-1:0]*/),
.multiply_right (multiply_right/*[7:0][8*4-1:0]*/),
.divide_right (divide_right/*[7:0][8/4-1:0]*/));
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's DC RAMs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instatiation of DC RAM blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_ram.v,v $
// Revision 1.6 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.2 2003/12/10 15:28:28 simons
// Support for ram with byte selects added.
//
// Revision 1.2.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
module or1200_dc_ram(
// Reset and clock
clk, rst,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Internal i/f
addr, en, we, datain, dataout
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
//
// I/O
//
input clk;
input rst;
input [aw-1:0] addr;
input en;
input [3:0] we;
input [dw-1:0] datain;
output [dw-1:0] dataout;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
`ifdef OR1200_NO_DC
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`else
//
// Instantiation of RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x32_bw dc_ram(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x32_bw dc_ram(
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.clk(clk),
.rst(rst),
.ce(en),
.we(we),
.oe(1'b1),
.addr(addr),
.di(datain),
.doq(dataout)
);
`endif
endmodule
|
`timescale 1ns/1ps
`define BAUDRATE (`CLOCK_RATE / 32)
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input rst,
output master_ready,
input in_ready,
input [31:0] in_command,
input [31:0] in_address,
input [31:0] in_data,
input [27:0] in_data_count,
input out_ready,
output out_en,
output [31:0] out_status,
output [31:0] out_address,
output [31:0] out_data,
output [27:0] out_data_count,
input [31:0] test_id,
input ih_reset,
output device_interrupt
);
//Parameters
//Registers/Wires
reg r_rst;
reg r_in_ready;
reg [31:0] r_in_command;
reg [31:0] r_in_address;
reg [31:0] r_in_data;
reg [27:0] r_in_data_count;
reg r_out_ready;
reg r_ih_reset;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
always @ (*) r_in_ready = in_ready;
always @ (*) r_in_command = in_command;
always @ (*) r_in_address = in_address;
always @ (*) r_in_data = in_data;
always @ (*) r_in_data_count = in_data_count;
always @ (*) r_out_ready = out_ready;
always @ (*) r_ih_reset = ih_reset;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Memory Interface
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire mem_o_we;
wire mem_o_stb;
wire mem_o_cyc;
wire [3:0] mem_o_sel;
wire [31:0] mem_o_adr;
wire [31:0] mem_o_dat;
wire [31:0] mem_i_dat;
wire mem_i_ack;
wire mem_i_int;
wire w_phy_rx;
wire w_phy_tx;
wire uart_wr_stb;
wire [7:0] uart_wr_data;
wire uart_wr_busy;
wire [7:0] uart_rd_data;
wire uart_rd_stb;
wire w_master_ready;
wire w_ih_ready;
wire [31:0] w_in_command;
wire [31:0] w_in_address;
wire [31:0] w_in_data;
wire [27:0] w_in_data_count;
wire w_oh_ready;
wire w_oh_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
wire w_ih_reset;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (r_rst ),
.i_ih_rst (w_ih_reset ),
.i_ready (w_ih_ready ),
.i_command (w_in_command ),
.i_address (w_in_address ),
.i_data (w_in_data ),
.i_data_count (w_in_data_count ),
.i_out_ready (w_oh_ready ),
.o_en (w_oh_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_msk (w_wbp_msk ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
uart_if_tester s1 (
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (r_rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (r_rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (r_rst ),
//masters
.i_m1_we (mem_o_we ),
.i_m1_stb (mem_o_stb ),
.i_m1_cyc (mem_o_cyc ),
.i_m1_sel (mem_o_sel ),
.i_m1_dat (mem_o_dat ),
.i_m1_adr (mem_o_adr ),
.o_m1_dat (mem_i_dat ),
.o_m1_ack (mem_i_ack ),
.o_m1_int (mem_i_int ),
.i_m0_we (w_sm0_i_wbs_we ),
.i_m0_stb (w_sm0_i_wbs_stb ),
.i_m0_cyc (w_sm0_i_wbs_cyc ),
.i_m0_sel (w_sm0_i_wbs_sel ),
.i_m0_dat (w_sm0_i_wbs_dat ),
.i_m0_adr (w_sm0_i_wbs_adr ),
.o_m0_dat (w_sm0_o_wbs_dat ),
.o_m0_ack (w_sm0_o_wbs_ack ),
.o_m0_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
wb_bram #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (10 )
)bram(
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
uart_io_handler #(
.BAUDRATE (`BAUDRATE )
) uih (
.clk (clk ),
.rst (rst ),
.o_ih_ready (w_ih_ready ),
.o_ih_reset (w_ih_reset ),
.i_master_ready (w_master_ready ),
.o_in_command (w_in_command ),
.o_in_address (w_in_address ),
.o_in_data (w_in_data ),
.o_in_data_count (w_in_data_count ),
.o_oh_ready (w_oh_ready ),
.i_oh_en (w_oh_en ),
.i_out_status (w_out_status ),
.i_out_address (w_out_address ),
.i_out_data (w_out_data ),
.i_out_data_count (w_out_data_count ),
.i_phy_uart_in (w_phy_rx ),
.o_phy_uart_out (w_phy_tx )
);
uart #(
.DEFAULT_BAUDRATE (`BAUDRATE )
) uart (
.clk (clk ),
.rst (rst ),
.tx (w_phy_rx ),
.transmit (uart_wr_stb ),
.tx_byte (uart_wr_data ),
.is_transmitting (uart_wr_busy ),
.rx (w_phy_tx ),
.rx_byte (uart_rd_data ),
.received (uart_rd_stb ),
.set_clock_div (1'h0 )
);
//Disable Slave 0
assign w_wbs0_int = 0;
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign device_interrupt = w_wbp_int;
/*
READ ME IF YOUR MODULE WILL INTERFACE WITH MEMORY
If you want to talk to memory over the wishbone bus directly, your module must control the following signals:
(Your module will be a wishbone master)
mem_o_we
mem_o_stb
mem_o_cyc
mem_o_sel
mem_o_adr
mem_o_dat
mem_i_dat
mem_i_ack
mem_i_int
Currently this bus is disabled so if will not interface with memory these signals can be left
For a reference check out wb_sd_host
*/
assign mem_o_we = 0;
assign mem_o_stb = 0;
assign mem_o_cyc = 0;
assign mem_o_sel = 0;
assign mem_o_adr = 0;
assign mem_o_dat = 0;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V
/**
* sdfrtn: Scan delay flop, inverted reset, inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sdfrtn (
Q ,
CLK_N ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk , CLK_N_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , mux_out, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 );
assign cond4 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFRTN_BEHAVIORAL_PP_V |
(** * Imp: Simple Imperative Programs *)
(** In this chapter, we begin a new direction that will continue for
the rest of the course. Up to now most of our attention has been
focused on various aspects of Coq itself, while from now on we'll
mostly be using Coq to formalize other things. (We'll continue to
pause from time to time to introduce a few additional aspects of
Coq.)
Our first case study is a _simple imperative programming language_
called Imp, embodying a tiny core fragment of conventional
mainstream languages such as C and Java. Here is a familiar
mathematical function written in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
*)
(** This chapter looks at how to define the _syntax_ and _semantics_
of Imp; the chapters that follow develop a theory of _program
equivalence_ and introduce _Hoare Logic_, a widely used logic for
reasoning about imperative programs. *)
(* ####################################################### *)
(** *** Sflib *)
(** A minor technical point: Instead of asking Coq to import our
earlier definitions from chapter [Logic], we import a small library
called [Sflib.v], containing just a few definitions and theorems
from earlier chapters that we'll actually use in the rest of the
course. This change should be nearly invisible, since most of what's
missing from Sflib has identical definitions in the Coq standard
library. The main reason for doing it is to tidy the global Coq
environment so that, for example, it is easier to search for
relevant theorems. *)
Require Export SfLib.
(* ####################################################### *)
(** * Arithmetic and Boolean Expressions *)
(** We'll present Imp in three parts: first a core language of
_arithmetic and boolean expressions_, then an extension of these
expressions with _variables_, and finally a language of _commands_
including assignment, conditions, sequencing, and loops. *)
(* ####################################################### *)
(** ** Syntax *)
Module AExp.
(** These two definitions specify the _abstract syntax_ of
arithmetic and boolean expressions. *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
(** In this chapter, we'll elide the translation from the
concrete syntax that a programmer would actually write to these
abstract syntax trees -- the process that, for example, would
translate the string ["1+2*3"] to the AST [APlus (ANum
1) (AMult (ANum 2) (ANum 3))]. The optional chapter [ImpParser]
develops a simple implementation of a lexical analyzer and parser
that can perform this translation. You do _not_ need to
understand that file to understand this one, but if you haven't
taken a course where these techniques are covered (e.g., a
compilers course) you may want to skim it. *)
(** *** *)
(** For comparison, here's a conventional BNF (Backus-Naur Form)
grammar defining the same abstract syntax:
a ::= nat
| a + a
| a - a
| a * a
b ::= true
| false
| a = a
| a <= a
| not b
| b and b
*)
(** Compared to the Coq version above...
- The BNF is more informal -- for example, it gives some
suggestions about the surface syntax of expressions (like the
fact that the addition operation is written [+] and is an
infix symbol) while leaving other aspects of lexical analysis
and parsing (like the relative precedence of [+], [-], and
[*]) unspecified. Some additional information -- and human
intelligence -- would be required to turn this description
into a formal definition (when implementing a compiler, for
example).
The Coq version consistently omits all this information and
concentrates on the abstract syntax only.
- On the other hand, the BNF version is lighter and
easier to read. Its informality makes it flexible, which is
a huge advantage in situations like discussions at the
blackboard, where conveying general ideas is more important
than getting every detail nailed down precisely.
Indeed, there are dozens of BNF-like notations and people
switch freely among them, usually without bothering to say which
form of BNF they're using because there is no need to: a
rough-and-ready informal understanding is all that's
needed. *)
(** It's good to be comfortable with both sorts of notations:
informal ones for communicating between humans and formal ones for
carrying out implementations and proofs. *)
(* ####################################################### *)
(** ** Evaluation *)
(** _Evaluating_ an arithmetic expression produces a number. *)
Fixpoint aeval (a : aexp) : nat :=
match a with
| ANum n => n
| APlus a1 a2 => (aeval a1) + (aeval a2)
| AMinus a1 a2 => (aeval a1) - (aeval a2)
| AMult a1 a2 => (aeval a1) * (aeval a2)
end.
Example test_aeval1:
aeval (APlus (ANum 2) (ANum 2)) = 4.
Proof. reflexivity. Qed.
(** *** *)
(** Similarly, evaluating a boolean expression yields a boolean. *)
Fixpoint beval (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval a1) (aeval a2)
| BLe a1 a2 => ble_nat (aeval a1) (aeval a2)
| BNot b1 => negb (beval b1)
| BAnd b1 b2 => andb (beval b1) (beval b2)
end.
(* ####################################################### *)
(** ** Optimization *)
(** We haven't defined very much yet, but we can already get
some mileage out of the definitions. Suppose we define a function
that takes an arithmetic expression and slightly simplifies it,
changing every occurrence of [0+e] (i.e., [(APlus (ANum 0) e])
into just [e]. *)
Fixpoint optimize_0plus (a:aexp) : aexp :=
match a with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
(** To make sure our optimization is doing the right thing we
can test it on some examples and see if the output looks OK. *)
Example test_optimize_0plus:
optimize_0plus (APlus (ANum 2)
(APlus (ANum 0)
(APlus (ANum 0) (ANum 1))))
= APlus (ANum 2) (ANum 1).
Proof. reflexivity. Qed.
(** But if we want to be sure the optimization is correct --
i.e., that evaluating an optimized expression gives the same
result as the original -- we should prove it. *)
Theorem optimize_0plus_sound: forall a,
aeval (optimize_0plus a) = aeval a.
induction a; crush.
- Case "plus". destruct a1; crush. destruct n; crush.
Qed.
Hint Rewrite optimize_0plus_sound.
(* ####################################################### *)
(** * Coq Automation *)
(** The repetition in this last proof is starting to be a little
annoying. If either the language of arithmetic expressions or the
optimization being proved sound were significantly more complex,
it would begin to be a real problem.
So far, we've been doing all our proofs using just a small handful
of Coq's tactics and completely ignoring its powerful facilities
for constructing parts of proofs automatically. This section
introduces some of these facilities, and we will see more over the
next several chapters. Getting used to them will take some
energy -- Coq's automation is a power tool -- but it will allow us
to scale up our efforts to more complex definitions and more
interesting properties without becoming overwhelmed by boring,
repetitive, low-level details. *)
(* ####################################################### *)
(** ** Tacticals *)
(** _Tacticals_ is Coq's term for tactics that take other tactics as
arguments -- "higher-order tactics," if you will. *)
(* ####################################################### *)
(** *** The [repeat] Tactical *)
(** The [repeat] tactical takes another tactic and keeps applying
this tactic until the tactic fails. Here is an example showing
that [100] is even using repeat. *)
Theorem ev100 : ev 100.
Proof.
repeat (apply ev_SS). (* applies ev_SS 50 times,
until [apply ev_SS] fails *)
apply ev_0.
Qed.
(* Print ev100. *)
(** The [repeat T] tactic never fails; if the tactic [T] doesn't apply
to the original goal, then repeat still succeeds without changing
the original goal (it repeats zero times). *)
Theorem ev100' : ev 100.
Proof.
repeat (apply ev_0). (* doesn't fail, applies ev_0 zero times *)
repeat (apply ev_SS). apply ev_0. (* we can continue the proof *)
Qed.
(** The [repeat T] tactic does not have any bound on the number of
times it applies [T]. If [T] is a tactic that always succeeds then
repeat [T] will loop forever (e.g. [repeat simpl] loops forever
since [simpl] always succeeds). While Coq's term language is
guaranteed to terminate, Coq's tactic language is not! *)
(* ####################################################### *)
(** *** The [try] Tactical *)
(** If [T] is a tactic, then [try T] is a tactic that is just like [T]
except that, if [T] fails, [try T] _successfully_ does nothing at
all (instead of failing). *)
Theorem silly1 : forall ae, aeval ae = aeval ae.
Proof. try reflexivity. (* this just does [reflexivity] *) Qed.
Theorem silly2 : forall (P : Prop), P -> P.
Proof.
intros P HP.
try reflexivity. (* just [reflexivity] would have failed *)
apply HP. (* we can still finish the proof in some other way *)
Qed.
(** Using [try] in a completely manual proof is a bit silly, but
we'll see below that [try] is very useful for doing automated
proofs in conjunction with the [;] tactical. *)
(* ####################################################### *)
(** *** The [;] Tactical (Simple Form) *)
(** In its most commonly used form, the [;] tactical takes two tactics
as argument: [T;T'] first performs the tactic [T] and then
performs the tactic [T'] on _each subgoal_ generated by [T]. *)
(** For example, consider the following trivial lemma: *)
Lemma foo : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n.
(* Leaves two subgoals, which are discharged identically... *)
Case "n=0". simpl. reflexivity.
Case "n=Sn'". simpl. reflexivity.
Qed.
(** We can simplify this proof using the [;] tactical: *)
Lemma foo' : forall n, ble_nat 0 n = true.
Proof.
intros.
destruct n; (* [destruct] the current goal *)
simpl; (* then [simpl] each resulting subgoal *)
reflexivity. (* and do [reflexivity] on each resulting subgoal *)
Qed.
(** Using [try] and [;] together, we can get rid of the repetition in
the proof that was bothering us a little while ago. *)
Theorem optimize_0plus_sound': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity).
(* The remaining cases -- ANum and APlus -- are different *)
Case "ANum". reflexivity.
Case "APlus".
destruct a1;
(* Again, most cases follow directly by the IH *)
try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
(* The interesting case, on which the [try...] does nothing,
is when [e1 = ANum n]. In this case, we have to destruct
[n] (to see whether the optimization applies) and rewrite
with the induction hypothesis. *)
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** Coq experts often use this "[...; try... ]" idiom after a tactic
like [induction] to take care of many similar cases all at once.
Naturally, this practice has an analog in informal proofs.
Here is an informal proof of this theorem that matches the
structure of the formal one:
_Theorem_: For all arithmetic expressions [a],
aeval (optimize_0plus a) = aeval a.
_Proof_: By induction on [a]. The [AMinus] and [AMult] cases
follow directly from the IH. The remaining cases are as follows:
- Suppose [a = ANum n] for some [n]. We must show
aeval (optimize_0plus (ANum n)) = aeval (ANum n).
This is immediate from the definition of [optimize_0plus].
- Suppose [a = APlus a1 a2] for some [a1] and [a2]. We
must show
aeval (optimize_0plus (APlus a1 a2))
= aeval (APlus a1 a2).
Consider the possible forms of [a1]. For most of them,
[optimize_0plus] simply calls itself recursively for the
subexpressions and rebuilds a new expression of the same form
as [a1]; in these cases, the result follows directly from the
IH.
The interesting case is when [a1 = ANum n] for some [n].
If [n = ANum 0], then
optimize_0plus (APlus a1 a2) = optimize_0plus a2
and the IH for [a2] is exactly what we need. On the other
hand, if [n = S n'] for some [n'], then again [optimize_0plus]
simply calls itself recursively, and the result follows from
the IH. [] *)
(** This proof can still be improved: the first case (for [a = ANum
n]) is very trivial -- even more trivial than the cases that we
said simply followed from the IH -- yet we have chosen to write it
out in full. It would be better and clearer to drop it and just
say, at the top, "Most cases are either immediate or direct from
the IH. The only interesting case is the one for [APlus]..." We
can make the same improvement in our formal proof too. Here's how
it looks: *)
Theorem optimize_0plus_sound'': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
induction a;
(* Most cases follow directly by the IH *)
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
(* ... or are immediate by definition *)
try reflexivity.
(* The interesting case is when a = APlus a1 a2. *)
Case "APlus".
destruct a1; try (simpl; simpl in IHa1; rewrite IHa1;
rewrite IHa2; reflexivity).
SCase "a1 = ANum n". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(* ####################################################### *)
(** *** The [;] Tactical (General Form) *)
(** The [;] tactical has a more general than the simple [T;T'] we've
seen above, which is sometimes also useful. If [T], [T1], ...,
[Tn] are tactics, then
T; [T1 | T2 | ... | Tn]
is a tactic that first performs [T] and then performs [T1] on the
first subgoal generated by [T], performs [T2] on the second
subgoal, etc.
So [T;T'] is just special notation for the case when all of the
[Ti]'s are the same tactic; i.e. [T;T'] is just a shorthand for:
T; [T' | T' | ... | T']
*)
(* ####################################################### *)
(** ** Defining New Tactic Notations *)
(** Coq also provides several ways of "programming" tactic scripts.
- The [Tactic Notation] idiom illustrated below gives a handy
way to define "shorthand tactics" that bundle several tactics
into a single command.
- For more sophisticated programming, Coq offers a small
built-in programming language called [Ltac] with primitives
that can examine and modify the proof state. The details are
a bit too complicated to get into here (and it is generally
agreed that [Ltac] is not the most beautiful part of Coq's
design!), but they can be found in the reference manual, and
there are many examples of [Ltac] definitions in the Coq
standard library that you can use as examples.
- There is also an OCaml API, which can be used to build tactics
that access Coq's internal structures at a lower level, but
this is seldom worth the trouble for ordinary Coq users.
The [Tactic Notation] mechanism is the easiest to come to grips with,
and it offers plenty of power for many purposes. Here's an example.
*)
Tactic Notation "simpl_and_try" tactic(c) :=
simpl;
try c.
(** This defines a new tactical called [simpl_and_try] which
takes one tactic [c] as an argument, and is defined to be
equivalent to the tactic [simpl; try c]. For example, writing
"[simpl_and_try reflexivity.]" in a proof would be the same as
writing "[simpl; try reflexivity.]" *)
(** The next subsection gives a more sophisticated use of this
feature... *)
(* ####################################################### *)
(** *** Bulletproofing Case Analyses *)
(** Being able to deal with most of the cases of an [induction]
or [destruct] all at the same time is very convenient, but it can
also be a little confusing. One problem that often comes up is
that _maintaining_ proofs written in this style can be difficult.
For example, suppose that, later, we extended the definition of
[aexp] with another constructor that also required a special
argument. The above proof might break because Coq generated the
subgoals for this constructor before the one for [APlus], so that,
at the point when we start working on the [APlus] case, Coq is
actually expecting the argument for a completely different
constructor. What we'd like is to get a sensible error message
saying "I was expecting the [AFoo] case at this point, but the
proof script is talking about [APlus]." Here's a nice trick (due
to Aaron Bohannon) that smoothly achieves this. *)
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** ([Case_aux] implements the common functionality of [Case],
[SCase], [SSCase], etc. For example, [Case "foo"] is defined as
[Case_aux Case "foo".) *)
(** For example, if [a] is a variable of type [aexp], then doing
aexp_cases (induction a) Case
will perform an induction on [a] (the same as if we had just typed
[induction a]) and _also_ add a [Case] tag to each subgoal
generated by the [induction], labeling which constructor it comes
from. For example, here is yet another proof of
[optimize_0plus_sound], using [aexp_cases]: *)
Theorem optimize_0plus_sound''': forall a,
aeval (optimize_0plus a) = aeval a.
Proof.
intros a.
aexp_cases (induction a) Case;
try (simpl; rewrite IHa1; rewrite IHa2; reflexivity);
try reflexivity.
(* At this point, there is already an ["APlus"] case name
in the context. The [Case "APlus"] here in the proof
text has the effect of a sanity check: if the "Case"
string in the context is anything _other_ than ["APlus"]
(for example, because we added a clause to the definition
of [aexp] and forgot to change the proof) we'll get a
helpful error at this point telling us that this is now
the wrong case. *)
Case "APlus".
aexp_cases (destruct a1) SCase;
try (simpl; simpl in IHa1;
rewrite IHa1; rewrite IHa2; reflexivity).
SCase "ANum". destruct n;
simpl; rewrite IHa2; reflexivity. Qed.
(** **** Exercise: 3 stars (optimize_0plus_b) *)
(** Since the [optimize_0plus] tranformation doesn't change the value
of [aexp]s, we should be able to apply it to all the [aexp]s that
appear in a [bexp] without changing the [bexp]'s value. Write a
function which performs that transformation on [bexp]s, and prove
it is sound. Use the tacticals we've just seen to make the proof
as elegant as possible. *)
Fixpoint optimize_0plus_b (b : bexp) : bexp :=
match b with
| BEq a b => BEq (optimize_0plus a) (optimize_0plus b)
| BLe a b => BLe (optimize_0plus a) (optimize_0plus b)
| BNot b => BNot (optimize_0plus_b b)
| BAnd a b => BAnd (optimize_0plus_b a) (optimize_0plus_b b)
| b => b
end.
Theorem optimize_0plus_b_sound : forall b,
beval (optimize_0plus_b b) = beval b.
Proof. induction b; crush. Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (optimizer) *)
(** _Design exercise_: The optimization implemented by our
[optimize_0plus] function is only one of many imaginable
optimizations on arithmetic and boolean expressions. Write a more
sophisticated optimizer and prove it correct.
*)
Theorem le_proc : forall n m, {n <= m} + {m <= n}.
Proof. induction n; destruct m; crush. destruct (IHn m); crush. Defined.
Theorem eq_nat_proc : forall n m : nat, {n = m} + {n <> m}.
Proof. induction n; destruct m; crush. destruct (IHn m); crush. Defined.
Fixpoint optimize_precompute_le (b : bexp) : bexp :=
match b with
| BLe a a0 => match ble_nat (aeval a) (aeval a0) with
| true => BTrue
| false => BFalse
end
| BNot b' => BNot (optimize_precompute_le b')
| BAnd b0_1 b0_2 => BAnd (optimize_precompute_le b0_1) (optimize_precompute_le b0_2)
| _ => b
end.
Lemma ble_nat_Sn_m : forall n m, ble_nat (S n) m = true -> ble_nat n m = true.
Proof. induction n; destruct m; crush. Qed.
Hint Resolve ble_nat_Sn_m.
Lemma ble_nat_n_Sm : forall n m, ble_nat n m = true -> ble_nat n (S m) = true.
induction n; crush. Qed.
Hint Resolve ble_nat_n_Sm.
Hint Rewrite ble_nat_refl.
Theorem true_ble_nat : forall a b, a <= b -> ble_nat a b = true.
induction 1; crush. Qed.
Hint Resolve true_ble_nat.
Theorem ble_nat_true : forall a b, ble_nat a b = true -> a <= b.
induction a; destruct b; crush. Qed.
Hint Resolve ble_nat_true.
Theorem eq_nat_proc_refl : forall n, exists p, eq_nat_proc n n = left p.
Proof. intros; destruct (eq_nat_proc n n) as [H|H]; destruct H; eauto. Qed.
Hint Rewrite eq_nat_proc_refl.
Lemma n_neq_Sn : forall n, n <> S n.
induction n; crush. Qed.
Lemma Sn_nle_n : forall n, ~ (S n <= n).
induction n; crush. Qed.
Lemma n_le_m_neq_Sm : forall n m, n <= m -> n <> S m.
induction n; crush. Qed.
Theorem optimize_precompute_le_sound : forall b,
beval b = beval (optimize_precompute_le b).
Proof. induction b; crush.
- Case "ble_nat a a0". destruct (ble_nat (aeval a) (aeval a0)); crush.
Qed.
(** [] *)
(* ####################################################### *)
(** ** The [omega] Tactic *)
(** The [omega] tactic implements a decision procedure for a subset of
first-order logic called _Presburger arithmetic_. It is based on
the Omega algorithm invented in 1992 by William Pugh.
If the goal is a universally quantified formula made out of
- numeric constants, addition ([+] and [S]), subtraction ([-]
and [pred]), and multiplication by constants (this is what
makes it Presburger arithmetic),
- equality ([=] and [<>]) and inequality ([<=]), and
- the logical connectives [/\], [\/], [~], and [->],
then invoking [omega] will either solve the goal or tell you that
it is actually false. *)
Example silly_presburger_example : forall m n o p,
m + n <= n + o /\ o + 3 = p + 3 ->
m <= p.
Proof.
intros. omega.
Qed.
(** Liebniz wrote, "It is unworthy of excellent men to lose
hours like slaves in the labor of calculation which could be
relegated to anyone else if machines were used." We recommend
using the omega tactic whenever possible. *)
(* ####################################################### *)
(** ** A Few More Handy Tactics *)
(** Finally, here are some miscellaneous tactics that you may find
convenient.
- [clear H]: Delete hypothesis [H] from the context.
- [subst x]: Find an assumption [x = e] or [e = x] in the
context, replace [x] with [e] throughout the context and
current goal, and clear the assumption.
- [subst]: Substitute away _all_ assumptions of the form [x = e]
or [e = x].
- [rename... into...]: Change the name of a hypothesis in the
proof context. For example, if the context includes a variable
named [x], then [rename x into y] will change all occurrences
of [x] to [y].
- [assumption]: Try to find a hypothesis [H] in the context that
exactly matches the goal; if one is found, behave just like
[apply H].
- [contradiction]: Try to find a hypothesis [H] in the current
context that is logically equivalent to [False]. If one is
found, solve the goal.
- [constructor]: Try to find a constructor [c] (from some
[Inductive] definition in the current environment) that can be
applied to solve the current goal. If one is found, behave
like [apply c]. *)
(** We'll see many examples of these in the proofs below. *)
(* ####################################################### *)
(** * Evaluation as a Relation *)
(** We have presented [aeval] and [beval] as functions defined by
[Fixpoints]. Another way to think about evaluation -- one that we
will see is often more flexible -- is as a _relation_ between
expressions and their values. This leads naturally to [Inductive]
definitions like the following one for arithmetic
expressions... *)
Module aevalR_first_try.
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n: nat),
aevalR (ANum n) n
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
| E_AMinus: forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMinus e1 e2) (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (AMult e1 e2) (n1 * n2).
(** As is often the case with relations, we'll find it
convenient to define infix notation for [aevalR]. We'll write [e
|| n] to mean that arithmetic expression [e] evaluates to value
[n]. (This notation is one place where the limitation to ASCII
symbols becomes a little bothersome. The standard notation for
the evaluation relation is a double down-arrow. We'll typeset it
like this in the HTML version of the notes and use a double
vertical bar as the closest approximation in [.v] files.) *)
Notation "e '||' n" := (aevalR e n) : type_scope.
End aevalR_first_try.
(** In fact, Coq provides a way to use this notation in the definition
of [aevalR] itself. This avoids situations where we're working on
a proof involving statements in the form [e || n] but we have to
refer back to a definition written using the form [aevalR e n].
We do this by first "reserving" the notation, then giving the
definition together with a declaration of what the notation
means. *)
Reserved Notation "e '||' n" (at level 50, left associativity).
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (APlus e1 e2) || (n1 + n2)
| E_AMinus : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMinus e1 e2) || (n1 - n2)
| E_AMult : forall (e1 e2: aexp) (n1 n2 : nat),
(e1 || n1) -> (e2 || n2) -> (AMult e1 e2) || (n1 * n2)
where "e '||' n" := (aevalR e n) : type_scope.
Hint Constructors aevalR.
Tactic Notation "aevalR_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_ANum" | Case_aux c "E_APlus"
| Case_aux c "E_AMinus" | Case_aux c "E_AMult" ].
(* ####################################################### *)
(** ** Inference Rule Notation *)
(** In informal discussions, it is convenient write the rules for
[aevalR] and similar relations in the more readable graphical form
of _inference rules_, where the premises above the line justify
the conclusion below the line (we have already seen them in the
Prop chapter). *)
(** For example, the constructor [E_APlus]...
| E_APlus : forall (e1 e2: aexp) (n1 n2: nat),
aevalR e1 n1 ->
aevalR e2 n2 ->
aevalR (APlus e1 e2) (n1 + n2)
...would be written like this as an inference rule:
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
*)
(** Formally, there is nothing very deep about inference rules:
they are just implications. You can read the rule name on the
right as the name of the constructor and read each of the
linebreaks between the premises above the line and the line itself
as [->]. All the variables mentioned in the rule ([e1], [n1],
etc.) are implicitly bound by universal quantifiers at the
beginning. (Such variables are often called _metavariables_ to
distinguish them from the variables of the language we are
defining. At the moment, our arithmetic expressions don't include
variables, but we'll soon be adding them.) The whole collection
of rules is understood as being wrapped in an [Inductive]
declaration (informally, this is either elided or else indicated
by saying something like "Let [aevalR] be the smallest relation
closed under the following rules..."). *)
(** For example, [||] is the smallest relation closed under these
rules:
----------- (E_ANum)
ANum n || n
e1 || n1
e2 || n2
-------------------- (E_APlus)
APlus e1 e2 || n1+n2
e1 || n1
e2 || n2
--------------------- (E_AMinus)
AMinus e1 e2 || n1-n2
e1 || n1
e2 || n2
-------------------- (E_AMult)
AMult e1 e2 || n1*n2
*)
(* ####################################################### *)
(** ** Equivalence of the Definitions *)
(** It is straightforward to prove that the relational and functional
definitions of evaluation agree on all possible arithmetic
expressions... *)
Theorem aeval_iff_aevalR : forall a n,
(a || n) <-> aeval a = n.
Proof. split.
- induction 1; crush.
- generalize dependent n; aexp_cases (induction a) Case; crush.
Qed.
Hint Rewrite aeval_iff_aevalR.
(** Note: if you're reading the HTML file, you'll see an empty square box instead
of a proof for this theorem.
You can click on this box to "unfold" the text to see the proof.
Click on the unfolded to text to "fold" it back up to a box. We'll be using
this style frequently from now on to help keep the HTML easier to read.
The full proofs always appear in the .v files. *)
(** We can make the proof quite a bit shorter by making more
use of tacticals... *)
Theorem aeval_iff_aevalR' : forall a n,
(a || n) <-> aeval a = n.
Proof. split.
Case "->". intros H; induction H; subst; reflexivity.
Case "<-". generalize dependent n.
induction a; simpl; intros; subst; constructor;
try apply IHa1; try apply IHa2; reflexivity.
Qed.
(** **** Exercise: 3 stars (bevalR) *)
(** Write a relation [bevalR] in the same style as
[aevalR], and prove that it is equivalent to [beval].*)
Reserved Notation "e '//' n" (at level 40, left associativity).
Inductive bevalR : bexp -> bool -> Prop :=
| E_BTrue : BTrue // true
| E_BFalse : BFalse // false
| E_BEq : forall (a b : aexp) (n m : nat),
a || n -> b || m -> BEq a b // beq_nat n m
| E_BLe : forall (a b : aexp) (n m : nat),
a || n -> b || m -> BLe a b // ble_nat n m
| E_BNot : forall (be : bexp) (b : bool), be // b -> BNot be // negb b
| E_Band : forall (be1 be2 : bexp) (b1 b2 : bool),
be1 // b1 -> be2 // b2 -> BAnd be1 be2 // andb b1 b2
where "a '//' b" := (bevalR a b) : type_scope.
Hint Constructors bevalR.
Theorem bevalR_iff : forall be b, be // b <-> beval be = b.
Proof. split; intros.
- induction H; crush.
- generalize dependent b; induction be; crush.
+ apply E_BEq; crush.
+ apply E_BLe; crush.
Qed.
(** [] *)
End AExp.
(* ####################################################### *)
(** ** Computational vs. Relational Definitions *)
(** For the definitions of evaluation for arithmetic and boolean
expressions, the choice of whether to use functional or relational
definitions is mainly a matter of taste. In general, Coq has
somewhat better support for working with relations. On the other
hand, in some sense function definitions carry more information,
because functions are necessarily deterministic and defined on all
arguments; for a relation we have to show these properties
explicitly if we need them. Functions also take advantage of Coq's
computations mechanism.
However, there are circumstances where relational definitions of
evaluation are preferable to functional ones. *)
Module aevalR_division.
(** For example, suppose that we wanted to extend the arithmetic
operations by considering also a division operation:*)
Inductive aexp : Type :=
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp
| ADiv : aexp -> aexp -> aexp. (* <--- new *)
(** Extending the definition of [aeval] to handle this new operation
would not be straightforward (what should we return as the result
of [ADiv (ANum 5) (ANum 0)]?). But extending [aevalR] is
straightforward. *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
| E_ADiv : forall (a1 a2: aexp) (n1 n2 n3: nat),
(a1 || n1) -> (a2 || n2) -> (mult n2 n3 = n1) -> (ADiv a1 a2) || n3
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_division.
Module aevalR_extended.
(** *** Adding nondeterminism *)
(* /TERSE *)
(** Suppose, instead, that we want to extend the arithmetic operations
by a nondeterministic number generator [any]:*)
Inductive aexp : Type :=
| AAny : aexp (* <--- NEW *)
| ANum : nat -> aexp
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
(** Again, extending [aeval] would be tricky (because evaluation is
_not_ a deterministic function from expressions to numbers), but
extending [aevalR] is no problem: *)
Inductive aevalR : aexp -> nat -> Prop :=
| E_Any : forall (n:nat),
AAny || n (* <--- new *)
| E_ANum : forall (n:nat),
(ANum n) || n
| E_APlus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (APlus a1 a2) || (n1 + n2)
| E_AMinus : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMinus a1 a2) || (n1 - n2)
| E_AMult : forall (a1 a2: aexp) (n1 n2 : nat),
(a1 || n1) -> (a2 || n2) -> (AMult a1 a2) || (n1 * n2)
where "a '||' n" := (aevalR a n) : type_scope.
End aevalR_extended.
(** * Expressions With Variables *)
(** Let's turn our attention back to defining Imp. The next thing we
need to do is to enrich our arithmetic and boolean expressions
with variables. To keep things simple, we'll assume that all
variables are global and that they only hold numbers. *)
(* ##################################################### *)
(** ** Identifiers *)
(** To begin, we'll need to formalize _identifiers_ such as program
variables. We could use strings for this -- or, in a real
compiler, fancier structures like pointers into a symbol table.
But for simplicity let's just use natural numbers as identifiers. *)
(** (We hide this section in a module because these definitions are
actually in [SfLib], but we want to repeat them here so that we
can explain them.) *)
Module Id.
(** We define a new inductive datatype [Id] so that we won't confuse
identifiers and numbers. We use [sumbool] to define a computable
equality operator on [Id]. *)
Inductive id : Type :=
Id : nat -> id.
Theorem eq_id_dec : forall id1 id2 : id, {id1 = id2} + {id1 <> id2}.
Proof. intros; destruct id1, id2.
destruct (eq_nat_dec n n0); [left | right]; crush.
Defined.
(** The following lemmas will be useful for rewriting terms involving [eq_id_dec]. *)
Lemma eq_id : forall (T:Type) x (p q:T),
(if eq_id_dec x x then p else q) = p.
Proof. intros; destruct (eq_id_dec x x); crush. Qed.
(** **** Exercise: 1 star, optional (neq_id) *)
Lemma neq_id : forall (T:Type) x y (p q:T), x <> y ->
(if eq_id_dec x y then p else q) = q.
Proof. intros; destruct (eq_id_dec x y); crush. Qed.
Hint Rewrite eq_id neq_id.
(** [] *)
End Id.
(* ####################################################### *)
(** ** States *)
(** A _state_ represents the current values of _all_ the variables at
some point in the execution of a program. *)
(** For simplicity (to avoid dealing with partial functions), we
let the state be defined for _all_ variables, even though any
given program is only going to mention a finite number of them.
The state captures all of the information stored in memory. For Imp
programs, because each variable stores only a natural number, we
can represent the state as a mapping from identifiers to [nat].
For more complex programming languages, the state might have more
structure.
*)
Definition state := id -> nat.
Definition empty_state : state :=
fun _ => 0.
Definition update (st : state) (x : id) (n : nat) : state :=
fun x' => if eq_id_dec x x' then n else st x'.
(** For proofs involving states, we'll need several simple properties
of [update]. *)
(** **** Exercise: 1 star (update_eq) *)
Theorem update_eq : forall n x st,
(update st x n) x = n.
Proof. intros; unfold update; rewrite eq_id; crush. Qed.
Hint Rewrite update_eq.
(** [] *)
(** **** Exercise: 1 star (update_neq) *)
Theorem update_neq : forall x2 x1 n st,
x2 <> x1 ->
(update st x2 n) x1 = (st x1).
Proof. unfold update; intros; rewrite neq_id; crush. Qed.
Hint Rewrite update_neq.
(** [] *)
(** **** Exercise: 1 star (update_example) *)
(** Before starting to play with tactics, make sure you understand
exactly what the theorem is saying! *)
Theorem update_example : forall (n:nat),
(update empty_state (Id 2) n) (Id 3) = 0.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (update_shadow) *)
Theorem update_shadow : forall n1 n2 x1 x2 (st : state),
(update (update st x2 n1) x2 n2) x1 = (update st x2 n2) x1.
Proof. intros; unfold update; destruct (eq_id_dec x2 x1); reflexivity. Qed.
(** [] *)
Hint Rewrite update_shadow.
(** **** Exercise: 2 stars (update_same) *)
Theorem update_same : forall n1 x1 x2 (st : state),
st x1 = n1 ->
(update st x1 n1) x2 = st x2.
Proof. intros; unfold update; destruct (eq_id_dec x1 x2); crush. Qed.
Hint Rewrite update_same.
(** [] *)
(** **** Exercise: 3 stars (update_permute) *)
Theorem update_permute : forall n1 n2 x1 x2 x3 st,
x2 <> x1 ->
(update (update st x2 n1) x1 n2) x3 = (update (update st x1 n2) x2 n1) x3.
Proof. intros; unfold update.
destruct (eq_id_dec x1 x3), (eq_id_dec x2 x3); crush.
Qed.
(** [] *)
(* ################################################### *)
(** ** Syntax *)
(** We can add variables to the arithmetic expressions we had before by
simply adding one more constructor: *)
Inductive aexp : Type :=
| ANum : nat -> aexp
| AId : id -> aexp (* <----- NEW *)
| APlus : aexp -> aexp -> aexp
| AMinus : aexp -> aexp -> aexp
| AMult : aexp -> aexp -> aexp.
Tactic Notation "aexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ANum" | Case_aux c "AId" | Case_aux c "APlus"
| Case_aux c "AMinus" | Case_aux c "AMult" ].
(** Defining a few variable names as notational shorthands will make
examples easier to read: *)
Definition X : id := Id 0.
Definition Y : id := Id 1.
Definition Z : id := Id 2.
(** (This convention for naming program variables ([X], [Y],
[Z]) clashes a bit with our earlier use of uppercase letters for
types. Since we're not using polymorphism heavily in this part of
the course, this overloading should not cause confusion.) *)
(** The definition of [bexp]s is the same as before (using the new
[aexp]s): *)
Inductive bexp : Type :=
| BTrue : bexp
| BFalse : bexp
| BEq : aexp -> aexp -> bexp
| BLe : aexp -> aexp -> bexp
| BNot : bexp -> bexp
| BAnd : bexp -> bexp -> bexp.
Tactic Notation "bexp_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "BTrue" | Case_aux c "BFalse" | Case_aux c "BEq"
| Case_aux c "BLe" | Case_aux c "BNot" | Case_aux c "BAnd" ].
(* ################################################### *)
(** ** Evaluation *)
(** The arith and boolean evaluators can be extended to handle
variables in the obvious way: *)
Fixpoint aeval (st : state) (a : aexp) : nat :=
match a with
| ANum n => n
| AId x => st x (* <----- NEW *)
| APlus a1 a2 => (aeval st a1) + (aeval st a2)
| AMinus a1 a2 => (aeval st a1) - (aeval st a2)
| AMult a1 a2 => (aeval st a1) * (aeval st a2)
end.
Fixpoint beval (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b1 => negb (beval st b1)
| BAnd b1 b2 => andb (beval st b1) (beval st b2)
end.
Example aexp1 :
aeval (update empty_state X 5)
(APlus (ANum 3) (AMult (AId X) (ANum 2)))
= 13.
Proof. reflexivity. Qed.
Example bexp1 :
beval (update empty_state X 5)
(BAnd BTrue (BNot (BLe (AId X) (ANum 4))))
= true.
Proof. reflexivity. Qed.
(* ####################################################### *)
(** * Commands *)
(** Now we are ready define the syntax and behavior of Imp
_commands_ (often called _statements_). *)
(* ################################################### *)
(** ** Syntax *)
(** Informally, commands [c] are described by the following BNF
grammar:
c ::= SKIP
| x ::= a
| c ;; c
| WHILE b DO c END
| IFB b THEN c ELSE c FI
END
]]
*)
(**
For example, here's the factorial function in Imp.
Z ::= X;;
Y ::= 1;;
WHILE not (Z = 0) DO
Y ::= Y * Z;;
Z ::= Z - 1
END
When this command terminates, the variable [Y] will contain the
factorial of the initial value of [X].
*)
(** Here is the formal definition of the syntax of commands: *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";;"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
(** As usual, we can use a few [Notation] declarations to make things
more readable. We need to be a bit careful to avoid conflicts
with Coq's built-in notations, so we'll keep this light -- in
particular, we won't introduce any notations for [aexps] and
[bexps] to avoid confusion with the numerical and boolean
operators we've already defined. We use the keyword [IFB] for
conditionals instead of [IF], for similar reasons. *)
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** For example, here is the factorial function again, written as a
formal definition to Coq: *)
Definition fact_in_coq : com :=
Z ::= AId X;;
Y ::= ANum 1;;
WHILE BNot (BEq (AId Z) (ANum 0)) DO
Y ::= AMult (AId Y) (AId Z);;
Z ::= AMinus (AId Z) (ANum 1)
END.
(* ####################################################### *)
(** ** Examples *)
(** Assignment: *)
Definition plus2 : com :=
X ::= (APlus (AId X) (ANum 2)).
Definition XtimesYinZ : com :=
Z ::= (AMult (AId X) (AId Y)).
Definition subtract_slowly_body : com :=
Z ::= AMinus (AId Z) (ANum 1) ;;
X ::= AMinus (AId X) (ANum 1).
(** *** Loops *)
Definition subtract_slowly : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
subtract_slowly_body
END.
Definition subtract_3_from_5_slowly : com :=
X ::= ANum 3 ;;
Z ::= ANum 5 ;;
subtract_slowly.
(** *** An infinite loop: *)
Definition loop : com :=
WHILE BTrue DO
SKIP
END.
(* ################################################################ *)
(** * Evaluation *)
(** Next we need to define what it means to evaluate an Imp command.
The fact that [WHILE] loops don't necessarily terminate makes defining
an evaluation function tricky... *)
(* #################################### *)
(** ** Evaluation as a Function (Failed Attempt) *)
(** Here's an attempt at defining an evaluation function for commands,
omitting the [WHILE] case. *)
Fixpoint ceval_fun_no_while (st : state) (c : com) : state :=
match c with
| SKIP =>
st
| x ::= a1 =>
update st x (aeval st a1)
| c1 ;; c2 =>
let st' := ceval_fun_no_while st c1 in
ceval_fun_no_while st' c2
| IFB b THEN c1 ELSE c2 FI =>
if (beval st b)
then ceval_fun_no_while st c1
else ceval_fun_no_while st c2
| WHILE b DO c END =>
st (* bogus *)
end.
(** In a traditional functional programming language like ML or
Haskell we could write the [WHILE] case as follows:
<<
Fixpoint ceval_fun (st : state) (c : com) : state :=
match c with
...
| WHILE b DO c END =>
if (beval st b1)
then ceval_fun st (c1; WHILE b DO c END)
else st
end.
>>
Coq doesn't accept such a definition ("Error: Cannot guess
decreasing argument of fix") because the function we want to
define is not guaranteed to terminate. Indeed, it doesn't always
terminate: for example, the full version of the [ceval_fun]
function applied to the [loop] program above would never
terminate. Since Coq is not just a functional programming
language, but also a consistent logic, any potentially
non-terminating function needs to be rejected. Here is
an (invalid!) Coq program showing what would go wrong if Coq
allowed non-terminating recursive functions:
<<
Fixpoint loop_false (n : nat) : False := loop_false n.
>>
That is, propositions like [False] would become provable
(e.g. [loop_false 0] would be a proof of [False]), which
would be a disaster for Coq's logical consistency.
Thus, because it doesn't terminate on all inputs, the full version
of [ceval_fun] cannot be written in Coq -- at least not without
additional tricks (see chapter [ImpCEvalFun] if curious). *)
(* #################################### *)
(** ** Evaluation as a Relation *)
(** Here's a better way: we define [ceval] as a _relation_ rather than
a _function_ -- i.e., we define it in [Prop] instead of [Type], as
we did for [aevalR] above. *)
(** This is an important change. Besides freeing us from the awkward
workarounds that would be needed to define evaluation as a
function, it gives us a lot more flexibility in the definition.
For example, if we added concurrency features to the language,
we'd want the definition of evaluation to be non-deterministic --
i.e., not only would it not be total, it would not even be a
partial function! *)
(** We'll use the notation [c / st || st'] for our [ceval] relation:
[c / st || st'] means that executing program [c] in a starting
state [st] results in an ending state [st']. This can be
pronounced "[c] takes state [st] to [st']".
*)
(** *** Operational Semantics
---------------- (E_Skip)
SKIP / st || st
aeval st a1 = n
-------------------------------- (E_Ass)
x := a1 / st || (update st x n)
c1 / st || st'
c2 / st' || st''
------------------- (E_Seq)
c1;;c2 / st || st''
beval st b1 = true
c1 / st || st'
------------------------------------- (E_IfTrue)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
c2 / st || st'
------------------------------------- (E_IfFalse)
IF b1 THEN c1 ELSE c2 FI / st || st'
beval st b1 = false
------------------------------ (E_WhileEnd)
WHILE b DO c END / st || st
beval st b1 = true
c / st || st'
WHILE b DO c END / st' || st''
--------------------------------- (E_WhileLoop)
WHILE b DO c END / st || st''
*)
(** Here is the formal definition. (Make sure you understand
how it corresponds to the inference rules.) *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st,
SKIP / st || st
| E_Ass : forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st || (update st x n)
| E_Seq : forall c1 c2 st st' st'',
c1 / st || st' ->
c2 / st' || st'' ->
(c1 ;; c2) / st || st''
| E_IfTrue : forall st st' b c1 c2,
beval st b = true ->
c1 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall st st' b c1 c2,
beval st b = false ->
c2 / st || st' ->
(IFB b THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall b st c,
beval st b = false ->
(WHILE b DO c END) / st || st
| E_WhileLoop : forall st st' st'' b c,
beval st b = true ->
c / st || st' ->
(WHILE b DO c END) / st' || st'' ->
(WHILE b DO c END) / st || st''
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop" ].
Hint Constructors ceval.
(** *** *)
(** The cost of defining evaluation as a relation instead of a
function is that we now need to construct _proofs_ that some
program evaluates to some result state, rather than just letting
Coq's computation mechanism do it for us. *)
Example ceval_example1:
(X ::= ANum 2;;
IFB BLe (AId X) (ANum 1)
THEN Y ::= ANum 3
ELSE Z ::= ANum 4
FI)
/ empty_state
|| (update (update empty_state X 2) Z 4).
Proof.
(* We must supply the intermediate state *)
apply E_Seq with (update empty_state X 2).
Case "assignment command".
apply E_Ass. reflexivity.
Case "if command".
apply E_IfFalse.
reflexivity.
apply E_Ass. reflexivity. Qed.
(** **** Exercise: 2 stars (ceval_example2) *)
Example ceval_example2:
(X ::= ANum 0;; Y ::= ANum 1;; Z ::= ANum 2) / empty_state ||
(update (update (update empty_state X 0) Y 1) Z 2).
Proof. eauto 10. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (pup_to_n) *)
(** Write an Imp program that sums the numbers from [1] to
[X] (inclusive: [1 + 2 + ... + X]) in the variable [Y].
Prove that this program executes as intended for X = 2
(this latter part is trickier than you might expect). *)
Definition pup_to_n : com :=
(Y ::= ANum 0;;
WHILE BNot (BEq (AId X) (ANum 0))
DO Y ::= APlus (AId X) (AId Y);; X ::= AMinus (AId X) (ANum 1)
END).
Theorem pup_to_2_ceval :
pup_to_n / (update empty_state X 2) ||
update (update (update (update (update (update empty_state
X 2) Y 0) Y 2) X 1) Y 3) X 0.
Proof. apply E_Seq with (update (update empty_state X 2) Y 0).
constructor. reflexivity.
eapply E_WhileLoop. reflexivity.
eapply E_Seq. eapply E_Ass. reflexivity.
eapply E_Ass. reflexivity.
eapply E_WhileLoop. reflexivity.
eapply E_Seq. eapply E_Ass. reflexivity.
eapply E_Ass. reflexivity.
simpl.
eapply E_WhileEnd. reflexivity.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Determinism of Evaluation *)
(** Changing from a computational to a relational definition of
evaluation is a good move because it allows us to escape from the
artificial requirement (imposed by Coq's restrictions on
[Fixpoint] definitions) that evaluation should be a total
function. But it also raises a question: Is the second definition
of evaluation actually a partial function? That is, is it
possible that, beginning from the same state [st], we could
evaluate some command [c] in different ways to reach two different
output states [st'] and [st'']?
In fact, this cannot happen: [ceval] is a partial function.
Here's the proof: *)
Theorem ceval_deterministic: forall c st st1 st2,
c / st || st1 ->
c / st || st2 ->
st1 = st2.
Proof. introv E1 E2; generalize dependent st2.
ceval_cases (induction E1) Case; intros; inverts E2; crush.
- Case "E_Seq". apply IHE1_1 in H1; crush.
- Case "E_WhileLoop". apply IHE1_1 in H3; crush.
Qed.
Hint Rewrite ceval_deterministic.
(* ####################################################### *)
(** * Reasoning About Imp Programs *)
(** We'll get much deeper into systematic techniques for reasoning
about Imp programs in the following chapters, but we can do quite
a bit just working with the bare definitions. *)
(* This section explores some examples. *)
Theorem plus2_spec : forall st n st',
st X = n ->
plus2 / st || st' ->
st' X = n + 2.
Proof.
intros st n st' HX. intro Heval.
(* Inverting Heval essentially forces Coq to expand one
step of the ceval computation - in this case revealing
that st' must be st extended with the new value of X,
since plus2 is an assignment *)
inversion Heval. subst. clear Heval. simpl.
apply update_eq. Qed.
(** **** Exercise: 3 stars (XtimesYinZ_spec) *)
(** State and prove a specification of [XtimesYinZ]. *)
(* What ix XtimesYinZ? What operation is that supposed to be? *)
(** [] *)
(** **** Exercise: 3 stars (loop_never_stops) *)
Theorem loop_never_stops : forall st st',
~(loop / st || st').
Proof. remember loop; induction 1; inverts Heqc; crush. Qed.
(** [] *)
(** **** Exercise: 3 stars (no_whilesR) *)
(** Consider the definition of the [no_whiles] property below: *)
Fixpoint no_whiles (c : com) : bool :=
match c with
| SKIP => true
| _ ::= _ => true
| c1 ;; c2 => andb (no_whiles c1) (no_whiles c2)
| IFB _ THEN ct ELSE cf FI => andb (no_whiles ct) (no_whiles cf)
| WHILE _ DO _ END => false
end.
(** This property yields [true] just on programs that
have no while loops. Using [Inductive], write a property
[no_whilesR] such that [no_whilesR c] is provable exactly when [c]
is a program with no while loops. Then prove its equivalence
with [no_whiles]. *)
Inductive no_whilesR: com -> Prop :=
| NW_S : no_whilesR SKIP
| NW_A : forall x y, no_whilesR (x ::= y)
| NW_Seq : forall c1 c2,
no_whilesR c1 -> no_whilesR c2 -> no_whilesR (c1 ;; c2)
| NW_If : forall c1 c2 c3,
no_whilesR c2 -> no_whilesR c3 -> no_whilesR (IFB c1 THEN c2 ELSE c3 FI).
Hint Constructors no_whilesR.
Theorem no_whiles_eqv:
forall c, no_whiles c = true <-> no_whilesR c.
Proof. split.
- induction c; crush; destruct (no_whiles c1), (no_whiles c2); crush.
- induction 1; crush.
Qed.
(** [] *)
(** **** Exercise: 4 stars (no_whiles_terminating) *)
(** Imp programs that don't involve while loops always terminate.
State and prove a theorem that says this. *)
(** (Use either [no_whiles] or [no_whilesR], as you prefer.) *)
Theorem no_whiles_terminates :
forall c st, no_whilesR c -> exists st', c / st || st'.
Proof. intros. generalize dependent st. induction H as [|i a| |]; crush;
try (eapply ex_intro; eauto; crush; fail).
- Case "c1 ;; c2".
destruct (IHno_whilesR1 st) as [st']; destruct (IHno_whilesR2 st') as [st''].
exists st''; apply E_Seq with (st' := st'); crush.
- Case "IFB c1 THEN c2 ELSE c3 FI".
destruct (IHno_whilesR1 st) as [st1 H1];
destruct (IHno_whilesR2 st) as [st2 H2].
destruct (beval st c1) eqn:be; [exists st1 | exists st2]; crush.
Qed.
(** [] *)
(* ####################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (stack_compiler) *)
(** HP Calculators, programming languages like Forth and Postscript,
and abstract machines like the Java Virtual Machine all evaluate
arithmetic expressions using a stack. For instance, the expression
<<
(2*3)+(3*(4-2))
>>
would be entered as
<<
2 3 * 3 4 2 - * +
>>
and evaluated like this:
<<
[] | 2 3 * 3 4 2 - * +
[2] | 3 * 3 4 2 - * +
[3, 2] | * 3 4 2 - * +
[6] | 3 4 2 - * +
[3, 6] | 4 2 - * +
[4, 3, 6] | 2 - * +
[2, 4, 3, 6] | - * +
[2, 3, 6] | * +
[6, 6] | +
[12] |
>>
The task of this exercise is to write a small compiler that
translates [aexp]s into stack machine instructions.
The instruction set for our stack language will consist of the
following instructions:
- [SPush n]: Push the number [n] on the stack.
- [SLoad x]: Load the identifier [x] from the store and push it
on the stack
- [SPlus]: Pop the two top numbers from the stack, add them, and
push the result onto the stack.
- [SMinus]: Similar, but subtract.
- [SMult]: Similar, but multiply. *)
Inductive sinstr : Type :=
| SPush : nat -> sinstr
| SLoad : id -> sinstr
| SPlus : sinstr
| SMinus : sinstr
| SMult : sinstr.
(** Write a function to evaluate programs in the stack language. It
takes as input a state, a stack represented as a list of
numbers (top stack item is the head of the list), and a program
represented as a list of instructions, and returns the stack after
executing the program. Test your function on the examples below.
Note that the specification leaves unspecified what to do when
encountering an [SPlus], [SMinus], or [SMult] instruction if the
stack contains less than two elements. In a sense, it is
immaterial what we do, since our compiler will never emit such a
malformed program. *)
Definition s_step (st : state) (stack : list nat) (i : sinstr) : list nat :=
match i with
| SPush n => n :: stack
| SLoad i => st i :: stack
| SPlus => match stack with
| x :: y :: ss => y + x :: ss
| s => s
end
| SMinus => match stack with
| x :: y :: ss => y - x :: ss
| s => s
end
| SMult => match stack with
| x :: y :: ss => y * x :: ss
| s => s
end
end.
Definition s_execute (st : state) : list sinstr -> list nat -> list nat :=
fold_left (s_step st).
Example s_execute1 :
s_execute empty_state [SPush 5; SPush 3; SPush 1; SMinus] []
= [2; 5].
Proof. reflexivity. Qed.
Example s_execute2 :
s_execute (update empty_state X 3)
[SPush 4; SLoad X; SMult; SPlus] [3;4]
= [15; 4].
Proof. reflexivity. Qed.
(** Next, write a function which compiles an [aexp] into a stack
machine program. The effect of running the program should be the
same as pushing the value of the expression on the stack. *)
Fixpoint s_compile (e : aexp) : list sinstr :=
match e with
| ANum n => [SPush n]
| AId i => [SLoad i]
| APlus a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SPlus]
| AMinus a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SMinus]
| AMult a1 a2 => (s_compile a1) ++ (s_compile a2) ++ [SMult]
end.
(** After you've defined [s_compile], uncomment the following to test
that it works. *)
Example s_compile1 :
s_compile (AMinus (AId X) (AMult (ANum 2) (AId Y)))
= [SLoad X; SPush 2; SLoad Y; SMult; SMinus].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (stack_compiler_correct) *)
(** The task of this exercise is to prove the correctness of the
calculator implemented in the previous exercise. Remember that
the specification left unspecified what to do when encountering an
[SPlus], [SMinus], or [SMult] instruction if the stack contains
less than two elements. (In order to make your correctness proof
easier you may find it useful to go back and change your
implementation!)
Prove the following theorem, stating that the [compile] function
behaves correctly. You will need to start by stating a more
general lemma to get a usable induction hypothesis; the main
theorem will then be a simple corollary of this lemma. *)
Lemma s_compile_correct' :
forall (st : state) (e : aexp) (xs : list nat) (ss : list sinstr),
s_execute st (s_compile e ++ ss) xs = s_execute st ss (aeval st e :: xs).
Proof. induction e; crush. Qed.
Hint Rewrite s_compile_correct'.
Theorem s_compile_correct : forall (st : state) (e : aexp),
s_execute st (s_compile e) [] = [ aeval st e ].
Proof. induction e; crush. Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced (break_imp) *)
Module BreakImp.
(** Imperative languages such as C or Java often have a [break] or
similar statement for interrupting the execution of loops. In this
exercise we will consider how to add [break] to Imp.
First, we need to enrich the language of commands with an
additional case. *)
Inductive com : Type :=
| CSkip : com
| CBreak : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "BREAK" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" ].
Notation "'SKIP'" :=
CSkip.
Notation "'BREAK'" :=
CBreak.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
(** Next, we need to define the behavior of [BREAK]. Informally,
whenever [BREAK] is executed in a sequence of commands, it stops
the execution of that sequence and signals that the innermost
enclosing loop (if any) should terminate. If there aren't any
enclosing loops, then the whole program simply terminates. The
final state should be the same as the one in which the [BREAK]
statement was executed.
One important point is what to do when there are multiple loops
enclosing a given [BREAK]. In those cases, [BREAK] should only
terminate the _innermost_ loop where it occurs. Thus, after
executing the following piece of code...
X ::= 0;
Y ::= 1;
WHILE 0 <> Y DO
WHILE TRUE DO
BREAK
END;
X ::= 1;
Y ::= Y - 1
END
... the value of [X] should be [1], and not [0].
One way of expressing this behavior is to add another parameter to
the evaluation relation that specifies whether evaluation of a
command executes a [BREAK] statement: *)
Inductive status : Type :=
| SContinue : status
| SBreak : status.
Reserved Notation "c1 '/' st '||' s '/' st'"
(at level 40, st, s at level 39).
(** Intuitively, [c / st || s / st'] means that, if [c] is started in
state [st], then it terminates in state [st'] and either signals
that any surrounding loop (or the whole program) should exit
immediately ([s = SBreak]) or that execution should continue
normally ([s = SContinue]).
The definition of the "[c / st || s / st']" relation is very
similar to the one we gave above for the regular evaluation
relation ([c / st || s / st']) -- we just need to handle the
termination signals appropriately:
- If the command is [SKIP], then the state doesn't change, and
execution of any enclosing loop can continue normally.
- If the command is [BREAK], the state stays unchanged, but we
signal a [SBreak].
- If the command is an assignment, then we update the binding for
that variable in the state accordingly and signal that execution
can continue normally.
- If the command is of the form [IF b THEN c1 ELSE c2 FI], then
the state is updated as in the original semantics of Imp, except
that we also propagate the signal from the execution of
whichever branch was taken.
- If the command is a sequence [c1 ; c2], we first execute
[c1]. If this yields a [SBreak], we skip the execution of [c2]
and propagate the [SBreak] signal to the surrounding context;
the resulting state should be the same as the one obtained by
executing [c1] alone. Otherwise, we execute [c2] on the state
obtained after executing [c1], and propagate the signal that was
generated there.
- Finally, for a loop of the form [WHILE b DO c END], the
semantics is almost the same as before. The only difference is
that, when [b] evaluates to true, we execute [c] and check the
signal that it raises. If that signal is [SContinue], then the
execution proceeds as in the original semantics. Otherwise, we
stop the execution of the loop, and the resulting state is the
same as the one resulting from the execution of the current
iteration. In either case, since [BREAK] only terminates the
innermost loop, [WHILE] signals [SContinue]. *)
(** Based on the above description, complete the definition of the
[ceval] relation. *)
Inductive ceval : com -> state -> status -> state -> Prop :=
| E_Skip : forall st,
CSkip / st || SContinue / st
| E_Ass : forall st a1 n x,
aeval st a1 = n -> (x ::= a1) / st || SContinue / update st x n
| E_Brk : forall st, CBreak / st || SBreak / st
| E_SeqBrk : forall c1 c2 st st',
c1 / st || SBreak / st' ->
(c1 ; c2) / st || SBreak / st'
| E_Seq : forall c1 c2 st st' st'' s,
c1 / st || SContinue / st' ->
c2 / st' || s / st'' ->
(c1 ; c2) / st || s / st''
| E_IfTrue : forall st st' b c1 c2 s,
beval st b = true ->
c1 / st || s / st' ->
IFB b THEN c1 ELSE c2 FI / st || s / st'
| E_IfFalse : forall st st' b c1 c2 s,
beval st b = false ->
c2 / st || s / st' ->
IFB b THEN c1 ELSE c2 FI / st || s / st'
| E_WhileEnd : forall b st c,
beval st b = false -> WHILE b DO c END / st || SContinue / st
| E_WhileBrk : forall st st' b c,
beval st b = true ->
c / st || SBreak / st' ->
WHILE b DO c END / st || SContinue / st'
| E_WhileLoop : forall st st' st'' b c s,
beval st b = true ->
c / st || SContinue / st' ->
WHILE b DO c END / st' || s / st'' ->
WHILE b DO c END / st || SContinue / st''
where "c1 '/' st '||' s '/' st'" := (ceval c1 st s st').
Hint Constructors ceval.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" |
Case_aux c "E_Ass" |
Case_aux c "E_Brk" |
Case_aux c "E_SeqBrk" |
Case_aux c "E_Seq" |
Case_aux c "E_IfTrue" |
Case_aux c "E_IfFalse" |
Case_aux c "E_WhileEnd" |
Case_aux c "E_WhileBrk" |
Case_aux c "E_WhileLoop" ].
(** Now the following properties of your definition of [ceval]: *)
Theorem break_ignore : forall c st st' s,
(BREAK; c) / st || s / st' ->
st = st'.
Proof. introv H; repeat inverts H as H; crush. Qed.
Theorem while_continue : forall b c st st' s,
(WHILE b DO c END) / st || s / st' ->
s = SContinue.
Proof. intros; inversion H; reflexivity. Qed.
Theorem while_stops_on_break : forall b c st st',
beval st b = true ->
c / st || SBreak / st' ->
(WHILE b DO c END) / st || SContinue / st'.
Proof. crush. Qed.
Theorem while_skip_no_term : forall b st st',
beval st b = true ->
~ (WHILE b DO SKIP END / st || SContinue / st').
introv H contra. remember (WHILE b DO SKIP END) as loopdef eqn:whb;
ceval_cases (induction contra) Case; inverts whb;
try match goal with
| [ cont : SKIP / ?st || _ / ?st' |- _ ] => inverts cont
| [ cont : WHILE b DO SKIP END / _ || _ / _ |- _ ] => inverts cont
end; crush.
Qed.
Hint Immediate while_skip_no_term.
(** **** Exercise: 3 stars, advanced, optional (while_break_true) *)
Theorem while_break_true : forall b c st st',
(WHILE b DO c END) / st || SContinue / st' ->
exists st, c / st || SBreak / st' \/ beval st b = false.
introv Hc; remember (WHILE b DO c END) as loopdef eqn:whb.
ceval_cases (induction Hc) Case; crush; exists st; crush.
Qed.
(** **** Exercise: 4 stars, advanced, optional (ceval_deterministic) *)
Theorem ceval_deterministic: forall c st st1 st2 s1 s2,
c / st || s1 / st1 ->
c / st || s2 / st2 ->
st1 = st2 /\ s1 = s2.
introv E1 E2; generalize dependent st2; generalize dependent s2.
ceval_cases (induction E1) Case; intros; inverts E2;
repeat match goal with
| [ p1 : ?c / ?st || ?s1 / ?st1,
p2 : ?c / ?st || ?s2 / ?st2,
IH : forall s2 st2, ?c / ?st || s2 / st2 -> ?st1 = st2 /\ ?s1 = s2 |- _] =>
apply IH in p2
| _ => crush
end.
Qed.
End BreakImp.
(** [] *)
(** **** Exercise: 3 stars, optional (short_circuit) *)
(** Most modern programming languages use a "short-circuit" evaluation
rule for boolean [and]: to evaluate [BAnd b1 b2], first evaluate
[b1]. If it evaluates to [false], then the entire [BAnd]
expression evaluates to [false] immediately, without evaluating
[b2]. Otherwise, [b2] is evaluated to determine the result of the
[BAnd] expression.
Write an alternate version of [beval] that performs short-circuit
evaluation of [BAnd] in this manner, and prove that it is
equivalent to [beval]. *)
Fixpoint beval_short (st : state) (b : bexp) : bool :=
match b with
| BTrue => true
| BFalse => false
| BEq a1 a2 => beq_nat (aeval st a1) (aeval st a2)
| BLe a1 a2 => ble_nat (aeval st a1) (aeval st a2)
| BNot b => negb (beval_short st b)
| BAnd b1 b2 => if beval_short st b1 then beval_short st b2 else false
end.
Theorem beval_short_correct : forall st b, beval st b = beval_short st b.
induction b; crush. Qed.
(** [] *)
(** **** Exercise: 4 stars, optional (add_for_loop) *)
(** Add C-style [for] loops to the language of commands, update the
[ceval] definition to define the semantics of [for] loops, and add
cases for [for] loops as needed so that all the proofs in this file
are accepted by Coq.
A [for] loop should be parameterized by (a) a statement executed
initially, (b) a test that is run on each iteration of the loop to
determine whether the loop should continue, (c) a statement
executed at the end of each loop iteration, and (d) a statement
that makes up the body of the loop. (You don't need to worry
about making up a concrete Notation for [for] loops, but feel free
to play with this too if you like.) *)
(* FILL IN HERE *)
(** [] *)
(* <$Date: 2014-02-22 09:43:41 -0500 (Sat, 22 Feb 2014) $ *)
|
/*
Memory will halt the processor clock until the data has been obtained from the USB-EPP interface
*/
module memory(
input wire mclk,
input wire epp_astb,
input wire epp_dstb,
input wire epp_wr,
output wire epp_wait,
inout wire[7:0] epp_data,
output reg core_stall = 0,
input wire read,
input wire write,
input wire[31:0] address,
input wire[31:0] din,
output reg[31:0] dout = 0
);
parameter state_idle = 2'b00;
parameter state_read = 2'b01;
parameter state_write = 2'b10;
reg[1:0] state = state_idle;
reg[7:6] status = 0; // -> EPP
wire complete; // <- EPP
reg complete_clr = 0; // -> EPP
wire[31:0] dout_val; // <- EPP
memory_epp memory_epp_inst (
.mclk(mclk),
.epp_astb(epp_astb),
.epp_dstb(epp_dstb),
.epp_wr(epp_wr),
.epp_wait(epp_wait),
.epp_data(epp_data),
.status(status),
.address(address),
.dout(dout_val),
.din(din),
.complete(complete),
.complete_clr(complete_clr)
);
// Process
always @ (posedge mclk) begin
case(state)
state_read:
if(complete == 1) begin
dout <= dout_val;
core_stall <= 0;
complete_clr <= 1;
status <= 0;
state <= state_idle;
end
state_write:
if(complete == 1) begin
core_stall <= 0;
complete_clr <= 1;
status <= 0;
state <= state_idle;
end
default: begin
if(read == 1) begin
core_stall <= 1;
state <= state_read;
status <= 2'b10; // Status Flag = Read
end else if(write == 1) begin
core_stall <= 1;
state <= state_write;
status <= 2'b01; // Status Flag = Write
end
complete_clr <= 0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_PP_SYMBOL_V
/**
* lpflow_inputiso0n: Input isolator with inverted enable.
*
* X = (A & SLEEP_B)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputiso0n (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP_B,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO0N_PP_SYMBOL_V
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_32x32_dp_be.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_32x32_dp_be (
address_a,
address_b,
byteena_a,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [4:0] address_a;
input [4:0] address_b;
input [3:0] byteena_a;
input clock_a;
input clock_b;
input [31:0] data_a;
input [31:0] data_b;
input wren_a;
input wren_b;
output [31:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena_a;
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] sub_wire1;
wire [31:0] q_a = sub_wire0[31:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.byteena_a (byteena_a),
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
altsyncram_component.intended_device_family = "Arria II GX",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 32,
altsyncram_component.numwords_b = 32,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 5,
altsyncram_component.widthad_b = 5,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 4,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 5 0 INPUT NODEFVAL "address_a[4..0]"
// Retrieval info: USED_PORT: address_b 0 0 5 0 INPUT NODEFVAL "address_b[4..0]"
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 5 0 address_a 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 address_b 0 0 5 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_32x32_dp_be_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ps / 1 ps
module zynq_1_wrapper
(BRAM_PORTB_addr,
BRAM_PORTB_clk,
BRAM_PORTB_din,
BRAM_PORTB_dout,
BRAM_PORTB_we,
DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
fclk_out_25,
gpio,
spi_clk,
spi_out);
input [10:0]BRAM_PORTB_addr;
input BRAM_PORTB_clk;
input [7:0]BRAM_PORTB_din;
output [7:0]BRAM_PORTB_dout;
input [0:0]BRAM_PORTB_we;
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
output fclk_out_25;
output [31:0]gpio;
output spi_clk;
output spi_out;
wire [10:0]BRAM_PORTB_addr;
wire BRAM_PORTB_clk;
wire [7:0]BRAM_PORTB_din;
wire [7:0]BRAM_PORTB_dout;
wire [0:0]BRAM_PORTB_we;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire fclk_out_25;
wire [31:0]gpio;
wire spi_clk;
wire spi_out;
zynq_1 zynq_1_i
(.BRAM_PORTB_addr(BRAM_PORTB_addr),
.BRAM_PORTB_clk(BRAM_PORTB_clk),
.BRAM_PORTB_din(BRAM_PORTB_din),
.BRAM_PORTB_dout(BRAM_PORTB_dout),
.BRAM_PORTB_we(BRAM_PORTB_we),
.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.fclk_out_25(fclk_out_25),
.gpio(gpio),
.spi_clk(spi_clk),
.spi_out(spi_out));
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 16:52:26 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67, n68,
n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81, n82,
n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95, n96,
n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119,
n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n133, n134, n135, n136, n137, n138, n139, n140, n141,
n142, n143, n144, n145, n146, n147, n148, n149, n150, n151, n152,
n153, n154, n155, n156, n157, n158, n159, n160, n161, n162, n163,
n164, n165, n166, n167, n168, n169, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181;
NAND2X1TS U73 ( .A(n156), .B(n153), .Y(n96) );
XNOR2X2TS U74 ( .A(n61), .B(in2[15]), .Y(n98) );
NAND2X1TS U75 ( .A(n62), .B(n57), .Y(n63) );
CMPR32X2TS U76 ( .A(n104), .B(in1[6]), .C(n81), .CO(n159) );
NOR2X1TS U77 ( .A(n64), .B(n56), .Y(n65) );
NAND2X1TS U78 ( .A(n84), .B(in1[10]), .Y(n140) );
NAND2X1TS U79 ( .A(n73), .B(n57), .Y(n74) );
INVX2TS U80 ( .A(add_sub), .Y(n56) );
NOR2X6TS U81 ( .A(n77), .B(in2[6]), .Y(n75) );
INVX4TS U82 ( .A(in2[0]), .Y(n128) );
INVX2TS U83 ( .A(in2[3]), .Y(n58) );
INVX2TS U84 ( .A(n56), .Y(n57) );
NOR2X1TS U85 ( .A(n71), .B(n56), .Y(n72) );
OAI21XLTS U86 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n114) );
NAND2X1TS U87 ( .A(n176), .B(in1[2]), .Y(n175) );
NOR2XLTS U88 ( .A(n75), .B(n56), .Y(n76) );
INVX2TS U89 ( .A(n170), .Y(n172) );
XOR2X2TS U90 ( .A(n65), .B(in2[13]), .Y(n93) );
NAND2BX2TS U91 ( .AN(in2[13]), .B(n64), .Y(n62) );
NOR2X1TS U92 ( .A(n170), .B(n150), .Y(n100) );
INVX2TS U93 ( .A(n155), .Y(n94) );
NAND2X2TS U94 ( .A(n97), .B(in1[14]), .Y(n166) );
OR2X2TS U95 ( .A(n93), .B(in1[13]), .Y(n156) );
XNOR2X2TS U96 ( .A(n67), .B(in2[12]), .Y(n92) );
OR2X2TS U97 ( .A(n90), .B(in1[11]), .Y(n144) );
OAI21X2TS U98 ( .A0(n130), .A1(n162), .B0(n131), .Y(n136) );
XOR2X2TS U99 ( .A(n72), .B(in2[9]), .Y(n83) );
NAND2X2TS U100 ( .A(n82), .B(in1[8]), .Y(n162) );
NOR2X6TS U101 ( .A(n69), .B(in2[10]), .Y(n88) );
XOR2X1TS U102 ( .A(n113), .B(n112), .Y(res[5]) );
XOR2X1TS U103 ( .A(n106), .B(n105), .Y(res[6]) );
OAI21X1TS U104 ( .A0(n127), .A1(n125), .B0(n126), .Y(n124) );
OAI21X1TS U105 ( .A0(n120), .A1(n122), .B0(n119), .Y(n118) );
NOR2X6TS U106 ( .A(n73), .B(in2[8]), .Y(n71) );
AO21X1TS U107 ( .A0(n107), .A1(in1[5]), .B0(n127), .Y(n103) );
AND2X2TS U108 ( .A(in1[5]), .B(n107), .Y(n81) );
XOR2XLTS U109 ( .A(n179), .B(n129), .Y(res[1]) );
OAI21X1TS U110 ( .A0(n179), .A1(in1[1]), .B0(n177), .Y(n178) );
OAI211X1TS U111 ( .A0(n176), .A1(in1[2]), .B0(in1[1]), .C0(n177), .Y(n116)
);
OAI21X1TS U112 ( .A0(n123), .A1(in1[4]), .B0(n120), .Y(n110) );
XOR2X1TS U113 ( .A(n177), .B(in1[1]), .Y(n129) );
AND2X2TS U114 ( .A(n117), .B(in1[3]), .Y(n120) );
OAI21X1TS U115 ( .A0(n176), .A1(in1[2]), .B0(n175), .Y(n181) );
AOI2BB1XLTS U116 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n179), .Y(res[0]) );
AO21X2TS U117 ( .A0(n100), .A1(n169), .B0(n99), .Y(res[16]) );
NOR2X2TS U118 ( .A(n79), .B(n56), .Y(n80) );
XNOR2X2TS U119 ( .A(n74), .B(in2[8]), .Y(n82) );
NAND4X6TS U120 ( .A(n60), .B(n128), .C(n59), .D(n58), .Y(n101) );
CLKXOR2X2TS U121 ( .A(n80), .B(in2[5]), .Y(n107) );
INVX2TS U122 ( .A(n165), .Y(n139) );
NOR2X4TS U123 ( .A(n66), .B(in2[12]), .Y(n64) );
XNOR2X2TS U124 ( .A(n70), .B(in2[10]), .Y(n84) );
INVX2TS U125 ( .A(n143), .Y(n91) );
AND2X2TS U126 ( .A(n123), .B(in1[4]), .Y(n127) );
NOR2X2TS U127 ( .A(n83), .B(in1[9]), .Y(n130) );
NAND2X1TS U128 ( .A(n83), .B(in1[9]), .Y(n131) );
NOR2X2TS U129 ( .A(n130), .B(n161), .Y(n135) );
INVX2TS U130 ( .A(n136), .Y(n137) );
XOR2X1TS U131 ( .A(n76), .B(in2[7]), .Y(n160) );
INVX2TS U132 ( .A(in2[1]), .Y(n60) );
INVX2TS U133 ( .A(in2[2]), .Y(n59) );
XNOR2X2TS U134 ( .A(n63), .B(in2[14]), .Y(n97) );
NAND2X1TS U135 ( .A(n90), .B(in1[11]), .Y(n143) );
AOI21X2TS U136 ( .A0(n136), .A1(n55), .B0(n85), .Y(n86) );
INVX2TS U137 ( .A(n140), .Y(n85) );
NAND2X1TS U138 ( .A(n92), .B(in1[12]), .Y(n148) );
INVX2TS U139 ( .A(n68), .Y(n153) );
NOR2X1TS U140 ( .A(n92), .B(in1[12]), .Y(n68) );
INVX2TS U141 ( .A(n166), .Y(n167) );
INVX2TS U142 ( .A(n150), .Y(n168) );
NOR2X2TS U143 ( .A(n97), .B(in1[14]), .Y(n150) );
NOR2X2TS U144 ( .A(n98), .B(in1[15]), .Y(n170) );
OAI31X1TS U145 ( .A0(n120), .A1(n119), .A2(n122), .B0(n118), .Y(res[3]) );
OAI31X1TS U146 ( .A0(n127), .A1(n126), .A2(n125), .B0(n124), .Y(res[4]) );
XOR2X1TS U147 ( .A(n107), .B(in1[5]), .Y(n113) );
INVX2TS U148 ( .A(n127), .Y(n111) );
OAI21XLTS U149 ( .A0(n107), .A1(in1[5]), .B0(n103), .Y(n106) );
INVX2TS U150 ( .A(n161), .Y(n163) );
OAI21XLTS U151 ( .A0(n139), .A1(n161), .B0(n162), .Y(n134) );
INVX2TS U152 ( .A(n130), .Y(n132) );
OAI21XLTS U153 ( .A0(n139), .A1(n138), .B0(n137), .Y(n142) );
INVX2TS U154 ( .A(n135), .Y(n138) );
OR2X2TS U155 ( .A(n84), .B(in1[10]), .Y(n55) );
XNOR2X2TS U156 ( .A(n115), .B(in2[1]), .Y(n177) );
XNOR2X2TS U157 ( .A(n114), .B(in2[2]), .Y(n176) );
NOR2X1TS U158 ( .A(in1[4]), .B(n123), .Y(n125) );
XNOR2X2TS U159 ( .A(n102), .B(in2[4]), .Y(n123) );
NOR2BX2TS U160 ( .AN(in1[0]), .B(n128), .Y(n179) );
OAI21X1TS U161 ( .A0(n170), .A1(n166), .B0(n171), .Y(n99) );
ADDFHX2TS U162 ( .A(n160), .B(in1[7]), .CI(n159), .CO(n165), .S(res[7]) );
XOR2X2TS U163 ( .A(n174), .B(n173), .Y(res[15]) );
XOR2X1TS U164 ( .A(n158), .B(n157), .Y(res[13]) );
AOI21X4TS U165 ( .A0(n154), .A1(n153), .B0(n152), .Y(n158) );
NOR2X2TS U166 ( .A(n117), .B(in1[3]), .Y(n122) );
NOR2X8TS U167 ( .A(n101), .B(in2[4]), .Y(n79) );
OAI21X4TS U168 ( .A0(n96), .A1(n147), .B0(n95), .Y(n169) );
AOI21X2TS U169 ( .A0(n156), .A1(n152), .B0(n94), .Y(n95) );
AOI21X4TS U170 ( .A0(n146), .A1(n144), .B0(n91), .Y(n147) );
XNOR2X1TS U171 ( .A(n104), .B(in1[6]), .Y(n105) );
NAND2BX4TS U172 ( .AN(in2[11]), .B(n88), .Y(n66) );
XOR2X1TS U173 ( .A(n89), .B(in2[11]), .Y(n90) );
INVX2TS U174 ( .A(n120), .Y(n121) );
INVX2TS U175 ( .A(n148), .Y(n152) );
NAND2BX4TS U176 ( .AN(in2[5]), .B(n79), .Y(n77) );
NAND2BX4TS U177 ( .AN(in2[7]), .B(n75), .Y(n73) );
NAND2BX4TS U178 ( .AN(in2[9]), .B(n71), .Y(n69) );
OAI21X2TS U179 ( .A0(n62), .A1(in2[14]), .B0(n57), .Y(n61) );
NAND2X1TS U180 ( .A(n66), .B(n57), .Y(n67) );
NAND2X1TS U181 ( .A(n69), .B(n57), .Y(n70) );
NOR2X2TS U182 ( .A(n82), .B(in1[8]), .Y(n161) );
NAND2X1TS U183 ( .A(n55), .B(n135), .Y(n87) );
NAND2X1TS U184 ( .A(n77), .B(add_sub), .Y(n78) );
XNOR2X1TS U185 ( .A(n78), .B(in2[6]), .Y(n104) );
OAI21X4TS U186 ( .A0(n87), .A1(n139), .B0(n86), .Y(n146) );
NOR2X1TS U187 ( .A(n88), .B(n56), .Y(n89) );
NAND2X1TS U188 ( .A(n93), .B(in1[13]), .Y(n155) );
NAND2X1TS U189 ( .A(n98), .B(in1[15]), .Y(n171) );
NAND2X1TS U190 ( .A(n101), .B(n57), .Y(n102) );
OR3X1TS U191 ( .A(in2[2]), .B(in2[0]), .C(in2[1]), .Y(n108) );
NAND2X1TS U192 ( .A(add_sub), .B(n108), .Y(n109) );
XNOR2X1TS U193 ( .A(n109), .B(in2[3]), .Y(n117) );
NAND2X1TS U194 ( .A(n111), .B(n110), .Y(n112) );
NAND2X1TS U195 ( .A(n57), .B(in2[0]), .Y(n115) );
NAND2X1TS U196 ( .A(n175), .B(n116), .Y(n119) );
OAI21X1TS U197 ( .A0(n122), .A1(n175), .B0(n121), .Y(n126) );
NAND2X1TS U198 ( .A(n132), .B(n131), .Y(n133) );
XNOR2X1TS U199 ( .A(n134), .B(n133), .Y(res[9]) );
NAND2X1TS U200 ( .A(n55), .B(n140), .Y(n141) );
XNOR2X1TS U201 ( .A(n142), .B(n141), .Y(res[10]) );
NAND2X1TS U202 ( .A(n144), .B(n143), .Y(n145) );
XNOR2X1TS U203 ( .A(n146), .B(n145), .Y(res[11]) );
INVX2TS U204 ( .A(n147), .Y(n154) );
NAND2X1TS U205 ( .A(n153), .B(n148), .Y(n149) );
XNOR2X1TS U206 ( .A(n154), .B(n149), .Y(res[12]) );
NAND2X1TS U207 ( .A(n168), .B(n166), .Y(n151) );
XNOR2X1TS U208 ( .A(n169), .B(n151), .Y(res[14]) );
NAND2X1TS U209 ( .A(n156), .B(n155), .Y(n157) );
NAND2X1TS U210 ( .A(n163), .B(n162), .Y(n164) );
XNOR2X1TS U211 ( .A(n165), .B(n164), .Y(res[8]) );
AOI21X4TS U212 ( .A0(n169), .A1(n168), .B0(n167), .Y(n174) );
NAND2X1TS U213 ( .A(n172), .B(n171), .Y(n173) );
OAI2BB1X1TS U214 ( .A0N(in1[1]), .A1N(n179), .B0(n178), .Y(n180) );
XNOR2X1TS U215 ( .A(n181), .B(n180), .Y(res[2]) );
initial $sdf_annotate("Approx_adder_add_approx_flow_syn_constraints.tcl_GeArN8R1P2_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/17/2017 08:14:19 AM
// Design Name:
// Module Name: INSTRUCTION_FETCH_STAGE
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module INSTRUCTION_FETCH_STAGE #(
parameter ADDRESS_WIDTH = 32 ,
parameter HIGH = 1'b1 ,
parameter LOW = 1'b0
) (
input CLK ,
input STALL_INSTRUCTION_FETCH_STAGE ,
input CLEAR_INSTRUCTION_FETCH_STAGE ,
input [ADDRESS_WIDTH - 1 : 0] PC_IN ,
input PC_VALID_IN ,
output [ADDRESS_WIDTH - 1 : 0] PC_OUT ,
output PC_VALID_OUT
);
reg [ADDRESS_WIDTH - 1 : 0] pc_reg ;
reg pc_valid_reg ;
always@(posedge CLK)
begin
if(CLEAR_INSTRUCTION_FETCH_STAGE == LOW)
begin
if(STALL_INSTRUCTION_FETCH_STAGE == LOW)
begin
pc_reg <= PC_IN ;
pc_valid_reg <= PC_VALID_IN ;
end
end
else
begin
pc_reg <= 32'b0;
pc_valid_reg <= LOW ;
end
end
assign PC_OUT = pc_reg ;
assign PC_VALID_OUT = pc_valid_reg ;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module cf_ddsx (
// dac interface
dac_div3_clk,
dds_master_enable,
// I frame/data (sample 0 is transmitted first)
dds_data_00,
dds_data_01,
dds_data_02,
// Q frame/data (sample 0 is transmitted first)
dds_data_10,
dds_data_11,
dds_data_12,
// 2's compl (0x1) or offset-bin (0x0)
dds_format_n,
// processor signals
up_dds_init_1a, // Initial phase value (for DDSX only)
up_dds_incr_1a, // Increment phase value (for DDSX only)
up_dds_scale_1a, // Samples scale value (for DDSX only)
up_dds_init_1b, // Initial phase value (for DDSX only)
up_dds_incr_1b, // Increment phase value (for DDSX only)
up_dds_scale_1b, // Samples scale value (for DDSX only)
up_dds_init_2a, // Initial phase value (for DDSX only)
up_dds_incr_2a, // Increment phase value (for DDSX only)
up_dds_scale_2a, // Samples scale value (for DDSX only)
up_dds_init_2b, // Initial phase value (for DDSX only)
up_dds_incr_2b, // Increment phase value (for DDSX only)
up_dds_scale_2b, // Samples scale value (for DDSX only)
// debug signals (chipscope)
debug_data,
debug_trigger);
// dac interface
input dac_div3_clk;
input dds_master_enable;
// I frame/data (sample 0 is transmitted first)
output [15:0] dds_data_00;
output [15:0] dds_data_01;
output [15:0] dds_data_02;
// Q frame/data (sample 0 is transmitted first)
output [15:0] dds_data_10;
output [15:0] dds_data_11;
output [15:0] dds_data_12;
// 2's compl (0x1) or offset-bin (0x0)
input dds_format_n;
// processor signals
input [15:0] up_dds_init_1a;
input [15:0] up_dds_incr_1a;
input [ 3:0] up_dds_scale_1a;
input [15:0] up_dds_init_1b;
input [15:0] up_dds_incr_1b;
input [ 3:0] up_dds_scale_1b;
input [15:0] up_dds_init_2a;
input [15:0] up_dds_incr_2a;
input [ 3:0] up_dds_scale_2a;
input [15:0] up_dds_init_2b;
input [15:0] up_dds_incr_2b;
input [ 3:0] up_dds_scale_2b;
// debug signals (chipscope)
output [79:0] debug_data;
output [ 7:0] debug_trigger;
reg [ 5:0] dds_enable_cnt = 'd0;
reg dds_enable_clr = 'd0;
reg dds_enable_int = 'd0;
reg dds_enable_m1 = 'd0;
reg dds_enable_m2 = 'd0;
reg dds_enable_m3 = 'd0;
reg dds_enable_m4 = 'd0;
reg dds_enable_m5 = 'd0;
reg dds_enable_m6 = 'd0;
reg dds_enable_m7 = 'd0;
reg [15:0] dds_init_m_1a = 'd0;
reg [15:0] dds_incr_m_1a = 'd0;
reg [15:0] dds_init_m_1b = 'd0;
reg [15:0] dds_incr_m_1b = 'd0;
reg [15:0] dds_init_m_2a = 'd0;
reg [15:0] dds_incr_m_2a = 'd0;
reg [15:0] dds_init_m_2b = 'd0;
reg [15:0] dds_incr_m_2b = 'd0;
reg [ 3:0] dds_scale_1a = 'd0;
reg [ 3:0] dds_scale_1b = 'd0;
reg [ 3:0] dds_scale_2a = 'd0;
reg [ 3:0] dds_scale_2b = 'd0;
reg dds_enable = 'd0;
reg [15:0] dds_incr_1a = 'd0;
reg [15:0] dds_init_1a_0 = 'd0;
reg [15:0] dds_init_1a_1 = 'd0;
reg [15:0] dds_init_1a_2 = 'd0;
reg [15:0] dds_incr_1b = 'd0;
reg [15:0] dds_init_1b_0 = 'd0;
reg [15:0] dds_init_1b_1 = 'd0;
reg [15:0] dds_init_1b_2 = 'd0;
reg [15:0] dds_incr_2a = 'd0;
reg [15:0] dds_init_2a_0 = 'd0;
reg [15:0] dds_init_2a_1 = 'd0;
reg [15:0] dds_init_2a_2 = 'd0;
reg [15:0] dds_incr_2b = 'd0;
reg [15:0] dds_init_2b_0 = 'd0;
reg [15:0] dds_init_2b_1 = 'd0;
reg [15:0] dds_init_2b_2 = 'd0;
reg dds_enable_d = 'd0;
reg [15:0] dds_data_in_1a_0 = 'd0;
reg [15:0] dds_data_in_1a_1 = 'd0;
reg [15:0] dds_data_in_1a_2 = 'd0;
reg [15:0] dds_data_in_1b_0 = 'd0;
reg [15:0] dds_data_in_1b_1 = 'd0;
reg [15:0] dds_data_in_1b_2 = 'd0;
reg [15:0] dds_data_in_2a_0 = 'd0;
reg [15:0] dds_data_in_2a_1 = 'd0;
reg [15:0] dds_data_in_2a_2 = 'd0;
reg [15:0] dds_data_in_2b_0 = 'd0;
reg [15:0] dds_data_in_2b_1 = 'd0;
reg [15:0] dds_data_in_2b_2 = 'd0;
reg [15:0] dds_data_out_1a_0 = 'd0;
reg [15:0] dds_data_out_1a_1 = 'd0;
reg [15:0] dds_data_out_1a_2 = 'd0;
reg [15:0] dds_data_out_1b_0 = 'd0;
reg [15:0] dds_data_out_1b_1 = 'd0;
reg [15:0] dds_data_out_1b_2 = 'd0;
reg [15:0] dds_data_out_2a_0 = 'd0;
reg [15:0] dds_data_out_2a_1 = 'd0;
reg [15:0] dds_data_out_2a_2 = 'd0;
reg [15:0] dds_data_out_2b_0 = 'd0;
reg [15:0] dds_data_out_2b_1 = 'd0;
reg [15:0] dds_data_out_2b_2 = 'd0;
reg [15:0] dds_data_out_00 = 'd0;
reg [15:0] dds_data_out_01 = 'd0;
reg [15:0] dds_data_out_02 = 'd0;
reg [15:0] dds_data_out_10 = 'd0;
reg [15:0] dds_data_out_11 = 'd0;
reg [15:0] dds_data_out_12 = 'd0;
reg [15:0] dds_data_00 = 'd0;
reg [15:0] dds_data_01 = 'd0;
reg [15:0] dds_data_02 = 'd0;
reg [15:0] dds_data_10 = 'd0;
reg [15:0] dds_data_11 = 'd0;
reg [15:0] dds_data_12 = 'd0;
wire [15:0] dds_data_out_1a_0_s;
wire [15:0] dds_data_out_1a_1_s;
wire [15:0] dds_data_out_1a_2_s;
wire [15:0] dds_data_out_1b_0_s;
wire [15:0] dds_data_out_1b_1_s;
wire [15:0] dds_data_out_1b_2_s;
wire [15:0] dds_data_out_2a_0_s;
wire [15:0] dds_data_out_2a_1_s;
wire [15:0] dds_data_out_2a_2_s;
wire [15:0] dds_data_out_2b_0_s;
wire [15:0] dds_data_out_2b_1_s;
wire [15:0] dds_data_out_2b_2_s;
// The DDS outputs are scaled and added together.
function [15:0] data_scale;
input [15:0] data;
input [ 3:0] scale;
reg [15:0] data_out;
begin
case (scale)
4'b1111: data_out = {{15{data[15]}}, data[15:15]};
4'b1110: data_out = {{14{data[15]}}, data[15:14]};
4'b1101: data_out = {{13{data[15]}}, data[15:13]};
4'b1100: data_out = {{12{data[15]}}, data[15:12]};
4'b1011: data_out = {{11{data[15]}}, data[15:11]};
4'b1010: data_out = {{10{data[15]}}, data[15:10]};
4'b1001: data_out = {{ 9{data[15]}}, data[15: 9]};
4'b1000: data_out = {{ 8{data[15]}}, data[15: 8]};
4'b0111: data_out = {{ 7{data[15]}}, data[15: 7]};
4'b0110: data_out = {{ 6{data[15]}}, data[15: 6]};
4'b0101: data_out = {{ 5{data[15]}}, data[15: 5]};
4'b0100: data_out = {{ 4{data[15]}}, data[15: 4]};
4'b0011: data_out = {{ 3{data[15]}}, data[15: 3]};
4'b0010: data_out = {{ 2{data[15]}}, data[15: 2]};
4'b0001: data_out = {{ 1{data[15]}}, data[15: 1]};
default: data_out = data;
endcase
data_scale = data_out;
end
endfunction
// debug ports
assign debug_trigger = {7'd0, dds_master_enable};
assign debug_data[79:79] = dds_master_enable;
assign debug_data[78:78] = dds_enable_m1;
assign debug_data[77:77] = dds_enable_m2;
assign debug_data[76:76] = dds_enable_m3;
assign debug_data[75:75] = dds_enable_m4;
assign debug_data[74:74] = dds_enable_m7;
assign debug_data[73:73] = dds_enable;
assign debug_data[72:72] = dds_enable_d;
assign debug_data[71:71] = dds_enable_clr;
assign debug_data[70:70] = dds_enable_int;
assign debug_data[69:64] = dds_enable_cnt;
assign debug_data[63:48] = dds_data_in_2a_2;
assign debug_data[47:32] = dds_data_in_2a_0;
assign debug_data[31:16] = dds_data_in_1a_2;
assign debug_data[15: 0] = dds_data_in_1a_0;
// The DDS cores need a reset when tones are changed, this is a synchronous clear
// for the DDS cores. If disabled, the DDS cores are held on rest for about 32
// clocks. After which processor control takes over.
always @(posedge dac_div3_clk) begin
if (dds_master_enable == 1'b0) begin
dds_enable_cnt <= 6'h20;
end else if (dds_enable_cnt[5] == 1'b1) begin
dds_enable_cnt <= dds_enable_cnt + 1'b1;
end
dds_enable_clr <= dds_enable_cnt[5];
dds_enable_int <= ~dds_enable_cnt[5];
end
// Transfer processor signals to the dac clock. A very long chain is created for
// enable. This allows the individual phase counters to stabilize before the
// actual increment happens.
always @(posedge dac_div3_clk) begin
dds_enable_m1 <= dds_enable_int;
dds_enable_m2 <= dds_enable_m1;
dds_enable_m3 <= dds_enable_m2;
dds_enable_m4 <= dds_enable_m3;
dds_enable_m5 <= dds_enable_m4;
dds_enable_m6 <= dds_enable_m5;
dds_enable_m7 <= dds_enable_m6;
if ((dds_enable_m2 == 1'b1) && (dds_enable_m3 == 1'b0)) begin
dds_init_m_1a <= up_dds_init_1a;
dds_incr_m_1a <= up_dds_incr_1a;
dds_init_m_1b <= up_dds_init_1b;
dds_incr_m_1b <= up_dds_incr_1b;
dds_init_m_2a <= up_dds_init_2a;
dds_incr_m_2a <= up_dds_incr_2a;
dds_init_m_2b <= up_dds_init_2b;
dds_incr_m_2b <= up_dds_incr_2b;
end
if ((dds_enable_m2 == 1'b1) && (dds_enable_m3 == 1'b0)) begin
dds_scale_1a <= up_dds_scale_1a;
dds_scale_1b <= up_dds_scale_1b;
dds_scale_2a <= up_dds_scale_2a;
dds_scale_2b <= up_dds_scale_2b;
end
end
// The initial phase values of the DDS cores are updated according to the increment
// value. Note from the above chain, that by the time enable comes out of that
// pipe, these values will be stable.
always @(posedge dac_div3_clk) begin
dds_enable <= dds_enable_m7;
dds_incr_1a <= dds_incr_m_1a + {dds_incr_m_1a[14:0], 1'd0};
dds_init_1a_0 <= dds_init_m_1a;
dds_init_1a_1 <= dds_init_m_1a + dds_incr_m_1a;
dds_init_1a_2 <= dds_init_m_1a + {dds_incr_m_1a[14:0], 1'd0};
dds_incr_1b <= dds_incr_m_1b + {dds_incr_m_1b[14:0], 1'd0};
dds_init_1b_0 <= dds_init_m_1b;
dds_init_1b_1 <= dds_init_m_1b + dds_incr_m_1b;
dds_init_1b_2 <= dds_init_m_1b + {dds_incr_m_1b[14:0], 1'd0};
dds_incr_2a <= dds_incr_m_2a + {dds_incr_m_2a[14:0], 1'd0};
dds_init_2a_0 <= dds_init_m_2a;
dds_init_2a_1 <= dds_init_m_2a + dds_incr_m_2a;
dds_init_2a_2 <= dds_init_m_2a + {dds_incr_m_2a[14:0], 1'd0};
dds_incr_2b <= dds_incr_m_2b + {dds_incr_m_2b[14:0], 1'd0};
dds_init_2b_0 <= dds_init_m_2b;
dds_init_2b_1 <= dds_init_m_2b + dds_incr_m_2b;
dds_init_2b_2 <= dds_init_m_2b + {dds_incr_m_2b[14:0], 1'd0};
end
// This is the running DDS phase counters
always @(posedge dac_div3_clk) begin
dds_enable_d <= dds_enable;
if (dds_enable_d == 1'b1) begin
dds_data_in_1a_0 <= dds_data_in_1a_0 + dds_incr_1a;
dds_data_in_1a_1 <= dds_data_in_1a_1 + dds_incr_1a;
dds_data_in_1a_2 <= dds_data_in_1a_2 + dds_incr_1a;
dds_data_in_1b_0 <= dds_data_in_1b_0 + dds_incr_1b;
dds_data_in_1b_1 <= dds_data_in_1b_1 + dds_incr_1b;
dds_data_in_1b_2 <= dds_data_in_1b_2 + dds_incr_1b;
dds_data_in_2a_0 <= dds_data_in_2a_0 + dds_incr_2a;
dds_data_in_2a_1 <= dds_data_in_2a_1 + dds_incr_2a;
dds_data_in_2a_2 <= dds_data_in_2a_2 + dds_incr_2a;
dds_data_in_2b_0 <= dds_data_in_2b_0 + dds_incr_2b;
dds_data_in_2b_1 <= dds_data_in_2b_1 + dds_incr_2b;
dds_data_in_2b_2 <= dds_data_in_2b_2 + dds_incr_2b;
end else if (dds_enable == 1'b1) begin
dds_data_in_1a_0 <= dds_init_1a_0;
dds_data_in_1a_1 <= dds_init_1a_1;
dds_data_in_1a_2 <= dds_init_1a_2;
dds_data_in_1b_0 <= dds_init_1b_0;
dds_data_in_1b_1 <= dds_init_1b_1;
dds_data_in_1b_2 <= dds_init_1b_2;
dds_data_in_2a_0 <= dds_init_2a_0;
dds_data_in_2a_1 <= dds_init_2a_1;
dds_data_in_2a_2 <= dds_init_2a_2;
dds_data_in_2b_0 <= dds_init_2b_0;
dds_data_in_2b_1 <= dds_init_2b_1;
dds_data_in_2b_2 <= dds_init_2b_2;
end else begin
dds_data_in_1a_0 <= 16'd0;
dds_data_in_1a_1 <= 16'd0;
dds_data_in_1a_2 <= 16'd0;
dds_data_in_1b_0 <= 16'd0;
dds_data_in_1b_1 <= 16'd0;
dds_data_in_1b_2 <= 16'd0;
dds_data_in_2a_0 <= 16'd0;
dds_data_in_2a_1 <= 16'd0;
dds_data_in_2a_2 <= 16'd0;
dds_data_in_2b_0 <= 16'd0;
dds_data_in_2b_1 <= 16'd0;
dds_data_in_2b_2 <= 16'd0;
end
end
// THe DDS outputs are scaled and added together (scaling avoids range overflow).
always @(posedge dac_div3_clk) begin
dds_data_out_1a_0 <= data_scale(dds_data_out_1a_0_s, dds_scale_1a);
dds_data_out_1a_1 <= data_scale(dds_data_out_1a_1_s, dds_scale_1a);
dds_data_out_1a_2 <= data_scale(dds_data_out_1a_2_s, dds_scale_1a);
dds_data_out_1b_0 <= data_scale(dds_data_out_1b_0_s, dds_scale_1b);
dds_data_out_1b_1 <= data_scale(dds_data_out_1b_1_s, dds_scale_1b);
dds_data_out_1b_2 <= data_scale(dds_data_out_1b_2_s, dds_scale_1b);
dds_data_out_2a_0 <= data_scale(dds_data_out_2a_0_s, dds_scale_2a);
dds_data_out_2a_1 <= data_scale(dds_data_out_2a_1_s, dds_scale_2a);
dds_data_out_2a_2 <= data_scale(dds_data_out_2a_2_s, dds_scale_2a);
dds_data_out_2b_0 <= data_scale(dds_data_out_2b_0_s, dds_scale_2b);
dds_data_out_2b_1 <= data_scale(dds_data_out_2b_1_s, dds_scale_2b);
dds_data_out_2b_2 <= data_scale(dds_data_out_2b_2_s, dds_scale_2b);
dds_data_out_00 <= dds_data_out_1a_0 + dds_data_out_1b_0;
dds_data_out_01 <= dds_data_out_1a_1 + dds_data_out_1b_1;
dds_data_out_02 <= dds_data_out_1a_2 + dds_data_out_1b_2;
dds_data_out_10 <= dds_data_out_2a_0 + dds_data_out_2b_0;
dds_data_out_11 <= dds_data_out_2a_1 + dds_data_out_2b_1;
dds_data_out_12 <= dds_data_out_2a_2 + dds_data_out_2b_2;
dds_data_00 <= {(dds_format_n ^ dds_data_out_00[15]), dds_data_out_00[14:0]};
dds_data_01 <= {(dds_format_n ^ dds_data_out_01[15]), dds_data_out_01[14:0]};
dds_data_02 <= {(dds_format_n ^ dds_data_out_02[15]), dds_data_out_02[14:0]};
dds_data_10 <= {(dds_format_n ^ dds_data_out_10[15]), dds_data_out_10[14:0]};
dds_data_11 <= {(dds_format_n ^ dds_data_out_11[15]), dds_data_out_11[14:0]};
dds_data_12 <= {(dds_format_n ^ dds_data_out_12[15]), dds_data_out_12[14:0]};
end
// Xilinx's DDS core, I sample 0
cf_ddsx_1 i_ddsx_1a_0 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_1a_0),
.sine (dds_data_out_1a_0_s));
// Xilinx's DDS core, I sample 1
cf_ddsx_1 i_ddsx_1a_1 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_1a_1),
.sine (dds_data_out_1a_1_s));
// Xilinx's DDS core, I sample 2
cf_ddsx_1 i_ddsx_1a_2 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_1a_2),
.sine (dds_data_out_1a_2_s));
// Xilinx's DDS core, I sample 0
cf_ddsx_1 i_ddsx_1b_0 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_1b_0),
.sine (dds_data_out_1b_0_s));
// Xilinx's DDS core, I sample 1
cf_ddsx_1 i_ddsx_1b_1 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_1b_1),
.sine (dds_data_out_1b_1_s));
// Xilinx's DDS core, I sample 2
cf_ddsx_1 i_ddsx_1b_2 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_1b_2),
.sine (dds_data_out_1b_2_s));
// Xilinx's DDS core, Q sample 0
cf_ddsx_1 i_ddsx_2a_0 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_2a_0),
.sine (dds_data_out_2a_0_s));
// Xilinx's DDS core, Q sample 1
cf_ddsx_1 i_ddsx_2a_1 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_2a_1),
.sine (dds_data_out_2a_1_s));
// Xilinx's DDS core, Q sample 2
cf_ddsx_1 i_ddsx_2a_2 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_2a_2),
.sine (dds_data_out_2a_2_s));
// Xilinx's DDS core, Q sample 0
cf_ddsx_1 i_ddsx_2b_0 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_2b_0),
.sine (dds_data_out_2b_0_s));
// Xilinx's DDS core, Q sample 1
cf_ddsx_1 i_ddsx_2b_1 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_2b_1),
.sine (dds_data_out_2b_1_s));
// Xilinx's DDS core, Q sample 2
cf_ddsx_1 i_ddsx_2b_2 (
.clk (dac_div3_clk),
.sclr (dds_enable_clr),
.phase_in (dds_data_in_2b_2),
.sine (dds_data_out_2b_2_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// Copyright (c) 2000-2012 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 29441 $
// $Date: 2012-08-27 21:58:03 +0000 (Mon, 27 Aug 2012) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
// Standard register with asynchronous reset
module RegAligned(CLK, RST, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0}} ;
input CLK;
input RST;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
reg [width - 1 : 0] Q_OUT;
always@(posedge CLK or `BSV_RESET_EDGE RST) begin
if (RST == `BSV_RESET_VALUE)
Q_OUT <= `BSV_ASSIGNMENT_DELAY init;
else
begin
if (EN)
Q_OUT <= `BSV_ASSIGNMENT_DELAY D_IN;
end
end // always@ (posedge CLK or `BSV_RESET_EDGE RST)
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
// synopsys translate_off
initial begin
Q_OUT = {((width + 1)/2){2'b10}} ;
end
// synopsys translate_on
`endif // BSV_NO_INITIAL_BLOCKS
endmodule
|
//`include "../rtl/setup.v"
module measure_core # (
parameter Int_ipv4_addr = {8'd10, 8'd0, 8'd21, 8'd105},
Int_ipv6_addr = 128'h3776_0000_0000_0021_0000_0000_0000_0105,
Int_mac_addr = 48'h003776_000101
) (
input sys_rst,
input sys_clk,
input pci_clk,
input sec_oneshot,
input [31:0] global_counter,
// GMII interfaces for 4 MACs
output [7:0] gmii_txd,
output gmii_tx_en,
input gmii_tx_clk,
input [7:0] gmii_rxd,
input gmii_rx_dv,
input gmii_rx_clk,
// PCI user registers
output reg [31:0] rx_pps,
output reg [31:0] rx_throughput,
output reg [23:0] rx_latency,
output reg [31:0] rx_ipv4_ip,
// mode
input tx_ipv6,
output reg [31:0] count_2976_latency
);
reg [31:0] rx_pps1, rx_pps2;
reg [31:0] rx_throughput1, rx_throughput2;
reg [23:0] rx_latency1, rx_latency2;
reg [31:0] rx_ipv4_ip1, rx_ipv4_ip2;
always @(posedge pci_clk) begin
rx_pps2 <= rx_pps1;
rx_throughput2 <= rx_throughput1;
rx_latency2 <= rx_latency1;
rx_ipv4_ip2 <= rx_ipv4_ip1;
rx_pps <= rx_pps2;
rx_throughput <= rx_throughput2;
rx_latency <= rx_latency2;
rx_ipv4_ip <= rx_ipv4_ip2;
end
//-----------------------------------
// RX FIFO (rxq)
//-----------------------------------
wire [8:0] rxq_din, rxq_dout;
wire rxq_full, rxq_wr_en;
wire rxq_empty;
reg rxq_rd_en;
`ifndef SIMULATION
`ifdef NETFPGA
asfifo9_4 rxq (
.din(rxq_din),
.full(rxq_full),
.wr_en(rxq_wr_en),
.wr_clk(gmii_rx_clk),
.dout(rxq_dout),
.empty(rxq_empty),
.rd_en(rxq_rd_en),
.rd_clk(gmii_tx_clk),
.rst(sys_rst)
);
`endif
`ifdef ECP3VERSA
asfifo9_4 rxq (
.Data(rxq_din),
.Full(rxq_full),
.WrEn(rxq_wr_en),
.WrClock(gmii_rx_clk),
.Q(rxq_dout),
.Empty(rxq_empty),
.RdEn(rxq_rd_en),
.RdClock(gmii_tx_clk),
.RPReset(),
.Reset(sys_rst)
);
`endif
`else
asfifo # (
.DATA_WIDTH(3),
.ADDRESS_WIDTH(4)
) rx0fifo (
.din(rxq_din),
.full(rxq_full),
.wr_en(rxq_wr_en),
.wr_clk(gmii_rx_clk),
.dout(rxq_dout),
.empty(rxq_empty),
.rd_en(rxq_rd_en),
.rd_clk(gmii_tx_clk),
.rst(sys_rst)
);
`endif
//-----------------------------------
// GMII2FIFO9 module
//-----------------------------------
gmii2fifo9 # (
.Gap(4'h8)
) rxgmii2fifo (
.sys_rst(sys_rst),
.gmii_rx_clk(gmii_rx_clk),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rxd(gmii_rxd),
.din(rxq_din),
.full(rxq_full),
.wr_en(rxq_wr_en),
.wr_clk()
);
//-----------------------------------
// Recive logic
//-----------------------------------
reg [15:0] rx_count = 0;
reg [39:0] rx_magic;
reg [31:0] counter_start;
reg [31:0] counter_end;
reg [31:0] pps;
reg [31:0] throughput;
reg [15:0] rx_type; // frame type
reg [47:0] rx_src_mac;
reg [31:0] rx_ipv4_srcip;
reg [15:0] rx_opcode;
reg [ 7:0] v6type;
reg arp_request;
reg neighbor_replay;
reg [47:0] tx_dst_mac;
reg [31:0] tx_ipv4_dstip;
reg [31:0] rx_arp_dst;
reg [11:0] count_2976;
wire [7:0] rx_data = rxq_dout[7:0];
always @(posedge gmii_tx_clk) begin
if (sys_rst) begin
rx_count <= 16'h0;
rx_magic <= 40'b0;
counter_start <= 32'h0;
counter_end <= 32'h0;
pps <= 32'h0;
throughput <= 32'h0;
rx_pps1 <= 32'h0;
rx_throughput1 <= 32'h0;
rx_ipv4_ip1 <= 32'h0;
rx_type <= 16'h0;
rx_opcode <= 16'h0;
rx_src_mac <= 48'h0;
rx_ipv4_srcip <= 32'h0;
v6type <= 8'h0;
arp_request <= 1'b0;
neighbor_replay <= 1'b0;
tx_dst_mac <= 48'h0;
tx_ipv4_dstip <= 32'h0;
rx_arp_dst <= 32'h0;
count_2976 <= 12'h0;
count_2976_latency <= 31'h0;
end else begin
rxq_rd_en <= ~rxq_empty;
if (count_2976 == 12'h0) begin
count_2976_latency <= 32'h0;
end else begin
if (count_2976 != 12'd2976) begin
count_2976_latency <= count_2976_latency + 32'h1;
end
end
if (sec_oneshot == 1'b1) begin
rx_pps1 <= pps;
rx_throughput1 <= throughput;
pps <= 32'h0;
throughput <= 32'h0;
end
if (rxq_rd_en == 1'b1) begin
rx_count <= rx_count + 16'h1;
if (rxq_dout[8] == 1'b1) begin
case (rx_count)
16'h00: if (sec_oneshot == 1'b0)
pps <= pps + 32'h1;
16'h06: rx_src_mac[47:40] <= rx_data;// Ethernet hdr: Source MAC
16'h07: rx_src_mac[39:32] <= rx_data;
16'h08: rx_src_mac[31:24] <= rx_data;
16'h09: rx_src_mac[23:16] <= rx_data;
16'h0a: rx_src_mac[15: 8] <= rx_data;
16'h0b: rx_src_mac[ 7: 0] <= rx_data;
16'h0c: rx_type[15:8] <= rx_data; // Type: IP=0800,ARP=0806
16'h0d: rx_type[ 7:0] <= rx_data;
16'h14: rx_opcode[15:8] <= rx_data; // ARP: Operation (ARP reply: 0x0002)
16'h15: rx_opcode[ 7:0] <= rx_data; // Opcode ARP Request=1
16'h1c: rx_ipv4_srcip[31:24] <= rx_data; // ARP: Source IP address
16'h1d: rx_ipv4_srcip[23:16] <= rx_data;
16'h1e: begin
rx_ipv4_srcip[15: 8] <= rx_data;
rx_ipv4_ip1[31:24] <= rx_data;
end
16'h1f: begin
rx_ipv4_srcip[ 7: 0] <= rx_data;
rx_ipv4_ip1[23:16] <= rx_data;
end
16'h20: rx_ipv4_ip1[15: 8] <= rx_data;
16'h21: rx_ipv4_ip1[ 7: 0] <= rx_data;
16'h26: rx_arp_dst[31:24] <= rx_data; // target IP for ARP
16'h27: rx_arp_dst[23:16] <= rx_data;
16'h28: rx_arp_dst[15: 8] <= rx_data;
16'h29: rx_arp_dst[ 7: 0] <= rx_data;
16'h2a: rx_magic[39:32] <= rx_data;
16'h2b: rx_magic[31:24] <= rx_data;
16'h2c: rx_magic[23:16] <= rx_data;
16'h2d: rx_magic[15:8] <= rx_data;
16'h2e: rx_magic[7:0] <= rx_data;
16'h2f: counter_start[31:24] <= rx_data;
16'h30: counter_start[23:16] <= rx_data;
16'h31: counter_start[15:8] <= rx_data;
16'h32: counter_start[7:0] <= rx_data;
16'h33: begin
if (rx_magic[39:0] == `MAGIC_CODE) begin
rx_latency1 <= global_counter - counter_start;
if (count_2976 != 12'd2976) begin
count_2976 <= count_2976 + 12'd1;
end
end else if (rx_type == 16'h0806 && rx_opcode == 16'h1 && rx_arp_dst == Int_ipv4_addr) begin // rx_magic[39:8] is Target IP Addres (ARP)
tx_dst_mac <= rx_src_mac;
tx_ipv4_dstip <= rx_ipv4_srcip;
arp_request <= 1'b1;
end
end
16'h36: v6type <= rx_data;
16'h3e: rx_magic[39:32] <= rx_data;
16'h3f: rx_magic[31:24] <= rx_data;
16'h40: rx_magic[23:16] <= rx_data;
16'h41: rx_magic[15:8] <= rx_data;
16'h42: rx_magic[7:0] <= rx_data;
16'h43: counter_start[31:24] <= rx_data;
16'h44: counter_start[23:16] <= rx_data;
16'h45: counter_start[15:8] <= rx_data;
16'h46: counter_start[7:0] <= rx_data;
16'h47: begin
if (rx_magic[39:0] == `MAGIC_CODE) begin
rx_latency1 <= global_counter - counter_start;
end
end
// frame type=IPv6(0x86dd) && Next Header=ICMPv6(0x3a) && Type=Router Advertisement(134)
16'h48: if (rx_type == 16'h86dd && rx_opcode[15:8] == 8'h3a && v6type == 8'h86) begin
tx_dst_mac <= rx_src_mac;
neighbor_replay <= 1'b1;
end
endcase
end else begin
arp_request <= 1'b0;
neighbor_replay <= 1'b0;
if (rx_count != 16'h0 && sec_oneshot == 1'b0) begin
throughput <= throughput + {16'h0, rx_count};
end
rx_count <= 16'h0;
end
end
end
end
//-----------------------------------
// ARP/ICMPv6 CRC
//-----------------------------------
reg [6:0] arp_count;
reg [6:0] neighbor_count;
reg [7:0] tx_data;
assign arp_crc_init = (arp_count == 7'h08) || (neighbor_count == 7'h08);
wire [31:0] arp_crc_out;
reg arp_crc_rd;
assign arp_crc_data_en = ~arp_crc_rd;
crc_gen arp_crc_inst (
.Reset(sys_rst),
.Clk(gmii_tx_clk),
.Init(arp_crc_init),
.Frame_data(tx_data),
.Data_en(arp_crc_data_en),
.CRC_rd(arp_crc_rd),
.CRC_end(),
.CRC_out(arp_crc_out)
);
//-----------------------------------
// ARP/ICMPv6 logic
//-----------------------------------
wire [47:0] tx_src_mac = Int_mac_addr;
wire [31:0] tx_ipv4_srcip = Int_ipv4_addr;
wire [127:0] tx_ipv6_srcip = Int_ipv6_addr;
reg tx_en;
reg [1:0] arp_state;
parameter ARP_IDLE = 2'h0;
parameter ARP_SEND = 2'h1;
parameter NEIGHBOR_SEND = 2'h2;
always @(posedge gmii_tx_clk) begin
if (sys_rst) begin
tx_data <= 8'h00;
tx_en <= 1'b0;
arp_crc_rd <= 1'b0;
arp_count <= 7'h0;
neighbor_count <= 7'h0;
arp_state <= ARP_IDLE;
end else begin
case (arp_state)
ARP_IDLE: begin
if (tx_ipv6 == 1'b0 && arp_request == 1'b1) begin
arp_count <= 7'h0;
arp_state <= ARP_SEND;
end else if (tx_ipv6 == 1'b1 && sec_oneshot == 1'b1) begin
neighbor_count <= 7'h0;
arp_state <= NEIGHBOR_SEND;
end
end
ARP_SEND: begin
case (arp_count)
7'h00: begin
tx_data <= 8'h55;
tx_en <= 1'b1;
end
7'h01: tx_data <= 8'h55; // preamble
7'h02: tx_data <= 8'h55;
7'h03: tx_data <= 8'h55;
7'h04: tx_data <= 8'h55;
7'h05: tx_data <= 8'h55;
7'h06: tx_data <= 8'h55;
7'h07: tx_data <= 8'hd5; // preamble + SFD (0b1101_0101)
7'h08: tx_data <= tx_dst_mac[47:40]; // Ethernet hdr: Destination MAC
7'h09: tx_data <= tx_dst_mac[39:32];
7'h0a: tx_data <= tx_dst_mac[31:24];
7'h0b: tx_data <= tx_dst_mac[23:16];
7'h0c: tx_data <= tx_dst_mac[15:8];
7'h0d: tx_data <= tx_dst_mac[7:0];
7'h0e: tx_data <= tx_src_mac[47:40]; // Ethernet hdr: Source MAC
7'h0f: tx_data <= tx_src_mac[39:32];
7'h10: tx_data <= tx_src_mac[31:24];
7'h11: tx_data <= tx_src_mac[23:16];
7'h12: tx_data <= tx_src_mac[15:8];
7'h13: tx_data <= tx_src_mac[7:0];
7'h14: tx_data <= 8'h08; // Ethernet hdr: Protocol type: ARP
7'h15: tx_data <= 8'h06;
7'h16: tx_data <= 8'h00; // ARP: Hardware type: Ethernet (1)
7'h17: tx_data <= 8'h01;
7'h18: tx_data <= 8'h08; // ARP: Protocol type: IPv4 (0x0800)
7'h19: tx_data <= 8'h00;
7'h1a: tx_data <= 8'h06; // ARP: MAC length
7'h1b: tx_data <= 8'h04; // ARP: IP address length
7'h1c: tx_data <= 8'h00; // ARP: Operation (ARP reply: 0x0002)
7'h1d: tx_data <= 8'h02;
7'h1e: tx_data <= tx_src_mac[47:40]; // ARP: Source MAC
7'h1f: tx_data <= tx_src_mac[39:32];
7'h20: tx_data <= tx_src_mac[31:24];
7'h21: tx_data <= tx_src_mac[23:16];
7'h22: tx_data <= tx_src_mac[15:8];
7'h23: tx_data <= tx_src_mac[7:0];
7'h24: tx_data <= tx_ipv4_srcip[31:24]; // ARP: Source IP address
7'h25: tx_data <= tx_ipv4_srcip[23:16];
7'h26: tx_data <= tx_ipv4_srcip[15:8];
7'h27: tx_data <= tx_ipv4_srcip[7:0];
7'h28: tx_data <= tx_dst_mac[47:40]; // ARP: Destination MAC
7'h29: tx_data <= tx_dst_mac[39:32];
7'h2a: tx_data <= tx_dst_mac[31:24];
7'h2b: tx_data <= tx_dst_mac[23:16];
7'h2c: tx_data <= tx_dst_mac[15:8];
7'h2d: tx_data <= tx_dst_mac[7:0];
7'h2e: tx_data <= tx_ipv4_dstip[31:24]; // ARP: Destination Address
7'h2f: tx_data <= tx_ipv4_dstip[23:16];
7'h30: tx_data <= tx_ipv4_dstip[15:8];
7'h31: tx_data <= tx_ipv4_dstip[7:0];
7'h32: tx_data <= 8'h00; // Padding (frame size = 64 byte)
7'h33: tx_data <= 8'h00;
7'h34: tx_data <= 8'h00;
7'h35: tx_data <= 8'h00;
7'h36: tx_data <= 8'h00;
7'h37: tx_data <= 8'h00;
7'h38: tx_data <= 8'h00;
7'h39: tx_data <= 8'h00;
7'h3a: tx_data <= 8'h00;
7'h3b: tx_data <= 8'h00;
7'h3c: tx_data <= 8'h00;
7'h3d: tx_data <= 8'h00;
7'h3e: tx_data <= 8'h00;
7'h3f: tx_data <= 8'h00;
7'h40: tx_data <= 8'h00;
7'h41: tx_data <= 8'h00;
7'h42: tx_data <= 8'h00;
7'h43: tx_data <= 8'h00;
7'h44: begin // FCS (CRC)
arp_crc_rd <= 1'b1;
tx_data <= arp_crc_out[31:24];
end
7'h45: tx_data <= arp_crc_out[23:16];
7'h46: tx_data <= arp_crc_out[15:8];
7'h47: tx_data <= arp_crc_out[7:0];
7'h48: begin
tx_en <= 1'b0;
arp_crc_rd <= 1'b0;
tx_data <= 8'h0;
arp_state <= ARP_IDLE;
end
default: tx_data <= 8'h00;
endcase
arp_count <= arp_count + 7'h1;
end
NEIGHBOR_SEND: begin
case (neighbor_count)
7'h00: begin
tx_data <= 8'h55;
tx_en <= 1'b1;
end
7'h01: tx_data <= 8'h55; // preamble
7'h02: tx_data <= 8'h55;
7'h03: tx_data <= 8'h55;
7'h04: tx_data <= 8'h55;
7'h05: tx_data <= 8'h55;
7'h06: tx_data <= 8'h55;
7'h07: tx_data <= 8'hd5; // preamble + SFD (0b1101_0101)
7'h08: tx_data <= 8'hff; // Ethernet hdr: Destination MAC
7'h09: tx_data <= 8'hff;
7'h0a: tx_data <= 8'hff;
7'h0b: tx_data <= 8'hff;
7'h0c: tx_data <= 8'hff;
7'h0d: tx_data <= 8'hff;
7'h0e: tx_data <= tx_src_mac[47:40]; // Ethernet hdr: Source MAC
7'h0f: tx_data <= tx_src_mac[39:32];
7'h10: tx_data <= tx_src_mac[31:24];
7'h11: tx_data <= tx_src_mac[23:16];
7'h12: tx_data <= tx_src_mac[15:8];
7'h13: tx_data <= tx_src_mac[7:0];
7'h14: tx_data <= 8'h86; // Ethernet hdr: Protocol type:IPv6
7'h15: tx_data <= 8'hdd;
7'h16: tx_data <= 8'h60; // Version:6 Flowlabel: 0x00000
7'h17: tx_data <= 8'h00;
7'h18: tx_data <= 8'h00;
7'h19: tx_data <= 8'h00;
7'h1a: tx_data <= 8'h00; // Payload Length: 8
7'h1b: tx_data <= 8'h08;
7'h1c: tx_data <= 8'h3a; // Next header: ICMPv6 (0x3a)
7'h1d: tx_data <= 8'hff; // Hop limit: 255
7'h1e: tx_data <= 8'hfe; // Source IPv6
7'h1f: tx_data <= 8'h80;
7'h20: tx_data <= 8'h00;
7'h21: tx_data <= 8'h00;
7'h22: tx_data <= 8'h00;
7'h23: tx_data <= 8'h00;
7'h24: tx_data <= 8'h00;
7'h25: tx_data <= 8'h00;
7'h26: tx_data <= 8'h00;
7'h27: tx_data <= 8'h00;
7'h28: tx_data <= tx_src_mac[ 47: 40];
7'h29: tx_data <= tx_src_mac[ 39: 32];
7'h2a: tx_data <= tx_src_mac[ 31: 24];
7'h2b: tx_data <= tx_src_mac[ 23: 16];
7'h2c: tx_data <= tx_src_mac[ 15: 8];
7'h2d: tx_data <= tx_src_mac[ 7: 0];
7'h2e: tx_data <= 8'hff; // dest IPv6 (All routers address: ff02::2)
7'h2f: tx_data <= 8'h02;
7'h30: tx_data <= 8'h00;
7'h31: tx_data <= 8'h00;
7'h32: tx_data <= 8'h00;
7'h33: tx_data <= 8'h00;
7'h34: tx_data <= 8'h00;
7'h35: tx_data <= 8'h00;
7'h36: tx_data <= 8'h00;
7'h37: tx_data <= 8'h00;
7'h38: tx_data <= 8'h00;
7'h39: tx_data <= 8'h00;
7'h3a: tx_data <= 8'h00;
7'h3b: tx_data <= 8'h00;
7'h3c: tx_data <= 8'h00;
7'h3d: tx_data <= 8'h02;
7'h3e: tx_data <= 8'h85; // Type: Router Solicitation (type: 133)
7'h3f: tx_data <= 8'h00; // Code: 0
7'h40: tx_data <= 8'h00; // Checksum
7'h41: tx_data <= 8'h00;
7'h42: tx_data <= 8'h00; // Reserved
7'h43: tx_data <= 8'h00;
7'h44: tx_data <= 8'h00;
7'h45: tx_data <= 8'h00;
7'h46: begin // FCS (CRC)
arp_crc_rd <= 1'b1;
tx_data <= arp_crc_out[31:24];
end
7'h47: tx_data <= arp_crc_out[23:16];
7'h48: tx_data <= arp_crc_out[15:8];
7'h49: tx_data <= arp_crc_out[7:0];
7'h4a: begin
tx_en <= 1'b0;
arp_crc_rd <= 1'b0;
tx_data <= 8'h0;
arp_state <= ARP_IDLE;
end
default: tx_data <= 8'h00;
endcase
neighbor_count <= neighbor_count + 7'h1;
end
endcase
end
end
assign gmii_txd = tx_data;
assign gmii_tx_en = tx_en;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Murai Lab
// Engineer: Takeshi Matsuya
//
// Create Date: 21:31:35 10/29/2011
// Design Name:
// Module Name: rgmii_io.v
// Project Name:
// Target Devices:
// Tool versions:
// Description: RGMII to GMII bridge
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: See XAPP692
//
//////////////////////////////////////////////////////////////////////////////////
module rgmii_io
(
//-----------------------------------------------------------------------
//-- Pad side signals
//-----------------------------------------------------------------------
output [3:0] rgmii_txd,
output rgmii_tx_ctl,
input rgmii_tx_clk_int,
input not_rgmii_tx_clk,
input [3:0] rgmii_rxd,
input rgmii_rx_ctl,
input rgmii_rx_clk,
//-----------------------------------------------------------------------
//-- Core side signals
//-----------------------------------------------------------------------
input [7:0] gmii_txd, // Internal gmii_txd signal.
input gmii_tx_en,
input gmii_tx_er,
output [7:0] gmii_rxd,
output gmii_rx_dv,
output gmii_rx_er,
output link,
output [1:0] speed,
output duplex,
input reset
);
//-----------------------------------------------------------------------
//-- RGMII_TXD[3:0]
//-----------------------------------------------------------------------
FDCE fdce_txd0 (
.Q(fdce_txd0_1),
.D (gmii_txd[0]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce_txd1 (
.Q(fdce_txd1_1),
.D (gmii_txd[1]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce_txd2 (
.Q(fdce_txd2_1),
.D (gmii_txd[2]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce_txd3 (
.Q(fdce_txd3_1),
.D (gmii_txd[3]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_txd4 (
.Q(fdce_txd4_1),
.D (gmii_txd[4]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_txd5 (
.Q(fdce_txd5_1),
.D (gmii_txd[5]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_txd6 (
.Q(fdce_txd6_1),
.D (gmii_txd[6]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_txd7 (
.Q(fdce_txd7_1),
.D (gmii_txd[7]),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
wire [3:0] rgmii_txd_obuf;
FDDRRSE fddrse_txd0 (
.Q (rgmii_txd_obuf[0]),
.D0(fdce_txd0_1),
.D1(fdce_txd4_1),
.C0(rgmii_tx_clk_int),
.C1(not_rgmii_tx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDDRRSE fddrse_txd1 (
.Q (rgmii_txd_obuf[1]),
.D0(fdce_txd1_1),
.D1(fdce_txd5_1),
.C0(rgmii_tx_clk_int),
.C1(not_rgmii_tx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDDRRSE fddrse_txd2 (
.Q (rgmii_txd_obuf[2]),
.D0(fdce_txd2_1),
.D1(fdce_txd6_1),
.C0(rgmii_tx_clk_int),
.C1(not_rgmii_tx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDDRRSE fddrse_txd3 (
.Q (rgmii_txd_obuf[3]),
.D0(fdce_txd3_1),
.D1(fdce_txd7_1),
.C0(rgmii_tx_clk_int),
.C1(not_rgmii_tx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
OBUF drive_rgmii_txd0 (.I(rgmii_txd_obuf[0]), .O(rgmii_txd[0]));
OBUF drive_rgmii_txd1 (.I(rgmii_txd_obuf[1]), .O(rgmii_txd[1]));
OBUF drive_rgmii_txd2 (.I(rgmii_txd_obuf[2]), .O(rgmii_txd[2]));
OBUF drive_rgmii_txd3 (.I(rgmii_txd_obuf[3]), .O(rgmii_txd[3]));
//-----------------------------------------------------------------------
//-- RGMII_TX_CTL
//-----------------------------------------------------------------------
assign tx_en_xor_tx_er = gmii_tx_en ^ gmii_tx_er;
FDCE fdce_txen (
.Q(fdce_txen_1),
.D (gmii_tx_en),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce_txer (
.Q(fdce_txer_1),
.D (tx_en_xor_tx_er),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce1_txer (
.Q(fdce1_txer_1),
.D (fdce_txer_1),
.C (rgmii_tx_clk_int),
.CE(1'b1),
.CLR(reset)
);
wire rgmii_tx_ctl_obuf;
FDDRRSE fddrse_txctl (
.Q (rgmii_tx_ctl_obuf),
.D0(fdce_txen_1),
.D1(fdce1_txer_1),
.C0(rgmii_tx_clk_int),
.C1(not_rgmii_tx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
OBUF drive_rgmii_txctl (.I(rgmii_tx_ctl_obuf), .O(rgmii_tx_ctl));
assign not_rgmii_rx_clk = ~rgmii_rx_clk;
//-----------------------------------------------------------------------
//-- RGMII_RXD[3:0]
//-----------------------------------------------------------------------
IFDDRRSE ifddrse_rxd0 (
.Q0(ifddrse_rxd0_1),
.Q1(ifddrse_rxd0_2),
.D (rgmii_rxd[0]),
.C0(rgmii_rx_clk),
.C1(not_rgmii_rx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
IFDDRRSE ifddrse_rxd1 (
.Q0(ifddrse_rxd1_1),
.Q1(ifddrse_rxd1_2),
.D (rgmii_rxd[1]),
.C0(rgmii_rx_clk),
.C1(not_rgmii_rx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
IFDDRRSE ifddrse_rxd2 (
.Q0(ifddrse_rxd2_1),
.Q1(ifddrse_rxd2_2),
.D (rgmii_rxd[2]),
.C0(rgmii_rx_clk),
.C1(not_rgmii_rx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
IFDDRRSE ifddrse_rxd3 (
.Q0(ifddrse_rxd3_1),
.Q1(ifddrse_rxd3_2),
.D (rgmii_rxd[3]),
.C0(rgmii_rx_clk),
.C1(not_rgmii_rx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDCE fdce_rxd0 (
.Q(fdce_rxd0_1),
.D (ifddrse_rxd0_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce_rxd1 (
.Q(fdce_rxd1_1),
.D (ifddrse_rxd1_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce_rxd2 (
.Q(fdce_rxd2_1),
.D (ifddrse_rxd2_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce_rxd3 (
.Q(fdce_rxd3_1),
.D (ifddrse_rxd3_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_rxd4 (
.Q(fdce_rxd4_1),
.D (ifddrse_rxd0_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_rxd5 (
.Q(fdce_rxd5_1),
.D (ifddrse_rxd1_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_rxd6 (
.Q(fdce_rxd6_1),
.D (ifddrse_rxd2_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_rxd7 (
.Q(fdce_rxd7_1),
.D (ifddrse_rxd3_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd0 (
.Q(fdce_rxd0_2),
.D (fdce_rxd0_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd1 (
.Q(fdce_rxd1_2),
.D (fdce_rxd1_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd2 (
.Q(fdce_rxd2_2),
.D (fdce_rxd2_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd3 (
.Q(fdce_rxd3_2),
.D (fdce_rxd3_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd4 (
.Q(fdce_rxd4_2),
.D (fdce_rxd4_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd5 (
.Q(fdce_rxd5_2),
.D (fdce_rxd5_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd6 (
.Q(fdce_rxd6_2),
.D (fdce_rxd6_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxd7 (
.Q(fdce_rxd7_2),
.D (fdce_rxd7_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd0 (
.Q (gmii_rxd[0]),
.D (fdce_rxd0_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd1 (
.Q (gmii_rxd[1]),
.D (fdce_rxd1_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd2 (
.Q (gmii_rxd[2]),
.D (fdce_rxd2_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd3 (
.Q (gmii_rxd[3]),
.D (fdce_rxd3_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd4 (
.Q (gmii_rxd[4]),
.D (fdce_rxd4_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd5 (
.Q (gmii_rxd[5]),
.D (fdce_rxd5_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd6 (
.Q (gmii_rxd[6]),
.D (fdce_rxd6_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxd7 (
.Q (gmii_rxd[7]),
.D (fdce_rxd7_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
//-----------------------------------------------------------------------
//-- RGMII_RX_CTL
//-----------------------------------------------------------------------
IFDDRRSE ifddrse_rxctl (
.Q0(ifddrse_rxctl_1),
.Q1(ifddrse_rxctl_2),
.D (rgmii_rx_ctl),
.C0(rgmii_rx_clk),
.C1(not_rgmii_rx_clk),
.CE(1'b1),
.R (reset),
.S (1'b0)
);
FDCE fdce_rxctl1 (
.Q (fdce_rxctl1_1),
.D (ifddrse_rxctl_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE_1 fdce_rxctl2 (
.Q (fdce_rxctl2_1),
.D (ifddrse_rxctl_2),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxctl1 (
.Q (fdce2_rxctl1_1),
.D (fdce_rxctl1_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce2_rxctl2 (
.Q (fdce2_rxctl2_1),
.D (fdce_rxctl2_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
FDCE fdce3_rxctl1 (
.Q (gmii_rx_dv),
.D (fdce2_rxctl1_1),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
assign fdce_xor = fdce_rxctl1_1 ^ fdce_rxctl2_1;
FDCE fdce3_rxctl2 (
.Q (gmii_rx_er),
.D (fdce_xor),
.C (rgmii_rx_clk),
.CE(1'b1),
.CLR(reset)
);
//-----------------------------------------------------------------------
//-- RGMII_STATUS
//-----------------------------------------------------------------------
assign ce = ~(gmii_rx_dv | gmii_rx_er);
FDRSE fdrse_link (
.Q (link),
.D (gmii_rxd[0]),
.C (rgmii_rx_clk),
.CE(ce),
.R (RESET),
.S (1'b0)
);
FDRSE fdrse_speed0 (
.Q (speed[0]),
.D (gmii_rxd[0]),
.C (rgmii_rx_clk),
.CE(ce),
.R (RESET),
.S (1'b0)
);
FDRSE fdrse_speed1 (
.Q (speed[1]),
.D (gmii_rxd[0]),
.C (rgmii_rx_clk),
.CE(ce),
.R (RESET),
.S (1'b0)
);
FDRSE fdrse_duplex (
.Q (duplex),
.D (gmii_rxd[0]),
.C (rgmii_rx_clk),
.CE(ce),
.R (RESET),
.S (1'b0)
);
endmodule // rgmii_io
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_57x64.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_57x64 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrempty,
wrfull,
wrusedw);
input aclr;
input [56:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [56:0] q;
output rdempty;
output wrempty;
output wrfull;
output [5:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "57"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "57"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "57"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 57 0 INPUT NODEFVAL "data[56..0]"
// Retrieval info: USED_PORT: q 0 0 57 0 OUTPUT NODEFVAL "q[56..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL "wrempty"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 6 0 OUTPUT NODEFVAL "wrusedw[5..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 57 0 data 0 0 57 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 57 0 @q 0 0 57 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: wrusedw 0 0 6 0 @wrusedw 0 0 6 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_57x64_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_1_V
`define SKY130_FD_SC_MS__EBUFN_1_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_1 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ebufn_1 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_1_V
|
/***********************************************************************
Interface for FTDI FT2232H in FT245 synchronous FIFO mode
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
Implements the interface to the FT245 Sync FIFO protocol. Fully
registered.
To Do:
-
Author:
- Marc Pignat, marc at pignat dot org
- Salvador E. Tropea, salvador en inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2015-2016 Marc Pignat
Copyright (c) 2017 Salvador E. Tropea <salvador en inti.gob.ar>
Copyright (c) 2017 Instituto Nacional de Tecnología Industrial
Distributed under Apache License Version 2.0
------------------------------------------------------------------------------
Design unit: LA_1(RTL) (Entity and architecture)
File name: ft245_sync_if.v
Note: None
Limitations: None known
Errors: None known
Library: avr
Dependencies: IEEE.std_logic_1164
IEEE.numeric_std
utils.stdlib
mems.devices
Target FPGA: iCE40HX4K-TQ144
Language: Verilog
Wishbone: None
Synthesis tools: Lattice iCECube2 2017.01.27914
Simulation tools: GHDL [Dunoon edition] (0.3x)
Text editor: SETEdit 0.5.x
***********************************************************************/
//
// Usage
//
// * This block MUST be clocked by the FTDI chip
//
// * FTDI Signals MUST be connected directly and tied into the IO pads.
// * For Xilinx FPGA, nothing has to be done since the "iob" attribute is set.
// * Same for Lattice iCE40
//
// * Host code at https://github.com/RandomReaper/ft2tcp
/////////////////////////////////////////////////////////////////////////////
//
// * FPGA -> FTDI
// Sending data to the FTDI chip is done using tx_* signals.
// Example: Sending 2 bytes:
// ____ ____ ____ ____ ____ ____
// clk_i ___/ \___/ \/\/\/\/ \___/ \___/ \___/ \____
//
// ____t1 t4__________________
// tx_empty (in) \____________________________/
//
// t2________________
// tx_read (out) _______________| \__________________
//
// t3
// tx_data (in) /////////////////////////< D0 >< D1 >/////////
//
// At t1, tx_empty is set to '0'.
//
// At t2, (after an unknown number of clock cycles) the ft245_sync_if is
// ready for sendind data and set tx_read to '1'.
//
// At t3, (one clock after tx_read) The data (D0) is on tx_data.
//
// At t4, tx_data contains the last data, tx_empty is set '0'. The
// ft245_sync_if sets tx_read to '0' at the same time.
//
// Note : This burst can be interrupted (tx_read will go to '0', when the
// FTDI chip FIFO is full.
//
/////////////////////////////////////////////////////////////////////////////
//
// * FTDI -> FPGA
// Receiving data from the FTDI chip is done using rx_* signals.
// Example: Receiving 2 bytes:
// ____ ____ ____ ____ ____ ____
// clk_i ___/ \___/ \/\/\/\/ \___/ \___/ \___/ \____
//
// ____t1 __________________
// rx_full (in) \____________________________/___________________
//
// t2________________t4
// rx_valid (out) _____________| \__________________
//
// t3
// rx_data (out) //////////////< D0 >< D1 >/////////
//
// At t1, the rx_full is set to '0'.
//
// At t2, (after an unknown number of clock cycles) and when the FTDI chip has
// received data the ft245_sync_if set rx_valid to '1' and set data
// on data out.
//
// At t3, There is a new data on every clock on rx_data
//
// At t4, rx_valid goes '0' (no more data).
//
// Note : Data receive can be interrupted at any time by setting rx_full to
// '1' at any time.
//
/////////////////////////////////////////////////////////////////////////////
// Note: wr_n_o and oe_n_o must be 1 for t=0, otherwise the FT chip could
// interpret a write and/or enable its outputs.
// Since defining their value to 1 for t=0 doesn't work we need an
// asynchronous reset asserted from t=0. This reset *MUST* be
// sincronized with the clock to avoid short reset pulses.
// Force signals into IO pads
// Warning XST specific syntax (not verified)
//synthesis attribute IOB of rxf_n_i is "FORCE"
//synthesis attribute IOB of txe_n_i is "FORCE"
//synthesis attribute IOB of rd_n_o is "FORCE"
//synthesis attribute IOB of wr_n_o is "FORCE"
//synthesis attribute IOB of oe_n_o is "FORCE"
//synthesis attribute IOB of siwu_o is "FORCE"
localparam // state_r
// State to wait for signals to settle down (isn't usually needed)
ST_RESET=0,
ST_IDLE=1,
// 2 waits:
// 1 to compensate the output register
// 1 mandatory before read
ST_WAIT_READ1=2,
ST_WAIT_READ2=3,
ST_READ=4,
ST_READ_OLD=5,
// After a read we disable the FT outputs, but this
// is delayed 1 cycle. The second is just an extra
// guard.
ST_AFTER_READ1=6,
ST_AFTER_READ2=7,
ST_WRITE=8,
ST_WRITE_OLD=9;
// State
reg [3:0] state_r=ST_RESET;
reg [3:0] next_state; // logic
// Positive versions of ft245 control signals
// Output signals (FPGA -> FTDI) before output FFs
wire ft_oe;
wire ft_wr;
wire ft_rd;
// Input signals (FTDI -> FPGA) registered
reg ft_txe_r=0;
reg ft_rxf_r=0;
// Data RX
reg [7:0] rx_data_old[1:0];
`define rx_data_old_a { rx_data_old[1], rx_data_old[0] }
reg [1:0] rx_valid_old;
reg [7:0] rx_data_r;
wire oe;
wire rx_valid;
wire ft_read_ok;
wire fpga_read_ok;
reg [1:0] ft_rd_old;
wire rx_pending;
// Data TX
reg [7:0] tx_data_old[2:0];
`define tx_data_old_a { tx_data_old[2], tx_data_old[1], tx_data_old[0] }
reg [2:0] tx_valid_old;
reg [1:0] ft_wr_old;
reg write_failed=0;
reg [1:0] old_counter=0;
wire tx_read_int;
reg tx_read_old=0;
reg [7:0] tx_data_r;
// Force signals into IO pads
// Warning XST specific syntax
//synthesis attribute IOB of tx_data_r is "FORCE"
//synthesis attribute IOB of ft_rxf_r is "FORCE"
//synthesis attribute IOB of ft_rxf_r is "FORCE"
reg rd_n;
reg wr_n;
reg oe_n;
assign rd_n_o=rd_n;
assign wr_n_o=wr_n;
assign oe_n_o=oe_n;
/////////////////////////////////////////////////////////////////////////////
// Ports
/////////////////////////////////////////////////////////////////////////////
// Unused output (Send Immediate/Wake-Up), must be 1 if not used
assign siwu_o=1'b1;
// Tristate for the data bus
assign adbus_io=oe ? tx_data_r : 8'bZ;
// Synchronize input signals
// Note: This core synchronize all signals to/from the FT chip.
// This makes much more easy to comply with the time constraints and
// provides very good signal integrity. The cost is a much more
// complex FSM.
always @(posedge clk_i or posedge rst_i)
begin : in_sync
if (rst_i)
begin
rx_data_r <= 8'b0;
ft_txe_r <= 1'b0;
ft_rxf_r <= 1'b0;
end
else
begin
rx_data_r <= adbus_io;
ft_txe_r <= ~txe_n_i;
ft_rxf_r <= ~rxf_n_i;
end
end // in_sync
// Synchronize output signals
always @(posedge clk_i or posedge rst_i)
begin : out_sync
if (rst_i)
begin
tx_data_r <= 8'b0;
rd_n <= 1'b1;
// The following two signals MUST be 1 for t=0
// On iCE40 it means async reset
wr_n <= 1'b1;
oe_n <= 1'b1;
end
else
begin
rd_n <= ~ft_rd;
wr_n <= ~ft_wr;
oe_n <= ~ft_oe;
if (state_r==ST_WRITE_OLD)
tx_data_r <= tx_data_old[2];
else
tx_data_r <= tx_data_i;
end
end // out_sync
/////////////////////////////////////////////////////////////////////////////
// State machine
/////////////////////////////////////////////////////////////////////////////
always @(posedge clk_i or posedge rst_i)
begin : state_machine
if (rst_i)
begin
if (USE_STATE_RESET)
state_r <= ST_RESET;
else
state_r <= ST_IDLE;
end
else
state_r <= next_state;
end // state_machine
always @*
begin : state_machine_next
next_state <= state_r;
case (state_r)
ST_RESET: next_state <= ST_IDLE;
ST_IDLE:
begin
// The FT chip can accept data
if (ft_txe_r)
begin
if (write_failed)
// We have pending data to transmit
next_state <= ST_WRITE_OLD;
else if (!tx_empty_i)
// The FPGA side has data to transmit
next_state <= ST_WRITE;
end
// The FPGA side can accept data
// Reading has more priority
if (!rx_full_i)
begin
if (rx_pending)
// We have a pending read queued
next_state <= ST_READ_OLD;
else if (ft_rxf_r)
// The FT has data
next_state <= ST_WAIT_READ1;
end
end // ST_IDLE
ST_WAIT_READ1:
// Here we enable the FT outputs
// As this signal is registered it will enable the FT 1 cycle later
next_state <= ST_WAIT_READ2;
ST_WAIT_READ2:
// Here the OE# is asserted, but it must be asserted 1 cycle before
// read according to the datasheet.
next_state <= ST_READ;
ST_READ:
if (!ft_rxf_r || rx_full_i)
// The FT RX FIFO is empty or the FPGA side is full
next_state <= ST_AFTER_READ1;
ST_AFTER_READ1:
if (EXTRA_READ_GUARD)
next_state <= ST_AFTER_READ2;
else
next_state <= ST_IDLE;
ST_AFTER_READ2: next_state <= ST_IDLE;
ST_WRITE:
if (!ft_txe_r || tx_empty_i)
// The FT TX FIFO is full or the FPGA side is empty
next_state <= ST_IDLE;
ST_WRITE_OLD:
if (old_counter==2)
begin
next_state <= ST_IDLE;
// This eliminates an extra stop in the flow, but takes
// 7 extra LUTs
if (FAST_WRITE_OLD && ft_txe_r && !tx_empty_i)
next_state <= ST_WRITE;
end
ST_READ_OLD:
if (!rx_pending || rx_full_i)
// No more pending data or the FPGA side is full
next_state <= ST_IDLE;
endcase
end // state_machine_next
// ft_oe and oe are not driven simultaneously to avoid bus contention.
assign ft_oe=state_r==ST_WAIT_READ1 || state_r==ST_WAIT_READ2 || state_r==ST_READ;
assign oe=~(state_r==ST_WAIT_READ1 || state_r==ST_WAIT_READ2 || state_r==ST_READ ||
state_r==ST_AFTER_READ1 || state_r==ST_AFTER_READ2);
/////////////////////////////////////////////////////////////////////////////
// RX data
/////////////////////////////////////////////////////////////////////////////
// All inputs and outputs are registered, so we don't know if a read from
// the FTDI was succesful until it already happened.
// This is why we store the data and its status in a buffer.
// We start reading 1 cycle before READ state.
// We stop as soon as the FPGA side is full.
assign ft_rd=state_r==ST_WAIT_READ2 || state_r==ST_READ ? ~rx_full_i : 1'b0;
// RD# signal delayed to compare with its corresponding RXF# value
// We assert RD# but we don't know if RXF# will be asserted when ft_rd
// reaches the outside world.
always @(posedge clk_i or posedge rst_i)
begin : old_rx
if (rst_i)
ft_rd_old <= 2'b0;
else
ft_rd_old <= { ft_rd_old[0], ft_rd };
end // old_rx
assign ft_read_ok=ft_rd_old[1] & ft_rxf_r;
// This buffer is used to store the reads from the FTDI that we couldn't
// dispatch. We have 2 cycles delay (1 register in + 1 register out) so we
// need to store upto 2 values.
// We store data when the FTDI read succeed and the FPGA side is full.
// We retire data in ST_READ_OLD when the FPGA isn't full.
always @(posedge clk_i or posedge rst_i)
begin : do_rx_pipe
if (rst_i)
begin
`rx_data_old_a <= {2{8'b0}};
rx_valid_old <= {2{1'b0}};
end
else
if ((ft_read_ok && !fpga_read_ok) || // Read but full
(state_r==ST_READ_OLD && !rx_full_i)) // Retire
begin
`rx_data_old_a <= { rx_data_old[0], rx_data_r };
rx_valid_old <= { rx_valid_old[0], ft_read_ok };
end
end // do_rx_pipe
// At least 1 of the 2 slots has data
assign rx_pending=rx_valid_old!=0;
// A valid read (from FTDI or stored data)
assign rx_valid= state_r==ST_READ ? ft_read_ok : // Valid read from FT FIFO
(state_r==ST_READ_OLD ? rx_valid_old[1] : 1'b0); // Queued data
assign fpga_read_ok=rx_valid & ~rx_full_i;
// Avoid asserting rx_valid when the FPGA side is full.
assign rx_valid_o=fpga_read_ok;
// Here we use the pending data buffer in the ST_READ_OLD
assign rx_data_o=state_r==ST_READ_OLD ? rx_data_old[1] : rx_data_r;
/////////////////////////////////////////////////////////////////////////////
// TX data
/////////////////////////////////////////////////////////////////////////////
// Here we also have a problem of not detecting a Tx fail when this is too
// late. To the two cycles problem we have in the Rx part we must add the
// fact that we are reading 1 byte ahead (to compensate for FPGA BRAMs).
// So here we when we fail we have to retry 3 bytes.
// We start reading data from the FPGA side 1 cycle before write.
// If the FT Tx FIFO gets full we stop.
assign tx_read_int=next_state==ST_WRITE ? ft_txe_r : 1'b0;
assign tx_read_o=tx_read_int;
// As with the Rx we need a delayed version of WR# to compare
always @(posedge clk_i or posedge rst_i)
begin : old_tx
if (rst_i)
ft_wr_old <= 2'b0;
else
ft_wr_old <= { ft_wr_old[0], ft_wr };
end // old_tx
// Delayed version of the tx_read_o signal
always @(posedge clk_i or posedge rst_i)
begin : tx_read_old_proc
if (rst_i)
tx_read_old <= 1'b0;
else
tx_read_old <= tx_read_int;
end // tx_read_old_proc
always @(posedge clk_i or posedge rst_i)
begin : do_tx_fifo
if (rst_i)
begin
`tx_data_old_a <= {2{8'b0}};
tx_valid_old <= {2{1'b0}};
old_counter <= 2'b0;
write_failed <= 1'b0;
end
else
begin
if (!write_failed)
begin
// Normal case: no write fail:
// Keep track of the data we tried to write.
// If we detect a fail we will send it again.
`tx_data_old_a <= { tx_data_old[1], tx_data_old[0], tx_data_i };
tx_valid_old <= { tx_valid_old[1:0], tx_read_old };
end
if (ft_wr_old[1] && !ft_txe_r)
// We asserted WR# but TXE# wasn't, a write failed
write_failed <= 1'b1;
if (tx_read_old && !ft_txe_r)
// We retired a value but TXE# was low
write_failed <= 1'b1;
if (state_r==ST_WRITE_OLD)
begin
// Retire one value and fill with 0
old_counter <= old_counter+1;
tx_valid_old <= { tx_valid_old[1:0], 1'b0 };
`tx_data_old_a <= { tx_data_old[1], tx_data_old[0], 8'b0 };
if (old_counter==2)
begin
// No more data to retire, we go to IDLE and reset the
// write_failed flag
old_counter <= 2'b0;
write_failed <= 1'b0;
end
end // state_r==ST_WRITE_OLD
end // !rst_i
end // do_tx_fifo
// FT WR# signal:
// In the ST_WRITE reflect the FPGA FIFO status (if FT has space we write)
// In the ST_WRITE_OLD we use the data from the buffer
assign ft_wr= state_r==ST_WRITE ? ft_txe_r :
(state_r==ST_WRITE_OLD ? tx_valid_old[2] : 0);
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:50:00 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ DemoInterconnect_clk_wiz_0_0_sim_netlist.v
// Design : DemoInterconnect_clk_wiz_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
uart,
reset,
locked,
clk_in1);
output aclk;
output uart;
input reset;
output locked;
input clk_in1;
wire aclk;
(* IBUF_LOW_PWR *) wire clk_in1;
wire locked;
wire reset;
wire uart;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_DemoInterconnect_clk_wiz_0_0_clk_wiz inst
(.aclk(aclk),
.clk_in1(clk_in1),
.locked(locked),
.reset(reset),
.uart(uart));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_DemoInterconnect_clk_wiz_0_0_clk_wiz
(aclk,
uart,
reset,
locked,
clk_in1);
output aclk;
output uart;
input reset;
output locked;
input clk_in1;
wire aclk;
wire aclk_DemoInterconnect_clk_wiz_0_0;
wire aclk_DemoInterconnect_clk_wiz_0_0_en_clk;
wire clk_in1;
wire clk_in1_DemoInterconnect_clk_wiz_0_0;
wire clkfbout_DemoInterconnect_clk_wiz_0_0;
wire clkfbout_buf_DemoInterconnect_clk_wiz_0_0;
wire locked;
wire reset;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [7:0]seq_reg1;
(* RTL_KEEP = "true" *) (* async_reg = "true" *) wire [7:0]seq_reg2;
wire uart;
wire uart_DemoInterconnect_clk_wiz_0_0;
wire uart_DemoInterconnect_clk_wiz_0_0_en_clk;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_DemoInterconnect_clk_wiz_0_0),
.O(clkfbout_buf_DemoInterconnect_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_DemoInterconnect_clk_wiz_0_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "BUFGCE" *)
(* XILINX_TRANSFORM_PINMAP = "CE:CE0 I:I0" *)
BUFGCTRL #(
.INIT_OUT(0),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE"))
clkout1_buf
(.CE0(seq_reg1[7]),
.CE1(1'b0),
.I0(aclk_DemoInterconnect_clk_wiz_0_0),
.I1(1'b1),
.IGNORE0(1'b0),
.IGNORE1(1'b1),
.O(aclk),
.S0(1'b1),
.S1(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFH clkout1_buf_en
(.I(aclk_DemoInterconnect_clk_wiz_0_0),
.O(aclk_DemoInterconnect_clk_wiz_0_0_en_clk));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "BUFGCE" *)
(* XILINX_TRANSFORM_PINMAP = "CE:CE0 I:I0" *)
BUFGCTRL #(
.INIT_OUT(0),
.PRESELECT_I0("TRUE"),
.PRESELECT_I1("FALSE"))
clkout2_buf
(.CE0(seq_reg2[7]),
.CE1(1'b0),
.I0(uart_DemoInterconnect_clk_wiz_0_0),
.I1(1'b1),
.IGNORE0(1'b0),
.IGNORE1(1'b1),
.O(uart),
.S0(1'b1),
.S1(1'b0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFH clkout2_buf_en
(.I(uart_DemoInterconnect_clk_wiz_0_0),
.O(uart_DemoInterconnect_clk_wiz_0_0_en_clk));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("HIGH"),
.CLKFBOUT_MULT_F(63.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(83.333000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.500000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(63),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_DemoInterconnect_clk_wiz_0_0),
.CLKFBOUT(clkfbout_DemoInterconnect_clk_wiz_0_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_DemoInterconnect_clk_wiz_0_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(aclk_DemoInterconnect_clk_wiz_0_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(uart_DemoInterconnect_clk_wiz_0_0),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[0]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(locked),
.Q(seq_reg1[0]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[1]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg1[0]),
.Q(seq_reg1[1]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[2]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg1[1]),
.Q(seq_reg1[2]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[3]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg1[2]),
.Q(seq_reg1[3]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[4]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg1[3]),
.Q(seq_reg1[4]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[5]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg1[4]),
.Q(seq_reg1[5]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[6]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg1[5]),
.Q(seq_reg1[6]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg1_reg[7]
(.C(aclk_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg1[6]),
.Q(seq_reg1[7]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[0]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(locked),
.Q(seq_reg2[0]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[1]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg2[0]),
.Q(seq_reg2[1]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[2]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg2[1]),
.Q(seq_reg2[2]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[3]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg2[2]),
.Q(seq_reg2[3]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[4]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg2[3]),
.Q(seq_reg2[4]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[5]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg2[4]),
.Q(seq_reg2[5]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[6]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg2[5]),
.Q(seq_reg2[6]));
(* ASYNC_REG *)
FDCE #(
.INIT(1'b0))
\seq_reg2_reg[7]
(.C(uart_DemoInterconnect_clk_wiz_0_0_en_clk),
.CE(1'b1),
.CLR(reset),
.D(seq_reg2[6]),
.Q(seq_reg2[7]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ADC channel-
`timescale 1ns/100ps
module axi_ad9625_channel (
// adc interface
adc_clk,
adc_rst,
adc_data,
adc_or,
// channel interface
adc_dfmt_data,
adc_enable,
up_adc_pn_err,
up_adc_pn_oos,
up_adc_or,
// processor interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// adc interface
input adc_clk;
input adc_rst;
input [191:0] adc_data;
input adc_or;
// channel interface
output [255:0] adc_dfmt_data;
output adc_enable;
output up_adc_pn_err;
output up_adc_pn_oos;
output up_adc_or;
// processor interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal signals
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
wire [ 3:0] adc_pnseq_sel_s;
// instantiations
axi_ad9625_pnmon i_pnmon (
.adc_clk (adc_clk),
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pnseq_sel (adc_pnseq_sel_s));
genvar n;
generate
for (n = 0; n < 16; n = n + 1) begin: g_ad_datafmt_1
ad_datafmt #(.DATA_WIDTH(12)) i_ad_datafmt (
.clk (adc_clk),
.valid (1'b1),
.data (adc_data[n*12+11:n*12]),
.valid_out (),
.data_out (adc_dfmt_data[n*16+15:n*16]),
.dfmt_enable (adc_dfmt_enable_s),
.dfmt_type (adc_dfmt_type_s),
.dfmt_se (adc_dfmt_se_s));
end
endgenerate
up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),
.up_adc_pn_err (up_adc_pn_err),
.up_adc_pn_oos (up_adc_pn_oos),
.up_adc_or (up_adc_or),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd16),
.adc_usr_datatype_bits (8'd16),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p/sky130_fd_sc_hvl__udp_dff_p.v"
`celldefine
module sky130_fd_sc_hvl__dfxtp (
Q ,
CLK,
D
);
// Module ports
output Q ;
input CLK;
input D ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_hvl__udp_dff$P `UNIT_DELAY dff0 (buf_Q , D, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFXTP_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: icd2
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module sgb_icd2(
input RST,
output CPU_RST,
input CLK,
input CLK_SYSCLK,
output CLK_CPU_EDGE,
// MMIO interface
input SNES_RD_start,
input SNES_WR_end,
input [23:0] SNES_ADDR,
input [7:0] DATA_IN,
output [7:0] DATA_OUT,
input BOOTROM_ACTIVE,
// Pixel interface
input PPU_DOT_EDGE,
input PPU_PIXEL_VALID,
input [1:0] PPU_PIXEL,
input PPU_VSYNC_EDGE,
input PPU_HSYNC_EDGE,
// Button/Serial interface
input [1:0] P1I,
output [3:0] P1O,
// Halt interface
output IDL,
// Features
input [15:0] FEAT,
// Debug state
input [11:0] DBG_ADDR,
output [7:0] DBG_DATA_OUT
);
integer i;
//-------------------------------------------------------------------
// DESCRIPTION
//-------------------------------------------------------------------
// The ICD2 interfaces the SNES with the SGB via two points:
// SNES - cartridge bus
// SGB - pixel output, button/serial
//
// The pixel interface takes the 2b PPU output and renders it back into a SNES
// 2bpp planar format before writing into 1 of 4 row (scanline) buffers.
// The 2b button interface serves as a way for the SGB to get the controller
// state from the SNES via ICD2 registers written over the SNES cart bus.
// The serial interface overloads the 2b button interface to transfer
// 16B packets to the SNES. The SGB boot ROMs use this to transfer a
// portion of the GB header. GB games may also be customized to generate these
// packets for SGB-enhanced content.
//-------------------------------------------------------------------
// Clocks
//-------------------------------------------------------------------
// GB Crystal - 20.97152 MHz
// GB CPU Frequency - 4.194304 MHz
// GB Bus Frequency - 1.048576 MHz
// To approximate the SGB2 frequency the SD2SNES implements a 84 MHz
// base clock which may be further divided down. With a skip
// clock every 737 base clocks the effective base frequency is:
// 84 MHz * 736 / 737 = 83.886024 MHz
// With /20 the frequency is roughly .000024% slower than the original SGB2.
//
// The CPU implementation is pipelined into a fetch and execute stage.
// Each stage is multiple base clocks some of which may be idle to
// pad out to the equivalent SGB2 clock.
//
// The clock logic generates clock edge signals in the base clock
// domain.
//
// The SGB supports a /4, /5 (default), /7, and /9 clock. This is
// accounted for by adjusting the number of base clocks per CPU clock
// assertion.
reg [9:0] clk_skp_ctr_r; // in base domain
reg [5:0] clk_cpu_ctr_r; // in base domain
reg [2:0] clk_sys_r;
reg [3:0] clk_cpu_snes_ctr_r;
reg [1:0] clk_mult_r;
reg clk_cpu_edge_r;
wire [1:0] clk_mult;
// assert on 736
assign clk_skp_ast = clk_skp_ctr_r[9] & &clk_skp_ctr_r[7:5];
// check for 15, 19, 27, and 35 based on divisor
assign clk_cpu_ast = ( ~clk_skp_ast
& ( (~clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_ctr_r[3:0] ) // 16-1
| (~clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_ctr_r[4:4] & &clk_cpu_ctr_r[1:0]) // 20-1
| ( clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_ctr_r[4:3] & &clk_cpu_ctr_r[1:0]) // 28-1
| ( clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_ctr_r[5:5] & &clk_cpu_ctr_r[1:0]) // 36-1
)
);
wire clk_sysclk_edge = (clk_sys_r[2:1] == 2'b01);
assign clk_cpu_snes_ast = ( clk_sysclk_edge
& ( (~clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_snes_ctr_r[1:0]) // 4-1
| (~clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_snes_ctr_r[2:2]) // 5-1
| ( clk_mult_r[1] & ~clk_mult_r[0] & &clk_cpu_snes_ctr_r[2:1]) // 7-1
| ( clk_mult_r[1] & clk_mult_r[0] & &clk_cpu_snes_ctr_r[3:3]) // 9-1
)
);
assign CLK_CPU_EDGE = clk_cpu_edge_r;
always @(posedge CLK) begin
if (RST) begin
clk_skp_ctr_r <= 0;
clk_cpu_ctr_r <= 0;
clk_sys_r <= 0;
clk_cpu_snes_ctr_r <= 0;
end
else begin
clk_skp_ctr_r <= clk_skp_ast ? 0 : clk_skp_ctr_r + 1;
// The CPU clock absorbs the skip clock since it's the primary that feeds all GB logic
clk_cpu_ctr_r <= clk_skp_ast ? clk_cpu_ctr_r : (clk_cpu_ast ? 0 : (clk_cpu_ctr_r + 1));
clk_sys_r <= {clk_sys_r[1:0], CLK_SYSCLK};
clk_cpu_snes_ctr_r <= ~clk_sysclk_edge ? clk_cpu_snes_ctr_r : (clk_cpu_snes_ast ? 0 : clk_cpu_snes_ctr_r + 1);
// arbitrary point assigned to define edge for cpu clock
clk_cpu_edge_r <= FEAT[`SGB_FEAT_SGB1_TIMING] ? clk_cpu_snes_ast : clk_cpu_ast;
end
end
// Generate a BUS clock edge from the incoming CPU clock edge. The
// BUS clock is always /4.
reg [1:0] clk_bus_ctr_r; always @(posedge CLK) clk_bus_ctr_r <= RST ? 0 : clk_bus_ctr_r + (CLK_CPU_EDGE ? 1 : 0);
wire CLK_BUS_EDGE = CLK_CPU_EDGE & &clk_bus_ctr_r;
// synchronize on bus edge
always @(posedge CLK) if (RST | CLK_BUS_EDGE) clk_mult_r <= clk_mult;
// Add a delay on cold reset since the SNES has to win the race to capture the buffer. Do we need this for CPU reset, too?
reg [15:0] rst_cnt_r;
always @(posedge CLK) if (RST) rst_cnt_r <= -1; else if (CLK_BUS_EDGE & |rst_cnt_r) rst_cnt_r <= rst_cnt_r - 1;
// Synchronize reset to bus edge. Want a full bus clock prior to first edge assertion
reg cpu_ireset_r; always @(posedge CLK) cpu_ireset_r <= RST | CPU_RST | (cpu_ireset_r & ~CLK_BUS_EDGE) | |rst_cnt_r;
//-------------------------------------------------------------------
// Row Buffers
//-------------------------------------------------------------------
`define ROW_CNT 4
wire row_wren[`ROW_CNT-1:0];
wire [8:0] row_address[`ROW_CNT-1:0];
//wire [7:0] row_rddata[`ROW_CNT-1:0];
wire [7:0] row_wrdata[`ROW_CNT-1:0];
//wire icd_row_wren[`ROW_CNT-1:0];
wire [8:0] icd_row_address[`ROW_CNT-1:0];
wire [7:0] icd_row_rddata[`ROW_CNT-1:0];
//wire [7:0] icd_row_wrdata[`ROW_CNT-1:0];
`ifdef MK2
row_buf row0 (
.clka(CLK), // input clka
.wea(row_wren[0]), // input [0 : 0] wea
.addra(row_address[0]), // input [8 : 0] addra
.dina(row_wrdata[0]), // input [7 : 0] dina
//.douta(row_rddata[0]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[0]), // input [0 : 0] web
.addrb(icd_row_address[0]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[0]), // input [7 : 0] dinb
.doutb(icd_row_rddata[0]) // output [7 : 0] doutb
);
row_buf row1 (
.clka(CLK), // input clka
.wea(row_wren[1]), // input [0 : 0] wea
.addra(row_address[1]), // input [8 : 0] addra
.dina(row_wrdata[1]), // input [7 : 0] dina
//.douta(row_rddata[1]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[1]), // input [0 : 0] web
.addrb(icd_row_address[1]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[1]), // input [7 : 0] dinb
.doutb(icd_row_rddata[1]) // output [7 : 0] doutb
);
row_buf row2 (
.clka(CLK), // input clka
.wea(row_wren[2]), // input [0 : 0] wea
.addra(row_address[2]), // input [8 : 0] addra
.dina(row_wrdata[2]), // input [7 : 0] dina
//.douta(row_rddata[2]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[2]), // input [0 : 0] web
.addrb(icd_row_address[2]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[2]), // input [7 : 0] dinb
.doutb(icd_row_rddata[2]) // output [7 : 0] doutb
);
row_buf row3 (
.clka(CLK), // input clka
.wea(row_wren[3]), // input [0 : 0] wea
.addra(row_address[3]), // input [8 : 0] addra
.dina(row_wrdata[3]), // input [7 : 0] dina
//.douta(row_rddata[3]), // output [7 : 0] douta
.clkb(CLK), // input clkb
//.web(icd_row_wren[3]), // input [0 : 0] web
.addrb(icd_row_address[3]), // input [12 : 0] addrb
//.dinb(icd_row_wrdata[3]), // input [7 : 0] dinb
.doutb(icd_row_rddata[3]) // output [7 : 0] doutb
);
`endif
`ifdef MK3
row_buf row0 (
.clock(CLK), // input clka
.wren(row_wren[0]), // input [0 : 0] wea
.wraddress(row_address[0]), // input [8 : 0] addra
.data(row_wrdata[0]), // input [7 : 0] dina
//.q_a(row_rddata[0]), // output [7 : 0] douta
//.wren_b(icd_row_wren[0]), // input [0 : 0] web
.rdaddress(icd_row_address[0]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[0]), // input [7 : 0] dinb
.q(icd_row_rddata[0]) // output [7 : 0] doutb
);
row_buf row1 (
.clock(CLK), // input clka
.wren(row_wren[1]), // input [0 : 0] wea
.wraddress(row_address[1]), // input [8 : 0] addra
.data(row_wrdata[1]), // input [7 : 0] dina
//.q_a(row_rddata[1]), // output [7 : 0] douta
//.wren_b(icd_row_wren[1]), // input [0 : 0] web
.rdaddress(icd_row_address[1]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[1]), // input [7 : 0] dinb
.q(icd_row_rddata[1]) // output [7 : 0] doutb
);
row_buf row2 (
.clock(CLK), // input clka
.wren(row_wren[2]), // input [0 : 0] wea
.wraddress(row_address[2]), // input [8 : 0] addra
.data(row_wrdata[2]), // input [7 : 0] dina
//.q_a(row_rddata[2]), // output [7 : 0] douta
//.wren_b(icd_row_wren[2]), // input [0 : 0] web
.rdaddress(icd_row_address[2]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[2]), // input [7 : 0] dinb
.q(icd_row_rddata[2]) // output [7 : 0] doutb
);
row_buf row3 (
.clock(CLK), // input clka
.wren(row_wren[3]), // input [0 : 0] wea
.wraddress(row_address[3]), // input [8 : 0] addra
.data(row_wrdata[3]), // input [7 : 0] dina
//.q_a(row_rddata[3]), // output [7 : 0] douta
//.wren_b(icd_row_wren[3]), // input [0 : 0] web
.rdaddress(icd_row_address[3]), // input [12 : 0] addrb
//.data_b(icd_row_wrdata[3]), // input [7 : 0] dinb
.q(icd_row_rddata[3]) // output [7 : 0] doutb
);
`endif
//-------------------------------------------------------------------
// REG
//-------------------------------------------------------------------
`define PKT_CNT 16
`define LCDC_ROW_INDEX 1:0
`define LCDC_CHAR_ROW 7:3
reg [7:0] REG_LCDCHW_r; // 6000 R
reg [7:0] REG_LCDCHR_r; // 6001 W
reg [7:0] REG_PKTRDY_r; // 6002 R
reg [7:0] REG_CTL_r; // 6003 W
reg [7:0] REG_PAD_r[3:0]; // 6004-6007 W
reg [7:0] REG_VER_r; // 600F R
reg [7:0] REG_PKT_r[`PKT_CNT-1:0];// 7000-700F R
reg [7:0] REG_CHDAT_r; // 7800 R
reg [7:0] reg_mdr_r;
reg [8:0] reg_row_index_read_r;
reg reg_pktrdy_clear_r;
assign DATA_OUT = reg_mdr_r;
assign CPU_RST = ~REG_CTL_r[7];
assign clk_mult = REG_CTL_r[1:0];
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_LCDCHR_r <= 0; // 6001 W
//REG_CTL_R <= 8'h01;
for (i = 0; i < 4; i = i + 1) REG_PAD_r[i] <= 8'hFF; // 6004-6007 W
REG_VER_r <= 8'h61; // 600F R
REG_CHDAT_r <= 0; // 7800-780F R
reg_row_index_read_r <= 0;
reg_pktrdy_clear_r <= 0;
end
else begin
// It's important to flop the data early in the SNES read cycle so that concurrent
// writes don't cause late changes on the bus which will lead to errors in the SNES.
case (REG_CTL_r[5:4]) // 1(0),2(1),4(3) players enabled. 0 out if not enabled to avoid spurious presses
0: begin REG_PAD_r[1] <= 8'hFF; REG_PAD_r[2] <= 8'hFF; REG_PAD_r[3] <= 8'hFF; end
1: begin REG_PAD_r[2] <= 8'hFF; REG_PAD_r[3] <= 8'hFF; end
endcase
reg_pktrdy_clear_r <= 0;
casez ({SNES_ADDR[22],SNES_ADDR[15:11],7'h00,SNES_ADDR[3:0]})
{1'b0,16'h6000}: if (SNES_RD_start) reg_mdr_r <= REG_LCDCHW_r; // R
{1'b0,16'h6001}: begin
if (SNES_WR_end) begin
REG_LCDCHR_r[`LCDC_ROW_INDEX] <= DATA_IN[`LCDC_ROW_INDEX]; // W
reg_row_index_read_r <= 0;
end
end
{1'b0,16'h6002}: if (SNES_RD_start) reg_mdr_r <= REG_PKTRDY_r; // R
//{1'b0,16'h6003}: if (SNES_WR_end) {REG_CTL_r[7],REG_CTL_r[5:4],REG_CTL_r[1:0]} <= {DATA_IN[7],DATA_IN[5:4],DATA_IN[1:0]}; // W
{1'b0,16'h6004}: if (SNES_WR_end) REG_PAD_r[0] <= DATA_IN; // W
{1'b0,16'h6005}: if (SNES_WR_end) REG_PAD_r[1] <= DATA_IN; // W
{1'b0,16'h6006}: if (SNES_WR_end) REG_PAD_r[2] <= DATA_IN; // W
{1'b0,16'h6007}: if (SNES_WR_end) REG_PAD_r[3] <= DATA_IN; // W
{1'b0,16'h600F}: if (SNES_RD_start) reg_mdr_r <= REG_VER_r; // R
{1'b0,16'h700?}: begin
if (SNES_RD_start) begin
reg_mdr_r <= REG_PKT_r[SNES_ADDR[3:0]];
// pulse PKTRDY clear
if (SNES_ADDR[3:0] == 0) reg_pktrdy_clear_r <= 1;
end
end
{1'b0,16'h7800}: begin
if (SNES_RD_start) begin
reg_mdr_r <= REG_CHDAT_r; // R
reg_row_index_read_r <= reg_row_index_read_r + 1;
end
end
endcase
REG_CHDAT_r <= icd_row_rddata[REG_LCDCHR_r[`LCDC_ROW_INDEX]];
end
// COLD reset forces a complete reinit. Otherwise this register is not affected by a WARM (CPU) reset.
REG_CTL_r <= ( RST ? 8'h01
: ({SNES_ADDR[22],SNES_ADDR[15:11],7'h00,SNES_ADDR[3:0]} == {1'b0,16'h6003} && SNES_WR_end) ? {DATA_IN[7],1'b0,DATA_IN[5:4],2'h0,DATA_IN[1:0]}
: REG_CTL_r
);
end
//-------------------------------------------------------------------
// PIXELS
//-------------------------------------------------------------------
reg [8:0] pix_row_index_r;
reg [2:0] pix_index_r;
reg [7:0] pix_data_r[1:0];
reg [1:0] pix_row_write_r;
reg [8:0] pix_row_index_write_r;
assign row_address[0] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_address[1] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_address[2] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_address[3] = {pix_row_index_write_r[8:1],pix_row_write_r[1]};
assign row_wrdata[0] = pix_data_r[pix_row_write_r[1]];
assign row_wrdata[1] = pix_data_r[pix_row_write_r[1]];
assign row_wrdata[2] = pix_data_r[pix_row_write_r[1]];
assign row_wrdata[3] = pix_data_r[pix_row_write_r[1]];
assign row_wren[0] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 0) ? |pix_row_write_r : 0;
assign row_wren[1] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 1) ? |pix_row_write_r : 0;
assign row_wren[2] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 2) ? |pix_row_write_r : 0;
assign row_wren[3] = (REG_LCDCHW_r[`LCDC_ROW_INDEX] == 3) ? |pix_row_write_r : 0;
assign icd_row_address[0] = reg_row_index_read_r;
assign icd_row_address[1] = reg_row_index_read_r;
assign icd_row_address[2] = reg_row_index_read_r;
assign icd_row_address[3] = reg_row_index_read_r;
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_LCDCHW_r <= 0;
pix_row_index_r <= 0;
pix_index_r <= 0;
pix_row_write_r <= 0;
end
else begin
pix_row_write_r <= {pix_row_write_r[0],1'b0};
if (PPU_DOT_EDGE) begin
if (PPU_PIXEL_VALID) begin
pix_index_r <= pix_index_r + 1;
// pack pixels into 2bpp planar format
{pix_data_r[1][~pix_index_r[2:0]],pix_data_r[0][~pix_index_r[2:0]]} <= PPU_PIXEL;
if (&pix_index_r) begin
pix_row_index_r[8:4] <= pix_row_index_r[8:4] + 1;
pix_row_write_r[0] <= 1;
pix_row_index_write_r <= pix_row_index_r;
end
end
else if (PPU_VSYNC_EDGE) begin
pix_row_index_r[8:4] <= 0;
pix_index_r <= 0;
REG_LCDCHW_r[`LCDC_CHAR_ROW] <= 0;
end
// early advance of line and row buffer write pointer on dot after 2b pixel 159
// fixes occasional flashing line 120 on BMGB (SGB + 4 controllers)
else if (pix_row_index_r[8] & pix_row_index_r[6]/*PPU_HSYNC_EDGE*/) begin
if (~REG_LCDCHW_r[7] | ~REG_LCDCHW_r[4]) begin
pix_row_index_r[3:1] <= pix_row_index_r[3:1] + 1;
pix_row_index_r[8:4] <= 0;
if (pix_row_index_r[3:1] == 3'h7) begin
REG_LCDCHW_r[`LCDC_ROW_INDEX] <= REG_LCDCHW_r[`LCDC_ROW_INDEX] + 1;
REG_LCDCHW_r[`LCDC_CHAR_ROW] <= REG_LCDCHW_r[`LCDC_CHAR_ROW] + 1;
end
end
end
end
end
end
//-------------------------------------------------------------------
// BUTTON/SERIAL
//-------------------------------------------------------------------
parameter
ST_BTN_IDLE = 4'b0001,
ST_BTN_RECV = 4'b0010,
ST_BTN_WAIT = 4'b0100,
ST_BTN_END = 4'b1000;
reg [3:0] btn_state_r;
reg [3:0] btn_state_next_r;
reg [1:0] btn_prev_r;
reg [1:0] btn_curr_id_r;
reg [6:0] btn_bit_pos_r;
reg btn_pktrdy_set_r;
// Output assignment is:
// IDLE P1I = 11 -> ~CurId (0=F,1=E,2=D,3=C)
// IDLE P1I = 01 -> ~Btn[7:4][CurID] // buttons
// IDLE P1I = 10 -> ~Btn[3:0][CurID] // d-pad
//
// IDLE P1I = 01 -> 10 or 11 -> Increment ID mod NumPad
assign P1O = &P1I ? ~{2'h0,btn_curr_id_r} : (({4{P1I[1]}} | REG_PAD_r[btn_curr_id_r][7:4]) & ({4{P1I[0]}} | REG_PAD_r[btn_curr_id_r][3:0]));
assign IDL = |(btn_state_r & ST_BTN_IDLE) | (|(btn_state_r & ST_BTN_WAIT) & ~|btn_bit_pos_r);
always @(posedge CLK) begin
if (cpu_ireset_r) begin
REG_PKTRDY_r <= 0;
for (i = 0; i < `PKT_CNT; i = i + 1) REG_PKT_r[i] <= 0;
btn_state_r <= ST_BTN_IDLE;
btn_prev_r <= 2'b00;
btn_curr_id_r <= 0;
btn_pktrdy_set_r <= 0;
end
else begin
btn_pktrdy_set_r <= 0;
if (CLK_CPU_EDGE) begin
btn_prev_r <= P1I;
if (P1I != btn_prev_r) begin
if (~|P1I & (BOOTROM_ACTIVE | ~FEAT[`SGB_FEAT_ENH_OVERRIDE])) begin
// *->00 from any state causes us to go to serial transfer mode
// Is this true if we are already in serial transfer mode? Convenient to assume so.
btn_bit_pos_r <= 0;
btn_state_next_r <= ST_BTN_RECV;
btn_state_r <= ST_BTN_WAIT;
end
else begin
case (btn_state_r)
ST_BTN_IDLE: begin
if (~btn_prev_r[1] & P1I[1]) begin
// 01->(10|11) transition increments id
btn_curr_id_r <= (btn_curr_id_r + 1) & REG_CTL_r[5:4];
end
end
ST_BTN_RECV: begin
// 11 is considered a NOP
if (^P1I) begin
// Xilinx compiler silently fails to create logic if we use the following code:
// REG_PKT_r[btn_bit_pos_r[6:3]][btn_bit_pos_r[2:0]] <= P1I[0];
case (btn_bit_pos_r[6:3])
0: REG_PKT_r[0 ][btn_bit_pos_r[2:0]] <= P1I[0];
1: REG_PKT_r[1 ][btn_bit_pos_r[2:0]] <= P1I[0];
2: REG_PKT_r[2 ][btn_bit_pos_r[2:0]] <= P1I[0];
3: REG_PKT_r[3 ][btn_bit_pos_r[2:0]] <= P1I[0];
4: REG_PKT_r[4 ][btn_bit_pos_r[2:0]] <= P1I[0];
5: REG_PKT_r[5 ][btn_bit_pos_r[2:0]] <= P1I[0];
6: REG_PKT_r[6 ][btn_bit_pos_r[2:0]] <= P1I[0];
7: REG_PKT_r[7 ][btn_bit_pos_r[2:0]] <= P1I[0];
8: REG_PKT_r[8 ][btn_bit_pos_r[2:0]] <= P1I[0];
9: REG_PKT_r[9 ][btn_bit_pos_r[2:0]] <= P1I[0];
10: REG_PKT_r[10][btn_bit_pos_r[2:0]] <= P1I[0];
11: REG_PKT_r[11][btn_bit_pos_r[2:0]] <= P1I[0];
12: REG_PKT_r[12][btn_bit_pos_r[2:0]] <= P1I[0];
13: REG_PKT_r[13][btn_bit_pos_r[2:0]] <= P1I[0];
14: REG_PKT_r[14][btn_bit_pos_r[2:0]] <= P1I[0];
15: REG_PKT_r[15][btn_bit_pos_r[2:0]] <= P1I[0];
endcase
btn_bit_pos_r <= btn_bit_pos_r + 1;
btn_state_next_r <= &btn_bit_pos_r ? ST_BTN_WAIT : ST_BTN_RECV;
btn_state_r <= ST_BTN_WAIT;
end
end
ST_BTN_WAIT: begin
// 11 transition unless we are looping WAIT->WAIT->IDLE on 10 (TERM).
if (P1I == {1'b1,~|(btn_state_next_r & ST_BTN_IDLE)}) begin
// set packet ready if we are successfully transitioning to idle
btn_pktrdy_set_r <= |(btn_state_next_r & ST_BTN_IDLE);
btn_state_next_r <= ST_BTN_IDLE;
btn_state_r <= btn_state_next_r;
end
else if (^P1I) begin
// 10|01 are bad transitions when not waiting for terminating 10. 11 is NOP when we are waiting for 10.
// exiting rather than ignoring these states seems to fix a few games like Bonk's Adventure (hang at start) and Pokemon Gold (no background)
btn_state_r <= ST_BTN_IDLE;
end
end
endcase
end
end
end
REG_PKTRDY_r[0] <= (REG_PKTRDY_r[0] & ~reg_pktrdy_clear_r) | btn_pktrdy_set_r;
end
end
//-------------------------------------------------------------------
// DBG
//-------------------------------------------------------------------
`ifdef SGB_DEBUG
reg [7:0] dbg_data_r = 0;
assign DBG_DATA_OUT = dbg_data_r;
always @(posedge CLK) begin
if (~DBG_ADDR[11]) begin
casez(DBG_ADDR[7:0])
8'h00: dbg_data_r <= REG_LCDCHW_r;
8'h01: dbg_data_r <= REG_LCDCHR_r;
8'h02: dbg_data_r <= REG_PKTRDY_r;
8'h03: dbg_data_r <= REG_CTL_r;
8'h04: dbg_data_r <= REG_PAD_r[0];
8'h05: dbg_data_r <= REG_PAD_r[1];
8'h06: dbg_data_r <= REG_PAD_r[2];
8'h07: dbg_data_r <= REG_PAD_r[3];
8'h08: dbg_data_r <= REG_CHDAT_r;
8'h1?: dbg_data_r <= REG_PKT_r[DBG_ADDR[3:0]];
8'h20: dbg_data_r <= P1I;
8'h21: dbg_data_r <= P1O;
8'h22: dbg_data_r <= btn_state_r;
8'h23: dbg_data_r <= btn_prev_r;
8'h24: dbg_data_r <= btn_curr_id_r;
8'h25: dbg_data_r <= btn_bit_pos_r;
8'h30: dbg_data_r <= REG_LCDCHW_r[`LCDC_CHAR_ROW];
8'h31: dbg_data_r <= REG_LCDCHW_r[`LCDC_ROW_INDEX];
8'h32: dbg_data_r <= pix_row_index_write_r[7:0];
8'h33: dbg_data_r <= pix_row_index_write_r[8];
8'h34: dbg_data_r <= reg_row_index_read_r[7:0];
8'h35: dbg_data_r <= reg_row_index_read_r[8];
default: dbg_data_r <= 0;
endcase
end
end
`endif
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_PP_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_pg/sky130_fd_sc_hs__u_dl_p_pg.v"
`celldefine
module sky130_fd_sc_hs__dlxbp (
VPWR,
VGND,
Q ,
Q_N ,
D ,
GATE
);
// Module ports
input VPWR;
input VGND;
output Q ;
output Q_N ;
input D ;
input GATE;
// Local signals
wire buf_Q GATE_delayed;
wire buf_Q D_delayed ;
wire buf_Q ;
// Delay Name Output Other arguments
sky130_fd_sc_hs__u_dl_p_pg `UNIT_DELAY u_dl_p_pg0 (buf_Q , D, GATE, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBP_FUNCTIONAL_PP_V |
// $Revision: #70 $$Date: 2002/10/19 $$Author: wsnyder $ -*- Verilog -*-
//====================================================================
module CmpEng (/*AUTOARG*/
// Inputs
clk, reset_l
);
input clk;
input reset_l;
// ****************************************************************
/*AUTOREG*/
/*AUTOWIRE*/
// ********* Prefetch FSM definitions ****************************
reg [3:0] m_cac_state_r;
reg [2:0] m_cac_sel_r, m_dat_sel_r, m_cac_rw_sel_r;
reg m_wid1_r;
reg [2:0] m_wid3_r;
reg [5:2] m_wid4_r_l;
logic [4:1] logic_four;
logic [PARAM-1:0] paramed;
`define M 2
`define L 1
parameter MS = 2;
parameter LS = 1;
reg [MS:LS] m_param_r;
reg [`M:`L] m_def2_r;
always @ (posedge clk) begin
if (~reset_l) begin
m_cac_state_r <= CAC_IDLE;
m_cac_sel_r <= CSEL_PF;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
logic_four <= '0;
m_def2_r <= '0;
m_param_r <= '0;
m_wid1_r <= '0;
m_wid3_r <= '0;
m_wid4_r_l <= ~'0;
paramed <= '0;
// End of automatics
end
else begin
m_wid1_r <= 0;
m_wid3_r <= 0;
m_wid4_r_l <= 0;
m_param_r <= 0;
m_def2_r <= 0;
logic_four <= 4;
paramed <= 1;
end
end
endmodule
// Local Variables:
// verilog-auto-read-includes:t
// verilog-auto-sense-defines-constant: t
// verilog-auto-reset-widths: unbased
// verilog-active-low-regexp: "_l$"
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_SYMBOL_V
`define SKY130_FD_SC_LP__EBUFN_SYMBOL_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__ebufn (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE_B
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////
//// ////
//// can_register.v ////
//// ////
//// ////
//// This file is part of the CAN Protocol Controller ////
//// http://www.opencores.org/projects/can/ ////
//// ////
//// ////
//// Author(s): ////
//// Igor Mohor ////
//// [email protected] ////
//// ////
//// ////
//// All additional information is available in the README.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2002, 2003, 2004 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//// The CAN protocol is developed by Robert Bosch GmbH and ////
//// protected by patents. Anybody who wants to implement this ////
//// CAN IP core on silicon has to obtain a CAN protocol license ////
//// from Bosch. ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6 2003/03/20 16:58:50 mohor
// unix.
//
// Revision 1.4 2003/03/11 16:32:34 mohor
// timescale.v is used for simulation only.
//
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
// Revision 1.1.1.1 2002/12/20 16:39:21 mohor
// Initial
//
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
module can_register
( data_in,
data_out,
we,
clk
);
parameter WIDTH = 8; // default parameter of the register width
input [WIDTH-1:0] data_in;
input we;
input clk;
output [WIDTH-1:0] data_out;
reg [WIDTH-1:0] data_out;
always @ (posedge clk)
begin
if (we) // write
data_out<=#1 data_in;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__AND3_BEHAVIORAL_V |
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2016-2020 NUDT, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//Vendor: NUDT
//Version: 0.1
//Filename: UM.v
//Target Device: Altera
//Dscription:
// 1)user difine module
// 2)a sdn network demo
// pkt type:
// pkt_site 2bit : 2'b01 pkt head / 2'b11 pkt body / 2'b10 pkt tail
// invalid 4bit : the invalid byte sum of every payload cycle
// payload 128bit : pkt payload
//
// rule type:
// ctrl 24bit : [31:29]:forwarding direction
// 0 discard
// 1 trans to CPU with thread id assignd by user /
// 2 trans to CPU with polling thread id /
// 3 trans to port
// port_id 8bit : outport id or thread id
//
//
//Author :
//Revision List:
// rn1: date: modifier: description:
// rn2: date: modifier: description:
//
module UM(
input clk,
input rst_n,
input [5:0] sys_max_cpuid,
//cdp
input cdp2um_data_wr,
input [133:0] cdp2um_data,
input cdp2um_valid_wr,
input cdp2um_valid,
output um2cdp_alf,
output um2cdp_data_wr,
output [133:0] um2cdp_data,
output um2cdp_valid_wr,
output um2cdp_valid,
input cdp2um_alf,
//npe
input npe2um_data_wr,
input [133:0] npe2um_data,
input npe2um_valid_wr,
input npe2um_valid,
output um2npe_alf,
output um2npe_data_wr,
output [133:0] um2npe_data,
output um2npe_valid_wr,
output um2npe_valid,
input npe2um_alf,
//localbus
input localbus_cs_n,
input localbus_rd_wr,
input [31:0] localbus_data,
input localbus_ale,
output localbus_ack_n,
output [31:0] localbus_data_out
);
wire slave2lookup_cs_n;
wire slave2lookup_rd_wr;
wire [31:0] slave2lookup_data;
wire slave2lookup_ale;
wire lookup2slave_ack_n;
wire [31:0] lookup2slave_data_out;
//to rule mgmt
wire slave2rule_cs;//high active
wire rule2slave_ack;//high active ;handshake with slave2rule_cs
wire slave2rule_rw;//0:read 1:write
wire [15:0] slave2rule_addr;
wire [31:0] slave2rule_wdata;
wire [31:0]rule2slave_rdata;
wire parser2lookup_key_wr;
wire [287:0] parser2lookup_key;
wire parser2exe_data_wr;
wire [133:0] parser2exe_data;
wire exe2parser_alf;
wire lookup2rule_index_wr;
wire [5:0] lookup2rule_index;
wire rule2exe_data_wr;//index read return valid
wire [31:0] rule2exe_data;
wire exe2disp_direction_req;
wire exe2disp_direction;//0:up cpu 1: down port
wire exe2disp_data_wr;
wire [133:0] exe2disp_data;
wire exe2disp_valid_wr;
wire exe2disp_valid;
wire disp2exe_alf;
wire disp2usermux_data_wr;
wire [133:0] disp2usermux_data;
wire disp2usermux_valid_wr;
wire disp2usermux_valid;
wire usermux2disp_alf;
user_mgmt_slave user_mgmt_slave(
.clk(clk),
.rst_n(rst_n),
//from localbus master
.localbus_cs_n(localbus_cs_n),
.localbus_rd_wr(localbus_rd_wr),//0 write 1:read
.localbus_data(localbus_data),
.localbus_ale(localbus_ale),
.localbus_ack_n(localbus_ack_n),
.localbus_data_out(localbus_data_out),
//to bv lookup
.cfg2lookup_cs_n(slave2lookup_cs_n),
.cfg2lookup_rd_wr(slave2lookup_rd_wr),
.cfg2lookup_data(slave2lookup_data),
.cfg2lookup_ale(slave2lookup_ale),
.lookup2cfg_ack_n(lookup2slave_ack_n),
.lookup2cfg_data_out(lookup2slave_data_out),
//to rule mgmt
.cfg2rule_cs(slave2rule_cs),//high active
.rule2cfg_ack(rule2slave_ack),//high active,handshake with cfg2rule_cs
.cfg2rule_rw(slave2rule_rw),//0:read 1:write
.cfg2rule_addr(slave2rule_addr),
.cfg2rule_wdata(slave2rule_wdata),
.rule2cfg_rdata(rule2slave_rdata)
);
parser parser(
.clk(clk),
.rst_n(rst_n),
//input pkt from port
.port2parser_data_wr(cdp2um_data_wr),
.port2parser_data(cdp2um_data),
.port2parser_valid_wr(cdp2um_valid_wr),
.port2parser_valid(cdp2um_valid),
.parser2port_alf(um2cdp_alf),
//parse key which transmit to lookup
.parser2lookup_key_wr(parser2lookup_key_wr),
.parser2lookup_key(parser2lookup_key),
//transport to next module
.parser2next_data_wr(parser2exe_data_wr),
.parser2next_data(parser2exe_data),
.next2parser_alf(exe2parser_alf)
);
lookup BV_Search_engine(
.clk(clk),
.reset(rst_n),//low active
.localbus_cs_n(slave2lookup_cs_n),
.localbus_rd_wr(slave2lookup_rd_wr),//0 write 1:read
.localbus_data(slave2lookup_data),
.localbus_ale(slave2lookup_ale),
.localbus_ack_n(lookup2slave_ack_n),
.localbus_data_out(lookup2slave_data_out),
.metadata_valid(parser2lookup_key_wr),
.metadata(parser2lookup_key),
.countid_valid(lookup2rule_index_wr),
.countid(lookup2rule_index)//6bit width?
);
rule_access rule_access(
.clk(clk),
.rst_n(rst_n),
//lookup rule read index
.lookup2rule_index_wr(lookup2rule_index_wr),
.lookup2rule_index({10'b0,lookup2rule_index}),//16bit width
.rule2lookup_data_wr(rule2exe_data_wr),//index read return valid
.rule2lookup_data(rule2exe_data),
//user cfg require
.cfg2rule_cs(slave2rule_cs),//high active
.rule2cfg_ack(rule2slave_ack),//high active,handshake with cfg2rule_cs
.cfg2rule_rw(slave2rule_rw),//0:read 1:write
.cfg2rule_addr(slave2rule_addr),
.cfg2rule_wdata(slave2rule_wdata),
.rule2cfg_rdata(rule2slave_rdata)
);
executer executer(
.clk(clk),
.rst_n(rst_n),
.sys_max_cpuid(sys_max_cpuid),
//pkt waiting for rule
.parser2exe_data_wr(parser2exe_data_wr),
.parser2exe_data(parser2exe_data),
.exe2parser_alf(exe2parser_alf),
//rule from lookup engine(BV_search_engine)
.lookup2exe_rule_wr(rule2exe_data_wr),
.lookup2exe_rule(rule2exe_data),
//execute's tranmit direction request
.exe2disp_direction_req(exe2disp_direction_req),
.exe2disp_direction(exe2disp_direction),//0:up cpu 1: down port
//transmit to next module(dispatch)
.exe2disp_data_wr(exe2disp_data_wr),
.exe2disp_data(exe2disp_data),
.exe2disp_valid_wr(exe2disp_valid_wr),
.exe2disp_valid(exe2disp_valid),
.disp2exe_alf(disp2exe_alf)
);
dispatch dispatch(
.clk(clk),
.rst_n(rst_n),
//execute module's pkt waiting for transmit
.exe2disp_data_wr(exe2disp_data_wr),
.exe2disp_data(exe2disp_data),
.exe2disp_valid_wr(exe2disp_valid_wr),
.exe2disp_valid(exe2disp_valid),
.disp2exe_alf(disp2exe_alf),
//execute's tranmit direction request
.exe2disp_direction_req(exe2disp_direction_req),
.exe2disp_direction(exe2disp_direction),//0:up cpu 1: down port
//transmit to up cpu
.disp2up_data_wr(um2npe_data_wr),
.disp2up_data(um2npe_data),
.disp2up_valid_wr(um2npe_valid_wr),
.disp2up_valid(um2npe_valid),
.up2disp_alf(npe2um_alf),
//transmit to down port
.disp2down_data_wr(disp2usermux_data_wr),
.disp2down_data(disp2usermux_data),
.disp2down_valid_wr(disp2usermux_valid_wr),
.disp2down_valid(disp2usermux_valid),
.down2disp_alf(usermux2disp_alf)
);
user_mux user_mux(
.clk(clk),
.rst_n(rst_n),
//lookup pkt waiting for transmit
.disp2usermux_data_wr(disp2usermux_data_wr),
.disp2usermux_data(disp2usermux_data),
.disp2usermux_valid_wr(disp2usermux_valid_wr),
.disp2usermux_valid(disp2usermux_valid),
.usermux2disp_alf(usermux2disp_alf),
//up cpu pkt waiting for transmit
.up2usermux_data_wr(npe2um_data_wr),
.up2usermux_data(npe2um_data),
.up2usermux_valid_wr(npe2um_valid_wr),
.up2usermux_valid(npe2um_valid),
.usermux2up_alf(um2npe_alf),
//transmit to down port
.usermux2down_data_wr(um2cdp_data_wr),
.usermux2down_data(um2cdp_data),
.usermux2down_valid_wr(um2cdp_valid_wr),
.usermux2down_valid(um2cdp_valid),
.down2usermux_alf(cdp2um_alf)
);
endmodule
/**********************************
Initial Inst
UM UM(
.clk();
.rst_n();
.sys_max_cpuid();
//cdp
.cdp2um_data_wr();
.cdp2um_data();
.cdp2um_valid_wr();
.cdp2um_valid();
.um2cdp_alf();
.um2cdp_data_wr();
.um2cdp_data();
.um2cdp_valid_wr();
.um2cdp_valid();
.cdp2um_alf();
//npe
.npe2um_data_wr();
.npe2um_data();
.npe2um_valid_wr();
.npe2um_valid();
.um2npe_alf();
.um2npe_data_wr();
.um2npe_data();
.um2npe_valid_wr();
.um2npe_valid();
.npe2um_alf();
//localbus
.localbus_cs_n();
.localbus_rd_wr();
.localbus_data();
.localbus_ale();
.localbus_ack_n();
.localbus_data_out()
);
**********************************/
|
`timescale 1ns / 1ps
`define WIDTH 170
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01/13/2017 01:30:56 PM
// Design Name:
// Module Name: recieve_data_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module recieve_data_tb();
reg dout_sr;
reg clk;
reg rst;
reg load_sr;
wire [`WIDTH-1:0] dout;
Recieve_Data DUT3(
.dout_sr(dout_sr),
.clk(clk),
.rst(rst),
.load_sr(load_sr),
.dout(dout)
);
initial begin
$dumpfile("recieve_data.dump");
$dumpvars(0, Recieve_Data);
end
initial begin
clk=0;
forever #50 clk=~clk;
end
initial begin
rst=1;
#200 rst=0;
end
initial begin
load_sr=0;
#400 load_sr=1;
#100 load_sr=0;
end
initial begin
dout_sr=0;
#500 dout_sr=1;
#100 dout_sr=0;
#100 dout_sr=1;
#200 dout_sr=0;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "base_zynq_design_auto_pc_1,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "base_zynq_design_auto_pc_1,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=0,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module base_zynq_design_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [11 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [11 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [11 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [11 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(0),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hvl__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_hvl__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_FUNCTIONAL_PP_V |
/*
* Author : Tom Stanway-Mayers
* Description : Top Level
* Version: :
* License : Apache License Version 2.0, January 2004
* License URL : http://www.apache.org/licenses/
*/
// TODO - generalise interface data widths
`include "riscv_defs.v"
module merlin
#(
parameter C_WORD_RESET_VECTOR = 30'h0
)
(
// global
input wire clk_i,
input wire fclk_i,
input wire reset_i,
// core status
output wire sleeping_o,
// hardware interrupt interface
input wire irqm_extern_i,
input wire irqm_softw_i,
input wire irqm_timer_i,
input wire irqs_extern_i,
// instruction port
input wire ireqready_i,
output wire ireqvalid_o,
output wire [1:0] ireqhpl_o,
output wire [`RV_XLEN-1:0] ireqaddr_o,
output wire irspready_o,
input wire irspvalid_i,
input wire irsprerr_i,
input wire [`RV_XLEN-1:0] irspdata_i,
// data port
input wire dreqready_i,
output wire dreqvalid_o,
output wire [1:0] dreqsize_o,
output wire dreqwrite_o,
output wire [1:0] dreqhpl_o,
output wire [31:0] dreqaddr_o,
output wire [31:0] dreqdata_o,
output wire drspready_o,
input wire drspvalid_i,
input wire drsprerr_i,
input wire drspwerr_i,
input wire [31:0] drspdata_i,
// instruction trace port
output wire mit_en_o,
output wire mit_commit_o,
output wire [`RV_XLEN-1:0] mit_pc_o,
output wire [`RV_XLEN-1:0] mit_ins_o,
output wire [`RV_XLEN-1:0] mit_regs2_data_o,
output wire [`RV_XLEN-1:0] mit_alu_dout_o,
output wire [1:0] mit_mode_o,
output wire mit_trap_o,
output wire [`RV_XLEN-1:0] mit_trap_cause_o,
output wire [`RV_XLEN-1:0] mit_trap_entry_addr_o,
output wire [`RV_XLEN-1:0] mit_trap_rtn_addr_o
// debug interface
// TODO - debug interface
);
//--------------------------------------------------------------
// prefetch unit
wire pfu_ids_dav;
wire [`RV_SOFID_RANGE] pfu_ids_sofid;
wire [31:0] pfu_ids_ins;
wire pfu_ids_ferr;
wire [`RV_XLEN-1:0] pfu_ids_pc;
// instruction decoder stage
wire ids_pfu_ack;
wire [1:0] ids_pfu_ack_size;
wire [`RV_XLEN-1:0] ids_exs_ins;
wire ids_exs_valid;
wire [`RV_SOFID_RANGE] ids_exs_sofid;
wire [1:0] ids_exs_ins_size;
wire ids_exs_ins_uerr;
wire ids_exs_ins_ferr;
wire ids_exs_fencei;
wire ids_exs_wfi;
wire ids_exs_jump;
wire ids_exs_ecall;
wire ids_exs_trap_rtn;
wire [1:0] ids_exs_trap_rtn_mode;
wire ids_exs_cond;
wire [`RV_ZONE_RANGE] ids_exs_zone;
wire ids_exs_link;
wire [`RV_XLEN-1:0] ids_exs_pc;
wire [`RV_ALUOP_RANGE] ids_exs_alu_op;
wire [`RV_XLEN-1:0] ids_exs_operand_left;
wire [`RV_XLEN-1:0] ids_exs_operand_right;
wire [`RV_XLEN-1:0] ids_exs_cmp_right;
wire [`RV_XLEN-1:0] ids_exs_regs1_data;
wire [`RV_XLEN-1:0] ids_exs_regs2_data;
wire [4:0] ids_exs_regd_addr;
wire [2:0] ids_exs_funct3;
wire ids_exs_csr_rd;
wire ids_exs_csr_wr;
wire [11:0] ids_exs_csr_addr;
wire [`RV_XLEN-1:0] ids_exs_csr_wr_data;
// execution stage
wire [1:0] exs_pfu_hpl;
wire exs_pfu_jump;
wire [`RV_XLEN-1:0] exs_pfu_jump_addr;
wire exs_ids_stall;
wire exs_ids_regd_cncl_load;
wire exs_ids_regd_wr;
wire [4:0] exs_ids_regd_addr;
wire [`RV_XLEN-1:0] exs_ids_regd_data;
wire exs_lsq_lq_wr;
wire exs_lsq_sq_wr;
wire [1:0] exs_lsq_hpl;
wire [2:0] exs_lsq_funct3;
wire [4:0] exs_lsq_regd_addr;
wire [`RV_XLEN-1:0] exs_lsq_regs2_data;
wire [`RV_XLEN-1:0] exs_lsq_addr;
// load/store queue
wire lsq_ids_reg_wr;
wire [4:0] lsq_ids_reg_addr;
wire [`RV_XLEN-1:0] lsq_ids_reg_data;
wire lsq_exs_full;
wire lsq_exs_empty;
//--------------------------------------------------------------
//--------------------------------------------------------------
// prefetch unit
//--------------------------------------------------------------
merlin_pfu32ic
#(
.C_FIFO_PASSTHROUGH (`RV_PFU_BYPASS),
.C_FIFO_DEPTH_X (2), // pfu fifo depth base 2 exponent
.C_WORD_RESET_VECTOR (C_WORD_RESET_VECTOR)
) i_merlin_pfu32ic (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// instruction cache interface
.ireqready_i (ireqready_i),
.ireqvalid_o (ireqvalid_o),
.ireqhpl_o (ireqhpl_o), // HART priv. level
.ireqaddr_o (ireqaddr_o),
.irspready_o (irspready_o),
.irspvalid_i (irspvalid_i),
.irsprerr_i (irsprerr_i),
.irspdata_i (irspdata_i),
// decoder interface
.ids_dav_o (pfu_ids_dav), // new fetch available
.ids_ack_i (ids_pfu_ack), // ack this fetch
.ids_ack_size_i (ids_pfu_ack_size), // ack this fetch
.ids_sofid_o (pfu_ids_sofid), // first fetch since vectoring
.ids_ins_o (pfu_ids_ins), // instruction fetched
.ids_ferr_o (pfu_ids_ferr), // this instruction fetch resulted in error
.ids_pc_o (pfu_ids_pc), // address of this instruction
// vectoring and exception controller interface
.exs_pc_wr_i (exs_pfu_jump),
.exs_pc_din_i (exs_pfu_jump_addr),
// pfu stage interface
.exs_hpl_i (exs_pfu_hpl)
);
//--------------------------------------------------------------
// instruction decoder stage
//--------------------------------------------------------------
merlin_id_stage i_merlin_id_stage (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// pfu interface
.pfu_dav_i (pfu_ids_dav), // new fetch available
.pfu_ack_o (ids_pfu_ack), // ack this fetch
.pfu_ack_size_o (ids_pfu_ack_size), // ack size
.pfu_sofid_i (pfu_ids_sofid), // first fetch since vectoring
.pfu_ins_i (pfu_ids_ins), // instruction fetched
.pfu_ferr_i (pfu_ids_ferr), // this instruction fetch resulted in error
.pfu_pc_i (pfu_ids_pc), // address of this instruction
// ex stage interface
.exs_ins_o (ids_exs_ins),
.exs_valid_o (ids_exs_valid),
.exs_stall_i (exs_ids_stall),
.exs_sofid_o (ids_exs_sofid),
.exs_ins_size_o (ids_exs_ins_size),
.exs_ins_uerr_o (ids_exs_ins_uerr),
.exs_ins_ferr_o (ids_exs_ins_ferr),
.exs_fencei_o (ids_exs_fencei),
.exs_wfi_o (ids_exs_wfi),
.exs_jump_o (ids_exs_jump),
.exs_ecall_o (ids_exs_ecall),
.exs_trap_rtn_o (ids_exs_trap_rtn),
.exs_trap_rtn_mode_o (ids_exs_trap_rtn_mode),
.exs_cond_o (ids_exs_cond),
.exs_zone_o (ids_exs_zone),
.exs_link_o (ids_exs_link),
.exs_pc_o (ids_exs_pc),
.exs_alu_op_o (ids_exs_alu_op),
.exs_operand_left_o (ids_exs_operand_left),
.exs_operand_right_o (ids_exs_operand_right),
.exs_cmp_right_o (ids_exs_cmp_right),
.exs_regs1_data_o (ids_exs_regs1_data),
.exs_regs2_data_o (ids_exs_regs2_data),
.exs_regd_addr_o (ids_exs_regd_addr),
.exs_funct3_o (ids_exs_funct3),
.exs_csr_rd_o (ids_exs_csr_rd),
.exs_csr_wr_o (ids_exs_csr_wr),
.exs_csr_addr_o (ids_exs_csr_addr),
.exs_csr_wr_data_o (ids_exs_csr_wr_data),
// write-back interface
.exs_regd_cncl_load_i (exs_ids_regd_cncl_load),
.exs_regd_wr_i (exs_ids_regd_wr),
.exs_regd_addr_i (exs_ids_regd_addr),
.exs_regd_data_i (exs_ids_regd_data),
// load/store queue interface
.lsq_reg_wr_i (lsq_ids_reg_wr),
.lsq_reg_addr_i (lsq_ids_reg_addr),
.lsq_reg_data_i (lsq_ids_reg_data)
);
//--------------------------------------------------------------
// execution stage
//--------------------------------------------------------------
merlin_ex_stage
#(
.C_WORD_RESET_VECTOR (C_WORD_RESET_VECTOR)
) i_merlin_ex_stage (
// global
.clk_i (clk_i),
.fclk_i (fclk_i),
.reset_i (reset_i),
// external interface
.sleeping_o (sleeping_o),
//
.irqm_extern_i (irqm_extern_i),
.irqm_softw_i (irqm_softw_i),
.irqm_timer_i (irqm_timer_i),
.irqs_extern_i (irqs_extern_i),
// pfu stage interface
.pfu_hpl_o (exs_pfu_hpl),
// hart vectoring interface
.pfu_jump_o (exs_pfu_jump),
.pfu_jump_addr_o (exs_pfu_jump_addr),
// instruction decoder stage interface
.ids_ins_i (ids_exs_ins),
.ids_valid_i (ids_exs_valid),
.ids_stall_o (exs_ids_stall),
.ids_sofid_i (ids_exs_sofid),
.ids_ins_size_i (ids_exs_ins_size),
.ids_ins_uerr_i (ids_exs_ins_uerr),
.ids_ins_ferr_i (ids_exs_ins_ferr),
.ids_fencei_i (ids_exs_fencei),
.ids_wfi_i (ids_exs_wfi),
.ids_jump_i (ids_exs_jump),
.ids_ecall_i (ids_exs_ecall),
.ids_trap_rtn_i (ids_exs_trap_rtn),
.ids_trap_rtn_mode_i (ids_exs_trap_rtn_mode),
.ids_cond_i (ids_exs_cond),
.ids_zone_i (ids_exs_zone),
.ids_link_i (ids_exs_link),
.ids_pc_i (ids_exs_pc),
.ids_alu_op_i (ids_exs_alu_op),
.ids_operand_left_i (ids_exs_operand_left),
.ids_operand_right_i (ids_exs_operand_right),
.ids_cmp_right_i (ids_exs_cmp_right),
.ids_regs1_data_i (ids_exs_regs1_data),
.ids_regs2_data_i (ids_exs_regs2_data),
.ids_regd_addr_i (ids_exs_regd_addr),
.ids_funct3_i (ids_exs_funct3),
.ids_csr_rd_i (ids_exs_csr_rd),
.ids_csr_wr_i (ids_exs_csr_wr),
.ids_csr_addr_i (ids_exs_csr_addr),
.ids_csr_wr_data_i (ids_exs_csr_wr_data),
// write-back interface
.ids_regd_cncl_load_o (exs_ids_regd_cncl_load),
.ids_regd_wr_o (exs_ids_regd_wr),
.ids_regd_addr_o (exs_ids_regd_addr),
.ids_regd_data_o (exs_ids_regd_data),
// load/store queue interface
.lsq_full_i (lsq_exs_full),
.lsq_empty_i (lsq_exs_empty),
.lsq_lq_wr_o (exs_lsq_lq_wr),
.lsq_sq_wr_o (exs_lsq_sq_wr),
.lsq_hpl_o (exs_lsq_hpl),
.lsq_funct3_o (exs_lsq_funct3),
.lsq_regd_addr_o (exs_lsq_regd_addr),
.lsq_regs2_data_o (exs_lsq_regs2_data),
.lsq_addr_o (exs_lsq_addr),
// instruction trace port
.mit_en_o (mit_en_o),
.mit_commit_o (mit_commit_o),
.mit_pc_o (mit_pc_o),
.mit_ins_o (mit_ins_o),
.mit_regs2_data_o (mit_regs2_data_o),
.mit_alu_dout_o (mit_alu_dout_o),
.mit_mode_o (mit_mode_o),
.mit_trap_o (mit_trap_o),
.mit_trap_cause_o (mit_trap_cause_o),
.mit_trap_entry_addr_o (mit_trap_entry_addr_o),
.mit_trap_rtn_addr_o (mit_trap_rtn_addr_o)
);
//--------------------------------------------------------------
// load/store queue
//--------------------------------------------------------------
merlin_lsqueue
#(
.C_FIFO_PASSTHROUGH (`RV_LSQUEUE_BYPASS),
.C_FIFO_DEPTH_X (2)
) i_merlin_lsqueue (
// global
.clk_i (clk_i),
.reset_i (reset_i),
// instruction decoder stage interface
.lsq_reg_wr_o (lsq_ids_reg_wr),
.lsq_reg_addr_o (lsq_ids_reg_addr),
.lsq_reg_data_o (lsq_ids_reg_data),
// execution stage interface
.exs_full_o (lsq_exs_full),
.exs_empty_o (lsq_exs_empty),
.exs_lq_wr_i (exs_lsq_lq_wr),
.exs_sq_wr_i (exs_lsq_sq_wr),
.exs_hpl_i (exs_lsq_hpl),
.exs_funct3_i (exs_lsq_funct3),
.exs_regd_addr_i (exs_lsq_regd_addr),
.exs_regs2_data_i (exs_lsq_regs2_data),
.exs_addr_i (exs_lsq_addr),
// imprecise exceptions
.plic_int_laf_o (), // load access fault
.plic_int_saf_o (), // store access fault
.plic_int_rspdata_o (), // response data
// data port
.dreqready_i (dreqready_i),
.dreqvalid_o (dreqvalid_o),
.dreqsize_o (dreqsize_o),
.dreqwrite_o (dreqwrite_o),
.dreqhpl_o (dreqhpl_o),
.dreqaddr_o (dreqaddr_o),
.dreqdata_o (dreqdata_o),
.drspready_o (drspready_o),
.drspvalid_i (drspvalid_i),
.drsprerr_i (drsprerr_i),
.drspwerr_i (drspwerr_i),
.drspdata_i (drspdata_i)
);
endmodule
|
module panel_driver
(
input clk,
input reset_n,
input test_panel_select_n,
input shift,
input load_led_vals,
input load_brightness,
input [7:0] pwm_time,
input [31:0] chunk_data,
input [3:0] chunk_addr,
input chunk_write_enable,
input [3:0] row_addr,
input [3:0] active_row_addr,
output [2:0] serial_data_out
);
wire [15:0] chunk_select;
wire [383:0] row_data;
decoder #(.WIDTH(4)) chunk_addr_decoder
(.addr(chunk_addr), .y(chunk_select));
genvar i;
generate
for (i=0; i<12; i=i+1)
begin : rams
altera_dual_port_ram_simple #(.DATA_WIDTH(32), .ADDR_WIDTH(8)) ram
(.clk(clk),
.write_enable(chunk_select[i] & chunk_write_enable),
.write_addr({4'h0, row_addr}),
.read_addr({4'h0, active_row_addr}),
.data_in(chunk_data),
.data_out(row_data[32*i+31:32*i]));
end
endgenerate
genvar j;
generate
for (j=0; j<3; j=j+1)
begin : color_component_drivers
color_component_driver color_component_driver_instance
(.clk(clk),
.reset_n(reset_n),
.test_panel_select_n(test_panel_select_n),
.shift(shift),
.load_led_vals(load_led_vals),
.load_brightness(load_brightness),
.pwm_time(pwm_time),
.component_values({row_data[383-8*j:376-8*j],
row_data[359-8*j:352-8*j],
row_data[335-8*j:328-8*j],
row_data[311-8*j:304-8*j],
row_data[287-8*j:280-8*j],
row_data[263-8*j:256-8*j],
row_data[239-8*j:232-8*j],
row_data[215-8*j:208-8*j],
row_data[191-8*j:184-8*j],
row_data[167-8*j:160-8*j],
row_data[143-8*j:136-8*j],
row_data[119-8*j:112-8*j],
row_data[95-8*j:88-8*j],
row_data[71-8*j:64-8*j],
row_data[47-8*j:40-8*j],
row_data[23-8*j:16-8*j]}),
.serial_data_out(serial_data_out[j]));
end
endgenerate
endmodule // panel_driver
|
/************************************************
The Verilog HDL code example is from the book
Computer Principles and Design in Verilog HDL
by Yamin Li, published by A JOHN WILEY & SONS
************************************************/
module CPU (clk,reset,pc,inst,Addr,Data_I,Data_O,WE,ACK,STB,debug_next_pc); // cpu kbd i/o
input clk, reset; // clock and reset
input [31:0] inst; // instruction
input [31:0] Data_I; // load data
input ACK;
output [31:0] pc; // program counter
output [31:0] Addr; // mem or i/o addr
output [31:0] Data_O; // store data
output WE; // data memory write
output STB;
// debug signals
output [31: 0] debug_next_pc;
// control signals
reg wreg; // write regfile
reg wmem,rmem; // write/read memory
reg [31:0] alu_out; // alu output
reg [4:0] dest_rn; // dest reg number
reg [31:0] next_pc; // next pc
wire [31:0] pc_plus_4 = pc + 4; // pc + 4
// instruction format
wire [05:00] opcode = inst[31:26];
wire [04:00] rs = inst[25:21];
wire [04:00] rt = inst[20:16];
wire [04:00] rd = inst[15:11];
wire [04:00] sa = inst[10:06];
wire [05:00] func = inst[05:00];
wire [15:00] imm = inst[15:00];
wire [25:00] addr = inst[25:00];
wire sign = inst[15];
wire [31:00] offset = {{14{sign}},imm,2'b00};
wire [31:00] j_addr = {pc_plus_4[31:28],addr,2'b00};
// instruction decode
wire i_add = (opcode == 6'h00) & (func == 6'h20); // add
wire i_sub = (opcode == 6'h00) & (func == 6'h22); // sub
wire i_and = (opcode == 6'h00) & (func == 6'h24); // and
wire i_or = (opcode == 6'h00) & (func == 6'h25); // or
wire i_xor = (opcode == 6'h00) & (func == 6'h26); // xor
wire i_sll = (opcode == 6'h00) & (func == 6'h00); // sll
wire i_srl = (opcode == 6'h00) & (func == 6'h02); // srl
wire i_sra = (opcode == 6'h00) & (func == 6'h03); // sra
wire i_jr = (opcode == 6'h00) & (func == 6'h08); // jr
wire i_addi = (opcode == 6'h08); // addi
wire i_andi = (opcode == 6'h0c); // andi
wire i_ori = (opcode == 6'h0d); // ori
wire i_xori = (opcode == 6'h0e); // xori
wire i_lw = (opcode == 6'h23); // lw
wire i_sw = (opcode == 6'h2b); // sw
wire i_beq = (opcode == 6'h04); // beq
wire i_bne = (opcode == 6'h05); // bne
wire i_lui = (opcode == 6'h0f); // lui
wire i_j = (opcode == 6'h02); // j
wire i_jal = (opcode == 6'h03); // jal
// pc
reg [31:0] pc;
always @ (posedge clk or posedge reset) begin
if (reset) pc <= 0;
// slave is not ready, you stay here
else begin
if (STB)
pc <= ACK ? next_pc : pc;
else
pc <= next_pc;
end
end
// data written to register file
wire [31:0] data_2_rf = i_lw ? Data_I : alu_out;
// register file
reg [31:0] regfile [1:31]; // $1 - $31
wire [31:0] a = (rs==0) ? 0 : regfile[rs]; // read port
wire [31:0] b = (rt==0) ? 0 : regfile[rt]; // read port
always @ (posedge clk) begin
if (wreg && (dest_rn != 0)) begin
regfile[dest_rn] <= data_2_rf; // write port
end
end
// output signals
assign WE = wmem; // data memory write
assign Data_O = b; // data to store
assign Addr = alu_out; // memory address
assign STB = rmem | wmem;
// control signals, will be combinational circuit
always @(*) begin
alu_out = 0; // alu output
dest_rn = rd; // dest reg number
wreg = 0; // write regfile
wmem = 0; // write memory (sw)
rmem = 0; // read memory (lw)
next_pc = pc_plus_4;
case (1'b1)
i_add: begin // add
alu_out = a + b;
wreg = 1; end
i_sub: begin // sub
alu_out = a - b;
wreg = 1; end
i_and: begin // and
alu_out = a & b;
wreg = 1; end
i_or: begin // or
alu_out = a | b;
wreg = 1; end
i_xor: begin // xor
alu_out = a ^ b;
wreg = 1; end
i_sll: begin // sll
alu_out = b << sa;
wreg = 1; end
i_srl: begin // srl
alu_out = b >> sa;
wreg = 1; end
i_sra: begin // sra
alu_out = $signed(b) >>> sa;
wreg = 1; end
i_jr: begin // jr
next_pc = a; end
i_addi: begin // addi
alu_out = a + {{16{sign}},imm};
dest_rn = rt;
wreg = 1; end
i_andi: begin // andi
alu_out = a & {16'h0,imm};
dest_rn = rt;
wreg = 1; end
i_ori: begin // ori
alu_out = a | {16'h0,imm};
dest_rn = rt;
wreg = 1; end
i_xori: begin // xori
alu_out = a ^ {16'h0,imm};
dest_rn = rt;
wreg = 1; end
i_lw: begin // lw
alu_out = a + {{16{sign}},imm};
dest_rn = rt;
rmem = 1;
wreg = 1; end
i_sw: begin // sw
alu_out = a + {{16{sign}},imm};
wmem = 1; end
i_beq: begin // beq
if (a == b)
next_pc = pc_plus_4 + offset; end
i_bne: begin // bne
if (a != b)
next_pc = pc_plus_4 + offset; end
i_lui: begin // lui
alu_out = {imm,16'h0};
dest_rn = rt;
wreg = 1; end
i_j: begin // j
next_pc = j_addr; end
i_jal: begin // jal
alu_out = pc_plus_4;
wreg = 1;
dest_rn = 5'd31;
next_pc = j_addr; end
default: ;
endcase
wreg = STB ? wreg & ACK : wreg;
end
// debug signals
assign debug_next_pc = next_pc;
endmodule
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-10-31 02:55:00
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
//assign i = Stop_I;
if (SW <=`STOP_SW1 || SW <=`STOP_SW2) begin : GENSTOP
mult #(.SW(SW))
inst_mult (
.Data_A_i(Data_A_i),
.Data_B_i(Data_B_i),
.sgf_result_o(sgf_result_o)
);
end else begin : RECURSIVE
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
reg [SW-1:0] Q_left;
reg [SW-1:0] Q_right;
reg [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
reg [2*(SW/2)-1:0] Q_left;
reg [2*(SW/2+1)-1:0] Q_right;
reg [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
end
endgenerate
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / / _no_description_
// /___/ /\ Filename : IBUFCTRL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module IBUFCTRL #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter ISTANDARD = "UNUSED",
parameter USE_IBUFDISABLE = "FALSE"
)(
output O,
input I,
input IBUFDISABLE,
input INTERMDISABLE,
input T
);
// define constants
localparam MODULE_NAME = "IBUFCTRL";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam USE_IBUFDISABLE_FALSE = 0;
localparam USE_IBUFDISABLE_TRUE = 1;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
localparam [40:1] USE_IBUFDISABLE_REG = USE_IBUFDISABLE;
wire USE_IBUFDISABLE_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire O_out;
wire O_delay;
wire IBUFDISABLE_in;
wire INTERMDISABLE_in;
wire I_in;
wire T_in;
wire IBUFDISABLE_delay;
wire INTERMDISABLE_delay;
wire I_delay;
wire T_delay;
wire NOT_T_OR_IBUFDISABLE;
assign #(out_delay) O = O_delay;
// inputs with no timing checks
assign #(in_delay) IBUFDISABLE_delay = IBUFDISABLE;
assign #(in_delay) INTERMDISABLE_delay = INTERMDISABLE;
assign #(in_delay) I_delay = I;
assign #(in_delay) T_delay = T;
assign O_delay = O_out;
assign IBUFDISABLE_in = IBUFDISABLE_delay;
assign INTERMDISABLE_in = INTERMDISABLE_delay;
assign I_in = I_delay;
assign T_in = T_delay;
assign USE_IBUFDISABLE_BIN =
(USE_IBUFDISABLE_REG == "FALSE") ? USE_IBUFDISABLE_FALSE :
(USE_IBUFDISABLE_REG == "TRUE") ? USE_IBUFDISABLE_TRUE :
USE_IBUFDISABLE_FALSE;
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-103] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((USE_IBUFDISABLE_REG != "FALSE") &&
(USE_IBUFDISABLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-104] USE_IBUFDISABLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_IBUFDISABLE_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
generate
case (USE_IBUFDISABLE)
"TRUE" : begin
assign NOT_T_OR_IBUFDISABLE = ~T_in || IBUFDISABLE_in;
assign O_out = (NOT_T_OR_IBUFDISABLE == 0)? I_in : (NOT_T_OR_IBUFDISABLE == 1)? 1'b0 : 1'bx;
end
"FALSE" : begin
assign O_out = I_in;
end
endcase
endgenerate
specify
(I => O) = (0:0:0, 0:0:0);
(IBUFDISABLE => O) = (0:0:0, 0:0:0);
(INTERMDISABLE => O) = (0:0:0, 0:0:0);
(T => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__NOR4_PP_BLACKBOX_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_PP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Mar 24 22:16:07 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/andrewandre/Documents/GitHub/axiplasma/hdl/projects/Nexys4/rtl_project/rtl_project.srcs/sources_1/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_0_0/mig_wrap_proc_sys_reset_0_0_stub.v
// Design : mig_wrap_proc_sys_reset_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "proc_sys_reset,Vivado 2016.4" *)
module mig_wrap_proc_sys_reset_0_0(slowest_sync_clk, ext_reset_in, aux_reset_in,
mb_debug_sys_rst, dcm_locked, mb_reset, bus_struct_reset, peripheral_reset,
interconnect_aresetn, peripheral_aresetn)
/* synthesis syn_black_box black_box_pad_pin="slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]" */;
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
output [0:0]bus_struct_reset;
output [0:0]peripheral_reset;
output [0:0]interconnect_aresetn;
output [0:0]peripheral_aresetn;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLRTN_SYMBOL_V
`define SKY130_FD_SC_HD__DLRTN_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLRTN_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND4BB_2_V
`define SKY130_FD_SC_HDLL__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND4BB_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_FUNCTIONAL_V
`define SKY130_FD_SC_LP__LSBUFISO1P_FUNCTIONAL_V
/**
* lsbufiso1p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Local signals
wire or0_out_X;
wire destpwr ;
wire vgnd ;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, destpwr, vgnd);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: UTFSM
// Engineer: Mauricio Solis
//
// Create Date: 09:01:45 29/04/2015
// Design Name:
// Module Name: kbd_ms
// Project Name: Experiencia 5
// Target Devices:
// Tool versions:
// Description: Es un driver para el teclado y es capaz de
// indicar si llego un make code,break code, E0 make code
// y E0 break code
//
// Dependencies: ps2_read_ms
// Additional Comments: Cada vez que llega un paquete, se genera un pulso en kbs_tot
// en data_type se indica el tipo de dato recibido.
// y en new_data estará el dato.
//////////////////////////////////////////////////////////////////////////////////
`define MAKE_CODE 3'b001
`define MAKE_CODE_E0 3'b010
`define BRAKE_CODE 3'b011
`define BRAKE_CODE_E0 3'b100
`define KBD_STATE_INIT 4'b0001
`define KBD_STATE_F0 4'b0010 //F0 detected
`define KBD_STATE_F0_MAKE 4'b0011 //F0 and then code
`define KBD_STATE_E0 4'b0100 //E0 detected
`define KBD_STATE_E0_F0 4'b0101 //E0 and then F0
`define KBD_STATE_E0_F0_MAKE 4'b0110 //E0_F0 and then code
`define KBD_STATE_E0_MAKE 4'b0111 //E0 and then code
`define KBD_STATE_MAKE 4'b1000 //make code
`define KBD_STATE_GEN_KBS 4'b1001 //To generate a kbs
module kbd_ms(clk,rst,kd,kc,new_data,data_type,kbs_tot,parity_error);
input clk,rst,kd,kc;
output reg[7:0] new_data;
output reg[2:0]data_type;
output reg kbs_tot;
output parity_error;
reg [3:0] kds_state_machine=`KBD_STATE_INIT;
reg [3:0] kds_state_machine_next;
wire [7:0]ps2_value;
wire kbs;
ps2_read_ms m_ps2read(clk, rst, kd, kc, kbs, ps2_value, parity_error);
//maquina de estados para saber que dato esta llegando
reg kbs_0=1'b0;
wire kbs_pe;
always@(posedge clk or posedge rst)
if (rst)
kbs_0 <= 1'b0;
else
kbs_0 <= kbs;
assign kbs_pe = (kbs & ( ~kbs_0 ) );
always@(*)
if(kbs_pe)
case(kds_state_machine)
`KBD_STATE_INIT: kds_state_machine_next=(ps2_value == 8'HF0)?`KBD_STATE_F0:
(ps2_value == 8'HE0)?`KBD_STATE_E0:
`KBD_STATE_MAKE;
`KBD_STATE_F0: kds_state_machine_next = `KBD_STATE_F0_MAKE;
`KBD_STATE_E0: kds_state_machine_next = (ps2_value == 8'HF0)?`KBD_STATE_E0_F0:
`KBD_STATE_E0_MAKE;
`KBD_STATE_E0_F0: kds_state_machine_next=`KBD_STATE_E0_F0_MAKE;
default: kds_state_machine_next=kds_state_machine;
endcase
else
case(kds_state_machine)
`KBD_STATE_INIT,
`KBD_STATE_F0,
`KBD_STATE_E0,
`KBD_STATE_E0_F0: kds_state_machine_next=kds_state_machine;
`KBD_STATE_F0_MAKE,
`KBD_STATE_E0_F0_MAKE,
`KBD_STATE_E0_MAKE,
`KBD_STATE_MAKE: kds_state_machine_next=`KBD_STATE_GEN_KBS;
`KBD_STATE_GEN_KBS: kds_state_machine_next=`KBD_STATE_INIT;
default: kds_state_machine_next=`KBD_STATE_INIT;
endcase
wire rst_state_machine;
assign rst_state_machine = parity_error|rst;
always@(posedge clk or posedge rst_state_machine)
if(rst_state_machine)
kds_state_machine <= `KBD_STATE_INIT;
else
kds_state_machine <= kds_state_machine_next;
//describiendo las salidas new_data
reg [7:0]new_data_next;
always@(*)
case(kds_state_machine)
`KBD_STATE_F0_MAKE,`KBD_STATE_E0_F0_MAKE,`KBD_STATE_E0_MAKE,`KBD_STATE_MAKE:
new_data_next = ps2_value;
default: new_data_next = new_data;
endcase
always@(posedge clk or posedge rst)
if(rst)
new_data <= 8'd0;
else
new_data <= new_data_next;
//describiendo la salida data_type;
reg [2:0]data_type_next;
always@(*)
case(kds_state_machine)
`KBD_STATE_F0_MAKE: data_type_next = `BRAKE_CODE;
`KBD_STATE_E0_F0_MAKE: data_type_next = `BRAKE_CODE_E0;
`KBD_STATE_E0_MAKE: data_type_next = `MAKE_CODE_E0;
`KBD_STATE_MAKE: data_type_next = `MAKE_CODE;
default: data_type_next = data_type;
endcase
always@(posedge clk or posedge rst)
if(rst)
data_type <= 3'd0;
else
data_type <= data_type_next;
//describiendo la salida kbs_tot;
reg kbs_tot_next;
always@(*)
if(kds_state_machine == `KBD_STATE_GEN_KBS)
kbs_tot_next = 1'b1;
else
kbs_tot_next = 1'b0;
always@(posedge clk)
kbs_tot <= kbs_tot_next;
endmodule
//////////////////////////////////////////////////////////////////////////////////
// Company: UTFSM
// Engineer: Mauricio Solis
//
// Create Date: 08:20:34 29/04/2015
// Design Name:
// Module Name: ps2_read_ms
// Project Name: Experiencia 5
// Target Devices:
// Tool versions:
// Description: Es un driver que permite recibir datos
// desde un dispositivo cuyo protocolo de
// comunicación es PS2
//
// Dependencies:
// Additional Comments:
//Cada vez que se lee un dato correctamente, se genera un pulso
//en la señal "kbs", lo que permite saber cuando leer "data"
//////////////////////////////////////////////////////////////////////////////////
module ps2_read_ms(clk,rst,kd,kc,kbs,data,parity_error);
input clk,rst,kd,kc;
output kbs;
output reg parity_error = 1'b0;
output reg [7:0]data;
reg [7:0] data_next;
reg [10:2]shift;
reg [10:2]shift_next;
reg [3:0] data_in_counter = 4'd0;
reg [3:0] data_in_counter_next;
reg [1:0]kd_s = 2'b00;
reg [1:0]kc_s = 2'b00;
reg reset_data_in_counter;
reg new_data_available = 1'b0;
reg new_data_available_next;
wire kc_ne;
assign kbs=new_data_available;
//sincronizando la entrada con el reloj de la FPGA
always@(posedge clk)
if(rst)
{kd_s,kc_s} <= 4'b0;
else
begin
kd_s <= {kd_s[0], kd};
kc_s <= {kc_s[0], kc};
end
// Canto de bajada de la senal de keyboard clock
assign kc_ne = (~kc_s[0]) & (kc_s[1]);
//asignacion del registro de desplazamiento
always@(*)
case ({rst,kc_ne})
2'b00:shift_next = shift;
2'b01:shift_next = {kd_s[1], shift[10:3]};
default:shift_next = 11'd0;
endcase
always@(posedge clk)
shift <= shift_next;
always @(*)
if(data_in_counter == 4'd11)//llego el stop y es necesario resetar la cuenta
reset_data_in_counter = 1'b1;
else
reset_data_in_counter=rst;
//contador de los bits de entrada
//por el carater sincronico del rst, la cuenta en 11 durar un ciclo de reloj
always@(*)
case({reset_data_in_counter,kc_ne})
2'b00: data_in_counter_next = data_in_counter;
2'b01: data_in_counter_next = data_in_counter + 4'd1;
default:data_in_counter_next = 4'd0;
endcase
always@(posedge clk)
data_in_counter <= data_in_counter_next;
//aviso de new data disponible
reg parity_error_next;
always@(*)
if((data_in_counter == 4'd10) && (!parity_error_next))//estamos en la paridad a la espera del stop
new_data_available_next = 1'b1;
else
new_data_available_next = 1'b0;
always@(posedge clk)
new_data_available <= new_data_available_next;
//la data
always@(*)
if(data_in_counter == 4'd9)//tengo el dato nuevo completo
data_next = shift[10:3];
else
data_next = data;
always@(posedge clk)
data <= data_next;
//checkeando paridad
wire parity_local;
assign parity_local = (^shift[10:2]);//calculando la paridad (odd)
always@(*)
if(data_in_counter == 4'd10)//acaba de llegar la paridad (ya esta almacenada)
if(parity_local == 1'b1)
parity_error_next = 1'b0;
else
parity_error_next = 1'b1;
else
parity_error_next = parity_error;
always@(posedge clk or posedge rst)
if(rst)
parity_error <= 1'b0;
else
parity_error<=parity_error_next;
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7:5.5
// IP Revision: 1
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2015.2.1" *)
(* CHECK_LICENSE_TYPE = "design_gpio_led_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *)
(* CORE_GENERATION_INFO = "design_gpio_led_processing_system7_0_0,processing_system7_v5_5_processing_system7,{x_ipProduct=Vivado 2015.2.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=processing_system7,x_ipVersion=5.5,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_EN_EMIO_PJTAG=0,C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_PIPELINE_WIDTH=8,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_IRQ_F2P_MODE=DIRECT,C_DQ_WIDTH=32,C_DQS_WIDTH=4,C_DM_WIDTH=4,C_MIO_PRIMITIVE=54,C_TRACE_INTERNAL_WIDTH=2,C_USE_AXI_NONSECURE=0,C_USE_M_AXI_GP0=1,C_USE_M_AXI_GP1=0,C_USE_S_AXI_GP0=0,C_USE_S_AXI_HP0=0,C_USE_S_AXI_HP1=0,C_USE_S_AXI_HP2=0,C_USE_S_AXI_HP3=0,C_USE_S_AXI_ACP=0,C_PS7_SI_REV=PRODUCTION,C_FCLK_CLK0_BUF=true,C_FCLK_CLK1_BUF=false,C_FCLK_CLK2_BUF=false,C_FCLK_CLK3_BUF=false,C_PACKAGE_NAME=clg484}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_gpio_led_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_RX" *)
output wire ENET0_PTP_DELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 DELAY_REQ_TX" *)
output wire ENET0_PTP_DELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_RX" *)
output wire ENET0_PTP_PDELAY_REQ_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_REQ_TX" *)
output wire ENET0_PTP_PDELAY_REQ_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_RX" *)
output wire ENET0_PTP_PDELAY_RESP_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 PDELAY_RESP_TX" *)
output wire ENET0_PTP_PDELAY_RESP_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_RX" *)
output wire ENET0_PTP_SYNC_FRAME_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SYNC_FRAME_TX" *)
output wire ENET0_PTP_SYNC_FRAME_TX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_RX" *)
output wire ENET0_SOF_RX;
(* X_INTERFACE_INFO = "xilinx.com:interface:ptp:1.0 PTP_ETHERNET_0 SOF_TX" *)
output wire ENET0_SOF_TX;
output wire TTC0_WAVE0_OUT;
output wire TTC0_WAVE1_OUT;
output wire TTC0_WAVE2_OUT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *)
output wire [1 : 0] USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *)
output wire USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *)
input wire USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *)
output wire M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *)
output wire M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *)
output wire M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *)
output wire M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *)
output wire M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *)
output wire M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *)
output wire [11 : 0] M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *)
output wire [11 : 0] M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *)
output wire [11 : 0] M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *)
output wire [1 : 0] M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *)
output wire [1 : 0] M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *)
output wire [2 : 0] M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *)
output wire [1 : 0] M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *)
output wire [1 : 0] M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *)
output wire [2 : 0] M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *)
output wire [2 : 0] M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *)
output wire [2 : 0] M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *)
output wire [31 : 0] M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *)
output wire [31 : 0] M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *)
output wire [31 : 0] M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *)
output wire [3 : 0] M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *)
output wire [3 : 0] M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *)
output wire [3 : 0] M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *)
output wire [3 : 0] M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *)
output wire [3 : 0] M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *)
output wire [3 : 0] M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *)
output wire [3 : 0] M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *)
input wire M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *)
input wire M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *)
input wire M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *)
input wire M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *)
input wire M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *)
input wire M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *)
input wire M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *)
input wire [11 : 0] M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *)
input wire [11 : 0] M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *)
input wire [1 : 0] M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *)
input wire [1 : 0] M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *)
input wire [31 : 0] M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *)
output wire FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *)
output wire FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *)
inout wire [53 : 0] MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *)
inout wire DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *)
inout wire DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *)
inout wire DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *)
inout wire DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *)
inout wire DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *)
inout wire DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *)
inout wire DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *)
inout wire DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *)
inout wire DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *)
inout wire [2 : 0] DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *)
inout wire [14 : 0] DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *)
inout wire DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *)
inout wire DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *)
inout wire [3 : 0] DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *)
inout wire [31 : 0] DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *)
inout wire [3 : 0] DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *)
inout wire [3 : 0] DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *)
inout wire PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *)
inout wire PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *)
inout wire PS_PORB;
processing_system7_v5_5_processing_system7 #(
.C_EN_EMIO_PJTAG(0),
.C_EN_EMIO_ENET0(0),
.C_EN_EMIO_ENET1(0),
.C_EN_EMIO_TRACE(0),
.C_INCLUDE_TRACE_BUFFER(0),
.C_TRACE_BUFFER_FIFO_SIZE(128),
.USE_TRACE_DATA_EDGE_DETECTOR(0),
.C_TRACE_PIPELINE_WIDTH(8),
.C_TRACE_BUFFER_CLOCK_DELAY(12),
.C_EMIO_GPIO_WIDTH(64),
.C_INCLUDE_ACP_TRANS_CHECK(0),
.C_USE_DEFAULT_ACP_USER_VAL(0),
.C_S_AXI_ACP_ARUSER_VAL(31),
.C_S_AXI_ACP_AWUSER_VAL(31),
.C_M_AXI_GP0_ID_WIDTH(12),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ID_WIDTH(12),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_S_AXI_GP0_ID_WIDTH(6),
.C_S_AXI_GP1_ID_WIDTH(6),
.C_S_AXI_ACP_ID_WIDTH(3),
.C_S_AXI_HP0_ID_WIDTH(6),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_ID_WIDTH(6),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_ID_WIDTH(6),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_ID_WIDTH(6),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_M_AXI_GP0_THREAD_ID_WIDTH(12),
.C_M_AXI_GP1_THREAD_ID_WIDTH(12),
.C_NUM_F2P_INTR_INPUTS(1),
.C_IRQ_F2P_MODE("DIRECT"),
.C_DQ_WIDTH(32),
.C_DQS_WIDTH(4),
.C_DM_WIDTH(4),
.C_MIO_PRIMITIVE(54),
.C_TRACE_INTERNAL_WIDTH(2),
.C_USE_AXI_NONSECURE(0),
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_USE_S_AXI_ACP(0),
.C_PS7_SI_REV("PRODUCTION"),
.C_FCLK_CLK0_BUF("true"),
.C_FCLK_CLK1_BUF("false"),
.C_FCLK_CLK2_BUF("false"),
.C_FCLK_CLK3_BUF("false"),
.C_PACKAGE_NAME("clg484")
) inst (
.CAN0_PHY_TX(),
.CAN0_PHY_RX(1'B0),
.CAN1_PHY_TX(),
.CAN1_PHY_RX(1'B0),
.ENET0_GMII_TX_EN(),
.ENET0_GMII_TX_ER(),
.ENET0_MDIO_MDC(),
.ENET0_MDIO_O(),
.ENET0_MDIO_T(),
.ENET0_PTP_DELAY_REQ_RX(ENET0_PTP_DELAY_REQ_RX),
.ENET0_PTP_DELAY_REQ_TX(ENET0_PTP_DELAY_REQ_TX),
.ENET0_PTP_PDELAY_REQ_RX(ENET0_PTP_PDELAY_REQ_RX),
.ENET0_PTP_PDELAY_REQ_TX(ENET0_PTP_PDELAY_REQ_TX),
.ENET0_PTP_PDELAY_RESP_RX(ENET0_PTP_PDELAY_RESP_RX),
.ENET0_PTP_PDELAY_RESP_TX(ENET0_PTP_PDELAY_RESP_TX),
.ENET0_PTP_SYNC_FRAME_RX(ENET0_PTP_SYNC_FRAME_RX),
.ENET0_PTP_SYNC_FRAME_TX(ENET0_PTP_SYNC_FRAME_TX),
.ENET0_SOF_RX(ENET0_SOF_RX),
.ENET0_SOF_TX(ENET0_SOF_TX),
.ENET0_GMII_TXD(),
.ENET0_GMII_COL(1'B0),
.ENET0_GMII_CRS(1'B0),
.ENET0_GMII_RX_CLK(1'B0),
.ENET0_GMII_RX_DV(1'B0),
.ENET0_GMII_RX_ER(1'B0),
.ENET0_GMII_TX_CLK(1'B0),
.ENET0_MDIO_I(1'B0),
.ENET0_EXT_INTIN(1'B0),
.ENET0_GMII_RXD(8'B0),
.ENET1_GMII_TX_EN(),
.ENET1_GMII_TX_ER(),
.ENET1_MDIO_MDC(),
.ENET1_MDIO_O(),
.ENET1_MDIO_T(),
.ENET1_PTP_DELAY_REQ_RX(),
.ENET1_PTP_DELAY_REQ_TX(),
.ENET1_PTP_PDELAY_REQ_RX(),
.ENET1_PTP_PDELAY_REQ_TX(),
.ENET1_PTP_PDELAY_RESP_RX(),
.ENET1_PTP_PDELAY_RESP_TX(),
.ENET1_PTP_SYNC_FRAME_RX(),
.ENET1_PTP_SYNC_FRAME_TX(),
.ENET1_SOF_RX(),
.ENET1_SOF_TX(),
.ENET1_GMII_TXD(),
.ENET1_GMII_COL(1'B0),
.ENET1_GMII_CRS(1'B0),
.ENET1_GMII_RX_CLK(1'B0),
.ENET1_GMII_RX_DV(1'B0),
.ENET1_GMII_RX_ER(1'B0),
.ENET1_GMII_TX_CLK(1'B0),
.ENET1_MDIO_I(1'B0),
.ENET1_EXT_INTIN(1'B0),
.ENET1_GMII_RXD(8'B0),
.GPIO_I(64'B0),
.GPIO_O(),
.GPIO_T(),
.I2C0_SDA_I(1'B0),
.I2C0_SDA_O(),
.I2C0_SDA_T(),
.I2C0_SCL_I(1'B0),
.I2C0_SCL_O(),
.I2C0_SCL_T(),
.I2C1_SDA_I(1'B0),
.I2C1_SDA_O(),
.I2C1_SDA_T(),
.I2C1_SCL_I(1'B0),
.I2C1_SCL_O(),
.I2C1_SCL_T(),
.PJTAG_TCK(1'B0),
.PJTAG_TMS(1'B0),
.PJTAG_TDI(1'B0),
.PJTAG_TDO(),
.SDIO0_CLK(),
.SDIO0_CLK_FB(1'B0),
.SDIO0_CMD_O(),
.SDIO0_CMD_I(1'B0),
.SDIO0_CMD_T(),
.SDIO0_DATA_I(4'B0),
.SDIO0_DATA_O(),
.SDIO0_DATA_T(),
.SDIO0_LED(),
.SDIO0_CDN(1'B0),
.SDIO0_WP(1'B0),
.SDIO0_BUSPOW(),
.SDIO0_BUSVOLT(),
.SDIO1_CLK(),
.SDIO1_CLK_FB(1'B0),
.SDIO1_CMD_O(),
.SDIO1_CMD_I(1'B0),
.SDIO1_CMD_T(),
.SDIO1_DATA_I(4'B0),
.SDIO1_DATA_O(),
.SDIO1_DATA_T(),
.SDIO1_LED(),
.SDIO1_CDN(1'B0),
.SDIO1_WP(1'B0),
.SDIO1_BUSPOW(),
.SDIO1_BUSVOLT(),
.SPI0_SCLK_I(1'B0),
.SPI0_SCLK_O(),
.SPI0_SCLK_T(),
.SPI0_MOSI_I(1'B0),
.SPI0_MOSI_O(),
.SPI0_MOSI_T(),
.SPI0_MISO_I(1'B0),
.SPI0_MISO_O(),
.SPI0_MISO_T(),
.SPI0_SS_I(1'B0),
.SPI0_SS_O(),
.SPI0_SS1_O(),
.SPI0_SS2_O(),
.SPI0_SS_T(),
.SPI1_SCLK_I(1'B0),
.SPI1_SCLK_O(),
.SPI1_SCLK_T(),
.SPI1_MOSI_I(1'B0),
.SPI1_MOSI_O(),
.SPI1_MOSI_T(),
.SPI1_MISO_I(1'B0),
.SPI1_MISO_O(),
.SPI1_MISO_T(),
.SPI1_SS_I(1'B0),
.SPI1_SS_O(),
.SPI1_SS1_O(),
.SPI1_SS2_O(),
.SPI1_SS_T(),
.UART0_DTRN(),
.UART0_RTSN(),
.UART0_TX(),
.UART0_CTSN(1'B0),
.UART0_DCDN(1'B0),
.UART0_DSRN(1'B0),
.UART0_RIN(1'B0),
.UART0_RX(1'B1),
.UART1_DTRN(),
.UART1_RTSN(),
.UART1_TX(),
.UART1_CTSN(1'B0),
.UART1_DCDN(1'B0),
.UART1_DSRN(1'B0),
.UART1_RIN(1'B0),
.UART1_RX(1'B1),
.TTC0_WAVE0_OUT(TTC0_WAVE0_OUT),
.TTC0_WAVE1_OUT(TTC0_WAVE1_OUT),
.TTC0_WAVE2_OUT(TTC0_WAVE2_OUT),
.TTC0_CLK0_IN(1'B0),
.TTC0_CLK1_IN(1'B0),
.TTC0_CLK2_IN(1'B0),
.TTC1_WAVE0_OUT(),
.TTC1_WAVE1_OUT(),
.TTC1_WAVE2_OUT(),
.TTC1_CLK0_IN(1'B0),
.TTC1_CLK1_IN(1'B0),
.TTC1_CLK2_IN(1'B0),
.WDT_CLK_IN(1'B0),
.WDT_RST_OUT(),
.TRACE_CLK(1'B0),
.TRACE_CLK_OUT(),
.TRACE_CTL(),
.TRACE_DATA(),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB1_PORT_INDCTL(),
.USB1_VBUS_PWRSELECT(),
.USB1_VBUS_PWRFAULT(1'B0),
.SRAM_INTIN(1'B0),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_RCOUNT(),
.S_AXI_HP0_WCOUNT(),
.S_AXI_HP0_RACOUNT(),
.S_AXI_HP0_WACOUNT(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RDISSUECAP1_EN(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WRISSUECAP1_EN(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_RCOUNT(),
.S_AXI_HP1_WCOUNT(),
.S_AXI_HP1_RACOUNT(),
.S_AXI_HP1_WACOUNT(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RDISSUECAP1_EN(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WRISSUECAP1_EN(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_RCOUNT(),
.S_AXI_HP2_WCOUNT(),
.S_AXI_HP2_RACOUNT(),
.S_AXI_HP2_WACOUNT(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RDISSUECAP1_EN(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WRISSUECAP1_EN(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_RCOUNT(),
.S_AXI_HP3_WCOUNT(),
.S_AXI_HP3_RACOUNT(),
.S_AXI_HP3_WACOUNT(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RDISSUECAP1_EN(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WRISSUECAP1_EN(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.IRQ_P2F_DMAC_ABORT(),
.IRQ_P2F_DMAC0(),
.IRQ_P2F_DMAC1(),
.IRQ_P2F_DMAC2(),
.IRQ_P2F_DMAC3(),
.IRQ_P2F_DMAC4(),
.IRQ_P2F_DMAC5(),
.IRQ_P2F_DMAC6(),
.IRQ_P2F_DMAC7(),
.IRQ_P2F_SMC(),
.IRQ_P2F_QSPI(),
.IRQ_P2F_CTI(),
.IRQ_P2F_GPIO(),
.IRQ_P2F_USB0(),
.IRQ_P2F_ENET0(),
.IRQ_P2F_ENET_WAKE0(),
.IRQ_P2F_SDIO0(),
.IRQ_P2F_I2C0(),
.IRQ_P2F_SPI0(),
.IRQ_P2F_UART0(),
.IRQ_P2F_CAN0(),
.IRQ_P2F_USB1(),
.IRQ_P2F_ENET1(),
.IRQ_P2F_ENET_WAKE1(),
.IRQ_P2F_SDIO1(),
.IRQ_P2F_I2C1(),
.IRQ_P2F_SPI1(),
.IRQ_P2F_UART1(),
.IRQ_P2F_CAN1(),
.IRQ_F2P(1'B0),
.Core0_nFIQ(1'B0),
.Core0_nIRQ(1'B0),
.Core1_nFIQ(1'B0),
.Core1_nIRQ(1'B0),
.DMA0_DATYPE(),
.DMA0_DAVALID(),
.DMA0_DRREADY(),
.DMA1_DATYPE(),
.DMA1_DAVALID(),
.DMA1_DRREADY(),
.DMA2_DATYPE(),
.DMA2_DAVALID(),
.DMA2_DRREADY(),
.DMA3_DATYPE(),
.DMA3_DAVALID(),
.DMA3_DRREADY(),
.DMA0_ACLK(1'B0),
.DMA0_DAREADY(1'B0),
.DMA0_DRLAST(1'B0),
.DMA0_DRVALID(1'B0),
.DMA1_ACLK(1'B0),
.DMA1_DAREADY(1'B0),
.DMA1_DRLAST(1'B0),
.DMA1_DRVALID(1'B0),
.DMA2_ACLK(1'B0),
.DMA2_DAREADY(1'B0),
.DMA2_DRLAST(1'B0),
.DMA2_DRVALID(1'B0),
.DMA3_ACLK(1'B0),
.DMA3_DAREADY(1'B0),
.DMA3_DRLAST(1'B0),
.DMA3_DRVALID(1'B0),
.DMA0_DRTYPE(2'B0),
.DMA1_DRTYPE(2'B0),
.DMA2_DRTYPE(2'B0),
.DMA3_DRTYPE(2'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_CLKTRIG0_N(1'B0),
.FCLK_CLKTRIG1_N(1'B0),
.FCLK_CLKTRIG2_N(1'B0),
.FCLK_CLKTRIG3_N(1'B0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.FTMD_TRACEIN_DATA(32'B0),
.FTMD_TRACEIN_VALID(1'B0),
.FTMD_TRACEIN_CLK(1'B0),
.FTMD_TRACEIN_ATID(4'B0),
.FTMT_F2P_TRIG_0(1'B0),
.FTMT_F2P_TRIGACK_0(),
.FTMT_F2P_TRIG_1(1'B0),
.FTMT_F2P_TRIGACK_1(),
.FTMT_F2P_TRIG_2(1'B0),
.FTMT_F2P_TRIGACK_2(),
.FTMT_F2P_TRIG_3(1'B0),
.FTMT_F2P_TRIGACK_3(),
.FTMT_F2P_DEBUG(32'B0),
.FTMT_P2F_TRIGACK_0(1'B0),
.FTMT_P2F_TRIG_0(),
.FTMT_P2F_TRIGACK_1(1'B0),
.FTMT_P2F_TRIG_1(),
.FTMT_P2F_TRIGACK_2(1'B0),
.FTMT_P2F_TRIG_2(),
.FTMT_P2F_TRIGACK_3(1'B0),
.FTMT_P2F_TRIG_3(),
.FTMT_P2F_DEBUG(),
.FPGA_IDLE_N(1'B0),
.EVENT_EVENTO(),
.EVENT_STANDBYWFE(),
.EVENT_STANDBYWFI(),
.EVENT_EVENTI(1'B0),
.DDR_ARB(4'B0),
.MIO(MIO),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_Clk_n(DDR_Clk_n),
.DDR_Clk(DDR_Clk),
.DDR_CS_n(DDR_CS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_WEB(DDR_WEB),
.DDR_BankAddr(DDR_BankAddr),
.DDR_Addr(DDR_Addr),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DQS(DDR_DQS),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR3_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__OR3_BEHAVIORAL_PP_V
/**
* or3: 3-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__or3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A, C );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR3_BEHAVIORAL_PP_V |
// -- (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
//-----------------------------------------------------------------------------
//
// File name: cdn_axi_bfm_0.v
//
// Description: Verilog wrapper for Cadence's "cdn_axi_bfm" module.
//
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
//-----------------------------------------------------------------------------
// The AXI4 Streaming Master BFM Top Level Wrapper
//-----------------------------------------------------------------------------
module cdn_axi_bfm_0 (m_axis_aclk, m_axis_aresetn,
m_axis_tvalid, m_axis_tready, m_axis_tdata,
m_axis_tkeep,m_axis_tid,m_axis_tdest,m_axis_tuser, m_axis_tlast);
//-----------------------------------------------------------------------------
parameter C_M_AXIS_NAME = "cdn_axi_bfm_0";
parameter C_M_AXIS_TDATA_WIDTH = 24;
parameter C_M_AXIS_TID_WIDTH = 8;
parameter C_M_AXIS_TDEST_WIDTH = 4;
parameter C_M_AXIS_TUSER_WIDTH = 8;
parameter C_M_AXIS_MAX_PACKET_SIZE = 10;
parameter C_M_AXIS_MAX_OUTSTANDING_TRANSACTIONS = 8;
parameter C_INTERCONNECT_M_AXIS_WRITE_ISSUING = 8;
parameter C_M_AXIS_STROBE_NOT_USED = 1;
parameter C_M_AXIS_KEEP_NOT_USED = 0;
//------------------------------------------------------------------------
// Signal Definitions
//------------------------------------------------------------------------
// Global Clock Input. All signals are sampled on the rising edge.
input wire m_axis_aclk;
// Internal Clock created by delaying the input clock and used for sampling
// and driving input and output signals respectively to avoid race conditions.
//wire bfm_aclk;
// Global Reset Input. Active Low.
input wire m_axis_aresetn;
// Transfer Channel Signals.
output wire m_axis_tvalid; // Master Transfer Valid.
input wire m_axis_tready; // Slave Transfer Ready.
output wire [C_M_AXIS_TDATA_WIDTH-1:0] m_axis_tdata; // Master Transfer Data.
output wire [(C_M_AXIS_TDATA_WIDTH/8)-1:0] m_axis_tkeep; // Master Transfer Keep.
output wire m_axis_tlast; // Master Transfer Last Flag.
output wire [C_M_AXIS_TID_WIDTH-1:0] m_axis_tid; // Master Transfer ID Tag.
output wire [C_M_AXIS_TDEST_WIDTH-1:0] m_axis_tdest; // Master Transfer Destination.
output wire [C_M_AXIS_TUSER_WIDTH-1:0] m_axis_tuser; // Master Transfer User Defined.
cdn_axi4_streaming_master_bfm #(.NAME(C_M_AXIS_NAME),
.DATA_BUS_WIDTH(C_M_AXIS_TDATA_WIDTH),
.ID_BUS_WIDTH(C_M_AXIS_TID_WIDTH),
.DEST_BUS_WIDTH(C_M_AXIS_TDEST_WIDTH),
.USER_BUS_WIDTH(C_M_AXIS_TUSER_WIDTH),
.MAX_PACKET_SIZE(C_M_AXIS_MAX_PACKET_SIZE),
.MAX_OUTSTANDING_TRANSACTIONS(C_M_AXIS_MAX_OUTSTANDING_TRANSACTIONS),
.STROBE_NOT_USED(C_M_AXIS_STROBE_NOT_USED),
.KEEP_NOT_USED(C_M_AXIS_KEEP_NOT_USED)
)
cdn_axi4_streaming_master_bfm_inst(.ACLK(m_axis_aclk),
.ARESETn(m_axis_aresetn),
.TVALID(m_axis_tvalid),
.TREADY(m_axis_tready),
.TDATA(m_axis_tdata),
.TKEEP(m_axis_tkeep),
.TID(m_axis_tid),
.TDEST(m_axis_tdest),
.TUSER(m_axis_tuser),
.TLAST(m_axis_tlast)
);
// These runtime parameters are set based on selection in GUI
// All these parameters can be changed during the runtime in the TB also
initial
begin
cdn_axi4_streaming_master_bfm_inst.set_response_timeout(500);
cdn_axi4_streaming_master_bfm_inst.set_clear_signals_after_handshake(0);
cdn_axi4_streaming_master_bfm_inst.set_stop_on_error(1);
cdn_axi4_streaming_master_bfm_inst.set_channel_level_info(0);
cdn_axi4_streaming_master_bfm_inst.set_packet_transfer_gap(0);
cdn_axi4_streaming_master_bfm_inst.set_task_call_and_reset_handling(0);
cdn_axi4_streaming_master_bfm_inst.set_input_signal_delay(0);
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`include "std_ovl_defines.h"
`module ovl_reg_loaded (clock, reset, enable, start_event, end_event, src_expr, dest_expr, fire);
parameter severity_level = `OVL_SEVERITY_DEFAULT;
parameter width = 4;
parameter start_count = 1;
parameter end_count = 10;
parameter property_type = `OVL_PROPERTY_DEFAULT;
parameter msg = `OVL_MSG_DEFAULT;
parameter coverage_level = `OVL_COVER_DEFAULT;
parameter clock_edge = `OVL_CLOCK_EDGE_DEFAULT;
parameter reset_polarity = `OVL_RESET_POLARITY_DEFAULT;
parameter gating_type = `OVL_GATING_TYPE_DEFAULT;
input clock, reset, enable;
input start_event, end_event;
input [width-1 : 0] src_expr, dest_expr;
output [`OVL_FIRE_WIDTH-1 : 0] fire;
// Parameters that should not be edited
parameter assert_name = "OVL_REG_LOADED";
`include "std_ovl_reset.h"
`include "std_ovl_clock.h"
`include "std_ovl_cover.h"
`include "std_ovl_task.h"
`include "std_ovl_init.h"
`ifdef OVL_SVA
`include "./sva05/ovl_reg_loaded_logic.sv"
assign fire = {`OVL_FIRE_WIDTH{1'b0}}; // Tied low in V2.3
`endif
`endmodule // ovl_reg_loaded
|
/*
Copyright (c) 2014 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream rate limiter (64 bit datapath)
*/
module axis_rate_limit_64 #
(
parameter DATA_WIDTH = 64,
parameter KEEP_WIDTH = (DATA_WIDTH/8)
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Configuration
*/
input wire [7:0] rate_num,
input wire [7:0] rate_denom,
input wire rate_by_frame
);
// internal datapath
reg [DATA_WIDTH-1:0] output_axis_tdata_int;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_int;
reg output_axis_tvalid_int;
reg output_axis_tready_int = 0;
reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early;
reg [23:0] acc_reg = 0, acc_next;
reg pause;
reg frame_reg = 0, frame_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
assign input_axis_tready = input_axis_tready_reg;
always @* begin
acc_next = acc_reg;
pause = 0;
frame_next = frame_reg & ~input_axis_tlast;
if (acc_reg >= rate_num) begin
acc_next = acc_reg - rate_num;
end
if (input_axis_tready & input_axis_tvalid) begin
// read input
frame_next = ~input_axis_tlast;
acc_next = acc_reg + (rate_denom - rate_num);
end
if (acc_next >= rate_num) begin
if (rate_by_frame) begin
pause = ~frame_next;
end else begin
pause = 1;
end
end
input_axis_tready_next = output_axis_tready_int_early & ~pause;
output_axis_tdata_int = input_axis_tdata;
output_axis_tkeep_int = input_axis_tkeep;
output_axis_tvalid_int = input_axis_tvalid & input_axis_tready;
output_axis_tlast_int = input_axis_tlast;
output_axis_tuser_int = input_axis_tuser;
end
always @(posedge clk or posedge rst) begin
if (rst) begin
acc_reg <= 0;
frame_reg <= 0;
input_axis_tready_reg <= 0;
end else begin
acc_reg <= acc_next;
frame_reg <= frame_next;
input_axis_tready_reg <= input_axis_tready_next;
end
end
// output datapath logic
reg [DATA_WIDTH-1:0] output_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] output_axis_tkeep_reg = 0;
reg output_axis_tvalid_reg = 0;
reg output_axis_tlast_reg = 0;
reg output_axis_tuser_reg = 0;
reg [DATA_WIDTH-1:0] temp_axis_tdata_reg = 0;
reg [KEEP_WIDTH-1:0] temp_axis_tkeep_reg = 0;
reg temp_axis_tvalid_reg = 0;
reg temp_axis_tlast_reg = 0;
reg temp_axis_tuser_reg = 0;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tkeep = output_axis_tkeep_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
// enable ready input next cycle if output is ready or if there is space in both output registers or if there is space in the temp register that will not be filled next cycle
assign output_axis_tready_int_early = output_axis_tready | (~temp_axis_tvalid_reg & ~output_axis_tvalid_reg) | (~temp_axis_tvalid_reg & ~output_axis_tvalid_int);
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tdata_reg <= 0;
output_axis_tkeep_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
output_axis_tready_int <= 0;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end else begin
// transfer sink ready state to source
output_axis_tready_int <= output_axis_tready_int_early;
if (output_axis_tready_int) begin
// input is ready
if (output_axis_tready | ~output_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
output_axis_tdata_reg <= output_axis_tdata_int;
output_axis_tkeep_reg <= output_axis_tkeep_int;
output_axis_tvalid_reg <= output_axis_tvalid_int;
output_axis_tlast_reg <= output_axis_tlast_int;
output_axis_tuser_reg <= output_axis_tuser_int;
end else begin
// output is not ready, store input in temp
temp_axis_tdata_reg <= output_axis_tdata_int;
temp_axis_tkeep_reg <= output_axis_tkeep_int;
temp_axis_tvalid_reg <= output_axis_tvalid_int;
temp_axis_tlast_reg <= output_axis_tlast_int;
temp_axis_tuser_reg <= output_axis_tuser_int;
end
end else if (output_axis_tready) begin
// input is not ready, but output is ready
output_axis_tdata_reg <= temp_axis_tdata_reg;
output_axis_tkeep_reg <= temp_axis_tkeep_reg;
output_axis_tvalid_reg <= temp_axis_tvalid_reg;
output_axis_tlast_reg <= temp_axis_tlast_reg;
output_axis_tuser_reg <= temp_axis_tuser_reg;
temp_axis_tdata_reg <= 0;
temp_axis_tkeep_reg <= 0;
temp_axis_tvalid_reg <= 0;
temp_axis_tlast_reg <= 0;
temp_axis_tuser_reg <= 0;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CONB_BEHAVIORAL_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__conb (
HI,
LO
);
// Module ports
output HI;
output LO;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Name Output
pullup pullup0 (HI );
pulldown pulldown0 (LO );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_BEHAVIORAL_V |
// ======================================================================
// BLE_Simple_ADC.v generated from TopDesign.cysch
// 11/10/2016 at 19:12
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4G 2
`define CYDEV_CHIP_REVISION_4G_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4G_ES 17
`define CYDEV_CHIP_REVISION_4G_ES2 33
`define CYDEV_CHIP_MEMBER_4U 3
`define CYDEV_CHIP_REVISION_4U_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4E 4
`define CYDEV_CHIP_REVISION_4E_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4O 5
`define CYDEV_CHIP_REVISION_4O_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4N 6
`define CYDEV_CHIP_REVISION_4N_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4D 7
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4J 8
`define CYDEV_CHIP_REVISION_4J_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4K 9
`define CYDEV_CHIP_REVISION_4K_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4H 10
`define CYDEV_CHIP_REVISION_4H_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4A 11
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4F 12
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4F 13
`define CYDEV_CHIP_REVISION_4F_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0
`define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0
`define CYDEV_CHIP_MEMBER_4M 14
`define CYDEV_CHIP_REVISION_4M_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4L 15
`define CYDEV_CHIP_REVISION_4L_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4I 16
`define CYDEV_CHIP_REVISION_4I_PRODUCTION 0
`define CYDEV_CHIP_MEMBER_4C 17
`define CYDEV_CHIP_REVISION_4C_PRODUCTION 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5B 18
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_MEMBER_5A 19
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 13
`define CYDEV_CHIP_REVISION_USED 0
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// BLE_v3_10(AutopopulateWhitelist=true, EnableExternalPAcontrol=false, EnableExternalPrepWriteBuff=false, EnableL2capLogicalChannels=true, EnableLinkLayerPrivacy=false, GapConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<CyGapConfiguration xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema">\r\n <DevAddress>00A050000000</DevAddress>\r\n <SiliconGeneratedAddress>false</SiliconGeneratedAddress>\r\n <MtuSize>23</MtuSize>\r\n <MaxTxPayloadSize>27</MaxTxPayloadSize>\r\n <MaxRxPayloadSize>27</MaxRxPayloadSize>\r\n <TxPowerLevel>0</TxPowerLevel>\r\n <TxPowerLevelConnection>0</TxPowerLevelConnection>\r\n <TxPowerLevelAdvScan>0</TxPowerLevelAdvScan>\r\n <SecurityConfig>\r\n <SecurityMode>SECURITY_MODE_1</SecurityMode>\r\n <SecurityLevel>NO_SECURITY</SecurityLevel>\r\n <StrictPairing>false</StrictPairing>\r\n <KeypressNotifications>false</KeypressNotifications>\r\n <IOCapability>DISPLAY</IOCapability>\r\n <PairingMethod>JUST_WORKS</PairingMethod>\r\n <Bonding>BOND</Bonding>\r\n <MaxBondedDevices>4</MaxBondedDevices>\r\n <AutoPopWhitelistBondedDev>true</AutoPopWhitelistBondedDev>\r\n <MaxWhitelistSize>8</MaxWhitelistSize>\r\n <EnableLinkLayerPrivacy>false</EnableLinkLayerPrivacy>\r\n <MaxResolvableDevices>8</MaxResolvableDevices>\r\n <EncryptionKeySize>16</EncryptionKeySize>\r\n </SecurityConfig>\r\n <AdvertisementConfig>\r\n <AdvScanMode>FAST_CONNECTION</AdvScanMode>\r\n <AdvFastScanInterval>\r\n <Minimum>20</Minimum>\r\n <Maximum>30</Maximum>\r\n </AdvFastScanInterval>\r\n <AdvReducedScanInterval>\r\n <Minimum>1000</Minimum>\r\n <Maximum>1000</Maximum>\r\n </AdvReducedScanInterval>\r\n <AdvDiscoveryMode>GENERAL</AdvDiscoveryMode>\r\n <AdvType>CONNECTABLE_UNDIRECTED</AdvType>\r\n <AdvFilterPolicy>SCAN_REQUEST_ANY_CONNECT_REQUEST_ANY</AdvFilterPolicy>\r\n <AdvChannelMap>ALL</AdvChannelMap>\r\n <AdvFastTimeout>30</AdvFastTimeout>\r\n <AdvReducedTimeout>0</AdvReducedTimeout>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </AdvertisementConfig>\r\n <ScanConfig>\r\n <ScanFastWindow>30</ScanFastWindow>\r\n <ScanFastInterval>30</ScanFastInterval>\r\n <ScanTimeout>30</ScanTimeout>\r\n <ScanReducedWindow>1125</ScanReducedWindow>\r\n <ScanReducedInterval>1280</ScanReducedInterval>\r\n <ScanReducedTimeout>150</ScanReducedTimeout>\r\n <EnableReducedScan>true</EnableReducedScan>\r\n <ScanDiscoveryMode>GENERAL</ScanDiscoveryMode>\r\n <ScanningState>ACTIVE</ScanningState>\r\n <ScanFilterPolicy>ACCEPT_ALL_ADV_PACKETS</ScanFilterPolicy>\r\n <DuplicateFiltering>false</DuplicateFiltering>\r\n <ConnectionInterval>\r\n <Minimum>7.5</Minimum>\r\n <Maximum>50</Maximum>\r\n </ConnectionInterval>\r\n <ConnectionSlaveLatency>0</ConnectionSlaveLatency>\r\n <ConnectionTimeout>10000</ConnectionTimeout>\r\n </ScanConfig>\r\n <AdvertisementPacket>\r\n <PacketType>ADVERTISEMENT</PacketType>\r\n <Items>\r\n <CyADStructure>\r\n <ADType>1</ADType>\r\n <ADData>06</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>9</ADType>\r\n <ADData>42:4C:45:20:41:44:43</ADData>\r\n </CyADStructure>\r\n <CyADStructure>\r\n <ADType>27</ADType>\r\n <ADData>00:00:00:00:50:A0:00</ADData>\r\n </CyADStructure>\r\n </Items>\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </AdvertisementPacket>\r\n <ScanResponsePacket>\r\n <PacketType>SCAN_RESPONSE</PacketType>\r\n <Items />\r\n <IncludedServicesServiceUuid />\r\n <IncludedServicesServiceSolicitation />\r\n <IncludedServicesServiceData />\r\n </ScanResponsePacket>\r\n</CyGapConfiguration>, HalBaudRate=115200, ImportFilePath=, KeypressNotifications=false, L2capMpsSize=23, L2capMtuSize=23, L2capNumChannels=1, L2capNumPsm=1, LLMaxRxPayloadSize=27, LLMaxTxPayloadSize=27, MaxAttrNoOfBuffer=1, MaxBondedDevices=4, MaxResolvableDevices=8, MaxWhitelistSize=8, Mode=0, ProfileConfig=<?xml version="1.0" encoding="utf-16"?>\r\n<Profile xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" ID="1" DisplayName="Custom" Name="Custom" Type="org.bluetooth.profile.custom">\r\n <CyProfileRole ID="2" DisplayName="Server" Name="Server">\r\n <CyService ID="3" DisplayName="Generic Access" Name="Generic Access" Type="org.bluetooth.service.generic_access" UUID="1800">\r\n <CyCharacteristic ID="4" DisplayName="Device Name" Name="Device Name" Type="org.bluetooth.characteristic.gap.device_name" UUID="2A00">\r\n <Field Name="Name">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>7</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>BLE ADC</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="5" DisplayName="Appearance" Name="Appearance" Type="org.bluetooth.characteristic.gap.appearance" UUID="2A01">\r\n <Field Name="Category">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="6" DisplayName="Peripheral Preferred Connection Parameters" Name="Peripheral Preferred Connection Parameters" Type="org.bluetooth.characteristic.gap.peripheral_preferred_connection_parameters" UUID="2A04">\r\n <Field Name="Minimum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0006</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Maximum Connection Interval">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>6</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x0028</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Slave Latency">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>1000</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="Connection Supervision Timeout Multiplier">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>10</Minimum>\r\n <Maximum>3200</Maximum>\r\n </Range>\r\n <FillRequirement>C1</FillRequirement>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>0x03E8</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <CyCharacteristic ID="7" DisplayName="Central Address Resolution" Name="Central Address Resolution" Type="org.bluetooth.characteristic.gap.central_address_resolution" UUID="2AA6">\r\n <Field Name="Central Address Resolution Support">\r\n <DataFormat>uint8</DataFormat>\r\n <ByteLength>1</ByteLength>\r\n <ValueType>ENUM</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="8" DisplayName="Generic Attribute" Name="Generic Attribute" Type="org.bluetooth.service.generic_attribute" UUID="1801">\r\n <CyCharacteristic ID="9" DisplayName="Service Changed" Name="Service Changed" Type="org.bluetooth.characteristic.gatt.service_changed" UUID="2A05">\r\n <CyDescriptor ID="10" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="true" />\r\n <Property Type="WRITE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <Field Name="Start of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Field Name="End of Affected Attribute Handle Range">\r\n <DataFormat>uint16</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>1</Minimum>\r\n <Maximum>65535</Maximum>\r\n </Range>\r\n <ValueType>BASIC</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="INDICATE" Present="true" Mandatory="true" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>NONE</AccessPermission>\r\n </Permission>\r\n </CyCharacteristic>\r\n <Declaration>Primary</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <CyService ID="11" DisplayName="ADC Service" Name="Custom Service" Type="org.bluetooth.service.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyCharacteristic ID="12" DisplayName="ADC_Read" Name="Custom Characteristic" Type="org.bluetooth.characteristic.custom" UUID="0000000000001000800000805F9B34FB">\r\n <CyDescriptor ID="14" DisplayName="Client Characteristic Configuration" Name="Client Characteristic Configuration" Type="org.bluetooth.descriptor.gatt.client_characteristic_configuration" UUID="2902">\r\n <Field Name="Properties">\r\n <DataFormat>16bit</DataFormat>\r\n <ByteLength>2</ByteLength>\r\n <Range>\r\n <IsDeclared>true</IsDeclared>\r\n <Minimum>0</Minimum>\r\n <Maximum>3</Maximum>\r\n </Range>\r\n <ValueType>BITFIELD</ValueType>\r\n <Bit>\r\n <Index>0</Index>\r\n <Size>1</Size>\r\n <Value>1</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Notifications disabled" />\r\n <Enumeration key="1" value="Notifications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <Bit>\r\n <Index>1</Index>\r\n <Size>1</Size>\r\n <Value>0</Value>\r\n <Enumerations>\r\n <Enumeration key="0" value="Indications disabled" />\r\n <Enumeration key="1" value="Indications enabled" />\r\n </Enumerations>\r\n </Bit>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="true" Mandatory="false" />\r\n </Properties>\r\n <Permission>\r\n <AccessPermission>READ_WRITE</AccessPermission>\r\n </Permission>\r\n </CyDescriptor>\r\n <CyDescriptor ID="15" DisplayName="Characteristic User Description" Name="Characteristic User Description" Type="org.bluetooth.descriptor.gatt.characteristic_user_description" UUID="2901">\r\n <Field Name="User Description">\r\n <DataFormat>utf8s</DataFormat>\r\n <ByteLength>8</ByteLength>\r\n <ValueType>BASIC</ValueType>\r\n <GeneralValue>ADC Read</GeneralValue>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyDescriptor>\r\n <Field Name="New field">\r\n <DataFormat>uint8_array</DataFormat>\r\n <ByteLength>4</ByteLength>\r\n <ValueType>ARRAY</ValueType>\r\n <ArrayValue />\r\n </Field>\r\n <Properties>\r\n <Property Type="BROADCAST" Present="false" Mandatory="false" />\r\n <Property Type="READ" Present="true" Mandatory="false" />\r\n <Property Type="WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITE_WITHOUT_RESPONSE" Present="false" Mandatory="false" />\r\n <Property Type="NOTIFY" Present="true" Mandatory="false" />\r\n <Property Type="INDICATE" Present="false" Mandatory="false" />\r\n <Property Type="AUTHENTICATED_SIGNED_WRITES" Present="false" Mandatory="false" />\r\n <Property Type="RELIABLE_WRITE" Present="false" Mandatory="false" />\r\n <Property Type="WRITABLE_AUXILIARIES" Present="false" Mandatory="false" />\r\n </Properties>\r\n <Permission />\r\n </CyCharacteristic>\r\n <Declaration>PrimarySingleInstance</Declaration>\r\n <IncludedServices />\r\n </CyService>\r\n <ProfileRoleIndex>0</ProfileRoleIndex>\r\n <RoleType>SERVER</RoleType>\r\n </CyProfileRole>\r\n <GapRole>PERIPHERAL</GapRole>\r\n</Profile>, SharingMode=0, StackMode=3, StrictPairing=false, UseDeepSleep=true, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=BLE_v3_10, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=BLE_v3_10.pdf, CY_FITTER_NAME=BLE, CY_INSTANCE_SHORT_NAME=BLE, CY_MAJOR_VERSION=3, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=BLE, )
module BLE_v3_10_0 (
clk,
pa_en);
output clk;
output pa_en;
wire Net_55;
wire Net_60;
wire Net_53;
wire Net_72;
wire Net_71;
wire Net_70;
wire Net_15;
wire Net_14;
cy_m0s8_ble_v1_0 cy_m0s8_ble (
.interrupt(Net_15),
.rf_ext_pa_en(pa_en));
cy_isr_v1_0
#(.int_type(2'b10))
bless_isr
(.int_signal(Net_15));
cy_clock_v1_0
#(.id("f7e4c631-7f18-4a80-b8dc-a27c020488da/5ae6fa4d-f41a-4a35-8821-7ce70389cb0c"),
.source_clock_id("9A908CA6-5BB3-4db0-B098-959E5D90882B"),
.divisor(0),
.period("0"),
.is_direct(1),
.is_digital(0))
LFCLK
(.clock_out(Net_53));
assign clk = Net_53 | Net_55;
assign Net_55 = 1'h0;
endmodule
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_analog_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`endif
// Component: Bus_Connect_v2_40
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v2_40\Bus_Connect_v2_40.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.3\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// ADC_SAR_SEQ_P4_v2_40(AdcAClock=2, AdcAdjust=0, AdcAlternateResolution=0, AdcAvgMode=1, AdcAvgSamplesNum=0, AdcBClock=2, AdcCClock=2, AdcChannelsEnConf=1, AdcChannelsModeConf=0, AdcClock=1, AdcClockFrequency=1000000, AdcCompareMode=0, AdcDataFormatJustification=0, AdcDClock=2, AdcDedicatedExtVref=true, AdcDifferentialResultFormat=0, AdcHighLimit=4095, AdcInjChannelEnabled=false, AdcInputBufGain=0, AdcLowLimit=0, AdcMaxResolution=12, AdcSampleMode=0, AdcSarMuxChannelConfig=00, AdcSequencedChannels=2, AdcSingleEndedNegativeInput=1, AdcSingleResultFormat=0, AdcSymbolHasSingleEndedInputChannel=false, AdcTotalChannels=2, AdcVrefSelect=6, AdcVrefVoltage_mV=1024, rm_int=false, SeqChannelsConfigTable=<?xml version="1.0" encoding="utf-16"?><CyChannelsConfigTable xmlns:Version="2_40"><m_channelsConfigTable><CyChannelsConfigTableRow><m_enabled>false</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Diff</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow><CyChannelsConfigTableRow><m_enabled>true</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Single</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow><CyChannelsConfigTableRow><m_enabled>false</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Single</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow></m_channelsConfigTable></CyChannelsConfigTable>, TermMode_aclk=0, TermMode_eoc=0, TermMode_sdone=0, TermMode_soc=0, TermMode_vinMinus0=0, TermMode_vinMinus1=0, TermMode_vinMinus10=0, TermMode_vinMinus11=0, TermMode_vinMinus12=0, TermMode_vinMinus13=0, TermMode_vinMinus14=0, TermMode_vinMinus15=0, TermMode_vinMinus2=0, TermMode_vinMinus3=0, TermMode_vinMinus4=0, TermMode_vinMinus5=0, TermMode_vinMinus6=0, TermMode_vinMinus7=0, TermMode_vinMinus8=0, TermMode_vinMinus9=0, TermMode_vinMinusINJ=0, TermMode_vinNeg=0, TermMode_vinPlus0=0, TermMode_vinPlus1=0, TermMode_vinPlus10=0, TermMode_vinPlus11=0, TermMode_vinPlus12=0, TermMode_vinPlus13=0, TermMode_vinPlus14=0, TermMode_vinPlus15=0, TermMode_vinPlus2=0, TermMode_vinPlus3=0, TermMode_vinPlus4=0, TermMode_vinPlus5=0, TermMode_vinPlus6=0, TermMode_vinPlus7=0, TermMode_vinPlus8=0, TermMode_vinPlus9=0, TermMode_vinPlusINJ=0, TermMode_Vref=0, TermVisibility_aclk=false, TermVisibility_eoc=true, TermVisibility_sdone=true, TermVisibility_soc=false, TermVisibility_vinMinus0=false, TermVisibility_vinMinus1=false, TermVisibility_vinMinus10=false, TermVisibility_vinMinus11=false, TermVisibility_vinMinus12=false, TermVisibility_vinMinus13=false, TermVisibility_vinMinus14=false, TermVisibility_vinMinus15=false, TermVisibility_vinMinus2=false, TermVisibility_vinMinus3=false, TermVisibility_vinMinus4=false, TermVisibility_vinMinus5=false, TermVisibility_vinMinus6=false, TermVisibility_vinMinus7=false, TermVisibility_vinMinus8=false, TermVisibility_vinMinus9=false, TermVisibility_vinMinusINJ=false, TermVisibility_vinNeg=false, TermVisibility_vinPlus0=true, TermVisibility_vinPlus1=true, TermVisibility_vinPlus10=false, TermVisibility_vinPlus11=false, TermVisibility_vinPlus12=false, TermVisibility_vinPlus13=false, TermVisibility_vinPlus14=false, TermVisibility_vinPlus15=false, TermVisibility_vinPlus2=false, TermVisibility_vinPlus3=false, TermVisibility_vinPlus4=false, TermVisibility_vinPlus5=false, TermVisibility_vinPlus6=false, TermVisibility_vinPlus7=false, TermVisibility_vinPlus8=false, TermVisibility_vinPlus9=false, TermVisibility_vinPlusINJ=false, TermVisibility_Vref=false, CY_API_CALLBACK_HEADER_INCLUDE=#include "cyapicallbacks.h", CY_COMPONENT_NAME=ADC_SAR_SEQ_P4_v2_40, CY_CONTROL_FILE=<:default:>, CY_DATASHEET_FILE=<:default:>, CY_FITTER_NAME=ADC, CY_INSTANCE_SHORT_NAME=ADC, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=PSoC Creator 3.3 CP3, INSTANCE_NAME=ADC, )
module ADC_SAR_SEQ_P4_v2_40_1 (
soc,
aclk,
Vref,
sdone,
eoc,
vinPlus1,
vinPlus0);
input soc;
input aclk;
inout Vref;
electrical Vref;
output sdone;
output eoc;
inout vinPlus1;
electrical vinPlus1;
inout vinPlus0;
electrical vinPlus0;
wire Net_3209;
electrical Net_3164;
wire Net_3128;
wire [11:0] Net_3111;
wire Net_3110;
wire [3:0] Net_3109;
wire Net_3108;
electrical Net_3166;
electrical Net_3167;
electrical Net_3168;
electrical Net_3169;
electrical Net_3170;
electrical Net_3171;
electrical Net_3172;
electrical Net_3173;
electrical Net_3174;
electrical Net_3175;
electrical Net_3176;
electrical Net_3177;
electrical Net_3178;
electrical Net_3179;
electrical Net_3180;
electrical muxout_plus;
electrical Net_3181;
electrical muxout_minus;
electrical Net_3227;
electrical Net_3113;
electrical Net_3225;
electrical [16:0] mux_bus_minus;
electrical [16:0] mux_bus_plus;
electrical Net_3226;
wire Net_3103;
wire Net_3104;
wire Net_3105;
wire Net_3106;
wire Net_3107;
electrical Net_3165;
electrical Net_3182;
electrical Net_3183;
electrical Net_3184;
electrical Net_3185;
electrical Net_3186;
electrical Net_3187;
electrical Net_3188;
electrical Net_3189;
electrical Net_3190;
electrical Net_3191;
electrical Net_3192;
electrical Net_3193;
electrical Net_3194;
electrical Net_3195;
electrical Net_3196;
electrical Net_3197;
electrical Net_3198;
electrical Net_3132;
electrical Net_3133;
electrical Net_3134;
electrical Net_3135;
electrical Net_3136;
electrical Net_3137;
electrical Net_3138;
electrical Net_3139;
electrical Net_3140;
electrical Net_3141;
electrical Net_3142;
electrical Net_3143;
electrical Net_3144;
electrical Net_3145;
electrical Net_3146;
electrical Net_3147;
electrical Net_3148;
electrical Net_3149;
electrical Net_3150;
electrical Net_3151;
electrical Net_3152;
electrical Net_3153;
electrical Net_3154;
electrical Net_3159;
electrical Net_3157;
electrical Net_3158;
electrical Net_3160;
electrical Net_3161;
electrical Net_3162;
electrical Net_3163;
electrical Net_3156;
electrical Net_3155;
wire Net_3120;
electrical Net_3119;
electrical Net_3118;
wire Net_3124;
electrical Net_3122;
electrical Net_3117;
electrical Net_3121;
electrical Net_3123;
wire Net_3112;
wire Net_3126;
wire Net_3125;
electrical Net_2793;
electrical Net_2794;
electrical Net_1851;
electrical Net_2580;
electrical [1:0] Net_2375;
electrical [1:0] Net_1450;
electrical Net_3046;
electrical Net_3016;
wire Net_3235;
electrical Net_2099;
wire Net_17;
wire Net_1845;
electrical Net_2020;
electrical Net_124;
electrical Net_2102;
wire [1:0] Net_3207;
electrical Net_8;
electrical Net_43;
ZeroTerminal ZeroTerminal_8 (
.z(Net_3125));
assign Net_3126 = Net_1845 | Net_3125;
cy_isr_v1_0
#(.int_type(2'b10))
IRQ
(.int_signal(Net_3112));
cy_analog_noconnect_v1_0 cy_analog_noconnect_44 (
.noconnect(Net_3123));
cy_analog_noconnect_v1_0 cy_analog_noconnect_40 (
.noconnect(Net_3121));
cy_analog_noconnect_v1_0 cy_analog_noconnect_39 (
.noconnect(Net_3117));
// cy_analog_virtualmux_43 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_43_connect(Net_124, muxout_minus);
defparam cy_analog_virtualmux_43_connect.sig_width = 1;
// cy_analog_virtualmux_42 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_42_connect(Net_2020, muxout_plus);
defparam cy_analog_virtualmux_42_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_38 (
.noconnect(Net_3118));
cy_analog_noconnect_v1_0 cy_analog_noconnect_41 (
.noconnect(Net_3119));
cy_analog_noconnect_v1_0 cy_analog_noconnect_43 (
.noconnect(Net_3122));
// adc_plus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_plus_in_sel_connect(muxout_plus, Net_2794);
defparam adc_plus_in_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_1 (
.in_bus(mux_bus_plus[16:0]),
.out_bus(Net_1450[1:0]));
defparam Connect_1.in_width = 17;
defparam Connect_1.out_width = 2;
// adc_minus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_minus_in_sel_connect(muxout_minus, Net_2793);
defparam adc_minus_in_sel_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_1851));
// cy_analog_virtualmux_37 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_37_connect(Net_3016, mux_bus_plus[2]);
defparam cy_analog_virtualmux_37_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_21 (
.noconnect(Net_3147));
cy_analog_noconnect_v1_0 cy_analog_noconnect_20 (
.noconnect(Net_3146));
cy_analog_noconnect_v1_0 cy_analog_noconnect_19 (
.noconnect(Net_3145));
cy_analog_noconnect_v1_0 cy_analog_noconnect_18 (
.noconnect(Net_3144));
cy_analog_noconnect_v1_0 cy_analog_noconnect_17 (
.noconnect(Net_3143));
cy_analog_noconnect_v1_0 cy_analog_noconnect_16 (
.noconnect(Net_3142));
cy_analog_noconnect_v1_0 cy_analog_noconnect_15 (
.noconnect(Net_3141));
cy_analog_noconnect_v1_0 cy_analog_noconnect_14 (
.noconnect(Net_3140));
cy_analog_noconnect_v1_0 cy_analog_noconnect_13 (
.noconnect(Net_3139));
cy_analog_noconnect_v1_0 cy_analog_noconnect_12 (
.noconnect(Net_3138));
cy_analog_noconnect_v1_0 cy_analog_noconnect_11 (
.noconnect(Net_3137));
cy_analog_noconnect_v1_0 cy_analog_noconnect_10 (
.noconnect(Net_3136));
cy_analog_noconnect_v1_0 cy_analog_noconnect_9 (
.noconnect(Net_3135));
cy_analog_noconnect_v1_0 cy_analog_noconnect_8 (
.noconnect(Net_3134));
cy_analog_noconnect_v1_0 cy_analog_noconnect_7 (
.noconnect(Net_3133));
cy_analog_noconnect_v1_0 cy_analog_noconnect_6 (
.noconnect(Net_3132));
// cy_analog_virtualmux_36 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_36_connect(Net_3046, mux_bus_minus[2]);
defparam cy_analog_virtualmux_36_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_37 (
.noconnect(Net_3165));
ZeroTerminal ZeroTerminal_5 (
.z(Net_3107));
ZeroTerminal ZeroTerminal_4 (
.z(Net_3106));
ZeroTerminal ZeroTerminal_3 (
.z(Net_3105));
ZeroTerminal ZeroTerminal_2 (
.z(Net_3104));
ZeroTerminal ZeroTerminal_1 (
.z(Net_3103));
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_3113));
// ext_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vref_sel_connect(Net_43, Net_3227);
defparam ext_vref_sel_connect.sig_width = 1;
Bus_Connect_v2_40 Connect_2 (
.in_bus(mux_bus_minus[16:0]),
.out_bus(Net_2375[1:0]));
defparam Connect_2.in_width = 17;
defparam Connect_2.out_width = 2;
cy_analog_noconnect_v1_0 cy_analog_noconnect_35 (
.noconnect(Net_3181));
cy_analog_noconnect_v1_0 cy_analog_noconnect_34 (
.noconnect(Net_3180));
cy_analog_noconnect_v1_0 cy_analog_noconnect_33 (
.noconnect(Net_3179));
cy_analog_noconnect_v1_0 cy_analog_noconnect_32 (
.noconnect(Net_3178));
cy_analog_noconnect_v1_0 cy_analog_noconnect_31 (
.noconnect(Net_3177));
cy_analog_noconnect_v1_0 cy_analog_noconnect_30 (
.noconnect(Net_3176));
cy_analog_noconnect_v1_0 cy_analog_noconnect_29 (
.noconnect(Net_3175));
cy_analog_noconnect_v1_0 cy_analog_noconnect_28 (
.noconnect(Net_3174));
cy_analog_noconnect_v1_0 cy_analog_noconnect_27 (
.noconnect(Net_3173));
cy_analog_noconnect_v1_0 cy_analog_noconnect_26 (
.noconnect(Net_3172));
cy_analog_noconnect_v1_0 cy_analog_noconnect_25 (
.noconnect(Net_3171));
cy_analog_noconnect_v1_0 cy_analog_noconnect_24 (
.noconnect(Net_3170));
cy_analog_noconnect_v1_0 cy_analog_noconnect_23 (
.noconnect(Net_3169));
cy_analog_noconnect_v1_0 cy_analog_noconnect_22 (
.noconnect(Net_3168));
cy_analog_noconnect_v1_0 cy_analog_noconnect_4 (
.noconnect(Net_3167));
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_3166));
// int_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 int_vref_sel_connect(Net_8, Net_3113);
defparam int_vref_sel_connect.sig_width = 1;
// clk_src_sel (cy_virtualmux_v1_0)
assign Net_17 = Net_1845;
cy_psoc4_sar_v1_0 cy_psoc4_sar (
.vplus(Net_2020),
.vminus(Net_124),
.vref(Net_8),
.ext_vref(Net_43),
.clock(Net_17),
.sw_negvref(Net_3103),
.cfg_st_sel(Net_3207[1:0]),
.cfg_average(Net_3104),
.cfg_resolution(Net_3105),
.cfg_differential(Net_3106),
.trigger(Net_3235),
.data_hilo_sel(Net_3107),
.sample_done(sdone),
.chan_id_valid(Net_3108),
.chan_id(Net_3109[3:0]),
.data_valid(Net_3110),
.eos_intr(eoc),
.data(Net_3111[11:0]),
.irq(Net_3112));
// ext_vneg_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vneg_sel_connect(Net_2580, Net_1851);
defparam ext_vneg_sel_connect.sig_width = 1;
cy_psoc4_sarmux_v1_0 cy_psoc4_sarmux_8 (
.muxin_plus(Net_1450[1:0]),
.muxin_minus(Net_2375[1:0]),
.cmn_neg(Net_2580),
.vout_plus(Net_2794),
.vout_minus(Net_2793));
defparam cy_psoc4_sarmux_8.input_mode = "00";
defparam cy_psoc4_sarmux_8.muxin_width = 2;
// VMux_soc (cy_virtualmux_v1_0)
assign Net_3235 = soc;
ZeroTerminal ZeroTerminal_6 (
.z(Net_3207[0]));
ZeroTerminal ZeroTerminal_7 (
.z(Net_3207[1]));
// cy_analog_virtualmux_vplus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus0_connect(mux_bus_plus[0], vinPlus0);
defparam cy_analog_virtualmux_vplus0_connect.sig_width = 1;
// cy_analog_virtualmux_vplus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus1_connect(mux_bus_plus[1], vinPlus1);
defparam cy_analog_virtualmux_vplus1_connect.sig_width = 1;
// cy_analog_virtualmux_vplus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus2_connect(mux_bus_plus[2], Net_3133);
defparam cy_analog_virtualmux_vplus2_connect.sig_width = 1;
// cy_analog_virtualmux_vplus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus3_connect(mux_bus_plus[3], Net_3134);
defparam cy_analog_virtualmux_vplus3_connect.sig_width = 1;
// cy_analog_virtualmux_vplus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus4_connect(mux_bus_plus[4], Net_3135);
defparam cy_analog_virtualmux_vplus4_connect.sig_width = 1;
// cy_analog_virtualmux_vplus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus5_connect(mux_bus_plus[5], Net_3136);
defparam cy_analog_virtualmux_vplus5_connect.sig_width = 1;
// cy_analog_virtualmux_vplus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus6_connect(mux_bus_plus[6], Net_3137);
defparam cy_analog_virtualmux_vplus6_connect.sig_width = 1;
// cy_analog_virtualmux_vplus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus7_connect(mux_bus_plus[7], Net_3138);
defparam cy_analog_virtualmux_vplus7_connect.sig_width = 1;
// cy_analog_virtualmux_vplus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus8_connect(mux_bus_plus[8], Net_3139);
defparam cy_analog_virtualmux_vplus8_connect.sig_width = 1;
// cy_analog_virtualmux_vplus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus9_connect(mux_bus_plus[9], Net_3140);
defparam cy_analog_virtualmux_vplus9_connect.sig_width = 1;
// cy_analog_virtualmux_vplus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus10_connect(mux_bus_plus[10], Net_3141);
defparam cy_analog_virtualmux_vplus10_connect.sig_width = 1;
// cy_analog_virtualmux_vplus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus11_connect(mux_bus_plus[11], Net_3142);
defparam cy_analog_virtualmux_vplus11_connect.sig_width = 1;
// cy_analog_virtualmux_vplus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus12_connect(mux_bus_plus[12], Net_3143);
defparam cy_analog_virtualmux_vplus12_connect.sig_width = 1;
// cy_analog_virtualmux_vplus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus13_connect(mux_bus_plus[13], Net_3144);
defparam cy_analog_virtualmux_vplus13_connect.sig_width = 1;
// cy_analog_virtualmux_vplus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus14_connect(mux_bus_plus[14], Net_3145);
defparam cy_analog_virtualmux_vplus14_connect.sig_width = 1;
// cy_analog_virtualmux_vplus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus15_connect(mux_bus_plus[15], Net_3146);
defparam cy_analog_virtualmux_vplus15_connect.sig_width = 1;
// cy_analog_virtualmux_vplus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus_inj_connect(Net_3016, Net_3147);
defparam cy_analog_virtualmux_vplus_inj_connect.sig_width = 1;
// cy_analog_virtualmux_vminus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus0_connect(mux_bus_minus[0], Net_3166);
defparam cy_analog_virtualmux_vminus0_connect.sig_width = 1;
// cy_analog_virtualmux_vminus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus1_connect(mux_bus_minus[1], Net_3167);
defparam cy_analog_virtualmux_vminus1_connect.sig_width = 1;
// cy_analog_virtualmux_vminus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus2_connect(mux_bus_minus[2], Net_3168);
defparam cy_analog_virtualmux_vminus2_connect.sig_width = 1;
// cy_analog_virtualmux_vminus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus3_connect(mux_bus_minus[3], Net_3169);
defparam cy_analog_virtualmux_vminus3_connect.sig_width = 1;
// cy_analog_virtualmux_vminus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus4_connect(mux_bus_minus[4], Net_3170);
defparam cy_analog_virtualmux_vminus4_connect.sig_width = 1;
// cy_analog_virtualmux_vminus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus5_connect(mux_bus_minus[5], Net_3171);
defparam cy_analog_virtualmux_vminus5_connect.sig_width = 1;
// cy_analog_virtualmux_vminus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus6_connect(mux_bus_minus[6], Net_3172);
defparam cy_analog_virtualmux_vminus6_connect.sig_width = 1;
// cy_analog_virtualmux_vminus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus7_connect(mux_bus_minus[7], Net_3173);
defparam cy_analog_virtualmux_vminus7_connect.sig_width = 1;
// cy_analog_virtualmux_vminus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus8_connect(mux_bus_minus[8], Net_3174);
defparam cy_analog_virtualmux_vminus8_connect.sig_width = 1;
// cy_analog_virtualmux_vminus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus9_connect(mux_bus_minus[9], Net_3175);
defparam cy_analog_virtualmux_vminus9_connect.sig_width = 1;
// cy_analog_virtualmux_vminus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus10_connect(mux_bus_minus[10], Net_3176);
defparam cy_analog_virtualmux_vminus10_connect.sig_width = 1;
// cy_analog_virtualmux_vminus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus11_connect(mux_bus_minus[11], Net_3177);
defparam cy_analog_virtualmux_vminus11_connect.sig_width = 1;
// cy_analog_virtualmux_vminus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus12_connect(mux_bus_minus[12], Net_3178);
defparam cy_analog_virtualmux_vminus12_connect.sig_width = 1;
// cy_analog_virtualmux_vminus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus13_connect(mux_bus_minus[13], Net_3179);
defparam cy_analog_virtualmux_vminus13_connect.sig_width = 1;
// cy_analog_virtualmux_vminus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus14_connect(mux_bus_minus[14], Net_3180);
defparam cy_analog_virtualmux_vminus14_connect.sig_width = 1;
// cy_analog_virtualmux_vminus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus15_connect(mux_bus_minus[15], Net_3181);
defparam cy_analog_virtualmux_vminus15_connect.sig_width = 1;
// cy_analog_virtualmux_vminus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus_inj_connect(Net_3046, Net_3165);
defparam cy_analog_virtualmux_vminus_inj_connect.sig_width = 1;
cy_clock_v1_0
#(.id("aa161331-e27a-4068-8928-be13b58312fd/5c71752a-e182-47ca-942c-9cb20adbdf2f"),
.source_clock_id(""),
.divisor(0),
.period("1000000000"),
.is_direct(0),
.is_digital(0))
intClock
(.clock_out(Net_1845));
cy_analog_noconnect_v1_0 cy_analog_noconnect_5 (
.noconnect(Net_3227));
endmodule
// top
module top ;
wire Net_3430;
wire Net_3429;
wire Net_3428;
wire Net_3427;
electrical Net_3426;
wire Net_3293;
wire Net_3292;
electrical Net_3234;
electrical Net_3367;
electrical Net_3223;
electrical Net_3701;
electrical Net_3702;
cy_annotation_universal_v1_0 GND_1 (
.connect({
Net_3234
})
);
defparam GND_1.comp_name = "Gnd_v1_0";
defparam GND_1.port_names = "T1";
defparam GND_1.width = 1;
cy_annotation_universal_v1_0 L_1 (
.connect({
Net_3234,
Net_3701
})
);
defparam L_1.comp_name = "Inductor_v1_0";
defparam L_1.port_names = "T1, T2";
defparam L_1.width = 2;
cy_annotation_universal_v1_0 C_1 (
.connect({
Net_3701,
Net_3702
})
);
defparam C_1.comp_name = "Capacitor_v1_0";
defparam C_1.port_names = "T1, T2";
defparam C_1.width = 2;
wire [0:0] tmpOE__ADC_1_net;
wire [0:0] tmpFB_0__ADC_1_net;
wire [0:0] tmpIO_0__ADC_1_net;
wire [0:0] tmpINTERRUPT_0__ADC_1_net;
electrical [0:0] tmpSIOVREF__ADC_1_net;
cy_psoc3_pins_v1_10
#(.id("a9c4e00c-7584-4803-8d8e-db8465638664"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
ADC_1
(.oe(tmpOE__ADC_1_net),
.y({1'b0}),
.fb({tmpFB_0__ADC_1_net[0:0]}),
.analog({Net_3367}),
.io({tmpIO_0__ADC_1_net[0:0]}),
.siovref(tmpSIOVREF__ADC_1_net),
.interrupt({tmpINTERRUPT_0__ADC_1_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__ADC_1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
BLE_v3_10_0 BLE (
.clk(Net_3292),
.pa_en(Net_3293));
ADC_SAR_SEQ_P4_v2_40_1 ADC (
.Vref(Net_3426),
.sdone(Net_3427),
.eoc(Net_3428),
.aclk(1'b0),
.soc(1'b0),
.vinPlus0(Net_3223),
.vinPlus1(Net_3367));
wire [0:0] tmpOE__ADC_0_net;
wire [0:0] tmpFB_0__ADC_0_net;
wire [0:0] tmpIO_0__ADC_0_net;
wire [0:0] tmpINTERRUPT_0__ADC_0_net;
electrical [0:0] tmpSIOVREF__ADC_0_net;
cy_psoc3_pins_v1_10
#(.id("77715107-f8d5-47e5-a629-0fb83101ac6b"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b1),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.sio_hifreq(""),
.sio_vohsel(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1),
.ovt_hyst_trim(1'b0),
.ovt_needed(1'b0),
.ovt_slew_control(2'b00),
.input_buffer_sel(2'b00))
ADC_0
(.oe(tmpOE__ADC_0_net),
.y({1'b0}),
.fb({tmpFB_0__ADC_0_net[0:0]}),
.analog({Net_3223}),
.io({tmpIO_0__ADC_0_net[0:0]}),
.siovref(tmpSIOVREF__ADC_0_net),
.interrupt({tmpINTERRUPT_0__ADC_0_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__ADC_0_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O21BAI_SYMBOL_V
`define SKY130_FD_SC_HS__O21BAI_SYMBOL_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o21bai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O21BAI_SYMBOL_V
|
// ====================================================================
// Bashkiria-2M FPGA REPLICA
//
// Copyright (C) 2010 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Bashkiria-2M home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: b2m_kbd.v
//
// Keyboard interface design file of Bashkiria-2M replica.
module b2m_kbd(
input clk,
input reset,
input ps2_clk,
input ps2_dat,
input[8:0] addr,
output reg cpurst,
output reg[7:0] odata);
reg[7:0] keystate[10:0];
always @(addr,keystate) begin
if (addr[8])
odata =
(keystate[8] & {8{addr[0]}})|
(keystate[9] & {8{addr[1]}})|
(keystate[10] & {8{addr[2]}});
else
odata =
(keystate[0] & {8{addr[0]}})|
(keystate[1] & {8{addr[1]}})|
(keystate[2] & {8{addr[2]}})|
(keystate[3] & {8{addr[3]}})|
(keystate[4] & {8{addr[4]}})|
(keystate[5] & {8{addr[5]}})|
(keystate[6] & {8{addr[6]}})|
(keystate[7] & {8{addr[7]}});
end
reg[2:0] c;
reg[3:0] r;
reg extkey;
reg unpress;
reg[3:0] prev_clk;
reg[11:0] shift_reg;
wire[11:0] kdata = {ps2_dat,shift_reg[11:1]};
wire[7:0] kcode = kdata[9:2];
always begin
case (kcode)
8'h4E: {c,r} <= 7'h74; // -
8'h41: {c,r} <= 7'h05; // ,
8'h4C: {c,r} <= 7'h15; // ;
8'h55: {c,r} <= 7'h25; // =
8'h0E: {c,r} <= 7'h35; // `
8'h5D: {c,r} <= 7'h55; // \!
8'h45: {c,r} <= 7'h65; // 0
8'h16: {c,r} <= 7'h45; // 1
8'h1E: {c,r} <= 7'h64; // 2
8'h26: {c,r} <= 7'h54; // 3
8'h25: {c,r} <= 7'h44; // 4
8'h2E: {c,r} <= 7'h34; // 5
8'h36: {c,r} <= 7'h24; // 6
8'h3D: {c,r} <= 7'h14; // 7
8'h3E: {c,r} <= 7'h04; // 8
8'h46: {c,r} <= 7'h75; // 9
8'h1C: {c,r} <= 7'h10; // A
8'h32: {c,r} <= 7'h61; // B
8'h21: {c,r} <= 7'h42; // C
8'h23: {c,r} <= 7'h02; // D
8'h24: {c,r} <= 7'h22; // E
8'h2B: {c,r} <= 7'h60; // F
8'h34: {c,r} <= 7'h72; // G
8'h33: {c,r} <= 7'h52; // H
8'h43: {c,r} <= 7'h43; // I
8'h3B: {c,r} <= 7'h01; // J
8'h42: {c,r} <= 7'h31; // K
8'h4B: {c,r} <= 7'h30; // L
8'h3A: {c,r} <= 7'h73; // M
8'h31: {c,r} <= 7'h32; // N
8'h44: {c,r} <= 7'h23; // O
8'h4D: {c,r} <= 7'h53; // P
8'h15: {c,r} <= 7'h51; // Q
8'h2D: {c,r} <= 7'h41; // R
8'h1B: {c,r} <= 7'h63; // S
8'h2C: {c,r} <= 7'h20; // T
8'h3C: {c,r} <= 7'h00; // U
8'h2A: {c,r} <= 7'h21; // V
8'h1D: {c,r} <= 7'h40; // W
8'h22: {c,r} <= 7'h13; // X
8'h35: {c,r} <= 7'h11; // Y
8'h1A: {c,r} <= 7'h62; // Z
8'h54: {c,r} <= 7'h71; // [
8'h5B: {c,r} <= 7'h03; // ]
8'h0B: {c,r} <= 7'h50; // F6
8'h83: {c,r} <= 7'h70; // F7
8'h0A: {c,r} <= 7'h12; // F8
8'h01: {c,r} <= 7'h33; // F9
8'h29: {c,r} <= 7'h06; // space
8'h0D: {c,r} <= 7'h16; // tab
8'h66: {c,r} <= 7'h26; // bksp
8'h7C: {c,r} <= 7'h46; // gray*
8'h07: {c,r} <= 7'h56; // F12 - stop
8'h7B: {c,r} <= 7'h66; // gray-
8'h5A: {c,r} <= 7'h76; // enter
8'h59: {c,r} <= 7'h07; // rshift
8'h11: {c,r} <= 7'h17; // lalt
8'h14: {c,r} <= extkey ? 7'h37 : 7'h27; // rctrl + lctrl
8'h76: {c,r} <= 7'h47; // esc
8'h78: {c,r} <= 7'h67; // F11 - rus
8'h12: {c,r} <= 7'h77; // lshift
8'h6C: {c,r} <= 7'h08; // 7 home
8'h74: {c,r} <= 7'h18; // 6 right
8'h73: {c,r} <= 7'h28; // 5 center
8'h6B: {c,r} <= 7'h38; // 4 left
8'h7A: {c,r} <= 7'h48; // 3 pgdn
8'h72: {c,r} <= 7'h58; // 2 down
8'h69: {c,r} <= 7'h68; // 1 end
8'h70: {c,r} <= 7'h78; // 0 ins
8'h4A: {c,r} <= extkey ? 7'h36 : 7'h09; // gray/ + /
8'h71: {c,r} <= 7'h19; // . del
8'h52: {c,r} <= 7'h29; // '
8'h49: {c,r} <= 7'h39; // .
8'h7D: {c,r} <= 7'h69; // 9 pgup
8'h75: {c,r} <= 7'h79; // 8 up
8'h05: {c,r} <= 7'h7A; // F1
8'h06: {c,r} <= 7'h6A; // F2
8'h04: {c,r} <= 7'h5A; // F3
8'h0C: {c,r} <= 7'h4A; // F4
8'h03: {c,r} <= 7'h3A; // F5
default: {c,r} <= 7'h7F;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
extkey <= 0;
unpress <= 0;
keystate[0] <= 0;
keystate[1] <= 0;
keystate[2] <= 0;
keystate[3] <= 0;
keystate[4] <= 0;
keystate[5] <= 0;
keystate[6] <= 0;
keystate[7] <= 0;
keystate[8] <= 0;
keystate[9] <= 0;
keystate[10] <= 0;
cpurst <= 0;
end else begin
prev_clk <= {ps2_clk,prev_clk[3:1]};
if (prev_clk==4'b1) begin
if (kdata[11]==1'b1 && ^kdata[10:2]==1'b1 && kdata[1:0]==2'b1) begin
shift_reg <= 12'hFFF;
if (kcode==8'hE0) extkey <= 1'b1; else
if (kcode==8'hF0) unpress <= 1'b1; else
begin
extkey <= 0;
unpress <= 0;
if(r!=4'hF) keystate[r][c] <= ~unpress;
if(kcode == 8'h7E && unpress == 1'b1) cpurst <= 1'b1; else cpurst <= 1'b0;
end
end else
shift_reg <= kdata;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__o21ai (
Y ,
A1,
A2,
B1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, B1, or0_out );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__O21AI_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_notify_pg/sky130_fd_sc_hs__u_dfb_setdom_notify_pg.v"
`celldefine
module sky130_fd_sc_hs__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_hs__u_dfb_setdom_notify_pg u_dfb_setdom_notify_pg0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DFBBN_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111A_BLACKBOX_V
`define SKY130_FD_SC_HD__O2111A_BLACKBOX_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o2111a (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111A_BLACKBOX_V
|
`default_nettype none
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief Transmitter for RPC network, protocol version 3
This module expects OUT_DATA_WIDTH to be equal to IN_DATA_WIDTH.
Network-side interface is standard RPCv3.
Router-side interface is a FIFO.
fifo_size Number of IN_DATA_WIDTH-bit words left in transmit FIFO.
FIFO is a fixed depth of 32 words regardless of data width, so capacity ranges from
4 to 32 messages depending on data width.
packet_start Asserted by router concurrently with first wr_en of a message
wr_en Asserted by router for (128 / IN_DATA_WIDTH) consecutive cycles
to indicate wr_data is valid
wr_data Data to be sent
packet_done Asserted by transmitter as the last cycle of the message is sent
RESOURCE USAGE (XST A7 rough estimate)
Width FF LUT Slice
16
32
64
128
*/
module RPCv3RouterTransmitter_buffering
#(
//Data width (must be one of 16, 32, 64, 128).
parameter OUT_DATA_WIDTH = 32,
parameter IN_DATA_WIDTH = 32
)
(
//Interface clock
input wire clk,
//Network interface, outbound side
output reg rpc_tx_en = 0,
output reg[OUT_DATA_WIDTH-1:0] rpc_tx_data = 0,
input wire rpc_tx_ready,
//Router interface, inbound side
output wire[5:0] rpc_fab_tx_fifo_size,
input wire rpc_fab_tx_packet_start,
input wire rpc_fab_tx_wr_en,
input wire[IN_DATA_WIDTH-1:0] rpc_fab_tx_wr_data,
output reg rpc_fab_tx_packet_done = 0
`ifdef FORMAL
, output fifo_rdata_valid
`endif
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Synthesis-time sanity checking
initial begin
case(IN_DATA_WIDTH)
16: begin
end
32: begin
end
64: begin
end
128: begin
end
default: begin
$display("ERROR: RPCv3RouterTransmitter_buffering IN_DATA_WIDTH must be 16/32/64/128");
$finish;
end
endcase
case(OUT_DATA_WIDTH)
16: begin
end
32: begin
end
64: begin
end
128: begin
end
default: begin
$display("ERROR: RPCv3RouterTransmitter_buffering OUT_DATA_WIDTH must be 16/32/64/128");
$finish;
end
endcase
if(IN_DATA_WIDTH != OUT_DATA_WIDTH) begin
$display("ERROR: RPCv3RouterTransmitter_buffering IN_DATA_WIDTH must be equal to OUT_DATA_WIDTH");
$finish;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Compute some useful values
//Number of clocks it takes to send/receive a message
localparam MESSAGE_CYCLES = 128 / IN_DATA_WIDTH;
localparam MESSAGE_MAX = MESSAGE_CYCLES - 1;
//Number of bits we need in the cycle counter
`include "../../synth_helpers/clog2.vh"
localparam CYCLE_BITS = clog2(MESSAGE_CYCLES);
localparam CYCLE_MAX = CYCLE_BITS ? CYCLE_BITS-1 : 0;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// The actual outbound data FIFO
reg fifo_rdata_valid = 0;
reg fifo_rd = 0;
wire fifo_empty;
wire fifo_rdata_packet_start;
wire[IN_DATA_WIDTH-1:0] fifo_rdata_data;
wire unused_overflow;
wire unused_underflow;
wire unused_full;
wire[5:0] unused_rsize;
SingleClockShiftRegisterFifo #(
.WIDTH(IN_DATA_WIDTH + 1),
.DEPTH(32),
.OUT_REG(1)
) tx_fifo (
.clk(clk),
.wr(rpc_fab_tx_wr_en),
.din({rpc_fab_tx_packet_start, rpc_fab_tx_wr_data}),
.rd(fifo_rd),
.dout({fifo_rdata_packet_start, fifo_rdata_data}),
.overflow(unused_overflow),
.underflow(unused_underflow),
.empty(fifo_empty),
.full(unused_full),
.rsize(unused_rsize),
.wsize(rpc_fab_tx_fifo_size),
.reset(1'b0) //never reset the fifo
);
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Main state machine
//Position within the message (in DATA_WIDTH-bit units)
reg[CYCLE_MAX:0] tx_count = 0;
//True if we're starting a transmit this cycle
wire tx_starting = fifo_rdata_valid && (tx_count == 0) && rpc_tx_ready;
//True if a transmit is in progress
wire tx_active = (tx_count != 0) || tx_starting;
//True if we're ending a transmit this cycle.
//The AND of tx_active is important to avoid staying high with 128-bit data width
wire tx_ending = (tx_count == MESSAGE_MAX) && tx_active;
//If we have data ready to read, read it.
//If we already have data in the outbox, don't read unless we're actively sending (and ready for more next clock)
always @(*) begin
fifo_rd <= (!fifo_empty && (!fifo_rdata_valid || tx_active) && !tx_ending );
end
//Push fifo output to the network
always @(*) begin
rpc_tx_en <= tx_starting;
rpc_tx_data <= fifo_rdata_data;
rpc_fab_tx_packet_done <= tx_ending;
end
//Keep track of position in the message
always @(posedge clk) begin
if(tx_active)
tx_count <= tx_count + 1'h1;
//Read data is not valid after the end of the packet
if(tx_ending)
fifo_rdata_valid <= 0;
//Read data is valid next cycle if we're reading this cycle
if(fifo_rd)
fifo_rdata_valid <= 1;
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author:
* Description:
*
* Changes:
*/
`timescale 1ns/1ps
`include "cbuilder_defines.v"
`define ID_DWORD 32'hCD15DBE5
`define ID_RESP (~`ID_DWORD)
module adapter_cocotb_2_ppfifo #(
parameter IN_FIFO_DEPTH = 8,
parameter OUT_FIFO_DEPTH = 8
)(
input clk,
input rst,
//Cocotb Interface
output reg o_ctb_master_ready,
input i_ctb_in_ready,
input [31:0] i_ctb_in_command,
input [31:0] i_ctb_in_address,
input [31:0] i_ctb_in_data,
input [27:0] i_ctb_in_data_count,
input i_ctb_out_ready,
output reg o_ctb_out_en,
output reg [31:0] o_ctb_out_status,
output reg [31:0] o_ctb_out_address,
output reg [31:0] o_ctb_out_data,
output reg [27:0] o_ctb_out_data_count,
output o_in_rdy,
input i_in_act,
output [23:0] o_in_size,
output i_in_stb,
output [31:0] o_in_data,
output [1:0] o_out_rdy,
input [1:0] i_out_act,
output [23:0] o_out_size,
input i_out_stb,
input [31:0] i_out_data
);
//local parameters
localparam IN_PACKET_CMD_SIZE = 4;
localparam OUT_PACKET_RESP_SIZE = 5;
localparam OUT_PACKET_PING_SIZE = 2;
//States
localparam IDLE = 0;
localparam HOST_SEND_COMMAND = 1;
localparam HOST_SEND_DATA = 2;
localparam WAIT_FOR_RESPONSE = 3;
localparam WRITE_DATA_TO_HOST = 4;
localparam FLUSH = 5;
//registes/wires
reg [3:0] state;
reg [31:0] in_packet[0:IN_PACKET_CMD_SIZE];
reg [23:0] in_packet_pos;
wire [1:0] hst_in_rdy;
reg [1:0] hst_in_act;
reg hst_in_stb;
wire [23:0] hst_in_size;
reg [31:0] hst_in_data;
reg [23:0] in_count;
reg [23:0] in_data_count;
wire hst_out_rdy;
reg hst_out_act;
reg hst_out_stb;
wire [23:0] hst_out_size;
wire [31:0] hst_out_data;
reg [23:0] out_count;
reg [23:0] resp_count;
reg [23:0] out_data_count;
wire [23:0] response_length;
//submodules
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (IN_FIFO_DEPTH )
) ingress (
.reset (rst ),
//write side
.write_clock (clk ),
.write_data (hst_in_data ),
.write_ready (hst_in_rdy ),
.write_activate (hst_in_act ),
.write_fifo_size (hst_in_size ),
.write_strobe (hst_in_stb ),
.starved ( ),
//read side
.read_clock (clk ),
.read_strobe (i_in_stb ),
.read_ready (o_in_rdy ),
.read_activate (i_in_act ),
.read_count (o_in_size ),
.read_data (o_in_data ),
.inactive ( )
);
ppfifo #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (OUT_FIFO_DEPTH )
) egress (
.reset (rst ),
//write side
.write_clock (clk ),
.write_data (i_out_data ),
.write_ready (o_out_rdy ),
.write_activate (i_out_act ),
.write_fifo_size (o_out_size ),
.write_strobe (i_out_stb ),
.starved ( ),
//read side
.read_clock (clk ),
.read_strobe (hst_out_stb ),
.read_ready (hst_out_rdy ),
.read_activate (hst_out_act ),
.read_count (hst_out_size ),
.read_data (hst_out_data ),
.inactive ( )
);
//asynchronous logic
assign response_length = (i_ctb_in_command[3:0] == `COMMAND_PING) ? OUT_PACKET_PING_SIZE : OUT_PACKET_RESP_SIZE;
//synchronous logic
always @ (posedge clk) begin
//De-assert Strobes
o_ctb_master_ready <= 0;
o_ctb_out_en <= 0;
hst_in_stb <= 0;
hst_out_stb <= 0;
if (rst) begin
state <= IDLE;
in_count <= 0;
in_packet_pos <= 0;
in_data_count <= 0;
out_count <= 0;
o_ctb_out_status <= 0;
o_ctb_out_address <= 0;
o_ctb_out_data <= 0;
o_ctb_out_data_count<= 0;
hst_in_act <= 0;
hst_in_data <= 0;
hst_out_act <= 0;
resp_count <= 0;
end
else begin
//Get an incomming FIFO to work with
if ((hst_in_rdy > 0) && hst_in_act == 0) begin
in_count <= 0;
if (hst_in_rdy[0]) begin
hst_in_act[0] <= 1;
end
else begin
hst_in_act[1] <= 1;
end
end
//If there are any outgoing FIFOs get one
if (hst_out_rdy && !hst_out_act) begin
out_count <= 0;
hst_out_act <= 1;
end
case (state)
IDLE: begin
o_ctb_master_ready <= 1;
resp_count <= 0;
in_data_count <= 1;
out_data_count <= 1;
in_packet_pos <= 0;
if (i_ctb_in_ready && hst_in_act) begin //There shouldn't be any data in the FIFO
o_ctb_master_ready<= 0;
in_packet[0] <= `ID_DWORD;
in_packet[1] <= {i_ctb_in_command[7:0], i_ctb_in_data_count[23:0]};
in_packet[2] <= i_ctb_in_address;
in_packet[3] <= i_ctb_in_data;
state <= HOST_SEND_COMMAND;
end
if (hst_out_act) begin
$display ("Interrupt Detected!");
state <= WAIT_FOR_RESPONSE;
end
end
HOST_SEND_COMMAND: begin
if (in_packet_pos < IN_PACKET_CMD_SIZE) begin
if (in_count < hst_in_size) begin
hst_in_data <= in_packet[in_packet_pos];
in_packet_pos <= in_packet_pos + 1;
in_count <= in_count + 1;
hst_in_stb <= 1;
end
else begin
hst_in_act <= 0;
end
end
else begin
//Done inserting the command inside the PPFIFO
if ((i_ctb_in_command[3:0] == `COMMAND_WRITE) && (i_ctb_in_data_count > 1)) begin
//There is more than one piece of data to send
state <= HOST_SEND_DATA;
end
else begin
//No more data to send to the host
//Release the fifo and wait for a response
state <= WAIT_FOR_RESPONSE;
hst_in_act <= 0;
end
end
end
HOST_SEND_DATA: begin
if (in_data_count < i_ctb_in_data_count) begin
if (hst_in_act) begin
if (in_count < hst_in_size) begin
o_ctb_master_ready <= 1;
if (i_ctb_in_ready && o_ctb_master_ready) begin //There shouldn't be any data in the FIFO
$display ("Wait for master");
o_ctb_master_ready <= 0;
in_count <= in_count + 1;
in_data_count <= in_data_count + 1;
hst_in_data <= i_ctb_in_data;
hst_in_stb <= 1;
end
end
else begin
hst_in_act <= 0;
end
end
end
else begin
state <= WAIT_FOR_RESPONSE;
hst_in_act <= 0;
end
end
WAIT_FOR_RESPONSE: begin
//Need to wait for a response from the host
if (i_ctb_out_ready && !o_ctb_out_en) begin
if (hst_out_act && i_ctb_out_ready) begin
if (out_count < hst_out_size) begin
if (resp_count < response_length) begin
//Unpack the Response
case (resp_count)
0: begin
hst_out_stb <= 1;
end
1: begin
o_ctb_out_status <= hst_out_data;
hst_out_stb <= 1;
end
2: begin
o_ctb_out_data_count <= hst_out_data;
hst_out_stb <= 1;
end
3: begin
o_ctb_out_address <= hst_out_data;
hst_out_stb <= 1;
end
4: begin
o_ctb_out_data <= hst_out_data;
end
default: begin
end
endcase
if (hst_out_stb) begin
out_count <= out_count + 1;
resp_count <= resp_count + 1;
end
end
else begin
o_ctb_out_en <= 1;
if (o_ctb_out_data_count > 1) begin
state <= WRITE_DATA_TO_HOST;
end
else begin
state <= FLUSH;
end
end
end
else begin
if (resp_count >= (response_length - 1)) begin
o_ctb_out_en <= 1;
$display("Reponse Count: %X" % resp_count);
state <= FLUSH;
end
end
end
end
end
WRITE_DATA_TO_HOST: begin
if (out_data_count < o_ctb_out_data_count) begin
if (hst_out_act) begin
if (out_count < hst_out_size) begin
if (i_ctb_out_ready && !o_ctb_out_en) begin
o_ctb_out_en <= 1;
hst_out_stb <= 1;
o_ctb_out_data <= hst_out_data;
out_data_count <= out_data_count + 1;
out_count <= out_count + 1;
end
end
else begin
hst_out_act <= 0;
end
end
end
else begin
state <= FLUSH;
end
end
FLUSH: begin
if (hst_out_act) begin
if (out_count < hst_out_size) begin
hst_out_stb <= 1;
out_count <= out_count + 1;
end
else begin
hst_out_act <= 0;
end
end
else begin
state <= IDLE;
end
end
default: begin
end
endcase
end
end
endmodule
|
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This write master module is responsible for taking in streaming data and
writing the contents out to memory. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as an error in transfer is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming.
2.1 Fixed control logic and removed the early termination enable logic (it's
always on now so for packet transfers make sure the length register is
programmed accordingly.
2.2 Added burst support.
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Corrected a packet problem where EOP wasn't qualified by ready and valid.
Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
snk_data,
snk_valid,
snk_ready,
snk_sop,
snk_eop,
snk_empty,
snk_error,
// data path master port
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter ACTUAL_BYTES_TRANSFERRED_WIDTH = 32; // GUI setting which can only be set when packet support is enabled (otherwise it'll be set to 32). A warning will be issued if overrun protection is enabled and this setting is less than the length width.
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0;
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set the maximum burst count to 1 (automatically done in the .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(MAX_BURST_COUNT) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value MAX_BURST_COUNT will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful and it's not tested. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
//need to buffer the empty, eop, sop, and error bits. If these are not needed then the logic will be synthesized away
localparam FIFO_WIDTH = (DATA_WIDTH + 2 + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH); // data, sop, eop, empty, and error bits
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // when stride isn't supported this will be the stride value used (i.e. sequential incrementing of the address)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path sink port
input [DATA_WIDTH-1:0] snk_data;
input snk_valid;
output wire snk_ready;
input snk_sop;
input snk_eop;
input [NUMBER_OF_SYMBOLS_LOG2-1:0] snk_empty;
input [ERROR_WIDTH-1:0] snk_error;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_write;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
output wire [DATA_WIDTH-1:0] master_writedata;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal wires and registers
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire descriptor_end_on_eop_enable;
wire [7:0] descriptor_programmable_burst_count;
reg [ADDRESS_WIDTH-1:0] address_counter;
wire [ADDRESS_WIDTH-1:0] address; // unfiltered version of master_address
wire write; // unfiltered version of master_write
reg [LENGTH_WIDTH-1:0] length_counter;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg descriptor_end_on_eop_enable_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignement the master started
reg first_access; // used to prevent extra writes when the unaligned access starts and ends during the same write
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
wire increment_address; // enable the address incrementing
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [DATA_WIDTH-1:0] fifo_read_data_rearranged; // if big endian support is enabled then this signal has the FIFO output byte lanes reversed
wire go;
wire done;
reg done_d1;
wire done_strobe;
wire [DATA_WIDTH-1:0] buffered_data;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] buffered_empty;
wire buffered_eop;
wire buffered_sop; // not wired to anything so synthesized away, included for debug purposes
wire [ERROR_WIDTH-1:0] buffered_error;
wire length_sync_reset; // syncronous reset for the length counter for eop support
reg [ACTUAL_BYTES_TRANSFERRED_WIDTH-1:0] actual_bytes_transferred_counter; // width will be in the range of 1-32
wire [31:0] response_actual_bytes_transferred;
wire early_termination;
reg early_termination_d1;
wire eop_enable;
reg [ERROR_WIDTH-1:0] error; // SRFF so that we don't loose any errors if EOP doesn't arrive right away
wire [7:0] response_error; // need to pad upper error bits with zeros if they are not present at the data streaming port
wire sw_stop_in;
wire sw_reset_in;
reg stopped; // SRFF to make sure we don't attempt to stop in the middle of a transfer
reg reset_taken; // FF to make sure we don't attempt to reset the master in the middle of a transfer
wire reset_taken_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst copmletes, 'reset_taken' will use this signal
wire stopped_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst completes, 'stopped' will use this signal
wire stop_state;
wire reset_delayed;
wire write_complete; // handy signal for determining when a write has occured and completed
wire write_stall_from_byte_enable_generator; // partial word access occuring which might take multiple write cycles to complete (or waitrequest has been asserted)
wire write_stall_from_write_burst_control; // when there isn't enough data buffered to start a burst this signal will be asserted
wire [BYTE_ENABLE_WIDTH-1:0] byteenable_masks [0:BYTE_ENABLE_WIDTH-1]; // a bunch of masks that will be provided to unsupported_byteenable
wire [BYTE_ENABLE_WIDTH-1:0] unsupported_byteenable; // input into the byte enable generation block which will take the unsupported byte enable and chop it up into supported transfers
wire [BYTE_ENABLE_WIDTH-1:0] supported_byteenable; // output from the byte enable generation block
wire extra_write; // when asserted master_write will be asserted but the FIFO will not be popped since it will not contain any more data for the transfer
wire st_to_mm_adapter_enable;
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_beat_size; // number of bytes coming in from the data stream when packet support is enabled
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered;
reg [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered_d1; // represents the number of bytes buffered in the ST to MM adapter (only applicable for unaligned accesses)
reg eop_seen; // when the beat containing EOP has been popped from the fifo this bit will be set, it will be reset when done is asserted. It is used to determine if an extra write must occur (unaligned accesses only)
wire last_access; // JCJB: new signal to flag that the final access is occuring, will be used to supress the burst counter from reloading incorrectly at the end of the transfer
/********************************************* REGISTERS ****************************************************************************************/
// registering the stride control bit
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stride_d1 <= 0;
end
else if (go == 1)
begin
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
end
end
// registering the end on eop bit (will be optimized away if packet support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
descriptor_end_on_eop_enable_d1 <= 1'b0;
end
else if (go == 1)
begin
descriptor_end_on_eop_enable_d1 <= descriptor_end_on_eop_enable;
end
end
// registering the programmable burst count (will be optimized away if this support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
programmable_burst_count_d1 <= 0;
end
else if (go == 1)
begin
programmable_burst_count_d1 <= ((descriptor_programmable_burst_count == 0) | (descriptor_programmable_burst_count > MAX_BURST_COUNT)) ? MAX_BURST_COUNT : descriptor_programmable_burst_count;
end
end
// master address increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (increment_address == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first write of a transaction, this will be used to filter 'extra_write' for unaligned accesses
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (increment_address == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1) // when packet support is enabled the length register might roll over so this sync reset will prevent that from happening (it's also used when a soft reset is triggered)
begin
length_counter <= 0; // when EOP arrives need to stop counting, length=0 is the done condition
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (increment_address == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// master actual bytes transferred logic, this will only be used when packet support is enabled, otherwise the value will be 0
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
actual_bytes_transferred_counter <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
actual_bytes_transferred_counter <= 0;
end
else if(increment_address == 1)
begin
actual_bytes_transferred_counter <= actual_bytes_transferred_counter + bytes_to_transfer;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // out of reset the master needs to be 'done' so that the done_strobe doesn't fire
end
else
begin
done_d1 <= done;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
early_termination_d1 <= 0;
end
else
begin
early_termination_d1 <= early_termination;
end
end
generate
genvar l;
for(l = 0; l < ERROR_WIDTH; l = l + 1)
begin: error_SRFF
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error[l] <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
error[l] <= 0;
end
else if ((buffered_error[l] == 1) & (done == 0))
begin
error[l] <= 1;
end
end
end
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if (((src_response_ready == 1) & (src_response_valid == 1)) | (reset_taken == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (reset_taken == 1)
begin
src_response_valid <= 0;
end
else if (done_strobe == 1)
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (reset_taken == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & (((write_complete == 1) & (stopped_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0))))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
reset_taken <= 0;
end
else
begin
reset_taken <= (sw_reset_in == 1) & (((write_complete == 1) & (reset_taken_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0)));
end
end
// eop_seen will be set when the last beat of a packet transfer has been popped from the fifo for ST to MM block flushing purposes (extra write)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
eop_seen <= 0;
end
else
begin
if (done == 1)
begin
eop_seen <= 0;
end
else if ((buffered_eop == 1) & (write_complete == 1))
begin
eop_seen <= 1;
end
end
end
// when unaligned accesses are enabled packet_bytes_buffered_d1 is the number of bytes buffered in the ST to MM block from the previous beat
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_bytes_buffered_d1 <= 0;
end
else
begin
if (go == 1)
begin
packet_bytes_buffered_d1 <= 0;
end
else if (write_complete == 1)
begin
packet_bytes_buffered_d1 <= packet_bytes_buffered;
end
end
end
/********************************************* END REGISTERS ************************************************************************************/
/********************************************* MODULE INSTANTIATIONS ****************************************************************************/
/* buffered sop, eop, empty, error, data (in that order). sop, eop, and empty are only used when packet support is enabled,
likewise error is only used when error support is enabled */
scfifo the_st_to_master_fifo (
.aclr (reset),
.sclr (reset_taken),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.q (fifo_read_data),
.rdreq (fifo_read),
.usedw (fifo_used),
.wrreq (fifo_write)
);
defparam the_st_to_master_fifo.lpm_width = FIFO_WIDTH;
defparam the_st_to_master_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_st_to_master_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_st_to_master_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_st_to_master_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.underflow_checking = "OFF";
defparam the_st_to_master_fifo.overflow_checking = "OFF";
/* This module will barrelshift the data from the FIFO when unaligned accesses is enabled (we are using
part of the FIFO word when off boundary). When unaligned accesses is disabled then the data passes
as wires. The byte enable generator might require multiple cycles to perform partial accesses so a
'stall' bit is used (triggers a stall like waitrequest)
*/
ST_to_MM_Adapter the_ST_to_MM_Adapter (
.clk (clk),
.reset (reset),
.enable (st_to_mm_adapter_enable),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.start (go),
.waitrequest (master_waitrequest),
.stall (write_stall_from_byte_enable_generator | write_stall_from_write_burst_control),
.write_data (master_writedata),
.fifo_data (buffered_data),
.fifo_empty (fifo_empty),
.fifo_readack (fifo_read)
);
defparam the_ST_to_MM_Adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_ST_to_MM_Adapter.BYTEENABLE_WIDTH_LOG2 = BYTE_ENABLE_WIDTH_LOG2;
defparam the_ST_to_MM_Adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_ST_to_MM_Adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
/* this block is responsible for presenting the fabric with supported byte enable combinations which can
take multiple cycles, if full word only support is enabled this block will reduce to wires during synthesis */
byte_enable_generator the_byte_enable_generator (
.clk (clk),
.reset (reset),
.write_in (write),
.byteenable_in (unsupported_byteenable),
.waitrequest_out (write_stall_from_byte_enable_generator),
.byteenable_out (supported_byteenable),
.waitrequest_in (master_waitrequest | write_stall_from_write_burst_control)
);
defparam the_byte_enable_generator.BYTEENABLE_WIDTH = BYTE_ENABLE_WIDTH;
// this block will be used to drive write, address, and burstcount to the fabric
write_burst_control the_write_burst_control (
.clk (clk),
.reset (reset),
.sw_reset (sw_reset_in),
.sw_stop (sw_stop_in),
.length (length_counter),
.eop_enabled (descriptor_end_on_eop_enable_d1),
.eop (snk_eop),
.ready (snk_ready),
.valid (snk_valid),
.early_termination (early_termination),
.address_in (address),
.write_in (write),
.max_burst_count (maximum_burst_count),
.write_fifo_used ({fifo_full,fifo_used}),
.waitrequest (master_waitrequest),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.last_access (last_access), // JCJB; feeding done signal into burst module so that we can suppress the burst logic from sending an extra burst if data if still buffered in FIFO
.address_out (master_address),
.write_out (master_write), // filtered version of 'write'
.burst_count (master_burstcount),
.stall (write_stall_from_write_burst_control),
.reset_taken (reset_taken_from_write_burst_control),
.stopped (stopped_from_write_burst_control)
);
defparam the_write_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_write_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_write_burst_control.WORD_SIZE = BYTE_ENABLE_WIDTH;
defparam the_write_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_write_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_write_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_write_burst_control.WRITE_FIFO_USED_WIDTH = FIFO_DEPTH_LOG2;
defparam the_write_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/********************************************* END MODULE INSTANTIATIONS ************************************************************************/
/********************************************* CONTROL AND COMBINATIONAL SIGNALS ****************************************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_programmable_burst_count = snk_command_data[75:68];
assign descriptor_stride = snk_command_data[91:76];
assign descriptor_end_on_eop_enable = snk_command_data[64];
assign sw_stop_in = snk_command_data[66];
assign sw_reset_in = snk_command_data[67];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
assign eop_enable = (PACKET_ENABLE == 1)? descriptor_end_on_eop_enable_d1 : 1'b0; // no eop or early termination support when packet support is disabled
assign done_strobe = (done == 1) & (done_d1 == 0) & (reset_taken == 0); // set_done asserts the done register so this strobe fires when the last write completes
assign response_error = (ERROR_ENABLE == 1)? error : 8'b00000000;
assign response_actual_bytes_transferred = (PACKET_ENABLE == 1)? actual_bytes_transferred_counter : 32'h00000000;
// transfer size amounts for special cases (starting unaligned, ending with a partial word, starting unaligned and ending with a partial word on the same write)
assign short_first_access_size = BYTE_ENABLE_WIDTH - start_byte_address;
assign short_last_access_size = (eop_enable == 1)? (packet_beat_size + packet_bytes_buffered_d1) : (length_counter & LSB_MASK);
assign short_first_and_last_access_size = (eop_enable == 1)? (BYTE_ENABLE_WIDTH - buffered_empty) : (length_counter & LSB_MASK);
// JCJB: new signal that is high any time there is a word or less to trasnfer, will be used to suppress reloading of the burst counter if data for the next descriptor is buffered
assign last_access = (length_counter <= (DATA_WIDTH/8));
/* special case transfer enables and counter increment values (address_counter, length_counter, and actual_bytes_transferred)
short_first_access_enable is for transfers that start aligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end with on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (may or may not be aligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
// all three enables are mutually exclusive to provide one-hot encoding for the bytes to transfer mux
assign short_first_access_enable = (start_byte_address != 0) & (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) >= BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 0));
assign short_last_access_enable = (first_access == 0) & ((eop_enable == 1)? ((packet_beat_size + packet_bytes_buffered_d1) < BYTE_ENABLE_WIDTH): (length_counter < BYTE_ENABLE_WIDTH));
assign short_first_and_last_access_enable = (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) < BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 1));
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = (eop_enable == 1)? (buffered_eop == 1) : (length_counter < BYTE_ENABLE_WIDTH); // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH;
end
end
endgenerate
// the control logic ensures this mux is one-hot with the fall through being the typical full word aligned access
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size; // unaligned and reaches the next word boundary
3'b010: bytes_to_transfer_mux = short_last_access_size; // aligned and does not reach the next word boundary
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size; // unaligned and does not reach the next word boundary
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH; // aligned and reaches the next word boundary (i.e. a full word transfer)
endcase
end
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before jamming them into the FIFO, changing the symbol width to something other than 8 might break something...
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign fifo_write_data[i +SYMBOL_WIDTH -1: i] = snk_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
// sticking the error, empty, eop, and eop bits at the top of the FIFO write data, flooring empty to zero when eop is not asserted (empty is only valid on eop cycles)
assign fifo_write_data[FIFO_WIDTH-1:DATA_WIDTH] = {snk_error, (snk_eop == 1)? snk_empty:{NUMBER_OF_SYMBOLS_LOG2{1'b0}}, snk_sop, snk_eop};
// swap the bytes if big endian is enabled (remember that this isn't tested so use at your own risk and make sure you understand the software impact this has)
generate
if(BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign fifo_read_data_rearranged[j +8 -1: j] = fifo_read_data[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
assign master_byteenable[j/8] = supported_byteenable[(DATA_WIDTH -j -1)/8];
end
end
else
begin
assign fifo_read_data_rearranged = fifo_read_data[DATA_WIDTH-1:0]; // little endian so no byte swapping necessary
assign master_byteenable = supported_byteenable; // dito
end
endgenerate
// fifo read data is in the format of {error, empty, sop, eop, data} with the following widths {ERROR_WIDTH, NUMBER_OF_SYMBOLS_LOG2, 1, 1, DATA_WIDTH}
assign buffered_data = fifo_read_data_rearranged;
assign buffered_error = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH -1: DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2];
generate
if (PACKET_ENABLE == 1)
begin
assign buffered_eop = fifo_read_data[DATA_WIDTH];
assign buffered_sop = fifo_read_data[DATA_WIDTH +1];
if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign buffered_empty = 0; // ignore the empty signal and assume it was a full beat
end
else
begin
assign buffered_empty = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 -1: DATA_WIDTH +2]; // empty is packed into the upper FIFO bits
end
end
else
begin
assign buffered_empty = 0;
assign buffered_eop = 0;
assign buffered_sop = 0;
end
endgenerate
/* Generating mask bits based on the size of the transfer before the unaligned access adjustment. This is based on the
transfer size to determine how many byte enables would be asserted in the aligned case. Afterwards the
byte enables will be shifted left based on how far out of alignment the address counter is (should only happen for the
first transfer). If the data path is 32 bits wide then the following masks are generated:
Transfer Size Index Mask
1 0 0001
2 1 0011
3 2 0111
4 3 1111
Note that the index is just the transfer size minus one
*/
generate if (BYTE_ENABLE_WIDTH > 1)
begin
genvar k;
for (k = 0; k < BYTE_ENABLE_WIDTH; k = k + 1)
begin: byte_enable_loop
assign byteenable_masks[k] = { {(BYTE_ENABLE_WIDTH-k-1){1'b0}}, {(k+1){1'b1}} }; // Byte enable width - k zeros followed by k ones
end
end
else
begin
assign byteenable_masks[0] = 1'b1; // will be stubbed at top level
end
endgenerate
/* byteenable_mask is based on an aligned access determined by the transfer size. This value is then shifted
to the left by the unaligned offset (first transfer only) to compensate for the unaligned offset so that the
correct byte enables are enabled. When the accesses are aligned then no barrelshifting is needed and when full
accesses are used then all byte enables will be asserted always. */
generate if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign unsupported_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // always full accesses so the byte enables are all ones
end
else if (UNALIGNED_ACCESSES_ENABLE == 0)
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1]; // aligned so no unaligned adjustment required
end
else // unaligned case
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1] << (address_counter & LSB_MASK); // barrelshift adjusts for unaligned start address
end
endgenerate
generate if (BYTE_ENABLE_WIDTH > 1)
begin
assign address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign done = (length_counter == 0) | ((PACKET_ENABLE == 1) & (eop_enable == 1) & (eop_seen == 1) & (extra_write == 0));
assign packet_beat_size = (eop_seen == 1) ? 0 : (BYTE_ENABLE_WIDTH - buffered_empty); // when the eop arrives we can't add more to packet_bytes_buffered_d1
assign packet_bytes_buffered = packet_beat_size + packet_bytes_buffered_d1 - bytes_to_transfer;
// extra_write is only applicable when unaligned accesses are performed. This extra access gets the remaining data buffered in the ST to MM adapter block written to memory
assign extra_write = (UNALIGNED_ACCESSES_ENABLE == 1) & (((PACKET_ENABLE == 1) & (eop_enable == 1))?
((eop_seen == 1) & (packet_bytes_buffered_d1 != 0)) : // when packets are used if there are left over bytes buffered after eop is seen perform an extra write
((first_access == 0) & (start_byte_address != 0) & (short_last_access_enable == 1) & (start_byte_address >= length_counter[BYTE_ENABLE_WIDTH_LOG2-1:0]))); // non-packet transfer and there are extra bytes buffered so performing an extra access
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary (not used for packet transfers)
assign write = ((fifo_empty == 0) | (extra_write == 1)) & (done == 0) & (stopped == 0) & (early_termination_d1 == 0);
assign st_to_mm_adapter_enable = (done == 0) & (extra_write == 0);
assign write_complete = (write == 1) & (master_waitrequest == 0) & (write_stall_from_byte_enable_generator == 0) & (write_stall_from_write_burst_control == 0); // writing still occuring and no reasons to prevent the write cycle from completing
assign increment_address = ((write == 1) & (write_complete == 1)) & (stopped == 0);
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign snk_ready = (fifo_full == 0) & // need to make sure more streaming data doesn't come in when the FIFO is full
(((PACKET_ENABLE == 1) & (snk_sop == 1) & ((eop_enable == 1) | (snk_command_ready == 1)) & (fifo_empty == 0)) != 1); // need to make sure that only one packet is buffered at any given time (sop will continue to be asserted until the buffer is written out)
assign length_sync_reset = (((reset_taken == 1) | (early_termination_d1 == 1)) & (done == 0)) | (done_strobe == 1); // abrupt stop cases or packet transfer just completed (otherwise the length register will reach 0 by itself)
assign fifo_write = (snk_ready == 1) & (snk_valid == 1);
assign early_termination = (eop_enable == 1) &
( ((write_complete == 1) & (length_counter < bytes_to_transfer)) | // packet transfer and the length counter is about to roll over so stop transfering
((length_counter == 0) & (eop_seen == 0) & (go == 0)) ); // length counter hit zero and eop beat still hasn't been written to memory
assign stop_state = stopped;
assign reset_delayed = (reset_taken == 0) & (sw_reset_in == 1);
assign src_response_data = {{212{1'b0}}, done_strobe, early_termination_d1, response_error, stop_state, reset_delayed, response_actual_bytes_transferred};
/********************************************* END CONTROL AND COMBINATIONAL SIGNALS ************************************************************/
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* Last modified by: Ye-sheng Kuo <[email protected]>
* 05/25 '15: Add double latch for DIN
*
* 04/08 '13: Added glitch reset
* */
`include "include/mbus_def.v"
module mbus_ctrl(
input CLK_EXT,
input RESETn,
input CLKIN,
output CLKOUT,
input DIN,
output reg DOUT,
input [`WATCH_DOG_WIDTH-1:0] THRESHOLD
);
`include "include/mbus_func.v"
parameter BUS_IDLE = 0;
parameter BUS_WAIT_START = 3;
parameter BUS_START = 4;
parameter BUS_ARBITRATE = 1;
parameter BUS_PRIO = 2;
parameter BUS_ACTIVE = 5;
parameter BUS_INTERRUPT = 7;
parameter BUS_SWITCH_ROLE = 6;
parameter BUS_CONTROL0 = 8;
parameter BUS_CONTROL1 = 9;
parameter BUS_BACK_TO_IDLE = 10;
parameter NUM_OF_BUS_STATE = 11;
parameter START_CYCLES = 10;
parameter BUS_INTERRUPT_COUNTER = 6;
reg [log2(START_CYCLES-1)-1:0] start_cycle_cnt, next_start_cycle_cnt;
reg [log2(NUM_OF_BUS_STATE-1)-1:0] bus_state, next_bus_state, bus_state_neg;
reg clk_en, next_clk_en;
reg [log2(BUS_INTERRUPT_COUNTER-1)-1:0] bus_interrupt_cnt, next_bus_interrupt_cnt;
reg clkin_sampled;
reg [2:0] din_sampled_neg, din_sampled_pos;
reg [`WATCH_DOG_WIDTH-1:0] threshold_cnt, next_threshold_cnt;
reg din_dly_1, din_dly_2;
always @(posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_dly_1 <= 1'b1;
din_dly_2 <= 1'b1;
end
else begin
din_dly_1 <= DIN;
din_dly_2 <= din_dly_1;
end
end
assign CLKOUT = (clk_en)? CLK_EXT : 1'b1;
wire [1:0] CONTROL_BITS = `CONTROL_SEQ; // EOM?, ~ACK?
always @ (posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
bus_state <= BUS_IDLE;
start_cycle_cnt <= START_CYCLES - 1'b1;
clk_en <= 0;
bus_interrupt_cnt <= BUS_INTERRUPT_COUNTER - 1'b1;
threshold_cnt <= 0;
end
else
begin
bus_state <= next_bus_state;
start_cycle_cnt <= next_start_cycle_cnt;
clk_en <= next_clk_en;
bus_interrupt_cnt <= next_bus_interrupt_cnt;
threshold_cnt <= next_threshold_cnt;
end
end
always @ *
begin
next_bus_state = bus_state;
next_start_cycle_cnt = start_cycle_cnt;
next_clk_en = clk_en;
next_bus_interrupt_cnt = bus_interrupt_cnt;
next_threshold_cnt = threshold_cnt;
case (bus_state)
BUS_IDLE:
begin
if (~din_dly_2)
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = START_CYCLES - 1'b1;
end
BUS_WAIT_START:
begin
next_threshold_cnt = 0;
if (start_cycle_cnt)
next_start_cycle_cnt = start_cycle_cnt - 1'b1;
else
begin
if (~din_dly_2)
begin
next_clk_en = 1;
next_bus_state = BUS_START;
end
else
next_bus_state = BUS_IDLE;
end
end
BUS_START:
begin
next_bus_state = BUS_ARBITRATE;
end
BUS_ARBITRATE:
begin
next_bus_state = BUS_PRIO;
// Glitch, reset bus immediately
if (DIN)
next_threshold_cnt = THRESHOLD;
end
BUS_PRIO:
begin
next_bus_state = BUS_ACTIVE;
end
BUS_ACTIVE:
begin
if ((threshold_cnt<THRESHOLD)&&(~clkin_sampled))
next_threshold_cnt = threshold_cnt + 1'b1;
else
begin
next_clk_en = 0;
next_bus_state = BUS_INTERRUPT;
end
next_bus_interrupt_cnt = BUS_INTERRUPT_COUNTER - 1'b1;
end
BUS_INTERRUPT:
begin
if (bus_interrupt_cnt)
next_bus_interrupt_cnt = bus_interrupt_cnt - 1'b1;
else
begin
if ({din_sampled_neg, din_sampled_pos}==6'b111_000)
begin
next_bus_state = BUS_SWITCH_ROLE;
next_clk_en = 1;
end
end
end
BUS_SWITCH_ROLE:
begin
next_bus_state = BUS_CONTROL0;
end
BUS_CONTROL0:
begin
next_bus_state = BUS_CONTROL1;
end
BUS_CONTROL1:
begin
next_bus_state = BUS_BACK_TO_IDLE;
end
BUS_BACK_TO_IDLE:
begin
if (~DIN)
begin
next_bus_state = BUS_WAIT_START;
next_start_cycle_cnt = 1;
end
else
begin
next_bus_state = BUS_IDLE;
end
next_clk_en = 0;
end
endcase
end
always @ (negedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_sampled_neg <= 0;
bus_state_neg <= BUS_IDLE;
end
else
begin
if (bus_state==BUS_INTERRUPT)
din_sampled_neg <= {din_sampled_neg[1:0], DIN};
bus_state_neg <= bus_state;
end
end
always @ (posedge CLK_EXT or negedge RESETn)
begin
if (~RESETn)
begin
din_sampled_pos <= 0;
clkin_sampled <= 0;
end
else
begin
if (bus_state==BUS_INTERRUPT)
din_sampled_pos <= {din_sampled_pos[1:0], DIN};
clkin_sampled <= CLKIN;
end
end
always @ *
begin
DOUT = DIN;
case (bus_state_neg)
BUS_IDLE: begin DOUT = 1; end
BUS_WAIT_START: begin DOUT = 1; end
BUS_START: begin DOUT = 1; end
BUS_INTERRUPT: begin DOUT = CLK_EXT; end
BUS_CONTROL0: begin if (threshold_cnt==THRESHOLD) DOUT = (~CONTROL_BITS[1]); end
BUS_BACK_TO_IDLE: begin DOUT = 1; end
endcase
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 3.6
// \ \ Application : MIG
// / / Filename : memc_ui_top_std.v
// /___/ /\ Date Last Modified : $Date: 2010/12/21 01:01:43 $
// \ \ / \ Date Created : Fri Oct 08 2010
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM & DDR3 SDRAM
// Purpose :
// Top level memory interface block. Instantiates a clock and
// reset generator, the memory controller, the phy and the
// user interface blocks.
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
(* X_CORE_INFO = "mig_7series_v1_0_ddr3_7Series, Coregen 13.0.2" , CORE_GENERATION_INFO = "ddr3_7Series,mig_7series_v1_0,{LANGUAGE=Verilog, SYNTHESIS_TOOL=ISE, LEVEL=CONTROLLER, USER_INTERFACE_TYPE=NATIVE, NO_OF_CONTROLLERS=1, INTERFACE_TYPE=DDR3, MEMORY_TYPE=COMP, ECC=OFF}" *)
module memc_ui_top_std #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "UNBUF",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter ECC_TEST = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 2, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter ORDERING = "NORM",
parameter IBUF_LPWR_MODE = "OFF",
parameter IODELAY_HP_MODE = "ON",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter OUTPUT_DRV = "HIGH",
parameter REG_CTRL = "OFF",
parameter RTT_NOM = "60",
parameter RTT_WR = "120",
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter WRLVL = "OFF",
parameter DEBUG_PORT = "OFF",
parameter CAL_WIDTH = "HALF",
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter ADDR_WIDTH = 32,
parameter APP_MASK_WIDTH = 8,
parameter APP_DATA_WIDTH = 64,
parameter BYTE_LANES_B0 = 4'hF,
parameter BYTE_LANES_B1 = 4'hF,
parameter BYTE_LANES_B2 = 4'hF,
parameter BYTE_LANES_B3 = 4'hF,
parameter BYTE_LANES_B4 = 4'hF,
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'h0,
parameter DATA_CTL_B4 = 4'h0,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter SLOT_0_CONFIG = 8'b0000_0001,
parameter SLOT_1_CONFIG = 8'b0000_0000,
parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN",
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000, // Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1 // Support ODT output
)
(
// Clock and reset ports
input clk,
input clk_ref,
input mem_refclk ,
input freq_refclk ,
input pll_lock,
input sync_pulse ,
input rst,
// memory interface ports
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
inout [DQS_WIDTH-1:0] ddr_dqs,
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CK_WIDTH-1:0] ddr_ck_n,
output [CK_WIDTH-1:0] ddr_ck,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [RANKS-1:0] ddr_odt,
output ddr_ras_n,
output ddr_reset_n,
output ddr_parity,
output ddr_we_n,
output [BM_CNT_WIDTH-1:0] bank_mach_next,
// user interface ports
input [ADDR_WIDTH-1:0] app_addr,
input [2:0] app_cmd,
input app_en,
input app_hi_pri,
input app_sz,
input [APP_DATA_WIDTH-1:0] app_wdf_data,
input app_wdf_end,
input [APP_MASK_WIDTH-1:0] app_wdf_mask,
input app_wdf_wren,
output [3:0] app_ecc_multiple_err,
output [APP_DATA_WIDTH-1:0] app_rd_data,
output app_rd_data_end,
output app_rd_data_valid,
output app_rdy,
output app_wdf_rdy,
// debug logic ports
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
output [255:0] dbg_calib_top,
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
output [255:0] dbg_phy_rdlvl,
output [15:0] dbg_phy_wrcal,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [4*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [4:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output init_calib_complete
);
wire correct_en;
wire [3:0] raw_not_ecc;
wire [3:0] ecc_single;
wire [3:0] ecc_multiple;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
wire [3:0] app_raw_not_ecc;
wire app_correct_en;
wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
wire wr_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire rd_data_en;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
wire accept;
wire accept_ns;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
wire rd_data_end;
wire use_addr;
wire size;
wire [ROW_WIDTH-1:0] row;
wire [RANK_WIDTH-1:0] rank;
wire hi_priority;
wire [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr;
wire [COL_WIDTH-1:0] col;
wire [2:0] cmd;
wire [BANK_WIDTH-1:0] bank;
wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data;
wire [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask;
mem_intfc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.AL (AL),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.nCS_PER_RANK (nCS_PER_RANK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DM_WIDTH (DM_WIDTH),
.DQ_CNT_WIDTH (DQ_CNT_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DRAM_WIDTH (DRAM_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.nAL (nAL),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.ORDERING (ORDERING),
.OUTPUT_DRV (OUTPUT_DRV),
.IBUF_LPWR_MODE (IBUF_LPWR_MODE),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.CL (CL),
.CWL (CWL),
.tCK (tCK),
.tFAW (tFAW),
.tPRDI (tPRDI),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS),
.WRLVL (WRLVL),
.DEBUG_PORT (DEBUG_PORT),
.CAL_WIDTH (CAL_WIDTH),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.ROW_WIDTH (ROW_WIDTH),
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.SLOT_0_CONFIG (SLOT_0_CONFIG),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.STARVE_LIMIT (STARVE_LIMIT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT)
)
mem_intfc0
(
.clk (clk),
.clk_ref (clk_ref),
.mem_refclk (mem_refclk), //memory clock
.freq_refclk (freq_refclk),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
.rst (rst),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs (ddr_dqs),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck (ddr_ck),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_we_n (ddr_we_n),
.slot_0_present (SLOT_0_CONFIG),
.slot_1_present (SLOT_1_CONFIG),
.correct_en (correct_en),
.bank (bank),
.cmd (cmd),
.col (col),
.data_buf_addr (data_buf_addr),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
.rank (rank),
.raw_not_ecc (raw_not_ecc),
.row (row),
.hi_priority (hi_priority),
.size (size),
.use_addr (use_addr),
.accept (accept),
.accept_ns (accept_ns),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.rd_data (rd_data),
.rd_data_addr (rd_data_addr),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.bank_mach_next (bank_mach_next),
.init_calib_complete (init_calib_complete),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start)
);
ui_top #
(
.TCQ (TCQ),
.APP_DATA_WIDTH (APP_DATA_WIDTH),
.APP_MASK_WIDTH (APP_MASK_WIDTH),
.BANK_WIDTH (BANK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.CWL (CWL),
.ECC (ECC),
.ECC_TEST (ECC_TEST),
.ORDERING (ORDERING),
.RANKS (RANKS),
.RANK_WIDTH (RANK_WIDTH),
.ROW_WIDTH (ROW_WIDTH),
.MEM_ADDR_ORDER (MEM_ADDR_ORDER)
)
u_ui_top
(
.wr_data_mask (wr_data_mask[APP_MASK_WIDTH-1:0]),
.wr_data (wr_data[APP_DATA_WIDTH-1:0]),
.use_addr (use_addr),
.size (size),
.row (row),
.raw_not_ecc (raw_not_ecc),
.rank (rank),
.hi_priority (hi_priority),
.data_buf_addr (data_buf_addr[3:0]),
.col (col),
.cmd (cmd),
.bank (bank),
.app_wdf_rdy (app_wdf_rdy),
.app_rdy (app_rdy),
.app_rd_data_valid (app_rd_data_valid),
.app_rd_data_end (app_rd_data_end),
.app_rd_data (app_rd_data),
.app_ecc_multiple_err (app_ecc_multiple_err),
.correct_en (correct_en),
.wr_data_offset (wr_data_offset),
.wr_data_en (wr_data_en),
.wr_data_addr (wr_data_addr[3:0]),
.rst (rst),
.rd_data_offset (rd_data_offset),
.rd_data_end (rd_data_end),
.rd_data_en (rd_data_en),
.rd_data_addr (rd_data_addr[3:0]),
.rd_data (rd_data[APP_DATA_WIDTH-1:0]),
.ecc_multiple (ecc_multiple),
.clk (clk),
.app_wdf_wren (app_wdf_wren),
.app_wdf_mask (app_wdf_mask),
.app_wdf_end (app_wdf_end),
.app_wdf_data (app_wdf_data),
.app_sz (app_sz),
.app_raw_not_ecc (app_raw_not_ecc),
.app_hi_pri (app_hi_pri),
.app_en (app_en),
.app_cmd (app_cmd),
.app_addr (app_addr),
.accept_ns (accept_ns),
.accept (accept),
.app_correct_en (app_correct_en)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EBUFN_BEHAVIORAL_PP_V |
(** * Logic: Logic in Coq *)
Require Export MoreCoq.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives.
*)
(* ########################################################### *)
(** * Propositions *)
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions
([forall x, P]).
*)
(** In Coq, the type of things that can (potentially)
be proven is [Prop]. *)
(** Here is an example of a provable proposition: *)
Check (3 = 3).
(* ===> Prop *)
(** Here is an example of an unprovable proposition: *)
Check (forall (n:nat), n = 2).
(* ===> Prop *)
(** Recall that [Check] asks Coq to tell us the type of the indicated
expression. *)
(* ########################################################### *)
(** * Proofs and Evidence *)
(** In Coq, propositions have the same status as other types, such as
[nat]. Just as the natural numbers [0], [1], [2], etc. inhabit
the type [nat], a Coq proposition [P] is inhabited by its
_proofs_. We will refer to such inhabitants as _proof term_ or
_proof object_ or _evidence_ for the truth of [P].
In Coq, when we state and then prove a lemma such as:
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
the tactics we use within the [Proof]...[Qed] keywords tell Coq
how to construct a proof term that inhabits the proposition. In
this case, the proposition [0 * 3 = 0] is justified by a
combination of the _definition_ of [mult], which says that [0 * 3]
_simplifies_ to just [0], and the _reflexive_ principle of
equality, which says that [0 = 0].
*)
(** *** *)
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
(** We can see which proof term Coq constructs for a given Lemma by
using the [Print] directive: *)
Print silly.
(* ===> silly = eq_refl : 0 * 3 = 0 *)
(** Here, the [eq_refl] proof term witnesses the equality. (More on
equality later!)*)
(** ** Implications _are_ functions *)
(** Just as we can implement natural number multiplication as a
function:
[
mult : nat -> nat -> nat
]
The _proof term_ for an implication [P -> Q] is a _function_ that
takes evidence for [P] as input and produces evidence for [Q] as its
output.
*)
Lemma silly_implication : (1 + 1) = 2 -> 0 * 3 = 0.
Proof. intros H. reflexivity. Qed.
(** We can see that the proof term for the above lemma is indeed a
function: *)
Print silly_implication.
(* ===> silly_implication = fun _ : 1 + 1 = 2 => eq_refl
: 1 + 1 = 2 -> 0 * 3 = 0 *)
(** ** Defining propositions *)
(** Just as we can create user-defined inductive types (like the
lists, binary representations of natural numbers, etc., that we
seen before), we can also create _user-defined_ propositions.
Question: How do you define the meaning of a proposition?
*)
(** *** *)
(** The meaning of a proposition is given by _rules_ and _definitions_
that say how to construct _evidence_ for the truth of the
proposition from other evidence.
- Typically, rules are defined _inductively_, just like any other
datatype.
- Sometimes a proposition is declared to be true without
substantiating evidence. Such propositions are called _axioms_.
In this, and subsequence chapters, we'll see more about how these
proof terms work in more detail.
*)
(* ########################################################### *)
(** * Conjunction (Logical "and") *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** ** "Introducing" conjunctions *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(0 = 0) /\ (4 = mult 2 2).
Proof.
apply conj.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(0 = 0) /\ (4 = mult 2 2).
Proof.
split.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** ** "Eliminating" conjunctions *)
(** Conversely, the [destruct] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
destruct H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
(* WORKED IN CLASS *)
intros P Q H.
destruct H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[destruct] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
destruct H as [HP [HQ HR]].
split.
split.
apply HP.
apply HQ.
apply HR.
Qed.
(* ###################################################### *)
(** * Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
destruct H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
destruct H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
(* FILL IN HERE *) Admitted.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
(* FILL IN HERE *) Admitted.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction (Logical "or") *)
(** ** Implementing disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** *** *)
(** Since [P \/ Q] has two constructors, doing [destruct] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
destruct H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
destruct H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. destruct H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros.
destruct H.
destruct H.
apply or_introl.
apply H.
destruct H0.
apply or_introl.
apply H0.
apply or_intror.
split.
apply H.
apply H0.
Qed.
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct H.
rewrite H. rewrite H0. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (andb_false) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros.
destruct b.
destruct c.
inversion H.
apply or_intror.
reflexivity.
destruct c.
apply or_introl.
reflexivity.
apply or_introl.
reflexivity.
Qed.
(** **** Exercise: 2 stars, optional (orb_false) *)
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros.
destruct b.
apply or_introl.
reflexivity.
destruct c.
apply or_intror.
reflexivity.
inversion H.
Qed.
(** **** Exercise: 2 stars, optional (orb_false_elim) *)
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** *** *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
Inductive True : Prop :=
| maketrue.
Check maketrue.
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
(** *** *)
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. destruct H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros.
unfold not.
intros.
apply H in H1.
destruct H0.
apply H1.
Qed.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** *** Constructive logic *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
Theorem peirce_equiv_classic : peirce <-> classic.
compute.
split.
intros.
apply H with (Q:=False).
intros.
apply H0 in H1.
inversion H1.
intros.
apply H.
intros.
apply H1 in H0.
inversion H0.
intros.
apply H1 in H2.
inversion H2.
Qed.
(** **** Exercise: 3 stars (excluded_middle_irrefutable) *)
(** This theorem implies that it is always safe to add a decidability
axiom (i.e. an instance of excluded middle) for any _particular_ Prop [P].
Why? Because we cannot prove the negation of such an axiom; if we could,
we would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)], a contradiction. *)
Theorem excluded_middle_irrefutable: forall (P:Prop), ~ ~ (P \/ ~ P).
Proof.
intros.
unfold not.
intros.
apply H.
right.
intros.
apply H.
left.
apply H0.
Qed.
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
intros n.
induction n.
induction m.
intros.
apply ex_falso_quodlibet.
unfold not in H.
apply H.
reflexivity.
intros.
compute.
reflexivity.
induction m.
intros.
compute.
reflexivity.
intros.
simpl.
apply IHn.
compute.
compute in H.
intros.
apply H.
rewrite H0.
reflexivity.
Qed.
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
intros n.
induction n.
induction m.
compute.
intros.
inversion H.
intros.
compute.
intros.
inversion H0.
induction m.
intros.
compute.
intros.
inversion H0.
intros.
simpl in H.
apply IHn in H.
compute.
intros.
apply H.
inversion H0.
reflexivity.
Qed.
(** $Date: 2014-12-31 11:17:56 -0500 (Wed, 31 Dec 2014) $ *)
|
// Implements GPIO pins from the PS/EMIO
// Works with 7010 (24 pins) or 7020 (48 pins) and
// either single-ended or differential IO
module parallella_gpio_emio
(/*AUTOARG*/
// Outputs
PS_GPIO_I,
// Inouts
GPIO_P, GPIO_N,
// Inputs
PS_GPIO_O, PS_GPIO_T
);
parameter NUM_GPIO_PAIRS = 24; // 12 or 24
parameter DIFF_GPIO = 0; // 0 or 1
parameter NUM_PS_SIGS = 64;
inout [NUM_GPIO_PAIRS-1:0] GPIO_P;
inout [NUM_GPIO_PAIRS-1:0] GPIO_N;
output [NUM_PS_SIGS-1:0] PS_GPIO_I;
input [NUM_PS_SIGS-1:0] PS_GPIO_O;
input [NUM_PS_SIGS-1:0] PS_GPIO_T;
genvar m;
generate
if( DIFF_GPIO == 1 ) begin: GPIO_DIFF
IOBUFDS
#(
.DIFF_TERM("TRUE"),
.IBUF_LOW_PWR("TRUE"),
.IOSTANDARD("LVDS_25"),
.SLEW("FAST")
)
GPIOBUF_DS [NUM_GPIO_PAIRS-1:0]
(
.O(PS_GPIO_I), // Buffer output
.IO(GPIO_P), // Diff_p inout (connect directly to top-level port)
.IOB(GPIO_N), // Diff_n inout (connect directly to top-level port)
.I(PS_GPIO_O), // Buffer input
.T(PS_GPIO_T) // 3-state enable input, high=input, low=output
);
end else begin: GPIO_SE // single-ended
wire [NUM_GPIO_PAIRS-1:0] gpio_i_n, gpio_i_p;
wire [NUM_GPIO_PAIRS-1:0] gpio_o_n, gpio_o_p;
wire [NUM_GPIO_PAIRS-1:0] gpio_t_n, gpio_t_p;
// Map P/N pins to single-ended signals
for(m=0; m<NUM_GPIO_PAIRS; m=m+2) begin : assign_se_sigs
assign PS_GPIO_I[2*m] = gpio_i_n[m];
assign PS_GPIO_I[2*m+1] = gpio_i_n[m+1];
assign PS_GPIO_I[2*m+2] = gpio_i_p[m];
assign PS_GPIO_I[2*m+3] = gpio_i_p[m+1];
assign gpio_o_n[m] = PS_GPIO_O[2*m];
assign gpio_o_n[m+1] = PS_GPIO_O[2*m+1];
assign gpio_o_p[m] = PS_GPIO_O[2*m+2];
assign gpio_o_p[m+1] = PS_GPIO_O[2*m+3];
assign gpio_t_n[m] = PS_GPIO_T[2*m];
assign gpio_t_n[m+1] = PS_GPIO_T[2*m+1];
assign gpio_t_p[m] = PS_GPIO_T[2*m+2];
assign gpio_t_p[m+1] = PS_GPIO_T[2*m+3];
end // block: assign_se_sigs
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
GPIOBUF_SE_N [NUM_GPIO_PAIRS-1:0]
(
.O(gpio_i_n), // Buffer output
.IO(GPIO_N), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_n), // Buffer input
.T(gpio_t_n) // 3-state enable input, high=input, low=output
);
IOBUF
#(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("LVCMOS25"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
)
GPIOBUF_SE_P [NUM_GPIO_PAIRS-1:0]
(
.O(gpio_i_p), // Buffer output
.IO(GPIO_P), // Buffer inout port (connect directly to top-level port)
.I(gpio_o_p), // Buffer input
.T(gpio_t_p) // 3-state enable input, high=input, low=output
);
end // block: GPIO_SE
endgenerate
// Tie unused PS signals back to themselves
genvar n;
generate for(n=NUM_GPIO_PAIRS*2; n<48; n=n+1) begin : unused_ps_sigs
assign PS_GPIO_I[n]
= PS_GPIO_O[n] &
~PS_GPIO_T[n];
end
endgenerate
endmodule // parallella_gpio_emio
/*
File: parallella_gpio_emio.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2014 Adapteva, Inc.
Contributed by Fred Huettig
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/*
-- ============================================================================
-- FILE NAME : uart_ctrl.v
-- DESCRIPTION : UART§äW
[
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2011/06/27 suito VKì¬
-- ============================================================================
*/
/********** ¤Êwb_t@C **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** ÂÊwb_t@C **********/
`include "uart.h"
/********** W
[ **********/
module uart_ctrl (
/********** NbN & Zbg **********/
input wire clk, // NbN
input wire reset, // ñ¯úZbg
/********** oXC^tF[X **********/
input wire cs_, // `bvZNg
input wire as_, // AhXXg[u
input wire rw, // Read / Write
input wire [`UartAddrBus] addr, // AhX
input wire [`WordDataBus] wr_data, // «Ýf[^
output reg [`WordDataBus] rd_data, // ÇÝoµf[^
output reg rdy_, // fB
/********** èÝ **********/
output reg irq_rx, // óM®¹èÝi§äWX^ 0j
output reg irq_tx, // M®¹èÝi§äWX^ 0j
/********** §äM **********/
// óM§ä
input wire rx_busy, // óMtOi§äWX^ 0j
input wire rx_end, // óM®¹M
input wire [`ByteDataBus] rx_data, // óMf[^
// M§ä
input wire tx_busy, // MtOi§äWX^ 0j
input wire tx_end, // M®¹M
output reg tx_start, // MJnM
output reg [`ByteDataBus] tx_data // Mf[^
);
/********** §äWc^ **********/
// §äWX^ 1 : óMf[^
reg [`ByteDataBus] rx_buf; // óMobt@
/********** UART§ä_ **********/
always @(posedge clk or `RESET_EDGE reset) begin
if (reset == `RESET_ENABLE) begin
/* ñ¯úZbg */
rd_data <= #1 `WORD_DATA_W'h0;
rdy_ <= #1 `DISABLE_;
irq_rx <= #1 `DISABLE;
irq_tx <= #1 `DISABLE;
rx_buf <= #1 `BYTE_DATA_W'h0;
tx_start <= #1 `DISABLE;
tx_data <= #1 `BYTE_DATA_W'h0;
end else begin
/* fB̶¬ */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_)) begin
rdy_ <= #1 `ENABLE_;
end else begin
rdy_ <= #1 `DISABLE_;
end
/* ÇÝoµANZX */
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) && (rw == `READ)) begin
case (addr)
`UART_ADDR_STATUS : begin // §äWX^ 0
rd_data <= #1 {{`WORD_DATA_W-4{1'b0}},
tx_busy, rx_busy, irq_tx, irq_rx};
end
`UART_ADDR_DATA : begin // §äWX^ 1
rd_data <= #1 {{`BYTE_DATA_W*2{1'b0}}, rx_buf};
end
endcase
end else begin
rd_data <= #1 `WORD_DATA_W'h0;
end
/* «ÝANZX */
// §äWX^ 0 : M®¹èÝ
if (tx_end == `ENABLE) begin
irq_tx<= #1 `ENABLE;
end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
irq_tx<= #1 wr_data[`UartCtrlIrqTx];
end
// §äWX^ 0 : óM®¹èÝ
if (rx_end == `ENABLE) begin
irq_rx<= #1 `ENABLE;
end else if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_STATUS)) begin
irq_rx<= #1 wr_data[`UartCtrlIrqRx];
end
// §äWX^ 1
if ((cs_ == `ENABLE_) && (as_ == `ENABLE_) &&
(rw == `WRITE) && (addr == `UART_ADDR_DATA)) begin // MJn
tx_start <= #1 `ENABLE;
tx_data <= #1 wr_data[`BYTE_MSB:`LSB];
end else begin
tx_start <= #1 `DISABLE;
tx_data <= #1 `BYTE_DATA_W'h0;
end
/* óMf[^ÌæèÝ */
if (rx_end == `ENABLE) begin
rx_buf <= #1 rx_data;
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_2_V
`define SKY130_FD_SC_LP__SDFSTP_2_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sdfstp_2 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A22O_M_V
`define SKY130_FD_SC_LP__A22O_M_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_m (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a22o_m (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A22O_M_V
|
//==================================================================================================
// Filename : tb_core.v
// Created On : Sun Sep 6 22:43:11 2015
// Last Modified : Sat Sep 12 21:24:12 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Antares core testbench
//==================================================================================================
`include "antares_defines.v"
`timescale 1ns / 100ps
`define MEM_ADDR_WIDTH 12 // 2^(MEM_ADDR_WIDTH + 2) = 16 KB of memory
module tb_core;
//--------------------------------------------------------------------------
// wires
//--------------------------------------------------------------------------
wire clk_core;
wire clk_bus;
wire rst;
wire [31:0] dport_address;
wire [31:0] dport_data_i;
wire [31:0] dport_data_o;
wire dport_enable;
wire [3:0] dport_wr;
wire dport_ready;
wire dport_error;
wire [31:0] iport_address;
wire [31:0] iport_data_i;
wire iport_enable;
wire [3:0] iport_wr;
wire iport_ready;
wire iport_error;
wire halted;
reg rst_sync;
//--------------------------------------------------------------------------
// Assigns
//--------------------------------------------------------------------------
assign iport_error = 1'b0; // No errors
assign dport_error = 1'b0; // No errors
always @(posedge clk_core) begin
rst_sync <= rst;
end
//--------------------------------------------------------------------------
// MIPS CORE
//--------------------------------------------------------------------------
antares_core #(
.ENABLE_HW_MULT ( 1 ),
.ENABLE_HW_DIV ( 1 ),
.ENABLE_HW_CLOZ ( 1 )
)
core(
// Outputs
.halted ( halted ),
.iport_address ( iport_address[31:0] ),
.iport_wr ( iport_wr[3:0] ),
.iport_enable ( iport_enable ),
.dport_address ( dport_address[31:0] ),
.dport_data_o ( dport_data_o[31:0] ),
.dport_wr ( dport_wr[3:0] ),
.dport_enable ( dport_enable ),
// Inputs
.clk ( clk_core ),
.rst ( rst_sync ),
.interrupts ( 5'b0 ), // No external interrupts.
.nmi ( 1'b0 ), // No external interrupts.
.iport_data_i ( iport_data_i[31:0] ),
.iport_ready ( iport_ready ),
.dport_data_i ( dport_data_i[31:0] ),
.dport_ready ( dport_ready ),
.iport_error ( iport_error ),
.dport_error ( dport_error )
);
//--------------------------------------------------------------------------
// Instruction/Data Memory
// Port A = Instruccion
// Port B = Data
//--------------------------------------------------------------------------
memory #(
.MEM_ADDR_WIDTH( `MEM_ADDR_WIDTH ) // Memory size
)
memory0(
.clk ( clk_bus ),
.rst ( rst_sync ),
.a_addr ( iport_address[2 +: `MEM_ADDR_WIDTH] ), // instruction port
.a_din ( 32'hB00B_B00B ),
.a_wr ( iport_wr[3:0] ),
.a_enable ( iport_enable ),
.a_dout ( iport_data_i[31:0] ),
.a_ready ( iport_ready ),
.b_addr ( dport_address[2 +: `MEM_ADDR_WIDTH] ), // data port
.b_din ( dport_data_o[31:0] ),
.b_wr ( dport_wr[3:0] ),
.b_enable ( dport_enable ),
.b_dout ( dport_data_i[31:0] ),
.b_ready ( dport_ready )
);
//--------------------------------------------------------------------------
// Monitor
//--------------------------------------------------------------------------
monitor monitor0(
.halt ( halted ),
.if_stall ( core.if_stall ),
.if_flush ( core.if_flush ),
.id_stall ( core.id_stall ),
.id_flush ( core.id_flush ),
.ex_stall ( core.ex_stall ),
.ex_flush ( core.ex_flush ),
.mem_stall ( core.mem_stall ),
.mem_flush ( core.mem_flush ),
.wb_stall ( core.wb_stall ),
.mem_exception_pc ( core.mem_exception_pc ),
.id_instruction ( core.id_instruction ),
.wb_gpr_wa ( core.wb_gpr_wa ),
.wb_gpr_wd ( core.wb_gpr_wd ),
.wb_gpr_we ( core.wb_gpr_we ),
.mem_address ( core.mem_alu_result ),
.mem_data ( core.mem_mem_store_data ),
.if_exception_ready ( core.cpzero0.if_exception_ready ),
.id_exception_ready ( core.cpzero0.id_exception_ready ),
.ex_exception_ready ( core.cpzero0.ex_exception_ready ),
.mem_exception_ready ( core.cpzero0.mem_exception_ready ),
.clk_core ( clk_core ),
.clk_bus ( clk_bus ),
.rst ( rst )
);
endmodule
// Local Variables:
// verilog-library-flags:("-y ../../../Hardware/ -y utils/")
// flycheck-verilator-include-path:("../../../Hardware/" "utils/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FILL_DIODE_8_V
`define SKY130_FD_SC_LS__FILL_DIODE_8_V
/**
* fill_diode: Fill diode.
*
* Verilog wrapper for fill_diode with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fill_diode.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fill_diode base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fill_diode_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fill_diode base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FILL_DIODE_8_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O211AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__O211AI_FUNCTIONAL_PP_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__o211ai (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
B1 ,
C1
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
// Local signals
wire C1 or0_out ;
wire nand0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, or0_out, B1 );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__O211AI_FUNCTIONAL_PP_V |
// Polyphase filter bank for upsampling from 48000.0kHz to 96000.0kHz
// Depth: 32
module rom_firbank_48_96(
input wire clk,
input wire [4:0] addr,
output wire [23:0] data);
reg [23:0] data_ff;
assign data = data_ff;
always @(posedge clk) begin
case(addr)
0: data_ff <= 24'h164B2D; // 1461037
1: data_ff <= 24'hF5BAE8; // -673048
2: data_ff <= 24'h0633AB; // 406443
3: data_ff <= 24'hFC29F9; // -251399
4: data_ff <= 24'h0242A4; // 148132
5: data_ff <= 24'hFEC9C7; // -79417
6: data_ff <= 24'h008EDD; // 36573
7: data_ff <= 24'hFFCE7B; // -12677
8: data_ff <= 24'h0005BB; // 1467
9: data_ff <= 24'h00091C; // 2332
10: data_ff <= 24'hFFF5DC; // -2596
11: data_ff <= 24'h0006AF; // 1711
12: data_ff <= 24'hFFFCC4; // -828
13: data_ff <= 24'h000124; // 292
14: data_ff <= 24'hFFFFC3; // -61
15: data_ff <= 24'h000004; // 4
16: data_ff <= 24'h35A6A3; // 3516067
17: data_ff <= 24'hF90C13; // -455661
18: data_ff <= 24'h01922A; // 102954
19: data_ff <= 24'h005211; // 21009
20: data_ff <= 24'hFEFDCB; // -66101
21: data_ff <= 24'h011F4C; // 73548
22: data_ff <= 24'hFF0A15; // -62955
23: data_ff <= 24'h00B389; // 45961
24: data_ff <= 24'hFF8D35; // -29387
25: data_ff <= 24'h00406C; // 16492
26: data_ff <= 24'hFFE0A7; // -8025
27: data_ff <= 24'h000CDE; // 3294
28: data_ff <= 24'hFFFBC5; // -1083
29: data_ff <= 24'h0000FE; // 254
30: data_ff <= 24'hFFFFE3; // -29
31: data_ff <= 24'hFFFFFF; // -1
default: data_ff <= 0;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
`define SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKBUF_BEHAVIORAL_V |
module fast162_dp(
input wire clk,
input wire reset,
input wire power,
input wire sw_single_step,
input wire sw_restart,
// 4 Membus slaves
input wire membus_wr_rs_p0,
input wire membus_rq_cyc_p0,
input wire membus_rd_rq_p0,
input wire membus_wr_rq_p0,
input wire [21:35] membus_ma_p0,
input wire [18:21] membus_sel_p0,
input wire membus_fmc_select_p0,
input wire [0:35] membus_mb_in_p0,
output wire membus_addr_ack_p0,
output wire membus_rd_rs_p0,
output wire [0:35] membus_mb_out_p0,
input wire membus_wr_rs_p1,
input wire membus_rq_cyc_p1,
input wire membus_rd_rq_p1,
input wire membus_wr_rq_p1,
input wire [21:35] membus_ma_p1,
input wire [18:21] membus_sel_p1,
input wire membus_fmc_select_p1,
input wire [0:35] membus_mb_in_p1,
output wire membus_addr_ack_p1,
output wire membus_rd_rs_p1,
output wire [0:35] membus_mb_out_p1,
input wire membus_wr_rs_p2,
input wire membus_rq_cyc_p2,
input wire membus_rd_rq_p2,
input wire membus_wr_rq_p2,
input wire [21:35] membus_ma_p2,
input wire [18:21] membus_sel_p2,
input wire membus_fmc_select_p2,
input wire [0:35] membus_mb_in_p2,
output wire membus_addr_ack_p2,
output wire membus_rd_rs_p2,
output wire [0:35] membus_mb_out_p2,
input wire membus_wr_rs_p3,
input wire membus_rq_cyc_p3,
input wire membus_rd_rq_p3,
input wire membus_wr_rq_p3,
input wire [21:35] membus_ma_p3,
input wire [18:21] membus_sel_p3,
input wire membus_fmc_select_p3,
input wire [0:35] membus_mb_in_p3,
output wire membus_addr_ack_p3,
output wire membus_rd_rs_p3,
output wire [0:35] membus_mb_out_p3,
// 36 bit Avalon Slave
input wire [17:0] s_address,
input wire s_write,
input wire s_read,
input wire [35:0] s_writedata,
output wire [35:0] s_readdata,
output wire s_waitrequest
);
/* Jumpers */
parameter memsel_p0 = 4'b0;
parameter memsel_p1 = 4'b0;
parameter memsel_p2 = 4'b0;
parameter memsel_p3 = 4'b0;
parameter fmc_p0_sel = 1'b1;
parameter fmc_p1_sel = 1'b0;
parameter fmc_p2_sel = 1'b0;
parameter fmc_p3_sel = 1'b0;
reg fmc_act;
reg fmc_rd0;
reg fmc_rs; // not used, what is this?
reg fmc_stop;
reg fmc_wr;
wire [0:35] fm_out = (fma != 0 | fmc_rd0) ? ff[fma] : 0;
reg [0:35] ff[0:15];
wire wr_rs = fmc_p0_sel ? membus_wr_rs_p0 :
fmc_p1_sel ? membus_wr_rs_p1 :
fmc_p2_sel ? membus_wr_rs_p2 :
fmc_p3_sel ? membus_wr_rs_p3 : 1'b0;
wire fma_rd_rq = fmc_p0_sel ? membus_rd_rq_p0 :
fmc_p1_sel ? membus_rd_rq_p1 :
fmc_p2_sel ? membus_rd_rq_p2 :
fmc_p3_sel ? membus_rd_rq_p3 : 1'b0;
wire fma_wr_rq = fmc_p0_sel ? membus_wr_rq_p0 :
fmc_p1_sel ? membus_wr_rq_p1 :
fmc_p2_sel ? membus_wr_rq_p2 :
fmc_p3_sel ? membus_wr_rq_p3 : 1'b0;
wire [21:35] fma = fmc_p0_sel ? membus_ma_p0[32:35] :
fmc_p1_sel ? membus_ma_p1[32:35] :
fmc_p2_sel ? membus_ma_p2[32:35] :
fmc_p3_sel ? membus_ma_p3[32:35] : 1'b0;
wire [0:35] mb_in = fmc_p0_wr_sel ? membus_mb_in_p0 :
fmc_p1_wr_sel ? membus_mb_in_p1 :
fmc_p2_wr_sel ? membus_mb_in_p2 :
fmc_p3_wr_sel ? membus_mb_in_p3 : 1'b0;
assign membus_addr_ack_p0 = fmc_addr_ack & fmc_p0_sel;
assign membus_rd_rs_p0 = fmc_rd_rs & fmc_p0_sel;
assign membus_mb_out_p0 = fmc_p0_sel ? mb_out : 1'b0;
assign membus_addr_ack_p1 = fmc_addr_ack & fmc_p1_sel;
assign membus_rd_rs_p1 = fmc_rd_rs & fmc_p1_sel;
assign membus_mb_out_p1 = fmc_p1_sel ? mb_out : 1'b0;
assign membus_addr_ack_p2 = fmc_addr_ack & fmc_p2_sel;
assign membus_rd_rs_p2 = fmc_rd_rs & fmc_p2_sel;
assign membus_mb_out_p2 = fmc_p2_sel ? mb_out : 1'b0;
assign membus_addr_ack_p3 = fmc_addr_ack & fmc_p3_sel;
assign membus_rd_rs_p3 = fmc_rd_rs & fmc_p3_sel;
assign membus_mb_out_p3 = fmc_p3_sel ? mb_out : 1'b0;
wire fmc_addr_ack;
wire fmc_rd_rs;
wire [0:35] mb_out = fmc_rd_strb ? fm_out : 36'b0;
wire fmc_p0_sel1 = fmc_p0_sel & ~fmc_stop;
wire fmc_p1_sel1 = fmc_p1_sel & ~fmc_stop;
wire fmc_p2_sel1 = fmc_p2_sel & ~fmc_stop;
wire fmc_p3_sel1 = fmc_p3_sel & ~fmc_stop;
wire fmc_p0_wr_sel = fmc_p0_sel & fmc_act & ~fma_rd_rq;
wire fmc_p1_wr_sel = fmc_p1_sel & fmc_act & ~fma_rd_rq;
wire fmc_p2_wr_sel = fmc_p2_sel & fmc_act & ~fma_rd_rq;
wire fmc_p3_wr_sel = fmc_p3_sel & fmc_act & ~fma_rd_rq;
wire fmpc_p0_rq = fmc_p0_sel1 & memsel_p0 == membus_sel_p0 &
membus_fmc_select_p0 & membus_rq_cyc_p0;
wire fmpc_p1_rq = fmc_p1_sel1 & memsel_p1 == membus_sel_p1 &
membus_fmc_select_p1 & membus_rq_cyc_p1;
wire fmpc_p2_rq = fmc_p2_sel1 & memsel_p2 == membus_sel_p2 &
membus_fmc_select_p2 & membus_rq_cyc_p2;
wire fmpc_p3_rq = fmc_p3_sel1 & memsel_p3 == membus_sel_p3 &
membus_fmc_select_p3 & membus_rq_cyc_p3;
wire fmc_pwr_on;
wire fmc_restart;
wire fmc_start;
wire fmc_rd_strb;
wire fmct0;
wire fmct1;
wire fmct3;
wire fmct4;
wire fmct5;
wire fm_clr;
wire fmc_wr_set;
wire fmc_wr_rs;
wire fma_rd_rq_P, fma_rd_rq_D, fmc_rd0_set;
wire fmct1_D, fmct3_D;
wire mb_pulse_in;
pg fmc_pg0(.clk(clk), .reset(reset), .in(power), .p(fmc_pwr_on));
pg fmc_pg1(.clk(clk), .reset(reset), .in(sw_restart & fmc_stop),
.p(fmc_restart));
pg fmc_pg2(.clk(clk), .reset(reset), .in(fmc_act), .p(fmct0));
pg fmc_pg3(.clk(clk), .reset(reset), .in(fma_rd_rq), .p(fma_rd_rq_P));
pg cmc_pg5(.clk(clk), .reset(reset), .in(wr_rs), .p(fmc_wr_rs));
pa fmc_pa0(.clk(clk), .reset(reset),
.in(fmc_start |
fmct4 & ~fmc_stop),
.p(fmct5));
pa fmc_pa1(.clk(clk), .reset(reset),
.in(fmct0 & fma_rd_rq),
.p(fmct1));
pa fmc_pa2(.clk(clk), .reset(reset),
.in(fma_rd_rq_D),
.p(fmc_rd0_set));
pa fmc_pa3(.clk(clk), .reset(reset),
.in(fmct3),
.p(fm_clr));
pa fmc_pa4(.clk(clk), .reset(reset),
.in(fmct3_D),
.p(fmc_wr_set));
pg fmc_pg5(.clk(clk), .reset(reset),
.in(fmct0 & ~fma_rd_rq & fma_wr_rq |
fmct1_D & fma_wr_rq),
.p(fmct3));
pa fmc_pa6(.clk(clk), .reset(reset),
.in(fmct1_D & ~fma_wr_rq |
fmc_wr_rs),
.p(fmct4));
dly200ns fmc_dly0(.clk(clk), .reset(reset),
.in(fmc_restart | fmc_pwr_on),
.p(fmc_start));
dly50ns fmc_dly1(.clk(clk), .reset(reset),
.in(fma_rd_rq_P),
.p(fma_rd_rq_D));
dly100ns fmc_dly3(.clk(clk), .reset(reset),
.in(fmct1),
.p(fmct1_D));
dly50ns fmc_dly4(.clk(clk), .reset(reset),
.in(fmct3),
.p(fmct3_D));
bd fmc_bd0(.clk(clk), .reset(reset), .in(fmct0), .p(fmc_addr_ack));
bd fmc_bd1(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_rs));
bd fmc_bd2(.clk(clk), .reset(reset), .in(fmct1), .p(fmc_rd_strb));
`ifdef simulation
always @(posedge reset) begin
fmc_act <= 0;
end
`endif
always @(posedge clk) begin
if(fmc_restart | fmc_pwr_on) begin
fmc_act <= 0;
fmc_stop <= 1;
end
if(fmpc_p0_rq | fmpc_p1_rq | fmpc_p2_rq | fmpc_p3_rq)
fmc_act <= 1;
if(fmc_wr_rs)
fmc_rs <= 1;
if(~fma_rd_rq)
fmc_rd0 <= 0;
if(fmc_rd0_set)
fmc_rd0 <= 1;
if(fmc_wr_set)
fmc_wr <= 1;
if(fm_clr)
ff[fma] <= 0;
if(fmc_wr)
ff[fma] <= ff[fma] | mb_in;
if(fmct0) begin
fmc_rs <= 0;
fmc_stop <= sw_single_step;
end
if(fmct4) begin
fmc_act <= 0;
fmc_rd0 <= 0;
end
if(fmct5) begin
fmc_stop <= 0;
fmc_wr <= 0;
end
if(s_write)
ff[s_address[3:0]] <= s_writedata;
end
assign s_readdata = ff[s_address[3:0]];
assign s_waitrequest = 0;
endmodule
|
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module cfg(
// --clock & reset
input usb_clk,
input usb_rst,
input core_clk,
input core_rst,
// -- usb config
input usb_en,
input usb_wr,
input [15:0] usb_data,
input capture_done,
// -- config output
output ext_clk_mode,
output test_mode,
output ext_test_mode,
output sd_lpb_mode,
output falling_mode,
output cons_mode,
output half_mode,
output quarter_mode,
output wireless_mode,
output [23:0] sample_divider,
output reg full_speed,
output trig_en,
output [3:0] trig_stages,
output trig_value_wr,
output trig_mask_wr,
output trig_edge_wr,
output trig_count_wr,
output trig_logic_wr,
output [1:0] trig_mu,
output [15:0] trig_mask,
output [15:0] trig_value,
output [15:0] trig_edge,
output [15:0] trig_count,
output [1:0] trig_logic,
output [31:0] sample_depth,
output reg [31:0] sample_last_cnt,
output reg [31:0] sample_real_start,
output [31:0] trig_set_pos,
output reg [31:0] trig_set_pos_minus1,
output [31:0] after_trig_depth,
output read_start,
output [31:0] sd_saddr,
output sd_fbe
);
// --
// parameters
// --
parameter SYNC_CODE = 8'hFF;
parameter UNSYNC_CODE = 8'h00;
// --
// configure protocol decode
// --
wire usb_cfg_wr;
wire [4:0] usb_cfg_addr;
wire [15:0] usb_cfg_din;
wire usb_cfg_rd;
reg [15:0] usb_cfg_dout;
reg usb_en_reg;
reg usb_wr_reg;
reg [15:0] usb_data_reg;
reg usb_cfg_sync;
wire usb_cfg_sync_nxt;
reg usb_cfg;
wire usb_cfg_nxt;
reg [7:0] usb_cfg_cnt;
wire [7:0] usb_cfg_cnt_nxt;
reg [5:0] usb_addr;
wire [5:0] usb_addr_nxt;
wire cfg_trig_value_wr;
wire cfg_trig_mask_wr;
wire cfg_trig_edge_wr;
wire cfg_trig_count_wr;
wire cfg_trig_logic_wr;
wire [1:0] cfg_trig_mu;
wire [15:0] cfg_trig_mask;
wire [15:0] cfg_trig_value;
wire [15:0] cfg_trig_edge;
wire [15:0] cfg_trig_count;
wire [15:0] cfg_trig_logic;
// -- usb_cfg
always @(posedge usb_clk or posedge usb_rst)
begin
if (usb_rst) begin
usb_en_reg <= `D 1'b0;
usb_wr_reg <= `D 1'b0;
usb_data_reg <= `D 16'b0;
end else begin
usb_en_reg <= `D usb_en;
usb_wr_reg <= `D usb_wr;
usb_data_reg <= `D usb_data;
end
end
assign usb_cfg_sync_nxt = usb_en_reg & usb_wr_reg & (usb_data_reg == 16'hf5a5) ? 1'b1 :
usb_en_reg & usb_wr_reg & (usb_data_reg == 16'hfa5a) ? 1'b0 : usb_cfg_sync;
assign usb_cfg_nxt = usb_cfg_sync & (usb_data_reg[15:14] == 2'b0) & |usb_data_reg & ~usb_cfg ? 1'b1 :
usb_cfg_sync & (usb_cfg_cnt == 8'd1) ? 1'b0 : usb_cfg;
assign usb_cfg_cnt_nxt = (usb_cfg_sync & (usb_data_reg[15:14] == 2'b0) & (usb_cfg_cnt == 8'b0)) ? usb_data_reg[7:0] :
(usb_cfg_sync & (usb_cfg_cnt != 8'b0)) ? usb_cfg_cnt - 1'b1 : usb_cfg_cnt;
assign usb_addr_nxt = (usb_cfg_nxt & ~usb_cfg) ? usb_data_reg[13:8] :
usb_cfg_wr ? usb_addr + 1'b1 : usb_addr;
always @(posedge usb_clk or posedge usb_rst)
begin
if (usb_rst) begin
usb_cfg_sync <= `D 1'b0;
usb_cfg <= `D 1'b0;
usb_cfg_cnt <= `D 8'b0;
usb_addr <= `D 6'b0;
end else begin
usb_cfg_sync <= `D usb_cfg_sync_nxt;
usb_cfg <= `D usb_cfg_nxt;
usb_cfg_cnt <= `D usb_cfg_cnt_nxt;
usb_addr <= `D usb_addr_nxt;
end
end
assign usb_cfg_wr = usb_cfg & usb_en_reg & usb_wr & (usb_addr[5:4] == 2'b0);
assign usb_cfg_addr = usb_addr[4:0];
assign usb_cfg_din = usb_data_reg;
assign usb_cfg_rd = 1'b0;
reg [5:0] cfg_trig_mu_addr;
wire [5:0] cfg_trig_mu_addr_nxt;
assign cfg_trig_mask_wr = usb_cfg & usb_en_reg & usb_wr & (cfg_trig_mu_addr[5:2] == 4'b0100);
assign cfg_trig_value_wr = usb_cfg & usb_en_reg & usb_wr & (cfg_trig_mu_addr[5:2] == 4'b0101);
assign cfg_trig_edge_wr = usb_cfg & usb_en_reg & usb_wr & (cfg_trig_mu_addr[5:2] == 4'b0110);
assign cfg_trig_count_wr = usb_cfg & usb_en_reg & usb_wr & (cfg_trig_mu_addr[5:2] == 4'b0111);
assign cfg_trig_logic_wr = usb_cfg & usb_en_reg & usb_wr & (cfg_trig_mu_addr[5:2] == 4'b1000);
assign cfg_trig_mu_addr_nxt = (usb_cfg_nxt & ~usb_cfg) ? usb_data_reg[13:8] : cfg_trig_mu_addr;
always @(posedge usb_clk)
begin
cfg_trig_mu_addr <= `D cfg_trig_mu_addr_nxt;
end
assign cfg_trig_mu = cfg_trig_mu_addr[1:0];
assign cfg_trig_mask = usb_data_reg;
assign cfg_trig_value = usb_data_reg;
assign cfg_trig_edge = usb_data_reg;
assign cfg_trig_count = usb_data_reg;
assign cfg_trig_logic = usb_data_reg;
wire mask_cfg_empty;
wire [17:0] mask_dout;
wire value_cfg_empty;
wire [17:0] value_dout;
wire edge_cfg_empty;
wire [17:0] edge_dout;
wire count_cfg_empty;
wire [17:0] count_dout;
wire logic_cfg_empty;
wire [17:0] logic_dout;
trig_cfg_fifo mask_cfg(
.wr_clk(usb_clk), // input wr_clk
.wr_rst(usb_rst), // input wr_rst
.rd_clk(core_clk), // input rd_clk
.rd_rst(core_rst), // input rd_rst
.din({cfg_trig_mu, cfg_trig_mask}), // input [17 : 0] din
.wr_en(cfg_trig_mask_wr), // input wr_en
.rd_en(~mask_cfg_empty), // input rd_en
.dout(mask_dout), // output [17 : 0] dout
.full(), // output full
.empty(mask_cfg_empty) // output empty
);
trig_cfg_fifo value_cfg(
.wr_clk(usb_clk), // input wr_clk
.wr_rst(usb_rst), // input wr_rst
.rd_clk(core_clk), // input rd_clk
.rd_rst(core_rst), // input rd_rst
.din({cfg_trig_mu, cfg_trig_value}), // input [17 : 0] din
.wr_en(cfg_trig_value_wr), // input wr_en
.rd_en(~value_cfg_empty), // input rd_en
.dout(value_dout), // output [17 : 0] dout
.full(), // output full
.empty(value_cfg_empty) // output empty
);
trig_cfg_fifo edge_cfg(
.wr_clk(usb_clk), // input wr_clk
.wr_rst(usb_rst), // input wr_rst
.rd_clk(core_clk), // input rd_clk
.rd_rst(core_rst), // input rd_rst
.din({cfg_trig_mu, cfg_trig_edge}), // input [17 : 0] din
.wr_en(cfg_trig_edge_wr), // input wr_en
.rd_en(~edge_cfg_empty), // input rd_en
.dout(edge_dout), // output [17 : 0] dout
.full(), // output full
.empty(edge_cfg_empty) // output empty
);
trig_cfg_fifo count_cfg(
.wr_clk(usb_clk), // input wr_clk
.wr_rst(usb_rst), // input wr_rst
.rd_clk(core_clk), // input rd_clk
.rd_rst(core_rst), // input rd_rst
.din({cfg_trig_mu, cfg_trig_count}), // input [17 : 0] din
.wr_en(cfg_trig_count_wr), // input wr_en
.rd_en(~count_cfg_empty), // input rd_en
.dout(count_dout), // output [17 : 0] dout
.full(), // output full
.empty(count_cfg_empty) // output empty
);
trig_cfg_fifo logic_cfg(
.wr_clk(usb_clk), // input wr_clk
.wr_rst(usb_rst), // input wr_rst
.rd_clk(core_clk), // input rd_clk
.rd_rst(core_rst), // input rd_rst
.din({cfg_trig_mu, cfg_trig_logic}), // input [17 : 0] din
.wr_en(cfg_trig_logic_wr), // input wr_en
.rd_en(~logic_cfg_empty), // input rd_en
.dout(logic_dout), // output [17 : 0] dout
.full(), // output full
.empty(logic_cfg_empty) // output empty
);
assign trig_mask_wr = ~mask_cfg_empty;
assign trig_value_wr = ~value_cfg_empty;
assign trig_edge_wr = ~edge_cfg_empty;
assign trig_count_wr = ~count_cfg_empty;
assign trig_logic_wr = ~logic_cfg_empty;
assign trig_mu = trig_mask_wr ? mask_dout[17:16] :
trig_value_wr ? value_dout[17:16] :
trig_edge_wr ? edge_dout[17:16] :
trig_count_wr ? count_dout[17:16] : logic_dout[17:16];
assign trig_mask = mask_dout[15:0];
assign trig_value = value_dout[15:0];
assign trig_edge = edge_dout[15:0];
assign trig_count = count_dout[15:0];
assign trig_logic = logic_dout[1:0];
// --
// configure registers
// --
reg [15:0] cfg0_reg;
wire [15:0] cfg0_reg_nxt;
reg [15:0] cfg1_reg;
wire [15:0] cfg1_reg_nxt;
reg [15:0] cfg2_reg;
wire [15:0] cfg2_reg_nxt;
reg [15:0] cfg3_reg;
wire [15:0] cfg3_reg_nxt;
reg [15:0] cfg4_reg;
wire [15:0] cfg4_reg_nxt;
reg [15:0] cfg5_reg;
wire [15:0] cfg5_reg_nxt;
reg [15:0] cfg6_reg;
wire [15:0] cfg6_reg_nxt;
reg [15:0] cfg7_reg;
wire [15:0] cfg7_reg_nxt;
reg [15:0] cfg8_reg;
wire [15:0] cfg8_reg_nxt;
reg [15:0] cfg9_reg;
wire [15:0] cfg9_reg_nxt;
reg [15:0] cfg10_reg;
wire [15:0] cfg10_reg_nxt;
reg [15:0] cfg11_reg;
wire [15:0] cfg11_reg_nxt;
reg [15:0] cfg12_reg;
wire [15:0] cfg12_reg_nxt;
reg [15:0] cfg13_reg;
wire [15:0] cfg13_reg_nxt;
// --
// registers output mapping
// --
assign trig_en = cfg0_reg[0];
assign ext_clk_mode = cfg0_reg[1];
assign falling_mode = cfg0_reg[2];
assign adv_mode = cfg0_reg[3];
assign cons_mode = cfg0_reg[4];
assign half_mode = cfg0_reg[5];
assign quarter_mode = cfg0_reg[6];
assign wireless_mode = cfg0_reg[7];
assign sd_lpb_mode = cfg0_reg[13];
assign ext_test_mode = cfg0_reg[14];
assign test_mode = cfg0_reg[15];
wire full_speed_nxt = (sample_divider == 24'd1);
always @(posedge usb_clk)
begin
full_speed <= `D full_speed_nxt;
end
assign sample_divider[15:0] = cfg1_reg;
assign sample_divider[23:16] = cfg2_reg[7:0];
assign sample_depth[15:0] = cfg3_reg;
assign sample_depth[31:16] = cfg4_reg;
always @(posedge usb_clk)
begin
sample_last_cnt <= `D sample_depth - 1'b1;
sample_real_start <= `D (trig_set_pos == 32'b0) ? 32'b0 : sample_depth - trig_set_pos;
trig_set_pos_minus1 <= `D (trig_set_pos == 32'b0) ? 32'b0 : trig_set_pos - 1'b1;
end
assign trig_set_pos[15:0] = half_mode ? {cfg6_reg[0], cfg5_reg[15:1]} :
quarter_mode ? {cfg6_reg[1:0], cfg5_reg[15:2]} : cfg5_reg;
assign trig_set_pos[31:16] = half_mode ? cfg6_reg >> 1 :
quarter_mode ? cfg6_reg >> 2 : cfg6_reg;
assign trig_stages = cfg7_reg[3:0];
assign after_trig_depth[15:0] = cfg10_reg;
assign after_trig_depth[31:16] = cfg11_reg;
assign read_start = cfg12_reg[0];
assign sd_fbe = cfg12_reg[1];
assign sd_saddr[31:16] = cfg13_reg;
assign sd_saddr[15:0] = {cfg12_reg[15:2], 2'b0};
// --
//
// --
wire r00 = usb_cfg_rd & (usb_cfg_addr == 5'd0);
wire r01 = usb_cfg_rd & (usb_cfg_addr == 5'd1);
wire r02 = usb_cfg_rd & (usb_cfg_addr == 5'd2);
wire r03 = usb_cfg_rd & (usb_cfg_addr == 5'd3);
wire r04 = usb_cfg_rd & (usb_cfg_addr == 5'd4);
wire r05 = usb_cfg_rd & (usb_cfg_addr == 5'd5);
wire r06 = usb_cfg_rd & (usb_cfg_addr == 5'd6);
wire r07 = usb_cfg_rd & (usb_cfg_addr == 5'd7);
wire r08 = usb_cfg_rd & (usb_cfg_addr == 5'd8);
wire r09 = usb_cfg_rd & (usb_cfg_addr == 5'd9);
wire r10 = usb_cfg_rd & (usb_cfg_addr == 5'd10);
wire r11 = usb_cfg_rd & (usb_cfg_addr == 5'd11);
wire r12 = usb_cfg_rd & (usb_cfg_addr == 5'd12);
wire r13 = usb_cfg_rd & (usb_cfg_addr == 5'd13);
wire r17 = usb_cfg_rd & (usb_cfg_addr == 5'd17);
wire r18 = usb_cfg_rd & (usb_cfg_addr == 5'd18);
wire r19 = usb_cfg_rd & (usb_cfg_addr == 5'd19);
wire w00 = usb_cfg_wr & (usb_cfg_addr == 5'd0);
wire w01 = usb_cfg_wr & (usb_cfg_addr == 5'd1);
wire w02 = usb_cfg_wr & (usb_cfg_addr == 5'd2);
wire w03 = usb_cfg_wr & (usb_cfg_addr == 5'd3);
wire w04 = usb_cfg_wr & (usb_cfg_addr == 5'd4);
wire w05 = usb_cfg_wr & (usb_cfg_addr == 5'd5);
wire w06 = usb_cfg_wr & (usb_cfg_addr == 5'd6);
wire w07 = usb_cfg_wr & (usb_cfg_addr == 5'd7);
wire w08 = usb_cfg_wr & (usb_cfg_addr == 5'd8);
wire w09 = usb_cfg_wr & (usb_cfg_addr == 5'd9);
wire w10 = usb_cfg_wr & (usb_cfg_addr == 5'd10);
wire w11 = usb_cfg_wr & (usb_cfg_addr == 5'd11);
wire w12 = usb_cfg_wr & (usb_cfg_addr == 5'd12);
wire w13 = usb_cfg_wr & (usb_cfg_addr == 5'd13);
// --
// config write
// --
assign cfg0_reg_nxt = w00 ? usb_cfg_din : cfg0_reg;
assign cfg1_reg_nxt = w01 ? usb_cfg_din : cfg1_reg;
assign cfg2_reg_nxt = w02 ? usb_cfg_din : cfg2_reg;
assign cfg3_reg_nxt = w03 ? usb_cfg_din : cfg3_reg;
assign cfg4_reg_nxt = w04 ? usb_cfg_din : cfg4_reg;
assign cfg5_reg_nxt = w05 ? usb_cfg_din : cfg5_reg;
assign cfg6_reg_nxt = w06 ? usb_cfg_din : cfg6_reg;
assign cfg7_reg_nxt = w07 ? usb_cfg_din : cfg7_reg;
assign cfg8_reg_nxt = w08 ? usb_cfg_din : cfg8_reg;
assign cfg9_reg_nxt = w09 ? usb_cfg_din : cfg9_reg;
assign cfg10_reg_nxt = w10 ? usb_cfg_din : cfg10_reg;
assign cfg11_reg_nxt = w11 ? usb_cfg_din : cfg11_reg;
assign cfg12_reg_nxt[15] = cfg12_reg[15] ? 1'b0 :
w12 ? usb_cfg_din[15] : cfg12_reg[15];
assign cfg12_reg_nxt[14:0] = w12 ? usb_cfg_din[14:0] : cfg12_reg[14:0];
assign cfg13_reg_nxt = w13 ? usb_cfg_din : cfg13_reg;
always @(posedge usb_clk or posedge usb_rst)
begin
if (usb_rst)
begin
cfg0_reg <= `D 16'b0;
cfg1_reg <= `D 16'b1;
cfg2_reg <= `D 16'b0;
cfg3_reg <= `D 16'b0;
cfg4_reg <= `D 16'b0;
cfg5_reg <= `D 16'b0;
cfg6_reg <= `D 16'b0;
cfg7_reg <= `D 16'b0;
cfg8_reg <= `D 16'b0;
cfg9_reg <= `D 16'b0;
cfg10_reg <= `D 16'b0;
cfg11_reg <= `D 16'b0;
cfg12_reg <= `D 16'b0;
cfg13_reg <= `D 16'b0;
end
else
begin
cfg0_reg <= `D cfg0_reg_nxt;
cfg1_reg <= `D cfg1_reg_nxt;
cfg2_reg <= `D cfg2_reg_nxt;
cfg3_reg <= `D cfg3_reg_nxt;
cfg4_reg <= `D cfg4_reg_nxt;
cfg5_reg <= `D cfg5_reg_nxt;
cfg6_reg <= `D cfg6_reg_nxt;
cfg7_reg <= `D cfg7_reg_nxt;
cfg8_reg <= `D cfg8_reg_nxt;
cfg9_reg <= `D cfg9_reg_nxt;
cfg10_reg <= `D cfg10_reg_nxt;
cfg11_reg <= `D cfg11_reg_nxt;
cfg12_reg <= `D cfg12_reg_nxt;
cfg13_reg <= `D cfg13_reg_nxt;
end
end
// --
// -- config read
// --
//reg [15:0] usb_cfg_dout;
wire [15:0] usb_cfg_dout_nxt;
assign usb_cfg_dout_nxt = r00 ? cfg0_reg :
r01 ? cfg1_reg :
r02 ? cfg2_reg :
r03 ? cfg3_reg :
r04 ? cfg4_reg :
r05 ? cfg5_reg :
r06 ? cfg6_reg :
r07 ? cfg7_reg :
r08 ? cfg8_reg :
r09 ? cfg9_reg :
r10 ? cfg10_reg :
r11 ? cfg11_reg :
r12 ? cfg12_reg :
r13 ? cfg13_reg : 16'b0;
always @(posedge usb_clk or posedge usb_rst)
begin
if (usb_rst)
usb_cfg_dout <= `D 16'b0;
else
usb_cfg_dout <= `D usb_cfg_dout_nxt;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o211ai (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Local signals
wire or0_out ;
wire nand0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y, C1, or0_out, B1);
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O211AI_FUNCTIONAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 00:30:32 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_0/zynq_design_1_auto_pc_0_sim_netlist.v
// Design : zynq_design_1_auto_pc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zynq_design_1_auto_pc_0,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zynq_design_1_auto_pc_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [11:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[11:0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[11:0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[11:0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "zynq" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_axi_protocol_converter" *)
(* P_AXI3 = "1" *) (* P_AXI4 = "0" *) (* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *) (* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *) (* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [11:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [11:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [11:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [11:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [11:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [11:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[11] = \<const0> ;
assign m_axi_arid[10] = \<const0> ;
assign m_axi_arid[9] = \<const0> ;
assign m_axi_arid[8] = \<const0> ;
assign m_axi_arid[7] = \<const0> ;
assign m_axi_arid[6] = \<const0> ;
assign m_axi_arid[5] = \<const0> ;
assign m_axi_arid[4] = \<const0> ;
assign m_axi_arid[3] = \<const0> ;
assign m_axi_arid[2] = \<const0> ;
assign m_axi_arid[1] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[11] = \<const0> ;
assign m_axi_awid[10] = \<const0> ;
assign m_axi_awid[9] = \<const0> ;
assign m_axi_awid[8] = \<const0> ;
assign m_axi_awid[7] = \<const0> ;
assign m_axi_awid[6] = \<const0> ;
assign m_axi_awid[5] = \<const0> ;
assign m_axi_awid[4] = \<const0> ;
assign m_axi_awid[3] = \<const0> ;
assign m_axi_awid[2] = \<const0> ;
assign m_axi_awid[1] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] ({s_axi_bid,s_axi_bresp}),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
s_axi_awvalid,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_axi_bvalid,
m_axi_rvalid,
s_axi_bready,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input s_axi_awvalid;
input aclk;
input [33:0]in;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_bready;
input s_axi_arvalid;
input aresetn;
wire [11:4]C;
wire [22:0]Q;
wire \RD.ar_channel_0_n_10 ;
wire \RD.ar_channel_0_n_11 ;
wire \RD.ar_channel_0_n_47 ;
wire \RD.ar_channel_0_n_48 ;
wire \RD.ar_channel_0_n_49 ;
wire \RD.ar_channel_0_n_50 ;
wire \RD.ar_channel_0_n_8 ;
wire \RD.ar_channel_0_n_9 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_2 ;
wire SI_REG_n_134;
wire SI_REG_n_135;
wire SI_REG_n_136;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_149;
wire SI_REG_n_150;
wire SI_REG_n_151;
wire SI_REG_n_158;
wire SI_REG_n_162;
wire SI_REG_n_163;
wire SI_REG_n_164;
wire SI_REG_n_165;
wire SI_REG_n_166;
wire SI_REG_n_167;
wire SI_REG_n_171;
wire SI_REG_n_175;
wire SI_REG_n_176;
wire SI_REG_n_177;
wire SI_REG_n_178;
wire SI_REG_n_179;
wire SI_REG_n_180;
wire SI_REG_n_181;
wire SI_REG_n_182;
wire SI_REG_n_183;
wire SI_REG_n_184;
wire SI_REG_n_185;
wire SI_REG_n_186;
wire SI_REG_n_187;
wire SI_REG_n_188;
wire SI_REG_n_189;
wire SI_REG_n_190;
wire SI_REG_n_191;
wire SI_REG_n_192;
wire SI_REG_n_193;
wire SI_REG_n_194;
wire SI_REG_n_195;
wire SI_REG_n_196;
wire SI_REG_n_20;
wire SI_REG_n_21;
wire SI_REG_n_22;
wire SI_REG_n_23;
wire SI_REG_n_29;
wire SI_REG_n_79;
wire SI_REG_n_80;
wire SI_REG_n_81;
wire SI_REG_n_82;
wire SI_REG_n_88;
wire \WR.aw_channel_0_n_10 ;
wire \WR.aw_channel_0_n_54 ;
wire \WR.aw_channel_0_n_55 ;
wire \WR.aw_channel_0_n_56 ;
wire \WR.aw_channel_0_n_57 ;
wire \WR.aw_channel_0_n_7 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire [1:0]\ar_cmd_fsm_0/state ;
wire \ar_pipe/p_1_in ;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire \aw_pipe/p_1_in ;
wire [11:0]b_awid;
wire [7:0]b_awlen;
wire b_push;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ;
wire [3:0]\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ;
wire \cmd_translator_0/incr_cmd_0/sel_first ;
wire \cmd_translator_0/incr_cmd_0/sel_first_4 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r ;
wire [3:0]\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire [11:0]s_arid;
wire [11:0]s_arid_r;
wire [11:0]s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire [11:0]si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire [11:0]si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
wire [3:0]wrap_cnt;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel \RD.ar_channel_0
(.CO(SI_REG_n_147),
.D({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.E(\ar_pipe/p_1_in ),
.O({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.Q(\ar_cmd_fsm_0/state ),
.S({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\cnt_read_reg[2]_rep__0 (\RD.r_channel_0_n_0 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_9 ),
.\m_payload_i_reg[0]_0 (\RD.ar_channel_0_n_10 ),
.\m_payload_i_reg[11] ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\m_payload_i_reg[38] (SI_REG_n_196),
.\m_payload_i_reg[3] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\m_payload_i_reg[44] (SI_REG_n_171),
.\m_payload_i_reg[46] (SI_REG_n_177),
.\m_payload_i_reg[47] (SI_REG_n_175),
.\m_payload_i_reg[51] (SI_REG_n_176),
.\m_payload_i_reg[64] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,si_rs_araddr}),
.\m_payload_i_reg[6] (SI_REG_n_187),
.\m_payload_i_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\r_arid_r_reg[11] (s_arid_r),
.r_push_r_reg(\RD.ar_channel_0_n_11 ),
.r_rlast(r_rlast),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_8 ),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}),
.\wrap_second_len_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel \RD.r_channel_0
(.D(s_arid_r),
.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg(\RD.r_channel_0_n_2 ),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_ready_i_reg(SI_REG_n_178),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_11 ));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice SI_REG
(.CO(SI_REG_n_134),
.D({wrap_cnt[3:2],wrap_cnt[0]}),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr_reg(\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_incr_reg[11] (C),
.\axaddr_incr_reg[11]_0 ({SI_REG_n_143,SI_REG_n_144,SI_REG_n_145,SI_REG_n_146}),
.\axaddr_incr_reg[3] ({SI_REG_n_148,SI_REG_n_149,SI_REG_n_150,SI_REG_n_151}),
.\axaddr_incr_reg[3]_0 (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg ),
.\axaddr_incr_reg[7] ({SI_REG_n_139,SI_REG_n_140,SI_REG_n_141,SI_REG_n_142}),
.\axaddr_incr_reg[7]_0 (SI_REG_n_147),
.axaddr_offset(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.axaddr_offset_0(\cmd_translator_0/wrap_cmd_0/axaddr_offset [2:0]),
.\axaddr_offset_r_reg[3] (SI_REG_n_179),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_187),
.\axaddr_offset_r_reg[3]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_2 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.\axaddr_offset_r_reg[3]_3 (\cmd_translator_0/wrap_cmd_0/axaddr_offset [3]),
.\axaddr_offset_r_reg[3]_4 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[3] (SI_REG_n_162),
.\axlen_cnt_reg[3]_0 (SI_REG_n_175),
.b_push(b_push),
.\cnt_read_reg[3]_rep__0 (SI_REG_n_178),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__0 (\RD.r_channel_0_n_2 ),
.\m_axi_araddr[10] (SI_REG_n_196),
.\m_axi_awaddr[10] (SI_REG_n_195),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_47 ,\RD.ar_channel_0_n_48 ,\RD.ar_channel_0_n_49 ,\RD.ar_channel_0_n_50 }),
.m_valid_i_reg(\ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_163),
.next_pending_r_reg_0(SI_REG_n_164),
.next_pending_r_reg_1(SI_REG_n_176),
.next_pending_r_reg_2(SI_REG_n_177),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[11] ({s_arid,SI_REG_n_79,SI_REG_n_80,SI_REG_n_81,SI_REG_n_82,si_rs_arlen,si_rs_arburst,SI_REG_n_88,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.sel_first_2(\cmd_translator_0/incr_cmd_0/sel_first ),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\WR.aw_channel_0_n_10 ),
.\state_reg[0]_rep_0 (\RD.ar_channel_0_n_9 ),
.\state_reg[1] (\ar_cmd_fsm_0/state ),
.\state_reg[1]_0 (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_7 ),
.\state_reg[1]_rep_1 (\RD.ar_channel_0_n_8 ),
.\state_reg[1]_rep_2 (\RD.ar_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_188,SI_REG_n_189,SI_REG_n_190,SI_REG_n_191,SI_REG_n_192,SI_REG_n_193,SI_REG_n_194}),
.\wrap_cnt_r_reg[3] (SI_REG_n_158),
.\wrap_cnt_r_reg[3]_0 ({SI_REG_n_165,SI_REG_n_166,SI_REG_n_167}),
.\wrap_cnt_r_reg[3]_1 (SI_REG_n_171),
.wrap_second_len(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.wrap_second_len_1(\cmd_translator_0/wrap_cmd_0/wrap_second_len [1]),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len [0]}),
.\wrap_second_len_r_reg[3]_1 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_2 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r [0]}));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel \WR.aw_channel_0
(.CO(SI_REG_n_134),
.D(\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [1]),
.E(\aw_pipe/p_1_in ),
.O({SI_REG_n_135,SI_REG_n_136,SI_REG_n_137,SI_REG_n_138}),
.Q(\aw_cmd_fsm_0/state ),
.S({\WR.aw_channel_0_n_54 ,\WR.aw_channel_0_n_55 ,\WR.aw_channel_0_n_56 ,\WR.aw_channel_0_n_57 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[3] (\cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5 ),
.\axaddr_offset_r_reg[3] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [3]),
.\axaddr_offset_r_reg[3]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[11] (C),
.\m_payload_i_reg[35] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 [2:0]),
.\m_payload_i_reg[38] (SI_REG_n_195),
.\m_payload_i_reg[44] (SI_REG_n_158),
.\m_payload_i_reg[46] (SI_REG_n_164),
.\m_payload_i_reg[47] (SI_REG_n_162),
.\m_payload_i_reg[48] (SI_REG_n_163),
.\m_payload_i_reg[64] ({s_awid,SI_REG_n_20,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,si_rs_awlen,si_rs_awburst,SI_REG_n_29,si_rs_awsize,si_rs_awaddr}),
.\m_payload_i_reg[6] (SI_REG_n_179),
.\m_payload_i_reg[6]_0 ({SI_REG_n_180,SI_REG_n_181,SI_REG_n_182,SI_REG_n_183,SI_REG_n_184,SI_REG_n_185,SI_REG_n_186}),
.sel_first(\cmd_translator_0/incr_cmd_0/sel_first_4 ),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_rep_0 (\WR.aw_channel_0_n_10 ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_7 ),
.\wrap_second_len_r_reg[3] ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3 [0]}),
.\wrap_second_len_r_reg[3]_0 ({\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [3:2],\cmd_translator_0/wrap_cmd_0/wrap_second_len_1 [0]}),
.\wrap_second_len_r_reg[3]_1 ({wrap_cnt[3:2],wrap_cnt[0]}));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep__0 (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep__1 (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_ar_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
wrap_second_len,
\wrap_boundary_axaddr_r_reg[11] ,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
r_push_r_reg,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
m_axi_arvalid,
r_rlast,
E,
m_axi_araddr,
\r_arid_r_reg[11] ,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_arvalid,
\m_payload_i_reg[44] ,
\m_payload_i_reg[64] ,
m_axi_arready,
CO,
\cnt_read_reg[2]_rep__0 ,
axaddr_offset,
\m_payload_i_reg[46] ,
\m_payload_i_reg[51] ,
areset_d1,
\m_payload_i_reg[6] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
D,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output [0:0]wrap_second_len;
output \wrap_boundary_axaddr_r_reg[11] ;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output r_push_r_reg;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output m_axi_arvalid;
output r_rlast;
output [0:0]E;
output [11:0]m_axi_araddr;
output [11:0]\r_arid_r_reg[11] ;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_arvalid;
input \m_payload_i_reg[44] ;
input [35:0]\m_payload_i_reg[64] ;
input m_axi_arready;
input [0:0]CO;
input \cnt_read_reg[2]_rep__0 ;
input [2:0]axaddr_offset;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[51] ;
input areset_d1;
input \m_payload_i_reg[6] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]D;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_12;
wire ar_cmd_fsm_0_n_15;
wire ar_cmd_fsm_0_n_16;
wire ar_cmd_fsm_0_n_17;
wire ar_cmd_fsm_0_n_20;
wire ar_cmd_fsm_0_n_21;
wire ar_cmd_fsm_0_n_3;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [3:0]\axaddr_incr_reg[3] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_8;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire [11:0]\r_arid_r_reg[11] ;
wire r_push_r_reg;
wire r_rlast;
wire sel_first;
wire sel_first_i;
wire si_rs_arvalid;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D(ar_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (ar_cmd_fsm_0_n_17),
.axaddr_offset(axaddr_offset),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[11] (ar_cmd_fsm_0_n_16),
.\axlen_cnt_reg[1] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[1]_0 ({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.\axlen_cnt_reg[1]_1 ({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.\axlen_cnt_reg[4] (cmd_translator_0_n_11),
.\cnt_read_reg[2]_rep__0 (\cnt_read_reg[2]_rep__0 ),
.incr_next_pending(incr_next_pending),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0]_0 ),
.\m_payload_i_reg[0]_0 (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_1 (E),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[64] [19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[51] (\m_payload_i_reg[51] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next_pending_r_reg(cmd_translator_0_n_0),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq0_reg(ar_cmd_fsm_0_n_12),
.s_axburst_eq1_reg(ar_cmd_fsm_0_n_15),
.s_axburst_eq1_reg_0(cmd_translator_0_n_13),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_20),
.sel_first_reg_0(ar_cmd_fsm_0_n_21),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.sel_first_reg_3(cmd_translator_0_n_8),
.si_rs_arvalid(si_rs_arvalid),
.wrap_next_pending(wrap_next_pending),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[1] (\wrap_cmd_0/wrap_second_len_r ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 cmd_translator_0
(.CO(CO),
.D({ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,axaddr_offset}),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (ar_cmd_fsm_0_n_12),
.\m_payload_i_reg[39]_0 (ar_cmd_fsm_0_n_15),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] (\m_payload_i_reg[64] [23:0]),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(ar_cmd_fsm_0_n_16),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_11),
.r_rlast(r_rlast),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(cmd_translator_0_n_8),
.sel_first_reg_2(ar_cmd_fsm_0_n_17),
.sel_first_reg_3(ar_cmd_fsm_0_n_20),
.sel_first_reg_4(ar_cmd_fsm_0_n_21),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0] (ar_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_13),
.\state_reg[0]_rep_0 (\m_payload_i_reg[0] ),
.\state_reg[1] (Q),
.\state_reg[1]_rep (\m_payload_i_reg[0]_0 ),
.\state_reg[1]_rep_0 (r_push_r_reg),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({D[2:1],wrap_second_len,D[0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_0 [2:1],ar_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_0 [0]}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(\r_arid_r_reg[11] [0]),
.R(1'b0));
FDRE \s_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(\r_arid_r_reg[11] [10]),
.R(1'b0));
FDRE \s_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(\r_arid_r_reg[11] [11]),
.R(1'b0));
FDRE \s_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(\r_arid_r_reg[11] [1]),
.R(1'b0));
FDRE \s_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(\r_arid_r_reg[11] [2]),
.R(1'b0));
FDRE \s_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(\r_arid_r_reg[11] [3]),
.R(1'b0));
FDRE \s_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(\r_arid_r_reg[11] [4]),
.R(1'b0));
FDRE \s_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(\r_arid_r_reg[11] [5]),
.R(1'b0));
FDRE \s_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(\r_arid_r_reg[11] [6]),
.R(1'b0));
FDRE \s_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(\r_arid_r_reg[11] [7]),
.R(1'b0));
FDRE \s_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(\r_arid_r_reg[11] [8]),
.R(1'b0));
FDRE \s_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(\r_arid_r_reg[11] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_aw_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel
(\axaddr_incr_reg[3] ,
sel_first,
Q,
\wrap_boundary_axaddr_r_reg[11] ,
D,
\state_reg[1]_rep ,
\state_reg[1]_rep_0 ,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
b_push,
\axaddr_offset_r_reg[3]_0 ,
E,
m_axi_awvalid,
m_axi_awaddr,
in,
S,
aclk,
O,
\m_payload_i_reg[47] ,
si_rs_awvalid,
\m_payload_i_reg[64] ,
\m_payload_i_reg[44] ,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
CO,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
areset_d1,
\m_payload_i_reg[46] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6]_0 );
output [3:0]\axaddr_incr_reg[3] ;
output sel_first;
output [1:0]Q;
output \wrap_boundary_axaddr_r_reg[11] ;
output [0:0]D;
output \state_reg[1]_rep ;
output \state_reg[1]_rep_0 ;
output [2:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_offset_r_reg[3] ;
output b_push;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [0:0]E;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [19:0]in;
output [3:0]S;
input aclk;
input [3:0]O;
input \m_payload_i_reg[47] ;
input si_rs_awvalid;
input [35:0]\m_payload_i_reg[64] ;
input \m_payload_i_reg[44] ;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [0:0]CO;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input areset_d1;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[6] ;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_0;
wire aw_cmd_fsm_0_n_13;
wire aw_cmd_fsm_0_n_17;
wire aw_cmd_fsm_0_n_20;
wire aw_cmd_fsm_0_n_21;
wire aw_cmd_fsm_0_n_24;
wire aw_cmd_fsm_0_n_25;
wire aw_cmd_fsm_0_n_3;
wire [3:0]\axaddr_incr_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_12;
wire cmd_translator_0_n_13;
wire cmd_translator_0_n_14;
wire cmd_translator_0_n_15;
wire cmd_translator_0_n_16;
wire cmd_translator_0_n_17;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_9;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire [7:0]\m_payload_i_reg[11] ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire [35:0]\m_payload_i_reg[64] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire next;
wire [5:0]p_1_in;
wire sel_first;
wire sel_first__0;
wire sel_first_i;
wire si_rs_awvalid;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [1:1]\wrap_cmd_0/wrap_second_len_r ;
wire wrap_next_pending;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D(aw_cmd_fsm_0_n_3),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[11] (aw_cmd_fsm_0_n_21),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_0 [3]),
.\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_20),
.\axlen_cnt_reg[2] (cmd_translator_0_n_16),
.\axlen_cnt_reg[3] (cmd_translator_0_n_15),
.\axlen_cnt_reg[3]_0 (cmd_translator_0_n_17),
.\axlen_cnt_reg[4] (aw_cmd_fsm_0_n_0),
.\axlen_cnt_reg[4]_0 (cmd_translator_0_n_13),
.\axlen_cnt_reg[5] ({p_1_in[5:4],p_1_in[1:0]}),
.\axlen_cnt_reg[5]_0 ({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.\cnt_read_reg[0]_rep__0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1 (\cnt_read_reg[1]_rep__1 ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (b_push),
.\m_payload_i_reg[0]_0 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[44] (\m_payload_i_reg[44] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[49] ({\m_payload_i_reg[64] [21:19],\m_payload_i_reg[64] [17:15]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_13),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_17),
.s_axburst_eq1_reg_0(cmd_translator_0_n_14),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_24),
.sel_first_reg_0(aw_cmd_fsm_0_n_25),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(sel_first),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[1]_rep_0 (\state_reg[1]_rep ),
.\state_reg[1]_rep_1 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[1] (D),
.\wrap_second_len_r_reg[1]_0 (\wrap_cmd_0/wrap_second_len_r ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator cmd_translator_0
(.CO(CO),
.D({p_1_in[5:4],p_1_in[1:0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_9,cmd_translator_0_n_10,cmd_translator_0_n_11,cmd_translator_0_n_12}),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11] (sel_first),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 ({\axaddr_offset_r_reg[3] ,\m_payload_i_reg[35] }),
.\axlen_cnt_reg[4] (cmd_translator_0_n_17),
.\axlen_cnt_reg[7] (cmd_translator_0_n_13),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_13),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_17),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[64] [23:22],\m_payload_i_reg[64] [19:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.m_valid_i_reg(aw_cmd_fsm_0_n_20),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_15),
.next_pending_r_reg_2(cmd_translator_0_n_16),
.sel_first__0(sel_first__0),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_21),
.sel_first_reg_2(aw_cmd_fsm_0_n_24),
.sel_first_reg_3(aw_cmd_fsm_0_n_25),
.\state_reg[0] (aw_cmd_fsm_0_n_0),
.\state_reg[0]_rep (b_push),
.\state_reg[1] (Q),
.\state_reg[1]_rep (cmd_translator_0_n_14),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] ({\wrap_second_len_r_reg[3] [2:1],\wrap_cmd_0/wrap_second_len_r ,\wrap_second_len_r_reg[3] [0]}),
.\wrap_second_len_r_reg[3]_0 ({\wrap_second_len_r_reg[3]_0 [2:1],D,\wrap_second_len_r_reg[3]_0 [0]}),
.\wrap_second_len_r_reg[3]_1 ({\wrap_second_len_r_reg[3]_1 [2:1],aw_cmd_fsm_0_n_3,\wrap_second_len_r_reg[3]_1 [0]}));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [34]),
.Q(in[18]),
.R(1'b0));
FDRE \s_awid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [35]),
.Q(in[19]),
.R(1'b0));
FDRE \s_awid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [25]),
.Q(in[9]),
.R(1'b0));
FDRE \s_awid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [26]),
.Q(in[10]),
.R(1'b0));
FDRE \s_awid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [27]),
.Q(in[11]),
.R(1'b0));
FDRE \s_awid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [28]),
.Q(in[12]),
.R(1'b0));
FDRE \s_awid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [29]),
.Q(in[13]),
.R(1'b0));
FDRE \s_awid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [30]),
.Q(in[14]),
.R(1'b0));
FDRE \s_awid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [31]),
.Q(in[15]),
.R(1'b0));
FDRE \s_awid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [32]),
.Q(in[16]),
.R(1'b0));
FDRE \s_awid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [33]),
.Q(in[17]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [19]),
.Q(in[3]),
.R(1'b0));
FDRE \s_awlen_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awlen_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awlen_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awlen_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[64] [23]),
.Q(in[7]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_b_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep__0 ,
\cnt_read_reg[1]_rep__1 ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bvalid,
in,
m_axi_bresp);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep__0 ;
output \cnt_read_reg[1]_rep__1 ;
output m_axi_bready;
output [11:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input m_axi_bvalid;
input [19:0]in;
input [1:0]m_axi_bresp;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_2;
wire bid_fifo_0_n_3;
wire bid_fifo_0_n_6;
wire \bresp_cnt[7]_i_3_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire [19:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [11:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bvalid_i_reg(bid_fifo_0_n_6),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_0 (bid_fifo_0_n_3),
.\cnt_read_reg[0]_rep__0_0 (\cnt_read_reg[0]_rep__0 ),
.\cnt_read_reg[1]_rep__1_0 (\cnt_read_reg[1]_rep__1 ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_3
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_3_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_2),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.\bresp_cnt_reg[3] (bid_fifo_0_n_3),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.sel(bresp_push),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_6),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT6 #(
.INIT(64'h00000000EACEAAAA))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(m_axi_bresp[0]),
.I2(m_axi_bresp[1]),
.I3(\s_bresp_acc_reg_n_0_[1] ),
.I4(mhandshake),
.I5(s_bresp_acc0),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'h00EC))
\s_bresp_acc[1]_i_1
(.I0(m_axi_bresp[1]),
.I1(\s_bresp_acc_reg_n_0_[1] ),
.I2(mhandshake),
.I3(s_bresp_acc0),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_cmd_translator" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first__0,
Q,
\axlen_cnt_reg[7] ,
\state_reg[1]_rep ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\axlen_cnt_reg[4] ,
m_axi_awaddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
O,
sel_first_reg_2,
sel_first_reg_3,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
CO,
D,
next,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first__0;
output [3:0]Q;
output \axlen_cnt_reg[7] ;
output \state_reg[1]_rep ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \axlen_cnt_reg[4] ;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input [3:0]O;
input sel_first_reg_2;
input sel_first_reg_3;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [21:0]\m_payload_i_reg[51] ;
input [0:0]CO;
input [3:0]D;
input next;
input [7:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[7] ;
wire incr_cmd_0_n_21;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire \m_payload_i_reg[47] ;
wire [21:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11]_0 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.\axlen_cnt_reg[4]_0 (\axlen_cnt_reg[4] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7] ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[1] (incr_cmd_0_n_21),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [21:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_2),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[1]_rep ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd wrap_cmd_0
(.E(E),
.aclk(aclk),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3:2],\axaddr_incr_reg[3] [0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_2),
.sel_first_reg_0(sel_first__0),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_21),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_cmd_translator" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
(next_pending_r_reg,
wrap_next_pending,
sel_first_reg_0,
\axaddr_incr_reg[3] ,
\axaddr_incr_reg[11] ,
sel_first_reg_1,
Q,
next_pending_r_reg_0,
r_rlast,
\state_reg[0]_rep ,
m_axi_araddr,
\axaddr_offset_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
S,
incr_next_pending,
aclk,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_2,
O,
sel_first_reg_3,
sel_first_reg_4,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
\state_reg[0]_rep_0 ,
si_rs_arvalid,
\state_reg[1]_rep ,
CO,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[38] ,
m_valid_i_reg,
D,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg;
output wrap_next_pending;
output sel_first_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output \axaddr_incr_reg[11] ;
output sel_first_reg_1;
output [1:0]Q;
output next_pending_r_reg_0;
output r_rlast;
output \state_reg[0]_rep ;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_2;
input [3:0]O;
input sel_first_reg_3;
input sel_first_reg_4;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [23:0]\m_payload_i_reg[51] ;
input \state_reg[0]_rep_0 ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input [0:0]CO;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input \m_payload_i_reg[38] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [3:0]\axaddr_offset_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire [11:4]axaddr_incr_reg;
wire [3:0]\axaddr_incr_reg[3] ;
wire axaddr_incr_reg_11__s_net_1;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_17;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire [23:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
assign \axaddr_incr_reg[11] = axaddr_incr_reg_11__s_net_1;
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 incr_cmd_0
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[11]_0 ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[11]_1 (axaddr_incr_reg_11__s_net_1),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[2] (incr_cmd_0_n_17),
.\m_axi_araddr[5] (incr_cmd_0_n_16),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[11] (\m_payload_i_reg[11] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [23:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [5],\m_payload_i_reg[51] [3:0]}),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.next_pending_r_reg_1(next_pending_r_reg_0),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_3),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 wrap_cmd_0
(.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({axaddr_incr_reg[11:6],axaddr_incr_reg[4]}),
.\axaddr_incr_reg[3] ({\axaddr_incr_reg[3] [3],\axaddr_incr_reg[3] [1:0]}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[38] (\m_payload_i_reg[38] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_4),
.sel_first_reg_2(incr_cmd_0_n_16),
.sel_first_reg_3(incr_cmd_0_n_17),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_incr_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
axaddr_incr_reg,
\axaddr_incr_reg[11]_0 ,
Q,
\axlen_cnt_reg[7]_0 ,
next_pending_r_reg_1,
\axlen_cnt_reg[4]_0 ,
\m_axi_awaddr[1] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
\state_reg[0]_rep );
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [7:0]axaddr_incr_reg;
output \axaddr_incr_reg[11]_0 ;
output [3:0]Q;
output \axlen_cnt_reg[7]_0 ;
output next_pending_r_reg_1;
output \axlen_cnt_reg[4]_0 ;
output \m_axi_awaddr[1] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [9:0]\m_payload_i_reg[51] ;
input [7:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [1:0]\state_reg[1] ;
input \state_reg[0]_rep ;
wire [0:0]CO;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2_n_0 ;
wire \axaddr_incr[4]_i_3_n_0 ;
wire \axaddr_incr[4]_i_4_n_0 ;
wire \axaddr_incr[4]_i_5_n_0 ;
wire \axaddr_incr[8]_i_2_n_0 ;
wire \axaddr_incr[8]_i_3_n_0 ;
wire \axaddr_incr[8]_i_4_n_0 ;
wire \axaddr_incr[8]_i_5_n_0 ;
wire [7:0]axaddr_incr_reg;
wire \axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1_n_0 ;
wire \axaddr_incr_reg[4]_i_1_n_1 ;
wire \axaddr_incr_reg[4]_i_1_n_2 ;
wire \axaddr_incr_reg[4]_i_1_n_3 ;
wire \axaddr_incr_reg[4]_i_1_n_4 ;
wire \axaddr_incr_reg[4]_i_1_n_5 ;
wire \axaddr_incr_reg[4]_i_1_n_6 ;
wire \axaddr_incr_reg[4]_i_1_n_7 ;
wire \axaddr_incr_reg[8]_i_1_n_1 ;
wire \axaddr_incr_reg[8]_i_1_n_2 ;
wire \axaddr_incr_reg[8]_i_1_n_3 ;
wire \axaddr_incr_reg[8]_i_1_n_4 ;
wire \axaddr_incr_reg[8]_i_1_n_5 ;
wire \axaddr_incr_reg[8]_i_1_n_6 ;
wire \axaddr_incr_reg[8]_i_1_n_7 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt[7]_i_4_n_0 ;
wire \axlen_cnt_reg[4]_0 ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[1] ;
wire [7:0]\m_payload_i_reg[11] ;
wire \m_payload_i_reg[47] ;
wire [9:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire [7:2]p_1_in;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'h559AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[3]));
LUT6 #(
.INIT(64'h0000AAAA559AAAAA))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[2]));
LUT6 #(
.INIT(64'h00000000559AAAAA))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [4]),
.I5(\m_payload_i_reg[51] [5]),
.O(S[1]));
LUT6 #(
.INIT(64'h000000000000559A))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(\state_reg[0]_rep ),
.I4(\m_payload_i_reg[51] [5]),
.I5(\m_payload_i_reg[51] [4]),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[3]),
.O(\axaddr_incr[4]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[2]),
.O(\axaddr_incr[4]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[1]),
.O(\axaddr_incr[4]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[0]),
.O(\axaddr_incr[4]_i_5_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2
(.I0(\m_payload_i_reg[11] [7]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[7]),
.O(\axaddr_incr[8]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3
(.I0(\m_payload_i_reg[11] [6]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[6]),
.O(\axaddr_incr[8]_i_3_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4
(.I0(\m_payload_i_reg[11] [5]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[5]),
.O(\axaddr_incr[8]_i_4_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5
(.I0(\m_payload_i_reg[11] [4]),
.I1(\axaddr_incr_reg[11]_0 ),
.I2(axaddr_incr_reg[4]),
.O(\axaddr_incr[8]_i_5_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_5 ),
.Q(axaddr_incr_reg[6]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_4 ),
.Q(axaddr_incr_reg[7]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_7 ),
.Q(axaddr_incr_reg[0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1_n_0 ,\axaddr_incr_reg[4]_i_1_n_1 ,\axaddr_incr_reg[4]_i_1_n_2 ,\axaddr_incr_reg[4]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1_n_4 ,\axaddr_incr_reg[4]_i_1_n_5 ,\axaddr_incr_reg[4]_i_1_n_6 ,\axaddr_incr_reg[4]_i_1_n_7 }),
.S({\axaddr_incr[4]_i_2_n_0 ,\axaddr_incr[4]_i_3_n_0 ,\axaddr_incr[4]_i_4_n_0 ,\axaddr_incr[4]_i_5_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_6 ),
.Q(axaddr_incr_reg[1]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_5 ),
.Q(axaddr_incr_reg[2]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1_n_4 ),
.Q(axaddr_incr_reg[3]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_7 ),
.Q(axaddr_incr_reg[4]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1
(.CI(\axaddr_incr_reg[4]_i_1_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1_n_1 ,\axaddr_incr_reg[8]_i_1_n_2 ,\axaddr_incr_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1_n_4 ,\axaddr_incr_reg[8]_i_1_n_5 ,\axaddr_incr_reg[8]_i_1_n_6 ,\axaddr_incr_reg[8]_i_1_n_7 }),
.S({\axaddr_incr[8]_i_2_n_0 ,\axaddr_incr[8]_i_3_n_0 ,\axaddr_incr[8]_i_4_n_0 ,\axaddr_incr[8]_i_5_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1_n_6 ),
.Q(axaddr_incr_reg[5]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1
(.I0(E),
.I1(\m_payload_i_reg[51] [7]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(p_1_in[2]));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt_reg[4]_0 ));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(Q[3]),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [8]),
.O(p_1_in[6]));
LUT6 #(
.INIT(64'hFFFFA900A900A900))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg[7]_0 ),
.I2(\axlen_cnt[7]_i_4_n_0 ),
.I3(\state_reg[0] ),
.I4(E),
.I5(\m_payload_i_reg[51] [9]),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[7]_i_3
(.I0(Q[2]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt_reg[7]_0 ));
LUT2 #(
.INIT(4'hE))
\axlen_cnt[7]_i_4
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(Q[3]),
.O(\axlen_cnt[7]_i_4_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[2]),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[6]),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(p_1_in[7]),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_awaddr[1]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_0 ),
.I1(\axaddr_incr_reg[3]_0 [1]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\m_payload_i_reg[51] [1]),
.O(\m_axi_awaddr[1] ));
LUT6 #(
.INIT(64'h0000000000000001))
next_pending_r_i_3
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(Q[2]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(Q[1]),
.I5(\axlen_cnt[7]_i_4_n_0 ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_incr_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
(next_pending_r_reg_0,
\axaddr_incr_reg[3]_0 ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[11]_1 ,
Q,
next_pending_r_reg_1,
\m_axi_araddr[5] ,
\m_axi_araddr[2] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
O,
sel_first_reg_1,
\state_reg[0] ,
\m_payload_i_reg[47] ,
CO,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[11] ,
m_valid_i_reg,
D,
\state_reg[1] ,
m_axi_arready);
output next_pending_r_reg_0;
output [3:0]\axaddr_incr_reg[3]_0 ;
output [6:0]\axaddr_incr_reg[11]_0 ;
output \axaddr_incr_reg[11]_1 ;
output [1:0]Q;
output next_pending_r_reg_1;
output \m_axi_araddr[5] ;
output \m_axi_araddr[2] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input [3:0]O;
input sel_first_reg_1;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]CO;
input [0:0]E;
input [12:0]\m_payload_i_reg[51] ;
input [3:0]\m_payload_i_reg[3] ;
input [3:0]\m_payload_i_reg[11] ;
input [0:0]m_valid_i_reg;
input [1:0]D;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [0:0]CO;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [1:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[4]_i_2__0_n_0 ;
wire \axaddr_incr[4]_i_3__0_n_0 ;
wire \axaddr_incr[4]_i_4__0_n_0 ;
wire \axaddr_incr[4]_i_5__0_n_0 ;
wire \axaddr_incr[8]_i_2__0_n_0 ;
wire \axaddr_incr[8]_i_3__0_n_0 ;
wire \axaddr_incr[8]_i_4__0_n_0 ;
wire \axaddr_incr[8]_i_5__0_n_0 ;
wire [5:5]axaddr_incr_reg;
wire [6:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_1 ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_0 ;
wire \axaddr_incr_reg[4]_i_1__0_n_1 ;
wire \axaddr_incr_reg[4]_i_1__0_n_2 ;
wire \axaddr_incr_reg[4]_i_1__0_n_3 ;
wire \axaddr_incr_reg[4]_i_1__0_n_4 ;
wire \axaddr_incr_reg[4]_i_1__0_n_5 ;
wire \axaddr_incr_reg[4]_i_1__0_n_6 ;
wire \axaddr_incr_reg[4]_i_1__0_n_7 ;
wire \axaddr_incr_reg[8]_i_1__0_n_1 ;
wire \axaddr_incr_reg[8]_i_1__0_n_2 ;
wire \axaddr_incr_reg[8]_i_1__0_n_3 ;
wire \axaddr_incr_reg[8]_i_1__0_n_4 ;
wire \axaddr_incr_reg[8]_i_1__0_n_5 ;
wire \axaddr_incr_reg[8]_i_1__0_n_6 ;
wire \axaddr_incr_reg[8]_i_1__0_n_7 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_2__0_n_0 ;
wire \axlen_cnt[5]_i_1__0_n_0 ;
wire \axlen_cnt[5]_i_2_n_0 ;
wire \axlen_cnt[6]_i_1__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_3__0_n_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[2] ;
wire \m_axi_araddr[5] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[11] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire [12:0]\m_payload_i_reg[51] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_4__0_n_0;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire \state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED ;
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[0]_i_15
(.I0(\m_payload_i_reg[51] [3]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[0]_i_16
(.I0(\m_payload_i_reg[51] [2]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[0]_i_17
(.I0(\m_payload_i_reg[51] [1]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [6]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[1]));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[0]_i_18
(.I0(\m_payload_i_reg[51] [0]),
.I1(\m_payload_i_reg[51] [6]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_2__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [2]),
.O(\axaddr_incr[4]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_3__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [1]),
.O(\axaddr_incr[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_4__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(axaddr_incr_reg),
.O(\axaddr_incr[4]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_5__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [0]),
.O(\axaddr_incr[4]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_2__0
(.I0(\m_payload_i_reg[11] [3]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [6]),
.O(\axaddr_incr[8]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_3__0
(.I0(\m_payload_i_reg[11] [2]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [5]),
.O(\axaddr_incr[8]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_4__0
(.I0(\m_payload_i_reg[11] [1]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [4]),
.O(\axaddr_incr[8]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_5__0
(.I0(\m_payload_i_reg[11] [0]),
.I1(\axaddr_incr_reg[11]_1 ),
.I2(\axaddr_incr_reg[11]_0 [3]),
.O(\axaddr_incr[8]_i_5__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[0]),
.Q(\axaddr_incr_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[1]),
.Q(\axaddr_incr_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[2]),
.Q(\axaddr_incr_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_0),
.D(O[3]),
.Q(\axaddr_incr_reg[3]_0 [3]),
.R(1'b0));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[4]_i_1__0
(.CI(CO),
.CO({\axaddr_incr_reg[4]_i_1__0_n_0 ,\axaddr_incr_reg[4]_i_1__0_n_1 ,\axaddr_incr_reg[4]_i_1__0_n_2 ,\axaddr_incr_reg[4]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[4]_i_1__0_n_4 ,\axaddr_incr_reg[4]_i_1__0_n_5 ,\axaddr_incr_reg[4]_i_1__0_n_6 ,\axaddr_incr_reg[4]_i_1__0_n_7 }),
.S({\axaddr_incr[4]_i_2__0_n_0 ,\axaddr_incr[4]_i_3__0_n_0 ,\axaddr_incr[4]_i_4__0_n_0 ,\axaddr_incr[4]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_6 ),
.Q(axaddr_incr_reg),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_5 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[4]_i_1__0_n_4 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_7 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[8]_i_1__0
(.CI(\axaddr_incr_reg[4]_i_1__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_1__0_n_1 ,\axaddr_incr_reg[8]_i_1__0_n_2 ,\axaddr_incr_reg[8]_i_1__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[8]_i_1__0_n_4 ,\axaddr_incr_reg[8]_i_1__0_n_5 ,\axaddr_incr_reg[8]_i_1__0_n_6 ,\axaddr_incr_reg[8]_i_1__0_n_7 }),
.S({\axaddr_incr[8]_i_2__0_n_0 ,\axaddr_incr[8]_i_3__0_n_0 ,\axaddr_incr[8]_i_4__0_n_0 ,\axaddr_incr[8]_i_5__0_n_0 }));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_0),
.D(\axaddr_incr_reg[8]_i_1__0_n_6 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[51] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt[4]_i_2__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [9]),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q[1]),
.I2(Q[0]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[4]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt[5]_i_2_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [10]),
.O(\axlen_cnt[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\axlen_cnt[5]_i_2
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [11]),
.O(\axlen_cnt[6]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[7]_i_2__0
(.I0(E),
.I1(\m_payload_i_reg[51] [12]),
.I2(\axlen_cnt_reg_n_0_[7] ),
.I3(\axlen_cnt[7]_i_3__0_n_0 ),
.I4(\axlen_cnt_reg_n_0_[6] ),
.I5(\state_reg[0] ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\axlen_cnt[7]_i_3__0
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt_reg_n_0_[3] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[7]_i_3__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[5]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[6]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[2]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(\axaddr_incr_reg[3]_0 [2]),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [2]),
.O(\m_axi_araddr[2] ));
LUT4 #(
.INIT(16'hEF40))
\m_axi_araddr[5]_INST_0_i_1
(.I0(\axaddr_incr_reg[11]_1 ),
.I1(axaddr_incr_reg),
.I2(\m_payload_i_reg[51] [7]),
.I3(\m_payload_i_reg[51] [4]),
.O(\m_axi_araddr[5] ));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_3__1
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[5] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(next_pending_r_i_4__0_n_0),
.O(next_pending_r_reg_1));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_4__0
(.I0(Q[1]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_4__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(\axaddr_incr_reg[11]_1 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_r_channel" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel
(\state_reg[1]_rep ,
m_axi_rready,
m_valid_i_reg,
out,
\skid_buffer_reg[46] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_ready_i_reg,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1,
D);
output \state_reg[1]_rep ;
output m_axi_rready;
output m_valid_i_reg;
output [33:0]out;
output [12:0]\skid_buffer_reg[46] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_ready_i_reg;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
input [11:0]D;
wire [11:0]D;
wire aclk;
wire areset_d1;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire m_valid_i_reg;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_0;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire rd_data_fifo_0_n_5;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [12:0]trans_in;
wire transaction_fifo_0_n_1;
wire wr_en0;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(trans_in[1]),
.R(1'b0));
FDRE \r_arid_r_reg[10]
(.C(aclk),
.CE(1'b1),
.D(D[10]),
.Q(trans_in[11]),
.R(1'b0));
FDRE \r_arid_r_reg[11]
(.C(aclk),
.CE(1'b1),
.D(D[11]),
.Q(trans_in[12]),
.R(1'b0));
FDRE \r_arid_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(trans_in[2]),
.R(1'b0));
FDRE \r_arid_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(trans_in[3]),
.R(1'b0));
FDRE \r_arid_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[3]),
.Q(trans_in[4]),
.R(1'b0));
FDRE \r_arid_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(D[4]),
.Q(trans_in[5]),
.R(1'b0));
FDRE \r_arid_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(D[5]),
.Q(trans_in[6]),
.R(1'b0));
FDRE \r_arid_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(D[6]),
.Q(trans_in[7]),
.R(1'b0));
FDRE \r_arid_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(D[7]),
.Q(trans_in[8]),
.R(1'b0));
FDRE \r_arid_r_reg[8]
(.C(aclk),
.CE(1'b1),
.D(D[8]),
.Q(trans_in[9]),
.R(1'b0));
FDRE \r_arid_r_reg[9]
(.C(aclk),
.CE(1'b1),
.D(D[9]),
.Q(trans_in[10]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[3]_rep__2_0 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__0_0 (m_valid_i_reg),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2_1 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(transaction_fifo_0_n_1),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_5),
.wr_en0(wr_en0));
zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_5),
.\cnt_read_reg[0]_rep__2_0 (rd_data_fifo_0_n_3),
.\cnt_read_reg[3]_rep__2 (rd_data_fifo_0_n_0),
.\cnt_read_reg[4]_rep__2 (transaction_fifo_0_n_1),
.\cnt_read_reg[4]_rep__2_0 (rd_data_fifo_0_n_2),
.in(trans_in),
.m_valid_i_reg(m_valid_i_reg),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[46] (\skid_buffer_reg[46] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.wr_en0(wr_en0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
(\axlen_cnt_reg[1] ,
Q,
D,
wrap_second_len,
r_push_r_reg,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
\axlen_cnt_reg[1]_0 ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
\axaddr_wrap_reg[11] ,
\axaddr_incr_reg[11] ,
m_axi_arvalid,
\m_payload_i_reg[0]_1 ,
sel_first_reg,
sel_first_reg_0,
si_rs_arvalid,
\axlen_cnt_reg[4] ,
\m_payload_i_reg[44] ,
m_axi_arready,
s_axburst_eq1_reg_0,
\cnt_read_reg[2]_rep__0 ,
\m_payload_i_reg[47] ,
\axlen_cnt_reg[1]_1 ,
\wrap_second_len_r_reg[1] ,
axaddr_offset,
wrap_next_pending,
\m_payload_i_reg[51] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first_reg_3,
aclk);
output \axlen_cnt_reg[1] ;
output [1:0]Q;
output [0:0]D;
output [0:0]wrap_second_len;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [1:0]\axlen_cnt_reg[1]_0 ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output [0:0]\axaddr_wrap_reg[11] ;
output \axaddr_incr_reg[11] ;
output m_axi_arvalid;
output [0:0]\m_payload_i_reg[0]_1 ;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_arvalid;
input \axlen_cnt_reg[4] ;
input \m_payload_i_reg[44] ;
input m_axi_arready;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[2]_rep__0 ;
input [3:0]\m_payload_i_reg[47] ;
input [1:0]\axlen_cnt_reg[1]_1 ;
input [0:0]\wrap_second_len_r_reg[1] ;
input [2:0]axaddr_offset;
input wrap_next_pending;
input \m_payload_i_reg[51] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first_reg_3;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [2:0]axaddr_offset;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire \axlen_cnt_reg[1] ;
wire [1:0]\axlen_cnt_reg[1]_0 ;
wire [1:0]\axlen_cnt_reg[1]_1 ;
wire \axlen_cnt_reg[4] ;
wire \cnt_read_reg[2]_rep__0 ;
wire incr_next_pending;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire [0:0]\m_payload_i_reg[0]_1 ;
wire \m_payload_i_reg[44] ;
wire [3:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[51] ;
wire \m_payload_i_reg[6] ;
wire next_pending_r_reg;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire wrap_next_pending;
wire [0:0]wrap_second_len;
wire [0:0]\wrap_second_len_r_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[0]_i_1__0
(.I0(sel_first_reg_2),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[47] [3]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__1
(.I0(Q[1]),
.I1(si_rs_arvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[47] [1]),
.I4(\axlen_cnt_reg[1]_1 [0]),
.I5(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[47] [2]),
.I2(\axlen_cnt_reg[1]_1 [1]),
.I3(\axlen_cnt_reg[1]_1 [0]),
.I4(\axlen_cnt_reg[1] ),
.O(\axlen_cnt_reg[1]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[7]_i_1__0
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(\m_payload_i_reg[0]_0 ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_wrap_reg[11] ));
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_4__0
(.I0(Q[0]),
.I1(si_rs_arvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[1] ));
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i_reg[0]_1 ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__2
(.I0(\m_payload_i_reg[51] ),
.I1(E),
.I2(\axlen_cnt_reg[4] ),
.I3(r_push_r_reg),
.I4(next_pending_r_reg),
.O(incr_next_pending));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\m_payload_i_reg[0]_0 ),
.I2(m_axi_arready),
.O(r_push_r_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__0
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\m_payload_i_reg[0]_0 ),
.I4(m_axi_arready),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__4
(.I0(m_axi_arready),
.I1(sel_first_reg_3),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg_0),
.I5(\cnt_read_reg[2]_rep__0 ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2]_rep__0 ),
.I1(s_axburst_eq1_reg_0),
.I2(m_axi_arready),
.I3(\m_payload_i_reg[0]_0 ),
.I4(\m_payload_i_reg[0] ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\m_payload_i_reg[0]_0 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\m_payload_i_reg[0]_0 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1__0
(.I0(wrap_second_len),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[1] ),
.I1(axaddr_offset[2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(axaddr_offset[0]),
.I4(axaddr_offset[1]),
.I5(E),
.O(wrap_second_len));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo
(\cnt_read_reg[0]_rep__0_0 ,
\cnt_read_reg[1]_rep__1_0 ,
D,
\cnt_read_reg[0]_0 ,
sel,
SR,
bvalid_i_reg,
out,
b_push,
shandshake_r,
Q,
areset_d1,
\bresp_cnt_reg[7] ,
mhandshake_r,
bvalid_i_reg_0,
si_rs_bready,
in,
aclk);
output \cnt_read_reg[0]_rep__0_0 ;
output \cnt_read_reg[1]_rep__1_0 ;
output [0:0]D;
output \cnt_read_reg[0]_0 ;
output sel;
output [0:0]SR;
output bvalid_i_reg;
output [11:0]out;
input b_push;
input shandshake_r;
input [1:0]Q;
input areset_d1;
input [7:0]\bresp_cnt_reg[7] ;
input mhandshake_r;
input bvalid_i_reg_0;
input si_rs_bready;
input [19:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire [7:0]\bresp_cnt_reg[7] ;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_0 ;
wire \cnt_read_reg[0]_rep__0_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire [19:0]in;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_i_4_n_0 ;
wire \memory_reg[3][0]_srl4_i_5_n_0 ;
wire \memory_reg[3][0]_srl4_i_6_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire \memory_reg[3][4]_srl4_n_0 ;
wire \memory_reg[3][5]_srl4_n_0 ;
wire \memory_reg[3][6]_srl4_n_0 ;
wire \memory_reg[3][7]_srl4_n_0 ;
wire mhandshake_r;
wire [11:0]out;
wire sel;
wire shandshake_r;
wire si_rs_bready;
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT2 #(
.INIT(4'hB))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(\cnt_read_reg[0]_0 ),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h002A))
bvalid_i_i_1
(.I0(bvalid_i_i_2_n_0),
.I1(bvalid_i_reg_0),
.I2(si_rs_bready),
.I3(areset_d1),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[1]_rep__1_0 ),
.I1(\cnt_read_reg[0]_rep__0_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT3 #(
.INIT(8'h69))
\cnt_read[0]_i_1
(.I0(\cnt_read_reg[0]_0 ),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep__0_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep__1_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT1 #(
.INIT(2'h1))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\cnt_read_reg[0]_0 ),
.O(sel));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFE))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I1(\memory_reg[3][0]_srl4_i_4_n_0 ),
.I2(\memory_reg[3][0]_srl4_i_5_n_0 ),
.I3(\memory_reg[3][0]_srl4_i_6_n_0 ),
.I4(\bresp_cnt_reg[7] [3]),
.I5(\memory_reg[3][3]_srl4_n_0 ),
.O(\cnt_read_reg[0]_0 ));
LUT6 #(
.INIT(64'h22F2FFFFFFFF22F2))
\memory_reg[3][0]_srl4_i_3
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\memory_reg[3][2]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [2]),
.I4(\memory_reg[3][1]_srl4_n_0 ),
.I5(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
LUT6 #(
.INIT(64'hF222FFFFFFFFF222))
\memory_reg[3][0]_srl4_i_4
(.I0(\bresp_cnt_reg[7] [5]),
.I1(\memory_reg[3][5]_srl4_n_0 ),
.I2(\cnt_read_reg[1]_rep__1_0 ),
.I3(\cnt_read_reg[0]_rep__0_0 ),
.I4(\bresp_cnt_reg[7] [7]),
.I5(\memory_reg[3][7]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_4_n_0 ));
LUT6 #(
.INIT(64'h2FF22FF2FFFF2FF2))
\memory_reg[3][0]_srl4_i_5
(.I0(\bresp_cnt_reg[7] [2]),
.I1(\memory_reg[3][2]_srl4_n_0 ),
.I2(\memory_reg[3][4]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [4]),
.I4(\bresp_cnt_reg[7] [0]),
.I5(\memory_reg[3][0]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_5_n_0 ));
LUT5 #(
.INIT(32'h6F6FFF6F))
\memory_reg[3][0]_srl4_i_6
(.I0(\memory_reg[3][6]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [6]),
.I2(mhandshake_r),
.I3(\memory_reg[3][5]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [5]),
.O(\memory_reg[3][0]_srl4_i_6_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][10]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[10]),
.Q(out[2]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][11]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[11]),
.Q(out[3]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][12]_srl4
(.A0(cnt_read[0]),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[12]),
.Q(out[4]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][13]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[13]),
.Q(out[5]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][14]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[14]),
.Q(out[6]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][15]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[15]),
.Q(out[7]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][16]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[16]),
.Q(out[8]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][17]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[17]),
.Q(out[9]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][18]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[18]),
.Q(out[10]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][19]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[19]),
.Q(out[11]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][4]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(\memory_reg[3][4]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][5]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep__0_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(\memory_reg[3][5]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][6]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(\memory_reg[3][6]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][7]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(\memory_reg[3][7]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out[0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][9]_srl4
(.A0(\cnt_read_reg[0]_rep_n_0 ),
.A1(\cnt_read_reg[1]_rep_n_0 ),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[9]),
.Q(out[1]));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0
(mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
\bresp_cnt_reg[3] ,
sel,
in,
aclk,
areset_d1,
D);
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input \bresp_cnt_reg[3] ;
input sel;
input [1:0]in;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \bresp_cnt_reg[3] ;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire sel;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(shandshake_r),
.I2(Q[0]),
.I3(\bresp_cnt_reg[3] ),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(sel),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1
(\cnt_read_reg[3]_rep__2_0 ,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[4]_rep__2_1 ,
m_axi_rready,
\state_reg[1]_rep ,
out,
s_ready_i_reg,
s_ready_i_reg_0,
si_rs_rready,
\cnt_read_reg[4]_rep__0_0 ,
m_axi_rvalid,
in,
aclk,
areset_d1);
output \cnt_read_reg[3]_rep__2_0 ;
output wr_en0;
output \cnt_read_reg[4]_rep__2_0 ;
output \cnt_read_reg[4]_rep__2_1 ;
output m_axi_rready;
output \state_reg[1]_rep ;
output [33:0]out;
input s_ready_i_reg;
input s_ready_i_reg_0;
input si_rs_rready;
input \cnt_read_reg[4]_rep__0_0 ;
input m_axi_rvalid;
input [33:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep__2_1 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hA96A))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(\cnt_read_reg[0]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'hA6AAAA9A))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(s_ready_i_reg),
.I3(wr_en0),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAA55AAA6A6AAA6AA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[4]_rep__2_1 ),
.I5(\cnt_read_reg[3]_rep__2_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(\cnt_read_reg[4]_rep__0_0 ),
.I3(wr_en0),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read_reg[4]_rep__2_1 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[3]_rep__2_0 ),
.I1(\cnt_read_reg[4]_rep__2_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[3]_rep__2_0 ),
.I2(\cnt_read_reg[4]_rep__2_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_simple_fifo" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2
(\state_reg[1]_rep ,
\cnt_read_reg[4]_rep__2 ,
m_valid_i_reg,
\skid_buffer_reg[46] ,
r_push_r,
s_ready_i_reg,
\cnt_read_reg[0]_rep__2 ,
si_rs_rready,
wr_en0,
\cnt_read_reg[4]_rep__2_0 ,
\cnt_read_reg[3]_rep__2 ,
\cnt_read_reg[0]_rep__2_0 ,
in,
aclk,
areset_d1);
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_rep__2 ;
output m_valid_i_reg;
output [12:0]\skid_buffer_reg[46] ;
input r_push_r;
input s_ready_i_reg;
input \cnt_read_reg[0]_rep__2 ;
input si_rs_rready;
input wr_en0;
input \cnt_read_reg[4]_rep__2_0 ;
input \cnt_read_reg[3]_rep__2 ;
input \cnt_read_reg[0]_rep__2_0 ;
input [12:0]in;
input aclk;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read[4]_i_4__0_n_0 ;
wire \cnt_read[4]_i_5__0_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[0]_rep__2_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__2 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__2 ;
wire \cnt_read_reg[4]_rep__2_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [12:0]in;
wire m_valid_i_reg;
wire r_push_r;
wire s_ready_i_reg;
wire si_rs_rready;
wire [12:0]\skid_buffer_reg[46] ;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(s_ready_i_reg),
.I2(r_push_r),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__1
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[0]_rep__0_n_0 ),
.I2(s_ready_i_reg),
.I3(r_push_r),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'hAA6AA9AA))
\cnt_read[2]_i_1__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(r_push_r),
.I3(s_ready_i_reg),
.I4(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAAA6AAAAAA9AAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[3]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(r_push_r),
.I4(s_ready_i_reg),
.I5(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h6A666A6AAA99AAAA))
\cnt_read[4]_i_1__0
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read[4]_i_4__0_n_0 ),
.I4(\cnt_read[4]_i_5__0_n_0 ),
.I5(\cnt_read_reg[3]_rep__0_n_0 ),
.O(\cnt_read[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h8A))
\cnt_read[4]_i_2__0
(.I0(r_push_r),
.I1(m_valid_i_reg),
.I2(si_rs_rready),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_3__0
(.I0(\cnt_read_reg[2]_rep__0_n_0 ),
.I1(\cnt_read_reg[1]_rep__0_n_0 ),
.I2(\cnt_read_reg[0]_rep__0_n_0 ),
.O(\cnt_read[4]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(m_valid_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read_reg[4]_rep__2 ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_4__0
(.I0(\cnt_read_reg[0]_rep__0_n_0 ),
.I1(si_rs_rready),
.I2(m_valid_i_reg),
.I3(r_push_r),
.O(\cnt_read[4]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_5__0
(.I0(\cnt_read_reg[1]_rep__0_n_0 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.O(\cnt_read[4]_i_5__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
LUT6 #(
.INIT(64'hFF80808080808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__0_n_0 ),
.I1(\cnt_read_reg[3]_rep__0_n_0 ),
.I2(\cnt_read[4]_i_3__0_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_0 ),
.I4(\cnt_read_reg[3]_rep__2 ),
.I5(\cnt_read_reg[0]_rep__2_0 ),
.O(m_valid_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[46] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[10]),
.Q(\skid_buffer_reg[46] [10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[11]),
.Q(\skid_buffer_reg[46] [11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[12]),
.Q(\skid_buffer_reg[46] [12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[46] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[2]),
.Q(\skid_buffer_reg[46] [2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[3]),
.Q(\skid_buffer_reg[46] [3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[4]),
.Q(\skid_buffer_reg[46] [4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(r_push_r),
.CLK(aclk),
.D(in[5]),
.Q(\skid_buffer_reg[46] [5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[6]),
.Q(\skid_buffer_reg[46] [6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[7]),
.Q(\skid_buffer_reg[46] [7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[8]),
.Q(\skid_buffer_reg[46] [8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A(cnt_read),
.CE(r_push_r),
.CLK(aclk),
.D(in[9]),
.Q(\skid_buffer_reg[46] [9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBEFEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(\cnt_read_reg[2]_rep__0_n_0 ),
.I2(\cnt_read_reg[1]_rep__0_n_0 ),
.I3(\cnt_read_reg[0]_rep__0_n_0 ),
.I4(\cnt_read_reg[3]_rep__0_n_0 ),
.I5(\cnt_read_reg[4]_rep__0_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
(\axlen_cnt_reg[4] ,
Q,
D,
\wrap_second_len_r_reg[1] ,
\state_reg[1]_rep_0 ,
\state_reg[1]_rep_1 ,
\axlen_cnt_reg[5] ,
E,
\axaddr_offset_r_reg[3] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
next,
\m_payload_i_reg[0] ,
\axaddr_wrap_reg[0] ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[0]_0 ,
m_axi_awvalid,
sel_first_reg,
sel_first_reg_0,
si_rs_awvalid,
\axlen_cnt_reg[3] ,
\m_payload_i_reg[44] ,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep__1 ,
\cnt_read_reg[0]_rep__0 ,
m_axi_awready,
\m_payload_i_reg[49] ,
\axlen_cnt_reg[5]_0 ,
\axlen_cnt_reg[3]_0 ,
\axlen_cnt_reg[4]_0 ,
\wrap_second_len_r_reg[1]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[48] ,
next_pending_r_reg,
areset_d1,
sel_first_reg_1,
\m_payload_i_reg[46] ,
\axlen_cnt_reg[2] ,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[6] ,
sel_first_reg_2,
sel_first__0,
aclk);
output \axlen_cnt_reg[4] ;
output [1:0]Q;
output [0:0]D;
output [0:0]\wrap_second_len_r_reg[1] ;
output \state_reg[1]_rep_0 ;
output \state_reg[1]_rep_1 ;
output [3:0]\axlen_cnt_reg[5] ;
output [0:0]E;
output [0:0]\axaddr_offset_r_reg[3] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output next;
output \m_payload_i_reg[0] ;
output [0:0]\axaddr_wrap_reg[0] ;
output \axaddr_incr_reg[11] ;
output [0:0]\m_payload_i_reg[0]_0 ;
output m_axi_awvalid;
output sel_first_reg;
output sel_first_reg_0;
input si_rs_awvalid;
input \axlen_cnt_reg[3] ;
input \m_payload_i_reg[44] ;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep__1 ;
input \cnt_read_reg[0]_rep__0 ;
input m_axi_awready;
input [5:0]\m_payload_i_reg[49] ;
input [3:0]\axlen_cnt_reg[5]_0 ;
input \axlen_cnt_reg[3]_0 ;
input \axlen_cnt_reg[4]_0 ;
input [0:0]\wrap_second_len_r_reg[1]_0 ;
input [2:0]\m_payload_i_reg[35] ;
input \m_payload_i_reg[48] ;
input next_pending_r_reg;
input areset_d1;
input sel_first_reg_1;
input \m_payload_i_reg[46] ;
input \axlen_cnt_reg[2] ;
input next_pending_r_reg_0;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[6] ;
input sel_first_reg_2;
input sel_first__0;
input aclk;
wire [0:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire \axaddr_incr_reg[11] ;
wire [0:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_wrap_reg[0] ;
wire \axlen_cnt_reg[2] ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[4]_0 ;
wire [3:0]\axlen_cnt_reg[5] ;
wire [3:0]\axlen_cnt_reg[5]_0 ;
wire \cnt_read_reg[0]_rep__0 ;
wire \cnt_read_reg[1]_rep__1 ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[0]_0 ;
wire [2:0]\m_payload_i_reg[35] ;
wire \m_payload_i_reg[44] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[48] ;
wire [5:0]\m_payload_i_reg[49] ;
wire \m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [0:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first__0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_awvalid;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire wrap_next_pending;
wire [0:0]\wrap_second_len_r_reg[1] ;
wire [0:0]\wrap_second_len_r_reg[1]_0 ;
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hEEFE))
\axaddr_incr[0]_i_1
(.I0(sel_first_reg_2),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_incr_reg[11] ));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r_reg[3]_0 ),
.I1(\m_payload_i_reg[49] [3]),
.I2(\state_reg[1]_rep_1 ),
.I3(si_rs_awvalid),
.I4(\state_reg[1]_rep_0 ),
.I5(\m_payload_i_reg[6] ),
.O(\axaddr_offset_r_reg[3] ));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[49] [1]),
.I4(\axlen_cnt_reg[5]_0 [0]),
.I5(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [2]),
.I2(\axlen_cnt_reg[5]_0 [1]),
.I3(\axlen_cnt_reg[5]_0 [0]),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [1]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[4]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [4]),
.I2(\axlen_cnt_reg[5]_0 [2]),
.I3(\axlen_cnt_reg[3]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [2]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[5]_i_1
(.I0(E),
.I1(\m_payload_i_reg[49] [5]),
.I2(\axlen_cnt_reg[5]_0 [3]),
.I3(\axlen_cnt_reg[4]_0 ),
.I4(\axlen_cnt_reg[4] ),
.O(\axlen_cnt_reg[5] [3]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hCCFE))
\axlen_cnt[7]_i_1
(.I0(si_rs_awvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\state_reg[1]_rep_0 ),
.I3(\state_reg[1]_rep_1 ),
.O(\axaddr_wrap_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_5
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[3] ),
.O(\axlen_cnt_reg[4] ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(\state_reg[1]_rep_1 ),
.I1(\state_reg[1]_rep_0 ),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(s_axburst_eq1_reg_0),
.O(\m_payload_i_reg[0] ));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1
(.I0(\m_payload_i_reg[48] ),
.I1(E),
.I2(\axlen_cnt_reg[3] ),
.I3(next),
.I4(next_pending_r_reg),
.O(incr_next_pending));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46] ),
.I1(E),
.I2(\axlen_cnt_reg[2] ),
.I3(next),
.I4(next_pending_r_reg_0),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hF3F35100FFFF0000))
next_pending_r_i_4
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[49] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hCCCEFCFFCCCECCCE))
sel_first_i_1
(.I0(si_rs_awvalid),
.I1(areset_d1),
.I2(\state_reg[1]_rep_1 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[0] ),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__1
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first_reg_2),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44440F04))
sel_first_i_1__2
(.I0(\m_payload_i_reg[0] ),
.I1(sel_first__0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h2F))
\state[0]_i_1
(.I0(si_rs_awvalid),
.I1(Q[0]),
.I2(\state[0]_i_2_n_0 ),
.O(next_state));
LUT6 #(
.INIT(64'hFA08FAFA0F0F0F0F))
\state[0]_i_2
(.I0(m_axi_awready),
.I1(s_axburst_eq1_reg_0),
.I2(\state_reg[1]_rep_0 ),
.I3(\cnt_read_reg[0]_rep__0 ),
.I4(\cnt_read_reg[1]_rep__1 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep__1 ),
.I2(\cnt_read_reg[0]_rep__0 ),
.I3(m_axi_awready),
.I4(\state_reg[1]_rep_0 ),
.I5(\state_reg[1]_rep_1 ),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(\state_reg[1]_rep_1 ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(\state_reg[1]_rep_0 ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(si_rs_awvalid),
.I2(\state_reg[1]_rep_1 ),
.O(E));
LUT2 #(
.INIT(4'h9))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1] ),
.I1(\m_payload_i_reg[44] ),
.O(D));
LUT6 #(
.INIT(64'hFF0000FCAAAAAAAA))
\wrap_second_len_r[1]_i_1
(.I0(\wrap_second_len_r_reg[1]_0 ),
.I1(\m_payload_i_reg[35] [2]),
.I2(\axaddr_offset_r_reg[3] ),
.I3(\m_payload_i_reg[35] [0]),
.I4(\m_payload_i_reg[35] [1]),
.I5(E),
.O(\wrap_second_len_r_reg[1] ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wrap_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
next,
axaddr_incr_reg,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input next;
input [7:0]axaddr_incr_reg;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [7:0]axaddr_incr_reg;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[11]_i_5_n_0 ;
wire \axaddr_wrap[11]_i_6_n_0 ;
wire \axaddr_wrap[11]_i_7_n_0 ;
wire \axaddr_wrap[11]_i_8_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_3_n_0 ;
wire \axaddr_wrap[7]_i_4_n_0 ;
wire \axaddr_wrap[7]_i_5_n_0 ;
wire \axaddr_wrap[7]_i_6_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1__0_n_0 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__0_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[38] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [11:0]wrap_boundary_axaddr_r;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(wrap_cnt_r[2]),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(wrap_cnt_r[1]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5
(.I0(axaddr_wrap[11]),
.O(\axaddr_wrap[11]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6
(.I0(axaddr_wrap[10]),
.O(\axaddr_wrap[11]_i_6_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7
(.I0(axaddr_wrap[9]),
.O(\axaddr_wrap[11]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8
(.I0(axaddr_wrap[8]),
.O(\axaddr_wrap[11]_i_8_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3
(.I0(axaddr_wrap[7]),
.O(\axaddr_wrap[7]_i_3_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4
(.I0(axaddr_wrap[6]),
.O(\axaddr_wrap[7]_i_4_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5
(.I0(axaddr_wrap[5]),
.O(\axaddr_wrap[7]_i_5_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6
(.I0(axaddr_wrap[4]),
.O(\axaddr_wrap[7]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S({\axaddr_wrap[11]_i_5_n_0 ,\axaddr_wrap[11]_i_6_n_0 ,\axaddr_wrap[11]_i_7_n_0 ,\axaddr_wrap[11]_i_8_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S({\axaddr_wrap[7]_i_3_n_0 ,\axaddr_wrap[7]_i_4_n_0 ,\axaddr_wrap[7]_i_5_n_0 ,\axaddr_wrap[7]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__0
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[0]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__0_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[7]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_awaddr[11]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_awaddr[1]_INST_0
(.I0(\m_payload_i_reg[47] [1]),
.I1(sel_first_reg_0),
.I2(axaddr_wrap[1]),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [5]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(\m_payload_i_reg[47] [14]),
.I3(axaddr_incr_reg[5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT3 #(
.INIT(8'h01))
next_pending_r_i_3__0
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_13_b2s_wrap_cmd" *)
module zynq_design_1_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
(wrap_next_pending,
sel_first_reg_0,
m_axi_araddr,
\axaddr_offset_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[0]_rep ,
si_rs_arvalid,
\state_reg[1]_rep ,
\m_payload_i_reg[46] ,
\state_reg[1]_rep_0 ,
\axaddr_incr_reg[11] ,
\m_payload_i_reg[38] ,
\axaddr_incr_reg[3] ,
sel_first_reg_2,
sel_first_reg_3,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output wrap_next_pending;
output sel_first_reg_0;
output [11:0]m_axi_araddr;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input \state_reg[0]_rep ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input \m_payload_i_reg[46] ;
input \state_reg[1]_rep_0 ;
input [6:0]\axaddr_incr_reg[11] ;
input \m_payload_i_reg[38] ;
input [2:0]\axaddr_incr_reg[3] ;
input sel_first_reg_2;
input sel_first_reg_3;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [3:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [6:0]\axaddr_incr_reg[11] ;
wire [2:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[11]_i_5__0_n_0 ;
wire \axaddr_wrap[11]_i_6__0_n_0 ;
wire \axaddr_wrap[11]_i_7__0_n_0 ;
wire \axaddr_wrap[11]_i_8__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_3__0_n_0 ;
wire \axaddr_wrap[7]_i_4__0_n_0 ;
wire \axaddr_wrap[7]_i_5__0_n_0 ;
wire \axaddr_wrap[7]_i_6__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__2_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[38] ;
wire \m_payload_i_reg[46] ;
wire [18:0]\m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_3__2_n_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire si_rs_arvalid;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_1 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\wrap_cnt_r_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\wrap_cnt_r_reg_n_0_[2] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[11] ),
.O(\axaddr_wrap[11]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[10] ),
.O(\axaddr_wrap[11]_i_6__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_7__0
(.I0(\axaddr_wrap_reg_n_0_[9] ),
.O(\axaddr_wrap[11]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[11]_i_8__0
(.I0(\axaddr_wrap_reg_n_0_[8] ),
.O(\axaddr_wrap[11]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_3__0
(.I0(\axaddr_wrap_reg_n_0_[7] ),
.O(\axaddr_wrap[7]_i_3__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_4__0
(.I0(\axaddr_wrap_reg_n_0_[6] ),
.O(\axaddr_wrap[7]_i_4__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_5__0
(.I0(\axaddr_wrap_reg_n_0_[5] ),
.O(\axaddr_wrap[7]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_wrap[7]_i_6__0
(.I0(\axaddr_wrap_reg_n_0_[4] ),
.O(\axaddr_wrap[7]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep_0 ),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap[11]_i_5__0_n_0 ,\axaddr_wrap[11]_i_6__0_n_0 ,\axaddr_wrap[11]_i_7__0_n_0 ,\axaddr_wrap[11]_i_8__0_n_0 }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap[7]_i_3__0_n_0 ,\axaddr_wrap[7]_i_4__0_n_0 ,\axaddr_wrap[7]_i_5__0_n_0 ,\axaddr_wrap[7]_i_6__0_n_0 }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__2
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [5]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [6]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [1]),
.O(m_axi_araddr[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[2]_INST_0
(.I0(\m_payload_i_reg[47] [2]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[2] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_3),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[3] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [0]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [4]),
.O(m_axi_araddr[4]));
LUT5 #(
.INIT(32'hB8FFB800))
\m_axi_araddr[5]_INST_0
(.I0(\m_payload_i_reg[47] [5]),
.I1(sel_first_reg_0),
.I2(\axaddr_wrap_reg_n_0_[5] ),
.I3(\m_payload_i_reg[47] [14]),
.I4(sel_first_reg_2),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [1]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [2]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [3]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEFE0EFEF4F404040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\axaddr_incr_reg[11] [4]),
.I4(\m_payload_i_reg[38] ),
.I5(\m_payload_i_reg[47] [9]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFD55FC0C))
next_pending_r_i_1__1
(.I0(\m_payload_i_reg[46] ),
.I1(next_pending_r_reg_n_0),
.I2(\state_reg[1]_rep_0 ),
.I3(next_pending_r_i_3__2_n_0),
.I4(E),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_3__2
(.I0(\state_reg[0]_rep ),
.I1(si_rs_arvalid),
.I2(\state_reg[1]_rep ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_3__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [3]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
Q,
\s_arid_r_reg[11] ,
\axaddr_incr_reg[11] ,
CO,
O,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11]_0 ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
axaddr_offset,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\wrap_cnt_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_cnt_r_reg[3]_1 ,
axaddr_offset_0,
\axlen_cnt_reg[3]_0 ,
next_pending_r_reg_1,
next_pending_r_reg_2,
\cnt_read_reg[3]_rep__0 ,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\m_axi_awaddr[10] ,
\m_axi_araddr[10] ,
\s_axi_bid[11] ,
\s_axi_rid[11] ,
aclk,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
\state_reg[1] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
b_push,
s_axi_awvalid,
S,
\m_payload_i_reg[3] ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[1]_0 ,
wrap_second_len,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_2 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_3 ,
\state_reg[1]_rep_1 ,
\axaddr_offset_r_reg[3]_4 ,
\state_reg[0]_rep_0 ,
\state_reg[1]_rep_2 ,
sel_first,
sel_first_2,
si_rs_bvalid,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
out,
\s_bresp_acc_reg[1] ,
r_push_r_reg,
\cnt_read_reg[4] ,
axaddr_incr_reg,
\axaddr_incr_reg[3]_0 ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [58:0]Q;
output [58:0]\s_arid_r_reg[11] ;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11]_0 ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output [2:0]axaddr_offset;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output [2:0]\wrap_cnt_r_reg[3]_0 ;
output [2:0]\wrap_second_len_r_reg[3]_0 ;
output \wrap_cnt_r_reg[3]_1 ;
output [2:0]axaddr_offset_0;
output \axlen_cnt_reg[3]_0 ;
output next_pending_r_reg_1;
output next_pending_r_reg_2;
output \cnt_read_reg[3]_rep__0 ;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[3]_0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output \m_axi_awaddr[10] ;
output \m_axi_araddr[10] ;
output [13:0]\s_axi_bid[11] ;
output [46:0]\s_axi_rid[11] ;
input aclk;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input [1:0]\state_reg[1] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [1:0]\state_reg[1]_0 ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_3 ;
input \state_reg[1]_rep_1 ;
input [3:0]\axaddr_offset_r_reg[3]_4 ;
input \state_reg[0]_rep_0 ;
input \state_reg[1]_rep_2 ;
input sel_first;
input sel_first_2;
input si_rs_bvalid;
input s_axi_bready;
input s_axi_arvalid;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [3:0]axaddr_incr_reg;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire ar_pipe_n_2;
wire aresetn;
wire aw_pipe_n_1;
wire aw_pipe_n_97;
wire [3:0]axaddr_incr_reg;
wire [7:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[11]_0 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire [2:0]axaddr_offset;
wire [2:0]axaddr_offset_0;
wire \axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [0:0]\axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire [0:0]\axaddr_offset_r_reg[3]_3 ;
wire [3:0]\axaddr_offset_r_reg[3]_4 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_axi_araddr[10] ;
wire \m_axi_awaddr[10] ;
wire [3:0]\m_payload_i_reg[3] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire [11:0]out;
wire [12:0]r_push_r_reg;
wire [58:0]\s_arid_r_reg[11] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire sel_first;
wire sel_first_2;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[0]_rep_0 ;
wire [1:0]\state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \state_reg[1]_rep_1 ;
wire \state_reg[1]_rep_2 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [2:0]\wrap_cnt_r_reg[3]_0 ;
wire \wrap_cnt_r_reg[3]_1 ;
wire [0:0]wrap_second_len;
wire [0:0]wrap_second_len_1;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice ar_pipe
(.Q(\s_arid_r_reg[11] ),
.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[0]_0 (aw_pipe_n_97),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11]_0 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[3]_0 (\axaddr_incr_reg[3]_0 ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.\axaddr_incr_reg[7]_0 (\axaddr_incr_reg[7]_0 ),
.\axaddr_offset_r_reg[0] (axaddr_offset_0[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset_0[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset_0[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_3 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_4 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_axi_araddr[10] (\m_axi_araddr[10] ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i_reg_0(ar_pipe_n_2),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_1),
.next_pending_r_reg_0(next_pending_r_reg_2),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.sel_first_2(sel_first_2),
.\state_reg[0]_rep (\state_reg[0]_rep_0 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep_1 ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_2 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3]_0 ),
.\wrap_cnt_r_reg[3]_0 (\wrap_cnt_r_reg[3]_1 ),
.wrap_second_len_1(wrap_second_len_1),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_2 ));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 aw_pipe
(.CO(CO),
.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (aw_pipe_n_97),
.\aresetn_d_reg[1]_inv_0 (ar_pipe_n_2),
.axaddr_incr_reg(axaddr_incr_reg),
.\axaddr_incr_reg[11] (\axaddr_incr_reg[11] ),
.\axaddr_offset_r_reg[0] (axaddr_offset[0]),
.\axaddr_offset_r_reg[1] (axaddr_offset[1]),
.\axaddr_offset_r_reg[2] (axaddr_offset[2]),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3]_1 ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_2 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.\m_axi_awaddr[10] (\m_axi_awaddr[10] ),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.next_pending_r_reg_0(next_pending_r_reg_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(aw_pipe_n_1),
.sel_first(sel_first),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1] (\state_reg[1]_0 ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_cnt_r_reg[3] (\wrap_cnt_r_reg[3] ),
.wrap_second_len(wrap_second_len),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3]_1 ));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.out(out),
.\s_axi_bid[11] (\s_axi_bid[11] ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[0]_0 (si_rs_bready));
zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (aw_pipe_n_1),
.\aresetn_d_reg[1]_inv (ar_pipe_n_2),
.\cnt_read_reg[3]_rep__0 (\cnt_read_reg[3]_rep__0 ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__0 (\cnt_read_reg[4]_rep__0 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[11] (\s_axi_rid[11] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[7] ,
\axaddr_incr_reg[11] ,
\axaddr_incr_reg[7]_0 ,
\axaddr_incr_reg[3] ,
\wrap_cnt_r_reg[3] ,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3]_0 ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_araddr[10] ,
\aresetn_d_reg[0] ,
aclk,
\aresetn_d_reg[0]_0 ,
\state_reg[1] ,
\m_payload_i_reg[3]_0 ,
\wrap_second_len_r_reg[3]_0 ,
wrap_second_len_1,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[3]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
sel_first_2,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
\axaddr_incr_reg[3]_0 ,
m_valid_i_reg_1);
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]\axaddr_incr_reg[11] ;
output [0:0]\axaddr_incr_reg[7]_0 ;
output [3:0]\axaddr_incr_reg[3] ;
output [2:0]\wrap_cnt_r_reg[3] ;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3]_0 ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_araddr[10] ;
input \aresetn_d_reg[0] ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [1:0]\state_reg[1] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [0:0]wrap_second_len_1;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input sel_first_2;
input s_axi_arvalid;
input [11:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [3:0]\axaddr_incr_reg[3]_0 ;
input [0:0]m_valid_i_reg_1;
wire [58:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[0]_i_10__0_n_0 ;
wire \axaddr_incr[0]_i_12__0_n_0 ;
wire \axaddr_incr[0]_i_13__0_n_0 ;
wire \axaddr_incr[0]_i_14__0_n_0 ;
wire \axaddr_incr[0]_i_3__0_n_0 ;
wire \axaddr_incr[0]_i_4__0_n_0 ;
wire \axaddr_incr[0]_i_5__0_n_0 ;
wire \axaddr_incr[0]_i_6__0_n_0 ;
wire \axaddr_incr[0]_i_7__0_n_0 ;
wire \axaddr_incr[0]_i_8__0_n_0 ;
wire \axaddr_incr[0]_i_9__0_n_0 ;
wire \axaddr_incr[4]_i_10__0_n_0 ;
wire \axaddr_incr[4]_i_7__0_n_0 ;
wire \axaddr_incr[4]_i_8__0_n_0 ;
wire \axaddr_incr[4]_i_9__0_n_0 ;
wire \axaddr_incr[8]_i_10__0_n_0 ;
wire \axaddr_incr[8]_i_7__0_n_0 ;
wire \axaddr_incr[8]_i_8__0_n_0 ;
wire \axaddr_incr[8]_i_9__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_0 ;
wire \axaddr_incr_reg[0]_i_11__0_n_1 ;
wire \axaddr_incr_reg[0]_i_11__0_n_2 ;
wire \axaddr_incr_reg[0]_i_11__0_n_3 ;
wire \axaddr_incr_reg[0]_i_11__0_n_4 ;
wire \axaddr_incr_reg[0]_i_11__0_n_5 ;
wire \axaddr_incr_reg[0]_i_11__0_n_6 ;
wire \axaddr_incr_reg[0]_i_11__0_n_7 ;
wire \axaddr_incr_reg[0]_i_2__0_n_1 ;
wire \axaddr_incr_reg[0]_i_2__0_n_2 ;
wire \axaddr_incr_reg[0]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[3]_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_0 ;
wire \axaddr_incr_reg[4]_i_6__0_n_1 ;
wire \axaddr_incr_reg[4]_i_6__0_n_2 ;
wire \axaddr_incr_reg[4]_i_6__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire [0:0]\axaddr_incr_reg[7]_0 ;
wire \axaddr_incr_reg[8]_i_6__0_n_1 ;
wire \axaddr_incr_reg[8]_i_6__0_n_2 ;
wire \axaddr_incr_reg[8]_i_6__0_n_3 ;
wire \axaddr_offset_r[0]_i_2__0_n_0 ;
wire \axaddr_offset_r[1]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire \m_axi_araddr[10] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__0_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__1_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[48]_i_1__0_n_0 ;
wire \m_payload_i[49]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[54]_i_1__0_n_0 ;
wire \m_payload_i[55]_i_1__0_n_0 ;
wire \m_payload_i[56]_i_1__0_n_0 ;
wire \m_payload_i[57]_i_1__0_n_0 ;
wire \m_payload_i[58]_i_1__0_n_0 ;
wire \m_payload_i[59]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[60]_i_1__0_n_0 ;
wire \m_payload_i[61]_i_1__0_n_0 ;
wire \m_payload_i[62]_i_1__0_n_0 ;
wire \m_payload_i[63]_i_1__0_n_0 ;
wire \m_payload_i[64]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first_2;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3__0_n_0 ;
wire [2:0]\wrap_cnt_r_reg[3] ;
wire \wrap_cnt_r_reg[3]_0 ;
wire [0:0]wrap_second_len_1;
wire \wrap_second_len_r[0]_i_2__0_n_0 ;
wire \wrap_second_len_r[0]_i_3__0_n_0 ;
wire \wrap_second_len_r[0]_i_4__0_n_0 ;
wire \wrap_second_len_r[3]_i_2__0_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [0]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_7 ),
.O(\axaddr_incr[0]_i_10__0_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14__0_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_3__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_4__0_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first_2),
.O(\axaddr_incr[0]_i_6__0_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [3]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_4 ),
.O(\axaddr_incr[0]_i_7__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8__0
(.I0(Q[36]),
.I1(Q[35]),
.I2(\axaddr_incr_reg[3]_0 [2]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_5 ),
.O(\axaddr_incr[0]_i_8__0_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9__0
(.I0(Q[35]),
.I1(Q[36]),
.I2(\axaddr_incr_reg[3]_0 [1]),
.I3(sel_first_2),
.I4(\axaddr_incr_reg[0]_i_11__0_n_6 ),
.O(\axaddr_incr[0]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10__0
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7__0
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8__0
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9__0
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10__0
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7__0
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8__0
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8__0_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9__0
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9__0_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11__0_n_0 ,\axaddr_incr_reg[0]_i_11__0_n_1 ,\axaddr_incr_reg[0]_i_11__0_n_2 ,\axaddr_incr_reg[0]_i_11__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12__0_n_0 ,\axaddr_incr[0]_i_13__0_n_0 ,\axaddr_incr[0]_i_14__0_n_0 }),
.O({\axaddr_incr_reg[0]_i_11__0_n_4 ,\axaddr_incr_reg[0]_i_11__0_n_5 ,\axaddr_incr_reg[0]_i_11__0_n_6 ,\axaddr_incr_reg[0]_i_11__0_n_7 }),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[0]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[7]_0 ,\axaddr_incr_reg[0]_i_2__0_n_1 ,\axaddr_incr_reg[0]_i_2__0_n_2 ,\axaddr_incr_reg[0]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3__0_n_0 ,\axaddr_incr[0]_i_4__0_n_0 ,\axaddr_incr[0]_i_5__0_n_0 ,\axaddr_incr[0]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S({\axaddr_incr[0]_i_7__0_n_0 ,\axaddr_incr[0]_i_8__0_n_0 ,\axaddr_incr[0]_i_9__0_n_0 ,\axaddr_incr[0]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6__0
(.CI(\axaddr_incr_reg[0]_i_11__0_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6__0_n_0 ,\axaddr_incr_reg[4]_i_6__0_n_1 ,\axaddr_incr_reg[4]_i_6__0_n_2 ,\axaddr_incr_reg[4]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S({\axaddr_incr[4]_i_7__0_n_0 ,\axaddr_incr[4]_i_8__0_n_0 ,\axaddr_incr[4]_i_9__0_n_0 ,\axaddr_incr[4]_i_10__0_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6__0
(.CI(\axaddr_incr_reg[4]_i_6__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6__0_n_1 ,\axaddr_incr_reg[8]_i_6__0_n_2 ,\axaddr_incr_reg[8]_i_6__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] ),
.S({\axaddr_incr[8]_i_7__0_n_0 ,\axaddr_incr[8]_i_8__0_n_0 ,\axaddr_incr[8]_i_9__0_n_0 ,\axaddr_incr[8]_i_10__0_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I1(\axaddr_offset_r[1]_i_2__0_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2__0
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2__0
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_araddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first_2),
.O(\m_axi_araddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__1
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1__0
(.I0(s_axi_arlen[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(\m_payload_i[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1__0
(.I0(s_axi_arlen[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(\m_payload_i[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arlen[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arlen[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1__0
(.I0(s_axi_arid[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(\m_payload_i[54]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1__0
(.I0(s_axi_arid[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(\m_payload_i[55]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1__0
(.I0(s_axi_arid[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(\m_payload_i[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1__0
(.I0(s_axi_arid[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(\m_payload_i[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1__0
(.I0(s_axi_arid[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(\m_payload_i[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1__0
(.I0(s_axi_arid[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(\m_payload_i[59]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1__0
(.I0(s_axi_arid[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(\m_payload_i[60]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1__0
(.I0(s_axi_arid[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(\m_payload_i[61]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1__0
(.I0(s_axi_arid[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(\m_payload_i[62]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1__0
(.I0(s_axi_arid[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(\m_payload_i[63]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1__0
(.I0(s_axi_arid[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(\m_payload_i[64]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__0_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__1_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[48]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[49]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[54]_i_1__0_n_0 ),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[55]_i_1__0_n_0 ),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[56]_i_1__0_n_0 ),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[57]_i_1__0_n_0 ),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[58]_i_1__0_n_0 ),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[59]_i_1__0_n_0 ),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[60]_i_1__0_n_0 ),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[61]_i_1__0_n_0 ),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[62]_i_1__0_n_0 ),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[63]_i_1__0_n_0 ),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[64]_i_1__0_n_0 ),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFFBBBB))
m_valid_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT5 #(
.INIT(32'hFFFFFFFD))
next_pending_r_i_2__1
(.I0(next_pending_r_reg_0),
.I1(Q[46]),
.I2(Q[44]),
.I3(Q[45]),
.I4(Q[43]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__2
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_cnt_r_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3]_0 ),
.I2(wrap_second_len_1),
.O(\wrap_cnt_r_reg[3] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len_1),
.I2(\wrap_cnt_r_reg[3]_0 ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_cnt_r[3]_i_3__0_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3]_0 ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3__0
(.I0(\axaddr_offset_r[0]_i_2__0_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(s_ready_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r[0]_i_2__0_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(s_ready_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2__0
(.I0(\wrap_second_len_r[0]_i_4__0_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2__0_n_0 ),
.O(\wrap_second_len_r[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3__0
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2__0_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4__0
(.I0(Q[39]),
.I1(\state_reg[1] [0]),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1] [1]),
.O(\wrap_second_len_r[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1__0
(.I0(\state_reg[1]_rep ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2__0_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2__0_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
Q,
\axaddr_incr_reg[11] ,
CO,
O,
D,
\wrap_second_len_r_reg[3] ,
\wrap_cnt_r_reg[3] ,
\axaddr_offset_r_reg[1] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[2] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\m_axi_awaddr[10] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
\state_reg[0]_rep ,
\state_reg[1]_rep ,
b_push,
s_axi_awvalid,
S,
\wrap_second_len_r_reg[3]_0 ,
\state_reg[1] ,
wrap_second_len,
\axaddr_offset_r_reg[3]_0 ,
\state_reg[1]_rep_0 ,
\axaddr_offset_r_reg[3]_1 ,
sel_first,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
axaddr_incr_reg,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [58:0]Q;
output [7:0]\axaddr_incr_reg[11] ;
output [0:0]CO;
output [3:0]O;
output [2:0]D;
output [2:0]\wrap_second_len_r_reg[3] ;
output \wrap_cnt_r_reg[3] ;
output \axaddr_offset_r_reg[1] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[2] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \m_axi_awaddr[10] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input \state_reg[0]_rep ;
input \state_reg[1]_rep ;
input b_push;
input s_axi_awvalid;
input [3:0]S;
input [2:0]\wrap_second_len_r_reg[3]_0 ;
input [1:0]\state_reg[1] ;
input [0:0]wrap_second_len;
input [0:0]\axaddr_offset_r_reg[3]_0 ;
input \state_reg[1]_rep_0 ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input sel_first;
input [11:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [3:0]axaddr_incr_reg;
input [0:0]E;
wire [3:0]C;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]O;
wire [58:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire \axaddr_incr[0]_i_10_n_0 ;
wire \axaddr_incr[0]_i_12_n_0 ;
wire \axaddr_incr[0]_i_13_n_0 ;
wire \axaddr_incr[0]_i_14_n_0 ;
wire \axaddr_incr[0]_i_3_n_0 ;
wire \axaddr_incr[0]_i_4_n_0 ;
wire \axaddr_incr[0]_i_5_n_0 ;
wire \axaddr_incr[0]_i_6_n_0 ;
wire \axaddr_incr[0]_i_7_n_0 ;
wire \axaddr_incr[0]_i_8_n_0 ;
wire \axaddr_incr[0]_i_9_n_0 ;
wire \axaddr_incr[4]_i_10_n_0 ;
wire \axaddr_incr[4]_i_7_n_0 ;
wire \axaddr_incr[4]_i_8_n_0 ;
wire \axaddr_incr[4]_i_9_n_0 ;
wire \axaddr_incr[8]_i_10_n_0 ;
wire \axaddr_incr[8]_i_7_n_0 ;
wire \axaddr_incr[8]_i_8_n_0 ;
wire \axaddr_incr[8]_i_9_n_0 ;
wire [3:0]axaddr_incr_reg;
wire \axaddr_incr_reg[0]_i_11_n_0 ;
wire \axaddr_incr_reg[0]_i_11_n_1 ;
wire \axaddr_incr_reg[0]_i_11_n_2 ;
wire \axaddr_incr_reg[0]_i_11_n_3 ;
wire \axaddr_incr_reg[0]_i_2_n_1 ;
wire \axaddr_incr_reg[0]_i_2_n_2 ;
wire \axaddr_incr_reg[0]_i_2_n_3 ;
wire [7:0]\axaddr_incr_reg[11] ;
wire \axaddr_incr_reg[4]_i_6_n_0 ;
wire \axaddr_incr_reg[4]_i_6_n_1 ;
wire \axaddr_incr_reg[4]_i_6_n_2 ;
wire \axaddr_incr_reg[4]_i_6_n_3 ;
wire \axaddr_incr_reg[8]_i_6_n_1 ;
wire \axaddr_incr_reg[8]_i_6_n_2 ;
wire \axaddr_incr_reg[8]_i_6_n_3 ;
wire \axaddr_offset_r[0]_i_2_n_0 ;
wire \axaddr_offset_r[1]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire \m_axi_awaddr[10] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire sel_first;
wire [64:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[54] ;
wire \skid_buffer_reg_n_0_[55] ;
wire \skid_buffer_reg_n_0_[56] ;
wire \skid_buffer_reg_n_0_[57] ;
wire \skid_buffer_reg_n_0_[58] ;
wire \skid_buffer_reg_n_0_[59] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[60] ;
wire \skid_buffer_reg_n_0_[61] ;
wire \skid_buffer_reg_n_0_[62] ;
wire \skid_buffer_reg_n_0_[63] ;
wire \skid_buffer_reg_n_0_[64] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_cnt_r[3]_i_3_n_0 ;
wire \wrap_cnt_r_reg[3] ;
wire [0:0]wrap_second_len;
wire \wrap_second_len_r[0]_i_2_n_0 ;
wire \wrap_second_len_r[0]_i_3_n_0 ;
wire \wrap_second_len_r[0]_i_4_n_0 ;
wire \wrap_second_len_r[3]_i_2_n_0 ;
wire [2:0]\wrap_second_len_r_reg[3] ;
wire [2:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:3]\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT5 #(
.INIT(32'hFFE100E1))
\axaddr_incr[0]_i_10
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[0]),
.I3(sel_first),
.I4(C[0]),
.O(\axaddr_incr[0]_i_10_n_0 ));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[0]_i_12
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_12_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[0]_i_13
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[0]_i_13_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[0]_i_14
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[0]_i_14_n_0 ));
LUT3 #(
.INIT(8'h08))
\axaddr_incr[0]_i_3
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_3_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_4
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_4_n_0 ));
LUT3 #(
.INIT(8'h04))
\axaddr_incr[0]_i_5
(.I0(Q[36]),
.I1(Q[35]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_5_n_0 ));
LUT3 #(
.INIT(8'h01))
\axaddr_incr[0]_i_6
(.I0(Q[35]),
.I1(Q[36]),
.I2(sel_first),
.O(\axaddr_incr[0]_i_6_n_0 ));
LUT5 #(
.INIT(32'hFF780078))
\axaddr_incr[0]_i_7
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[3]),
.I3(sel_first),
.I4(C[3]),
.O(\axaddr_incr[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_8
(.I0(Q[36]),
.I1(Q[35]),
.I2(axaddr_incr_reg[2]),
.I3(sel_first),
.I4(C[2]),
.O(\axaddr_incr[0]_i_8_n_0 ));
LUT5 #(
.INIT(32'hFFD200D2))
\axaddr_incr[0]_i_9
(.I0(Q[35]),
.I1(Q[36]),
.I2(axaddr_incr_reg[1]),
.I3(sel_first),
.I4(C[1]),
.O(\axaddr_incr[0]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_10
(.I0(Q[4]),
.O(\axaddr_incr[4]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_7
(.I0(Q[7]),
.O(\axaddr_incr[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_8
(.I0(Q[6]),
.O(\axaddr_incr[4]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[4]_i_9
(.I0(Q[5]),
.O(\axaddr_incr[4]_i_9_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_10
(.I0(Q[8]),
.O(\axaddr_incr[8]_i_10_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_7
(.I0(Q[11]),
.O(\axaddr_incr[8]_i_7_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_8
(.I0(Q[10]),
.O(\axaddr_incr[8]_i_8_n_0 ));
LUT1 #(
.INIT(2'h2))
\axaddr_incr[8]_i_9
(.I0(Q[9]),
.O(\axaddr_incr[8]_i_9_n_0 ));
CARRY4 \axaddr_incr_reg[0]_i_11
(.CI(1'b0),
.CO({\axaddr_incr_reg[0]_i_11_n_0 ,\axaddr_incr_reg[0]_i_11_n_1 ,\axaddr_incr_reg[0]_i_11_n_2 ,\axaddr_incr_reg[0]_i_11_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[0]_i_12_n_0 ,\axaddr_incr[0]_i_13_n_0 ,\axaddr_incr[0]_i_14_n_0 }),
.O(C),
.S(S));
CARRY4 \axaddr_incr_reg[0]_i_2
(.CI(1'b0),
.CO({CO,\axaddr_incr_reg[0]_i_2_n_1 ,\axaddr_incr_reg[0]_i_2_n_2 ,\axaddr_incr_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_incr[0]_i_3_n_0 ,\axaddr_incr[0]_i_4_n_0 ,\axaddr_incr[0]_i_5_n_0 ,\axaddr_incr[0]_i_6_n_0 }),
.O(O),
.S({\axaddr_incr[0]_i_7_n_0 ,\axaddr_incr[0]_i_8_n_0 ,\axaddr_incr[0]_i_9_n_0 ,\axaddr_incr[0]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[4]_i_6
(.CI(\axaddr_incr_reg[0]_i_11_n_0 ),
.CO({\axaddr_incr_reg[4]_i_6_n_0 ,\axaddr_incr_reg[4]_i_6_n_1 ,\axaddr_incr_reg[4]_i_6_n_2 ,\axaddr_incr_reg[4]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [3:0]),
.S({\axaddr_incr[4]_i_7_n_0 ,\axaddr_incr[4]_i_8_n_0 ,\axaddr_incr[4]_i_9_n_0 ,\axaddr_incr[4]_i_10_n_0 }));
CARRY4 \axaddr_incr_reg[8]_i_6
(.CI(\axaddr_incr_reg[4]_i_6_n_0 ),
.CO({\NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED [3],\axaddr_incr_reg[8]_i_6_n_1 ,\axaddr_incr_reg[8]_i_6_n_2 ,\axaddr_incr_reg[8]_i_6_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[11] [7:4]),
.S({\axaddr_incr[8]_i_7_n_0 ,\axaddr_incr[8]_i_8_n_0 ,\axaddr_incr[8]_i_9_n_0 ,\axaddr_incr[8]_i_10_n_0 }));
LUT6 #(
.INIT(64'hF0F0F0F0F088F0F0))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\axaddr_offset_r_reg[3]_1 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\axaddr_offset_r_reg[0] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r[2]_i_3_n_0 ),
.I1(\axaddr_offset_r[1]_i_2_n_0 ),
.I2(Q[35]),
.I3(Q[40]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [1]),
.O(\axaddr_offset_r_reg[1] ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_2
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAC00FFFFAC000000))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(\axaddr_offset_r[2]_i_3_n_0 ),
.I2(Q[35]),
.I3(Q[41]),
.I4(\state_reg[1]_rep_0 ),
.I5(\axaddr_offset_r_reg[3]_1 [2]),
.O(\axaddr_offset_r_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\axlen_cnt_reg[3] ));
LUT2 #(
.INIT(4'h2))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(Q[37]),
.I1(sel_first),
.O(\m_axi_awaddr[10] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(s_axi_awlen[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(s_axi_awlen[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awlen[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awlen[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[54]_i_1
(.I0(s_axi_awid[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[54] ),
.O(skid_buffer[54]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[55]_i_1
(.I0(s_axi_awid[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[55] ),
.O(skid_buffer[55]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[56]_i_1
(.I0(s_axi_awid[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[56] ),
.O(skid_buffer[56]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[57]_i_1
(.I0(s_axi_awid[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[57] ),
.O(skid_buffer[57]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[58]_i_1
(.I0(s_axi_awid[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[58] ),
.O(skid_buffer[58]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[59]_i_1
(.I0(s_axi_awid[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[59] ),
.O(skid_buffer[59]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[60]_i_1
(.I0(s_axi_awid[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[60] ),
.O(skid_buffer[60]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[61]_i_1
(.I0(s_axi_awid[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[61] ),
.O(skid_buffer[61]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[62]_i_1
(.I0(s_axi_awid[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[62] ),
.O(skid_buffer[62]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[63]_i_1
(.I0(s_axi_awid[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[63] ),
.O(skid_buffer[63]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[64]_i_1
(.I0(s_axi_awid[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[64] ),
.O(skid_buffer[64]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[54]
(.C(aclk),
.CE(E),
.D(skid_buffer[54]),
.Q(Q[48]),
.R(1'b0));
FDRE \m_payload_i_reg[55]
(.C(aclk),
.CE(E),
.D(skid_buffer[55]),
.Q(Q[49]),
.R(1'b0));
FDRE \m_payload_i_reg[56]
(.C(aclk),
.CE(E),
.D(skid_buffer[56]),
.Q(Q[50]),
.R(1'b0));
FDRE \m_payload_i_reg[57]
(.C(aclk),
.CE(E),
.D(skid_buffer[57]),
.Q(Q[51]),
.R(1'b0));
FDRE \m_payload_i_reg[58]
(.C(aclk),
.CE(E),
.D(skid_buffer[58]),
.Q(Q[52]),
.R(1'b0));
FDRE \m_payload_i_reg[59]
(.C(aclk),
.CE(E),
.D(skid_buffer[59]),
.Q(Q[53]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[60]
(.C(aclk),
.CE(E),
.D(skid_buffer[60]),
.Q(Q[54]),
.R(1'b0));
FDRE \m_payload_i_reg[61]
(.C(aclk),
.CE(E),
.D(skid_buffer[61]),
.Q(Q[55]),
.R(1'b0));
FDRE \m_payload_i_reg[62]
(.C(aclk),
.CE(E),
.D(skid_buffer[62]),
.Q(Q[56]),
.R(1'b0));
FDRE \m_payload_i_reg[63]
(.C(aclk),
.CE(E),
.D(skid_buffer[63]),
.Q(Q[57]),
.R(1'b0));
FDRE \m_payload_i_reg[64]
(.C(aclk),
.CE(E),
.D(skid_buffer[64]),
.Q(Q[58]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
next_pending_r_i_2
(.I0(next_pending_r_reg_0),
.I1(Q[43]),
.I2(Q[44]),
.I3(Q[46]),
.I4(Q[45]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2__0
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hBFBB))
s_ready_i_i_2
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[0]),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[54]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[1]),
.Q(\skid_buffer_reg_n_0_[54] ),
.R(1'b0));
FDRE \skid_buffer_reg[55]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[2]),
.Q(\skid_buffer_reg_n_0_[55] ),
.R(1'b0));
FDRE \skid_buffer_reg[56]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[3]),
.Q(\skid_buffer_reg_n_0_[56] ),
.R(1'b0));
FDRE \skid_buffer_reg[57]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[4]),
.Q(\skid_buffer_reg_n_0_[57] ),
.R(1'b0));
FDRE \skid_buffer_reg[58]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[5]),
.Q(\skid_buffer_reg_n_0_[58] ),
.R(1'b0));
FDRE \skid_buffer_reg[59]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[6]),
.Q(\skid_buffer_reg_n_0_[59] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[60]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[7]),
.Q(\skid_buffer_reg_n_0_[60] ),
.R(1'b0));
FDRE \skid_buffer_reg[61]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[8]),
.Q(\skid_buffer_reg_n_0_[61] ),
.R(1'b0));
FDRE \skid_buffer_reg[62]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[9]),
.Q(\skid_buffer_reg_n_0_[62] ),
.R(1'b0));
FDRE \skid_buffer_reg[63]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[10]),
.Q(\skid_buffer_reg_n_0_[63] ),
.R(1'b0));
FDRE \skid_buffer_reg[64]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid[11]),
.Q(\skid_buffer_reg_n_0_[64] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'hA0A0202AAAAA202A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[40]),
.I2(Q[35]),
.I3(Q[41]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A882A222AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[40]),
.I5(Q[41]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'hBBBBBABBCCCCC0CC))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'h9A))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [1]),
.I1(\wrap_cnt_r_reg[3] ),
.I2(wrap_second_len),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(wrap_second_len),
.I2(\wrap_cnt_r_reg[3] ),
.I3(\wrap_second_len_r_reg[3] [1]),
.O(D[2]));
LUT5 #(
.INIT(32'hAAAAAAAB))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_cnt_r[3]_i_3_n_0 ),
.I1(\axaddr_offset_r_reg[1] ),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[3]_0 ),
.I4(\axaddr_offset_r_reg[2] ),
.O(\wrap_cnt_r_reg[3] ));
LUT6 #(
.INIT(64'h0F0F0F0F0F880F0F))
\wrap_cnt_r[3]_i_3
(.I0(\axaddr_offset_r[0]_i_2_n_0 ),
.I1(Q[39]),
.I2(\wrap_second_len_r_reg[3]_0 [0]),
.I3(\state_reg[1] [1]),
.I4(m_valid_i_reg_0),
.I5(\state_reg[1] [0]),
.O(\wrap_cnt_r[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h4444454444444044))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r[0]_i_2_n_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(\state_reg[1] [0]),
.I3(m_valid_i_reg_0),
.I4(\state_reg[1] [1]),
.I5(\wrap_second_len_r[0]_i_3_n_0 ),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAAAA8080000A808))
\wrap_second_len_r[0]_i_2
(.I0(\wrap_second_len_r[0]_i_4_n_0 ),
.I1(Q[0]),
.I2(Q[36]),
.I3(Q[2]),
.I4(Q[35]),
.I5(\axaddr_offset_r[1]_i_2_n_0 ),
.O(\wrap_second_len_r[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFBA))
\wrap_second_len_r[0]_i_3
(.I0(\axaddr_offset_r_reg[2] ),
.I1(\state_reg[1]_rep_0 ),
.I2(\axaddr_offset_r_reg[3]_1 [3]),
.I3(\wrap_second_len_r[3]_i_2_n_0 ),
.I4(\axaddr_offset_r_reg[0] ),
.I5(\axaddr_offset_r_reg[1] ),
.O(\wrap_second_len_r[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT4 #(
.INIT(16'h0020))
\wrap_second_len_r[0]_i_4
(.I0(Q[39]),
.I1(\state_reg[0]_rep ),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_rep ),
.O(\wrap_second_len_r[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'hEE10FFFFEE100000))
\wrap_second_len_r[2]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.I1(\axaddr_offset_r_reg[0] ),
.I2(\axaddr_offset_r_reg[3]_0 ),
.I3(\axaddr_offset_r_reg[2] ),
.I4(\state_reg[1]_rep_0 ),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hFFFFFFF444444444))
\wrap_second_len_r[3]_i_1
(.I0(\state_reg[1]_rep_0 ),
.I1(\wrap_second_len_r_reg[3]_0 [2]),
.I2(\axaddr_offset_r_reg[0] ),
.I3(\axaddr_offset_r_reg[1] ),
.I4(\axaddr_offset_r_reg[2] ),
.I5(\wrap_second_len_r[3]_i_2_n_0 ),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r[3]_i_2_n_0 ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(s_axi_bvalid,
\skid_buffer_reg[0]_0 ,
\s_axi_bid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
si_rs_bvalid,
s_axi_bready,
out,
\s_bresp_acc_reg[1] );
output s_axi_bvalid;
output \skid_buffer_reg[0]_0 ;
output [13:0]\s_axi_bid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input si_rs_bvalid;
input s_axi_bready;
input [11:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_2_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i0;
wire [11:0]out;
wire p_1_in;
wire [13:0]\s_axi_bid[11] ;
wire s_axi_bready;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(out[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(out[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(out[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[13]_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_2
(.I0(out[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(out[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(out[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(out[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(out[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(out[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(out[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(out[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(out[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_2_n_0 ),
.Q(\s_axi_bid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_bid[11] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[8]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[9]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[10]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[11]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\s_bresp_acc_reg[1] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[0]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[1]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[2]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[3]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[4]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[5]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[6]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(out[7]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module zynq_design_1_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[3]_rep__0 ,
\s_axi_rid[11] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
\cnt_read_reg[4]_rep__0 ,
s_axi_rready,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[3]_rep__0 ;
output [46:0]\s_axi_rid[11] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input \cnt_read_reg[4]_rep__0 ;
input s_axi_rready;
input [12:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[3]_rep__0 ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__0 ;
wire \m_payload_i[0]_i_1__2_n_0 ;
wire \m_payload_i[10]_i_1__2_n_0 ;
wire \m_payload_i[11]_i_1__2_n_0 ;
wire \m_payload_i[12]_i_1__2_n_0 ;
wire \m_payload_i[13]_i_1__2_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__2_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__2_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__1_n_0 ;
wire \m_payload_i[37]_i_1_n_0 ;
wire \m_payload_i[38]_i_1__1_n_0 ;
wire \m_payload_i[39]_i_1__1_n_0 ;
wire \m_payload_i[3]_i_1__2_n_0 ;
wire \m_payload_i[40]_i_1_n_0 ;
wire \m_payload_i[41]_i_1_n_0 ;
wire \m_payload_i[42]_i_1_n_0 ;
wire \m_payload_i[43]_i_1_n_0 ;
wire \m_payload_i[44]_i_1__1_n_0 ;
wire \m_payload_i[45]_i_1__1_n_0 ;
wire \m_payload_i[46]_i_2_n_0 ;
wire \m_payload_i[4]_i_1__2_n_0 ;
wire \m_payload_i[5]_i_1__2_n_0 ;
wire \m_payload_i[6]_i_1__2_n_0 ;
wire \m_payload_i[7]_i_1__2_n_0 ;
wire \m_payload_i[8]_i_1__2_n_0 ;
wire \m_payload_i[9]_i_1__2_n_0 ;
wire m_valid_i_i_1__1_n_0;
wire p_1_in;
wire [12:0]r_push_r_reg;
wire [46:0]\s_axi_rid[11] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__0 ),
.O(\cnt_read_reg[3]_rep__0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__2
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__2
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__2
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__2
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__2
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__2
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(r_push_r_reg[2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(r_push_r_reg[3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(\m_payload_i[37]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(r_push_r_reg[4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(r_push_r_reg[5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__2
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(r_push_r_reg[6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(\m_payload_i[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(r_push_r_reg[7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(\m_payload_i[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(r_push_r_reg[8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(\m_payload_i[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(r_push_r_reg[9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(\m_payload_i[43]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(r_push_r_reg[10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(r_push_r_reg[11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[46]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(r_push_r_reg[12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__2
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__2
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__2
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__2
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__2
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__2
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__2_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[36]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[37]_i_1_n_0 ),
.Q(\s_axi_rid[11] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[38]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[39]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[40]_i_1_n_0 ),
.Q(\s_axi_rid[11] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[41]_i_1_n_0 ),
.Q(\s_axi_rid[11] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[42]_i_1_n_0 ),
.Q(\s_axi_rid[11] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[43]_i_1_n_0 ),
.Q(\s_axi_rid[11] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[44]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[45]_i_1__1_n_0 ),
.Q(\s_axi_rid[11] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[46]_i_2_n_0 ),
.Q(\s_axi_rid[11] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__2_n_0 ),
.Q(\s_axi_rid[11] [9]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\cnt_read_reg[4]_rep__0 ),
.I3(\skid_buffer_reg[0]_0 ),
.O(m_valid_i_i_1__1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\cnt_read_reg[4]_rep__0 ),
.I1(\skid_buffer_reg[0]_0 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[2]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[3]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[4]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[5]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[6]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[7]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[8]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[9]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[10]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[11]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[12]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
//Date : Sat Sep 23 22:44:16 2017
//Host : DarkCube running 64-bit major release (build 9200)
//Command : generate_target zqynq_lab_1_design_wrapper.bd
//Design : zqynq_lab_1_design_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module zqynq_lab_1_design_wrapper
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb,
btns_5bits_tri_i,
leds_8bits_tri_o);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
input [4:0]btns_5bits_tri_i;
output [7:0]leds_8bits_tri_o;
wire [14:0]DDR_addr;
wire [2:0]DDR_ba;
wire DDR_cas_n;
wire DDR_ck_n;
wire DDR_ck_p;
wire DDR_cke;
wire DDR_cs_n;
wire [3:0]DDR_dm;
wire [31:0]DDR_dq;
wire [3:0]DDR_dqs_n;
wire [3:0]DDR_dqs_p;
wire DDR_odt;
wire DDR_ras_n;
wire DDR_reset_n;
wire DDR_we_n;
wire FIXED_IO_ddr_vrn;
wire FIXED_IO_ddr_vrp;
wire [53:0]FIXED_IO_mio;
wire FIXED_IO_ps_clk;
wire FIXED_IO_ps_porb;
wire FIXED_IO_ps_srstb;
wire [4:0]btns_5bits_tri_i;
wire [7:0]leds_8bits_tri_o;
zqynq_lab_1_design zqynq_lab_1_design_i
(.DDR_addr(DDR_addr),
.DDR_ba(DDR_ba),
.DDR_cas_n(DDR_cas_n),
.DDR_ck_n(DDR_ck_n),
.DDR_ck_p(DDR_ck_p),
.DDR_cke(DDR_cke),
.DDR_cs_n(DDR_cs_n),
.DDR_dm(DDR_dm),
.DDR_dq(DDR_dq),
.DDR_dqs_n(DDR_dqs_n),
.DDR_dqs_p(DDR_dqs_p),
.DDR_odt(DDR_odt),
.DDR_ras_n(DDR_ras_n),
.DDR_reset_n(DDR_reset_n),
.DDR_we_n(DDR_we_n),
.FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
.FIXED_IO_mio(FIXED_IO_mio),
.FIXED_IO_ps_clk(FIXED_IO_ps_clk),
.FIXED_IO_ps_porb(FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb(FIXED_IO_ps_srstb),
.btns_5bits_tri_i(btns_5bits_tri_i),
.leds_8bits_tri_o(leds_8bits_tri_o));
endmodule
|
`include "src/rom.v"
`include "src/serializer.v"
`include "src/transmitter.v"
`include "src/receiver.v"
`include "src/comparator.v"
`include "src/iserdes_sdr_ddr_test.v"
`default_nettype none
// ============================================================================
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led,
inout wire [9:0] io
);
// ============================================================================
// Clock & reset
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0])
rst_sr <= 4'hF;
else
rst_sr <= rst_sr >> 1;
wire CLK = clk;
wire RST = rst_sr[0];
// ============================================================================
// Test uints
wire [9:0] error;
genvar i;
generate for (i=0; i<10; i=i+1) begin
localparam DATA_WIDTH = (i == 0) ? 2 :
(i == 1) ? 3 :
(i == 2) ? 4 :
(i == 3) ? 5 :
(i == 4) ? 6 :
(i == 5) ? 7 :
(i == 6) ? 8 :
(i == 7) ? 4 :
(i == 8) ? 6 :
/*(i == 9) ?*/ 8;
localparam DATA_RATE = (i < 7) ? "SDR" : "DDR";
iserdes_sdr_ddr_test #
(
.DATA_WIDTH (DATA_WIDTH),
.DATA_RATE (DATA_RATE)
)
iserdes_test
(
.CLK (CLK),
.RST (RST),
.IO_DAT (io[i]),
.O_ERROR (error[i])
);
end endgenerate
// ============================================================================
// I/O connections
reg [23:0] heartbeat_cnt;
always @(posedge CLK)
heartbeat_cnt <= heartbeat_cnt + 1;
assign led[9: 0] = (RST) ? 9'd0 : ~error;
assign led[ 10] = heartbeat_cnt[22];
assign led[15:11] = 0;
endmodule
|
/*
* Copyright (c) Mercury Federal Systems, Inc., Arlington VA., 2009-2010
*
* Mercury Federal Systems, Incorporated
* 1901 South Bell Street
* Suite 402
* Arlington, Virginia 22202
* United States of America
* Telephone 703-413-0781
* FAX 703-413-0784
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
//
// Generated by Bluespec Compiler, version 2009.11.beta2 (build 18693, 2009-11-24)
//
// On Thu Aug 19 14:08:06 EDT 2010
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 32 reg
// wsiM0_MByteEn O 4 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 20
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 32
// wsiS0_MByteEn I 4
// wsiS0_MReqInfo I 8
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef ORIGINAL
module mkPSD(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n);
parameter [31 : 0] psdCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [19 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [31 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [3 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [31 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [3 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// signals for module outputs
wire [31 : 0] wciS0_SData, wsiM0_MData;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [3 : 0] wsiM0_MByteEn;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
`else
`define NOT_EMPTY_psd.v
`include "psd_defs.v"
`endif
// inlined wires
wire [95 : 0] wsiM_extStatusW$wget, wsiS_extStatusW$wget;
wire [60 : 0] wsiM_reqFifo_x_wire$wget, wsiS_wsiReq$wget;
wire [59 : 0] wci_wciReq$wget;
wire [33 : 0] wci_respF_x_wire$wget;
wire [31 : 0] w2p_dataF_wDataIn$wget,
w2p_dataF_wDataOut$wget,
wci_Es_mData_w$wget,
wsi_Es_mData_w$wget;
wire [19 : 0] wci_Es_mAddr_w$wget;
wire [15 : 0] fft_xnIm_w$wget, fft_xnRe_w$wget;
wire [11 : 0] fft_scale_w$wget, wsi_Es_mBurstLength_w$wget;
wire [7 : 0] wsi_Es_mReqInfo_w$wget;
wire [3 : 0] wci_Es_mByteEn_w$wget, wsi_Es_mByteEn_w$wget;
wire [2 : 0] wci_Es_mCmd_w$wget, wci_wEdge$wget, wsi_Es_mCmd_w$wget;
wire fft_fwd_w$wget,
fft_fwd_w$whas,
fft_fwd_we_w$wget,
fft_fwd_we_w$whas,
fft_scale_w$whas,
fft_scale_we_w$wget,
fft_scale_we_w$whas,
fft_start_w$wget,
fft_start_w$whas,
fft_xnIm_w$whas,
fft_xnRe_w$whas,
w2p_dataF_pwDequeue$whas,
w2p_dataF_pwEnqueue$whas,
w2p_dataF_wDataIn$whas,
w2p_dataF_wDataOut$whas,
w2p_operateW$wget,
w2p_operateW$whas,
wci_Es_mAddrSpace_w$wget,
wci_Es_mAddrSpace_w$whas,
wci_Es_mAddr_w$whas,
wci_Es_mByteEn_w$whas,
wci_Es_mCmd_w$whas,
wci_Es_mData_w$whas,
wci_ctlAckReg_1$wget,
wci_ctlAckReg_1$whas,
wci_reqF_r_clr$whas,
wci_reqF_r_deq$whas,
wci_reqF_r_enq$whas,
wci_respF_dequeueing$whas,
wci_respF_enqueueing$whas,
wci_respF_x_wire$whas,
wci_sFlagReg_1$wget,
wci_sFlagReg_1$whas,
wci_sThreadBusy_pw$whas,
wci_wEdge$whas,
wci_wciReq$whas,
wci_wci_cfrd_pw$whas,
wci_wci_cfwr_pw$whas,
wci_wci_ctrl_pw$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wsiS_operateD_1$wget,
wsiS_operateD_1$whas,
wsiS_peerIsReady_1$wget,
wsiS_peerIsReady_1$whas,
wsiS_reqFifo_doResetClr$whas,
wsiS_reqFifo_doResetDeq$whas,
wsiS_reqFifo_doResetEnq$whas,
wsiS_reqFifo_r_clr$whas,
wsiS_reqFifo_r_deq$whas,
wsiS_reqFifo_r_enq$whas,
wsiS_sThreadBusy_dw$wget,
wsiS_sThreadBusy_dw$whas,
wsiS_wsiReq$whas,
wsi_Es_mBurstLength_w$whas,
wsi_Es_mBurstPrecise_w$whas,
wsi_Es_mByteEn_w$whas,
wsi_Es_mCmd_w$whas,
wsi_Es_mDataInfo_w$whas,
wsi_Es_mData_w$whas,
wsi_Es_mReqInfo_w$whas,
wsi_Es_mReqLast_w$whas;
// register evenMag
reg [15 : 0] evenMag;
wire [15 : 0] evenMag$D_IN;
wire evenMag$EN;
// register fft_fftStarted
reg fft_fftStarted;
wire fft_fftStarted$D_IN, fft_fftStarted$EN;
// register fft_loadFrames
reg [15 : 0] fft_loadFrames;
wire [15 : 0] fft_loadFrames$D_IN;
wire fft_loadFrames$EN;
// register fft_loadIndex
reg [15 : 0] fft_loadIndex;
wire [15 : 0] fft_loadIndex$D_IN;
wire fft_loadIndex$EN;
// register fft_unloadFrames
reg [15 : 0] fft_unloadFrames;
wire [15 : 0] fft_unloadFrames$D_IN;
wire fft_unloadFrames$EN;
// register fft_unloadIndex
reg [15 : 0] fft_unloadIndex;
wire [15 : 0] fft_unloadIndex$D_IN;
wire fft_unloadIndex$EN;
// register psdCtrl
reg [31 : 0] psdCtrl;
wire [31 : 0] psdCtrl$D_IN;
wire psdCtrl$EN;
// register sendEven
reg sendEven;
wire sendEven$D_IN, sendEven$EN;
// register takeEven
reg takeEven;
wire takeEven$D_IN, takeEven$EN;
// register unloadCnt
reg [15 : 0] unloadCnt;
wire [15 : 0] unloadCnt$D_IN;
wire unloadCnt$EN;
// register w2p_dataF_rCache
reg [45 : 0] w2p_dataF_rCache;
wire [45 : 0] w2p_dataF_rCache$D_IN;
wire w2p_dataF_rCache$EN;
// register w2p_dataF_rRdPtr
reg [12 : 0] w2p_dataF_rRdPtr;
wire [12 : 0] w2p_dataF_rRdPtr$D_IN;
wire w2p_dataF_rRdPtr$EN;
// register w2p_dataF_rWrPtr
reg [12 : 0] w2p_dataF_rWrPtr;
wire [12 : 0] w2p_dataF_rWrPtr$D_IN;
wire w2p_dataF_rWrPtr$EN;
// register w2p_wordsDequed
reg [15 : 0] w2p_wordsDequed;
wire [15 : 0] w2p_wordsDequed$D_IN;
wire w2p_wordsDequed$EN;
// register w2p_wordsEnqued
reg [15 : 0] w2p_wordsEnqued;
wire [15 : 0] w2p_wordsEnqued$D_IN;
wire w2p_wordsEnqued$EN;
// register w2p_wordsExact
reg [15 : 0] w2p_wordsExact;
wire [15 : 0] w2p_wordsExact$D_IN;
wire w2p_wordsExact$EN;
// register wci_cEdge
reg [2 : 0] wci_cEdge;
wire [2 : 0] wci_cEdge$D_IN;
wire wci_cEdge$EN;
// register wci_cState
reg [2 : 0] wci_cState;
wire [2 : 0] wci_cState$D_IN;
wire wci_cState$EN;
// register wci_ctlAckReg
reg wci_ctlAckReg;
wire wci_ctlAckReg$D_IN, wci_ctlAckReg$EN;
// register wci_ctlOpActive
reg wci_ctlOpActive;
wire wci_ctlOpActive$D_IN, wci_ctlOpActive$EN;
// register wci_illegalEdge
reg wci_illegalEdge;
wire wci_illegalEdge$D_IN, wci_illegalEdge$EN;
// register wci_nState
reg [2 : 0] wci_nState;
reg [2 : 0] wci_nState$D_IN;
wire wci_nState$EN;
// register wci_reqF_countReg
reg [1 : 0] wci_reqF_countReg;
wire [1 : 0] wci_reqF_countReg$D_IN;
wire wci_reqF_countReg$EN;
// register wci_respF_c_r
reg [1 : 0] wci_respF_c_r;
wire [1 : 0] wci_respF_c_r$D_IN;
wire wci_respF_c_r$EN;
// register wci_respF_q_0
reg [33 : 0] wci_respF_q_0;
reg [33 : 0] wci_respF_q_0$D_IN;
wire wci_respF_q_0$EN;
// register wci_respF_q_1
reg [33 : 0] wci_respF_q_1;
reg [33 : 0] wci_respF_q_1$D_IN;
wire wci_respF_q_1$EN;
// register wci_sFlagReg
reg wci_sFlagReg;
wire wci_sFlagReg$D_IN, wci_sFlagReg$EN;
// register wci_sThreadBusy_d
reg wci_sThreadBusy_d;
wire wci_sThreadBusy_d$D_IN, wci_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind$D_IN;
wire wsiS_burstKind$EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky$D_IN, wsiS_errorSticky$EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount$D_IN;
wire wsiS_iMesgCount$EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength$D_IN;
wire wsiS_mesgWordLength$EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD$D_IN, wsiS_operateD$EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount$D_IN;
wire wsiS_pMesgCount$EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady$D_IN, wsiS_peerIsReady$EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg$D_IN;
wire wsiS_reqFifo_countReg$EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid$D_IN, wsiS_reqFifo_levelsValid$EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR$D_IN;
wire wsiS_statusR$EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount$D_IN;
wire wsiS_tBusyCount$EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky$D_IN, wsiS_trafficSticky$EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount$D_IN;
wire wsiS_wordCount$EN;
// ports of submodule fft_fft
wire [15 : 0] fft_fft$xk_im, fft_fft$xk_re, fft_fft$xn_im, fft_fft$xn_re;
wire [11 : 0] fft_fft$scale_sch;
wire fft_fft$dv,
fft_fft$fwd_inv,
fft_fft$fwd_inv_we,
fft_fft$rfd,
fft_fft$scale_sch_we,
fft_fft$start;
// ports of submodule fft_xkF
wire [31 : 0] fft_xkF$D_IN, fft_xkF$D_OUT;
wire fft_xkF$CLR, fft_xkF$DEQ, fft_xkF$EMPTY_N, fft_xkF$ENQ, fft_xkF$FULL_N;
// ports of submodule fft_xnF
wire [31 : 0] fft_xnF$D_IN, fft_xnF$D_OUT;
wire fft_xnF$CLR, fft_xnF$DEQ, fft_xnF$EMPTY_N, fft_xnF$ENQ, fft_xnF$FULL_N;
// ports of submodule w2p_dataF_memory
wire [31 : 0] w2p_dataF_memory$DIA,
w2p_dataF_memory$DIB,
w2p_dataF_memory$DOB;
wire [11 : 0] w2p_dataF_memory$ADDRA, w2p_dataF_memory$ADDRB;
wire w2p_dataF_memory$ENA,
w2p_dataF_memory$ENB,
w2p_dataF_memory$WEA,
w2p_dataF_memory$WEB;
// ports of submodule w2p_inF
wire [60 : 0] w2p_inF$D_IN, w2p_inF$D_OUT;
wire w2p_inF$CLR, w2p_inF$DEQ, w2p_inF$EMPTY_N, w2p_inF$ENQ, w2p_inF$FULL_N;
// ports of submodule w2p_outF
wire [60 : 0] w2p_outF$D_IN, w2p_outF$D_OUT;
wire w2p_outF$CLR,
w2p_outF$DEQ,
w2p_outF$EMPTY_N,
w2p_outF$ENQ,
w2p_outF$FULL_N;
// ports of submodule w2p_reqF
wire [7 : 0] w2p_reqF$D_IN, w2p_reqF$D_OUT;
wire w2p_reqF$CLR,
w2p_reqF$DEQ,
w2p_reqF$EMPTY_N,
w2p_reqF$ENQ,
w2p_reqF$FULL_N;
// ports of submodule wci_isReset
wire wci_isReset$VAL;
// ports of submodule wci_reqF
wire [59 : 0] wci_reqF$D_IN, wci_reqF$D_OUT;
wire wci_reqF$CLR, wci_reqF$DEQ, wci_reqF$EMPTY_N, wci_reqF$ENQ;
// ports of submodule wsiM_isReset
wire wsiM_isReset$VAL;
// ports of submodule wsiS_isReset
wire wsiS_isReset$VAL;
// ports of submodule wsiS_reqFifo
wire [60 : 0] wsiS_reqFifo$D_IN, wsiS_reqFifo$D_OUT;
wire wsiS_reqFifo$CLR,
wsiS_reqFifo$DEQ,
wsiS_reqFifo$EMPTY_N,
wsiS_reqFifo$ENQ,
wsiS_reqFifo$FULL_N;
// ports of submodule xnF
wire [31 : 0] xnF$D_IN, xnF$D_OUT;
wire xnF$CLR, xnF$DEQ, xnF$EMPTY_N, xnF$ENQ, xnF$FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_fft_drive_fft_always_enabled,
CAN_FIRE_RL_fft_fft_stream_egress,
CAN_FIRE_RL_fft_fft_stream_ingress,
CAN_FIRE_RL_fft_frame_start,
CAN_FIRE_RL_operating_actions,
CAN_FIRE_RL_psdFFT_doEgress,
CAN_FIRE_RL_psdFFT_doIngress,
CAN_FIRE_RL_psdPass_bypass,
CAN_FIRE_RL_psdPrecise_input,
CAN_FIRE_RL_psdPrecise_output_bypassFFT,
CAN_FIRE_RL_psdPrecise_output_feedFFT,
CAN_FIRE_RL_w2p_dataF_portA,
CAN_FIRE_RL_w2p_dataF_portB,
CAN_FIRE_RL_w2p_dataF_portB_read_data,
CAN_FIRE_RL_w2p_imprecise_enq,
CAN_FIRE_RL_w2p_precise_deq,
CAN_FIRE_RL_wci_Es_doAlways_Req,
CAN_FIRE_RL_wci_cfrd,
CAN_FIRE_RL_wci_cfwr,
CAN_FIRE_RL_wci_ctlAckReg__dreg_update,
CAN_FIRE_RL_wci_ctl_op_complete,
CAN_FIRE_RL_wci_ctl_op_start,
CAN_FIRE_RL_wci_ctrl_EiI,
CAN_FIRE_RL_wci_ctrl_IsO,
CAN_FIRE_RL_wci_ctrl_OrE,
CAN_FIRE_RL_wci_reqF__updateLevelCounter,
CAN_FIRE_RL_wci_reqF_enq,
CAN_FIRE_RL_wci_request_decode,
CAN_FIRE_RL_wci_respF_both,
CAN_FIRE_RL_wci_respF_decCtr,
CAN_FIRE_RL_wci_respF_deq,
CAN_FIRE_RL_wci_respF_incCtr,
CAN_FIRE_RL_wci_sFlagReg__dreg_update,
CAN_FIRE_RL_wci_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_ext_status_assign,
CAN_FIRE_RL_wsiM_inc_tBusyCount,
CAN_FIRE_RL_wsiM_operateD__dreg_update,
CAN_FIRE_RL_wsiM_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiM_reqFifo_both,
CAN_FIRE_RL_wsiM_reqFifo_decCtr,
CAN_FIRE_RL_wsiM_reqFifo_deq,
CAN_FIRE_RL_wsiM_reqFifo_incCtr,
CAN_FIRE_RL_wsiM_sThreadBusy_reg,
CAN_FIRE_RL_wsiM_update_statusR,
CAN_FIRE_RL_wsiS_backpressure,
CAN_FIRE_RL_wsiS_ext_status_assign,
CAN_FIRE_RL_wsiS_inc_tBusyCount,
CAN_FIRE_RL_wsiS_operateD__dreg_update,
CAN_FIRE_RL_wsiS_peerIsReady__dreg_update,
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
CAN_FIRE_RL_wsiS_reqFifo_enq,
CAN_FIRE_RL_wsiS_reqFifo_reset,
CAN_FIRE_RL_wsiS_update_statusR,
CAN_FIRE_RL_wsi_Es_doAlways,
CAN_FIRE_wciS0_mAddr,
CAN_FIRE_wciS0_mAddrSpace,
CAN_FIRE_wciS0_mByteEn,
CAN_FIRE_wciS0_mCmd,
CAN_FIRE_wciS0_mData,
CAN_FIRE_wciS0_mFlag,
CAN_FIRE_wsiM0_sReset_n,
CAN_FIRE_wsiM0_sThreadBusy,
CAN_FIRE_wsiS0_mBurstLength,
CAN_FIRE_wsiS0_mBurstPrecise,
CAN_FIRE_wsiS0_mByteEn,
CAN_FIRE_wsiS0_mCmd,
CAN_FIRE_wsiS0_mData,
CAN_FIRE_wsiS0_mDataInfo,
CAN_FIRE_wsiS0_mReqInfo,
CAN_FIRE_wsiS0_mReqLast,
CAN_FIRE_wsiS0_mReset_n,
WILL_FIRE_RL_fft_drive_fft_always_enabled,
WILL_FIRE_RL_fft_fft_stream_egress,
WILL_FIRE_RL_fft_fft_stream_ingress,
WILL_FIRE_RL_fft_frame_start,
WILL_FIRE_RL_operating_actions,
WILL_FIRE_RL_psdFFT_doEgress,
WILL_FIRE_RL_psdFFT_doIngress,
WILL_FIRE_RL_psdPass_bypass,
WILL_FIRE_RL_psdPrecise_input,
WILL_FIRE_RL_psdPrecise_output_bypassFFT,
WILL_FIRE_RL_psdPrecise_output_feedFFT,
WILL_FIRE_RL_w2p_dataF_portA,
WILL_FIRE_RL_w2p_dataF_portB,
WILL_FIRE_RL_w2p_dataF_portB_read_data,
WILL_FIRE_RL_w2p_imprecise_enq,
WILL_FIRE_RL_w2p_precise_deq,
WILL_FIRE_RL_wci_Es_doAlways_Req,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctlAckReg__dreg_update,
WILL_FIRE_RL_wci_ctl_op_complete,
WILL_FIRE_RL_wci_ctl_op_start,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_reqF__updateLevelCounter,
WILL_FIRE_RL_wci_reqF_enq,
WILL_FIRE_RL_wci_request_decode,
WILL_FIRE_RL_wci_respF_both,
WILL_FIRE_RL_wci_respF_decCtr,
WILL_FIRE_RL_wci_respF_deq,
WILL_FIRE_RL_wci_respF_incCtr,
WILL_FIRE_RL_wci_sFlagReg__dreg_update,
WILL_FIRE_RL_wci_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_ext_status_assign,
WILL_FIRE_RL_wsiM_inc_tBusyCount,
WILL_FIRE_RL_wsiM_operateD__dreg_update,
WILL_FIRE_RL_wsiM_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiM_sThreadBusy_reg,
WILL_FIRE_RL_wsiM_update_statusR,
WILL_FIRE_RL_wsiS_backpressure,
WILL_FIRE_RL_wsiS_ext_status_assign,
WILL_FIRE_RL_wsiS_inc_tBusyCount,
WILL_FIRE_RL_wsiS_operateD__dreg_update,
WILL_FIRE_RL_wsiS_peerIsReady__dreg_update,
WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset,
WILL_FIRE_RL_wsiS_update_statusR,
WILL_FIRE_RL_wsi_Es_doAlways,
WILL_FIRE_wciS0_mAddr,
WILL_FIRE_wciS0_mAddrSpace,
WILL_FIRE_wciS0_mByteEn,
WILL_FIRE_wciS0_mCmd,
WILL_FIRE_wciS0_mData,
WILL_FIRE_wciS0_mFlag,
WILL_FIRE_wsiM0_sReset_n,
WILL_FIRE_wsiM0_sThreadBusy,
WILL_FIRE_wsiS0_mBurstLength,
WILL_FIRE_wsiS0_mBurstPrecise,
WILL_FIRE_wsiS0_mByteEn,
WILL_FIRE_wsiS0_mCmd,
WILL_FIRE_wsiS0_mData,
WILL_FIRE_wsiS0_mDataInfo,
WILL_FIRE_wsiS0_mReqInfo,
WILL_FIRE_wsiS0_mReqLast,
WILL_FIRE_wsiS0_mReset_n;
// inputs to muxes for submodule ports
reg [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
reg [33 : 0] MUX_wci_respF_q_0$write_1__VAL_1;
wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_2,
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
wire [33 : 0] MUX_wci_respF_q_0$write_1__VAL_2,
MUX_wci_respF_q_1$write_1__VAL_2,
MUX_wci_respF_x_wire$wset_1__VAL_1,
MUX_wci_respF_x_wire$wset_1__VAL_2;
wire [1 : 0] MUX_wci_respF_c_r$write_1__VAL_1,
MUX_wci_respF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_fft_fftStarted$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_1,
MUX_wci_illegalEdge$write_1__SEL_2,
MUX_wci_illegalEdge$write_1__VAL_2,
MUX_wci_respF_q_0$write_1__SEL_1,
MUX_wci_respF_q_1$write_1__SEL_1,
MUX_wsiM_reqFifo_q_0$write_1__SEL_1,
MUX_wsiM_reqFifo_q_1$write_1__SEL_1,
MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1,
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4;
// remaining internal signals
reg [63 : 0] v__h14361, v__h2625, v__h2772, v__h3671;
reg [31 : 0] x_data__h14493;
wire [31 : 0] psdStatus__h14238,
rdat__h14517,
rdat__h14617,
rdat__h14631,
rdat__h14639,
rdat__h14645,
rdat__h14659,
rdat__h14667,
rdat__h14673,
x__h7434,
x_data__h13251,
x_data__h7856,
x_fftFrameCounts__h12666;
wire [15 : 0] IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d140,
IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d646,
IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d137,
IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d644,
IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d135,
IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d643,
dReal__h13383,
result__h13444,
w2p_wordsExact_28_MINUS_1___d645,
x__h13415,
x__h14521;
wire [12 : 0] x__h7326;
wire NOT_w2p_dataF_rRdPtr_11_PLUS_2048_39_EQ_w2p_da_ETC___d349,
w2p_wordsDequed_27_EQ_w2p_wordsExact_28_MINUS__ETC___d608,
w2p_wordsEnqued_43_EQ_w2p_wordsExact_28_MINUS__ETC___d674,
wsiS_reqFifo_notFull__03_AND_wsiS_burstKind_83_ETC___d423;
// action method wciS0_mCmd
assign CAN_FIRE_wciS0_mCmd = 1'd1 ;
assign WILL_FIRE_wciS0_mCmd = 1'd1 ;
// action method wciS0_mAddrSpace
assign CAN_FIRE_wciS0_mAddrSpace = 1'd1 ;
assign WILL_FIRE_wciS0_mAddrSpace = 1'd1 ;
// action method wciS0_mByteEn
assign CAN_FIRE_wciS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wciS0_mByteEn = 1'd1 ;
// action method wciS0_mAddr
assign CAN_FIRE_wciS0_mAddr = 1'd1 ;
assign WILL_FIRE_wciS0_mAddr = 1'd1 ;
// action method wciS0_mData
assign CAN_FIRE_wciS0_mData = 1'd1 ;
assign WILL_FIRE_wciS0_mData = 1'd1 ;
// value method wciS0_sResp
assign wciS0_SResp = wci_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy = wci_reqF_countReg > 2'd1 || wci_isReset$VAL ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_sFlagReg } ;
// action method wciS0_mFlag
assign CAN_FIRE_wciS0_mFlag = 1'd1 ;
assign WILL_FIRE_wciS0_mFlag = 1'd1 ;
// action method wsiS0_mCmd
assign CAN_FIRE_wsiS0_mCmd = 1'd1 ;
assign WILL_FIRE_wsiS0_mCmd = 1'd1 ;
// action method wsiS0_mReqLast
assign CAN_FIRE_wsiS0_mReqLast = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqLast = wsiS0_MReqLast ;
// action method wsiS0_mBurstPrecise
assign CAN_FIRE_wsiS0_mBurstPrecise = 1'd1 ;
assign WILL_FIRE_wsiS0_mBurstPrecise = wsiS0_MBurstPrecise ;
// action method wsiS0_mBurstLength
assign CAN_FIRE_wsiS0_mBurstLength = 1'd1 ;
assign WILL_FIRE_wsiS0_mBurstLength = 1'd1 ;
// action method wsiS0_mData
assign CAN_FIRE_wsiS0_mData = 1'd1 ;
assign WILL_FIRE_wsiS0_mData = 1'd1 ;
// action method wsiS0_mByteEn
assign CAN_FIRE_wsiS0_mByteEn = 1'd1 ;
assign WILL_FIRE_wsiS0_mByteEn = 1'd1 ;
// action method wsiS0_mReqInfo
assign CAN_FIRE_wsiS0_mReqInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mReqInfo = 1'd1 ;
// action method wsiS0_mDataInfo
assign CAN_FIRE_wsiS0_mDataInfo = 1'd1 ;
assign WILL_FIRE_wsiS0_mDataInfo = 1'd1 ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset$VAL && wsiS_operateD ;
// action method wsiS0_mReset_n
assign CAN_FIRE_wsiS0_mReset_n = 1'd1 ;
assign WILL_FIRE_wsiS0_mReset_n = wsiS0_MReset_n ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// action method wsiM0_sThreadBusy
assign CAN_FIRE_wsiM0_sThreadBusy = 1'd1 ;
assign WILL_FIRE_wsiM0_sThreadBusy = wsiM0_SThreadBusy ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset$VAL && wsiM_operateD ;
// action method wsiM0_sReset_n
assign CAN_FIRE_wsiM0_sReset_n = 1'd1 ;
assign WILL_FIRE_wsiM0_sReset_n = wsiM0_SReset_n ;
// submodule fft_fft
xfft_v7_1 fft_fft(.clk(wciS0_Clk),
.fwd_inv(fft_fft$fwd_inv),
.fwd_inv_we(fft_fft$fwd_inv_we),
.scale_sch(fft_fft$scale_sch),
.scale_sch_we(fft_fft$scale_sch_we),
.start(fft_fft$start),
.xn_im(fft_fft$xn_im),
.xn_re(fft_fft$xn_re),
.busy(),
.dv(fft_fft$dv),
.rfd(fft_fft$rfd),
.edone(),
.done(),
.xn_index(),
.xk_re(fft_fft$xk_re),
.xk_im(fft_fft$xk_im),
.xk_index());
// submodule fft_xkF
FIFO2 #(.width(32'd32), .guarded(32'd1)) fft_xkF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(fft_xkF$D_IN),
.ENQ(fft_xkF$ENQ),
.DEQ(fft_xkF$DEQ),
.CLR(fft_xkF$CLR),
.D_OUT(fft_xkF$D_OUT),
.FULL_N(fft_xkF$FULL_N),
.EMPTY_N(fft_xkF$EMPTY_N));
// submodule fft_xnF
FIFO2 #(.width(32'd32), .guarded(32'd1)) fft_xnF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(fft_xnF$D_IN),
.ENQ(fft_xnF$ENQ),
.DEQ(fft_xnF$DEQ),
.CLR(fft_xnF$CLR),
.D_OUT(fft_xnF$D_OUT),
.FULL_N(fft_xnF$FULL_N),
.EMPTY_N(fft_xnF$EMPTY_N));
// submodule w2p_dataF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd12),
.DATA_WIDTH(32'd32),
.MEMSIZE(13'd4096)) w2p_dataF_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(w2p_dataF_memory$ADDRA),
.ADDRB(w2p_dataF_memory$ADDRB),
.DIA(w2p_dataF_memory$DIA),
.DIB(w2p_dataF_memory$DIB),
.WEA(w2p_dataF_memory$WEA),
.WEB(w2p_dataF_memory$WEB),
.ENA(w2p_dataF_memory$ENA),
.ENB(w2p_dataF_memory$ENB),
.DOA(),
.DOB(w2p_dataF_memory$DOB));
// submodule w2p_inF
FIFO2 #(.width(32'd61), .guarded(32'd1)) w2p_inF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(w2p_inF$D_IN),
.ENQ(w2p_inF$ENQ),
.DEQ(w2p_inF$DEQ),
.CLR(w2p_inF$CLR),
.D_OUT(w2p_inF$D_OUT),
.FULL_N(w2p_inF$FULL_N),
.EMPTY_N(w2p_inF$EMPTY_N));
// submodule w2p_outF
FIFO2 #(.width(32'd61), .guarded(32'd1)) w2p_outF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(w2p_outF$D_IN),
.ENQ(w2p_outF$ENQ),
.DEQ(w2p_outF$DEQ),
.CLR(w2p_outF$CLR),
.D_OUT(w2p_outF$D_OUT),
.FULL_N(w2p_outF$FULL_N),
.EMPTY_N(w2p_outF$EMPTY_N));
// submodule w2p_reqF
FIFO2 #(.width(32'd8), .guarded(32'd1)) w2p_reqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(w2p_reqF$D_IN),
.ENQ(w2p_reqF$ENQ),
.DEQ(w2p_reqF$DEQ),
.CLR(w2p_reqF$CLR),
.D_OUT(w2p_reqF$D_OUT),
.FULL_N(w2p_reqF$FULL_N),
.EMPTY_N(w2p_reqF$EMPTY_N));
// submodule wci_isReset
ResetToBool wci_isReset(.RST(wciS0_MReset_n), .VAL(wci_isReset$VAL));
// submodule wci_reqF
SizedFIFO #(.p1width(32'd60),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_reqF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_reqF$D_IN),
.ENQ(wci_reqF$ENQ),
.DEQ(wci_reqF$DEQ),
.CLR(wci_reqF$CLR),
.D_OUT(wci_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_reqF$EMPTY_N));
// submodule wsiM_isReset
ResetToBool wsiM_isReset(.RST(wciS0_MReset_n), .VAL(wsiM_isReset$VAL));
// submodule wsiS_isReset
ResetToBool wsiS_isReset(.RST(wciS0_MReset_n), .VAL(wsiS_isReset$VAL));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd61),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo$D_IN),
.ENQ(wsiS_reqFifo$ENQ),
.DEQ(wsiS_reqFifo$DEQ),
.CLR(wsiS_reqFifo$CLR),
.D_OUT(wsiS_reqFifo$D_OUT),
.FULL_N(wsiS_reqFifo$FULL_N),
.EMPTY_N(wsiS_reqFifo$EMPTY_N));
// submodule xnF
FIFO2 #(.width(32'd32), .guarded(32'd1)) xnF(.RST_N(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(xnF$D_IN),
.ENQ(xnF$ENQ),
.DEQ(xnF$DEQ),
.CLR(xnF$CLR),
.D_OUT(xnF$D_OUT),
.FULL_N(xnF$FULL_N),
.EMPTY_N(xnF$EMPTY_N));
// rule RL_wsiS_backpressure
assign CAN_FIRE_RL_wsiS_backpressure =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign WILL_FIRE_RL_wsiS_backpressure = CAN_FIRE_RL_wsiS_backpressure ;
// rule RL_wci_request_decode
assign CAN_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
assign WILL_FIRE_RL_wci_request_decode = wci_reqF$EMPTY_N ;
// rule RL_wci_ctl_op_start
assign CAN_FIRE_RL_wci_ctl_op_start =
wci_reqF$EMPTY_N && wci_wci_ctrl_pw$whas ;
assign WILL_FIRE_RL_wci_ctl_op_start =
CAN_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign CAN_FIRE_RL_wci_ctrl_EiI =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd0 &&
wci_reqF$D_OUT[36:34] == 3'd0 ;
assign WILL_FIRE_RL_wci_ctrl_EiI = CAN_FIRE_RL_wci_ctrl_EiI ;
// rule RL_wci_ctrl_IsO
assign CAN_FIRE_RL_wci_ctrl_IsO =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd1 &&
wci_reqF$D_OUT[36:34] == 3'd1 ;
assign WILL_FIRE_RL_wci_ctrl_IsO = CAN_FIRE_RL_wci_ctrl_IsO ;
// rule RL_wci_ctrl_OrE
assign CAN_FIRE_RL_wci_ctrl_OrE =
wci_wci_ctrl_pw$whas && WILL_FIRE_RL_wci_ctl_op_start &&
wci_cState == 3'd2 &&
wci_reqF$D_OUT[36:34] == 3'd3 ;
assign WILL_FIRE_RL_wci_ctrl_OrE = CAN_FIRE_RL_wci_ctrl_OrE ;
// rule RL_wsi_Es_doAlways
assign CAN_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
assign WILL_FIRE_RL_wsi_Es_doAlways = 1'd1 ;
// rule RL_wci_Es_doAlways_Req
assign CAN_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
assign WILL_FIRE_RL_wci_Es_doAlways_Req = 1'd1 ;
// rule RL_psdFFT_doEgress
assign CAN_FIRE_RL_psdFFT_doEgress =
fft_xkF$EMPTY_N && (sendEven || wsiM_reqFifo_c_r != 2'd2) &&
wci_cState == 3'd2 &&
psdCtrl[1:0] == 2'd2 ;
assign WILL_FIRE_RL_psdFFT_doEgress = CAN_FIRE_RL_psdFFT_doEgress ;
// rule RL_psdPrecise_output_feedFFT
assign CAN_FIRE_RL_psdPrecise_output_feedFFT =
w2p_outF$EMPTY_N && xnF$FULL_N && wci_cState == 3'd2 &&
psdCtrl[1:0] == 2'd2 ;
assign WILL_FIRE_RL_psdPrecise_output_feedFFT =
CAN_FIRE_RL_psdPrecise_output_feedFFT ;
// rule RL_psdPrecise_output_bypassFFT
assign CAN_FIRE_RL_psdPrecise_output_bypassFFT =
wsiM_reqFifo_c_r != 2'd2 && w2p_outF$EMPTY_N &&
wci_cState == 3'd2 &&
psdCtrl[1:0] == 2'd1 ;
assign WILL_FIRE_RL_psdPrecise_output_bypassFFT =
CAN_FIRE_RL_psdPrecise_output_bypassFFT ;
// rule RL_operating_actions
assign CAN_FIRE_RL_operating_actions = wci_cState == 3'd2 ;
assign WILL_FIRE_RL_operating_actions = CAN_FIRE_RL_operating_actions ;
// rule RL_fft_frame_start
assign CAN_FIRE_RL_fft_frame_start = fft_xnF$EMPTY_N && !fft_fftStarted ;
assign WILL_FIRE_RL_fft_frame_start = CAN_FIRE_RL_fft_frame_start ;
// rule RL_psdFFT_doIngress
assign CAN_FIRE_RL_psdFFT_doIngress =
fft_xnF$FULL_N && xnF$EMPTY_N && wci_cState == 3'd2 &&
psdCtrl[1:0] == 2'd2 ;
assign WILL_FIRE_RL_psdFFT_doIngress = CAN_FIRE_RL_psdFFT_doIngress ;
// rule RL_wsiM_update_statusR
assign CAN_FIRE_RL_wsiM_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiM_update_statusR = 1'd1 ;
// rule RL_wsiM_ext_status_assign
assign CAN_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiM_ext_status_assign = 1'd1 ;
// rule RL_wsiM_inc_tBusyCount
assign CAN_FIRE_RL_wsiM_inc_tBusyCount =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_inc_tBusyCount = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// rule RL_wsiM_reqFifo_deq
assign CAN_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
assign WILL_FIRE_RL_wsiM_reqFifo_deq = CAN_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_sThreadBusy_reg
assign CAN_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wsiM_sThreadBusy_reg = 1'd1 ;
// rule RL_wsiM_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiM_operateD__dreg_update
assign CAN_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiM_operateD__dreg_update = 1'd1 ;
// rule RL_w2p_dataF_portB_read_data
assign CAN_FIRE_RL_w2p_dataF_portB_read_data = 1'd1 ;
assign WILL_FIRE_RL_w2p_dataF_portB_read_data = 1'd1 ;
// rule RL_w2p_precise_deq
assign CAN_FIRE_RL_w2p_precise_deq =
w2p_dataF_rRdPtr != w2p_dataF_rWrPtr && w2p_outF$FULL_N &&
w2p_reqF$EMPTY_N &&
wci_cState == 3'd2 &&
w2p_reqF$EMPTY_N ;
assign WILL_FIRE_RL_w2p_precise_deq = CAN_FIRE_RL_w2p_precise_deq ;
// rule RL_w2p_imprecise_enq
assign CAN_FIRE_RL_w2p_imprecise_enq =
NOT_w2p_dataF_rRdPtr_11_PLUS_2048_39_EQ_w2p_da_ETC___d349 &&
wci_cState == 3'd2 ;
assign WILL_FIRE_RL_w2p_imprecise_enq = CAN_FIRE_RL_w2p_imprecise_enq ;
// rule RL_w2p_dataF_portB
assign CAN_FIRE_RL_w2p_dataF_portB = 1'd1 ;
assign WILL_FIRE_RL_w2p_dataF_portB = 1'd1 ;
// rule RL_w2p_dataF_portA
assign CAN_FIRE_RL_w2p_dataF_portA = 1'd1 ;
assign WILL_FIRE_RL_w2p_dataF_portA = 1'd1 ;
// rule RL_wsiS_update_statusR
assign CAN_FIRE_RL_wsiS_update_statusR = 1'd1 ;
assign WILL_FIRE_RL_wsiS_update_statusR = 1'd1 ;
// rule RL_wsiS_ext_status_assign
assign CAN_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
assign WILL_FIRE_RL_wsiS_ext_status_assign = 1'd1 ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_reqF$EMPTY_N && wci_respF_c_r != 2'd2 &&
wci_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_fft_fft_stream_egress
assign CAN_FIRE_RL_fft_fft_stream_egress = fft_xkF$FULL_N && fft_fft$dv ;
assign WILL_FIRE_RL_fft_fft_stream_egress =
CAN_FIRE_RL_fft_fft_stream_egress ;
// rule RL_fft_fft_stream_ingress
assign CAN_FIRE_RL_fft_fft_stream_ingress =
fft_xnF$EMPTY_N && fft_fft$rfd && fft_fftStarted ;
assign WILL_FIRE_RL_fft_fft_stream_ingress =
CAN_FIRE_RL_fft_fft_stream_ingress ;
// rule RL_fft_drive_fft_always_enabled
assign CAN_FIRE_RL_fft_drive_fft_always_enabled = 1'd1 ;
assign WILL_FIRE_RL_fft_drive_fft_always_enabled = 1'd1 ;
// rule RL_wsiS_inc_tBusyCount
assign CAN_FIRE_RL_wsiS_inc_tBusyCount =
wsiS_operateD && wsiS_peerIsReady &&
(!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget) ;
assign WILL_FIRE_RL_wsiS_inc_tBusyCount = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// rule RL_wsiS_reqFifo_enq
assign CAN_FIRE_RL_wsiS_reqFifo_enq =
wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq$wget[60:58] == 3'd1 ;
assign WILL_FIRE_RL_wsiS_reqFifo_enq = CAN_FIRE_RL_wsiS_reqFifo_enq ;
// rule RL_psdPrecise_input
assign CAN_FIRE_RL_psdPrecise_input =
wsiS_reqFifo$EMPTY_N && w2p_inF$FULL_N && wci_cState == 3'd2 &&
(psdCtrl[1:0] == 2'd1 || psdCtrl[1:0] == 2'd2) ;
assign WILL_FIRE_RL_psdPrecise_input = CAN_FIRE_RL_psdPrecise_input ;
// rule RL_psdPass_bypass
assign CAN_FIRE_RL_psdPass_bypass =
wsiM_reqFifo_c_r != 2'd2 && wsiS_reqFifo$EMPTY_N &&
wci_cState == 3'd2 &&
psdCtrl[1:0] == 2'd0 ;
assign WILL_FIRE_RL_psdPass_bypass = CAN_FIRE_RL_psdPass_bypass ;
// rule RL_wci_ctl_op_complete
assign CAN_FIRE_RL_wci_ctl_op_complete =
wci_respF_c_r != 2'd2 && wci_ctlOpActive && wci_ctlAckReg ;
assign WILL_FIRE_RL_wci_ctl_op_complete = CAN_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wci_cfwr
assign CAN_FIRE_RL_wci_cfwr =
wci_reqF$EMPTY_N && wci_respF_c_r != 2'd2 &&
wci_wci_cfwr_pw$whas ;
assign WILL_FIRE_RL_wci_cfwr =
CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_ctl_op_start &&
!WILL_FIRE_RL_wci_ctl_op_complete ;
// rule RL_wsiM_reqFifo_both
assign CAN_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_x_wire$whas) &&
CAN_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_both = CAN_FIRE_RL_wsiM_reqFifo_both ;
// rule RL_wsiM_reqFifo_decCtr
assign CAN_FIRE_RL_wsiM_reqFifo_decCtr =
CAN_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr = CAN_FIRE_RL_wsiM_reqFifo_decCtr ;
// rule RL_wsiM_reqFifo_incCtr
assign CAN_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_x_wire$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_x_wire$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr = CAN_FIRE_RL_wsiM_reqFifo_incCtr ;
// rule RL_wsiS_peerIsReady__dreg_update
assign CAN_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_peerIsReady__dreg_update = 1'd1 ;
// rule RL_wsiS_operateD__dreg_update
assign CAN_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wsiS_operateD__dreg_update = 1'd1 ;
// rule RL_wsiS_reqFifo_reset
assign CAN_FIRE_RL_wsiS_reqFifo_reset =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ||
wsiS_reqFifo_r_deq$whas ;
assign WILL_FIRE_RL_wsiS_reqFifo_reset = CAN_FIRE_RL_wsiS_reqFifo_reset ;
// rule RL_wsiS_reqFifo__updateLevelCounter
assign CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 !=
wsiS_reqFifo_r_deq$whas ;
assign WILL_FIRE_RL_wsiS_reqFifo__updateLevelCounter =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// rule RL_wci_respF_deq
assign CAN_FIRE_RL_wci_respF_deq = 1'd1 ;
assign WILL_FIRE_RL_wci_respF_deq = 1'd1 ;
// rule RL_wci_reqF_enq
assign CAN_FIRE_RL_wci_reqF_enq = wci_wciReq$wget[59:57] != 3'd0 ;
assign WILL_FIRE_RL_wci_reqF_enq = CAN_FIRE_RL_wci_reqF_enq ;
// rule RL_wci_sThreadBusy_reg
assign CAN_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
assign WILL_FIRE_RL_wci_sThreadBusy_reg = 1'd1 ;
// rule RL_wci_ctlAckReg__dreg_update
assign CAN_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_ctlAckReg__dreg_update = 1'd1 ;
// rule RL_wci_sFlagReg__dreg_update
assign CAN_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
assign WILL_FIRE_RL_wci_sFlagReg__dreg_update = 1'd1 ;
// rule RL_wci_respF_both
assign CAN_FIRE_RL_wci_respF_both =
((wci_respF_c_r == 2'd1) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd2 || wci_respF_x_wire$whas) &&
wci_respF_c_r != 2'd0 &&
wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_both = CAN_FIRE_RL_wci_respF_both ;
// rule RL_wci_respF_decCtr
assign CAN_FIRE_RL_wci_respF_decCtr =
wci_respF_c_r != 2'd0 && !wci_respF_enqueueing$whas ;
assign WILL_FIRE_RL_wci_respF_decCtr = CAN_FIRE_RL_wci_respF_decCtr ;
// rule RL_wci_respF_incCtr
assign CAN_FIRE_RL_wci_respF_incCtr =
((wci_respF_c_r == 2'd0) ?
wci_respF_x_wire$whas :
wci_respF_c_r != 2'd1 || wci_respF_x_wire$whas) &&
wci_respF_enqueueing$whas &&
!(wci_respF_c_r != 2'd0) ;
assign WILL_FIRE_RL_wci_respF_incCtr = CAN_FIRE_RL_wci_respF_incCtr ;
// rule RL_wci_reqF__updateLevelCounter
assign CAN_FIRE_RL_wci_reqF__updateLevelCounter =
(wci_wciReq$wget[59:57] != 3'd0) != wci_reqF_r_deq$whas ;
assign WILL_FIRE_RL_wci_reqF__updateLevelCounter =
CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// inputs to muxes for submodule ports
assign MUX_fft_fftStarted$write_1__SEL_1 =
WILL_FIRE_RL_fft_fft_stream_ingress &&
fft_loadIndex == 16'd4095 ;
assign MUX_wci_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 =
WILL_FIRE_RL_psdFFT_doEgress && !sendEven ;
assign MUX_wci_illegalEdge$write_1__VAL_2 =
wci_reqF$D_OUT[36:34] != 3'd4 && wci_reqF$D_OUT[36:34] != 3'd5 &&
wci_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_respF_c_r$write_1__VAL_1 = wci_respF_c_r - 2'd1 ;
assign MUX_wci_respF_c_r$write_1__VAL_2 = wci_respF_c_r + 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_1 =
wci_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 =
{ 3'd1,
unloadCnt == 16'd4095,
13'd6144,
x_data__h13251,
12'd3840 } ;
always@(MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1 or
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_psdPrecise_output_bypassFFT or
w2p_outF$D_OUT or WILL_FIRE_RL_psdPass_bypass or wsiS_reqFifo$D_OUT)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_x_wire$wset_1__SEL_1:
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
MUX_wsiM_reqFifo_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_psdPrecise_output_bypassFFT:
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = w2p_outF$D_OUT;
WILL_FIRE_RL_psdPass_bypass:
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 = wsiS_reqFifo$D_OUT;
default: MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_2 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 :
61'h00000AAAAAAAAA00 ;
assign MUX_wci_illegalEdge$write_1__SEL_2 =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState != 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 && wci_cState != 3'd1 &&
wci_cState != 3'd3 ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState != 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 && wci_cState != 3'd3 &&
wci_cState != 3'd2 &&
wci_cState != 3'd1 ||
wci_reqF$D_OUT[36:34] == 3'd4 ||
wci_reqF$D_OUT[36:34] == 3'd5 ||
wci_reqF$D_OUT[36:34] == 3'd6 ||
wci_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_respF_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ;
assign MUX_wci_respF_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ;
assign MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_wci_respF_x_wire$wset_1__VAL_2 = { 2'd1, x_data__h14493 } ;
always@(WILL_FIRE_RL_wci_ctl_op_complete or
MUX_wci_respF_x_wire$wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_respF_x_wire$wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_ctl_op_complete:
MUX_wci_respF_q_0$write_1__VAL_1 =
MUX_wci_respF_x_wire$wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_respF_q_0$write_1__VAL_1 =
MUX_wci_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr: MUX_wci_respF_q_0$write_1__VAL_1 = 34'h1C0DE4201;
default: MUX_wci_respF_q_0$write_1__VAL_1 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_respF_q_0$write_1__VAL_2 =
(wci_respF_c_r == 2'd1) ?
MUX_wci_respF_q_0$write_1__VAL_1 :
wci_respF_q_1 ;
assign MUX_wci_respF_q_1$write_1__VAL_2 =
(wci_respF_c_r == 2'd2) ?
MUX_wci_respF_q_0$write_1__VAL_1 :
34'h0AAAAAAAA ;
// inlined wires
assign wci_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wciReq$whas = 1'd1 ;
assign wci_reqF_r_enq$whas = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF_r_clr$whas = 1'b0 ;
assign wci_respF_dequeueing$whas = wci_respF_c_r != 2'd0 ;
assign wci_wEdge$wget = wci_reqF$D_OUT[36:34] ;
assign wci_sFlagReg_1$whas = 1'b0 ;
assign wci_sThreadBusy_pw$whas = 1'b0 ;
assign wci_sFlagReg_1$wget = 1'b0 ;
assign wci_wci_cfwr_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd1 ;
assign wci_wci_cfrd_pw$whas =
wci_reqF$EMPTY_N && wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_wci_ctrl_pw$whas =
wci_reqF$EMPTY_N && !wci_reqF$D_OUT[56] &&
wci_reqF$D_OUT[59:57] == 3'd2 ;
assign wci_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_respF_enqueueing$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_respF_x_wire$whas =
WILL_FIRE_RL_wci_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wEdge$whas = WILL_FIRE_RL_wci_ctl_op_start ;
assign wci_ctlAckReg_1$wget = 1'd1 ;
assign wci_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wsiS_wsiReq$wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq$whas = 1'd1 ;
assign wsiS_reqFifo_r_enq$whas =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
assign wsiS_reqFifo_r_deq$whas =
WILL_FIRE_RL_psdPass_bypass || WILL_FIRE_RL_psdPrecise_input ;
assign wsiS_reqFifo_r_clr$whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq$whas =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
assign wsiS_reqFifo_doResetDeq$whas = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo_doResetClr$whas = 1'b0 ;
assign wsiS_operateD_1$wget = 1'd1 ;
assign wsiS_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiS_peerIsReady_1$wget = 1'd1 ;
assign wsiS_peerIsReady_1$whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw$wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw$whas = CAN_FIRE_RL_wsiS_backpressure ;
assign wsiS_extStatusW$wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
assign w2p_dataF_pwDequeue$whas = CAN_FIRE_RL_w2p_precise_deq ;
assign w2p_dataF_pwEnqueue$whas = CAN_FIRE_RL_w2p_imprecise_enq ;
assign w2p_dataF_wDataIn$wget = w2p_inF$D_OUT[43:12] ;
assign w2p_dataF_wDataIn$whas = CAN_FIRE_RL_w2p_imprecise_enq ;
assign w2p_dataF_wDataOut$wget = x_data__h7856 ;
assign w2p_dataF_wDataOut$whas = 1'd1 ;
assign w2p_operateW$wget = 1'd1 ;
assign w2p_operateW$whas = CAN_FIRE_RL_operating_actions ;
assign wsiM_reqFifo_enqueueing$whas =
WILL_FIRE_RL_psdFFT_doEgress && !sendEven ||
WILL_FIRE_RL_psdPass_bypass ||
WILL_FIRE_RL_psdPrecise_output_bypassFFT ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_1 ;
assign wsiM_reqFifo_x_wire$whas =
WILL_FIRE_RL_psdFFT_doEgress && !sendEven ||
WILL_FIRE_RL_psdPrecise_output_bypassFFT ||
WILL_FIRE_RL_psdPass_bypass ;
assign wsiM_reqFifo_dequeueing$whas = CAN_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign wsiM_operateD_1$whas = CAN_FIRE_RL_operating_actions ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
assign wci_respF_x_wire$wget = MUX_wci_respF_q_0$write_1__VAL_1 ;
assign fft_fwd_w$wget = 1'b0 ;
assign fft_fwd_w$whas = 1'b0 ;
assign fft_fwd_we_w$wget = 1'b0 ;
assign fft_fwd_we_w$whas = 1'b0 ;
assign fft_scale_w$wget = 12'h0 ;
assign fft_scale_w$whas = 1'b0 ;
assign fft_scale_we_w$wget = 1'b0 ;
assign fft_scale_we_w$whas = 1'b0 ;
assign fft_start_w$wget = 1'd1 ;
assign fft_start_w$whas = CAN_FIRE_RL_fft_frame_start ;
assign fft_xnRe_w$wget = fft_xnF$D_OUT[31:16] ;
assign fft_xnRe_w$whas = CAN_FIRE_RL_fft_fft_stream_ingress ;
assign fft_xnIm_w$wget = fft_xnF$D_OUT[15:0] ;
assign fft_xnIm_w$whas = CAN_FIRE_RL_fft_fft_stream_ingress ;
assign wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_Es_mData_w$wget = wciS0_MData ;
assign wci_Es_mData_w$whas = 1'd1 ;
assign wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mCmd_w$wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w$whas = 1'd1 ;
assign wsi_Es_mReqLast_w$whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w$whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mBurstLength_w$wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w$whas = 1'd1 ;
assign wsi_Es_mData_w$wget = wsiS0_MData ;
assign wsi_Es_mData_w$whas = 1'd1 ;
assign wsi_Es_mByteEn_w$wget = wsiS0_MByteEn ;
assign wsi_Es_mReqInfo_w$wget = wsiS0_MReqInfo ;
assign wsi_Es_mByteEn_w$whas = 1'd1 ;
assign wsi_Es_mReqInfo_w$whas = 1'd1 ;
assign wsi_Es_mDataInfo_w$whas = 1'd1 ;
// register evenMag
assign evenMag$D_IN =
IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d646 -
IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d140 ;
assign evenMag$EN = WILL_FIRE_RL_psdFFT_doEgress && sendEven ;
// register fft_fftStarted
assign fft_fftStarted$D_IN = !MUX_fft_fftStarted$write_1__SEL_1 ;
assign fft_fftStarted$EN =
WILL_FIRE_RL_fft_fft_stream_ingress &&
fft_loadIndex == 16'd4095 ||
WILL_FIRE_RL_fft_frame_start ;
// register fft_loadFrames
assign fft_loadFrames$D_IN = fft_loadFrames + 16'd1 ;
assign fft_loadFrames$EN = MUX_fft_fftStarted$write_1__SEL_1 ;
// register fft_loadIndex
assign fft_loadIndex$D_IN =
(fft_loadIndex == 16'd4095) ? 16'd0 : fft_loadIndex + 16'd1 ;
assign fft_loadIndex$EN = CAN_FIRE_RL_fft_fft_stream_ingress ;
// register fft_unloadFrames
assign fft_unloadFrames$D_IN = fft_unloadFrames + 16'd1 ;
assign fft_unloadFrames$EN =
WILL_FIRE_RL_fft_fft_stream_egress &&
fft_unloadIndex == 16'd4095 ;
// register fft_unloadIndex
assign fft_unloadIndex$D_IN =
(fft_unloadIndex == 16'd4095) ? 16'd0 : fft_unloadIndex + 16'd1 ;
assign fft_unloadIndex$EN = CAN_FIRE_RL_fft_fft_stream_egress ;
// register psdCtrl
assign psdCtrl$D_IN = wci_reqF$D_OUT[31:0] ;
assign psdCtrl$EN =
WILL_FIRE_RL_wci_cfwr && wci_reqF$D_OUT[51:32] == 20'h00004 ;
// register sendEven
assign sendEven$D_IN = !sendEven ;
assign sendEven$EN = CAN_FIRE_RL_psdFFT_doEgress ;
// register takeEven
assign takeEven$D_IN = !takeEven ;
assign takeEven$EN = CAN_FIRE_RL_psdFFT_doIngress ;
// register unloadCnt
assign unloadCnt$D_IN =
(unloadCnt == 16'd4095) ? 16'd0 : unloadCnt + 16'd1 ;
assign unloadCnt$EN = CAN_FIRE_RL_psdFFT_doEgress ;
// register w2p_dataF_rCache
assign w2p_dataF_rCache$D_IN = { 1'd1, w2p_dataF_rWrPtr, x__h7434 } ;
assign w2p_dataF_rCache$EN = CAN_FIRE_RL_w2p_imprecise_enq ;
// register w2p_dataF_rRdPtr
assign w2p_dataF_rRdPtr$D_IN = x__h7326 ;
assign w2p_dataF_rRdPtr$EN = CAN_FIRE_RL_w2p_precise_deq ;
// register w2p_dataF_rWrPtr
assign w2p_dataF_rWrPtr$D_IN = w2p_dataF_rWrPtr + 13'd1 ;
assign w2p_dataF_rWrPtr$EN = CAN_FIRE_RL_w2p_imprecise_enq ;
// register w2p_wordsDequed
assign w2p_wordsDequed$D_IN =
w2p_wordsDequed_27_EQ_w2p_wordsExact_28_MINUS__ETC___d608 ?
16'd0 :
w2p_wordsDequed + 16'd1 ;
assign w2p_wordsDequed$EN = CAN_FIRE_RL_w2p_precise_deq ;
// register w2p_wordsEnqued
assign w2p_wordsEnqued$D_IN =
w2p_wordsEnqued_43_EQ_w2p_wordsExact_28_MINUS__ETC___d674 ?
16'd0 :
w2p_wordsEnqued + 16'd1 ;
assign w2p_wordsEnqued$EN = CAN_FIRE_RL_w2p_imprecise_enq ;
// register w2p_wordsExact
assign w2p_wordsExact$D_IN = 16'h0 ;
assign w2p_wordsExact$EN = 1'b0 ;
// register wci_cEdge
assign wci_cEdge$D_IN = wci_reqF$D_OUT[36:34] ;
assign wci_cEdge$EN = WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_cState
assign wci_cState$D_IN = wci_nState ;
assign wci_cState$EN =
WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge ;
// register wci_ctlAckReg
assign wci_ctlAckReg$D_IN = wci_ctlAckReg_1$whas ;
assign wci_ctlAckReg$EN = 1'd1 ;
// register wci_ctlOpActive
assign wci_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_ctl_op_complete ;
assign wci_ctlOpActive$EN =
WILL_FIRE_RL_wci_ctl_op_complete ||
WILL_FIRE_RL_wci_ctl_op_start ;
// register wci_illegalEdge
assign wci_illegalEdge$D_IN =
!MUX_wci_illegalEdge$write_1__SEL_1 &&
MUX_wci_illegalEdge$write_1__VAL_2 ;
assign wci_illegalEdge$EN =
WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge ||
MUX_wci_illegalEdge$write_1__SEL_2 ;
// register wci_nState
always@(wci_reqF$D_OUT)
begin
case (wci_reqF$D_OUT[36:34])
3'd0: wci_nState$D_IN = 3'd1;
3'd1: wci_nState$D_IN = 3'd2;
3'd2: wci_nState$D_IN = 3'd3;
default: wci_nState$D_IN = 3'd0;
endcase
end
assign wci_nState$EN =
WILL_FIRE_RL_wci_ctl_op_start &&
(wci_reqF$D_OUT[36:34] == 3'd0 && wci_cState == 3'd0 ||
wci_reqF$D_OUT[36:34] == 3'd1 &&
(wci_cState == 3'd1 || wci_cState == 3'd3) ||
wci_reqF$D_OUT[36:34] == 3'd2 && wci_cState == 3'd2 ||
wci_reqF$D_OUT[36:34] == 3'd3 &&
(wci_cState == 3'd3 || wci_cState == 3'd2 ||
wci_cState == 3'd1)) ;
// register wci_reqF_countReg
assign wci_reqF_countReg$D_IN =
(wci_wciReq$wget[59:57] != 3'd0) ?
wci_reqF_countReg + 2'd1 :
wci_reqF_countReg - 2'd1 ;
assign wci_reqF_countReg$EN = CAN_FIRE_RL_wci_reqF__updateLevelCounter ;
// register wci_respF_c_r
assign wci_respF_c_r$D_IN =
WILL_FIRE_RL_wci_respF_decCtr ?
MUX_wci_respF_c_r$write_1__VAL_1 :
MUX_wci_respF_c_r$write_1__VAL_2 ;
assign wci_respF_c_r$EN =
WILL_FIRE_RL_wci_respF_decCtr || WILL_FIRE_RL_wci_respF_incCtr ;
// register wci_respF_q_0
always@(MUX_wci_respF_q_0$write_1__SEL_1 or
MUX_wci_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_respF_decCtr or wci_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_0$write_1__SEL_1:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_0$D_IN = MUX_wci_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_0$D_IN = wci_respF_q_1;
default: wci_respF_q_0$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_0$EN =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_respF_q_1
always@(MUX_wci_respF_q_1$write_1__SEL_1 or
MUX_wci_respF_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wci_respF_both or
MUX_wci_respF_q_1$write_1__VAL_2 or WILL_FIRE_RL_wci_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_respF_q_1$write_1__SEL_1:
wci_respF_q_1$D_IN = MUX_wci_respF_q_0$write_1__VAL_1;
WILL_FIRE_RL_wci_respF_both:
wci_respF_q_1$D_IN = MUX_wci_respF_q_1$write_1__VAL_2;
WILL_FIRE_RL_wci_respF_decCtr: wci_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_respF_q_1$D_IN = 34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_respF_q_1$EN =
WILL_FIRE_RL_wci_respF_incCtr && wci_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_respF_both ||
WILL_FIRE_RL_wci_respF_decCtr ;
// register wci_sFlagReg
assign wci_sFlagReg$D_IN = 1'b0 ;
assign wci_sFlagReg$EN = 1'd1 ;
// register wci_sThreadBusy_d
assign wci_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[57]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0$write_1__SEL_1:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1$write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1$write_1__SEL_1:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset$VAL,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN = CAN_FIRE_RL_wsiM_inc_tBusyCount ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind$D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq$wget[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
wsiS_reqFifo_notFull__03_AND_wsiS_burstKind_83_ETC___d423 ;
// register wsiS_errorSticky
assign wsiS_errorSticky$D_IN = 1'd1 ;
assign wsiS_errorSticky$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && !wsiS_reqFifo$FULL_N ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount$D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_burstKind == 2'd2 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength$D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_wsiReq$wget[57] ;
// register wsiS_operateD
assign wsiS_operateD$D_IN = CAN_FIRE_RL_operating_actions ;
assign wsiS_operateD$EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount$D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N &&
wsiS_burstKind == 2'd1 &&
wsiS_wsiReq$wget[57] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady$D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady$EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg$D_IN =
MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg$EN =
CAN_FIRE_RL_wsiS_reqFifo__updateLevelCounter ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid$D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid$EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_reqFifo$FULL_N ||
WILL_FIRE_RL_psdPass_bypass ||
WILL_FIRE_RL_psdPrecise_input ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR$D_IN =
{ wsiS_isReset$VAL,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!CAN_FIRE_RL_wsiS_backpressure || wsiS_sThreadBusy_dw$wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR$EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount$D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount$EN = CAN_FIRE_RL_wsiS_inc_tBusyCount ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky$D_IN = 1'd1 ;
assign wsiS_trafficSticky$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
// register wsiS_wordCount
assign wsiS_wordCount$D_IN =
wsiS_wsiReq$wget[57] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount$EN = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
// submodule fft_fft
assign fft_fft$fwd_inv = 1'b0 ;
assign fft_fft$fwd_inv_we = 1'b0 ;
assign fft_fft$scale_sch = 12'd0 ;
assign fft_fft$scale_sch_we = 1'b0 ;
assign fft_fft$start = CAN_FIRE_RL_fft_frame_start ;
assign fft_fft$xn_im =
CAN_FIRE_RL_fft_fft_stream_ingress ?
fft_xnF$D_OUT[15:0] :
16'd0 ;
assign fft_fft$xn_re =
CAN_FIRE_RL_fft_fft_stream_ingress ?
fft_xnF$D_OUT[31:16] :
16'd0 ;
// submodule fft_xkF
assign fft_xkF$D_IN = { fft_fft$xk_re, fft_fft$xk_im } ;
assign fft_xkF$DEQ = CAN_FIRE_RL_psdFFT_doEgress ;
assign fft_xkF$ENQ = CAN_FIRE_RL_fft_fft_stream_egress ;
assign fft_xkF$CLR = 1'b0 ;
// submodule fft_xnF
assign fft_xnF$D_IN = { x__h13415, 16'd0 } ;
assign fft_xnF$DEQ = CAN_FIRE_RL_fft_fft_stream_ingress ;
assign fft_xnF$ENQ = CAN_FIRE_RL_psdFFT_doIngress ;
assign fft_xnF$CLR = 1'b0 ;
// submodule w2p_dataF_memory
assign w2p_dataF_memory$WEA = CAN_FIRE_RL_w2p_imprecise_enq ;
assign w2p_dataF_memory$ADDRA = w2p_dataF_rWrPtr[11:0] ;
assign w2p_dataF_memory$DIA = x__h7434 ;
assign w2p_dataF_memory$WEB = 1'd0 ;
assign w2p_dataF_memory$ADDRB =
CAN_FIRE_RL_w2p_precise_deq ?
x__h7326[11:0] :
w2p_dataF_rRdPtr[11:0] ;
assign w2p_dataF_memory$DIB = 32'hAAAAAAAA /* unspecified value */ ;
assign w2p_dataF_memory$ENA = 1'd1 ;
assign w2p_dataF_memory$ENB = 1'd1 ;
// submodule w2p_inF
assign w2p_inF$D_IN = wsiS_reqFifo$D_OUT ;
assign w2p_inF$DEQ = CAN_FIRE_RL_w2p_imprecise_enq ;
assign w2p_inF$ENQ = CAN_FIRE_RL_psdPrecise_input ;
assign w2p_inF$CLR = 1'b0 ;
// submodule w2p_outF
assign w2p_outF$D_IN =
{ 3'd1,
w2p_wordsDequed_27_EQ_w2p_wordsExact_28_MINUS__ETC___d608,
1'd1,
w2p_wordsExact[11:0],
x_data__h7856,
4'd15,
w2p_reqF$D_OUT } ;
assign w2p_outF$DEQ =
WILL_FIRE_RL_psdPrecise_output_bypassFFT ||
WILL_FIRE_RL_psdPrecise_output_feedFFT ;
assign w2p_outF$ENQ = CAN_FIRE_RL_w2p_precise_deq ;
assign w2p_outF$CLR = 1'b0 ;
// submodule w2p_reqF
assign w2p_reqF$D_IN = w2p_inF$D_OUT[7:0] ;
assign w2p_reqF$DEQ =
WILL_FIRE_RL_w2p_precise_deq &&
w2p_wordsDequed_27_EQ_w2p_wordsExact_28_MINUS__ETC___d608 ;
assign w2p_reqF$ENQ =
WILL_FIRE_RL_w2p_imprecise_enq &&
w2p_wordsEnqued_43_EQ_w2p_wordsExact_28_MINUS__ETC___d674 ;
assign w2p_reqF$CLR = 1'b0 ;
// submodule wci_reqF
assign wci_reqF$D_IN = wci_wciReq$wget ;
assign wci_reqF$DEQ = wci_reqF_r_deq$whas ;
assign wci_reqF$ENQ = CAN_FIRE_RL_wci_reqF_enq ;
assign wci_reqF$CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo$D_IN = wsiS_wsiReq$wget ;
assign wsiS_reqFifo$DEQ = wsiS_reqFifo_r_deq$whas ;
assign wsiS_reqFifo$ENQ = MUX_wsiS_reqFifo_levelsValid$write_1__SEL_4 ;
assign wsiS_reqFifo$CLR = 1'b0 ;
// submodule xnF
assign xnF$D_IN = w2p_outF$D_OUT[43:12] ;
assign xnF$DEQ = WILL_FIRE_RL_psdFFT_doIngress && !takeEven ;
assign xnF$ENQ = CAN_FIRE_RL_psdPrecise_output_feedFFT ;
assign xnF$CLR = 1'b0 ;
// remaining internal signals
assign IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d140 =
IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d646 /
16'd16 ;
assign IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d646 =
(IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d643 <=
IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d644) ?
IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d135 +
IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d644 :
IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d643 +
IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d137 ;
assign IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d137 =
IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d644 /
16'd2 ;
assign IF_fft_xkF_first__25_BIT_15_30_THEN_NEG_fft_xk_ETC___d644 =
fft_xkF$D_OUT[15] ? -fft_xkF$D_OUT[15:0] : fft_xkF$D_OUT[15:0] ;
assign IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d135 =
IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d643 /
16'd2 ;
assign IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_xk_ETC___d643 =
fft_xkF$D_OUT[31] ?
-fft_xkF$D_OUT[31:16] :
fft_xkF$D_OUT[31:16] ;
assign NOT_w2p_dataF_rRdPtr_11_PLUS_2048_39_EQ_w2p_da_ETC___d349 =
w2p_dataF_rRdPtr + 13'd2048 != w2p_dataF_rWrPtr &&
w2p_inF$EMPTY_N &&
(!w2p_wordsEnqued_43_EQ_w2p_wordsExact_28_MINUS__ETC___d674 ||
w2p_reqF$FULL_N) ;
assign dReal__h13383 = takeEven ? xnF$D_OUT[15:0] : xnF$D_OUT[31:16] ;
assign psdStatus__h14238 = { 31'd0, hasDebugLogic } ;
assign rdat__h14517 = hasDebugLogic ? { 16'd0, x__h14521 } : 32'd0 ;
assign rdat__h14617 = hasDebugLogic ? wsiS_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h14631 = hasDebugLogic ? wsiS_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h14639 = hasDebugLogic ? wsiS_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h14645 = hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
assign rdat__h14659 = hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
assign rdat__h14667 = hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
assign rdat__h14673 = hasDebugLogic ? x_fftFrameCounts__h12666 : 32'd0 ;
assign result__h13444 = { ~dReal__h13383[15], dReal__h13383[14:0] } ;
assign w2p_wordsDequed_27_EQ_w2p_wordsExact_28_MINUS__ETC___d608 =
w2p_wordsDequed == w2p_wordsExact_28_MINUS_1___d645 ;
assign w2p_wordsEnqued_43_EQ_w2p_wordsExact_28_MINUS__ETC___d674 =
w2p_wordsEnqued == w2p_wordsExact_28_MINUS_1___d645 ;
assign w2p_wordsExact_28_MINUS_1___d645 = w2p_wordsExact - 16'd1 ;
assign wsiS_reqFifo_notFull__03_AND_wsiS_burstKind_83_ETC___d423 =
wsiS_reqFifo$FULL_N &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq$wget[57]) ;
assign x__h13415 = psdCtrl[4] ? result__h13444 : dReal__h13383 ;
assign x__h14521 = { wsiS_statusR, wsiM_statusR } ;
assign x__h7326 = w2p_dataF_rRdPtr + 13'd1 ;
assign x__h7434 =
CAN_FIRE_RL_w2p_imprecise_enq ? w2p_inF$D_OUT[43:12] : 32'd0 ;
assign x_data__h13251 =
{ IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d646 -
IF_IF_fft_xkF_first__25_BIT_31_26_THEN_NEG_fft_ETC___d140,
evenMag } ;
assign x_data__h7856 =
(w2p_dataF_rCache[45] &&
w2p_dataF_rCache[44:32] == w2p_dataF_rRdPtr) ?
w2p_dataF_rCache[31:0] :
w2p_dataF_memory$DOB ;
assign x_fftFrameCounts__h12666 = { fft_loadFrames, fft_unloadFrames } ;
always@(wci_reqF$D_OUT or
psdStatus__h14238 or
psdCtrl or
rdat__h14517 or
rdat__h14617 or
rdat__h14631 or
rdat__h14639 or
rdat__h14645 or rdat__h14659 or rdat__h14667 or rdat__h14673)
begin
case (wci_reqF$D_OUT[51:32])
20'h0: x_data__h14493 = psdStatus__h14238;
20'h00004: x_data__h14493 = psdCtrl;
20'h00010: x_data__h14493 = rdat__h14517;
20'h00014: x_data__h14493 = rdat__h14617;
20'h00018: x_data__h14493 = rdat__h14631;
20'h0001C: x_data__h14493 = rdat__h14639;
20'h00020: x_data__h14493 = rdat__h14645;
20'h00024: x_data__h14493 = rdat__h14659;
20'h00028: x_data__h14493 = rdat__h14667;
20'h0002C: x_data__h14493 = rdat__h14673;
default: x_data__h14493 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (!wciS0_MReset_n)
begin
fft_fftStarted <= `BSV_ASSIGNMENT_DELAY 1'd0;
fft_loadFrames <= `BSV_ASSIGNMENT_DELAY 16'd0;
fft_loadIndex <= `BSV_ASSIGNMENT_DELAY 16'd0;
fft_unloadFrames <= `BSV_ASSIGNMENT_DELAY 16'd0;
fft_unloadIndex <= `BSV_ASSIGNMENT_DELAY 16'd0;
psdCtrl <= `BSV_ASSIGNMENT_DELAY psdCtrlInit;
sendEven <= `BSV_ASSIGNMENT_DELAY 1'd1;
takeEven <= `BSV_ASSIGNMENT_DELAY 1'd1;
unloadCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
w2p_dataF_rCache <= `BSV_ASSIGNMENT_DELAY 46'h0AAAAAAAAAAA;
w2p_dataF_rRdPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
w2p_dataF_rWrPtr <= `BSV_ASSIGNMENT_DELAY 13'd0;
w2p_wordsDequed <= `BSV_ASSIGNMENT_DELAY 16'd0;
w2p_wordsEnqued <= `BSV_ASSIGNMENT_DELAY 16'd0;
w2p_wordsExact <= `BSV_ASSIGNMENT_DELAY 16'd2048;
wci_cEdge <= `BSV_ASSIGNMENT_DELAY 3'd7;
wci_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (fft_fftStarted$EN)
fft_fftStarted <= `BSV_ASSIGNMENT_DELAY fft_fftStarted$D_IN;
if (fft_loadFrames$EN)
fft_loadFrames <= `BSV_ASSIGNMENT_DELAY fft_loadFrames$D_IN;
if (fft_loadIndex$EN)
fft_loadIndex <= `BSV_ASSIGNMENT_DELAY fft_loadIndex$D_IN;
if (fft_unloadFrames$EN)
fft_unloadFrames <= `BSV_ASSIGNMENT_DELAY fft_unloadFrames$D_IN;
if (fft_unloadIndex$EN)
fft_unloadIndex <= `BSV_ASSIGNMENT_DELAY fft_unloadIndex$D_IN;
if (psdCtrl$EN) psdCtrl <= `BSV_ASSIGNMENT_DELAY psdCtrl$D_IN;
if (sendEven$EN) sendEven <= `BSV_ASSIGNMENT_DELAY sendEven$D_IN;
if (takeEven$EN) takeEven <= `BSV_ASSIGNMENT_DELAY takeEven$D_IN;
if (unloadCnt$EN) unloadCnt <= `BSV_ASSIGNMENT_DELAY unloadCnt$D_IN;
if (w2p_dataF_rCache$EN)
w2p_dataF_rCache <= `BSV_ASSIGNMENT_DELAY w2p_dataF_rCache$D_IN;
if (w2p_dataF_rRdPtr$EN)
w2p_dataF_rRdPtr <= `BSV_ASSIGNMENT_DELAY w2p_dataF_rRdPtr$D_IN;
if (w2p_dataF_rWrPtr$EN)
w2p_dataF_rWrPtr <= `BSV_ASSIGNMENT_DELAY w2p_dataF_rWrPtr$D_IN;
if (w2p_wordsDequed$EN)
w2p_wordsDequed <= `BSV_ASSIGNMENT_DELAY w2p_wordsDequed$D_IN;
if (w2p_wordsEnqued$EN)
w2p_wordsEnqued <= `BSV_ASSIGNMENT_DELAY w2p_wordsEnqued$D_IN;
if (w2p_wordsExact$EN)
w2p_wordsExact <= `BSV_ASSIGNMENT_DELAY w2p_wordsExact$D_IN;
if (wci_cEdge$EN) wci_cEdge <= `BSV_ASSIGNMENT_DELAY wci_cEdge$D_IN;
if (wci_cState$EN)
wci_cState <= `BSV_ASSIGNMENT_DELAY wci_cState$D_IN;
if (wci_ctlAckReg$EN)
wci_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_ctlAckReg$D_IN;
if (wci_ctlOpActive$EN)
wci_ctlOpActive <= `BSV_ASSIGNMENT_DELAY wci_ctlOpActive$D_IN;
if (wci_illegalEdge$EN)
wci_illegalEdge <= `BSV_ASSIGNMENT_DELAY wci_illegalEdge$D_IN;
if (wci_nState$EN)
wci_nState <= `BSV_ASSIGNMENT_DELAY wci_nState$D_IN;
if (wci_reqF_countReg$EN)
wci_reqF_countReg <= `BSV_ASSIGNMENT_DELAY wci_reqF_countReg$D_IN;
if (wci_respF_c_r$EN)
wci_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_respF_c_r$D_IN;
if (wci_respF_q_0$EN)
wci_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_0$D_IN;
if (wci_respF_q_1$EN)
wci_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_respF_q_1$D_IN;
if (wci_sFlagReg$EN)
wci_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_sFlagReg$D_IN;
if (wci_sThreadBusy_d$EN)
wci_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wci_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
if (wsiS_burstKind$EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind$D_IN;
if (wsiS_errorSticky$EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky$D_IN;
if (wsiS_iMesgCount$EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount$D_IN;
if (wsiS_operateD$EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD$D_IN;
if (wsiS_pMesgCount$EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount$D_IN;
if (wsiS_peerIsReady$EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady$D_IN;
if (wsiS_reqFifo_countReg$EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg$D_IN;
if (wsiS_reqFifo_levelsValid$EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid$D_IN;
if (wsiS_tBusyCount$EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount$D_IN;
if (wsiS_trafficSticky$EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky$D_IN;
if (wsiS_wordCount$EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount$D_IN;
end
if (evenMag$EN) evenMag <= `BSV_ASSIGNMENT_DELAY evenMag$D_IN;
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
if (wsiS_mesgWordLength$EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength$D_IN;
if (wsiS_statusR$EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
evenMag = 16'hAAAA;
fft_fftStarted = 1'h0;
fft_loadFrames = 16'hAAAA;
fft_loadIndex = 16'hAAAA;
fft_unloadFrames = 16'hAAAA;
fft_unloadIndex = 16'hAAAA;
psdCtrl = 32'hAAAAAAAA;
sendEven = 1'h0;
takeEven = 1'h0;
unloadCnt = 16'hAAAA;
w2p_dataF_rCache = 46'h2AAAAAAAAAAA;
w2p_dataF_rRdPtr = 13'h0AAA;
w2p_dataF_rWrPtr = 13'h0AAA;
w2p_wordsDequed = 16'hAAAA;
w2p_wordsEnqued = 16'hAAAA;
w2p_wordsExact = 16'hAAAA;
wci_cEdge = 3'h2;
wci_cState = 3'h2;
wci_ctlAckReg = 1'h0;
wci_ctlOpActive = 1'h0;
wci_illegalEdge = 1'h0;
wci_nState = 3'h2;
wci_reqF_countReg = 2'h2;
wci_respF_c_r = 2'h2;
wci_respF_q_0 = 34'h2AAAAAAAA;
wci_respF_q_1 = 34'h2AAAAAAAA;
wci_sFlagReg = 1'h0;
wci_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
begin
v__h3671 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3671,
wci_reqF$D_OUT[36:34],
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h14361 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting PSD psdCtrl:%0x", v__h14361, psdCtrl);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/PSD.bsv\", line 198, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_IsO and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/PSD.bsv\", line 204, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_IsO fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctrl_OrE && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/PSD.bsv\", line 204, column 6: (R0001)\n Mutually exclusive rules RL_wci_ctrl_OrE and RL_wci_ctrl_EiI fired in the\n same clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/PSD.bsv\", line 180, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/PSD.bsv\", line 180, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/PSD.bsv\", line 180, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfrd and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
begin
v__h2772 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h2772,
wci_cEdge,
wci_cState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
begin
v__h2625 = $time;
#0;
end
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_ctl_op_complete && !wci_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h2625,
wci_cEdge,
wci_cState,
wci_nState);
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/PSD.bsv\", line 171, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_OrE fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/PSD.bsv\", line 171, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_IsO fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/PSD.bsv\", line 171, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_ctrl_EiI fired in the same\n clock cycle.\n");
if (wciS0_MReset_n)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/PSD.bsv\", line 171, column 6: (R0001)\n Mutually exclusive rules RL_wci_cfwr and RL_wci_cfrd fired in the same clock\n cycle.\n");
end
// synopsys translate_on
endmodule // mkPSD
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_eac_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:29 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_eac_e.v,v 1.1 2004/04/06 10:50:23 wig Exp $
// $Date: 2004/04/06 10:50:23 $
// $Log: inst_eac_e.v,v $
// Revision 1.1 2004/04/06 10:50:23 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_eac_e
//
// No `defines in this module
module inst_eac_e
//
// Generated module inst_eac
//
(
adp_bist_fail,
cp_laddr,
cp_lcmd,
cpu_bist_fail,
cvi_sbist_fail0,
cvi_sbist_fail1,
ema_bist_fail,
ga_sbist_fail0,
ga_sbist_fail1,
gpio_int,
ifu_bist_fail,
mcu_bist_fail,
nreset,
nreset_s,
pdu_bist_fail0,
pdu_bist_fail1,
tmu_dac_reset,
tsd_bist_fail
);
// Generated Module Inputs:
input [31:0] cp_laddr;
input [6:0] cp_lcmd;
input cvi_sbist_fail0;
input cvi_sbist_fail1;
input ga_sbist_fail0;
input ga_sbist_fail1;
input nreset;
input nreset_s;
// Generated Module Outputs:
output adp_bist_fail;
output cpu_bist_fail;
output ema_bist_fail;
output [4:0] gpio_int;
output ifu_bist_fail;
output mcu_bist_fail;
output pdu_bist_fail0;
output pdu_bist_fail1;
output tmu_dac_reset;
output tsd_bist_fail;
// Generated Wires:
wire adp_bist_fail;
wire [31:0] cp_laddr;
wire [6:0] cp_lcmd;
wire cpu_bist_fail;
wire cvi_sbist_fail0;
wire cvi_sbist_fail1;
wire ema_bist_fail;
wire ga_sbist_fail0;
wire ga_sbist_fail1;
wire [4:0] gpio_int;
wire ifu_bist_fail;
wire mcu_bist_fail;
wire nreset;
wire nreset_s;
wire pdu_bist_fail0;
wire pdu_bist_fail1;
wire tmu_dac_reset;
wire tsd_bist_fail;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_eac_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
(** * Maps: Total and Partial Maps *)
(** Maps (or dictionaries) are ubiquitous data structures, both in
software construction generally and in the theory of programming
languages in particular; we're going to need them in many places
in the coming chapters. They also make a nice case study using
ideas we've seen in previous chapters, including building data
structures out of higher-order functions (from [Basics] and
[Poly]) and the use of reflection to streamline proofs (from
[IndProp]).
We'll define two flavors of maps: _total_ maps, which include a
"default" element to be returned when a key being looked up
doesn't exist, and _partial_ maps, which return an [option] to
indicate success or failure. The latter is defined in terms of
the former, using [None] as the default element. *)
(* ###################################################################### *)
(** * The Coq Standard Library *)
(** One small digression before we start.
Unlike the chapters we have seen so far, this one does not
[Require Import] the chapter before it (and, transitively, all the
earlier chapters). Instead, in this chapter and from now, on
we're going to import the definitions and theorems we need
directly from Coq's standard library stuff. You should not notice
much difference, though, because we've been careful to name our
own definitions and theorems the same as their counterparts in the
standard library, wherever they overlap. *)
Require Import Coq.Arith.Arith.
Require Import Coq.Bool.Bool.
Require Import Coq.Logic.FunctionalExtensionality.
(** Documentation for the standard library can be found at
http://coq.inria.fr/library/.
The [SearchAbout] command is a good way to look for theorems
involving objects of specific types. *)
(* ###################################################################### *)
(** * Identifiers *)
(** First, we need a type for the keys that we use to index into our
maps. For this purpose, we again use the type [id] from the
[Lists] chapter. To make this chapter self contained, we repeat
its definition here, together with the equality comparison
function for [id]s and its fundamental property. *)
Inductive id : Type :=
| Id : nat -> id.
Definition beq_id id1 id2 :=
match id1,id2 with
| Id n1, Id n2 => beq_nat n1 n2
end.
Theorem beq_id_refl : forall id, true = beq_id id id.
Proof.
intros [n]. simpl. rewrite <- beq_nat_refl.
reflexivity. Qed.
(** (In the HTML version, the proof of this theorem is elided, since
the details are pretty routine at this point. Click on the box if
you want to see it.)
The following useful property of [beq_id] follows from an
analogous lemma about numbers: *)
Theorem beq_id_true_iff : forall id1 id2 : id,
beq_id id1 id2 = true <-> id1 = id2.
Proof.
intros [n1] [n2].
unfold beq_id.
rewrite beq_nat_true_iff.
split.
- (* -> *) intros H. rewrite H. reflexivity.
- (* <- *) intros H. inversion H. reflexivity.
Qed.
(** Similarly: *)
Theorem beq_id_false_iff : forall x y : id,
beq_id x y = false
<-> x <> y.
Proof.
intros x y. rewrite <- beq_id_true_iff.
rewrite not_true_iff_false. reflexivity. Qed.
(** This useful variant follows just by rewriting: *)
Theorem false_beq_id : forall x y : id,
x <> y
-> beq_id x y = false.
Proof.
intros x y. rewrite beq_id_false_iff.
intros H. apply H. Qed.
(* ###################################################################### *)
(** * Total Maps *)
(** Our main job in this chapter will be to build a definition of
partial maps that is similar in behavior to the one we saw in the
[Lists] chapter, plus accompanying lemmas about their behavior.
This time around, though, we're going to use _functions_, rather
than lists of key-value pairs, to build maps. The advantage of
this representation is that it offers a more _extensional_ view of
maps, where two maps that respond to queries in the same way will
be represented as literally the same thing (the same function),
rather than just "equivalent" data structures. This, in turn,
simplifies proofs that use maps.
We build partial maps in two steps. First, we define a type of
_total maps_ that return a default value when we look up a key
that is not present in the map. *)
Definition total_map (A:Type) := id -> A.
(** Intuitively, a total map over an element type [A] _is_ just a
function that can be used to look up [id]s, yielding [A]s.
The function [t_empty] yields an empty total map, given a default
element; this map always returns the default element when applied
to any id. *)
Definition t_empty {A:Type} (v : A) : total_map A :=
(fun _ => v).
(** More interesting is the [update] function, which (as before) takes
a map [m], a key [x], and a value [v] and returns a new map that
takes [x] to [v] and takes every other key to whatever [m] does. *)
Definition t_update {A:Type} (m : total_map A)
(x : id) (v : A) :=
fun x' => if beq_id x x' then v else m x'.
(** This definition is a nice example of higher-order programming.
The [t_update] function takes a _function_ [m] and yields a new
function [fun x' => ...] that behaves like the desired map.
For example, we can build a map taking [id]s to [bool]s, where [Id
3] is mapped to [true] and every other key is mapped to [false],
like this: *)
Definition examplemap :=
t_update (t_update (t_empty false) (Id 1) false)
(Id 3) true.
(** This completes the definition of total maps. Note that we don't
need to define a [find] operation because it is just function
application! *)
Example update_example1 : examplemap (Id 0) = false.
Proof. reflexivity. Qed.
Example update_example2 : examplemap (Id 1) = false.
Proof. reflexivity. Qed.
Example update_example3 : examplemap (Id 2) = false.
Proof. reflexivity. Qed.
Example update_example4 : examplemap (Id 3) = true.
Proof. reflexivity. Qed.
(** To use maps in later chapters, we'll need several fundamental
facts about how they behave. Even if you don't work the following
exercises, make sure you thoroughly understand the statements of
the lemmas! (Some of the proofs require the functional
extensionality axiom discussed in the [Logic] chapter, which is
also included in the standard library.) *)
(** **** Exercise: 2 stars, optional (t_update_eq) *)
(** First, if we update a map [m] at a key [x] with a new value [v]
and then look up [x] in the map resulting from the [update], we
get back [v]: *)
Lemma t_update_eq : forall A (m: total_map A) x v,
(t_update m x v) x = v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_neq) *)
(** On the other hand, if we update a map [m] at a key [x1] and then
look up a _different_ key [x2] in the resulting map, we get the
same result that [m] would have given: *)
Theorem t_update_neq : forall (X:Type) v x1 x2
(m : total_map X),
x1 <> x2 ->
(t_update m x1 v) x2 = m x2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (t_update_shadow) *)
(** If we update a map [m] at a key [x] with a value [v1] and then
update again with the same key [x] and another value [v2], the
resulting map behaves the same (gives the same result when applied
to any key) as the simpler map obtained by performing just
the second [update] on [m]: *)
Lemma t_update_shadow : forall A (m: total_map A) v1 v2 x,
t_update (t_update m x v1) x v2
= t_update m x v2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** For the final two lemmas about total maps, it's convenient to use
the reflection idioms introduced in chapter [IndProp]. We begin
by proving a fundamental _reflection lemma_ relating the equality
proposition on [id]s with the boolean function [beq_id]. *)
(** **** Exercise: 2 stars (beq_idP) *)
(** Use the proof of [beq_natP] in chapter [IndProp] as a template to
prove the following: *)
Lemma beq_idP : forall x y, reflect (x = y) (beq_id x y).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Now, given [id]s [x1] and [x2], we can use the [destruct (beq_idP
x1 x2)] to simultaneously perform case analysis on the result of
[beq_id x1 x2] and generate hypotheses about the equality (in the
sense of [=]) of [x1] and [x2]. *)
(** **** Exercise: 2 stars (t_update_same) *)
(** Using the example in chapter [IndProp] as a template, use
[beq_idP] to prove the following theorem, which states that if we
update a map to assign key [x] the same value as it already has in
[m], then the result is equal to [m]: *)
Theorem t_update_same : forall X x (m : total_map X),
t_update m x (m x) = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, recommended (t_update_permute) *)
(** Use [beq_idP] to prove one final property of the [update]
function: If we update a map [m] at two distinct keys, it doesn't
matter in which order we do the updates. *)
Theorem t_update_permute : forall (X:Type) v1 v2 x1 x2
(m : total_map X),
x2 <> x1 ->
(t_update (t_update m x2 v2) x1 v1)
= (t_update (t_update m x1 v1) x2 v2).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################################### *)
(** * Partial maps *)
(** Finally, we define _partial maps_ on top of total maps. A partial
map with elements of type [A] is simply a total map with elements
of type [option A] and default element [None]. *)
Definition partial_map (A:Type) := total_map (option A).
Definition empty {A:Type} : partial_map A :=
t_empty None.
Definition update {A:Type} (m : partial_map A)
(x : id) (v : A) :=
t_update m x (Some v).
(** We can now lift all of the basic lemmas about total maps to
partial maps. *)
Lemma update_eq : forall A (m: partial_map A) x v,
(update m x v) x = Some v.
Proof.
intros. unfold update. rewrite t_update_eq.
reflexivity.
Qed.
Theorem update_neq : forall (X:Type) v x1 x2
(m : partial_map X),
x2 <> x1 ->
(update m x2 v) x1 = m x1.
Proof.
intros X v x1 x2 m H.
unfold update. rewrite t_update_neq. reflexivity.
apply H. Qed.
Lemma update_shadow : forall A (m: partial_map A) v1 v2 x,
update (update m x v1) x v2 = update m x v2.
Proof.
intros A m v1 v2 x1. unfold update. rewrite t_update_shadow.
reflexivity.
Qed.
Theorem update_same : forall X v x (m : partial_map X),
m x = Some v ->
update m x v = m.
Proof.
intros X v x m H. unfold update. rewrite <- H.
apply t_update_same.
Qed.
Theorem update_permute : forall (X:Type) v1 v2 x1 x2
(m : partial_map X),
x2 <> x1 ->
(update (update m x2 v2) x1 v1)
= (update (update m x1 v1) x2 v2).
Proof.
intros X v1 v2 x1 x2 m. unfold update.
apply t_update_permute.
Qed.
(** $Date: 2015-12-11 17:17:29 -0500 (Fri, 11 Dec 2015) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_S_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_S_BLACKBOX_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_pwrgood_pp$PG$S (
UDP_OUT,
UDP_IN ,
VPWR ,
VGND ,
SLEEP
);
output UDP_OUT;
input UDP_IN ;
input VPWR ;
input VGND ;
input SLEEP ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_PWRGOOD_PP_PG_S_BLACKBOX_V
|
// lpddr2_cntrlr_s0.v
// This file was auto-generated from qsys_sequencer_110_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module lpddr2_cntrlr_s0 (
input wire avl_clk, // avl_clk.clk
input wire avl_reset_n, // sequencer_rst.reset
output wire [15:0] avl_address, // avl.address
output wire avl_read, // .read
input wire [31:0] avl_readdata, // .readdata
output wire avl_write, // .write
output wire [31:0] avl_writedata, // .writedata
input wire avl_waitrequest, // .waitrequest
output wire [0:0] scc_data, // scc.scc_data
output wire [3:0] scc_dqs_ena, // .scc_dqs_ena
output wire [3:0] scc_dqs_io_ena, // .scc_dqs_io_ena
output wire [31:0] scc_dq_ena, // .scc_dq_ena
output wire [3:0] scc_dm_ena, // .scc_dm_ena
input wire [3:0] capture_strobe_tracking, // .capture_strobe_tracking
output wire [0:0] scc_upd, // .scc_upd
input wire afi_init_req, // afi_init_cal_req.afi_init_req
input wire afi_cal_req, // .afi_cal_req
input wire scc_clk, // scc_clk.clk
input wire reset_n_scc_clk, // scc_reset.reset_n
output wire [0:0] afi_seq_busy, // trk_afi.afi_seq_busy
input wire [0:0] afi_ctl_long_idle, // .afi_ctl_long_idle
input wire [0:0] afi_ctl_refresh_done // .afi_ctl_refresh_done
);
wire sequencer_rst_reset_out_reset; // sequencer_rst:reset_out -> [cpu_inst:reset_n, hphy_bridge:reset_n, irq_mapper:reset, mm_interconnect_0:cpu_inst_reset_n_reset_bridge_in_reset_reset, mm_interconnect_0:sequencer_trk_mgr_inst_avl_reset_reset_bridge_in_reset_reset, mm_interconnect_1:trk_mm_bridge_reset_reset_bridge_in_reset_reset, sequencer_mem:reset1, sequencer_reg_file_inst:avl_reset_n, sequencer_scc_mgr_inst:avl_reset_n, sequencer_trk_mgr_inst:avl_reset_n, trk_mm_bridge:reset]
wire sequencer_rst_clken_out_clken; // sequencer_rst:clken_out -> sequencer_mem:clken1
wire [31:0] cpu_inst_data_master_readdata; // mm_interconnect_0:cpu_inst_data_master_readdata -> cpu_inst:d_readdata
wire cpu_inst_data_master_waitrequest; // mm_interconnect_0:cpu_inst_data_master_waitrequest -> cpu_inst:d_waitrequest
wire [19:0] cpu_inst_data_master_address; // cpu_inst:d_address -> mm_interconnect_0:cpu_inst_data_master_address
wire [3:0] cpu_inst_data_master_byteenable; // cpu_inst:d_byteenable -> mm_interconnect_0:cpu_inst_data_master_byteenable
wire cpu_inst_data_master_read; // cpu_inst:d_read -> mm_interconnect_0:cpu_inst_data_master_read
wire cpu_inst_data_master_write; // cpu_inst:d_write -> mm_interconnect_0:cpu_inst_data_master_write
wire [31:0] cpu_inst_data_master_writedata; // cpu_inst:d_writedata -> mm_interconnect_0:cpu_inst_data_master_writedata
wire [31:0] sequencer_trk_mgr_inst_trkm_readdata; // mm_interconnect_0:sequencer_trk_mgr_inst_trkm_readdata -> sequencer_trk_mgr_inst:trkm_readdata
wire sequencer_trk_mgr_inst_trkm_waitrequest; // mm_interconnect_0:sequencer_trk_mgr_inst_trkm_waitrequest -> sequencer_trk_mgr_inst:trkm_waitrequest
wire [19:0] sequencer_trk_mgr_inst_trkm_address; // sequencer_trk_mgr_inst:trkm_address -> mm_interconnect_0:sequencer_trk_mgr_inst_trkm_address
wire sequencer_trk_mgr_inst_trkm_read; // sequencer_trk_mgr_inst:trkm_read -> mm_interconnect_0:sequencer_trk_mgr_inst_trkm_read
wire sequencer_trk_mgr_inst_trkm_write; // sequencer_trk_mgr_inst:trkm_write -> mm_interconnect_0:sequencer_trk_mgr_inst_trkm_write
wire [31:0] sequencer_trk_mgr_inst_trkm_writedata; // sequencer_trk_mgr_inst:trkm_writedata -> mm_interconnect_0:sequencer_trk_mgr_inst_trkm_writedata
wire [31:0] cpu_inst_instruction_master_readdata; // mm_interconnect_0:cpu_inst_instruction_master_readdata -> cpu_inst:i_readdata
wire cpu_inst_instruction_master_waitrequest; // mm_interconnect_0:cpu_inst_instruction_master_waitrequest -> cpu_inst:i_waitrequest
wire [16:0] cpu_inst_instruction_master_address; // cpu_inst:i_address -> mm_interconnect_0:cpu_inst_instruction_master_address
wire cpu_inst_instruction_master_read; // cpu_inst:i_read -> mm_interconnect_0:cpu_inst_instruction_master_read
wire [31:0] mm_interconnect_0_trk_mm_bridge_s0_readdata; // trk_mm_bridge:s0_readdata -> mm_interconnect_0:trk_mm_bridge_s0_readdata
wire mm_interconnect_0_trk_mm_bridge_s0_waitrequest; // trk_mm_bridge:s0_waitrequest -> mm_interconnect_0:trk_mm_bridge_s0_waitrequest
wire mm_interconnect_0_trk_mm_bridge_s0_debugaccess; // mm_interconnect_0:trk_mm_bridge_s0_debugaccess -> trk_mm_bridge:s0_debugaccess
wire [15:0] mm_interconnect_0_trk_mm_bridge_s0_address; // mm_interconnect_0:trk_mm_bridge_s0_address -> trk_mm_bridge:s0_address
wire mm_interconnect_0_trk_mm_bridge_s0_read; // mm_interconnect_0:trk_mm_bridge_s0_read -> trk_mm_bridge:s0_read
wire [3:0] mm_interconnect_0_trk_mm_bridge_s0_byteenable; // mm_interconnect_0:trk_mm_bridge_s0_byteenable -> trk_mm_bridge:s0_byteenable
wire mm_interconnect_0_trk_mm_bridge_s0_readdatavalid; // trk_mm_bridge:s0_readdatavalid -> mm_interconnect_0:trk_mm_bridge_s0_readdatavalid
wire mm_interconnect_0_trk_mm_bridge_s0_write; // mm_interconnect_0:trk_mm_bridge_s0_write -> trk_mm_bridge:s0_write
wire [31:0] mm_interconnect_0_trk_mm_bridge_s0_writedata; // mm_interconnect_0:trk_mm_bridge_s0_writedata -> trk_mm_bridge:s0_writedata
wire [0:0] mm_interconnect_0_trk_mm_bridge_s0_burstcount; // mm_interconnect_0:trk_mm_bridge_s0_burstcount -> trk_mm_bridge:s0_burstcount
wire [31:0] mm_interconnect_0_hphy_bridge_s0_readdata; // hphy_bridge:s0_readdata -> mm_interconnect_0:hphy_bridge_s0_readdata
wire mm_interconnect_0_hphy_bridge_s0_waitrequest; // hphy_bridge:s0_waitrequest -> mm_interconnect_0:hphy_bridge_s0_waitrequest
wire [15:0] mm_interconnect_0_hphy_bridge_s0_address; // mm_interconnect_0:hphy_bridge_s0_address -> hphy_bridge:s0_address
wire mm_interconnect_0_hphy_bridge_s0_read; // mm_interconnect_0:hphy_bridge_s0_read -> hphy_bridge:s0_read
wire mm_interconnect_0_hphy_bridge_s0_write; // mm_interconnect_0:hphy_bridge_s0_write -> hphy_bridge:s0_write
wire [31:0] mm_interconnect_0_hphy_bridge_s0_writedata; // mm_interconnect_0:hphy_bridge_s0_writedata -> hphy_bridge:s0_writedata
wire mm_interconnect_0_sequencer_mem_s1_chipselect; // mm_interconnect_0:sequencer_mem_s1_chipselect -> sequencer_mem:s1_chipselect
wire [31:0] mm_interconnect_0_sequencer_mem_s1_readdata; // sequencer_mem:s1_readdata -> mm_interconnect_0:sequencer_mem_s1_readdata
wire [11:0] mm_interconnect_0_sequencer_mem_s1_address; // mm_interconnect_0:sequencer_mem_s1_address -> sequencer_mem:s1_address
wire [3:0] mm_interconnect_0_sequencer_mem_s1_byteenable; // mm_interconnect_0:sequencer_mem_s1_byteenable -> sequencer_mem:s1_be
wire mm_interconnect_0_sequencer_mem_s1_write; // mm_interconnect_0:sequencer_mem_s1_write -> sequencer_mem:s1_write
wire [31:0] mm_interconnect_0_sequencer_mem_s1_writedata; // mm_interconnect_0:sequencer_mem_s1_writedata -> sequencer_mem:s1_writedata
wire [31:0] mm_interconnect_0_sequencer_trk_mgr_inst_trks_readdata; // sequencer_trk_mgr_inst:trks_readdata -> mm_interconnect_0:sequencer_trk_mgr_inst_trks_readdata
wire mm_interconnect_0_sequencer_trk_mgr_inst_trks_waitrequest; // sequencer_trk_mgr_inst:trks_waitrequest -> mm_interconnect_0:sequencer_trk_mgr_inst_trks_waitrequest
wire [5:0] mm_interconnect_0_sequencer_trk_mgr_inst_trks_address; // mm_interconnect_0:sequencer_trk_mgr_inst_trks_address -> sequencer_trk_mgr_inst:trks_address
wire mm_interconnect_0_sequencer_trk_mgr_inst_trks_read; // mm_interconnect_0:sequencer_trk_mgr_inst_trks_read -> sequencer_trk_mgr_inst:trks_read
wire mm_interconnect_0_sequencer_trk_mgr_inst_trks_write; // mm_interconnect_0:sequencer_trk_mgr_inst_trks_write -> sequencer_trk_mgr_inst:trks_write
wire [31:0] mm_interconnect_0_sequencer_trk_mgr_inst_trks_writedata; // mm_interconnect_0:sequencer_trk_mgr_inst_trks_writedata -> sequencer_trk_mgr_inst:trks_writedata
wire trk_mm_bridge_m0_waitrequest; // mm_interconnect_1:trk_mm_bridge_m0_waitrequest -> trk_mm_bridge:m0_waitrequest
wire [31:0] trk_mm_bridge_m0_readdata; // mm_interconnect_1:trk_mm_bridge_m0_readdata -> trk_mm_bridge:m0_readdata
wire trk_mm_bridge_m0_debugaccess; // trk_mm_bridge:m0_debugaccess -> mm_interconnect_1:trk_mm_bridge_m0_debugaccess
wire [15:0] trk_mm_bridge_m0_address; // trk_mm_bridge:m0_address -> mm_interconnect_1:trk_mm_bridge_m0_address
wire trk_mm_bridge_m0_read; // trk_mm_bridge:m0_read -> mm_interconnect_1:trk_mm_bridge_m0_read
wire [3:0] trk_mm_bridge_m0_byteenable; // trk_mm_bridge:m0_byteenable -> mm_interconnect_1:trk_mm_bridge_m0_byteenable
wire trk_mm_bridge_m0_readdatavalid; // mm_interconnect_1:trk_mm_bridge_m0_readdatavalid -> trk_mm_bridge:m0_readdatavalid
wire [31:0] trk_mm_bridge_m0_writedata; // trk_mm_bridge:m0_writedata -> mm_interconnect_1:trk_mm_bridge_m0_writedata
wire trk_mm_bridge_m0_write; // trk_mm_bridge:m0_write -> mm_interconnect_1:trk_mm_bridge_m0_write
wire [0:0] trk_mm_bridge_m0_burstcount; // trk_mm_bridge:m0_burstcount -> mm_interconnect_1:trk_mm_bridge_m0_burstcount
wire [31:0] mm_interconnect_1_sequencer_scc_mgr_inst_avl_readdata; // sequencer_scc_mgr_inst:avl_readdata -> mm_interconnect_1:sequencer_scc_mgr_inst_avl_readdata
wire mm_interconnect_1_sequencer_scc_mgr_inst_avl_waitrequest; // sequencer_scc_mgr_inst:avl_waitrequest -> mm_interconnect_1:sequencer_scc_mgr_inst_avl_waitrequest
wire [12:0] mm_interconnect_1_sequencer_scc_mgr_inst_avl_address; // mm_interconnect_1:sequencer_scc_mgr_inst_avl_address -> sequencer_scc_mgr_inst:avl_address
wire mm_interconnect_1_sequencer_scc_mgr_inst_avl_read; // mm_interconnect_1:sequencer_scc_mgr_inst_avl_read -> sequencer_scc_mgr_inst:avl_read
wire mm_interconnect_1_sequencer_scc_mgr_inst_avl_write; // mm_interconnect_1:sequencer_scc_mgr_inst_avl_write -> sequencer_scc_mgr_inst:avl_write
wire [31:0] mm_interconnect_1_sequencer_scc_mgr_inst_avl_writedata; // mm_interconnect_1:sequencer_scc_mgr_inst_avl_writedata -> sequencer_scc_mgr_inst:avl_writedata
wire [31:0] mm_interconnect_1_sequencer_reg_file_inst_avl_readdata; // sequencer_reg_file_inst:avl_readdata -> mm_interconnect_1:sequencer_reg_file_inst_avl_readdata
wire mm_interconnect_1_sequencer_reg_file_inst_avl_waitrequest; // sequencer_reg_file_inst:avl_waitrequest -> mm_interconnect_1:sequencer_reg_file_inst_avl_waitrequest
wire [3:0] mm_interconnect_1_sequencer_reg_file_inst_avl_address; // mm_interconnect_1:sequencer_reg_file_inst_avl_address -> sequencer_reg_file_inst:avl_address
wire mm_interconnect_1_sequencer_reg_file_inst_avl_read; // mm_interconnect_1:sequencer_reg_file_inst_avl_read -> sequencer_reg_file_inst:avl_read
wire [3:0] mm_interconnect_1_sequencer_reg_file_inst_avl_byteenable; // mm_interconnect_1:sequencer_reg_file_inst_avl_byteenable -> sequencer_reg_file_inst:avl_be
wire mm_interconnect_1_sequencer_reg_file_inst_avl_write; // mm_interconnect_1:sequencer_reg_file_inst_avl_write -> sequencer_reg_file_inst:avl_write
wire [31:0] mm_interconnect_1_sequencer_reg_file_inst_avl_writedata; // mm_interconnect_1:sequencer_reg_file_inst_avl_writedata -> sequencer_reg_file_inst:avl_writedata
wire [31:0] cpu_inst_d_irq_irq; // irq_mapper:sender_irq -> cpu_inst:d_irq
altera_mem_if_sequencer_rst #(
.DEPTH (10),
.CLKEN_LAGS_RESET (0)
) sequencer_rst (
.clk (avl_clk), // clk.clk
.rst (avl_reset_n), // rst.reset
.reset_out (sequencer_rst_reset_out_reset), // reset_out.reset
.clken_out (sequencer_rst_clken_out_clken) // clken_out.clken
);
altera_mem_if_sequencer_cpu_cv_synth_cpu_inst #(
.DEVICE_FAMILY ("CYCLONEV")
) cpu_inst (
.clk (avl_clk), // clk.clk
.reset_n (~sequencer_rst_reset_out_reset), // reset_n.reset_n
.d_address (cpu_inst_data_master_address), // data_master.address
.d_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.d_read (cpu_inst_data_master_read), // .read
.d_readdata (cpu_inst_data_master_readdata), // .readdata
.d_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.d_write (cpu_inst_data_master_write), // .write
.d_writedata (cpu_inst_data_master_writedata), // .writedata
.i_address (cpu_inst_instruction_master_address), // instruction_master.address
.i_read (cpu_inst_instruction_master_read), // .read
.i_readdata (cpu_inst_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_inst_d_irq_irq), // d_irq.irq
.no_ci_readra () // custom_instruction_master.readra
);
sequencer_scc_mgr #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (13),
.MEM_IF_READ_DQS_WIDTH (4),
.MEM_IF_WRITE_DQS_WIDTH (4),
.MEM_IF_DQ_WIDTH (32),
.MEM_IF_DM_WIDTH (4),
.MEM_NUMBER_OF_RANKS (1),
.DLL_DELAY_CHAIN_LENGTH (8),
.FAMILY ("CYCLONEV"),
.USE_2X_DLL ("false"),
.USE_SHADOW_REGS (0),
.USE_DQS_TRACKING (1),
.DUAL_WRITE_CLOCK (0),
.SCC_DATA_WIDTH (1),
.TRK_PARALLEL_SCC_LOAD (0)
) sequencer_scc_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~sequencer_rst_reset_out_reset), // avl_reset.reset_n
.avl_address (mm_interconnect_1_sequencer_scc_mgr_inst_avl_address), // avl.address
.avl_write (mm_interconnect_1_sequencer_scc_mgr_inst_avl_write), // .write
.avl_writedata (mm_interconnect_1_sequencer_scc_mgr_inst_avl_writedata), // .writedata
.avl_read (mm_interconnect_1_sequencer_scc_mgr_inst_avl_read), // .read
.avl_readdata (mm_interconnect_1_sequencer_scc_mgr_inst_avl_readdata), // .readdata
.avl_waitrequest (mm_interconnect_1_sequencer_scc_mgr_inst_avl_waitrequest), // .waitrequest
.scc_clk (scc_clk), // scc_clk.clk
.scc_reset_n (reset_n_scc_clk), // scc_reset.reset_n
.scc_data (scc_data), // scc.scc_data
.scc_dqs_ena (scc_dqs_ena), // .scc_dqs_ena
.scc_dqs_io_ena (scc_dqs_io_ena), // .scc_dqs_io_ena
.scc_dq_ena (scc_dq_ena), // .scc_dq_ena
.scc_dm_ena (scc_dm_ena), // .scc_dm_ena
.capture_strobe_tracking (capture_strobe_tracking), // .capture_strobe_tracking
.scc_upd (scc_upd), // .scc_upd
.afi_init_req (afi_init_req), // afi_init_cal_req.afi_init_req
.afi_cal_req (afi_cal_req), // .afi_cal_req
.scc_sr_dqsenable_delayctrl (), // (terminated)
.scc_sr_dqsdisablen_delayctrl (), // (terminated)
.scc_sr_multirank_delayctrl () // (terminated)
);
sequencer_reg_file #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (4),
.AVL_NUM_SYMBOLS (4),
.AVL_SYMBOL_WIDTH (8),
.REGISTER_RDATA (0),
.NUM_REGFILE_WORDS (16)
) sequencer_reg_file_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~sequencer_rst_reset_out_reset), // avl_reset.reset_n
.avl_address (mm_interconnect_1_sequencer_reg_file_inst_avl_address), // avl.address
.avl_write (mm_interconnect_1_sequencer_reg_file_inst_avl_write), // .write
.avl_writedata (mm_interconnect_1_sequencer_reg_file_inst_avl_writedata), // .writedata
.avl_read (mm_interconnect_1_sequencer_reg_file_inst_avl_read), // .read
.avl_readdata (mm_interconnect_1_sequencer_reg_file_inst_avl_readdata), // .readdata
.avl_waitrequest (mm_interconnect_1_sequencer_reg_file_inst_avl_waitrequest), // .waitrequest
.avl_be (mm_interconnect_1_sequencer_reg_file_inst_avl_byteenable) // .byteenable
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (16),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (0),
.PIPELINE_RESPONSE (0)
) trk_mm_bridge (
.clk (avl_clk), // clk.clk
.reset (sequencer_rst_reset_out_reset), // reset.reset
.s0_waitrequest (mm_interconnect_0_trk_mm_bridge_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_trk_mm_bridge_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_trk_mm_bridge_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_trk_mm_bridge_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_trk_mm_bridge_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_trk_mm_bridge_s0_address), // .address
.s0_write (mm_interconnect_0_trk_mm_bridge_s0_write), // .write
.s0_read (mm_interconnect_0_trk_mm_bridge_s0_read), // .read
.s0_byteenable (mm_interconnect_0_trk_mm_bridge_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_trk_mm_bridge_s0_debugaccess), // .debugaccess
.m0_waitrequest (trk_mm_bridge_m0_waitrequest), // m0.waitrequest
.m0_readdata (trk_mm_bridge_m0_readdata), // .readdata
.m0_readdatavalid (trk_mm_bridge_m0_readdatavalid), // .readdatavalid
.m0_burstcount (trk_mm_bridge_m0_burstcount), // .burstcount
.m0_writedata (trk_mm_bridge_m0_writedata), // .writedata
.m0_address (trk_mm_bridge_m0_address), // .address
.m0_write (trk_mm_bridge_m0_write), // .write
.m0_read (trk_mm_bridge_m0_read), // .read
.m0_byteenable (trk_mm_bridge_m0_byteenable), // .byteenable
.m0_debugaccess (trk_mm_bridge_m0_debugaccess), // .debugaccess
.s0_response (), // (terminated)
.m0_response (2'b00) // (terminated)
);
altera_mem_if_simple_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SLAVE_DATA_WIDTH (32),
.MASTER_DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.ADDRESS_WIDTH (16),
.MASTER_ADDRESS_WIDTH (10),
.SLAVE_ADDRESS_WIDTH (10),
.BURSTCOUNT_WIDTH (3),
.WORKAROUND_HARD_PHY_ISSUE (1)
) hphy_bridge (
.clk (avl_clk), // clk.clk
.reset_n (~sequencer_rst_reset_out_reset), // reset.reset_n
.s0_address (mm_interconnect_0_hphy_bridge_s0_address), // s0.address
.s0_read (mm_interconnect_0_hphy_bridge_s0_read), // .read
.s0_readdata (mm_interconnect_0_hphy_bridge_s0_readdata), // .readdata
.s0_write (mm_interconnect_0_hphy_bridge_s0_write), // .write
.s0_writedata (mm_interconnect_0_hphy_bridge_s0_writedata), // .writedata
.s0_waitrequest (mm_interconnect_0_hphy_bridge_s0_waitrequest), // .waitrequest
.m0_address (avl_address), // m0.address
.m0_read (avl_read), // .read
.m0_readdata (avl_readdata), // .readdata
.m0_write (avl_write), // .write
.m0_writedata (avl_writedata), // .writedata
.m0_waitrequest (avl_waitrequest), // .waitrequest
.s0_waitrequest_n (), // (terminated)
.s0_beginbursttransfer (1'b0), // (terminated)
.s0_burstcount (3'b000), // (terminated)
.s0_byteenable (4'b1111), // (terminated)
.s0_readdatavalid (), // (terminated)
.m0_beginbursttransfer (), // (terminated)
.m0_burstcount (), // (terminated)
.m0_byteenable (), // (terminated)
.m0_readdatavalid (1'b0) // (terminated)
);
sequencer_trk_mgr #(
.MEM_CHIP_SELECT_WIDTH (1),
.MEM_NUMBER_OF_RANKS (1),
.AVL_DATA_WIDTH (32),
.AVL_MTR_ADDR_WIDTH (20),
.AVL_ADDR_WIDTH (6),
.RATE ("Full"),
.MEM_READ_DQS_WIDTH (4),
.PHASE_WIDTH (3),
.READ_VALID_FIFO_SIZE (16),
.MUX_SEL_SEQUENCER_VAL (3),
.MUX_SEL_CONTROLLER_VAL (2),
.PHY_MGR_BASE (557056),
.RW_MGR_BASE (589824),
.SCC_MGR_BASE (98304),
.HARD_PHY (1),
.HARD_VFIFO (1),
.IO_DQS_EN_DELAY_OFFSET (0),
.TRK_PARALLEL_SCC_LOAD (0)
) sequencer_trk_mgr_inst (
.avl_clk (avl_clk), // avl_clk.clk
.avl_reset_n (~sequencer_rst_reset_out_reset), // avl_reset.reset_n
.trkm_address (sequencer_trk_mgr_inst_trkm_address), // trkm.address
.trkm_write (sequencer_trk_mgr_inst_trkm_write), // .write
.trkm_writedata (sequencer_trk_mgr_inst_trkm_writedata), // .writedata
.trkm_read (sequencer_trk_mgr_inst_trkm_read), // .read
.trkm_readdata (sequencer_trk_mgr_inst_trkm_readdata), // .readdata
.trkm_waitrequest (sequencer_trk_mgr_inst_trkm_waitrequest), // .waitrequest
.trks_address (mm_interconnect_0_sequencer_trk_mgr_inst_trks_address), // trks.address
.trks_write (mm_interconnect_0_sequencer_trk_mgr_inst_trks_write), // .write
.trks_writedata (mm_interconnect_0_sequencer_trk_mgr_inst_trks_writedata), // .writedata
.trks_read (mm_interconnect_0_sequencer_trk_mgr_inst_trks_read), // .read
.trks_readdata (mm_interconnect_0_sequencer_trk_mgr_inst_trks_readdata), // .readdata
.trks_waitrequest (mm_interconnect_0_sequencer_trk_mgr_inst_trks_waitrequest), // .waitrequest
.afi_seq_busy (afi_seq_busy), // afi.afi_seq_busy
.afi_ctl_long_idle (afi_ctl_long_idle), // .afi_ctl_long_idle
.afi_ctl_refresh_done (afi_ctl_refresh_done) // .afi_ctl_refresh_done
);
altera_mem_if_sequencer_mem_no_ifdef_params #(
.AVL_DATA_WIDTH (32),
.AVL_ADDR_WIDTH (12),
.AVL_NUM_SYMBOLS (4),
.AVL_SYMBOL_WIDTH (8),
.MEM_SIZE (14336),
.INIT_FILE ("lpddr2_cntrlr_s0_sequencer_mem.hex"),
.RAM_BLOCK_TYPE ("AUTO")
) sequencer_mem (
.clk1 (avl_clk), // clk1.clk
.reset1 (sequencer_rst_reset_out_reset), // reset1.reset
.clken1 (sequencer_rst_clken_out_clken), // clken1.clken
.s1_address (mm_interconnect_0_sequencer_mem_s1_address), // s1.address
.s1_write (mm_interconnect_0_sequencer_mem_s1_write), // .write
.s1_writedata (mm_interconnect_0_sequencer_mem_s1_writedata), // .writedata
.s1_readdata (mm_interconnect_0_sequencer_mem_s1_readdata), // .readdata
.s1_be (mm_interconnect_0_sequencer_mem_s1_byteenable), // .byteenable
.s1_chipselect (mm_interconnect_0_sequencer_mem_s1_chipselect) // .chipselect
);
lpddr2_cntrlr_s0_mm_interconnect_0 mm_interconnect_0 (
.avl_clk_out_clk_clk (avl_clk), // avl_clk_out_clk.clk
.cpu_inst_reset_n_reset_bridge_in_reset_reset (sequencer_rst_reset_out_reset), // cpu_inst_reset_n_reset_bridge_in_reset.reset
.sequencer_trk_mgr_inst_avl_reset_reset_bridge_in_reset_reset (sequencer_rst_reset_out_reset), // sequencer_trk_mgr_inst_avl_reset_reset_bridge_in_reset.reset
.cpu_inst_data_master_address (cpu_inst_data_master_address), // cpu_inst_data_master.address
.cpu_inst_data_master_waitrequest (cpu_inst_data_master_waitrequest), // .waitrequest
.cpu_inst_data_master_byteenable (cpu_inst_data_master_byteenable), // .byteenable
.cpu_inst_data_master_read (cpu_inst_data_master_read), // .read
.cpu_inst_data_master_readdata (cpu_inst_data_master_readdata), // .readdata
.cpu_inst_data_master_write (cpu_inst_data_master_write), // .write
.cpu_inst_data_master_writedata (cpu_inst_data_master_writedata), // .writedata
.cpu_inst_instruction_master_address (cpu_inst_instruction_master_address), // cpu_inst_instruction_master.address
.cpu_inst_instruction_master_waitrequest (cpu_inst_instruction_master_waitrequest), // .waitrequest
.cpu_inst_instruction_master_read (cpu_inst_instruction_master_read), // .read
.cpu_inst_instruction_master_readdata (cpu_inst_instruction_master_readdata), // .readdata
.sequencer_trk_mgr_inst_trkm_address (sequencer_trk_mgr_inst_trkm_address), // sequencer_trk_mgr_inst_trkm.address
.sequencer_trk_mgr_inst_trkm_waitrequest (sequencer_trk_mgr_inst_trkm_waitrequest), // .waitrequest
.sequencer_trk_mgr_inst_trkm_read (sequencer_trk_mgr_inst_trkm_read), // .read
.sequencer_trk_mgr_inst_trkm_readdata (sequencer_trk_mgr_inst_trkm_readdata), // .readdata
.sequencer_trk_mgr_inst_trkm_write (sequencer_trk_mgr_inst_trkm_write), // .write
.sequencer_trk_mgr_inst_trkm_writedata (sequencer_trk_mgr_inst_trkm_writedata), // .writedata
.hphy_bridge_s0_address (mm_interconnect_0_hphy_bridge_s0_address), // hphy_bridge_s0.address
.hphy_bridge_s0_write (mm_interconnect_0_hphy_bridge_s0_write), // .write
.hphy_bridge_s0_read (mm_interconnect_0_hphy_bridge_s0_read), // .read
.hphy_bridge_s0_readdata (mm_interconnect_0_hphy_bridge_s0_readdata), // .readdata
.hphy_bridge_s0_writedata (mm_interconnect_0_hphy_bridge_s0_writedata), // .writedata
.hphy_bridge_s0_waitrequest (mm_interconnect_0_hphy_bridge_s0_waitrequest), // .waitrequest
.sequencer_mem_s1_address (mm_interconnect_0_sequencer_mem_s1_address), // sequencer_mem_s1.address
.sequencer_mem_s1_write (mm_interconnect_0_sequencer_mem_s1_write), // .write
.sequencer_mem_s1_readdata (mm_interconnect_0_sequencer_mem_s1_readdata), // .readdata
.sequencer_mem_s1_writedata (mm_interconnect_0_sequencer_mem_s1_writedata), // .writedata
.sequencer_mem_s1_byteenable (mm_interconnect_0_sequencer_mem_s1_byteenable), // .byteenable
.sequencer_mem_s1_chipselect (mm_interconnect_0_sequencer_mem_s1_chipselect), // .chipselect
.sequencer_trk_mgr_inst_trks_address (mm_interconnect_0_sequencer_trk_mgr_inst_trks_address), // sequencer_trk_mgr_inst_trks.address
.sequencer_trk_mgr_inst_trks_write (mm_interconnect_0_sequencer_trk_mgr_inst_trks_write), // .write
.sequencer_trk_mgr_inst_trks_read (mm_interconnect_0_sequencer_trk_mgr_inst_trks_read), // .read
.sequencer_trk_mgr_inst_trks_readdata (mm_interconnect_0_sequencer_trk_mgr_inst_trks_readdata), // .readdata
.sequencer_trk_mgr_inst_trks_writedata (mm_interconnect_0_sequencer_trk_mgr_inst_trks_writedata), // .writedata
.sequencer_trk_mgr_inst_trks_waitrequest (mm_interconnect_0_sequencer_trk_mgr_inst_trks_waitrequest), // .waitrequest
.trk_mm_bridge_s0_address (mm_interconnect_0_trk_mm_bridge_s0_address), // trk_mm_bridge_s0.address
.trk_mm_bridge_s0_write (mm_interconnect_0_trk_mm_bridge_s0_write), // .write
.trk_mm_bridge_s0_read (mm_interconnect_0_trk_mm_bridge_s0_read), // .read
.trk_mm_bridge_s0_readdata (mm_interconnect_0_trk_mm_bridge_s0_readdata), // .readdata
.trk_mm_bridge_s0_writedata (mm_interconnect_0_trk_mm_bridge_s0_writedata), // .writedata
.trk_mm_bridge_s0_burstcount (mm_interconnect_0_trk_mm_bridge_s0_burstcount), // .burstcount
.trk_mm_bridge_s0_byteenable (mm_interconnect_0_trk_mm_bridge_s0_byteenable), // .byteenable
.trk_mm_bridge_s0_readdatavalid (mm_interconnect_0_trk_mm_bridge_s0_readdatavalid), // .readdatavalid
.trk_mm_bridge_s0_waitrequest (mm_interconnect_0_trk_mm_bridge_s0_waitrequest), // .waitrequest
.trk_mm_bridge_s0_debugaccess (mm_interconnect_0_trk_mm_bridge_s0_debugaccess) // .debugaccess
);
lpddr2_cntrlr_s0_mm_interconnect_1 mm_interconnect_1 (
.avl_clk_out_clk_clk (avl_clk), // avl_clk_out_clk.clk
.trk_mm_bridge_reset_reset_bridge_in_reset_reset (sequencer_rst_reset_out_reset), // trk_mm_bridge_reset_reset_bridge_in_reset.reset
.trk_mm_bridge_m0_address (trk_mm_bridge_m0_address), // trk_mm_bridge_m0.address
.trk_mm_bridge_m0_waitrequest (trk_mm_bridge_m0_waitrequest), // .waitrequest
.trk_mm_bridge_m0_burstcount (trk_mm_bridge_m0_burstcount), // .burstcount
.trk_mm_bridge_m0_byteenable (trk_mm_bridge_m0_byteenable), // .byteenable
.trk_mm_bridge_m0_read (trk_mm_bridge_m0_read), // .read
.trk_mm_bridge_m0_readdata (trk_mm_bridge_m0_readdata), // .readdata
.trk_mm_bridge_m0_readdatavalid (trk_mm_bridge_m0_readdatavalid), // .readdatavalid
.trk_mm_bridge_m0_write (trk_mm_bridge_m0_write), // .write
.trk_mm_bridge_m0_writedata (trk_mm_bridge_m0_writedata), // .writedata
.trk_mm_bridge_m0_debugaccess (trk_mm_bridge_m0_debugaccess), // .debugaccess
.sequencer_reg_file_inst_avl_address (mm_interconnect_1_sequencer_reg_file_inst_avl_address), // sequencer_reg_file_inst_avl.address
.sequencer_reg_file_inst_avl_write (mm_interconnect_1_sequencer_reg_file_inst_avl_write), // .write
.sequencer_reg_file_inst_avl_read (mm_interconnect_1_sequencer_reg_file_inst_avl_read), // .read
.sequencer_reg_file_inst_avl_readdata (mm_interconnect_1_sequencer_reg_file_inst_avl_readdata), // .readdata
.sequencer_reg_file_inst_avl_writedata (mm_interconnect_1_sequencer_reg_file_inst_avl_writedata), // .writedata
.sequencer_reg_file_inst_avl_byteenable (mm_interconnect_1_sequencer_reg_file_inst_avl_byteenable), // .byteenable
.sequencer_reg_file_inst_avl_waitrequest (mm_interconnect_1_sequencer_reg_file_inst_avl_waitrequest), // .waitrequest
.sequencer_scc_mgr_inst_avl_address (mm_interconnect_1_sequencer_scc_mgr_inst_avl_address), // sequencer_scc_mgr_inst_avl.address
.sequencer_scc_mgr_inst_avl_write (mm_interconnect_1_sequencer_scc_mgr_inst_avl_write), // .write
.sequencer_scc_mgr_inst_avl_read (mm_interconnect_1_sequencer_scc_mgr_inst_avl_read), // .read
.sequencer_scc_mgr_inst_avl_readdata (mm_interconnect_1_sequencer_scc_mgr_inst_avl_readdata), // .readdata
.sequencer_scc_mgr_inst_avl_writedata (mm_interconnect_1_sequencer_scc_mgr_inst_avl_writedata), // .writedata
.sequencer_scc_mgr_inst_avl_waitrequest (mm_interconnect_1_sequencer_scc_mgr_inst_avl_waitrequest) // .waitrequest
);
lpddr2_cntrlr_s0_irq_mapper irq_mapper (
.clk (avl_clk), // clk.clk
.reset (sequencer_rst_reset_out_reset), // clk_reset.reset
.sender_irq (cpu_inst_d_irq_irq) // sender.irq
);
endmodule
|
/* This file is part of JT51.
JT51 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-4-2017
*/
module jt51_mod(
input m1_enters,
input m2_enters,
input c1_enters,
input c2_enters,
input [2:0] alg_I,
output reg use_prevprev1,
output reg use_internal_x,
output reg use_internal_y,
output reg use_prev2,
output reg use_prev1
);
reg [7:0] alg_hot;
always @(*) begin
case( alg_I )
3'd0: alg_hot = 8'h1; // D0
3'd1: alg_hot = 8'h2; // D1
3'd2: alg_hot = 8'h4; // D2
3'd3: alg_hot = 8'h8; // D3
3'd4: alg_hot = 8'h10; // D4
3'd5: alg_hot = 8'h20; // D5
3'd6: alg_hot = 8'h40; // D6
3'd7: alg_hot = 8'h80; // D7
default: alg_hot = 8'hx;
endcase
end
always @(*) begin
use_prevprev1 = m1_enters | (m2_enters&alg_hot[5]);
use_prev2 = (m2_enters&(|alg_hot[2:0])) | (c2_enters&alg_hot[3]);
use_internal_x = c2_enters & alg_hot[2];
use_internal_y = c2_enters & (|{alg_hot[4:3],alg_hot[1:0]});
use_prev1 = m1_enters | (m2_enters&alg_hot[1]) |
(c1_enters&(|{alg_hot[6:3],alg_hot[0]}) )|
(c2_enters&(|{alg_hot[5],alg_hot[2]}));
end
endmodule
|
//----------------------------------------------------------------------------
// Module: simple_pic.v
// Description: Super Simple Priority Interrupt Controller
//
// This module controls the hardware interrupts. A table is set up in lower
// RAM that contains 4 bytes per vector and continues up to 0xFF. The first
// 8 slots are assigned here The program counter is loaded with the address 4
// times the INT. E.g. IRQ7 pointer is 4 * 0x0f = 0x3C.
//
// Set the interupt vectors in the lower 256 bytes of memory
// INT 0x00 - Reset - SYSTEM RESET;
// INT 0x04 - NMI - Non-maskable interrupt
// INT 0x08 - IRQ0 - SYSTEM TIMER
// INT 0x09 - IRQ1 - KEYBOARD DATA READY
// INT 0x0A - IRQ2 - LPT2/EGA,VGA/IRQ9
// INT 0x0B - IRQ3 - SERIAL COMMUNICATIONS (COM2)
// INT 0x0C - IRQ4 - SERIAL COMMUNICATIONS (COM1)
// INT 0x0D - IRQ5 - FIXED DISK/LPT2/reserved
// INT 0x0E - IRQ6 - DISKETTE CONTROLLER
// INT 0x0F - IRQ7 - PARALLEL PRINTER, (we are are going to steal this one)
//
//----------------------------------------------------------------------------
module simple_pic (
input clk,
input rst,
input [7:0] intv,
input inta,
output intr,
output reg [2:0] iid
);
reg inta_r;
reg [7:0] irr;
reg [7:0] int_r;
assign intr = irr[7] | irr[6] | irr[5] | irr[4] | irr[3] | irr[2] | irr[1] | irr[0];
always @(posedge clk) inta_r <= inta;
// the first 2 are handled differently, depends on ISR always being present
// always @(posedge clk) irr[0] <= rst ? 1'b0 : (intv[0] | irr[0] & !(iid == 3'b000 && inta_r && !inta));
always @(posedge clk) int_r[0] <= rst ? 1'b0 : intv[0]; // int0
always @(posedge clk) int_r[1] <= rst ? 1'b0 : intv[1]; // int1
always @(posedge clk) int_r[2] <= rst ? 1'b0 : intv[2]; // int2
always @(posedge clk) int_r[3] <= rst ? 1'b0 : intv[3]; // int3
always @(posedge clk) int_r[4] <= rst ? 1'b0 : intv[4]; // int4
always @(posedge clk) int_r[5] <= rst ? 1'b0 : intv[5]; // int5
always @(posedge clk) int_r[6] <= rst ? 1'b0 : intv[6]; // int6
always @(posedge clk) int_r[7] <= rst ? 1'b0 : intv[7]; // int7
always @(posedge clk) irr[0] <= rst ? 1'b0 : ((intv[0] && !int_r[0]) | irr[0] & !(iid == 3'd0 && inta_r && !inta));
always @(posedge clk) irr[1] <= rst ? 1'b0 : ((intv[1] && !int_r[1]) | irr[1] & !(iid == 3'd1 && inta_r && !inta));
always @(posedge clk) irr[2] <= rst ? 1'b0 : ((intv[2] && !int_r[2]) | irr[2] & !(iid == 3'd2 && inta_r && !inta));
always @(posedge clk) irr[3] <= rst ? 1'b0 : ((intv[3] && !int_r[3]) | irr[3] & !(iid == 3'd3 && inta_r && !inta));
always @(posedge clk) irr[4] <= rst ? 1'b0 : ((intv[4] && !int_r[4]) | irr[4] & !(iid == 3'd4 && inta_r && !inta));
always @(posedge clk) irr[5] <= rst ? 1'b0 : ((intv[5] && !int_r[5]) | irr[5] & !(iid == 3'd5 && inta_r && !inta));
always @(posedge clk) irr[6] <= rst ? 1'b0 : ((intv[6] && !int_r[6]) | irr[6] & !(iid == 3'd6 && inta_r && !inta));
always @(posedge clk) irr[7] <= rst ? 1'b0 : ((intv[7] && !int_r[7]) | irr[7] & !(iid == 3'd7 && inta_r && !inta));
always @(posedge clk) // Set the interrupt ID
iid <= rst ? 3'b0 : (inta ? iid :
(irr[0] ? 3'b000 :
(irr[1] ? 3'b001 :
(irr[2] ? 3'b010 :
(irr[3] ? 3'b011 :
(irr[4] ? 3'b100 :
(irr[5] ? 3'b101 :
(irr[6] ? 3'b110 :
(irr[7] ? 3'b111 :
3'b000 )))))))));
//----------------------------------------------------------------------------
endmodule
//----------------------------------------------------------------------------
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module system_processing_system7_0_0 (
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1 : 0] S_AXI_ACP_BRESP;
output [1 : 0] S_AXI_ACP_RRESP;
output [2 : 0] S_AXI_ACP_BID;
output [2 : 0] S_AXI_ACP_RID;
output [63 : 0] S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2 : 0] S_AXI_ACP_ARID;
input [2 : 0] S_AXI_ACP_ARPROT;
input [2 : 0] S_AXI_ACP_AWID;
input [2 : 0] S_AXI_ACP_AWPROT;
input [2 : 0] S_AXI_ACP_WID;
input [31 : 0] S_AXI_ACP_ARADDR;
input [31 : 0] S_AXI_ACP_AWADDR;
input [3 : 0] S_AXI_ACP_ARCACHE;
input [3 : 0] S_AXI_ACP_ARLEN;
input [3 : 0] S_AXI_ACP_ARQOS;
input [3 : 0] S_AXI_ACP_AWCACHE;
input [3 : 0] S_AXI_ACP_AWLEN;
input [3 : 0] S_AXI_ACP_AWQOS;
input [1 : 0] S_AXI_ACP_ARBURST;
input [1 : 0] S_AXI_ACP_ARLOCK;
input [2 : 0] S_AXI_ACP_ARSIZE;
input [1 : 0] S_AXI_ACP_AWBURST;
input [1 : 0] S_AXI_ACP_AWLOCK;
input [2 : 0] S_AXI_ACP_AWSIZE;
input [4 : 0] S_AXI_ACP_ARUSER;
input [4 : 0] S_AXI_ACP_AWUSER;
input [63 : 0] S_AXI_ACP_WDATA;
input [7 : 0] S_AXI_ACP_WSTRB;
input [1 : 0] IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(1),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(100),
.C_FCLK_CLK1_FREQ(50),
.C_FCLK_CLK2_FREQ(50),
.C_FCLK_CLK3_FREQ(50),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(S_AXI_ACP_ARREADY),
.S_AXI_ACP_AWREADY(S_AXI_ACP_AWREADY),
.S_AXI_ACP_BVALID(S_AXI_ACP_BVALID),
.S_AXI_ACP_RLAST(S_AXI_ACP_RLAST),
.S_AXI_ACP_RVALID(S_AXI_ACP_RVALID),
.S_AXI_ACP_WREADY(S_AXI_ACP_WREADY),
.S_AXI_ACP_BRESP(S_AXI_ACP_BRESP),
.S_AXI_ACP_RRESP(S_AXI_ACP_RRESP),
.S_AXI_ACP_BID(S_AXI_ACP_BID),
.S_AXI_ACP_RID(S_AXI_ACP_RID),
.S_AXI_ACP_RDATA(S_AXI_ACP_RDATA),
.S_AXI_ACP_ACLK(S_AXI_ACP_ACLK),
.S_AXI_ACP_ARVALID(S_AXI_ACP_ARVALID),
.S_AXI_ACP_AWVALID(S_AXI_ACP_AWVALID),
.S_AXI_ACP_BREADY(S_AXI_ACP_BREADY),
.S_AXI_ACP_RREADY(S_AXI_ACP_RREADY),
.S_AXI_ACP_WLAST(S_AXI_ACP_WLAST),
.S_AXI_ACP_WVALID(S_AXI_ACP_WVALID),
.S_AXI_ACP_ARID(S_AXI_ACP_ARID),
.S_AXI_ACP_ARPROT(S_AXI_ACP_ARPROT),
.S_AXI_ACP_AWID(S_AXI_ACP_AWID),
.S_AXI_ACP_AWPROT(S_AXI_ACP_AWPROT),
.S_AXI_ACP_WID(S_AXI_ACP_WID),
.S_AXI_ACP_ARADDR(S_AXI_ACP_ARADDR),
.S_AXI_ACP_AWADDR(S_AXI_ACP_AWADDR),
.S_AXI_ACP_ARCACHE(S_AXI_ACP_ARCACHE),
.S_AXI_ACP_ARLEN(S_AXI_ACP_ARLEN),
.S_AXI_ACP_ARQOS(S_AXI_ACP_ARQOS),
.S_AXI_ACP_AWCACHE(S_AXI_ACP_AWCACHE),
.S_AXI_ACP_AWLEN(S_AXI_ACP_AWLEN),
.S_AXI_ACP_AWQOS(S_AXI_ACP_AWQOS),
.S_AXI_ACP_ARBURST(S_AXI_ACP_ARBURST),
.S_AXI_ACP_ARLOCK(S_AXI_ACP_ARLOCK),
.S_AXI_ACP_ARSIZE(S_AXI_ACP_ARSIZE),
.S_AXI_ACP_AWBURST(S_AXI_ACP_AWBURST),
.S_AXI_ACP_AWLOCK(S_AXI_ACP_AWLOCK),
.S_AXI_ACP_AWSIZE(S_AXI_ACP_AWSIZE),
.S_AXI_ACP_ARUSER(S_AXI_ACP_ARUSER),
.S_AXI_ACP_AWUSER(S_AXI_ACP_AWUSER),
.S_AXI_ACP_WDATA(S_AXI_ACP_WDATA),
.S_AXI_ACP_WSTRB(S_AXI_ACP_WSTRB),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(IRQ_F2P),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MAJ3_BLACKBOX_V
`define SKY130_FD_SC_MS__MAJ3_BLACKBOX_V
/**
* maj3: 3-input majority vote.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__maj3 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MAJ3_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 26 16:00:34 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[7:0],probe20[0:0],probe21[2:0],probe22[2:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [7:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's interface to SPRs ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Decoding of SPR addresses and access to SPRs ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_sprs.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.11 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.9.4.1 2003/12/17 13:43:38 simons
// Exception prefix configuration changed.
//
// Revision 1.9 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.8 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
// Revision 1.7 2002/03/29 15:16:56 lampret
// Some of the warnings fixed.
//
// Revision 1.6 2002/03/11 01:26:57 lampret
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
//
// Revision 1.5 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.4 2002/01/23 07:52:36 lampret
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
//
// Revision 1.3 2002/01/19 09:27:49 lampret
// SR[TEE] should be zero after reset.
//
// Revision 1.2 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.11 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10 2001/11/12 01:45:41 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8 2001/10/14 13:12:10 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
// Revision 1.3 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:21 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_sprs(
// Clk & Rst
clk, rst,
// Internal CPU interface
flagforw, flag_we, flag, cyforw, cy_we, carry,
addrbase, addrofs, dat_i, alu_op, branch_op,
epcr, eear, esr, except_started,
to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr_we, to_sr, sr,
spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
// From/to other RISC units
spr_dat_pic, spr_dat_tt, spr_dat_pm,
spr_dat_dmmu, spr_dat_immu, spr_dat_du,
spr_addr, spr_dat_o, spr_cs, spr_we,
du_addr, du_dat_du, du_read,
du_write, du_dat_cpu
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O Ports
//
//
// Internal CPU interface
//
input clk; // Clock
input rst; // Reset
input flagforw; // From ALU
input flag_we; // From ALU
output flag; // SR[F]
input cyforw; // From ALU
input cy_we; // From ALU
output carry; // SR[CY]
input [width-1:0] addrbase; // SPR base address
input [15:0] addrofs; // SPR offset
input [width-1:0] dat_i; // SPR write data
input [`OR1200_ALUOP_WIDTH-1:0] alu_op; // ALU operation
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch operation
input [width-1:0] epcr; // EPCR0
input [width-1:0] eear; // EEAR0
input [`OR1200_SR_WIDTH-1:0] esr; // ESR0
input except_started; // Exception was started
output [width-1:0] to_wbmux; // For l.mfspr
output epcr_we; // EPCR0 write enable
output eear_we; // EEAR0 write enable
output esr_we; // ESR0 write enable
output pc_we; // PC write enable
output sr_we; // Write enable SR
output [`OR1200_SR_WIDTH-1:0] to_sr; // Data to SR
output [`OR1200_SR_WIDTH-1:0] sr; // SR
input [31:0] spr_dat_cfgr; // Data from CFGR
input [31:0] spr_dat_rf; // Data from RF
input [31:0] spr_dat_npc; // Data from NPC
input [31:0] spr_dat_ppc; // Data from PPC
input [31:0] spr_dat_mac; // Data from MAC
//
// To/from other RISC units
//
input [31:0] spr_dat_pic; // Data from PIC
input [31:0] spr_dat_tt; // Data from TT
input [31:0] spr_dat_pm; // Data from PM
input [31:0] spr_dat_dmmu; // Data from DMMU
input [31:0] spr_dat_immu; // Data from IMMU
input [31:0] spr_dat_du; // Data from DU
output [31:0] spr_addr; // SPR Address
output [31:0] spr_dat_o; // Data to unit
output [31:0] spr_cs; // Unit select
output spr_we; // SPR write enable
//
// To/from Debug Unit
//
input [width-1:0] du_addr; // Address
input [width-1:0] du_dat_du; // Data from DU to SPRS
input du_read; // Read qualifier
input du_write; // Write qualifier
output [width-1:0] du_dat_cpu; // Data from SPRS to DU
//
// Internal regs & wires
//
reg [`OR1200_SR_WIDTH-1:0] sr; // SR
reg write_spr; // Write SPR
reg read_spr; // Read SPR
reg [width-1:0] to_wbmux; // For l.mfspr
wire cfgr_sel; // Select for cfg regs
wire rf_sel; // Select for RF
wire npc_sel; // Select for NPC
wire ppc_sel; // Select for PPC
wire sr_sel; // Select for SR
wire epcr_sel; // Select for EPCR0
wire eear_sel; // Select for EEAR0
wire esr_sel; // Select for ESR0
wire [31:0] sys_data; // Read data from system SPRs
wire du_access; // Debug unit access
wire [`OR1200_ALUOP_WIDTH-1:0] sprs_op; // ALU operation
reg [31:0] unqualified_cs; // Unqualified chip selects
//
// Decide if it is debug unit access
//
assign du_access = du_read | du_write;
//
// Generate sprs opcode
//
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
//
// Generate SPR address from base address and offset
// OR from debug unit address
//
assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
//
// SPR is written by debug unit or by l.mtspr
//
assign spr_dat_o = du_write ? du_dat_du : dat_i;
//
// debug unit data input:
// - write into debug unit SPRs by debug unit itself
// - read of SPRS by debug unit
// - write into debug unit SPRs by l.mtspr
//
assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
//
// Write into SPRs when l.mtspr
//
assign spr_we = du_write | write_spr;
//
// Qualify chip selects
//
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
//
// Decoding of groups
//
always @(spr_addr)
case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
`OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
`OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
`OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
`OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
`OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
`OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
`OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
`OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
`OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
`OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
`OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
`OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
`OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
`OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
`OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
endcase
//
// SPRs System Group
//
//
// What to write into SR
//
assign to_sr[`OR1200_SR_FO:`OR1200_SR_OV] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_FO:`OR1200_SR_OV] :
(write_spr && sr_sel) ? {1'b1, spr_dat_o[`OR1200_SR_FO-1:`OR1200_SR_OV]}:
sr[`OR1200_SR_FO:`OR1200_SR_OV];
assign to_sr[`OR1200_SR_CY] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CY] :
cy_we ? cyforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CY] :
sr[`OR1200_SR_CY];
assign to_sr[`OR1200_SR_F] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_F] :
flag_we ? flagforw :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_F] :
sr[`OR1200_SR_F];
assign to_sr[`OR1200_SR_CE:`OR1200_SR_SM] =
(branch_op == `OR1200_BRANCHOP_RFE) ? esr[`OR1200_SR_CE:`OR1200_SR_SM] :
(write_spr && sr_sel) ? spr_dat_o[`OR1200_SR_CE:`OR1200_SR_SM]:
sr[`OR1200_SR_CE:`OR1200_SR_SM];
//
// Selects for system SPRs
//
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
//
// Write enables for system SPRs
//
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE) | flag_we | cy_we;
assign pc_we = (write_spr && (npc_sel | ppc_sel));
assign epcr_we = (write_spr && epcr_sel);
assign eear_we = (write_spr && eear_sel);
assign esr_we = (write_spr && esr_sel);
//
// Output from system SPRs
//
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
(spr_dat_rf & {32{read_spr & rf_sel}}) |
(spr_dat_npc & {32{read_spr & npc_sel}}) |
(spr_dat_ppc & {32{read_spr & ppc_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
(epcr & {32{read_spr & epcr_sel}}) |
(eear & {32{read_spr & eear_sel}}) |
({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
//
// Flag alias
//
assign flag = sr[`OR1200_SR_F];
//
// Carry alias
//
assign carry = sr[`OR1200_SR_CY];
//
// Supervision register
//
always @(posedge clk or posedge rst)
if (rst)
sr <= #1 {1'b1, `OR1200_SR_EPH_DEF, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
else if (except_started) begin
sr[`OR1200_SR_SM] <= #1 1'b1;
sr[`OR1200_SR_TEE] <= #1 1'b0;
sr[`OR1200_SR_IEE] <= #1 1'b0;
sr[`OR1200_SR_DME] <= #1 1'b0;
sr[`OR1200_SR_IME] <= #1 1'b0;
end
else if (sr_we)
sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
//
// MTSPR/MFSPR interface
//
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
case (sprs_op) // synopsys parallel_case
`OR1200_ALUOP_MTSR : begin
write_spr = 1'b1;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
`OR1200_ALUOP_MFSR : begin
casex (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
`OR1200_SPR_GROUP_TT:
to_wbmux = spr_dat_tt;
`OR1200_SPR_GROUP_PIC:
to_wbmux = spr_dat_pic;
`OR1200_SPR_GROUP_PM:
to_wbmux = spr_dat_pm;
`OR1200_SPR_GROUP_DMMU:
to_wbmux = spr_dat_dmmu;
`OR1200_SPR_GROUP_IMMU:
to_wbmux = spr_dat_immu;
`OR1200_SPR_GROUP_MAC:
to_wbmux = spr_dat_mac;
`OR1200_SPR_GROUP_DU:
to_wbmux = spr_dat_du;
`OR1200_SPR_GROUP_SYS:
to_wbmux = sys_data;
default:
to_wbmux = 32'b0;
endcase
write_spr = 1'b0;
read_spr = 1'b1;
end
default : begin
write_spr = 1'b0;
read_spr = 1'b0;
to_wbmux = 32'b0;
end
endcase
end
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DEBUG INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the debug interface: */
/* - CPU Control features. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 95 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2011-02-24 21:37:57 +0100 (Thu, 24 Feb 2011) $ */
/*===========================================================================*/
integer test_nr;
integer test_var;
integer dco_clk_counter;
always @ (negedge dco_clk)
dco_clk_counter <= dco_clk_counter+1;
integer dbg_clk_counter;
always @ (negedge dbg_clk)
dbg_clk_counter <= dbg_clk_counter+1;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DBG_EN
`ifdef DBG_I2C
`ifdef ASIC_CLOCKING
test_nr = 0;
#1 dbg_en = 0;
repeat(30) @(posedge dco_clk);
stimulus_done = 0;
// Make sure the CPU always starts executing when the
// debug interface is disabled during POR.
// Also make sure that the debug interface clock is stopped
// and that it is under reset
//--------------------------------------------------------
dbg_en = 0;
test_nr = 1;
@(negedge dco_clk) dbg_clk_counter = 0;
repeat(300) @(posedge dco_clk);
if (r14 === 16'h0000) tb_error("====== CPU is stopped event though the debug interface is disabled - test 1 =====");
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not stopped (test 1) =====");
if (dbg_rst == 1'b0) tb_error("====== DBG_RST signal is not active (test 3) =====");
test_var = r14;
// Make sure that enabling the debug interface after the POR
// don't stop the cpu
// Also make sure that the debug interface clock is running
// and that its reset is released
//--------------------------------------------------------
dbg_en = 1;
test_nr = 2;
@(negedge dco_clk) dbg_clk_counter = 0;
repeat(300) @(posedge dco_clk);
if (r14 === test_var[15:0]) tb_error("====== CPU is stopped when the debug interface is disabled after POR - test 4 =====");
if (dbg_clk_counter == 0) tb_error("====== DBG_CLK is not running (test 5) =====");
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 6) =====");
// Make sure that disabling the CPU with debug enabled
// will stop the CPU
// Also make sure that the debug interface clock is stopped
// and that it is NOT under reset
//--------------------------------------------------------
cpu_en = 0;
dbg_en = 1;
test_nr = 3;
#(6*50);
test_var = r14;
dbg_clk_counter = 0;
#(300*50);
if (r14 !== test_var[15:0]) tb_error("====== CPU is not stopped (test 7) =====");
if (dbg_clk_counter !== 0) tb_error("====== DBG_CLK is not running (test 8) =====");
if (dbg_rst !== 1'b0) tb_error("====== DBG_RST signal is active (test 9) =====");
cpu_en = 1;
repeat(6) @(negedge dco_clk);
// Create POR with debug enable and observe the
// behavior depending on the DBG_RST_BRK_EN define
//--------------------------------------------------------
dbg_en = 1;
test_nr = 4;
@(posedge dco_clk); // Generate POR
reset_n = 1'b0;
@(posedge dco_clk);
reset_n = 1'b1;
repeat(300) @(posedge dco_clk);
`ifdef DBG_RST_BRK_EN
if (r14 !== 16'h0000) tb_error("====== CPU is not stopped with the debug interface enabled and DBG_RST_BRK_EN=1 - test 3 =====");
`else
if (r14 === 16'h0000) tb_error("====== CPU is stopped with the debug interface enabled and DBG_RST_BRK_EN=0 - test 3 =====");
`endif
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 4 =====");
`endif
// Make sure that DBG_EN resets the debug interface
//--------------------------------------------------------
test_nr = 5;
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge dco_clk);
dbg_i2c_wr(CPU_CTL, 16'h0000);
dbg_i2c_wr(MEM_DATA, 16'haa55);
dbg_i2c_rd(CPU_CTL);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 5 =====");
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 6 =====");
test_var = r14; // Backup the current register value
@(posedge dco_clk); // Resets the debug interface
dbg_en = 1'b0;
repeat(2) @(posedge dco_clk);
dbg_en = 1'b1;
// Make sure that the register was not reseted
if (r14 < test_var) tb_error("====== CPU was reseted with DBG_EN - test 7 =====");
repeat(2) @(posedge dco_clk);
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Make sure that RESET_N resets the debug interface
//--------------------------------------------------------
test_nr = 6;
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
repeat(300) @(posedge dco_clk);
dbg_i2c_wr(CPU_CTL, 16'h0000);
dbg_i2c_wr(MEM_DATA, 16'haa55);
dbg_i2c_rd(CPU_CTL);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== CPU_CTL write access failed - test 10 =====");
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'haa55) tb_error("====== MEM_DATA write access failed - test 11 =====");
test_nr = 7;
@(posedge dco_clk); // Generates POR
reset_n = 1'b0;
repeat(2) @(posedge dco_clk);
reset_n = 1'b1;
// Make sure that the register was reseted
if (r14 !== 16'h0000) tb_error("====== CPU was not reseted with RESET_N - test 12 =====");
repeat(2) @(posedge dco_clk);
test_nr = 8;
// Check CPU_CTL reset value
dbg_i2c_rd(CPU_CTL);
`ifdef DBG_RST_BRK_EN
if (dbg_i2c_buf !== 16'h0030) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`else
if (dbg_i2c_buf !== 16'h0010) tb_error("====== CPU_CTL wrong reset value - test 8 =====");
`endif
dbg_i2c_rd(MEM_DATA);
if (dbg_i2c_buf !== 16'h0000) tb_error("====== MEM_DATA read access failed - test 9 =====");
// Let the CPU run
dbg_i2c_wr(CPU_CTL, 16'h0002);
test_nr = 9;
// Generate IRQ to terminate the test pattern
irq[`IRQ_NR-15] = 1'b1;
@(r13);
irq[`IRQ_NR-15] = 1'b0;
stimulus_done = 1;
`else
tb_skip_finish("| (this test is not supported in FPGA mode) |");
`endif
`else
tb_skip_finish("| (serial debug interface I2C not included) |");
`endif
`else
tb_skip_finish("| (serial debug interface not included) |");
`endif
end
|
// 8-N-1: 8bit no parity 1 stop bit
module uart(
input wire clk,
input wire rx,
output wire tx,
output wire [7:0] data_o,
output wire ack_o,
input wire [7:0] data_i,
input wire ack_i,
output wire pop_o);
// trig_baud16 is 1 at 9600 * 16Hz = 153600Hz
// 50MHz / 153600Hz = 325.52
wire trig_baud16;
wire trig_baud;
`define UART_DIV 11'd325
reg [10:0] bauddiv_counter_ff;
`ifdef SIMULATION
initial bauddiv_counter_ff = 11'd567; // random
`endif
always @(posedge clk) begin
if (bauddiv_counter_ff == 0) begin
bauddiv_counter_ff <= `UART_DIV;
end else begin
bauddiv_counter_ff <= bauddiv_counter_ff - 1;
end
end
assign trig_baud16 = (bauddiv_counter_ff == 4'd0);
reg [3:0] baudrate_counter_ff;
`ifdef SIMULATION
initial baudrate_counter_ff = 4'd14; // random
`endif
always @(posedge clk) begin
if (trig_baud16)
baudrate_counter_ff <= baudrate_counter_ff + 1;
end
reg trig_baud_ff;
always @(posedge clk) begin
trig_baud_ff <= trig_baud16 && (baudrate_counter_ff == 4'd0);
end
assign trig_baud = trig_baud_ff;
// rx
reg [1:0] rx_hist_ff;
`ifdef SIMULATION
initial rx_hist_ff = 4'd3; // random
`endif
always @(posedge clk)
rx_hist_ff <= {rx_hist_ff[0], rx};
wire rx_posedge = rx_hist_ff[1:0] == 2'b01;
wire rx_negedge = rx_hist_ff[1:0] == 2'b10;
reg [4:0] rx_counter_ff;
reg [4:0] rx_poscounter_ff;
`ifdef SIMULATION
initial rx_counter_ff = 4'd3; // random
initial rx_counter_ff = 4'd10; // random
`endif
wire trig_next_uartbit = (rx_counter_ff == 5'd17) || rx_negedge || rx_posedge;
always @(posedge clk) begin
if (trig_next_uartbit) begin
rx_counter_ff <= 0;
rx_poscounter_ff <= 0;
end else begin
if (trig_baud16) begin
rx_counter_ff <= rx_counter_ff + 1;
if (rx_hist_ff[0] == 1'b1)
rx_poscounter_ff <= rx_poscounter_ff + 1;
end
end
end
wire currbit = rx_poscounter_ff > 8;
reg [7:0] rxbuf_ff;
always @(posedge clk) begin
if (trig_next_uartbit)
rxbuf_ff <= {currbit, rxbuf_ff[7:1]};
end
assign data_o = rxbuf_ff;
reg [3:0] rx_frame_counter_ff;
`ifdef SIMULATION
initial rx_frame_counter_ff = 4'd12; // random
`endif
always @(posedge clk) begin
if (trig_next_uartbit) begin
if (rx_frame_counter_ff > 4'd8) begin
if (rx_negedge) begin
rx_frame_counter_ff <= 0;
end
end else begin
rx_frame_counter_ff <= rx_frame_counter_ff + 1;
end
end
end
reg rx_pop_ff;
always @(posedge clk) begin
rx_pop_ff <= trig_next_uartbit && rx_frame_counter_ff == 4'd8;
end
assign ack_o = rx_pop_ff;
// tx
reg [3:0] tx_frame_counter_ff;
`ifdef SIMULATION
initial tx_frame_counter_ff = 4'd13; // random
`endif
always @(posedge clk) begin
if (ack_i) begin
tx_frame_counter_ff <= 0;
end else if (trig_baud) begin
tx_frame_counter_ff <= tx_frame_counter_ff + 1;
end
end
assign pop_o = tx_frame_counter_ff > 4'd9;
reg [10:0] txbuf_ff;
always @(posedge clk) begin
if (ack_i) begin
// stop start, preserve H until next trig_baud
txbuf_ff <= {1'b1, data_i, 1'b0, 1'b1};
end else if (trig_baud) begin
txbuf_ff <= {1'b1, txbuf_ff[9:1]};
end
end
assign tx = txbuf_ff[0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nor4bb (
Y ,
A ,
B ,
C_N,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
input D_N;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, nor0_out, C_N, D_N);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4BB_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKMUX2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__CLKMUX2_BEHAVIORAL_V
/**
* clkmux2: Clock mux.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hdll__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_hdll__clkmux2 (
X ,
A0,
A1,
S
);
// Module ports
output X ;
input A0;
input A1;
input S ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire mux_2to10_out_X;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1 mux_2to10 (mux_2to10_out_X, A0, A1, S );
buf buf0 (X , mux_2to10_out_X);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKMUX2_BEHAVIORAL_V |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2018.2
// Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="pointer_basic,hls_ip_2018_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=2.552000,HLS_SYN_LAT=0,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=33,HLS_SYN_LUT=39,HLS_VERSION=2018_2}" *)
module pointer_basic (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_idle,
ap_ready,
d_i,
d_o,
d_o_ap_vld
);
parameter ap_ST_fsm_state1 = 1'd1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
output ap_idle;
output ap_ready;
input [31:0] d_i;
output [31:0] d_o;
output d_o_ap_vld;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg d_o_ap_vld;
(* fsm_encoding = "none" *) reg [0:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg [31:0] acc;
wire [31:0] acc_assign_fu_31_p2;
reg [0:0] ap_NS_fsm;
// power-on initialization
initial begin
#0 ap_CS_fsm = 1'd1;
#0 acc = 32'd0;
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
acc <= acc_assign_fu_31_p2;
end
end
always @ (*) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((ap_start == 1'b1) & (1'b1 == ap_CS_fsm_state1))) begin
d_o_ap_vld = 1'b1;
end else begin
d_o_ap_vld = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
ap_NS_fsm = ap_ST_fsm_state1;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign acc_assign_fu_31_p2 = (acc + d_i);
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign d_o = (acc + d_i);
endmodule //pointer_basic
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 09/26/2015 09:30:33 PM
// Design Name:
// Module Name: seven_segment_display_x_4
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments: Note that the segments are a_to_g with a in position 0, b in position 1, etc.
// The reverse assignments are commented out to the right.
// To turn off decimal point set the corresponding bit low.
//
//////////////////////////////////////////////////////////////////////////////////
module seven_segment_display_x_4(
input [15:0] bcd_in,
input [3:0] decimal_points,
input clk,
output reg [6:0] a_to_g,
output reg decimal_point,
output reg [3:0] anode
);
wire [1:0] counter;
reg [3:0] digit;
reg [19:0] clkdiv;
assign counter = clkdiv[19:18]; //count every 2.6 ms (with 100 MHz clock)
//4 to 1 MUX
always @(posedge clk)
case(counter)
0: {digit, decimal_point, anode} = {bcd_in[3:0], ~decimal_points[0], 4'b1110};
1: {digit, decimal_point, anode} = {bcd_in[7:4], ~decimal_points[1], 4'b1101};
2: {digit, decimal_point, anode} = {bcd_in[11:8], ~decimal_points[2], 4'b1011};
3: {digit, decimal_point, anode} = {bcd_in[15:12], ~decimal_points[3],4'b0111};
endcase
//7-segment decoder
always @(posedge clk)
case(digit)
0: a_to_g = 8'b1000000; // 8'b0000001;
1: a_to_g = 8'b1111001; // 8'b1001111;
2: a_to_g = 8'b0100100; // 8'b0010010;
3: a_to_g = 8'b0110000; // 8'b0000110;
4: a_to_g = 8'b0011001; // 8'b1001100;
5: a_to_g = 8'b0010010; // 8'b0100100;
6: a_to_g = 8'b0000010; // 8'b0100000;
7: a_to_g = 8'b1111000; // 8'b0001111;
8: a_to_g = 8'b0000000; // 8'b0000000;
9: a_to_g = 8'b0010000; // 8'b0000100;
default: a_to_g = 8'b11111111; //default to blank
endcase
//clock divider
always @ (posedge clk)
begin
clkdiv <= clkdiv + 20'b1;
end
endmodule
|
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