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// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 14
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zqynq_lab_1_design_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *)
input wire [0 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *)
output wire [0 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI AWLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI AWLEN [7:0] [31:24]" *)
output wire [31 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWSIZE [2:0] [11:9]" *)
output wire [11 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI AWBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI AWBURST [1:0] [7:6]" *)
output wire [7 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWLOCK [0:0] [3:3]" *)
output wire [3 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWCACHE [3:0] [15:12]" *)
output wire [15 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWREGION [3:0] [15:12]" *)
output wire [15 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI AWQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI AWQOS [3:0] [15:12]" *)
output wire [15 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96]" *)
output wire [127 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12]" *)
output wire [15 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WLAST [0:0] [3:3]" *)
output wire [3 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96]" *)
output wire [127 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8], xilinx.com:interface:aximm:1.0 M02_AXI ARLEN [7:0] [23:16], xilinx.com:interface:aximm:1.0 M03_AXI ARLEN [7:0] [31:24]" *)
output wire [31 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARSIZE [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARSIZE [2:0] [11:9]" *)
output wire [11 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI ARBURST [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI ARBURST [1:0] [7:6]" *)
output wire [7 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARLOCK [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARLOCK [0:0] [3:3]" *)
output wire [3 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARCACHE [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARCACHE [3:0] [15:12]" *)
output wire [15 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9]" *)
output wire [11 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARREGION [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARREGION [3:0] [15:12]" *)
output wire [15 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI ARQOS [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI ARQOS [3:0] [15:12]" *)
output wire [15 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3]" *)
output wire [3 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3]" *)
input wire [3 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96]" *)
input wire [127 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6]" *)
input wire [7 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RLAST [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RLAST [0:0] [3:3]" *)
input wire [3 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3]" *)
input wire [3 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3]" *)
output wire [3 : 0] m_axi_rready;
axi_crossbar_v2_1_14_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(4),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(256'H0000000040000000000000004280000000000000412100000000000041200000),
.C_M_AXI_ADDR_WIDTH(128'H00000010000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H0000000c),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(128'H00000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(128'H00000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(128'H00000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(128'H00000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(12'H000),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(48'H000000000000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(4'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(48'H000000000000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(4'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:27:23 11/11/2015
// Design Name:
// Module Name: PongWithSound
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module PongWithSound(
input Clock, Reset, rota, rotb, partyMode, growSquares, shiftX, shiftY,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output hsync, vsync,
output Speaker
);
wire [9:0] xpos;
wire [9:0] ypos;
parameter [9:0] NumberofPixels=10'd640, NumberofLines=10'd480;
parameter [9:0] SystemClockFreq=10'd100, CRTClockFreq=10'd25; //MHz
CRTcontroller2015fall VGAdisplay(NumberofPixels, NumberofLines, SystemClockFreq, CRTClockFreq, hsync, vsync, xpos, ypos, Reset, Clock);
GameWithSound game_inst(Clock, Reset, xpos, ypos, rota, rotb, partyMode, growSquares, shiftX, shiftY, red, green, blue, Speaker);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2BB2A_TB_V
`define SKY130_FD_SC_MS__O2BB2A_TB_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2bb2a.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_ms__o2bb2a dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2BB2A_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_PP_SYMBOL_V
/**
* lpflow_lsbuf_lh_hl_isowell_tap: Level-shift buffer, low-to-high,
* isolated well on input buffer,
* vpb/vnb taps, double-row-height
* cell.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VPWRIN,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_HL_ISOWELL_TAP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4BB_2_V
`define SKY130_FD_SC_MS__NAND4BB_2_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog wrapper for nand4bb with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_2 (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__nand4bb_2 (
Y ,
A_N,
B_N,
C ,
D
);
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__nand4bb base (
.Y(Y),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4BB_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_1_V
`define SKY130_FD_SC_LP__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_1_V
|
`timescale 1ns / 1ps
`default_nettype none
module csr_spi_t;
// ins
reg clk;
reg rst;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg sck;
parameter TCLK_SCK = 80;
reg mosi;
reg ss;
parameter NUM_CH = 8;
parameter NUM_SPDIF_IN = 3;
parameter NUM_RATE = 5;
wire [(NUM_RATE*NUM_SPDIF_IN-1):0] rate_i = {5'b00001, 5'b00100, 5'b10000};
wire [(192*NUM_SPDIF_IN-1):0] udata_i = {NUM_SPDIF_IN{192'h0102030405060708090a0b0c0d0e0f1011121314151617}};
wire [(192*NUM_SPDIF_IN-1):0] cdata_i = {NUM_SPDIF_IN{192'h0102030405060708090a0b0c0d0e0f1011121314151617}};
wire [27:0] csr_dram_addr;
wire [31:0] csr_dram_data;
wire csr_dram_we;
wire csr_dram_pop;
wire [31:0] dram_csr_data;
wire dram_csr_ack;
wire dram_csr_busy;
wire [31:0] mig_rd_data = 32'h12345678;
reg [6:0] mig_rd_count;
simple_ddr3 dram(
.clk(clk),
.rst(rst),
.addr_i(csr_dram_addr),
.data_i(csr_dram_data),
.we_i(csr_dram_we),
.pop_i(csr_dram_pop),
.data_o(dram_csr_data),
.ack_o(dram_csr_ack),
.busy_o(dram_csr_busy),
.mig_cmd_empty(1'b1),
.mig_cmd_full(1'b0),
.mig_wr_full(1'b1),
.mig_wr_empty(1'b0),
// .mig_wr_count,
// .mig_wr_underrun,
// .mig_wr_error,
.mig_rd_data(mig_rd_data),
// .mig_rd_full,
// .mig_rd_empty,
.mig_rd_count(mig_rd_count)
// .mig_rd_overflow,
// .mig_rd_error,
);
always @(posedge clk) begin
if (dram.mig_cmd_en == 1'b1 && dram.mig_cmd_instr[0] == 1'b1) begin
#(TCLK*5)
mig_rd_count = 'd1;
#(TCLK)
mig_rd_count = 'd0;
end
end
csr_spi uut(
.clk(clk), .rst(rst),
.sck(sck),
.mosi(mosi),
.ss(ss),
.rate_i(rate_i), .udata_i(udata_i), .cdata_i(cdata_i),
.dram0_addr_o(csr_dram_addr),
.dram0_data_o(csr_dram_data),
.dram0_we_o(csr_dram_we),
.dram0_pop_o(csr_dram_pop),
.dram0_data_i(dram_csr_data),
.dram0_ack_i(dram_csr_ack),
.dram0_busy_i(dram_csr_busy));
task spi_cycle;
input [7:0] data;
begin
#(TCLK_SCK/2);
ss = 0;
#(TCLK_SCK/2);
mosi = data[7];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[6];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[5];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[4];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[3];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[2];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[1];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
mosi = data[0];
sck = 0; #(TCLK_SCK/2);
sck = 1; #(TCLK_SCK/2);
#(TCLK_SCK/2);
ss = 1;
#(TCLK_SCK/2);
end
endtask
initial begin
$dumpfile("csr_spi_t.lxt");
$dumpvars(0, csr_spi_t);
sck = 0;
mosi = 0;
ss = 1;
rst = 0;
#(TCLK);
rst = 1;
#(TCLK);
rst = 0;
uut.csr.vol_ff = 64'h0123456789abcdef;
$display("vol_ff: %x", uut.csr.vol_ff);
#(TCLK*3);
spi_cycle(8'b1_01_0_0000);
spi_cycle(8'h03);
spi_cycle(8'h99);
spi_cycle(8'h00); // NOP padding
#(TCLK*3);
$display("after csr[12'h003] <= 8'h99");
$display("vol_ff: %x", uut.csr.vol_ff);
#(TCLK*3);
spi_cycle({4'b0_01_0, 4'h8}); // high 8
spi_cycle(8'h01); // low 01
spi_cycle(8'h00); // read result 12'h801
spi_cycle(8'h00); // NOP padding
#(TCLK*3);
$display("---");
#(TCLK*3);
spi_cycle({4'b0_10_0, 4'h9}); // high 9
spi_cycle(8'h00); // low 00
spi_cycle(8'h00); // read result 000
spi_cycle(8'h00); // read result 001
spi_cycle(8'h00); // read result 002
spi_cycle(8'h00); // read result 003
spi_cycle(8'h00); // NOP padding
#(TCLK*3);
$display("---");
#(TCLK*3);
spi_cycle(8'b1_10_0_0000);
spi_cycle(8'h04); // offset
spi_cycle(8'hef); // data[4]
spi_cycle(8'hbe); // data[5]
spi_cycle(8'had); // data[6]
spi_cycle(8'hde); // data[7]
#(TCLK*3);
$display("vol_ff: %x", uut.csr.vol_ff);
$display("--- PROM write begin");
#(TCLK*3);
spi_cycle(8'b1_01_1_0000); // high 0
spi_cycle(8'h00); // mid 00
spi_cycle(8'h00); // low 00
spi_cycle(8'hef); //
spi_cycle(8'hbe); //
spi_cycle(8'had); //
spi_cycle(8'hde); //
// write prom[20'h00000] => 32'hdeadbeef
#(TCLK*3);
$display("--- NKMD dbgin[3] => 8'hac");
#(TCLK*3);
spi_cycle({4'b1_01_0, 4'h6});
spi_cycle(8'h03); // offset
spi_cycle(8'hac);
#(TCLK*3);
$display("--- NKMD rst => 1");
#(TCLK*3);
spi_cycle({4'b1_01_0, 4'h4});
spi_cycle(8'h00); // offset
spi_cycle(8'h01);
#(TCLK*3);
$display("--- NKMD rst => 0");
#(TCLK*3);
spi_cycle({4'b1_01_0, 4'h4});
spi_cycle(8'h00); // offset
spi_cycle(8'h00);
#(TCLK*3);
$display("--- end");
#(TCLK*3);
spi_cycle(8'h0f); // special
spi_cycle({4'b1_10_0, 4'h0}); // we, burst 4, special 0 -> dram 1
spi_cycle(8'h12); // addr ms byte
spi_cycle(8'h34);
spi_cycle(8'h56);
spi_cycle(8'h78); // addr ls byte
spi_cycle(8'hef); // data ms byte
spi_cycle(8'hbe);
spi_cycle(8'had);
spi_cycle(8'hde); // data ls byte
spi_cycle(8'hef); // data ms byte
spi_cycle(8'hbe);
spi_cycle(8'had);
spi_cycle(8'hde); // data ls byte
spi_cycle(8'hef); // data ms byte
spi_cycle(8'hbe);
spi_cycle(8'had);
spi_cycle(8'hde); // data ls byte
spi_cycle(8'hef); // data ms byte
spi_cycle(8'hbe);
spi_cycle(8'had);
spi_cycle(8'hde); // data ls byte
spi_cycle(8'h00);
#(TCLK*3);
$display("--- end");
#(TCLK*3);
// write dram[0x12345678] => 32'hdeadbeef
$finish(2);
end
always @(posedge clk) begin
if(uut.spi_trx.ack_i)
$display("spi data tx: %x", uut.spi_trx.data_i);
if(uut.spi_trx.ack_pop_o)
$display("spi data rx: %x", uut.spi_trx.data_o);
end
always @(posedge uut.nkmd_rst_o)
$display("nkmd_rst_o posedge");
always @(negedge uut.nkmd_rst_o)
$display("nkmd_rst_o negedge");
always @(posedge uut.csr.clk)
if (uut.csr.ack_i)
$display("csr write addr: %x data: %x", uut.csr.addr_i, uut.csr.data_i);
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4BB_1_V
`define SKY130_FD_SC_HD__AND4BB_1_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog wrapper for and4bb with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4bb_1 (
X ,
A_N,
B_N,
C ,
D
);
output X ;
input A_N;
input B_N;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4bb base (
.X(X),
.A_N(A_N),
.B_N(B_N),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4BB_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A22OI_2_V
`define SKY130_FD_SC_HD__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A22OI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
`define SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V
/**
* clkinv: Clock tree inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkinv (
Y,
A
);
// Module ports
output Y;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINV_BEHAVIORAL_V |
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
// GOLD VERSION
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'hfffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'h00112233445566778899aabbccddeeff1;
//parameter max_128_bits = 128'h123415678901234567890123456789012;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
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// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ==============================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
/*
* ========================================================
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*=======================================================
*/
// ==============================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
// ==============================================================
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRA instruction
`aluwsra:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[5:7]) // byte 0
3'd0:
result[0:7]<=reg_A[0:7];
3'd1:
result[0:7]<={{1{reg_A[0]}},reg_A[0:6]};
3'd2:
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
3'd3:
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
3'd4:
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
3'd5:
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
3'd6:
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
3'd7:
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[13:15]) // byte 1
3'd0:
result[8:15]<=reg_A[8:15];
3'd1:
result[8:15]<={{1{reg_A[8]}},reg_A[8:14]};
3'd2:
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
3'd3:
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
3'd4:
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
3'd5:
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
3'd6:
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
3'd7:
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
endcase
case(reg_B[21:23]) // byte 2
3'd0:
result[16:23]<=reg_A[16:23];
3'd1:
result[16:23]<={{1{reg_A[16]}},reg_A[16:22]};
3'd2:
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
3'd3:
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
3'd4:
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
3'd5:
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
3'd6:
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
3'd7:
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[29:31]) // byte 3
3'd0:
result[24:31]<=reg_A[24:31];
3'd1:
result[24:31]<={{1{reg_A[24]}},reg_A[24:30]};
3'd2:
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
3'd3:
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
3'd4:
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
3'd5:
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
3'd6:
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
3'd7:
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
endcase
case(reg_B[37:39]) // byte 4
3'd0:
result[32:39]<=reg_A[32:39];
3'd1:
result[32:39]<={{1{reg_A[32]}},reg_A[32:38]};
3'd2:
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
3'd3:
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
3'd4:
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
3'd5:
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
3'd6:
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
3'd7:
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[45:47]) // byte 5
3'd0:
result[40:47]<=reg_A[40:47];
3'd1:
result[40:47]<={{1{reg_A[40]}},reg_A[40:46]};
3'd2:
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
3'd3:
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
3'd4:
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
3'd5:
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
3'd6:
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
3'd7:
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
endcase
case(reg_B[53:55]) // byte 6
3'd0:
result[48:55]<=reg_A[48:55];
3'd1:
result[48:55]<={{1{reg_A[48]}},reg_A[48:54]};
3'd2:
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
3'd3:
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
3'd4:
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
3'd5:
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
3'd6:
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
3'd7:
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[61:63]) // byte 7
3'd0:
result[56:63]<=reg_A[56:63];
3'd1:
result[56:63]<={{1{reg_A[56]}},reg_A[56:62]};
3'd2:
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
3'd3:
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
3'd4:
result[56:63]<={{4{reg_A[56]}},reg_A[56:59]};
3'd5:
result[56:63]<={{5{reg_A[56]}},reg_A[56:58]};
3'd6:
result[56:63]<={{6{reg_A[56]}},reg_A[56:57]};
3'd7:
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
endcase
case(reg_B[69:71]) // byte 8
3'd0:
result[64:71]<=reg_A[64:71];
3'd1:
result[64:71]<={{1{reg_A[64]}},reg_A[64:70]};
3'd2:
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
3'd3:
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
3'd4:
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
3'd5:
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
3'd6:
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
3'd7:
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[77:79]) // byte 9
3'd0:
result[72:79]<=reg_A[72:79];
3'd1:
result[72:79]<={{1{reg_A[72]}},reg_A[72:78]};
3'd2:
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
3'd3:
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
3'd4:
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
3'd5:
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
3'd6:
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
3'd7:
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
endcase
case(reg_B[85:87]) // byte 10
3'd0:
result[80:87]<=reg_A[80:87];
3'd1:
result[80:87]<={{1{reg_A[80]}},reg_A[80:86]};
3'd2:
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
3'd3:
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
3'd4:
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
3'd5:
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
3'd6:
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
3'd7:
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[93:95]) // byte 11
3'd0:
result[88:95]<=reg_A[88:95];
3'd1:
result[88:95]<={{1{reg_A[88]}},reg_A[88:94]};
3'd2:
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
3'd3:
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
3'd4:
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
3'd5:
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
3'd6:
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
3'd7:
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
endcase
case(reg_B[101:103]) // byte 12
3'd0:
result[96:103]<=reg_A[96:103];
3'd1:
result[96:103]<={{1{reg_A[96]}},reg_A[96:102]};
3'd2:
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
3'd3:
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
3'd4:
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
3'd5:
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
3'd6:
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
3'd7:
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[109:111]) // byte 13
3'd0:
result[104:111]<=reg_A[104:111];
3'd1:
result[104:111]<={{1{reg_A[104]}},reg_A[104:110]};
3'd2:
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
3'd3:
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
3'd4:
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
3'd5:
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
3'd6:
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
3'd7:
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
endcase
case(reg_B[117:119]) // byte 14
3'd0:
result[112:119]<=reg_A[112:119];
3'd1:
result[112:119]<={{1{reg_A[112]}},reg_A[112:118]};
3'd2:
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
3'd3:
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
3'd4:
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
3'd5:
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
3'd6:
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
3'd7:
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
endcase
case(reg_B[125:127]) // byte 15
3'd0:
result[120:127]<=reg_A[120:127];
3'd1:
result[120:127]<={{1{reg_A[120]}},reg_A[120:126]};
3'd2:
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
3'd3:
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
3'd4:
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
3'd5:
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
3'd6:
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
3'd7:
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
endcase
end
`w16:
begin
case(reg_B[12:15]) // word0
4'd0:
result[0:15]<=reg_A[0:15];
4'd1:
result[0:15]<={{1{reg_A[0]}},reg_A[0:14]};
4'd2:
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
4'd3:
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
4'd4:
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
4'd5:
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
4'd6:
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
4'd7:
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
4'd8:
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
4'd9:
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
4'd10:
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
4'd11:
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
4'd12:
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
4'd13:
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
4'd14:
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
4'd15:
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[28:31]) //word1
4'd0:
result[16:31]<=reg_A[16:31];
4'd1:
result[16:31]<={{1{reg_A[16]}},reg_A[16:30]};
4'd2:
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
4'd3:
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
4'd4:
result[16:31]<={{4{reg_A[16]}},reg_A[16:27]};
4'd5:
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
4'd6:
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
4'd7:
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
4'd8:
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
4'd9:
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
4'd10:
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
4'd11:
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
4'd12:
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
4'd13:
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
4'd14:
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
4'd15:
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[44:47]) // word2
4'd0:
result[32:47]<=reg_A[32:47];
4'd1:
result[32:47]<={{1{reg_A[32]}},reg_A[32:46]};
4'd2:
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
4'd3:
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
4'd4:
result[32:47]<={{4{reg_A[32]}},reg_A[32:43]};
4'd5:
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
4'd6:
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
4'd7:
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
4'd8:
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
4'd9:
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
4'd10:
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
4'd11:
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
4'd12:
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
4'd13:
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
4'd14:
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
4'd15:
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[60:63]) // word3
4'd0:
result[48:63]<=reg_A[48:63];
4'd1:
result[48:63]<={{1{reg_A[48]}},reg_A[48:62]};
4'd2:
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
4'd3:
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
4'd4:
result[48:63]<={{4{reg_A[48]}},reg_A[48:59]};
4'd5:
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
4'd6:
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
4'd7:
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
4'd8:
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
4'd9:
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
4'd10:
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
4'd11:
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
4'd12:
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
4'd13:
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
4'd14:
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
4'd15:
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[76:79]) // word4
4'd0:
result[64:79]<=reg_A[64:79];
4'd1:
result[64:79]<={{1{reg_A[64]}},reg_A[64:78]};
4'd2:
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
4'd3:
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
4'd4:
result[64:79]<={{4{reg_A[64]}},reg_A[64:75]};
4'd5:
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
4'd6:
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
4'd7:
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
4'd8:
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
4'd9:
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
4'd10:
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
4'd11:
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
4'd12:
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
4'd13:
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
4'd14:
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
4'd15:
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[92:95]) // word5
4'd0:
result[80:95]<=reg_A[80:95];
4'd1:
result[80:95]<={{1{reg_A[80]}},reg_A[80:94]};
4'd2:
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
4'd3:
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
4'd4:
result[80:95]<={{4{reg_A[80]}},reg_A[80:91]};
4'd5:
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
4'd6:
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
4'd7:
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
4'd8:
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
4'd9:
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
4'd10:
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
4'd11:
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
4'd12:
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
4'd13:
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
4'd14:
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
4'd15:
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[92:111]) // word6
4'd0:
result[96:111]<=reg_A[96:111];
4'd1:
result[96:111]<={{1{reg_A[96]}},reg_A[96:110]};
4'd2:
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
4'd3:
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
4'd4:
result[96:111]<={{4{reg_A[96]}},reg_A[96:107]};
4'd5:
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
4'd6:
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
4'd7:
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
4'd8:
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
4'd9:
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
4'd10:
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
4'd11:
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
4'd12:
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
4'd13:
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
4'd14:
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
4'd15:
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[92:127]) // word7
4'd0:
result[112:127]<=reg_A[112:127];
4'd1:
result[112:127]<={{1{reg_A[112]}},reg_A[112:126]};
4'd2:
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
4'd3:
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
4'd4:
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
4'd5:
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
4'd6:
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
4'd7:
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
4'd8:
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
4'd9:
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
4'd10:
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
4'd11:
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
4'd12:
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
4'd13:
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
4'd14:
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
4'd15:
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
endcase
end
`w32:
begin
case(reg_B[27:31])
5'd0:
result[0:31]<=reg_A[0:31];
5'd1:
result[0:31]<={{1{reg_A[0]}},reg_A[0:30]};
5'd2:
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
5'd3:
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
5'd4:
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
5'd5:
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
5'd6:
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
5'd7:
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
5'd8:
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
5'd9:
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
5'd10:
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
5'd11:
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
5'd12:
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
5'd13:
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
5'd14:
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
5'd15:
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
5'd16:
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
5'd17:
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
5'd18:
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
5'd19:
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
5'd20:
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
5'd21:
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
5'd22:
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
5'd23:
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
5'd24:
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
5'd25:
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
5'd26:
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
5'd27:
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
5'd28:
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
5'd29:
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
5'd30:
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
5'd31:
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[59:63])
5'd0:
result[32:63]<=reg_A[32:63];
5'd1:
result[32:63]<={{1{reg_A[32]}},reg_A[32:62]};
5'd2:
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
5'd3:
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
5'd4:
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
5'd5:
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
5'd6:
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
5'd7:
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
5'd8:
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
5'd9:
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
5'd10:
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
5'd11:
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
5'd12:
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
5'd13:
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
5'd14:
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
5'd15:
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
5'd16:
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
5'd17:
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
5'd18:
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
5'd19:
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
5'd20:
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
5'd21:
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
5'd22:
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
5'd23:
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
5'd24:
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
5'd25:
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
5'd26:
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
5'd27:
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
5'd28:
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
5'd29:
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
5'd30:
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
5'd31:
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[91:95])
5'd0:
result[64:95]<=reg_A[64:95];
5'd1:
result[64:95]<={{1{reg_A[64]}},reg_A[64:94]};
5'd2:
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
5'd3:
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
5'd4:
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
5'd5:
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
5'd6:
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
5'd7:
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
5'd8:
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
5'd9:
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
5'd10:
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
5'd11:
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
5'd12:
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
5'd13:
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
5'd14:
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
5'd15:
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
5'd16:
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
5'd17:
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
5'd18:
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
5'd19:
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
5'd20:
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
5'd21:
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
5'd22:
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
5'd23:
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
5'd24:
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
5'd25:
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
5'd26:
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
5'd27:
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
5'd28:
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
5'd29:
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
5'd30:
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
5'd31:
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[123:127])
5'd0:
result[96:127]<=reg_A[96:127];
5'd1:
result[96:127]<={{1{reg_A[96]}},reg_A[96:126]};
5'd2:
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
5'd3:
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
5'd4:
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
5'd5:
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
5'd6:
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
5'd7:
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
5'd8:
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
5'd9:
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
5'd10:
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
5'd11:
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
5'd12:
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
5'd13:
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
5'd14:
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
5'd15:
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
5'd16:
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
5'd17:
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
5'd18:
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
5'd19:
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
5'd20:
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
5'd21:
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
5'd22:
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
5'd23:
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
5'd24:
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
5'd25:
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
5'd26:
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
5'd27:
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
5'd28:
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
5'd29:
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
5'd30:
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
5'd31:
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
endcase
end
endcase
end
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4B_1_V
`define SKY130_FD_SC_LS__NAND4B_1_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog wrapper for nand4b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nand4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4b_1 (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nand4b_1 (
Y ,
A_N,
B ,
C ,
D
);
output Y ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nand4b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4B_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 3 18:00:16 2016
/////////////////////////////////////////////////////////////
module CORDIC_Arch3v1_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, ready_cordic,
data_output, beg_add_subt, add_subt_dataA, add_subt_dataB,
result_add_subt, op_add_subt, ready_add_subt, enab_cont_iter );
input [31:0] data_in;
input [1:0] shift_region_flag;
output [31:0] data_output;
output [31:0] add_subt_dataA;
output [31:0] add_subt_dataB;
input [31:0] result_add_subt;
input clk, rst, beg_fsm_cordic, ack_cordic, operation, ready_add_subt;
output ready_cordic, beg_add_subt, op_add_subt, enab_cont_iter;
wire d_ff1_operation_out, d_ff3_sign_out, n281, n640, n641, n642, n643,
n644, n645, n646, n647, n648, n649, n650, n651, n652, n653, n654,
n655, n656, n657, n658, n659, n660, n661, n662, n663, n664, n665,
n666, n667, n668, n669, n670, n671, n672, n673, n674, n675, n676,
n677, n678, n679, n680, n681, n682, n683, n684, n685, n686, n687,
n688, n689, n690, n691, n692, n693, n694, n695, n696, n697, n698,
n699, n700, n701, n702, n703, n704, n705, n706, n707, n708, n709,
n710, n711, n712, n713, n714, n715, n716, n717, n718, n719, n720,
n721, n722, n723, n724, n725, n726, n727, n728, n729, n730, n731,
n732, n733, n734, n735, n736, n737, n738, n739, n740, n741, n742,
n743, n744, n745, n746, n747, n748, n749, n750, n751, n752, n753,
n754, n755, n756, n757, n758, n759, n760, n761, n762, n763, n764,
n765, n766, n767, n768, n769, n770, n771, n772, n773, n774, n775,
n776, n777, n778, n779, n780, n781, n782, n783, n784, n785, n786,
n787, n788, n789, n790, n791, n792, n793, n794, n795, n796, n797,
n798, n799, n800, n801, n802, n803, n804, n805, n806, n807, n808,
n809, n810, n811, n812, n813, n814, n815, n816, n817, n818, n819,
n820, n821, n822, n823, n824, n825, n826, n827, n828, n829, n830,
n831, n832, n833, n834, n835, n836, n837, n838, n839, n840, n841,
n842, n843, n844, n845, n846, n847, n848, n849, n850, n851, n852,
n853, n854, n855, n856, n857, n858, n859, n860, n861, n862, n863,
n864, n865, n866, n867, n868, n869, n870, n871, n872, n873, n874,
n875, n876, n877, n878, n879, n880, n881, n882, n883, n884, n885,
n886, n887, n888, n889, n890, n891, n892, n893, n894, n895, n896,
n897, n898, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518;
wire [3:0] cont_iter_out;
wire [1:0] cont_var_out;
wire [1:0] d_ff1_shift_region_flag_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] d_ff_Yn;
wire [31:0] d_ff_Zn;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [7:0] inst_CORDIC_FSM_v3_state_next;
wire [7:0] inst_CORDIC_FSM_v3_state_reg;
DFFRX1TS reg_val_muxY_2stage_Q_reg_28_ ( .D(n716), .CK(n1513), .RN(n1455),
.Q(d_ff2_Y[28]), .QN(n1447) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(n984), .CK(n1487), .RN(n1482), .Q(
d_ff1_operation_out), .QN(n1446) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(n652), .CK(n1516), .RN(n1449),
.Q(d_ff2_X[28]), .QN(n1444) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_23_ ( .D(n721), .CK(n1511), .RN(n1455),
.Q(d_ff2_Y[23]), .QN(n1443) );
DFFRX1TS reg_shift_x_Q_reg_29_ ( .D(n643), .CK(n1507), .RN(n1463), .QN(n1442) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(n656), .CK(n1067), .RN(n1449),
.Q(d_ff2_X[24]), .QN(n1441) );
DFFRX2TS ITER_CONT_temp_reg_3_ ( .D(n986), .CK(n1486), .RN(n1484), .Q(
cont_iter_out[3]), .QN(n1439) );
DFFRX1TS reg_region_flag_Q_reg_0_ ( .D(n983), .CK(n1071), .RN(n1482), .Q(
d_ff1_shift_region_flag_out[0]), .QN(n1438) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(n812), .CK(n1504), .RN(n1466), .QN(n1437) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(n806), .CK(n1068), .RN(n1465), .QN(n1436) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(n810), .CK(n1068), .RN(n1466), .QN(n1435) );
DFFRX1TS reg_LUT_Q_reg_3_ ( .D(n818), .CK(n1499), .RN(n1466), .QN(n1434) );
DFFRX1TS reg_LUT_Q_reg_13_ ( .D(n809), .CK(n1506), .RN(n1465), .QN(n1433) );
DFFRX1TS reg_LUT_Q_reg_15_ ( .D(n808), .CK(n1503), .RN(n1465), .QN(n1432) );
DFFRX2TS VAR_CONT_temp_reg_0_ ( .D(n985), .CK(n1071), .RN(n1482), .Q(
cont_var_out[0]), .QN(n1431) );
DFFRX2TS ITER_CONT_temp_reg_1_ ( .D(n988), .CK(n1490), .RN(n1483), .Q(
cont_iter_out[1]), .QN(n1430) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(n982), .CK(n1490), .RN(n1482), .Q(
d_ff1_shift_region_flag_out[1]), .QN(n1429) );
DFFRX2TS ITER_CONT_temp_reg_2_ ( .D(n987), .CK(n1071), .RN(n1484), .Q(
cont_iter_out[2]), .QN(n1428) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(n853), .CK(n1493), .RN(n1473), .Q(
data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(n852), .CK(n1494), .RN(n1473), .Q(
data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(n851), .CK(n1494), .RN(n1473), .Q(
data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(n850), .CK(n1492), .RN(n1472), .Q(
data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(n849), .CK(n1498), .RN(n1472), .Q(
data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(n848), .CK(n1497), .RN(n1472), .Q(
data_output[5]) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(n847), .CK(n1065), .RN(n1472), .Q(
data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(n846), .CK(n1502), .RN(n1472), .Q(
data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(n845), .CK(n1502), .RN(n1471), .Q(
data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(n844), .CK(n1500), .RN(n1471), .Q(
data_output[9]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(n843), .CK(n1497), .RN(n1471), .Q(
data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(n842), .CK(n1065), .RN(n1471), .Q(
data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(n841), .CK(n1500), .RN(n1471), .Q(
data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(n840), .CK(n1498), .RN(n1470), .Q(
data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(n839), .CK(n1499), .RN(n1470), .Q(
data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(n838), .CK(n1497), .RN(n1470), .Q(
data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(n837), .CK(n1065), .RN(n1470), .Q(
data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(n836), .CK(n1498), .RN(n1470), .Q(
data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(n835), .CK(n1500), .RN(n1469), .Q(
data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(n834), .CK(n1499), .RN(n1469), .Q(
data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(n833), .CK(n1501), .RN(n1469), .Q(
data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(n832), .CK(n1500), .RN(n1469), .Q(
data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(n831), .CK(n1498), .RN(n1469), .Q(
data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(n830), .CK(n1499), .RN(n1468), .Q(
data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(n829), .CK(n1501), .RN(n1468), .Q(
data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(n828), .CK(n1497), .RN(n1468), .Q(
data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(n827), .CK(n1065), .RN(n1468), .Q(
data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(n826), .CK(n1501), .RN(n1468), .Q(
data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(n825), .CK(n1499), .RN(n1467), .Q(
data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(n824), .CK(n1500), .RN(n1467), .Q(
data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(n823), .CK(n1501), .RN(n1467), .Q(
data_output[30]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(n706), .CK(n1506), .RN(n1464), .Q(
d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(n704), .CK(n1509), .RN(n1454), .Q(
d_ff3_sh_y_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(n640), .CK(n1067), .RN(n1449), .Q(
d_ff3_sh_x_out[31]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(n642), .CK(n1504), .RN(n1463), .Q(
d_ff3_sh_x_out[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(n822), .CK(n1497), .RN(n1467), .Q(
data_output[31]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(n813), .CK(n1504), .RN(n1466), .Q(
d_ff3_LUT_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(n949), .CK(n1487), .RN(n1479), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(n712), .CK(n1507), .RN(n1464), .Q(
d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(n711), .CK(n1506), .RN(n1464), .Q(
d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(n710), .CK(n1508), .RN(n1464), .Q(
d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(n766), .CK(n1513), .RN(n1460), .Q(
d_ff3_sh_y_out[0]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(n764), .CK(n1512), .RN(n1459), .Q(
d_ff3_sh_y_out[1]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(n762), .CK(n1511), .RN(n1459), .Q(
d_ff3_sh_y_out[2]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(n758), .CK(n1512), .RN(n1459), .Q(
d_ff3_sh_y_out[4]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(n754), .CK(n1066), .RN(n1458), .Q(
d_ff3_sh_y_out[6]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(n750), .CK(n1514), .RN(n1458), .Q(
d_ff3_sh_y_out[8]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(n746), .CK(n1512), .RN(n1458), .Q(
d_ff3_sh_y_out[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(n948), .CK(n1491), .RN(n1479), .Q(d_ff_Zn[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(n947), .CK(n1486), .RN(n1479), .Q(d_ff_Zn[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(n946), .CK(n1491), .RN(n1479), .Q(d_ff_Zn[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(n945), .CK(n1490), .RN(n1479), .Q(d_ff_Zn[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(n944), .CK(n1071), .RN(n1479), .Q(d_ff_Zn[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(n943), .CK(n1489), .RN(n1479), .Q(d_ff_Zn[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(n942), .CK(n1489), .RN(n1479), .Q(d_ff_Zn[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(n941), .CK(n1486), .RN(n1479), .Q(d_ff_Zn[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(n940), .CK(n1486), .RN(n1479), .Q(d_ff_Zn[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(n939), .CK(n1489), .RN(n1478), .Q(
d_ff_Zn[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(n938), .CK(n1489), .RN(n1478), .Q(
d_ff_Zn[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(n937), .CK(n1490), .RN(n1478), .Q(
d_ff_Zn[12]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(n936), .CK(n1496), .RN(n1478), .Q(
d_ff_Zn[13]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(n935), .CK(n1492), .RN(n1478), .Q(
d_ff_Zn[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(n934), .CK(n1069), .RN(n1478), .Q(
d_ff_Zn[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(n933), .CK(n1069), .RN(n1478), .Q(
d_ff_Zn[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(n932), .CK(n1069), .RN(n1478), .Q(
d_ff_Zn[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(n931), .CK(n1069), .RN(n1478), .Q(
d_ff_Zn[18]) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(n930), .CK(n1494), .RN(n1478), .Q(
d_ff_Zn[19]) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(n929), .CK(n1494), .RN(n1477), .Q(
d_ff_Zn[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(n928), .CK(n1494), .RN(n1477), .Q(
d_ff_Zn[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(n927), .CK(n1494), .RN(n1477), .Q(
d_ff_Zn[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(n926), .CK(n1495), .RN(n1477), .Q(
d_ff_Zn[23]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(n925), .CK(n1495), .RN(n1477), .Q(
d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(n924), .CK(n1494), .RN(n1477), .Q(
d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(n923), .CK(n1494), .RN(n1477), .Q(
d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(n922), .CK(n1493), .RN(n1477), .Q(
d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(n921), .CK(n1496), .RN(n1477), .Q(
d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(n920), .CK(n1492), .RN(n1477), .Q(
d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(n919), .CK(n1494), .RN(n1476), .Q(
d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(n918), .CK(n1494), .RN(n1476), .Q(
d_ff_Zn[31]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(n981), .CK(n1489), .RN(n1482), .Q(d_ff1_Z[0])
);
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(n980), .CK(n1491), .RN(n1482), .Q(d_ff1_Z[1])
);
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(n979), .CK(n1491), .RN(n1481), .Q(d_ff1_Z[2])
);
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(n978), .CK(n1491), .RN(n1481), .Q(d_ff1_Z[3])
);
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(n977), .CK(n1489), .RN(n1481), .Q(d_ff1_Z[4])
);
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(n976), .CK(n1487), .RN(n1481), .Q(d_ff1_Z[5])
);
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(n975), .CK(n1487), .RN(n1481), .Q(d_ff1_Z[6])
);
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(n974), .CK(n1487), .RN(n1481), .Q(d_ff1_Z[7])
);
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(n973), .CK(n1071), .RN(n1481), .Q(d_ff1_Z[8])
);
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(n972), .CK(n1489), .RN(n1481), .Q(d_ff1_Z[9])
);
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(n971), .CK(n1490), .RN(n1481), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(n970), .CK(n1071), .RN(n1481), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(n968), .CK(n1486), .RN(n1484), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(n967), .CK(n1071), .RN(n1485), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(n965), .CK(n1489), .RN(n1483), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(n964), .CK(n1486), .RN(n1484), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(n963), .CK(n1490), .RN(n1485), .Q(d_ff1_Z[18]) );
DFFRX1TS reg_Z0_Q_reg_19_ ( .D(n962), .CK(n1071), .RN(n281), .Q(d_ff1_Z[19])
);
DFFRX1TS reg_Z0_Q_reg_20_ ( .D(n961), .CK(n1490), .RN(n281), .Q(d_ff1_Z[20])
);
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(n959), .CK(n1489), .RN(n1480), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(n958), .CK(n1489), .RN(n1480), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(n957), .CK(n1487), .RN(n1480), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(n956), .CK(n1490), .RN(n1480), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(n955), .CK(n1487), .RN(n1480), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(n954), .CK(n1491), .RN(n1480), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(n953), .CK(n1486), .RN(n1480), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(n952), .CK(n1490), .RN(n1480), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(n951), .CK(n1071), .RN(n1480), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(n950), .CK(n1071), .RN(n1480), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(n648), .CK(n1505), .RN(n1464), .Q(
d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(n647), .CK(n1505), .RN(n1464), .Q(
d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(n646), .CK(n1508), .RN(n1463), .Q(
d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(n702), .CK(n1503), .RN(n1454), .Q(
d_ff3_sh_x_out[0]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(n700), .CK(n1502), .RN(n1454), .Q(
d_ff3_sh_x_out[1]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(n698), .CK(clk), .RN(n1454), .Q(
d_ff3_sh_x_out[2]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(n690), .CK(n1488), .RN(n1453), .Q(
d_ff3_sh_x_out[6]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(n686), .CK(clk), .RN(n1452), .Q(
d_ff3_sh_x_out[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(n798), .CK(n1068), .RN(n1463),
.Q(d_ff2_Z[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(n796), .CK(n1508), .RN(n1463),
.Q(d_ff2_Z[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(n794), .CK(n1505), .RN(n1462),
.Q(d_ff2_Z[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(n792), .CK(n1507), .RN(n1462),
.Q(d_ff2_Z[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(n790), .CK(n1504), .RN(n1462),
.Q(d_ff2_Z[10]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(n708), .CK(n1507), .RN(n1464), .Q(
d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(n760), .CK(n1514), .RN(n1459), .Q(
d_ff3_sh_y_out[3]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(n756), .CK(n1513), .RN(n1459), .Q(
d_ff3_sh_y_out[5]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(n752), .CK(n1066), .RN(n1458), .Q(
d_ff3_sh_y_out[7]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(n748), .CK(n1511), .RN(n1458), .Q(
d_ff3_sh_y_out[9]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(n744), .CK(n1510), .RN(n1457), .Q(
d_ff3_sh_y_out[11]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(n742), .CK(n1513), .RN(n1457), .Q(
d_ff3_sh_y_out[12]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(n740), .CK(n1066), .RN(n1457), .Q(
d_ff3_sh_y_out[13]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(n738), .CK(n1512), .RN(n1457), .Q(
d_ff3_sh_y_out[14]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(n736), .CK(n1509), .RN(n1457), .Q(
d_ff3_sh_y_out[15]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(n734), .CK(n1509), .RN(n1456), .Q(
d_ff3_sh_y_out[16]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(n732), .CK(n1510), .RN(n1456), .Q(
d_ff3_sh_y_out[17]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(n730), .CK(n1513), .RN(n1456), .Q(
d_ff3_sh_y_out[18]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(n728), .CK(n1514), .RN(n1456), .Q(
d_ff3_sh_y_out[19]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(n726), .CK(n1511), .RN(n1456), .Q(
d_ff3_sh_y_out[20]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(n724), .CK(n1510), .RN(n1455), .Q(
d_ff3_sh_y_out[21]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(n722), .CK(n1512), .RN(n1455), .Q(
d_ff3_sh_y_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(n709), .CK(n1506), .RN(n1464), .Q(
d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(n644), .CK(n1503), .RN(n1463), .Q(
d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(n696), .CK(n1488), .RN(n1453), .Q(
d_ff3_sh_x_out[3]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(n692), .CK(clk), .RN(n1453), .Q(
d_ff3_sh_x_out[5]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(n688), .CK(clk), .RN(n1453), .Q(
d_ff3_sh_x_out[7]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(n684), .CK(n1516), .RN(n1452), .Q(
d_ff3_sh_x_out[9]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(n680), .CK(n1518), .RN(n1452), .Q(
d_ff3_sh_x_out[11]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(n678), .CK(n1517), .RN(n1452), .Q(
d_ff3_sh_x_out[12]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(n676), .CK(n1067), .RN(n1451), .Q(
d_ff3_sh_x_out[13]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(n674), .CK(n1067), .RN(n1451), .Q(
d_ff3_sh_x_out[14]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(n672), .CK(n1515), .RN(n1451), .Q(
d_ff3_sh_x_out[15]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(n670), .CK(n1516), .RN(n1451), .Q(
d_ff3_sh_x_out[16]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(n668), .CK(n1517), .RN(n1451), .Q(
d_ff3_sh_x_out[17]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(n666), .CK(n1067), .RN(n1450), .Q(
d_ff3_sh_x_out[18]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(n664), .CK(n1515), .RN(n1450), .Q(
d_ff3_sh_x_out[19]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(n662), .CK(n1517), .RN(n1450), .Q(
d_ff3_sh_x_out[20]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(n660), .CK(n1516), .RN(n1450), .Q(
d_ff3_sh_x_out[21]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(n658), .CK(n1517), .RN(n1450), .Q(
d_ff3_sh_x_out[22]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(n707), .CK(n1503), .RN(n1464), .Q(
d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(n645), .CK(n1504), .RN(n1463), .Q(
d_ff3_sh_x_out[27]) );
DFFRX1TS reg_LUT_Q_reg_0_ ( .D(n821), .CK(n1501), .RN(n1467), .Q(
d_ff3_LUT_out[0]) );
DFFRX1TS reg_LUT_Q_reg_2_ ( .D(n819), .CK(n1498), .RN(n1466), .Q(
d_ff3_LUT_out[2]) );
DFFRX1TS reg_LUT_Q_reg_1_ ( .D(n820), .CK(n1500), .RN(n1467), .Q(
d_ff3_LUT_out[1]) );
DFFRX1TS reg_LUT_Q_reg_4_ ( .D(n817), .CK(n1065), .RN(n1466), .Q(
d_ff3_LUT_out[4]) );
DFFRX1TS reg_LUT_Q_reg_10_ ( .D(n811), .CK(n1507), .RN(n1466), .Q(
d_ff3_LUT_out[10]) );
DFFRX1TS reg_LUT_Q_reg_24_ ( .D(n804), .CK(n1068), .RN(n1465), .Q(
d_ff3_LUT_out[24]) );
DFFRX1TS reg_LUT_Q_reg_26_ ( .D(n802), .CK(n1505), .RN(n1465), .Q(
d_ff3_LUT_out[26]) );
DFFRX1TS reg_shift_y_Q_reg_23_ ( .D(n713), .CK(n1508), .RN(n1465), .Q(
d_ff3_sh_y_out[23]) );
DFFRX1TS reg_LUT_Q_reg_25_ ( .D(n803), .CK(n1506), .RN(n1465), .Q(
d_ff3_LUT_out[25]) );
DFFRX1TS reg_shift_x_Q_reg_23_ ( .D(n649), .CK(n1508), .RN(n1464), .Q(
d_ff3_sh_x_out[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_23_ ( .D(n777), .CK(n1068), .RN(n1461),
.Q(d_ff2_Z[23]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_24_ ( .D(n776), .CK(n1508), .RN(n1461),
.Q(d_ff2_Z[24]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_27_ ( .D(n773), .CK(n1506), .RN(n1460),
.Q(d_ff2_Z[27]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_28_ ( .D(n772), .CK(n1510), .RN(n1460),
.Q(d_ff2_Z[28]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_29_ ( .D(n771), .CK(n1066), .RN(n1460),
.Q(d_ff2_Z[29]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_30_ ( .D(n770), .CK(n1514), .RN(n1460),
.Q(d_ff2_Z[30]) );
DFFRX1TS reg_LUT_Q_reg_19_ ( .D(n807), .CK(n1506), .RN(n1465), .Q(
d_ff3_LUT_out[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_30_ ( .D(n855), .CK(n1498), .RN(n1467), .Q(
d_ff_Xn[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_23_ ( .D(n894), .CK(n1495), .RN(n1474), .Q(
d_ff_Yn[23]) );
DFFRX1TS d_ff4_Yn_Q_reg_28_ ( .D(n889), .CK(n1069), .RN(n1473), .Q(
d_ff_Yn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_4_ ( .D(n881), .CK(n1492), .RN(n1472), .Q(d_ff_Xn[4]) );
DFFRX1TS d_ff4_Xn_Q_reg_8_ ( .D(n877), .CK(n1501), .RN(n1471), .Q(d_ff_Xn[8]) );
DFFRX1TS d_ff4_Xn_Q_reg_9_ ( .D(n876), .CK(n1502), .RN(n1471), .Q(d_ff_Xn[9]) );
DFFRX1TS d_ff4_Xn_Q_reg_11_ ( .D(n874), .CK(n1500), .RN(n1471), .Q(
d_ff_Xn[11]) );
DFFRX1TS d_ff4_Xn_Q_reg_15_ ( .D(n870), .CK(n1498), .RN(n1470), .Q(
d_ff_Xn[15]) );
DFFRX1TS d_ff4_Xn_Q_reg_18_ ( .D(n867), .CK(n1502), .RN(n1469), .Q(
d_ff_Xn[18]) );
DFFRX1TS d_ff4_Xn_Q_reg_21_ ( .D(n864), .CK(n1502), .RN(n1469), .Q(
d_ff_Xn[21]) );
DFFRX1TS d_ff4_Xn_Q_reg_22_ ( .D(n863), .CK(n1501), .RN(n1469), .Q(
d_ff_Xn[22]) );
DFFRX1TS d_ff4_Xn_Q_reg_23_ ( .D(n862), .CK(n1065), .RN(n1468), .Q(
d_ff_Xn[23]) );
DFFRX1TS d_ff4_Yn_Q_reg_1_ ( .D(n916), .CK(n1492), .RN(n1476), .Q(d_ff_Yn[1]) );
DFFRX1TS d_ff4_Yn_Q_reg_2_ ( .D(n915), .CK(n1493), .RN(n1476), .Q(d_ff_Yn[2]) );
DFFRX1TS d_ff4_Yn_Q_reg_3_ ( .D(n914), .CK(n1495), .RN(n1476), .Q(d_ff_Yn[3]) );
DFFRX1TS d_ff4_Yn_Q_reg_4_ ( .D(n913), .CK(n1493), .RN(n1476), .Q(d_ff_Yn[4]) );
DFFRX1TS d_ff4_Yn_Q_reg_5_ ( .D(n912), .CK(n1496), .RN(n1476), .Q(d_ff_Yn[5]) );
DFFRX1TS d_ff4_Yn_Q_reg_6_ ( .D(n911), .CK(n1496), .RN(n1476), .Q(d_ff_Yn[6]) );
DFFRX1TS d_ff4_Yn_Q_reg_7_ ( .D(n910), .CK(n1495), .RN(n1476), .Q(d_ff_Yn[7]) );
DFFRX1TS d_ff4_Yn_Q_reg_8_ ( .D(n909), .CK(n1493), .RN(n1475), .Q(d_ff_Yn[8]) );
DFFRX1TS d_ff4_Yn_Q_reg_9_ ( .D(n908), .CK(n1493), .RN(n1475), .Q(d_ff_Yn[9]) );
DFFRX1TS d_ff4_Yn_Q_reg_10_ ( .D(n907), .CK(n1069), .RN(n1475), .Q(
d_ff_Yn[10]) );
DFFRX1TS d_ff4_Yn_Q_reg_11_ ( .D(n906), .CK(n1495), .RN(n1475), .Q(
d_ff_Yn[11]) );
DFFRX1TS d_ff4_Yn_Q_reg_12_ ( .D(n905), .CK(n1492), .RN(n1475), .Q(
d_ff_Yn[12]) );
DFFRX1TS d_ff4_Yn_Q_reg_13_ ( .D(n904), .CK(n1495), .RN(n1475), .Q(
d_ff_Yn[13]) );
DFFRX1TS d_ff4_Yn_Q_reg_14_ ( .D(n903), .CK(n1496), .RN(n1475), .Q(
d_ff_Yn[14]) );
DFFRX1TS d_ff4_Yn_Q_reg_15_ ( .D(n902), .CK(n1069), .RN(n1475), .Q(
d_ff_Yn[15]) );
DFFRX1TS d_ff4_Yn_Q_reg_16_ ( .D(n901), .CK(n1069), .RN(n1475), .Q(
d_ff_Yn[16]) );
DFFRX1TS d_ff4_Yn_Q_reg_17_ ( .D(n900), .CK(n1069), .RN(n1475), .Q(
d_ff_Yn[17]) );
DFFRX1TS d_ff4_Yn_Q_reg_18_ ( .D(n899), .CK(n1496), .RN(n1474), .Q(
d_ff_Yn[18]) );
DFFRX1TS d_ff4_Yn_Q_reg_19_ ( .D(n898), .CK(n1496), .RN(n1474), .Q(
d_ff_Yn[19]) );
DFFRX1TS d_ff4_Yn_Q_reg_20_ ( .D(n897), .CK(n1492), .RN(n1474), .Q(
d_ff_Yn[20]) );
DFFRX1TS d_ff4_Yn_Q_reg_21_ ( .D(n896), .CK(n1492), .RN(n1474), .Q(
d_ff_Yn[21]) );
DFFRX1TS d_ff4_Yn_Q_reg_22_ ( .D(n895), .CK(n1069), .RN(n1474), .Q(
d_ff_Yn[22]) );
DFFRX1TS d_ff4_Yn_Q_reg_24_ ( .D(n893), .CK(n1493), .RN(n1474), .Q(
d_ff_Yn[24]) );
DFFRX1TS d_ff4_Yn_Q_reg_25_ ( .D(n892), .CK(n1493), .RN(n1474), .Q(
d_ff_Yn[25]) );
DFFRX1TS d_ff4_Yn_Q_reg_26_ ( .D(n891), .CK(n1496), .RN(n1474), .Q(
d_ff_Yn[26]) );
DFFRX1TS d_ff4_Yn_Q_reg_27_ ( .D(n890), .CK(n1493), .RN(n1474), .Q(
d_ff_Yn[27]) );
DFFRX1TS d_ff4_Yn_Q_reg_29_ ( .D(n888), .CK(n1492), .RN(n1473), .Q(
d_ff_Yn[29]) );
DFFRX1TS d_ff4_Yn_Q_reg_30_ ( .D(n887), .CK(n1495), .RN(n1473), .Q(
d_ff_Yn[30]) );
DFFRX1TS d_ff4_Xn_Q_reg_0_ ( .D(n885), .CK(n1495), .RN(n1473), .Q(d_ff_Xn[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_0_ ( .D(n703), .CK(n1517), .RN(n1454),
.Q(d_ff2_X[0]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_4_ ( .D(n695), .CK(n1067), .RN(n1453),
.Q(d_ff2_X[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_8_ ( .D(n687), .CK(n1517), .RN(n1452),
.Q(d_ff2_X[8]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_9_ ( .D(n685), .CK(n1067), .RN(n1452),
.Q(d_ff2_X[9]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_11_ ( .D(n681), .CK(n1517), .RN(n1452),
.Q(d_ff2_X[11]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_15_ ( .D(n673), .CK(n1517), .RN(n1451),
.Q(d_ff2_X[15]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_18_ ( .D(n667), .CK(n1067), .RN(n1450),
.Q(d_ff2_X[18]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_21_ ( .D(n661), .CK(n1515), .RN(n1450),
.Q(d_ff2_X[21]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_22_ ( .D(n659), .CK(n1518), .RN(n1450),
.Q(d_ff2_X[22]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_31_ ( .D(n641), .CK(n1067), .RN(n1449),
.Q(d_ff2_X[31]) );
DFFRX1TS d_ff4_Yn_Q_reg_0_ ( .D(n917), .CK(n1495), .RN(n1476), .Q(d_ff_Yn[0]) );
DFFRX1TS reg_sign_Q_reg_0_ ( .D(n768), .CK(n1510), .RN(n1460), .Q(
d_ff3_sign_out) );
DFFRX1TS reg_LUT_Q_reg_5_ ( .D(n816), .CK(n1068), .RN(n1466), .Q(
d_ff3_LUT_out[5]) );
DFFRX1TS reg_LUT_Q_reg_7_ ( .D(n814), .CK(n1505), .RN(n1466), .Q(
d_ff3_LUT_out[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_1_ ( .D(n701), .CK(n1515), .RN(n1454),
.Q(d_ff2_X[1]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_2_ ( .D(n699), .CK(n1518), .RN(n1454),
.Q(d_ff2_X[2]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_3_ ( .D(n697), .CK(n1518), .RN(n1453),
.Q(d_ff2_X[3]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_5_ ( .D(n693), .CK(n1515), .RN(n1453),
.Q(d_ff2_X[5]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_6_ ( .D(n691), .CK(n1516), .RN(n1453),
.Q(d_ff2_X[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_7_ ( .D(n689), .CK(n1518), .RN(n1453),
.Q(d_ff2_X[7]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_10_ ( .D(n683), .CK(n1067), .RN(n1452),
.Q(d_ff2_X[10]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_12_ ( .D(n679), .CK(n1515), .RN(n1452),
.Q(d_ff2_X[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_13_ ( .D(n677), .CK(n1516), .RN(n1451),
.Q(d_ff2_X[13]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_14_ ( .D(n675), .CK(n1518), .RN(n1451),
.Q(d_ff2_X[14]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_16_ ( .D(n671), .CK(n1515), .RN(n1451),
.Q(d_ff2_X[16]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_17_ ( .D(n669), .CK(n1516), .RN(n1451),
.Q(d_ff2_X[17]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_19_ ( .D(n665), .CK(n1518), .RN(n1450),
.Q(d_ff2_X[19]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_20_ ( .D(n663), .CK(n1517), .RN(n1450),
.Q(d_ff2_X[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_0_ ( .D(n767), .CK(n1511), .RN(n1460),
.Q(d_ff2_Y[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_1_ ( .D(n765), .CK(n1511), .RN(n1459),
.Q(d_ff2_Y[1]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_2_ ( .D(n763), .CK(n1066), .RN(n1459),
.Q(d_ff2_Y[2]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_3_ ( .D(n761), .CK(n1513), .RN(n1459),
.Q(d_ff2_Y[3]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_4_ ( .D(n759), .CK(n1510), .RN(n1459),
.Q(d_ff2_Y[4]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_5_ ( .D(n757), .CK(n1511), .RN(n1459),
.Q(d_ff2_Y[5]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_6_ ( .D(n755), .CK(n1509), .RN(n1458),
.Q(d_ff2_Y[6]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_7_ ( .D(n753), .CK(n1066), .RN(n1458),
.Q(d_ff2_Y[7]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_8_ ( .D(n751), .CK(n1514), .RN(n1458),
.Q(d_ff2_Y[8]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_9_ ( .D(n749), .CK(n1514), .RN(n1458),
.Q(d_ff2_Y[9]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_10_ ( .D(n747), .CK(n1514), .RN(n1458),
.Q(d_ff2_Y[10]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_11_ ( .D(n745), .CK(n1513), .RN(n1457),
.Q(d_ff2_Y[11]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_12_ ( .D(n743), .CK(n1066), .RN(n1457),
.Q(d_ff2_Y[12]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_13_ ( .D(n741), .CK(n1513), .RN(n1457),
.Q(d_ff2_Y[13]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_14_ ( .D(n739), .CK(n1066), .RN(n1457),
.Q(d_ff2_Y[14]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_15_ ( .D(n737), .CK(n1511), .RN(n1457),
.Q(d_ff2_Y[15]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_16_ ( .D(n735), .CK(n1509), .RN(n1456),
.Q(d_ff2_Y[16]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_17_ ( .D(n733), .CK(n1510), .RN(n1456),
.Q(d_ff2_Y[17]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_18_ ( .D(n731), .CK(n1511), .RN(n1456),
.Q(d_ff2_Y[18]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_19_ ( .D(n729), .CK(n1514), .RN(n1456),
.Q(d_ff2_Y[19]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_20_ ( .D(n727), .CK(n1514), .RN(n1456),
.Q(d_ff2_Y[20]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_21_ ( .D(n725), .CK(n1066), .RN(n1455),
.Q(d_ff2_Y[21]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_22_ ( .D(n723), .CK(n1511), .RN(n1455),
.Q(d_ff2_Y[22]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_31_ ( .D(n705), .CK(n1513), .RN(n1454),
.Q(d_ff2_Y[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_24_ ( .D(n861), .CK(n1500), .RN(n1468), .Q(
d_ff_Xn[24]) );
DFFRX1TS d_ff4_Xn_Q_reg_27_ ( .D(n858), .CK(n1501), .RN(n1468), .Q(
d_ff_Xn[27]) );
DFFRX1TS d_ff4_Xn_Q_reg_28_ ( .D(n857), .CK(n1499), .RN(n1467), .Q(
d_ff_Xn[28]) );
DFFRX1TS d_ff4_Xn_Q_reg_29_ ( .D(n856), .CK(n1500), .RN(n1467), .Q(
d_ff_Xn[29]) );
DFFRX1TS d_ff4_Xn_Q_reg_1_ ( .D(n884), .CK(n1493), .RN(n1473), .Q(d_ff_Xn[1]) );
DFFRX1TS d_ff4_Xn_Q_reg_2_ ( .D(n883), .CK(n1492), .RN(n1473), .Q(d_ff_Xn[2]) );
DFFRX1TS d_ff4_Xn_Q_reg_3_ ( .D(n882), .CK(n1496), .RN(n1472), .Q(d_ff_Xn[3]) );
DFFRX1TS d_ff4_Xn_Q_reg_5_ ( .D(n880), .CK(n1499), .RN(n1472), .Q(d_ff_Xn[5]) );
DFFRX1TS d_ff4_Xn_Q_reg_6_ ( .D(n879), .CK(n1499), .RN(n1472), .Q(d_ff_Xn[6]) );
DFFRX1TS d_ff4_Xn_Q_reg_7_ ( .D(n878), .CK(n1065), .RN(n1472), .Q(d_ff_Xn[7]) );
DFFRX1TS d_ff4_Xn_Q_reg_10_ ( .D(n875), .CK(n1498), .RN(n1471), .Q(
d_ff_Xn[10]) );
DFFRX1TS d_ff4_Xn_Q_reg_12_ ( .D(n873), .CK(n1500), .RN(n1471), .Q(
d_ff_Xn[12]) );
DFFRX1TS d_ff4_Xn_Q_reg_13_ ( .D(n872), .CK(n1498), .RN(n1470), .Q(
d_ff_Xn[13]) );
DFFRX1TS d_ff4_Xn_Q_reg_14_ ( .D(n871), .CK(n1065), .RN(n1470), .Q(
d_ff_Xn[14]) );
DFFRX1TS d_ff4_Xn_Q_reg_16_ ( .D(n869), .CK(n1501), .RN(n1470), .Q(
d_ff_Xn[16]) );
DFFRX1TS d_ff4_Xn_Q_reg_17_ ( .D(n868), .CK(n1499), .RN(n1470), .Q(
d_ff_Xn[17]) );
DFFRX1TS d_ff4_Xn_Q_reg_19_ ( .D(n866), .CK(n1065), .RN(n1469), .Q(
d_ff_Xn[19]) );
DFFRX1TS d_ff4_Xn_Q_reg_20_ ( .D(n865), .CK(n1498), .RN(n1469), .Q(
d_ff_Xn[20]) );
DFFRX1TS d_ff4_Xn_Q_reg_25_ ( .D(n860), .CK(n1501), .RN(n1468), .Q(
d_ff_Xn[25]) );
DFFRX1TS d_ff4_Xn_Q_reg_26_ ( .D(n859), .CK(n1065), .RN(n1468), .Q(
d_ff_Xn[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_30_ ( .D(n650), .CK(n1515), .RN(n1449),
.Q(d_ff2_X[30]) );
DFFRX1TS d_ff4_Yn_Q_reg_31_ ( .D(n886), .CK(n1496), .RN(n1473), .Q(
d_ff_Yn[31]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
inst_CORDIC_FSM_v3_state_next[1]), .CK(n1491), .RN(n1482), .Q(
inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_31_ ( .D(n769), .CK(n1510), .RN(n1460),
.Q(d_ff2_Z[31]) );
DFFRX1TS d_ff4_Xn_Q_reg_31_ ( .D(n854), .CK(n1499), .RN(n1467), .Q(
d_ff_Xn[31]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n1448), .CK(n1491), .RN(
n1482), .Q(inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS reg_LUT_Q_reg_27_ ( .D(n801), .CK(n1507), .RN(n1465), .Q(
d_ff3_LUT_out[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_30_ ( .D(n714), .CK(n1513), .RN(n1454),
.Q(d_ff2_Y[30]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(n719), .CK(n1066), .RN(n1455),
.Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(n718), .CK(n1510), .RN(n1455),
.Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(n655), .CK(n1516), .RN(n1449),
.Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(n654), .CK(n1518), .RN(n1449),
.Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(n720), .CK(n1514), .RN(n1455),
.Q(d_ff2_Y[24]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
inst_CORDIC_FSM_v3_state_next[4]), .CK(n1486), .RN(n1485), .Q(
inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(n651), .CK(n1517), .RN(n1449),
.Q(d_ff2_X[29]) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
inst_CORDIC_FSM_v3_state_next[2]), .CK(n1487), .RN(n1482), .Q(
inst_CORDIC_FSM_v3_state_reg[2]) );
DFFSX2TS inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
inst_CORDIC_FSM_v3_state_next[0]), .CK(n1516), .SN(n1484), .Q(
inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(n715), .CK(n1509), .RN(n1454),
.Q(d_ff2_Y[29]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_23_ ( .D(n657), .CK(n1518), .RN(n1449),
.Q(d_ff2_X[23]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
inst_CORDIC_FSM_v3_state_next[7]), .CK(n1491), .RN(n1485), .Q(
inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX2TS reg_val_muxX_2stage_Q_reg_27_ ( .D(n653), .CK(n1518), .RN(n1449),
.Q(d_ff2_X[27]) );
DFFRX2TS inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
inst_CORDIC_FSM_v3_state_next[5]), .CK(n1486), .RN(n1482), .Q(
inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX2TS reg_val_muxY_2stage_Q_reg_27_ ( .D(n717), .CK(n1510), .RN(n1455),
.Q(d_ff2_Y[27]) );
DFFRX1TS VAR_CONT_temp_reg_1_ ( .D(n990), .CK(n1516), .RN(n1485), .Q(
cont_var_out[1]), .QN(n1440) );
DFFRX1TS reg_LUT_Q_reg_6_ ( .D(n815), .CK(n1508), .RN(n1466), .Q(
d_ff3_LUT_out[6]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_26_ ( .D(n774), .CK(n1505), .RN(n1460),
.Q(d_ff2_Z[26]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_25_ ( .D(n775), .CK(n1508), .RN(n1460),
.Q(d_ff2_Z[25]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_22_ ( .D(n778), .CK(n1068), .RN(n1461),
.Q(d_ff2_Z[22]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_21_ ( .D(n779), .CK(n1508), .RN(n1461),
.Q(d_ff2_Z[21]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_20_ ( .D(n780), .CK(n1507), .RN(n1461),
.Q(d_ff2_Z[20]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_19_ ( .D(n781), .CK(n1503), .RN(n1461),
.Q(d_ff2_Z[19]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_18_ ( .D(n782), .CK(n1505), .RN(n1461),
.Q(d_ff2_Z[18]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_17_ ( .D(n783), .CK(n1507), .RN(n1461),
.Q(d_ff2_Z[17]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_16_ ( .D(n784), .CK(n1506), .RN(n1461),
.Q(d_ff2_Z[16]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_15_ ( .D(n785), .CK(n1068), .RN(n1461),
.Q(d_ff2_Z[15]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_14_ ( .D(n786), .CK(n1503), .RN(n1462),
.Q(d_ff2_Z[14]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_13_ ( .D(n787), .CK(n1507), .RN(n1462),
.Q(d_ff2_Z[13]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_12_ ( .D(n788), .CK(n1506), .RN(n1462),
.Q(d_ff2_Z[12]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_11_ ( .D(n789), .CK(n1505), .RN(n1462),
.Q(d_ff2_Z[11]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_9_ ( .D(n791), .CK(n1507), .RN(n1462),
.Q(d_ff2_Z[9]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_7_ ( .D(n793), .CK(n1505), .RN(n1462),
.Q(d_ff2_Z[7]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_5_ ( .D(n795), .CK(n1505), .RN(n1462),
.Q(d_ff2_Z[5]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_3_ ( .D(n797), .CK(n1068), .RN(n1463),
.Q(d_ff2_Z[3]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_1_ ( .D(n799), .CK(n1508), .RN(n1463),
.Q(d_ff2_Z[1]) );
DFFRX1TS reg_val_muxZ_2stage_Q_reg_0_ ( .D(n800), .CK(n1506), .RN(n1463),
.Q(d_ff2_Z[0]) );
DFFRX1TS reg_LUT_Q_reg_23_ ( .D(n805), .CK(n1068), .RN(n1465), .Q(
d_ff3_LUT_out[23]) );
DFFRX1TS reg_shift_x_Q_reg_4_ ( .D(n694), .CK(n1515), .RN(n1453), .Q(
d_ff3_sh_x_out[4]) );
DFFRX1TS reg_shift_x_Q_reg_10_ ( .D(n682), .CK(n1515), .RN(n1452), .Q(
d_ff3_sh_x_out[10]) );
DFFRX2TS ITER_CONT_temp_reg_0_ ( .D(n989), .CK(n1487), .RN(n1483), .Q(
cont_iter_out[0]), .QN(n1427) );
DFFRX1TS inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
inst_CORDIC_FSM_v3_state_next[6]), .CK(n1490), .RN(n1483), .Q(
inst_CORDIC_FSM_v3_state_reg[6]), .QN(n1445) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(n969), .CK(n1487), .RN(n281), .Q(d_ff1_Z[12])
);
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(n966), .CK(n1486), .RN(n281), .Q(d_ff1_Z[15])
);
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(n960), .CK(n1491), .RN(n281), .Q(d_ff1_Z[21])
);
NAND4XLTS U705 ( .A(n1439), .B(n1428), .C(n1059), .D(n1430), .Y(n1092) );
CLKBUFX3TS U706 ( .A(n1417), .Y(n1416) );
CLKBUFX2TS U707 ( .A(n1310), .Y(n1308) );
AOI222X1TS U708 ( .A0(n1232), .A1(d_ff2_Y[9]), .B0(n1315), .B1(d_ff2_X[9]),
.C0(d_ff2_Z[9]), .C1(n1248), .Y(n1230) );
AOI222X1TS U709 ( .A0(n1232), .A1(d_ff2_Y[15]), .B0(n1235), .B1(d_ff2_X[15]),
.C0(d_ff2_Z[15]), .C1(n1248), .Y(n1224) );
AOI222X1TS U710 ( .A0(n1232), .A1(d_ff2_Y[16]), .B0(n1235), .B1(d_ff2_X[16]),
.C0(d_ff2_Z[16]), .C1(n1392), .Y(n1223) );
AOI222X1TS U711 ( .A0(n1273), .A1(d_ff2_Y[21]), .B0(n1272), .B1(d_ff2_X[21]),
.C0(d_ff2_Z[21]), .C1(n1248), .Y(n1219) );
AOI222X1TS U712 ( .A0(n1273), .A1(d_ff2_Y[22]), .B0(n1272), .B1(d_ff2_X[22]),
.C0(d_ff2_Z[22]), .C1(n1392), .Y(n1218) );
AOI222X1TS U713 ( .A0(n1189), .A1(d_ff2_Z[19]), .B0(n1120), .B1(d_ff1_Z[19]),
.C0(d_ff_Zn[19]), .C1(n1116), .Y(n1117) );
AOI211X1TS U714 ( .A0(n1059), .A1(n1430), .B0(n1410), .C0(n1409), .Y(n1080)
);
CLKINVX3TS U715 ( .A(n1074), .Y(n1448) );
AOI222X1TS U716 ( .A0(n1176), .A1(data_output[24]), .B0(n1175), .B1(
d_ff_Yn[24]), .C0(n1161), .C1(d_ff_Xn[24]), .Y(n1169) );
AOI222X1TS U717 ( .A0(n1167), .A1(data_output[23]), .B0(n1175), .B1(
d_ff_Yn[23]), .C0(n1107), .C1(d_ff_Xn[23]), .Y(n1168) );
AOI222X1TS U718 ( .A0(n1176), .A1(data_output[22]), .B0(n1175), .B1(
d_ff_Yn[22]), .C0(n1174), .C1(d_ff_Xn[22]), .Y(n1166) );
AOI222X1TS U719 ( .A0(n1167), .A1(data_output[14]), .B0(n1162), .B1(
d_ff_Yn[14]), .C0(n1107), .C1(d_ff_Xn[14]), .Y(n1151) );
AND2X2TS U720 ( .A(n1092), .B(n1448), .Y(n1057) );
INVX2TS U721 ( .A(n1427), .Y(n1058) );
INVX2TS U722 ( .A(n1058), .Y(n1059) );
INVX2TS U723 ( .A(n1057), .Y(n1060) );
INVX2TS U724 ( .A(n1057), .Y(n1061) );
INVX2TS U725 ( .A(n1057), .Y(n1062) );
AOI222X1TS U726 ( .A0(n1185), .A1(data_output[12]), .B0(n1162), .B1(
d_ff_Yn[12]), .C0(n1161), .C1(d_ff_Xn[12]), .Y(n1148) );
AOI222X1TS U727 ( .A0(n1167), .A1(data_output[16]), .B0(n1162), .B1(
d_ff_Yn[16]), .C0(n1174), .C1(d_ff_Xn[16]), .Y(n1153) );
AOI222X1TS U728 ( .A0(n1167), .A1(data_output[18]), .B0(n1162), .B1(
d_ff_Yn[18]), .C0(n1161), .C1(d_ff_Xn[18]), .Y(n1155) );
AOI222X4TS U729 ( .A0(n1167), .A1(data_output[20]), .B0(n1162), .B1(
d_ff_Yn[20]), .C0(n1107), .C1(d_ff_Xn[20]), .Y(n1163) );
AOI32X1TS U730 ( .A0(cont_iter_out[0]), .A1(n1426), .A2(n1313), .B0(
d_ff3_LUT_out[23]), .B1(n1410), .Y(n1126) );
CLKINVX3TS U731 ( .A(n1300), .Y(n1426) );
CLKBUFX3TS U732 ( .A(n1485), .Y(n1483) );
CLKBUFX3TS U733 ( .A(n281), .Y(n1485) );
CLKINVX3TS U734 ( .A(n1448), .Y(n1113) );
CLKINVX3TS U735 ( .A(n1416), .Y(n1140) );
CLKINVX3TS U736 ( .A(n1300), .Y(n1414) );
CLKBUFX3TS U737 ( .A(n1079), .Y(n1300) );
INVX2TS U738 ( .A(n1358), .Y(n1063) );
INVX2TS U739 ( .A(n1063), .Y(n1064) );
INVX2TS U740 ( .A(n1146), .Y(n1174) );
NOR2X2TS U741 ( .A(cont_iter_out[3]), .B(n1428), .Y(n1349) );
NOR2X2TS U742 ( .A(n1439), .B(n1428), .Y(n1205) );
NOR4X2TS U743 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[3]),
.D(inst_CORDIC_FSM_v3_state_reg[0]), .Y(n1197) );
NOR3X4TS U744 ( .A(n1405), .B(n1427), .C(n1430), .Y(n1406) );
BUFX3TS U745 ( .A(n1085), .Y(n1502) );
CLKINVX6TS U746 ( .A(n1070), .Y(n1065) );
BUFX6TS U747 ( .A(n1085), .Y(n1500) );
BUFX6TS U748 ( .A(n1085), .Y(n1501) );
BUFX6TS U749 ( .A(n1085), .Y(n1499) );
BUFX6TS U750 ( .A(n1085), .Y(n1498) );
BUFX3TS U751 ( .A(n1088), .Y(n1509) );
CLKINVX6TS U752 ( .A(n1070), .Y(n1066) );
BUFX6TS U753 ( .A(n1088), .Y(n1513) );
BUFX6TS U754 ( .A(n1088), .Y(n1510) );
BUFX6TS U755 ( .A(n1088), .Y(n1511) );
BUFX6TS U756 ( .A(n1088), .Y(n1514) );
CLKINVX6TS U757 ( .A(n1070), .Y(n1067) );
BUFX6TS U758 ( .A(n1497), .Y(n1515) );
BUFX6TS U759 ( .A(clk), .Y(n1518) );
BUFX6TS U760 ( .A(n1512), .Y(n1517) );
BUFX6TS U761 ( .A(n1504), .Y(n1516) );
BUFX3TS U762 ( .A(n1084), .Y(n1503) );
CLKINVX6TS U763 ( .A(n1070), .Y(n1068) );
BUFX6TS U764 ( .A(n1084), .Y(n1505) );
BUFX6TS U765 ( .A(n1084), .Y(n1506) );
BUFX6TS U766 ( .A(n1084), .Y(n1507) );
BUFX6TS U767 ( .A(n1084), .Y(n1508) );
CLKINVX6TS U768 ( .A(n1070), .Y(n1069) );
BUFX6TS U769 ( .A(n1087), .Y(n1494) );
BUFX6TS U770 ( .A(n1087), .Y(n1492) );
BUFX6TS U771 ( .A(n1087), .Y(n1496) );
BUFX6TS U772 ( .A(n1087), .Y(n1493) );
BUFX6TS U773 ( .A(n1087), .Y(n1495) );
INVX2TS U774 ( .A(n1488), .Y(n1070) );
CLKINVX6TS U775 ( .A(n1070), .Y(n1071) );
CLKBUFX2TS U776 ( .A(n1086), .Y(n1488) );
BUFX6TS U777 ( .A(n1086), .Y(n1489) );
BUFX6TS U778 ( .A(n1086), .Y(n1490) );
BUFX6TS U779 ( .A(n1086), .Y(n1486) );
BUFX6TS U780 ( .A(n1086), .Y(n1491) );
BUFX6TS U781 ( .A(n1086), .Y(n1487) );
CLKBUFX3TS U782 ( .A(n1072), .Y(n1073) );
CLKBUFX3TS U783 ( .A(n281), .Y(n1072) );
XOR2XLTS U784 ( .A(d_ff_Yn[31]), .B(n1157), .Y(n1158) );
OAI33X4TS U785 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .A2(n1438), .B0(n1429), .B1(n1446), .B2(
d_ff1_shift_region_flag_out[0]), .Y(n1157) );
AOI222X1TS U786 ( .A0(n1396), .A1(d_ff3_sh_x_out[23]), .B0(n1215), .B1(
d_ff3_sh_y_out[23]), .C0(n1392), .C1(d_ff3_LUT_out[23]), .Y(n1251) );
AOI222X1TS U787 ( .A0(n1273), .A1(d_ff2_Y[0]), .B0(n1315), .B1(d_ff2_X[0]),
.C0(d_ff2_Z[0]), .C1(n1271), .Y(n1242) );
AOI222X1TS U788 ( .A0(n1243), .A1(d_ff2_Y[1]), .B0(n1315), .B1(d_ff2_X[1]),
.C0(d_ff2_Z[1]), .C1(n1271), .Y(n1240) );
AOI222X1TS U789 ( .A0(n1140), .A1(d_ff2_Z[3]), .B0(n1132), .B1(d_ff1_Z[3]),
.C0(d_ff_Zn[3]), .C1(n1139), .Y(n1133) );
AOI222X1TS U790 ( .A0(n1243), .A1(d_ff2_Y[3]), .B0(n1315), .B1(d_ff2_X[3]),
.C0(d_ff2_Z[3]), .C1(n1401), .Y(n1244) );
AOI222X1TS U791 ( .A0(n1140), .A1(d_ff2_Z[5]), .B0(n1132), .B1(d_ff1_Z[5]),
.C0(d_ff_Zn[5]), .C1(n1139), .Y(n1129) );
AOI222X1TS U792 ( .A0(n1140), .A1(d_ff2_Z[7]), .B0(n1132), .B1(d_ff1_Z[7]),
.C0(d_ff_Zn[7]), .C1(n1139), .Y(n1115) );
AOI222X1TS U793 ( .A0(n1113), .A1(d_ff2_Z[9]), .B0(n1132), .B1(d_ff1_Z[9]),
.C0(d_ff_Zn[9]), .C1(n1139), .Y(n1098) );
AOI222X1TS U794 ( .A0(n1113), .A1(d_ff2_Z[11]), .B0(n1109), .B1(d_ff1_Z[11]),
.C0(d_ff_Zn[11]), .C1(n1116), .Y(n1110) );
AOI222X1TS U795 ( .A0(n1113), .A1(d_ff2_Z[12]), .B0(n1120), .B1(d_ff1_Z[12]),
.C0(d_ff_Zn[12]), .C1(n1116), .Y(n1093) );
AOI222X1TS U796 ( .A0(n1232), .A1(d_ff2_Y[12]), .B0(n1235), .B1(d_ff2_X[12]),
.C0(d_ff2_Z[12]), .C1(n1401), .Y(n1227) );
AOI222X1TS U797 ( .A0(n1113), .A1(d_ff2_Z[13]), .B0(n1120), .B1(d_ff1_Z[13]),
.C0(d_ff_Zn[13]), .C1(n1116), .Y(n1094) );
AOI222X1TS U798 ( .A0(n1232), .A1(d_ff2_Y[13]), .B0(n1272), .B1(d_ff2_X[13]),
.C0(d_ff2_Z[13]), .C1(n1400), .Y(n1226) );
AOI222X1TS U799 ( .A0(n1113), .A1(d_ff2_Z[14]), .B0(n1120), .B1(d_ff1_Z[14]),
.C0(d_ff_Zn[14]), .C1(n1116), .Y(n1097) );
AOI222X1TS U800 ( .A0(n1232), .A1(d_ff2_Y[14]), .B0(n1235), .B1(d_ff2_X[14]),
.C0(d_ff2_Z[14]), .C1(n1241), .Y(n1225) );
AOI222X1TS U801 ( .A0(n1113), .A1(d_ff2_Z[15]), .B0(n1120), .B1(d_ff1_Z[15]),
.C0(d_ff_Zn[15]), .C1(n1116), .Y(n1099) );
AOI222X1TS U802 ( .A0(n1113), .A1(d_ff2_Z[16]), .B0(n1120), .B1(d_ff1_Z[16]),
.C0(d_ff_Zn[16]), .C1(n1116), .Y(n1106) );
AOI222X1TS U803 ( .A0(n1113), .A1(d_ff2_Z[17]), .B0(n1120), .B1(d_ff1_Z[17]),
.C0(d_ff_Zn[17]), .C1(n1116), .Y(n1111) );
AOI222X1TS U804 ( .A0(n1232), .A1(d_ff2_Y[17]), .B0(n1235), .B1(d_ff2_X[17]),
.C0(d_ff2_Z[17]), .C1(n1271), .Y(n1222) );
AOI222X1TS U805 ( .A0(n1113), .A1(d_ff2_Z[18]), .B0(n1120), .B1(d_ff1_Z[18]),
.C0(d_ff_Zn[18]), .C1(n1116), .Y(n1114) );
AOI222X1TS U806 ( .A0(n1273), .A1(d_ff2_Y[18]), .B0(n1235), .B1(d_ff2_X[18]),
.C0(d_ff2_Z[18]), .C1(n1401), .Y(n1221) );
AOI222X1TS U807 ( .A0(n1273), .A1(d_ff2_Y[19]), .B0(n1235), .B1(d_ff2_X[19]),
.C0(d_ff2_Z[19]), .C1(n1400), .Y(n1220) );
AOI222X1TS U808 ( .A0(n1189), .A1(d_ff2_Z[20]), .B0(n1120), .B1(d_ff1_Z[20]),
.C0(d_ff_Zn[20]), .C1(n1188), .Y(n1119) );
AOI222X1TS U809 ( .A0(n1273), .A1(d_ff2_Y[20]), .B0(n1272), .B1(d_ff2_X[20]),
.C0(d_ff2_Z[20]), .C1(n1241), .Y(n1238) );
AOI222X1TS U810 ( .A0(n1189), .A1(d_ff2_Z[21]), .B0(n1120), .B1(d_ff1_Z[21]),
.C0(d_ff_Zn[21]), .C1(n1188), .Y(n1121) );
AOI222X1TS U811 ( .A0(n1273), .A1(d_ff2_Y[25]), .B0(n1272), .B1(d_ff2_X[25]),
.C0(d_ff2_Z[25]), .C1(n1271), .Y(n1212) );
AOI222X1TS U812 ( .A0(n1273), .A1(d_ff2_Y[26]), .B0(n1272), .B1(d_ff2_X[26]),
.C0(d_ff2_Z[26]), .C1(n1401), .Y(n1211) );
AOI222X1TS U813 ( .A0(n1396), .A1(d_ff3_sh_x_out[6]), .B0(n1272), .B1(
d_ff3_sh_y_out[6]), .C0(d_ff3_LUT_out[6]), .C1(n1400), .Y(n1266) );
NOR2X2TS U814 ( .A(n1349), .B(n1359), .Y(n1412) );
AOI222X1TS U815 ( .A0(n1149), .A1(data_output[1]), .B0(n1164), .B1(
d_ff_Yn[1]), .C0(n1161), .C1(d_ff_Xn[1]), .Y(n1104) );
AOI222X1TS U816 ( .A0(n1167), .A1(data_output[13]), .B0(n1164), .B1(
d_ff_Yn[13]), .C0(n1107), .C1(d_ff_Xn[13]), .Y(n1150) );
AOI222X4TS U817 ( .A0(n1167), .A1(data_output[15]), .B0(n1164), .B1(
d_ff_Yn[15]), .C0(n1161), .C1(d_ff_Xn[15]), .Y(n1152) );
AOI222X4TS U818 ( .A0(n1167), .A1(data_output[17]), .B0(n1164), .B1(
d_ff_Yn[17]), .C0(n1174), .C1(d_ff_Xn[17]), .Y(n1154) );
AOI222X4TS U819 ( .A0(n1167), .A1(data_output[19]), .B0(n1164), .B1(
d_ff_Yn[19]), .C0(n1107), .C1(d_ff_Xn[19]), .Y(n1156) );
AOI222X1TS U820 ( .A0(n1149), .A1(data_output[0]), .B0(d_ff_Yn[0]), .B1(
n1164), .C0(d_ff_Xn[0]), .C1(n1174), .Y(n1108) );
AOI222X1TS U821 ( .A0(n1140), .A1(d_ff2_Z[0]), .B0(n1139), .B1(d_ff_Zn[0]),
.C0(n1138), .C1(d_ff1_Z[0]), .Y(n1141) );
AOI222X1TS U822 ( .A0(n1140), .A1(d_ff2_Z[1]), .B0(n1138), .B1(d_ff1_Z[1]),
.C0(d_ff_Zn[1]), .C1(n1139), .Y(n1136) );
AOI222X4TS U823 ( .A0(n1140), .A1(d_ff2_Z[2]), .B0(n1138), .B1(d_ff1_Z[2]),
.C0(d_ff_Zn[2]), .C1(n1139), .Y(n1135) );
AOI222X4TS U824 ( .A0(n1140), .A1(d_ff2_Z[4]), .B0(n1138), .B1(d_ff1_Z[4]),
.C0(d_ff_Zn[4]), .C1(n1139), .Y(n1131) );
AOI222X4TS U825 ( .A0(n1113), .A1(d_ff2_Z[10]), .B0(n1138), .B1(d_ff1_Z[10]),
.C0(d_ff_Zn[10]), .C1(n1116), .Y(n1105) );
AOI222X4TS U826 ( .A0(n1140), .A1(d_ff2_Z[8]), .B0(n1138), .B1(d_ff1_Z[8]),
.C0(d_ff_Zn[8]), .C1(n1139), .Y(n1096) );
AOI222X4TS U827 ( .A0(n1140), .A1(d_ff2_Z[6]), .B0(n1138), .B1(d_ff1_Z[6]),
.C0(d_ff_Zn[6]), .C1(n1139), .Y(n1095) );
CLKBUFX3TS U828 ( .A(n1308), .Y(n1304) );
CLKBUFX3TS U829 ( .A(n1321), .Y(n1319) );
CLKBUFX3TS U830 ( .A(n1345), .Y(n1320) );
CLKBUFX3TS U831 ( .A(n1295), .Y(n1280) );
AOI222X1TS U832 ( .A0(n1176), .A1(data_output[30]), .B0(n1175), .B1(
d_ff_Yn[30]), .C0(n1161), .C1(d_ff_Xn[30]), .Y(n1112) );
AOI222X4TS U833 ( .A0(n1167), .A1(data_output[21]), .B0(n1164), .B1(
d_ff_Yn[21]), .C0(n1107), .C1(d_ff_Xn[21]), .Y(n1165) );
AOI222X1TS U834 ( .A0(n1176), .A1(data_output[25]), .B0(n1175), .B1(
d_ff_Yn[25]), .C0(n1174), .C1(d_ff_Xn[25]), .Y(n1170) );
AOI222X1TS U835 ( .A0(n1396), .A1(d_ff3_sh_x_out[25]), .B0(n1253), .B1(
d_ff3_sh_y_out[25]), .C0(d_ff3_LUT_out[25]), .C1(n1392), .Y(n1249) );
AOI222X4TS U836 ( .A0(n1243), .A1(d_ff2_Y[2]), .B0(n1315), .B1(d_ff2_X[2]),
.C0(d_ff2_Z[2]), .C1(n1248), .Y(n1239) );
AOI222X4TS U837 ( .A0(n1243), .A1(d_ff2_Y[4]), .B0(n1315), .B1(d_ff2_X[4]),
.C0(d_ff2_Z[4]), .C1(n1241), .Y(n1237) );
AOI222X1TS U838 ( .A0(n1243), .A1(d_ff2_Y[5]), .B0(n1235), .B1(d_ff2_X[5]),
.C0(d_ff2_Z[5]), .C1(n1400), .Y(n1236) );
AOI222X4TS U839 ( .A0(n1243), .A1(d_ff2_Y[6]), .B0(n1315), .B1(d_ff2_X[6]),
.C0(d_ff2_Z[6]), .C1(n1401), .Y(n1234) );
AOI222X1TS U840 ( .A0(n1232), .A1(d_ff2_Y[7]), .B0(n1315), .B1(d_ff2_X[7]),
.C0(d_ff2_Z[7]), .C1(n1271), .Y(n1233) );
AOI222X4TS U841 ( .A0(n1243), .A1(d_ff2_Y[8]), .B0(n1315), .B1(d_ff2_X[8]),
.C0(d_ff2_Z[8]), .C1(n1392), .Y(n1231) );
AOI222X4TS U842 ( .A0(n1232), .A1(d_ff2_Y[10]), .B0(n1235), .B1(d_ff2_X[10]),
.C0(d_ff2_Z[10]), .C1(n1241), .Y(n1229) );
AOI222X1TS U843 ( .A0(n1232), .A1(d_ff2_Y[11]), .B0(n1235), .B1(d_ff2_X[11]),
.C0(d_ff2_Z[11]), .C1(n1400), .Y(n1228) );
NOR3X2TS U844 ( .A(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(inst_CORDIC_FSM_v3_state_reg[1]),
.Y(n1077) );
OAI21X2TS U845 ( .A0(n1205), .A1(n1427), .B0(n1409), .Y(n1359) );
OAI211X2TS U846 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[0]), .B0(n1193),
.C0(n1409), .Y(n1334) );
NAND2X2TS U847 ( .A(cont_iter_out[3]), .B(n1428), .Y(n1409) );
AOI222X1TS U848 ( .A0(n1189), .A1(d_ff2_Z[22]), .B0(n1201), .B1(d_ff1_Z[22]),
.C0(d_ff_Zn[22]), .C1(n1188), .Y(n1122) );
AOI222X1TS U849 ( .A0(n1189), .A1(d_ff2_Z[25]), .B0(n1201), .B1(d_ff1_Z[25]),
.C0(d_ff_Zn[25]), .C1(n1188), .Y(n1123) );
AOI222X1TS U850 ( .A0(n1189), .A1(d_ff2_Z[26]), .B0(n1201), .B1(d_ff1_Z[26]),
.C0(d_ff_Zn[26]), .C1(n1188), .Y(n1125) );
CLKINVX3TS U851 ( .A(n1416), .Y(n1189) );
NOR3X4TS U852 ( .A(inst_CORDIC_FSM_v3_state_reg[5]), .B(n1445), .C(n1089),
.Y(enab_cont_iter) );
NOR2XLTS U853 ( .A(n1405), .B(n1387), .Y(n1100) );
OAI21XLTS U854 ( .A0(n1410), .A1(n1289), .B0(n1194), .Y(n713) );
OAI21XLTS U855 ( .A0(n1383), .A1(n1437), .B0(n1264), .Y(add_subt_dataB[9])
);
OAI21XLTS U856 ( .A0(n1262), .A1(n1432), .B0(n1254), .Y(add_subt_dataB[20])
);
OAI21XLTS U857 ( .A0(n1246), .A1(n1443), .B0(n1217), .Y(add_subt_dataA[23])
);
INVX2TS U858 ( .A(rst), .Y(n281) );
BUFX3TS U859 ( .A(n1483), .Y(n1475) );
CLKBUFX3TS U860 ( .A(n1485), .Y(n1484) );
BUFX3TS U861 ( .A(n1484), .Y(n1481) );
BUFX3TS U862 ( .A(n1483), .Y(n1477) );
BUFX3TS U863 ( .A(n1483), .Y(n1476) );
BUFX3TS U864 ( .A(n1483), .Y(n1478) );
BUFX3TS U865 ( .A(n1072), .Y(n1462) );
BUFX3TS U866 ( .A(n1073), .Y(n1461) );
BUFX3TS U867 ( .A(n1072), .Y(n1452) );
BUFX3TS U868 ( .A(n1073), .Y(n1453) );
BUFX3TS U869 ( .A(n1483), .Y(n1474) );
BUFX3TS U870 ( .A(n1484), .Y(n1480) );
BUFX3TS U871 ( .A(n1072), .Y(n1465) );
BUFX3TS U872 ( .A(n1484), .Y(n1482) );
BUFX3TS U873 ( .A(n281), .Y(n1471) );
BUFX3TS U874 ( .A(n1072), .Y(n1472) );
BUFX3TS U875 ( .A(n1485), .Y(n1470) );
BUFX3TS U876 ( .A(n1485), .Y(n1473) );
BUFX3TS U877 ( .A(n1073), .Y(n1469) );
BUFX3TS U878 ( .A(n1073), .Y(n1455) );
BUFX3TS U879 ( .A(n1484), .Y(n1468) );
BUFX3TS U880 ( .A(n1072), .Y(n1449) );
BUFX3TS U881 ( .A(n1072), .Y(n1460) );
BUFX3TS U882 ( .A(n1072), .Y(n1454) );
BUFX3TS U883 ( .A(n1483), .Y(n1463) );
BUFX3TS U884 ( .A(n1073), .Y(n1450) );
BUFX3TS U885 ( .A(n1073), .Y(n1451) );
BUFX3TS U886 ( .A(n1073), .Y(n1456) );
BUFX3TS U887 ( .A(n1072), .Y(n1457) );
BUFX3TS U888 ( .A(n1484), .Y(n1479) );
BUFX3TS U889 ( .A(n1072), .Y(n1466) );
BUFX3TS U890 ( .A(n1485), .Y(n1467) );
BUFX3TS U891 ( .A(n1073), .Y(n1458) );
BUFX3TS U892 ( .A(n1073), .Y(n1459) );
BUFX3TS U893 ( .A(n1073), .Y(n1464) );
NOR3BX1TS U894 ( .AN(n1197), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[1]), .Y(n1075) );
NAND3BXLTS U895 ( .AN(inst_CORDIC_FSM_v3_state_reg[4]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(n1075), .Y(n1074) );
NOR3BX1TS U896 ( .AN(n1077), .B(inst_CORDIC_FSM_v3_state_reg[7]), .C(
inst_CORDIC_FSM_v3_state_reg[3]), .Y(n1195) );
NAND2BX1TS U897 ( .AN(inst_CORDIC_FSM_v3_state_reg[0]), .B(n1195), .Y(n1089)
);
NAND3BX1TS U898 ( .AN(inst_CORDIC_FSM_v3_state_reg[2]), .B(
inst_CORDIC_FSM_v3_state_reg[4]), .C(n1075), .Y(n1384) );
NOR3BX2TS U899 ( .AN(n1384), .B(enab_cont_iter), .C(ready_add_subt), .Y(
n1275) );
NAND2X1TS U900 ( .A(cont_var_out[0]), .B(n1440), .Y(n1214) );
NAND2X1TS U901 ( .A(cont_var_out[1]), .B(n1431), .Y(n1246) );
NAND2X1TS U902 ( .A(n1275), .B(cont_var_out[1]), .Y(n1076) );
OAI211XLTS U903 ( .A0(n1275), .A1(n1214), .B0(n1246), .C0(n1076), .Y(n990)
);
NAND3X1TS U904 ( .A(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1197), .C(n1077),
.Y(n1388) );
INVX2TS U905 ( .A(n1388), .Y(ready_cordic) );
NOR3XLTS U906 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .C(inst_CORDIC_FSM_v3_state_reg[0]),
.Y(n1078) );
NAND4BXLTS U907 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(
inst_CORDIC_FSM_v3_state_reg[3]), .C(n1078), .D(n1077), .Y(n1079) );
NAND2X2TS U908 ( .A(n1414), .B(n1430), .Y(n1352) );
CLKBUFX2TS U909 ( .A(n1079), .Y(n1279) );
CLKBUFX2TS U910 ( .A(n1279), .Y(n1287) );
CLKBUFX3TS U911 ( .A(n1287), .Y(n1410) );
NAND2X2TS U912 ( .A(n1414), .B(cont_iter_out[1]), .Y(n1347) );
NOR3X1TS U913 ( .A(cont_iter_out[2]), .B(n1059), .C(n1347), .Y(n1191) );
AOI211X1TS U914 ( .A0(d_ff3_LUT_out[6]), .A1(n1410), .B0(n1080), .C0(n1191),
.Y(n1081) );
OAI31X1TS U915 ( .A0(cont_iter_out[3]), .A1(cont_iter_out[0]), .A2(n1352),
.B0(n1081), .Y(n815) );
NAND3XLTS U916 ( .A(n1440), .B(n1431), .C(ready_add_subt), .Y(n1082) );
CLKBUFX2TS U917 ( .A(n1082), .Y(n1326) );
INVX2TS U918 ( .A(n1326), .Y(n1314) );
CLKBUFX2TS U919 ( .A(n1082), .Y(n1321) );
AO22XLTS U920 ( .A0(n1314), .A1(result_add_subt[31]), .B0(n1321), .B1(
d_ff_Xn[31]), .Y(n854) );
INVX2TS U921 ( .A(n1352), .Y(n1332) );
INVX2TS U922 ( .A(n1349), .Y(n1193) );
AOI22X1TS U923 ( .A0(n1332), .A1(n1334), .B0(d_ff3_LUT_out[1]), .B1(n1410),
.Y(n1083) );
OAI2BB1X1TS U924 ( .A0N(n1409), .A1N(n1193), .B0(n1414), .Y(n1118) );
NAND2X1TS U925 ( .A(n1083), .B(n1118), .Y(n820) );
CLKBUFX2TS U926 ( .A(clk), .Y(n1085) );
CLKBUFX2TS U927 ( .A(clk), .Y(n1086) );
BUFX3TS U928 ( .A(n1085), .Y(n1497) );
CLKBUFX2TS U929 ( .A(clk), .Y(n1084) );
BUFX3TS U930 ( .A(n1084), .Y(n1504) );
CLKBUFX2TS U931 ( .A(clk), .Y(n1088) );
BUFX3TS U932 ( .A(n1088), .Y(n1512) );
CLKBUFX2TS U933 ( .A(clk), .Y(n1087) );
NAND3BX1TS U934 ( .AN(n1089), .B(inst_CORDIC_FSM_v3_state_reg[5]), .C(n1445),
.Y(n1385) );
NAND2X1TS U935 ( .A(n1384), .B(n1385), .Y(beg_add_subt) );
INVX2TS U936 ( .A(n1214), .Y(n1215) );
CLKBUFX2TS U937 ( .A(n1215), .Y(n1253) );
CLKBUFX2TS U938 ( .A(n1253), .Y(n1404) );
INVX2TS U939 ( .A(n1246), .Y(n1396) );
CLKBUFX2TS U940 ( .A(n1396), .Y(n1260) );
CLKBUFX2TS U941 ( .A(n1260), .Y(n1398) );
CLKBUFX3TS U942 ( .A(n1398), .Y(n1243) );
OR2X2TS U943 ( .A(n1440), .B(n1431), .Y(n1262) );
CLKBUFX2TS U944 ( .A(n1262), .Y(n1389) );
INVX2TS U945 ( .A(n1389), .Y(n1401) );
AOI22X1TS U946 ( .A0(n1243), .A1(d_ff2_Y[29]), .B0(d_ff2_Z[29]), .B1(n1248),
.Y(n1090) );
OAI2BB1X1TS U947 ( .A0N(n1253), .A1N(d_ff2_X[29]), .B0(n1090), .Y(
add_subt_dataA[29]) );
AOI22X1TS U948 ( .A0(n1243), .A1(d_ff2_Y[27]), .B0(d_ff2_Z[27]), .B1(n1392),
.Y(n1091) );
OAI2BB1X1TS U949 ( .A0N(n1216), .A1N(d_ff2_X[27]), .B0(n1091), .Y(
add_subt_dataA[27]) );
CLKBUFX2TS U950 ( .A(n1448), .Y(n1417) );
NOR2X1TS U951 ( .A(n1140), .B(n1092), .Y(n1109) );
CLKBUFX2TS U952 ( .A(n1109), .Y(n1132) );
CLKBUFX3TS U953 ( .A(n1132), .Y(n1120) );
INVX2TS U954 ( .A(n1060), .Y(n1328) );
CLKBUFX2TS U955 ( .A(n1328), .Y(n1337) );
CLKBUFX3TS U956 ( .A(n1337), .Y(n1116) );
INVX2TS U957 ( .A(n1093), .Y(n788) );
INVX2TS U958 ( .A(n1094), .Y(n787) );
CLKBUFX2TS U959 ( .A(n1132), .Y(n1138) );
CLKBUFX3TS U960 ( .A(n1337), .Y(n1139) );
INVX2TS U961 ( .A(n1095), .Y(n794) );
INVX2TS U962 ( .A(n1096), .Y(n792) );
INVX2TS U963 ( .A(n1097), .Y(n786) );
INVX2TS U964 ( .A(n1098), .Y(n791) );
INVX2TS U965 ( .A(n1099), .Y(n785) );
INVX2TS U966 ( .A(enab_cont_iter), .Y(n1405) );
NAND3X1TS U967 ( .A(n1205), .B(cont_iter_out[0]), .C(cont_iter_out[1]), .Y(
n1387) );
NOR2XLTS U968 ( .A(ready_cordic), .B(n1100), .Y(n1101) );
CLKBUFX2TS U969 ( .A(n1101), .Y(n1149) );
XNOR2X1TS U970 ( .A(d_ff1_shift_region_flag_out[1]), .B(d_ff1_operation_out),
.Y(n1102) );
XNOR2X1TS U971 ( .A(d_ff1_shift_region_flag_out[0]), .B(n1102), .Y(n1103) );
NOR2BX1TS U972 ( .AN(n1103), .B(n1149), .Y(n1127) );
CLKBUFX2TS U973 ( .A(n1127), .Y(n1162) );
CLKBUFX2TS U974 ( .A(n1162), .Y(n1164) );
CLKBUFX3TS U975 ( .A(n1149), .Y(n1176) );
OR2X2TS U976 ( .A(n1176), .B(n1103), .Y(n1146) );
INVX2TS U977 ( .A(n1146), .Y(n1183) );
INVX2TS U978 ( .A(n1104), .Y(n852) );
INVX2TS U979 ( .A(n1105), .Y(n790) );
INVX2TS U980 ( .A(n1106), .Y(n784) );
INVX2TS U981 ( .A(n1146), .Y(n1107) );
INVX2TS U982 ( .A(n1108), .Y(n853) );
INVX2TS U983 ( .A(n1347), .Y(n1360) );
INVX2TS U984 ( .A(n1205), .Y(n1313) );
NAND2X1TS U985 ( .A(n1360), .B(n1313), .Y(n1411) );
OAI211XLTS U986 ( .A0(n1426), .A1(n1432), .B0(n1118), .C0(n1411), .Y(n808)
);
INVX2TS U987 ( .A(n1110), .Y(n789) );
INVX2TS U988 ( .A(n1111), .Y(n783) );
CLKBUFX3TS U989 ( .A(n1162), .Y(n1175) );
INVX2TS U990 ( .A(n1112), .Y(n823) );
INVX2TS U991 ( .A(n1114), .Y(n782) );
INVX2TS U992 ( .A(n1115), .Y(n793) );
INVX2TS U993 ( .A(n1117), .Y(n781) );
NAND2X1TS U994 ( .A(n1332), .B(n1313), .Y(n1124) );
OAI211XLTS U995 ( .A0(n1426), .A1(n1434), .B0(n1118), .C0(n1124), .Y(n818)
);
CLKBUFX3TS U996 ( .A(n1328), .Y(n1188) );
INVX2TS U997 ( .A(n1119), .Y(n780) );
INVX2TS U998 ( .A(n1121), .Y(n779) );
CLKBUFX3TS U999 ( .A(n1132), .Y(n1201) );
INVX2TS U1000 ( .A(n1122), .Y(n778) );
INVX2TS U1001 ( .A(n1123), .Y(n775) );
NAND2X1TS U1002 ( .A(n1360), .B(n1334), .Y(n1408) );
OAI211XLTS U1003 ( .A0(n1426), .A1(n1437), .B0(n1124), .C0(n1408), .Y(n812)
);
INVX2TS U1004 ( .A(n1125), .Y(n774) );
NAND2X1TS U1005 ( .A(n1414), .B(n1059), .Y(n1350) );
OAI21XLTS U1006 ( .A0(n1313), .A1(n1350), .B0(n1126), .Y(n805) );
CLKBUFX2TS U1007 ( .A(n1260), .Y(n1378) );
NAND2X1TS U1008 ( .A(n1378), .B(ready_add_subt), .Y(n1276) );
CLKBUFX2TS U1009 ( .A(n1276), .Y(n1295) );
NOR2XLTS U1010 ( .A(n1385), .B(n1280), .Y(inst_CORDIC_FSM_v3_state_next[6])
);
CLKBUFX3TS U1011 ( .A(n1127), .Y(n1184) );
AOI222X1TS U1012 ( .A0(n1149), .A1(data_output[2]), .B0(n1184), .B1(
d_ff_Yn[2]), .C0(n1183), .C1(d_ff_Xn[2]), .Y(n1128) );
INVX2TS U1013 ( .A(n1128), .Y(n851) );
INVX2TS U1014 ( .A(n1129), .Y(n795) );
CLKBUFX3TS U1015 ( .A(n1149), .Y(n1185) );
AOI222X1TS U1016 ( .A0(n1185), .A1(data_output[3]), .B0(n1184), .B1(
d_ff_Yn[3]), .C0(n1183), .C1(d_ff_Xn[3]), .Y(n1130) );
INVX2TS U1017 ( .A(n1130), .Y(n850) );
INVX2TS U1018 ( .A(n1131), .Y(n796) );
INVX2TS U1019 ( .A(n1133), .Y(n797) );
AOI222X1TS U1020 ( .A0(n1185), .A1(data_output[4]), .B0(n1184), .B1(
d_ff_Yn[4]), .C0(n1183), .C1(d_ff_Xn[4]), .Y(n1134) );
INVX2TS U1021 ( .A(n1134), .Y(n849) );
INVX2TS U1022 ( .A(n1135), .Y(n798) );
INVX2TS U1023 ( .A(n1136), .Y(n799) );
AOI222X1TS U1024 ( .A0(n1185), .A1(data_output[6]), .B0(n1184), .B1(
d_ff_Yn[6]), .C0(n1183), .C1(d_ff_Xn[6]), .Y(n1137) );
INVX2TS U1025 ( .A(n1137), .Y(n847) );
INVX2TS U1026 ( .A(n1141), .Y(n800) );
AOI222X1TS U1027 ( .A0(n1185), .A1(data_output[7]), .B0(n1184), .B1(
d_ff_Yn[7]), .C0(n1183), .C1(d_ff_Xn[7]), .Y(n1142) );
INVX2TS U1028 ( .A(n1142), .Y(n846) );
AOI222X1TS U1029 ( .A0(n1185), .A1(data_output[8]), .B0(n1184), .B1(
d_ff_Yn[8]), .C0(n1183), .C1(d_ff_Xn[8]), .Y(n1143) );
INVX2TS U1030 ( .A(n1143), .Y(n845) );
AOI222X1TS U1031 ( .A0(n1185), .A1(data_output[9]), .B0(n1184), .B1(
d_ff_Yn[9]), .C0(n1183), .C1(d_ff_Xn[9]), .Y(n1144) );
INVX2TS U1032 ( .A(n1144), .Y(n844) );
AOI222X1TS U1033 ( .A0(n1185), .A1(data_output[10]), .B0(n1184), .B1(
d_ff_Yn[10]), .C0(n1161), .C1(d_ff_Xn[10]), .Y(n1145) );
INVX2TS U1034 ( .A(n1145), .Y(n843) );
INVX2TS U1035 ( .A(n1146), .Y(n1161) );
AOI222X1TS U1036 ( .A0(n1185), .A1(data_output[11]), .B0(n1184), .B1(
d_ff_Yn[11]), .C0(n1174), .C1(d_ff_Xn[11]), .Y(n1147) );
INVX2TS U1037 ( .A(n1147), .Y(n842) );
INVX2TS U1038 ( .A(n1148), .Y(n841) );
CLKBUFX3TS U1039 ( .A(n1149), .Y(n1167) );
INVX2TS U1040 ( .A(n1150), .Y(n840) );
INVX2TS U1041 ( .A(n1151), .Y(n839) );
INVX2TS U1042 ( .A(n1152), .Y(n838) );
INVX2TS U1043 ( .A(n1153), .Y(n837) );
INVX2TS U1044 ( .A(n1154), .Y(n836) );
INVX2TS U1045 ( .A(n1155), .Y(n835) );
INVX2TS U1046 ( .A(n1156), .Y(n834) );
XNOR2X1TS U1047 ( .A(n1157), .B(d_ff_Xn[31]), .Y(n1160) );
AOI22X1TS U1048 ( .A0(n1176), .A1(data_output[31]), .B0(n1175), .B1(n1158),
.Y(n1159) );
OAI21XLTS U1049 ( .A0(n1160), .A1(n1146), .B0(n1159), .Y(n822) );
INVX2TS U1050 ( .A(n1163), .Y(n833) );
INVX2TS U1051 ( .A(n1165), .Y(n832) );
INVX2TS U1052 ( .A(n1166), .Y(n831) );
INVX2TS U1053 ( .A(n1168), .Y(n830) );
INVX2TS U1054 ( .A(n1169), .Y(n829) );
INVX2TS U1055 ( .A(n1170), .Y(n828) );
AOI222X1TS U1056 ( .A0(n1176), .A1(data_output[26]), .B0(n1175), .B1(
d_ff_Yn[26]), .C0(n1174), .C1(d_ff_Xn[26]), .Y(n1171) );
INVX2TS U1057 ( .A(n1171), .Y(n827) );
AOI222X1TS U1058 ( .A0(n1176), .A1(data_output[27]), .B0(n1175), .B1(
d_ff_Yn[27]), .C0(n1161), .C1(d_ff_Xn[27]), .Y(n1172) );
INVX2TS U1059 ( .A(n1172), .Y(n826) );
AOI222X1TS U1060 ( .A0(n1176), .A1(data_output[28]), .B0(n1175), .B1(
d_ff_Yn[28]), .C0(n1107), .C1(d_ff_Xn[28]), .Y(n1173) );
INVX2TS U1061 ( .A(n1173), .Y(n825) );
AOI222X1TS U1062 ( .A0(n1176), .A1(data_output[29]), .B0(n1175), .B1(
d_ff_Yn[29]), .C0(n1174), .C1(d_ff_Xn[29]), .Y(n1177) );
INVX2TS U1063 ( .A(n1177), .Y(n824) );
INVX2TS U1064 ( .A(n1416), .Y(n1374) );
AOI222X1TS U1065 ( .A0(n1374), .A1(d_ff2_Z[29]), .B0(n1201), .B1(d_ff1_Z[29]), .C0(d_ff_Zn[29]), .C1(n1188), .Y(n1178) );
INVX2TS U1066 ( .A(n1178), .Y(n771) );
CLKBUFX3TS U1067 ( .A(n1337), .Y(n1375) );
AOI222X1TS U1068 ( .A0(n1374), .A1(d_ff2_Z[30]), .B0(n1201), .B1(d_ff1_Z[30]), .C0(d_ff_Zn[30]), .C1(n1375), .Y(n1179) );
INVX2TS U1069 ( .A(n1179), .Y(n770) );
AOI222X1TS U1070 ( .A0(n1189), .A1(d_ff2_Z[28]), .B0(n1201), .B1(d_ff1_Z[28]), .C0(d_ff_Zn[28]), .C1(n1188), .Y(n1180) );
INVX2TS U1071 ( .A(n1180), .Y(n772) );
AOI21X1TS U1072 ( .A0(cont_iter_out[2]), .A1(cont_iter_out[0]), .B0(
cont_iter_out[3]), .Y(n1207) );
CLKBUFX3TS U1073 ( .A(n1279), .Y(n1424) );
AOI22X1TS U1074 ( .A0(n1426), .A1(n1207), .B0(d_ff3_LUT_out[26]), .B1(n1424),
.Y(n1181) );
OAI21XLTS U1075 ( .A0(cont_iter_out[3]), .A1(n1352), .B0(n1181), .Y(n802) );
OAI21XLTS U1076 ( .A0(n1241), .A1(n1384), .B0(n1424), .Y(
inst_CORDIC_FSM_v3_state_next[4]) );
AOI222X1TS U1077 ( .A0(n1189), .A1(d_ff2_Z[27]), .B0(n1201), .B1(d_ff1_Z[27]), .C0(d_ff_Zn[27]), .C1(n1188), .Y(n1182) );
INVX2TS U1078 ( .A(n1182), .Y(n773) );
AOI222X1TS U1079 ( .A0(n1185), .A1(data_output[5]), .B0(n1184), .B1(
d_ff_Yn[5]), .C0(n1107), .C1(d_ff_Xn[5]), .Y(n1186) );
INVX2TS U1080 ( .A(n1186), .Y(n848) );
AOI222X1TS U1081 ( .A0(n1189), .A1(d_ff2_Z[24]), .B0(n1201), .B1(d_ff1_Z[24]), .C0(d_ff_Zn[24]), .C1(n1188), .Y(n1187) );
INVX2TS U1082 ( .A(n1187), .Y(n776) );
AOI222X1TS U1083 ( .A0(n1189), .A1(d_ff2_Z[23]), .B0(n1201), .B1(d_ff1_Z[23]), .C0(d_ff_Zn[23]), .C1(n1188), .Y(n1190) );
INVX2TS U1084 ( .A(n1190), .Y(n777) );
AOI21X1TS U1085 ( .A0(d_ff3_LUT_out[2]), .A1(n1424), .B0(n1191), .Y(n1192)
);
OAI21XLTS U1086 ( .A0(n1352), .A1(n1193), .B0(n1192), .Y(n819) );
NAND2X1TS U1087 ( .A(cont_iter_out[0]), .B(n1443), .Y(n1289) );
INVX2TS U1088 ( .A(n1350), .Y(n1418) );
AOI22X1TS U1089 ( .A0(d_ff2_Y[23]), .A1(n1418), .B0(d_ff3_sh_y_out[23]),
.B1(n1424), .Y(n1194) );
NOR2XLTS U1090 ( .A(inst_CORDIC_FSM_v3_state_reg[6]), .B(
inst_CORDIC_FSM_v3_state_reg[5]), .Y(n1196) );
NAND3X1TS U1091 ( .A(n1196), .B(inst_CORDIC_FSM_v3_state_reg[0]), .C(n1195),
.Y(n1382) );
NAND2BXLTS U1092 ( .AN(inst_CORDIC_FSM_v3_state_reg[7]), .B(n1197), .Y(n1198) );
NOR4BX1TS U1093 ( .AN(inst_CORDIC_FSM_v3_state_reg[1]), .B(
inst_CORDIC_FSM_v3_state_reg[2]), .C(inst_CORDIC_FSM_v3_state_reg[4]),
.D(n1198), .Y(n1358) );
NOR2BX4TS U1094 ( .AN(n1382), .B(n1064), .Y(n1311) );
INVX2TS U1095 ( .A(n1311), .Y(n1310) );
INVX2TS U1096 ( .A(n1305), .Y(n1306) );
NOR4X1TS U1097 ( .A(enab_cont_iter), .B(n1414), .C(n1417), .D(beg_add_subt),
.Y(n1199) );
AOI32X1TS U1098 ( .A0(n1306), .A1(n1388), .A2(n1199), .B0(ready_cordic),
.B1(ack_cordic), .Y(n1200) );
OAI21XLTS U1099 ( .A0(beg_fsm_cordic), .A1(n1382), .B0(n1200), .Y(
inst_CORDIC_FSM_v3_state_next[0]) );
AOI222X1TS U1100 ( .A0(n1374), .A1(d_ff2_Z[31]), .B0(n1201), .B1(d_ff1_Z[31]), .C0(d_ff_Zn[31]), .C1(n1375), .Y(n1202) );
INVX2TS U1101 ( .A(n1202), .Y(n769) );
NAND2X1TS U1102 ( .A(cont_iter_out[0]), .B(n1313), .Y(n1203) );
AOI22X1TS U1103 ( .A0(n1332), .A1(n1203), .B0(d_ff3_LUT_out[24]), .B1(n1410),
.Y(n1204) );
OAI21XLTS U1104 ( .A0(n1059), .A1(n1411), .B0(n1204), .Y(n804) );
AOI211X1TS U1105 ( .A0(cont_iter_out[0]), .A1(n1439), .B0(cont_iter_out[2]),
.C0(n1352), .Y(n1362) );
AOI21X1TS U1106 ( .A0(d_ff3_LUT_out[0]), .A1(n1424), .B0(n1362), .Y(n1206)
);
OAI21XLTS U1107 ( .A0(n1412), .A1(n1347), .B0(n1206), .Y(n821) );
AOI22X1TS U1108 ( .A0(n1207), .A1(n1332), .B0(d_ff3_LUT_out[4]), .B1(n1410),
.Y(n1208) );
OAI21XLTS U1109 ( .A0(cont_iter_out[2]), .A1(n1347), .B0(n1208), .Y(n817) );
CLKBUFX3TS U1110 ( .A(n1378), .Y(n1273) );
CLKBUFX3TS U1111 ( .A(n1404), .Y(n1272) );
INVX2TS U1112 ( .A(n1389), .Y(n1400) );
AOI222X1TS U1113 ( .A0(n1273), .A1(d_ff2_Y[31]), .B0(n1272), .B1(d_ff2_X[31]), .C0(d_ff2_Z[31]), .C1(n1271), .Y(n1209) );
INVX2TS U1114 ( .A(n1209), .Y(add_subt_dataA[31]) );
AOI22X1TS U1115 ( .A0(n1396), .A1(d_ff2_Y[28]), .B0(d_ff2_Z[28]), .B1(n1271),
.Y(n1210) );
OAI21XLTS U1116 ( .A0(n1214), .A1(n1444), .B0(n1210), .Y(add_subt_dataA[28])
);
INVX2TS U1117 ( .A(n1211), .Y(add_subt_dataA[26]) );
INVX2TS U1118 ( .A(n1212), .Y(add_subt_dataA[25]) );
AOI22X1TS U1119 ( .A0(n1243), .A1(d_ff2_Y[24]), .B0(d_ff2_Z[24]), .B1(n1401),
.Y(n1213) );
OAI21XLTS U1120 ( .A0(n1214), .A1(n1441), .B0(n1213), .Y(add_subt_dataA[24])
);
CLKBUFX2TS U1121 ( .A(n1215), .Y(n1216) );
CLKBUFX3TS U1122 ( .A(n1216), .Y(n1395) );
AOI22X1TS U1123 ( .A0(n1395), .A1(d_ff2_X[23]), .B0(d_ff2_Z[23]), .B1(n1400),
.Y(n1217) );
INVX2TS U1124 ( .A(n1218), .Y(add_subt_dataA[22]) );
INVX2TS U1125 ( .A(n1219), .Y(add_subt_dataA[21]) );
CLKBUFX3TS U1126 ( .A(n1404), .Y(n1235) );
INVX2TS U1127 ( .A(n1389), .Y(n1241) );
INVX2TS U1128 ( .A(n1220), .Y(add_subt_dataA[19]) );
INVX2TS U1129 ( .A(n1221), .Y(add_subt_dataA[18]) );
CLKBUFX3TS U1130 ( .A(n1378), .Y(n1232) );
INVX2TS U1131 ( .A(n1222), .Y(add_subt_dataA[17]) );
INVX2TS U1132 ( .A(n1223), .Y(add_subt_dataA[16]) );
INVX2TS U1133 ( .A(n1224), .Y(add_subt_dataA[15]) );
INVX2TS U1134 ( .A(n1225), .Y(add_subt_dataA[14]) );
INVX2TS U1135 ( .A(n1226), .Y(add_subt_dataA[13]) );
INVX2TS U1136 ( .A(n1227), .Y(add_subt_dataA[12]) );
INVX2TS U1137 ( .A(n1389), .Y(n1248) );
INVX2TS U1138 ( .A(n1228), .Y(add_subt_dataA[11]) );
INVX2TS U1139 ( .A(n1229), .Y(add_subt_dataA[10]) );
CLKBUFX3TS U1140 ( .A(n1253), .Y(n1315) );
INVX2TS U1141 ( .A(n1230), .Y(add_subt_dataA[9]) );
INVX2TS U1142 ( .A(n1231), .Y(add_subt_dataA[8]) );
INVX2TS U1143 ( .A(n1233), .Y(add_subt_dataA[7]) );
INVX2TS U1144 ( .A(n1234), .Y(add_subt_dataA[6]) );
INVX2TS U1145 ( .A(n1236), .Y(add_subt_dataA[5]) );
INVX2TS U1146 ( .A(n1237), .Y(add_subt_dataA[4]) );
INVX2TS U1147 ( .A(n1238), .Y(add_subt_dataA[20]) );
INVX2TS U1148 ( .A(n1239), .Y(add_subt_dataA[2]) );
INVX2TS U1149 ( .A(n1389), .Y(n1271) );
INVX2TS U1150 ( .A(n1240), .Y(add_subt_dataA[1]) );
INVX2TS U1151 ( .A(n1242), .Y(add_subt_dataA[0]) );
INVX2TS U1152 ( .A(n1244), .Y(add_subt_dataA[3]) );
AOI22X1TS U1153 ( .A0(n1395), .A1(d_ff3_sh_y_out[29]), .B0(n1241), .B1(
d_ff3_LUT_out[27]), .Y(n1245) );
OAI21XLTS U1154 ( .A0(n1246), .A1(n1442), .B0(n1245), .Y(add_subt_dataB[29])
);
AOI222X1TS U1155 ( .A0(n1396), .A1(d_ff3_sh_x_out[26]), .B0(n1215), .B1(
d_ff3_sh_y_out[26]), .C0(n1400), .C1(d_ff3_LUT_out[26]), .Y(n1247) );
INVX2TS U1156 ( .A(n1247), .Y(add_subt_dataB[26]) );
INVX2TS U1157 ( .A(n1249), .Y(add_subt_dataB[25]) );
AOI222X1TS U1158 ( .A0(n1378), .A1(d_ff3_sh_x_out[24]), .B0(n1216), .B1(
d_ff3_sh_y_out[24]), .C0(n1401), .C1(d_ff3_LUT_out[24]), .Y(n1250) );
INVX2TS U1159 ( .A(n1250), .Y(add_subt_dataB[24]) );
INVX2TS U1160 ( .A(n1251), .Y(add_subt_dataB[23]) );
CLKBUFX2TS U1161 ( .A(n1262), .Y(n1383) );
CLKBUFX3TS U1162 ( .A(n1260), .Y(n1402) );
AOI22X1TS U1163 ( .A0(n1402), .A1(d_ff3_sh_x_out[21]), .B0(n1395), .B1(
d_ff3_sh_y_out[21]), .Y(n1252) );
OAI21XLTS U1164 ( .A0(n1383), .A1(n1436), .B0(n1252), .Y(add_subt_dataB[21])
);
AOI22X1TS U1165 ( .A0(n1402), .A1(d_ff3_sh_x_out[20]), .B0(n1216), .B1(
d_ff3_sh_y_out[20]), .Y(n1254) );
AOI22X1TS U1166 ( .A0(n1260), .A1(d_ff3_sh_x_out[18]), .B0(n1395), .B1(
d_ff3_sh_y_out[18]), .Y(n1255) );
OAI21XLTS U1167 ( .A0(n1262), .A1(n1433), .B0(n1255), .Y(add_subt_dataB[18])
);
AOI22X1TS U1168 ( .A0(n1402), .A1(d_ff3_sh_x_out[17]), .B0(n1215), .B1(
d_ff3_sh_y_out[17]), .Y(n1256) );
OAI21XLTS U1169 ( .A0(n1383), .A1(n1432), .B0(n1256), .Y(add_subt_dataB[17])
);
AOI22X1TS U1170 ( .A0(n1260), .A1(d_ff3_sh_x_out[16]), .B0(n1253), .B1(
d_ff3_sh_y_out[16]), .Y(n1257) );
OAI21XLTS U1171 ( .A0(n1262), .A1(n1434), .B0(n1257), .Y(add_subt_dataB[16])
);
AOI22X1TS U1172 ( .A0(n1398), .A1(d_ff3_sh_x_out[15]), .B0(n1395), .B1(
d_ff3_sh_y_out[15]), .Y(n1258) );
OAI21XLTS U1173 ( .A0(n1383), .A1(n1432), .B0(n1258), .Y(add_subt_dataB[15])
);
AOI22X1TS U1174 ( .A0(n1398), .A1(d_ff3_sh_x_out[13]), .B0(n1216), .B1(
d_ff3_sh_y_out[13]), .Y(n1259) );
OAI21XLTS U1175 ( .A0(n1262), .A1(n1433), .B0(n1259), .Y(add_subt_dataB[13])
);
AOI22X1TS U1176 ( .A0(n1260), .A1(d_ff3_sh_x_out[12]), .B0(n1395), .B1(
d_ff3_sh_y_out[12]), .Y(n1261) );
OAI21XLTS U1177 ( .A0(n1262), .A1(n1435), .B0(n1261), .Y(add_subt_dataB[12])
);
AOI222X1TS U1178 ( .A0(n1260), .A1(d_ff3_sh_x_out[10]), .B0(n1404), .B1(
d_ff3_sh_y_out[10]), .C0(n1400), .C1(d_ff3_LUT_out[10]), .Y(n1263) );
INVX2TS U1179 ( .A(n1263), .Y(add_subt_dataB[10]) );
AOI22X1TS U1180 ( .A0(n1398), .A1(d_ff3_sh_x_out[9]), .B0(n1215), .B1(
d_ff3_sh_y_out[9]), .Y(n1264) );
AOI222X1TS U1181 ( .A0(n1378), .A1(d_ff3_sh_x_out[8]), .B0(n1215), .B1(
d_ff3_sh_y_out[8]), .C0(n1241), .C1(d_ff3_LUT_out[8]), .Y(n1265) );
INVX2TS U1182 ( .A(n1265), .Y(add_subt_dataB[8]) );
INVX2TS U1183 ( .A(n1266), .Y(add_subt_dataB[6]) );
AOI222X1TS U1184 ( .A0(n1396), .A1(d_ff3_sh_x_out[4]), .B0(n1404), .B1(
d_ff3_sh_y_out[4]), .C0(n1248), .C1(d_ff3_LUT_out[4]), .Y(n1267) );
INVX2TS U1185 ( .A(n1267), .Y(add_subt_dataB[4]) );
AOI22X1TS U1186 ( .A0(n1398), .A1(d_ff3_sh_x_out[3]), .B0(n1253), .B1(
d_ff3_sh_y_out[3]), .Y(n1268) );
OAI21XLTS U1187 ( .A0(n1383), .A1(n1434), .B0(n1268), .Y(add_subt_dataB[3])
);
AOI222X1TS U1188 ( .A0(n1378), .A1(d_ff3_sh_x_out[2]), .B0(n1215), .B1(
d_ff3_sh_y_out[2]), .C0(n1392), .C1(d_ff3_LUT_out[2]), .Y(n1269) );
INVX2TS U1189 ( .A(n1269), .Y(add_subt_dataB[2]) );
AOI222X1TS U1190 ( .A0(n1396), .A1(d_ff3_sh_x_out[1]), .B0(n1272), .B1(
d_ff3_sh_y_out[1]), .C0(n1271), .C1(d_ff3_LUT_out[1]), .Y(n1270) );
INVX2TS U1191 ( .A(n1270), .Y(add_subt_dataB[1]) );
AOI222X1TS U1192 ( .A0(n1273), .A1(d_ff3_sh_x_out[0]), .B0(n1272), .B1(
d_ff3_sh_y_out[0]), .C0(n1401), .C1(d_ff3_LUT_out[0]), .Y(n1274) );
INVX2TS U1193 ( .A(n1274), .Y(add_subt_dataB[0]) );
AO22XLTS U1194 ( .A0(d_ff2_Y[28]), .A1(n1374), .B0(n1057), .B1(d_ff_Yn[28]),
.Y(n716) );
INVX2TS U1195 ( .A(n1280), .Y(n1386) );
CLKBUFX3TS U1196 ( .A(n1295), .Y(n1286) );
AO22XLTS U1197 ( .A0(n1386), .A1(result_add_subt[19]), .B0(n1286), .B1(
d_ff_Zn[19]), .Y(n930) );
AO22XLTS U1198 ( .A0(n1386), .A1(result_add_subt[20]), .B0(n1286), .B1(
d_ff_Zn[20]), .Y(n929) );
CLKBUFX2TS U1199 ( .A(n1279), .Y(n1298) );
INVX2TS U1200 ( .A(n1298), .Y(n1363) );
CLKBUFX3TS U1201 ( .A(n1287), .Y(n1312) );
AO22XLTS U1202 ( .A0(n1363), .A1(d_ff2_Y[4]), .B0(n1312), .B1(
d_ff3_sh_y_out[4]), .Y(n758) );
AOI2BB2XLTS U1203 ( .B0(n1275), .B1(n1431), .A0N(n1431), .A1N(n1275), .Y(
n985) );
AO22XLTS U1204 ( .A0(n1306), .A1(d_ff1_shift_region_flag_out[1]), .B0(n1304),
.B1(shift_region_flag[1]), .Y(n982) );
INVX2TS U1205 ( .A(n1298), .Y(n1364) );
AO22XLTS U1206 ( .A0(n1364), .A1(d_ff2_Y[2]), .B0(n1312), .B1(
d_ff3_sh_y_out[2]), .Y(n762) );
AOI2BB2XLTS U1207 ( .B0(cont_iter_out[2]), .B1(n1406), .A0N(n1406), .A1N(
cont_iter_out[2]), .Y(n987) );
INVX2TS U1208 ( .A(n1295), .Y(n1296) );
AO22XLTS U1209 ( .A0(n1296), .A1(result_add_subt[18]), .B0(n1286), .B1(
d_ff_Zn[18]), .Y(n931) );
INVX2TS U1210 ( .A(n1300), .Y(n1343) );
AO22XLTS U1211 ( .A0(n1343), .A1(d_ff2_Y[6]), .B0(n1312), .B1(
d_ff3_sh_y_out[6]), .Y(n754) );
CLKBUFX3TS U1212 ( .A(n1295), .Y(n1278) );
AO22XLTS U1213 ( .A0(n1296), .A1(result_add_subt[15]), .B0(n1278), .B1(
d_ff_Zn[15]), .Y(n934) );
AO22XLTS U1214 ( .A0(n1343), .A1(d_ff2_Y[8]), .B0(n1279), .B1(
d_ff3_sh_y_out[8]), .Y(n750) );
AO22XLTS U1215 ( .A0(n1296), .A1(result_add_subt[16]), .B0(n1278), .B1(
d_ff_Zn[16]), .Y(n933) );
AO22XLTS U1216 ( .A0(n1296), .A1(result_add_subt[17]), .B0(n1286), .B1(
d_ff_Zn[17]), .Y(n932) );
AO22XLTS U1217 ( .A0(n1296), .A1(result_add_subt[14]), .B0(n1278), .B1(
d_ff_Zn[14]), .Y(n935) );
AO22XLTS U1218 ( .A0(n1343), .A1(d_ff2_Y[10]), .B0(n1298), .B1(
d_ff3_sh_y_out[10]), .Y(n746) );
INVX2TS U1219 ( .A(n1276), .Y(n1297) );
AO22XLTS U1220 ( .A0(n1297), .A1(result_add_subt[13]), .B0(n1278), .B1(
d_ff_Zn[13]), .Y(n936) );
AO22XLTS U1221 ( .A0(n1297), .A1(result_add_subt[12]), .B0(n1278), .B1(
d_ff_Zn[12]), .Y(n937) );
AO22XLTS U1222 ( .A0(n1296), .A1(result_add_subt[1]), .B0(n1280), .B1(
d_ff_Zn[1]), .Y(n948) );
AO22XLTS U1223 ( .A0(n1306), .A1(d_ff1_shift_region_flag_out[0]), .B0(n1303),
.B1(shift_region_flag[0]), .Y(n983) );
NOR2X1TS U1224 ( .A(d_ff2_Y[27]), .B(n1341), .Y(n1340) );
OR3X1TS U1225 ( .A(d_ff2_Y[27]), .B(d_ff2_Y[28]), .C(n1341), .Y(n1368) );
OAI21XLTS U1226 ( .A0(n1340), .A1(n1447), .B0(n1368), .Y(n1277) );
CLKBUFX3TS U1227 ( .A(n1279), .Y(n1344) );
AO22XLTS U1228 ( .A0(n1363), .A1(n1277), .B0(n1344), .B1(d_ff3_sh_y_out[28]),
.Y(n708) );
AO22XLTS U1229 ( .A0(n1297), .A1(result_add_subt[11]), .B0(n1278), .B1(
d_ff_Zn[11]), .Y(n938) );
AO22XLTS U1230 ( .A0(n1364), .A1(d_ff2_Y[3]), .B0(n1312), .B1(
d_ff3_sh_y_out[3]), .Y(n760) );
AO22XLTS U1231 ( .A0(n1296), .A1(result_add_subt[2]), .B0(n1280), .B1(
d_ff_Zn[2]), .Y(n947) );
AO22XLTS U1232 ( .A0(n1364), .A1(d_ff2_Y[5]), .B0(n1312), .B1(
d_ff3_sh_y_out[5]), .Y(n756) );
AO22XLTS U1233 ( .A0(n1297), .A1(result_add_subt[10]), .B0(n1278), .B1(
d_ff_Zn[10]), .Y(n939) );
AO22XLTS U1234 ( .A0(n1363), .A1(d_ff2_Y[7]), .B0(n1312), .B1(
d_ff3_sh_y_out[7]), .Y(n752) );
AO22XLTS U1235 ( .A0(n1364), .A1(d_ff2_Y[9]), .B0(n1300), .B1(
d_ff3_sh_y_out[9]), .Y(n748) );
CLKBUFX2TS U1236 ( .A(n1287), .Y(n1354) );
INVX2TS U1237 ( .A(n1354), .Y(n1366) );
AO22XLTS U1238 ( .A0(n1366), .A1(d_ff2_Y[11]), .B0(n1354), .B1(
d_ff3_sh_y_out[11]), .Y(n744) );
AO22XLTS U1239 ( .A0(n1297), .A1(result_add_subt[9]), .B0(n1278), .B1(
d_ff_Zn[9]), .Y(n940) );
AO22XLTS U1240 ( .A0(n1296), .A1(result_add_subt[3]), .B0(n1280), .B1(
d_ff_Zn[3]), .Y(n946) );
AO22XLTS U1241 ( .A0(n1343), .A1(d_ff2_Y[12]), .B0(n1279), .B1(
d_ff3_sh_y_out[12]), .Y(n742) );
AO22XLTS U1242 ( .A0(d_ff2_Y[23]), .A1(n1374), .B0(n1057), .B1(d_ff_Yn[23]),
.Y(n721) );
AO22XLTS U1243 ( .A0(n1363), .A1(d_ff2_Y[13]), .B0(n1300), .B1(
d_ff3_sh_y_out[13]), .Y(n740) );
AO22XLTS U1244 ( .A0(n1386), .A1(result_add_subt[8]), .B0(n1278), .B1(
d_ff_Zn[8]), .Y(n941) );
AO22XLTS U1245 ( .A0(n1414), .A1(d_ff2_Y[14]), .B0(n1298), .B1(
d_ff3_sh_y_out[14]), .Y(n738) );
AO22XLTS U1246 ( .A0(n1296), .A1(result_add_subt[4]), .B0(n1280), .B1(
d_ff_Zn[4]), .Y(n945) );
AO22XLTS U1247 ( .A0(n1414), .A1(d_ff2_Y[15]), .B0(n1354), .B1(
d_ff3_sh_y_out[15]), .Y(n736) );
INVX2TS U1248 ( .A(n1276), .Y(n1281) );
AO22XLTS U1249 ( .A0(n1281), .A1(result_add_subt[7]), .B0(n1278), .B1(
d_ff_Zn[7]), .Y(n942) );
AO22XLTS U1250 ( .A0(n1364), .A1(d_ff2_Y[16]), .B0(n1279), .B1(
d_ff3_sh_y_out[16]), .Y(n734) );
AO22XLTS U1251 ( .A0(n1306), .A1(d_ff1_operation_out), .B0(n1308), .B1(
operation), .Y(n984) );
AO22XLTS U1252 ( .A0(n1343), .A1(d_ff2_Y[17]), .B0(n1300), .B1(
d_ff3_sh_y_out[17]), .Y(n732) );
AO22XLTS U1253 ( .A0(n1281), .A1(result_add_subt[6]), .B0(n1280), .B1(
d_ff_Zn[6]), .Y(n943) );
AO22XLTS U1254 ( .A0(n1363), .A1(d_ff2_Y[18]), .B0(n1344), .B1(
d_ff3_sh_y_out[18]), .Y(n730) );
AO22XLTS U1255 ( .A0(n1281), .A1(result_add_subt[5]), .B0(n1280), .B1(
d_ff_Zn[5]), .Y(n944) );
AO22XLTS U1256 ( .A0(n1363), .A1(d_ff2_Y[1]), .B0(n1312), .B1(
d_ff3_sh_y_out[1]), .Y(n764) );
AO22XLTS U1257 ( .A0(n1386), .A1(result_add_subt[21]), .B0(n1286), .B1(
d_ff_Zn[21]), .Y(n928) );
AO22XLTS U1258 ( .A0(n1386), .A1(result_add_subt[22]), .B0(n1286), .B1(
d_ff_Zn[22]), .Y(n927) );
AO22XLTS U1259 ( .A0(n1364), .A1(d_ff2_Y[0]), .B0(n1312), .B1(
d_ff3_sh_y_out[0]), .Y(n766) );
AO22XLTS U1260 ( .A0(n1386), .A1(result_add_subt[23]), .B0(n1286), .B1(
d_ff_Zn[23]), .Y(n926) );
INVX2TS U1261 ( .A(n1354), .Y(n1369) );
CLKBUFX3TS U1262 ( .A(n1287), .Y(n1371) );
AO22XLTS U1263 ( .A0(n1369), .A1(d_ff2_X[10]), .B0(n1371), .B1(
d_ff3_sh_x_out[10]), .Y(n682) );
CMPR32X2TS U1264 ( .A(d_ff2_Y[26]), .B(n1439), .C(n1282), .CO(n1341), .S(
n1283) );
AO22XLTS U1265 ( .A0(n1364), .A1(n1283), .B0(n1344), .B1(d_ff3_sh_y_out[26]),
.Y(n710) );
CLKBUFX3TS U1266 ( .A(n1287), .Y(n1365) );
AO22XLTS U1267 ( .A0(n1369), .A1(d_ff2_X[8]), .B0(n1365), .B1(
d_ff3_sh_x_out[8]), .Y(n686) );
AO22XLTS U1268 ( .A0(n1386), .A1(result_add_subt[24]), .B0(n1286), .B1(
d_ff_Zn[24]), .Y(n925) );
AO22XLTS U1269 ( .A0(n1369), .A1(d_ff2_X[6]), .B0(n1365), .B1(
d_ff3_sh_x_out[6]), .Y(n690) );
INVX2TS U1270 ( .A(n1298), .Y(n1373) );
AO22XLTS U1271 ( .A0(n1373), .A1(d_ff2_X[4]), .B0(n1365), .B1(
d_ff3_sh_x_out[4]), .Y(n694) );
AO22XLTS U1272 ( .A0(n1297), .A1(result_add_subt[25]), .B0(n1286), .B1(
d_ff_Zn[25]), .Y(n924) );
AO22XLTS U1273 ( .A0(n1366), .A1(d_ff2_X[2]), .B0(n1365), .B1(
d_ff3_sh_x_out[2]), .Y(n698) );
CMPR32X2TS U1274 ( .A(d_ff2_Y[25]), .B(n1428), .C(n1284), .CO(n1282), .S(
n1285) );
AO22XLTS U1275 ( .A0(n1343), .A1(n1285), .B0(n1344), .B1(d_ff3_sh_y_out[25]),
.Y(n711) );
AO22XLTS U1276 ( .A0(n1366), .A1(d_ff2_X[1]), .B0(n1365), .B1(
d_ff3_sh_x_out[1]), .Y(n700) );
AO22XLTS U1277 ( .A0(n1373), .A1(d_ff2_X[0]), .B0(n1365), .B1(
d_ff3_sh_x_out[0]), .Y(n702) );
AO22XLTS U1278 ( .A0(n1297), .A1(result_add_subt[26]), .B0(n1286), .B1(
d_ff_Zn[26]), .Y(n923) );
NOR2X2TS U1279 ( .A(d_ff2_X[23]), .B(n1427), .Y(n1420) );
AOI222X1TS U1280 ( .A0(cont_iter_out[1]), .A1(n1420), .B0(cont_iter_out[1]),
.B1(n1441), .C0(n1420), .C1(n1441), .Y(n1291) );
CLKBUFX3TS U1281 ( .A(n1287), .Y(n1413) );
AO22XLTS U1282 ( .A0(n1363), .A1(n1288), .B0(n1413), .B1(d_ff3_sh_x_out[26]),
.Y(n646) );
CMPR32X2TS U1283 ( .A(d_ff2_Y[24]), .B(n1430), .C(n1289), .CO(n1284), .S(
n1290) );
AO22XLTS U1284 ( .A0(n1343), .A1(n1290), .B0(n1344), .B1(d_ff3_sh_y_out[24]),
.Y(n712) );
CMPR32X2TS U1285 ( .A(n1428), .B(d_ff2_X[25]), .C(n1291), .CO(n1299), .S(
n1292) );
AO22XLTS U1286 ( .A0(n1363), .A1(n1292), .B0(n1413), .B1(d_ff3_sh_x_out[25]),
.Y(n647) );
AO22XLTS U1287 ( .A0(n1297), .A1(result_add_subt[27]), .B0(n1295), .B1(
d_ff_Zn[27]), .Y(n922) );
XOR2X1TS U1288 ( .A(n1420), .B(d_ff2_X[24]), .Y(n1293) );
MXI2X1TS U1289 ( .A(n1347), .B(n1352), .S0(n1293), .Y(n1294) );
AO21XLTS U1290 ( .A0(d_ff3_sh_x_out[24]), .A1(n1312), .B0(n1294), .Y(n648)
);
INVX2TS U1291 ( .A(n1310), .Y(n1309) );
CLKBUFX2TS U1292 ( .A(n1308), .Y(n1305) );
AO22XLTS U1293 ( .A0(n1309), .A1(d_ff1_Z[31]), .B0(n1305), .B1(data_in[31]),
.Y(n950) );
AO22XLTS U1294 ( .A0(n1297), .A1(result_add_subt[28]), .B0(n1280), .B1(
d_ff_Zn[28]), .Y(n921) );
AO22XLTS U1295 ( .A0(n1309), .A1(d_ff1_Z[30]), .B0(n1305), .B1(data_in[30]),
.Y(n951) );
AO22XLTS U1296 ( .A0(n1296), .A1(result_add_subt[0]), .B0(n1295), .B1(
d_ff_Zn[0]), .Y(n949) );
AO22XLTS U1297 ( .A0(n1309), .A1(d_ff1_Z[29]), .B0(n1305), .B1(data_in[29]),
.Y(n952) );
AO22XLTS U1298 ( .A0(n1297), .A1(result_add_subt[29]), .B0(n1280), .B1(
d_ff_Zn[29]), .Y(n920) );
AO22XLTS U1299 ( .A0(n1309), .A1(d_ff1_Z[28]), .B0(n1305), .B1(data_in[28]),
.Y(n953) );
AO22XLTS U1300 ( .A0(n1309), .A1(d_ff1_Z[27]), .B0(n1305), .B1(data_in[27]),
.Y(n954) );
AO22XLTS U1301 ( .A0(n1373), .A1(n1428), .B0(n1298), .B1(d_ff3_LUT_out[8]),
.Y(n813) );
AO22XLTS U1302 ( .A0(n1309), .A1(d_ff1_Z[26]), .B0(n1305), .B1(data_in[26]),
.Y(n955) );
AO22XLTS U1303 ( .A0(n1386), .A1(result_add_subt[30]), .B0(n1276), .B1(
d_ff_Zn[30]), .Y(n919) );
INVX2TS U1304 ( .A(n1308), .Y(n1302) );
AO22XLTS U1305 ( .A0(n1302), .A1(d_ff1_Z[25]), .B0(n1304), .B1(data_in[25]),
.Y(n956) );
CLKBUFX3TS U1306 ( .A(n1308), .Y(n1303) );
AO22XLTS U1307 ( .A0(n1302), .A1(d_ff1_Z[24]), .B0(n1304), .B1(data_in[24]),
.Y(n957) );
AO22XLTS U1308 ( .A0(n1386), .A1(result_add_subt[31]), .B0(n1295), .B1(
d_ff_Zn[31]), .Y(n918) );
AO22XLTS U1309 ( .A0(n1302), .A1(d_ff1_Z[23]), .B0(n1303), .B1(data_in[23]),
.Y(n958) );
AO22XLTS U1310 ( .A0(n1302), .A1(d_ff1_Z[22]), .B0(n1304), .B1(data_in[22]),
.Y(n959) );
AO22XLTS U1311 ( .A0(n1306), .A1(d_ff1_Z[0]), .B0(n1304), .B1(data_in[0]),
.Y(n981) );
AO22XLTS U1312 ( .A0(n1302), .A1(d_ff1_Z[21]), .B0(n1303), .B1(data_in[21]),
.Y(n960) );
AO22XLTS U1313 ( .A0(n1302), .A1(d_ff1_Z[20]), .B0(n1304), .B1(data_in[20]),
.Y(n961) );
CMPR32X2TS U1314 ( .A(n1439), .B(d_ff2_X[26]), .C(n1299), .CO(n1353), .S(
n1288) );
OR3X1TS U1315 ( .A(n1353), .B(d_ff2_X[27]), .C(d_ff2_X[28]), .Y(n1423) );
NOR2X1TS U1316 ( .A(d_ff2_X[29]), .B(n1423), .Y(n1422) );
XOR2XLTS U1317 ( .A(d_ff2_X[30]), .B(n1422), .Y(n1301) );
AO22XLTS U1318 ( .A0(n1373), .A1(n1301), .B0(n1300), .B1(d_ff3_sh_x_out[30]),
.Y(n642) );
AO22XLTS U1319 ( .A0(n1306), .A1(d_ff1_Z[1]), .B0(n1303), .B1(data_in[1]),
.Y(n980) );
AO22XLTS U1320 ( .A0(n1302), .A1(d_ff1_Z[19]), .B0(n1303), .B1(data_in[19]),
.Y(n962) );
AO22XLTS U1321 ( .A0(n1302), .A1(d_ff1_Z[18]), .B0(n1304), .B1(data_in[18]),
.Y(n963) );
AO22XLTS U1322 ( .A0(n1302), .A1(d_ff1_Z[17]), .B0(n1303), .B1(data_in[17]),
.Y(n964) );
AO22XLTS U1323 ( .A0(n1306), .A1(d_ff1_Z[2]), .B0(n1304), .B1(data_in[2]),
.Y(n979) );
AO22XLTS U1324 ( .A0(n1366), .A1(d_ff2_X[31]), .B0(n1365), .B1(
d_ff3_sh_x_out[31]), .Y(n640) );
AO22XLTS U1325 ( .A0(n1302), .A1(d_ff1_Z[16]), .B0(n1304), .B1(data_in[16]),
.Y(n965) );
AO22XLTS U1326 ( .A0(n1311), .A1(d_ff1_Z[15]), .B0(n1303), .B1(data_in[15]),
.Y(n966) );
AO22XLTS U1327 ( .A0(n1306), .A1(d_ff1_Z[3]), .B0(n1303), .B1(data_in[3]),
.Y(n978) );
AO22XLTS U1328 ( .A0(n1311), .A1(d_ff1_Z[14]), .B0(n1310), .B1(data_in[14]),
.Y(n967) );
AO22XLTS U1329 ( .A0(n1366), .A1(d_ff2_Y[31]), .B0(n1365), .B1(
d_ff3_sh_y_out[31]), .Y(n704) );
AO22XLTS U1330 ( .A0(n1311), .A1(d_ff1_Z[13]), .B0(n1310), .B1(data_in[13]),
.Y(n968) );
AO22XLTS U1331 ( .A0(n1306), .A1(d_ff1_Z[4]), .B0(n1304), .B1(data_in[4]),
.Y(n977) );
AO22XLTS U1332 ( .A0(n1311), .A1(d_ff1_Z[12]), .B0(n1310), .B1(data_in[12]),
.Y(n969) );
AO22XLTS U1333 ( .A0(n1311), .A1(d_ff1_Z[11]), .B0(n1308), .B1(data_in[11]),
.Y(n970) );
AO22XLTS U1334 ( .A0(n1306), .A1(d_ff1_Z[5]), .B0(n1303), .B1(data_in[5]),
.Y(n976) );
AO22XLTS U1335 ( .A0(n1309), .A1(d_ff1_Z[10]), .B0(n1310), .B1(data_in[10]),
.Y(n971) );
NOR2X1TS U1336 ( .A(d_ff2_Y[29]), .B(n1368), .Y(n1367) );
XOR2XLTS U1337 ( .A(d_ff2_Y[30]), .B(n1367), .Y(n1307) );
AO22XLTS U1338 ( .A0(n1366), .A1(n1307), .B0(n1344), .B1(d_ff3_sh_y_out[30]),
.Y(n706) );
AO22XLTS U1339 ( .A0(n1311), .A1(d_ff1_Z[9]), .B0(n1308), .B1(data_in[9]),
.Y(n972) );
AO22XLTS U1340 ( .A0(n1309), .A1(d_ff1_Z[8]), .B0(n1310), .B1(data_in[8]),
.Y(n973) );
AO22XLTS U1341 ( .A0(n1309), .A1(d_ff1_Z[6]), .B0(n1310), .B1(data_in[6]),
.Y(n975) );
AO22XLTS U1342 ( .A0(n1311), .A1(d_ff1_Z[7]), .B0(n1310), .B1(data_in[7]),
.Y(n974) );
INVX2TS U1343 ( .A(n1326), .Y(n1339) );
CLKBUFX3TS U1344 ( .A(n1321), .Y(n1338) );
AO22XLTS U1345 ( .A0(n1339), .A1(result_add_subt[25]), .B0(n1338), .B1(
d_ff_Xn[25]), .Y(n860) );
AO22XLTS U1346 ( .A0(n1343), .A1(n1313), .B0(n1312), .B1(d_ff3_LUT_out[19]),
.Y(n807) );
INVX2TS U1347 ( .A(n1326), .Y(n1318) );
AO22XLTS U1348 ( .A0(n1318), .A1(result_add_subt[19]), .B0(n1338), .B1(
d_ff_Xn[19]), .Y(n866) );
AO22XLTS U1349 ( .A0(n1314), .A1(result_add_subt[30]), .B0(n1321), .B1(
d_ff_Xn[30]), .Y(n855) );
CLKBUFX3TS U1350 ( .A(n1321), .Y(n1317) );
AO22XLTS U1351 ( .A0(n1318), .A1(result_add_subt[17]), .B0(n1317), .B1(
d_ff_Xn[17]), .Y(n868) );
NAND2X1TS U1352 ( .A(n1315), .B(ready_add_subt), .Y(n1316) );
INVX2TS U1353 ( .A(n1316), .Y(n1325) );
CLKBUFX2TS U1354 ( .A(n1316), .Y(n1345) );
CLKBUFX3TS U1355 ( .A(n1345), .Y(n1324) );
AO22XLTS U1356 ( .A0(n1325), .A1(result_add_subt[23]), .B0(n1324), .B1(
d_ff_Yn[23]), .Y(n894) );
AO22XLTS U1357 ( .A0(n1325), .A1(result_add_subt[28]), .B0(n1345), .B1(
d_ff_Yn[28]), .Y(n889) );
AO22XLTS U1358 ( .A0(n1318), .A1(result_add_subt[16]), .B0(n1317), .B1(
d_ff_Xn[16]), .Y(n869) );
INVX2TS U1359 ( .A(n1319), .Y(n1327) );
AO22XLTS U1360 ( .A0(n1327), .A1(result_add_subt[4]), .B0(n1319), .B1(
d_ff_Xn[4]), .Y(n881) );
AO22XLTS U1361 ( .A0(n1318), .A1(result_add_subt[14]), .B0(n1317), .B1(
d_ff_Xn[14]), .Y(n871) );
AO22XLTS U1362 ( .A0(n1327), .A1(result_add_subt[8]), .B0(n1317), .B1(
d_ff_Xn[8]), .Y(n877) );
AO22XLTS U1363 ( .A0(n1327), .A1(result_add_subt[9]), .B0(n1317), .B1(
d_ff_Xn[9]), .Y(n876) );
AO22XLTS U1364 ( .A0(n1318), .A1(result_add_subt[13]), .B0(n1317), .B1(
d_ff_Xn[13]), .Y(n872) );
AO22XLTS U1365 ( .A0(n1318), .A1(result_add_subt[11]), .B0(n1317), .B1(
d_ff_Xn[11]), .Y(n874) );
AO22XLTS U1366 ( .A0(n1318), .A1(result_add_subt[12]), .B0(n1317), .B1(
d_ff_Xn[12]), .Y(n873) );
AO22XLTS U1367 ( .A0(n1318), .A1(result_add_subt[15]), .B0(n1317), .B1(
d_ff_Xn[15]), .Y(n870) );
AO22XLTS U1368 ( .A0(n1318), .A1(result_add_subt[18]), .B0(n1338), .B1(
d_ff_Xn[18]), .Y(n867) );
AO22XLTS U1369 ( .A0(n1318), .A1(result_add_subt[10]), .B0(n1317), .B1(
d_ff_Xn[10]), .Y(n875) );
AO22XLTS U1370 ( .A0(n1339), .A1(result_add_subt[21]), .B0(n1338), .B1(
d_ff_Xn[21]), .Y(n864) );
AO22XLTS U1371 ( .A0(n1327), .A1(result_add_subt[7]), .B0(n1319), .B1(
d_ff_Xn[7]), .Y(n878) );
AO22XLTS U1372 ( .A0(n1339), .A1(result_add_subt[22]), .B0(n1338), .B1(
d_ff_Xn[22]), .Y(n863) );
AO22XLTS U1373 ( .A0(n1339), .A1(result_add_subt[23]), .B0(n1338), .B1(
d_ff_Xn[23]), .Y(n862) );
AO22XLTS U1374 ( .A0(n1327), .A1(result_add_subt[6]), .B0(n1319), .B1(
d_ff_Xn[6]), .Y(n879) );
INVX2TS U1375 ( .A(n1320), .Y(n1331) );
AO22XLTS U1376 ( .A0(n1331), .A1(result_add_subt[1]), .B0(n1320), .B1(
d_ff_Yn[1]), .Y(n916) );
AO22XLTS U1377 ( .A0(n1327), .A1(result_add_subt[5]), .B0(n1319), .B1(
d_ff_Xn[5]), .Y(n880) );
AO22XLTS U1378 ( .A0(n1331), .A1(result_add_subt[2]), .B0(n1320), .B1(
d_ff_Yn[2]), .Y(n915) );
AO22XLTS U1379 ( .A0(n1331), .A1(result_add_subt[3]), .B0(n1320), .B1(
d_ff_Yn[3]), .Y(n914) );
AO22XLTS U1380 ( .A0(n1327), .A1(result_add_subt[3]), .B0(n1319), .B1(
d_ff_Xn[3]), .Y(n882) );
AO22XLTS U1381 ( .A0(n1331), .A1(result_add_subt[4]), .B0(n1320), .B1(
d_ff_Yn[4]), .Y(n913) );
AO22XLTS U1382 ( .A0(n1327), .A1(result_add_subt[2]), .B0(n1319), .B1(
d_ff_Xn[2]), .Y(n883) );
AO22XLTS U1383 ( .A0(n1331), .A1(result_add_subt[5]), .B0(n1320), .B1(
d_ff_Yn[5]), .Y(n912) );
AO22XLTS U1384 ( .A0(n1331), .A1(result_add_subt[6]), .B0(n1320), .B1(
d_ff_Yn[6]), .Y(n911) );
AO22XLTS U1385 ( .A0(n1327), .A1(result_add_subt[1]), .B0(n1319), .B1(
d_ff_Xn[1]), .Y(n884) );
AO22XLTS U1386 ( .A0(n1331), .A1(result_add_subt[7]), .B0(n1320), .B1(
d_ff_Yn[7]), .Y(n910) );
AO22XLTS U1387 ( .A0(n1339), .A1(result_add_subt[29]), .B0(n1321), .B1(
d_ff_Xn[29]), .Y(n856) );
CLKBUFX3TS U1388 ( .A(n1345), .Y(n1322) );
AO22XLTS U1389 ( .A0(n1331), .A1(result_add_subt[8]), .B0(n1322), .B1(
d_ff_Yn[8]), .Y(n909) );
AO22XLTS U1390 ( .A0(n1331), .A1(result_add_subt[9]), .B0(n1322), .B1(
d_ff_Yn[9]), .Y(n908) );
AO22XLTS U1391 ( .A0(n1339), .A1(result_add_subt[28]), .B0(n1321), .B1(
d_ff_Xn[28]), .Y(n857) );
INVX2TS U1392 ( .A(n1316), .Y(n1323) );
AO22XLTS U1393 ( .A0(n1323), .A1(result_add_subt[10]), .B0(n1322), .B1(
d_ff_Yn[10]), .Y(n907) );
AO22XLTS U1394 ( .A0(n1339), .A1(result_add_subt[27]), .B0(n1338), .B1(
d_ff_Xn[27]), .Y(n858) );
AO22XLTS U1395 ( .A0(n1323), .A1(result_add_subt[11]), .B0(n1322), .B1(
d_ff_Yn[11]), .Y(n906) );
AO22XLTS U1396 ( .A0(n1323), .A1(result_add_subt[12]), .B0(n1322), .B1(
d_ff_Yn[12]), .Y(n905) );
AO22XLTS U1397 ( .A0(n1339), .A1(result_add_subt[24]), .B0(n1338), .B1(
d_ff_Xn[24]), .Y(n861) );
AO22XLTS U1398 ( .A0(n1323), .A1(result_add_subt[13]), .B0(n1322), .B1(
d_ff_Yn[13]), .Y(n904) );
CLKBUFX3TS U1399 ( .A(n1328), .Y(n1377) );
INVX2TS U1400 ( .A(n1416), .Y(n1372) );
AO22XLTS U1401 ( .A0(n1377), .A1(d_ff_Yn[31]), .B0(d_ff2_Y[31]), .B1(n1372),
.Y(n705) );
AO22XLTS U1402 ( .A0(n1323), .A1(result_add_subt[14]), .B0(n1322), .B1(
d_ff_Yn[14]), .Y(n903) );
AO22XLTS U1403 ( .A0(n1323), .A1(result_add_subt[15]), .B0(n1322), .B1(
d_ff_Yn[15]), .Y(n902) );
CLKBUFX3TS U1404 ( .A(n1328), .Y(n1330) );
INVX2TS U1405 ( .A(n1448), .Y(n1376) );
AO22XLTS U1406 ( .A0(n1330), .A1(d_ff_Yn[22]), .B0(d_ff2_Y[22]), .B1(n1376),
.Y(n723) );
AO22XLTS U1407 ( .A0(n1323), .A1(result_add_subt[16]), .B0(n1322), .B1(
d_ff_Yn[16]), .Y(n901) );
AO22XLTS U1408 ( .A0(n1330), .A1(d_ff_Yn[21]), .B0(d_ff2_Y[21]), .B1(n1376),
.Y(n725) );
AO22XLTS U1409 ( .A0(n1323), .A1(result_add_subt[17]), .B0(n1322), .B1(
d_ff_Yn[17]), .Y(n900) );
AO22XLTS U1410 ( .A0(n1323), .A1(result_add_subt[18]), .B0(n1324), .B1(
d_ff_Yn[18]), .Y(n899) );
AO22XLTS U1411 ( .A0(n1330), .A1(d_ff_Yn[20]), .B0(d_ff2_Y[20]), .B1(n1376),
.Y(n727) );
AO22XLTS U1412 ( .A0(n1323), .A1(result_add_subt[19]), .B0(n1324), .B1(
d_ff_Yn[19]), .Y(n898) );
AO22XLTS U1413 ( .A0(n1330), .A1(d_ff_Yn[19]), .B0(d_ff2_Y[19]), .B1(n1376),
.Y(n729) );
AO22XLTS U1414 ( .A0(n1325), .A1(result_add_subt[20]), .B0(n1324), .B1(
d_ff_Yn[20]), .Y(n897) );
AO22XLTS U1415 ( .A0(n1325), .A1(result_add_subt[21]), .B0(n1324), .B1(
d_ff_Yn[21]), .Y(n896) );
AO22XLTS U1416 ( .A0(n1330), .A1(d_ff_Yn[18]), .B0(d_ff2_Y[18]), .B1(n1376),
.Y(n731) );
AO22XLTS U1417 ( .A0(n1325), .A1(result_add_subt[22]), .B0(n1324), .B1(
d_ff_Yn[22]), .Y(n895) );
INVX2TS U1418 ( .A(n1417), .Y(n1329) );
AO22XLTS U1419 ( .A0(n1330), .A1(d_ff_Yn[17]), .B0(d_ff2_Y[17]), .B1(n1329),
.Y(n733) );
AO22XLTS U1420 ( .A0(n1325), .A1(result_add_subt[24]), .B0(n1324), .B1(
d_ff_Yn[24]), .Y(n893) );
AO22XLTS U1421 ( .A0(n1325), .A1(result_add_subt[25]), .B0(n1324), .B1(
d_ff_Yn[25]), .Y(n892) );
AO22XLTS U1422 ( .A0(n1330), .A1(d_ff_Yn[16]), .B0(d_ff2_Y[16]), .B1(n1329),
.Y(n735) );
AO22XLTS U1423 ( .A0(n1325), .A1(result_add_subt[26]), .B0(n1324), .B1(
d_ff_Yn[26]), .Y(n891) );
AO22XLTS U1424 ( .A0(n1330), .A1(d_ff_Yn[15]), .B0(d_ff2_Y[15]), .B1(n1329),
.Y(n737) );
AO22XLTS U1425 ( .A0(n1325), .A1(result_add_subt[27]), .B0(n1324), .B1(
d_ff_Yn[27]), .Y(n890) );
AO22XLTS U1426 ( .A0(n1325), .A1(result_add_subt[29]), .B0(n1345), .B1(
d_ff_Yn[29]), .Y(n888) );
AO22XLTS U1427 ( .A0(n1328), .A1(d_ff_Yn[14]), .B0(d_ff2_Y[14]), .B1(n1329),
.Y(n739) );
INVX2TS U1428 ( .A(n1320), .Y(n1346) );
AO22XLTS U1429 ( .A0(n1346), .A1(result_add_subt[30]), .B0(n1345), .B1(
d_ff_Yn[30]), .Y(n887) );
AO22XLTS U1430 ( .A0(n1337), .A1(d_ff_Yn[13]), .B0(d_ff2_Y[13]), .B1(n1329),
.Y(n741) );
AO22XLTS U1431 ( .A0(n1327), .A1(result_add_subt[0]), .B0(n1326), .B1(
d_ff_Xn[0]), .Y(n885) );
AO22XLTS U1432 ( .A0(n1377), .A1(d_ff_Xn[0]), .B0(d_ff2_X[0]), .B1(n1372),
.Y(n703) );
AO22XLTS U1433 ( .A0(n1328), .A1(d_ff_Yn[12]), .B0(d_ff2_Y[12]), .B1(n1329),
.Y(n743) );
AO22XLTS U1434 ( .A0(n1377), .A1(d_ff_Xn[4]), .B0(d_ff2_X[4]), .B1(n1372),
.Y(n695) );
AO22XLTS U1435 ( .A0(n1328), .A1(d_ff_Yn[11]), .B0(d_ff2_Y[11]), .B1(n1329),
.Y(n745) );
AO22XLTS U1436 ( .A0(n1377), .A1(d_ff_Xn[8]), .B0(d_ff2_X[8]), .B1(n1372),
.Y(n687) );
AO22XLTS U1437 ( .A0(n1375), .A1(d_ff_Xn[9]), .B0(d_ff2_X[9]), .B1(n1372),
.Y(n685) );
AO22XLTS U1438 ( .A0(n1330), .A1(d_ff_Yn[10]), .B0(d_ff2_Y[10]), .B1(n1329),
.Y(n747) );
AO22XLTS U1439 ( .A0(n1375), .A1(d_ff_Xn[11]), .B0(d_ff2_X[11]), .B1(n1372),
.Y(n681) );
AO22XLTS U1440 ( .A0(n1328), .A1(d_ff_Yn[9]), .B0(d_ff2_Y[9]), .B1(n1329),
.Y(n749) );
AO22XLTS U1441 ( .A0(n1375), .A1(d_ff_Xn[15]), .B0(d_ff2_X[15]), .B1(n1372),
.Y(n673) );
AO22XLTS U1442 ( .A0(n1375), .A1(d_ff_Xn[18]), .B0(d_ff2_X[18]), .B1(n1372),
.Y(n667) );
AO22XLTS U1443 ( .A0(n1057), .A1(d_ff_Yn[8]), .B0(d_ff2_Y[8]), .B1(n1329),
.Y(n751) );
AO22XLTS U1444 ( .A0(n1375), .A1(d_ff_Xn[21]), .B0(d_ff2_X[21]), .B1(n1374),
.Y(n661) );
INVX2TS U1445 ( .A(n1448), .Y(n1336) );
AO22XLTS U1446 ( .A0(n1328), .A1(d_ff_Yn[7]), .B0(d_ff2_Y[7]), .B1(n1336),
.Y(n753) );
AO22XLTS U1447 ( .A0(n1375), .A1(d_ff_Xn[22]), .B0(d_ff2_X[22]), .B1(n1374),
.Y(n659) );
AO22XLTS U1448 ( .A0(n1330), .A1(d_ff_Xn[31]), .B0(d_ff2_X[31]), .B1(n1376),
.Y(n641) );
AO22XLTS U1449 ( .A0(n1337), .A1(d_ff_Yn[6]), .B0(d_ff2_Y[6]), .B1(n1336),
.Y(n755) );
AO22XLTS U1450 ( .A0(n1331), .A1(result_add_subt[0]), .B0(n1316), .B1(
d_ff_Yn[0]), .Y(n917) );
AO22XLTS U1451 ( .A0(n1337), .A1(d_ff_Yn[5]), .B0(d_ff2_Y[5]), .B1(n1336),
.Y(n757) );
AO22XLTS U1452 ( .A0(n1354), .A1(d_ff3_sign_out), .B0(n1369), .B1(
d_ff2_Z[31]), .Y(n768) );
AOI22X1TS U1453 ( .A0(n1332), .A1(n1359), .B0(d_ff3_LUT_out[5]), .B1(n1410),
.Y(n1333) );
NAND2X1TS U1454 ( .A(n1333), .B(n1408), .Y(n816) );
AO22XLTS U1455 ( .A0(n1057), .A1(d_ff_Yn[4]), .B0(d_ff2_Y[4]), .B1(n1336),
.Y(n759) );
AOI22X1TS U1456 ( .A0(n1426), .A1(n1334), .B0(d_ff3_LUT_out[7]), .B1(n1410),
.Y(n1335) );
NAND2X1TS U1457 ( .A(n1335), .B(n1411), .Y(n814) );
AO22XLTS U1458 ( .A0(n1057), .A1(d_ff_Yn[3]), .B0(d_ff2_Y[3]), .B1(n1336),
.Y(n761) );
AO22XLTS U1459 ( .A0(n1057), .A1(d_ff_Yn[2]), .B0(d_ff2_Y[2]), .B1(n1336),
.Y(n763) );
AO22XLTS U1460 ( .A0(n1337), .A1(d_ff_Yn[1]), .B0(d_ff2_Y[1]), .B1(n1336),
.Y(n765) );
AO22XLTS U1461 ( .A0(n1375), .A1(d_ff_Yn[0]), .B0(d_ff2_Y[0]), .B1(n1374),
.Y(n767) );
AO22XLTS U1462 ( .A0(n1339), .A1(result_add_subt[20]), .B0(n1338), .B1(
d_ff_Xn[20]), .Y(n865) );
AO22XLTS U1463 ( .A0(n1364), .A1(d_ff2_Y[19]), .B0(n1344), .B1(
d_ff3_sh_y_out[19]), .Y(n728) );
AO22XLTS U1464 ( .A0(n1339), .A1(result_add_subt[26]), .B0(n1338), .B1(
d_ff_Xn[26]), .Y(n859) );
AOI21X1TS U1465 ( .A0(n1341), .A1(d_ff2_Y[27]), .B0(n1340), .Y(n1342) );
AOI2BB2XLTS U1466 ( .B0(n1426), .B1(n1342), .A0N(d_ff3_sh_y_out[27]), .A1N(
n1369), .Y(n709) );
AO22XLTS U1467 ( .A0(n1373), .A1(d_ff2_X[19]), .B0(n1413), .B1(
d_ff3_sh_x_out[19]), .Y(n664) );
AO22XLTS U1468 ( .A0(n1373), .A1(d_ff2_X[16]), .B0(n1371), .B1(
d_ff3_sh_x_out[16]), .Y(n670) );
AO22XLTS U1469 ( .A0(n1343), .A1(d_ff2_Y[20]), .B0(n1344), .B1(
d_ff3_sh_y_out[20]), .Y(n726) );
AO22XLTS U1470 ( .A0(n1343), .A1(d_ff2_Y[22]), .B0(n1344), .B1(
d_ff3_sh_y_out[22]), .Y(n722) );
AO22XLTS U1471 ( .A0(d_ff2_X[30]), .A1(n1374), .B0(n1328), .B1(d_ff_Xn[30]),
.Y(n650) );
AO22XLTS U1472 ( .A0(n1369), .A1(d_ff2_X[14]), .B0(n1371), .B1(
d_ff3_sh_x_out[14]), .Y(n674) );
AO22XLTS U1473 ( .A0(n1377), .A1(d_ff_Yn[27]), .B0(d_ff2_Y[27]), .B1(n1376),
.Y(n717) );
AO22XLTS U1474 ( .A0(n1377), .A1(d_ff_Yn[24]), .B0(d_ff2_Y[24]), .B1(n1376),
.Y(n720) );
AO22XLTS U1475 ( .A0(n1364), .A1(d_ff2_Y[21]), .B0(n1344), .B1(
d_ff3_sh_y_out[21]), .Y(n724) );
AO22XLTS U1476 ( .A0(n1346), .A1(result_add_subt[31]), .B0(n1345), .B1(
d_ff_Yn[31]), .Y(n886) );
NOR2XLTS U1477 ( .A(n1059), .B(n1347), .Y(n1348) );
AOI22X1TS U1478 ( .A0(n1349), .A1(n1348), .B0(d_ff3_LUT_out[25]), .B1(n1424),
.Y(n1351) );
AOI32X1TS U1479 ( .A0(n1352), .A1(n1351), .A2(n1350), .B0(cont_iter_out[2]),
.B1(n1351), .Y(n803) );
AO22XLTS U1480 ( .A0(n1366), .A1(d_ff2_X[17]), .B0(n1413), .B1(
d_ff3_sh_x_out[17]), .Y(n668) );
NAND2BXLTS U1481 ( .AN(d_ff3_LUT_out[27]), .B(n1424), .Y(n801) );
AO22XLTS U1482 ( .A0(n1366), .A1(d_ff2_X[13]), .B0(n1371), .B1(
d_ff3_sh_x_out[13]), .Y(n676) );
AO22XLTS U1483 ( .A0(n1369), .A1(d_ff2_X[9]), .B0(n1371), .B1(
d_ff3_sh_x_out[9]), .Y(n684) );
AO22XLTS U1484 ( .A0(n1369), .A1(d_ff2_X[11]), .B0(n1371), .B1(
d_ff3_sh_x_out[11]), .Y(n680) );
AO22XLTS U1485 ( .A0(n1373), .A1(d_ff2_X[18]), .B0(n1371), .B1(
d_ff3_sh_x_out[18]), .Y(n666) );
NOR2X1TS U1486 ( .A(d_ff2_X[27]), .B(n1353), .Y(n1356) );
AOI21X1TS U1487 ( .A0(n1353), .A1(d_ff2_X[27]), .B0(n1356), .Y(n1355) );
INVX2TS U1488 ( .A(n1354), .Y(n1421) );
AOI2BB2XLTS U1489 ( .B0(n1414), .B1(n1355), .A0N(d_ff3_sh_x_out[27]), .A1N(
n1421), .Y(n645) );
OAI21XLTS U1490 ( .A0(n1356), .A1(n1444), .B0(n1423), .Y(n1357) );
AO22XLTS U1491 ( .A0(n1363), .A1(n1357), .B0(n1413), .B1(d_ff3_sh_x_out[28]),
.Y(n644) );
AO22XLTS U1492 ( .A0(n1377), .A1(d_ff_Yn[29]), .B0(d_ff2_Y[29]), .B1(n1372),
.Y(n715) );
AO21XLTS U1493 ( .A0(enab_cont_iter), .A1(n1387), .B0(n1064), .Y(
inst_CORDIC_FSM_v3_state_next[2]) );
AO22XLTS U1494 ( .A0(n1377), .A1(d_ff_Yn[25]), .B0(d_ff2_Y[25]), .B1(n1376),
.Y(n719) );
AOI22X1TS U1495 ( .A0(n1360), .A1(n1359), .B0(d_ff3_LUT_out[10]), .B1(n1424),
.Y(n1361) );
NAND2BXLTS U1496 ( .AN(n1362), .B(n1361), .Y(n811) );
AO22XLTS U1497 ( .A0(n1366), .A1(d_ff2_X[12]), .B0(n1371), .B1(
d_ff3_sh_x_out[12]), .Y(n678) );
AO22XLTS U1498 ( .A0(n1363), .A1(d_ff2_X[22]), .B0(n1413), .B1(
d_ff3_sh_x_out[22]), .Y(n658) );
AO22XLTS U1499 ( .A0(n1364), .A1(d_ff2_X[5]), .B0(n1365), .B1(
d_ff3_sh_x_out[5]), .Y(n692) );
AO22XLTS U1500 ( .A0(n1366), .A1(d_ff2_X[3]), .B0(n1365), .B1(
d_ff3_sh_x_out[3]), .Y(n696) );
AO22XLTS U1501 ( .A0(n1373), .A1(d_ff2_X[20]), .B0(n1413), .B1(
d_ff3_sh_x_out[20]), .Y(n662) );
AO22XLTS U1502 ( .A0(n1369), .A1(d_ff2_X[7]), .B0(n1371), .B1(
d_ff3_sh_x_out[7]), .Y(n688) );
AOI21X1TS U1503 ( .A0(d_ff2_Y[29]), .A1(n1368), .B0(n1367), .Y(n1370) );
AOI2BB2XLTS U1504 ( .B0(n1426), .B1(n1370), .A0N(d_ff3_sh_y_out[29]), .A1N(
n1369), .Y(n707) );
AO22XLTS U1505 ( .A0(n1373), .A1(d_ff2_X[15]), .B0(n1371), .B1(
d_ff3_sh_x_out[15]), .Y(n672) );
AO22XLTS U1506 ( .A0(n1377), .A1(d_ff_Yn[30]), .B0(d_ff2_Y[30]), .B1(n1372),
.Y(n714) );
AO22XLTS U1507 ( .A0(n1373), .A1(d_ff2_X[21]), .B0(n1413), .B1(
d_ff3_sh_x_out[21]), .Y(n660) );
AO22XLTS U1508 ( .A0(n1375), .A1(d_ff_Xn[23]), .B0(d_ff2_X[23]), .B1(n1374),
.Y(n657) );
AO22XLTS U1509 ( .A0(n1377), .A1(d_ff_Yn[26]), .B0(d_ff2_Y[26]), .B1(n1376),
.Y(n718) );
AO22XLTS U1510 ( .A0(n1378), .A1(d_ff3_sh_x_out[31]), .B0(n1404), .B1(
d_ff3_sh_y_out[31]), .Y(add_subt_dataB[31]) );
AO22XLTS U1511 ( .A0(n1398), .A1(d_ff3_sh_x_out[30]), .B0(n1404), .B1(
d_ff3_sh_y_out[30]), .Y(add_subt_dataB[30]) );
AOI22X1TS U1512 ( .A0(n1402), .A1(d_ff3_sh_x_out[28]), .B0(n1395), .B1(
d_ff3_sh_y_out[28]), .Y(n1379) );
NAND2X1TS U1513 ( .A(n1248), .B(d_ff3_LUT_out[27]), .Y(n1380) );
NAND2X1TS U1514 ( .A(n1379), .B(n1380), .Y(add_subt_dataB[28]) );
AOI22X1TS U1515 ( .A0(n1402), .A1(d_ff3_sh_x_out[27]), .B0(n1395), .B1(
d_ff3_sh_y_out[27]), .Y(n1381) );
NAND2X1TS U1516 ( .A(n1381), .B(n1380), .Y(add_subt_dataB[27]) );
AOI2BB2XLTS U1517 ( .B0(cont_var_out[0]), .B1(d_ff3_sign_out), .A0N(
d_ff3_sign_out), .A1N(cont_var_out[0]), .Y(op_add_subt) );
NOR2BX1TS U1518 ( .AN(beg_fsm_cordic), .B(n1382), .Y(
inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U1519 ( .A0(n1386), .A1(n1385), .B0(n1384), .B1(n1383), .Y(
inst_CORDIC_FSM_v3_state_next[5]) );
OAI22X1TS U1520 ( .A0(ack_cordic), .A1(n1388), .B0(n1405), .B1(n1387), .Y(
inst_CORDIC_FSM_v3_state_next[7]) );
INVX2TS U1521 ( .A(n1389), .Y(n1392) );
AOI22X1TS U1522 ( .A0(n1402), .A1(d_ff3_sh_x_out[22]), .B0(n1395), .B1(
d_ff3_sh_y_out[22]), .Y(n1390) );
OAI2BB1X1TS U1523 ( .A0N(n1248), .A1N(d_ff3_LUT_out[19]), .B0(n1390), .Y(
add_subt_dataB[22]) );
AOI22X1TS U1524 ( .A0(n1402), .A1(d_ff3_sh_x_out[19]), .B0(n1253), .B1(
d_ff3_sh_y_out[19]), .Y(n1391) );
OAI2BB1X1TS U1525 ( .A0N(n1392), .A1N(d_ff3_LUT_out[19]), .B0(n1391), .Y(
add_subt_dataB[19]) );
AOI22X1TS U1526 ( .A0(n1402), .A1(d_ff3_sh_x_out[14]), .B0(n1216), .B1(
d_ff3_sh_y_out[14]), .Y(n1393) );
OAI2BB1X1TS U1527 ( .A0N(n1271), .A1N(d_ff3_LUT_out[5]), .B0(n1393), .Y(
add_subt_dataB[14]) );
AOI22X1TS U1528 ( .A0(n1402), .A1(d_ff3_sh_x_out[11]), .B0(n1215), .B1(
d_ff3_sh_y_out[11]), .Y(n1394) );
OAI2BB1X1TS U1529 ( .A0N(n1401), .A1N(d_ff3_LUT_out[7]), .B0(n1394), .Y(
add_subt_dataB[11]) );
AOI22X1TS U1530 ( .A0(n1396), .A1(d_ff3_sh_x_out[7]), .B0(n1395), .B1(
d_ff3_sh_y_out[7]), .Y(n1397) );
OAI2BB1X1TS U1531 ( .A0N(n1400), .A1N(d_ff3_LUT_out[7]), .B0(n1397), .Y(
add_subt_dataB[7]) );
AOI22X1TS U1532 ( .A0(n1398), .A1(d_ff3_sh_x_out[5]), .B0(n1216), .B1(
d_ff3_sh_y_out[5]), .Y(n1399) );
OAI2BB1X1TS U1533 ( .A0N(n1241), .A1N(d_ff3_LUT_out[5]), .B0(n1399), .Y(
add_subt_dataB[5]) );
AOI22X1TS U1534 ( .A0(n1402), .A1(d_ff2_Y[30]), .B0(d_ff2_Z[30]), .B1(n1241),
.Y(n1403) );
OAI2BB1X1TS U1535 ( .A0N(n1404), .A1N(d_ff2_X[30]), .B0(n1403), .Y(
add_subt_dataA[30]) );
AOI22X1TS U1536 ( .A0(enab_cont_iter), .A1(cont_iter_out[0]), .B0(n1059),
.B1(n1405), .Y(n989) );
OAI32X1TS U1537 ( .A0(n1406), .A1(n1427), .A2(n1405), .B0(n1430), .B1(n1406),
.Y(n988) );
NAND2X1TS U1538 ( .A(cont_iter_out[2]), .B(n1406), .Y(n1407) );
XNOR2X1TS U1539 ( .A(cont_iter_out[3]), .B(n1407), .Y(n986) );
OAI221XLTS U1540 ( .A0(n1414), .A1(n1435), .B0(n1413), .B1(n1409), .C0(n1408), .Y(n810) );
AOI22X1TS U1541 ( .A0(n1426), .A1(n1412), .B0(n1433), .B1(n1410), .Y(n809)
);
OAI221XLTS U1542 ( .A0(n1414), .A1(n1436), .B0(n1413), .B1(n1412), .C0(n1411), .Y(n806) );
OA22X1TS U1543 ( .A0(d_ff_Xn[1]), .A1(n1060), .B0(n1416), .B1(d_ff2_X[1]),
.Y(n701) );
OA22X1TS U1544 ( .A0(d_ff_Xn[2]), .A1(n1060), .B0(n1417), .B1(d_ff2_X[2]),
.Y(n699) );
OA22X1TS U1545 ( .A0(d_ff_Xn[3]), .A1(n1060), .B0(n1417), .B1(d_ff2_X[3]),
.Y(n697) );
OA22X1TS U1546 ( .A0(d_ff_Xn[5]), .A1(n1060), .B0(n1448), .B1(d_ff2_X[5]),
.Y(n693) );
CLKBUFX3TS U1547 ( .A(n1417), .Y(n1415) );
OA22X1TS U1548 ( .A0(d_ff_Xn[6]), .A1(n1060), .B0(n1415), .B1(d_ff2_X[6]),
.Y(n691) );
OA22X1TS U1549 ( .A0(d_ff_Xn[7]), .A1(n1060), .B0(n1415), .B1(d_ff2_X[7]),
.Y(n689) );
OA22X1TS U1550 ( .A0(d_ff_Xn[10]), .A1(n1062), .B0(n1415), .B1(d_ff2_X[10]),
.Y(n683) );
OA22X1TS U1551 ( .A0(d_ff_Xn[12]), .A1(n1061), .B0(n1415), .B1(d_ff2_X[12]),
.Y(n679) );
OA22X1TS U1552 ( .A0(d_ff_Xn[13]), .A1(n1062), .B0(n1415), .B1(d_ff2_X[13]),
.Y(n677) );
OA22X1TS U1553 ( .A0(d_ff_Xn[14]), .A1(n1061), .B0(n1415), .B1(d_ff2_X[14]),
.Y(n675) );
OA22X1TS U1554 ( .A0(d_ff_Xn[16]), .A1(n1062), .B0(n1415), .B1(d_ff2_X[16]),
.Y(n671) );
OA22X1TS U1555 ( .A0(d_ff_Xn[17]), .A1(n1061), .B0(n1415), .B1(d_ff2_X[17]),
.Y(n669) );
OA22X1TS U1556 ( .A0(d_ff_Xn[19]), .A1(n1062), .B0(n1415), .B1(d_ff2_X[19]),
.Y(n665) );
OA22X1TS U1557 ( .A0(d_ff_Xn[20]), .A1(n1061), .B0(n1415), .B1(d_ff2_X[20]),
.Y(n663) );
OA22X1TS U1558 ( .A0(n1416), .A1(d_ff2_X[24]), .B0(d_ff_Xn[24]), .B1(n1062),
.Y(n656) );
OA22X1TS U1559 ( .A0(d_ff_Xn[25]), .A1(n1062), .B0(n1448), .B1(d_ff2_X[25]),
.Y(n655) );
OA22X1TS U1560 ( .A0(d_ff_Xn[26]), .A1(n1061), .B0(n1448), .B1(d_ff2_X[26]),
.Y(n654) );
OA22X1TS U1561 ( .A0(n1448), .A1(d_ff2_X[27]), .B0(d_ff_Xn[27]), .B1(n1061),
.Y(n653) );
OA22X1TS U1562 ( .A0(n1416), .A1(d_ff2_X[28]), .B0(d_ff_Xn[28]), .B1(n1062),
.Y(n652) );
OA22X1TS U1563 ( .A0(n1417), .A1(d_ff2_X[29]), .B0(d_ff_Xn[29]), .B1(n1061),
.Y(n651) );
AOI22X1TS U1564 ( .A0(n1418), .A1(d_ff2_X[23]), .B0(d_ff3_sh_x_out[23]),
.B1(n1424), .Y(n1419) );
OAI2BB1X1TS U1565 ( .A0N(n1421), .A1N(n1420), .B0(n1419), .Y(n649) );
AOI21X1TS U1566 ( .A0(d_ff2_X[29]), .A1(n1423), .B0(n1422), .Y(n1425) );
AOI22X1TS U1567 ( .A0(n1426), .A1(n1425), .B0(n1442), .B1(n1424), .Y(n643)
);
initial $sdf_annotate("CORDIC_Arch3v1_ASIC_fpu_syn_constraints_noclk.tcl_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/30 21:37:23
// Design Name:
// Module Name: lab6_1_1_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module lab6_1_1_tb(
);
reg Clk,load,reset;
reg [3:0] D;
wire [3:0] Q;
lab6_1_1 dut(D,Clk,reset,load,Q);
initial
begin
for(Clk = 0;Clk >= 0;Clk=Clk+1)
begin
#10;
end
end
initial
begin
#60 load = 1;
#20 load = 0;
#40 load = 1;
#20 load = 0;
#55 load = 1;
#20 load = 0;
#65 load = 1;
end
initial
begin
reset = 0;
#155 reset = 1;
#85 reset = 0;
end
initial
begin
D = 0;
#20 D = 4'b0101;
#60 D = 4'b1001;
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.58f
// \ \ Application: netgen
// / / Filename: sub_float_float_float.v
// /___/ /\ Timestamp: Wed Jan 27 15:39:36 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/lol/ipcore_dir/tmp/_cg/sub_float_float_float.ngc /home/jhegarty/lol/ipcore_dir/tmp/_cg/sub_float_float_float.v
// Device : 7z100ffg900-2
// Input file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/sub_float_float_float.ngc
// Output file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/sub_float_float_float.v
// # of Modules : 1
// Design Name : sub_float_float_float
// Xilinx : /opt/Xilinx/14.5/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
module sub_float32_float32_float32 (
CLK, ce, inp, out
);
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [63 : 0] inp;
output [31 : 0] out;
wire clk;
assign clk=CLK;
wire [31:0] a;
wire [31:0] b;
wire [31:0] result;
assign a = inp[31:0];
assign b = inp[63:32];
assign out = result;
wire \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/sign_op ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire sig00000149;
wire sig0000014a;
wire sig0000014b;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000195;
wire sig00000196;
wire sig00000197;
wire sig00000198;
wire sig00000199;
wire sig0000019a;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
wire sig0000019e;
wire sig0000019f;
wire sig000001a0;
wire sig000001a1;
wire sig000001a2;
wire sig000001a3;
wire sig000001a4;
wire sig000001a5;
wire sig000001a6;
wire sig000001a7;
wire sig000001a8;
wire sig000001a9;
wire sig000001aa;
wire sig000001ab;
wire sig000001ac;
wire sig000001ad;
wire sig000001ae;
wire sig000001af;
wire sig000001b0;
wire sig000001b1;
wire sig000001b2;
wire sig000001b3;
wire sig000001b4;
wire sig000001b5;
wire sig000001b6;
wire sig000001b7;
wire sig000001b8;
wire sig000001b9;
wire sig000001ba;
wire sig000001bb;
wire sig000001bc;
wire sig000001bd;
wire sig000001be;
wire sig000001bf;
wire sig000001c0;
wire sig000001c1;
wire sig000001c2;
wire sig000001c3;
wire sig000001c4;
wire sig000001c5;
wire sig000001c6;
wire sig000001c7;
wire sig000001c8;
wire sig000001c9;
wire sig000001ca;
wire sig000001cb;
wire sig000001cc;
wire sig000001cd;
wire sig000001ce;
wire sig000001cf;
wire sig000001d0;
wire sig000001d1;
wire sig000001d2;
wire sig000001d3;
wire sig000001d4;
wire sig000001d5;
wire sig000001d6;
wire sig000001d7;
wire sig000001d8;
wire sig000001d9;
wire sig000001da;
wire sig000001db;
wire sig000001dc;
wire sig000001dd;
wire sig000001de;
wire sig000001df;
wire sig000001e0;
wire sig000001e1;
wire sig000001e2;
wire sig000001e3;
wire sig000001e4;
wire sig000001e5;
wire sig000001e6;
wire sig000001e7;
wire sig000001e8;
wire sig000001e9;
wire sig000001ea;
wire sig000001eb;
wire sig000001ec;
wire sig000001ed;
wire sig000001ee;
wire sig000001ef;
wire sig000001f0;
wire sig000001f1;
wire sig000001f2;
wire sig000001f3;
wire sig000001f4;
wire sig000001f5;
wire sig000001f6;
wire sig000001f7;
wire sig000001f8;
wire sig000001f9;
wire sig000001fa;
wire sig000001fb;
wire sig000001fc;
wire sig000001fd;
wire sig000001fe;
wire sig000001ff;
wire sig00000200;
wire sig00000201;
wire sig00000202;
wire sig00000203;
wire sig00000204;
wire sig00000205;
wire sig00000206;
wire sig00000207;
wire sig00000208;
wire sig00000209;
wire sig0000020a;
wire sig0000020b;
wire sig0000020c;
wire sig0000020d;
wire sig0000020e;
wire sig0000020f;
wire sig00000210;
wire sig00000211;
wire sig00000212;
wire sig00000213;
wire sig00000214;
wire sig00000215;
wire sig00000216;
wire sig00000217;
wire sig00000218;
wire sig00000219;
wire sig0000021a;
wire sig0000021b;
wire sig0000021c;
wire sig0000021d;
wire sig0000021e;
wire sig0000021f;
wire sig00000220;
wire sig00000221;
wire sig00000222;
wire sig00000223;
wire sig00000224;
wire sig00000225;
wire sig00000226;
wire sig00000227;
wire sig00000228;
wire sig00000229;
wire sig0000022a;
wire sig0000022b;
wire sig0000022c;
wire sig0000022d;
wire sig0000022e;
wire sig0000022f;
wire sig00000230;
wire sig00000231;
wire sig00000232;
wire sig00000233;
wire sig00000234;
wire sig00000235;
wire sig00000236;
wire sig00000237;
wire sig00000238;
wire sig00000239;
wire sig0000023a;
wire sig0000023b;
wire sig0000023c;
wire sig0000023d;
wire sig0000023e;
wire sig0000023f;
wire sig00000240;
wire sig00000241;
wire sig00000242;
wire sig00000243;
wire sig00000244;
wire sig00000245;
wire sig00000246;
wire sig00000247;
wire sig00000248;
wire sig00000249;
wire sig0000024a;
wire sig0000024b;
wire sig0000024c;
wire sig0000024d;
wire sig0000024e;
wire sig0000024f;
wire sig00000250;
wire sig00000251;
wire sig00000252;
wire sig00000253;
wire sig00000254;
wire sig00000255;
wire sig00000256;
wire sig00000257;
wire sig00000258;
wire sig00000259;
wire sig0000025a;
wire sig0000025b;
wire sig0000025c;
wire sig0000025d;
wire sig0000025e;
wire sig0000025f;
wire sig00000260;
wire sig00000261;
wire sig00000262;
wire sig00000263;
wire sig00000264;
wire sig00000265;
wire sig00000266;
wire sig00000267;
wire sig00000268;
wire sig00000269;
wire sig0000026a;
wire sig0000026b;
wire sig0000026c;
wire sig0000026d;
wire sig0000026e;
wire sig0000026f;
wire sig00000270;
wire sig00000271;
wire sig00000272;
wire sig00000273;
wire sig00000274;
wire sig00000275;
wire sig00000276;
wire sig00000277;
wire sig00000278;
wire sig00000279;
wire sig0000027a;
wire sig0000027b;
wire sig0000027c;
wire sig0000027d;
wire sig0000027e;
wire sig0000027f;
wire sig00000280;
wire sig00000281;
wire sig00000282;
wire sig00000283;
wire sig00000284;
wire sig00000285;
wire sig00000286;
wire sig00000287;
wire sig00000288;
wire sig00000289;
wire sig0000028a;
wire sig0000028b;
wire sig0000028c;
wire sig0000028d;
wire sig0000028e;
wire sig0000028f;
wire sig00000290;
wire sig00000291;
wire sig00000292;
wire sig00000293;
wire sig00000294;
wire sig00000295;
wire sig00000296;
wire sig00000297;
wire sig00000298;
wire sig00000299;
wire sig0000029a;
wire sig0000029b;
wire sig0000029c;
wire sig0000029d;
wire sig0000029e;
wire sig0000029f;
wire sig000002a0;
wire sig000002a1;
wire sig000002a2;
wire sig000002a3;
wire sig000002a4;
wire sig000002a5;
wire sig000002a6;
wire sig000002a7;
wire sig000002a8;
wire sig000002a9;
wire sig000002aa;
wire sig000002ab;
wire sig000002ac;
wire sig000002ad;
wire sig000002ae;
wire sig000002af;
wire sig000002b0;
wire sig000002b1;
wire sig000002b2;
wire sig000002b3;
wire sig000002b4;
wire sig000002b5;
wire sig000002b6;
wire sig000002b7;
wire sig000002b8;
wire sig000002b9;
wire sig000002ba;
wire sig000002bb;
wire sig000002bc;
wire sig000002bd;
wire sig000002be;
wire sig000002bf;
wire sig000002c0;
wire sig000002c1;
wire sig000002c2;
wire sig000002c3;
wire sig000002c4;
wire sig000002c5;
wire sig000002c6;
wire sig000002c7;
wire sig000002c8;
wire sig000002c9;
wire sig000002ca;
wire sig000002cb;
wire sig000002cc;
wire sig000002cd;
wire sig000002ce;
wire sig000002cf;
wire sig000002d0;
wire sig000002d1;
wire sig000002d2;
wire sig000002d3;
wire sig000002d4;
wire sig000002d5;
wire sig000002d6;
wire sig000002d7;
wire sig000002d8;
wire sig000002d9;
wire sig000002da;
wire sig000002db;
wire sig000002dc;
wire sig000002dd;
wire sig000002de;
wire sig000002df;
wire sig000002e0;
wire sig000002e1;
wire sig000002e2;
wire sig000002e3;
wire sig000002e4;
wire sig000002e5;
wire NLW_blk00000082_O_UNCONNECTED;
wire NLW_blk000000cb_O_UNCONNECTED;
wire NLW_blk000002a4_Q15_UNCONNECTED;
wire NLW_blk000002a6_Q15_UNCONNECTED;
wire NLW_blk000002a8_Q15_UNCONNECTED;
wire NLW_blk000002aa_Q15_UNCONNECTED;
wire NLW_blk000002ac_Q15_UNCONNECTED;
wire NLW_blk000002ae_Q15_UNCONNECTED;
wire NLW_blk000002b0_Q15_UNCONNECTED;
wire NLW_blk000002b2_Q15_UNCONNECTED;
wire NLW_blk000002b4_Q15_UNCONNECTED;
wire NLW_blk000002b6_Q15_UNCONNECTED;
wire NLW_blk000002b8_Q15_UNCONNECTED;
wire NLW_blk000002ba_Q15_UNCONNECTED;
wire NLW_blk000002bc_Q15_UNCONNECTED;
wire NLW_blk000002be_Q15_UNCONNECTED;
wire NLW_blk000002c0_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk000002c0_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk000002c0_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk000002c0_UNDERFLOW_UNCONNECTED;
wire NLW_blk000002c0_OVERFLOW_UNCONNECTED;
wire \NLW_blk000002c0_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c0_P<47>_UNCONNECTED ;
wire \NLW_blk000002c0_P<46>_UNCONNECTED ;
wire \NLW_blk000002c0_P<45>_UNCONNECTED ;
wire \NLW_blk000002c0_P<44>_UNCONNECTED ;
wire \NLW_blk000002c0_P<43>_UNCONNECTED ;
wire \NLW_blk000002c0_P<42>_UNCONNECTED ;
wire \NLW_blk000002c0_P<41>_UNCONNECTED ;
wire \NLW_blk000002c0_P<40>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c0_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c1_P<26>_UNCONNECTED ;
wire NLW_blk000002c1_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk000002c1_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk000002c1_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk000002c1_UNDERFLOW_UNCONNECTED;
wire NLW_blk000002c1_PATTERNDETECT_UNCONNECTED;
wire NLW_blk000002c1_OVERFLOW_UNCONNECTED;
wire \NLW_blk000002c1_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c1_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c1_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c1_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c1_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c1_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c1_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk000002c1_P<47>_UNCONNECTED ;
wire \NLW_blk000002c1_P<46>_UNCONNECTED ;
wire \NLW_blk000002c1_P<45>_UNCONNECTED ;
wire \NLW_blk000002c1_P<44>_UNCONNECTED ;
wire \NLW_blk000002c1_P<43>_UNCONNECTED ;
wire \NLW_blk000002c1_P<42>_UNCONNECTED ;
wire \NLW_blk000002c1_P<41>_UNCONNECTED ;
wire \NLW_blk000002c1_P<40>_UNCONNECTED ;
wire \NLW_blk000002c1_P<39>_UNCONNECTED ;
wire \NLW_blk000002c1_P<38>_UNCONNECTED ;
wire \NLW_blk000002c1_P<37>_UNCONNECTED ;
wire \NLW_blk000002c1_P<36>_UNCONNECTED ;
wire \NLW_blk000002c1_P<35>_UNCONNECTED ;
wire \NLW_blk000002c1_P<25>_UNCONNECTED ;
wire \NLW_blk000002c1_P<1>_UNCONNECTED ;
wire \NLW_blk000002c1_P<0>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk000002c1_PCOUT<0>_UNCONNECTED ;
wire [7 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op ;
wire [22 : 0] \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op ;
assign
result[31] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/sign_op ,
result[30] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [7],
result[29] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [6],
result[28] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [5],
result[27] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [4],
result[26] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [3],
result[25] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [2],
result[24] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [1],
result[23] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [0],
result[22] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [22],
result[21] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [21],
result[20] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [20],
result[19] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [19],
result[18] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [18],
result[17] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [17],
result[16] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [16],
result[15] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [15],
result[14] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [14],
result[13] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [13],
result[12] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [12],
result[11] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [11],
result[10] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [10],
result[9] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [9],
result[8] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [8],
result[7] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [7],
result[6] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [6],
result[5] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [5],
result[4] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [4],
result[3] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [3],
result[2] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [2],
result[1] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [1],
result[0] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [0];
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(ce),
.D(sig000000af),
.Q(sig0000000f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.CE(ce),
.D(sig000000ae),
.Q(sig0000000e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.CE(ce),
.D(sig000000ad),
.Q(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.CE(ce),
.D(sig000000de),
.Q(sig00000010)
);
FDE #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.CE(ce),
.D(sig000000df),
.Q(sig0000000d)
);
XORCY blk00000008 (
.CI(sig0000008c),
.LI(sig00000001),
.O(sig000000dd)
);
MUXCY blk00000009 (
.CI(sig0000008d),
.DI(sig00000002),
.S(sig00000001),
.O(sig0000008c)
);
XORCY blk0000000a (
.CI(sig0000008f),
.LI(sig0000008e),
.O(sig000000dc)
);
MUXCY blk0000000b (
.CI(sig0000008f),
.DI(sig000000eb),
.S(sig0000008e),
.O(sig0000008d)
);
XORCY blk0000000c (
.CI(sig00000091),
.LI(sig00000090),
.O(sig000000db)
);
MUXCY blk0000000d (
.CI(sig00000091),
.DI(sig000000ea),
.S(sig00000090),
.O(sig0000008f)
);
XORCY blk0000000e (
.CI(sig00000093),
.LI(sig00000092),
.O(sig000000da)
);
MUXCY blk0000000f (
.CI(sig00000093),
.DI(sig000000e9),
.S(sig00000092),
.O(sig00000091)
);
XORCY blk00000010 (
.CI(sig00000095),
.LI(sig00000094),
.O(sig000000d9)
);
MUXCY blk00000011 (
.CI(sig00000095),
.DI(sig000000e8),
.S(sig00000094),
.O(sig00000093)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000012 (
.I0(sig000000e8),
.I1(sig00000067),
.O(sig00000094)
);
XORCY blk00000013 (
.CI(sig00000097),
.LI(sig00000096),
.O(sig000000d8)
);
MUXCY blk00000014 (
.CI(sig00000097),
.DI(sig000000e7),
.S(sig00000096),
.O(sig00000095)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000015 (
.I0(sig000000e7),
.I1(sig00000068),
.O(sig00000096)
);
XORCY blk00000016 (
.CI(sig00000099),
.LI(sig00000098),
.O(sig000000d7)
);
MUXCY blk00000017 (
.CI(sig00000099),
.DI(sig000000e6),
.S(sig00000098),
.O(sig00000097)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000018 (
.I0(sig000000e6),
.I1(sig00000069),
.O(sig00000098)
);
XORCY blk00000019 (
.CI(sig0000009b),
.LI(sig0000009a),
.O(sig000000d6)
);
MUXCY blk0000001a (
.CI(sig0000009b),
.DI(sig000000e5),
.S(sig0000009a),
.O(sig00000099)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001b (
.I0(sig000000e5),
.I1(sig0000006a),
.O(sig0000009a)
);
XORCY blk0000001c (
.CI(sig00000001),
.LI(sig0000009c),
.O(sig000000d5)
);
MUXCY blk0000001d (
.CI(sig00000001),
.DI(sig000000e4),
.S(sig0000009c),
.O(sig0000009b)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000001e (
.I0(sig000000e4),
.I1(sig0000006b),
.O(sig0000009c)
);
XORCY blk0000001f (
.CI(sig0000009d),
.LI(sig00000001),
.O(sig000000cc)
);
XORCY blk00000020 (
.CI(sig0000009f),
.LI(sig0000009e),
.O(sig000000cb)
);
MUXCY blk00000021 (
.CI(sig0000009f),
.DI(b[30]),
.S(sig0000009e),
.O(sig0000009d)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000022 (
.I0(b[30]),
.I1(a[30]),
.O(sig0000009e)
);
XORCY blk00000023 (
.CI(sig000000a1),
.LI(sig000000a0),
.O(sig000000ca)
);
MUXCY blk00000024 (
.CI(sig000000a1),
.DI(b[29]),
.S(sig000000a0),
.O(sig0000009f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000025 (
.I0(b[29]),
.I1(a[29]),
.O(sig000000a0)
);
XORCY blk00000026 (
.CI(sig000000a3),
.LI(sig000000a2),
.O(sig000000c9)
);
MUXCY blk00000027 (
.CI(sig000000a3),
.DI(b[28]),
.S(sig000000a2),
.O(sig000000a1)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000028 (
.I0(b[28]),
.I1(a[28]),
.O(sig000000a2)
);
XORCY blk00000029 (
.CI(sig000000a5),
.LI(sig000000a4),
.O(sig000000c8)
);
MUXCY blk0000002a (
.CI(sig000000a5),
.DI(b[27]),
.S(sig000000a4),
.O(sig000000a3)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002b (
.I0(b[27]),
.I1(a[27]),
.O(sig000000a4)
);
XORCY blk0000002c (
.CI(sig000000a7),
.LI(sig000000a6),
.O(sig000000c7)
);
MUXCY blk0000002d (
.CI(sig000000a7),
.DI(b[26]),
.S(sig000000a6),
.O(sig000000a5)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000002e (
.I0(b[26]),
.I1(a[26]),
.O(sig000000a6)
);
XORCY blk0000002f (
.CI(sig000000a9),
.LI(sig000000a8),
.O(sig000000c6)
);
MUXCY blk00000030 (
.CI(sig000000a9),
.DI(b[25]),
.S(sig000000a8),
.O(sig000000a7)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000031 (
.I0(b[25]),
.I1(a[25]),
.O(sig000000a8)
);
XORCY blk00000032 (
.CI(sig000000ab),
.LI(sig000000aa),
.O(sig000000c5)
);
MUXCY blk00000033 (
.CI(sig000000ab),
.DI(b[24]),
.S(sig000000aa),
.O(sig000000a9)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000034 (
.I0(b[24]),
.I1(a[24]),
.O(sig000000aa)
);
XORCY blk00000035 (
.CI(sig00000001),
.LI(sig000000ac),
.O(sig000000c4)
);
MUXCY blk00000036 (
.CI(sig00000001),
.DI(b[23]),
.S(sig000000ac),
.O(sig000000ab)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000037 (
.I0(b[23]),
.I1(a[23]),
.O(sig000000ac)
);
FDE #(
.INIT ( 1'b0 ))
blk00000038 (
.C(clk),
.CE(ce),
.D(sig000000bf),
.Q(sig000000e0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000039 (
.C(clk),
.CE(ce),
.D(sig000000e3),
.Q(sig000000e2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003a (
.C(clk),
.CE(ce),
.D(sig000000be),
.Q(sig000000e1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003b (
.C(clk),
.CE(ce),
.D(sig000000ce),
.Q(sig000000b0)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003c (
.C(clk),
.CE(ce),
.D(a[31]),
.Q(sig000000ff)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003d (
.C(clk),
.CE(ce),
.D(sig000000d4),
.Q(sig000000fe)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003e (
.C(clk),
.CE(ce),
.D(sig0000008b),
.Q(sig000000b1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000003f (
.C(clk),
.CE(ce),
.D(sig0000001a),
.Q(sig000000fd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000040 (
.C(clk),
.CE(ce),
.D(sig000000c1),
.Q(sig000000fc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000041 (
.C(clk),
.CE(ce),
.D(sig000000c3),
.Q(sig000000fb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000042 (
.C(clk),
.CE(ce),
.D(sig000000c2),
.Q(sig000000f9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000043 (
.C(clk),
.CE(ce),
.D(sig000000c0),
.Q(sig000001a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000044 (
.C(clk),
.CE(ce),
.D(sig000000d1),
.Q(sig000000f8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000045 (
.C(clk),
.CE(ce),
.D(sig000000d2),
.Q(sig000000fa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000046 (
.C(clk),
.CE(ce),
.D(sig000000d3),
.Q(sig000000f7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000047 (
.C(clk),
.CE(ce),
.D(sig000000cd),
.Q(sig0000001b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000048 (
.C(clk),
.CE(ce),
.D(sig000000b5),
.Q(sig00000111)
);
FDE #(
.INIT ( 1'b0 ))
blk00000049 (
.C(clk),
.CE(ce),
.D(sig000000b4),
.Q(sig00000112)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004a (
.C(clk),
.CE(ce),
.D(sig000000b3),
.Q(sig00000114)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004b (
.C(clk),
.CE(ce),
.D(sig000000b2),
.Q(sig00000115)
);
MUXCY blk0000004c (
.CI(sig00000001),
.DI(sig00000002),
.S(sig0000011d),
.O(sig00000117)
);
MUXCY blk0000004d (
.CI(sig00000117),
.DI(sig00000002),
.S(sig0000011c),
.O(sig00000118)
);
MUXCY blk0000004e (
.CI(sig00000118),
.DI(sig00000002),
.S(sig0000011b),
.O(sig00000119)
);
MUXCY blk0000004f (
.CI(sig00000119),
.DI(sig00000002),
.S(sig0000011e),
.O(sig0000011a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000050 (
.C(clk),
.CE(ce),
.D(sig0000011a),
.Q(sig00000116)
);
MUXCY blk00000051 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000125),
.O(sig0000011f)
);
MUXCY blk00000052 (
.CI(sig0000011f),
.DI(sig00000002),
.S(sig00000124),
.O(sig00000120)
);
MUXCY blk00000053 (
.CI(sig00000120),
.DI(sig00000002),
.S(sig00000123),
.O(sig00000121)
);
MUXCY blk00000054 (
.CI(sig00000121),
.DI(sig00000002),
.S(sig00000126),
.O(sig00000122)
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(clk),
.CE(ce),
.D(sig00000122),
.Q(sig00000113)
);
MUXCY blk00000056 (
.CI(sig00000148),
.DI(sig00000127),
.S(sig00000128),
.O(sig00000147)
);
MUXCY blk00000057 (
.CI(sig00000149),
.DI(sig00000129),
.S(sig0000012a),
.O(sig00000148)
);
MUXCY blk00000058 (
.CI(sig0000014a),
.DI(sig0000012b),
.S(sig0000012c),
.O(sig00000149)
);
MUXCY blk00000059 (
.CI(sig0000014b),
.DI(sig0000012d),
.S(sig0000012e),
.O(sig0000014a)
);
MUXCY blk0000005a (
.CI(sig0000014c),
.DI(sig0000012f),
.S(sig00000130),
.O(sig0000014b)
);
MUXCY blk0000005b (
.CI(sig0000014d),
.DI(sig00000131),
.S(sig00000132),
.O(sig0000014c)
);
MUXCY blk0000005c (
.CI(sig0000014e),
.DI(sig00000133),
.S(sig00000134),
.O(sig0000014d)
);
MUXCY blk0000005d (
.CI(sig0000014f),
.DI(sig00000135),
.S(sig00000136),
.O(sig0000014e)
);
MUXCY blk0000005e (
.CI(sig00000150),
.DI(sig00000137),
.S(sig00000138),
.O(sig0000014f)
);
MUXCY blk0000005f (
.CI(sig00000151),
.DI(sig00000139),
.S(sig0000013a),
.O(sig00000150)
);
MUXCY blk00000060 (
.CI(sig00000152),
.DI(sig0000013b),
.S(sig0000013c),
.O(sig00000151)
);
MUXCY blk00000061 (
.CI(sig00000153),
.DI(sig0000013d),
.S(sig0000013e),
.O(sig00000152)
);
MUXCY blk00000062 (
.CI(sig00000154),
.DI(sig0000013f),
.S(sig00000140),
.O(sig00000153)
);
MUXCY blk00000063 (
.CI(sig00000155),
.DI(sig00000141),
.S(sig00000142),
.O(sig00000154)
);
MUXCY blk00000064 (
.CI(sig00000156),
.DI(sig00000143),
.S(sig00000144),
.O(sig00000155)
);
MUXCY blk00000065 (
.CI(sig00000002),
.DI(sig00000145),
.S(sig00000146),
.O(sig00000156)
);
FDE #(
.INIT ( 1'b0 ))
blk00000066 (
.C(clk),
.CE(ce),
.D(sig00000147),
.Q(sig00000019)
);
FDE #(
.INIT ( 1'b0 ))
blk00000067 (
.C(clk),
.CE(ce),
.D(b[30]),
.Q(sig00000107)
);
FDE #(
.INIT ( 1'b0 ))
blk00000068 (
.C(clk),
.CE(ce),
.D(b[29]),
.Q(sig00000106)
);
FDE #(
.INIT ( 1'b0 ))
blk00000069 (
.C(clk),
.CE(ce),
.D(b[28]),
.Q(sig00000105)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006a (
.C(clk),
.CE(ce),
.D(b[27]),
.Q(sig00000104)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006b (
.C(clk),
.CE(ce),
.D(b[26]),
.Q(sig00000103)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006c (
.C(clk),
.CE(ce),
.D(b[25]),
.Q(sig00000102)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006d (
.C(clk),
.CE(ce),
.D(b[24]),
.Q(sig00000101)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006e (
.C(clk),
.CE(ce),
.D(b[23]),
.Q(sig00000100)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006f (
.C(clk),
.CE(ce),
.D(a[30]),
.Q(sig0000010f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000070 (
.C(clk),
.CE(ce),
.D(a[29]),
.Q(sig0000010e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000071 (
.C(clk),
.CE(ce),
.D(a[28]),
.Q(sig0000010d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000072 (
.C(clk),
.CE(ce),
.D(a[27]),
.Q(sig0000010c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000073 (
.C(clk),
.CE(ce),
.D(a[26]),
.Q(sig0000010b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000074 (
.C(clk),
.CE(ce),
.D(a[25]),
.Q(sig0000010a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000075 (
.C(clk),
.CE(ce),
.D(a[24]),
.Q(sig00000109)
);
FDE #(
.INIT ( 1'b0 ))
blk00000076 (
.C(clk),
.CE(ce),
.D(a[23]),
.Q(sig00000108)
);
FDE #(
.INIT ( 1'b0 ))
blk00000077 (
.C(clk),
.CE(ce),
.D(sig000000cc),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk00000078 (
.C(clk),
.CE(ce),
.D(sig000000cb),
.Q(sig00000004)
);
FDE #(
.INIT ( 1'b0 ))
blk00000079 (
.C(clk),
.CE(ce),
.D(sig000000ca),
.Q(sig00000005)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007a (
.C(clk),
.CE(ce),
.D(sig000000c9),
.Q(sig00000006)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007b (
.C(clk),
.CE(ce),
.D(sig000000c8),
.Q(sig00000007)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007c (
.C(clk),
.CE(ce),
.D(sig000000c7),
.Q(sig00000008)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007d (
.C(clk),
.CE(ce),
.D(sig000000c6),
.Q(sig00000009)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007e (
.C(clk),
.CE(ce),
.D(sig000000c5),
.Q(sig0000000a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007f (
.C(clk),
.CE(ce),
.D(sig000000c4),
.Q(sig0000000b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000080 (
.C(clk),
.CE(ce),
.D(sig000000d0),
.Q(sig00000158)
);
FDE #(
.INIT ( 1'b0 ))
blk00000081 (
.C(clk),
.CE(ce),
.D(sig000000cf),
.Q(sig00000157)
);
XORCY blk00000082 (
.CI(sig00000159),
.LI(sig00000002),
.O(NLW_blk00000082_O_UNCONNECTED)
);
XORCY blk00000083 (
.CI(sig0000015a),
.LI(sig000000bd),
.O(sig000000f3)
);
MUXCY blk00000084 (
.CI(sig0000015a),
.DI(sig00000002),
.S(sig000000bd),
.O(sig00000159)
);
XORCY blk00000085 (
.CI(sig0000015b),
.LI(sig000000bc),
.O(sig000000f2)
);
MUXCY blk00000086 (
.CI(sig0000015b),
.DI(sig00000002),
.S(sig000000bc),
.O(sig0000015a)
);
XORCY blk00000087 (
.CI(sig0000015c),
.LI(sig000000bb),
.O(sig000000f1)
);
MUXCY blk00000088 (
.CI(sig0000015c),
.DI(sig00000002),
.S(sig000000bb),
.O(sig0000015b)
);
XORCY blk00000089 (
.CI(sig0000015d),
.LI(sig000000ba),
.O(sig000000f0)
);
MUXCY blk0000008a (
.CI(sig0000015d),
.DI(sig00000002),
.S(sig000000ba),
.O(sig0000015c)
);
XORCY blk0000008b (
.CI(sig0000015e),
.LI(sig000000b9),
.O(sig000000ef)
);
MUXCY blk0000008c (
.CI(sig0000015e),
.DI(sig00000002),
.S(sig000000b9),
.O(sig0000015d)
);
XORCY blk0000008d (
.CI(sig0000015f),
.LI(sig000000b8),
.O(sig000000ee)
);
MUXCY blk0000008e (
.CI(sig0000015f),
.DI(sig00000002),
.S(sig000000b8),
.O(sig0000015e)
);
XORCY blk0000008f (
.CI(sig00000160),
.LI(sig000000b7),
.O(sig000000ed)
);
MUXCY blk00000090 (
.CI(sig00000160),
.DI(sig00000002),
.S(sig000000b7),
.O(sig0000015f)
);
XORCY blk00000091 (
.CI(sig00000002),
.LI(sig000000b6),
.O(sig000000ec)
);
MUXCY blk00000092 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig000000b6),
.O(sig00000160)
);
FDE #(
.INIT ( 1'b0 ))
blk00000093 (
.C(clk),
.CE(ce),
.D(sig000000dd),
.Q(sig000000e3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000094 (
.C(clk),
.CE(ce),
.D(sig000000dc),
.Q(sig00000011)
);
FDE #(
.INIT ( 1'b0 ))
blk00000095 (
.C(clk),
.CE(ce),
.D(sig000000db),
.Q(sig00000012)
);
FDE #(
.INIT ( 1'b0 ))
blk00000096 (
.C(clk),
.CE(ce),
.D(sig000000da),
.Q(sig00000013)
);
FDE #(
.INIT ( 1'b0 ))
blk00000097 (
.C(clk),
.CE(ce),
.D(sig000000d9),
.Q(sig00000014)
);
FDE #(
.INIT ( 1'b0 ))
blk00000098 (
.C(clk),
.CE(ce),
.D(sig000000d8),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk00000099 (
.C(clk),
.CE(ce),
.D(sig000000d7),
.Q(sig00000016)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009a (
.C(clk),
.CE(ce),
.D(sig000000d6),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009b (
.C(clk),
.CE(ce),
.D(sig000000d5),
.Q(sig00000018)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009c (
.C(clk),
.CE(ce),
.D(a[22]),
.Q(sig0000001c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009d (
.C(clk),
.CE(ce),
.D(a[21]),
.Q(sig0000001d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009e (
.C(clk),
.CE(ce),
.D(a[20]),
.Q(sig0000001e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009f (
.C(clk),
.CE(ce),
.D(a[19]),
.Q(sig0000001f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a0 (
.C(clk),
.CE(ce),
.D(a[18]),
.Q(sig00000020)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a1 (
.C(clk),
.CE(ce),
.D(a[17]),
.Q(sig00000021)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a2 (
.C(clk),
.CE(ce),
.D(a[16]),
.Q(sig00000022)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a3 (
.C(clk),
.CE(ce),
.D(a[15]),
.Q(sig00000023)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a4 (
.C(clk),
.CE(ce),
.D(a[14]),
.Q(sig00000024)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a5 (
.C(clk),
.CE(ce),
.D(a[13]),
.Q(sig00000025)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a6 (
.C(clk),
.CE(ce),
.D(a[12]),
.Q(sig00000026)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a7 (
.C(clk),
.CE(ce),
.D(a[11]),
.Q(sig00000027)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a8 (
.C(clk),
.CE(ce),
.D(a[10]),
.Q(sig00000028)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a9 (
.C(clk),
.CE(ce),
.D(a[9]),
.Q(sig00000029)
);
FDE #(
.INIT ( 1'b0 ))
blk000000aa (
.C(clk),
.CE(ce),
.D(a[8]),
.Q(sig0000002a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ab (
.C(clk),
.CE(ce),
.D(a[7]),
.Q(sig0000002b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ac (
.C(clk),
.CE(ce),
.D(a[6]),
.Q(sig0000002c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ad (
.C(clk),
.CE(ce),
.D(a[5]),
.Q(sig0000002d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ae (
.C(clk),
.CE(ce),
.D(a[4]),
.Q(sig0000002e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000af (
.C(clk),
.CE(ce),
.D(a[3]),
.Q(sig0000002f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b0 (
.C(clk),
.CE(ce),
.D(a[2]),
.Q(sig00000030)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b1 (
.C(clk),
.CE(ce),
.D(a[1]),
.Q(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b2 (
.C(clk),
.CE(ce),
.D(a[0]),
.Q(sig00000032)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b3 (
.C(clk),
.CE(ce),
.D(b[22]),
.Q(sig00000033)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b4 (
.C(clk),
.CE(ce),
.D(b[21]),
.Q(sig00000034)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b5 (
.C(clk),
.CE(ce),
.D(b[20]),
.Q(sig00000035)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b6 (
.C(clk),
.CE(ce),
.D(b[19]),
.Q(sig00000036)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b7 (
.C(clk),
.CE(ce),
.D(b[18]),
.Q(sig00000037)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b8 (
.C(clk),
.CE(ce),
.D(b[17]),
.Q(sig00000038)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b9 (
.C(clk),
.CE(ce),
.D(b[16]),
.Q(sig00000039)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ba (
.C(clk),
.CE(ce),
.D(b[15]),
.Q(sig0000003a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bb (
.C(clk),
.CE(ce),
.D(b[14]),
.Q(sig0000003b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bc (
.C(clk),
.CE(ce),
.D(b[13]),
.Q(sig0000003c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.CE(ce),
.D(b[12]),
.Q(sig0000003d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.CE(ce),
.D(b[11]),
.Q(sig0000003e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.CE(ce),
.D(b[10]),
.Q(sig0000003f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.CE(ce),
.D(b[9]),
.Q(sig00000040)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.CE(ce),
.D(b[8]),
.Q(sig00000041)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.CE(ce),
.D(b[7]),
.Q(sig00000042)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.CE(ce),
.D(b[6]),
.Q(sig00000043)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.CE(ce),
.D(b[5]),
.Q(sig00000044)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.CE(ce),
.D(b[4]),
.Q(sig00000045)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.CE(ce),
.D(b[3]),
.Q(sig00000046)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.CE(ce),
.D(b[2]),
.Q(sig00000047)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.CE(ce),
.D(b[1]),
.Q(sig00000048)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.CE(ce),
.D(b[0]),
.Q(sig00000049)
);
MUXCY blk000000ca (
.CI(sig000001fb),
.DI(sig00000001),
.S(sig000002d7),
.O(sig000001a3)
);
XORCY blk000000cb (
.CI(sig000001fb),
.LI(sig000002d7),
.O(NLW_blk000000cb_O_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000000cc (
.C(clk),
.CE(ce),
.D(sig000001a3),
.Q(sig000001fa)
);
FDE #(
.INIT ( 1'b0 ))
blk000000cd (
.C(clk),
.CE(ce),
.D(sig000001a4),
.Q(sig000001fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ce (
.C(clk),
.CE(ce),
.D(sig000001c1),
.Q(sig000001a5)
);
FDE #(
.INIT ( 1'b0 ))
blk000000cf (
.C(clk),
.CE(ce),
.D(sig000001a5),
.Q(sig000001a2)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d0 (
.C(clk),
.CE(ce),
.D(sig000001fd),
.Q(sig000001a6)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d1 (
.C(clk),
.CE(ce),
.D(sig000001a6),
.Q(sig000001a1)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d2 (
.C(clk),
.CE(ce),
.D(sig000001c0),
.Q(sig000001f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d3 (
.C(clk),
.CE(ce),
.D(sig000001bf),
.Q(sig00000065)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d4 (
.C(clk),
.CE(ce),
.D(sig00000215),
.Q(sig00000189)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d5 (
.C(clk),
.CE(ce),
.D(sig00000214),
.Q(sig0000018a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d6 (
.C(clk),
.CE(ce),
.D(sig00000213),
.Q(sig0000018b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d7 (
.C(clk),
.CE(ce),
.D(sig00000212),
.Q(sig0000018c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d8 (
.C(clk),
.CE(ce),
.D(sig00000211),
.Q(sig0000018d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(clk),
.CE(ce),
.D(sig00000210),
.Q(sig0000018e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.CE(ce),
.D(sig0000020f),
.Q(sig0000018f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.CE(ce),
.D(sig0000020e),
.Q(sig00000190)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.CE(ce),
.D(sig0000020d),
.Q(sig00000191)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.CE(ce),
.D(sig0000020c),
.Q(sig00000192)
);
FDE #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.CE(ce),
.D(sig0000020b),
.Q(sig00000193)
);
FDE #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.CE(ce),
.D(sig0000020a),
.Q(sig00000194)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.CE(ce),
.D(sig00000209),
.Q(sig00000195)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.CE(ce),
.D(sig00000208),
.Q(sig00000196)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.CE(ce),
.D(sig00000207),
.Q(sig00000197)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.CE(ce),
.D(sig00000206),
.Q(sig00000198)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.CE(ce),
.D(sig00000205),
.Q(sig00000199)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.CE(ce),
.D(sig00000204),
.Q(sig0000019a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.CE(ce),
.D(sig00000203),
.Q(sig0000019b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.CE(ce),
.D(sig00000202),
.Q(sig0000019c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.CE(ce),
.D(sig00000201),
.Q(sig0000019d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.CE(ce),
.D(sig00000200),
.Q(sig0000019e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.CE(ce),
.D(sig000001ff),
.Q(sig0000019f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.CE(ce),
.D(sig000001fe),
.Q(sig000001a0)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.CE(ce),
.D(sig00000001),
.Q(sig00000215)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.CE(ce),
.D(sig000001ea),
.Q(sig00000214)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.CE(ce),
.D(sig000001e9),
.Q(sig00000213)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.CE(ce),
.D(sig000001e8),
.Q(sig00000212)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.CE(ce),
.D(sig000001e7),
.Q(sig00000211)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.CE(ce),
.D(sig000001e6),
.Q(sig00000210)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.CE(ce),
.D(sig000001e5),
.Q(sig0000020f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.CE(ce),
.D(sig000001e4),
.Q(sig0000020e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.CE(ce),
.D(sig000001e3),
.Q(sig0000020d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.CE(ce),
.D(sig000001e2),
.Q(sig0000020c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.CE(ce),
.D(sig000001e1),
.Q(sig0000020b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.CE(ce),
.D(sig000001e0),
.Q(sig0000020a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.CE(ce),
.D(sig000001df),
.Q(sig00000209)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.CE(ce),
.D(sig000001de),
.Q(sig00000208)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.CE(ce),
.D(sig000001dd),
.Q(sig00000207)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.CE(ce),
.D(sig000001dc),
.Q(sig00000206)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.CE(ce),
.D(sig000001db),
.Q(sig00000205)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.CE(ce),
.D(sig000001da),
.Q(sig00000204)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.CE(ce),
.D(sig000001d9),
.Q(sig00000203)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.CE(ce),
.D(sig000001d8),
.Q(sig00000202)
);
FDE #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.CE(ce),
.D(sig000001d7),
.Q(sig00000201)
);
FDE #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.CE(ce),
.D(sig000001d6),
.Q(sig00000200)
);
FDE #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.CE(ce),
.D(sig000001d5),
.Q(sig000001ff)
);
FDE #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.CE(ce),
.D(sig000001d4),
.Q(sig000001fe)
);
MUXCY blk00000104 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000222),
.O(sig00000216)
);
MUXCY blk00000105 (
.CI(sig00000216),
.DI(sig00000002),
.S(sig00000221),
.O(sig00000217)
);
MUXCY blk00000106 (
.CI(sig00000217),
.DI(sig00000002),
.S(sig00000220),
.O(sig00000218)
);
MUXCY blk00000107 (
.CI(sig00000218),
.DI(sig00000002),
.S(sig0000021f),
.O(sig00000219)
);
MUXCY blk00000108 (
.CI(sig00000219),
.DI(sig00000002),
.S(sig0000021e),
.O(sig0000021a)
);
MUXCY blk00000109 (
.CI(sig0000021a),
.DI(sig00000002),
.S(sig0000021d),
.O(sig0000021b)
);
MUXCY blk0000010a (
.CI(sig0000021b),
.DI(sig00000002),
.S(sig0000021c),
.O(sig000001fb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.CE(ce),
.D(sig000001d1),
.Q(sig00000179)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.CE(ce),
.D(sig000001d0),
.Q(sig0000017a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.CE(ce),
.D(sig000001cf),
.Q(sig0000017b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010e (
.C(clk),
.CE(ce),
.D(sig000001ce),
.Q(sig0000017c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010f (
.C(clk),
.CE(ce),
.D(sig000001cd),
.Q(sig0000017d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000110 (
.C(clk),
.CE(ce),
.D(sig000001cc),
.Q(sig0000017e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000111 (
.C(clk),
.CE(ce),
.D(sig000001cb),
.Q(sig0000017f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000112 (
.C(clk),
.CE(ce),
.D(sig000001ca),
.Q(sig00000180)
);
FDE #(
.INIT ( 1'b0 ))
blk00000113 (
.C(clk),
.CE(ce),
.D(sig000001c9),
.Q(sig00000181)
);
FDE #(
.INIT ( 1'b0 ))
blk00000114 (
.C(clk),
.CE(ce),
.D(sig000001c8),
.Q(sig00000182)
);
FDE #(
.INIT ( 1'b0 ))
blk00000115 (
.C(clk),
.CE(ce),
.D(sig000001c7),
.Q(sig00000183)
);
FDE #(
.INIT ( 1'b0 ))
blk00000116 (
.C(clk),
.CE(ce),
.D(sig000001c6),
.Q(sig00000184)
);
FDE #(
.INIT ( 1'b0 ))
blk00000117 (
.C(clk),
.CE(ce),
.D(sig000001c5),
.Q(sig00000185)
);
FDE #(
.INIT ( 1'b0 ))
blk00000118 (
.C(clk),
.CE(ce),
.D(sig000001c4),
.Q(sig00000186)
);
FDE #(
.INIT ( 1'b0 ))
blk00000119 (
.C(clk),
.CE(ce),
.D(sig000001c3),
.Q(sig00000187)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011a (
.C(clk),
.CE(ce),
.D(sig000001c2),
.Q(sig00000188)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011b (
.C(clk),
.CE(ce),
.D(sig000001be),
.Q(sig00000161)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011c (
.C(clk),
.CE(ce),
.D(sig000001bd),
.Q(sig00000162)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011d (
.C(clk),
.CE(ce),
.D(sig000001bc),
.Q(sig00000163)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011e (
.C(clk),
.CE(ce),
.D(sig000001bb),
.Q(sig00000164)
);
FDE #(
.INIT ( 1'b0 ))
blk0000011f (
.C(clk),
.CE(ce),
.D(sig000001ba),
.Q(sig00000165)
);
FDE #(
.INIT ( 1'b0 ))
blk00000120 (
.C(clk),
.CE(ce),
.D(sig000001b9),
.Q(sig00000166)
);
FDE #(
.INIT ( 1'b0 ))
blk00000121 (
.C(clk),
.CE(ce),
.D(sig000001b8),
.Q(sig00000167)
);
FDE #(
.INIT ( 1'b0 ))
blk00000122 (
.C(clk),
.CE(ce),
.D(sig000001b7),
.Q(sig00000168)
);
FDE #(
.INIT ( 1'b0 ))
blk00000123 (
.C(clk),
.CE(ce),
.D(sig000001b6),
.Q(sig00000169)
);
FDE #(
.INIT ( 1'b0 ))
blk00000124 (
.C(clk),
.CE(ce),
.D(sig000001b5),
.Q(sig0000016a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000125 (
.C(clk),
.CE(ce),
.D(sig000001b4),
.Q(sig0000016b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000126 (
.C(clk),
.CE(ce),
.D(sig000001b3),
.Q(sig0000016c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000127 (
.C(clk),
.CE(ce),
.D(sig000001b2),
.Q(sig0000016d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000128 (
.C(clk),
.CE(ce),
.D(sig000001b1),
.Q(sig0000016e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000129 (
.C(clk),
.CE(ce),
.D(sig000001b0),
.Q(sig0000016f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012a (
.C(clk),
.CE(ce),
.D(sig000001af),
.Q(sig00000170)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012b (
.C(clk),
.CE(ce),
.D(sig000001ae),
.Q(sig00000171)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012c (
.C(clk),
.CE(ce),
.D(sig000001ad),
.Q(sig00000172)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012d (
.C(clk),
.CE(ce),
.D(sig000001ac),
.Q(sig00000173)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012e (
.C(clk),
.CE(ce),
.D(sig000001ab),
.Q(sig00000174)
);
FDE #(
.INIT ( 1'b0 ))
blk0000012f (
.C(clk),
.CE(ce),
.D(sig000001aa),
.Q(sig00000175)
);
FDE #(
.INIT ( 1'b0 ))
blk00000130 (
.C(clk),
.CE(ce),
.D(sig000001a9),
.Q(sig00000176)
);
FDE #(
.INIT ( 1'b0 ))
blk00000131 (
.C(clk),
.CE(ce),
.D(sig000001a8),
.Q(sig00000177)
);
FDE #(
.INIT ( 1'b0 ))
blk00000132 (
.C(clk),
.CE(ce),
.D(sig000001a7),
.Q(sig00000178)
);
FDE #(
.INIT ( 1'b0 ))
blk00000133 (
.C(clk),
.CE(ce),
.D(sig0000022a),
.Q(sig00000223)
);
FDE #(
.INIT ( 1'b0 ))
blk00000134 (
.C(clk),
.CE(ce),
.D(sig00000223),
.Q(sig0000022b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000135 (
.C(clk),
.CE(ce),
.D(sig00000229),
.Q(sig00000224)
);
FDE #(
.INIT ( 1'b0 ))
blk00000136 (
.C(clk),
.CE(ce),
.D(sig00000224),
.Q(sig0000022f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000137 (
.C(clk),
.CE(ce),
.D(sig00000228),
.Q(sig00000225)
);
FDE #(
.INIT ( 1'b0 ))
blk00000138 (
.C(clk),
.CE(ce),
.D(sig00000225),
.Q(sig0000022e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000139 (
.C(clk),
.CE(ce),
.D(sig00000227),
.Q(sig00000231)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013a (
.C(clk),
.CE(ce),
.D(sig00000232),
.Q(sig00000230)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013b (
.C(clk),
.CE(ce),
.D(sig00000226),
.Q(sig0000022d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013c (
.C(clk),
.CE(ce),
.D(sig00000286),
.Q(sig0000024d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013d (
.C(clk),
.CE(ce),
.D(sig00000283),
.Q(sig0000024e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013e (
.C(clk),
.CE(ce),
.D(sig00000282),
.Q(sig0000024f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000013f (
.C(clk),
.CE(ce),
.D(sig00000281),
.Q(sig00000250)
);
FDE #(
.INIT ( 1'b0 ))
blk00000140 (
.C(clk),
.CE(ce),
.D(sig00000280),
.Q(sig00000251)
);
FDE #(
.INIT ( 1'b0 ))
blk00000141 (
.C(clk),
.CE(ce),
.D(sig0000027d),
.Q(sig00000252)
);
FDE #(
.INIT ( 1'b0 ))
blk00000142 (
.C(clk),
.CE(ce),
.D(sig0000027c),
.Q(sig00000253)
);
FDE #(
.INIT ( 1'b0 ))
blk00000143 (
.C(clk),
.CE(ce),
.D(sig0000027b),
.Q(sig00000254)
);
FDE #(
.INIT ( 1'b0 ))
blk00000144 (
.C(clk),
.CE(ce),
.D(sig0000027a),
.Q(sig00000255)
);
FDE #(
.INIT ( 1'b0 ))
blk00000145 (
.C(clk),
.CE(ce),
.D(sig00000277),
.Q(sig00000256)
);
FDE #(
.INIT ( 1'b0 ))
blk00000146 (
.C(clk),
.CE(ce),
.D(sig00000276),
.Q(sig00000257)
);
FDE #(
.INIT ( 1'b0 ))
blk00000147 (
.C(clk),
.CE(ce),
.D(sig00000275),
.Q(sig00000258)
);
FDE #(
.INIT ( 1'b0 ))
blk00000148 (
.C(clk),
.CE(ce),
.D(sig00000274),
.Q(sig00000259)
);
FDE #(
.INIT ( 1'b0 ))
blk00000149 (
.C(clk),
.CE(ce),
.D(sig00000271),
.Q(sig0000025a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014a (
.C(clk),
.CE(ce),
.D(sig00000270),
.Q(sig0000025b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014b (
.C(clk),
.CE(ce),
.D(sig0000026f),
.Q(sig0000025c)
);
MUXCY blk0000014c (
.CI(sig0000025e),
.DI(sig00000002),
.S(sig00000265),
.O(sig0000025d)
);
MUXCY blk0000014d (
.CI(sig0000025f),
.DI(sig00000002),
.S(sig00000266),
.O(sig0000025e)
);
MUXCY blk0000014e (
.CI(sig00000260),
.DI(sig00000002),
.S(sig00000267),
.O(sig0000025f)
);
MUXCY blk0000014f (
.CI(sig00000261),
.DI(sig00000002),
.S(sig00000268),
.O(sig00000260)
);
MUXCY blk00000150 (
.CI(sig00000262),
.DI(sig00000002),
.S(sig00000269),
.O(sig00000261)
);
MUXCY blk00000151 (
.CI(sig00000263),
.DI(sig00000002),
.S(sig0000026a),
.O(sig00000262)
);
MUXCY blk00000152 (
.CI(sig00000264),
.DI(sig00000002),
.S(sig0000026b),
.O(sig00000263)
);
MUXCY blk00000153 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig0000026c),
.O(sig00000264)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk00000154 (
.I0(sig00000002),
.I1(sig0000023d),
.I2(sig0000023e),
.I3(sig0000023f),
.I4(sig00000240),
.O(sig00000272)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk00000155 (
.I0(sig00000002),
.I1(sig0000023d),
.I2(sig0000023e),
.I3(sig0000023f),
.I4(sig00000240),
.O(sig00000273)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk00000156 (
.I0(sig00000002),
.I1(sig00000241),
.I2(sig00000242),
.I3(sig00000243),
.I4(sig00000244),
.O(sig00000278)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk00000157 (
.I0(sig00000002),
.I1(sig00000241),
.I2(sig00000242),
.I3(sig00000243),
.I4(sig00000244),
.O(sig00000279)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk00000158 (
.I0(sig00000002),
.I1(sig00000245),
.I2(sig00000246),
.I3(sig00000247),
.I4(sig00000248),
.O(sig0000027e)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk00000159 (
.I0(sig00000002),
.I1(sig00000245),
.I2(sig00000246),
.I3(sig00000247),
.I4(sig00000248),
.O(sig0000027f)
);
LUT5 #(
.INIT ( 32'h000000FC ))
blk0000015a (
.I0(sig00000002),
.I1(sig00000249),
.I2(sig0000024a),
.I3(sig0000024c),
.I4(sig0000024b),
.O(sig00000284)
);
LUT5 #(
.INIT ( 32'h0000FF0C ))
blk0000015b (
.I0(sig00000002),
.I1(sig00000249),
.I2(sig0000024a),
.I3(sig0000024c),
.I4(sig0000024b),
.O(sig00000285)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(ce),
.D(sig0000026e),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015d (
.C(clk),
.CE(ce),
.D(sig0000026d),
.Q(sig0000006a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(ce),
.D(sig00000287),
.Q(sig00000069)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015f (
.C(clk),
.CE(ce),
.D(sig0000028c),
.Q(sig00000068)
);
FDE #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.CE(ce),
.D(sig00000290),
.Q(sig00000067)
);
FDE #(
.INIT ( 1'b0 ))
blk00000161 (
.C(clk),
.CE(ce),
.D(sig00000066),
.Q(sig00000290)
);
FDE #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.CE(ce),
.D(sig0000025d),
.Q(sig00000288)
);
FDE #(
.INIT ( 1'b0 ))
blk00000163 (
.C(clk),
.CE(ce),
.D(sig0000025e),
.Q(sig00000289)
);
FDE #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.CE(ce),
.D(sig0000025f),
.Q(sig0000028a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000165 (
.C(clk),
.CE(ce),
.D(sig00000260),
.Q(sig0000028b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.CE(ce),
.D(sig00000261),
.Q(sig0000028c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000167 (
.C(clk),
.CE(ce),
.D(sig00000262),
.Q(sig0000028d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.CE(ce),
.D(sig00000263),
.Q(sig0000028e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000169 (
.C(clk),
.CE(ce),
.D(sig00000264),
.Q(sig0000028f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.CE(ce),
.D(sig000002aa),
.Q(sig0000024b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016b (
.C(clk),
.CE(ce),
.D(sig000002a9),
.Q(sig0000024c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016c (
.C(clk),
.CE(ce),
.D(sig000002a8),
.Q(sig0000024a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016d (
.C(clk),
.CE(ce),
.D(sig000002a7),
.Q(sig00000249)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016e (
.C(clk),
.CE(ce),
.D(sig000002a6),
.Q(sig00000248)
);
FDE #(
.INIT ( 1'b0 ))
blk0000016f (
.C(clk),
.CE(ce),
.D(sig000002a5),
.Q(sig00000247)
);
FDE #(
.INIT ( 1'b0 ))
blk00000170 (
.C(clk),
.CE(ce),
.D(sig000002a4),
.Q(sig00000246)
);
FDE #(
.INIT ( 1'b0 ))
blk00000171 (
.C(clk),
.CE(ce),
.D(sig000002a3),
.Q(sig00000245)
);
FDE #(
.INIT ( 1'b0 ))
blk00000172 (
.C(clk),
.CE(ce),
.D(sig000002a2),
.Q(sig00000244)
);
FDE #(
.INIT ( 1'b0 ))
blk00000173 (
.C(clk),
.CE(ce),
.D(sig000002a1),
.Q(sig00000243)
);
FDE #(
.INIT ( 1'b0 ))
blk00000174 (
.C(clk),
.CE(ce),
.D(sig000002a0),
.Q(sig00000242)
);
FDE #(
.INIT ( 1'b0 ))
blk00000175 (
.C(clk),
.CE(ce),
.D(sig0000029f),
.Q(sig00000241)
);
FDE #(
.INIT ( 1'b0 ))
blk00000176 (
.C(clk),
.CE(ce),
.D(sig0000029e),
.Q(sig00000240)
);
FDE #(
.INIT ( 1'b0 ))
blk00000177 (
.C(clk),
.CE(ce),
.D(sig0000029d),
.Q(sig0000023f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000178 (
.C(clk),
.CE(ce),
.D(sig0000029c),
.Q(sig0000023e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000179 (
.C(clk),
.CE(ce),
.D(sig0000029b),
.Q(sig0000023d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017a (
.C(clk),
.CE(ce),
.D(sig0000029a),
.Q(sig0000023c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017b (
.C(clk),
.CE(ce),
.D(sig00000299),
.Q(sig0000023b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017c (
.C(clk),
.CE(ce),
.D(sig00000298),
.Q(sig0000023a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017d (
.C(clk),
.CE(ce),
.D(sig00000297),
.Q(sig00000239)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017e (
.C(clk),
.CE(ce),
.D(sig00000296),
.Q(sig00000238)
);
FDE #(
.INIT ( 1'b0 ))
blk0000017f (
.C(clk),
.CE(ce),
.D(sig00000295),
.Q(sig00000237)
);
FDE #(
.INIT ( 1'b0 ))
blk00000180 (
.C(clk),
.CE(ce),
.D(sig00000294),
.Q(sig00000236)
);
FDE #(
.INIT ( 1'b0 ))
blk00000181 (
.C(clk),
.CE(ce),
.D(sig00000293),
.Q(sig00000235)
);
FDE #(
.INIT ( 1'b0 ))
blk00000182 (
.C(clk),
.CE(ce),
.D(sig00000292),
.Q(sig00000234)
);
FDE #(
.INIT ( 1'b0 ))
blk00000183 (
.C(clk),
.CE(ce),
.D(sig00000291),
.Q(sig00000233)
);
FD blk00000184 (
.C(clk),
.D(sig000002c1),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [22])
);
FD blk00000185 (
.C(clk),
.D(sig000002c0),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [21])
);
FD blk00000186 (
.C(clk),
.D(sig000002bf),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [20])
);
FD blk00000187 (
.C(clk),
.D(sig000002be),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [19])
);
FD blk00000188 (
.C(clk),
.D(sig000002bd),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [18])
);
FD blk00000189 (
.C(clk),
.D(sig000002bc),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [17])
);
FD blk0000018a (
.C(clk),
.D(sig000002bb),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [16])
);
FD blk0000018b (
.C(clk),
.D(sig000002ba),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [15])
);
FD blk0000018c (
.C(clk),
.D(sig000002b9),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [14])
);
FD blk0000018d (
.C(clk),
.D(sig000002b8),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [13])
);
FD blk0000018e (
.C(clk),
.D(sig000002b7),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [12])
);
FD blk0000018f (
.C(clk),
.D(sig000002b6),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [11])
);
FD blk00000190 (
.C(clk),
.D(sig000002b5),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [10])
);
FD blk00000191 (
.C(clk),
.D(sig000002b4),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [9])
);
FD blk00000192 (
.C(clk),
.D(sig000002b3),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [8])
);
FD blk00000193 (
.C(clk),
.D(sig000002b2),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [7])
);
FD blk00000194 (
.C(clk),
.D(sig000002b1),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [6])
);
FD blk00000195 (
.C(clk),
.D(sig000002b0),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [5])
);
FD blk00000196 (
.C(clk),
.D(sig000002af),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [4])
);
FD blk00000197 (
.C(clk),
.D(sig000002ae),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [3])
);
FD blk00000198 (
.C(clk),
.D(sig000002ad),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [2])
);
FD blk00000199 (
.C(clk),
.D(sig000002ac),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [1])
);
FD blk0000019a (
.C(clk),
.D(sig000002ab),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [0])
);
LUT4 #(
.INIT ( 16'hAA8A ))
blk0000019b (
.I0(sig000000f4),
.I1(sig000000f6),
.I2(sig00000110),
.I3(sig000000f5),
.O(sig000000cd)
);
LUT4 #(
.INIT ( 16'hEA2A ))
blk0000019c (
.I0(sig000000fe),
.I1(sig00000115),
.I2(sig00000116),
.I3(sig000000ff),
.O(sig000000d1)
);
LUT4 #(
.INIT ( 16'hF888 ))
blk0000019d (
.I0(sig00000112),
.I1(sig00000113),
.I2(sig00000115),
.I3(sig00000116),
.O(sig000000c2)
);
LUT4 #(
.INIT ( 16'h8000 ))
blk0000019e (
.I0(sig00000112),
.I1(sig00000113),
.I2(sig00000115),
.I3(sig00000116),
.O(sig000000c3)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk0000019f (
.I0(sig00000110),
.I1(sig000000e0),
.I2(sig000000e2),
.I3(sig000000e1),
.I4(sig000000f5),
.I5(sig000000f6),
.O(sig000000ad)
);
LUT5 #(
.INIT ( 32'h55555554 ))
blk000001a0 (
.I0(sig000000f5),
.I1(sig00000110),
.I2(sig000000f6),
.I3(sig000000e2),
.I4(sig000000e1),
.O(sig000000af)
);
LUT5 #(
.INIT ( 32'hFFFF1504 ))
blk000001a1 (
.I0(sig000000fc),
.I1(sig000000fb),
.I2(sig000001a4),
.I3(sig000000f9),
.I4(sig000000fd),
.O(sig000000d0)
);
LUT4 #(
.INIT ( 16'h5554 ))
blk000001a2 (
.I0(sig000000fd),
.I1(sig000000fb),
.I2(sig000000f9),
.I3(sig000000fc),
.O(sig000000cf)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF55555554 ))
blk000001a3 (
.I0(sig000000f5),
.I1(sig00000110),
.I2(sig000000e0),
.I3(sig000000e2),
.I4(sig000000e1),
.I5(sig000000f6),
.O(sig000000df)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000001a4 (
.I0(sig000000f6),
.I1(sig000000f5),
.O(sig000000ae)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAABAA ))
blk000001a5 (
.I0(sig000000f5),
.I1(sig00000110),
.I2(sig000000f6),
.I3(sig000000e0),
.I4(sig000000e2),
.I5(sig000000e1),
.O(sig000000de)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a6 (
.I0(sig00000003),
.I1(sig00000109),
.I2(sig00000101),
.O(sig000000b7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a7 (
.I0(sig00000003),
.I1(sig0000010a),
.I2(sig00000102),
.O(sig000000b8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a8 (
.I0(sig00000003),
.I1(sig0000010b),
.I2(sig00000103),
.O(sig000000b9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001a9 (
.I0(sig00000003),
.I1(sig0000010c),
.I2(sig00000104),
.O(sig000000ba)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001aa (
.I0(sig00000003),
.I1(sig0000010d),
.I2(sig00000105),
.O(sig000000bb)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ab (
.I0(sig00000003),
.I1(sig0000010e),
.I2(sig00000106),
.O(sig000000bc)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ac (
.I0(sig00000003),
.I1(sig0000010f),
.I2(sig00000107),
.O(sig000000bd)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ad (
.I0(sig00000019),
.I1(sig000000fe),
.I2(sig000000ff),
.O(sig000000d3)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001ae (
.I0(sig000000ff),
.I1(sig000000fe),
.O(sig000000c0)
);
LUT3 #(
.INIT ( 8'h1B ))
blk000001af (
.I0(sig00000003),
.I1(sig00000100),
.I2(sig00000108),
.O(sig000000b6)
);
LUT4 #(
.INIT ( 16'h22F2 ))
blk000001b0 (
.I0(sig00000115),
.I1(sig00000116),
.I2(sig00000112),
.I3(sig00000113),
.O(sig000000c1)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000001b1 (
.I0(sig000000ff),
.I1(sig000000fe),
.O(sig000000d2)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000001b2 (
.I0(sig00000111),
.I1(sig00000114),
.O(sig0000001a)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b3 (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000011b)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b4 (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000011c)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b5 (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000011d)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk000001b6 (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.O(sig0000011e)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b7 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000123)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b8 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000124)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001b9 (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000125)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk000001ba (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.O(sig00000126)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bb (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000134)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bc (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000136)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bd (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig00000138)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001be (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig0000013a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001bf (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000013c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c0 (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig0000013e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c1 (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig00000140)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c2 (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000142)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c3 (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000144)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c4 (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig0000012a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c5 (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000012c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c6 (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig0000012e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c7 (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig00000130)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c8 (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000132)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk000001c9 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000146)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001ca (
.I0(b[29]),
.I1(a[29]),
.I2(b[28]),
.I3(a[28]),
.O(sig00000129)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cb (
.I0(b[27]),
.I1(a[27]),
.I2(b[26]),
.I3(a[26]),
.O(sig0000012b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cc (
.I0(b[25]),
.I1(a[25]),
.I2(b[24]),
.I3(a[24]),
.O(sig0000012d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cd (
.I0(b[23]),
.I1(a[23]),
.I2(b[22]),
.I3(a[22]),
.O(sig0000012f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001ce (
.I0(b[21]),
.I1(a[21]),
.I2(b[20]),
.I3(a[20]),
.O(sig00000131)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001cf (
.I0(b[19]),
.I1(a[19]),
.I2(b[18]),
.I3(a[18]),
.O(sig00000133)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d0 (
.I0(b[17]),
.I1(a[17]),
.I2(b[16]),
.I3(a[16]),
.O(sig00000135)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d1 (
.I0(b[15]),
.I1(a[15]),
.I2(b[14]),
.I3(a[14]),
.O(sig00000137)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d2 (
.I0(b[13]),
.I1(a[13]),
.I2(b[12]),
.I3(a[12]),
.O(sig00000139)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d3 (
.I0(b[11]),
.I1(a[11]),
.I2(b[10]),
.I3(a[10]),
.O(sig0000013b)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d4 (
.I0(b[9]),
.I1(a[9]),
.I2(b[8]),
.I3(a[8]),
.O(sig0000013d)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d5 (
.I0(b[7]),
.I1(a[7]),
.I2(b[6]),
.I3(a[6]),
.O(sig0000013f)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d6 (
.I0(b[5]),
.I1(a[5]),
.I2(b[4]),
.I3(a[4]),
.O(sig00000141)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d7 (
.I0(b[3]),
.I1(a[3]),
.I2(b[2]),
.I3(a[2]),
.O(sig00000143)
);
LUT4 #(
.INIT ( 16'h22B2 ))
blk000001d8 (
.I0(b[1]),
.I1(a[1]),
.I2(b[0]),
.I3(a[0]),
.O(sig00000145)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000001d9 (
.I0(a[30]),
.I1(b[30]),
.O(sig00000127)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000001da (
.I0(a[30]),
.I1(b[30]),
.O(sig00000128)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001db (
.I0(sig0000001c),
.I1(sig00000033),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001bd)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001dc (
.I0(sig0000001d),
.I1(sig00000034),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001bc)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001dd (
.I0(sig0000001e),
.I1(sig00000035),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001bb)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001de (
.I0(sig0000001f),
.I1(sig00000036),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001ba)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001df (
.I0(sig00000020),
.I1(sig00000037),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b9)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e0 (
.I0(sig00000021),
.I1(sig00000038),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b8)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e1 (
.I0(sig00000022),
.I1(sig00000039),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b7)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e2 (
.I0(sig00000023),
.I1(sig0000003a),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b6)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk000001e3 (
.I0(sig00000024),
.I1(sig0000003b),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e4 (
.I0(sig00000019),
.I1(sig00000049),
.I2(sig00000032),
.O(sig000001d4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e5 (
.I0(sig00000019),
.I1(sig0000003f),
.I2(sig00000028),
.O(sig000001de)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e6 (
.I0(sig00000019),
.I1(sig0000003e),
.I2(sig00000027),
.O(sig000001df)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e7 (
.I0(sig00000019),
.I1(sig0000003d),
.I2(sig00000026),
.O(sig000001e0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e8 (
.I0(sig00000019),
.I1(sig0000003c),
.I2(sig00000025),
.O(sig000001e1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001e9 (
.I0(sig00000019),
.I1(sig0000003b),
.I2(sig00000024),
.O(sig000001e2)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ea (
.I0(sig00000019),
.I1(sig0000003a),
.I2(sig00000023),
.O(sig000001e3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001eb (
.I0(sig00000019),
.I1(sig00000039),
.I2(sig00000022),
.O(sig000001e4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ec (
.I0(sig00000019),
.I1(sig00000038),
.I2(sig00000021),
.O(sig000001e5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ed (
.I0(sig00000019),
.I1(sig00000037),
.I2(sig00000020),
.O(sig000001e6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ee (
.I0(sig00000019),
.I1(sig00000036),
.I2(sig0000001f),
.O(sig000001e7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ef (
.I0(sig00000019),
.I1(sig00000048),
.I2(sig00000031),
.O(sig000001d5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f0 (
.I0(sig00000019),
.I1(sig00000035),
.I2(sig0000001e),
.O(sig000001e8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f1 (
.I0(sig00000019),
.I1(sig00000034),
.I2(sig0000001d),
.O(sig000001e9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f2 (
.I0(sig00000019),
.I1(sig00000033),
.I2(sig0000001c),
.O(sig000001ea)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f3 (
.I0(sig00000019),
.I1(sig00000047),
.I2(sig00000030),
.O(sig000001d6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f4 (
.I0(sig00000019),
.I1(sig00000046),
.I2(sig0000002f),
.O(sig000001d7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f5 (
.I0(sig00000019),
.I1(sig00000045),
.I2(sig0000002e),
.O(sig000001d8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f6 (
.I0(sig00000019),
.I1(sig00000044),
.I2(sig0000002d),
.O(sig000001d9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f7 (
.I0(sig00000019),
.I1(sig00000043),
.I2(sig0000002c),
.O(sig000001da)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f8 (
.I0(sig00000019),
.I1(sig00000042),
.I2(sig0000002b),
.O(sig000001db)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001f9 (
.I0(sig00000019),
.I1(sig00000041),
.I2(sig0000002a),
.O(sig000001dc)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001fa (
.I0(sig00000019),
.I1(sig00000040),
.I2(sig00000029),
.O(sig000001dd)
);
LUT2 #(
.INIT ( 4'h4 ))
blk000001fb (
.I0(sig000001fa),
.I1(sig000001a4),
.O(sig000001c0)
);
LUT4 #(
.INIT ( 16'h1537 ))
blk000001fc (
.I0(sig0000004a),
.I1(sig00000064),
.I2(sig0000004b),
.I3(sig00000063),
.O(sig00000227)
);
LUT3 #(
.INIT ( 8'hA2 ))
blk000001fd (
.I0(sig0000022f),
.I1(sig00000230),
.I2(sig0000022e),
.O(sig00000226)
);
LUT6 #(
.INIT ( 64'hFBEAEAEA51404040 ))
blk000001fe (
.I0(sig0000004a),
.I1(sig0000004b),
.I2(sig00000062),
.I3(sig00000063),
.I4(sig0000004c),
.I5(sig00000061),
.O(sig00000228)
);
LUT6 #(
.INIT ( 64'hFBEAEAEA51404040 ))
blk000001ff (
.I0(sig0000004a),
.I1(sig0000004b),
.I2(sig00000063),
.I3(sig00000064),
.I4(sig0000004c),
.I5(sig00000062),
.O(sig00000229)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000200 (
.I0(sig0000024c),
.I1(sig0000024b),
.O(sig0000022a)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000201 (
.I0(sig00000231),
.I1(sig00000065),
.O(sig00000232)
);
LUT3 #(
.INIT ( 8'hF1 ))
blk00000202 (
.I0(sig00000059),
.I1(sig00000058),
.I2(sig00000066),
.O(sig00000265)
);
LUT3 #(
.INIT ( 8'hF1 ))
blk00000203 (
.I0(sig00000057),
.I1(sig00000056),
.I2(sig00000066),
.O(sig00000266)
);
LUT4 #(
.INIT ( 16'h0F11 ))
blk00000204 (
.I0(sig00000055),
.I1(sig00000054),
.I2(sig00000064),
.I3(sig00000066),
.O(sig00000267)
);
LUT5 #(
.INIT ( 32'h000F1111 ))
blk00000205 (
.I0(sig00000053),
.I1(sig00000052),
.I2(sig00000062),
.I3(sig00000063),
.I4(sig00000066),
.O(sig00000268)
);
LUT5 #(
.INIT ( 32'h000F1111 ))
blk00000206 (
.I0(sig0000004f),
.I1(sig0000004e),
.I2(sig0000005f),
.I3(sig0000005e),
.I4(sig00000066),
.O(sig0000026a)
);
LUT5 #(
.INIT ( 32'h03030055 ))
blk00000207 (
.I0(sig0000004d),
.I1(sig0000005d),
.I2(sig0000005c),
.I3(sig0000004c),
.I4(sig00000066),
.O(sig0000026b)
);
LUT5 #(
.INIT ( 32'h000F1111 ))
blk00000208 (
.I0(sig00000051),
.I1(sig00000050),
.I2(sig00000060),
.I3(sig00000061),
.I4(sig00000066),
.O(sig00000269)
);
LUT5 #(
.INIT ( 32'h1111000F ))
blk00000209 (
.I0(sig0000005b),
.I1(sig0000005a),
.I2(sig0000004b),
.I3(sig0000004a),
.I4(sig00000066),
.O(sig0000026c)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000020a (
.I0(sig0000028c),
.I1(sig0000028a),
.I2(sig0000028e),
.O(sig00000287)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020b (
.I0(sig00000066),
.I1(sig0000005a),
.O(sig0000029a)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020c (
.I0(sig00000066),
.I1(sig00000059),
.O(sig0000029b)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020d (
.I0(sig00000066),
.I1(sig00000058),
.O(sig0000029c)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020e (
.I0(sig00000066),
.I1(sig00000057),
.O(sig0000029d)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000020f (
.I0(sig00000066),
.I1(sig00000056),
.O(sig0000029e)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000210 (
.I0(sig00000066),
.I1(sig00000055),
.O(sig0000029f)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000211 (
.I0(sig00000066),
.I1(sig00000064),
.I2(sig00000054),
.O(sig000002a0)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000212 (
.I0(sig00000066),
.I1(sig00000063),
.I2(sig00000053),
.O(sig000002a1)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000213 (
.I0(sig00000066),
.I1(sig00000062),
.I2(sig00000052),
.O(sig000002a2)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000214 (
.I0(sig00000066),
.I1(sig00000061),
.I2(sig00000051),
.O(sig000002a3)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000215 (
.I0(sig00000066),
.I1(sig00000063),
.O(sig00000291)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000216 (
.I0(sig00000066),
.I1(sig00000060),
.I2(sig00000050),
.O(sig000002a4)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000217 (
.I0(sig00000066),
.I1(sig0000005f),
.I2(sig0000004f),
.O(sig000002a5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000218 (
.I0(sig00000066),
.I1(sig0000005e),
.I2(sig0000004e),
.O(sig000002a6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000219 (
.I0(sig00000066),
.I1(sig0000005d),
.I2(sig0000004d),
.O(sig000002a7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000021a (
.I0(sig00000066),
.I1(sig0000005c),
.I2(sig0000004c),
.O(sig000002a8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000021b (
.I0(sig00000066),
.I1(sig0000005b),
.I2(sig0000004b),
.O(sig000002a9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000021c (
.I0(sig00000066),
.I1(sig0000005a),
.I2(sig0000004a),
.O(sig000002aa)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000021d (
.I0(sig00000066),
.I1(sig00000062),
.O(sig00000292)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000021e (
.I0(sig00000066),
.I1(sig00000061),
.O(sig00000293)
);
LUT2 #(
.INIT ( 4'h4 ))
blk0000021f (
.I0(sig00000066),
.I1(sig00000060),
.O(sig00000294)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000220 (
.I0(sig00000066),
.I1(sig0000005f),
.O(sig00000295)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000221 (
.I0(sig00000066),
.I1(sig0000005e),
.O(sig00000296)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000222 (
.I0(sig00000066),
.I1(sig0000005d),
.O(sig00000297)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000223 (
.I0(sig00000066),
.I1(sig0000005c),
.O(sig00000298)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000224 (
.I0(sig00000066),
.I1(sig0000005b),
.O(sig00000299)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000225 (
.I0(sig0000023d),
.I1(sig0000023e),
.I2(sig00000289),
.I3(sig00000288),
.O(sig0000026f)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000226 (
.I0(sig0000023e),
.I1(sig00000289),
.I2(sig00000288),
.O(sig00000270)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000227 (
.I0(sig0000023f),
.I1(sig00000240),
.I2(sig0000028a),
.I3(sig00000289),
.O(sig00000271)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000228 (
.I0(sig00000240),
.I1(sig0000028a),
.I2(sig00000289),
.O(sig00000274)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000229 (
.I0(sig00000241),
.I1(sig00000242),
.I2(sig0000028b),
.I3(sig0000028a),
.O(sig00000275)
);
LUT3 #(
.INIT ( 8'h08 ))
blk0000022a (
.I0(sig00000242),
.I1(sig0000028b),
.I2(sig0000028a),
.O(sig00000276)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk0000022b (
.I0(sig00000243),
.I1(sig00000244),
.I2(sig0000028c),
.I3(sig0000028b),
.O(sig00000277)
);
LUT3 #(
.INIT ( 8'h08 ))
blk0000022c (
.I0(sig00000244),
.I1(sig0000028c),
.I2(sig0000028b),
.O(sig0000027a)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk0000022d (
.I0(sig00000245),
.I1(sig00000246),
.I2(sig0000028d),
.I3(sig0000028c),
.O(sig0000027b)
);
LUT3 #(
.INIT ( 8'h08 ))
blk0000022e (
.I0(sig00000246),
.I1(sig0000028d),
.I2(sig0000028c),
.O(sig0000027c)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk0000022f (
.I0(sig00000247),
.I1(sig00000248),
.I2(sig0000028e),
.I3(sig0000028d),
.O(sig0000027d)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000230 (
.I0(sig00000248),
.I1(sig0000028e),
.I2(sig0000028d),
.O(sig00000280)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000231 (
.I0(sig00000249),
.I1(sig0000024a),
.I2(sig0000028f),
.I3(sig0000028e),
.O(sig00000281)
);
LUT3 #(
.INIT ( 8'h08 ))
blk00000232 (
.I0(sig0000024a),
.I1(sig0000028f),
.I2(sig0000028e),
.O(sig00000282)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000233 (
.I0(sig0000024c),
.I1(sig0000024b),
.I2(sig0000028f),
.O(sig00000283)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000234 (
.I0(sig0000028f),
.I1(sig0000024b),
.O(sig00000286)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000235 (
.I0(sig00000290),
.I1(sig00000288),
.O(sig0000008b)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000236 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000082),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [0]),
.O(sig000002ab)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000237 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000081),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [1]),
.O(sig000002ac)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000238 (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007f),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [3]),
.O(sig000002ae)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000239 (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007e),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [4]),
.O(sig000002af)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023a (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000080),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [2]),
.O(sig000002ad)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023b (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [5]),
.O(sig000002b0)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023c (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007c),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [6]),
.O(sig000002b1)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023d (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007b),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [7]),
.O(sig000002b2)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023e (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000007a),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [8]),
.O(sig000002b3)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023f (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000079),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [9]),
.O(sig000002b4)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000240 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000078),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [10]),
.O(sig000002b5)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000241 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000076),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [12]),
.O(sig000002b7)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000242 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000075),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [13]),
.O(sig000002b8)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000243 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000077),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [11]),
.O(sig000002b6)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000244 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000074),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [14]),
.O(sig000002b9)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000245 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000073),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [15]),
.O(sig000002ba)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000246 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000072),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [16]),
.O(sig000002bb)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000247 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000071),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [17]),
.O(sig000002bc)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000248 (
.I0(ce),
.I1(sig0000000c),
.I2(sig00000070),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [18]),
.O(sig000002bd)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000249 (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000006f),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [19]),
.O(sig000002be)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024a (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000006d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [21]),
.O(sig000002c0)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024b (
.I0(ce),
.I1(sig0000000c),
.I2(sig0000006e),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [20]),
.O(sig000002bf)
);
LUT5 #(
.INIT ( 32'h77752220 ))
blk0000024c (
.I0(ce),
.I1(sig0000000d),
.I2(sig0000000e),
.I3(sig0000006c),
.I4(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/mant_op [22]),
.O(sig000002c1)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000024d (
.I0(sig0000000f),
.I1(ce),
.O(sig000002c2)
);
LUT4 #(
.INIT ( 16'hF7FF ))
blk0000024e (
.I0(sig00000013),
.I1(sig00000015),
.I2(sig000000e3),
.I3(sig00000014),
.O(sig000002c3)
);
LUT6 #(
.INIT ( 64'h0000000080000000 ))
blk0000024f (
.I0(sig00000017),
.I1(sig00000018),
.I2(sig00000016),
.I3(sig00000011),
.I4(sig00000012),
.I5(sig000002c3),
.O(sig000000bf)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000250 (
.I0(sig000000f9),
.I1(sig000000f8),
.I2(sig000000f7),
.O(sig000002c4)
);
LUT5 #(
.INIT ( 32'hAA0BAA08 ))
blk00000251 (
.I0(sig000000fa),
.I1(sig000000fb),
.I2(sig000000fc),
.I3(sig000000fd),
.I4(sig000002c4),
.O(sig000000ce)
);
LUT3 #(
.INIT ( 8'h80 ))
blk00000252 (
.I0(a[25]),
.I1(a[24]),
.I2(a[23]),
.O(sig000002c5)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000253 (
.I0(a[30]),
.I1(a[29]),
.I2(a[28]),
.I3(a[27]),
.I4(a[26]),
.I5(sig000002c5),
.O(sig000000b2)
);
LUT3 #(
.INIT ( 8'hFE ))
blk00000254 (
.I0(a[25]),
.I1(a[24]),
.I2(a[23]),
.O(sig000002c6)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000255 (
.I0(a[30]),
.I1(a[29]),
.I2(a[28]),
.I3(a[27]),
.I4(a[26]),
.I5(sig000002c6),
.O(sig000000b3)
);
LUT3 #(
.INIT ( 8'h80 ))
blk00000256 (
.I0(b[25]),
.I1(b[24]),
.I2(b[23]),
.O(sig000002c7)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000257 (
.I0(b[30]),
.I1(b[29]),
.I2(b[28]),
.I3(b[27]),
.I4(b[26]),
.I5(sig000002c7),
.O(sig000000b4)
);
LUT3 #(
.INIT ( 8'hFE ))
blk00000258 (
.I0(b[25]),
.I1(b[24]),
.I2(b[23]),
.O(sig000002c8)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000259 (
.I0(b[30]),
.I1(b[29]),
.I2(b[28]),
.I3(b[27]),
.I4(b[26]),
.I5(sig000002c8),
.O(sig000000b5)
);
LUT4 #(
.INIT ( 16'hFFFE ))
blk0000025a (
.I0(sig00000013),
.I1(sig00000015),
.I2(sig00000014),
.I3(sig000000e3),
.O(sig000002c9)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000025b (
.I0(sig00000017),
.I1(sig00000018),
.I2(sig00000016),
.I3(sig00000011),
.I4(sig00000012),
.I5(sig000002c9),
.O(sig000000be)
);
LUT2 #(
.INIT ( 4'hE ))
blk0000025c (
.I0(sig00000111),
.I1(sig00000114),
.O(sig000002ca)
);
LUT6 #(
.INIT ( 64'h0000000000008001 ))
blk0000025d (
.I0(sig00000005),
.I1(sig00000004),
.I2(sig00000003),
.I3(sig00000006),
.I4(sig000002ca),
.I5(sig000001d2),
.O(sig000001c1)
);
LUT6 #(
.INIT ( 64'h0000000000010000 ))
blk0000025e (
.I0(sig000001ee),
.I1(sig000001ef),
.I2(sig000001f0),
.I3(sig000001f1),
.I4(sig000001f8),
.I5(sig000001f2),
.O(sig000002cb)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000025f (
.I0(sig000001f4),
.I1(sig000001f3),
.I2(sig000001f5),
.I3(sig000001f6),
.I4(sig000001eb),
.I5(sig000001ec),
.O(sig000002cc)
);
LUT4 #(
.INIT ( 16'h0020 ))
blk00000260 (
.I0(sig000002cc),
.I1(sig000001f7),
.I2(sig000002cb),
.I3(sig000001ed),
.O(sig000001bf)
);
LUT3 #(
.INIT ( 8'h1B ))
blk00000261 (
.I0(sig0000028e),
.I1(sig00000284),
.I2(sig0000027e),
.O(sig000002cd)
);
LUT5 #(
.INIT ( 32'h8A80DFD5 ))
blk00000262 (
.I0(sig0000028c),
.I1(sig00000272),
.I2(sig0000028a),
.I3(sig00000278),
.I4(sig000002cd),
.O(sig0000026d)
);
LUT3 #(
.INIT ( 8'h1B ))
blk00000263 (
.I0(sig0000028e),
.I1(sig00000285),
.I2(sig0000027f),
.O(sig000002ce)
);
LUT5 #(
.INIT ( 32'h8A80DFD5 ))
blk00000264 (
.I0(sig0000028c),
.I1(sig00000273),
.I2(sig0000028a),
.I3(sig00000279),
.I4(sig000002ce),
.O(sig0000026e)
);
FDRE blk00000265 (
.C(clk),
.CE(ce),
.D(sig000002cf),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [7])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000266 (
.I0(sig00000083),
.I1(sig00000010),
.O(sig000002cf)
);
FDRE blk00000267 (
.C(clk),
.CE(ce),
.D(sig000002d0),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [6])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000268 (
.I0(sig00000084),
.I1(sig00000010),
.O(sig000002d0)
);
FDRE blk00000269 (
.C(clk),
.CE(ce),
.D(sig000002d1),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [5])
);
LUT2 #(
.INIT ( 4'hE ))
blk0000026a (
.I0(sig00000085),
.I1(sig00000010),
.O(sig000002d1)
);
FDRE blk0000026b (
.C(clk),
.CE(ce),
.D(sig000002d2),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [4])
);
LUT2 #(
.INIT ( 4'hE ))
blk0000026c (
.I0(sig00000086),
.I1(sig00000010),
.O(sig000002d2)
);
FDRE blk0000026d (
.C(clk),
.CE(ce),
.D(sig000002d3),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [3])
);
LUT2 #(
.INIT ( 4'hE ))
blk0000026e (
.I0(sig00000087),
.I1(sig00000010),
.O(sig000002d3)
);
FDRE blk0000026f (
.C(clk),
.CE(ce),
.D(sig000002d4),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [2])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000270 (
.I0(sig00000088),
.I1(sig00000010),
.O(sig000002d4)
);
FDRE blk00000271 (
.C(clk),
.CE(ce),
.D(sig000002d5),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [1])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000272 (
.I0(sig00000089),
.I1(sig00000010),
.O(sig000002d5)
);
FDRE blk00000273 (
.C(clk),
.CE(ce),
.D(sig000002d6),
.R(sig000002c2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/exp_op [0])
);
LUT2 #(
.INIT ( 4'hE ))
blk00000274 (
.I0(sig0000008a),
.I1(sig00000010),
.O(sig000002d6)
);
FDE blk00000275 (
.C(clk),
.CE(ce),
.D(sig0000001b),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.DSP.OP/OP/sign_op )
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000276 (
.I0(sig000001d3),
.O(sig000002d7)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000277 (
.I0(sig00000019),
.I1(sig00000031),
.I2(sig00000032),
.I3(sig00000048),
.I4(sig00000049),
.O(sig00000222)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000278 (
.I0(sig00000019),
.I1(sig0000002f),
.I2(sig00000030),
.I3(sig00000046),
.I4(sig00000047),
.O(sig00000221)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000279 (
.I0(sig00000046),
.I1(sig0000002f),
.I2(sig00000021),
.I3(sig00000038),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001aa)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000027a (
.I0(sig00000047),
.I1(sig00000030),
.I2(sig00000022),
.I3(sig00000039),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001a9)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000027b (
.I0(sig00000048),
.I1(sig00000031),
.I2(sig00000023),
.I3(sig0000003a),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001a8)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk0000027c (
.I0(sig00000049),
.I1(sig00000032),
.I2(sig00000024),
.I3(sig0000003b),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001a7)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk0000027d (
.I0(sig00000019),
.I1(sig0000002e),
.I2(sig0000002d),
.I3(sig00000045),
.I4(sig00000044),
.O(sig00000220)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk0000027e (
.I0(sig00000019),
.I1(sig0000002c),
.I2(sig0000002b),
.I3(sig00000043),
.I4(sig00000042),
.O(sig0000021f)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk0000027f (
.I0(sig00000019),
.I1(sig0000002a),
.I2(sig00000029),
.I3(sig00000041),
.I4(sig00000040),
.O(sig0000021e)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000280 (
.I0(sig00000019),
.I1(sig00000028),
.I2(sig00000027),
.I3(sig0000003f),
.I4(sig0000003e),
.O(sig0000021d)
);
LUT5 #(
.INIT ( 32'h02020257 ))
blk00000281 (
.I0(sig00000019),
.I1(sig00000026),
.I2(sig00000025),
.I3(sig0000003d),
.I4(sig0000003c),
.O(sig0000021c)
);
LUT2 #(
.INIT ( 4'h7 ))
blk00000282 (
.I0(sig00000111),
.I1(sig00000114),
.O(sig000001fd)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000283 (
.I0(sig00000041),
.I1(sig0000002a),
.I2(sig0000001c),
.I3(sig00000033),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001af)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000284 (
.I0(sig00000042),
.I1(sig0000002b),
.I2(sig0000001d),
.I3(sig00000034),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001ae)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000285 (
.I0(sig00000043),
.I1(sig0000002c),
.I2(sig0000001e),
.I3(sig00000035),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001ad)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000286 (
.I0(sig00000044),
.I1(sig0000002d),
.I2(sig0000001f),
.I3(sig00000036),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001ac)
);
LUT6 #(
.INIT ( 64'hF0F0FF00CCCCAAAA ))
blk00000287 (
.I0(sig00000045),
.I1(sig0000002e),
.I2(sig00000020),
.I3(sig00000037),
.I4(sig00000019),
.I5(sig000001d3),
.O(sig000001ab)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk00000288 (
.I0(sig00000028),
.I1(sig0000003f),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b1)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk00000289 (
.I0(sig00000027),
.I1(sig0000003e),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b2)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk0000028a (
.I0(sig00000026),
.I1(sig0000003d),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b3)
);
LUT4 #(
.INIT ( 16'h00AC ))
blk0000028b (
.I0(sig00000025),
.I1(sig0000003c),
.I2(sig00000019),
.I3(sig000001d3),
.O(sig000001b4)
);
LUT4 #(
.INIT ( 16'hFFD8 ))
blk0000028c (
.I0(sig00000019),
.I1(sig00000029),
.I2(sig00000040),
.I3(sig000001d3),
.O(sig000001b0)
);
INV blk0000028d (
.I(b[31]),
.O(sig000000d4)
);
INV blk0000028e (
.I(sig000001d3),
.O(sig000001be)
);
INV blk0000028f (
.I(sig000000e9),
.O(sig00000092)
);
INV blk00000290 (
.I(sig000000ea),
.O(sig00000090)
);
INV blk00000291 (
.I(sig000000eb),
.O(sig0000008e)
);
LUT6 #(
.INIT ( 64'h0818181018181810 ))
blk00000292 (
.I0(sig00000008),
.I1(sig00000007),
.I2(sig00000006),
.I3(sig0000000a),
.I4(sig00000009),
.I5(sig0000000b),
.O(sig000001d2)
);
LUT6 #(
.INIT ( 64'h666666666666666A ))
blk00000293 (
.I0(sig00000007),
.I1(sig00000006),
.I2(sig00000008),
.I3(sig00000009),
.I4(sig0000000a),
.I5(sig0000000b),
.O(sig000001d3)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk00000294 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.O(sig000001d1)
);
LUT6 #(
.INIT ( 64'h8000000000000002 ))
blk00000295 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001d0)
);
LUT6 #(
.INIT ( 64'h4001000000010004 ))
blk00000296 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001cf)
);
LUT6 #(
.INIT ( 64'h2800000000000028 ))
blk00000297 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000007),
.I3(sig00000009),
.I4(sig00000008),
.I5(sig00000006),
.O(sig000001ce)
);
LUT6 #(
.INIT ( 64'h0400400000100004 ))
blk00000298 (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001cd)
);
LUT6 #(
.INIT ( 64'h0820000000000820 ))
blk00000299 (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000007),
.I4(sig00000008),
.I5(sig00000006),
.O(sig000001cc)
);
LUT6 #(
.INIT ( 64'h1000040000040040 ))
blk0000029a (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001cb)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk0000029b (
.I0(sig0000000b),
.I1(sig00000007),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig00000008),
.I5(sig00000009),
.O(sig000001ca)
);
LUT6 #(
.INIT ( 64'h0010100004000010 ))
blk0000029c (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig00000008),
.I3(sig0000000a),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001c9)
);
LUT5 #(
.INIT ( 32'h00800200 ))
blk0000029d (
.I0(sig0000000b),
.I1(sig0000000a),
.I2(sig00000009),
.I3(sig00000008),
.I4(sig00000007),
.O(sig000001c8)
);
LUT6 #(
.INIT ( 64'h0400001000101000 ))
blk0000029e (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig00000008),
.I3(sig0000000a),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001c7)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk0000029f (
.I0(sig0000000b),
.I1(sig00000007),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig00000009),
.I5(sig00000008),
.O(sig000001c6)
);
LUT6 #(
.INIT ( 64'h0010000404004000 ))
blk000002a0 (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000006),
.I4(sig00000007),
.I5(sig00000008),
.O(sig000001c5)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk000002a1 (
.I0(sig0000000b),
.I1(sig00000006),
.I2(sig00000008),
.I3(sig00000007),
.I4(sig0000000a),
.I5(sig00000009),
.O(sig000001c4)
);
LUT6 #(
.INIT ( 64'h0010000404004000 ))
blk000002a2 (
.I0(sig0000000b),
.I1(sig00000009),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000007),
.I5(sig00000006),
.O(sig000001c3)
);
LUT6 #(
.INIT ( 64'h0000002828000000 ))
blk000002a3 (
.I0(sig0000000b),
.I1(sig00000007),
.I2(sig0000000a),
.I3(sig00000008),
.I4(sig00000009),
.I5(sig00000006),
.O(sig000001c2)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a4 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000b0),
.Q(sig000002d8),
.Q15(NLW_blk000002a4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a5 (
.C(clk),
.CE(ce),
.D(sig000002d8),
.Q(sig000000f4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a6 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000b1),
.Q(sig000002d9),
.Q15(NLW_blk000002a6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a7 (
.C(clk),
.CE(ce),
.D(sig000002d9),
.Q(sig00000110)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a8 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig00000158),
.Q(sig000002da),
.Q15(NLW_blk000002a8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a9 (
.C(clk),
.CE(ce),
.D(sig000002da),
.Q(sig000000f6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002aa (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig00000157),
.Q(sig000002db),
.Q15(NLW_blk000002aa_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ab (
.C(clk),
.CE(ce),
.D(sig000002db),
.Q(sig000000f5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ac (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000f1),
.Q(sig000002dc),
.Q15(NLW_blk000002ac_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ad (
.C(clk),
.CE(ce),
.D(sig000002dc),
.Q(sig000000e9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ae (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000f3),
.Q(sig000002dd),
.Q15(NLW_blk000002ae_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002af (
.C(clk),
.CE(ce),
.D(sig000002dd),
.Q(sig000000eb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b0 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000f2),
.Q(sig000002de),
.Q15(NLW_blk000002b0_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b1 (
.C(clk),
.CE(ce),
.D(sig000002de),
.Q(sig000000ea)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b2 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000f0),
.Q(sig000002df),
.Q15(NLW_blk000002b2_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b3 (
.C(clk),
.CE(ce),
.D(sig000002df),
.Q(sig000000e8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b4 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ef),
.Q(sig000002e0),
.Q15(NLW_blk000002b4_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b5 (
.C(clk),
.CE(ce),
.D(sig000002e0),
.Q(sig000000e7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b6 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ee),
.Q(sig000002e1),
.Q15(NLW_blk000002b6_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b7 (
.C(clk),
.CE(ce),
.D(sig000002e1),
.Q(sig000000e6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b8 (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ed),
.Q(sig000002e2),
.Q15(NLW_blk000002b8_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b9 (
.C(clk),
.CE(ce),
.D(sig000002e2),
.Q(sig000000e5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ba (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig0000024c),
.Q(sig000002e3),
.Q15(NLW_blk000002ba_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002bb (
.C(clk),
.CE(ce),
.D(sig000002e3),
.Q(sig0000022c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002bc (
.A0(sig00000002),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000000ec),
.Q(sig000002e4),
.Q15(NLW_blk000002bc_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002bd (
.C(clk),
.CE(ce),
.D(sig000002e4),
.Q(sig000000e4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002be (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000002),
.A3(sig00000002),
.CE(ce),
.CLK(clk),
.D(sig000001fa),
.Q(sig000002e5),
.Q15(NLW_blk000002be_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002bf (
.C(clk),
.CE(ce),
.D(sig000002e5),
.Q(sig000001f8)
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 1 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( 0),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'hFF0000FFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "PATDET" ),
.USE_SIMD ( "ONE48" ))
blk000002c0 (
.CEM(ce),
.PATTERNDETECT(sig00000066),
.CLK(clk),
.CARRYIN(sig000001f9),
.PATTERNBDETECT(NLW_blk000002c0_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000002),
.CEB1(sig00000002),
.MULTSIGNOUT(NLW_blk000002c0_MULTSIGNOUT_UNCONNECTED),
.CEC(ce),
.RSTM(sig00000002),
.MULTSIGNIN(sig00000002),
.CEB2(ce),
.RSTCTRL(sig00000002),
.CEP(ce),
.CARRYCASCOUT(NLW_blk000002c0_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000002),
.CECARRYIN(ce),
.UNDERFLOW(NLW_blk000002c0_UNDERFLOW_UNCONNECTED),
.RSTALUMODE(sig00000002),
.RSTALLCARRYIN(sig00000002),
.CEALUMODE(ce),
.CEA2(ce),
.CEA1(sig00000002),
.RSTB(sig00000002),
.CEMULTCARRYIN(sig00000002),
.OVERFLOW(NLW_blk000002c0_OVERFLOW_UNCONNECTED),
.CECTRL(ce),
.CARRYCASCIN(sig00000002),
.RSTP(sig00000002),
.CARRYINSEL({sig00000002, sig00000002, sig00000002}),
.OPMODE({sig00000002, sig000001a1, sig000001a1, sig00000002, sig000001a2, sig00000002, sig000001a2}),
.ALUMODE({sig00000002, sig00000002, sig000001fc, sig000001fc}),
.C({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000189, sig0000018a
, sig0000018b, sig0000018c, sig0000018d, sig0000018e, sig0000018f, sig00000190, sig00000191, sig00000192, sig00000193, sig00000194, sig00000195,
sig00000196, sig00000197, sig00000198, sig00000199, sig0000019a, sig0000019b, sig0000019c, sig0000019d, sig0000019e, sig0000019f, sig000001a0,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002}),
.B({sig00000002, sig00000002, sig00000179, sig0000017a, sig0000017b, sig0000017c, sig0000017d, sig0000017e, sig0000017f, sig00000180, sig00000181
, sig00000182, sig00000183, sig00000184, sig00000185, sig00000186, sig00000187, sig00000188}),
.P({\NLW_blk000002c0_P<47>_UNCONNECTED , \NLW_blk000002c0_P<46>_UNCONNECTED , \NLW_blk000002c0_P<45>_UNCONNECTED ,
\NLW_blk000002c0_P<44>_UNCONNECTED , \NLW_blk000002c0_P<43>_UNCONNECTED , \NLW_blk000002c0_P<42>_UNCONNECTED , \NLW_blk000002c0_P<41>_UNCONNECTED ,
\NLW_blk000002c0_P<40>_UNCONNECTED , sig0000004a, sig0000004b, sig0000004c, sig0000004d, sig0000004e, sig0000004f, sig00000050, sig00000051,
sig00000052, sig00000053, sig00000054, sig00000055, sig00000056, sig00000057, sig00000058, sig00000059, sig0000005a, sig0000005b, sig0000005c,
sig0000005d, sig0000005e, sig0000005f, sig00000060, sig00000061, sig00000062, sig00000063, sig00000064, sig000001eb, sig000001ec, sig000001ed,
sig000001ee, sig000001ef, sig000001f0, sig000001f1, sig000001f2, sig000001f3, sig000001f4, sig000001f5, sig000001f6, sig000001f7}),
.A({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000161, sig00000162, sig00000163, sig00000164, sig00000165
, sig00000166, sig00000167, sig00000168, sig00000169, sig0000016a, sig0000016b, sig0000016c, sig0000016d, sig0000016e, sig0000016f, sig00000170,
sig00000171, sig00000172, sig00000173, sig00000174, sig00000175, sig00000176, sig00000177, sig00000178}),
.ACOUT({\NLW_blk000002c0_ACOUT<29>_UNCONNECTED , \NLW_blk000002c0_ACOUT<28>_UNCONNECTED , \NLW_blk000002c0_ACOUT<27>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<26>_UNCONNECTED , \NLW_blk000002c0_ACOUT<25>_UNCONNECTED , \NLW_blk000002c0_ACOUT<24>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<23>_UNCONNECTED , \NLW_blk000002c0_ACOUT<22>_UNCONNECTED , \NLW_blk000002c0_ACOUT<21>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<20>_UNCONNECTED , \NLW_blk000002c0_ACOUT<19>_UNCONNECTED , \NLW_blk000002c0_ACOUT<18>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<17>_UNCONNECTED , \NLW_blk000002c0_ACOUT<16>_UNCONNECTED , \NLW_blk000002c0_ACOUT<15>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<14>_UNCONNECTED , \NLW_blk000002c0_ACOUT<13>_UNCONNECTED , \NLW_blk000002c0_ACOUT<12>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<11>_UNCONNECTED , \NLW_blk000002c0_ACOUT<10>_UNCONNECTED , \NLW_blk000002c0_ACOUT<9>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<8>_UNCONNECTED , \NLW_blk000002c0_ACOUT<7>_UNCONNECTED , \NLW_blk000002c0_ACOUT<6>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<5>_UNCONNECTED , \NLW_blk000002c0_ACOUT<4>_UNCONNECTED , \NLW_blk000002c0_ACOUT<3>_UNCONNECTED ,
\NLW_blk000002c0_ACOUT<2>_UNCONNECTED , \NLW_blk000002c0_ACOUT<1>_UNCONNECTED , \NLW_blk000002c0_ACOUT<0>_UNCONNECTED }),
.PCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.CARRYOUT({\NLW_blk000002c0_CARRYOUT<3>_UNCONNECTED , \NLW_blk000002c0_CARRYOUT<2>_UNCONNECTED , \NLW_blk000002c0_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk000002c0_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.BCOUT({\NLW_blk000002c0_BCOUT<17>_UNCONNECTED , \NLW_blk000002c0_BCOUT<16>_UNCONNECTED , \NLW_blk000002c0_BCOUT<15>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<14>_UNCONNECTED , \NLW_blk000002c0_BCOUT<13>_UNCONNECTED , \NLW_blk000002c0_BCOUT<12>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<11>_UNCONNECTED , \NLW_blk000002c0_BCOUT<10>_UNCONNECTED , \NLW_blk000002c0_BCOUT<9>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<8>_UNCONNECTED , \NLW_blk000002c0_BCOUT<7>_UNCONNECTED , \NLW_blk000002c0_BCOUT<6>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<5>_UNCONNECTED , \NLW_blk000002c0_BCOUT<4>_UNCONNECTED , \NLW_blk000002c0_BCOUT<3>_UNCONNECTED ,
\NLW_blk000002c0_BCOUT<2>_UNCONNECTED , \NLW_blk000002c0_BCOUT<1>_UNCONNECTED , \NLW_blk000002c0_BCOUT<0>_UNCONNECTED }),
.PCOUT({\NLW_blk000002c0_PCOUT<47>_UNCONNECTED , \NLW_blk000002c0_PCOUT<46>_UNCONNECTED , \NLW_blk000002c0_PCOUT<45>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<44>_UNCONNECTED , \NLW_blk000002c0_PCOUT<43>_UNCONNECTED , \NLW_blk000002c0_PCOUT<42>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<41>_UNCONNECTED , \NLW_blk000002c0_PCOUT<40>_UNCONNECTED , \NLW_blk000002c0_PCOUT<39>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<38>_UNCONNECTED , \NLW_blk000002c0_PCOUT<37>_UNCONNECTED , \NLW_blk000002c0_PCOUT<36>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<35>_UNCONNECTED , \NLW_blk000002c0_PCOUT<34>_UNCONNECTED , \NLW_blk000002c0_PCOUT<33>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<32>_UNCONNECTED , \NLW_blk000002c0_PCOUT<31>_UNCONNECTED , \NLW_blk000002c0_PCOUT<30>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<29>_UNCONNECTED , \NLW_blk000002c0_PCOUT<28>_UNCONNECTED , \NLW_blk000002c0_PCOUT<27>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<26>_UNCONNECTED , \NLW_blk000002c0_PCOUT<25>_UNCONNECTED , \NLW_blk000002c0_PCOUT<24>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<23>_UNCONNECTED , \NLW_blk000002c0_PCOUT<22>_UNCONNECTED , \NLW_blk000002c0_PCOUT<21>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<20>_UNCONNECTED , \NLW_blk000002c0_PCOUT<19>_UNCONNECTED , \NLW_blk000002c0_PCOUT<18>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<17>_UNCONNECTED , \NLW_blk000002c0_PCOUT<16>_UNCONNECTED , \NLW_blk000002c0_PCOUT<15>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<14>_UNCONNECTED , \NLW_blk000002c0_PCOUT<13>_UNCONNECTED , \NLW_blk000002c0_PCOUT<12>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<11>_UNCONNECTED , \NLW_blk000002c0_PCOUT<10>_UNCONNECTED , \NLW_blk000002c0_PCOUT<9>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<8>_UNCONNECTED , \NLW_blk000002c0_PCOUT<7>_UNCONNECTED , \NLW_blk000002c0_PCOUT<6>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<5>_UNCONNECTED , \NLW_blk000002c0_PCOUT<4>_UNCONNECTED , \NLW_blk000002c0_PCOUT<3>_UNCONNECTED ,
\NLW_blk000002c0_PCOUT<2>_UNCONNECTED , \NLW_blk000002c0_PCOUT<1>_UNCONNECTED , \NLW_blk000002c0_PCOUT<0>_UNCONNECTED }),
.ACIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 1 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( 0 ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 1 ),
.CARRYINSELREG ( 1 ),
.CREG ( 1 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 1 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk000002c1 (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk000002c1_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000002),
.CEB1(sig00000002),
.MULTSIGNOUT(NLW_blk000002c1_MULTSIGNOUT_UNCONNECTED),
.CEC(ce),
.RSTM(sig00000002),
.MULTSIGNIN(sig00000002),
.CEB2(ce),
.RSTCTRL(sig00000002),
.CEP(ce),
.CARRYCASCOUT(NLW_blk000002c1_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000002),
.CECARRYIN(ce),
.UNDERFLOW(NLW_blk000002c1_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk000002c1_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000002),
.RSTALLCARRYIN(sig00000002),
.CEALUMODE(ce),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000002),
.CEMULTCARRYIN(sig00000002),
.OVERFLOW(NLW_blk000002c1_OVERFLOW_UNCONNECTED),
.CECTRL(ce),
.CARRYIN(sig00000002),
.CARRYCASCIN(sig00000002),
.RSTP(sig00000002),
.CARRYINSEL({sig00000002, sig00000002, sig00000002}),
.C({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002
, sig00000002, sig00000002, sig00000011, sig00000012, sig00000013, sig00000014, sig00000015, sig00000016, sig00000017, sig00000018, sig00000001,
sig0000022c, sig0000022b, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig0000022d, sig00000002, sig00000002}),
.B({sig00000002, sig00000002, sig0000025c, sig0000025b, sig0000025a, sig00000259, sig00000258, sig00000257, sig00000256, sig00000255, sig00000254
, sig00000253, sig00000252, sig00000251, sig00000250, sig0000024f, sig0000024e, sig0000024d}),
.P({\NLW_blk000002c1_P<47>_UNCONNECTED , \NLW_blk000002c1_P<46>_UNCONNECTED , \NLW_blk000002c1_P<45>_UNCONNECTED ,
\NLW_blk000002c1_P<44>_UNCONNECTED , \NLW_blk000002c1_P<43>_UNCONNECTED , \NLW_blk000002c1_P<42>_UNCONNECTED , \NLW_blk000002c1_P<41>_UNCONNECTED ,
\NLW_blk000002c1_P<40>_UNCONNECTED , \NLW_blk000002c1_P<39>_UNCONNECTED , \NLW_blk000002c1_P<38>_UNCONNECTED , \NLW_blk000002c1_P<37>_UNCONNECTED ,
\NLW_blk000002c1_P<36>_UNCONNECTED , \NLW_blk000002c1_P<35>_UNCONNECTED , sig00000083, sig00000084, sig00000085, sig00000086, sig00000087, sig00000088
, sig00000089, sig0000008a, \NLW_blk000002c1_P<26>_UNCONNECTED , \NLW_blk000002c1_P<25>_UNCONNECTED , sig0000006c, sig0000006d, sig0000006e,
sig0000006f, sig00000070, sig00000071, sig00000072, sig00000073, sig00000074, sig00000075, sig00000076, sig00000077, sig00000078, sig00000079,
sig0000007a, sig0000007b, sig0000007c, sig0000007d, sig0000007e, sig0000007f, sig00000080, sig00000081, sig00000082,
\NLW_blk000002c1_P<1>_UNCONNECTED , \NLW_blk000002c1_P<0>_UNCONNECTED }),
.A({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig0000024a, sig00000249, sig00000248, sig00000247, sig00000246
, sig00000245, sig00000244, sig00000243, sig00000242, sig00000241, sig00000240, sig0000023f, sig0000023e, sig0000023d, sig0000023c, sig0000023b,
sig0000023a, sig00000239, sig00000238, sig00000237, sig00000236, sig00000235, sig00000234, sig00000233}),
.ACOUT({\NLW_blk000002c1_ACOUT<29>_UNCONNECTED , \NLW_blk000002c1_ACOUT<28>_UNCONNECTED , \NLW_blk000002c1_ACOUT<27>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<26>_UNCONNECTED , \NLW_blk000002c1_ACOUT<25>_UNCONNECTED , \NLW_blk000002c1_ACOUT<24>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<23>_UNCONNECTED , \NLW_blk000002c1_ACOUT<22>_UNCONNECTED , \NLW_blk000002c1_ACOUT<21>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<20>_UNCONNECTED , \NLW_blk000002c1_ACOUT<19>_UNCONNECTED , \NLW_blk000002c1_ACOUT<18>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<17>_UNCONNECTED , \NLW_blk000002c1_ACOUT<16>_UNCONNECTED , \NLW_blk000002c1_ACOUT<15>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<14>_UNCONNECTED , \NLW_blk000002c1_ACOUT<13>_UNCONNECTED , \NLW_blk000002c1_ACOUT<12>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<11>_UNCONNECTED , \NLW_blk000002c1_ACOUT<10>_UNCONNECTED , \NLW_blk000002c1_ACOUT<9>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<8>_UNCONNECTED , \NLW_blk000002c1_ACOUT<7>_UNCONNECTED , \NLW_blk000002c1_ACOUT<6>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<5>_UNCONNECTED , \NLW_blk000002c1_ACOUT<4>_UNCONNECTED , \NLW_blk000002c1_ACOUT<3>_UNCONNECTED ,
\NLW_blk000002c1_ACOUT<2>_UNCONNECTED , \NLW_blk000002c1_ACOUT<1>_UNCONNECTED , \NLW_blk000002c1_ACOUT<0>_UNCONNECTED }),
.OPMODE({sig00000002, sig00000001, sig00000001, sig00000002, sig00000001, sig00000002, sig00000001}),
.PCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.ALUMODE({sig00000002, sig00000002, sig00000002, sig00000002}),
.CARRYOUT({\NLW_blk000002c1_CARRYOUT<3>_UNCONNECTED , \NLW_blk000002c1_CARRYOUT<2>_UNCONNECTED , \NLW_blk000002c1_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk000002c1_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002}),
.BCOUT({\NLW_blk000002c1_BCOUT<17>_UNCONNECTED , \NLW_blk000002c1_BCOUT<16>_UNCONNECTED , \NLW_blk000002c1_BCOUT<15>_UNCONNECTED ,
\NLW_blk000002c1_BCOUT<14>_UNCONNECTED , \NLW_blk000002c1_BCOUT<13>_UNCONNECTED , \NLW_blk000002c1_BCOUT<12>_UNCONNECTED ,
\NLW_blk000002c1_BCOUT<11>_UNCONNECTED , \NLW_blk000002c1_BCOUT<10>_UNCONNECTED , \NLW_blk000002c1_BCOUT<9>_UNCONNECTED ,
\NLW_blk000002c1_BCOUT<8>_UNCONNECTED , \NLW_blk000002c1_BCOUT<7>_UNCONNECTED , \NLW_blk000002c1_BCOUT<6>_UNCONNECTED ,
\NLW_blk000002c1_BCOUT<5>_UNCONNECTED , \NLW_blk000002c1_BCOUT<4>_UNCONNECTED , \NLW_blk000002c1_BCOUT<3>_UNCONNECTED ,
\NLW_blk000002c1_BCOUT<2>_UNCONNECTED , \NLW_blk000002c1_BCOUT<1>_UNCONNECTED , \NLW_blk000002c1_BCOUT<0>_UNCONNECTED }),
.PCOUT({\NLW_blk000002c1_PCOUT<47>_UNCONNECTED , \NLW_blk000002c1_PCOUT<46>_UNCONNECTED , \NLW_blk000002c1_PCOUT<45>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<44>_UNCONNECTED , \NLW_blk000002c1_PCOUT<43>_UNCONNECTED , \NLW_blk000002c1_PCOUT<42>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<41>_UNCONNECTED , \NLW_blk000002c1_PCOUT<40>_UNCONNECTED , \NLW_blk000002c1_PCOUT<39>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<38>_UNCONNECTED , \NLW_blk000002c1_PCOUT<37>_UNCONNECTED , \NLW_blk000002c1_PCOUT<36>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<35>_UNCONNECTED , \NLW_blk000002c1_PCOUT<34>_UNCONNECTED , \NLW_blk000002c1_PCOUT<33>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<32>_UNCONNECTED , \NLW_blk000002c1_PCOUT<31>_UNCONNECTED , \NLW_blk000002c1_PCOUT<30>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<29>_UNCONNECTED , \NLW_blk000002c1_PCOUT<28>_UNCONNECTED , \NLW_blk000002c1_PCOUT<27>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<26>_UNCONNECTED , \NLW_blk000002c1_PCOUT<25>_UNCONNECTED , \NLW_blk000002c1_PCOUT<24>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<23>_UNCONNECTED , \NLW_blk000002c1_PCOUT<22>_UNCONNECTED , \NLW_blk000002c1_PCOUT<21>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<20>_UNCONNECTED , \NLW_blk000002c1_PCOUT<19>_UNCONNECTED , \NLW_blk000002c1_PCOUT<18>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<17>_UNCONNECTED , \NLW_blk000002c1_PCOUT<16>_UNCONNECTED , \NLW_blk000002c1_PCOUT<15>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<14>_UNCONNECTED , \NLW_blk000002c1_PCOUT<13>_UNCONNECTED , \NLW_blk000002c1_PCOUT<12>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<11>_UNCONNECTED , \NLW_blk000002c1_PCOUT<10>_UNCONNECTED , \NLW_blk000002c1_PCOUT<9>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<8>_UNCONNECTED , \NLW_blk000002c1_PCOUT<7>_UNCONNECTED , \NLW_blk000002c1_PCOUT<6>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<5>_UNCONNECTED , \NLW_blk000002c1_PCOUT<4>_UNCONNECTED , \NLW_blk000002c1_PCOUT<3>_UNCONNECTED ,
\NLW_blk000002c1_PCOUT<2>_UNCONNECTED , \NLW_blk000002c1_PCOUT<1>_UNCONNECTED , \NLW_blk000002c1_PCOUT<0>_UNCONNECTED }),
.ACIN({sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002,
sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002, sig00000002})
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21O_TB_V
`define SKY130_FD_SC_HD__A21O_TB_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1 = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1 = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1 = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1 = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_hd__a21o dut (.A1(A1), .A2(A2), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21O_TB_V
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based relations, tactics and standard instances
This is the basic theory needed to formalize morphisms and setoids.
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Export Coq.Classes.Init.
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Import Coq.Relations.Relation_Definitions.
(** We allow to unfold the [relation] definition while doing morphism search. *)
Notation inverse R := (flip (R:relation _) : relation _).
Definition complement {A} (R : relation A) : relation A := fun x y => R x y -> False.
(** Opaque for proof-search. *)
Typeclasses Opaque complement.
(** These are convertible. *)
Lemma complement_inverse : forall A (R : relation A), complement (inverse R) = inverse (complement R).
Proof. reflexivity. Qed.
(** We rebind relations in separate classes to be able to overload each proof. *)
Set Implicit Arguments.
Unset Strict Implicit.
Class Reflexive {A} (R : relation A) :=
reflexivity : forall x, R x x.
Class Irreflexive {A} (R : relation A) :=
irreflexivity : Reflexive (complement R).
Hint Extern 1 (Reflexive (complement _)) => class_apply @irreflexivity : typeclass_instances.
Class Symmetric {A} (R : relation A) :=
symmetry : forall x y, R x y -> R y x.
Class Asymmetric {A} (R : relation A) :=
asymmetry : forall x y, R x y -> R y x -> False.
Class Transitive {A} (R : relation A) :=
transitivity : forall x y z, R x y -> R y z -> R x z.
Hint Resolve @irreflexivity : ord.
Unset Implicit Arguments.
(** A HintDb for relations. *)
Ltac solve_relation :=
match goal with
| [ |- ?R ?x ?x ] => reflexivity
| [ H : ?R ?x ?y |- ?R ?y ?x ] => symmetry ; exact H
end.
Hint Extern 4 => solve_relation : relations.
(** We can already dualize all these properties. *)
Generalizable Variables A B C D R S T U l eqA eqB eqC eqD.
Lemma flip_Reflexive `{Reflexive A R} : Reflexive (flip R).
Proof. tauto. Qed.
Hint Extern 3 (Reflexive (flip _)) => apply flip_Reflexive : typeclass_instances.
Program Definition flip_Irreflexive `(Irreflexive A R) : Irreflexive (flip R) :=
irreflexivity (R:=R).
Program Definition flip_Symmetric `(Symmetric A R) : Symmetric (flip R) :=
fun x y H => symmetry (R:=R) H.
Program Definition flip_Asymmetric `(Asymmetric A R) : Asymmetric (flip R) :=
fun x y H H' => asymmetry (R:=R) H H'.
Program Definition flip_Transitive `(Transitive A R) : Transitive (flip R) :=
fun x y z H H' => transitivity (R:=R) H' H.
Hint Extern 3 (Irreflexive (flip _)) => class_apply flip_Irreflexive : typeclass_instances.
Hint Extern 3 (Symmetric (flip _)) => class_apply flip_Symmetric : typeclass_instances.
Hint Extern 3 (Asymmetric (flip _)) => class_apply flip_Asymmetric : typeclass_instances.
Hint Extern 3 (Transitive (flip _)) => class_apply flip_Transitive : typeclass_instances.
Definition Reflexive_complement_Irreflexive `(Reflexive A (R : relation A))
: Irreflexive (complement R).
Proof. firstorder. Qed.
Definition complement_Symmetric `(Symmetric A (R : relation A)) : Symmetric (complement R).
Proof. firstorder. Qed.
Hint Extern 3 (Symmetric (complement _)) => class_apply complement_Symmetric : typeclass_instances.
Hint Extern 3 (Irreflexive (complement _)) => class_apply Reflexive_complement_Irreflexive : typeclass_instances.
(** * Standard instances. *)
Ltac reduce_hyp H :=
match type of H with
| context [ _ <-> _ ] => fail 1
| _ => red in H ; try reduce_hyp H
end.
Ltac reduce_goal :=
match goal with
| [ |- _ <-> _ ] => fail 1
| _ => red ; intros ; try reduce_goal
end.
Tactic Notation "reduce" "in" hyp(Hid) := reduce_hyp Hid.
Ltac reduce := reduce_goal.
Tactic Notation "apply" "*" constr(t) :=
first [ refine t | refine (t _) | refine (t _ _) | refine (t _ _ _) | refine (t _ _ _ _) |
refine (t _ _ _ _ _) | refine (t _ _ _ _ _ _) | refine (t _ _ _ _ _ _ _) ].
Ltac simpl_relation :=
unfold flip, impl, arrow ; try reduce ; program_simpl ;
try ( solve [ intuition ]).
Local Obligation Tactic := simpl_relation.
(** Logical implication. *)
Program Instance impl_Reflexive : Reflexive impl.
Program Instance impl_Transitive : Transitive impl.
(** Logical equivalence. *)
Program Instance iff_Reflexive : Reflexive iff.
Program Instance iff_Symmetric : Symmetric iff.
Program Instance iff_Transitive : Transitive iff.
(** Leibniz equality. *)
Instance eq_Reflexive {A} : Reflexive (@eq A) := @eq_refl A.
Instance eq_Symmetric {A} : Symmetric (@eq A) := @eq_sym A.
Instance eq_Transitive {A} : Transitive (@eq A) := @eq_trans A.
(** Various combinations of reflexivity, symmetry and transitivity. *)
(** A [PreOrder] is both Reflexive and Transitive. *)
Class PreOrder {A} (R : relation A) : Prop := {
PreOrder_Reflexive :> Reflexive R ;
PreOrder_Transitive :> Transitive R }.
(** A partial equivalence relation is Symmetric and Transitive. *)
Class PER {A} (R : relation A) : Prop := {
PER_Symmetric :> Symmetric R ;
PER_Transitive :> Transitive R }.
(** Equivalence relations. *)
Class Equivalence {A} (R : relation A) : Prop := {
Equivalence_Reflexive :> Reflexive R ;
Equivalence_Symmetric :> Symmetric R ;
Equivalence_Transitive :> Transitive R }.
(** An Equivalence is a PER plus reflexivity. *)
Instance Equivalence_PER `(Equivalence A R) : PER R | 10 :=
{ PER_Symmetric := Equivalence_Symmetric ;
PER_Transitive := Equivalence_Transitive }.
(** We can now define antisymmetry w.r.t. an equivalence relation on the carrier. *)
Class Antisymmetric A eqA `{equ : Equivalence A eqA} (R : relation A) :=
antisymmetry : forall {x y}, R x y -> R y x -> eqA x y.
Program Definition flip_antiSymmetric `(Antisymmetric A eqA R) :
Antisymmetric A eqA (flip R).
Proof. firstorder. Qed.
(** Leibinz equality [eq] is an equivalence relation.
The instance has low priority as it is always applicable
if only the type is constrained. *)
Program Instance eq_equivalence : Equivalence (@eq A) | 10.
(** Logical equivalence [iff] is an equivalence relation. *)
Program Instance iff_equivalence : Equivalence iff.
(** We now develop a generalization of results on relations for arbitrary predicates.
The resulting theory can be applied to homogeneous binary relations but also to
arbitrary n-ary predicates. *)
Local Open Scope list_scope.
(* Notation " [ ] " := nil : list_scope. *)
(* Notation " [ x ; .. ; y ] " := (cons x .. (cons y nil) ..) (at level 1) : list_scope. *)
(** A compact representation of non-dependent arities, with the codomain singled-out. *)
Fixpoint arrows (l : list Type) (r : Type) : Type :=
match l with
| nil => r
| A :: l' => A -> arrows l' r
end.
(** We can define abbreviations for operation and relation types based on [arrows]. *)
Definition unary_operation A := arrows (A::nil) A.
Definition binary_operation A := arrows (A::A::nil) A.
Definition ternary_operation A := arrows (A::A::A::nil) A.
(** We define n-ary [predicate]s as functions into [Prop]. *)
Notation predicate l := (arrows l Prop).
(** Unary predicates, or sets. *)
Definition unary_predicate A := predicate (A::nil).
(** Homogeneous binary relations, equivalent to [relation A]. *)
Definition binary_relation A := predicate (A::A::nil).
(** We can close a predicate by universal or existential quantification. *)
Fixpoint predicate_all (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => forall x : A, predicate_all tl (f x)
end.
Fixpoint predicate_exists (l : list Type) : predicate l -> Prop :=
match l with
| nil => fun f => f
| A :: tl => fun f => exists x : A, predicate_exists tl (f x)
end.
(** Pointwise extension of a binary operation on [T] to a binary operation
on functions whose codomain is [T].
For an operator on [Prop] this lifts the operator to a binary operation. *)
Fixpoint pointwise_extension {T : Type} (op : binary_operation T)
(l : list Type) : binary_operation (arrows l T) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
fun x => pointwise_extension op tl (R x) (R' x)
end.
(** Pointwise lifting, equivalent to doing [pointwise_extension] and closing using [predicate_all]. *)
Fixpoint pointwise_lifting (op : binary_relation Prop) (l : list Type) : binary_relation (predicate l) :=
match l with
| nil => fun R R' => op R R'
| A :: tl => fun R R' =>
forall x, pointwise_lifting op tl (R x) (R' x)
end.
(** The n-ary equivalence relation, defined by lifting the 0-ary [iff] relation. *)
Definition predicate_equivalence {l : list Type} : binary_relation (predicate l) :=
pointwise_lifting iff l.
(** The n-ary implication relation, defined by lifting the 0-ary [impl] relation. *)
Definition predicate_implication {l : list Type} :=
pointwise_lifting impl l.
(** Notations for pointwise equivalence and implication of predicates. *)
Infix "<∙>" := predicate_equivalence (at level 95, no associativity) : predicate_scope.
Infix "-∙>" := predicate_implication (at level 70, right associativity) : predicate_scope.
Open Local Scope predicate_scope.
(** The pointwise liftings of conjunction and disjunctions.
Note that these are [binary_operation]s, building new relations out of old ones. *)
Definition predicate_intersection := pointwise_extension and.
Definition predicate_union := pointwise_extension or.
Infix "/∙\" := predicate_intersection (at level 80, right associativity) : predicate_scope.
Infix "\∙/" := predicate_union (at level 85, right associativity) : predicate_scope.
(** The always [True] and always [False] predicates. *)
Fixpoint true_predicate {l : list Type} : predicate l :=
match l with
| nil => True
| A :: tl => fun _ => @true_predicate tl
end.
Fixpoint false_predicate {l : list Type} : predicate l :=
match l with
| nil => False
| A :: tl => fun _ => @false_predicate tl
end.
Notation "∙⊤∙" := true_predicate : predicate_scope.
Notation "∙⊥∙" := false_predicate : predicate_scope.
(** Predicate equivalence is an equivalence, and predicate implication defines a preorder. *)
Program Instance predicate_equivalence_equivalence : Equivalence (@predicate_equivalence l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
fold pointwise_lifting.
induction l. firstorder.
intros. simpl in *. pose (IHl (x x0) (y x0) (z x0)).
firstorder.
Qed.
Program Instance predicate_implication_preorder :
PreOrder (@predicate_implication l).
Next Obligation.
induction l ; firstorder.
Qed.
Next Obligation.
induction l. firstorder.
unfold predicate_implication in *. simpl in *.
intro. pose (IHl (x x0) (y x0) (z x0)). firstorder.
Qed.
(** We define the various operations which define the algebra on binary relations,
from the general ones. *)
Definition relation_equivalence {A : Type} : relation (relation A) :=
@predicate_equivalence (_::_::nil).
Class subrelation {A:Type} (R R' : relation A) : Prop :=
is_subrelation : @predicate_implication (A::A::nil) R R'.
Implicit Arguments subrelation [[A]].
Definition relation_conjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_intersection (A::A::nil) R R'.
Definition relation_disjunction {A} (R : relation A) (R' : relation A) : relation A :=
@predicate_union (A::A::nil) R R'.
(** Relation equivalence is an equivalence, and subrelation defines a partial order. *)
Set Automatic Introduction.
Instance relation_equivalence_equivalence (A : Type) :
Equivalence (@relation_equivalence A).
Proof. exact (@predicate_equivalence_equivalence (A::A::nil)). Qed.
Instance relation_implication_preorder A : PreOrder (@subrelation A).
Proof. exact (@predicate_implication_preorder (A::A::nil)). Qed.
(** *** Partial Order.
A partial order is a preorder which is additionally antisymmetric.
We give an equivalent definition, up-to an equivalence relation
on the carrier. *)
Class PartialOrder {A} eqA `{equ : Equivalence A eqA} R `{preo : PreOrder A R} :=
partial_order_equivalence : relation_equivalence eqA (relation_conjunction R (inverse R)).
(** The equivalence proof is sufficient for proving that [R] must be a morphism
for equivalence (see Morphisms).
It is also sufficient to show that [R] is antisymmetric w.r.t. [eqA] *)
Instance partial_order_antisym `(PartialOrder A eqA R) : ! Antisymmetric A eqA R.
Proof with auto.
reduce_goal.
pose proof partial_order_equivalence as poe. do 3 red in poe.
apply <- poe. firstorder.
Qed.
(** The partial order defined by subrelation and relation equivalence. *)
Program Instance subrelation_partial_order :
! PartialOrder (relation A) relation_equivalence subrelation.
Next Obligation.
Proof.
unfold relation_equivalence in *. compute; firstorder.
Qed.
Typeclasses Opaque arrows predicate_implication predicate_equivalence
relation_equivalence pointwise_lifting.
(** Rewrite relation on a given support: declares a relation as a rewrite
relation for use by the generalized rewriting tactic.
It helps choosing if a rewrite should be handled
by the generalized or the regular rewriting tactic using leibniz equality.
Users can declare an [RewriteRelation A RA] anywhere to declare default
relations. This is also done automatically by the [Declare Relation A RA]
commands. *)
Class RewriteRelation {A : Type} (RA : relation A).
Instance: RewriteRelation impl.
Instance: RewriteRelation iff.
Instance: RewriteRelation (@relation_equivalence A).
(** Any [Equivalence] declared in the context is automatically considered
a rewrite relation. *)
Instance equivalence_rewrite_relation `(Equivalence A eqA) : RewriteRelation eqA.
(** Strict Order *)
Class StrictOrder {A : Type} (R : relation A) := {
StrictOrder_Irreflexive :> Irreflexive R ;
StrictOrder_Transitive :> Transitive R
}.
Instance StrictOrder_Asymmetric `(StrictOrder A R) : Asymmetric R.
Proof. firstorder. Qed.
(** Inversing a [StrictOrder] gives another [StrictOrder] *)
Lemma StrictOrder_inverse `(StrictOrder A R) : StrictOrder (inverse R).
Proof. firstorder. Qed.
(** Same for [PartialOrder]. *)
Lemma PreOrder_inverse `(PreOrder A R) : PreOrder (inverse R).
Proof. firstorder. Qed.
Hint Extern 3 (StrictOrder (inverse _)) => class_apply StrictOrder_inverse : typeclass_instances.
Hint Extern 3 (PreOrder (inverse _)) => class_apply PreOrder_inverse : typeclass_instances.
Lemma PartialOrder_inverse `(PartialOrder A eqA R) : PartialOrder eqA (inverse R).
Proof. firstorder. Qed.
Hint Extern 3 (PartialOrder (inverse _)) => class_apply PartialOrder_inverse : typeclass_instances.
|
module fsm(x, y, clk, reset, state_out);
// Inputs:
input wire x, clk, reset;
// Outputs:
output wire y;
output wire [2:0] state_out;
// Internal representation (state):
reg [2:0] State;
reg [2:0] NextState;
// State Encoding Parameters:
localparam STATE_Initial = 3'b000,
STATE_1 = 3'b001,
STATE_2 = 3'b010,
STATE_3 = 3'b011,
STATE_4 = 3'b100,
STATE_5 = 3'b101,
STATE_6 = 3'b110,
STATE_7_UNUSED = 3'b111;
// Implement state updating (note non-blocking assignment operator)
always @(posedge clk) begin
if (reset) State <= STATE_Initial;
else State <= NextState;
end
// Now handle output (y) value
assign y = (State == STATE_5) | (State == STATE_6);
assign state_out = State;
// Implement the actual state transition based on the current state and the input value
// Note the use of blocking assignment here
always @(*) begin
NextState = State;
case (State)
STATE_Initial: begin
if (x) NextState = STATE_1;
else NextState = STATE_Initial;
end
STATE_1 : begin
if (x) NextState = STATE_1;
else NextState = STATE_2;
end
STATE_2 : begin
if (x) NextState = STATE_3;
else NextState = STATE_Initial;
end
STATE_3 : begin
if (x) NextState = STATE_4;
else NextState = STATE_2;
end
STATE_4 : begin
if (x) NextState = STATE_5;
else NextState = STATE_6;
end
STATE_5 : begin
if (x) NextState = STATE_1;
else NextState = STATE_2;
end
STATE_6 : begin
if (x) NextState = STATE_3;
else NextState = STATE_Initial;
end
STATE_7_UNUSED : begin
NextState = STATE_Initial;
end
endcase
end
endmodule |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_best_delta_seg1 (
dth_0_V_read,
dth_1_V_read,
dth_2_V_read,
dth_3_V_read,
dth_4_V_read,
dth_5_V_read,
dth_6_V_read,
dth_7_V_read,
sth_V,
dvl_V,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
parameter ap_const_lv2_3 = 2'b11;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv7_7F = 7'b1111111;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv2_2 = 2'b10;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv3_4 = 3'b100;
parameter ap_const_lv3_5 = 3'b101;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv3_6 = 3'b110;
parameter ap_const_lv3_7 = 3'b111;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv8_0 = 8'b00000000;
input [6:0] dth_0_V_read;
input [6:0] dth_1_V_read;
input [6:0] dth_2_V_read;
input [6:0] dth_3_V_read;
input [6:0] dth_4_V_read;
input [6:0] dth_5_V_read;
input [6:0] dth_6_V_read;
input [6:0] dth_7_V_read;
input [7:0] sth_V;
input [7:0] dvl_V;
output [6:0] ap_return_0;
output [0:0] ap_return_1;
output [0:0] ap_return_2;
output [2:0] ap_return_3;
wire [1:0] tmp_2762_fu_142_p1;
wire [0:0] tmp_404_fu_136_p2;
wire [0:0] tmp_fu_146_p2;
wire [0:0] sel_tmp_fu_158_p2;
wire [0:0] tmp_405_fu_152_p2;
wire [0:0] sel_tmp1_fu_164_p2;
wire [0:0] not_sel_tmp1_fu_170_p2;
wire [0:0] tmp_406_fu_188_p2;
wire [6:0] cmp1_V_load_s_fu_180_p3;
wire [1:0] p_Result_1231_1_fu_208_p4;
wire [0:0] tmp_1156_1_fu_202_p2;
wire [0:0] tmp_1_fu_218_p2;
wire [0:0] sel_tmp9_fu_230_p2;
wire [0:0] tmp_1157_1_fu_224_p2;
wire [0:0] sel_tmp10_fu_236_p2;
wire [0:0] tmp_1175_1_fu_258_p2;
wire [6:0] cmp1_V_load_13_s_fu_250_p3;
wire [1:0] p_Result_1231_2_fu_278_p4;
wire [0:0] tmp_1156_2_fu_272_p2;
wire [0:0] tmp_2_fu_288_p2;
wire [0:0] sel_tmp18_fu_300_p2;
wire [0:0] tmp_1157_2_fu_294_p2;
wire [0:0] sel_tmp19_fu_306_p2;
wire [0:0] tmp_1175_2_fu_328_p2;
wire [6:0] cmp1_V_load_2_fu_320_p3;
wire [1:0] p_Result_1231_3_fu_348_p4;
wire [0:0] tmp_1156_3_fu_342_p2;
wire [0:0] tmp_3_fu_358_p2;
wire [0:0] sel_tmp27_fu_386_p2;
wire [0:0] tmp_1157_3_fu_364_p2;
wire [0:0] sel_tmp28_fu_392_p2;
wire [0:0] tmp_2763_fu_370_p3;
wire [0:0] tmp_2764_fu_378_p3;
wire [0:0] tmp_1175_3_fu_422_p2;
wire [6:0] cmp1_V_load_13_2_fu_406_p3;
wire [6:0] cmp1_V_load_fu_194_p3;
wire [6:0] cmp1_V_load_3_fu_264_p3;
wire [0:0] tmp_2765_fu_442_p1;
wire [0:0] tmp_2766_fu_446_p3;
wire [0:0] tmp_2767_fu_462_p3;
wire [0:0] tmp_2768_fu_470_p3;
wire [0:0] tmp_407_fu_436_p2;
wire [1:0] num1_V_load_cast_fu_176_p1;
wire [1:0] num1_V_load_2_fu_242_p3;
wire [1:0] a_bnm_V_fu_486_p3;
wire [6:0] cmp1_V_load_1_fu_334_p3;
wire [6:0] cmp1_V_load_13_1_fu_428_p3;
wire [0:0] tmp_2769_fu_512_p3;
wire [0:0] tmp_2770_fu_520_p3;
wire [0:0] tmp_1161_1_fu_506_p2;
wire [2:0] num1_V_load_1_fu_312_p3;
wire [2:0] num1_V_load_2_1_cast_cast_fu_398_p3;
wire [0:0] tmp_226_fu_528_p3;
wire [0:0] tmp_217_fu_414_p3;
wire [6:0] a_bth_V_fu_498_p3;
wire [6:0] a_bth_V_1_fu_544_p3;
wire [0:0] tmp_220_fu_454_p3;
wire [0:0] tmp_223_fu_478_p3;
wire [0:0] tmp_s_fu_560_p2;
wire [0:0] tmp_228_fu_566_p3;
wire [0:0] tmp_227_fu_552_p3;
wire [2:0] a_bnm_V_cast_fu_494_p1;
wire [2:0] a_bnm_V_1_fu_536_p3;
wire [6:0] a_bth_V_2_fu_574_p3;
wire [0:0] a_bsg_V_fu_582_p3;
wire [0:0] a_bvl_V_fu_598_p2;
wire [2:0] a_bnm_V_2_fu_590_p3;
assign a_bnm_V_1_fu_536_p3 = ((tmp_1161_1_fu_506_p2[0:0] === 1'b1) ? num1_V_load_1_fu_312_p3 : num1_V_load_2_1_cast_cast_fu_398_p3);
assign a_bnm_V_2_fu_590_p3 = ((tmp_s_fu_560_p2[0:0] === 1'b1) ? a_bnm_V_cast_fu_494_p1 : a_bnm_V_1_fu_536_p3);
assign a_bnm_V_cast_fu_494_p1 = a_bnm_V_fu_486_p3;
assign a_bnm_V_fu_486_p3 = ((tmp_407_fu_436_p2[0:0] === 1'b1) ? num1_V_load_cast_fu_176_p1 : num1_V_load_2_fu_242_p3);
assign a_bsg_V_fu_582_p3 = ((tmp_s_fu_560_p2[0:0] === 1'b1) ? tmp_228_fu_566_p3 : tmp_227_fu_552_p3);
assign a_bth_V_1_fu_544_p3 = ((tmp_1161_1_fu_506_p2[0:0] === 1'b1) ? cmp1_V_load_1_fu_334_p3 : cmp1_V_load_13_1_fu_428_p3);
assign a_bth_V_2_fu_574_p3 = ((tmp_s_fu_560_p2[0:0] === 1'b1) ? a_bth_V_fu_498_p3 : a_bth_V_1_fu_544_p3);
assign a_bth_V_fu_498_p3 = ((tmp_407_fu_436_p2[0:0] === 1'b1) ? cmp1_V_load_fu_194_p3 : cmp1_V_load_3_fu_264_p3);
assign a_bvl_V_fu_598_p2 = ((dvl_V != ap_const_lv8_0) ? 1'b1 : 1'b0);
assign ap_return_0 = a_bth_V_2_fu_574_p3;
assign ap_return_1 = a_bsg_V_fu_582_p3;
assign ap_return_2 = a_bvl_V_fu_598_p2;
assign ap_return_3 = a_bnm_V_2_fu_590_p3;
assign cmp1_V_load_13_1_fu_428_p3 = ((tmp_1175_3_fu_422_p2[0:0] === 1'b1) ? ap_const_lv7_7F : cmp1_V_load_13_2_fu_406_p3);
assign cmp1_V_load_13_2_fu_406_p3 = ((sel_tmp28_fu_392_p2[0:0] === 1'b1) ? dth_6_V_read : dth_7_V_read);
assign cmp1_V_load_13_s_fu_250_p3 = ((sel_tmp10_fu_236_p2[0:0] === 1'b1) ? dth_2_V_read : dth_3_V_read);
assign cmp1_V_load_1_fu_334_p3 = ((tmp_1175_2_fu_328_p2[0:0] === 1'b1) ? ap_const_lv7_7F : cmp1_V_load_2_fu_320_p3);
assign cmp1_V_load_2_fu_320_p3 = ((sel_tmp19_fu_306_p2[0:0] === 1'b1) ? dth_4_V_read : dth_5_V_read);
assign cmp1_V_load_3_fu_264_p3 = ((tmp_1175_1_fu_258_p2[0:0] === 1'b1) ? ap_const_lv7_7F : cmp1_V_load_13_s_fu_250_p3);
assign cmp1_V_load_fu_194_p3 = ((tmp_406_fu_188_p2[0:0] === 1'b1) ? ap_const_lv7_7F : cmp1_V_load_s_fu_180_p3);
assign cmp1_V_load_s_fu_180_p3 = ((sel_tmp1_fu_164_p2[0:0] === 1'b1) ? dth_0_V_read : dth_1_V_read);
assign not_sel_tmp1_fu_170_p2 = (sel_tmp1_fu_164_p2 ^ 1'b1);
assign num1_V_load_1_fu_312_p3 = ((sel_tmp19_fu_306_p2[0:0] === 1'b1) ? ap_const_lv3_4 : ap_const_lv3_5);
assign num1_V_load_2_1_cast_cast_fu_398_p3 = ((sel_tmp28_fu_392_p2[0:0] === 1'b1) ? ap_const_lv3_6 : ap_const_lv3_7);
assign num1_V_load_2_fu_242_p3 = ((sel_tmp10_fu_236_p2[0:0] === 1'b1) ? ap_const_lv2_2 : ap_const_lv2_3);
assign num1_V_load_cast_fu_176_p1 = not_sel_tmp1_fu_170_p2;
assign p_Result_1231_1_fu_208_p4 = {{dvl_V[ap_const_lv32_3 : ap_const_lv32_2]}};
assign p_Result_1231_2_fu_278_p4 = {{dvl_V[ap_const_lv32_5 : ap_const_lv32_4]}};
assign p_Result_1231_3_fu_348_p4 = {{dvl_V[ap_const_lv32_7 : ap_const_lv32_6]}};
assign sel_tmp10_fu_236_p2 = (sel_tmp9_fu_230_p2 | tmp_1157_1_fu_224_p2);
assign sel_tmp18_fu_300_p2 = (tmp_1156_2_fu_272_p2 & tmp_2_fu_288_p2);
assign sel_tmp19_fu_306_p2 = (sel_tmp18_fu_300_p2 | tmp_1157_2_fu_294_p2);
assign sel_tmp1_fu_164_p2 = (sel_tmp_fu_158_p2 | tmp_405_fu_152_p2);
assign sel_tmp27_fu_386_p2 = (tmp_1156_3_fu_342_p2 & tmp_3_fu_358_p2);
assign sel_tmp28_fu_392_p2 = (sel_tmp27_fu_386_p2 | tmp_1157_3_fu_364_p2);
assign sel_tmp9_fu_230_p2 = (tmp_1156_1_fu_202_p2 & tmp_1_fu_218_p2);
assign sel_tmp_fu_158_p2 = (tmp_404_fu_136_p2 & tmp_fu_146_p2);
assign tmp_1156_1_fu_202_p2 = ((dth_2_V_read < dth_3_V_read) ? 1'b1 : 1'b0);
assign tmp_1156_2_fu_272_p2 = ((dth_4_V_read < dth_5_V_read) ? 1'b1 : 1'b0);
assign tmp_1156_3_fu_342_p2 = ((dth_6_V_read < dth_7_V_read) ? 1'b1 : 1'b0);
assign tmp_1157_1_fu_224_p2 = ((p_Result_1231_1_fu_208_p4 == ap_const_lv2_1) ? 1'b1 : 1'b0);
assign tmp_1157_2_fu_294_p2 = ((p_Result_1231_2_fu_278_p4 == ap_const_lv2_1) ? 1'b1 : 1'b0);
assign tmp_1157_3_fu_364_p2 = ((p_Result_1231_3_fu_348_p4 == ap_const_lv2_1) ? 1'b1 : 1'b0);
assign tmp_1161_1_fu_506_p2 = ((cmp1_V_load_1_fu_334_p3 < cmp1_V_load_13_1_fu_428_p3) ? 1'b1 : 1'b0);
assign tmp_1175_1_fu_258_p2 = ((p_Result_1231_1_fu_208_p4 == ap_const_lv2_0) ? 1'b1 : 1'b0);
assign tmp_1175_2_fu_328_p2 = ((p_Result_1231_2_fu_278_p4 == ap_const_lv2_0) ? 1'b1 : 1'b0);
assign tmp_1175_3_fu_422_p2 = ((p_Result_1231_3_fu_348_p4 == ap_const_lv2_0) ? 1'b1 : 1'b0);
assign tmp_1_fu_218_p2 = ((p_Result_1231_1_fu_208_p4 == ap_const_lv2_3) ? 1'b1 : 1'b0);
assign tmp_217_fu_414_p3 = ((sel_tmp28_fu_392_p2[0:0] === 1'b1) ? tmp_2763_fu_370_p3 : tmp_2764_fu_378_p3);
assign tmp_220_fu_454_p3 = ((sel_tmp1_fu_164_p2[0:0] === 1'b1) ? tmp_2765_fu_442_p1 : tmp_2766_fu_446_p3);
assign tmp_223_fu_478_p3 = ((sel_tmp10_fu_236_p2[0:0] === 1'b1) ? tmp_2767_fu_462_p3 : tmp_2768_fu_470_p3);
assign tmp_226_fu_528_p3 = ((sel_tmp19_fu_306_p2[0:0] === 1'b1) ? tmp_2769_fu_512_p3 : tmp_2770_fu_520_p3);
assign tmp_227_fu_552_p3 = ((tmp_1161_1_fu_506_p2[0:0] === 1'b1) ? tmp_226_fu_528_p3 : tmp_217_fu_414_p3);
assign tmp_228_fu_566_p3 = ((tmp_407_fu_436_p2[0:0] === 1'b1) ? tmp_220_fu_454_p3 : tmp_223_fu_478_p3);
assign tmp_2762_fu_142_p1 = dvl_V[1:0];
assign tmp_2763_fu_370_p3 = sth_V[ap_const_lv32_6];
assign tmp_2764_fu_378_p3 = sth_V[ap_const_lv32_7];
assign tmp_2765_fu_442_p1 = sth_V[0:0];
assign tmp_2766_fu_446_p3 = sth_V[ap_const_lv32_1];
assign tmp_2767_fu_462_p3 = sth_V[ap_const_lv32_2];
assign tmp_2768_fu_470_p3 = sth_V[ap_const_lv32_3];
assign tmp_2769_fu_512_p3 = sth_V[ap_const_lv32_4];
assign tmp_2770_fu_520_p3 = sth_V[ap_const_lv32_5];
assign tmp_2_fu_288_p2 = ((p_Result_1231_2_fu_278_p4 == ap_const_lv2_3) ? 1'b1 : 1'b0);
assign tmp_3_fu_358_p2 = ((p_Result_1231_3_fu_348_p4 == ap_const_lv2_3) ? 1'b1 : 1'b0);
assign tmp_404_fu_136_p2 = ((dth_0_V_read < dth_1_V_read) ? 1'b1 : 1'b0);
assign tmp_405_fu_152_p2 = ((tmp_2762_fu_142_p1 == ap_const_lv2_1) ? 1'b1 : 1'b0);
assign tmp_406_fu_188_p2 = ((tmp_2762_fu_142_p1 == ap_const_lv2_0) ? 1'b1 : 1'b0);
assign tmp_407_fu_436_p2 = ((cmp1_V_load_fu_194_p3 < cmp1_V_load_3_fu_264_p3) ? 1'b1 : 1'b0);
assign tmp_fu_146_p2 = ((tmp_2762_fu_142_p1 == ap_const_lv2_3) ? 1'b1 : 1'b0);
assign tmp_s_fu_560_p2 = ((a_bth_V_fu_498_p3 < a_bth_V_1_fu_544_p3) ? 1'b1 : 1'b0);
endmodule //sp_best_delta_seg1
|
// (c) Copyright 1995-2019 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 17
(* X_CORE_INFO = "axi_protocol_converter_v2_1_17_axi_protocol_converter,Vivado 2018.2" *)
(* CHECK_LICENSE_TYPE = "gcd_block_design_auto_pc_1,axi_protocol_converter_v2_1_17_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "gcd_block_design_auto_pc_1,axi_protocol_converter_v2_1_17_axi_protocol_converter,{x_ipProduct=Vivado 2018.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=17,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_A\
XI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module gcd_block_design_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_READ_\
THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 8, NUM_WRITE_OUTSTANDING 8, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN gcd_block_design_processing_system7_0_2_FCLK_CLK0, NUM_REA\
D_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_17_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`include "hglobal.v"
`default_nettype none
`define NS_NUM_TEST 6
`define NS_TEST_MIN_ADDR 0
`define NS_TEST_MAX_ADDR 55
`define NS_TEST_REF_ADDR 23
module test_top
#(parameter ASZ=`NS_ADDRESS_SIZE, DSZ=`NS_DATA_SIZE, RSZ=`NS_REDUN_SIZE)
(
input i_clk, // Main Clock (25 MHz)
input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output o_Segment1_A,
output o_Segment1_B,
output o_Segment1_C,
output o_Segment1_D,
output o_Segment1_E,
output o_Segment1_F,
output o_Segment1_G,
output o_Segment2_A,
output o_Segment2_B,
output o_Segment2_C,
output o_Segment2_D,
output o_Segment2_E,
output o_Segment2_F,
output o_Segment2_G,
output o_LED_1,
output o_LED_2,
output o_LED_3,
output o_LED_4
);
reg [0:0] reset = 0;
wire ready;
wire w_Switch_1;
reg r_Switch_1 = `NS_OFF;
wire w_Switch_2;
reg r_Switch_2 = `NS_OFF;
wire w_Switch_3;
reg r_Switch_3 = `NS_OFF;
wire w_Switch_4;
reg r_Switch_4 = `NS_OFF;
localparam TOT_DEBOUNCE_CLICK = 250000; // 10 ms at 25 MHz
`NS_DECLARE_GLB_LINK(gch0)
assign gch0_clk = i_clk;
assign gch0_reset = reset;
`NS_DEBOUNCER_DBG_BUT(gch0, 1)
`NS_DEBOUNCER_DBG_BUT(gch0, 2)
`NS_DEBOUNCER_DBG_BUT(gch0, 3)
`NS_DEBOUNCER_DBG_BUT(gch0, 4)
localparam CLK_WDH = 17;
localparam CLK_IDX_WDH = 2;
reg [CLK_WDH-1:0] lim_clks_arr [6:0]; // 2, 3, 5, 7, 11, 13, 17
reg [CLK_IDX_WDH:0] lims_idxs [3:0];
reg lims_idxs_inited = 0;
reg clk_lims_inited = 0;
`NS_DECLARE_DBG_CLK(kl0, 0, 17'b00000000000000010) // 2
`NS_DECLARE_DBG_CLK(kl1, 1, 2) // 3
`NS_DECLARE_DBG_CLK(kl2, 2, 2) // 5
`NS_DECLARE_DBG_CLK(kl3, 3, 2) // 7
reg [3:0] changing_clks = 0;
always @(posedge i_clk)
begin
if(changing_clks == 0) begin
`NS_INC_DBG_CLK(kl0, i_clk)
`NS_INC_DBG_CLK(kl1, i_clk)
`NS_INC_DBG_CLK(kl2, i_clk)
`NS_INC_DBG_CLK(kl3, i_clk)
end
end
always @(posedge i_clk)
begin
if(! clk_lims_inited) begin
clk_lims_inited <= 1;
lim_clks_arr[0] <= 17'b00000000000000010; // 2
lim_clks_arr[1] <= 17'b00000000000000100; // 3
lim_clks_arr[2] <= 17'b00000000000010000; // 5
lim_clks_arr[3] <= 17'b00000000001000000; // 7
lim_clks_arr[4] <= 17'b00000010000000000; // 11
lim_clks_arr[5] <= 17'b00001000000000000; // 13
lim_clks_arr[6] <= 17'b10000000000000000; // 17
end
end
reg [DSZ-1:0] disp_i_data = `NS_NUM_TEST;
reg [DSZ-1:0] disp_o_data = `NS_NUM_TEST;
//reg r_LED_1 = `NS_OFF;
reg r_LED_2 = `NS_OFF;
reg r_LED_3 = `NS_OFF;
reg r_LED_4 = `NS_OFF;
/*
wire err_0;
wire err_1;
wire err_2;
wire [DSZ-1:0] fst_err_0_inp;
wire [DSZ-1:0] fst_err_0_dat;
wire [DSZ-1:0] fst_err_1_inp;
wire [DSZ-1:0] fst_err_1_dat;
*/
`NS_DECLARE_DBG_LINK(dbg0)
// LNK_0
`NS_DECLARE_LINK(lnk_0)
// LNK_1_
`NS_DECLARE_LINK(lnk_1)
// LNK_2
`NS_DECLARE_LINK(lnk_2)
//wire [DSZ-1:0] lnk_2_ck_dat;
wire w_Segment1_A;
wire w_Segment1_B;
wire w_Segment1_C;
wire w_Segment1_D;
wire w_Segment1_E;
wire w_Segment1_F;
wire w_Segment1_G;
wire w_Segment2_A;
wire w_Segment2_B;
wire w_Segment2_C;
wire w_Segment2_D;
wire w_Segment2_E;
wire w_Segment2_F;
wire w_Segment2_G;
nd_2to1
gt1to2 (
`NS_INSTA_GLB_CHNL_VALS(gch, i_clk, reset, ready),
//i_clk, clk_kl3
//.i_clk(i_clk),
// out0
`NS_INSTA_SND_CHNL(snd0, lnk_0),
// in0
`NS_INSTA_RCV_CHNL(rcv0, lnk_1),
// in1
`NS_INSTA_RCV_CHNL(rcv1, lnk_2)
);
io_2to1 #(.MIN_ADDR(`NS_TEST_MIN_ADDR), .MAX_ADDR(`NS_TEST_MAX_ADDR))
io_t6 (
.src0_clk(clk_kl0),
.src1_clk(clk_kl1),
.snk0_clk(clk_kl2),
.reset(reset),
//i_clk, clk_0, clk_1
// 1,1,0 fails
// 0,1,2 fails
// SRC0
`NS_INSTA_SND_CHNL(o0, lnk_1),
// SRC1
`NS_INSTA_SND_CHNL(o1, lnk_2),
// SNK0
`NS_INSTA_RCV_CHNL(i0, lnk_0),
`NS_INSTA_DBG_CHNL(dbg, dbg0, i_clk)
);
localparam TOT_TM_LIMS = 250000;
reg [$clog2(TOT_TM_LIMS):0] cnt_inc_lims = 0;
always @(posedge i_clk)
begin
if(cnt_inc_lims == TOT_TM_LIMS) begin
cnt_inc_lims <= 1;
`NS_INC_DBG_IDXS_ARR(lims_idxs, 6)
`NS_SET_LIM_DBG_CLK(kl0, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl1, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl2, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl3, lim_clks_arr, lims_idxs)
end
else begin
cnt_inc_lims <= cnt_inc_lims + 1;
end
end
/*
wire sw1_ON = ((w_Switch_1 == `NS_ON) && (r_Switch_1 == `NS_OFF));
wire sw1_OFF = ((w_Switch_1 == `NS_OFF) && (r_Switch_1 == `NS_ON));
always @(posedge i_clk)
begin
r_Switch_1 <= w_Switch_1;
if(sw1_ON)
begin
if(changing_clks == 0) begin
changing_clks <= 1;
end
end
if(changing_clks == 1) begin
changing_clks <= 2;
if(clk_lims_inited) begin
`NS_INC_DBG_IDXS_ARR(lims_idxs, 6)
`NS_SET_LIM_DBG_CLK(kl0, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl1, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl2, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl3, lim_clks_arr, lims_idxs)
end
end
if(changing_clks == 2) begin
changing_clks <= 0;
end
end
*/
wire sw2_ON = ((w_Switch_2 == `NS_ON) && (r_Switch_2 == `NS_OFF));
wire sw2_OFF = ((w_Switch_2 == `NS_OFF) && (r_Switch_2 == `NS_ON));
always @(posedge i_clk)
begin
r_Switch_2 <= w_Switch_2;
if(sw2_ON)
begin
/*if(clk_lims_inited) begin
lims_idxs[0] <= 2;
lims_idxs[1] <= 0;
lims_idxs[2] <= 0;
lims_idxs[3] <= 0;
`NS_SET_LIM_DBG_CLK(kl0, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl1, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl2, lim_clks_arr, lims_idxs)
`NS_SET_LIM_DBG_CLK(kl3, lim_clks_arr, lims_idxs)
end*/
end
end
/*
localparam TOT_DEBOUNCE_CLICK = 250000; // 10 ms at 25 MHz
debouncer #(.TOT_CKS(TOT_DEBOUNCE_CLICK))
sw1_inst(
.i_Clk(i_clk),
.i_Switch(i_Switch_1),
.o_Switch(w_Switch_1)
);
always @(posedge i_clk)
begin
r_Switch_1 <= w_Switch_1;
if((w_Switch_1 == `NS_ON) && (r_Switch_1 == `NS_OFF))
begin
if(err_0 || err_1 || err_2) begin
disp_i_data <= fst_err_0_inp;
disp_o_data <= fst_err_0_dat;
end else begin
disp_i_data <= lnk_0_dat;
disp_o_data <= lnk_0_ck_dat;
end
end
end
bin_to_disp disp_1(
.i_Clk(i_clk),
.i_Binary_Num(disp_i_data),
.o_Segment_A(w_Segment1_A),
.o_Segment_B(w_Segment1_B),
.o_Segment_C(w_Segment1_C),
.o_Segment_D(w_Segment1_D),
.o_Segment_E(w_Segment1_E),
.o_Segment_F(w_Segment1_F),
.o_Segment_G(w_Segment1_G)
);
bin_to_disp disp2(
.i_Clk(i_clk),
.i_Binary_Num(disp_o_data),
.o_Segment_A(w_Segment2_A),
.o_Segment_B(w_Segment2_B),
.o_Segment_C(w_Segment2_C),
.o_Segment_D(w_Segment2_D),
.o_Segment_E(w_Segment2_E),
.o_Segment_F(w_Segment2_F),
.o_Segment_G(w_Segment2_G)
);
assign o_Segment1_A = ~w_Segment1_A;
assign o_Segment1_B = ~w_Segment1_B;
assign o_Segment1_C = ~w_Segment1_C;
assign o_Segment1_D = ~w_Segment1_D;
assign o_Segment1_E = ~w_Segment1_E;
assign o_Segment1_F = ~w_Segment1_F;
assign o_Segment1_G = ~w_Segment1_G;
assign o_Segment2_A = ~w_Segment2_A;
assign o_Segment2_B = ~w_Segment2_B;
assign o_Segment2_C = ~w_Segment2_C;
assign o_Segment2_D = ~w_Segment2_D;
assign o_Segment2_E = ~w_Segment2_E;
assign o_Segment2_F = ~w_Segment2_F;
assign o_Segment2_G = ~w_Segment2_G;
*/
assign o_Segment1_A = ~(lims_idxs[0][0]);
assign o_Segment1_B = ~(lims_idxs[0][1]);
assign o_Segment1_C = ~(lims_idxs[0][2]);
assign o_Segment1_D = ~(lims_idxs[1][0]);
assign o_Segment1_E = ~(lims_idxs[1][1]);
assign o_Segment1_F = ~(lims_idxs[1][2]);
assign o_Segment1_G = 1;
assign o_Segment2_A = ~(lims_idxs[2][0]);
assign o_Segment2_B = ~(lims_idxs[2][1]);
assign o_Segment2_C = ~(lims_idxs[2][2]);
assign o_Segment2_D = ~(lims_idxs[3][0]);
assign o_Segment2_E = ~(lims_idxs[3][1]);
assign o_Segment2_F = ~(lims_idxs[3][2]);
assign o_Segment2_G = 1;
assign o_LED_1 = dbg0_leds[0:0];
assign o_LED_2 = dbg0_leds[1:1];
assign o_LED_3 = dbg0_leds[2:2];
assign o_LED_4 = dbg0_leds[3:3];
endmodule
|
module wb_mem_2_ppfifo(
input clk,
input rst,
output [31:0] debug,
//Control
input i_enable,
input [31:0] i_memory_0_base,
input [31:0] i_memory_0_size,
output [31:0] o_memory_0_count,
input i_memory_0_new_data,
output o_memory_0_empty,
input [31:0] o_default_mem_0_base,
input [31:0] i_memory_1_base,
input [31:0] i_memory_1_size,
output [31:0] o_memory_1_count,
input i_memory_1_new_data,
output o_memory_1_empty,
input [31:0] o_default_mem_1_base,
output reg o_read_finished,
//master control signal for memory arbitration
output reg o_mem_we,
output reg o_mem_stb,
output reg o_mem_cyc,
output reg [3:0] o_mem_sel,
output [31:0] o_mem_adr,
output reg [31:0] o_mem_dat,
input [31:0] i_mem_dat,
input i_mem_ack,
input i_mem_int,
//Ping Pong FIFO Interface
input [1:0] i_ppfifo_rdy,
output reg [1:0] o_ppfifo_act,
input [23:0] i_ppfifo_size,
output reg o_ppfifo_stb,
output [31:0] o_ppfifo_data
);
//Local Parameters
//States
localparam IDLE = 4'h0;
localparam GET_MEMORY_BLOCK = 4'h1;
localparam READ_DATA = 4'h2;
localparam FINISHED = 4'h3;
//Registers/Wires
reg [23:0] r_ppfifo_count; //Ping Pong FIFO Count
reg [31:0] r_mem_read_size; //Current Memory Size to read
wire [31:0] w_mem_base [1:0];
reg [31:0] r_mem_ptr [1:0];
wire [31:0] r_mem_count [1:0];
wire [31:0] w_mem_0_ptr;
wire [31:0] w_mem_1_ptr;
wire [31:0] w_mem_0_count;
wire [31:0] w_mem_1_count;
wire [31:0] w_mem_0_base;
reg r_active_bank;
reg r_memory_ready;
reg [3:0] state;
//Submodules
//Asynchronous Logic
//Debug Assignments
//assign debug[19:0] = r_mem_ptr[r_active_bank];
//assign debug[20] = ((r_mem_ptr[r_active_bank] == 0) && (o_mem_cyc == 1));
//assign debug[21] = o_memory_0_empty;
//assign debug[22] = o_ppfifo_stb;
//assign debug[26:23] = state;
//assign debug[27] = r_active_bank;
//assign debug[28] = r_memory_ready;
//
//assign debug[3] = r_memory_ready;
//assign debug[7:4] = state;
//assign debug[8] = o_read_finished;
//assign debug[10] = o_memory_1_empty;
//assign debug[13:12] = i_ppfifo_rdy;
//assign debug[15:14] = o_ppfifo_act;
//assign debug[1] = i_mem_dat[31];
assign debug[1] = o_mem_cyc;
assign debug[2] = o_mem_stb;
assign debug[3] = i_mem_ack;
assign debug[4] = i_mem_dat[31];
assign debug[11] = ((r_mem_ptr[r_active_bank] == 0) && (o_mem_cyc == 1));
assign debug[12] = r_active_bank;
assign debug[13] = r_memory_ready;
assign debug[14] = o_memory_0_empty;
assign debug[15] = o_ppfifo_stb;
assign debug[31:16] = i_mem_dat[23:8];
//assign o_default_mem_0_base = 32'h00000000;
//assign o_default_mem_1_base = 32'h00080000;
assign o_ppfifo_data = i_mem_dat;
assign o_mem_adr = w_mem_base[r_active_bank] + r_mem_ptr[r_active_bank];
assign r_mem_count[0] = i_memory_0_size - r_mem_ptr[0];
assign r_mem_count[1] = i_memory_1_size - r_mem_ptr[1];
assign o_memory_0_empty = (r_mem_count[0] == 0);
assign o_memory_1_empty = (r_mem_count[1] == 0);
//assign w_mem_0_empty = (r_mem_count[0] == 0);
//assign w_mem_1_empty = (r_mem_count[1] == 0);
assign o_memory_0_count = r_mem_count[0];
assign o_memory_1_count = r_mem_count[1];
assign w_mem_0_ptr = r_mem_ptr[0];
assign w_mem_1_ptr = r_mem_ptr[1];
assign w_mem_base[0] = i_memory_0_base;
assign w_mem_base[1] = i_memory_1_base;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_read_finished <= 0;
//Wishbone Bus Signals
o_mem_we <= 0;
o_mem_stb <= 0;
o_mem_cyc <= 0;
o_mem_sel <= 4'b1111;
o_mem_dat <= 32'h00000000;
//Ping Pong FIFO Signals
o_ppfifo_act <= 0;
o_ppfifo_stb <= 0;
r_ppfifo_count <= 0;
//Memory Interface
r_mem_read_size <= 0;
r_mem_ptr[0] <= 0;
r_mem_ptr[1] <= 0;
state <= IDLE;
end
else begin
//De-assert Strobes
o_ppfifo_stb <= 0;
o_read_finished <= 0;
//Grab an Available FIFO if the core is activated
if (i_enable) begin
if ((i_ppfifo_rdy > 0) && (o_ppfifo_act == 0)) begin
r_ppfifo_count <= 0;
if (i_ppfifo_rdy[0]) begin
o_ppfifo_act[0] <= 1;
end
else begin
o_ppfifo_act[1] <= 1;
end
end
end
case (state)
IDLE: begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
if (i_enable) begin
state <= GET_MEMORY_BLOCK;
end
end
GET_MEMORY_BLOCK: begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
if (r_memory_ready) begin
r_mem_read_size <= r_mem_count[r_active_bank];
state <= READ_DATA;
end
else begin
if (!i_enable) begin
state <= IDLE;
end
end
end
READ_DATA: begin
if (r_mem_ptr[r_active_bank] < r_mem_read_size) begin
//If the FIFO has room
if (o_ppfifo_act > 0) begin
if (r_ppfifo_count < i_ppfifo_size) begin
o_mem_cyc <= 1;
o_mem_stb <= 1;
//Ping Pong FIFO has room
//if we received data from the memory bus, read them in
if (i_mem_ack && o_mem_stb) begin
r_ppfifo_count <= r_ppfifo_count + 1;
r_mem_ptr[r_active_bank] <= r_mem_ptr[r_active_bank] + 1;
o_ppfifo_stb <= 1;
o_mem_stb <= 0;
end
end
else begin
//Release the Activate
//Release the Wishbone cycle so the host has a chance to write
//data
o_mem_cyc <= 0;
o_mem_stb <= 0;
o_ppfifo_act <= 0;
end
end
else begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
end
end
else begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
state <= FINISHED;
end
end
FINISHED: begin
o_mem_cyc <= 0;
o_mem_stb <= 0;
//If a memory block is not active but there is data in a PPFIFO
//Then we need to flush it, this usually happens at the end of
//a write
o_read_finished <= 1; //Launch a signal to indicate that we
//consumed a block of memory
if (r_ppfifo_count > 0) begin
//Flush the FIFO
r_ppfifo_count <= 0;
o_ppfifo_act <= 0;
end
state <= GET_MEMORY_BLOCK;
end
endcase
end
//Reset the pointers
if (i_memory_0_new_data) begin
r_mem_ptr[0] <= 0;
end
if (i_memory_1_new_data) begin
r_mem_ptr[1] <= 0;
end
end
//Bank Select and Memory Ready
always @ (posedge clk) begin
if (rst) begin
r_active_bank <= 0;
r_memory_ready <= 0;
end
else begin
//Activate Memory Logic
if (!r_memory_ready) begin
//If there is any data at all in the memory blocks
if (r_mem_count[0] > 0) begin
r_memory_ready <= 1;
r_active_bank <= 0;
end
else if (r_mem_count[1] > 0) begin
r_memory_ready <= 1;
r_active_bank <= 1;
end
end
else begin
//If we're currently active and the active block is empty
//disable the block
if ((r_active_bank == 0) && (r_mem_count[0] == 0) && (!o_ppfifo_stb)) begin
r_memory_ready <= 0;
end
else if ((r_active_bank == 1) && (r_mem_count[1] == 0) && (!o_ppfifo_stb)) begin
r_memory_ready <= 0;
end
end
end
end
//Simulation information
always @ (posedge clk) begin
if (o_ppfifo_stb) begin
`ifdef VERBOSE: $display ("\twb_mem_2_ppfifo: Wrote: %h: Write Count: %h", o_ppfifo_data, r_ppfifo_count); `endif
end
end
endmodule
|
module motor_dummy_control #(parameter BASE_ADR = 10'h0,
parameter CLOCK_FREQUENCY = 16000000,
parameter MAX_SPEED = 100,
parameter PWM_FREQ = 100,
parameter SOFT_START_LENGTH = 5000,
parameter SOFT_START_EXPONENTIAL = "FALSE",
parameter END_SW_DETECTION_LENGTH = 128) (
//*** Connections to SpartanMC Core (do not change) ***
input wire clk_peri, //System-Clock
input wire [17:0] do_peri, //Data Bus from MC
output wire [17:0] di_peri, //Data Bus to MC
input wire [9:0] addr_peri, //Address Bus from MC
input wire access_peri, //Peripheral Access Signal
input wire wr_peri, //Write Enable Signal
//*** Connections to SpartanMC Core which can be changed ***
input wire reset, //Reset-Signal (could be external)
//*** io interface ***
output reg active,
output reg direction,
input wire end_sw_down,
input wire end_sw_up,
output reg dest_reached
);
parameter PWM_REG_WIDTH = 32;
wire select;
// Address decoder generates the select sinal out of the upper part of the peripheral address.
pselect iCSL (
.addr ( addr_peri[9:0] ),
.activ_peri ( access_peri ),
.select ( select )
);
defparam iCSL.ADDR_WIDTH = 10;
defparam iCSL.BASE_WIDTH = 10;
defparam iCSL.BASE_ADDR = BASE_ADR;
//control registers
reg destination;
wire active_int;
wire end_sw_down_wire;
wire end_sw_up_wire;
reg [END_SW_DETECTION_LENGTH-1:0] end_sw_down_regs;
reg [END_SW_DETECTION_LENGTH-1:0] end_sw_up_regs;
reg [PWM_REG_WIDTH-1:0] pwm_counter;
reg [PWM_REG_WIDTH-1:0] pwm_on_time;
wire pwm;
assign pwm = (pwm_counter < pwm_on_time);
//delay read signals by one cycle (for new pipeline)
reg read_access;
always @(posedge clk_peri) begin
read_access <= (select & !wr_peri);
end
assign di_peri = read_access ? {16'd0, direction, active_int} : 18'b0;
assign active_int = (destination ? end_sw_up_wire : end_sw_down_wire) && !dest_reached;
always @(posedge clk_peri) begin
direction <= destination;
active <= (active_int & pwm) ^ direction;
end
//SpartanMC peripheral interface logic
always @(posedge clk_peri) begin
if (reset) begin
destination <= 1'b0;
dest_reached <= 1'b1;
end else begin
if (select & wr_peri) begin
destination <= do_peri[0];
dest_reached <= 1'b0;
end else begin
dest_reached <= !active_int;
end
end
end
assign end_sw_down_wire = !(end_sw_down_regs == {(END_SW_DETECTION_LENGTH){1'b1}}); //end sw is only pressed when all recorded values in shift register are 1
assign end_sw_up_wire = !(end_sw_up_regs == {(END_SW_DETECTION_LENGTH){1'b1}});
always @(posedge clk_peri) begin
end_sw_down_regs <= {end_sw_down_regs[END_SW_DETECTION_LENGTH-2:0], end_sw_down}; //shift register, shift end_sw_down in
end_sw_up_regs <= {end_sw_up_regs[END_SW_DETECTION_LENGTH-2:0], end_sw_up}; //shift register, shift end_sw_up in
end
parameter PWM_CYCLE = CLOCK_FREQUENCY / PWM_FREQ;
parameter PWM_MAX_ON_TIME = PWM_CYCLE * MAX_SPEED / 100;
parameter SOFT_START_INCREASE = PWM_MAX_ON_TIME * 1000 / (SOFT_START_LENGTH * PWM_FREQ);
//PWM logic
always @(posedge clk_peri) begin
if (active_int == 0) begin
pwm_counter <= {(PWM_REG_WIDTH){1'b0}};
pwm_on_time <= {(PWM_REG_WIDTH){1'b0}};
end else begin
if (pwm_counter == PWM_CYCLE) begin
pwm_counter <= {(PWM_REG_WIDTH){1'b0}};
if (pwm_on_time < PWM_MAX_ON_TIME) begin //increase on_time if smaller than max value
if (SOFT_START_EXPONENTIAL == "FALSE") begin
pwm_on_time <= pwm_on_time + SOFT_START_INCREASE;
end else begin
pwm_on_time <= pwm_on_time + 1 + (pwm_on_time >> SOFT_START_LENGTH); //+1 for start phase, otherwise 0+0
end
end
end else begin
pwm_counter <= pwm_counter + 1;
end
end
end
endmodule |
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 29-10-2018
*/
module jt12_eg_pure(
input attack,
input step,
input [ 5:1] rate,
input [ 9:0] eg_in,
input ssg_en,
input sum_up,
output reg [9:0] eg_pure
);
reg [ 3:0] dr_sum;
reg [ 9:0] dr_adj;
reg [10:0] dr_result;
always @(*) begin : dr_calculation
case( rate[5:2] )
4'b1100: dr_sum = { 2'b0, step, ~step }; // 12
4'b1101: dr_sum = { 1'b0, step, ~step, 1'b0 }; // 13
4'b1110: dr_sum = { step, ~step, 2'b0 }; // 14
4'b1111: dr_sum = 4'd8;// 15
default: dr_sum = { 2'b0, step, 1'b0 };
endcase
// Decay rate attenuation is multiplied by 4 for SSG operation
dr_adj = ssg_en ? {4'd0, dr_sum, 2'd0} : {6'd0, dr_sum};
dr_result = dr_adj + eg_in;
end
reg [ 7:0] ar_sum0;
reg [ 8:0] ar_sum1;
reg [10:0] ar_result;
reg [ 9:0] ar_sum;
always @(*) begin : ar_calculation
casez( rate[5:2] )
default: ar_sum0 = {2'd0, eg_in[9:4]};
4'b1101: ar_sum0 = {1'd0, eg_in[9:3]};
4'b111?: ar_sum0 = eg_in[9:2];
endcase
ar_sum1 = ar_sum0+9'd1;
if( rate[5:4] == 2'b11 )
ar_sum = step ? { ar_sum1, 1'b0 } : { 1'b0, ar_sum1 };
else
ar_sum = step ? { 1'b0, ar_sum1 } : 10'd0;
ar_result = eg_in-ar_sum;
end
///////////////////////////////////////////////////////////
// rate not used below this point
reg [9:0] eg_pre_fastar; // pre fast attack rate
always @(*) begin
if(sum_up) begin
if( attack )
eg_pre_fastar = ar_result[10] ? 10'd0: ar_result[9:0];
else
eg_pre_fastar = dr_result[10] ? 10'h3FF : dr_result[9:0];
end
else eg_pre_fastar = eg_in;
eg_pure = (attack&rate[5:1]==5'h1F) ? 10'd0 : eg_pre_fastar;
end
endmodule // jt12_eg_pure |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFSBP_2_V
`define SKY130_FD_SC_MS__DFSBP_2_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfsbp_2 (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFSBP_2_V
|
// *******************************************************************************************************
// ** **
// ** 23LC1024.v - 23LC1024 1 MBIT SPI SERIAL SRAM (VCC = +2.5V TO +5.5V) **
// ** **
// *******************************************************************************************************
// ** **
// ** This information is distributed under license from Young Engineering. **
// ** COPYRIGHT (c) 2014 YOUNG ENGINEERING **
// ** ALL RIGHTS RESERVED **
// ** **
// ** **
// ** Young Engineering provides design expertise for the digital world **
// ** Started in 1990, Young Engineering offers products and services for your electronic design **
// ** project. We have the expertise in PCB, FPGA, ASIC, firmware, and software design. **
// ** From concept to prototype to production, we can help you. **
// ** **
// ** http://www.young-engineering.com/ **
// ** **
// *******************************************************************************************************
// ** **
// ** This information is provided to you for your convenience and use with Microchip products only. **
// ** Microchip disclaims all liability arising from this information and its use. **
// ** **
// ** THIS INFORMATION IS PROVIDED "AS IS." MICROCHIP MAKES NO REPRESENTATION OR WARRANTIES OF **
// ** ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO **
// ** THE INFORMATION PROVIDED TO YOU, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, **
// ** PERFORMANCE, MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR PURPOSE. **
// ** MICROCHIP IS NOT LIABLE, UNDER ANY CIRCUMSTANCES, FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL **
// ** DAMAGES, FOR ANY REASON WHATSOEVER. **
// ** **
// ** It is your responsibility to ensure that your application meets with your specifications. **
// ** **
// *******************************************************************************************************
// ** **
// ** Revision : 1.0 **
// ** Modified Date : 04/23/2014 **
// ** Revision History: **
// ** **
// ** 04/23/2014: Initial design **
// ** **
// *******************************************************************************************************
// ** TABLE OF CONTENTS **
// *******************************************************************************************************
// **---------------------------------------------------------------------------------------------------**
// ** DECLARATIONS **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** INITIALIZATION **
// **---------------------------------------------------------------------------------------------------**
// **---------------------------------------------------------------------------------------------------**
// ** CORE LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 1.01: Internal Reset Logic **
// ** 1.02: Input Data Shifter **
// ** 1.03: Clock Cycle Counter **
// ** 1.04: Instruction Register **
// ** 1.05: Address Register **
// ** 1.06: Status Register Write **
// ** 1.07: I/O Mode Instructions **
// ** 1.08: Array Write **
// ** 1.09: Output Data Shifter **
// ** 1.10: Output Data Buffer **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** DEBUG LOGIC **
// **---------------------------------------------------------------------------------------------------**
// ** 2.01: Memory Data Bytes **
// ** **
// **---------------------------------------------------------------------------------------------------**
// ** TIMING CHECKS **
// **---------------------------------------------------------------------------------------------------**
// ** **
// *******************************************************************************************************
`timescale 1ns/10ps
module M23LC1024 (SI_SIO0, SO_SIO1, SCK, CS_N, SIO2, HOLD_N_SIO3, RESET);
inout SI_SIO0; // serial data input/output
input SCK; // serial data clock
input CS_N; // chip select - active low
inout SIO2; // serial data input/output
inout HOLD_N_SIO3; // interface suspend - active low/
// serial data input/output
input RESET; // model reset/power-on reset
inout SO_SIO1; // serial data input/output
// *******************************************************************************************************
// ** DECLARATIONS **
// *******************************************************************************************************
reg [07:00] DataShifterI; // serial input data shifter
reg [07:00] DataShifterO; // serial output data shifter
reg [31:00] ClockCounter; // serial input clock counter
reg [07:00] InstRegister; // instruction register
reg [16:00] AddrRegister; // address register
wire InstructionREAD; // decoded instruction byte
wire InstructionRDMR; // decoded instruction byte
wire InstructionWRMR; // decoded instruction byte
wire InstructionWRITE; // decoded instruction byte
wire InstructionEDIO; // decoded instruction byte
wire InstructionEQIO; // decoded instruction byte
wire InstructionRSTIO; // decoded instruction byte
reg [01:00] OpMode; // operation mode
reg [01:00] IOMode; // I/O mode
wire Hold; // hold function
reg [07:00] MemoryBlock [0:131071]; // SRAM data memory array (131072x8)
reg [03:00] SO_DO; // serial output data - data
wire SO_OE; // serial output data - output enable
reg SO_Enable; // serial data output enable
wire OutputEnable1; // timing accurate output enable
wire OutputEnable2; // timing accurate output enable
wire OutputEnable3; // timing accurate output enable
integer tV; // timing parameter
integer tHZ; // timing parameter
integer tHV; // timing parameter
integer tDIS; // timing parameter
`define READ 8'b0000_0011 // Read instruction
`define WRMR 8'b0000_0001 // Write Mode Register instruction
`define WRITE 8'b0000_0010 // Write instruction
`define RDMR 8'b0000_0101 // Read Mode Register instruction
`define EDIO 8'b0011_1011 // Enter Dual I/O instruction
`define EQIO 8'b0011_1000 // Enter Quad I/O instruction
`define RSTIO 8'b1111_1111 // Reset Dual and Quad I/O instruction
`define BYTEMODE 2'b00 // Byte operation mode
`define PAGEMODE 2'b10 // Page operation mode
`define SEQMODE 2'b01 // Sequential operation mode
`define SPIMODE 2'b00 // SPI I/O mode
`define SDIMODE 2'b01 // SDI I/O mode
`define SQIMODE 2'b10 // SQI I/O mode
// *******************************************************************************************************
// ** INITIALIZATION **
// *******************************************************************************************************
initial begin
`ifdef TEMP_INDUSTRIAL
tV = 25; // output valid from SCK low
tHZ = 10; // HOLD_N low to output high-z
tHV = 50; // HOLD_N high to output valid
tDIS = 20; // CS_N high to output disable
`else
`ifdef TEMP_EXTENDED
tV = 32; // output valid from SCK low
tHZ = 10; // HOLD_N low to output high-z
tHV = 50; // HOLD_N high to output valid
tDIS = 20; // CS_N high to output disable
`else
tV = 25; // output valid from SCK low
tHZ = 10; // HOLD_N low to output high-z
tHV = 50; // HOLD_N high to output valid
tDIS = 20; // CS_N high to output disable
`endif
`endif
end
initial begin
OpMode = `SEQMODE;
IOMode = `SPIMODE;
end
assign Hold = (HOLD_N_SIO3 == 0) & (IOMode == `SPIMODE);
// *******************************************************************************************************
// ** CORE LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 1.01: Internal Reset Logic
// -------------------------------------------------------------------------------------------------------
always @(negedge CS_N) ClockCounter <= 0;
always @(negedge CS_N) SO_Enable <= 0;
// -------------------------------------------------------------------------------------------------------
// 1.02: Input Data Shifter
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (Hold == 0) begin
if (CS_N == 0) begin
case (IOMode)
`SPIMODE: DataShifterI <= {DataShifterI[06:00],SI_SIO0};
`SDIMODE: DataShifterI <= {DataShifterI[05:00],SO_SIO1,SI_SIO0};
`SQIMODE: DataShifterI <= {DataShifterI[03:00],HOLD_N_SIO3,SIO2,SO_SIO1,SI_SIO0};
default: $error("IOMode set to invalid value.");
endcase
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.03: Clock Cycle Counter
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (Hold == 0) begin
if (CS_N == 0) ClockCounter <= ClockCounter + 1;
end
end
// -------------------------------------------------------------------------------------------------------
// 1.04: Instruction Register
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (Hold == 0) begin
case (IOMode)
`SPIMODE: begin
if (ClockCounter == 7) InstRegister <= {DataShifterI[06:00],SI_SIO0};
end
`SDIMODE: begin
if (ClockCounter == 3) InstRegister <= {DataShifterI[05:00],SO_SIO1,SI_SIO0};
end
`SQIMODE: begin
if (ClockCounter == 1) InstRegister <= {DataShifterI[03:00],HOLD_N_SIO3,SIO2,SO_SIO1,SI_SIO0};
end
default: $error("IOMode set to invalid value.");
endcase
end
end
assign InstructionREAD = (InstRegister[7:0] == `READ);
assign InstructionRDMR = (InstRegister[7:0] == `RDMR);
assign InstructionWRMR = (InstRegister[7:0] == `WRMR);
assign InstructionWRITE = (InstRegister[7:0] == `WRITE);
assign InstructionEDIO = (InstRegister[7:0] == `EDIO);
assign InstructionEQIO = (InstRegister[7:0] == `EQIO);
assign InstructionRSTIO = (InstRegister[7:0] == `RSTIO);
// -------------------------------------------------------------------------------------------------------
// 1.05: Address Register
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (Hold == 0 & (InstructionREAD | InstructionWRITE)) begin
case (IOMode)
`SPIMODE: begin
if (ClockCounter == 15) AddrRegister[16] <= SI_SIO0;
else if (ClockCounter == 23) AddrRegister[15:08] <= {DataShifterI[06:00],SI_SIO0};
else if (ClockCounter == 31) AddrRegister[07:00] <= {DataShifterI[06:00],SI_SIO0};
end
`SDIMODE: begin
if (ClockCounter == 7) AddrRegister[16] <= SI_SIO0;
else if (ClockCounter == 11) AddrRegister[15:08] <= {DataShifterI[05:00],SO_SIO1,SI_SIO0};
else if (ClockCounter == 15) AddrRegister[07:00] <= {DataShifterI[05:00],SO_SIO1,SI_SIO0};
end
`SQIMODE: begin
if (ClockCounter == 3) AddrRegister[16] <= SI_SIO0;
else if (ClockCounter == 5) AddrRegister[15:08] <= {DataShifterI[03:00],HOLD_N_SIO3,SIO2,SO_SIO1,SI_SIO0};
else if (ClockCounter == 7) AddrRegister[07:00] <= {DataShifterI[03:00],HOLD_N_SIO3,SIO2,SO_SIO1,SI_SIO0};
end
default: $error("IOMode set to invalid value.");
endcase
end
end
// -------------------------------------------------------------------------------------------------------
// 1.06: Status Register Write
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (Hold == 0 & InstructionWRMR) begin
case (IOMode)
`SPIMODE: begin
if (ClockCounter == 15) OpMode <= DataShifterI[06:05];
end
`SDIMODE: begin
if (ClockCounter == 7) OpMode <= DataShifterI[05:04];
end
`SQIMODE: begin
if (ClockCounter == 3) OpMode <= DataShifterI[03:02];
end
default: $error("IOMode set to invalid value.");
endcase
end
end
// -------------------------------------------------------------------------------------------------------
// 1.07: I/O Mode Instructions
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
case (IOMode)
`SPIMODE: begin
if (ClockCounter == 7) begin
if ({DataShifterI[06:00],SI_SIO0} == `EDIO) IOMode <= `SDIMODE;
else if ({DataShifterI[06:00],SI_SIO0} == `EQIO) IOMode <= `SQIMODE;
end
end
`SDIMODE: begin
if (ClockCounter == 3) begin
if ({DataShifterI[05:00],SO_SIO1,SI_SIO0} == `EQIO) IOMode <= `SQIMODE;
else if ({DataShifterI[05:00],SO_SIO1,SI_SIO0} == `RSTIO) IOMode <= `SPIMODE;
end
end
`SQIMODE: begin
if (ClockCounter == 1) begin
if ({DataShifterI[03:00],HOLD_N_SIO3,SIO2,SO_SIO1,SI_SIO0} == `EDIO) IOMode <= `SDIMODE;
else if ({DataShifterI[03:00],HOLD_N_SIO3,SIO2,SO_SIO1,SI_SIO0} == `RSTIO) IOMode <= `SPIMODE;
end
end
endcase
end
// -------------------------------------------------------------------------------------------------------
// 1.08: Array Write
// -------------------------------------------------------------------------------------------------------
always @(posedge SCK) begin
if (Hold == 0 & InstructionWRITE) begin
case (IOMode)
`SPIMODE: begin
if ((ClockCounter >= 39) & (ClockCounter[2:0] == 3'b111)) begin
MemoryBlock[AddrRegister[16:00]] <= {DataShifterI[06:00],SI_SIO0};
case (OpMode)
`PAGEMODE: AddrRegister[04:00] <= AddrRegister[04:00] + 1;
`SEQMODE: AddrRegister[16:00] <= AddrRegister[16:00] + 1;
endcase
end
end
`SDIMODE: begin
if ((ClockCounter >= 19) & (ClockCounter[1:0] == 2'b11)) begin
MemoryBlock[AddrRegister[16:00]] <= {DataShifterI[05:00],SO_SIO1,SI_SIO0};
case (OpMode)
`PAGEMODE: AddrRegister[04:00] <= AddrRegister[04:00] + 1;
`SEQMODE: AddrRegister[16:00] <= AddrRegister[16:00] + 1;
endcase
end
end
`SQIMODE: begin
if ((ClockCounter >= 9) & (ClockCounter[0] == 1'b1)) begin
MemoryBlock[AddrRegister[16:00]] <= {DataShifterI[03:00],HOLD_N_SIO3,SIO2,SO_SIO1,SI_SIO0};
case (OpMode)
`PAGEMODE: AddrRegister[04:00] <= AddrRegister[04:00] + 1;
`SEQMODE: AddrRegister[16:00] <= AddrRegister[16:00] + 1;
endcase
end
end
default: $error("IOMode set to invalid value.");
endcase
end
end
// -------------------------------------------------------------------------------------------------------
// 1.09: Output Data Shifter
// -------------------------------------------------------------------------------------------------------
always @(negedge SCK) begin
if (Hold == 0) begin
if (InstructionREAD) begin
case (IOMode)
`SPIMODE: begin
if ((ClockCounter >= 32) & (ClockCounter[2:0] == 3'b000)) begin
DataShifterO <= MemoryBlock[AddrRegister[16:00]];
SO_Enable <= 1;
case (OpMode)
`PAGEMODE: AddrRegister[04:00] <= AddrRegister[04:00] + 1;
`SEQMODE: AddrRegister[16:00] <= AddrRegister[16:00] + 1;
endcase
end
else DataShifterO <= DataShifterO << 1;
end
`SDIMODE: begin
if ((ClockCounter >= 20) & (ClockCounter[1:0] == 2'b00)) begin
DataShifterO <= MemoryBlock[AddrRegister[16:00]];
SO_Enable <= 1;
case (OpMode)
`PAGEMODE: AddrRegister[04:00] <= AddrRegister[04:00] + 1;
`SEQMODE: AddrRegister[16:00] <= AddrRegister[16:00] + 1;
endcase
end
else DataShifterO <= DataShifterO << 2;
end
`SQIMODE: begin
if ((ClockCounter >= 10) & (ClockCounter[0] == 1'b0)) begin
DataShifterO <= MemoryBlock[AddrRegister[16:00]];
SO_Enable <= 1;
case (OpMode)
`PAGEMODE: AddrRegister[04:00] <= AddrRegister[04:00] + 1;
`SEQMODE: AddrRegister[16:00] <= AddrRegister[16:00] + 1;
endcase
end
else DataShifterO <= DataShifterO << 4;
end
default: $error("IOMode set to invalid value.");
endcase
end
else if (InstructionRDMR) begin
case (IOMode)
`SPIMODE: begin
if ((ClockCounter > 7) & (ClockCounter[2:0] == 3'b000)) begin
DataShifterO <= {OpMode,6'b000000};
SO_Enable <= 1;
end
else DataShifterO <= DataShifterO << 1;
end
`SDIMODE: begin
if ((ClockCounter > 3) & (ClockCounter[1:0] == 2'b00)) begin
DataShifterO <= {OpMode,6'b000000};
SO_Enable <= 1;
end
else DataShifterO <= DataShifterO << 2;
end
`SQIMODE: begin
if ((ClockCounter > 1) & (ClockCounter[0] == 1'b0)) begin
DataShifterO <= {OpMode,6'b000000};
SO_Enable <= 1;
end
else DataShifterO <= DataShifterO << 4;
end
default: $error("IOMode set to invalid value.");
endcase
end
end
end
// -------------------------------------------------------------------------------------------------------
// 1.10: Output Data Buffer
// -------------------------------------------------------------------------------------------------------
// Buffer for SPI mode
bufif1 (SO_SIO1, SO_DO[0], SO_OE & (IOMode == `SPIMODE));
// Buffers for SDI mode
bufif1 (SI_SIO0, SO_DO[0], SO_OE & (IOMode == `SDIMODE));
bufif1 (SO_SIO1, SO_DO[1], SO_OE & (IOMode == `SDIMODE));
// Buffers for SQI Mode
bufif1 (SI_SIO0, SO_DO[0], SO_OE & (IOMode == `SQIMODE));
bufif1 (SO_SIO1, SO_DO[1], SO_OE & (IOMode == `SQIMODE));
bufif1 (SIO2, SO_DO[2], SO_OE & (IOMode == `SQIMODE));
bufif1 (HOLD_N_SIO3, SO_DO[3], SO_OE & (IOMode == `SQIMODE));
always @(DataShifterO) begin
case (IOMode)
`SPIMODE: begin
SO_DO[0] <= #(tV) DataShifterO[07];
end
`SDIMODE: begin
SO_DO[1] <= #(tV) DataShifterO[07];
SO_DO[0] <= #(tV) DataShifterO[06];
end
`SQIMODE: begin
SO_DO[3] <= #(tV) DataShifterO[07];
SO_DO[2] <= #(tV) DataShifterO[06];
SO_DO[1] <= #(tV) DataShifterO[05];
SO_DO[0] <= #(tV) DataShifterO[04];
end
endcase
end
bufif1 #(tV,0) (OutputEnable1, SO_Enable, 1);
notif1 #(tDIS) (OutputEnable2, CS_N, 1);
bufif1 #(tHV,tHZ) (OutputEnable3, HOLD_N_SIO3 | !(IOMode == `SPIMODE), 1);
assign SO_OE = OutputEnable1 & OutputEnable2 & OutputEnable3;
// *******************************************************************************************************
// ** DEBUG LOGIC **
// *******************************************************************************************************
// -------------------------------------------------------------------------------------------------------
// 2.01: Memory Data Bytes
// -------------------------------------------------------------------------------------------------------
wire [07:00] MemoryByte00000 = MemoryBlock[000000];
wire [07:00] MemoryByte00001 = MemoryBlock[000001];
wire [07:00] MemoryByte00002 = MemoryBlock[000002];
wire [07:00] MemoryByte00003 = MemoryBlock[000003];
wire [07:00] MemoryByte00004 = MemoryBlock[000004];
wire [07:00] MemoryByte00005 = MemoryBlock[000005];
wire [07:00] MemoryByte00006 = MemoryBlock[000006];
wire [07:00] MemoryByte00007 = MemoryBlock[000007];
wire [07:00] MemoryByte00008 = MemoryBlock[000008];
wire [07:00] MemoryByte00009 = MemoryBlock[000009];
wire [07:00] MemoryByte0000A = MemoryBlock[000010];
wire [07:00] MemoryByte0000B = MemoryBlock[000011];
wire [07:00] MemoryByte0000C = MemoryBlock[000012];
wire [07:00] MemoryByte0000D = MemoryBlock[000013];
wire [07:00] MemoryByte0000E = MemoryBlock[000014];
wire [07:00] MemoryByte0000F = MemoryBlock[000015];
wire [07:00] MemoryByte1FFF0 = MemoryBlock[131056];
wire [07:00] MemoryByte1FFF1 = MemoryBlock[131057];
wire [07:00] MemoryByte1FFF2 = MemoryBlock[131058];
wire [07:00] MemoryByte1FFF3 = MemoryBlock[131059];
wire [07:00] MemoryByte1FFF4 = MemoryBlock[131060];
wire [07:00] MemoryByte1FFF5 = MemoryBlock[131061];
wire [07:00] MemoryByte1FFF6 = MemoryBlock[131062];
wire [07:00] MemoryByte1FFF7 = MemoryBlock[131063];
wire [07:00] MemoryByte1FFF8 = MemoryBlock[131064];
wire [07:00] MemoryByte1FFF9 = MemoryBlock[131065];
wire [07:00] MemoryByte1FFFA = MemoryBlock[131066];
wire [07:00] MemoryByte1FFFB = MemoryBlock[131067];
wire [07:00] MemoryByte1FFFC = MemoryBlock[131068];
wire [07:00] MemoryByte1FFFD = MemoryBlock[131069];
wire [07:00] MemoryByte1FFFE = MemoryBlock[131070];
wire [07:00] MemoryByte1FFFF = MemoryBlock[131071];
// *******************************************************************************************************
// ** TIMING CHECKS **
// *******************************************************************************************************
wire TimingCheckEnable = (RESET == 0) & (CS_N == 0);
wire SPITimingCheckEnable = TimingCheckEnable & (IOMode == `SPIMODE);
wire SDITimingCheckEnable = TimingCheckEnable & (IOMode == `SDIMODE) & (SO_Enable == 0);
wire SQITimingCheckEnable = TimingCheckEnable & (IOMode == `SQIMODE) & (SO_Enable == 0);
specify
`ifdef TEMP_INDUSTRIAL
specparam
tHI = 25, // Clock high time
tLO = 25, // Clock low time
tSU = 10, // Data setup time
tHD = 10, // Data hold time
tHS = 10, // HOLD_N setup time
tHH = 10, // HOLD_N hold time
tCSD = 25, // CS_N disable time
tCSS = 25, // CS_N setup time
tCSH = 50, // CS_N hold time
tCLD = 25; // Clock delay time
`else
`ifdef TEMP_EXTENDED
specparam
tHI = 32, // Clock high time
tLO = 32, // Clock low time
tSU = 10, // Data setup time
tHD = 10, // Data hold time
tHS = 10, // HOLD_N setup time
tHH = 10, // HOLD_N hold time
tCSD = 32, // CS_N disable time
tCSS = 32, // CS_N setup time
tCSH = 50, // CS_N hold time
tCLD = 32; // Clock delay time
`else
specparam
tHI = 25, // Clock high time
tLO = 25, // Clock low time
tSU = 10, // Data setup time
tHD = 10, // Data hold time
tHS = 10, // HOLD_N setup time
tHH = 10, // HOLD_N hold time
tCSD = 25, // CS_N disable time
tCSS = 25, // CS_N setup time
tCSH = 50, // CS_N hold time
tCLD = 25; // Clock delay time
`endif
`endif
$width (posedge SCK, tHI);
$width (negedge SCK, tLO);
$width (posedge CS_N, tCSD);
$setup (negedge CS_N, posedge SCK &&& TimingCheckEnable, tCSS);
$setup (posedge CS_N, posedge SCK &&& TimingCheckEnable, tCLD);
$hold (posedge SCK &&& TimingCheckEnable, posedge CS_N, tCSH);
// SPI-specific timing checks
$setup (SI_SIO0, posedge SCK &&& SPITimingCheckEnable, tSU);
$setup (negedge SCK, negedge HOLD_N_SIO3 &&& SPITimingCheckEnable, tHS);
$hold (posedge SCK &&& SPITimingCheckEnable, SI_SIO0, tHD);
$hold (posedge HOLD_N_SIO3 &&& SPITimingCheckEnable, posedge SCK, tHH);
// SDI-specific timing checks
$setup (SI_SIO0, posedge SCK &&& SDITimingCheckEnable, tSU);
$setup (SO_SIO1, posedge SCK &&& SDITimingCheckEnable, tSU);
$hold (posedge SCK &&& SDITimingCheckEnable, SI_SIO0, tHD);
$hold (posedge SCK &&& SDITimingCheckEnable, SO_SIO1, tHD);
// SQI-specific timing checks
$setup (SI_SIO0, posedge SCK &&& SQITimingCheckEnable, tSU);
$setup (SO_SIO1, posedge SCK &&& SQITimingCheckEnable, tSU);
$setup (SIO2, posedge SCK &&& SQITimingCheckEnable, tSU);
$setup (HOLD_N_SIO3, posedge SCK &&& SQITimingCheckEnable, tSU);
$hold (posedge SCK &&& SQITimingCheckEnable, SI_SIO0, tHD);
$hold (posedge SCK &&& SQITimingCheckEnable, SO_SIO1, tHD);
$hold (posedge SCK &&& SQITimingCheckEnable, SIO2, tHD);
$hold (posedge SCK &&& SQITimingCheckEnable, HOLD_N_SIO3, tHD);
endspecify
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXBN_1_V
`define SKY130_FD_SC_HS__DLXBN_1_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXBN_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2I_M_V
`define SKY130_FD_SC_LP__MUX2I_M_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog wrapper for mux2i with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2i.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_m (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2i_m (
Y ,
A0,
A1,
S
);
output Y ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2i base (
.Y(Y),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2I_M_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLRBN_FUNCTIONAL_V
`define SKY130_FD_SC_HS__DLRBN_FUNCTIONAL_V
/**
* dlrbn: Delay latch, inverted reset, inverted enable,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dl_p_r_pg/sky130_fd_sc_hs__u_dl_p_r_pg.v"
`celldefine
module sky130_fd_sc_hs__dlrbn (
VPWR ,
VGND ,
Q ,
Q_N ,
RESET_B,
D ,
GATE_N
);
// Module ports
input VPWR ;
input VGND ;
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE_N ;
// Local signals
wire RESET ;
wire intgate;
wire buf_Q ;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (intgate, GATE_N );
sky130_fd_sc_hs__u_dl_p_r_pg `UNIT_DELAY u_dl_p_r_pg0 (buf_Q , D, intgate, RESET, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLRBN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
`define SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand4bb (
//# {{data|Data Signals}}
input A_N,
input B_N,
input C ,
input D ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_SYMBOL_V
|
`timescale 1 ps / 1 ps
module ram_r(
input clk,
input rst,
output wire[ADD_WIDTH-1:0] ram_r_address,
input ram_r_waitrequest,
input ram_r_readdatavalid,
output wire[BYTE_ENABLE_WIDTH-1:0] ram_r_byteenable,
output wire ram_r_read,
input wire[DATA_WIDTH-1:0] ram_r_readdata,
output wire[BURST_WIDTH_R-1:0] ram_r_burstcount,
output wire [DATA_WIDTH-1:0] data_fifo_in,
input read_fifo_in,
input start_fifo_in,
input [ADD_WIDTH-1:0] address_fifo_in,
input [DATA_WIDTH-1:0] n_burst_fifo_in,
output wire bussy_fifo_in,
output wire empty_fifo_in,
output wire [FIFO_DEPTH_LOG2:0] usedw_fifo_in
);
parameter DATA_WIDTH = 32;
parameter ADD_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4;
parameter MAX_BURST_COUNT_R = 32;
parameter BURST_WIDTH_R = 6;
parameter FIFO_DEPTH_LOG2 = 8;
parameter FIFO_DEPTH = 256;
wire read_complete;
reg [DATA_WIDTH-1:0] reads_pending;
wire read_burst_end;
reg next_r;
wire too_many_reads_pending;
reg [ADD_WIDTH-1:0] read_address;
reg [DATA_WIDTH-1:0] in_n;
reg [DATA_WIDTH-1:0] in_n_2;
wire fifo_full;
wire fifo_empty;
wire [FIFO_DEPTH_LOG2:0] fifo_used;
scfifo master_to_st_fifo(
.aclr(start_fifo_in),
.clock(clk),
.data(ram_r_readdata),
.wrreq(read_complete),
.q(data_fifo_in),
.rdreq(read_fifo_in),
.full(fifo_full),
.empty(fifo_empty),
.usedw(fifo_used[FIFO_DEPTH_LOG2-1:0])
);
defparam master_to_st_fifo.lpm_width = DATA_WIDTH;
defparam master_to_st_fifo.lpm_numwords = FIFO_DEPTH;
defparam master_to_st_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam master_to_st_fifo.lpm_showahead = "ON";
defparam master_to_st_fifo.use_eab = "ON";
defparam master_to_st_fifo.add_ram_output_register = "OFF"; // FIFO latency of 2
defparam master_to_st_fifo.underflow_checking = "OFF";
defparam master_to_st_fifo.overflow_checking = "OFF";
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_complete == 1) begin
in_n <= in_n - 1;
end
end
end
end
always @(posedge clk or posedge rst) begin
if (rst == 1) begin
in_n_2 <= 0;
end else begin
if (start_fifo_in == 1) begin
in_n_2 <= n_burst_fifo_in * MAX_BURST_COUNT_R;
end else begin
if (read_burst_end == 1) begin
in_n_2 <= in_n_2 - MAX_BURST_COUNT_R;
end
end
end
end
always @(posedge clk) begin
if (start_fifo_in == 1) begin
read_address <= address_fifo_in;
end else begin
if (read_burst_end == 1) begin
read_address <= read_address + MAX_BURST_COUNT_R * BYTE_ENABLE_WIDTH;
end
end
end
// tracking FIFO
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
reads_pending <= 0;
end else begin
if(read_burst_end == 1) begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R;
end else begin
reads_pending <= reads_pending + MAX_BURST_COUNT_R - 1; // a burst read was posted, but a word returned
end
end else begin
if(ram_r_readdatavalid == 0) begin
reads_pending <= reads_pending; // burst read was not posted and no read returned
end else begin
reads_pending <= reads_pending - 1; // burst read was not posted but a word returned
end
end
end
end
always @ (posedge clk) begin
if (start_fifo_in == 1) begin
next_r <= 0;
end else begin
if(read_burst_end == 1) begin
next_r <= 0;
end else begin
if (ram_r_read == 1) begin
next_r <= 1;
end
end
end
end
assign read_complete = (ram_r_readdatavalid == 1);
assign read_burst_end = (ram_r_waitrequest == 0) & (next_r == 1);// & (header_c > 4);
assign too_many_reads_pending = (reads_pending + fifo_used) >= (FIFO_DEPTH - MAX_BURST_COUNT_R - 4); // make sure there are fewer reads posted than room in the FIFO
assign ram_r_address = read_address;
assign ram_r_read = (too_many_reads_pending == 0) & (in_n_2 != 0);// & (header_c > 4);
assign ram_r_byteenable = {BYTE_ENABLE_WIDTH{1'b1}};
assign ram_r_burstcount = MAX_BURST_COUNT_R;
assign bussy_fifo_in = in_n != 0;
assign empty_fifo_in = fifo_empty;
assign usedw_fifo_in = fifo_used;
endmodule
|
module tv80 (
x884,
x825,
x717,
x1023,
x916,
x964,
x1012,
x672,
x800,
x856,
x947,
x956,
x762,
x974,
x332,
x179,
x423,
x606,
x557,
x79,
x285,
x633,
x0,
x160,
x142,
x475,
x40,
x307,
x256,
x450,
x593,
x409,
x90,
x204,
x639,
x350,
x626,
x128,
x388,
x23,
x437,
x368,
x232,
x615,
x105,
x60);
// Start PIs
input x884;
input x825;
input x717;
input x1023;
input x916;
input x964;
input x1012;
input x672;
input x800;
input x856;
input x947;
input x956;
input x762;
input x974;
// Start POs
output x332;
output x179;
output x423;
output x606;
output x557;
output x79;
output x285;
output x633;
output x0;
output x160;
output x142;
output x475;
output x40;
output x307;
output x256;
output x450;
output x593;
output x409;
output x90;
output x204;
output x639;
output x350;
output x626;
output x128;
output x388;
output x23;
output x437;
output x368;
output x232;
output x615;
output x105;
output x60;
// Start wires
wire net_5030;
wire net_2449;
wire net_4065;
wire net_1317;
wire net_416;
wire net_215;
wire net_2394;
wire net_4854;
wire net_2418;
wire net_1382;
wire net_943;
wire net_4598;
wire net_4508;
wire net_4392;
wire net_1897;
wire net_980;
wire net_53;
wire net_3498;
wire net_2542;
wire net_1786;
wire net_1377;
wire net_4513;
wire net_3996;
wire net_4382;
wire net_1393;
wire net_2169;
wire net_1324;
wire net_4934;
wire net_2256;
wire net_4306;
wire net_264;
wire net_3904;
wire net_4122;
wire net_4315;
wire net_2207;
wire net_263;
wire net_4323;
wire net_3527;
wire net_1138;
wire net_2769;
wire net_4996;
wire net_3483;
wire net_3707;
wire net_1064;
wire net_2082;
wire net_5035;
wire net_3292;
wire net_1439;
wire x717;
wire net_4832;
wire net_4464;
wire net_4189;
wire net_1778;
wire net_508;
wire net_5098;
wire net_1090;
wire net_3685;
wire net_4285;
wire net_703;
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wire net_4744;
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wire net_201;
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wire net_3817;
wire net_3280;
wire net_4043;
wire net_3085;
wire net_2896;
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wire net_3434;
wire net_2060;
wire net_2051;
wire net_2780;
wire net_4535;
wire net_4480;
wire net_789;
wire net_3756;
wire net_3244;
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wire net_2171;
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wire net_2765;
wire net_3833;
wire net_742;
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wire net_4509;
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wire net_3063;
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wire net_5217;
wire net_4973;
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wire net_2745;
wire net_2546;
wire net_5084;
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wire net_1876;
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wire x79;
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wire net_2998;
wire net_721;
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wire net_2757;
wire net_1018;
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wire net_818;
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wire net_5024;
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wire net_1488;
wire net_4966;
wire net_2812;
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wire net_1684;
wire net_811;
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wire x884;
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wire x639;
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wire net_210;
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wire x825;
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wire net_2881;
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wire x0;
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wire x615;
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wire net_353;
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wire net_5251;
wire net_4994;
wire net_3588;
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wire net_2642;
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wire net_4471;
wire net_1102;
wire net_4802;
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wire net_5245;
wire net_3371;
wire net_618;
wire net_2244;
wire net_2692;
wire net_3688;
wire x368;
wire net_3777;
wire net_1875;
wire net_3420;
wire net_783;
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wire net_1487;
wire net_4572;
wire net_754;
wire net_2759;
wire net_2605;
wire net_921;
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wire net_550;
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wire net_5238;
wire net_3308;
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wire net_4543;
wire net_2835;
wire net_5086;
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wire net_1240;
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wire net_3000;
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wire net_2564;
wire net_2821;
wire net_1512;
wire net_1658;
wire net_4827;
wire net_654;
wire net_330;
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wire net_5025;
wire net_1330;
wire net_3506;
wire net_3007;
wire net_4275;
wire net_3015;
wire net_4487;
wire net_1785;
wire net_4766;
wire net_4771;
wire net_3174;
wire net_2876;
wire net_570;
wire net_444;
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wire net_2577;
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wire net_1503;
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wire net_2102;
wire net_4451;
wire net_4639;
wire net_1442;
wire net_449;
wire net_5234;
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wire net_4054;
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wire x60;
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wire x800;
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wire net_4621;
wire net_4340;
wire net_4071;
wire net_4954;
wire net_1634;
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wire net_5102;
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wire net_4533;
wire net_1816;
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wire net_2220;
wire net_4762;
wire net_2823;
wire net_1217;
wire net_1508;
wire net_3379;
wire net_4761;
wire net_2933;
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wire net_5173;
wire net_1273;
wire net_3283;
wire net_1137;
wire net_4433;
wire net_3948;
wire net_2114;
wire net_2506;
wire net_4830;
wire net_5012;
wire net_5036;
wire net_3230;
wire net_4865;
wire net_285;
wire net_5296;
wire net_1310;
wire net_3819;
wire net_254;
wire net_2499;
wire net_1501;
wire net_1297;
wire net_3003;
wire net_1304;
wire net_4381;
wire net_574;
wire net_2177;
wire net_3357;
// Start cells
NAND2_X2 inst_1783 ( .A1(net_1202), .A2(net_1117), .ZN(net_1062) );
CLKBUF_X2 inst_5101 ( .A(net_4473), .Z(net_5087) );
CLKBUF_X2 inst_4728 ( .A(net_4713), .Z(net_4714) );
CLKBUF_X2 inst_4385 ( .A(net_4370), .Z(net_4371) );
INV_X2 inst_2685 ( .ZN(net_1804), .A(net_1753) );
OAI21_X2 inst_481 ( .B1(net_2970), .ZN(net_2964), .B2(net_2963), .A(net_2458) );
AND2_X4 inst_4123 ( .ZN(net_4047), .A1(net_2551), .A2(net_2003) );
NAND2_X2 inst_1751 ( .ZN(net_1382), .A1(net_1228), .A2(net_321) );
CLKBUF_X2 inst_4606 ( .A(net_4591), .Z(net_4592) );
INV_X4 inst_2235 ( .ZN(net_1863), .A(net_1814) );
OAI211_X2 inst_779 ( .C1(net_3424), .A(net_3422), .ZN(net_2862), .B(net_2736), .C2(net_1351) );
CLKBUF_X2 inst_5306 ( .A(net_4455), .Z(net_5292) );
INV_X4 inst_2205 ( .ZN(net_2254), .A(net_2233) );
INV_X2 inst_2858 ( .ZN(net_330), .A(net_64) );
AND2_X4 inst_4131 ( .ZN(net_4060), .A2(net_1192), .A1(net_1188) );
OAI21_X4 inst_452 ( .B1(net_3808), .ZN(net_2790), .B2(net_2529), .A(net_2366) );
OR2_X4 inst_214 ( .ZN(net_2597), .A1(net_2212), .A2(net_742) );
INV_X2 inst_3061 ( .ZN(net_4175), .A(net_2703) );
CLKBUF_X2 inst_4228 ( .A(net_4204), .Z(net_4214) );
OAI21_X2 inst_548 ( .B2(net_2909), .B1(net_2887), .ZN(net_2883), .A(net_2466) );
AND2_X4 inst_4144 ( .ZN(net_4080), .A1(net_3627), .A2(net_246) );
CLKBUF_X2 inst_4647 ( .A(net_4632), .Z(net_4633) );
CLKBUF_X2 inst_4372 ( .A(net_4274), .Z(net_4358) );
OAI21_X2 inst_728 ( .ZN(net_713), .B2(net_587), .B1(net_584), .A(net_421) );
DFF_X2 inst_3121 ( .Q(net_3147), .D(net_2728), .CK(net_4589) );
INV_X2 inst_2780 ( .ZN(net_806), .A(net_760) );
INV_X4 inst_2485 ( .A(net_3072), .ZN(net_470) );
CLKBUF_X2 inst_4709 ( .A(net_4694), .Z(net_4695) );
AND2_X4 inst_4152 ( .A2(net_4117), .ZN(net_4100), .A1(net_1699) );
INV_X4 inst_2217 ( .ZN(net_2096), .A(net_1973) );
OAI211_X2 inst_850 ( .ZN(net_633), .B(net_632), .C1(net_449), .A(net_387), .C2(net_254) );
DFF_X1 inst_3347 ( .D(net_2756), .CK(net_4344), .Q(x79) );
DFF_X2 inst_3130 ( .D(net_3535), .QN(net_3468), .CK(net_4815) );
INV_X2 inst_2844 ( .ZN(net_388), .A(net_376) );
INV_X4 inst_2492 ( .A(net_3061), .ZN(net_735) );
AND2_X4 inst_4136 ( .ZN(net_4065), .A2(net_1586), .A1(net_1063) );
AOI22_X2 inst_3582 ( .A1(net_4063), .B1(net_4058), .B2(net_4015), .A2(net_4013), .ZN(net_1435) );
NAND4_X2 inst_1228 ( .A1(net_4111), .ZN(net_791), .A3(net_775), .A4(net_527), .A2(net_403) );
AOI22_X2 inst_3480 ( .A1(net_2675), .ZN(net_2658), .B1(net_2657), .A2(net_991), .B2(net_225) );
CLKBUF_X2 inst_4985 ( .A(net_4970), .Z(net_4971) );
CLKBUF_X2 inst_4221 ( .A(net_4206), .Z(net_4207) );
OAI21_X2 inst_521 ( .B1(net_3302), .ZN(net_2918), .B2(net_2917), .A(net_2394) );
CLKBUF_X2 inst_5164 ( .A(net_5149), .Z(net_5150) );
CLKBUF_X2 inst_4473 ( .A(net_4458), .Z(net_4459) );
NAND2_X2 inst_1685 ( .A1(net_3219), .ZN(net_1987), .A2(net_558) );
INV_X4 inst_2511 ( .A(net_3062), .ZN(net_478) );
INV_X4 inst_2438 ( .A(net_3145), .ZN(net_137) );
NAND2_X2 inst_1655 ( .A1(net_2590), .ZN(net_2185), .A2(net_2003) );
AOI22_X2 inst_3578 ( .A1(net_4060), .B1(net_4055), .ZN(net_1472), .A2(net_234), .B2(net_169) );
INV_X2 inst_2772 ( .ZN(net_861), .A(net_860) );
INV_X4 inst_2543 ( .ZN(net_3753), .A(net_3675) );
OR2_X4 inst_237 ( .ZN(net_3413), .A2(net_1126), .A1(net_1124) );
CLKBUF_X2 inst_4847 ( .A(net_4832), .Z(net_4833) );
CLKBUF_X2 inst_4818 ( .A(net_4803), .Z(net_4804) );
OAI211_X2 inst_813 ( .B(net_1628), .C1(net_1627), .ZN(net_1625), .A(net_1553), .C2(net_334) );
XNOR2_X2 inst_51 ( .A(net_3552), .ZN(net_2618), .B(net_1693) );
NAND2_X2 inst_1837 ( .ZN(net_1200), .A1(net_722), .A2(net_721) );
NOR2_X2 inst_1066 ( .A2(net_3732), .ZN(net_896), .A1(net_853) );
NOR2_X4 inst_974 ( .ZN(net_3933), .A2(net_3932), .A1(net_3722) );
DFF_X1 inst_3392 ( .D(net_1633), .CK(net_5255), .Q(x615) );
CLKBUF_X2 inst_5063 ( .A(net_4726), .Z(net_5049) );
INV_X4 inst_2342 ( .ZN(net_1717), .A(net_1381) );
CLKBUF_X2 inst_4608 ( .A(net_4564), .Z(net_4594) );
DFF_X1 inst_3291 ( .QN(net_3013), .D(net_2889), .CK(net_5224) );
INV_X4 inst_2294 ( .A(net_3723), .ZN(net_1015) );
NAND2_X2 inst_1617 ( .A1(net_2919), .ZN(net_2399), .A2(net_140) );
SDFF_X2 inst_151 ( .D(net_3611), .SE(net_2625), .SI(net_101), .Q(net_101), .CK(net_4938) );
XNOR2_X2 inst_64 ( .ZN(net_1787), .B(net_1765), .A(net_1618) );
INV_X4 inst_2256 ( .ZN(net_1211), .A(net_1156) );
NOR2_X2 inst_1001 ( .A2(net_4050), .A1(net_3504), .ZN(net_2126) );
CLKBUF_X2 inst_4821 ( .A(net_4806), .Z(net_4807) );
AND4_X4 inst_4051 ( .ZN(net_4104), .A1(net_3766), .A2(net_618), .A3(net_607), .A4(net_385) );
MUX2_X2 inst_2106 ( .S(net_2915), .A(net_2573), .Z(net_2571), .B(net_201) );
OAI21_X2 inst_743 ( .B2(net_4052), .B1(net_3694), .ZN(net_3310), .A(net_1560) );
INV_X2 inst_2723 ( .ZN(net_1504), .A(net_1503) );
AOI21_X4 inst_3931 ( .B2(net_3757), .ZN(net_3726), .A(net_3725), .B1(net_3403) );
INV_X2 inst_3033 ( .A(net_3764), .ZN(net_3565) );
CLKBUF_X2 inst_4880 ( .A(net_4865), .Z(net_4866) );
INV_X2 inst_2925 ( .A(net_3094), .ZN(net_196) );
CLKBUF_X2 inst_4265 ( .A(net_4207), .Z(net_4251) );
AOI221_X2 inst_3867 ( .B2(net_3119), .B1(net_2020), .C1(net_2019), .ZN(net_1940), .A(net_1939), .C2(x256) );
NAND2_X2 inst_1828 ( .A1(net_912), .ZN(net_828), .A2(net_526) );
NAND2_X2 inst_2072 ( .ZN(net_3990), .A2(net_3988), .A1(net_963) );
NAND2_X2 inst_1603 ( .A1(net_2969), .ZN(net_2414), .A2(net_468) );
NAND2_X2 inst_1809 ( .A2(net_1213), .ZN(net_950), .A1(net_901) );
OAI22_X2 inst_340 ( .ZN(net_3256), .A2(net_3255), .A1(net_1712), .B1(net_1711), .B2(net_1710) );
DFF_X1 inst_3388 ( .D(net_1756), .QN(net_79), .CK(net_4250) );
AOI222_X2 inst_3735 ( .B1(net_3386), .C2(net_3385), .A1(net_3384), .A2(net_1826), .ZN(net_1764), .C1(net_574), .B2(net_361) );
CLKBUF_X2 inst_5311 ( .A(net_4805), .Z(net_5297) );
INV_X2 inst_2675 ( .ZN(net_1897), .A(net_1860) );
CLKBUF_X2 inst_4280 ( .A(net_4265), .Z(net_4266) );
OR4_X2 inst_158 ( .ZN(net_2712), .A1(net_2711), .A2(net_2710), .A3(net_2709), .A4(net_50) );
SDFF_X2 inst_141 ( .SE(net_2625), .D(net_2315), .SI(net_99), .Q(net_99), .CK(net_4750) );
CLKBUF_X2 inst_4344 ( .A(net_4329), .Z(net_4330) );
INV_X4 inst_2520 ( .ZN(net_3225), .A(net_2874) );
CLKBUF_X2 inst_4244 ( .A(net_4229), .Z(net_4230) );
NAND2_X2 inst_1490 ( .A1(net_4150), .A2(net_3600), .ZN(net_2860) );
OAI21_X2 inst_507 ( .B1(net_3274), .B2(net_2969), .ZN(net_2935), .A(net_2415) );
OAI21_X2 inst_571 ( .B2(net_3428), .ZN(net_2834), .B1(net_2762), .A(net_2116) );
AOI21_X1 inst_4011 ( .ZN(net_3304), .A(net_1601), .B2(net_1600), .B1(net_64) );
CLKBUF_X2 inst_4559 ( .A(net_4544), .Z(net_4545) );
CLKBUF_X2 inst_4289 ( .A(net_4274), .Z(net_4275) );
AOI22_X2 inst_3709 ( .B2(net_4124), .A2(net_555), .ZN(net_455), .A1(net_454), .B1(net_453) );
NAND2_X2 inst_1974 ( .A1(net_3666), .ZN(net_3346), .A2(net_767) );
NAND2_X2 inst_2017 ( .A2(net_4023), .ZN(net_3649), .A1(net_3647) );
NOR3_X2 inst_884 ( .A1(net_4154), .A3(net_3175), .ZN(net_2757), .A2(net_2688) );
NOR2_X2 inst_1154 ( .ZN(net_4001), .A2(net_4000), .A1(net_3728) );
OAI21_X2 inst_711 ( .ZN(net_958), .B1(net_843), .A(net_842), .B2(net_408) );
OAI211_X2 inst_827 ( .ZN(net_1453), .A(net_1313), .B(net_1193), .C1(net_1076), .C2(net_399) );
OAI21_X2 inst_469 ( .B1(net_3509), .ZN(net_2981), .B2(net_2969), .A(net_2417) );
INV_X2 inst_3040 ( .ZN(net_3657), .A(net_3655) );
INV_X2 inst_2980 ( .A(net_3006), .ZN(net_222) );
CLKBUF_X2 inst_5197 ( .A(net_5140), .Z(net_5183) );
AND2_X4 inst_4191 ( .ZN(net_4195), .A1(net_4137), .A2(net_42) );
AOI221_X2 inst_3870 ( .B2(net_3114), .B1(net_2020), .C1(net_2019), .ZN(net_1935), .A(net_1934), .C2(x160) );
CLKBUF_X2 inst_4269 ( .A(net_4254), .Z(net_4255) );
CLKBUF_X2 inst_4640 ( .A(net_4549), .Z(net_4626) );
XOR2_X2 inst_18 ( .Z(net_3553), .B(net_3551), .A(net_1692) );
NOR3_X2 inst_915 ( .A2(net_3821), .A1(net_3674), .ZN(net_3604), .A3(net_3171) );
AND2_X4 inst_4128 ( .ZN(net_4055), .A2(net_1247), .A1(net_1192) );
CLKBUF_X2 inst_4416 ( .A(net_4401), .Z(net_4402) );
INV_X4 inst_2263 ( .ZN(net_1283), .A(net_1165) );
INV_X4 inst_2339 ( .ZN(net_963), .A(net_716) );
CLKBUF_X2 inst_4861 ( .A(net_4846), .Z(net_4847) );
CLKBUF_X2 inst_4796 ( .A(net_4781), .Z(net_4782) );
CLKBUF_X2 inst_5183 ( .A(net_4225), .Z(net_5169) );
AOI22_X2 inst_3549 ( .B1(net_4054), .A2(net_2037), .A1(net_1578), .ZN(net_1572), .B2(net_182) );
AOI22_X2 inst_3501 ( .ZN(net_2065), .A1(net_2063), .B1(net_1904), .B2(net_1401), .A2(net_1400) );
NAND4_X2 inst_1216 ( .ZN(net_1099), .A4(net_879), .A3(net_547), .A2(net_501), .A1(net_460) );
AOI21_X2 inst_3936 ( .B1(net_3882), .B2(net_3858), .A(net_2529), .ZN(net_2344) );
CLKBUF_X2 inst_4807 ( .A(net_4792), .Z(net_4793) );
NOR2_X4 inst_952 ( .ZN(net_3662), .A1(net_3106), .A2(net_283) );
AND2_X4 inst_4175 ( .ZN(net_4129), .A2(net_251), .A1(net_77) );
NAND2_X2 inst_1668 ( .A1(net_3185), .ZN(net_2090), .A2(net_212) );
CLKBUF_X2 inst_4811 ( .A(net_4796), .Z(net_4797) );
OAI21_X2 inst_721 ( .A(net_825), .ZN(net_678), .B1(net_603), .B2(net_359) );
CLKBUF_X2 inst_4741 ( .A(net_4726), .Z(net_4727) );
OAI22_X2 inst_293 ( .B2(net_3620), .A1(net_3439), .ZN(net_1809), .A2(net_1808), .B1(net_896) );
AOI222_X1 inst_3744 ( .A1(net_4189), .C1(net_3504), .B1(net_3472), .ZN(net_2317), .A2(net_396), .C2(net_387), .B2(net_282) );
INV_X2 inst_3009 ( .ZN(net_3354), .A(net_3353) );
NAND3_X2 inst_1366 ( .ZN(net_3971), .A3(net_3967), .A1(net_1058), .A2(net_877) );
CLKBUF_X2 inst_4397 ( .A(net_4382), .Z(net_4383) );
HA_X1 inst_3102 ( .S(net_274), .CO(net_273), .B(net_75), .A(net_74) );
INV_X2 inst_2695 ( .A(net_2378), .ZN(net_1689) );
AOI221_X2 inst_3860 ( .B2(net_3121), .ZN(net_2022), .B1(net_2020), .C1(net_2019), .A(net_1901), .C2(x307) );
NAND2_X2 inst_1915 ( .A2(net_3108), .ZN(net_285), .A1(net_259) );
INV_X2 inst_2794 ( .A(net_1340), .ZN(net_1324) );
NAND2_X2 inst_2063 ( .ZN(net_3925), .A2(net_3923), .A1(net_840) );
NAND4_X2 inst_1254 ( .ZN(net_3856), .A4(net_3191), .A2(net_2088), .A1(net_2087), .A3(net_1987) );
INV_X2 inst_2953 ( .A(net_3016), .ZN(net_200) );
AOI22_X2 inst_3553 ( .A1(net_4060), .B1(net_4055), .ZN(net_1497), .A2(net_197), .B2(net_175) );
CLKBUF_X2 inst_4801 ( .A(net_4786), .Z(net_4787) );
AOI22_X2 inst_3723 ( .B2(net_3972), .A1(net_3724), .ZN(net_3625), .A2(net_3621), .B1(net_1183) );
AOI22_X2 inst_3521 ( .A2(net_2203), .B1(net_2202), .B2(net_2033), .ZN(net_1925), .A1(net_1847) );
NAND2_X2 inst_1811 ( .A2(net_1105), .ZN(net_895), .A1(net_748) );
XNOR2_X2 inst_98 ( .ZN(net_664), .A(net_663), .B(net_428) );
CLKBUF_X2 inst_4544 ( .A(net_4529), .Z(net_4530) );
AOI21_X2 inst_3985 ( .A(net_3819), .B2(net_3606), .ZN(net_845), .B1(net_844) );
HA_X1 inst_3087 ( .CO(net_1875), .S(net_1743), .A(net_1570), .B(net_243) );
NAND2_X2 inst_2036 ( .A1(net_3894), .A2(net_3867), .ZN(net_3778) );
NOR2_X4 inst_959 ( .A2(net_3942), .ZN(net_3766), .A1(net_3669) );
AOI21_X2 inst_4001 ( .ZN(net_3709), .A(net_3708), .B1(net_3704), .B2(net_284) );
NAND2_X2 inst_2049 ( .ZN(net_3862), .A1(net_2084), .A2(net_1985) );
NOR4_X2 inst_868 ( .A4(net_4096), .A2(net_4001), .A1(net_1103), .ZN(net_1048), .A3(net_583) );
OR3_X4 inst_163 ( .A3(net_3443), .A2(net_2597), .ZN(net_2521), .A1(net_2303) );
OAI221_X2 inst_394 ( .C2(net_3407), .ZN(net_2358), .B1(net_2357), .C1(net_2223), .A(net_1871), .B2(net_112) );
OR2_X4 inst_201 ( .A1(net_3204), .ZN(net_2917), .A2(net_2354) );
OAI21_X2 inst_605 ( .B2(net_2815), .ZN(net_2333), .B1(net_2332), .A(net_1798) );
AOI22_X2 inst_3627 ( .A1(net_3385), .ZN(net_1101), .A2(net_721), .B2(net_641), .B1(net_261) );
NOR2_X2 inst_1084 ( .ZN(net_697), .A1(net_542), .A2(net_261) );
OAI22_X2 inst_304 ( .A2(net_3150), .A1(net_1543), .B1(net_1542), .ZN(net_1538), .B2(net_1537) );
NAND2_X2 inst_1814 ( .ZN(net_1029), .A1(net_867), .A2(net_866) );
INV_X2 inst_2799 ( .ZN(net_1026), .A(net_751) );
AND2_X4 inst_4157 ( .ZN(net_4108), .A1(net_533), .A2(net_529) );
NOR2_X2 inst_1027 ( .A2(net_4052), .ZN(net_1598), .A1(net_1438) );
CLKBUF_X2 inst_4470 ( .A(net_4455), .Z(net_4456) );
NOR2_X2 inst_1143 ( .ZN(net_3876), .A2(net_3251), .A1(net_2245) );
NAND3_X2 inst_1345 ( .ZN(net_3419), .A3(net_3418), .A2(net_3417), .A1(net_3416) );
INV_X2 inst_2947 ( .A(net_3041), .ZN(net_194) );
NAND2_X2 inst_2048 ( .ZN(net_3861), .A2(net_2104), .A1(net_2085) );
CLKBUF_X2 inst_5122 ( .A(net_5107), .Z(net_5108) );
INV_X2 inst_2948 ( .A(net_3052), .ZN(net_150) );
OAI221_X2 inst_361 ( .B1(net_4036), .C1(net_3352), .B2(net_3348), .ZN(net_2789), .A(net_2554), .C2(net_2165) );
AOI22_X2 inst_3608 ( .A1(net_4062), .B1(net_4057), .ZN(net_1409), .A2(net_462), .B2(net_461) );
DFF_X1 inst_3400 ( .Q(net_3117), .D(net_1539), .CK(net_4471) );
NOR2_X2 inst_1016 ( .A2(net_3802), .A1(net_3321), .ZN(net_1828) );
AND2_X4 inst_4147 ( .ZN(net_4084), .A1(net_963), .A2(net_414) );
NAND2_X2 inst_1538 ( .A1(net_2907), .ZN(net_2484), .A2(net_165) );
OAI211_X2 inst_848 ( .ZN(net_2717), .B(net_1998), .A(net_406), .C2(net_344), .C1(net_309) );
NAND2_X2 inst_1931 ( .ZN(net_3199), .A1(net_3198), .A2(net_205) );
CLKBUF_X2 inst_4735 ( .A(net_4720), .Z(net_4721) );
INV_X2 inst_3002 ( .ZN(net_3179), .A(net_3178) );
INV_X4 inst_2479 ( .ZN(net_290), .A(net_29) );
CLKBUF_X2 inst_4389 ( .A(net_4374), .Z(net_4375) );
INV_X4 inst_2179 ( .ZN(net_2740), .A(net_2739) );
INV_X4 inst_2578 ( .ZN(net_3600), .A(net_3599) );
OAI211_X2 inst_786 ( .C2(net_2778), .ZN(net_2761), .B(net_2674), .A(net_2651), .C1(net_2638) );
INV_X2 inst_2940 ( .A(net_3099), .ZN(net_232) );
NAND2_X2 inst_1996 ( .ZN(net_3486), .A2(net_3485), .A1(net_3484) );
NAND2_X2 inst_1554 ( .A1(net_2909), .ZN(net_2468), .A2(net_177) );
NAND2_X2 inst_1542 ( .A1(net_3207), .ZN(net_2480), .A2(net_157) );
CLKBUF_X2 inst_4511 ( .A(net_4440), .Z(net_4497) );
XOR2_X2 inst_2 ( .B(net_4180), .Z(net_1928), .A(net_1878) );
DFF_X1 inst_3340 ( .D(net_2761), .CK(net_4357), .Q(x40) );
OAI21_X2 inst_644 ( .ZN(net_2590), .B2(net_1975), .B1(net_1878), .A(net_1658) );
CLKBUF_X2 inst_4683 ( .A(net_4668), .Z(net_4669) );
CLKBUF_X2 inst_5015 ( .A(net_5000), .Z(net_5001) );
AOI22_X2 inst_3474 ( .B1(net_4039), .ZN(net_2677), .A1(net_2675), .A2(net_225), .B2(x128) );
NAND3_X1 inst_1380 ( .ZN(net_3359), .A2(net_3358), .A1(net_2550), .A3(net_1737) );
INV_X2 inst_2806 ( .A(net_1105), .ZN(net_986) );
OAI21_X2 inst_578 ( .B2(net_2912), .B1(net_2803), .ZN(net_2800), .A(net_2462) );
NOR3_X2 inst_888 ( .A2(net_4066), .ZN(net_2562), .A1(net_2524), .A3(net_2523) );
NAND2_X2 inst_1769 ( .A2(net_3789), .ZN(net_1174), .A1(net_997) );
AOI221_X2 inst_3891 ( .ZN(net_1390), .A(net_1229), .C1(net_1176), .C2(net_1124), .B1(net_656), .B2(net_432) );
AOI22_X2 inst_3625 ( .A1(net_3564), .ZN(net_964), .A2(net_963), .B1(net_957), .B2(net_408) );
AOI21_X2 inst_4008 ( .ZN(net_4159), .B1(net_2241), .A(net_2191), .B2(net_1189) );
CLKBUF_X2 inst_4834 ( .A(net_4313), .Z(net_4820) );
AOI22_X2 inst_3472 ( .B2(net_3119), .A1(net_2724), .B1(net_2722), .ZN(net_2716), .A2(net_32) );
INV_X4 inst_2581 ( .ZN(net_3620), .A(net_3619) );
CLKBUF_X2 inst_4896 ( .A(net_4881), .Z(net_4882) );
AND2_X4 inst_4110 ( .A1(net_3123), .A2(net_3103), .ZN(net_253) );
INV_X8 inst_2164 ( .ZN(net_3769), .A(net_3768) );
NAND2_X2 inst_1498 ( .ZN(net_2819), .A1(net_2774), .A2(net_2720) );
OAI221_X2 inst_432 ( .ZN(net_630), .A(net_629), .B1(net_628), .C1(net_627), .B2(net_393), .C2(net_329) );
OAI22_X2 inst_282 ( .B2(net_4041), .B1(net_2641), .A1(net_2591), .ZN(net_2527), .A2(net_2377) );
NAND3_X2 inst_1358 ( .ZN(net_3718), .A2(net_3715), .A1(net_3682), .A3(net_152) );
CLKBUF_X2 inst_4392 ( .A(net_4377), .Z(net_4378) );
CLKBUF_X2 inst_4915 ( .A(net_4900), .Z(net_4901) );
INV_X4 inst_2322 ( .ZN(net_1117), .A(net_720) );
OAI21_X2 inst_513 ( .B1(net_3274), .B2(net_3208), .ZN(net_2929), .A(net_2492) );
CLKBUF_X2 inst_4775 ( .A(net_4760), .Z(net_4761) );
DFF_X1 inst_3266 ( .QN(net_3070), .D(net_2931), .CK(net_4864) );
DFF_X2 inst_3171 ( .D(net_1949), .QN(net_124), .CK(net_5279) );
NAND2_X2 inst_1630 ( .A1(net_3581), .ZN(net_2513), .A2(net_2373) );
CLKBUF_X2 inst_4450 ( .A(net_4435), .Z(net_4436) );
NAND2_X2 inst_1586 ( .A1(net_2925), .ZN(net_2434), .A2(net_162) );
DFF_X1 inst_3385 ( .D(net_1832), .CK(net_5295), .Q(x633) );
DFF_X2 inst_3182 ( .QN(net_3125), .D(net_1804), .CK(net_4798) );
NAND2_X2 inst_1572 ( .A1(net_2912), .ZN(net_2449), .A2(net_195) );
INV_X2 inst_2866 ( .A(net_3127), .ZN(net_928) );
OAI21_X1 inst_774 ( .ZN(net_4010), .B2(net_2959), .B1(net_2893), .A(net_2504) );
INV_X4 inst_2292 ( .ZN(net_2268), .A(net_914) );
CLKBUF_X2 inst_4906 ( .A(net_4891), .Z(net_4892) );
CLKBUF_X2 inst_4256 ( .A(net_4241), .Z(net_4242) );
OAI211_X2 inst_838 ( .C1(net_1359), .ZN(net_1352), .C2(net_1351), .A(net_1233), .B(net_593) );
CLKBUF_X2 inst_5300 ( .A(net_5285), .Z(net_5286) );
INV_X2 inst_2766 ( .ZN(net_933), .A(net_870) );
CLKBUF_X2 inst_4326 ( .A(net_4308), .Z(net_4312) );
NAND2_X2 inst_1508 ( .A2(net_3600), .ZN(net_2689), .A1(net_2688) );
NAND4_X2 inst_1222 ( .ZN(net_951), .A4(net_733), .A3(net_554), .A1(net_520), .A2(net_480) );
CLKBUF_X2 inst_4978 ( .A(net_4538), .Z(net_4964) );
NAND2_X4 inst_1405 ( .A1(net_3498), .ZN(net_3238), .A2(net_2858) );
DFF_X1 inst_3407 ( .Q(net_4029), .D(net_1398), .CK(net_4500) );
AND4_X2 inst_4058 ( .ZN(net_1344), .A1(net_1343), .A4(net_1301), .A2(net_1174), .A3(net_1040) );
NOR2_X2 inst_1073 ( .ZN(net_698), .A1(net_697), .A2(net_611) );
INV_X4 inst_2323 ( .A(net_1041), .ZN(net_819) );
AOI222_X1 inst_3741 ( .A1(net_4189), .C1(net_3504), .B1(net_3472), .C2(net_3418), .ZN(net_2320), .A2(net_2033), .B2(net_179) );
INV_X2 inst_2749 ( .ZN(net_1079), .A(net_1078) );
NAND2_X4 inst_1449 ( .ZN(net_3808), .A2(net_3807), .A1(net_3537) );
XNOR2_X1 inst_127 ( .ZN(net_1732), .B(net_1608), .A(net_1597) );
CLKBUF_X2 inst_4367 ( .A(net_4307), .Z(net_4353) );
NAND2_X2 inst_2013 ( .A1(net_3913), .ZN(net_3614), .A2(net_3613) );
OR3_X2 inst_187 ( .ZN(net_3425), .A1(net_1650), .A2(net_966), .A3(net_415) );
OR2_X4 inst_206 ( .ZN(net_2965), .A2(net_2352), .A1(net_2350) );
CLKBUF_X2 inst_4506 ( .A(net_4491), .Z(net_4492) );
AOI222_X1 inst_3739 ( .B2(net_4030), .A2(net_3445), .C1(net_3242), .A1(net_3241), .B1(net_2752), .ZN(net_2635), .C2(net_2386) );
INV_X2 inst_3029 ( .ZN(net_3522), .A(net_434) );
NAND3_X4 inst_1268 ( .ZN(net_3869), .A3(net_3718), .A1(net_3683), .A2(net_3527) );
XNOR2_X2 inst_122 ( .B(net_4139), .ZN(net_4138), .A(net_818) );
INV_X2 inst_2756 ( .ZN(net_999), .A(net_998) );
OAI221_X2 inst_405 ( .C1(net_3492), .ZN(net_1947), .B2(net_1946), .A(net_1868), .B1(net_1800), .C2(net_1694) );
NAND2_X2 inst_1731 ( .A1(net_1556), .ZN(net_1554), .A2(x762) );
OAI21_X2 inst_492 ( .B1(net_3588), .B2(net_2967), .ZN(net_2950), .A(net_2405) );
CLKBUF_X2 inst_4788 ( .A(net_4773), .Z(net_4774) );
INV_X2 inst_2960 ( .A(net_3031), .ZN(net_213) );
NAND2_X2 inst_1909 ( .A2(net_3165), .ZN(net_325), .A1(net_321) );
AOI221_X2 inst_3912 ( .B2(net_4127), .A(net_4113), .ZN(net_687), .C1(net_686), .C2(net_342), .B1(net_245) );
CLKBUF_X2 inst_4318 ( .A(net_4268), .Z(net_4304) );
INV_X4 inst_2306 ( .A(net_1338), .ZN(net_837) );
CLKBUF_X2 inst_4335 ( .A(net_4320), .Z(net_4321) );
XNOR2_X2 inst_82 ( .B(net_4081), .ZN(net_1522), .A(net_1027) );
AND2_X4 inst_4187 ( .ZN(net_4183), .A1(net_2553), .A2(net_2003) );
CLKBUF_X2 inst_4239 ( .A(net_4224), .Z(net_4225) );
NAND2_X2 inst_1646 ( .ZN(net_2699), .A2(net_2169), .A1(net_2126) );
INV_X4 inst_2176 ( .ZN(net_2855), .A(net_2759) );
INV_X2 inst_2892 ( .A(net_3051), .ZN(net_146) );
NOR2_X2 inst_1121 ( .ZN(net_3414), .A2(net_3413), .A1(net_2718) );
NOR2_X2 inst_1102 ( .ZN(net_339), .A2(net_258), .A1(net_53) );
DFF_X2 inst_3161 ( .D(net_2164), .QN(net_109), .CK(net_4376) );
DFF_X2 inst_3187 ( .D(net_1742), .QN(net_266), .CK(net_4835) );
OAI22_X2 inst_307 ( .A2(net_2637), .A1(net_1543), .B1(net_1542), .ZN(net_1533), .B2(net_1532) );
INV_X2 inst_2816 ( .A(net_3733), .ZN(net_710) );
OAI21_X2 inst_702 ( .A(net_4084), .ZN(net_910), .B1(net_902), .B2(net_853) );
NAND2_X2 inst_2034 ( .ZN(net_3772), .A1(net_1809), .A2(net_360) );
NAND2_X2 inst_1505 ( .A2(net_3515), .ZN(net_2730), .A1(net_2620) );
OAI21_X2 inst_717 ( .B2(net_4000), .ZN(net_925), .B1(net_904), .A(net_702) );
OAI22_X4 inst_276 ( .A1(net_3556), .A2(net_3003), .B2(net_3000), .ZN(net_2110), .B1(net_1973) );
INV_X4 inst_2482 ( .A(net_3049), .ZN(net_495) );
INV_X2 inst_2957 ( .ZN(net_229), .A(net_112) );
DFF_X1 inst_3339 ( .D(net_2771), .CK(net_4360), .Q(x23) );
AOI222_X1 inst_3791 ( .ZN(net_985), .A2(net_984), .C1(net_983), .A1(net_638), .B1(net_599), .C2(net_333), .B2(net_225) );
INV_X2 inst_2711 ( .A(net_3437), .ZN(net_1602) );
AOI22_X2 inst_3531 ( .A1(net_3782), .B2(net_3160), .ZN(net_1883), .B1(net_1882), .A2(net_1762) );
INV_X2 inst_2753 ( .ZN(net_2189), .A(net_1044) );
AOI22_X2 inst_3672 ( .ZN(net_550), .A1(net_458), .B1(net_457), .A2(net_199), .B2(net_165) );
CLKBUF_X2 inst_5297 ( .A(net_5282), .Z(net_5283) );
XNOR2_X2 inst_91 ( .ZN(net_855), .B(net_854), .A(net_715) );
NAND2_X2 inst_1762 ( .A2(net_1394), .ZN(net_1237), .A1(net_34) );
SDFF_X2 inst_132 ( .D(net_3483), .SI(net_3024), .Q(net_3024), .SE(net_2912), .CK(net_5055) );
NAND2_X2 inst_2023 ( .ZN(net_3714), .A1(net_3712), .A2(net_976) );
INV_X2 inst_2779 ( .ZN(net_807), .A(net_761) );
AOI22_X2 inst_3686 ( .B2(net_4123), .A2(net_509), .ZN(net_494), .A1(net_493), .B1(net_492) );
AOI221_X2 inst_3842 ( .B2(net_2203), .C1(net_2202), .ZN(net_2200), .A(net_2072), .B1(net_2059), .C2(net_1791) );
CLKBUF_X2 inst_4919 ( .A(net_4904), .Z(net_4905) );
NAND2_X2 inst_1703 ( .ZN(net_1784), .A2(net_1783), .A1(net_1739) );
AOI22_X2 inst_3545 ( .B1(net_4054), .A1(net_1578), .ZN(net_1577), .A2(net_168), .B2(net_156) );
CLKBUF_X2 inst_4715 ( .A(net_4482), .Z(net_4701) );
AOI22_X2 inst_3611 ( .A1(net_4063), .B1(net_4058), .ZN(net_1406), .B2(net_176), .A2(net_163) );
INV_X2 inst_2928 ( .A(net_3126), .ZN(net_145) );
AOI221_X2 inst_3813 ( .A(net_2642), .B1(net_2641), .C1(net_2590), .ZN(net_2588), .C2(net_2581), .B2(net_280) );
OAI221_X2 inst_400 ( .B2(net_3428), .ZN(net_2284), .C1(net_2235), .B1(net_2184), .A(net_1991), .C2(net_110) );
INV_X2 inst_2991 ( .A(net_3120), .ZN(net_1541) );
OAI21_X2 inst_614 ( .A(net_3156), .ZN(net_2591), .B1(net_2293), .B2(net_2248) );
AOI22_X2 inst_3513 ( .B1(net_2625), .ZN(net_1970), .A1(net_1969), .A2(net_1837), .B2(net_152) );
NAND2_X2 inst_1896 ( .ZN(net_514), .A2(net_349), .A1(net_185) );
OR2_X2 inst_261 ( .A1(net_877), .ZN(net_863), .A2(net_745) );
NOR2_X2 inst_1031 ( .ZN(net_1578), .A1(net_1459), .A2(net_1458) );
NOR2_X4 inst_945 ( .ZN(net_3518), .A2(net_3454), .A1(net_2030) );
OR2_X2 inst_268 ( .A1(net_4137), .ZN(net_3374), .A2(net_42) );
NAND2_X2 inst_1518 ( .A1(net_3689), .ZN(net_2510), .A2(net_239) );
OAI221_X2 inst_369 ( .C1(net_3618), .ZN(net_2700), .C2(net_2699), .B2(net_2698), .B1(net_2543), .A(net_2368) );
CLKBUF_X2 inst_5161 ( .A(net_4542), .Z(net_5147) );
NAND2_X2 inst_1900 ( .A1(net_3657), .ZN(net_826), .A2(net_357) );
AOI21_X2 inst_3975 ( .B2(net_3399), .A(net_3337), .ZN(net_1159), .B1(net_995) );
OAI22_X2 inst_327 ( .A2(net_3468), .ZN(net_884), .B2(net_721), .A1(net_641), .B1(net_43) );
AOI22_X2 inst_3509 ( .B1(net_3676), .B2(net_3138), .A1(net_2012), .ZN(net_2008), .A2(net_1791) );
INV_X2 inst_2916 ( .A(net_3067), .ZN(net_244) );
NAND3_X2 inst_1286 ( .ZN(net_2261), .A1(net_2198), .A3(net_1952), .A2(net_1917) );
OR2_X2 inst_266 ( .ZN(net_3253), .A1(net_1161), .A2(net_1160) );
NAND2_X2 inst_2051 ( .ZN(net_3873), .A1(net_1982), .A2(net_177) );
AOI221_X2 inst_3853 ( .ZN(net_2061), .A(net_2060), .C1(net_2059), .C2(net_1908), .B2(net_749), .B1(net_94) );
NAND4_X2 inst_1198 ( .ZN(net_1676), .A3(net_1479), .A4(net_1478), .A1(net_1413), .A2(net_1412) );
XNOR2_X2 inst_77 ( .A(net_3379), .ZN(net_1387), .B(net_1291) );
OR3_X4 inst_171 ( .A2(net_3978), .ZN(net_882), .A3(net_881), .A1(net_707) );
HA_X1 inst_3097 ( .S(net_821), .CO(net_820), .A(net_642), .B(net_216) );
AOI22_X2 inst_3661 ( .A2(net_3027), .B2(net_3026), .A1(net_571), .B1(net_570), .ZN(net_566) );
OAI221_X2 inst_374 ( .B2(net_2733), .C1(net_2686), .ZN(net_2682), .A(net_2560), .B1(net_2332), .C2(net_2147) );
OAI21_X2 inst_502 ( .B1(net_3588), .B2(net_2959), .ZN(net_2940), .A(net_2498) );
XNOR2_X2 inst_103 ( .ZN(net_507), .A(net_372), .B(net_348) );
AOI22_X2 inst_3690 ( .B2(net_4124), .A2(net_555), .ZN(net_486), .B1(net_241), .A1(net_212) );
DFF_X1 inst_3221 ( .QN(net_3059), .D(net_2978), .CK(net_4568) );
AOI22_X2 inst_3645 ( .A1(net_4142), .B1(net_4112), .ZN(net_757), .B2(net_378), .A2(x717) );
NAND2_X2 inst_1598 ( .A1(net_2917), .ZN(net_2420), .A2(net_203) );
AOI222_X2 inst_3738 ( .C2(net_3418), .B2(net_1826), .ZN(net_977), .B1(net_677), .A1(net_626), .C1(net_578), .A2(net_225) );
OAI222_X1 inst_357 ( .C1(net_3784), .ZN(net_3362), .B2(net_3354), .A2(net_3153), .B1(net_1815), .A1(net_1814), .C2(net_117) );
INV_X2 inst_2855 ( .A(net_3657), .ZN(net_334) );
AND2_X4 inst_4092 ( .ZN(net_2849), .A1(net_2758), .A2(net_1825) );
NAND2_X2 inst_2058 ( .ZN(net_3910), .A2(net_3909), .A1(net_3908) );
OAI211_X2 inst_809 ( .A(net_3730), .ZN(net_1662), .C1(net_1617), .B(net_785), .C2(net_325) );
AOI21_X2 inst_3980 ( .A(net_4033), .ZN(net_981), .B2(net_770), .B1(net_57) );
AOI22_X2 inst_3675 ( .B2(net_555), .ZN(net_546), .A1(net_457), .A2(net_234), .B1(net_205) );
DFF_X2 inst_3152 ( .QN(net_3165), .D(net_2271), .CK(net_4805) );
AND2_X4 inst_4161 ( .ZN(net_4112), .A2(net_671), .A1(net_511) );
AOI222_X1 inst_3758 ( .A1(net_3676), .B1(net_2055), .C1(net_2054), .ZN(net_2034), .B2(net_2033), .A2(net_252), .C2(net_106) );
INV_X4 inst_2562 ( .ZN(net_3516), .A(net_3515) );
NAND4_X2 inst_1234 ( .ZN(net_869), .A3(net_557), .A1(net_524), .A2(net_490), .A4(net_465) );
NOR3_X2 inst_912 ( .ZN(net_3448), .A3(net_3447), .A2(net_3446), .A1(net_3445) );
INV_X4 inst_2398 ( .ZN(net_398), .A(net_320) );
INV_X4 inst_2595 ( .A(net_3951), .ZN(net_3727) );
NOR2_X2 inst_1022 ( .A1(net_3492), .ZN(net_1747), .A2(net_1641) );
DFF_X2 inst_3196 ( .D(net_1612), .Q(net_85), .CK(net_4797) );
INV_X4 inst_2371 ( .A(net_1126), .ZN(net_912) );
INV_X2 inst_2939 ( .A(net_3121), .ZN(net_1545) );
AOI211_X2 inst_4025 ( .ZN(net_1197), .A(net_1196), .C1(net_1135), .B(net_968), .C2(net_407) );
OAI22_X2 inst_322 ( .A1(net_2167), .A2(net_1071), .ZN(net_1021), .B2(net_433), .B1(net_135) );
NAND4_X2 inst_1223 ( .ZN(net_906), .A4(net_682), .A3(net_572), .A2(net_496), .A1(net_486) );
AOI22_X2 inst_3516 ( .B1(net_4045), .A2(net_3133), .A1(net_1955), .ZN(net_1954), .B2(net_282) );
INV_X2 inst_2785 ( .ZN(net_801), .A(net_755) );
AOI221_X2 inst_3906 ( .A(net_4090), .C2(net_1045), .ZN(net_1010), .C1(net_790), .B1(net_694), .B2(net_414) );
AND2_X2 inst_4200 ( .A1(net_3925), .ZN(net_900), .A2(net_403) );
AND2_X4 inst_4188 ( .ZN(net_4184), .A1(net_1308), .A2(net_59) );
OAI21_X2 inst_681 ( .B2(net_3974), .ZN(net_1290), .A(net_1279), .B1(net_1108) );
CLKBUF_X2 inst_4886 ( .A(net_4842), .Z(net_4872) );
AND2_X4 inst_4169 ( .ZN(net_4123), .A1(net_338), .A2(net_144) );
AOI221_X2 inst_3902 ( .ZN(net_1609), .B2(net_1011), .A(net_993), .B1(net_787), .C1(net_696), .C2(net_432) );
NAND2_X2 inst_2010 ( .A2(net_3866), .ZN(net_3582), .A1(net_3516) );
INV_X2 inst_2915 ( .A(net_3096), .ZN(net_167) );
DFF_X1 inst_3296 ( .QN(net_3008), .D(net_2884), .CK(net_5220) );
AND2_X4 inst_4181 ( .ZN(net_4142), .A1(net_1463), .A2(x1023) );
NOR4_X2 inst_871 ( .A4(net_4106), .A1(net_3429), .ZN(net_1143), .A2(net_919), .A3(net_794) );
INV_X4 inst_2315 ( .A(net_1200), .ZN(net_983) );
INV_X2 inst_2684 ( .A(net_2076), .ZN(net_1836) );
NOR2_X4 inst_962 ( .ZN(net_3787), .A2(net_3216), .A1(net_2110) );
OAI21_X2 inst_532 ( .B1(net_3195), .B2(net_2969), .ZN(net_2901), .A(net_2418) );
DFF_X2 inst_3164 ( .D(net_2162), .QN(net_61), .CK(net_4654) );
INV_X2 inst_2965 ( .A(net_3118), .ZN(net_130) );
INV_X4 inst_2382 ( .ZN(net_931), .A(net_401) );
NAND2_X2 inst_2008 ( .A1(net_3817), .ZN(net_3538), .A2(net_199) );
NOR2_X1 inst_1171 ( .ZN(net_3690), .A1(net_2307), .A2(net_70) );
OAI21_X2 inst_641 ( .ZN(net_1995), .B1(net_1993), .A(net_1895), .B2(net_1532) );
CLKBUF_X2 inst_5274 ( .A(net_4908), .Z(net_5260) );
INV_X2 inst_2969 ( .ZN(net_149), .A(net_107) );
OAI21_X2 inst_498 ( .B1(net_3588), .B2(net_2963), .ZN(net_2944), .A(net_2455) );
DFF_X1 inst_3314 ( .Q(net_3132), .D(net_2841), .CK(net_4658) );
NAND2_X2 inst_1988 ( .A1(net_3969), .A2(net_3634), .ZN(net_3432) );
CLKBUF_X2 inst_5113 ( .A(net_5098), .Z(net_5099) );
INV_X4 inst_2594 ( .ZN(net_3721), .A(net_3720) );
AND4_X4 inst_4037 ( .ZN(net_1760), .A2(net_1589), .A1(net_1055), .A3(net_1005), .A4(net_971) );
NAND2_X2 inst_1912 ( .ZN(net_293), .A1(net_290), .A2(net_250) );
AOI21_X2 inst_3976 ( .ZN(net_1156), .A(net_1155), .B1(net_1154), .B2(net_1153) );
NAND2_X2 inst_1831 ( .ZN(net_794), .A2(net_745), .A1(net_674) );
NAND3_X2 inst_1327 ( .A2(net_3713), .A3(net_3590), .ZN(net_672), .A1(net_602) );
AOI22_X2 inst_3468 ( .B2(net_3117), .A1(net_2724), .ZN(net_2723), .B1(net_2722), .A2(net_34) );
OAI222_X2 inst_350 ( .C1(net_3784), .A2(net_2165), .ZN(net_1937), .A1(net_1815), .B1(net_1814), .B2(net_327), .C2(net_116) );
INV_X4 inst_2395 ( .ZN(net_594), .A(net_358) );
OR2_X4 inst_231 ( .A1(net_3158), .ZN(net_409), .A2(net_406) );
NOR2_X2 inst_1119 ( .ZN(net_3409), .A1(net_2610), .A2(net_2385) );
DFF_X1 inst_3309 ( .QN(net_3014), .D(net_2867), .CK(net_5204) );
AOI22_X2 inst_3699 ( .B1(net_4123), .A1(net_555), .ZN(net_473), .A2(net_203), .B2(net_173) );
CLKBUF_X2 inst_5104 ( .A(net_5089), .Z(net_5090) );
CLKBUF_X2 inst_5082 ( .A(net_5067), .Z(net_5068) );
NAND4_X2 inst_1255 ( .ZN(net_3879), .A3(net_3210), .A2(net_3209), .A4(net_3205), .A1(net_2177) );
CLKBUF_X2 inst_5050 ( .A(net_4422), .Z(net_5036) );
INV_X4 inst_2317 ( .ZN(net_1652), .A(net_1637) );
NAND2_X2 inst_1791 ( .A2(net_1264), .ZN(net_993), .A1(net_882) );
NAND2_X4 inst_1452 ( .ZN(net_3831), .A2(net_3830), .A1(net_3202) );
CLKBUF_X2 inst_4925 ( .A(net_4652), .Z(net_4911) );
DFF_X1 inst_3420 ( .D(net_1358), .Q(net_32), .CK(net_4285) );
CLKBUF_X2 inst_5000 ( .A(net_4356), .Z(net_4986) );
AND3_X4 inst_4077 ( .ZN(net_4096), .A1(net_3993), .A3(net_3628), .A2(net_337) );
DFF_X2 inst_3139 ( .QN(net_2985), .D(net_2574), .CK(net_5238) );
CLKBUF_X2 inst_4457 ( .A(net_4442), .Z(net_4443) );
CLKBUF_X2 inst_5064 ( .A(net_5049), .Z(net_5050) );
OAI21_X2 inst_528 ( .B1(net_3302), .B2(net_3207), .ZN(net_2906), .A(net_2479) );
INV_X4 inst_2558 ( .ZN(net_3503), .A(net_3502) );
NOR3_X2 inst_903 ( .A2(net_1717), .ZN(net_960), .A1(net_913), .A3(net_847) );
NAND2_X2 inst_1725 ( .A1(net_2042), .ZN(net_1653), .A2(net_671) );
CLKBUF_X2 inst_4957 ( .A(net_4942), .Z(net_4943) );
NAND2_X4 inst_1396 ( .A1(net_3229), .ZN(net_1600), .A2(net_294) );
OAI222_X2 inst_352 ( .C1(net_3784), .A2(net_2272), .C2(net_1960), .ZN(net_1858), .A1(net_1815), .B1(net_1814), .B2(net_316) );
OAI211_X2 inst_846 ( .C1(net_1274), .ZN(net_892), .B(net_891), .A(net_779), .C2(net_777) );
OAI22_X2 inst_286 ( .B2(net_3164), .A2(net_2514), .ZN(net_1974), .A1(net_1843), .B1(x475) );
AOI22_X2 inst_3504 ( .B1(net_3676), .B2(net_3147), .A2(net_2033), .ZN(net_2014), .A1(net_2012) );
AOI21_X4 inst_3924 ( .B2(net_3600), .ZN(net_3482), .A(net_3481), .B1(net_3372) );
NAND2_X2 inst_1734 ( .A1(net_1556), .ZN(net_1551), .A2(x916) );
CLKBUF_X2 inst_4510 ( .A(net_4424), .Z(net_4496) );
CLKBUF_X2 inst_4646 ( .A(net_4631), .Z(net_4632) );
CLKBUF_X2 inst_4572 ( .A(net_4557), .Z(net_4558) );
CLKBUF_X2 inst_5189 ( .A(net_5174), .Z(net_5175) );
INV_X2 inst_3003 ( .A(net_3219), .ZN(net_3206) );
AOI221_X2 inst_3841 ( .B2(net_2203), .C1(net_2202), .ZN(net_2201), .A(net_2078), .B1(net_1823), .C2(net_168) );
AOI22_X2 inst_3464 ( .ZN(net_2767), .A1(net_2738), .B1(net_2711), .A2(net_1323), .B2(net_211) );
INV_X4 inst_2185 ( .ZN(net_2675), .A(net_2546) );
AND4_X4 inst_4050 ( .ZN(net_4094), .A1(net_3900), .A3(net_3395), .A4(net_513), .A2(net_386) );
NOR2_X2 inst_1044 ( .A1(net_1587), .ZN(net_1180), .A2(net_1064) );
DFF_X1 inst_3354 ( .D(net_2632), .Q(net_68), .CK(net_4262) );
INV_X4 inst_2370 ( .A(net_533), .ZN(net_430) );
CLKBUF_X2 inst_4993 ( .A(net_4978), .Z(net_4979) );
AOI221_X2 inst_3882 ( .B1(net_2020), .C1(net_2019), .ZN(net_1813), .A(net_1812), .B2(net_77), .C2(x450) );
INV_X2 inst_2811 ( .ZN(net_651), .A(net_650) );
INV_X2 inst_3014 ( .ZN(net_3401), .A(net_3011) );
CLKBUF_X2 inst_4615 ( .A(net_4600), .Z(net_4601) );
SDFF_X2 inst_137 ( .SE(net_2625), .D(net_2367), .SI(net_94), .Q(net_94), .CK(net_4961) );
OAI221_X2 inst_425 ( .C1(net_3924), .C2(net_3755), .B1(net_3566), .B2(net_3478), .ZN(net_1147), .A(net_998) );
INV_X4 inst_2567 ( .A(net_3685), .ZN(net_3533) );
DFF_X2 inst_3206 ( .QN(net_3102), .D(net_1303), .CK(net_4985) );
NAND2_X2 inst_1532 ( .A1(net_3208), .ZN(net_2490), .A2(net_596) );
OR2_X4 inst_227 ( .ZN(net_1105), .A1(net_693), .A2(net_605) );
CLKBUF_X2 inst_4303 ( .A(net_4288), .Z(net_4289) );
INV_X8 inst_2136 ( .A(net_3108), .ZN(net_337) );
AOI21_X4 inst_3927 ( .ZN(net_3583), .B1(net_3366), .A(net_3297), .B2(net_2607) );
INV_X2 inst_2891 ( .ZN(net_770), .A(x956) );
INV_X2 inst_2718 ( .A(net_3859), .ZN(net_2342) );
INV_X4 inst_2572 ( .A(net_3672), .ZN(net_3550) );
XNOR2_X2 inst_58 ( .ZN(net_2121), .B(net_1928), .A(net_1787) );
AOI22_X2 inst_3633 ( .A1(net_990), .ZN(net_876), .B1(net_874), .B2(net_721), .A2(net_371) );
AND4_X4 inst_4046 ( .A2(net_4110), .ZN(net_4075), .A4(net_3327), .A3(net_722), .A1(net_433) );
DFF_X1 inst_3365 ( .D(net_2308), .CK(net_4253), .Q(x179) );
NAND2_X4 inst_1469 ( .ZN(net_3901), .A2(net_3900), .A1(net_3899) );
DFF_X1 inst_3254 ( .QN(net_3079), .D(net_2951), .CK(net_4539) );
CLKBUF_X2 inst_5029 ( .A(net_4670), .Z(net_5015) );
NOR2_X2 inst_983 ( .ZN(net_2693), .A1(net_2624), .A2(net_2623) );
CLKBUF_X2 inst_4980 ( .A(net_4965), .Z(net_4966) );
NAND2_X2 inst_1897 ( .ZN(net_362), .A1(net_345), .A2(net_144) );
DFF_X2 inst_3159 ( .D(net_2157), .QN(net_58), .CK(net_4381) );
CLKBUF_X2 inst_5288 ( .A(net_5273), .Z(net_5274) );
INV_X4 inst_2551 ( .A(net_3686), .ZN(net_3456) );
OAI21_X2 inst_581 ( .B2(net_3207), .B1(net_2803), .ZN(net_2797), .A(net_2488) );
CLKBUF_X2 inst_4407 ( .A(net_4392), .Z(net_4393) );
XOR2_X1 inst_28 ( .Z(net_1281), .B(net_1280), .A(net_1085) );
INV_X4 inst_2424 ( .A(net_3128), .ZN(net_248) );
CLKBUF_X2 inst_4517 ( .A(net_4502), .Z(net_4503) );
CLKBUF_X2 inst_4776 ( .A(net_4761), .Z(net_4762) );
NAND2_X2 inst_1569 ( .A1(net_2912), .ZN(net_2452), .A2(net_202) );
DFF_X2 inst_3144 ( .D(net_2539), .QN(net_111), .CK(net_4395) );
INV_X2 inst_2633 ( .A(net_2670), .ZN(net_2659) );
NAND2_X2 inst_1772 ( .ZN(net_1369), .A1(net_1050), .A2(net_748) );
OAI21_X2 inst_592 ( .B1(net_2615), .ZN(net_2580), .B2(net_1529), .A(net_671) );
AOI22_X2 inst_3666 ( .B2(net_4015), .A2(net_4013), .A1(net_571), .B1(net_570), .ZN(net_561) );
NOR2_X2 inst_993 ( .A2(net_3447), .ZN(net_2299), .A1(net_2216) );
INV_X8 inst_2143 ( .ZN(net_3198), .A(net_3197) );
NAND3_X2 inst_1291 ( .ZN(net_2256), .A1(net_2199), .A3(net_1950), .A2(net_1922) );
CLKBUF_X2 inst_5177 ( .A(net_5162), .Z(net_5163) );
CLKBUF_X2 inst_5143 ( .A(net_5128), .Z(net_5129) );
INV_X8 inst_2130 ( .A(net_3613), .ZN(net_358) );
OAI221_X2 inst_359 ( .B2(net_3381), .ZN(net_2830), .B1(net_2826), .C1(net_2825), .A(net_2586), .C2(net_1516) );
CLKBUF_X2 inst_4388 ( .A(net_4373), .Z(net_4374) );
NOR2_X2 inst_1055 ( .A1(net_1132), .ZN(net_1050), .A2(net_532) );
CLKBUF_X2 inst_5096 ( .A(net_5081), .Z(net_5082) );
NAND2_X1 inst_2100 ( .ZN(net_3805), .A2(net_3803), .A1(net_3329) );
AOI21_X2 inst_3948 ( .A(net_3363), .B1(net_2238), .ZN(net_2208), .B2(net_243) );
INV_X4 inst_2284 ( .ZN(net_1656), .A(net_1120) );
NAND2_X2 inst_1962 ( .A2(net_3751), .A1(net_3694), .ZN(net_3311) );
OAI21_X2 inst_630 ( .B1(net_4044), .ZN(net_2241), .A(net_2142), .B2(net_2127) );
CLKBUF_X2 inst_5227 ( .A(net_5212), .Z(net_5213) );
CLKBUF_X2 inst_4829 ( .A(net_4814), .Z(net_4815) );
CLKBUF_X2 inst_5268 ( .A(net_5253), .Z(net_5254) );
CLKBUF_X2 inst_4757 ( .A(net_4338), .Z(net_4743) );
NAND3_X2 inst_1273 ( .ZN(net_2879), .A1(net_2864), .A2(net_2796), .A3(net_2751) );
NOR2_X4 inst_923 ( .ZN(net_2279), .A1(net_2178), .A2(net_2112) );
OAI21_X2 inst_512 ( .B1(net_3274), .B2(net_2959), .ZN(net_2930), .A(net_2500) );
CLKBUF_X2 inst_4966 ( .A(net_4381), .Z(net_4952) );
NAND3_X2 inst_1301 ( .A2(net_3406), .A3(net_1845), .ZN(net_1377), .A1(net_1376) );
CLKBUF_X2 inst_5283 ( .A(net_5268), .Z(net_5269) );
INV_X8 inst_2151 ( .A(net_3569), .ZN(net_3345) );
INV_X2 inst_2830 ( .A(net_3215), .ZN(net_440) );
OAI21_X2 inst_647 ( .ZN(net_2114), .B2(net_1852), .A(net_620), .B1(net_619) );
INV_X2 inst_3054 ( .ZN(net_3914), .A(net_3912) );
OR2_X4 inst_194 ( .ZN(net_2907), .A2(net_2354), .A1(net_2353) );
CLKBUF_X2 inst_4764 ( .A(net_4305), .Z(net_4750) );
CLKBUF_X2 inst_5137 ( .A(net_5059), .Z(net_5123) );
INV_X2 inst_2985 ( .A(net_3114), .ZN(net_1537) );
AOI222_X1 inst_3766 ( .B1(net_4048), .A1(net_1968), .ZN(net_1966), .C1(net_375), .C2(net_361), .A2(net_240), .B2(net_69) );
OAI211_X2 inst_833 ( .C1(net_1359), .ZN(net_1358), .A(net_1240), .B(net_593), .C2(net_331) );
AOI222_X1 inst_3772 ( .A2(net_2033), .ZN(net_1900), .A1(net_1863), .B1(net_1862), .C1(net_1861), .C2(net_1280), .B2(net_856) );
AND2_X2 inst_4210 ( .A1(net_4126), .ZN(net_3985), .A2(net_3979) );
INV_X4 inst_2536 ( .A(net_3867), .ZN(net_3347) );
NAND2_X2 inst_2043 ( .ZN(net_3845), .A2(net_3842), .A1(net_432) );
NOR2_X4 inst_960 ( .A2(net_3837), .ZN(net_3775), .A1(net_3574) );
CLKBUF_X2 inst_4924 ( .A(net_4909), .Z(net_4910) );
XNOR2_X2 inst_118 ( .ZN(net_3794), .B(net_3792), .A(net_1285) );
INV_X4 inst_2411 ( .ZN(net_271), .A(net_59) );
OAI221_X2 inst_442 ( .B2(net_3978), .C2(net_3634), .ZN(net_3558), .B1(net_1152), .C1(net_897), .A(net_841) );
INV_X4 inst_2507 ( .A(net_3059), .ZN(net_568) );
INV_X4 inst_2245 ( .ZN(net_1840), .A(net_1465) );
XOR2_X1 inst_38 ( .Z(net_4147), .B(net_1511), .A(net_1310) );
INV_X4 inst_2601 ( .ZN(net_3760), .A(net_3759) );
NAND2_X2 inst_2037 ( .A2(net_3959), .ZN(net_3789), .A1(net_3606) );
OAI221_X2 inst_381 ( .B2(net_2670), .C1(net_2668), .ZN(net_2639), .B1(net_2638), .C2(net_2637), .A(net_1386) );
CLKBUF_X2 inst_5237 ( .A(net_5222), .Z(net_5223) );
AOI221_X2 inst_3837 ( .B1(net_3774), .C1(net_2227), .ZN(net_2223), .C2(net_2222), .A(net_2113), .B2(net_294) );
NAND2_X2 inst_1925 ( .ZN(net_3188), .A1(net_3187), .A2(net_188) );
CLKBUF_X2 inst_4298 ( .A(net_4283), .Z(net_4284) );
NOR3_X2 inst_883 ( .ZN(net_2812), .A1(net_2770), .A2(net_2749), .A3(net_2616) );
XNOR2_X2 inst_40 ( .ZN(net_2828), .A(net_2678), .B(net_1696) );
CLKBUF_X2 inst_4437 ( .A(net_4208), .Z(net_4423) );
NAND4_X2 inst_1249 ( .A3(net_3971), .A4(net_3970), .ZN(net_3626), .A2(net_3625), .A1(net_3624) );
OAI21_X2 inst_756 ( .ZN(net_3710), .A(net_3709), .B2(net_3407), .B1(net_2229) );
AND2_X4 inst_4099 ( .A1(net_4067), .ZN(net_1365), .A2(net_996) );
CLKBUF_X2 inst_4740 ( .A(net_4725), .Z(net_4726) );
NAND2_X4 inst_1416 ( .ZN(net_3510), .A2(net_2342), .A1(net_2288) );
NAND3_X2 inst_1318 ( .ZN(net_1845), .A2(net_432), .A1(net_339), .A3(net_321) );
OAI221_X2 inst_439 ( .ZN(net_3386), .C2(net_3385), .A(net_629), .C1(net_628), .B1(net_627), .B2(net_42) );
CLKBUF_X2 inst_4597 ( .A(net_4582), .Z(net_4583) );
NAND4_X2 inst_1188 ( .A4(net_4112), .A1(net_3427), .A3(net_3406), .ZN(net_1993), .A2(net_1376) );
NOR2_X1 inst_1165 ( .A1(net_3229), .ZN(net_1373), .A2(net_69) );
CLKBUF_X2 inst_4529 ( .A(net_4514), .Z(net_4515) );
INV_X2 inst_2644 ( .ZN(net_2337), .A(net_2316) );
CLKBUF_X2 inst_4584 ( .A(net_4569), .Z(net_4570) );
NOR2_X2 inst_1070 ( .A1(net_3563), .A2(net_3549), .ZN(net_867) );
INV_X4 inst_2626 ( .ZN(net_4004), .A(net_3167) );
CLKBUF_X2 inst_4629 ( .A(net_4614), .Z(net_4615) );
INV_X4 inst_2454 ( .A(net_3090), .ZN(net_596) );
AOI22_X2 inst_3601 ( .A1(net_4062), .B1(net_4057), .ZN(net_1416), .B2(net_492), .A2(net_471) );
AOI221_X2 inst_3873 ( .B1(net_2020), .C1(net_2019), .ZN(net_1930), .A(net_1929), .B2(net_255), .C2(x423) );
CLKBUF_X2 inst_4536 ( .A(net_4521), .Z(net_4522) );
NOR2_X2 inst_992 ( .A1(net_3882), .A2(net_3516), .ZN(net_2529) );
OAI21_X2 inst_488 ( .B1(net_3588), .B2(net_2972), .ZN(net_2954), .A(net_2427) );
CLKBUF_X2 inst_5196 ( .A(net_5181), .Z(net_5182) );
OAI221_X2 inst_387 ( .B2(net_3795), .ZN(net_2602), .B1(net_2601), .C1(net_2521), .A(net_1386), .C2(net_316) );
OR2_X2 inst_254 ( .ZN(net_1334), .A1(net_1168), .A2(net_1167) );
CLKBUF_X2 inst_4601 ( .A(net_4586), .Z(net_4587) );
OAI21_X2 inst_654 ( .B2(net_2147), .ZN(net_1943), .B1(net_1815), .A(net_1803) );
NAND2_X2 inst_1673 ( .A1(net_3185), .ZN(net_2085), .A2(net_191) );
INV_X8 inst_2129 ( .A(net_3940), .ZN(net_516) );
NAND2_X4 inst_1412 ( .ZN(net_3342), .A1(net_3341), .A2(net_3288) );
NAND2_X2 inst_1708 ( .A2(net_4082), .ZN(net_1728), .A1(net_1726) );
NAND4_X2 inst_1181 ( .A1(net_3449), .ZN(net_2385), .A2(net_2384), .A3(net_1381), .A4(net_387) );
NOR2_X2 inst_1153 ( .ZN(net_3979), .A1(net_3659), .A2(net_283) );
AOI221_X2 inst_3823 ( .B2(net_3141), .A(net_2642), .B1(net_2591), .C1(net_2589), .ZN(net_2554), .C2(net_2553) );
CLKBUF_X2 inst_5045 ( .A(net_4505), .Z(net_5031) );
OAI221_X2 inst_391 ( .C2(net_3408), .ZN(net_2362), .B1(net_2361), .C1(net_2221), .A(net_1932), .B2(net_107) );
OAI21_X2 inst_661 ( .A(net_1912), .ZN(net_1723), .B2(net_1582), .B1(net_1300) );
AND2_X4 inst_4107 ( .A1(net_3108), .ZN(net_305), .A2(net_50) );
NAND2_X2 inst_1548 ( .A1(net_2961), .ZN(net_2474), .A2(net_487) );
NAND2_X2 inst_2073 ( .ZN(net_4007), .A1(net_3168), .A2(net_3167) );
INV_X2 inst_2738 ( .A(net_3229), .ZN(net_2690) );
CLKBUF_X2 inst_4682 ( .A(net_4620), .Z(net_4668) );
AOI21_X2 inst_3984 ( .B1(net_4106), .ZN(net_909), .A(net_908), .B2(net_246) );
OAI21_X2 inst_634 ( .ZN(net_2077), .B2(net_2076), .A(net_1962), .B1(net_1671) );
OAI221_X2 inst_419 ( .B2(net_3103), .C1(net_1614), .ZN(net_1249), .A(net_1119), .B1(net_1069), .C2(net_332) );
DFF_X2 inst_3122 ( .QN(net_3137), .D(net_2682), .CK(net_4585) );
NAND2_X4 inst_1477 ( .ZN(net_3942), .A2(net_3171), .A1(net_52) );
CLKBUF_X2 inst_5130 ( .A(net_5115), .Z(net_5116) );
AOI22_X2 inst_3717 ( .ZN(net_3566), .A2(net_3565), .A1(net_963), .B1(net_728), .B2(net_659) );
XOR2_X1 inst_34 ( .A(net_4136), .Z(net_3312), .B(net_1510) );
NAND2_X2 inst_1799 ( .ZN(net_941), .A1(net_830), .A2(net_601) );
XOR2_X2 inst_12 ( .Z(net_1289), .B(net_1288), .A(net_1087) );
OAI21_X2 inst_529 ( .B2(net_2965), .B1(net_2923), .ZN(net_2905), .A(net_2440) );
CLKBUF_X2 inst_4442 ( .A(net_4427), .Z(net_4428) );
NAND2_X2 inst_1528 ( .A1(net_3208), .ZN(net_2494), .A2(net_567) );
NAND2_X4 inst_1424 ( .ZN(net_3587), .A2(net_3586), .A1(net_3584) );
CLKBUF_X2 inst_5290 ( .A(net_5275), .Z(net_5276) );
CLKBUF_X2 inst_4694 ( .A(net_4441), .Z(net_4680) );
NAND3_X2 inst_1313 ( .A2(net_4080), .A3(net_3664), .ZN(net_945), .A1(net_943) );
NAND2_X4 inst_1425 ( .ZN(net_3601), .A2(net_3600), .A1(net_3597) );
OAI21_X2 inst_675 ( .ZN(net_1542), .B1(net_1340), .B2(net_1334), .A(net_671) );
AND3_X4 inst_4068 ( .A2(net_3925), .ZN(net_1057), .A3(net_1016), .A1(net_945) );
AND2_X4 inst_4116 ( .ZN(net_3996), .A1(net_3995), .A2(net_3167) );
INV_X2 inst_2886 ( .A(net_3035), .ZN(net_180) );
INV_X2 inst_2705 ( .ZN(net_1668), .A(net_1667) );
INV_X4 inst_2307 ( .A(net_2523), .ZN(net_2522) );
INV_X4 inst_2198 ( .A(net_2641), .ZN(net_2375) );
OR2_X2 inst_258 ( .A2(net_4103), .ZN(net_965), .A1(net_849) );
CLKBUF_X2 inst_5150 ( .A(net_5135), .Z(net_5136) );
INV_X4 inst_2611 ( .ZN(net_3823), .A(net_3820) );
CLKBUF_X2 inst_5004 ( .A(net_4767), .Z(net_4990) );
INV_X2 inst_2773 ( .ZN(net_846), .A(net_792) );
NAND2_X1 inst_2081 ( .A1(net_3532), .ZN(net_2853), .A2(net_2515) );
DFF_X1 inst_3261 ( .QN(net_3075), .D(net_2933), .CK(net_4871) );
INV_X4 inst_2405 ( .A(net_1173), .ZN(net_671) );
INV_X2 inst_2994 ( .A(net_3040), .ZN(net_195) );
INV_X2 inst_3023 ( .ZN(net_3451), .A(net_3171) );
NAND4_X2 inst_1243 ( .ZN(net_3353), .A1(net_739), .A2(net_560), .A3(net_494), .A4(net_472) );
INV_X1 inst_3076 ( .ZN(net_1055), .A(net_1054) );
NAND4_X2 inst_1211 ( .ZN(net_1248), .A2(net_1048), .A4(net_893), .A1(net_865), .A3(net_795) );
OAI21_X2 inst_482 ( .B1(net_2970), .ZN(net_2962), .B2(net_2961), .A(net_2473) );
AOI222_X1 inst_3751 ( .B1(net_4044), .C1(net_3114), .A1(net_2055), .C2(net_2053), .ZN(net_2052), .A2(net_2051), .B2(net_1190) );
NAND4_X2 inst_1192 ( .ZN(net_1906), .A4(net_1498), .A3(net_1496), .A1(net_1434), .A2(net_1429) );
OAI21_X2 inst_682 ( .ZN(net_1455), .A(net_1273), .B2(net_1154), .B1(net_1077) );
AOI22_X2 inst_3534 ( .A2(net_1908), .ZN(net_1771), .A1(net_1672), .B2(net_749), .B1(net_104) );
OR2_X4 inst_238 ( .ZN(net_3441), .A1(net_3196), .A2(net_262) );
DFF_X1 inst_3276 ( .QN(net_3036), .D(net_2908), .CK(net_5018) );
AOI21_X2 inst_3996 ( .B2(net_3804), .ZN(net_3369), .A(net_3330), .B1(net_3269) );
NOR2_X2 inst_1093 ( .A1(net_3755), .A2(net_530), .ZN(net_403) );
OAI21_X2 inst_539 ( .ZN(net_4008), .B2(net_2972), .B1(net_2893), .A(net_2433) );
INV_X4 inst_2222 ( .ZN(net_2043), .A(net_1869) );
CLKBUF_X2 inst_4578 ( .A(net_4563), .Z(net_4564) );
DFF_X1 inst_3333 ( .D(net_3357), .Q(net_3138), .CK(net_4642) );
NOR3_X2 inst_895 ( .A2(net_3486), .A1(net_1800), .ZN(net_1750), .A3(net_1686) );
AND4_X2 inst_4059 ( .ZN(net_3691), .A4(net_3690), .A1(net_3687), .A3(net_3309), .A2(net_3308) );
DFF_X2 inst_3109 ( .QN(net_2995), .D(net_2801), .CK(net_5104) );
DFF_X1 inst_3271 ( .QN(net_3100), .D(net_2924), .CK(net_5029) );
NAND2_X4 inst_1430 ( .ZN(net_3633), .A2(net_3632), .A1(net_3544) );
NAND2_X2 inst_1755 ( .ZN(net_1278), .A1(net_1277), .A2(net_1082) );
DFF_X1 inst_3257 ( .QN(net_3086), .D(net_2942), .CK(net_4723) );
INV_X4 inst_2240 ( .A(net_1653), .ZN(net_1603) );
NAND4_X2 inst_1210 ( .ZN(net_1260), .A2(net_1059), .A1(net_1053), .A3(net_1024), .A4(net_929) );
INV_X4 inst_2341 ( .A(net_3961), .ZN(net_1096) );
INV_X4 inst_2437 ( .A(net_3172), .ZN(net_198) );
OAI211_X2 inst_806 ( .ZN(net_1777), .C2(net_1776), .A(net_1683), .C1(net_1562), .B(net_1403) );
CLKBUF_X2 inst_4521 ( .A(net_4506), .Z(net_4507) );
AND2_X4 inst_4122 ( .ZN(net_4046), .A1(net_2594), .A2(net_2003) );
NAND2_X2 inst_1981 ( .ZN(net_3391), .A2(net_3389), .A1(net_3128) );
OAI21_X2 inst_763 ( .B1(net_3902), .ZN(net_3891), .B2(net_3890), .A(net_3889) );
INV_X4 inst_2330 ( .A(net_3524), .ZN(net_749) );
OAI21_X2 inst_491 ( .B1(net_3394), .B2(net_2967), .ZN(net_2951), .A(net_2406) );
CLKBUF_X2 inst_4943 ( .A(net_4928), .Z(net_4929) );
AOI22_X2 inst_3636 ( .A1(net_2220), .ZN(net_1160), .B1(net_1071), .A2(net_401), .B2(net_265) );
AOI222_X1 inst_3775 ( .ZN(net_1895), .C2(net_1874), .A1(net_1863), .B1(net_1862), .C1(net_1861), .A2(net_1797), .B2(net_1123) );
OAI21_X2 inst_537 ( .B1(net_3195), .B2(net_2959), .ZN(net_2896), .A(net_2503) );
CLKBUF_X2 inst_4797 ( .A(net_4782), .Z(net_4783) );
INV_X4 inst_2472 ( .A(net_3057), .ZN(net_488) );
OAI211_X2 inst_826 ( .ZN(net_2551), .A(net_1252), .C1(net_1206), .B(net_1186), .C2(net_347) );
INV_X1 inst_3086 ( .ZN(net_3998), .A(net_3996) );
AOI21_X2 inst_4002 ( .A(net_4146), .ZN(net_3730), .B2(net_788), .B1(net_675) );
INV_X2 inst_2791 ( .A(net_850), .ZN(net_789) );
CLKBUF_X2 inst_5069 ( .A(net_5054), .Z(net_5055) );
OR4_X2 inst_159 ( .A4(net_2596), .ZN(net_2270), .A1(net_2269), .A3(net_2268), .A2(net_1569) );
NOR4_X2 inst_872 ( .A3(net_1611), .ZN(net_369), .A4(net_355), .A1(net_286), .A2(net_84) );
CLKBUF_X2 inst_4419 ( .A(net_4229), .Z(net_4405) );
CLKBUF_X2 inst_5234 ( .A(net_5219), .Z(net_5220) );
NAND2_X2 inst_1667 ( .A1(net_2134), .ZN(net_2091), .A2(net_146) );
NAND3_X2 inst_1349 ( .ZN(net_3631), .A1(net_3630), .A2(net_3545), .A3(net_3542) );
AOI21_X2 inst_3950 ( .B1(net_3736), .ZN(net_1991), .A(net_1943), .B2(net_1507) );
OAI21_X4 inst_462 ( .A(net_3859), .B2(net_3791), .ZN(net_3517), .B1(net_3333) );
CLKBUF_X2 inst_4288 ( .A(net_4273), .Z(net_4274) );
NOR4_X2 inst_869 ( .A2(net_3841), .A3(net_3563), .ZN(net_970), .A1(net_809), .A4(net_700) );
INV_X2 inst_2646 ( .A(net_3875), .ZN(net_2315) );
XOR2_X2 inst_19 ( .Z(net_4036), .A(net_2517), .B(net_1709) );
AOI222_X1 inst_3745 ( .A1(net_4189), .C1(net_3504), .B1(net_3472), .C2(net_3385), .B2(net_3151), .ZN(net_2316), .A2(net_379) );
CLKBUF_X2 inst_4347 ( .A(net_4332), .Z(net_4333) );
CLKBUF_X2 inst_4268 ( .A(net_4220), .Z(net_4254) );
INV_X4 inst_2224 ( .ZN(net_2012), .A(net_1890) );
AOI221_X2 inst_3830 ( .B1(net_4189), .C1(net_2534), .ZN(net_2369), .A(net_2289), .B2(net_1797), .C2(net_267) );
CLKBUF_X2 inst_5226 ( .A(net_5211), .Z(net_5212) );
DFF_X1 inst_3267 ( .QN(net_3097), .D(net_2914), .CK(net_5039) );
DFF_X2 inst_3205 ( .D(net_1368), .QN(net_52), .CK(net_5263) );
NAND2_X2 inst_1686 ( .A1(net_3219), .ZN(net_1986), .A2(net_154) );
CLKBUF_X2 inst_4909 ( .A(x1012), .Z(net_4895) );
CLKBUF_X2 inst_5310 ( .A(net_5132), .Z(net_5296) );
NAND2_X2 inst_1914 ( .A2(net_322), .ZN(net_288), .A1(net_225) );
CLKBUF_X2 inst_4996 ( .A(net_4981), .Z(net_4982) );
NAND2_X2 inst_1975 ( .ZN(net_3348), .A1(net_2527), .A2(net_2374) );
NAND2_X2 inst_1890 ( .A1(net_4004), .ZN(net_825), .A2(net_655) );
INV_X4 inst_2308 ( .ZN(net_1719), .A(net_828) );
AND2_X4 inst_4093 ( .ZN(net_2803), .A1(net_2689), .A2(net_1907) );
OAI21_X2 inst_612 ( .B2(net_4130), .A(net_2296), .ZN(net_2295), .B1(net_1036) );
CLKBUF_X2 inst_4806 ( .A(net_4791), .Z(net_4792) );
INV_X2 inst_2879 ( .A(net_389), .ZN(net_164) );
NAND2_X2 inst_1789 ( .ZN(net_1001), .A2(net_1000), .A1(net_950) );
NAND2_X2 inst_1692 ( .A1(net_3293), .ZN(net_1978), .A2(net_242) );
AOI21_X2 inst_3986 ( .A(net_3968), .ZN(net_841), .B1(net_840), .B2(net_691) );
INV_X4 inst_2338 ( .A(net_1264), .ZN(net_740) );
AOI22_X2 inst_3475 ( .B1(net_4039), .ZN(net_2676), .A1(net_2675), .A2(net_333), .B2(x90) );
INV_X2 inst_3017 ( .ZN(net_3417), .A(net_3413) );
OAI211_X2 inst_845 ( .C2(net_3214), .ZN(net_1212), .B(net_1024), .A(net_926), .C1(net_849) );
AOI22_X2 inst_3554 ( .A1(net_4059), .B1(net_4056), .ZN(net_1496), .A2(net_227), .B2(net_181) );
INV_X4 inst_2455 ( .ZN(net_686), .A(net_245) );
NAND3_X2 inst_1367 ( .ZN(net_3980), .A2(net_3979), .A3(net_3604), .A1(net_3603) );
CLKBUF_X2 inst_5198 ( .A(net_5183), .Z(net_5184) );
CLKBUF_X2 inst_4828 ( .A(net_4813), .Z(net_4814) );
NAND2_X2 inst_2016 ( .ZN(net_3648), .A1(net_3647), .A2(net_189) );
CLKBUF_X2 inst_5218 ( .A(net_5203), .Z(net_5204) );
AOI22_X2 inst_3687 ( .B1(net_4123), .A1(net_555), .ZN(net_491), .B2(net_222), .A2(net_141) );
CLKBUF_X2 inst_4860 ( .A(net_4831), .Z(net_4846) );
INV_X4 inst_2287 ( .ZN(net_1517), .A(net_950) );
NAND2_X4 inst_1460 ( .ZN(net_3871), .A2(net_3870), .A1(net_3868) );
NAND3_X2 inst_1344 ( .ZN(net_3421), .A2(net_3420), .A1(net_3419), .A3(net_2611) );
NOR3_X2 inst_885 ( .A2(net_3151), .ZN(net_2749), .A1(net_2748), .A3(net_2746) );
INV_X2 inst_2630 ( .ZN(net_2765), .A(net_2764) );
AOI21_X1 inst_4012 ( .B2(net_4145), .ZN(net_3624), .A(net_3623), .B1(net_1212) );
INV_X2 inst_3053 ( .ZN(net_3902), .A(net_3901) );
NAND2_X4 inst_1443 ( .A2(net_3870), .ZN(net_3780), .A1(net_3779) );
NOR2_X2 inst_1028 ( .A1(net_4184), .ZN(net_1597), .A2(net_1504) );
OAI221_X2 inst_393 ( .C2(net_3407), .ZN(net_2359), .B1(net_2357), .C1(net_2234), .A(net_1813), .B2(net_106) );
AOI21_X2 inst_3935 ( .B2(net_3859), .ZN(net_2540), .A(net_2380), .B1(net_2367) );
CLKBUF_X2 inst_4810 ( .A(net_4795), .Z(net_4796) );
AOI22_X2 inst_3610 ( .A1(net_4062), .B1(net_4057), .ZN(net_1407), .A2(net_205), .B2(net_193) );
INV_X2 inst_2999 ( .ZN(net_251), .A(net_78) );
NAND2_X2 inst_1813 ( .A1(net_1107), .ZN(net_938), .A2(net_640) );
XNOR2_X2 inst_92 ( .ZN(net_1273), .B(net_987), .A(net_814) );
OAI22_X2 inst_345 ( .A2(net_3978), .B2(net_3681), .ZN(net_3561), .B1(net_408), .A1(net_403) );
NAND3_X4 inst_1271 ( .ZN(net_3994), .A2(net_3644), .A1(net_283), .A3(net_257) );
DFF_X2 inst_3103 ( .QN(net_3124), .D(net_2862), .CK(net_4691) );
INV_X4 inst_2321 ( .ZN(net_990), .A(net_777) );
DFF_X1 inst_3304 ( .QN(net_3020), .D(net_2866), .CK(net_5210) );
CLKBUF_X2 inst_5305 ( .A(net_5290), .Z(net_5291) );
AND2_X4 inst_4156 ( .ZN(net_4106), .A2(net_3664), .A1(net_583) );
OR2_X4 inst_200 ( .A1(net_3179), .ZN(net_2919), .A2(net_2354) );
CLKBUF_X2 inst_4425 ( .A(net_4410), .Z(net_4411) );
CLKBUF_X2 inst_4461 ( .A(net_4446), .Z(net_4447) );
CLKBUF_X2 inst_4373 ( .A(net_4358), .Z(net_4359) );
XNOR2_X2 inst_57 ( .ZN(net_2184), .A(net_2160), .B(net_1508) );
CLKBUF_X2 inst_4723 ( .A(net_4684), .Z(net_4709) );
AOI22_X2 inst_3655 ( .A2(net_3029), .B2(net_3028), .ZN(net_634), .A1(net_458), .B1(net_457) );
NAND2_X2 inst_1750 ( .ZN(net_1366), .A1(net_1365), .A2(net_1230) );
CLKBUF_X2 inst_5242 ( .A(net_5227), .Z(net_5228) );
INV_X4 inst_2236 ( .ZN(net_2547), .A(net_1690) );
DFF_X1 inst_3368 ( .D(net_3749), .CK(net_4441), .Q(x285) );
NAND2_X2 inst_1553 ( .A1(net_2961), .ZN(net_2469), .A2(net_196) );
INV_X2 inst_2843 ( .A(net_1274), .ZN(net_913) );
NAND2_X2 inst_1888 ( .A1(net_416), .ZN(net_397), .A2(net_357) );
AND2_X4 inst_4130 ( .ZN(net_4059), .A2(net_3339), .A1(net_1188) );
DFF_X1 inst_3379 ( .D(net_2250), .CK(net_5157), .Q(x639) );
NAND2_X2 inst_1763 ( .A2(net_1394), .ZN(net_1236), .A1(net_35) );
NAND2_X2 inst_1635 ( .A1(net_4041), .ZN(net_2247), .A2(net_220) );
NAND3_X2 inst_1307 ( .A3(net_1613), .ZN(net_1145), .A1(net_1014), .A2(net_967) );
NAND2_X2 inst_1500 ( .ZN(net_2810), .A1(net_2766), .A2(net_2721) );
INV_X2 inst_2805 ( .A(net_3922), .ZN(net_919) );
NOR2_X2 inst_1094 ( .A2(net_3128), .ZN(net_317), .A1(net_276) );
AOI22_X2 inst_3499 ( .B1(net_3219), .ZN(net_2136), .A1(net_2134), .A2(net_552), .B2(net_551) );
AND2_X4 inst_4145 ( .ZN(net_4082), .A1(net_1613), .A2(net_619) );
INV_X2 inst_2932 ( .ZN(net_255), .A(net_79) );
CLKBUF_X2 inst_4590 ( .A(net_4575), .Z(net_4576) );
NOR3_X2 inst_893 ( .A3(net_3157), .A2(net_2384), .ZN(net_2130), .A1(net_2065) );
AOI22_X2 inst_3680 ( .B1(net_4124), .A1(net_509), .ZN(net_503), .B2(net_200), .A2(net_140) );
INV_X2 inst_3048 ( .ZN(net_3744), .A(net_3743) );
CLKBUF_X2 inst_4878 ( .A(net_4863), .Z(net_4864) );
CLKBUF_X2 inst_4854 ( .A(net_4839), .Z(net_4840) );
NAND2_X2 inst_1699 ( .A1(net_3505), .ZN(net_1835), .A2(net_1834) );
OAI211_X2 inst_851 ( .A(net_4153), .ZN(net_3320), .C2(net_3319), .C1(net_3318), .B(net_3317) );
OAI211_X2 inst_831 ( .ZN(net_1361), .C1(net_1359), .A(net_1234), .B(net_593), .C2(net_318) );
XNOR2_X2 inst_50 ( .ZN(net_2621), .A(net_2531), .B(net_294) );
DFF_X1 inst_3346 ( .D(net_2755), .CK(net_4349), .Q(x60) );
OAI21_X2 inst_569 ( .B2(net_3207), .B1(net_2849), .ZN(net_2843), .A(net_2481) );
INV_X2 inst_2992 ( .A(net_3042), .ZN(net_176) );
CLKBUF_X2 inst_4264 ( .A(net_4208), .Z(net_4250) );
INV_X4 inst_2589 ( .A(net_3711), .ZN(net_3671) );
NOR2_X2 inst_1080 ( .A1(net_3958), .ZN(net_838), .A2(net_605) );
INV_X4 inst_2374 ( .A(net_3670), .ZN(net_583) );
NOR2_X2 inst_1103 ( .A1(net_3161), .ZN(net_158), .A2(net_84) );
CLKBUF_X2 inst_4430 ( .A(net_4415), .Z(net_4416) );
CLKBUF_X2 inst_4329 ( .A(net_4314), .Z(net_4315) );
NAND2_X2 inst_1650 ( .ZN(net_2154), .A1(net_2153), .A2(net_321) );
OAI21_X2 inst_549 ( .B2(net_2907), .B1(net_2887), .ZN(net_2882), .A(net_2485) );
CLKBUF_X2 inst_4708 ( .A(net_4693), .Z(net_4694) );
CLKBUF_X2 inst_4220 ( .A(net_4205), .Z(net_4206) );
NAND2_X2 inst_1497 ( .ZN(net_2820), .A1(net_2772), .A2(net_2719) );
OAI21_X2 inst_522 ( .B1(net_3302), .ZN(net_2916), .B2(net_2915), .A(net_2436) );
CLKBUF_X2 inst_5202 ( .A(net_5134), .Z(net_5188) );
CLKBUF_X2 inst_5040 ( .A(net_4273), .Z(net_5026) );
CLKBUF_X2 inst_4439 ( .A(net_4424), .Z(net_4425) );
INV_X2 inst_2872 ( .ZN(net_254), .A(net_253) );
NOR2_X2 inst_1002 ( .A1(net_3772), .ZN(net_2230), .A2(net_1746) );
INV_X2 inst_2809 ( .ZN(net_840), .A(net_680) );
OAI21_X2 inst_478 ( .ZN(net_2971), .B1(net_2970), .B2(net_2969), .A(net_2416) );
DFF_X1 inst_3380 ( .D(net_2253), .Q(net_76), .CK(net_5296) );
INV_X2 inst_2673 ( .ZN(net_1901), .A(net_1900) );
NAND2_X2 inst_1618 ( .A1(net_2919), .ZN(net_2398), .A2(net_187) );
CLKBUF_X2 inst_5062 ( .A(net_4344), .Z(net_5048) );
INV_X8 inst_2126 ( .ZN(net_509), .A(net_351) );
OAI211_X2 inst_804 ( .C1(net_2190), .ZN(net_2123), .C2(net_2122), .A(net_2013), .B(net_2000) );
DFF_X1 inst_3290 ( .QN(net_3046), .D(net_2897), .CK(net_4712) );
XOR2_X2 inst_13 ( .A(net_4074), .B(net_1148), .Z(net_1140) );
INV_X4 inst_2584 ( .ZN(net_3629), .A(net_3211) );
CLKBUF_X2 inst_4931 ( .A(net_4916), .Z(net_4917) );
AOI22_X2 inst_3600 ( .A1(net_4063), .B1(net_4058), .ZN(net_1417), .A2(net_559), .B2(net_558) );
INV_X2 inst_2765 ( .ZN(net_2165), .A(net_951) );
OAI211_X2 inst_799 ( .C1(net_2190), .ZN(net_2188), .C2(net_2187), .B(net_2056), .A(net_2009) );
AOI22_X2 inst_3481 ( .B1(net_4038), .A1(net_2675), .ZN(net_2656), .A2(net_984), .B2(net_402) );
OR2_X4 inst_219 ( .ZN(net_949), .A1(net_948), .A2(net_908) );
OAI21_X2 inst_738 ( .B2(net_3124), .ZN(net_310), .A(net_309), .B1(net_164) );
OAI21_X2 inst_719 ( .B1(net_3929), .ZN(net_724), .A(net_669), .B2(net_334) );
AND2_X4 inst_4166 ( .ZN(net_4120), .A2(net_404), .A1(net_248) );
INV_X2 inst_2755 ( .ZN(net_1003), .A(net_1002) );
CLKBUF_X2 inst_4881 ( .A(net_4866), .Z(net_4867) );
NAND2_X2 inst_1819 ( .ZN(net_871), .A1(net_817), .A2(net_766) );
AOI221_X2 inst_3868 ( .B2(net_3118), .B1(net_2020), .C1(net_2019), .ZN(net_1938), .A(net_1937), .C2(x232) );
OR2_X2 inst_255 ( .A2(net_4119), .ZN(net_1161), .A1(net_932) );
INV_X2 inst_2726 ( .A(net_2212), .ZN(net_2042) );
OAI21_X4 inst_453 ( .ZN(net_2160), .B1(net_2043), .A(net_1595), .B2(net_1505) );
NOR2_X2 inst_1134 ( .A1(net_3722), .ZN(net_3666), .A2(net_3665) );
OAI21_X2 inst_493 ( .B1(net_3394), .B2(net_2965), .ZN(net_2949), .A(net_2442) );
INV_X2 inst_2674 ( .ZN(net_1899), .A(net_1898) );
INV_X4 inst_2204 ( .A(net_3511), .ZN(net_2364) );
XOR2_X2 inst_23 ( .Z(net_4092), .A(net_681), .B(net_387) );
NOR2_X2 inst_1113 ( .A2(net_3515), .A1(net_3405), .ZN(net_3332) );
NAND2_X2 inst_1822 ( .A2(net_3900), .ZN(net_1008), .A1(net_902) );
NAND2_X2 inst_1609 ( .A1(net_2967), .ZN(net_2407), .A2(net_471) );
AND2_X4 inst_4105 ( .A1(net_4128), .A2(net_3163), .ZN(net_457) );
AOI222_X1 inst_3790 ( .B1(net_4115), .C1(net_1882), .A1(net_1385), .ZN(net_1056), .A2(net_894), .B2(net_844), .C2(net_122) );
AND2_X2 inst_4206 ( .ZN(net_3446), .A2(net_2518), .A1(net_1051) );
AOI22_X2 inst_3546 ( .B1(net_4054), .A1(net_1578), .ZN(net_1576), .A2(net_379), .B2(net_238) );
OAI221_X2 inst_408 ( .B2(net_4071), .C2(net_3123), .ZN(net_1666), .B1(net_1615), .A(net_816), .C1(net_437) );
NOR2_X2 inst_1144 ( .ZN(net_3893), .A1(net_3892), .A2(net_3867) );
CLKBUF_X2 inst_5165 ( .A(net_5132), .Z(net_5151) );
CLKBUF_X2 inst_4701 ( .A(net_4686), .Z(net_4687) );
OAI211_X2 inst_812 ( .C2(net_3755), .B(net_1628), .C1(net_1627), .ZN(net_1626), .A(net_1554) );
INV_X4 inst_2568 ( .ZN(net_3541), .A(net_3540) );
INV_X4 inst_2295 ( .A(net_1261), .ZN(net_898) );
OR3_X2 inst_179 ( .A2(net_4075), .ZN(net_2561), .A1(net_2528), .A3(net_2522) );
NAND2_X2 inst_1730 ( .A1(net_1556), .ZN(net_1555), .A2(x800) );
AOI221_X2 inst_3799 ( .ZN(net_2782), .C1(net_2781), .B1(net_2775), .A(net_2685), .C2(net_1699), .B2(net_292) );
AOI221_X2 inst_3814 ( .C1(net_3445), .A(net_2642), .ZN(net_2586), .B1(net_2584), .C2(net_2583), .B2(net_1326) );
AOI222_X2 inst_3734 ( .A2(net_1826), .ZN(net_1765), .A1(net_1387), .B2(net_991), .C2(net_920), .B1(net_624), .C1(net_580) );
AOI22_X2 inst_3532 ( .B1(net_2625), .ZN(net_1839), .A1(net_1838), .A2(net_1837), .B2(net_184) );
INV_X2 inst_3028 ( .ZN(net_3506), .A(net_3505) );
INV_X4 inst_2191 ( .ZN(net_2383), .A(net_2382) );
XNOR2_X2 inst_76 ( .A(net_3229), .ZN(net_1448), .B(net_1447) );
CLKBUF_X2 inst_5296 ( .A(net_5281), .Z(net_5282) );
AOI221_X2 inst_3854 ( .B1(net_3736), .ZN(net_2058), .C1(net_2049), .C2(net_1902), .A(net_1854), .B2(net_240) );
NOR2_X2 inst_1127 ( .A2(net_4155), .A1(net_3597), .ZN(net_3474) );
AOI22_X2 inst_3514 ( .B1(net_4045), .ZN(net_1957), .A1(net_1955), .A2(net_265), .B2(net_228) );
OR3_X4 inst_172 ( .ZN(net_2523), .A2(net_988), .A1(net_843), .A3(net_526) );
OAI221_X2 inst_362 ( .ZN(net_2783), .A(net_2726), .C1(net_2565), .B1(net_2561), .B2(net_2051), .C2(net_1537) );
CLKBUF_X2 inst_4366 ( .A(net_4351), .Z(net_4352) );
NAND2_X2 inst_1530 ( .A1(net_3208), .ZN(net_2492), .A2(net_558) );
OAI22_X4 inst_277 ( .B1(net_3871), .ZN(net_3216), .A1(net_3177), .B2(net_3002), .A2(net_3001) );
NAND2_X2 inst_1510 ( .ZN(net_2735), .A1(net_2624), .A2(net_2623) );
XNOR2_X2 inst_83 ( .ZN(net_1139), .A(net_1138), .B(net_1137) );
XNOR2_X2 inst_121 ( .ZN(net_4137), .B(net_322), .A(net_192) );
OAI22_X2 inst_306 ( .A2(net_2665), .A1(net_1543), .B1(net_1542), .ZN(net_1534), .B2(net_130) );
AND2_X4 inst_4186 ( .ZN(net_4180), .A2(net_4179), .A1(net_4178) );
NOR2_X2 inst_1065 ( .A2(net_923), .ZN(net_897), .A1(net_853) );
AND2_X4 inst_4119 ( .A2(net_4050), .ZN(net_4042), .A1(net_1959) );
CLKBUF_X2 inst_4332 ( .A(net_4317), .Z(net_4318) );
DFF_X1 inst_3386 ( .D(net_1805), .QN(net_39), .CK(net_5002) );
HA_X1 inst_3095 ( .S(net_1035), .CO(net_875), .B(net_874), .A(net_676) );
NAND2_X2 inst_1715 ( .A1(net_3492), .ZN(net_1785), .A2(net_1640) );
SDFF_X2 inst_140 ( .SE(net_2625), .D(net_2336), .SI(net_98), .Q(net_98), .CK(net_4954) );
OR2_X2 inst_267 ( .ZN(net_3355), .A2(net_3354), .A1(net_3352) );
INV_X2 inst_2824 ( .ZN(net_638), .A(net_517) );
OAI21_X2 inst_716 ( .B1(net_4125), .ZN(net_776), .A(net_775), .B2(net_644) );
CLKBUF_X2 inst_4671 ( .A(net_4656), .Z(net_4657) );
AOI22_X2 inst_3594 ( .A1(net_4059), .B1(net_4057), .ZN(net_1423), .B2(net_222), .A2(net_202) );
AND2_X4 inst_4174 ( .ZN(net_4128), .A2(net_3162), .A1(net_223) );
NAND2_X2 inst_1906 ( .ZN(net_314), .A2(net_303), .A1(net_198) );
OAI21_X2 inst_530 ( .B2(net_2963), .B1(net_2923), .ZN(net_2904), .A(net_2454) );
OAI211_X2 inst_792 ( .C2(net_2876), .ZN(net_2701), .A(net_2622), .C1(net_2621), .B(net_2139) );
NAND2_X2 inst_2024 ( .ZN(net_3719), .A2(net_3715), .A1(net_3682) );
DFF_X2 inst_3124 ( .D(net_2646), .QN(net_112), .CK(net_4396) );
INV_X2 inst_2952 ( .A(net_3101), .ZN(net_161) );
NAND3_X2 inst_1353 ( .ZN(net_3688), .A1(net_3687), .A3(net_3309), .A2(net_3308) );
INV_X4 inst_2502 ( .ZN(net_2037), .A(net_289) );
INV_X4 inst_2216 ( .ZN(net_2235), .A(net_2137) );
OAI21_X2 inst_769 ( .ZN(net_3966), .A(net_3960), .B1(net_1212), .B2(net_851) );
OR3_X4 inst_174 ( .ZN(net_627), .A3(net_389), .A2(net_344), .A1(net_309) );
NAND4_X2 inst_1200 ( .ZN(net_1767), .A3(net_1477), .A4(net_1476), .A1(net_1411), .A2(net_1410) );
INV_X2 inst_2988 ( .A(net_292), .ZN(net_142) );
CLKBUF_X2 inst_4494 ( .A(net_4479), .Z(net_4480) );
MUX2_X2 inst_2105 ( .S(net_2917), .A(net_2573), .Z(net_2572), .B(net_230) );
NAND4_X2 inst_1199 ( .ZN(net_1674), .A3(net_1495), .A4(net_1494), .A1(net_1428), .A2(net_1427) );
XOR2_X2 inst_5 ( .A(net_3492), .Z(net_1695), .B(net_1694) );
AOI21_X2 inst_3974 ( .ZN(net_1177), .A(net_1176), .B2(net_1011), .B1(net_846) );
INV_X2 inst_3021 ( .A(net_3634), .ZN(net_3440) );
OAI21_X2 inst_729 ( .A(net_629), .B1(net_628), .ZN(net_581), .B2(net_333) );
INV_X8 inst_2157 ( .A(net_3898), .ZN(net_3618) );
NAND2_X2 inst_1662 ( .ZN(net_2101), .A1(net_2099), .A2(net_241) );
CLKBUF_X2 inst_4553 ( .A(net_4538), .Z(net_4539) );
INV_X2 inst_2783 ( .ZN(net_803), .A(net_757) );
OR2_X4 inst_213 ( .A1(net_3781), .ZN(net_1815), .A2(net_711) );
OAI21_X2 inst_604 ( .B2(net_3486), .ZN(net_2334), .B1(net_2330), .A(net_1946) );
OR2_X4 inst_205 ( .ZN(net_2915), .A2(net_2354), .A1(net_2350) );
NAND2_X2 inst_1645 ( .A1(net_3190), .A2(net_3181), .ZN(net_2170) );
NAND3_X2 inst_1285 ( .ZN(net_2262), .A1(net_2204), .A3(net_1957), .A2(net_1916) );
OAI221_X2 inst_380 ( .C2(net_4088), .B2(net_2733), .C1(net_2686), .ZN(net_2652), .A(net_2588), .B1(net_2538) );
AND4_X2 inst_4057 ( .A3(net_2737), .ZN(net_1380), .A1(net_1221), .A2(net_977), .A4(net_314) );
NAND4_X2 inst_1179 ( .ZN(net_2854), .A2(net_2823), .A1(net_2812), .A3(net_2793), .A4(net_2753) );
AOI22_X2 inst_3722 ( .A2(net_4145), .ZN(net_3622), .B2(net_3621), .B1(net_845), .A1(net_743) );
OAI22_X2 inst_292 ( .A1(net_3781), .B1(net_1884), .ZN(net_1811), .A2(net_1810), .B2(net_389) );
CLKBUF_X2 inst_4311 ( .A(net_4296), .Z(net_4297) );
AOI22_X2 inst_3650 ( .ZN(net_736), .A1(net_735), .B1(net_734), .A2(net_458), .B2(net_457) );
NAND2_X2 inst_2012 ( .ZN(net_3593), .A2(net_3592), .A1(net_3591) );
AOI221_X2 inst_3911 ( .A(net_4113), .ZN(net_701), .B1(net_686), .C2(net_393), .B2(net_329), .C1(net_245) );
NAND2_X2 inst_1515 ( .ZN(net_2537), .A1(net_2367), .A2(net_2195) );
CLKBUF_X2 inst_4970 ( .A(net_4955), .Z(net_4956) );
OAI21_X2 inst_706 ( .ZN(net_873), .A(net_769), .B2(net_768), .B1(net_206) );
CLKBUF_X2 inst_5173 ( .A(net_5158), .Z(net_5159) );
NAND2_X2 inst_1782 ( .A2(net_3559), .ZN(net_2127), .A1(net_1183) );
INV_X2 inst_2951 ( .ZN(net_209), .A(net_106) );
CLKBUF_X2 inst_4472 ( .A(net_4225), .Z(net_4458) );
AOI221_X2 inst_3890 ( .B1(net_4027), .C1(net_3111), .A(net_2525), .ZN(net_1395), .B2(net_1394), .C2(net_1393) );
OAI211_X2 inst_839 ( .C1(net_1359), .ZN(net_1349), .A(net_1238), .B(net_671), .C2(net_302) );
NOR2_X2 inst_1015 ( .A1(net_1738), .ZN(net_1736), .A2(net_1632) );
CLKBUF_X2 inst_4734 ( .A(net_4719), .Z(net_4720) );
OR2_X4 inst_240 ( .A1(net_3959), .A2(net_3720), .ZN(net_3681) );
AOI21_X2 inst_3966 ( .B2(net_3968), .B1(net_1884), .ZN(net_1389), .A(net_1388) );
XNOR2_X2 inst_110 ( .ZN(net_538), .A(net_309), .B(net_47) );
AOI221_X2 inst_3899 ( .B2(net_4107), .B1(net_3561), .ZN(net_1209), .C2(net_1011), .C1(net_961), .A(net_864) );
NAND2_X2 inst_2047 ( .ZN(net_3860), .A2(net_3859), .A1(net_3857) );
DFF_X2 inst_3213 ( .D(net_807), .QN(net_327), .CK(net_4794) );
CLKBUF_X2 inst_4545 ( .A(net_4530), .Z(net_4531) );
AOI221_X2 inst_3825 ( .B1(net_3469), .B2(net_3147), .ZN(net_2536), .C1(net_2534), .A(net_2340), .C2(net_252) );
INV_X4 inst_2535 ( .A(net_3877), .ZN(net_3343) );
XNOR2_X2 inst_99 ( .A(net_729), .ZN(net_653), .B(net_387) );
CLKBUF_X2 inst_4569 ( .A(net_4554), .Z(net_4555) );
NAND2_X2 inst_1661 ( .A2(net_4019), .ZN(net_2102), .A1(net_2099) );
CLKBUF_X2 inst_4384 ( .A(net_4369), .Z(net_4370) );
NAND2_X2 inst_2059 ( .ZN(net_3908), .A1(net_3187), .A2(net_186) );
CLKBUF_X2 inst_4480 ( .A(net_4237), .Z(net_4466) );
INV_X2 inst_2949 ( .A(net_3047), .ZN(net_212) );
INV_X4 inst_2414 ( .ZN(net_276), .A(net_262) );
OAI22_X2 inst_283 ( .A1(net_3883), .A2(net_3859), .B2(net_3858), .ZN(net_2372), .B1(net_2371) );
OAI22_X2 inst_311 ( .B1(net_4077), .B2(net_3789), .ZN(net_1774), .A1(net_1050), .A2(net_877) );
DFF_X1 inst_3406 ( .Q(net_4028), .D(net_1396), .CK(net_4504) );
INV_X4 inst_2519 ( .A(net_3391), .ZN(net_3220) );
NAND2_X2 inst_1597 ( .A1(net_2925), .ZN(net_2421), .A2(net_169) );
AOI22_X2 inst_3502 ( .ZN(net_2057), .A1(net_1903), .B2(net_1719), .A2(net_1717), .B1(net_1621) );
INV_X4 inst_2203 ( .A(net_3248), .ZN(net_2543) );
AOI22_X2 inst_3473 ( .A2(net_3149), .B2(net_3113), .A1(net_2775), .B1(net_2722), .ZN(net_2713) );
OAI221_X2 inst_431 ( .B2(net_3620), .A(net_1007), .ZN(net_905), .B1(net_904), .C2(net_903), .C1(net_638) );
OAI222_X2 inst_348 ( .A2(net_2815), .ZN(net_1819), .A1(net_1818), .B1(net_1817), .C1(net_1816), .C2(net_289), .B2(net_107) );
NAND2_X2 inst_1930 ( .A2(net_4011), .ZN(net_3193), .A1(net_3186) );
NOR3_X2 inst_889 ( .ZN(net_2781), .A1(net_2528), .A2(net_1168), .A3(net_1124) );
OAI21_X2 inst_577 ( .B2(net_2915), .B1(net_2803), .ZN(net_2801), .A(net_2448) );
CLKBUF_X2 inst_5123 ( .A(net_5108), .Z(net_5109) );
INV_X2 inst_2686 ( .A(net_3407), .ZN(net_1888) );
CLKBUF_X2 inst_4975 ( .A(net_4960), .Z(net_4961) );
AOI222_X1 inst_3740 ( .C1(net_4039), .B1(net_4038), .ZN(net_2617), .A1(net_2594), .A2(net_2346), .B2(net_1523), .C2(x105) );
INV_X4 inst_2293 ( .ZN(net_2122), .A(net_906) );
CLKBUF_X2 inst_5188 ( .A(net_5173), .Z(net_5174) );
INV_X4 inst_2379 ( .A(net_3438), .ZN(net_923) );
NAND3_X2 inst_1364 ( .ZN(net_3924), .A3(net_3923), .A2(net_3627), .A1(net_963) );
AOI21_X2 inst_3938 ( .ZN(net_2330), .B1(net_2283), .B2(net_2144), .A(net_1778) );
INV_X2 inst_2865 ( .ZN(net_991), .A(net_47) );
OAI21_X2 inst_645 ( .ZN(net_1949), .B1(net_1912), .A(net_1873), .B2(net_1292) );
CLKBUF_X2 inst_4916 ( .A(net_4901), .Z(net_4902) );
CLKBUF_X2 inst_4891 ( .A(net_4224), .Z(net_4877) );
AOI22_X2 inst_3571 ( .A1(net_4059), .B1(net_4056), .ZN(net_1479), .B2(net_468), .A2(net_453) );
INV_X2 inst_3041 ( .A(net_3711), .ZN(net_3673) );
INV_X2 inst_2719 ( .ZN(net_2669), .A(net_2551) );
INV_X4 inst_2352 ( .ZN(net_618), .A(net_513) );
OR2_X2 inst_269 ( .A2(net_3447), .ZN(net_3426), .A1(net_1606) );
NAND4_X2 inst_1190 ( .ZN(net_1823), .A3(net_1493), .A4(net_1492), .A1(net_1426), .A2(net_1425) );
OAI221_X2 inst_444 ( .B1(net_4159), .ZN(net_3696), .B2(net_3407), .C1(net_2328), .A(net_1935), .C2(net_1447) );
INV_X4 inst_2544 ( .A(net_3674), .ZN(net_3667) );
OAI21_X2 inst_514 ( .B1(net_3278), .ZN(net_2928), .B2(net_2912), .A(net_2449) );
CLKBUF_X2 inst_4905 ( .A(net_4890), .Z(net_4891) );
NAND2_X2 inst_1541 ( .A1(net_3207), .ZN(net_2481), .A2(net_160) );
CLKBUF_X2 inst_4236 ( .A(net_4221), .Z(net_4222) );
OAI21_X2 inst_685 ( .B1(net_3228), .ZN(net_1310), .A(net_1259), .B2(net_260) );
XNOR2_X2 inst_63 ( .A(net_3264), .ZN(net_1902), .B(net_1526) );
XNOR2_X2 inst_119 ( .ZN(net_4074), .A(net_701), .B(net_402) );
DFF_X2 inst_3181 ( .D(net_1811), .QN(net_389), .CK(net_4837) );
NOR2_X4 inst_939 ( .ZN(net_3227), .A1(net_915), .A2(net_877) );
CLKBUF_X2 inst_4656 ( .A(net_4641), .Z(net_4642) );
NAND4_X2 inst_1233 ( .ZN(net_1637), .A4(net_550), .A3(net_545), .A1(net_503), .A2(net_473) );
INV_X2 inst_2924 ( .A(net_3002), .ZN(net_160) );
NOR2_X2 inst_1019 ( .A1(net_1815), .ZN(net_1812), .A2(net_1655) );
NAND2_X2 inst_2006 ( .A2(net_3859), .ZN(net_3534), .A1(net_3533) );
NAND2_X2 inst_1827 ( .ZN(net_779), .A1(net_778), .A2(net_777) );
OAI21_X2 inst_742 ( .B1(net_3611), .B2(net_3516), .A(net_3344), .ZN(net_3286) );
OAI221_X2 inst_427 ( .B2(net_4133), .B1(net_3733), .ZN(net_1061), .A(net_953), .C2(net_904), .C1(net_680) );
AOI221_X2 inst_3840 ( .ZN(net_2204), .B2(net_2203), .C1(net_2202), .A(net_2074), .C2(net_2037), .B1(net_1906) );
INV_X4 inst_2619 ( .A(net_3991), .ZN(net_3923) );
AOI22_X2 inst_3465 ( .B2(net_4026), .ZN(net_2753), .B1(net_2752), .A1(net_2750), .A2(net_361) );
NAND2_X2 inst_2033 ( .ZN(net_3768), .A1(net_3168), .A2(net_3108) );
INV_X8 inst_2144 ( .A(net_3871), .ZN(net_3219) );
CLKBUF_X2 inst_4481 ( .A(net_4466), .Z(net_4467) );
INV_X4 inst_2559 ( .ZN(net_3505), .A(net_3503) );
SDFF_X2 inst_138 ( .D(net_3290), .SE(net_2625), .SI(net_96), .Q(net_96), .CK(net_4957) );
CLKBUF_X2 inst_5289 ( .A(net_5274), .Z(net_5275) );
NAND2_X2 inst_1955 ( .ZN(net_3284), .A2(net_3186), .A1(net_172) );
INV_X2 inst_2810 ( .ZN(net_669), .A(net_407) );
AOI22_X2 inst_3618 ( .B1(net_3134), .ZN(net_1640), .B2(net_1071), .A1(net_1044), .A2(net_1036) );
NAND3_X4 inst_1269 ( .A3(net_4149), .ZN(net_3951), .A1(net_3950), .A2(net_3790) );
CLKBUF_X2 inst_4944 ( .A(net_4929), .Z(net_4930) );
NOR3_X2 inst_899 ( .A2(net_4072), .A3(net_3935), .ZN(net_1187), .A1(net_1054) );
OAI22_X2 inst_312 ( .A1(net_2384), .B1(net_1274), .ZN(net_1218), .A2(net_1217), .B2(net_773) );
DFF_X1 inst_3241 ( .QN(net_3045), .D(net_2957), .CK(net_5182) );
INV_X2 inst_2704 ( .ZN(net_1671), .A(net_1670) );
NAND2_X2 inst_1620 ( .A1(net_2917), .ZN(net_2396), .A2(net_166) );
CLKBUF_X2 inst_4958 ( .A(net_4487), .Z(net_4944) );
OAI22_X2 inst_309 ( .B2(net_3102), .B1(net_1884), .ZN(net_1303), .A1(net_1159), .A2(net_1090) );
DFF_X1 inst_3416 ( .D(net_1353), .Q(net_33), .CK(net_4334) );
OAI222_X2 inst_347 ( .A2(net_2815), .ZN(net_1997), .A1(net_1996), .B1(net_1817), .C1(net_1816), .C2(net_505), .B2(net_108) );
INV_X8 inst_2149 ( .ZN(net_3293), .A(net_3292) );
OAI21_X2 inst_755 ( .ZN(net_3707), .A(net_3706), .B2(net_3407), .B1(net_2228) );
CLKBUF_X2 inst_5001 ( .A(net_4590), .Z(net_4987) );
NAND2_X2 inst_1724 ( .A2(net_3490), .ZN(net_1594), .A1(net_1593) );
CLKBUF_X2 inst_4505 ( .A(net_4485), .Z(net_4491) );
INV_X4 inst_2610 ( .A(net_3823), .ZN(net_3822) );
INV_X2 inst_2694 ( .ZN(net_1716), .A(net_1680) );
NOR2_X2 inst_1043 ( .A1(net_1196), .ZN(net_1182), .A2(net_1116) );
AOI211_X2 inst_4030 ( .B(net_3916), .A(net_3656), .C1(net_889), .ZN(net_708), .C2(net_607) );
NAND2_X2 inst_1968 ( .ZN(net_3335), .A1(net_3280), .A2(net_493) );
CLKBUF_X2 inst_4817 ( .A(net_4802), .Z(net_4803) );
CLKBUF_X2 inst_4456 ( .A(net_4300), .Z(net_4442) );
CLKBUF_X2 inst_4926 ( .A(net_4911), .Z(net_4912) );
AND3_X4 inst_4078 ( .ZN(net_4098), .A3(net_3913), .A1(net_432), .A2(net_418) );
AND3_X4 inst_4067 ( .A1(net_4194), .ZN(net_1321), .A3(net_1254), .A2(net_1133) );
NAND2_X2 inst_1792 ( .ZN(net_975), .A1(net_974), .A2(net_145) );
CLKBUF_X2 inst_4426 ( .A(net_4206), .Z(net_4412) );
NAND3_X2 inst_1330 ( .A3(net_4125), .A1(net_3523), .ZN(net_711), .A2(net_407) );
CLKBUF_X2 inst_4571 ( .A(net_4556), .Z(net_4557) );
CLKBUF_X2 inst_5111 ( .A(net_5096), .Z(net_5097) );
AOI21_X4 inst_3928 ( .B2(net_3600), .ZN(net_3588), .B1(net_3587), .A(net_2186) );
DFF_X1 inst_3353 ( .D(net_2629), .QN(net_41), .CK(net_4338) );
NAND2_X2 inst_1898 ( .ZN(net_394), .A2(net_307), .A1(net_293) );
AOI22_X2 inst_3634 ( .ZN(net_932), .B1(net_931), .A1(net_869), .A2(net_401), .B2(net_252) );
AOI221_X2 inst_3883 ( .C1(net_3782), .B1(net_1882), .C2(net_1834), .ZN(net_1802), .A(net_1648), .B2(net_84) );
AOI211_X2 inst_4017 ( .ZN(net_1775), .A(net_1774), .B(net_1682), .C2(net_1383), .C1(net_1071) );
NAND2_X2 inst_1714 ( .ZN(net_2298), .A2(net_1568), .A1(net_1566) );
CLKBUF_X2 inst_4598 ( .A(net_4583), .Z(net_4584) );
CLKBUF_X2 inst_4681 ( .A(net_4548), .Z(net_4667) );
CLKBUF_X2 inst_5135 ( .A(net_5120), .Z(net_5121) );
CLKBUF_X2 inst_4777 ( .A(net_4710), .Z(net_4763) );
NAND2_X2 inst_1496 ( .ZN(net_2821), .A1(net_2776), .A2(net_2725) );
CLKBUF_X2 inst_4297 ( .A(net_4282), .Z(net_4283) );
NAND2_X2 inst_1565 ( .A1(net_2963), .ZN(net_2456), .A2(net_453) );
NOR2_X4 inst_924 ( .A2(net_3400), .A1(net_3236), .ZN(net_2280) );
CLKBUF_X2 inst_5095 ( .A(net_4483), .Z(net_5081) );
OAI22_X2 inst_287 ( .A1(net_3781), .ZN(net_1885), .B1(net_1884), .A2(net_1761), .B2(net_270) );
OAI221_X2 inst_426 ( .A(net_3731), .ZN(net_1130), .C1(net_1129), .B2(net_887), .B1(net_798), .C2(net_721) );
DFF_X2 inst_3145 ( .QN(net_3105), .D(net_2508), .CK(net_5150) );
INV_X4 inst_2577 ( .ZN(net_3595), .A(net_3592) );
CLKBUF_X2 inst_5144 ( .A(net_4572), .Z(net_5130) );
OAI21_X2 inst_648 ( .B2(net_3338), .ZN(net_1926), .A(net_1839), .B1(net_1838) );
HA_X1 inst_3094 ( .CO(net_1085), .S(net_1038), .A(net_820), .B(net_229) );
INV_X2 inst_2903 ( .A(net_3030), .ZN(net_233) );
OR2_X2 inst_270 ( .ZN(net_3737), .A1(net_3428), .A2(net_3229) );
AND4_X4 inst_4045 ( .ZN(net_4053), .A1(net_3228), .A4(net_1386), .A2(net_1115), .A3(net_1111) );
NAND2_X2 inst_1901 ( .ZN(net_353), .A1(net_350), .A2(net_144) );
CLKBUF_X2 inst_4302 ( .A(net_4287), .Z(net_4288) );
CLKBUF_X2 inst_4890 ( .A(net_4774), .Z(net_4876) );
NOR2_X2 inst_984 ( .ZN(net_2750), .A1(net_2609), .A2(net_1270) );
AOI221_X2 inst_3804 ( .C1(net_2781), .B1(net_2775), .ZN(net_2766), .A(net_2639), .B2(net_2637), .C2(net_206) );
NAND2_X2 inst_2064 ( .ZN(net_3941), .A2(net_3109), .A1(net_352) );
AND2_X4 inst_4104 ( .ZN(net_778), .A1(net_413), .A2(net_412) );
INV_X4 inst_2266 ( .ZN(net_1232), .A(net_1049) );
NAND3_X2 inst_1292 ( .A2(net_4121), .A1(net_4043), .ZN(net_2206), .A3(net_2180) );
INV_X4 inst_2552 ( .ZN(net_3471), .A(net_2126) );
CLKBUF_X2 inst_5014 ( .A(net_4999), .Z(net_5000) );
NAND2_X2 inst_1963 ( .ZN(net_3316), .A1(net_3315), .A2(net_330) );
OAI21_X2 inst_631 ( .B2(net_2525), .ZN(net_2231), .A(net_2119), .B1(net_2118) );
NOR2_X2 inst_1056 ( .A2(net_4076), .ZN(net_1108), .A1(net_661) );
CLKBUF_X2 inst_4247 ( .A(net_4232), .Z(net_4233) );
AOI22_X2 inst_3648 ( .A1(net_1011), .ZN(net_798), .B1(net_432), .A2(net_408), .B2(net_403) );
AOI22_X2 inst_3674 ( .A2(net_571), .B2(net_570), .ZN(net_547), .B1(net_235), .A1(net_232) );
INV_X4 inst_2514 ( .A(net_3886), .ZN(net_3175) );
CLKBUF_X2 inst_4988 ( .A(net_4973), .Z(net_4974) );
AOI21_X2 inst_3995 ( .ZN(net_3296), .B1(net_3295), .B2(net_2578), .A(net_2343) );
NOR2_X2 inst_1128 ( .A2(net_3568), .ZN(net_3525), .A1(net_434) );
CLKBUF_X2 inst_4211 ( .A(x1012), .Z(net_4197) );
AOI222_X1 inst_3759 ( .C1(net_4045), .ZN(net_2004), .B1(net_1968), .A1(net_1849), .A2(net_1836), .B2(net_1511), .C2(net_179) );
DFF_X1 inst_3222 ( .QN(net_3058), .D(net_2974), .CK(net_4566) );
CLKBUF_X2 inst_5074 ( .A(net_5059), .Z(net_5060) );
NAND2_X2 inst_1745 ( .ZN(net_1465), .A2(net_1386), .A1(net_1336) );
AOI221_X2 inst_3831 ( .B1(net_4189), .C1(net_2534), .ZN(net_2368), .A(net_2290), .B2(net_378), .C2(net_280) );
NAND2_X2 inst_2079 ( .ZN(net_4168), .A1(net_3736), .A2(net_73) );
XNOR2_X2 inst_102 ( .ZN(net_681), .A(net_322), .B(net_49) );
INV_X4 inst_2527 ( .ZN(net_3270), .A(net_3130) );
DFF_X1 inst_3277 ( .QN(net_3035), .D(net_2916), .CK(net_5014) );
AND3_X4 inst_4070 ( .A2(net_3819), .ZN(net_3619), .A3(net_3196), .A1(net_262) );
INV_X2 inst_2786 ( .ZN(net_2147), .A(net_800) );
NAND4_X2 inst_1224 ( .A4(net_4125), .A1(net_4097), .A3(net_3656), .ZN(net_1046), .A2(net_717) );
AOI221_X2 inst_3905 ( .A(net_4091), .B2(net_3559), .ZN(net_1019), .C2(net_1018), .B1(net_924), .C1(net_799) );
NAND2_X2 inst_1924 ( .A1(net_3817), .ZN(net_3182), .A2(net_183) );
NOR2_X1 inst_1170 ( .A2(net_4150), .ZN(net_3475), .A1(net_3271) );
INV_X4 inst_2596 ( .ZN(net_3736), .A(net_3735) );
INV_X2 inst_3022 ( .ZN(net_3442), .A(net_2303) );
OAI21_X2 inst_680 ( .B1(net_3228), .B2(net_3153), .ZN(net_1440), .A(net_1307) );
CLKBUF_X2 inst_4748 ( .A(net_4733), .Z(net_4734) );
OAI211_X2 inst_785 ( .C2(net_2778), .ZN(net_2763), .C1(net_2732), .B(net_2672), .A(net_2650) );
INV_X4 inst_2362 ( .A(net_1173), .ZN(net_593) );
DFF_X1 inst_3299 ( .D(net_3748), .Q(net_3745), .QN(net_67), .CK(net_4284) );
AND2_X4 inst_4160 ( .ZN(net_4111), .A2(net_3912), .A1(net_3900) );
DFF_X1 inst_3255 ( .QN(net_3087), .D(net_2950), .CK(net_4603) );
INV_X2 inst_2856 ( .ZN(net_2033), .A(net_260) );
NOR2_X4 inst_961 ( .ZN(net_3776), .A1(net_3346), .A2(net_3345) );
NAND2_X2 inst_1590 ( .A1(net_2972), .ZN(net_2428), .A2(net_781) );
INV_X4 inst_2318 ( .A(net_767), .ZN(net_747) );
OAI221_X2 inst_399 ( .C2(net_3407), .B1(net_2328), .ZN(net_2285), .C1(net_2208), .A(net_1936), .B2(net_70) );
CLKBUF_X2 inst_5103 ( .A(net_4830), .Z(net_5089) );
OAI21_X2 inst_527 ( .B1(net_3302), .ZN(net_2908), .B2(net_2907), .A(net_2483) );
AOI21_X2 inst_3957 ( .ZN(net_1631), .B1(net_1593), .A(net_1047), .B2(net_127) );
AOI22_X2 inst_3567 ( .A1(net_4059), .B1(net_4056), .ZN(net_1483), .B2(net_493), .A2(net_470) );
OR2_X4 inst_226 ( .ZN(net_902), .A1(net_692), .A2(net_691) );
NAND4_X2 inst_1180 ( .ZN(net_2697), .A2(net_2537), .A1(net_2341), .A3(net_2318), .A4(net_2276) );
AOI211_X2 inst_4020 ( .A(net_4091), .ZN(net_1599), .B(net_1512), .C1(net_1015), .C2(net_408) );
OAI221_X2 inst_414 ( .C1(net_4093), .ZN(net_1528), .C2(net_1381), .A(net_1231), .B1(net_1221), .B2(net_406) );
OAI21_X2 inst_531 ( .B1(net_3195), .B2(net_2972), .ZN(net_2902), .A(net_2432) );
INV_X2 inst_2737 ( .ZN(net_1309), .A(net_1308) );
INV_X4 inst_2316 ( .ZN(net_929), .A(net_763) );
OR2_X4 inst_212 ( .A1(net_3492), .A2(net_3364), .ZN(net_1740) );
INV_X2 inst_2732 ( .ZN(net_1392), .A(net_1347) );
NAND3_X2 inst_1299 ( .A1(net_3112), .ZN(net_1531), .A2(net_1337), .A3(net_671) );
OAI21_X2 inst_499 ( .B1(net_3394), .B2(net_2961), .ZN(net_2943), .A(net_2471) );
NAND2_X2 inst_1952 ( .A2(net_3578), .A1(net_3370), .ZN(net_3277) );
OAI21_X2 inst_674 ( .A(net_3793), .ZN(net_1362), .B1(net_1332), .B2(net_1041) );
CLKBUF_X2 inst_5259 ( .A(net_4436), .Z(net_5245) );
INV_X4 inst_2400 ( .ZN(net_333), .A(net_46) );
NAND2_X4 inst_1451 ( .ZN(net_3827), .A2(net_3237), .A1(net_2244) );
CLKBUF_X2 inst_4781 ( .A(net_4611), .Z(net_4767) );
AND3_X2 inst_4082 ( .A3(net_4110), .A1(net_3448), .ZN(net_2711), .A2(net_2518) );
CLKBUF_X2 inst_5023 ( .A(net_5008), .Z(net_5009) );
AOI22_X2 inst_3698 ( .B2(net_4124), .A2(net_555), .ZN(net_476), .A1(net_475), .B1(net_474) );
INV_X4 inst_2253 ( .A(net_3845), .ZN(net_1292) );
AND2_X4 inst_4155 ( .ZN(net_4105), .A1(net_3656), .A2(net_359) );
CLKBUF_X2 inst_5118 ( .A(net_5103), .Z(net_5104) );
INV_X2 inst_2966 ( .A(net_3004), .ZN(net_188) );
NAND2_X2 inst_2009 ( .A2(net_3820), .ZN(net_3545), .A1(net_3211) );
DFF_X1 inst_3246 ( .QN(net_3083), .D(net_2949), .CK(net_4555) );
INV_X2 inst_2868 ( .ZN(net_259), .A(net_50) );
OAI21_X2 inst_501 ( .B1(net_3394), .B2(net_2959), .ZN(net_2941), .A(net_2499) );
NAND2_X1 inst_2093 ( .ZN(net_415), .A2(net_281), .A1(x557) );
CLKBUF_X2 inst_4904 ( .A(net_4889), .Z(net_4890) );
NOR2_X2 inst_1081 ( .A1(net_3614), .ZN(net_613), .A2(net_436) );
DFF_X2 inst_3195 ( .QN(net_3107), .D(net_1626), .CK(net_4831) );
CLKBUF_X2 inst_4887 ( .A(net_4382), .Z(net_4873) );
INV_X4 inst_2381 ( .A(net_3789), .ZN(net_414) );
INV_X2 inst_2905 ( .A(net_3026), .ZN(net_136) );
NAND2_X2 inst_1832 ( .ZN(net_746), .A2(net_745), .A1(net_685) );
OAI21_X2 inst_570 ( .B2(net_3599), .ZN(net_2837), .B1(net_2836), .A(net_2061) );
INV_X2 inst_2819 ( .A(net_3521), .ZN(net_667) );
NAND2_X2 inst_1570 ( .A1(net_2912), .ZN(net_2451), .A2(net_200) );
CLKBUF_X2 inst_4562 ( .A(net_4254), .Z(net_4548) );
OAI21_X2 inst_640 ( .B2(net_3338), .ZN(net_2070), .A(net_1970), .B1(net_1969) );
NAND2_X2 inst_1612 ( .A1(net_2967), .ZN(net_2404), .A2(net_191) );
NAND2_X4 inst_1478 ( .A1(net_3995), .ZN(net_3943), .A2(net_3109) );
CLKBUF_X2 inst_4645 ( .A(net_4630), .Z(net_4631) );
NOR2_X2 inst_1114 ( .A2(net_3854), .ZN(net_3365), .A1(net_3286) );
OAI21_X4 inst_454 ( .B1(net_3264), .ZN(net_1869), .B2(net_1525), .A(net_1372) );
AND2_X4 inst_4163 ( .A2(net_4122), .ZN(net_4117), .A1(net_272) );
NAND2_X2 inst_1982 ( .A1(net_3881), .A2(net_3618), .ZN(net_3405) );
NAND2_X1 inst_2089 ( .A2(net_4021), .A1(net_2967), .ZN(net_2411) );
AOI22_X2 inst_3718 ( .B2(net_4099), .ZN(net_3573), .A2(net_3571), .B1(net_963), .A1(net_838) );
NAND2_X2 inst_1849 ( .ZN(net_665), .A1(net_600), .A2(net_450) );
NAND2_X2 inst_1679 ( .A1(net_3281), .ZN(net_2029), .A2(net_181) );
CLKBUF_X2 inst_4932 ( .A(net_4917), .Z(net_4918) );
NAND2_X2 inst_1976 ( .ZN(net_3352), .A1(net_2527), .A2(net_2376) );
AOI22_X2 inst_3681 ( .B1(net_4123), .A1(net_555), .ZN(net_502), .B2(net_170), .A2(net_166) );
INV_X2 inst_2744 ( .ZN(net_1195), .A(net_1144) );
INV_X4 inst_2215 ( .ZN(net_2120), .A(net_1945) );
INV_X1 inst_3077 ( .A(net_867), .ZN(net_812) );
NAND2_X2 inst_1855 ( .ZN(net_1041), .A1(net_641), .A2(net_403) );
OAI22_X2 inst_337 ( .ZN(net_429), .A2(net_347), .A1(net_344), .B2(net_263), .B1(net_47) );
CLKBUF_X2 inst_5277 ( .A(net_5262), .Z(net_5263) );
CLKBUF_X2 inst_4614 ( .A(net_4268), .Z(net_4600) );
INV_X4 inst_2384 ( .A(net_3664), .ZN(net_390) );
NAND4_X2 inst_1212 ( .ZN(net_1311), .A1(net_992), .A2(net_985), .A4(net_913), .A3(net_878) );
OAI21_X2 inst_670 ( .ZN(net_1468), .A(net_1341), .B1(net_182), .B2(net_115) );
CLKBUF_X2 inst_5224 ( .A(net_5209), .Z(net_5210) );
NAND2_X4 inst_1423 ( .ZN(net_3586), .A1(net_3585), .A2(net_2383) );
AND2_X4 inst_4180 ( .ZN(net_4140), .A2(net_3171), .A1(net_283) );
INV_X4 inst_2419 ( .ZN(net_247), .A(net_201) );
NOR2_X2 inst_1034 ( .ZN(net_1368), .A1(net_1243), .A2(net_1090) );
NAND4_X2 inst_1207 ( .A1(net_2020), .ZN(net_1628), .A4(net_321), .A3(net_258), .A2(net_53) );
AOI221_X2 inst_3901 ( .ZN(net_1204), .A(net_1203), .B1(net_1202), .C1(net_1201), .C2(net_1200), .B2(net_983) );
OAI21_X2 inst_613 ( .ZN(net_2641), .B1(net_2293), .B2(net_2246), .A(net_356) );
CLKBUF_X2 inst_4275 ( .A(net_4260), .Z(net_4261) );
CLKBUF_X2 inst_5041 ( .A(net_5026), .Z(net_5027) );
INV_X4 inst_2396 ( .ZN(net_404), .A(net_343) );
NAND2_X4 inst_1428 ( .A1(net_4002), .ZN(net_3615), .A2(net_376) );
OAI21_X2 inst_483 ( .B1(net_2970), .ZN(net_2960), .B2(net_2959), .A(net_2501) );
CLKBUF_X2 inst_5005 ( .A(net_4990), .Z(net_4991) );
INV_X2 inst_2739 ( .A(net_3931), .ZN(net_1282) );
OR2_X2 inst_259 ( .A1(net_4103), .A2(net_3670), .ZN(net_850) );
NOR2_X2 inst_1046 ( .A1(net_4156), .A2(net_3968), .ZN(net_1080) );
OR2_X4 inst_246 ( .ZN(net_4143), .A1(net_3780), .A2(net_2988) );
CLKBUF_X2 inst_4443 ( .A(net_4250), .Z(net_4429) );
CLKBUF_X2 inst_4355 ( .A(net_4340), .Z(net_4341) );
OAI21_X2 inst_635 ( .B2(net_2076), .ZN(net_2075), .A(net_1963), .B1(net_1673) );
CLKBUF_X2 inst_4707 ( .A(net_4692), .Z(net_4693) );
OAI211_X2 inst_807 ( .C2(net_3755), .ZN(net_1834), .C1(net_1513), .B(net_1197), .A(net_1187) );
CLKBUF_X2 inst_4846 ( .A(net_4494), .Z(net_4832) );
OAI21_X2 inst_705 ( .B1(net_3328), .ZN(net_890), .A(net_889), .B2(net_530) );
NOR3_X2 inst_911 ( .ZN(net_3415), .A3(net_3414), .A2(net_3412), .A1(net_3411) );
OAI21_X2 inst_519 ( .B2(net_2972), .B1(net_2923), .ZN(net_2921), .A(net_2426) );
AOI221_X2 inst_3796 ( .C2(net_3738), .B1(net_3736), .ZN(net_2856), .C1(net_2855), .A(net_1995), .B2(net_71) );
NOR3_X2 inst_909 ( .A2(net_4052), .ZN(net_3308), .A1(net_3307), .A3(net_1373) );
NOR2_X2 inst_1003 ( .ZN(net_2169), .A1(net_2129), .A2(net_2125) );
INV_X4 inst_2484 ( .A(net_3084), .ZN(net_780) );
NOR2_X2 inst_1053 ( .A2(net_4024), .ZN(net_1136), .A1(net_962) );
CLKBUF_X2 inst_5158 ( .A(net_5143), .Z(net_5144) );
INV_X2 inst_2919 ( .A(net_3137), .ZN(net_267) );
NOR3_X2 inst_894 ( .A3(net_4193), .ZN(net_1892), .A2(net_1891), .A1(net_1789) );
CLKBUF_X2 inst_5039 ( .A(net_5024), .Z(net_5025) );
INV_X4 inst_2425 ( .A(net_3123), .ZN(net_874) );
NAND2_X2 inst_1872 ( .A1(net_3713), .ZN(net_707), .A2(net_590) );
AOI22_X2 inst_3469 ( .B2(net_3116), .A1(net_2724), .B1(net_2722), .ZN(net_2721), .A2(net_35) );
NOR2_X2 inst_994 ( .A1(net_2300), .ZN(net_2296), .A2(net_1646) );
INV_X2 inst_2774 ( .ZN(net_2746), .A(net_901) );
CLKBUF_X2 inst_4577 ( .A(net_4562), .Z(net_4563) );
OR2_X4 inst_239 ( .A2(net_3640), .ZN(net_3599), .A1(net_3598) );
AOI211_X2 inst_4028 ( .A(net_4185), .C2(net_3900), .ZN(net_926), .B(net_925), .C1(net_692) );
NAND2_X2 inst_2080 ( .ZN(net_4181), .A1(net_3589), .A2(net_3184) );
NAND2_X2 inst_1879 ( .A2(net_3395), .ZN(net_637), .A1(net_407) );
NAND4_X2 inst_1193 ( .ZN(net_1667), .A3(net_1491), .A4(net_1490), .A2(net_1432), .A1(net_1424) );
NAND2_X2 inst_1625 ( .A1(net_2391), .ZN(net_2390), .A2(net_370) );
NAND2_X2 inst_1863 ( .A1(net_3156), .A2(net_1463), .ZN(net_1006) );
OAI21_X2 inst_593 ( .B1(net_2584), .ZN(net_2577), .A(net_2390), .B2(net_2114) );
INV_X4 inst_2223 ( .ZN(net_2115), .A(net_1993) );
CLKBUF_X2 inst_4522 ( .A(net_4507), .Z(net_4508) );
INV_X8 inst_2135 ( .A(net_3450), .ZN(net_513) );
OAI21_X2 inst_601 ( .B1(net_3886), .B2(net_3599), .ZN(net_2573), .A(net_1848) );
DFF_X2 inst_3119 ( .QN(net_3155), .D(net_2705), .CK(net_4489) );
CLKBUF_X2 inst_5138 ( .A(net_5123), .Z(net_5124) );
AOI222_X1 inst_3777 ( .ZN(net_1878), .A2(net_1826), .A1(net_1616), .B2(net_984), .C2(net_874), .B1(net_622), .C1(net_579) );
OAI21_X2 inst_764 ( .ZN(net_3917), .A(net_3913), .B2(net_3109), .B1(net_3106) );
NAND2_X2 inst_1773 ( .A1(net_4033), .ZN(net_1172), .A2(net_1108) );
OAI21_X2 inst_479 ( .B1(net_2970), .ZN(net_2968), .B2(net_2967), .A(net_2408) );
INV_X4 inst_2344 ( .A(net_3328), .ZN(net_788) );
NAND2_X2 inst_1547 ( .A1(net_2961), .ZN(net_2475), .A2(net_189) );
XOR2_X1 inst_29 ( .A(net_4117), .B(net_1699), .Z(net_673) );
DFF_X1 inst_3326 ( .Q(net_3110), .D(net_2829), .CK(net_4645) );
NAND2_X2 inst_1583 ( .A1(net_2915), .ZN(net_2437), .A2(net_237) );
OAI21_X1 inst_771 ( .ZN(net_4016), .B2(net_2969), .B1(net_2893), .A(net_2419) );
CLKBUF_X2 inst_4387 ( .A(net_4372), .Z(net_4373) );
INV_X4 inst_2369 ( .ZN(net_666), .A(net_397) );
INV_X8 inst_2152 ( .A(net_3531), .ZN(net_3366) );
AOI21_X2 inst_3947 ( .B1(net_4043), .A(net_2298), .ZN(net_2216), .B2(net_269) );
NAND3_X2 inst_1274 ( .ZN(net_2784), .A3(net_2715), .A2(net_2713), .A1(net_2660) );
AOI221_X2 inst_3838 ( .B1(net_3774), .C1(net_2227), .ZN(net_2221), .C2(net_2220), .A(net_2109), .B2(net_271) );
OAI21_X2 inst_538 ( .B2(net_3208), .B1(net_3195), .ZN(net_2895), .A(net_2495) );
INV_X2 inst_2831 ( .A(net_3396), .ZN(net_439) );
CLKBUF_X2 inst_4497 ( .A(net_4482), .Z(net_4483) );
CLKBUF_X2 inst_4756 ( .A(net_4741), .Z(net_4742) );
INV_X2 inst_2651 ( .ZN(net_2290), .A(net_2278) );
NAND3_X2 inst_1319 ( .A2(net_4105), .A3(net_4004), .ZN(net_785), .A1(net_784) );
NAND3_X2 inst_1300 ( .ZN(net_2815), .A2(net_1458), .A1(net_1378), .A3(net_1036) );
CLKBUF_X2 inst_5280 ( .A(net_5265), .Z(net_5266) );
CLKBUF_X2 inst_4537 ( .A(net_4522), .Z(net_4523) );
AND2_X2 inst_4201 ( .A1(net_4100), .ZN(net_772), .A2(net_82) );
XOR2_X1 inst_35 ( .A(net_4138), .Z(net_3384), .B(net_3377) );
OAI221_X2 inst_358 ( .C1(net_3352), .B2(net_3348), .ZN(net_2833), .B1(net_2816), .A(net_2564), .C2(net_2187) );
XNOR2_X2 inst_48 ( .A(net_3310), .ZN(net_2633), .B(net_2286) );
CLKBUF_X2 inst_4765 ( .A(net_4658), .Z(net_4751) );
CLKBUF_X2 inst_4462 ( .A(net_4447), .Z(net_4448) );
INV_X4 inst_2246 ( .ZN(net_1617), .A(net_1583) );
NAND2_X2 inst_1756 ( .A1(net_4064), .A2(net_4028), .ZN(net_1268) );
INV_X4 inst_2279 ( .ZN(net_1148), .A(net_922) );
OAI221_X2 inst_443 ( .B1(net_4158), .ZN(net_3695), .B2(net_3407), .C1(net_2328), .A(net_1933), .C2(net_132) );
INV_X4 inst_2600 ( .A(net_3995), .ZN(net_3755) );
NAND2_X2 inst_2038 ( .A1(net_3882), .A2(net_3880), .ZN(net_3791) );
CLKBUF_X2 inst_4259 ( .A(net_4229), .Z(net_4245) );
NAND2_X2 inst_2044 ( .A2(net_3887), .ZN(net_3849), .A1(net_3848) );
OAI21_X2 inst_655 ( .ZN(net_1931), .B1(net_1815), .A(net_1803), .B2(net_752) );
CLKBUF_X2 inst_5178 ( .A(net_5157), .Z(net_5164) );
INV_X4 inst_2274 ( .A(net_3339), .ZN(net_1192) );
NAND2_X2 inst_1700 ( .A1(net_4120), .ZN(net_1852), .A2(net_1807) );
INV_X4 inst_2571 ( .ZN(net_3543), .A(net_3542) );
CLKBUF_X2 inst_4438 ( .A(net_4274), .Z(net_4424) );
OAI21_X2 inst_695 ( .ZN(net_1458), .B1(net_1029), .B2(net_1028), .A(net_432) );
OAI21_X2 inst_730 ( .B2(net_991), .A(net_629), .B1(net_628), .ZN(net_580) );
AND4_X4 inst_4038 ( .A4(net_3973), .ZN(net_1255), .A1(net_1254), .A2(net_1253), .A3(net_748) );
OAI22_X2 inst_321 ( .A1(net_1154), .ZN(net_1027), .B1(net_1026), .B2(net_686), .A2(net_245) );
INV_X4 inst_2493 ( .A(net_2994), .ZN(net_217) );
OAI21_X2 inst_511 ( .B1(net_3274), .B2(net_2961), .ZN(net_2931), .A(net_2472) );
XNOR2_X2 inst_41 ( .ZN(net_2762), .A(net_2648), .B(net_1448) );
DFF_X2 inst_3131 ( .D(net_2619), .QN(net_114), .CK(net_4422) );
AOI22_X2 inst_3559 ( .A1(net_4059), .B1(net_4056), .ZN(net_1491), .B2(net_488), .A2(net_474) );
INV_X2 inst_2645 ( .A(net_3876), .ZN(net_2336) );
NAND2_X2 inst_1989 ( .ZN(net_3438), .A1(net_358), .A2(net_328) );
NOR2_X1 inst_1164 ( .A1(net_3554), .ZN(net_2379), .A2(net_1685) );
DFF_X2 inst_3112 ( .QN(net_2991), .D(net_2802), .CK(net_5241) );
SDFF_X2 inst_152 ( .D(net_3511), .SE(net_2514), .SI(net_103), .Q(net_103), .CK(net_4746) );
NOR2_X2 inst_1152 ( .ZN(net_3982), .A2(net_3981), .A1(net_1052) );
NAND4_X2 inst_1242 ( .ZN(net_3357), .A4(net_3356), .A3(net_3355), .A2(net_3351), .A1(net_3350) );
NAND2_X4 inst_1400 ( .A1(net_3661), .ZN(net_767), .A2(net_432) );
CLKBUF_X2 inst_5217 ( .A(net_5172), .Z(net_5203) );
CLKBUF_X2 inst_5233 ( .A(net_5218), .Z(net_5219) );
XNOR2_X2 inst_89 ( .ZN(net_936), .B(net_513), .A(net_408) );
NAND2_X2 inst_1520 ( .A1(net_2959), .ZN(net_2502), .A2(net_734) );
OAI221_X2 inst_388 ( .B2(net_2699), .C2(net_2698), .ZN(net_2542), .A(net_2369), .C1(net_2364), .B1(net_2314) );
CLKBUF_X2 inst_4600 ( .A(net_4483), .Z(net_4586) );
AOI221_X2 inst_3872 ( .B1(net_2020), .C1(net_2019), .ZN(net_1932), .A(net_1931), .B2(net_251), .C2(x437) );
NAND2_X2 inst_1535 ( .A1(net_2907), .ZN(net_2487), .A2(net_186) );
OR3_X2 inst_182 ( .ZN(net_1287), .A1(net_1168), .A3(net_1124), .A2(net_717) );
OAI211_X2 inst_788 ( .C2(net_2778), .ZN(net_2756), .C1(net_2666), .A(net_2653), .B(net_2606) );
OAI21_X2 inst_489 ( .B1(net_3394), .B2(net_2969), .ZN(net_2953), .A(net_2414) );
NOR2_X4 inst_931 ( .A1(net_3556), .A2(net_3019), .ZN(net_2027) );
DFF_X2 inst_3174 ( .D(net_1911), .Q(net_122), .CK(net_4997) );
AOI221_X2 inst_3824 ( .B2(net_3147), .A(net_2642), .B1(net_2591), .C1(net_2589), .ZN(net_2552), .C2(net_2551) );
NAND2_X2 inst_1674 ( .A1(net_2134), .ZN(net_2084), .A2(net_232) );
AOI22_X2 inst_3622 ( .B2(net_3158), .B1(net_1882), .ZN(net_1095), .A2(net_1094), .A1(net_939) );
NAND2_X2 inst_1579 ( .A1(net_2965), .ZN(net_2441), .A2(net_597) );
NAND2_X4 inst_1411 ( .A1(net_3898), .A2(net_3827), .ZN(net_3333) );
SDFF_X2 inst_149 ( .D(net_3248), .SE(net_2514), .SI(net_104), .Q(net_104), .CK(net_4747) );
OR2_X4 inst_193 ( .A1(net_3881), .A2(net_3515), .ZN(net_2366) );
XOR2_X1 inst_39 ( .Z(net_4196), .B(net_817), .A(net_766) );
AND3_X2 inst_4089 ( .A1(net_4093), .A2(net_1717), .ZN(net_859), .A3(net_40) );
NAND2_X4 inst_1415 ( .A1(net_3525), .ZN(net_3430), .A2(net_401) );
INV_X2 inst_2627 ( .A(net_3342), .ZN(net_2892) );
NAND2_X2 inst_1709 ( .A2(net_2268), .ZN(net_1727), .A1(net_1726) );
DFF_X1 inst_3301 ( .Q(net_3111), .D(net_2879), .CK(net_4523) );
INV_X4 inst_2320 ( .ZN(net_853), .A(net_683) );
DFF_X2 inst_3173 ( .D(net_1913), .QN(net_123), .CK(net_5276) );
XNOR2_X2 inst_125 ( .ZN(net_4155), .A(net_3369), .B(net_2347) );
INV_X4 inst_2534 ( .A(net_4004), .ZN(net_3319) );
INV_X4 inst_2202 ( .A(net_3857), .ZN(net_2288) );
CLKBUF_X2 inst_4770 ( .A(net_4755), .Z(net_4756) );
DFF_X2 inst_3180 ( .D(net_1819), .QN(net_107), .CK(net_4375) );
CLKBUF_X2 inst_4737 ( .A(net_4722), .Z(net_4723) );
INV_X2 inst_2987 ( .A(net_3009), .ZN(net_214) );
AOI222_X2 inst_3737 ( .B1(net_4196), .B2(net_1826), .ZN(net_1221), .A1(net_630), .C1(net_576), .C2(net_393), .A2(net_323) );
NAND2_X2 inst_1636 ( .A1(net_4041), .A2(net_3159), .ZN(net_2377) );
OAI221_X2 inst_430 ( .B1(net_3990), .C1(net_1129), .ZN(net_972), .A(net_971), .B2(net_667), .C2(net_646) );
CLKBUF_X2 inst_4599 ( .A(net_4584), .Z(net_4585) );
CLKBUF_X2 inst_4677 ( .A(net_4662), .Z(net_4663) );
OAI21_X2 inst_515 ( .B2(net_2961), .ZN(net_2927), .B1(net_2923), .A(net_2469) );
NAND2_X2 inst_1501 ( .ZN(net_2808), .A1(net_2794), .A2(net_2626) );
INV_X4 inst_2473 ( .A(net_2985), .ZN(net_147) );
DFF_X2 inst_3212 ( .D(net_801), .QN(net_289), .CK(net_4620) );
NAND2_X2 inst_1698 ( .A2(net_3506), .ZN(net_1886), .A1(net_1833) );
CLKBUF_X2 inst_5248 ( .A(net_5233), .Z(net_5234) );
INV_X4 inst_2565 ( .A(net_3631), .ZN(net_3521) );
NOR2_X4 inst_944 ( .A1(net_3983), .A2(net_3935), .ZN(net_3452) );
CLKBUF_X2 inst_4516 ( .A(net_4501), .Z(net_4502) );
INV_X2 inst_2945 ( .A(net_3053), .ZN(net_208) );
NAND2_X2 inst_1584 ( .A1(net_2915), .ZN(net_2436), .A2(net_180) );
OAI21_X2 inst_642 ( .ZN(net_1994), .B1(net_1993), .A(net_1859), .B2(net_1535) );
OAI21_X4 inst_459 ( .B1(net_4184), .ZN(net_3263), .B2(net_1608), .A(net_1503) );
INV_X2 inst_2993 ( .A(net_3020), .ZN(net_165) );
INV_X2 inst_2864 ( .A(net_3142), .ZN(net_295) );
AOI22_X2 inst_3476 ( .B1(net_4039), .A1(net_2675), .ZN(net_2674), .A2(net_1523), .B2(x40) );
NOR2_X2 inst_1018 ( .A1(net_2661), .A2(net_1905), .ZN(net_1824) );
AOI222_X1 inst_3789 ( .B1(net_4185), .C1(net_4101), .A2(net_3440), .ZN(net_1111), .C2(net_1011), .A1(net_897), .B2(net_649) );
INV_X2 inst_2933 ( .ZN(net_132), .A(net_73) );
OAI21_X2 inst_700 ( .B1(net_4088), .B2(net_3152), .ZN(net_934), .A(net_401) );
DFF_X1 inst_3393 ( .Q(net_3112), .D(net_1619), .CK(net_4473) );
OAI221_X2 inst_367 ( .B1(net_3553), .C1(net_3352), .B2(net_3348), .ZN(net_2728), .A(net_2552), .C2(net_2167) );
NOR2_X4 inst_957 ( .A1(net_4006), .A2(net_3942), .ZN(net_3713) );
NOR2_X4 inst_979 ( .ZN(net_3956), .A2(net_3954), .A1(net_3953) );
INV_X2 inst_2713 ( .A(net_3858), .ZN(net_2373) );
CLKBUF_X2 inst_4976 ( .A(net_4791), .Z(net_4962) );
NOR2_X2 inst_1008 ( .ZN(net_1782), .A2(net_1747), .A1(net_1689) );
DFF_X1 inst_3409 ( .D(net_1402), .Q(net_56), .CK(net_4819) );
CLKBUF_X2 inst_4568 ( .A(net_4553), .Z(net_4554) );
OAI21_X2 inst_559 ( .B2(net_2907), .B1(net_2871), .ZN(net_2866), .A(net_2484) );
NAND2_X2 inst_1871 ( .A2(net_3755), .ZN(net_603), .A1(net_337) );
INV_X4 inst_2296 ( .ZN(net_1586), .A(net_1064) );
AOI22_X2 inst_3591 ( .A1(net_4062), .B1(net_4057), .ZN(net_1426), .B2(net_170), .A2(net_166) );
INV_X4 inst_2300 ( .ZN(net_872), .A(net_871) );
CLKBUF_X2 inst_4964 ( .A(net_4949), .Z(net_4950) );
OAI221_X1 inst_450 ( .ZN(net_3743), .B1(net_3735), .C1(net_1993), .A(net_1898), .C2(net_1541), .B2(net_67) );
OAI21_X2 inst_520 ( .B1(net_3302), .ZN(net_2920), .B2(net_2919), .A(net_2398) );
OAI21_X2 inst_745 ( .B1(net_3430), .ZN(net_3339), .B2(net_3102), .A(net_862) );
AOI22_X2 inst_3658 ( .ZN(net_573), .A1(net_458), .B1(net_457), .B2(net_188), .A2(net_174) );
DFF_X1 inst_3405 ( .Q(net_4027), .D(net_1466), .CK(net_4508) );
AOI221_X2 inst_3888 ( .C2(net_4079), .A(net_4072), .ZN(net_1589), .C1(net_1224), .B2(net_1011), .B1(net_705) );
NAND2_X2 inst_2032 ( .A2(net_4164), .A1(net_3974), .ZN(net_3763) );
CLKBUF_X2 inst_4554 ( .A(net_4258), .Z(net_4540) );
CLKBUF_X2 inst_4258 ( .A(net_4243), .Z(net_4244) );
AND2_X4 inst_4113 ( .A2(net_3389), .ZN(net_401), .A1(net_248) );
AOI22_X2 inst_3623 ( .B1(net_3141), .ZN(net_1316), .B2(net_1071), .A2(net_1036), .A1(net_951) );
XNOR2_X2 inst_80 ( .ZN(net_1285), .B(net_1139), .A(net_1088) );
NAND2_X2 inst_2026 ( .A2(net_4162), .A1(net_4001), .ZN(net_3733) );
OAI211_X2 inst_836 ( .C2(net_3149), .C1(net_1359), .ZN(net_1354), .A(net_1239), .B(net_593) );
NAND2_X2 inst_1556 ( .A1(net_2909), .ZN(net_2466), .A2(net_222) );
AND4_X4 inst_4040 ( .A1(net_3901), .A2(net_3836), .A4(net_3547), .ZN(net_1084), .A3(net_767) );
CLKBUF_X2 inst_4334 ( .A(net_4259), .Z(net_4320) );
OR2_X4 inst_241 ( .ZN(net_3735), .A1(net_3427), .A2(net_1173) );
NOR2_X2 inst_1059 ( .ZN(net_1063), .A2(net_958), .A1(net_938) );
CLKBUF_X2 inst_5120 ( .A(net_5105), .Z(net_5106) );
CLKBUF_X2 inst_4409 ( .A(net_4394), .Z(net_4395) );
CLKBUF_X2 inst_4934 ( .A(net_4355), .Z(net_4920) );
NOR2_X2 inst_1075 ( .A2(net_3755), .ZN(net_675), .A1(net_618) );
NOR4_X2 inst_862 ( .A3(net_3777), .A2(net_3640), .ZN(net_2309), .A4(net_1325), .A1(net_1322) );
CLKBUF_X2 inst_4390 ( .A(net_4369), .Z(net_4376) );
CLKBUF_X2 inst_4358 ( .A(net_4290), .Z(net_4344) );
AOI221_X2 inst_3918 ( .B2(net_3788), .ZN(net_3570), .C2(net_3559), .A(net_1061), .C1(net_907), .B1(net_521) );
INV_X2 inst_2758 ( .A(net_1650), .ZN(net_1279) );
CLKBUF_X2 inst_4504 ( .A(net_4315), .Z(net_4490) );
NOR2_X2 inst_1116 ( .ZN(net_3389), .A1(net_3388), .A2(net_3127) );
CLKBUF_X2 inst_4328 ( .A(net_4313), .Z(net_4314) );
INV_X4 inst_2257 ( .ZN(net_1186), .A(net_1122) );
AND2_X4 inst_4173 ( .ZN(net_4127), .A1(net_3468), .A2(net_41) );
AOI222_X1 inst_3753 ( .A1(net_3676), .B1(net_2055), .C1(net_2054), .ZN(net_2040), .C2(net_821), .B2(net_378), .A2(net_280) );
NAND2_X2 inst_1764 ( .A2(net_1394), .ZN(net_1235), .A1(net_33) );
CLKBUF_X2 inst_5271 ( .A(net_4229), .Z(net_5257) );
NOR2_X2 inst_1104 ( .A2(net_4190), .A1(net_3299), .ZN(net_3184) );
NOR2_X2 inst_1159 ( .ZN(net_4097), .A1(net_526), .A2(net_380) );
INV_X4 inst_2355 ( .A(net_3997), .ZN(net_537) );
DFF_X2 inst_3136 ( .QN(net_2989), .D(net_2575), .CK(net_5153) );
OAI221_X2 inst_402 ( .C2(net_4034), .ZN(net_2300), .C1(net_2212), .B1(net_2042), .B2(net_2032), .A(net_1284) );
OAI22_X2 inst_329 ( .B1(net_3438), .ZN(net_864), .A1(net_863), .B2(net_513), .A2(net_408) );
OAI21_X2 inst_494 ( .B1(net_3588), .B2(net_2965), .ZN(net_2948), .A(net_2441) );
OAI21_X2 inst_574 ( .B2(net_2925), .ZN(net_2805), .B1(net_2803), .A(net_2434) );
NOR2_X4 inst_938 ( .A1(net_4007), .A2(net_3106), .ZN(net_376) );
INV_X4 inst_2347 ( .ZN(net_600), .A(net_541) );
AND2_X4 inst_4102 ( .A2(net_3490), .ZN(net_1837), .A1(x475) );
NAND4_X2 inst_1229 ( .A4(net_987), .A3(net_854), .ZN(net_730), .A2(net_729), .A1(net_604) );
NAND3_X2 inst_1288 ( .ZN(net_2259), .A1(net_2200), .A3(net_1953), .A2(net_1918) );
AOI221_X2 inst_3844 ( .B2(net_2203), .C1(net_2202), .ZN(net_2198), .A(net_2075), .B1(net_1767), .C2(net_378) );
CLKBUF_X2 inst_5219 ( .A(net_4457), .Z(net_5205) );
INV_X2 inst_2894 ( .A(net_3037), .ZN(net_183) );
INV_X4 inst_2358 ( .A(net_3656), .ZN(net_529) );
INV_X8 inst_2125 ( .ZN(net_641), .A(net_516) );
AOI22_X2 inst_3638 ( .ZN(net_782), .A1(net_781), .B1(net_780), .A2(net_458), .B2(net_457) );
CLKBUF_X2 inst_4365 ( .A(net_4266), .Z(net_4351) );
INV_X2 inst_2959 ( .ZN(net_258), .A(net_54) );
OAI21_X2 inst_599 ( .ZN(net_2508), .B1(net_2507), .A(net_2295), .B2(net_299) );
NOR2_X2 inst_1033 ( .A1(net_3229), .ZN(net_1443), .A2(net_294) );
NAND2_X2 inst_1683 ( .A1(net_3176), .ZN(net_2023), .A2(net_194) );
CLKBUF_X2 inst_4673 ( .A(net_4465), .Z(net_4659) );
AOI221_X2 inst_3865 ( .B1(net_2020), .C1(net_2019), .ZN(net_1944), .A(net_1943), .B2(net_206), .C2(x368) );
NAND3_X2 inst_1348 ( .A2(net_4088), .ZN(net_3485), .A3(net_3152), .A1(net_433) );
NAND2_X1 inst_2102 ( .ZN(net_4148), .A1(net_3198), .A2(net_213) );
CLKBUF_X2 inst_4908 ( .A(net_4893), .Z(net_4894) );
NAND2_X2 inst_1748 ( .A1(net_3229), .ZN(net_1437), .A2(net_68) );
OAI21_X2 inst_541 ( .ZN(net_4022), .B2(net_2961), .B1(net_2893), .A(net_2476) );
AND4_X4 inst_4047 ( .A4(net_4125), .A1(net_4097), .ZN(net_4076), .A2(net_3656), .A3(net_384) );
OAI21_X2 inst_505 ( .B1(net_3278), .ZN(net_2937), .B2(net_2917), .A(net_2393) );
NAND3_X2 inst_1365 ( .ZN(net_3970), .A3(net_3967), .A2(net_3789), .A1(net_1132) );
OR2_X4 inst_198 ( .A1(net_3179), .ZN(net_2969), .A2(net_2352) );
AND2_X4 inst_4125 ( .ZN(net_4051), .A1(net_3331), .A2(net_426) );
NAND3_X2 inst_1371 ( .ZN(net_4157), .A3(net_3999), .A1(net_3526), .A2(net_3171) );
CLKBUF_X2 inst_4321 ( .A(net_4280), .Z(net_4307) );
NAND2_X2 inst_1644 ( .A1(net_3199), .ZN(net_2171), .A2(net_2103) );
AOI22_X2 inst_3543 ( .B1(net_4054), .B2(net_3110), .ZN(net_1580), .A1(net_1578), .A2(net_396) );
OAI211_X2 inst_784 ( .C2(net_2778), .ZN(net_2771), .C1(net_2704), .B(net_2673), .A(net_2656) );
DFF_X1 inst_3237 ( .QN(net_3041), .D(net_2938), .CK(net_5194) );
NAND3_X4 inst_1264 ( .A3(net_4143), .ZN(net_3520), .A2(net_3519), .A1(net_3518) );
AOI22_X4 inst_3461 ( .A1(net_3817), .ZN(net_3209), .B1(net_3186), .A2(net_3029), .B2(net_3028) );
OAI21_X2 inst_690 ( .ZN(net_1083), .A(net_1082), .B1(net_1081), .B2(net_1026) );
CLKBUF_X2 inst_4969 ( .A(net_4928), .Z(net_4955) );
AOI22_X2 inst_3511 ( .B1(net_3676), .B2(net_3132), .A1(net_2012), .ZN(net_2006), .A2(net_396) );
CLKBUF_X2 inst_4692 ( .A(net_4660), .Z(net_4678) );
NAND2_X2 inst_2025 ( .A2(net_3947), .ZN(net_3728), .A1(net_3612) );
CLKBUF_X2 inst_4883 ( .A(net_4868), .Z(net_4869) );
INV_X4 inst_2461 ( .ZN(net_1444), .A(net_68) );
OAI21_X2 inst_732 ( .A(net_629), .B1(net_628), .ZN(net_578), .B2(net_225) );
CLKBUF_X2 inst_4717 ( .A(net_4702), .Z(net_4703) );
INV_X4 inst_2178 ( .A(net_3808), .ZN(net_2741) );
OR2_X2 inst_263 ( .A2(net_4120), .ZN(net_1776), .A1(net_586) );
OR3_X2 inst_185 ( .ZN(net_904), .A1(net_889), .A2(net_435), .A3(net_334) );
XNOR2_X2 inst_75 ( .A(net_3229), .ZN(net_1449), .B(net_70) );
OR3_X4 inst_166 ( .A2(net_4095), .ZN(net_1891), .A1(net_1012), .A3(net_56) );
AOI221_X2 inst_3815 ( .C1(net_3445), .A(net_2642), .C2(net_2594), .ZN(net_2585), .B1(net_2584), .B2(net_686) );
CLKBUF_X2 inst_4786 ( .A(net_4547), .Z(net_4772) );
XNOR2_X2 inst_79 ( .ZN(net_1329), .B(net_1221), .A(net_977) );
NAND2_X2 inst_1757 ( .A1(net_3500), .ZN(net_2125), .A2(net_1264) );
AOI221_X2 inst_3851 ( .A(net_4183), .ZN(net_2066), .C2(net_1908), .C1(net_1664), .B2(net_749), .B1(net_101) );
INV_X2 inst_2654 ( .ZN(net_2275), .A(net_2274) );
AND2_X4 inst_4118 ( .ZN(net_4039), .A1(net_2325), .A2(net_1386) );
NAND2_X2 inst_1605 ( .A1(net_2969), .ZN(net_2412), .A2(net_226) );
CLKBUF_X2 inst_4849 ( .A(net_4708), .Z(net_4835) );
CLKBUF_X2 inst_4413 ( .A(net_4398), .Z(net_4399) );
CLKBUF_X2 inst_4649 ( .A(net_4634), .Z(net_4635) );
INV_X2 inst_2975 ( .ZN(net_216), .A(net_111) );
NAND2_X2 inst_1741 ( .ZN(net_1512), .A1(net_1370), .A2(net_863) );
NOR2_X2 inst_1024 ( .A2(net_4070), .A1(net_1646), .ZN(net_1610) );
INV_X4 inst_2232 ( .ZN(net_1807), .A(net_38) );
CLKBUF_X2 inst_5308 ( .A(net_5293), .Z(net_5294) );
CLKBUF_X2 inst_4546 ( .A(net_4531), .Z(net_4532) );
NAND2_X2 inst_1658 ( .ZN(net_2105), .A1(net_1982), .A2(net_233) );
NAND2_X2 inst_1689 ( .A1(net_1982), .ZN(net_1981), .A2(net_170) );
CLKBUF_X2 inst_4475 ( .A(net_4460), .Z(net_4461) );
CLKBUF_X2 inst_4267 ( .A(net_4252), .Z(net_4253) );
AOI21_X2 inst_3965 ( .ZN(net_1452), .A(net_1318), .B1(net_1258), .B2(net_991) );
INV_X2 inst_2846 ( .ZN(net_408), .A(net_403) );
AOI22_X2 inst_3584 ( .A1(net_4063), .B1(net_4058), .B2(net_3455), .ZN(net_1433), .A2(net_201) );
CLKBUF_X2 inst_5034 ( .A(net_5019), .Z(net_5020) );
CLKBUF_X2 inst_4853 ( .A(net_4838), .Z(net_4839) );
NAND2_X4 inst_1448 ( .A1(net_3849), .ZN(net_3803), .A2(net_3517) );
OAI221_X2 inst_440 ( .B2(net_4180), .ZN(net_3465), .C2(net_3464), .C1(net_3463), .B1(net_3462), .A(net_3461) );
NAND2_X2 inst_1816 ( .A1(net_4110), .ZN(net_830), .A2(net_829) );
AOI221_X2 inst_3898 ( .B2(net_3418), .B1(net_1656), .C2(net_1288), .ZN(net_1252), .C1(net_1246), .A(net_1070) );
CLKBUF_X2 inst_5254 ( .A(net_4206), .Z(net_5240) );
CLKBUF_X2 inst_5201 ( .A(net_5150), .Z(net_5187) );
CLKBUF_X2 inst_5012 ( .A(net_4605), .Z(net_4998) );
INV_X4 inst_2373 ( .ZN(net_2642), .A(net_1386) );
CLKBUF_X2 inst_4927 ( .A(net_4912), .Z(net_4913) );
DFF_X1 inst_3381 ( .D(net_2236), .QN(net_62), .CK(net_4209) );
AOI22_X2 inst_3503 ( .B1(net_4080), .ZN(net_2032), .A2(net_1807), .A1(net_1774), .B2(net_39) );
NOR2_X2 inst_1091 ( .ZN(net_413), .A1(net_266), .A2(net_164) );
NAND2_X2 inst_1887 ( .A1(net_3929), .ZN(net_889), .A2(net_398) );
NAND3_X2 inst_1331 ( .A2(net_3395), .ZN(net_534), .A3(net_516), .A1(net_376) );
AND2_X4 inst_4138 ( .ZN(net_4067), .A1(net_3905), .A2(net_1037) );
XNOR2_X2 inst_52 ( .A(net_3311), .ZN(net_2512), .B(net_1598) );
CLKBUF_X2 inst_5059 ( .A(net_4688), .Z(net_5045) );
CLKBUF_X2 inst_4837 ( .A(net_4822), .Z(net_4823) );
OAI21_X2 inst_668 ( .A(net_4191), .ZN(net_1592), .B1(net_1389), .B2(net_786) );
DFF_X1 inst_3223 ( .QN(net_3057), .D(net_2981), .CK(net_4742) );
AOI22_X2 inst_3579 ( .A1(net_4059), .B1(net_4056), .ZN(net_1471), .B2(net_226), .A2(net_167) );
INV_X2 inst_3049 ( .A(net_3959), .ZN(net_3818) );
AND2_X4 inst_4154 ( .ZN(net_4103), .A1(net_3214), .A2(net_881) );
AOI22_X2 inst_3560 ( .A1(net_4060), .B1(net_4055), .ZN(net_1490), .B2(net_735), .A2(net_734) );
AND2_X4 inst_4159 ( .ZN(net_4110), .A2(net_3662), .A1(net_775) );
INV_X2 inst_2683 ( .ZN(net_1846), .A(net_1802) );
CLKBUF_X2 inst_4816 ( .A(net_4801), .Z(net_4802) );
NAND2_X2 inst_1672 ( .ZN(net_2086), .A1(net_2082), .A2(net_180) );
CLKBUF_X2 inst_4223 ( .A(net_4208), .Z(net_4209) );
DFF_X1 inst_3349 ( .D(net_2729), .CK(net_4343), .Q(x105) );
NAND2_X2 inst_2015 ( .A1(net_3647), .ZN(net_3646), .A2(net_492) );
DFF_X2 inst_3179 ( .D(net_1877), .Q(net_53), .CK(net_4841) );
INV_X4 inst_2545 ( .ZN(net_3445), .A(net_3444) );
INV_X2 inst_3059 ( .A(net_3994), .ZN(net_3993) );
AOI21_X2 inst_3937 ( .ZN(net_2301), .B1(net_2300), .A(net_2267), .B2(net_248) );
INV_X2 inst_2970 ( .ZN(net_224), .A(net_110) );
INV_X2 inst_2768 ( .ZN(net_918), .A(net_917) );
NAND2_X2 inst_1835 ( .A1(net_4004), .ZN(net_829), .A2(net_669) );
AND3_X2 inst_4085 ( .A1(net_1254), .ZN(net_1207), .A2(net_1037), .A3(net_899) );
NAND2_X2 inst_1910 ( .ZN(net_298), .A1(net_284), .A2(net_264) );
CLKBUF_X2 inst_4990 ( .A(net_4672), .Z(net_4976) );
CLKBUF_X2 inst_4639 ( .A(net_4624), .Z(net_4625) );
INV_X4 inst_2587 ( .ZN(net_3659), .A(net_3655) );
OAI21_X2 inst_621 ( .B1(net_2235), .ZN(net_2162), .A(net_2058), .B2(net_109) );
DFF_X2 inst_3115 ( .QN(net_2993), .D(net_2804), .CK(net_5239) );
INV_X4 inst_2560 ( .ZN(net_3508), .A(net_3507) );
DFF_X1 inst_3219 ( .QN(net_3061), .D(net_2980), .CK(net_4613) );
OAI211_X2 inst_815 ( .B(net_1628), .C1(net_1627), .ZN(net_1623), .A(net_1550), .C2(net_359) );
INV_X2 inst_3031 ( .ZN(net_3557), .A(net_3555) );
INV_X8 inst_2165 ( .A(net_3816), .ZN(net_3815) );
NOR4_X2 inst_875 ( .A3(net_4186), .ZN(net_4156), .A4(net_3788), .A1(net_969), .A2(net_706) );
NAND4_X2 inst_1257 ( .A4(net_4003), .ZN(net_3977), .A1(net_3976), .A2(net_3919), .A3(net_3811) );
DFF_X1 inst_3298 ( .QN(net_3006), .D(net_2883), .CK(net_5216) );
AOI22_X2 inst_3482 ( .A1(net_4038), .B2(net_3418), .B1(net_2657), .ZN(net_2655), .A2(net_991) );
INV_X1 inst_3081 ( .A(net_3722), .ZN(net_3547) );
NAND2_X4 inst_1387 ( .ZN(net_2839), .A2(net_2838), .A1(net_2791) );
CLKBUF_X2 inst_5187 ( .A(net_4625), .Z(net_5173) );
CLKBUF_X2 inst_5075 ( .A(net_5060), .Z(net_5061) );
NAND2_X2 inst_1991 ( .A1(net_3534), .ZN(net_3457), .A2(net_3456) );
NAND2_X2 inst_2069 ( .ZN(net_3975), .A2(net_3822), .A1(net_3721) );
INV_X4 inst_2365 ( .ZN(net_1998), .A(net_1826) );
MUX2_X2 inst_2108 ( .S(net_2909), .A(net_2573), .Z(net_2569), .B(net_148) );
AOI22_X2 inst_3572 ( .A1(net_4060), .B1(net_4055), .ZN(net_1478), .B2(net_781), .A2(net_780) );
INV_X16 inst_3066 ( .A(net_3489), .ZN(net_283) );
AND2_X4 inst_4098 ( .A2(net_1548), .ZN(net_1210), .A1(net_1023) );
INV_X4 inst_2250 ( .ZN(net_1514), .A(net_1509) );
INV_X2 inst_2978 ( .ZN(net_185), .A(net_108) );
OAI221_X2 inst_413 ( .C2(net_3720), .A(net_3570), .ZN(net_1562), .B1(net_1207), .C1(net_927), .B2(net_877) );
CLKBUF_X2 inst_5094 ( .A(net_5079), .Z(net_5080) );
INV_X4 inst_2187 ( .ZN(net_2752), .A(net_2519) );
NOR4_X2 inst_859 ( .ZN(net_1879), .A1(net_1829), .A2(net_1042), .A3(net_877), .A4(net_328) );
CLKBUF_X2 inst_4703 ( .A(net_4688), .Z(net_4689) );
INV_X2 inst_2672 ( .ZN(net_1914), .A(net_1883) );
XOR2_X2 inst_25 ( .Z(net_4139), .A(net_4137), .B(net_3385) );
DFF_X1 inst_3323 ( .D(net_4151), .Q(net_3134), .CK(net_4199) );
NAND2_X2 inst_2019 ( .ZN(net_3658), .A2(net_3655), .A1(net_279) );
CLKBUF_X2 inst_5239 ( .A(net_4356), .Z(net_5225) );
AOI22_X2 inst_3527 ( .A2(net_3134), .A1(net_1923), .B1(net_1921), .ZN(net_1917), .B2(net_207) );
CLKBUF_X2 inst_5032 ( .A(net_5017), .Z(net_5018) );
CLKBUF_X2 inst_5166 ( .A(net_5151), .Z(net_5152) );
CLKBUF_X2 inst_5186 ( .A(net_5171), .Z(net_5172) );
INV_X4 inst_2500 ( .A(net_2992), .ZN(net_227) );
XNOR2_X2 inst_69 ( .A(net_3794), .ZN(net_1621), .B(net_1289) );
CLKBUF_X2 inst_4395 ( .A(net_4380), .Z(net_4381) );
CLKBUF_X2 inst_4296 ( .A(net_4281), .Z(net_4282) );
AOI222_X1 inst_3764 ( .A2(net_3151), .C1(net_3118), .A1(net_2055), .B2(net_2054), .C2(net_2053), .ZN(net_1989), .B1(net_1571) );
INV_X2 inst_2669 ( .A(net_3504), .ZN(net_1959) );
NAND2_X2 inst_1691 ( .A1(net_1982), .ZN(net_1979), .A2(net_173) );
OAI211_X2 inst_844 ( .C2(net_4185), .ZN(net_1098), .C1(net_986), .A(net_432), .B(net_207) );
INV_X4 inst_2489 ( .A(net_3157), .ZN(net_1032) );
AOI22_X2 inst_3688 ( .B1(net_4123), .A1(net_555), .ZN(net_490), .A2(net_230), .B2(net_148) );
AOI22_X2 inst_3619 ( .ZN(net_1141), .B1(net_1131), .A1(net_1074), .A2(net_667), .B2(net_399) );
CLKBUF_X2 inst_4641 ( .A(net_4626), .Z(net_4627) );
INV_X4 inst_2340 ( .ZN(net_2376), .A(net_2374) );
OAI21_X4 inst_460 ( .ZN(net_3439), .B2(net_3438), .B1(net_3437), .A(net_3436) );
NAND2_X4 inst_1455 ( .ZN(net_3836), .A2(net_3835), .A1(net_3834) );
DFF_X2 inst_3204 ( .QN(net_3171), .D(net_1364), .CK(net_5267) );
INV_X4 inst_2497 ( .ZN(net_211), .A(net_55) );
AOI22_X2 inst_3660 ( .A1(net_571), .B1(net_570), .ZN(net_569), .A2(net_568), .B2(net_567) );
DFF_X1 inst_3421 ( .Q(net_4033), .D(net_1091), .CK(net_4852) );
CLKBUF_X2 inst_4444 ( .A(net_4429), .Z(net_4430) );
OAI21_X2 inst_560 ( .B2(net_3207), .B1(net_2871), .ZN(net_2865), .A(net_2480) );
INV_X2 inst_2679 ( .ZN(net_1876), .A(net_1822) );
XOR2_X2 inst_16 ( .A(net_4093), .B(net_3418), .Z(net_916) );
CLKBUF_X2 inst_5199 ( .A(net_5184), .Z(net_5185) );
CLKBUF_X2 inst_4230 ( .A(net_4215), .Z(net_4216) );
AOI21_X2 inst_3949 ( .B1(net_2238), .ZN(net_2194), .A(net_2168), .B2(net_1280) );
CLKBUF_X2 inst_4809 ( .A(net_4634), .Z(net_4795) );
INV_X2 inst_2808 ( .ZN(net_689), .A(net_688) );
SDFF_X2 inst_156 ( .SE(net_2625), .D(net_1834), .SI(net_87), .Q(net_87), .CK(net_4975) );
CLKBUF_X2 inst_4617 ( .A(net_4602), .Z(net_4603) );
NAND2_X2 inst_1777 ( .A1(net_4079), .ZN(net_1301), .A2(net_1089) );
NAND2_X2 inst_1802 ( .A1(net_4082), .ZN(net_1975), .A2(net_266) );
NOR2_X4 inst_950 ( .A1(net_3777), .ZN(net_3636), .A2(net_3602) );
NOR2_X2 inst_1068 ( .A1(net_1090), .ZN(net_823), .A2(x947) );
NOR3_X2 inst_886 ( .A2(net_3115), .A1(net_2748), .ZN(net_2747), .A3(net_2746) );
AOI21_X2 inst_3955 ( .ZN(net_1714), .B1(net_1604), .A(net_1547), .B2(net_717) );
INV_X2 inst_2982 ( .A(net_3110), .ZN(net_1960) );
INV_X2 inst_2693 ( .ZN(net_1729), .A(net_1661) );
DFF_X1 inst_3359 ( .D(net_2360), .CK(net_4234), .Q(x423) );
NAND4_X2 inst_1218 ( .A4(net_3984), .ZN(net_997), .A2(net_996), .A1(net_748), .A3(net_679) );
CLKBUF_X2 inst_4418 ( .A(net_4403), .Z(net_4404) );
CLKBUF_X2 inst_4468 ( .A(net_4453), .Z(net_4454) );
XNOR2_X2 inst_96 ( .ZN(net_817), .B(net_587), .A(net_585) );
INV_X2 inst_3020 ( .A(net_3763), .ZN(net_3429) );
XNOR2_X2 inst_101 ( .B(net_874), .ZN(net_617), .A(net_616) );
NAND2_X2 inst_1549 ( .A1(net_2961), .ZN(net_2473), .A2(net_478) );
CLKBUF_X2 inst_4346 ( .A(net_4331), .Z(net_4332) );
AOI22_X2 inst_3555 ( .A1(net_4059), .B1(net_4056), .ZN(net_1495), .B2(net_495), .A2(net_241) );
NAND2_X2 inst_1969 ( .ZN(net_3336), .A1(net_2099), .A2(net_470) );
INV_X2 inst_2881 ( .ZN(net_143), .A(x557) );
OAI211_X2 inst_821 ( .ZN(net_2555), .A(net_1384), .B(net_1304), .C1(net_1204), .C2(net_46) );
NOR2_X4 inst_980 ( .A1(net_3994), .ZN(net_3974), .A2(net_319) );
CLKBUF_X2 inst_4722 ( .A(net_4707), .Z(net_4708) );
OAI21_X2 inst_510 ( .B1(net_3274), .B2(net_2963), .ZN(net_2932), .A(net_2457) );
INV_X4 inst_2436 ( .ZN(net_406), .A(net_266) );
INV_X2 inst_2832 ( .A(net_616), .ZN(net_437) );
NAND2_X2 inst_1677 ( .A1(net_3185), .ZN(net_2080), .A2(net_475) );
OAI21_X2 inst_603 ( .B1(net_2597), .ZN(net_2349), .A(net_2326), .B2(net_375) );
OAI211_X2 inst_830 ( .A(net_3924), .ZN(net_1363), .C1(net_1182), .B(net_1129), .C2(net_900) );
NAND2_X2 inst_1785 ( .A2(net_1613), .A1(net_1332), .ZN(net_1203) );
OAI22_X2 inst_291 ( .A1(net_3781), .B1(net_1884), .ZN(net_1830), .A2(net_1829), .B2(net_263) );
INV_X2 inst_2878 ( .A(net_3153), .ZN(net_1791) );
CLKBUF_X2 inst_4213 ( .A(net_4198), .Z(net_4199) );
DFF_X2 inst_3150 ( .D(net_2305), .QN(net_264), .CK(net_4385) );
INV_X4 inst_2494 ( .A(net_3076), .ZN(net_737) );
OAI21_X1 inst_776 ( .A(net_3331), .ZN(net_1643), .B1(net_931), .B2(net_327) );
INV_X4 inst_2526 ( .A(net_3854), .ZN(net_3268) );
CLKBUF_X2 inst_5047 ( .A(net_5032), .Z(net_5033) );
INV_X4 inst_2286 ( .A(net_1295), .ZN(net_1052) );
NOR4_X2 inst_866 ( .A1(net_1183), .ZN(net_1133), .A3(net_1132), .A4(net_1131), .A2(net_858) );
CLKBUF_X2 inst_5313 ( .A(net_5298), .Z(net_5299) );
INV_X8 inst_2137 ( .ZN(net_322), .A(net_290) );
NAND2_X4 inst_1439 ( .A2(net_4188), .ZN(net_3715), .A1(net_3714) );
NAND2_X2 inst_1972 ( .ZN(net_3340), .A1(net_3287), .A2(net_3277) );
OAI21_X2 inst_558 ( .B2(net_2909), .B1(net_2871), .ZN(net_2867), .A(net_2465) );
AOI22_X2 inst_3640 ( .A1(net_4142), .B1(net_4112), .ZN(net_762), .B2(net_168), .A2(x856) );
OR2_X2 inst_248 ( .A1(net_3352), .ZN(net_2614), .A2(net_2272) );
NAND2_X2 inst_1613 ( .A1(net_2917), .ZN(net_2403), .A2(net_159) );
DFF_X2 inst_3107 ( .QN(net_2997), .D(net_2805), .CK(net_5247) );
CLKBUF_X2 inst_5179 ( .A(net_5164), .Z(net_5165) );
OAI221_X2 inst_389 ( .B1(net_3449), .B2(net_2661), .C1(net_2521), .ZN(net_2505), .A(net_671), .C2(net_670) );
NAND2_X2 inst_1919 ( .A1(net_3165), .ZN(net_246), .A2(net_125) );
INV_X2 inst_2712 ( .A(net_3858), .ZN(net_2838) );
NAND3_X1 inst_1382 ( .A1(net_3514), .ZN(net_3484), .A3(net_3135), .A2(net_931) );
INV_X2 inst_2795 ( .A(net_1007), .ZN(net_754) );
NOR2_X2 inst_1141 ( .A2(net_3858), .ZN(net_3852), .A1(net_3251) );
NAND2_X2 inst_1807 ( .A1(net_4082), .A2(net_1717), .ZN(net_1120) );
AOI22_X2 inst_3589 ( .A1(net_4062), .B1(net_4057), .ZN(net_1428), .A2(net_212), .B2(net_189) );
INV_X4 inst_2488 ( .ZN(net_204), .A(net_49) );
NOR2_X4 inst_932 ( .A1(net_3556), .ZN(net_2025), .A2(net_133) );
CLKBUF_X2 inst_5266 ( .A(net_5251), .Z(net_5252) );
OR3_X2 inst_180 ( .ZN(net_2217), .A1(net_2153), .A2(net_2141), .A3(net_1293) );
NOR3_X2 inst_913 ( .ZN(net_3461), .A2(net_3460), .A1(net_2747), .A3(net_2580) );
CLKBUF_X2 inst_4766 ( .A(net_4751), .Z(net_4752) );
NAND2_X2 inst_1960 ( .ZN(net_3298), .A1(net_3290), .A2(net_2874) );
CLKBUF_X2 inst_4445 ( .A(net_4430), .Z(net_4431) );
CLKBUF_X2 inst_4636 ( .A(net_4621), .Z(net_4622) );
OAI22_X2 inst_302 ( .A1(net_1543), .B1(net_1542), .ZN(net_1540), .A2(net_331), .B2(net_134) );
OAI21_X2 inst_673 ( .ZN(net_1375), .B1(net_1315), .B2(net_1314), .A(net_641) );
AOI22_X2 inst_3585 ( .A1(net_4063), .B1(net_4058), .ZN(net_1432), .A2(net_568), .B2(net_567) );
DFF_X1 inst_3287 ( .QN(net_3049), .D(net_2901), .CK(net_4968) );
OR2_X4 inst_211 ( .A1(net_3408), .A2(net_3406), .ZN(net_1803) );
INV_X4 inst_2483 ( .A(net_3093), .ZN(net_834) );
NOR2_X2 inst_1151 ( .ZN(net_3955), .A2(net_3954), .A1(net_3953) );
CLKBUF_X2 inst_4659 ( .A(net_4644), .Z(net_4645) );
DFF_X2 inst_3120 ( .Q(net_3145), .D(net_2727), .CK(net_4640) );
NAND2_X4 inst_1414 ( .A2(net_3858), .A1(net_3829), .ZN(net_3404) );
OAI21_X2 inst_561 ( .B1(net_4035), .B2(net_2876), .ZN(net_2863), .A(net_2840) );
AOI21_X2 inst_3994 ( .B2(net_3880), .A(net_3858), .ZN(net_3813), .B1(net_3290) );
OAI221_X2 inst_449 ( .ZN(net_4178), .C1(net_4177), .A(net_1826), .B1(net_1502), .C2(net_918), .B2(net_917) );
CLKBUF_X2 inst_4212 ( .A(net_4197), .Z(net_4198) );
INV_X4 inst_2505 ( .A(net_2982), .ZN(net_148) );
INV_X2 inst_2790 ( .ZN(net_795), .A(net_794) );
INV_X8 inst_2138 ( .A(net_3270), .ZN(net_3211) );
NAND2_X2 inst_1641 ( .ZN(net_3213), .A1(net_2086), .A2(net_1986) );
INV_X2 inst_2736 ( .ZN(net_1322), .A(net_1272) );
DFF_X1 inst_3249 ( .QN(net_3082), .D(net_2939), .CK(net_4542) );
OR2_X4 inst_196 ( .A1(net_3645), .ZN(net_2961), .A2(net_2352) );
CLKBUF_X2 inst_4935 ( .A(net_4920), .Z(net_4921) );
NAND2_X2 inst_1567 ( .A1(net_2963), .ZN(net_2454), .A2(net_167) );
CLKBUF_X2 inst_4489 ( .A(net_4423), .Z(net_4475) );
INV_X4 inst_2417 ( .A(net_1521), .ZN(net_1107) );
INV_X4 inst_2309 ( .A(net_1614), .ZN(net_1244) );
NAND2_X4 inst_1403 ( .A2(net_3760), .ZN(net_320), .A1(net_319) );
OAI22_X2 inst_298 ( .A1(net_3781), .A2(net_3500), .B1(net_1884), .ZN(net_1612), .B2(net_1611) );
INV_X4 inst_2180 ( .ZN(net_2649), .A(net_2602) );
NAND2_X2 inst_1856 ( .A2(net_988), .A1(net_778), .ZN(net_615) );
AOI22_X2 inst_3614 ( .ZN(net_1339), .B1(net_1338), .A1(net_1287), .B2(net_1071), .A2(net_1036) );
INV_X4 inst_2603 ( .A(net_3939), .ZN(net_3767) );
CLKBUF_X2 inst_4603 ( .A(net_4588), .Z(net_4589) );
XNOR2_X2 inst_42 ( .ZN(net_2759), .A(net_2692), .B(net_71) );
INV_X8 inst_2153 ( .ZN(net_3394), .A(net_3393) );
AND3_X2 inst_4084 ( .A1(net_4061), .ZN(net_1342), .A2(net_182), .A3(net_156) );
OAI21_X2 inst_588 ( .B2(net_3428), .ZN(net_2632), .B1(net_2512), .A(net_2117) );
NAND2_X4 inst_1479 ( .ZN(net_3949), .A1(net_3948), .A2(net_3612) );
AOI22_X2 inst_3529 ( .A1(net_1955), .B1(net_1921), .ZN(net_1915), .B2(net_371), .A2(net_252) );
NAND2_X2 inst_2040 ( .A2(net_3893), .A1(net_3869), .ZN(net_3800) );
OAI221_X2 inst_437 ( .C2(net_3123), .B2(net_874), .A(net_629), .B1(net_628), .C1(net_627), .ZN(net_622) );
CLKBUF_X2 inst_4742 ( .A(net_4603), .Z(net_4728) );
CLKBUF_X2 inst_4752 ( .A(net_4413), .Z(net_4738) );
NAND3_X2 inst_1356 ( .ZN(net_3702), .A2(net_3698), .A1(net_3389), .A3(net_317) );
NAND2_X2 inst_1706 ( .A1(net_1740), .ZN(net_1737), .A2(net_1690) );
INV_X2 inst_2628 ( .A(net_3532), .ZN(net_2852) );
CLKBUF_X2 inst_4561 ( .A(net_4546), .Z(net_4547) );
INV_X4 inst_2196 ( .ZN(net_2391), .A(net_2326) );
AOI22_X2 inst_3485 ( .A1(net_4038), .B1(net_2657), .ZN(net_2651), .A2(net_393), .B2(net_323) );
INV_X4 inst_2220 ( .ZN(net_1948), .A(net_1909) );
NOR2_X2 inst_1045 ( .ZN(net_1188), .A1(net_1068), .A2(net_1002) );
INV_X2 inst_2743 ( .ZN(net_1216), .A(net_1215) );
OR2_X2 inst_252 ( .A2(net_1507), .ZN(net_1442), .A1(net_1441) );
NOR4_X2 inst_865 ( .ZN(net_1230), .A1(net_1229), .A3(net_1228), .A2(net_1013), .A4(net_640) );
NAND2_X1 inst_2083 ( .A2(net_4011), .A1(net_2959), .ZN(net_2504) );
NOR2_X4 inst_956 ( .A1(net_3888), .ZN(net_3701), .A2(net_3615) );
NAND2_X4 inst_1470 ( .A2(net_3951), .A1(net_3921), .ZN(net_3899) );
CLKBUF_X2 inst_4684 ( .A(net_4669), .Z(net_4670) );
INV_X4 inst_2247 ( .A(net_3331), .ZN(net_1561) );
NAND4_X2 inst_1213 ( .A1(net_3174), .A4(net_3173), .ZN(net_1293), .A2(net_1108), .A3(net_955) );
INV_X1 inst_3072 ( .ZN(net_2367), .A(net_2335) );
OAI21_X2 inst_484 ( .B2(net_3208), .B1(net_2970), .ZN(net_2958), .A(net_2493) );
INV_X4 inst_2452 ( .A(net_3147), .ZN(net_135) );
CLKBUF_X2 inst_4474 ( .A(net_4459), .Z(net_4460) );
XOR2_X1 inst_32 ( .Z(net_364), .A(net_273), .B(net_76) );
OAI221_X2 inst_428 ( .B1(net_3941), .ZN(net_1288), .B2(net_987), .A(net_942), .C1(net_721), .C2(net_329) );
NAND2_X2 inst_1821 ( .A1(net_1213), .ZN(net_1000), .A2(net_371) );
DFF_X1 inst_3418 ( .D(net_1356), .Q(net_35), .CK(net_4293) );
DFF_X1 inst_3334 ( .D(net_2819), .QN(net_315), .CK(net_4319) );
OAI221_X2 inst_407 ( .B2(net_4050), .B1(net_3781), .C2(net_3159), .C1(net_1884), .ZN(net_1752), .A(net_1751) );
AOI22_X2 inst_3558 ( .A1(net_4060), .B1(net_4055), .ZN(net_1492), .A2(net_188), .B2(net_174) );
NAND4_X2 inst_1208 ( .A2(net_1719), .ZN(net_1297), .A3(net_1125), .A1(net_1102), .A4(net_982) );
XNOR2_X2 inst_97 ( .ZN(net_670), .A(net_507), .B(net_410) );
OAI21_X2 inst_616 ( .B2(net_4066), .A(net_3156), .ZN(net_2388), .B1(net_2269) );
OAI21_X1 inst_775 ( .ZN(net_2817), .B1(net_2816), .B2(net_2815), .A(net_1575) );
CLKBUF_X2 inst_4652 ( .A(net_4637), .Z(net_4638) );
OAI21_X2 inst_620 ( .B2(net_2815), .ZN(net_2164), .B1(net_2163), .A(net_1796) );
OAI21_X2 inst_652 ( .ZN(net_1832), .B2(net_1776), .A(net_1775), .B1(net_1635) );
NAND2_X2 inst_1784 ( .ZN(net_1167), .A1(net_1124), .A2(net_530) );
DFF_X2 inst_3118 ( .QN(net_3146), .D(net_2742), .CK(net_4423) );
NAND2_X2 inst_2071 ( .ZN(net_3984), .A2(net_3979), .A1(net_416) );
OAI21_X2 inst_677 ( .B2(net_2717), .ZN(net_1323), .A(net_1311), .B1(net_1025) );
SDFF_X2 inst_130 ( .D(net_3483), .SE(net_3207), .SI(net_3026), .Q(net_3026), .CK(net_5057) );
NAND2_X4 inst_1427 ( .ZN(net_3596), .A2(net_3595), .A1(net_3594) );
NAND2_X2 inst_1566 ( .A1(net_2963), .ZN(net_2455), .A2(net_497) );
NAND2_X4 inst_1409 ( .ZN(net_3299), .A2(net_3298), .A1(net_3226) );
CLKBUF_X2 inst_4662 ( .A(net_4647), .Z(net_4648) );
INV_X4 inst_2242 ( .ZN(net_2661), .A(net_2555) );
XNOR2_X2 inst_87 ( .ZN(net_1025), .A(net_855), .B(net_813) );
CLKBUF_X2 inst_5037 ( .A(net_5022), .Z(net_5023) );
INV_X2 inst_2996 ( .A(net_3038), .ZN(net_193) );
NOR2_X2 inst_1054 ( .A1(net_1132), .ZN(net_1053), .A2(net_684) );
INV_X2 inst_2918 ( .ZN(net_243), .A(net_117) );
NOR2_X4 inst_972 ( .ZN(net_3912), .A2(net_3167), .A1(net_249) );
INV_X2 inst_2721 ( .ZN(net_1634), .A(net_1562) );
NAND2_X2 inst_1671 ( .A1(net_2134), .ZN(net_2087), .A2(net_559) );
INV_X1 inst_3074 ( .A(net_3486), .ZN(net_1684) );
OAI211_X2 inst_800 ( .B(net_2302), .ZN(net_2269), .C1(net_2212), .C2(net_1517), .A(net_994) );
CLKBUF_X2 inst_5281 ( .A(net_5266), .Z(net_5267) );
NAND2_X2 inst_1843 ( .A1(net_4111), .ZN(net_679), .A2(net_590) );
CLKBUF_X2 inst_4581 ( .A(net_4532), .Z(net_4567) );
XOR2_X2 inst_10 ( .B(net_4071), .Z(net_1616), .A(net_1615) );
AOI222_X1 inst_3795 ( .B2(net_4082), .ZN(net_3793), .A1(net_3792), .A2(net_1246), .B1(net_1245), .C1(net_1244), .C2(net_396) );
XOR2_X2 inst_4 ( .B(net_3263), .Z(net_1715), .A(net_1446) );
INV_X2 inst_2884 ( .A(net_3046), .ZN(net_189) );
CLKBUF_X2 inst_4337 ( .A(net_4322), .Z(net_4323) );
OAI21_X2 inst_600 ( .B1(net_3553), .B2(net_2815), .ZN(net_2392), .A(net_1579) );
DFF_X1 inst_3272 ( .QN(net_3099), .D(net_2905), .CK(net_5025) );
CLKBUF_X2 inst_4498 ( .A(net_4483), .Z(net_4484) );
NAND4_X2 inst_1194 ( .ZN(net_1664), .A3(net_1487), .A4(net_1486), .A1(net_1421), .A2(net_1420) );
OR2_X4 inst_204 ( .A1(net_3816), .ZN(net_2972), .A2(net_2352) );
XNOR2_X2 inst_49 ( .ZN(net_2645), .A(net_2334), .B(net_1695) );
NAND2_X2 inst_1866 ( .A1(net_3702), .A2(net_3391), .ZN(net_582) );
NAND2_X2 inst_1550 ( .A1(net_2961), .ZN(net_2472), .A2(net_492) );
NAND2_X2 inst_1878 ( .A1(net_4003), .A2(net_3396), .ZN(net_541) );
CLKBUF_X2 inst_5136 ( .A(net_4820), .Z(net_5122) );
NOR3_X2 inst_910 ( .A3(net_3399), .ZN(net_3337), .A2(net_1882), .A1(net_995) );
AND2_X4 inst_4097 ( .ZN(net_1827), .A1(net_1645), .A2(net_1564) );
OAI21_X2 inst_693 ( .ZN(net_1043), .B1(net_1042), .A(net_940), .B2(net_776) );
CLKBUF_X2 inst_4731 ( .A(net_4716), .Z(net_4717) );
OAI21_X2 inst_765 ( .ZN(net_3944), .A(net_3943), .B1(net_305), .B2(net_277) );
NAND3_X2 inst_1276 ( .ZN(net_2785), .A1(net_2738), .A2(net_2737), .A3(net_1998) );
OR2_X2 inst_256 ( .A1(net_1013), .ZN(net_961), .A2(net_710) );
NAND2_X2 inst_1902 ( .A2(net_3163), .ZN(net_351), .A1(net_350) );
NOR2_X4 inst_937 ( .ZN(net_368), .A2(net_359), .A1(net_306) );
NOR3_X2 inst_908 ( .A1(net_514), .ZN(net_423), .A2(net_264), .A3(net_109) );
OAI222_X2 inst_355 ( .ZN(net_922), .B1(net_921), .C2(net_920), .A1(net_689), .C1(net_662), .A2(net_245), .B2(net_43) );
CLKBUF_X2 inst_5052 ( .A(net_5037), .Z(net_5038) );
OR2_X4 inst_218 ( .A2(net_4091), .ZN(net_1135), .A1(net_1015) );
AOI22_X2 inst_3647 ( .A1(net_4142), .B1(net_4112), .B2(net_2037), .ZN(net_755), .A2(x884) );
AOI22_X2 inst_3498 ( .A1(net_3815), .B1(net_3186), .ZN(net_2175), .A2(net_834), .B2(net_833) );
DFF_X1 inst_3422 ( .Q(net_3173), .D(net_718), .CK(net_4700) );
AOI21_X2 inst_3978 ( .ZN(net_1014), .B1(net_1013), .A(net_925), .B2(net_399) );
AOI221_X2 inst_3832 ( .ZN(net_2313), .A(net_2311), .C2(net_1908), .C1(net_1670), .B2(net_749), .B1(net_105) );
AND4_X4 inst_4039 ( .A1(net_1138), .ZN(net_1102), .A2(net_1101), .A3(net_1100), .A4(net_1092) );
AOI22_X2 inst_3693 ( .B1(net_4123), .A2(net_3023), .B2(net_3022), .A1(net_555), .ZN(net_483) );
INV_X2 inst_2967 ( .ZN(net_1699), .A(net_81) );
AOI222_X1 inst_3769 ( .B1(net_4048), .C1(net_3447), .A1(net_1968), .ZN(net_1963), .C2(net_984), .A2(net_330), .B2(net_72) );
AND4_X2 inst_4053 ( .A4(net_4180), .A1(net_3240), .ZN(net_2192), .A2(net_1878), .A3(net_1766) );
NAND2_X2 inst_2078 ( .ZN(net_4169), .A1(net_4168), .A2(net_73) );
NAND2_X2 inst_1747 ( .ZN(net_1608), .A2(net_1511), .A1(net_1310) );
CLKBUF_X2 inst_5236 ( .A(net_5221), .Z(net_5222) );
CLKBUF_X2 inst_5109 ( .A(net_5094), .Z(net_5095) );
OAI21_X2 inst_699 ( .B2(net_3153), .B1(net_1652), .ZN(net_935), .A(net_401) );
AOI221_X2 inst_3917 ( .ZN(net_3507), .C2(net_1908), .A(net_1824), .C1(net_1667), .B1(net_749), .B2(net_100) );
NAND2_X4 inst_1462 ( .ZN(net_3880), .A2(net_3810), .A1(net_3798) );
INV_X4 inst_2273 ( .A(net_3227), .ZN(net_1017) );
INV_X2 inst_2682 ( .A(net_3773), .ZN(net_1851) );
INV_X4 inst_2574 ( .A(net_3866), .ZN(net_3581) );
CLKBUF_X2 inst_4699 ( .A(net_4622), .Z(net_4685) );
INV_X4 inst_2229 ( .ZN(net_1757), .A(net_1723) );
NAND2_X2 inst_2003 ( .ZN(net_3512), .A1(net_3510), .A2(net_2364) );
CLKBUF_X2 inst_5119 ( .A(net_4666), .Z(net_5105) );
CLKBUF_X2 inst_4963 ( .A(net_4948), .Z(net_4949) );
CLKBUF_X2 inst_4749 ( .A(net_4610), .Z(net_4735) );
NOR2_X4 inst_964 ( .ZN(net_3812), .A1(net_2135), .A2(net_2111) );
INV_X2 inst_2787 ( .ZN(net_799), .A(net_798) );
DFF_X1 inst_3372 ( .D(net_2284), .QN(net_63), .CK(net_4213) );
INV_X4 inst_2599 ( .A(net_3995), .ZN(net_3754) );
INV_X4 inst_2426 ( .A(net_323), .ZN(net_250) );
NAND4_X2 inst_1245 ( .A3(net_3648), .ZN(net_3528), .A2(net_3249), .A4(net_3189), .A1(net_2090) );
INV_X4 inst_2313 ( .ZN(net_943), .A(net_774) );
AOI21_X2 inst_3971 ( .A(net_3157), .ZN(net_1276), .B1(net_1275), .B2(net_1274) );
AOI222_X1 inst_3788 ( .A2(net_1826), .ZN(net_1461), .A1(net_979), .B1(net_625), .C1(net_581), .C2(net_402), .B2(net_333) );
NAND2_X4 inst_1485 ( .ZN(net_4006), .A1(net_3397), .A2(net_3167) );
AOI22_X2 inst_3663 ( .A1(net_571), .B1(net_570), .ZN(net_564), .A2(net_180), .B2(net_154) );
INV_X2 inst_3001 ( .A(net_3131), .ZN(net_1326) );
INV_X2 inst_2818 ( .A(net_988), .ZN(net_784) );
INV_X2 inst_3008 ( .ZN(net_3305), .A(net_3304) );
DFF_X2 inst_3198 ( .QN(net_3169), .D(net_1625), .CK(net_5271) );
OAI22_X2 inst_317 ( .B2(net_3941), .A1(net_1975), .B1(net_1332), .ZN(net_1122), .A2(net_977) );
OAI21_X2 inst_750 ( .ZN(net_3427), .B2(net_3426), .A(net_3425), .B1(net_1605) );
NOR2_X2 inst_1123 ( .ZN(net_3436), .A2(net_3435), .A1(net_3433) );
INV_X2 inst_2904 ( .ZN(net_156), .A(net_115) );
CLKBUF_X2 inst_4429 ( .A(net_4414), .Z(net_4415) );
OAI22_X4 inst_278 ( .ZN(net_3774), .B2(net_3773), .B1(net_3772), .A2(net_3771), .A1(net_3770) );
INV_X4 inst_2383 ( .A(net_1071), .ZN(net_433) );
NAND2_X2 inst_1701 ( .ZN(net_2076), .A1(net_1790), .A2(net_1735) );
OAI21_X4 inst_467 ( .ZN(net_3906), .A(net_3900), .B2(net_3727), .B1(net_3562) );
AOI22_X2 inst_3677 ( .B1(net_4124), .ZN(net_524), .A1(net_509), .B2(net_242), .A2(net_147) );
AND3_X4 inst_4071 ( .ZN(net_4038), .A3(net_3559), .A1(net_2345), .A2(net_656) );
CLKBUF_X2 inst_4987 ( .A(net_4972), .Z(net_4973) );
INV_X2 inst_2963 ( .ZN(net_272), .A(net_80) );
NAND2_X2 inst_1628 ( .A2(net_3860), .A1(net_3510), .ZN(net_2515) );
NAND3_X2 inst_1329 ( .A2(net_3628), .ZN(net_1168), .A3(net_655), .A1(net_446) );
INV_X4 inst_2469 ( .ZN(net_294), .A(net_65) );
NAND4_X2 inst_1204 ( .ZN(net_1849), .A4(net_1499), .A3(net_1469), .A2(net_1435), .A1(net_1430) );
AND3_X4 inst_4066 ( .A3(net_3441), .A2(net_3156), .ZN(net_1645), .A1(net_1527) );
CLKBUF_X2 inst_4840 ( .A(net_4603), .Z(net_4826) );
OR2_X4 inst_225 ( .ZN(net_727), .A1(net_716), .A2(net_439) );
CLKBUF_X2 inst_5020 ( .A(net_4436), .Z(net_5006) );
OAI21_X2 inst_508 ( .B1(net_3274), .B2(net_2967), .ZN(net_2934), .A(net_2407) );
CLKBUF_X2 inst_4888 ( .A(net_4574), .Z(net_4874) );
CLKBUF_X2 inst_4736 ( .A(net_4286), .Z(net_4722) );
INV_X4 inst_2618 ( .ZN(net_3894), .A(net_3892) );
NOR2_X2 inst_1135 ( .ZN(net_3665), .A1(net_3615), .A2(net_530) );
CLKBUF_X2 inst_4950 ( .A(net_4935), .Z(net_4936) );
AOI22_X2 inst_3715 ( .ZN(net_3464), .A2(net_1717), .A1(net_1522), .B1(net_1137), .B2(net_912) );
OAI21_X2 inst_590 ( .B1(net_3691), .B2(net_3229), .ZN(net_2593), .A(net_72) );
INV_X4 inst_2553 ( .A(net_3644), .ZN(net_3477) );
DFF_X2 inst_3127 ( .QN(net_3144), .D(net_2681), .CK(net_4766) );
INV_X2 inst_3042 ( .A(net_3885), .ZN(net_3685) );
DFF_X1 inst_3243 ( .QN(net_3085), .D(net_2955), .CK(net_4559) );
NAND2_X2 inst_1729 ( .ZN(net_1557), .A1(net_1556), .A2(x825) );
CLKBUF_X2 inst_4531 ( .A(net_4516), .Z(net_4517) );
NOR2_X2 inst_1105 ( .A1(net_3871), .ZN(net_3218), .A2(net_3018) );
INV_X2 inst_2746 ( .A(net_3641), .ZN(net_1266) );
NOR2_X4 inst_981 ( .ZN(net_3986), .A2(net_3168), .A1(net_3106) );
NAND3_X4 inst_1266 ( .A1(net_3901), .ZN(net_3576), .A3(net_3575), .A2(net_3452) );
CLKBUF_X2 inst_4648 ( .A(net_4295), .Z(net_4634) );
NAND2_X1 inst_2094 ( .A1(net_3817), .ZN(net_3183), .A2(net_155) );
CLKBUF_X2 inst_5102 ( .A(net_5087), .Z(net_5088) );
CLKBUF_X2 inst_4872 ( .A(net_4857), .Z(net_4858) );
CLKBUF_X2 inst_4317 ( .A(net_4302), .Z(net_4303) );
OAI22_X2 inst_330 ( .A2(net_881), .ZN(net_839), .A1(net_727), .B1(net_637), .B2(net_549) );
DFF_X1 inst_3417 ( .D(net_1357), .Q(net_34), .CK(net_4465) );
AOI22_X1 inst_3733 ( .ZN(net_3865), .A1(net_3815), .B2(net_3186), .B1(net_190), .A2(net_161) );
OR3_X4 inst_165 ( .A2(net_3773), .ZN(net_2142), .A1(net_2118), .A3(net_1927) );
CLKBUF_X2 inst_4305 ( .A(net_4222), .Z(net_4291) );
AOI22_X2 inst_3491 ( .A2(net_3128), .ZN(net_2507), .B1(net_2300), .A1(net_2296), .B2(net_671) );
AOI22_X2 inst_3566 ( .A1(net_4060), .B1(net_4055), .ZN(net_1484), .B2(net_199), .A2(net_165) );
INV_X4 inst_2393 ( .A(net_1884), .ZN(net_1882) );
NAND4_X4 inst_1176 ( .A3(net_4140), .A1(net_3643), .ZN(net_3548), .A2(net_3106), .A4(net_278) );
NAND2_X2 inst_1838 ( .ZN(net_1340), .A2(net_1036), .A1(net_356) );
XNOR2_X2 inst_71 ( .A(net_1583), .ZN(net_1582), .B(net_207) );
NAND2_X4 inst_1454 ( .A2(net_4165), .ZN(net_3832), .A1(net_3753) );
AND3_X4 inst_4079 ( .ZN(net_4116), .A3(net_3662), .A2(net_528), .A1(net_337) );
NAND4_X2 inst_1232 ( .ZN(net_2220), .A3(net_556), .A2(net_510), .A4(net_459), .A1(net_443) );
DFF_X1 inst_3231 ( .QN(net_3068), .D(net_2960), .CK(net_4875) );
DFF_X2 inst_3147 ( .D(net_2392), .QN(net_113), .CK(net_4418) );
NAND2_X2 inst_1945 ( .A1(net_3815), .ZN(net_3249), .A2(net_208) );
AND2_X4 inst_4172 ( .ZN(net_4126), .A1(net_3397), .A2(net_3167) );
INV_X2 inst_2657 ( .A(net_2699), .ZN(net_2195) );
INV_X4 inst_2605 ( .ZN(net_3782), .A(net_3781) );
OAI21_X2 inst_758 ( .ZN(net_3739), .A(net_2735), .B1(net_2693), .B2(net_2690) );
OAI22_X2 inst_336 ( .B1(net_3122), .ZN(net_438), .A1(net_344), .B2(net_263), .A2(net_250) );
INV_X8 inst_2146 ( .ZN(net_3274), .A(net_3273) );
INV_X2 inst_2703 ( .ZN(net_1673), .A(net_1672) );
OAI221_X2 inst_376 ( .ZN(net_2671), .B1(net_2670), .B2(net_2669), .C1(net_2668), .A(net_1386), .C2(net_318) );
CLKBUF_X2 inst_5157 ( .A(net_4310), .Z(net_5143) );
NAND2_X2 inst_1939 ( .A2(net_3618), .ZN(net_3226), .A1(net_3225) );
DFF_X1 inst_3268 ( .QN(net_3096), .D(net_2904), .CK(net_5035) );
INV_X2 inst_2902 ( .A(net_318), .ZN(net_179) );
SDFF_X2 inst_143 ( .D(net_3882), .SE(net_2625), .SI(net_95), .Q(net_95), .CK(net_5048) );
NAND2_X2 inst_1953 ( .ZN(net_3282), .A2(net_3281), .A1(net_495) );
CLKBUF_X2 inst_5286 ( .A(net_5202), .Z(net_5272) );
CLKBUF_X2 inst_4570 ( .A(net_4234), .Z(net_4556) );
INV_X2 inst_3016 ( .ZN(net_3410), .A(net_2562) );
CLKBUF_X2 inst_4272 ( .A(net_4243), .Z(net_4258) );
NAND2_X2 inst_1958 ( .A1(net_3530), .A2(net_3513), .ZN(net_3297) );
INV_X4 inst_2337 ( .A(net_711), .ZN(net_657) );
DFF_X1 inst_3250 ( .D(net_3267), .QN(net_3090), .CK(net_4736) );
DFF_X1 inst_3240 ( .QN(net_3038), .D(net_2956), .CK(net_5186) );
NAND2_X2 inst_1778 ( .A2(net_2523), .A1(net_2518), .ZN(net_1151) );
CLKBUF_X2 inst_5174 ( .A(net_5159), .Z(net_5160) );
NAND2_X2 inst_1736 ( .A2(net_4082), .ZN(net_1530), .A1(net_1528) );
NOR2_X2 inst_1040 ( .A1(net_1458), .A2(net_1340), .ZN(net_1215) );
AOI211_X2 inst_4027 ( .C1(net_3962), .B(net_1606), .ZN(net_1034), .C2(net_928), .A(net_404) );
AOI221_X2 inst_3880 ( .A(net_4047), .C2(net_1908), .ZN(net_1848), .C1(net_1847), .B2(net_749), .B1(net_90) );
HA_X1 inst_3100 ( .S(net_643), .CO(net_642), .B(net_423), .A(net_224) );
CLKBUF_X2 inst_5042 ( .A(net_5027), .Z(net_5028) );
AND4_X4 inst_4052 ( .ZN(net_4107), .A2(net_3940), .A4(net_3395), .A3(net_594), .A1(net_376) );
CLKBUF_X2 inst_4251 ( .A(net_4236), .Z(net_4237) );
CLKBUF_X2 inst_4487 ( .A(net_4472), .Z(net_4473) );
XNOR2_X2 inst_111 ( .A(net_4132), .ZN(net_417), .B(net_402) );
NAND2_X2 inst_1596 ( .A1(net_2925), .ZN(net_2422), .A2(net_183) );
CLKBUF_X2 inst_4364 ( .A(net_4237), .Z(net_4350) );
DFF_X2 inst_3146 ( .QN(net_3127), .D(net_2509), .CK(net_5146) );
NAND2_X2 inst_1723 ( .ZN(net_1596), .A2(net_1595), .A1(net_1506) );
DFF_X1 inst_3278 ( .QN(net_3034), .D(net_2906), .CK(net_5010) );
CLKBUF_X2 inst_5145 ( .A(net_5130), .Z(net_5131) );
NAND2_X2 inst_2056 ( .ZN(net_3904), .A1(net_3901), .A2(net_3833) );
AOI222_X1 inst_3752 ( .A1(net_3676), .B1(net_2055), .C1(net_2054), .ZN(net_2041), .B2(net_1797), .C2(net_643), .A2(net_267) );
INV_X8 inst_2116 ( .ZN(net_2923), .A(net_2891) );
INV_X4 inst_2265 ( .A(net_2127), .ZN(net_2054) );
OAI22_X2 inst_284 ( .A1(net_3611), .A2(net_2838), .ZN(net_2347), .B1(net_2324), .B2(net_2323) );
CLKBUF_X2 inst_5071 ( .A(net_5056), .Z(net_5057) );
INV_X2 inst_2825 ( .ZN(net_640), .A(net_526) );
NAND2_X2 inst_1555 ( .A1(net_2909), .ZN(net_2467), .A2(net_170) );
AOI211_X2 inst_4031 ( .ZN(net_3246), .C1(net_1363), .B(net_1185), .A(net_999), .C2(net_337) );
NAND3_X2 inst_1293 ( .ZN(net_2143), .A1(net_2142), .A2(net_1890), .A3(net_1845) );
AOI221_X2 inst_3805 ( .B2(net_4031), .ZN(net_2754), .B1(net_2752), .C1(net_2710), .A(net_2505), .C2(net_145) );
INV_X4 inst_2579 ( .ZN(net_3606), .A(net_3605) );
OAI22_X2 inst_280 ( .ZN(net_2822), .A1(net_2748), .B1(net_2615), .B2(net_1214), .A2(net_901) );
OAI22_X2 inst_346 ( .A2(net_3989), .ZN(net_3964), .B2(net_3960), .B1(net_1340), .A1(net_1006) );
DFF_X2 inst_3157 ( .D(net_2179), .QN(net_44), .CK(net_4625) );
NOR2_X4 inst_978 ( .ZN(net_3957), .A1(net_3956), .A2(net_3675) );
NAND2_X2 inst_1713 ( .A1(net_3782), .ZN(net_1814), .A2(net_1271) );
INV_X2 inst_2955 ( .A(net_3050), .ZN(net_171) );
AOI21_X4 inst_3926 ( .B1(net_3957), .B2(net_3763), .ZN(net_3574), .A(net_399) );
CLKBUF_X2 inst_4527 ( .A(net_4512), .Z(net_4513) );
AOI21_X4 inst_3929 ( .B2(net_3860), .ZN(net_3591), .B1(net_3366), .A(net_2708) );
DFF_X2 inst_3137 ( .QN(net_2988), .D(net_2568), .CK(net_5095) );
CLKBUF_X2 inst_4676 ( .A(net_4661), .Z(net_4662) );
AOI221_X2 inst_3852 ( .ZN(net_2062), .A(net_2060), .C2(net_1908), .C1(net_1678), .B2(net_749), .B1(net_102) );
CLKBUF_X2 inst_4496 ( .A(net_4197), .Z(net_4482) );
INV_X4 inst_2566 ( .A(net_3568), .ZN(net_3523) );
OAI21_X2 inst_495 ( .B1(net_3278), .ZN(net_2947), .B2(net_2907), .A(net_2482) );
NOR2_X2 inst_1051 ( .ZN(net_1158), .A1(net_1035), .A2(net_751) );
NOR2_X4 inst_951 ( .ZN(net_3661), .A1(net_3660), .A2(net_346) );
NAND2_X2 inst_1864 ( .ZN(net_1381), .A2(net_588), .A1(net_406) );
AOI22_X2 inst_3603 ( .A1(net_4063), .B1(net_4058), .A2(net_3027), .B2(net_3026), .ZN(net_1414) );
DFF_X1 inst_3224 ( .QN(net_3056), .D(net_2977), .CK(net_4740) );
CLKBUF_X2 inst_4393 ( .A(net_4378), .Z(net_4379) );
INV_X2 inst_3043 ( .A(net_3889), .ZN(net_3699) );
NAND3_X2 inst_1359 ( .A3(net_3836), .ZN(net_3802), .A2(net_3801), .A1(net_1371) );
DFF_X2 inst_3188 ( .D(net_1731), .QN(net_121), .CK(net_5137) );
DFF_X2 inst_3129 ( .D(net_2697), .QN(net_43), .CK(net_4636) );
CLKBUF_X2 inst_4674 ( .A(net_4659), .Z(net_4660) );
INV_X2 inst_2893 ( .A(net_3033), .ZN(net_187) );
OAI21_X2 inst_573 ( .B2(net_2815), .ZN(net_2814), .B1(net_2813), .A(net_1573) );
AOI221_X2 inst_3797 ( .C1(net_4035), .C2(net_3738), .B1(net_3736), .ZN(net_2840), .B2(net_2623), .A(net_1992) );
XNOR2_X2 inst_100 ( .ZN(net_1291), .A(net_538), .B(net_43) );
CLKBUF_X2 inst_4352 ( .A(net_4337), .Z(net_4338) );
CLKBUF_X2 inst_4245 ( .A(net_4212), .Z(net_4231) );
NOR2_X4 inst_921 ( .A2(net_3367), .ZN(net_2890), .A1(net_2859) );
NAND2_X4 inst_1453 ( .ZN(net_3833), .A1(net_3832), .A2(net_3606) );
OAI22_X2 inst_279 ( .ZN(net_2809), .A2(net_2785), .B1(net_2764), .A1(net_2193), .B2(net_2064) );
AOI21_X2 inst_3970 ( .ZN(net_1588), .A(net_1220), .B2(net_1011), .B1(net_836) );
DFF_X1 inst_3387 ( .D(net_1777), .CK(net_5291), .Q(x626) );
INV_X2 inst_3007 ( .ZN(net_3258), .A(net_2309) );
XNOR2_X2 inst_81 ( .ZN(net_1269), .A(net_1080), .B(net_248) );
AND2_X4 inst_4185 ( .ZN(net_4149), .A1(net_3947), .A2(net_3108) );
AOI22_X2 inst_3544 ( .B1(net_4054), .A2(net_2033), .ZN(net_1579), .A1(net_1578), .B2(net_1280) );
AOI22_X2 inst_3512 ( .ZN(net_1972), .B1(net_1882), .A2(net_1879), .A1(net_1810), .B2(net_198) );
OAI211_X2 inst_790 ( .C2(net_2876), .ZN(net_2706), .A(net_2634), .C1(net_2633), .B(net_2047) );
NOR2_X2 inst_1009 ( .ZN(net_1780), .A1(net_1779), .A2(net_1778) );
NAND4_X2 inst_1206 ( .ZN(net_2067), .A3(net_1489), .A4(net_1488), .A2(net_1423), .A1(net_1422) );
INV_X2 inst_2954 ( .A(net_3012), .ZN(net_221) );
INV_X4 inst_2197 ( .A(net_3860), .ZN(net_2322) );
OAI21_X2 inst_733 ( .A(net_629), .B2(net_628), .ZN(net_577), .B1(net_204) );
AOI22_X2 inst_3466 ( .B2(net_4027), .B1(net_2752), .ZN(net_2751), .A1(net_2750), .A2(net_1523) );
NAND2_X2 inst_1959 ( .A2(net_3600), .ZN(net_3300), .A1(net_3299) );
INV_X4 inst_2582 ( .ZN(net_3627), .A(net_3620) );
SDFF_X2 inst_142 ( .SE(net_2514), .D(net_2288), .SI(net_102), .Q(net_102), .CK(net_4749) );
CLKBUF_X2 inst_4800 ( .A(net_4303), .Z(net_4786) );
CLKBUF_X2 inst_4394 ( .A(net_4379), .Z(net_4380) );
XNOR2_X2 inst_78 ( .A(net_1522), .ZN(net_1379), .B(net_1140) );
NAND2_X2 inst_1487 ( .A1(net_4155), .A2(net_3600), .ZN(net_2894) );
INV_X2 inst_2813 ( .A(net_838), .ZN(net_639) );
OR3_X4 inst_177 ( .ZN(net_3360), .A2(net_2815), .A1(net_2550), .A3(net_1737) );
OAI211_X2 inst_783 ( .ZN(net_2779), .C2(net_2778), .B(net_2676), .C1(net_2661), .A(net_2654) );
AOI22_X2 inst_3522 ( .A2(net_3141), .B2(net_3140), .ZN(net_1924), .A1(net_1923), .B1(net_1921) );
NAND2_X2 inst_1933 ( .ZN(net_3200), .A1(net_3198), .A2(net_166) );
NAND2_X2 inst_2014 ( .ZN(net_3634), .A2(net_3632), .A1(net_3543) );
CLKBUF_X2 inst_4471 ( .A(net_4355), .Z(net_4457) );
NOR2_X2 inst_1142 ( .ZN(net_3863), .A2(net_3862), .A1(net_3861) );
NAND2_X2 inst_1758 ( .A2(net_1394), .ZN(net_1241), .A1(net_31) );
CLKBUF_X2 inst_4320 ( .A(net_4305), .Z(net_4306) );
OAI21_X2 inst_615 ( .ZN(net_2325), .B1(net_2282), .B2(net_1853), .A(net_356) );
AOI221_X2 inst_3816 ( .A(net_2642), .B1(net_2641), .C2(net_2583), .ZN(net_2582), .C1(net_2581), .B2(net_287) );
INV_X2 inst_2822 ( .ZN(net_535), .A(net_534) );
INV_X4 inst_2467 ( .ZN(net_1511), .A(net_58) );
AOI221_X2 inst_3843 ( .B2(net_2203), .C1(net_2202), .ZN(net_2199), .A(net_2073), .C2(net_1797), .B1(net_1769) );
NAND3_X1 inst_1381 ( .ZN(net_3462), .A2(net_2680), .A1(net_1319), .A3(net_1217) );
NAND2_X2 inst_2031 ( .ZN(net_3762), .A1(net_3761), .A2(net_3606) );
CLKBUF_X2 inst_4386 ( .A(net_4371), .Z(net_4372) );
OAI21_X2 inst_643 ( .B1(net_1993), .ZN(net_1992), .A(net_1900), .B2(net_1545) );
CLKBUF_X2 inst_4771 ( .A(net_4756), .Z(net_4757) );
CLKBUF_X2 inst_4941 ( .A(net_4926), .Z(net_4927) );
CLKBUF_X2 inst_5133 ( .A(net_4596), .Z(net_5119) );
CLKBUF_X2 inst_4961 ( .A(net_4644), .Z(net_4947) );
CLKBUF_X2 inst_4669 ( .A(net_4536), .Z(net_4655) );
OAI22_X2 inst_338 ( .B2(net_3196), .B1(net_635), .ZN(net_420), .A2(net_381), .A1(net_210) );
INV_X4 inst_2412 ( .ZN(net_2180), .A(net_269) );
CLKBUF_X2 inst_4928 ( .A(net_4913), .Z(net_4914) );
AOI21_X2 inst_4005 ( .ZN(net_3915), .A(net_3914), .B1(net_650), .B2(net_592) );
CLKBUF_X2 inst_4323 ( .A(net_4308), .Z(net_4309) );
INV_X4 inst_2214 ( .ZN(net_2238), .A(net_2142) );
AND2_X4 inst_4146 ( .A2(net_4111), .A1(net_4102), .ZN(net_4083) );
NAND2_X2 inst_1997 ( .A2(net_3514), .ZN(net_3487), .A1(net_931) );
INV_X4 inst_2474 ( .A(net_3069), .ZN(net_732) );
NOR2_X2 inst_1017 ( .ZN(net_1731), .A1(net_1631), .A2(net_1090) );
OAI21_X2 inst_579 ( .B2(net_2909), .B1(net_2803), .ZN(net_2799), .A(net_2468) );
CLKBUF_X2 inst_5247 ( .A(net_4733), .Z(net_5233) );
AOI222_X2 inst_3736 ( .B2(net_4109), .C2(net_1791), .C1(net_1244), .ZN(net_1199), .A1(net_1198), .B1(net_1118), .A2(net_920) );
INV_X4 inst_2495 ( .A(net_3148), .ZN(net_252) );
INV_X4 inst_2297 ( .ZN(net_1103), .A(net_1046) );
AOI211_X2 inst_4019 ( .C2(net_4098), .A(net_4070), .ZN(net_1647), .B(net_1646), .C1(net_55) );
DFF_X1 inst_3341 ( .D(net_2777), .QN(net_116), .CK(net_4452) );
OAI22_X2 inst_281 ( .B1(net_3463), .A1(net_3462), .ZN(net_2770), .A2(net_1764), .B2(net_1620) );
DFF_X1 inst_3236 ( .QN(net_3042), .D(net_2946), .CK(net_5044) );
OAI21_X2 inst_698 ( .B1(net_4087), .ZN(net_2596), .A(net_1274), .B2(net_270) );
NAND2_X2 inst_1836 ( .A1(net_1107), .ZN(net_1042), .A2(net_594) );
AOI21_X2 inst_3964 ( .B2(net_3702), .A(net_3640), .ZN(net_1454), .B1(net_886) );
AOI21_X2 inst_3944 ( .B1(net_3774), .ZN(net_2226), .A(net_2149), .B2(net_330) );
DFF_X1 inst_3394 ( .Q(net_3113), .D(net_1536), .CK(net_4316) );
DFF_X1 inst_3408 ( .D(net_1399), .Q(net_36), .CK(net_4498) );
XNOR2_X2 inst_88 ( .ZN(net_979), .B(net_978), .A(net_871) );
INV_X2 inst_2863 ( .ZN(net_2181), .A(net_286) );
INV_X4 inst_2508 ( .ZN(net_239), .A(net_70) );
CLKBUF_X2 inst_4274 ( .A(net_4259), .Z(net_4260) );
CLKBUF_X2 inst_4250 ( .A(net_4235), .Z(net_4236) );
INV_X8 inst_2170 ( .ZN(net_3999), .A(net_138) );
OAI221_X2 inst_360 ( .ZN(net_2827), .B1(net_2826), .C1(net_2825), .A(net_2585), .C2(net_1519), .B2(net_645) );
AOI221_X2 inst_3897 ( .ZN(net_1304), .B1(net_1244), .C1(net_1198), .A(net_1121), .C2(net_714), .B2(net_168) );
OAI21_X1 inst_773 ( .ZN(net_4018), .B2(net_2963), .B1(net_2893), .A(net_2461) );
INV_X2 inst_2946 ( .A(net_2990), .ZN(net_177) );
AOI221_X2 inst_3908 ( .A(net_4185), .B2(net_4111), .ZN(net_1343), .C2(net_923), .C1(net_902), .B1(net_651) );
AOI22_X2 inst_3620 ( .B1(net_1244), .A1(net_1198), .ZN(net_1128), .A2(net_874), .B2(net_378) );
AOI222_X1 inst_3754 ( .A1(net_3676), .A2(net_3133), .B1(net_2055), .C1(net_2054), .ZN(net_2039), .C2(net_1038), .B2(net_396) );
OR2_X2 inst_260 ( .A2(net_3221), .A1(net_2376), .ZN(net_763) );
NOR2_X2 inst_1129 ( .ZN(net_3554), .A1(net_3551), .A2(net_3495) );
OAI211_X2 inst_837 ( .C2(net_2665), .C1(net_1359), .ZN(net_1353), .A(net_1235), .B(net_593) );
OAI21_X2 inst_744 ( .ZN(net_3325), .A(net_3324), .B2(net_3319), .B1(net_655) );
CLKBUF_X2 inst_4973 ( .A(net_4958), .Z(net_4959) );
DFF_X2 inst_3211 ( .D(net_808), .QN(net_505), .CK(net_4667) );
AOI221_X2 inst_3827 ( .B1(net_3469), .C2(net_3133), .B2(net_3132), .C1(net_2534), .ZN(net_2533), .A(net_2338) );
AND2_X4 inst_4139 ( .ZN(net_4069), .A1(net_960), .A2(net_828) );
AND2_X4 inst_4112 ( .A2(net_4131), .ZN(net_3390), .A1(net_3389) );
CLKBUF_X2 inst_4611 ( .A(net_4596), .Z(net_4597) );
CLKBUF_X2 inst_4567 ( .A(net_4552), .Z(net_4553) );
AOI221_X2 inst_3889 ( .B1(net_4026), .C1(net_3140), .A(net_2525), .ZN(net_1397), .B2(net_1394), .C2(net_1393) );
XNOR2_X2 inst_65 ( .ZN(net_1754), .A(net_1649), .B(net_1379) );
OAI21_X2 inst_536 ( .B1(net_3195), .B2(net_2961), .ZN(net_2897), .A(net_2475) );
AOI22_X2 inst_3592 ( .A1(net_4063), .B1(net_4058), .ZN(net_1425), .A2(net_219), .B2(net_160) );
INV_X4 inst_2386 ( .ZN(net_1071), .A(net_401) );
CLKBUF_X2 inst_5121 ( .A(net_4201), .Z(net_5107) );
OAI21_X2 inst_516 ( .B1(net_3302), .ZN(net_2926), .B2(net_2925), .A(net_2422) );
AOI22_X1 inst_3732 ( .ZN(net_3610), .B1(net_3219), .A1(net_2134), .A2(net_244), .B2(net_139) );
INV_X4 inst_2258 ( .ZN(net_1620), .A(net_1127) );
OR2_X4 inst_190 ( .A1(net_2615), .ZN(net_2609), .A2(net_2268) );
AND2_X4 inst_4103 ( .A1(net_920), .A2(net_449), .ZN(net_448) );
NAND3_X4 inst_1267 ( .A1(net_3928), .ZN(net_3834), .A3(net_3726), .A2(net_451) );
NAND2_X2 inst_1507 ( .A2(net_3686), .A1(net_3536), .ZN(net_2695) );
CLKBUF_X2 inst_4503 ( .A(net_4488), .Z(net_4489) );
CLKBUF_X2 inst_4907 ( .A(net_4458), .Z(net_4893) );
CLKBUF_X2 inst_4873 ( .A(net_4858), .Z(net_4859) );
NAND2_X2 inst_2027 ( .A1(net_4164), .A2(net_4162), .ZN(net_3734) );
INV_X2 inst_2926 ( .A(net_3034), .ZN(net_154) );
OAI221_X2 inst_416 ( .B1(net_4067), .ZN(net_1302), .A(net_1301), .C2(net_1228), .C1(net_1105), .B2(net_1011) );
NOR2_X2 inst_1158 ( .ZN(net_4091), .A1(net_3789), .A2(net_745) );
NAND2_X2 inst_1870 ( .A1(net_920), .ZN(net_712), .A2(net_538) );
NAND2_X2 inst_2062 ( .ZN(net_3920), .A1(net_3108), .A2(net_3107) );
AOI222_X1 inst_3786 ( .C2(net_4125), .A2(net_3755), .ZN(net_1335), .A1(net_1164), .C1(net_788), .B1(net_638), .B2(net_383) );
INV_X4 inst_2350 ( .ZN(net_1090), .A(net_671) );
NAND2_X4 inst_1406 ( .ZN(net_3273), .A1(net_3272), .A2(net_2062) );
DFF_X1 inst_3404 ( .D(net_1464), .CK(net_5248), .Q(x593) );
CLKBUF_X2 inst_5270 ( .A(net_5156), .Z(net_5256) );
OAI21_X2 inst_542 ( .ZN(net_4014), .B2(net_3208), .B1(net_2893), .A(net_2496) );
SDFF_X2 inst_128 ( .D(net_3483), .SI(net_3029), .Q(net_3029), .SE(net_2925), .CK(net_5066) );
CLKBUF_X2 inst_4319 ( .A(net_4304), .Z(net_4305) );
INV_X4 inst_2445 ( .A(net_3064), .ZN(net_518) );
CLKBUF_X2 inst_4432 ( .A(net_4417), .Z(net_4418) );
INV_X2 inst_3039 ( .ZN(net_3642), .A(net_3168) );
NOR2_X4 inst_973 ( .ZN(net_3919), .A1(net_3918), .A2(net_380) );
AOI21_X2 inst_4000 ( .ZN(net_3706), .B2(net_3705), .B1(net_3704), .A(net_3703) );
INV_X2 inst_3058 ( .ZN(net_3988), .A(net_3987) );
OAI21_X4 inst_461 ( .ZN(net_3504), .B2(net_3503), .B1(net_3500), .A(net_3156) );
DFF_X1 inst_3218 ( .D(net_3245), .QN(net_3126), .CK(net_5005) );
OAI211_X2 inst_829 ( .ZN(net_1821), .C1(net_1124), .A(net_726), .B(net_594), .C2(net_530) );
OR2_X4 inst_197 ( .A1(net_3645), .ZN(net_2909), .A2(net_2354) );
CLKBUF_X2 inst_4702 ( .A(net_4687), .Z(net_4688) );
INV_X2 inst_2958 ( .ZN(net_210), .A(net_123) );
NAND2_X2 inst_1973 ( .A1(net_3877), .A2(net_3859), .ZN(net_3344) );
HA_X1 inst_3089 ( .A(net_3492), .S(net_1709), .CO(net_1708), .B(net_1316) );
XOR2_X2 inst_24 ( .A(net_4113), .Z(net_4093), .B(net_393) );
INV_X2 inst_3051 ( .ZN(net_3840), .A(net_3835) );
INV_X2 inst_2668 ( .ZN(net_2005), .A(net_1972) );
NOR2_X2 inst_1122 ( .ZN(net_3424), .A2(net_3423), .A1(net_3412) );
DFF_X1 inst_3324 ( .D(net_2834), .Q(net_72), .CK(net_4272) );
NAND4_X2 inst_1209 ( .ZN(net_1262), .A4(net_1261), .A2(net_1060), .A3(net_1008), .A1(net_1004) );
SDFF_X2 inst_150 ( .SI(net_3174), .Q(net_3174), .SE(net_2251), .D(net_1647), .CK(net_4789) );
NAND2_X2 inst_1611 ( .A1(net_2967), .ZN(net_2405), .A2(net_462) );
CLKBUF_X2 inst_4469 ( .A(net_4454), .Z(net_4455) );
CLKBUF_X2 inst_4540 ( .A(net_4525), .Z(net_4526) );
NOR3_X2 inst_887 ( .A2(net_4066), .ZN(net_2610), .A1(net_2524), .A3(net_2522) );
CLKBUF_X2 inst_4808 ( .A(net_4793), .Z(net_4794) );
CLKBUF_X2 inst_4657 ( .A(net_4286), .Z(net_4643) );
INV_X2 inst_2981 ( .ZN(net_920), .A(net_43) );
NAND2_X2 inst_1669 ( .A1(net_3815), .ZN(net_2089), .A2(net_735) );
CLKBUF_X2 inst_4998 ( .A(net_4983), .Z(net_4984) );
CLKBUF_X2 inst_5175 ( .A(net_5160), .Z(net_5161) );
NAND2_X2 inst_1663 ( .ZN(net_2100), .A1(net_2099), .A2(net_474) );
CLKBUF_X2 inst_4406 ( .A(net_4391), .Z(net_4392) );
INV_X2 inst_2714 ( .A(net_1698), .ZN(net_1591) );
DFF_X2 inst_3162 ( .D(net_2159), .QN(net_60), .CK(net_4204) );
AOI21_X2 inst_3956 ( .B2(net_3497), .A(net_3492), .B1(net_1691), .ZN(net_1685) );
XNOR2_X2 inst_90 ( .ZN(net_917), .B(net_712), .A(net_698) );
CLKBUF_X2 inst_4316 ( .A(net_4301), .Z(net_4302) );
INV_X4 inst_2357 ( .ZN(net_854), .A(net_438) );
CLKBUF_X2 inst_4650 ( .A(net_4635), .Z(net_4636) );
NAND2_X2 inst_1801 ( .A2(net_4025), .A1(net_3430), .ZN(net_962) );
CLKBUF_X2 inst_5093 ( .A(net_5078), .Z(net_5079) );
AOI221_X2 inst_3833 ( .ZN(net_2312), .A(net_2311), .C1(net_2196), .C2(net_1908), .B2(net_749), .B1(net_97) );
OAI21_X2 inst_720 ( .ZN(net_815), .B2(net_712), .B1(net_697), .A(net_610) );
NOR2_X4 inst_958 ( .A2(net_3978), .ZN(net_3722), .A1(net_3548) );
NAND2_X2 inst_1961 ( .ZN(net_3306), .A1(net_1601), .A2(net_64) );
INV_X4 inst_2460 ( .A(net_3087), .ZN(net_462) );
NAND4_X2 inst_1217 ( .A4(net_1200), .ZN(net_1170), .A2(net_1041), .A1(net_936), .A3(net_827) );
OAI221_X2 inst_368 ( .C1(net_3352), .B2(net_3348), .ZN(net_2727), .B1(net_2618), .A(net_2595), .C2(net_2122) );
NOR2_X2 inst_1010 ( .ZN(net_2017), .A1(net_1746), .A2(net_1096) );
NAND2_X2 inst_1697 ( .ZN(net_2190), .A2(net_1927), .A1(net_1851) );
NOR4_X2 inst_867 ( .ZN(net_1076), .A1(net_1072), .A2(net_1029), .A3(net_1028), .A4(net_1018) );
INV_X2 inst_3027 ( .ZN(net_3496), .A(net_3493) );
OAI211_X2 inst_820 ( .ZN(net_1567), .A(net_1515), .B(net_1366), .C1(net_1365), .C2(net_1011) );
AOI22_X2 inst_3689 ( .B2(net_4123), .A2(net_509), .ZN(net_489), .A1(net_488), .B1(net_487) );
AOI22_X2 inst_3556 ( .A1(net_4060), .B1(net_4055), .ZN(net_1494), .B2(net_208), .A2(net_150) );
SDFF_X2 inst_157 ( .SI(net_4025), .Q(net_4025), .D(net_3320), .SE(net_2514), .CK(net_4971) );
NAND2_X4 inst_1441 ( .A1(net_3974), .A2(net_3919), .ZN(net_3764) );
INV_X2 inst_2929 ( .A(net_3005), .ZN(net_174) );
AOI22_X2 inst_3568 ( .A1(net_4060), .B1(net_4055), .ZN(net_1482), .B2(net_738), .A2(net_737) );
XNOR2_X2 inst_68 ( .A(net_1657), .ZN(net_1649), .B(net_1075) );
CLKBUF_X2 inst_4287 ( .A(net_4246), .Z(net_4273) );
NAND2_X2 inst_1966 ( .ZN(net_3328), .A2(net_3319), .A1(net_430) );
AOI221_X2 inst_3914 ( .A(net_4090), .C2(net_4004), .B2(net_3680), .ZN(net_3326), .B1(net_924), .C1(net_923) );
NAND4_X2 inst_1253 ( .ZN(net_3855), .A4(net_3646), .A3(net_3336), .A2(net_3335), .A1(net_3334) );
CLKBUF_X2 inst_4716 ( .A(net_4701), .Z(net_4702) );
INV_X4 inst_2177 ( .ZN(net_2836), .A(net_2743) );
INV_X2 inst_2793 ( .ZN(net_773), .A(net_723) );
NAND2_X2 inst_1884 ( .A1(net_590), .ZN(net_525), .A2(net_398) );
NAND2_X2 inst_2018 ( .ZN(net_3650), .A1(net_3647), .A2(net_487) );
INV_X4 inst_2435 ( .ZN(net_635), .A(net_124) );
AND2_X4 inst_4158 ( .ZN(net_4109), .A1(net_3929), .A2(net_530) );
NAND2_X2 inst_1643 ( .ZN(net_2172), .A1(net_2097), .A2(net_2023) );
CLKBUF_X2 inst_4660 ( .A(net_4568), .Z(net_4646) );
DFF_X1 inst_3410 ( .Q(net_4030), .D(net_1391), .CK(net_4496) );
NAND2_X2 inst_1690 ( .A1(net_1982), .ZN(net_1980), .A2(net_222) );
INV_X2 inst_2678 ( .ZN(net_2666), .A(net_2553) );
INV_X8 inst_2120 ( .ZN(net_721), .A(net_641) );
NAND2_X2 inst_1678 ( .ZN(net_2302), .A1(net_2114), .A2(net_369) );
CLKBUF_X2 inst_5312 ( .A(net_5297), .Z(net_5298) );
INV_X4 inst_2613 ( .ZN(net_3828), .A(net_3827) );
XOR2_X2 inst_17 ( .A(net_505), .Z(net_336), .B(net_260) );
OR2_X2 inst_249 ( .ZN(net_2565), .A1(net_2528), .A2(net_641) );
NAND3_X2 inst_1287 ( .ZN(net_2260), .A1(net_2201), .A3(net_1956), .A2(net_1919) );
INV_X4 inst_2233 ( .A(net_1866), .ZN(net_1800) );
CLKBUF_X2 inst_4231 ( .A(net_4216), .Z(net_4217) );
AOI221_X2 inst_3866 ( .B1(net_2020), .C1(net_2019), .ZN(net_1942), .A(net_1941), .B2(net_83), .C2(x350) );
INV_X4 inst_2234 ( .A(net_3784), .ZN(net_1861) );
CLKBUF_X2 inst_5253 ( .A(net_4445), .Z(net_5239) );
CLKBUF_X2 inst_5204 ( .A(net_5189), .Z(net_5190) );
CLKBUF_X2 inst_4371 ( .A(net_4356), .Z(net_4357) );
CLKBUF_X2 inst_4266 ( .A(net_4237), .Z(net_4252) );
NOR2_X1 inst_1169 ( .A2(net_3939), .A1(net_3756), .ZN(net_3396) );
NAND2_X2 inst_1649 ( .ZN(net_2156), .A2(net_2155), .A1(net_2018) );
AOI22_X2 inst_3483 ( .A1(net_4038), .B1(net_2657), .ZN(net_2654), .A2(net_984), .B2(net_402) );
NAND2_X4 inst_1480 ( .ZN(net_3948), .A2(net_3720), .A1(net_3674) );
OAI221_X2 inst_396 ( .C2(net_3407), .B1(net_2328), .ZN(net_2308), .B2(net_2307), .C1(net_2242), .A(net_2015) );
DFF_X1 inst_3382 ( .QN(net_3172), .D(net_2005), .CK(net_4856) );
DFF_X1 inst_3377 ( .D(net_2254), .Q(net_75), .CK(net_5256) );
INV_X2 inst_2877 ( .A(net_3124), .ZN(net_371) );
OAI21_X2 inst_669 ( .A(net_1884), .ZN(net_1698), .B1(net_1339), .B2(net_1173) );
CLKBUF_X2 inst_5128 ( .A(net_4216), .Z(net_5114) );
OAI21_X2 inst_664 ( .A(net_4053), .ZN(net_1682), .B2(net_1636), .B1(net_1634) );
NAND2_X2 inst_1918 ( .A2(net_3160), .ZN(net_286), .A1(net_220) );
INV_X2 inst_2845 ( .ZN(net_384), .A(net_352) );
NAND2_X4 inst_1418 ( .ZN(net_3539), .A2(net_3538), .A1(net_2106) );
NAND2_X2 inst_1740 ( .ZN(net_1615), .A1(net_1502), .A2(net_917) );
INV_X2 inst_2977 ( .ZN(net_768), .A(net_83) );
NOR2_X2 inst_1092 ( .ZN(net_340), .A1(net_339), .A2(net_297) );
AND3_X4 inst_4064 ( .A3(net_3802), .ZN(net_2203), .A1(net_1790), .A2(net_1703) );
CLKBUF_X2 inst_4427 ( .A(net_4412), .Z(net_4413) );
CLKBUF_X2 inst_4836 ( .A(net_4821), .Z(net_4822) );
NAND2_X2 inst_2001 ( .ZN(net_3500), .A1(net_1135), .A2(net_403) );
CLKBUF_X2 inst_4897 ( .A(net_4610), .Z(net_4883) );
CLKBUF_X2 inst_4635 ( .A(net_4545), .Z(net_4621) );
NAND2_X2 inst_1657 ( .A1(net_3201), .ZN(net_2111), .A2(net_1980) );
AOI221_X2 inst_3839 ( .ZN(net_2205), .B2(net_2203), .C1(net_2202), .A(net_2071), .B1(net_2067), .C2(net_379) );
NAND2_X2 inst_1844 ( .ZN(net_777), .A2(net_722), .A1(net_641) );
CLKBUF_X2 inst_5209 ( .A(net_4786), .Z(net_5195) );
NAND2_X2 inst_1913 ( .A2(net_347), .ZN(net_291), .A1(net_290) );
NAND2_X2 inst_2077 ( .ZN(net_4171), .A2(net_4170), .A1(net_2703) );
INV_X4 inst_2368 ( .A(net_3214), .ZN(net_659) );
NAND2_X2 inst_1990 ( .ZN(net_3444), .A2(net_3443), .A1(net_3442) );
INV_X2 inst_2735 ( .ZN(net_1337), .A(net_1336) );
XOR2_X1 inst_36 ( .Z(net_3546), .B(net_3545), .A(net_3196) );
INV_X2 inst_2934 ( .ZN(net_178), .A(net_120) );
INV_X2 inst_2767 ( .A(net_1029), .ZN(net_927) );
NAND3_X2 inst_1370 ( .ZN(net_3991), .A1(net_3986), .A2(net_3913), .A3(net_3912) );
CLKBUF_X2 inst_4592 ( .A(net_4449), .Z(net_4578) );
INV_X4 inst_2512 ( .A(net_3075), .ZN(net_559) );
OAI21_X4 inst_451 ( .B2(net_3599), .ZN(net_2891), .B1(net_2890), .A(net_2313) );
INV_X8 inst_2166 ( .ZN(net_3959), .A(net_3819) );
OAI211_X2 inst_797 ( .ZN(net_2250), .C1(net_2249), .A(net_1338), .B(net_593), .C2(net_445) );
NAND2_X2 inst_1495 ( .A2(net_3151), .ZN(net_2823), .A1(net_2822) );
CLKBUF_X2 inst_5051 ( .A(net_5036), .Z(net_5037) );
AND2_X4 inst_4124 ( .ZN(net_4049), .A1(net_1643), .A2(net_1642) );
INV_X16 inst_3067 ( .ZN(net_3483), .A(net_3482) );
INV_X2 inst_3032 ( .A(net_3978), .ZN(net_3559) );
CLKBUF_X2 inst_5295 ( .A(net_5280), .Z(net_5281) );
AOI22_X2 inst_3657 ( .ZN(net_595), .B1(net_555), .A1(net_457), .B2(net_213), .A2(net_172) );
NAND2_X2 inst_1998 ( .ZN(net_3493), .A2(net_3492), .A1(net_1691) );
CLKBUF_X2 inst_5307 ( .A(net_5292), .Z(net_5293) );
DFF_X1 inst_3302 ( .D(net_2875), .Q(net_71), .CK(net_4276) );
INV_X2 inst_2870 ( .A(net_3388), .ZN(net_299) );
OAI21_X2 inst_676 ( .B2(net_3964), .ZN(net_1459), .B1(net_1215), .A(net_671) );
AOI22_X2 inst_3583 ( .A1(net_4063), .B1(net_4058), .ZN(net_1434), .B2(net_217), .A2(net_153) );
DFF_X1 inst_3348 ( .D(net_2706), .Q(net_69), .CK(net_4269) );
CLKBUF_X2 inst_4933 ( .A(net_4918), .Z(net_4919) );
NOR2_X2 inst_1115 ( .ZN(net_3381), .A1(net_3380), .A2(net_588) );
CLKBUF_X2 inst_4848 ( .A(net_4833), .Z(net_4834) );
CLKBUF_X2 inst_4222 ( .A(x1012), .Z(net_4208) );
NOR4_X2 inst_874 ( .ZN(net_4152), .A3(net_3985), .A4(net_3275), .A2(net_919), .A1(net_648) );
INV_X2 inst_2976 ( .ZN(net_1797), .A(net_332) );
NOR2_X2 inst_1021 ( .ZN(net_1856), .A1(net_1815), .A2(net_1652) );
NAND2_X2 inst_1681 ( .A1(net_3281), .ZN(net_2026), .A2(net_140) );
CLKBUF_X2 inst_4859 ( .A(net_4844), .Z(net_4845) );
CLKBUF_X2 inst_4820 ( .A(net_4253), .Z(net_4806) );
NAND2_X2 inst_1684 ( .A1(net_3219), .ZN(net_1988), .A2(net_171) );
AND2_X2 inst_4204 ( .A1(net_3878), .A2(net_3858), .ZN(net_3330) );
NAND2_X4 inst_1386 ( .ZN(net_2874), .A1(net_2839), .A2(net_2824) );
CLKBUF_X2 inst_4560 ( .A(net_4545), .Z(net_4546) );
INV_X4 inst_2255 ( .ZN(net_1388), .A(net_1290) );
NAND2_X2 inst_1652 ( .ZN(net_2209), .A1(net_2029), .A2(net_1977) );
CLKBUF_X2 inst_4827 ( .A(net_4425), .Z(net_4813) );
OR2_X4 inst_217 ( .A2(net_4034), .ZN(net_1165), .A1(net_356) );
NOR2_X2 inst_1076 ( .ZN(net_702), .A2(net_614), .A1(net_613) );
OAI21_X2 inst_572 ( .ZN(net_2829), .B1(net_2828), .B2(net_2815), .A(net_1580) );
NAND2_X2 inst_1622 ( .A1(net_2917), .ZN(net_2394), .A2(net_213) );
CLKBUF_X2 inst_4852 ( .A(net_4610), .Z(net_4838) );
NAND2_X2 inst_1735 ( .A1(net_1556), .ZN(net_1550), .A2(x884) );
CLKBUF_X2 inst_5036 ( .A(net_5021), .Z(net_5022) );
OR2_X2 inst_257 ( .A2(net_3438), .ZN(net_996), .A1(net_844) );
CLKBUF_X2 inst_4616 ( .A(net_4601), .Z(net_4602) );
NAND2_X2 inst_2050 ( .ZN(net_3874), .A2(net_3873), .A1(net_3872) );
NAND2_X2 inst_2000 ( .ZN(net_3499), .A1(net_2787), .A2(net_2768) );
AOI222_X1 inst_3748 ( .C1(net_3113), .ZN(net_2237), .B1(net_2079), .A1(net_2055), .B2(net_2054), .C2(net_2053), .A2(net_282) );
CLKBUF_X2 inst_4555 ( .A(net_4540), .Z(net_4541) );
INV_X4 inst_2213 ( .ZN(net_2124), .A(net_2068) );
OAI21_X2 inst_485 ( .B1(net_3278), .ZN(net_2957), .B2(net_2925), .A(net_2421) );
NAND4_X2 inst_1195 ( .ZN(net_2059), .A3(net_1485), .A4(net_1484), .A1(net_1419), .A2(net_1418) );
OAI21_X2 inst_672 ( .ZN(net_1450), .A(net_1265), .B1(net_1152), .B2(net_1039) );
NAND2_X4 inst_1471 ( .A1(net_3992), .ZN(net_3921), .A2(net_3521) );
AOI221_X2 inst_3826 ( .B1(net_3469), .B2(net_3145), .ZN(net_2535), .C1(net_2534), .A(net_2339), .C2(net_265) );
NAND4_X2 inst_1189 ( .ZN(net_1762), .A2(net_1760), .A4(net_1609), .A1(net_1370), .A3(net_1020) );
NAND4_X2 inst_1205 ( .ZN(net_1847), .A3(net_1500), .A4(net_1497), .A1(net_1433), .A2(net_1431) );
INV_X4 inst_2360 ( .ZN(net_609), .A(net_525) );
NAND2_X2 inst_1525 ( .A1(net_2959), .ZN(net_2497), .A2(net_190) );
DFF_X1 inst_3230 ( .QN(net_3065), .D(net_2971), .CK(net_4876) );
INV_X4 inst_2248 ( .ZN(net_1383), .A(net_1382) );
CLKBUF_X2 inst_5085 ( .A(net_4926), .Z(net_5071) );
INV_X4 inst_2453 ( .A(net_3161), .ZN(net_355) );
NAND3_X2 inst_1312 ( .ZN(net_956), .A1(net_955), .A2(net_954), .A3(net_810) );
DFF_X1 inst_3281 ( .QN(net_3030), .D(net_2910), .CK(net_5176) );
OAI21_X2 inst_703 ( .A(net_1253), .ZN(net_907), .B2(net_881), .B1(net_541) );
XOR2_X1 inst_33 ( .Z(net_324), .B(net_251), .A(net_77) );
MUX2_X2 inst_2107 ( .S(net_2912), .A(net_2573), .Z(net_2570), .B(net_242) );
INV_X4 inst_2546 ( .ZN(net_3443), .A(net_2302) );
CLKBUF_X2 inst_4693 ( .A(net_4678), .Z(net_4679) );
OR2_X4 inst_232 ( .ZN(net_629), .A2(net_389), .A1(net_374) );
DFF_X1 inst_3419 ( .D(net_1360), .Q(net_31), .CK(net_4290) );
NOR2_X2 inst_1067 ( .A2(net_4103), .ZN(net_948), .A1(net_774) );
CLKBUF_X2 inst_4628 ( .A(net_4268), .Z(net_4614) );
CLKBUF_X2 inst_4787 ( .A(net_4278), .Z(net_4773) );
AOI222_X1 inst_3794 ( .B1(net_4048), .ZN(net_3750), .B2(net_3745), .C2(net_3447), .A1(net_1968), .C1(net_323), .A2(net_271) );
CLKBUF_X2 inst_4951 ( .A(net_4404), .Z(net_4937) );
NAND2_X2 inst_1824 ( .A2(net_4097), .ZN(net_901), .A1(net_690) );
AOI22_X2 inst_3716 ( .ZN(net_3479), .A2(net_1908), .A1(net_1769), .B1(net_749), .B2(net_95) );
NAND4_X2 inst_1214 ( .A2(net_4074), .A3(net_4073), .ZN(net_1149), .A1(net_1148), .A4(net_859) );
OR2_X2 inst_253 ( .ZN(net_1179), .A1(net_1178), .A2(net_605) );
NOR2_X4 inst_971 ( .ZN(net_3911), .A2(net_3910), .A1(net_3217) );
NAND2_X4 inst_1417 ( .A1(net_3804), .ZN(net_3531), .A2(net_3365) );
NAND4_X2 inst_1219 ( .ZN(net_1044), .A4(net_835), .A3(net_598), .A2(net_499), .A1(net_463) );
AOI22_X2 inst_3652 ( .B1(net_4132), .ZN(net_818), .A1(net_713), .B2(net_402), .A2(net_395) );
OAI21_X2 inst_589 ( .B2(net_2815), .ZN(net_2619), .B1(net_2618), .A(net_1572) );
CLKBUF_X2 inst_5229 ( .A(net_4690), .Z(net_5215) );
CLKBUF_X2 inst_4868 ( .A(net_4853), .Z(net_4854) );
CLKBUF_X2 inst_5043 ( .A(net_5028), .Z(net_5029) );
CLKBUF_X2 inst_4273 ( .A(net_4258), .Z(net_4259) );
CLKBUF_X2 inst_4488 ( .A(net_4206), .Z(net_4474) );
OAI21_X2 inst_602 ( .B1(net_3449), .B2(net_2669), .ZN(net_2365), .A(net_671) );
XNOR2_X2 inst_59 ( .ZN(net_2064), .A(net_2063), .B(net_1872) );
NAND2_X2 inst_1877 ( .ZN(net_447), .A1(net_401), .A2(net_396) );
INV_X4 inst_2367 ( .ZN(net_729), .A(net_429) );
SDFF_X2 inst_135 ( .D(net_3483), .SI(net_3027), .Q(net_3027), .SE(net_2915), .CK(net_5053) );
DFF_X1 inst_3335 ( .QN(net_3149), .D(net_2784), .CK(net_4486) );
DFF_X1 inst_3256 ( .QN(net_3080), .D(net_2945), .CK(net_4724) );
INV_X1 inst_3073 ( .A(net_3439), .ZN(net_1806) );
NAND2_X2 inst_1865 ( .ZN(net_903), .A2(net_775), .A1(net_723) );
XOR2_X1 inst_37 ( .Z(net_4134), .B(net_4092), .A(net_1872) );
NAND2_X2 inst_1980 ( .ZN(net_3387), .A1(net_341), .A2(net_42) );
NAND2_X2 inst_1664 ( .ZN(net_2098), .A1(net_2096), .A2(net_215) );
NAND2_X4 inst_1447 ( .ZN(net_3804), .A1(net_3803), .A2(net_3404) );
DFF_X2 inst_3117 ( .Q(net_3133), .D(net_2734), .CK(net_4593) );
INV_X2 inst_2885 ( .A(net_2999), .ZN(net_166) );
CLKBUF_X2 inst_4795 ( .A(net_4523), .Z(net_4781) );
INV_X2 inst_2632 ( .A(net_3536), .ZN(net_2620) );
INV_X4 inst_2221 ( .ZN(net_2063), .A(net_1904) );
AOI222_X1 inst_3770 ( .B1(net_4048), .C1(net_3447), .A1(net_1968), .ZN(net_1962), .A2(net_294), .C2(net_204), .B2(net_73) );
NAND2_X1 inst_2082 ( .A1(net_4154), .A2(net_3600), .ZN(net_2758) );
DFF_X1 inst_3286 ( .QN(net_3050), .D(net_2895), .CK(net_4717) );
CLKBUF_X2 inst_4225 ( .A(net_4210), .Z(net_4211) );
INV_X2 inst_2709 ( .ZN(net_2119), .A(net_2016) );
OR2_X4 inst_224 ( .A2(net_4101), .ZN(net_1131), .A1(net_656) );
CLKBUF_X2 inst_4730 ( .A(net_4715), .Z(net_4716) );
AOI22_X2 inst_3635 ( .ZN(net_1710), .B1(net_1071), .A1(net_753), .A2(net_433), .B2(net_256) );
INV_X1 inst_3075 ( .A(net_3320), .ZN(net_1564) );
CLKBUF_X2 inst_5058 ( .A(net_5043), .Z(net_5044) );
INV_X2 inst_2800 ( .ZN(net_744), .A(net_708) );
INV_X4 inst_2406 ( .ZN(net_380), .A(net_304) );
OAI21_X2 inst_766 ( .ZN(net_3961), .B1(net_3960), .A(net_3634), .B2(net_923) );
AND2_X4 inst_4141 ( .ZN(net_4077), .A1(net_702), .A2(net_606) );
DFF_X1 inst_3270 ( .QN(net_3094), .D(net_2927), .CK(net_5030) );
NAND2_X2 inst_1908 ( .A1(net_323), .A2(net_322), .ZN(net_307) );
DFF_X1 inst_3273 ( .QN(net_3098), .D(net_2922), .CK(net_5020) );
OAI211_X2 inst_801 ( .C1(net_2190), .ZN(net_2168), .C2(net_2167), .A(net_2014), .B(net_1999) );
CLKBUF_X2 inst_4591 ( .A(net_4576), .Z(net_4577) );
OAI21_X2 inst_692 ( .B1(net_3734), .A(net_1650), .ZN(net_1178), .B2(net_540) );
NAND2_X2 inst_1517 ( .A1(net_3582), .ZN(net_2578), .A2(net_2513) );
XNOR2_X2 inst_70 ( .B(net_1764), .ZN(net_1618), .A(net_1462) );
NOR4_X2 inst_870 ( .A3(net_4094), .A4(net_3549), .ZN(net_967), .A2(net_966), .A1(net_919) );
XOR2_X2 inst_11 ( .Z(net_1508), .B(net_1507), .A(net_1441) );
CLKBUF_X2 inst_4528 ( .A(net_4373), .Z(net_4514) );
OR3_X2 inst_188 ( .ZN(net_3724), .A3(net_3680), .A1(net_723), .A2(net_432) );
AOI222_X1 inst_3768 ( .B1(net_4048), .C1(net_3447), .A1(net_1968), .ZN(net_1964), .C2(net_1523), .A2(net_1507), .B2(net_71) );
NAND2_X2 inst_1619 ( .A1(net_2919), .ZN(net_2397), .A2(net_194) );
AND2_X2 inst_4207 ( .ZN(net_3460), .A1(net_3445), .A2(net_2563) );
DFF_X2 inst_3110 ( .QN(net_2994), .D(net_2797), .CK(net_5099) );
OAI221_X2 inst_441 ( .C1(net_3877), .B2(net_3685), .ZN(net_3535), .B1(net_2699), .C2(net_2698), .A(net_2370) );
INV_X2 inst_3011 ( .ZN(net_3376), .A(net_3375) );
INV_X4 inst_2276 ( .ZN(net_2213), .A(net_994) );
CLKBUF_X2 inst_5228 ( .A(net_5213), .Z(net_5214) );
INV_X2 inst_2848 ( .ZN(net_370), .A(net_369) );
INV_X4 inst_2301 ( .ZN(net_2167), .A(net_856) );
CLKBUF_X2 inst_4826 ( .A(net_4811), .Z(net_4812) );
OAI211_X2 inst_808 ( .ZN(net_1681), .B(net_1588), .C1(net_1501), .A(net_1177), .C2(net_1124) );
NAND2_X2 inst_1537 ( .A1(net_2907), .ZN(net_2485), .A2(net_221) );
OAI21_X2 inst_557 ( .B2(net_2912), .B1(net_2871), .ZN(net_2868), .A(net_2451) );
NAND2_X2 inst_2041 ( .ZN(net_3809), .A1(net_3294), .A2(net_2026) );
AOI221_X2 inst_3859 ( .C2(net_4147), .B1(net_3736), .C1(net_2049), .ZN(net_2045), .A(net_1812), .B2(net_1511) );
CLKBUF_X2 inst_5235 ( .A(net_4622), .Z(net_5221) );
AOI22_X2 inst_3593 ( .A1(net_4062), .B1(net_4057), .ZN(net_1424), .B2(net_487), .A2(net_475) );
NAND3_X1 inst_1383 ( .A3(net_3827), .ZN(net_3498), .A1(net_2787), .A2(net_2768) );
DFF_X1 inst_3279 ( .QN(net_3033), .D(net_2920), .CK(net_5085) );
OAI211_X2 inst_823 ( .A(net_3843), .ZN(net_1520), .C1(net_1369), .B(net_1195), .C2(net_1150) );
NAND2_X4 inst_1461 ( .ZN(net_3872), .A1(net_3198), .A2(net_159) );
CLKBUF_X2 inst_4589 ( .A(net_4574), .Z(net_4575) );
INV_X2 inst_2838 ( .ZN(net_605), .A(net_594) );
AOI222_X1 inst_3773 ( .A2(net_2037), .ZN(net_1898), .A1(net_1863), .B1(net_1862), .C1(net_1861), .B2(net_906), .C2(net_182) );
DFF_X1 inst_3423 ( .D(net_771), .Q(net_57), .CK(net_4695) );
DFF_X2 inst_3176 ( .D(net_1876), .Q(net_54), .CK(net_4845) );
INV_X2 inst_2833 ( .ZN(net_1351), .A(net_371) );
CLKBUF_X2 inst_4767 ( .A(net_4752), .Z(net_4753) );
NAND2_X2 inst_2042 ( .ZN(net_3830), .A2(net_1982), .A1(net_148) );
DFF_X1 inst_3325 ( .Q(net_3136), .D(net_2833), .CK(net_4649) );
AND2_X4 inst_4168 ( .A2(net_4129), .ZN(net_4122), .A1(net_255) );
OR2_X4 inst_195 ( .ZN(net_2959), .A1(net_2353), .A2(net_2352) );
CLKBUF_X2 inst_5156 ( .A(net_5141), .Z(net_5142) );
NAND2_X2 inst_1987 ( .ZN(net_3433), .A2(net_3432), .A1(net_3431) );
INV_X2 inst_2796 ( .ZN(net_2150), .A(net_753) );
NOR2_X2 inst_1150 ( .ZN(net_3947), .A1(net_3654), .A2(net_3107) );
INV_X2 inst_2729 ( .ZN(net_1399), .A(net_1355) );
NAND2_X4 inst_1413 ( .A1(net_3601), .ZN(net_3393), .A2(net_3392) );
CLKBUF_X2 inst_4914 ( .A(net_4224), .Z(net_4900) );
NAND2_X2 inst_1815 ( .A2(net_3900), .ZN(net_1261), .A1(net_853) );
AOI21_X2 inst_3993 ( .B1(net_4134), .ZN(net_3240), .A(net_3239), .B2(net_1826) );
CLKBUF_X2 inst_4780 ( .A(net_4765), .Z(net_4766) );
CLKBUF_X2 inst_5267 ( .A(net_4306), .Z(net_5253) );
CLKBUF_X2 inst_4658 ( .A(net_4643), .Z(net_4644) );
NAND2_X2 inst_1589 ( .A1(net_2972), .ZN(net_2429), .A2(net_738) );
CLKBUF_X2 inst_4535 ( .A(net_4520), .Z(net_4521) );
INV_X8 inst_2169 ( .ZN(net_3995), .A(net_3107) );
NAND3_X2 inst_1326 ( .A3(net_721), .ZN(net_683), .A1(net_609), .A2(net_435) );
CLKBUF_X2 inst_4499 ( .A(net_4484), .Z(net_4485) );
CLKBUF_X2 inst_4238 ( .A(net_4223), .Z(net_4224) );
CLKBUF_X2 inst_5275 ( .A(net_5260), .Z(net_5261) );
CLKBUF_X2 inst_4758 ( .A(net_4743), .Z(net_4744) );
OAI22_X2 inst_335 ( .ZN(net_663), .A1(net_344), .B2(net_263), .A2(net_192), .B1(net_49) );
AOI221_X2 inst_3875 ( .A(net_4046), .C2(net_1908), .ZN(net_1907), .C1(net_1906), .B2(net_749), .B1(net_91) );
INV_X2 inst_2629 ( .ZN(net_2842), .A(net_2832) );
OAI21_X2 inst_658 ( .ZN(net_1763), .B1(net_1701), .A(net_1669), .B2(net_77) );
CLKBUF_X2 inst_4520 ( .A(net_4505), .Z(net_4506) );
OAI221_X2 inst_438 ( .C2(net_987), .A(net_629), .B2(net_628), .C1(net_627), .ZN(net_621), .B1(net_387) );
NAND3_X2 inst_1341 ( .A2(net_4139), .ZN(net_3383), .A3(net_3374), .A1(net_818) );
INV_X8 inst_2154 ( .ZN(net_3492), .A(net_3491) );
OAI21_X2 inst_587 ( .B2(net_2815), .ZN(net_2646), .B1(net_2645), .A(net_1744) );
OAI21_X2 inst_666 ( .B1(net_4034), .ZN(net_2016), .A(net_1646), .B2(net_1173) );
CLKBUF_X2 inst_4602 ( .A(net_4587), .Z(net_4588) );
INV_X4 inst_2602 ( .ZN(net_3613), .A(net_3171) );
OAI22_X2 inst_324 ( .B2(net_3123), .ZN(net_1137), .B1(net_721), .A1(net_641), .A2(net_43) );
NAND2_X2 inst_1829 ( .ZN(net_1614), .A1(net_1613), .A2(net_270) );
AOI22_X2 inst_3550 ( .A1(net_4059), .B1(net_4056), .ZN(net_1500), .A2(net_242), .B2(net_147) );
XNOR2_X2 inst_109 ( .ZN(net_419), .A(net_349), .B(net_108) );
NAND4_X2 inst_1182 ( .A3(net_3193), .ZN(net_2245), .A1(net_2128), .A4(net_2102), .A2(net_2092) );
AND3_X2 inst_4083 ( .ZN(net_1590), .A1(net_1589), .A2(net_1588), .A3(net_1009) );
AOI21_X2 inst_3983 ( .B1(net_983), .ZN(net_942), .A(net_638), .B2(net_371) );
XNOR2_X2 inst_43 ( .B(net_3537), .ZN(net_2743), .A(net_2540) );
INV_X8 inst_2128 ( .ZN(net_571), .A(net_362) );
NAND2_X2 inst_1707 ( .A1(net_3321), .A2(net_3320), .ZN(net_1790) );
NAND2_X4 inst_1444 ( .ZN(net_3784), .A2(net_3783), .A1(net_3782) );
CLKBUF_X2 inst_5252 ( .A(net_5233), .Z(net_5238) );
NAND4_X2 inst_1231 ( .ZN(net_753), .A4(net_573), .A3(net_563), .A2(net_502), .A1(net_456) );
OAI221_X2 inst_375 ( .B2(net_2733), .C1(net_2686), .ZN(net_2681), .A(net_2558), .C2(net_2150), .B1(net_1996) );
AOI22_X2 inst_3490 ( .B2(net_3882), .A1(net_3881), .A2(net_3516), .ZN(net_2576), .B1(net_2381) );
NOR3_X2 inst_904 ( .ZN(net_827), .A1(net_826), .A2(net_825), .A3(net_605) );
DFF_X1 inst_3315 ( .QN(net_3150), .D(net_2842), .CK(net_4517) );
INV_X8 inst_2159 ( .ZN(net_3644), .A(net_3168) );
OAI22_X2 inst_285 ( .ZN(net_2310), .B1(net_2309), .A1(net_2274), .B2(net_975), .A2(net_974) );
NAND2_X2 inst_1830 ( .A1(net_3398), .ZN(net_969), .A2(net_810) );
AOI21_X4 inst_3923 ( .B2(net_3515), .ZN(net_2607), .B1(net_2364), .A(net_2322) );
CLKBUF_X2 inst_4831 ( .A(net_4816), .Z(net_4817) );
OAI21_X2 inst_757 ( .B2(net_4146), .B1(net_4099), .A(net_4084), .ZN(net_3731) );
OAI22_X2 inst_343 ( .ZN(net_3494), .B1(net_2122), .B2(net_1071), .A1(net_1036), .A2(net_137) );
NAND2_X2 inst_1627 ( .ZN(net_2519), .A2(net_2518), .A1(net_2389) );
CLKBUF_X2 inst_4739 ( .A(net_4211), .Z(net_4725) );
NAND2_X2 inst_1563 ( .A1(net_2963), .ZN(net_2458), .A2(net_518) );
OAI21_X2 inst_543 ( .B2(net_2925), .ZN(net_2889), .B1(net_2887), .A(net_2424) );
NOR2_X2 inst_1106 ( .A1(net_3876), .A2(net_3515), .ZN(net_3222) );
CLKBUF_X2 inst_4455 ( .A(net_4440), .Z(net_4441) );
DFF_X1 inst_3242 ( .QN(net_3044), .D(net_2947), .CK(net_5180) );
AOI221_X2 inst_3817 ( .B2(net_3136), .A(net_2642), .B1(net_2591), .C2(net_2589), .ZN(net_2564), .C1(net_2563) );
DFF_X2 inst_3138 ( .QN(net_2986), .D(net_2567), .CK(net_5152) );
NOR2_X4 inst_982 ( .ZN(net_4002), .A2(net_4000), .A1(net_3658) );
NOR2_X4 inst_929 ( .A1(net_3814), .A2(net_2989), .ZN(net_2094) );
NAND2_X2 inst_2070 ( .ZN(net_3978), .A2(net_3822), .A1(net_3721) );
NAND2_X4 inst_1397 ( .A2(net_3125), .ZN(net_1259), .A1(net_1017) );
CLKBUF_X2 inst_5065 ( .A(net_5050), .Z(net_5051) );
NAND4_X2 inst_1256 ( .ZN(net_3882), .A3(net_3210), .A2(net_3209), .A4(net_3205), .A1(net_2177) );
INV_X2 inst_2890 ( .A(net_3015), .ZN(net_203) );
OAI22_X2 inst_299 ( .B1(net_2374), .ZN(net_2293), .B2(net_1606), .A1(net_1565), .A2(net_946) );
NAND2_X2 inst_1798 ( .A2(net_3156), .ZN(net_1650), .A1(net_837) );
INV_X2 inst_2927 ( .A(net_3027), .ZN(net_133) );
DFF_X1 inst_3303 ( .QN(net_3021), .D(net_2873), .CK(net_5214) );
NAND2_X2 inst_1903 ( .A1(net_3613), .A2(net_3106), .ZN(net_346) );
CLKBUF_X2 inst_4304 ( .A(net_4289), .Z(net_4290) );
INV_X2 inst_2760 ( .A(net_1228), .ZN(net_1089) );
NAND2_X2 inst_1938 ( .A2(net_3769), .ZN(net_3215), .A1(net_590) );
INV_X4 inst_2554 ( .A(net_3976), .ZN(net_3478) );
INV_X2 inst_2745 ( .A(net_1259), .ZN(net_1193) );
NAND2_X1 inst_2095 ( .ZN(net_3368), .A2(net_3366), .A1(net_2608) );
INV_X4 inst_2604 ( .ZN(net_3779), .A(net_3778) );
CLKBUF_X2 inst_5129 ( .A(net_5114), .Z(net_5115) );
CLKBUF_X2 inst_4410 ( .A(net_4234), .Z(net_4396) );
NAND4_X2 inst_1244 ( .A2(net_3652), .ZN(net_3511), .A3(net_3194), .A4(net_2136), .A1(net_2133) );
CLKBUF_X2 inst_4995 ( .A(net_4796), .Z(net_4981) );
DFF_X1 inst_3260 ( .QN(net_3076), .D(net_2930), .CK(net_4925) );
DFF_X1 inst_3248 ( .QN(net_3084), .D(net_2941), .CK(net_4547) );
AND2_X4 inst_4190 ( .ZN(net_4189), .A1(net_4042), .A2(net_2129) );
DFF_X2 inst_3158 ( .QN(net_3129), .D(net_2156), .CK(net_5287) );
OAI21_X2 inst_582 ( .B2(net_4069), .B1(net_3230), .ZN(net_2786), .A(net_2785) );
OAI21_X2 inst_683 ( .ZN(net_1265), .B2(net_1183), .B1(net_1073), .A(net_1011) );
DFF_X1 inst_3269 ( .QN(net_3095), .D(net_2911), .CK(net_5033) );
INV_X4 inst_2186 ( .ZN(net_2657), .A(net_2545) );
NAND2_X2 inst_1944 ( .A1(net_3476), .ZN(net_3244), .A2(net_2309) );
OR2_X4 inst_210 ( .A2(net_3959), .A1(net_1891), .ZN(net_1880) );
CLKBUF_X2 inst_4515 ( .A(net_4236), .Z(net_4501) );
HA_X1 inst_3101 ( .CO(net_349), .S(net_308), .A(net_209), .B(net_149) );
MUX2_X2 inst_2110 ( .B(net_3455), .S(net_3207), .A(net_2573), .Z(net_2567) );
NAND2_X2 inst_1850 ( .A1(net_4114), .ZN(net_750), .A2(net_594) );
CLKBUF_X2 inst_4942 ( .A(net_4927), .Z(net_4928) );
AOI22_X2 inst_3477 ( .B1(net_4039), .ZN(net_2673), .A1(net_2657), .A2(net_333), .B2(x23) );
NAND2_X2 inst_1950 ( .A1(net_3600), .ZN(net_3272), .A2(net_3271) );
AOI221_X2 inst_3881 ( .C2(net_1908), .ZN(net_1825), .A(net_1824), .C1(net_1823), .B2(net_749), .B1(net_92) );
CLKBUF_X2 inst_4778 ( .A(net_4763), .Z(net_4764) );
CLKBUF_X2 inst_5287 ( .A(net_5067), .Z(net_5273) );
NAND3_X2 inst_1294 ( .A1(net_4044), .ZN(net_1961), .A3(net_1960), .A2(net_1189) );
NAND2_X2 inst_1712 ( .A1(net_1884), .ZN(net_1758), .A2(net_1585) );
CLKBUF_X2 inst_5238 ( .A(net_4359), .Z(net_5224) );
NAND2_X2 inst_2057 ( .A1(net_3915), .ZN(net_3905), .A2(net_3900) );
CLKBUF_X2 inst_4576 ( .A(net_4561), .Z(net_4562) );
DFF_X2 inst_3108 ( .QN(net_2996), .D(net_2798), .CK(net_5106) );
OAI21_X2 inst_747 ( .B2(net_4138), .ZN(net_3378), .B1(net_3377), .A(net_3376) );
OAI211_X2 inst_843 ( .B(net_3323), .ZN(net_1113), .A(net_980), .C1(net_889), .C2(net_723) );
AOI221_X2 inst_3806 ( .C2(net_4032), .ZN(net_2736), .B2(net_2612), .C1(net_2562), .A(net_2365), .B1(net_2130) );
INV_X2 inst_2853 ( .A(net_3447), .ZN(net_356) );
NAND2_X2 inst_1779 ( .A2(net_4024), .ZN(net_1191), .A1(net_1068) );
CLKBUF_X2 inst_4486 ( .A(net_4235), .Z(net_4472) );
INV_X8 inst_2115 ( .ZN(net_2970), .A(net_2903) );
CLKBUF_X2 inst_5146 ( .A(net_4368), .Z(net_5132) );
DFF_X1 inst_3251 ( .QN(net_3089), .D(net_2952), .CK(net_4734) );
XNOR2_X2 inst_112 ( .ZN(net_410), .B(net_354), .A(net_336) );
NAND2_X2 inst_1728 ( .ZN(net_1558), .A1(net_1556), .A2(x856) );
INV_X2 inst_2775 ( .A(net_996), .ZN(net_836) );
NOR3_X2 inst_916 ( .A1(net_3903), .A2(net_3890), .ZN(net_3712), .A3(net_749) );
NAND2_X2 inst_1722 ( .ZN(net_1604), .A1(net_1515), .A2(net_1344) );
OAI22_X2 inst_305 ( .A2(net_3149), .A1(net_1543), .B1(net_1542), .ZN(net_1536), .B2(net_1535) );
NAND2_X2 inst_1595 ( .A1(net_2925), .ZN(net_2423), .A2(net_199) );
AOI22_X2 inst_3665 ( .B2(net_3402), .A2(net_3401), .A1(net_571), .B1(net_570), .ZN(net_562) );
INV_X2 inst_2724 ( .ZN(net_1467), .A(net_1397) );
INV_X4 inst_2525 ( .A(net_3895), .ZN(net_3261) );
INV_X2 inst_2968 ( .ZN(net_300), .A(net_60) );
INV_X2 inst_2964 ( .ZN(net_152), .A(net_88) );
AOI22_X2 inst_3721 ( .ZN(net_3609), .A1(net_3185), .B1(net_1982), .A2(net_519), .B2(net_478) );
INV_X4 inst_2349 ( .ZN(net_2625), .A(x475) );
OAI21_X2 inst_646 ( .A(net_3256), .ZN(net_1945), .B1(net_1643), .B2(net_1642) );
CLKBUF_X2 inst_5076 ( .A(net_4207), .Z(net_5062) );
AOI211_X2 inst_4032 ( .A(net_4068), .ZN(net_3317), .B(net_1147), .C1(net_1116), .C2(net_407) );
DFF_X2 inst_3169 ( .D(net_1926), .QN(net_89), .CK(net_5093) );
NOR2_X4 inst_963 ( .ZN(net_3810), .A1(net_3809), .A2(net_3539) );
OAI221_X2 inst_382 ( .B1(net_3581), .C2(net_2699), .B2(net_2698), .ZN(net_2631), .C1(net_2630), .A(net_2533) );
INV_X4 inst_2329 ( .A(net_3661), .ZN(net_748) );
NOR3_X2 inst_907 ( .A2(net_3954), .ZN(net_656), .A3(net_641), .A1(net_637) );
NOR2_X4 inst_922 ( .ZN(net_2788), .A1(net_2741), .A2(net_2576) );
NAND2_X2 inst_1614 ( .A1(net_2919), .ZN(net_2402), .A2(net_181) );
NAND2_X2 inst_1502 ( .ZN(net_2807), .A1(net_2782), .A2(net_2723) );
INV_X2 inst_2788 ( .ZN(net_797), .A(net_796) );
AND3_X2 inst_4091 ( .A1(net_4162), .A2(net_4126), .ZN(net_3732), .A3(net_3628) );
NOR2_X2 inst_1049 ( .A1(net_4075), .A2(net_1052), .ZN(net_1051) );
AOI221_X2 inst_3907 ( .B1(net_4109), .ZN(net_992), .B2(net_991), .C1(net_990), .A(net_832), .C2(net_361) );
OR3_X4 inst_168 ( .ZN(net_1543), .A1(net_1521), .A2(net_1334), .A3(net_1071) );
CLKBUF_X2 inst_5116 ( .A(net_5101), .Z(net_5102) );
NAND2_X2 inst_1568 ( .A1(net_2912), .ZN(net_2453), .A2(net_236) );
CLKBUF_X2 inst_4575 ( .A(net_4560), .Z(net_4561) );
AOI22_X2 inst_3692 ( .B2(net_4123), .B1(net_4023), .A1(net_4017), .A2(net_509), .ZN(net_484) );
DFF_X1 inst_3366 ( .D(net_3696), .CK(net_4251), .Q(x160) );
NOR4_X2 inst_873 ( .ZN(net_3551), .A1(net_2145), .A2(net_1947), .A3(net_1801), .A4(net_1750) );
NOR2_X2 inst_991 ( .A1(net_3880), .A2(net_3859), .ZN(net_2380) );
OAI21_X2 inst_653 ( .ZN(net_1831), .A(net_1773), .B2(net_347), .B1(x475) );
AOI222_X1 inst_3767 ( .B1(net_4048), .A1(net_1968), .ZN(net_1965), .A2(net_1439), .C2(net_991), .C1(net_375), .B2(net_239) );
OAI21_X2 inst_580 ( .B2(net_2907), .B1(net_2803), .ZN(net_2798), .A(net_2487) );
OR3_X4 inst_170 ( .A3(net_4094), .A2(net_4085), .ZN(net_1072), .A1(net_1058) );
NAND2_X2 inst_1746 ( .A2(net_4005), .ZN(net_1583), .A1(net_1282) );
AOI22_X2 inst_3691 ( .B1(net_4123), .ZN(net_485), .A1(net_458), .B2(net_233), .A2(net_183) );
CLKBUF_X2 inst_4431 ( .A(net_4416), .Z(net_4417) );
DFF_X1 inst_3371 ( .D(net_2294), .CK(net_4217), .Q(x307) );
INV_X2 inst_3052 ( .ZN(net_3851), .A(net_2245) );
AOI22_X2 inst_3649 ( .ZN(net_739), .A1(net_738), .B1(net_737), .A2(net_458), .B2(net_457) );
NAND2_X2 inst_1857 ( .A2(net_3153), .ZN(net_612), .A1(net_433) );
CLKBUF_X2 inst_4609 ( .A(net_4594), .Z(net_4595) );
INV_X2 inst_2907 ( .A(net_3139), .ZN(net_287) );
AND3_X4 inst_4072 ( .A1(net_4043), .ZN(net_4040), .A2(net_2181), .A3(net_2180) );
INV_X2 inst_2656 ( .A(net_2698), .ZN(net_2240) );
INV_X2 inst_3000 ( .A(net_3024), .ZN(net_126) );
NOR2_X2 inst_1163 ( .ZN(net_4170), .A2(net_4169), .A1(net_1994) );
OAI21_X4 inst_468 ( .ZN(net_3983), .A(net_3980), .B2(net_3755), .B1(net_3615) );
NOR2_X2 inst_1099 ( .A1(net_3654), .ZN(net_278), .A2(net_138) );
CLKBUF_X2 inst_4428 ( .A(net_4218), .Z(net_4414) );
AOI22_X2 inst_3616 ( .A1(net_1518), .ZN(net_1327), .B2(net_1326), .B1(net_1146), .A2(net_1001) );
CLKBUF_X2 inst_4889 ( .A(net_4874), .Z(net_4875) );
NAND2_X2 inst_1604 ( .A1(net_2969), .ZN(net_2413), .A2(net_498) );
DFF_X1 inst_3239 ( .QN(net_3039), .D(net_2937), .CK(net_5187) );
INV_X4 inst_2314 ( .ZN(net_1385), .A(net_1042) );
INV_X4 inst_2190 ( .ZN(net_2584), .A(net_2349) );
OAI221_X2 inst_429 ( .B2(net_3789), .ZN(net_1054), .A(net_1009), .B1(net_1008), .C1(net_1007), .C2(net_526) );
INV_X2 inst_2692 ( .ZN(net_1733), .A(net_1700) );
NAND2_X2 inst_1599 ( .A1(net_2969), .ZN(net_2418), .A2(net_495) );
INV_X2 inst_2812 ( .A(net_1400), .ZN(net_645) );
CLKBUF_X2 inst_5026 ( .A(net_5011), .Z(net_5012) );
AOI22_X2 inst_3565 ( .A1(net_4059), .B1(net_4056), .ZN(net_1485), .A2(net_200), .B2(net_140) );
CLKBUF_X2 inst_4743 ( .A(net_4728), .Z(net_4729) );
DFF_X2 inst_3197 ( .QN(net_3167), .D(net_1622), .CK(net_5131) );
CLKBUF_X2 inst_4651 ( .A(net_4286), .Z(net_4637) );
XOR2_X2 inst_7 ( .B(net_3492), .Z(net_1692), .A(net_1691) );
AOI21_X2 inst_3977 ( .B2(net_3559), .A(net_1196), .ZN(net_1115), .B1(net_895) );
AOI22_X2 inst_3467 ( .B2(net_3118), .ZN(net_2725), .A1(net_2724), .B1(net_2722), .A2(net_33) );
INV_X4 inst_2593 ( .ZN(net_3717), .A(net_3715) );
INV_X16 inst_3064 ( .ZN(net_1982), .A(net_1865) );
AOI22_X2 inst_3676 ( .A1(net_571), .B1(net_570), .ZN(net_545), .A2(net_237), .B2(net_157) );
CLKBUF_X2 inst_5021 ( .A(net_5006), .Z(net_5007) );
NOR2_X2 inst_1083 ( .A1(net_3614), .ZN(net_614), .A2(net_388) );
AND3_X4 inst_4073 ( .ZN(net_4048), .A3(net_3802), .A2(net_3320), .A1(net_1645) );
OAI22_X2 inst_318 ( .A2(net_4074), .B1(net_1250), .ZN(net_1121), .A1(net_1120), .B2(net_1100) );
AOI211_X2 inst_4033 ( .C1(net_4094), .B(net_4085), .ZN(net_3839), .C2(net_3834), .A(net_969) );
NOR2_X2 inst_1136 ( .A1(net_3995), .ZN(net_3757), .A2(net_3109) );
INV_X4 inst_2466 ( .A(net_2989), .ZN(net_175) );
CLKBUF_X2 inst_5044 ( .A(net_4447), .Z(net_5030) );
INV_X2 inst_2899 ( .A(net_3018), .ZN(net_157) );
AND3_X4 inst_4065 ( .A3(net_3802), .A2(net_3321), .ZN(net_1921), .A1(net_1827) );
NAND2_X4 inst_1486 ( .ZN(net_4163), .A1(net_3713), .A2(net_3628) );
INV_X4 inst_2281 ( .ZN(net_1198), .A(net_1069) );
OAI21_X2 inst_696 ( .A(net_3907), .B1(net_3905), .B2(net_3789), .ZN(net_1022) );
NAND4_X4 inst_1175 ( .A3(net_3649), .ZN(net_3251), .A4(net_3250), .A1(net_3234), .A2(net_2093) );
DFF_X1 inst_3311 ( .D(net_2863), .QN(net_66), .CK(net_4244) );
CLKBUF_X2 inst_5256 ( .A(net_4469), .Z(net_5242) );
AND2_X4 inst_4096 ( .ZN(net_2019), .A1(net_1651), .A2(net_1650) );
CLKBUF_X2 inst_5055 ( .A(net_5040), .Z(net_5041) );
CLKBUF_X2 inst_5117 ( .A(net_5102), .Z(net_5103) );
CLKBUF_X2 inst_5081 ( .A(net_4703), .Z(net_5067) );
CLKBUF_X2 inst_4509 ( .A(net_4494), .Z(net_4495) );
CLKBUF_X2 inst_5114 ( .A(net_4537), .Z(net_5100) );
CLKBUF_X2 inst_4929 ( .A(net_4743), .Z(net_4915) );
OAI221_X2 inst_395 ( .C2(net_3408), .B1(net_2361), .ZN(net_2356), .C1(net_2226), .A(net_1942), .B2(net_111) );
OAI211_X2 inst_841 ( .C2(net_4109), .ZN(net_1258), .A(net_1257), .C1(net_1256), .B(net_1065) );
AOI21_X2 inst_3963 ( .ZN(net_1456), .B1(net_1455), .B2(net_1153), .A(net_765) );
OAI21_X2 inst_689 ( .B1(net_4004), .ZN(net_1086), .A(net_641), .B2(net_384) );
AOI21_X2 inst_3969 ( .A(net_3558), .ZN(net_1313), .B1(net_1134), .B2(net_1011) );
CLKBUF_X2 inst_4453 ( .A(net_4438), .Z(net_4439) );
INV_X4 inst_2363 ( .A(net_3954), .ZN(net_446) );
INV_X2 inst_2689 ( .A(net_3844), .ZN(net_1755) );
CLKBUF_X2 inst_4895 ( .A(net_4857), .Z(net_4881) );
AOI211_X2 inst_4029 ( .B(net_3525), .C1(net_3322), .A(net_1018), .ZN(net_865), .C2(net_594) );
NAND2_X2 inst_1629 ( .ZN(net_2341), .A1(net_2288), .A2(net_2240) );
AOI221_X2 inst_3896 ( .C1(net_4030), .A(net_2525), .C2(net_1394), .B1(net_1393), .ZN(net_1346), .B2(net_218) );
NAND2_X2 inst_1558 ( .A1(net_2909), .ZN(net_2464), .A2(net_233) );
AOI22_X2 inst_3679 ( .B1(net_4124), .ZN(net_510), .A1(net_509), .B2(net_227), .A2(net_181) );
INV_X2 inst_2906 ( .A(net_3144), .ZN(net_256) );
DFF_X1 inst_3424 ( .Q(net_4009), .D(net_4008), .CK(net_4921) );
AOI221_X2 inst_3886 ( .C2(net_1656), .ZN(net_1524), .B2(net_1523), .C1(net_1522), .B1(net_1263), .A(net_1249) );
NAND2_X2 inst_1615 ( .A1(net_2919), .ZN(net_2401), .A2(net_151) );
INV_X4 inst_2580 ( .ZN(net_3623), .A(net_3622) );
AOI22_X2 inst_3713 ( .ZN(net_3247), .A1(net_3178), .B1(net_2099), .A2(net_498), .B2(net_497) );
INV_X4 inst_2394 ( .ZN(net_379), .A(net_327) );
INV_X8 inst_2145 ( .ZN(net_3228), .A(net_3227) );
OAI21_X2 inst_709 ( .B2(net_881), .ZN(net_851), .A(net_850), .B1(net_849) );
CLKBUF_X2 inst_4574 ( .A(net_4316), .Z(net_4560) );
INV_X4 inst_2375 ( .ZN(net_1463), .A(net_511) );
NOR3_X1 inst_920 ( .A1(net_3581), .A2(net_3248), .ZN(net_2343), .A3(net_2342) );
NAND2_X2 inst_2054 ( .ZN(net_3896), .A2(net_3892), .A1(net_3867) );
CLKBUF_X2 inst_5294 ( .A(net_4341), .Z(net_5280) );
CLKBUF_X2 inst_5251 ( .A(net_5236), .Z(net_5237) );
CLKBUF_X2 inst_4422 ( .A(net_4407), .Z(net_4408) );
NAND4_X2 inst_1259 ( .ZN(net_4188), .A4(net_3699), .A2(net_3617), .A3(net_3524), .A1(net_3430) );
CLKBUF_X2 inst_5092 ( .A(net_5077), .Z(net_5078) );
CLKBUF_X2 inst_4610 ( .A(net_4595), .Z(net_4596) );
NAND2_X2 inst_1796 ( .ZN(net_998), .A1(net_839), .A2(net_432) );
CLKBUF_X2 inst_4403 ( .A(net_4388), .Z(net_4389) );
OAI21_X2 inst_535 ( .B1(net_3195), .B2(net_2963), .ZN(net_2898), .A(net_2460) );
INV_X2 inst_2889 ( .A(net_3113), .ZN(net_1535) );
NAND2_X2 inst_1670 ( .A1(net_3817), .ZN(net_2088), .A2(net_738) );
INV_X4 inst_2189 ( .A(net_2686), .ZN(net_2640) );
INV_X4 inst_2427 ( .A(net_3054), .ZN(net_487) );
AND2_X2 inst_4198 ( .ZN(net_1402), .A1(net_1296), .A2(net_671) );
OAI22_X2 inst_315 ( .A1(net_4073), .A2(net_1381), .ZN(net_1127), .B1(net_1126), .B2(net_1125) );
INV_X2 inst_2935 ( .A(net_3117), .ZN(net_131) );
OR2_X4 inst_216 ( .ZN(net_1214), .A2(net_1213), .A1(net_1151) );
DFF_X1 inst_3317 ( .QN(net_3004), .D(net_2844), .CK(net_5118) );
DFF_X1 inst_3369 ( .D(net_2285), .CK(net_4437), .Q(x204) );
CLKBUF_X2 inst_5027 ( .A(net_5012), .Z(net_5013) );
DFF_X2 inst_3113 ( .QN(net_2990), .D(net_2799), .CK(net_5199) );
NAND2_X2 inst_2060 ( .ZN(net_3909), .A1(net_3817), .A2(net_162) );
AOI22_X2 inst_3695 ( .B2(net_4124), .A1(net_4021), .B1(net_4019), .A2(net_555), .ZN(net_481) );
INV_X2 inst_2680 ( .ZN(net_1859), .A(net_1858) );
DFF_X2 inst_3168 ( .Q(net_3161), .D(net_1958), .CK(net_4762) );
INV_X4 inst_2336 ( .A(net_3734), .ZN(net_661) );
INV_X4 inst_2385 ( .ZN(net_381), .A(net_276) );
OAI221_X2 inst_415 ( .ZN(net_1318), .C1(net_1250), .A(net_1199), .B2(net_1148), .B1(net_1120), .C2(net_1101) );
AOI221_X2 inst_3855 ( .B1(net_3736), .ZN(net_2050), .C1(net_2049), .A(net_1931), .C2(net_1732), .B2(net_271) );
NAND2_X2 inst_1795 ( .ZN(net_1183), .A2(net_866), .A1(net_852) );
OAI211_X2 inst_828 ( .ZN(net_1527), .B(net_1266), .A(net_1210), .C1(net_1182), .C2(net_408) );
CLKBUF_X2 inst_4697 ( .A(net_4682), .Z(net_4683) );
DFF_X1 inst_3318 ( .QN(net_3003), .D(net_2847), .CK(net_5113) );
OR2_X4 inst_223 ( .A2(net_4107), .ZN(net_1028), .A1(net_924) );
AND2_X4 inst_4164 ( .ZN(net_4118), .A1(net_3767), .A2(net_3628) );
CLKBUF_X2 inst_5278 ( .A(net_4590), .Z(net_5264) );
INV_X4 inst_2420 ( .ZN(net_281), .A(net_246) );
NAND2_X2 inst_1561 ( .A1(net_2963), .ZN(net_2460), .A2(net_241) );
CLKBUF_X2 inst_5176 ( .A(net_4727), .Z(net_5162) );
AOI22_X2 inst_3564 ( .A1(net_4060), .B1(net_4055), .ZN(net_1486), .B2(net_732), .A2(net_731) );
MUX2_X2 inst_2104 ( .S(net_2919), .Z(net_2574), .A(net_2573), .B(net_147) );
AND2_X2 inst_4205 ( .A1(net_3480), .ZN(net_3392), .A2(net_1770) );
NAND3_X2 inst_1322 ( .A3(net_3243), .ZN(net_725), .A2(net_641), .A1(net_376) );
INV_X4 inst_2573 ( .A(net_3617), .ZN(net_3567) );
NAND2_X1 inst_2096 ( .A2(net_3870), .A1(net_3868), .ZN(net_3453) );
OAI21_X2 inst_552 ( .B2(net_2876), .ZN(net_2875), .A(net_2856), .B1(net_2855) );
INV_X2 inst_3050 ( .A(net_3820), .ZN(net_3819) );
CLKBUF_X2 inst_4793 ( .A(net_4778), .Z(net_4779) );
CLKBUF_X2 inst_4997 ( .A(net_4982), .Z(net_4983) );
AOI22_X2 inst_3493 ( .ZN(net_2233), .A1(net_2231), .B1(net_2230), .B2(net_276), .A2(net_75) );
CLKBUF_X2 inst_4622 ( .A(net_4226), .Z(net_4608) );
INV_X2 inst_3019 ( .ZN(net_3423), .A(net_2613) );
INV_X4 inst_2327 ( .ZN(net_924), .A(net_660) );
AOI221_X2 inst_3913 ( .C2(net_3196), .ZN(net_636), .C1(net_635), .A(net_420), .B2(net_381), .B1(net_210) );
NAND2_X2 inst_1564 ( .A1(net_2963), .ZN(net_2457), .A2(net_470) );
CLKBUF_X2 inst_5078 ( .A(net_5063), .Z(net_5064) );
AOI22_X2 inst_3487 ( .B1(net_4039), .A1(net_4038), .ZN(net_2606), .A2(net_204), .B2(x79) );
AOI22_X2 inst_3597 ( .A1(net_4063), .B1(net_4058), .ZN(net_1420), .A2(net_244), .B2(net_139) );
NAND2_X2 inst_1941 ( .ZN(net_3236), .A1(net_3235), .A2(net_3183) );
INV_X4 inst_2607 ( .A(net_3817), .ZN(net_3814) );
XNOR2_X2 inst_113 ( .A(net_3152), .ZN(net_372), .B(net_316) );
XOR2_X2 inst_9 ( .Z(net_1644), .A(net_1643), .B(net_1642) );
OAI222_X2 inst_356 ( .ZN(net_3969), .A2(net_3968), .B2(net_3967), .C1(net_1261), .A1(net_1141), .B1(net_896), .C2(net_414) );
DFF_X1 inst_3358 ( .D(net_2356), .CK(net_4404), .Q(x350) );
INV_X2 inst_2690 ( .ZN(net_1735), .A(net_1734) );
NAND2_X2 inst_1594 ( .A1(net_2925), .ZN(net_2424), .A2(net_155) );
NOR3_X2 inst_902 ( .A2(net_4104), .A3(net_4079), .ZN(net_989), .A1(net_740) );
AOI22_X2 inst_3489 ( .B1(net_4039), .A1(net_4038), .A2(net_3418), .ZN(net_2604), .B2(x60) );
OAI211_X4 inst_778 ( .ZN(net_3867), .C2(net_3717), .C1(net_3684), .B(net_3672), .A(net_3635) );
CLKBUF_X2 inst_4286 ( .A(net_4271), .Z(net_4272) );
NAND2_X2 inst_1544 ( .A1(net_3207), .ZN(net_2478), .A2(net_176) );
NAND2_X2 inst_1935 ( .ZN(net_3202), .A1(net_3198), .A2(net_230) );
AND3_X4 inst_4063 ( .A2(net_3770), .A1(net_3439), .ZN(net_2055), .A3(net_1808) );
INV_X4 inst_2625 ( .ZN(net_4003), .A(net_4000) );
DFF_X2 inst_3148 ( .D(net_2333), .QN(net_110), .CK(net_4390) );
INV_X8 inst_2140 ( .A(net_3281), .ZN(net_3177) );
CLKBUF_X2 inst_4761 ( .A(net_4485), .Z(net_4747) );
DFF_X1 inst_3329 ( .D(net_2814), .QN(net_119), .CK(net_4457) );
OAI211_X2 inst_781 ( .C1(net_3230), .ZN(net_2806), .A(net_2767), .B(net_2754), .C2(net_2057) );
CLKBUF_X2 inst_5180 ( .A(net_5165), .Z(net_5166) );
AND4_X4 inst_4042 ( .ZN(net_3676), .A2(net_3439), .A4(net_1845), .A1(net_1844), .A3(net_1808) );
INV_X2 inst_3026 ( .ZN(net_3490), .A(net_3104) );
AOI22_X2 inst_3696 ( .B2(net_4123), .A2(net_509), .ZN(net_480), .A1(net_479), .B1(net_478) );
NAND2_X4 inst_1442 ( .ZN(net_3777), .A2(net_3776), .A1(net_3775) );
INV_X2 inst_2847 ( .ZN(net_386), .A(net_373) );
OAI22_X2 inst_332 ( .A2(net_3214), .ZN(net_703), .B2(net_605), .A1(net_541), .B1(net_534) );
AOI22_X2 inst_3639 ( .ZN(net_764), .A2(net_621), .B1(net_577), .B2(net_387), .A1(net_204) );
NAND3_X2 inst_1289 ( .ZN(net_2258), .A1(net_2197), .A3(net_1954), .A2(net_1920) );
INV_X8 inst_2132 ( .ZN(net_359), .A(net_279) );
AOI211_X2 inst_4013 ( .ZN(net_2678), .C1(net_2599), .B(net_2598), .C2(net_1785), .A(net_1687) );
CLKBUF_X2 inst_4979 ( .A(net_4964), .Z(net_4965) );
NAND2_X2 inst_1559 ( .A1(net_2909), .ZN(net_2463), .A2(net_193) );
NAND2_X2 inst_1928 ( .ZN(net_3191), .A1(net_3186), .A2(net_737) );
NAND2_X2 inst_1967 ( .ZN(net_3334), .A2(net_3185), .A1(net_471) );
CLKBUF_X2 inst_4686 ( .A(net_4671), .Z(net_4672) );
CLKBUF_X2 inst_4485 ( .A(net_4452), .Z(net_4471) );
NOR2_X4 inst_927 ( .ZN(net_2177), .A1(net_2095), .A2(net_2031) );
CLKBUF_X2 inst_4869 ( .A(net_4854), .Z(net_4855) );
OAI21_X2 inst_752 ( .ZN(net_3502), .A(net_3501), .B1(net_1599), .B2(net_530) );
DFF_X1 inst_3245 ( .QN(net_3092), .D(net_2940), .CK(net_4737) );
XNOR2_X2 inst_73 ( .ZN(net_1510), .A(net_1509), .B(net_64) );
NAND2_X2 inst_1488 ( .ZN(net_2880), .A1(net_2860), .A2(net_1850) );
NAND2_X2 inst_1719 ( .A1(net_3492), .ZN(net_1866), .A2(net_1694) );
NAND2_X2 inst_1947 ( .ZN(net_3259), .A2(net_3258), .A1(net_3257) );
DFF_X2 inst_3202 ( .D(net_1607), .Q(net_38), .CK(net_4986) );
CLKBUF_X2 inst_4279 ( .A(net_4264), .Z(net_4265) );
OAI221_X2 inst_378 ( .B1(net_2670), .C1(net_2668), .ZN(net_2664), .B2(net_2663), .A(net_1386), .C2(net_315) );
NAND2_X2 inst_1951 ( .ZN(net_3271), .A1(net_2861), .A2(net_2853) );
NAND2_X4 inst_1384 ( .ZN(net_2903), .A1(net_2894), .A2(net_2066) );
CLKBUF_X2 inst_4690 ( .A(net_4675), .Z(net_4676) );
INV_X8 inst_2118 ( .ZN(net_2099), .A(net_1973) );
NOR3_X2 inst_890 ( .A1(net_2521), .ZN(net_2348), .A2(net_544), .A3(net_506) );
INV_X4 inst_2200 ( .ZN(net_2357), .A(net_2266) );
NAND2_X2 inst_1851 ( .A2(net_4003), .ZN(net_810), .A1(net_536) );
CLKBUF_X2 inst_4585 ( .A(net_4335), .Z(net_4571) );
CLKBUF_X2 inst_4937 ( .A(net_4922), .Z(net_4923) );
CLKBUF_X2 inst_4514 ( .A(net_4499), .Z(net_4500) );
CLKBUF_X2 inst_5048 ( .A(net_4256), .Z(net_5034) );
NOR2_X1 inst_1168 ( .A1(net_826), .A2(net_416), .ZN(net_383) );
CLKBUF_X2 inst_4356 ( .A(net_4341), .Z(net_4342) );
OR2_X2 inst_250 ( .ZN(net_1686), .A1(net_1639), .A2(net_1638) );
OAI21_X2 inst_659 ( .A(net_3491), .ZN(net_2548), .B1(net_1747), .B2(net_1317) );
CLKBUF_X2 inst_4363 ( .A(net_4348), .Z(net_4349) );
NOR2_X2 inst_1161 ( .ZN(net_4114), .A1(net_436), .A2(net_400) );
DFF_X1 inst_3362 ( .D(net_2358), .CK(net_4397), .Q(x332) );
CLKBUF_X2 inst_5273 ( .A(net_5258), .Z(net_5259) );
NAND2_X2 inst_1523 ( .A1(net_2959), .ZN(net_2499), .A2(net_780) );
INV_X4 inst_2539 ( .ZN(net_3388), .A(net_3105) );
NOR2_X2 inst_1048 ( .ZN(net_1059), .A1(net_1058), .A2(net_956) );
DFF_X2 inst_3199 ( .QN(net_3170), .D(net_1623), .CK(net_5129) );
INV_X2 inst_2797 ( .A(net_2220), .ZN(net_752) );
AOI22_X2 inst_3612 ( .A1(net_4062), .B1(net_4057), .ZN(net_1405), .B2(net_196), .A2(net_191) );
DFF_X1 inst_3431 ( .Q(net_4023), .D(net_4022), .CK(net_4894) );
NAND2_X2 inst_1581 ( .A1(net_2915), .ZN(net_2439), .A2(net_219) );
INV_X4 inst_2270 ( .ZN(net_1067), .A(net_1066) );
NAND2_X1 inst_2085 ( .A2(net_4013), .A1(net_2965), .ZN(net_2447) );
INV_X4 inst_2388 ( .A(net_3756), .ZN(net_590) );
INV_X4 inst_2401 ( .A(net_3999), .ZN(net_328) );
INV_X4 inst_2312 ( .A(net_3990), .ZN(net_908) );
CLKBUF_X2 inst_4309 ( .A(net_4294), .Z(net_4295) );
AOI22_X2 inst_3500 ( .A1(net_3178), .ZN(net_2133), .B1(net_2099), .A2(net_468), .B2(net_453) );
INV_X2 inst_2634 ( .A(net_2578), .ZN(net_2541) );
CLKBUF_X2 inst_5264 ( .A(net_5249), .Z(net_5250) );
AOI22_X2 inst_3711 ( .A1(net_3815), .ZN(net_3194), .B1(net_3186), .A2(net_781), .B2(net_780) );
INV_X4 inst_2241 ( .ZN(net_2003), .A(net_1905) );
INV_X4 inst_2182 ( .ZN(net_2680), .A(net_2609) );
OAI21_X2 inst_556 ( .B2(net_2915), .B1(net_2871), .ZN(net_2869), .A(net_2437) );
OAI21_X2 inst_650 ( .ZN(net_1877), .B2(net_1821), .A(net_1759), .B1(net_1171) );
OAI22_X2 inst_289 ( .A2(net_4092), .ZN(net_1904), .A1(net_1872), .B2(net_987), .B1(net_681) );
INV_X2 inst_2667 ( .ZN(net_2704), .A(net_2590) );
AOI22_X2 inst_3632 ( .B2(net_1523), .B1(net_1117), .ZN(net_878), .A1(net_784), .A2(net_323) );
AND2_X2 inst_4194 ( .ZN(net_2218), .A1(net_2217), .A2(net_1226) );
NOR2_X2 inst_987 ( .ZN(net_2724), .A1(net_2528), .A2(net_2523) );
OAI221_X2 inst_420 ( .A(net_1257), .C1(net_1256), .ZN(net_1205), .B1(net_959), .B2(net_646), .C2(net_638) );
OAI21_X2 inst_679 ( .B1(net_3228), .ZN(net_1441), .A(net_1307), .B2(net_332) );
CLKBUF_X2 inst_5147 ( .A(net_4736), .Z(net_5133) );
INV_X2 inst_3006 ( .ZN(net_3242), .A(net_3240) );
AOI21_X2 inst_3992 ( .B2(net_3853), .B1(net_3806), .ZN(net_3223), .A(net_3222) );
DFF_X1 inst_3265 ( .QN(net_3071), .D(net_2934), .CK(net_4923) );
DFF_X1 inst_3364 ( .D(net_2331), .QN(net_64), .CK(net_4226) );
NAND3_X2 inst_1351 ( .A1(net_3836), .ZN(net_3641), .A3(net_3639), .A2(net_3547) );
XNOR2_X2 inst_44 ( .ZN(net_2816), .A(net_2636), .B(net_1707) );
CLKBUF_X2 inst_4433 ( .A(net_4415), .Z(net_4419) );
DFF_X1 inst_3300 ( .D(net_2877), .Q(net_73), .CK(net_4280) );
OAI221_X2 inst_371 ( .C2(net_4089), .B2(net_2733), .ZN(net_2687), .C1(net_2686), .A(net_2557), .B1(net_2163) );
NAND3_X2 inst_1305 ( .A3(net_4076), .A1(net_1178), .ZN(net_1175), .A2(net_1046) );
OAI22_X2 inst_314 ( .B2(net_3627), .ZN(net_1144), .A1(net_1143), .B1(net_1142), .A2(net_668) );
OAI221_X2 inst_435 ( .B1(net_920), .A(net_629), .B2(net_628), .C1(net_627), .ZN(net_624), .C2(net_43) );
DFF_X1 inst_3225 ( .QN(net_3055), .D(net_2979), .CK(net_4607) );
CLKBUF_X2 inst_4962 ( .A(net_4947), .Z(net_4948) );
AOI221_X2 inst_3822 ( .B2(net_3143), .A(net_2642), .B1(net_2591), .C1(net_2589), .ZN(net_2556), .C2(net_2555) );
OAI21_X2 inst_597 ( .B2(net_3978), .ZN(net_2546), .A(net_2345), .B1(net_1253) );
CLKBUF_X2 inst_4593 ( .A(net_4578), .Z(net_4579) );
DFF_X1 inst_3307 ( .QN(net_3016), .D(net_2868), .CK(net_5205) );
CLKBUF_X2 inst_4619 ( .A(net_4604), .Z(net_4605) );
NAND2_X2 inst_1587 ( .A1(net_2972), .ZN(net_2432), .A2(net_208) );
NAND4_X2 inst_1185 ( .A1(net_3772), .ZN(net_2153), .A2(net_2042), .A3(net_1891), .A4(net_1097) );
AOI222_X1 inst_3787 ( .A2(net_4105), .C2(net_3656), .ZN(net_1286), .A1(net_1086), .B1(net_890), .C1(net_678), .B2(net_359) );
CLKBUF_X2 inst_4982 ( .A(net_4967), .Z(net_4968) );
OAI21_X2 inst_628 ( .B1(net_2190), .ZN(net_2148), .B2(net_2147), .A(net_2041) );
AOI22_X2 inst_3684 ( .B2(net_4124), .A2(net_509), .ZN(net_499), .A1(net_498), .B1(net_497) );
NAND2_X2 inst_1923 ( .A1(net_3817), .ZN(net_3181), .A2(net_169) );
INV_X2 inst_2748 ( .ZN(net_1110), .A(net_1109) );
INV_X2 inst_3013 ( .A(net_3429), .ZN(net_3398) );
CLKBUF_X2 inst_4744 ( .A(net_4729), .Z(net_4730) );
OAI21_X2 inst_472 ( .B1(net_3509), .ZN(net_2978), .B2(net_2965), .A(net_2445) );
CLKBUF_X2 inst_4533 ( .A(net_4518), .Z(net_4519) );
OAI221_X2 inst_447 ( .ZN(net_3792), .C1(net_988), .B2(net_987), .A(net_876), .B1(net_720), .C2(net_40) );
AOI22_X2 inst_3642 ( .A1(net_4142), .B1(net_4112), .B2(net_1791), .ZN(net_760), .A2(x800) );
OAI21_X4 inst_457 ( .ZN(net_3229), .B1(net_3228), .A(net_1307), .B2(net_316) );
CLKBUF_X2 inst_5087 ( .A(net_5072), .Z(net_5073) );
NAND2_X2 inst_1738 ( .A1(net_2212), .ZN(net_1646), .A2(x1023) );
INV_X4 inst_2623 ( .ZN(net_3958), .A(net_3441) );
INV_X2 inst_2802 ( .ZN(net_728), .A(net_727) );
AND2_X4 inst_4171 ( .ZN(net_4125), .A1(net_3450), .A2(net_359) );
NAND2_X4 inst_1391 ( .ZN(net_2173), .A1(net_2083), .A2(net_1984) );
HA_X1 inst_3092 ( .S(net_1526), .CO(net_1525), .A(net_1306), .B(net_61) );
OAI21_X2 inst_665 ( .B2(net_3149), .ZN(net_1619), .A(net_1531), .B1(net_1465) );
CLKBUF_X2 inst_4843 ( .A(net_4369), .Z(net_4829) );
INV_X2 inst_2734 ( .ZN(net_1384), .A(net_1333) );
CLKBUF_X2 inst_4920 ( .A(net_4905), .Z(net_4906) );
DFF_X1 inst_3395 ( .Q(net_3119), .D(net_1540), .CK(net_4311) );
NOR2_X2 inst_1130 ( .A2(net_3764), .ZN(net_3563), .A1(net_526) );
AOI22_X2 inst_3538 ( .A1(net_1794), .B1(net_1793), .ZN(net_1744), .B2(net_396), .A2(net_229) );
OAI211_X2 inst_855 ( .ZN(net_3748), .C2(net_3747), .B(net_3744), .A(net_3742), .C1(net_3739) );
NAND2_X2 inst_2039 ( .ZN(net_3797), .A1(net_3203), .A2(net_1979) );
AOI222_X1 inst_3755 ( .A1(net_3676), .B1(net_2055), .C1(net_2054), .ZN(net_2038), .B2(net_2037), .C2(net_308), .A2(net_265) );
SDFF_X2 inst_146 ( .D(net_3883), .SE(net_2514), .SI(net_91), .Q(net_91), .CK(net_4945) );
DFF_X1 inst_3233 ( .QN(net_3063), .D(net_2968), .CK(net_4931) );
AOI21_X2 inst_3999 ( .B2(net_3777), .B1(net_3711), .ZN(net_3635), .A(net_749) );
NAND4_X2 inst_1196 ( .ZN(net_1678), .A3(net_1483), .A4(net_1482), .A1(net_1417), .A2(net_1416) );
OAI22_X2 inst_326 ( .B1(net_3619), .ZN(net_930), .A1(net_929), .A2(net_928), .B2(net_299) );
OAI211_X2 inst_817 ( .C1(net_1764), .ZN(net_1726), .A(net_1620), .B(net_1112), .C2(net_406) );
CLKBUF_X2 inst_4295 ( .A(net_4245), .Z(net_4281) );
INV_X4 inst_2194 ( .ZN(net_2531), .A(net_2306) );
DFF_X1 inst_3428 ( .Q(net_4017), .D(net_4016), .CK(net_4906) );
OAI21_X2 inst_518 ( .B2(net_3208), .B1(net_2923), .ZN(net_2922), .A(net_2489) );
NAND3_X2 inst_1363 ( .ZN(net_3888), .A1(net_3698), .A2(net_3390), .A3(net_317) );
CLKBUF_X2 inst_4851 ( .A(net_4836), .Z(net_4837) );
DFF_X1 inst_3336 ( .D(net_3361), .QN(net_117), .CK(net_4456) );
AOI221_X2 inst_3863 ( .B2(net_3116), .B1(net_2020), .C1(net_2019), .ZN(net_2015), .A(net_1896), .C2(x179) );
DFF_X1 inst_3293 ( .QN(net_3011), .D(net_2885), .CK(net_5122) );
INV_X4 inst_2345 ( .A(net_3789), .ZN(net_1011) );
INV_X2 inst_2837 ( .A(net_627), .ZN(net_588) );
AOI222_X1 inst_3793 ( .ZN(net_3677), .A1(net_3676), .B1(net_2055), .C1(net_2054), .B2(net_1791), .C2(net_515), .A2(net_287) );
XNOR2_X2 inst_108 ( .A(net_3818), .ZN(net_427), .B(net_122) );
NAND2_X2 inst_1845 ( .ZN(net_720), .A1(net_641), .A2(net_407) );
CLKBUF_X2 inst_4799 ( .A(net_4441), .Z(net_4785) );
AOI222_X1 inst_3778 ( .ZN(net_1798), .C2(net_1797), .B1(net_1795), .A1(net_1794), .C1(net_1793), .B2(net_1045), .A2(net_224) );
AOI22_X2 inst_3602 ( .A1(net_4059), .B1(net_4057), .A2(net_3024), .B2(net_3022), .ZN(net_1415) );
CLKBUF_X2 inst_5260 ( .A(net_5245), .Z(net_5246) );
AOI21_X2 inst_3940 ( .A(net_2525), .ZN(net_2255), .B1(net_2217), .B2(net_2154) );
CLKBUF_X2 inst_5190 ( .A(net_5175), .Z(net_5176) );
NAND3_X2 inst_1354 ( .ZN(net_3687), .A1(net_3305), .A2(net_2161), .A3(net_1436) );
NAND2_X4 inst_1429 ( .A2(net_3823), .ZN(net_3630), .A1(net_3629) );
NOR2_X4 inst_970 ( .ZN(net_3881), .A2(net_3880), .A1(net_3879) );
NAND3_X2 inst_1278 ( .ZN(net_2825), .A2(net_2597), .A1(net_2577), .A3(net_914) );
AOI222_X1 inst_3763 ( .C1(net_3121), .A1(net_2055), .B1(net_2054), .C2(net_2053), .ZN(net_1999), .B2(net_1281), .A2(net_179) );
OAI21_X2 inst_638 ( .B2(net_2076), .ZN(net_2072), .A(net_1965), .B1(net_1679) );
OAI21_X2 inst_586 ( .ZN(net_2792), .B1(net_2609), .A(net_2391), .B2(net_1275) );
OAI21_X2 inst_749 ( .ZN(net_3403), .B2(net_3124), .B1(net_3108), .A(net_296) );
CLKBUF_X2 inst_5220 ( .A(net_4940), .Z(net_5206) );
NOR2_X2 inst_1030 ( .ZN(net_1795), .A1(net_1459), .A2(net_1036) );
INV_X8 inst_2127 ( .ZN(net_555), .A(net_353) );
INV_X4 inst_2591 ( .A(net_3720), .ZN(net_3680) );
INV_X2 inst_2649 ( .A(net_3883), .ZN(net_2371) );
CLKBUF_X2 inst_5008 ( .A(net_4993), .Z(net_4994) );
DFF_X1 inst_3275 ( .QN(net_3037), .D(net_2926), .CK(net_5179) );
NAND2_X4 inst_1466 ( .A1(net_3933), .ZN(net_3890), .A2(net_767) );
NAND2_X2 inst_1726 ( .A1(net_3599), .ZN(net_1905), .A2(net_1568) );
INV_X2 inst_2841 ( .ZN(net_521), .A(net_399) );
CLKBUF_X2 inst_5221 ( .A(net_5206), .Z(net_5207) );
NAND3_X2 inst_1373 ( .ZN(net_4173), .A1(net_4172), .A3(net_4168), .A2(net_3737) );
INV_X4 inst_2268 ( .ZN(net_1548), .A(net_1022) );
INV_X2 inst_2652 ( .ZN(net_2289), .A(net_2277) );
NAND4_X2 inst_1203 ( .ZN(net_1670), .A3(net_1471), .A4(net_1470), .A1(net_1405), .A2(net_1404) );
INV_X4 inst_2458 ( .A(net_3115), .ZN(net_2637) );
AOI221_X2 inst_3828 ( .B1(net_3469), .B2(net_3141), .C1(net_2534), .ZN(net_2532), .A(net_2337), .C2(net_295) );
OAI22_X2 inst_296 ( .B2(net_3163), .A2(net_2514), .A1(net_1808), .ZN(net_1697), .B1(x475) );
OAI211_X2 inst_802 ( .C1(net_2190), .ZN(net_2166), .C2(net_2165), .A(net_2010), .B(net_1989) );
NOR3_X2 inst_905 ( .A1(net_4113), .A3(net_3387), .A2(net_920), .ZN(net_688) );
DFF_X2 inst_3155 ( .D(net_2255), .QN(net_125), .CK(net_4800) );
DFF_X2 inst_3134 ( .D(net_2627), .QN(net_42), .CK(net_4807) );
CLKBUF_X2 inst_4370 ( .A(net_4355), .Z(net_4356) );
NOR2_X2 inst_1006 ( .A1(net_1807), .ZN(net_1805), .A2(net_1090) );
NAND2_X2 inst_1985 ( .A2(net_4141), .ZN(net_3420), .A1(net_3416) );
CLKBUF_X2 inst_4214 ( .A(net_4197), .Z(net_4200) );
AOI221_X2 inst_3834 ( .ZN(net_2251), .C1(net_2249), .B2(net_1636), .C2(net_1294), .A(net_1227), .B1(net_861) );
AND4_X4 inst_4043 ( .ZN(net_4041), .A3(net_3160), .A1(net_2114), .A4(net_158), .A2(net_85) );
AOI21_X2 inst_3943 ( .B1(net_3774), .ZN(net_2229), .A(net_2146), .B2(net_240) );
AOI22_X2 inst_3651 ( .ZN(net_733), .A1(net_732), .B1(net_731), .A2(net_458), .B2(net_457) );
NAND2_X2 inst_1759 ( .A2(net_1394), .ZN(net_1240), .A1(net_32) );
INV_X4 inst_2615 ( .ZN(net_3859), .A(net_3858) );
INV_X4 inst_2532 ( .ZN(net_3307), .A(net_3306) );
CLKBUF_X2 inst_5134 ( .A(net_5119), .Z(net_5120) );
INV_X4 inst_2463 ( .A(net_3073), .ZN(net_493) );
AOI22_X2 inst_3463 ( .B2(net_4078), .A2(net_3140), .ZN(net_2793), .A1(net_2792), .B1(net_2707) );
CLKBUF_X2 inst_4753 ( .A(net_4738), .Z(net_4739) );
AND4_X2 inst_4055 ( .ZN(net_1761), .A1(net_1760), .A2(net_1548), .A4(net_1264), .A3(net_1225) );
NAND4_X2 inst_1247 ( .ZN(net_3572), .A4(net_3571), .A3(net_1385), .A1(net_1011), .A2(net_618) );
NAND2_X4 inst_1464 ( .ZN(net_3884), .A2(net_3812), .A1(net_2280) );
CLKBUF_X2 inst_5284 ( .A(net_5269), .Z(net_5270) );
CLKBUF_X2 inst_4947 ( .A(net_4932), .Z(net_4933) );
CLKBUF_X2 inst_5031 ( .A(net_5016), .Z(net_5017) );
NAND2_X2 inst_1493 ( .A2(net_3884), .ZN(net_2831), .A1(net_2795) );
NAND3_X2 inst_1308 ( .A3(net_1261), .ZN(net_1134), .A1(net_1053), .A2(net_915) );
CLKBUF_X2 inst_4733 ( .A(net_4718), .Z(net_4719) );
XNOR2_X2 inst_85 ( .B(net_4119), .ZN(net_1748), .A(net_932) );
INV_X1 inst_3070 ( .A(net_3463), .ZN(net_2707) );
CLKBUF_X2 inst_4588 ( .A(net_4524), .Z(net_4574) );
INV_X2 inst_2998 ( .A(net_3066), .ZN(net_139) );
INV_X4 inst_2612 ( .ZN(net_3824), .A(net_3769) );
AND2_X4 inst_4184 ( .A2(net_4162), .ZN(net_4146), .A1(net_3729) );
AND4_X4 inst_4049 ( .ZN(net_4089), .A3(net_562), .A4(net_548), .A2(net_491), .A1(net_477) );
CLKBUF_X2 inst_5067 ( .A(net_5052), .Z(net_5053) );
INV_X2 inst_2702 ( .ZN(net_1675), .A(net_1674) );
INV_X2 inst_2910 ( .ZN(net_1447), .A(net_72) );
CLKBUF_X2 inst_4670 ( .A(net_4655), .Z(net_4656) );
AOI211_X2 inst_4022 ( .C1(net_4084), .C2(net_3915), .ZN(net_1299), .B(net_1110), .A(net_944) );
NAND3_X2 inst_1362 ( .ZN(net_3878), .A3(net_3877), .A2(net_3876), .A1(net_3875) );
DFF_X1 inst_3238 ( .QN(net_3040), .D(net_2928), .CK(net_5191) );
OAI22_X2 inst_290 ( .A1(net_3781), .B1(net_1884), .ZN(net_1864), .A2(net_1714), .B2(net_322) );
SDFF_X2 inst_145 ( .D(net_3866), .SE(net_2625), .SI(net_105), .Q(net_105), .CK(net_4946) );
NAND2_X2 inst_1978 ( .ZN(net_3377), .A1(net_978), .A2(net_872) );
OR2_X2 inst_272 ( .ZN(net_3801), .A1(net_3318), .A2(net_513) );
CLKBUF_X2 inst_4718 ( .A(net_4208), .Z(net_4704) );
INV_X2 inst_2854 ( .A(net_3669), .ZN(net_543) );
INV_X2 inst_3030 ( .ZN(net_3542), .A(net_3540) );
MUX2_X2 inst_2112 ( .A(net_3999), .B(net_3734), .Z(net_1243), .S(net_1178) );
CLKBUF_X2 inst_4594 ( .A(net_4579), .Z(net_4580) );
OAI211_X2 inst_814 ( .B(net_1628), .C1(net_1627), .ZN(net_1624), .A(net_1551), .C2(net_513) );
INV_X2 inst_3036 ( .ZN(net_3589), .A(net_3587) );
INV_X4 inst_2230 ( .ZN(net_1829), .A(net_1681) );
CLKBUF_X2 inst_5203 ( .A(net_5188), .Z(net_5189) );
AND2_X4 inst_4133 ( .ZN(net_4062), .A2(net_3339), .A1(net_1136) );
NAND2_X4 inst_1458 ( .ZN(net_3853), .A2(net_3852), .A1(net_3851) );
AOI22_X2 inst_3471 ( .B2(net_3121), .A1(net_2724), .B1(net_2722), .ZN(net_2719), .A2(net_30) );
OAI211_X2 inst_789 ( .C2(net_2778), .ZN(net_2755), .C1(net_2684), .A(net_2658), .B(net_2604) );
NAND2_X2 inst_1806 ( .A1(net_4082), .ZN(net_1250), .A2(net_912) );
NAND2_X2 inst_1810 ( .ZN(net_1132), .A2(net_899), .A1(net_695) );
NAND2_X2 inst_1860 ( .A2(net_4125), .ZN(net_650), .A1(net_609) );
INV_X4 inst_2275 ( .ZN(net_1196), .A(net_1005) );
NAND2_X2 inst_1885 ( .ZN(net_517), .A2(net_516), .A1(net_403) );
NAND2_X4 inst_1437 ( .ZN(net_3684), .A1(net_3682), .A2(net_86) );
OAI211_X2 inst_822 ( .ZN(net_1657), .A(net_1331), .C2(net_1330), .B(net_1277), .C1(net_1079) );
CLKBUF_X2 inst_4341 ( .A(net_4326), .Z(net_4327) );
NOR2_X2 inst_1125 ( .ZN(net_3454), .A1(net_3453), .A2(net_2986) );
CLKBUF_X2 inst_4885 ( .A(net_4710), .Z(net_4871) );
OAI21_X2 inst_609 ( .B2(net_2815), .ZN(net_2305), .B1(net_2304), .A(net_1792) );
CLKBUF_X2 inst_4477 ( .A(net_4462), .Z(net_4463) );
INV_X4 inst_2533 ( .ZN(net_3313), .A(net_1436) );
INV_X4 inst_2391 ( .ZN(net_412), .A(net_363) );
OAI211_X2 inst_795 ( .C2(net_4069), .ZN(net_2603), .C1(net_2601), .A(net_2387), .B(net_218) );
INV_X4 inst_2496 ( .A(net_2996), .ZN(net_186) );
INV_X4 inst_2239 ( .A(net_1817), .ZN(net_1794) );
XOR2_X1 inst_27 ( .Z(net_1446), .A(net_1445), .B(net_300) );
INV_X4 inst_2491 ( .A(net_3091), .ZN(net_597) );
NAND2_X2 inst_1639 ( .ZN(net_2183), .A2(net_2155), .A1(net_2069) );
CLKBUF_X2 inst_4381 ( .A(net_4236), .Z(net_4367) );
CLKBUF_X2 inst_4446 ( .A(net_4431), .Z(net_4432) );
OAI21_X2 inst_619 ( .ZN(net_2283), .B1(net_2152), .A(net_1799), .B2(net_1738) );
INV_X2 inst_2671 ( .A(net_3772), .ZN(net_2118) );
CLKBUF_X2 inst_5155 ( .A(net_4725), .Z(net_5141) );
NAND2_X2 inst_1654 ( .A2(net_4017), .A1(net_3280), .ZN(net_2128) );
CLKBUF_X2 inst_4547 ( .A(net_4532), .Z(net_4533) );
CLKBUF_X2 inst_5230 ( .A(net_5215), .Z(net_5216) );
OAI21_X2 inst_639 ( .B2(net_2076), .ZN(net_2071), .A(net_1966), .B1(net_1665) );
NAND3_X2 inst_1355 ( .ZN(net_3694), .A1(net_3687), .A2(net_3309), .A3(net_3306) );
NOR3_X4 inst_877 ( .A3(net_3969), .A1(net_3626), .ZN(net_3437), .A2(net_1321) );
SDFF_X2 inst_155 ( .SI(net_4024), .Q(net_4024), .SE(net_2514), .D(net_1784), .CK(net_4936) );
CLKBUF_X2 inst_4858 ( .A(net_4843), .Z(net_4844) );
AOI21_X2 inst_3939 ( .A(net_2300), .ZN(net_2267), .B1(net_2212), .B2(net_248) );
CLKBUF_X2 inst_5309 ( .A(net_5294), .Z(net_5295) );
XNOR2_X2 inst_55 ( .ZN(net_2332), .A(net_2283), .B(net_1780) );
INV_X8 inst_2167 ( .ZN(net_3870), .A(net_3869) );
INV_X4 inst_2280 ( .A(net_1256), .ZN(net_1201) );
NAND2_X2 inst_2076 ( .A2(net_4175), .ZN(net_4167), .A1(net_4166) );
CLKBUF_X2 inst_4248 ( .A(net_4233), .Z(net_4234) );
NAND2_X2 inst_1651 ( .A1(net_2597), .A2(net_2302), .ZN(net_2214) );
AND2_X4 inst_4127 ( .ZN(net_4054), .A2(net_1328), .A1(net_1216) );
INV_X4 inst_2481 ( .A(net_3151), .ZN(net_2665) );
CLKBUF_X2 inst_4285 ( .A(net_4270), .Z(net_4271) );
NOR2_X2 inst_1137 ( .A2(net_3954), .A1(net_3953), .ZN(net_3761) );
OAI22_X2 inst_323 ( .B1(net_2717), .A2(net_1274), .ZN(net_1245), .B2(net_987), .A1(net_831) );
NOR2_X2 inst_1162 ( .ZN(net_4166), .A1(net_1994), .A2(net_73) );
NAND2_X4 inst_1389 ( .A1(net_3537), .ZN(net_2739), .A2(net_2530) );
INV_X2 inst_2973 ( .A(net_3025), .ZN(net_129) );
INV_X16 inst_3065 ( .ZN(net_530), .A(net_337) );
OAI21_X2 inst_715 ( .A(net_1264), .ZN(net_1229), .B1(net_658), .B2(net_652) );
OAI211_X2 inst_793 ( .ZN(net_2692), .B(net_2691), .C2(net_2690), .C1(net_2511), .A(net_2510) );
NAND2_X4 inst_1433 ( .ZN(net_3669), .A1(net_3654), .A2(net_3107) );
NAND2_X2 inst_1494 ( .ZN(net_2824), .A1(net_2790), .A2(net_2323) );
CLKBUF_X2 inst_5206 ( .A(net_4306), .Z(net_5192) );
CLKBUF_X2 inst_5213 ( .A(net_4917), .Z(net_5199) );
NAND2_X2 inst_1894 ( .A2(net_513), .ZN(net_436), .A1(net_377) );
CLKBUF_X2 inst_4815 ( .A(net_4276), .Z(net_4801) );
AOI22_X2 inst_3525 ( .A2(net_3143), .A1(net_1923), .B1(net_1921), .ZN(net_1919), .B2(net_301) );
CLKBUF_X2 inst_4643 ( .A(net_4628), .Z(net_4629) );
NAND2_X2 inst_1999 ( .ZN(net_3491), .A2(net_3331), .A1(net_447) );
NAND2_X2 inst_1682 ( .A1(net_3176), .ZN(net_2024), .A2(net_187) );
CLKBUF_X2 inst_5077 ( .A(net_5062), .Z(net_5063) );
INV_X2 inst_2733 ( .ZN(net_1391), .A(net_1346) );
NAND3_X2 inst_1340 ( .ZN(net_3373), .A1(net_3371), .A3(net_2836), .A2(net_2757) );
NAND2_X4 inst_1481 ( .ZN(net_3967), .A2(net_3959), .A1(net_3958) );
OAI21_X2 inst_475 ( .B1(net_3509), .ZN(net_2975), .B2(net_2959), .A(net_2502) );
CLKBUF_X2 inst_4738 ( .A(net_4308), .Z(net_4724) );
CLKBUF_X2 inst_4412 ( .A(net_4242), .Z(net_4398) );
XOR2_X1 inst_31 ( .A(net_4129), .Z(net_382), .B(net_255) );
INV_X2 inst_2701 ( .ZN(net_1677), .A(net_1676) );
AOI22_X2 inst_3505 ( .B1(net_3676), .B2(net_3145), .A2(net_2037), .ZN(net_2013), .A1(net_2012) );
DFF_X2 inst_3165 ( .D(net_2070), .QN(net_88), .CK(net_5142) );
DFF_X2 inst_3217 ( .D(net_805), .QN(net_332), .CK(net_4616) );
OAI21_X2 inst_575 ( .B2(net_2919), .ZN(net_2804), .B1(net_2803), .A(net_2402) );
CLKBUF_X2 inst_4331 ( .A(net_4197), .Z(net_4317) );
CLKBUF_X2 inst_4376 ( .A(net_4361), .Z(net_4362) );
AOI22_X2 inst_3537 ( .A1(net_1794), .B1(net_1793), .ZN(net_1745), .B2(net_378), .A2(net_216) );
CLKBUF_X2 inst_4705 ( .A(net_4690), .Z(net_4691) );
CLKBUF_X2 inst_4556 ( .A(net_4541), .Z(net_4542) );
OAI21_X2 inst_627 ( .B2(net_4088), .B1(net_2190), .ZN(net_2149), .A(net_2040) );
CLKBUF_X2 inst_4725 ( .A(net_4710), .Z(net_4711) );
DFF_X1 inst_3352 ( .QN(net_3123), .D(net_2700), .CK(net_4820) );
OAI22_X2 inst_344 ( .ZN(net_3552), .A1(net_3551), .A2(net_3496), .B2(net_3492), .B1(net_1691) );
NAND2_X2 inst_1833 ( .A2(net_3627), .ZN(net_1129), .A1(net_614) );
CLKBUF_X2 inst_5301 ( .A(net_5286), .Z(net_5287) );
INV_X8 inst_2122 ( .ZN(net_723), .A(net_435) );
INV_X2 inst_3044 ( .ZN(net_3703), .A(net_1857) );
AOI22_X2 inst_3520 ( .B1(net_4045), .B2(net_3115), .A1(net_1955), .ZN(net_1950), .A2(net_267) );
AOI22_X2 inst_3573 ( .A1(net_4059), .B1(net_4056), .ZN(net_1477), .A2(net_215), .B2(net_187) );
OAI21_X2 inst_623 ( .B1(net_2235), .ZN(net_2158), .A(net_2050), .B2(net_107) );
NOR2_X2 inst_1072 ( .A1(net_2525), .ZN(net_718), .A2(x964) );
AOI22_X2 inst_3580 ( .A1(net_4060), .B1(net_4055), .ZN(net_1470), .A2(net_190), .B2(net_161) );
AOI221_X2 inst_3818 ( .A(net_2642), .B1(net_2641), .C2(net_2581), .C1(net_2563), .ZN(net_2560), .B2(net_267) );
NAND2_X2 inst_1621 ( .A1(net_2917), .ZN(net_2395), .A2(net_141) );
NAND2_X2 inst_1993 ( .ZN(net_3463), .A2(net_2680), .A1(net_2596) );
NAND3_X2 inst_1338 ( .A3(net_3343), .ZN(net_3288), .A1(net_3287), .A2(net_3277) );
INV_X4 inst_2430 ( .A(net_3079), .ZN(net_454) );
INV_X1 inst_3080 ( .A(net_3135), .ZN(net_280) );
CLKBUF_X2 inst_4952 ( .A(net_4937), .Z(net_4938) );
INV_X4 inst_2434 ( .A(net_3055), .ZN(net_475) );
DFF_X1 inst_3226 ( .QN(net_3054), .D(net_2976), .CK(net_4564) );
AOI22_X1 inst_3731 ( .B1(net_4054), .B2(net_1874), .A2(net_1797), .A1(net_1578), .ZN(net_1575) );
NOR2_X2 inst_1107 ( .A1(net_3871), .ZN(net_3233), .A2(net_136) );
AOI22_X2 inst_3617 ( .B1(net_3156), .B2(net_1636), .ZN(net_1325), .A1(net_1324), .A2(net_1228) );
CLKBUF_X2 inst_4839 ( .A(net_4819), .Z(net_4825) );
NAND3_X1 inst_1377 ( .A2(net_3321), .A1(net_1827), .ZN(net_1773), .A3(net_1772) );
NAND2_X2 inst_2028 ( .ZN(net_3742), .A2(net_3741), .A1(net_3739) );
DFF_X2 inst_3125 ( .QN(net_3139), .D(net_2696), .CK(net_4577) );
INV_X4 inst_2201 ( .ZN(net_2361), .A(net_2265) );
CLKBUF_X2 inst_4253 ( .A(net_4238), .Z(net_4239) );
OAI21_X2 inst_722 ( .B2(net_3387), .ZN(net_921), .A(net_662), .B1(net_311) );
INV_X2 inst_2776 ( .ZN(net_832), .A(net_831) );
OAI21_X2 inst_760 ( .ZN(net_3751), .B2(net_3745), .A(net_3229), .B1(net_2623) );
OAI21_X2 inst_746 ( .B1(net_4187), .ZN(net_3367), .B2(net_3366), .A(net_2579) );
NAND2_X2 inst_1696 ( .A2(net_3229), .ZN(net_2876), .A1(net_2049) );
CLKBUF_X2 inst_4232 ( .A(net_4202), .Z(net_4218) );
CLKBUF_X2 inst_4270 ( .A(net_4255), .Z(net_4256) );
INV_X4 inst_2267 ( .ZN(net_2272), .A(net_1099) );
INV_X2 inst_3010 ( .ZN(net_3372), .A(net_3371) );
CLKBUF_X2 inst_4911 ( .A(net_4896), .Z(net_4897) );
CLKBUF_X2 inst_4525 ( .A(net_4510), .Z(net_4511) );
AND2_X4 inst_4115 ( .A2(net_4131), .ZN(net_3616), .A1(net_3220) );
DFF_X2 inst_3133 ( .D(net_2628), .QN(net_40), .CK(net_4808) );
AOI22_X2 inst_3727 ( .ZN(net_3747), .B1(net_3746), .A2(net_3745), .A1(net_3738), .B2(net_67) );
NAND2_X2 inst_1577 ( .A1(net_2965), .ZN(net_2443), .A2(net_559) );
NAND2_X2 inst_1687 ( .A1(net_3219), .ZN(net_1985), .A2(net_235) );
NOR2_X2 inst_1110 ( .A1(net_3752), .ZN(net_3309), .A2(net_1443) );
NAND2_X2 inst_1970 ( .A2(net_3399), .ZN(net_3338), .A1(x475) );
INV_X4 inst_2588 ( .ZN(net_3668), .A(net_3521) );
AOI21_X2 inst_3989 ( .ZN(net_1058), .A(net_881), .B1(net_707), .B2(net_541) );
INV_X2 inst_2873 ( .A(net_3109), .ZN(net_249) );
CLKBUF_X2 inst_4665 ( .A(net_4650), .Z(net_4651) );
INV_X4 inst_2442 ( .A(net_3071), .ZN(net_471) );
AOI22_X2 inst_3569 ( .B1(net_4062), .A1(net_4056), .A2(net_3025), .B2(net_3023), .ZN(net_1481) );
NAND2_X2 inst_2066 ( .ZN(net_3960), .A2(net_3959), .A1(net_3958) );
DFF_X1 inst_3411 ( .D(net_1392), .Q(net_51), .CK(net_4495) );
INV_X4 inst_2524 ( .ZN(net_3262), .A(net_3261) );
NAND2_X4 inst_1446 ( .A2(net_3893), .A1(net_3870), .ZN(net_3799) );
OAI221_X2 inst_390 ( .C2(net_3408), .ZN(net_2363), .B1(net_2361), .C1(net_2225), .A(net_1944), .B2(net_110) );
INV_X4 inst_2421 ( .A(net_3103), .ZN(net_261) );
CLKBUF_X2 inst_4842 ( .A(net_4827), .Z(net_4828) );
NAND2_X2 inst_1742 ( .ZN(net_1595), .A1(net_1440), .A2(net_1439) );
CLKBUF_X2 inst_4466 ( .A(net_4451), .Z(net_4452) );
NOR2_X2 inst_1062 ( .A1(net_3661), .ZN(net_1037), .A2(net_705) );
INV_X2 inst_2663 ( .A(net_3186), .ZN(net_2353) );
INV_X2 inst_2875 ( .ZN(net_303), .A(net_207) );
DFF_X1 inst_3289 ( .QN(net_3048), .D(net_2898), .CK(net_4714) );
CLKBUF_X2 inst_4779 ( .A(net_4764), .Z(net_4765) );
OAI221_X2 inst_401 ( .C2(net_3428), .ZN(net_2236), .B1(net_2235), .C1(net_2044), .A(net_1990), .B2(net_264) );
INV_X4 inst_2302 ( .A(net_3430), .ZN(net_1908) );
DFF_X2 inst_3175 ( .D(net_1864), .QN(net_29), .CK(net_4679) );
DFF_X1 inst_3389 ( .D(net_1729), .QN(net_80), .CK(net_4249) );
DFF_X2 inst_3210 ( .D(net_804), .QN(net_316), .CK(net_4672) );
INV_X4 inst_2447 ( .A(net_2995), .ZN(net_153) );
OAI211_X2 inst_782 ( .ZN(net_2780), .C2(net_2778), .B(net_2677), .C1(net_2669), .A(net_2655) );
CLKBUF_X2 inst_5200 ( .A(net_5185), .Z(net_5186) );
INV_X2 inst_2642 ( .ZN(net_2339), .A(net_2319) );
INV_X2 inst_2869 ( .ZN(net_301), .A(net_50) );
CLKBUF_X2 inst_4653 ( .A(net_4638), .Z(net_4639) );
XOR2_X2 inst_6 ( .A(net_3497), .B(net_3492), .Z(net_1693) );
INV_X4 inst_2486 ( .A(net_3080), .ZN(net_453) );
INV_X4 inst_2410 ( .A(net_3106), .ZN(net_306) );
CLKBUF_X2 inst_4465 ( .A(net_4450), .Z(net_4451) );
CLKBUF_X2 inst_4865 ( .A(net_4850), .Z(net_4851) );
CLKBUF_X2 inst_5250 ( .A(net_5235), .Z(net_5236) );
XNOR2_X2 inst_123 ( .ZN(net_4150), .A(net_3805), .B(net_2811) );
NOR2_X4 inst_930 ( .A1(net_3557), .ZN(net_2030), .A2(net_247) );
CLKBUF_X2 inst_4803 ( .A(net_4788), .Z(net_4789) );
INV_X8 inst_2160 ( .ZN(net_3645), .A(net_1982) );
NOR2_X4 inst_935 ( .A1(net_3324), .ZN(net_435), .A2(net_359) );
CLKBUF_X2 inst_5181 ( .A(net_5166), .Z(net_5167) );
CLKBUF_X2 inst_4772 ( .A(net_4205), .Z(net_4758) );
CLKBUF_X2 inst_4634 ( .A(net_4497), .Z(net_4620) );
INV_X4 inst_2298 ( .ZN(net_1092), .A(net_824) );
OR3_X4 inst_167 ( .ZN(net_1912), .A1(net_1587), .A3(net_1586), .A2(net_1583) );
INV_X2 inst_2944 ( .A(net_3045), .ZN(net_169) );
NOR2_X2 inst_1026 ( .A1(net_1646), .ZN(net_1607), .A2(net_1367) );
NAND3_X2 inst_1320 ( .A1(net_4100), .ZN(net_769), .A3(net_768), .A2(net_206) );
CLKBUF_X2 inst_5011 ( .A(net_4896), .Z(net_4997) );
CLKBUF_X2 inst_4913 ( .A(net_4898), .Z(net_4899) );
AOI221_X2 inst_3874 ( .A(net_4046), .ZN(net_1909), .C2(net_1908), .C1(net_1674), .B2(net_749), .B1(net_99) );
NAND4_X2 inst_1251 ( .A2(net_3911), .ZN(net_3846), .A4(net_3812), .A3(net_3787), .A1(net_3786) );
CLKBUF_X2 inst_5246 ( .A(net_5231), .Z(net_5232) );
XNOR2_X2 inst_95 ( .ZN(net_978), .A(net_713), .B(net_417) );
DFF_X1 inst_3376 ( .D(net_2258), .QN(net_49), .CK(net_4476) );
CLKBUF_X2 inst_4874 ( .A(net_4859), .Z(net_4860) );
INV_X4 inst_2475 ( .ZN(net_323), .A(net_45) );
INV_X2 inst_2921 ( .A(net_3125), .ZN(net_231) );
INV_X2 inst_2862 ( .ZN(net_361), .A(net_192) );
OAI22_X2 inst_331 ( .B2(net_3468), .ZN(net_824), .B1(net_721), .A1(net_641), .A2(net_40) );
AOI21_X2 inst_4009 ( .ZN(net_4160), .B1(net_2243), .A(net_2132), .B2(net_156) );
CLKBUF_X2 inst_4900 ( .A(net_4885), .Z(net_4886) );
INV_X4 inst_2172 ( .ZN(net_2893), .A(net_2880) );
INV_X4 inst_2353 ( .ZN(net_549), .A(net_418) );
OAI21_X2 inst_667 ( .ZN(net_1817), .B1(net_1451), .B2(net_1340), .A(net_1328) );
INV_X2 inst_2762 ( .A(net_3326), .ZN(net_968) );
INV_X2 inst_2896 ( .A(net_3032), .ZN(net_215) );
CLKBUF_X2 inst_4454 ( .A(net_4439), .Z(net_4440) );
NOR2_X2 inst_997 ( .A2(net_3874), .A1(net_3831), .ZN(net_2182) );
NOR4_X2 inst_857 ( .A4(net_4075), .A2(net_4040), .ZN(net_2281), .A3(net_2213), .A1(net_1569) );
CLKBUF_X2 inst_4901 ( .A(net_4886), .Z(net_4887) );
CLKBUF_X2 inst_4824 ( .A(net_4809), .Z(net_4810) );
INV_X2 inst_2691 ( .A(net_3770), .ZN(net_1844) );
AOI22_X2 inst_3590 ( .A1(net_4063), .B1(net_4058), .ZN(net_1427), .B2(net_171), .A2(net_146) );
NAND2_X2 inst_1511 ( .A2(net_3738), .ZN(net_2622), .A1(net_2621) );
CLKBUF_X2 inst_4315 ( .A(net_4300), .Z(net_4301) );
AND2_X4 inst_4179 ( .ZN(net_4136), .A1(net_2161), .A2(net_1436) );
OAI221_X2 inst_365 ( .ZN(net_2734), .B2(net_2733), .C1(net_2732), .C2(net_2731), .B1(net_2645), .A(net_2643) );
AOI21_X2 inst_4006 ( .ZN(net_3931), .B2(net_3930), .B1(net_1167), .A(net_843) );
XNOR2_X2 inst_67 ( .A(net_1718), .ZN(net_1660), .B(net_1456) );
CLKBUF_X2 inst_4243 ( .A(net_4228), .Z(net_4229) );
NOR2_X4 inst_954 ( .ZN(net_3686), .A1(net_3533), .A2(net_3515) );
DFF_X2 inst_3203 ( .Q(net_3157), .D(net_1549), .CK(net_4825) );
CLKBUF_X2 inst_4974 ( .A(net_4959), .Z(net_4960) );
CLKBUF_X2 inst_5073 ( .A(net_5058), .Z(net_5059) );
NAND2_X2 inst_1504 ( .A2(net_3332), .ZN(net_2768), .A1(net_2739) );
INV_X4 inst_2476 ( .A(net_2997), .ZN(net_162) );
DFF_X1 inst_3403 ( .Q(net_4026), .D(net_1467), .CK(net_4509) );
CLKBUF_X2 inst_5084 ( .A(net_5069), .Z(net_5070) );
NAND2_X2 inst_1823 ( .A1(net_4102), .A2(net_4097), .ZN(net_954) );
OR2_X4 inst_202 ( .ZN(net_2963), .A2(net_2352), .A1(net_2351) );
NAND3_X2 inst_1310 ( .A1(net_1279), .ZN(net_1104), .A2(net_1103), .A3(net_1045) );
INV_X4 inst_2212 ( .ZN(net_2263), .A(net_2143) );
DFF_X1 inst_3280 ( .QN(net_3032), .D(net_2913), .CK(net_5083) );
NAND2_X4 inst_1401 ( .ZN(net_451), .A1(net_391), .A2(net_303) );
CLKBUF_X2 inst_4491 ( .A(net_4399), .Z(net_4477) );
CLKBUF_X2 inst_4502 ( .A(net_4443), .Z(net_4488) );
INV_X2 inst_2823 ( .ZN(net_532), .A(net_531) );
CLKBUF_X2 inst_4830 ( .A(net_4206), .Z(net_4816) );
NAND2_X2 inst_2030 ( .A1(net_3995), .ZN(net_3756), .A2(net_3655) );
AOI221_X2 inst_3807 ( .ZN(net_2726), .B1(net_2714), .C2(net_2659), .C1(net_2590), .B2(net_2051), .A(net_1173) );
NOR2_X2 inst_1069 ( .A1(net_2525), .ZN(net_771), .A2(net_770) );
XOR2_X1 inst_30 ( .A(net_4122), .Z(net_512), .B(net_272) );
SDFF_X2 inst_136 ( .D(net_3533), .SE(net_2514), .SI(net_92), .Q(net_92), .CK(net_4963) );
OAI21_X2 inst_610 ( .B2(net_4121), .ZN(net_2352), .A(net_2299), .B1(net_2298) );
AOI22_X2 inst_3541 ( .A1(net_2042), .ZN(net_1605), .B2(net_1463), .B1(net_1453), .A2(net_1377) );
NOR2_X2 inst_1036 ( .A1(net_1340), .ZN(net_1336), .A2(net_1287) );
OR2_X4 inst_233 ( .A1(net_3156), .ZN(net_1884), .A2(net_1173) );
NAND2_X2 inst_1526 ( .A2(net_4015), .A1(net_3208), .ZN(net_2496) );
INV_X4 inst_2547 ( .ZN(net_3447), .A(net_3156) );
CLKBUF_X2 inst_4637 ( .A(net_4622), .Z(net_4623) );
NOR2_X2 inst_1047 ( .ZN(net_1254), .A1(net_1074), .A2(net_898) );
CLKBUF_X2 inst_5167 ( .A(net_4238), .Z(net_5153) );
XNOR2_X2 inst_60 ( .ZN(net_2044), .A(net_2043), .B(net_1596) );
AOI221_X2 inst_3850 ( .A(net_4183), .ZN(net_2068), .C1(net_2067), .C2(net_1908), .B2(net_749), .B1(net_93) );
AOI22_X2 inst_3700 ( .B2(net_4124), .A2(net_555), .ZN(net_472), .A1(net_471), .B1(net_470) );
CLKBUF_X2 inst_4613 ( .A(net_4598), .Z(net_4599) );
NAND2_X2 inst_1858 ( .ZN(net_1264), .A2(net_666), .A1(net_522) );
NAND2_X2 inst_1786 ( .A1(net_2596), .ZN(net_2384), .A2(net_266) );
INV_X4 inst_2376 ( .ZN(net_591), .A(net_411) );
AOI221_X2 inst_3846 ( .B1(net_3736), .ZN(net_2139), .C1(net_2137), .A(net_1870), .B2(net_294), .C2(net_229) );
NAND3_X2 inst_1334 ( .A3(net_3395), .A1(net_528), .ZN(net_442), .A2(net_416) );
CLKBUF_X2 inst_4360 ( .A(net_4345), .Z(net_4346) );
OAI21_X2 inst_496 ( .B1(net_3278), .B2(net_3207), .ZN(net_2946), .A(net_2478) );
NOR4_X2 inst_860 ( .A3(net_3486), .ZN(net_1801), .A1(net_1800), .A4(net_1799), .A2(net_1779) );
OAI21_X2 inst_563 ( .B2(net_2919), .ZN(net_2850), .B1(net_2849), .A(net_2401) );
AOI21_X2 inst_3962 ( .ZN(net_1460), .B1(net_1278), .A(net_1223), .B2(net_1222) );
NOR2_X4 inst_943 ( .ZN(net_3371), .A2(net_3291), .A1(net_2788) );
AOI22_X2 inst_3478 ( .B1(net_4039), .A1(net_2675), .ZN(net_2672), .A2(net_204), .B2(x0) );
AOI222_X1 inst_3749 ( .ZN(net_2069), .B1(net_2017), .C1(net_2016), .A1(net_1893), .A2(net_1881), .C2(net_276), .B2(net_274) );
INV_X4 inst_2620 ( .ZN(net_3927), .A(net_3926) );
CLKBUF_X2 inst_4711 ( .A(net_4696), .Z(net_4697) );
INV_X2 inst_2782 ( .ZN(net_804), .A(net_758) );
NAND2_X2 inst_1964 ( .ZN(net_3315), .A2(net_3314), .A1(net_2161) );
NAND2_X2 inst_1633 ( .A2(net_3516), .A1(net_3248), .ZN(net_2679) );
NAND2_X2 inst_1765 ( .A2(net_1394), .ZN(net_1234), .A1(net_30) );
NAND3_X4 inst_1262 ( .A1(net_3554), .ZN(net_2549), .A3(net_2378), .A2(net_1788) );
CLKBUF_X2 inst_5303 ( .A(net_5288), .Z(net_5289) );
OR2_X2 inst_265 ( .A2(net_3166), .ZN(net_363), .A1(net_322) );
AOI22_X2 inst_3720 ( .ZN(net_3608), .A1(net_3178), .B1(net_2099), .B2(net_518), .A2(net_479) );
NAND2_X2 inst_2005 ( .ZN(net_3532), .A2(net_3531), .A1(net_3530) );
NAND2_X2 inst_2055 ( .ZN(net_3903), .A2(net_3901), .A1(net_3430) );
AOI221_X2 inst_3856 ( .B1(net_3736), .C1(net_2049), .ZN(net_2048), .A(net_1929), .C2(net_1715), .B2(net_300) );
OAI21_X2 inst_544 ( .B2(net_2919), .ZN(net_2888), .B1(net_2887), .A(net_2400) );
OAI21_X2 inst_736 ( .A(net_629), .B1(net_628), .ZN(net_574), .B2(net_361) );
CLKBUF_X2 inst_5091 ( .A(net_5076), .Z(net_5077) );
DFF_X1 inst_3262 ( .QN(net_3074), .D(net_2929), .CK(net_4870) );
OR3_X2 inst_178 ( .ZN(net_2857), .A1(net_2835), .A2(net_2809), .A3(net_2806) );
CLKBUF_X2 inst_4566 ( .A(net_4551), .Z(net_4552) );
CLKBUF_X2 inst_4402 ( .A(net_4387), .Z(net_4388) );
OAI21_X2 inst_734 ( .A(net_629), .B1(net_628), .ZN(net_576), .B2(net_323) );
NAND3_X2 inst_1282 ( .ZN(net_2686), .A2(net_2377), .A3(net_2376), .A1(net_2375) );
NOR2_X2 inst_1077 ( .A1(net_3733), .A2(net_3681), .ZN(net_648) );
NOR2_X2 inst_1148 ( .A1(net_3926), .A2(net_3106), .ZN(net_418) );
AOI221_X2 inst_3919 ( .ZN(net_3843), .B2(net_3842), .B1(net_3841), .C2(net_3789), .C1(net_1369), .A(net_933) );
AOI21_X2 inst_3954 ( .ZN(net_1730), .B1(net_1594), .B2(net_1104), .A(net_1090) );
INV_X2 inst_2757 ( .ZN(net_2187), .A(net_1123) );
OR2_X4 inst_222 ( .A2(net_3997), .ZN(net_1295), .A1(net_877) );
NAND2_X2 inst_1932 ( .A2(net_3869), .A1(net_3261), .ZN(net_3197) );
AOI22_X2 inst_3704 ( .B1(net_4124), .A1(net_509), .ZN(net_464), .B2(net_215), .A2(net_187) );
CLKBUF_X2 inst_4350 ( .A(net_4335), .Z(net_4336) );
AOI22_X2 inst_3587 ( .A1(net_4062), .B1(net_4057), .B2(net_4023), .A2(net_4021), .ZN(net_1430) );
NOR2_X2 inst_1052 ( .A1(net_1154), .ZN(net_1078), .A2(net_1033) );
NAND3_X2 inst_1280 ( .A2(net_3449), .ZN(net_2709), .A3(net_2521), .A1(net_2519) );
NAND3_X2 inst_1302 ( .A1(net_4061), .ZN(net_1341), .A2(net_182), .A3(net_115) );
NAND2_X2 inst_1648 ( .ZN(net_2161), .A1(net_2160), .A2(net_1442) );
OAI211_X2 inst_842 ( .ZN(net_1208), .A(net_1109), .B(net_1010), .C1(net_909), .C2(net_667) );
NOR2_X2 inst_1079 ( .A1(net_3984), .ZN(net_692), .A2(net_385) );
NAND2_X2 inst_2068 ( .ZN(net_3973), .A2(net_3967), .A1(net_923) );
AOI21_X4 inst_3925 ( .B2(net_3600), .ZN(net_3509), .A(net_3508), .B1(net_3342) );
OAI21_X2 inst_551 ( .B1(net_4176), .A(net_4174), .ZN(net_2877), .B2(net_2876) );
INV_X4 inst_2606 ( .ZN(net_3785), .A(net_3662) );
CLKBUF_X2 inst_4314 ( .A(net_4282), .Z(net_4300) );
NAND2_X1 inst_2101 ( .ZN(net_3806), .A1(net_3803), .A2(net_3404) );
INV_X4 inst_2523 ( .ZN(net_3257), .A(net_2310) );
OAI21_X2 inst_506 ( .B1(net_3274), .B2(net_2972), .ZN(net_2936), .A(net_2429) );
OAI222_X2 inst_353 ( .A1(net_2815), .B1(net_1817), .C1(net_1816), .ZN(net_1749), .A2(net_1748), .C2(net_260), .B2(net_106) );
AOI221_X2 inst_3808 ( .C1(net_2724), .ZN(net_2715), .B1(net_2714), .A(net_2525), .B2(net_282), .C2(net_37) );
NAND2_X2 inst_1940 ( .A1(net_3280), .ZN(net_3231), .A2(net_488) );
SDFF_X2 inst_134 ( .D(net_3483), .SI(net_3022), .Q(net_3022), .SE(net_2909), .CK(net_5198) );
INV_X4 inst_2409 ( .ZN(net_1401), .A(net_312) );
DFF_X1 inst_3322 ( .QN(net_2998), .D(net_2845), .CK(net_5200) );
NOR2_X2 inst_1085 ( .ZN(net_444), .A1(net_340), .A2(net_281) );
NAND3_X2 inst_1323 ( .ZN(net_1007), .A1(net_723), .A2(net_528), .A3(net_334) );
DFF_X1 inst_3425 ( .Q(net_4011), .D(net_4010), .CK(net_4919) );
CLKBUF_X2 inst_4632 ( .A(net_4617), .Z(net_4618) );
INV_X4 inst_2328 ( .ZN(net_1018), .A(net_685) );
INV_X2 inst_2655 ( .A(net_3611), .ZN(net_2324) );
OR4_X2 inst_160 ( .A3(net_3771), .A4(net_2054), .ZN(net_1890), .A2(net_1844), .A1(net_1806) );
NAND2_X2 inst_1720 ( .A2(net_1884), .ZN(net_1651), .A1(net_1646) );
AND4_X4 inst_4041 ( .A3(net_3934), .ZN(net_3640), .A4(net_3639), .A2(net_3575), .A1(net_1084) );
AOI22_X2 inst_3701 ( .B2(net_4123), .A2(net_509), .ZN(net_469), .A1(net_468), .B1(net_467) );
DFF_X1 inst_3357 ( .D(net_3710), .CK(net_4408), .Q(x409) );
XOR2_X2 inst_8 ( .B(net_4051), .Z(net_1818), .A(net_1163) );
INV_X2 inst_2912 ( .A(net_3014), .ZN(net_173) );
OAI21_X2 inst_762 ( .ZN(net_3841), .A(net_3840), .B2(net_3620), .B1(net_810) );
OAI221_X2 inst_370 ( .B2(net_2733), .ZN(net_2696), .C1(net_2686), .A(net_2582), .B1(net_2304), .C2(net_1652) );
INV_X2 inst_3025 ( .ZN(net_3466), .A(net_331) );
NAND3_X4 inst_1265 ( .A3(net_4144), .ZN(net_3524), .A2(net_3523), .A1(net_3522) );
NAND2_X1 inst_2090 ( .A2(net_3777), .ZN(net_1565), .A1(net_1322) );
NOR2_X4 inst_965 ( .ZN(net_3825), .A1(net_3824), .A2(net_281) );
DFF_X1 inst_3370 ( .D(net_2287), .CK(net_4222), .Q(x232) );
CLKBUF_X2 inst_4530 ( .A(net_4515), .Z(net_4516) );
NAND3_X2 inst_1321 ( .A2(net_3767), .A1(net_963), .ZN(net_774), .A3(net_543) );
NOR2_X2 inst_1012 ( .A2(net_3961), .ZN(net_1893), .A1(net_1746) );
CLKBUF_X2 inst_5255 ( .A(net_5240), .Z(net_5241) );
NOR3_X2 inst_901 ( .A1(net_1650), .ZN(net_1047), .A2(net_1046), .A3(net_1045) );
NAND2_X2 inst_1956 ( .ZN(net_3294), .A1(net_3293), .A2(net_200) );
AOI22_X2 inst_3492 ( .B1(net_3469), .B2(net_3138), .A1(net_2534), .ZN(net_2276), .A2(net_287) );
OAI21_X2 inst_751 ( .ZN(net_3495), .B1(net_3494), .A(net_3493), .B2(net_3491) );
DFF_X2 inst_3149 ( .QN(net_3128), .D(net_2355), .CK(net_5145) );
CLKBUF_X2 inst_4283 ( .A(net_4268), .Z(net_4269) );
INV_X4 inst_2403 ( .ZN(net_326), .A(net_325) );
INV_X4 inst_2471 ( .ZN(net_138), .A(net_52) );
AOI211_X2 inst_4034 ( .ZN(net_4153), .B(net_1208), .C1(net_1196), .A(net_1066), .C2(net_407) );
OAI221_X2 inst_377 ( .B1(net_2670), .C1(net_2668), .ZN(net_2667), .B2(net_2666), .C2(net_2665), .A(net_593) );
CLKBUF_X2 inst_4948 ( .A(net_4933), .Z(net_4934) );
CLKBUF_X2 inst_4760 ( .A(net_4745), .Z(net_4746) );
NAND2_X2 inst_1934 ( .ZN(net_3201), .A1(net_3198), .A2(net_141) );
AOI21_X2 inst_3946 ( .B1(net_3774), .ZN(net_2219), .A(net_2151), .B2(net_300) );
HA_X1 inst_3098 ( .CO(net_766), .S(net_677), .B(net_504), .A(net_452) );
DFF_X1 inst_3244 ( .QN(net_3093), .D(net_2954), .CK(net_4784) );
AOI221_X2 inst_3916 ( .B1(net_3504), .ZN(net_3470), .C1(net_3469), .A(net_3467), .C2(net_3143), .B2(net_402) );
AOI221_X1 inst_3920 ( .C1(net_3241), .B2(net_3132), .B1(net_2591), .C2(net_2589), .ZN(net_2566), .A(net_1090) );
AOI221_X2 inst_3821 ( .A(net_2642), .B1(net_2641), .C1(net_2581), .ZN(net_2557), .C2(net_2553), .B2(net_295) );
INV_X2 inst_3018 ( .ZN(net_3418), .A(net_40) );
INV_X1 inst_3078 ( .A(net_3478), .ZN(net_649) );
CLKBUF_X2 inst_5013 ( .A(net_4825), .Z(net_4999) );
CLKBUF_X2 inst_4623 ( .A(net_4532), .Z(net_4609) );
CLKBUF_X2 inst_5054 ( .A(net_4480), .Z(net_5040) );
AOI221_X2 inst_3835 ( .B1(net_3774), .ZN(net_2234), .C1(net_2227), .A(net_2107), .B2(net_1511), .C2(net_869) );
CLKBUF_X2 inst_4627 ( .A(net_4612), .Z(net_4613) );
NAND2_X1 inst_2097 ( .A2(net_3876), .A1(net_3875), .ZN(net_3577) );
CLKBUF_X2 inst_4484 ( .A(net_4469), .Z(net_4470) );
NOR2_X4 inst_928 ( .A1(net_3283), .ZN(net_2095), .A2(net_129) );
XNOR2_X2 inst_107 ( .A(net_3123), .B(net_3103), .ZN(net_428) );
INV_X8 inst_2117 ( .A(net_3520), .ZN(net_2292) );
NOR2_X2 inst_990 ( .A1(net_2641), .ZN(net_2581), .A2(net_2377) );
DFF_X2 inst_3140 ( .QN(net_2984), .D(net_2570), .CK(net_5237) );
CLKBUF_X2 inst_4710 ( .A(net_4620), .Z(net_4696) );
NAND2_X2 inst_1539 ( .A1(net_2907), .ZN(net_2483), .A2(net_172) );
INV_X2 inst_2662 ( .ZN(net_2107), .A(net_2034) );
AOI22_X2 inst_3628 ( .ZN(net_1138), .A2(net_721), .B2(net_641), .B1(net_387), .A1(net_261) );
NAND2_X2 inst_1718 ( .ZN(net_2144), .A1(net_1639), .A2(net_1638) );
NOR2_X2 inst_1050 ( .A2(net_3559), .A1(net_1228), .ZN(net_1039) );
INV_X4 inst_2366 ( .ZN(net_911), .A(net_891) );
CLKBUF_X2 inst_4642 ( .A(net_4627), .Z(net_4628) );
CLKBUF_X2 inst_5049 ( .A(net_5034), .Z(net_5035) );
DFF_X1 inst_3316 ( .QN(net_3005), .D(net_2851), .CK(net_5201) );
NAND3_X2 inst_1296 ( .ZN(net_1663), .A1(net_1584), .A2(net_1335), .A3(net_1286) );
CLKBUF_X2 inst_4661 ( .A(net_4646), .Z(net_4647) );
CLKBUF_X2 inst_4411 ( .A(net_4274), .Z(net_4397) );
NAND2_X2 inst_1852 ( .A1(net_4164), .A2(net_4116), .ZN(net_695) );
AOI22_X2 inst_3671 ( .A2(net_571), .B2(net_570), .ZN(net_553), .A1(net_552), .B1(net_551) );
DFF_X1 inst_3282 ( .QN(net_3031), .D(net_2918), .CK(net_5172) );
AOI211_X2 inst_4014 ( .ZN(net_2526), .A(net_2525), .B(net_2348), .C1(net_2303), .C2(net_207) );
CLKBUF_X2 inst_4605 ( .A(net_4590), .Z(net_4591) );
AOI22_X2 inst_3694 ( .B1(net_4124), .A2(net_509), .ZN(net_482), .B2(net_195), .A1(net_194) );
AND3_X4 inst_4074 ( .A3(net_4116), .ZN(net_4070), .A2(net_4001), .A1(net_1036) );
CLKBUF_X2 inst_4513 ( .A(net_4256), .Z(net_4499) );
AOI222_X1 inst_3783 ( .B2(net_2020), .C1(net_1840), .ZN(net_1700), .A1(net_1699), .A2(net_1698), .B1(net_673), .C2(net_142) );
NAND2_X2 inst_1557 ( .A1(net_2909), .ZN(net_2465), .A2(net_173) );
CLKBUF_X2 inst_4882 ( .A(net_4530), .Z(net_4868) );
INV_X4 inst_2399 ( .A(net_528), .ZN(net_385) );
INV_X2 inst_2698 ( .ZN(net_1683), .A(net_1682) );
NAND4_X2 inst_1237 ( .A2(net_3993), .A1(net_3713), .A4(net_3657), .ZN(net_2374), .A3(net_403) );
DFF_X1 inst_3412 ( .D(net_1354), .Q(net_37), .CK(net_4468) );
CLKBUF_X2 inst_4698 ( .A(net_4683), .Z(net_4684) );
CLKBUF_X2 inst_4452 ( .A(net_4324), .Z(net_4438) );
INV_X4 inst_2518 ( .ZN(net_3204), .A(net_3198) );
CLKBUF_X2 inst_5152 ( .A(net_4874), .Z(net_5138) );
NAND2_X2 inst_1616 ( .A1(net_2919), .ZN(net_2400), .A2(net_214) );
NAND2_X2 inst_2075 ( .ZN(net_4165), .A1(net_4164), .A2(net_3974) );
INV_X2 inst_3062 ( .ZN(net_4177), .A(net_1502) );
DFF_X1 inst_3310 ( .QN(net_3017), .D(net_2872), .CK(net_5163) );
NAND2_X2 inst_1911 ( .A2(net_3108), .ZN(net_296), .A1(net_207) );
AND2_X4 inst_4151 ( .A1(net_4118), .A2(net_4116), .ZN(net_4099) );
NAND2_X2 inst_1825 ( .A1(net_4099), .A2(net_3900), .ZN(net_899) );
OAI21_X2 inst_585 ( .B2(net_3428), .ZN(net_2702), .B1(net_2587), .A(net_2046) );
NAND2_X2 inst_1606 ( .A1(net_2967), .ZN(net_2410), .A2(net_212) );
INV_X2 inst_2851 ( .ZN(net_342), .A(net_341) );
CLKBUF_X2 inst_5100 ( .A(net_4501), .Z(net_5086) );
CLKBUF_X2 inst_5126 ( .A(net_4453), .Z(net_5112) );
OAI221_X2 inst_410 ( .A(net_3572), .C1(net_1884), .ZN(net_1549), .B1(net_1548), .B2(net_1521), .C2(net_1032) );
OAI22_X2 inst_316 ( .B1(net_3136), .ZN(net_1705), .A1(net_1123), .A2(net_1071), .B2(net_1036) );
CLKBUF_X2 inst_5107 ( .A(net_4309), .Z(net_5093) );
NOR2_X1 inst_1174 ( .ZN(net_4194), .A1(net_1212), .A2(net_743) );
NOR2_X2 inst_1023 ( .A1(net_3492), .ZN(net_1687), .A2(net_1640) );
OAI221_X2 inst_383 ( .C1(net_3875), .B2(net_2699), .C2(net_2698), .ZN(net_2629), .A(net_2535), .B1(net_2371) );
INV_X4 inst_2428 ( .A(net_3083), .ZN(net_552) );
CLKBUF_X2 inst_5115 ( .A(net_5100), .Z(net_5101) );
AND2_X4 inst_4132 ( .ZN(net_4061), .A2(net_1280), .A1(net_1085) );
DFF_X2 inst_3186 ( .QN(net_3104), .D(net_1730), .CK(net_5140) );
OAI21_X2 inst_678 ( .B1(net_3228), .B2(net_3152), .ZN(net_1509), .A(net_1307) );
NOR2_X2 inst_1124 ( .A2(net_3958), .ZN(net_3435), .A1(net_3434) );
AND3_X2 inst_4086 ( .A1(net_1517), .ZN(net_1060), .A3(net_965), .A2(net_797) );
AOI222_X1 inst_3762 ( .C1(net_3120), .A1(net_2055), .B1(net_2054), .C2(net_2053), .ZN(net_2000), .B2(net_1345), .A2(net_228) );
OAI211_X2 inst_854 ( .ZN(net_3363), .C2(net_3354), .C1(net_2190), .A(net_2008), .B(net_2001) );
DFF_X1 inst_3259 ( .QN(net_3077), .D(net_2936), .CK(net_4930) );
CLKBUF_X2 inst_4359 ( .A(net_4259), .Z(net_4345) );
INV_X4 inst_2555 ( .A(net_3653), .ZN(net_3488) );
DFF_X1 inst_3375 ( .D(net_2261), .QN(net_48), .CK(net_4513) );
OR2_X4 inst_234 ( .A1(net_3468), .ZN(net_341), .A2(net_329) );
CLKBUF_X2 inst_5293 ( .A(net_5278), .Z(net_5279) );
AOI22_X2 inst_3678 ( .B2(net_4124), .A2(net_555), .ZN(net_520), .A1(net_519), .B1(net_518) );
CLKBUF_X2 inst_5240 ( .A(net_5225), .Z(net_5226) );
AOI21_X2 inst_3979 ( .B1(net_4079), .ZN(net_1040), .A(net_986), .B2(net_528) );
NAND2_X2 inst_1946 ( .A2(net_4015), .ZN(net_3250), .A1(net_3219) );
AOI22_X2 inst_3714 ( .A2(net_3966), .B1(net_3661), .ZN(net_3434), .A1(net_1255), .B2(net_667) );
CLKBUF_X2 inst_5285 ( .A(net_5270), .Z(net_5271) );
NAND3_X2 inst_1304 ( .A3(net_1613), .A1(net_1548), .ZN(net_1315), .A2(net_857) );
DFF_X1 inst_3429 ( .Q(net_4019), .D(net_4018), .CK(net_4903) );
NAND3_X2 inst_1328 ( .A3(net_3395), .ZN(net_1024), .A2(net_666), .A1(net_539) );
OAI21_X2 inst_688 ( .A(net_1257), .B1(net_1256), .ZN(net_1184), .B2(net_819) );
NAND2_X2 inst_1749 ( .ZN(net_1372), .A1(net_1305), .A2(net_240) );
INV_X4 inst_2549 ( .ZN(net_3450), .A(net_3106) );
DFF_X1 inst_3292 ( .QN(net_3012), .D(net_2882), .CK(net_5126) );
NAND2_X2 inst_1776 ( .ZN(net_1106), .A2(net_1105), .A1(net_989) );
AOI22_X2 inst_3641 ( .A1(net_4142), .B1(net_4112), .ZN(net_761), .B2(net_379), .A2(x825) );
CLKBUF_X2 inst_4894 ( .A(net_4879), .Z(net_4880) );
CLKBUF_X2 inst_5024 ( .A(net_5009), .Z(net_5010) );
INV_X4 inst_2335 ( .ZN(net_668), .A(net_667) );
INV_X4 inst_2387 ( .ZN(net_1386), .A(net_1173) );
NOR3_X1 inst_919 ( .A1(net_3463), .A3(net_3103), .ZN(net_2745), .A2(net_2717) );
CLKBUF_X2 inst_4391 ( .A(net_4229), .Z(net_4377) );
OAI21_X2 inst_598 ( .B2(net_3127), .ZN(net_2509), .B1(net_2507), .A(net_2297) );
NAND2_X2 inst_1916 ( .ZN(net_632), .A1(net_253), .A2(net_43) );
DFF_X2 inst_3156 ( .QN(net_3130), .D(net_2183), .CK(net_5289) );
INV_X2 inst_2747 ( .A(net_1275), .ZN(net_1146) );
OAI211_X2 inst_840 ( .ZN(net_1263), .A(net_1257), .C1(net_1256), .C2(net_1117), .B(net_1062) );
NAND2_X2 inst_1624 ( .ZN(net_2615), .A1(net_2391), .A2(net_2302) );
NAND4_X2 inst_1220 ( .ZN(net_1123), .A4(net_782), .A3(net_553), .A2(net_469), .A1(net_455) );
NAND2_X4 inst_1456 ( .A1(net_3906), .ZN(net_3837), .A2(net_3836) );
INV_X4 inst_2181 ( .A(net_3230), .ZN(net_2738) );
NAND2_X2 inst_1797 ( .A1(net_2522), .ZN(net_994), .A2(net_947) );
DFF_X2 inst_3167 ( .QN(net_3164), .D(net_1974), .CK(net_4966) );
CLKBUF_X2 inst_4408 ( .A(net_4393), .Z(net_4394) );
INV_X2 inst_2708 ( .ZN(net_1751), .A(net_1648) );
CLKBUF_X2 inst_5154 ( .A(net_5139), .Z(net_5140) );
CLKBUF_X2 inst_4294 ( .A(net_4279), .Z(net_4280) );
AND2_X2 inst_4195 ( .A2(net_1946), .ZN(net_1781), .A1(net_1684) );
AOI22_X2 inst_3530 ( .B1(net_2017), .ZN(net_1894), .A1(net_1893), .A2(net_1880), .B2(net_128) );
CLKBUF_X2 inst_5009 ( .A(net_4994), .Z(net_4995) );
CLKBUF_X2 inst_4785 ( .A(net_4770), .Z(net_4771) );
CLKBUF_X2 inst_4440 ( .A(net_4425), .Z(net_4426) );
INV_X4 inst_2592 ( .ZN(net_3682), .A(net_3636) );
OAI22_X2 inst_325 ( .A1(net_4089), .B2(net_3142), .ZN(net_1642), .A2(net_931), .B1(net_433) );
CLKBUF_X2 inst_4769 ( .A(net_4402), .Z(net_4755) );
NAND4_X2 inst_1197 ( .ZN(net_1769), .A3(net_1481), .A4(net_1480), .A2(net_1415), .A1(net_1414) );
DFF_X2 inst_3116 ( .QN(net_3154), .D(net_2760), .CK(net_4684) );
CLKBUF_X2 inst_4378 ( .A(net_4363), .Z(net_4364) );
NOR2_X4 inst_955 ( .A1(net_3821), .ZN(net_3698), .A2(net_3543) );
AND2_X2 inst_4199 ( .A1(net_4061), .ZN(net_1345), .A2(net_114) );
XNOR2_X2 inst_114 ( .A(net_3153), .ZN(net_354), .B(net_332) );
INV_X4 inst_2278 ( .A(net_2596), .ZN(net_2518) );
CLKBUF_X2 inst_4866 ( .A(net_4851), .Z(net_4852) );
OAI21_X2 inst_617 ( .B2(net_3407), .ZN(net_2266), .A(net_2264), .B1(net_2263) );
AND2_X4 inst_4150 ( .ZN(net_4095), .A1(net_636), .A2(net_427) );
OAI21_X2 inst_534 ( .B1(net_3195), .B2(net_2965), .ZN(net_2899), .A(net_2446) );
CLKBUF_X2 inst_4420 ( .A(net_4405), .Z(net_4406) );
NOR2_X2 inst_1057 ( .A1(net_3838), .A2(net_3567), .ZN(net_976) );
CLKBUF_X2 inst_5191 ( .A(net_4908), .Z(net_5177) );
INV_X2 inst_2842 ( .A(net_3941), .ZN(net_391) );
CLKBUF_X2 inst_5193 ( .A(net_5178), .Z(net_5179) );
NAND2_X1 inst_2084 ( .A2(net_4019), .A1(net_2963), .ZN(net_2461) );
INV_X2 inst_2836 ( .A(net_825), .ZN(net_607) );
AOI222_X1 inst_3792 ( .ZN(net_3323), .A2(net_3319), .B2(net_826), .C2(net_825), .A1(net_724), .B1(net_618), .C1(net_528) );
CLKBUF_X2 inst_4336 ( .A(net_4321), .Z(net_4322) );
OAI21_X2 inst_748 ( .B2(net_4195), .ZN(net_3375), .A(net_3374), .B1(net_818) );
INV_X2 inst_2839 ( .A(net_3468), .ZN(net_402) );
CLKBUF_X2 inst_4582 ( .A(net_4567), .Z(net_4568) );
INV_X2 inst_2770 ( .ZN(net_886), .A(net_885) );
CLKBUF_X2 inst_4573 ( .A(net_4558), .Z(net_4559) );
CLKBUF_X2 inst_4526 ( .A(net_4511), .Z(net_4512) );
OAI211_X2 inst_803 ( .C1(net_2190), .ZN(net_2132), .C2(net_2131), .A(net_2011), .B(net_2002) );
CLKBUF_X2 inst_4587 ( .A(net_4572), .Z(net_4573) );
NAND2_X2 inst_1986 ( .A2(net_4142), .ZN(net_3428), .A1(net_3427) );
INV_X2 inst_2909 ( .ZN(net_206), .A(net_82) );
CLKBUF_X2 inst_4732 ( .A(net_4465), .Z(net_4718) );
NAND2_X2 inst_1949 ( .A2(net_3281), .ZN(net_3265), .A1(net_147) );
INV_X4 inst_2348 ( .A(net_707), .ZN(net_589) );
DFF_X2 inst_3135 ( .QN(net_2987), .D(net_2571), .CK(net_5156) );
AOI211_X2 inst_4021 ( .ZN(net_1371), .C2(net_1228), .B(net_1194), .A(net_1130), .C1(net_949) );
OAI21_X2 inst_701 ( .A(net_3925), .B2(net_3478), .ZN(net_1116), .B1(net_699) );
OAI21_X2 inst_662 ( .B1(net_4100), .ZN(net_1841), .B2(net_1701), .A(net_1591) );
INV_X2 inst_2911 ( .ZN(net_2286), .A(net_69) );
NAND2_X2 inst_1533 ( .A1(net_3208), .ZN(net_2489), .A2(net_235) );
INV_X4 inst_2380 ( .A(net_3633), .ZN(net_432) );
AOI22_X2 inst_3495 ( .B2(net_3818), .A1(net_2231), .B1(net_2230), .ZN(net_2224), .A2(net_74) );
CLKBUF_X2 inst_5261 ( .A(net_5246), .Z(net_5247) );
NAND2_X2 inst_1859 ( .A2(net_3440), .A1(net_923), .ZN(net_608) );
CLKBUF_X2 inst_5080 ( .A(net_5065), .Z(net_5066) );
CLKBUF_X2 inst_4666 ( .A(net_4651), .Z(net_4652) );
NAND2_X4 inst_1465 ( .ZN(net_3886), .A1(net_2292), .A2(net_2210) );
CLKBUF_X2 inst_5030 ( .A(net_5015), .Z(net_5016) );
XNOR2_X2 inst_53 ( .A(net_3876), .B(net_3515), .ZN(net_2811) );
CLKBUF_X2 inst_5265 ( .A(net_5250), .Z(net_5251) );
NOR2_X2 inst_1007 ( .ZN(net_2202), .A1(net_1790), .A2(net_1734) );
INV_X2 inst_2815 ( .A(net_3755), .ZN(net_1045) );
AND2_X2 inst_4208 ( .ZN(net_3501), .A1(net_1187), .A2(net_741) );
AOI22_X2 inst_3605 ( .A1(net_4063), .B1(net_4058), .ZN(net_1412), .A2(net_552), .B2(net_551) );
INV_X4 inst_2614 ( .ZN(net_3842), .A(net_3834) );
DFF_X1 inst_3337 ( .Q(net_3141), .D(net_2789), .CK(net_4771) );
CLKBUF_X2 inst_5066 ( .A(net_5051), .Z(net_5052) );
CLKBUF_X2 inst_4215 ( .A(net_4200), .Z(net_4201) );
OAI21_X2 inst_651 ( .B2(net_3492), .ZN(net_2598), .A(net_2548), .B1(net_1741) );
AND3_X2 inst_4090 ( .ZN(net_3467), .A3(net_3466), .A1(net_2129), .A2(net_2126) );
NOR2_X2 inst_999 ( .A2(net_4049), .ZN(net_2152), .A1(net_2120) );
MUX2_X2 inst_2111 ( .A(net_1774), .Z(net_1403), .S(net_1228), .B(net_321) );
INV_X2 inst_2883 ( .A(net_987), .ZN(net_387) );
NOR2_X2 inst_1157 ( .ZN(net_4081), .A1(net_765), .A2(net_371) );
NAND2_X2 inst_1846 ( .ZN(net_742), .A1(net_613), .A2(net_414) );
INV_X8 inst_2139 ( .A(net_3177), .ZN(net_3176) );
CLKBUF_X2 inst_4278 ( .A(net_4263), .Z(net_4264) );
NAND2_X4 inst_1463 ( .A1(net_3911), .ZN(net_3883), .A2(net_3303) );
OR3_X2 inst_186 ( .ZN(net_3351), .A2(net_3348), .A1(net_2550), .A3(net_1737) );
CLKBUF_X2 inst_4271 ( .A(net_4256), .Z(net_4257) );
AOI22_X2 inst_3528 ( .A2(net_3145), .A1(net_1923), .B1(net_1921), .ZN(net_1916), .B2(net_686) );
OAI21_X2 inst_759 ( .ZN(net_3741), .A(net_3740), .B1(net_2876), .B2(net_67) );
INV_X1 inst_3071 ( .A(net_3691), .ZN(net_2506) );
NAND2_X2 inst_2061 ( .ZN(net_3918), .A1(net_3653), .A2(net_3107) );
AOI22_X2 inst_3685 ( .B2(net_4123), .A2(net_509), .ZN(net_496), .A1(net_495), .B1(net_189) );
CLKBUF_X2 inst_4255 ( .A(net_4240), .Z(net_4241) );
NOR4_X2 inst_863 ( .ZN(net_1515), .A2(net_1262), .A1(net_1260), .A4(net_1248), .A3(net_1145) );
NAND2_X4 inst_1472 ( .A2(net_4003), .A1(net_3992), .ZN(net_3922) );
CLKBUF_X2 inst_4261 ( .A(net_4203), .Z(net_4247) );
NAND2_X4 inst_1385 ( .ZN(net_2878), .A1(net_2831), .A2(net_2808) );
NAND2_X2 inst_1573 ( .A1(net_2915), .ZN(net_2448), .A2(net_153) );
NAND4_X2 inst_1183 ( .A4(net_3650), .A3(net_3192), .ZN(net_2207), .A2(net_2089), .A1(net_2080) );
AOI222_X1 inst_3784 ( .B1(net_2020), .C1(net_1840), .A1(net_1698), .ZN(net_1680), .B2(net_324), .A2(net_251), .C2(net_228) );
NAND2_X4 inst_1390 ( .A1(net_3188), .A2(net_3180), .ZN(net_2178) );
AOI22_X2 inst_3586 ( .A1(net_4062), .B1(net_4057), .ZN(net_1431), .A2(net_230), .B2(net_148) );
OR2_X4 inst_229 ( .ZN(net_988), .A2(net_516), .A1(net_384) );
INV_X4 inst_2282 ( .ZN(net_1202), .A(net_959) );
NAND2_X2 inst_1489 ( .ZN(net_2861), .A1(net_2852), .A2(net_2516) );
CLKBUF_X2 inst_5272 ( .A(net_5257), .Z(net_5258) );
CLKBUF_X2 inst_4992 ( .A(net_4977), .Z(net_4978) );
INV_X4 inst_2415 ( .A(net_3122), .ZN(net_1523) );
CLKBUF_X2 inst_4689 ( .A(net_4674), .Z(net_4675) );
INV_X4 inst_2262 ( .ZN(net_1166), .A(net_1095) );
DFF_X1 inst_3288 ( .QN(net_3047), .D(net_2900), .CK(net_4772) );
CLKBUF_X2 inst_4981 ( .A(net_4242), .Z(net_4967) );
NOR2_X2 inst_1160 ( .ZN(net_4113), .A1(net_1326), .A2(net_449) );
NAND2_X4 inst_1394 ( .A1(net_3219), .ZN(net_1984), .A2(net_176) );
INV_X8 inst_2131 ( .A(net_3642), .ZN(net_357) );
NAND2_X2 inst_1808 ( .A1(net_4082), .ZN(net_1332), .A2(net_911) );
NOR2_X2 inst_988 ( .ZN(net_2355), .A1(net_2301), .A2(net_1090) );
NAND2_X2 inst_1876 ( .ZN(net_450), .A1(net_411), .A2(net_390) );
OR3_X4 inst_169 ( .ZN(net_1701), .A1(net_1232), .A3(net_1173), .A2(net_947) );
OAI221_X2 inst_421 ( .C1(net_3560), .ZN(net_1194), .A(net_1057), .B1(net_964), .B2(net_877), .C2(net_408) );
CLKBUF_X2 inst_4954 ( .A(net_4939), .Z(net_4940) );
NAND3_X2 inst_1315 ( .A1(net_4087), .ZN(net_974), .A3(net_619), .A2(x475) );
CLKBUF_X2 inst_5035 ( .A(net_4325), .Z(net_5021) );
OAI21_X2 inst_555 ( .B2(net_2917), .B1(net_2871), .ZN(net_2870), .A(net_2420) );
CLKBUF_X2 inst_4759 ( .A(net_4744), .Z(net_4745) );
OAI211_X2 inst_816 ( .C2(net_3319), .B(net_1628), .C1(net_1627), .ZN(net_1622), .A(net_1558) );
INV_X4 inst_2392 ( .A(net_3324), .ZN(net_416) );
CLKBUF_X2 inst_4308 ( .A(net_4235), .Z(net_4294) );
CLKBUF_X2 inst_4678 ( .A(net_4581), .Z(net_4664) );
INV_X2 inst_2798 ( .ZN(net_1655), .A(net_869) );
AOI22_X2 inst_3667 ( .A1(net_571), .B1(net_570), .ZN(net_560), .A2(net_559), .B2(net_558) );
NAND4_X2 inst_1184 ( .ZN(net_2179), .A1(net_2004), .A4(net_1971), .A2(net_1925), .A3(net_1915) );
CLKBUF_X2 inst_4434 ( .A(net_4419), .Z(net_4420) );
CLKBUF_X2 inst_4685 ( .A(net_4670), .Z(net_4671) );
CLKBUF_X2 inst_4967 ( .A(net_4952), .Z(net_4953) );
OAI21_X2 inst_656 ( .B2(net_2150), .ZN(net_1929), .B1(net_1815), .A(net_1803) );
XNOR2_X2 inst_45 ( .ZN(net_2813), .A(net_2600), .B(net_1786) );
NOR2_X2 inst_1108 ( .A1(net_3808), .ZN(net_3291), .A2(net_2344) );
CLKBUF_X2 inst_5148 ( .A(net_5133), .Z(net_5134) );
CLKBUF_X2 inst_5140 ( .A(net_5125), .Z(net_5126) );
OAI21_X4 inst_458 ( .B2(net_4051), .ZN(net_3254), .A(net_3253), .B1(net_1162) );
HA_X1 inst_3093 ( .S(net_1163), .CO(net_1162), .A(net_1161), .B(net_1160) );
NAND2_X2 inst_1562 ( .A1(net_2963), .ZN(net_2459), .A2(net_474) );
AND2_X4 inst_4148 ( .ZN(net_4086), .A2(net_2374), .A1(net_711) );
CLKBUF_X2 inst_4618 ( .A(net_4282), .Z(net_4604) );
CLKBUF_X2 inst_4534 ( .A(net_4495), .Z(net_4520) );
NAND2_X2 inst_1922 ( .A1(net_3817), .ZN(net_3180), .A2(net_174) );
DFF_X1 inst_3361 ( .D(net_2359), .CK(net_4400), .Q(x450) );
OAI21_X2 inst_741 ( .ZN(net_3279), .B1(net_3278), .B2(net_2915), .A(net_2435) );
DFF_X2 inst_3170 ( .Q(net_3160), .D(net_1914), .CK(net_4998) );
DFF_X1 inst_3232 ( .QN(net_3064), .D(net_2964), .CK(net_4873) );
AOI21_X2 inst_3991 ( .B1(net_4190), .B2(net_3600), .ZN(net_3195), .A(net_1948) );
DFF_X1 inst_3343 ( .D(net_2780), .CK(net_4352), .Q(x128) );
NAND3_X2 inst_1350 ( .A3(net_3762), .ZN(net_3638), .A1(net_3637), .A2(net_3452) );
AND2_X4 inst_4140 ( .ZN(net_4072), .A1(net_1131), .A2(net_432) );
INV_X2 inst_3012 ( .ZN(net_3385), .A(net_42) );
INV_X2 inst_2635 ( .A(net_2601), .ZN(net_2520) );
NAND2_X2 inst_1543 ( .A1(net_3207), .ZN(net_2479), .A2(net_154) );
INV_X2 inst_2828 ( .A(net_3702), .ZN(net_441) );
CLKBUF_X2 inst_4219 ( .A(net_4202), .Z(net_4205) );
INV_X2 inst_2801 ( .ZN(net_1314), .A(net_742) );
NOR2_X2 inst_1118 ( .ZN(net_3422), .A2(net_3421), .A1(net_3415) );
INV_X4 inst_2303 ( .A(net_1028), .ZN(net_852) );
CLKBUF_X2 inst_4745 ( .A(net_4730), .Z(net_4731) );
DFF_X1 inst_3363 ( .D(net_2363), .CK(net_4227), .Q(x368) );
AOI221_X2 inst_3877 ( .B1(net_2020), .C1(net_2019), .ZN(net_1857), .A(net_1856), .B2(net_1699), .C2(x388) );
INV_X2 inst_2666 ( .A(net_2230), .ZN(net_2155) );
OAI21_X2 inst_473 ( .B1(net_3509), .ZN(net_2977), .B2(net_2963), .A(net_2459) );
NOR2_X2 inst_1131 ( .ZN(net_3578), .A1(net_3577), .A2(net_2373) );
NAND3_X2 inst_1357 ( .ZN(net_3716), .A2(net_3715), .A1(net_3682), .A3(net_87) );
OAI21_X2 inst_691 ( .A(net_1650), .ZN(net_1049), .B1(net_1006), .B2(net_608) );
INV_X4 inst_2211 ( .A(net_3241), .ZN(net_2732) );
AOI222_X1 inst_3771 ( .A1(net_4065), .C1(net_1882), .ZN(net_1873), .A2(net_1662), .B1(net_1385), .B2(net_941), .C2(net_635) );
INV_X1 inst_3083 ( .A(net_3938), .ZN(net_3639) );
NAND2_X2 inst_1695 ( .A1(net_2264), .ZN(net_2137), .A2(net_1993) );
OAI21_X2 inst_770 ( .ZN(net_4182), .B2(net_4181), .B1(net_3260), .A(net_3259) );
OAI21_X2 inst_565 ( .B2(net_2915), .B1(net_2849), .ZN(net_2847), .A(net_2439) );
CLKBUF_X2 inst_5302 ( .A(net_4594), .Z(net_5288) );
OAI21_X2 inst_622 ( .B1(net_2235), .ZN(net_2159), .A(net_2048), .B2(net_108) );
NAND2_X2 inst_1971 ( .A2(net_3877), .ZN(net_3341), .A1(net_3340) );
NAND2_X4 inst_1404 ( .A2(net_4021), .ZN(net_3234), .A1(net_3185) );
CLKBUF_X2 inst_4476 ( .A(net_4301), .Z(net_4462) );
INV_X2 inst_2989 ( .A(net_3100), .ZN(net_190) );
AOI22_X2 inst_3479 ( .A1(net_3241), .B2(net_3112), .B1(net_2781), .ZN(net_2660), .A2(net_2659) );
OAI221_X2 inst_409 ( .ZN(net_2594), .B1(net_1614), .C1(net_1613), .A(net_1530), .B2(net_289), .C2(net_250) );
INV_X4 inst_2288 ( .ZN(net_1125), .A(net_884) );
NAND3_X2 inst_1339 ( .ZN(net_3361), .A2(net_3360), .A1(net_3359), .A3(net_1574) );
CLKBUF_X2 inst_4284 ( .A(net_4216), .Z(net_4270) );
CLKBUF_X2 inst_4971 ( .A(net_4956), .Z(net_4957) );
CLKBUF_X2 inst_4704 ( .A(net_4613), .Z(net_4690) );
CLKBUF_X2 inst_4724 ( .A(net_4709), .Z(net_4710) );
CLKBUF_X2 inst_4841 ( .A(net_4826), .Z(net_4827) );
NAND2_X2 inst_1834 ( .A1(net_4105), .ZN(net_842), .A2(net_513) );
CLKBUF_X2 inst_4467 ( .A(net_4391), .Z(net_4453) );
AOI22_X2 inst_3575 ( .A1(net_4059), .B1(net_4056), .ZN(net_1475), .B2(net_498), .A2(net_497) );
CLKBUF_X2 inst_4493 ( .A(net_4474), .Z(net_4479) );
AOI22_X2 inst_3506 ( .B1(net_3676), .B2(net_3143), .A1(net_2012), .ZN(net_2011), .A2(net_168) );
AOI22_X2 inst_3654 ( .B2(net_4011), .A2(net_4009), .ZN(net_654), .A1(net_458), .B1(net_457) );
NOR2_X4 inst_977 ( .A1(net_3939), .ZN(net_3936), .A2(net_281) );
INV_X4 inst_2228 ( .A(net_1893), .ZN(net_1789) );
AOI22_X2 inst_3574 ( .A1(net_4060), .B1(net_4055), .ZN(net_1476), .B2(net_183), .A2(net_172) );
OAI21_X2 inst_768 ( .B2(net_4131), .B1(net_4086), .ZN(net_3963), .A(net_3960) );
OAI21_X2 inst_663 ( .A(net_3229), .ZN(net_2691), .B1(net_1559), .B2(net_69) );
INV_X8 inst_2121 ( .ZN(net_877), .A(net_432) );
CLKBUF_X2 inst_4802 ( .A(net_4787), .Z(net_4788) );
CLKBUF_X2 inst_4850 ( .A(net_4583), .Z(net_4836) );
OAI22_X2 inst_297 ( .A1(net_3487), .ZN(net_1738), .B1(net_1637), .B2(net_612), .A2(net_287) );
DFF_X1 inst_3227 ( .QN(net_3067), .D(net_2966), .CK(net_4887) );
NAND2_X4 inst_1395 ( .A2(net_3869), .A1(net_3868), .ZN(net_1865) );
INV_X4 inst_2477 ( .A(net_3063), .ZN(net_519) );
CLKBUF_X2 inst_4838 ( .A(net_4516), .Z(net_4824) );
INV_X4 inst_2188 ( .ZN(net_2612), .A(net_2524) );
AOI22_X2 inst_3494 ( .B2(net_3543), .ZN(net_2232), .A1(net_2231), .B1(net_2230), .A2(net_76) );
CLKBUF_X2 inst_4224 ( .A(net_4205), .Z(net_4210) );
NAND2_X2 inst_1875 ( .A1(net_3619), .ZN(net_947), .A2(net_299) );
DFF_X1 inst_3351 ( .D(net_2701), .QN(net_65), .CK(net_4239) );
NAND2_X2 inst_1867 ( .A1(net_3713), .ZN(net_849), .A2(net_543) );
DFF_X2 inst_3190 ( .QN(net_3156), .D(net_1704), .CK(net_4989) );
OR3_X4 inst_162 ( .ZN(net_2778), .A1(net_2325), .A2(net_2206), .A3(net_1173) );
DFF_X1 inst_3308 ( .QN(net_3015), .D(net_2870), .CK(net_5168) );
INV_X4 inst_2290 ( .A(net_938), .ZN(net_937) );
DFF_X1 inst_3397 ( .D(net_1563), .CK(net_5252), .Q(x606) );
CLKBUF_X2 inst_4421 ( .A(net_4406), .Z(net_4407) );
INV_X2 inst_2829 ( .ZN(net_601), .A(net_424) );
AOI221_X2 inst_3819 ( .A(net_2642), .B1(net_2641), .C1(net_2581), .ZN(net_2559), .C2(net_2551), .B2(net_252) );
CLKBUF_X2 inst_4233 ( .A(net_4218), .Z(net_4219) );
AOI22_X2 inst_3668 ( .B2(net_3455), .A1(net_571), .B1(net_570), .ZN(net_557), .A2(net_201) );
CLKBUF_X2 inst_5070 ( .A(net_4474), .Z(net_5056) );
CLKBUF_X2 inst_4912 ( .A(net_4897), .Z(net_4898) );
AOI21_X2 inst_3968 ( .ZN(net_1370), .A(net_1315), .B1(net_1314), .B2(net_517) );
DFF_X1 inst_3342 ( .Q(net_3143), .D(net_2769), .CK(net_4599) );
CLKBUF_X2 inst_4825 ( .A(net_4810), .Z(net_4811) );
CLKBUF_X2 inst_4633 ( .A(net_4618), .Z(net_4619) );
NOR2_X2 inst_1098 ( .A2(net_3162), .ZN(net_350), .A1(net_223) );
INV_X4 inst_2621 ( .ZN(net_3940), .A(net_3109) );
AND2_X4 inst_4149 ( .A1(net_4186), .ZN(net_4087), .A2(net_3521) );
AOI221_X2 inst_3895 ( .C2(net_1394), .B1(net_1393), .ZN(net_1347), .A(net_1173), .B2(net_207), .C1(net_51) );
INV_X4 inst_2443 ( .A(net_3088), .ZN(net_497) );
OAI21_X2 inst_723 ( .B2(net_3619), .ZN(net_647), .B1(net_641), .A(net_537) );
OAI22_X2 inst_303 ( .A1(net_1543), .B1(net_1542), .ZN(net_1539), .A2(net_292), .B2(net_131) );
OAI21_X2 inst_618 ( .B2(net_3408), .ZN(net_2265), .A(net_2264), .B1(net_2263) );
INV_X4 inst_2444 ( .A(net_3086), .ZN(net_461) );
AOI221_X2 inst_3893 ( .C2(net_4029), .C1(net_1394), .B1(net_1393), .ZN(net_1350), .A(net_1173), .B2(net_686) );
NAND2_X2 inst_1647 ( .A1(net_3774), .ZN(net_2328), .A2(net_1888) );
DFF_X1 inst_3263 ( .QN(net_3073), .D(net_2935), .CK(net_4867) );
INV_X2 inst_3057 ( .ZN(net_3952), .A(net_3948) );
NAND3_X2 inst_1275 ( .ZN(net_2764), .A1(net_2738), .A2(net_2737), .A3(net_1826) );
INV_X4 inst_2462 ( .A(net_3085), .ZN(net_781) );
OAI21_X2 inst_474 ( .B1(net_3509), .ZN(net_2976), .B2(net_2961), .A(net_2474) );
XOR2_X1 inst_26 ( .Z(net_1910), .A(net_1875), .B(net_1874) );
NAND2_X2 inst_2067 ( .ZN(net_3965), .A2(net_3960), .A1(net_930) );
OAI21_X2 inst_626 ( .B1(net_2190), .ZN(net_2151), .B2(net_2150), .A(net_2036) );
NAND3_X1 inst_1376 ( .A3(net_2691), .ZN(net_2648), .A1(net_2647), .A2(net_2506) );
INV_X2 inst_2882 ( .ZN(net_240), .A(net_61) );
INV_X2 inst_2777 ( .A(net_3907), .ZN(net_811) );
CLKBUF_X2 inst_4864 ( .A(net_4831), .Z(net_4850) );
INV_X4 inst_2446 ( .A(net_3065), .ZN(net_479) );
CLKBUF_X2 inst_5046 ( .A(net_5031), .Z(net_5032) );
AOI222_X1 inst_3765 ( .B1(net_4048), .C1(net_3447), .A1(net_1968), .ZN(net_1967), .C2(net_333), .A2(net_300), .B2(net_68) );
NAND2_X2 inst_1659 ( .ZN(net_2104), .A1(net_1982), .A2(net_196) );
CLKBUF_X2 inst_4218 ( .A(net_4203), .Z(net_4204) );
OAI211_X2 inst_798 ( .ZN(net_2191), .C1(net_2190), .C2(net_2189), .B(net_2052), .A(net_2007) );
CLKBUF_X2 inst_5210 ( .A(net_5195), .Z(net_5196) );
OAI221_X2 inst_398 ( .C2(net_3407), .B1(net_2328), .ZN(net_2287), .B2(net_2286), .C1(net_2239), .A(net_1938) );
CLKBUF_X2 inst_4340 ( .A(net_4325), .Z(net_4326) );
OAI221_X2 inst_436 ( .C2(net_3103), .A(net_629), .B1(net_628), .C1(net_627), .ZN(net_623), .B2(net_261) );
NAND2_X4 inst_1434 ( .ZN(net_3672), .A1(net_3671), .A2(net_3636) );
NAND2_X2 inst_1886 ( .A2(net_3418), .ZN(net_587), .A1(net_365) );
AOI22_X2 inst_3705 ( .B2(net_4123), .A2(net_555), .ZN(net_463), .A1(net_462), .B1(net_461) );
CLKBUF_X2 inst_5053 ( .A(net_5038), .Z(net_5039) );
INV_X4 inst_2231 ( .ZN(net_1872), .A(net_1666) );
CLKBUF_X2 inst_4349 ( .A(net_4239), .Z(net_4335) );
SDFF_X2 inst_144 ( .D(net_3886), .SE(net_2625), .SI(net_90), .Q(net_90), .CK(net_4951) );
NAND2_X4 inst_1457 ( .ZN(net_3838), .A2(net_3836), .A1(net_3637) );
NAND2_X4 inst_1438 ( .A1(net_3891), .ZN(net_3711), .A2(net_3700) );
NAND2_X2 inst_1818 ( .A2(net_3627), .A1(net_1463), .ZN(net_1338) );
AOI22_X2 inst_3662 ( .A1(net_571), .B1(net_570), .ZN(net_565), .B2(net_176), .A2(net_163) );
NAND2_X2 inst_1766 ( .A2(net_4032), .A1(net_1394), .ZN(net_1233) );
INV_X2 inst_2670 ( .ZN(net_2638), .A(net_2563) );
NOR3_X4 inst_880 ( .A3(net_3822), .ZN(net_3790), .A1(net_3785), .A2(net_357) );
CLKBUF_X2 inst_4857 ( .A(net_4842), .Z(net_4843) );
INV_X2 inst_2974 ( .ZN(net_1189), .A(net_119) );
NAND2_X2 inst_1895 ( .A1(net_4128), .ZN(net_367), .A2(net_144) );
INV_X2 inst_2681 ( .ZN(net_1853), .A(net_1852) );
INV_X2 inst_2730 ( .ZN(net_1398), .A(net_1350) );
CLKBUF_X2 inst_4548 ( .A(net_4281), .Z(net_4534) );
OAI21_X2 inst_737 ( .ZN(net_445), .B2(net_343), .B1(net_248), .A(x639) );
CLKBUF_X2 inst_4447 ( .A(net_4432), .Z(net_4433) );
NOR3_X4 inst_876 ( .ZN(net_2599), .A1(net_2549), .A2(net_2547), .A3(net_1706) );
INV_X2 inst_2979 ( .A(net_3021), .ZN(net_199) );
CLKBUF_X2 inst_4727 ( .A(net_4343), .Z(net_4713) );
OAI21_X2 inst_545 ( .B2(net_2917), .B1(net_2887), .ZN(net_2886), .A(net_2395) );
AOI21_X2 inst_3972 ( .ZN(net_1231), .A(net_1093), .B1(net_704), .B2(net_323) );
NAND2_X4 inst_1388 ( .ZN(net_2787), .A1(net_2740), .A2(net_2373) );
INV_X4 inst_2433 ( .ZN(net_396), .A(net_316) );
INV_X2 inst_2699 ( .A(net_3321), .ZN(net_1783) );
AOI22_X2 inst_3517 ( .B1(net_4045), .A1(net_1955), .ZN(net_1953), .A2(net_287), .B2(net_142) );
OAI21_X2 inst_562 ( .B2(net_2925), .ZN(net_2851), .B1(net_2849), .A(net_2425) );
INV_X4 inst_2480 ( .ZN(net_393), .A(net_41) );
NAND3_X2 inst_1372 ( .ZN(net_4174), .A3(net_4173), .A2(net_4171), .A1(net_4167) );
DFF_X1 inst_3396 ( .Q(net_3116), .D(net_1533), .CK(net_4309) );
NAND3_X2 inst_1360 ( .A3(net_3881), .ZN(net_3829), .A2(net_3828), .A1(net_3618) );
OAI21_X4 inst_466 ( .A(net_3858), .ZN(net_3848), .B2(net_3847), .B1(net_3846) );
INV_X2 inst_2761 ( .ZN(net_1153), .A(net_1033) );
AOI21_X2 inst_3981 ( .A(net_3916), .ZN(net_980), .B1(net_646), .B2(net_523) );
CLKBUF_X2 inst_4953 ( .A(net_4301), .Z(net_4939) );
NOR2_X2 inst_989 ( .A1(net_2591), .ZN(net_2589), .A2(net_2247) );
CLKBUF_X2 inst_5205 ( .A(net_5190), .Z(net_5191) );
INV_X4 inst_2283 ( .A(net_1250), .ZN(net_1246) );
INV_X2 inst_3038 ( .ZN(net_3632), .A(net_3630) );
NOR4_X2 inst_858 ( .A4(net_3796), .ZN(net_2274), .A1(net_2192), .A2(net_1659), .A3(net_1312) );
AOI22_X2 inst_3659 ( .ZN(net_572), .A1(net_571), .B1(net_570), .B2(net_171), .A2(net_146) );
AOI22_X2 inst_3604 ( .A1(net_4062), .B1(net_4057), .ZN(net_1413), .B2(net_467), .A2(net_454) );
NOR2_X2 inst_1109 ( .A2(net_3874), .ZN(net_3303), .A1(net_2209) );
AOI221_X2 inst_3864 ( .B1(net_4048), .C2(net_3147), .B2(net_2623), .ZN(net_1971), .C1(net_1923), .A(net_1831) );
CLKBUF_X2 inst_4415 ( .A(net_4333), .Z(net_4401) );
AND2_X2 inst_4209 ( .ZN(net_3972), .A1(net_3967), .A2(net_3478) );
INV_X2 inst_3037 ( .A(net_3973), .ZN(net_3621) );
XNOR2_X2 inst_54 ( .A(net_2543), .ZN(net_2382), .B(net_2342) );
INV_X4 inst_2468 ( .A(net_3077), .ZN(net_738) );
INV_X2 inst_2936 ( .A(net_3166), .ZN(net_344) );
NAND3_X2 inst_1314 ( .A2(net_4108), .ZN(net_894), .A3(net_829), .A1(net_783) );
NAND2_X4 inst_1420 ( .A1(net_3788), .ZN(net_3569), .A2(net_3521) );
NAND2_X4 inst_1482 ( .ZN(net_3976), .A2(net_3975), .A1(net_3679) );
CLKBUF_X2 inst_4260 ( .A(net_4245), .Z(net_4246) );
NOR2_X2 inst_1156 ( .ZN(net_4058), .A2(net_3339), .A1(net_1191) );
DFF_X1 inst_3378 ( .D(net_2252), .Q(net_74), .CK(net_5299) );
CLKBUF_X2 inst_5214 ( .A(net_5007), .Z(net_5200) );
AOI22_X2 inst_3484 ( .B2(net_3385), .A1(net_2675), .B1(net_2657), .ZN(net_2653), .A2(net_361) );
AND3_X4 inst_4062 ( .A3(net_3802), .ZN(net_1923), .A1(net_1827), .A2(net_1783) );
NOR2_X4 inst_942 ( .ZN(net_3289), .A2(net_3285), .A1(net_2174) );
CLKBUF_X2 inst_4626 ( .A(net_4611), .Z(net_4612) );
AND2_X4 inst_4108 ( .ZN(net_3590), .A2(net_3106), .A1(net_283) );
NAND3_X2 inst_1295 ( .A2(net_2054), .ZN(net_1889), .A1(net_1888), .A3(net_514) );
NAND2_X2 inst_1880 ( .ZN(net_881), .A1(net_398), .A2(net_368) );
CLKBUF_X2 inst_4794 ( .A(net_4779), .Z(net_4780) );
OR2_X2 inst_262 ( .A1(net_663), .A2(net_632), .ZN(net_631) );
AOI221_X2 inst_3829 ( .B1(net_4189), .C1(net_2534), .ZN(net_2370), .A(net_2291), .C2(net_256), .B2(net_168) );
AOI22_X2 inst_3630 ( .B1(net_4114), .A2(net_1094), .A1(net_963), .ZN(net_887), .B2(net_838) );
CLKBUF_X2 inst_4675 ( .A(net_4660), .Z(net_4661) );
OAI21_X2 inst_497 ( .B1(net_3394), .B2(net_2963), .ZN(net_2945), .A(net_2456) );
CLKBUF_X2 inst_4501 ( .A(net_4238), .Z(net_4487) );
INV_X4 inst_2195 ( .ZN(net_2389), .A(net_2327) );
CLKBUF_X2 inst_4252 ( .A(net_4237), .Z(net_4238) );
NOR2_X2 inst_1035 ( .A2(net_4080), .A1(net_1774), .ZN(net_1367) );
INV_X8 inst_2168 ( .ZN(net_3950), .A(net_3949) );
NAND3_X2 inst_1335 ( .A3(net_1401), .ZN(net_405), .A2(net_371), .A1(net_344) );
AOI221_X2 inst_3845 ( .B2(net_2203), .C1(net_2202), .ZN(net_2197), .B1(net_2196), .A(net_2077), .C2(net_396) );
AOI22_X2 inst_3637 ( .ZN(net_835), .A1(net_834), .B1(net_833), .A2(net_458), .B2(net_457) );
CLKBUF_X2 inst_5168 ( .A(net_4492), .Z(net_5154) );
DFF_X2 inst_3128 ( .QN(net_3148), .D(net_2683), .CK(net_4570) );
NAND2_X2 inst_1883 ( .ZN(net_1217), .A2(net_412), .A1(net_164) );
CLKBUF_X2 inst_4322 ( .A(net_4307), .Z(net_4308) );
NOR2_X2 inst_1078 ( .A2(net_4004), .ZN(net_644), .A1(net_618) );
INV_X4 inst_2517 ( .A(net_3543), .ZN(net_3196) );
AOI22_X2 inst_3621 ( .A1(net_1246), .A2(net_1137), .ZN(net_1119), .B1(net_1118), .B2(net_1117) );
NOR4_X2 inst_864 ( .A1(net_4064), .A2(net_1518), .ZN(net_1320), .A3(net_1319), .A4(net_793) );
OAI221_X2 inst_418 ( .C1(net_1332), .ZN(net_1251), .B1(net_1250), .B2(net_1138), .A(net_1128), .C2(net_646) );
XNOR2_X2 inst_86 ( .B(net_4073), .ZN(net_1075), .A(net_916) );
AND2_X4 inst_4183 ( .ZN(net_4145), .A1(net_3967), .A2(net_3620) );
NOR2_X4 inst_949 ( .A1(net_3701), .ZN(net_3617), .A2(net_3616) );
DFF_X1 inst_3283 ( .QN(net_3053), .D(net_2902), .CK(net_4780) );
AOI22_X2 inst_3557 ( .A1(net_4059), .B1(net_4056), .ZN(net_1493), .A2(net_236), .B2(net_151) );
NOR2_X2 inst_1039 ( .A1(net_1521), .A2(net_1170), .ZN(net_1169) );
NAND2_X2 inst_1992 ( .ZN(net_3458), .A2(net_2329), .A1(net_2321) );
AOI21_X2 inst_3961 ( .B1(net_4067), .ZN(net_1501), .A(net_1302), .B2(net_1298) );
OAI21_X2 inst_714 ( .B2(net_3789), .A(net_3733), .B1(net_810), .ZN(net_809) );
AOI22_X2 inst_3730 ( .ZN(net_4179), .B2(net_1523), .B1(net_623), .A1(net_575), .A2(net_261) );
INV_X2 inst_2895 ( .A(net_3098), .ZN(net_235) );
INV_X2 inst_3005 ( .ZN(net_3239), .A(net_764) );
AOI22_X2 inst_3598 ( .A1(net_4062), .B1(net_4057), .ZN(net_1419), .A2(net_203), .B2(net_173) );
AND4_X4 inst_4048 ( .ZN(net_4088), .A1(net_595), .A4(net_564), .A2(net_485), .A3(net_464) );
NAND2_X2 inst_1826 ( .A1(net_947), .ZN(net_786), .A2(net_671) );
MUX2_X2 inst_2109 ( .S(net_2907), .A(net_2573), .Z(net_2568), .B(net_197) );
AOI21_X2 inst_4003 ( .ZN(net_3752), .B2(net_3745), .A(net_3229), .B1(net_2623) );
NAND2_X2 inst_2020 ( .A2(net_3767), .A1(net_3766), .ZN(net_3670) );
CLKBUF_X2 inst_5033 ( .A(net_4249), .Z(net_5019) );
NOR2_X2 inst_1061 ( .ZN(net_939), .A1(net_938), .A2(net_399) );
CLKBUF_X2 inst_4361 ( .A(net_4346), .Z(net_4347) );
NAND4_X4 inst_1177 ( .ZN(net_3887), .A4(net_3886), .A3(net_3885), .A2(net_3884), .A1(net_3883) );
INV_X4 inst_2326 ( .ZN(net_957), .A(net_699) );
INV_X2 inst_2820 ( .ZN(net_717), .A(net_530) );
INV_X4 inst_2548 ( .ZN(net_3449), .A(net_3445) );
XNOR2_X2 inst_72 ( .B(net_3124), .A(net_1583), .ZN(net_1581) );
INV_X4 inst_2404 ( .A(net_3920), .ZN(net_352) );
CLKBUF_X2 inst_5127 ( .A(net_5112), .Z(net_5113) );
NAND2_X2 inst_1578 ( .A1(net_2965), .ZN(net_2442), .A2(net_552) );
NAND2_X2 inst_1634 ( .A2(net_3156), .ZN(net_2303), .A1(net_2215) );
NAND2_X2 inst_1666 ( .A2(net_4009), .A1(net_3817), .ZN(net_2092) );
AOI22_X2 inst_3542 ( .ZN(net_1584), .A1(net_1583), .B1(net_744), .B2(net_513), .A2(net_297) );
OAI21_X2 inst_735 ( .B2(net_1523), .A(net_629), .B1(net_628), .ZN(net_575) );
NAND2_X2 inst_1529 ( .A1(net_3208), .ZN(net_2493), .A2(net_139) );
XNOR2_X2 inst_115 ( .ZN(net_348), .A(net_327), .B(net_289) );
CLKBUF_X2 inst_4612 ( .A(net_4323), .Z(net_4598) );
NAND2_X2 inst_1653 ( .ZN(net_2135), .A1(net_2028), .A2(net_1976) );
CLKBUF_X2 inst_4691 ( .A(net_4676), .Z(net_4677) );
AOI22_X2 inst_3726 ( .A1(net_4107), .ZN(net_3723), .A2(net_3680), .B1(net_1018), .B2(net_521) );
CLKBUF_X2 inst_4638 ( .A(net_4623), .Z(net_4624) );
INV_X2 inst_3045 ( .ZN(net_3705), .A(net_264) );
NAND2_X2 inst_1582 ( .A2(net_3401), .A1(net_2915), .ZN(net_2438) );
INV_X2 inst_2984 ( .A(net_3007), .ZN(net_141) );
OR3_X4 inst_175 ( .ZN(net_628), .A2(net_389), .A1(net_309), .A3(net_263) );
DFF_X1 inst_3258 ( .QN(net_3078), .D(net_2943), .CK(net_4537) );
CLKBUF_X2 inst_5010 ( .A(net_4995), .Z(net_4996) );
NAND2_X2 inst_1737 ( .A2(net_2268), .ZN(net_1529), .A1(net_1528) );
NAND2_X2 inst_1805 ( .A1(net_4082), .ZN(net_959), .A2(net_913) );
NAND2_X2 inst_1840 ( .A2(net_4111), .ZN(net_1213), .A1(net_690) );
INV_X2 inst_2995 ( .ZN(net_127), .A(net_121) );
AOI22_X2 inst_3563 ( .A1(net_4059), .B1(net_4056), .ZN(net_1487), .A2(net_518), .B2(net_479) );
SDFF_X2 inst_133 ( .D(net_3483), .SI(net_3023), .Q(net_3023), .SE(net_2917), .CK(net_5161) );
NAND3_X4 inst_1263 ( .A3(net_3965), .ZN(net_2212), .A1(net_1269), .A2(net_1034) );
CLKBUF_X2 inst_4541 ( .A(net_4526), .Z(net_4527) );
INV_X2 inst_2752 ( .ZN(net_1124), .A(net_641) );
DFF_X1 inst_3330 ( .D(net_2820), .QN(net_318), .CK(net_4325) );
NOR2_X2 inst_1149 ( .ZN(net_3934), .A2(net_3932), .A1(net_3221) );
NAND2_X2 inst_1721 ( .A1(net_3320), .ZN(net_1739), .A2(net_360) );
NAND2_X4 inst_1445 ( .A1(net_3922), .A2(net_3826), .ZN(net_3788) );
NAND3_X2 inst_1281 ( .A2(net_4101), .A3(net_3559), .ZN(net_2545), .A1(net_2345) );
NAND2_X2 inst_1509 ( .A2(net_3738), .ZN(net_2634), .A1(net_2633) );
HA_X1 inst_3088 ( .S(net_1713), .CO(net_1712), .A(net_1711), .B(net_1710) );
AOI21_X2 inst_3990 ( .B1(net_3984), .A(net_3438), .ZN(net_705), .B2(net_442) );
XNOR2_X2 inst_126 ( .ZN(net_4190), .B(net_3224), .A(net_3223) );
AOI222_X1 inst_3782 ( .C2(net_3466), .B1(net_2020), .C1(net_1840), .ZN(net_1722), .A1(net_1698), .B2(net_382), .A2(net_255) );
CLKBUF_X2 inst_4719 ( .A(net_4704), .Z(net_4705) );
NAND2_X2 inst_1512 ( .ZN(net_2611), .A1(net_2610), .A2(net_1000) );
AOI221_X2 inst_3887 ( .C1(net_4064), .C2(net_4029), .ZN(net_1519), .B1(net_1518), .B2(net_1517), .A(net_1320) );
CLKBUF_X2 inst_5160 ( .A(net_4498), .Z(net_5146) );
NAND2_X2 inst_1631 ( .A1(net_3883), .A2(net_3858), .ZN(net_2321) );
CLKBUF_X2 inst_4353 ( .A(net_4279), .Z(net_4339) );
AOI21_X2 inst_3934 ( .ZN(net_2613), .B1(net_2612), .A(net_2388), .B2(net_1276) );
NOR2_X4 inst_948 ( .A2(net_3764), .ZN(net_3562), .A1(net_3478) );
NOR2_X2 inst_1140 ( .A1(net_3994), .ZN(net_3811), .A2(net_319) );
NOR2_X2 inst_1086 ( .A1(net_641), .ZN(net_431), .A2(net_334) );
INV_X2 inst_2643 ( .ZN(net_2338), .A(net_2317) );
NAND2_X2 inst_1688 ( .A1(net_3219), .ZN(net_1983), .A2(net_567) );
INV_X4 inst_2299 ( .A(net_3620), .ZN(net_1228) );
NAND2_X2 inst_1800 ( .A1(net_4081), .ZN(net_1082), .A2(net_245) );
CLKBUF_X2 inst_4773 ( .A(net_4758), .Z(net_4759) );
OAI221_X2 inst_448 ( .ZN(net_4151), .B1(net_3352), .C2(net_3348), .C1(net_2813), .A(net_2592), .B2(net_2189) );
CLKBUF_X2 inst_5292 ( .A(net_5277), .Z(net_5278) );
NOR3_X2 inst_914 ( .ZN(net_3473), .A2(net_3373), .A1(net_3238), .A3(net_2878) );
CLKBUF_X2 inst_4921 ( .A(net_4203), .Z(net_4907) );
CLKBUF_X2 inst_5170 ( .A(net_5155), .Z(net_5156) );
CLKBUF_X2 inst_5182 ( .A(net_5167), .Z(net_5168) );
CLKBUF_X2 inst_4380 ( .A(net_4365), .Z(net_4366) );
NAND2_X2 inst_2002 ( .A2(net_3858), .ZN(net_3513), .A1(net_3512) );
OAI221_X2 inst_384 ( .C1(net_3876), .B1(net_3175), .B2(net_2699), .C2(net_2698), .ZN(net_2628), .A(net_2536) );
NAND2_X2 inst_1642 ( .ZN(net_2174), .A1(net_2098), .A2(net_2024) );
NAND4_X2 inst_1252 ( .ZN(net_3847), .A2(net_2292), .A1(net_2280), .A4(net_2279), .A3(net_2182) );
OAI21_X2 inst_608 ( .B1(net_4136), .A(net_3316), .ZN(net_2306), .B2(net_1514) );
NAND3_X2 inst_1343 ( .ZN(net_3411), .A3(net_3410), .A1(net_3409), .A2(net_2613) );
AOI221_X2 inst_3800 ( .C1(net_2781), .ZN(net_2776), .B1(net_2775), .A(net_2667), .B2(net_2665), .C2(net_272) );
OAI211_X2 inst_834 ( .C1(net_1359), .ZN(net_1357), .A(net_1237), .B(net_671), .C2(net_292) );
INV_X2 inst_2920 ( .A(net_2984), .ZN(net_242) );
AND4_X2 inst_4054 ( .ZN(net_1766), .A1(net_1765), .A2(net_1764), .A4(net_1461), .A3(net_1380) );
NOR2_X4 inst_966 ( .ZN(net_3835), .A2(net_3633), .A1(net_3548) );
OR2_X4 inst_199 ( .A1(net_3204), .ZN(net_2967), .A2(net_2352) );
NAND4_X2 inst_1246 ( .ZN(net_3529), .A4(net_3282), .A1(net_2101), .A2(net_2091), .A3(net_1988) );
INV_X2 inst_2961 ( .A(net_3150), .ZN(net_2051) );
DFF_X2 inst_3185 ( .D(net_1763), .Q(net_77), .CK(net_4461) );
CLKBUF_X2 inst_4679 ( .A(net_4664), .Z(net_4665) );
INV_X4 inst_2209 ( .A(net_2377), .ZN(net_2246) );
INV_X4 inst_2506 ( .A(net_2987), .ZN(net_201) );
INV_X2 inst_2722 ( .ZN(net_1506), .A(net_1505) );
NAND4_X2 inst_1238 ( .A4(net_3153), .A3(net_3152), .ZN(net_544), .A1(net_332), .A2(net_316) );
INV_X8 inst_2171 ( .ZN(net_4164), .A(net_4163) );
CLKBUF_X2 inst_5245 ( .A(net_5230), .Z(net_5231) );
CLKBUF_X2 inst_4875 ( .A(net_4532), .Z(net_4861) );
CLKBUF_X2 inst_4557 ( .A(net_4385), .Z(net_4543) );
AOI22_X2 inst_3607 ( .A1(net_4062), .B1(net_4057), .ZN(net_1410), .B2(net_233), .A2(net_213) );
NAND2_X2 inst_2029 ( .ZN(net_3740), .A1(net_3738), .A2(net_67) );
DFF_X1 inst_3402 ( .Q(net_3120), .D(net_1544), .CK(net_4299) );
NOR2_X2 inst_1011 ( .ZN(net_2264), .A1(net_1863), .A2(net_1861) );
AND2_X4 inst_4114 ( .ZN(net_3469), .A1(net_2126), .A2(net_2125) );
OAI21_X2 inst_540 ( .ZN(net_4020), .B2(net_2967), .B1(net_2893), .A(net_2411) );
CLKBUF_X2 inst_4936 ( .A(net_4555), .Z(net_4922) );
OAI221_X2 inst_404 ( .B1(net_3781), .B2(net_3506), .ZN(net_1958), .C1(net_1884), .A(net_1751), .C2(net_355) );
INV_X4 inst_2356 ( .A(net_4005), .ZN(net_536) );
NOR2_X2 inst_998 ( .A2(net_3233), .ZN(net_3210), .A1(net_2025) );
DFF_X2 inst_3209 ( .QN(net_4034), .D(net_823), .CK(net_4823) );
DFF_X2 inst_3160 ( .D(net_2158), .QN(net_59), .CK(net_4207) );
INV_X2 inst_2861 ( .ZN(net_321), .A(net_125) );
XNOR2_X2 inst_66 ( .B(net_3492), .ZN(net_1696), .A(net_1242) );
AOI22_X2 inst_3615 ( .ZN(net_1331), .A2(net_1330), .A1(net_1211), .B1(net_1083), .B2(net_1035) );
CLKBUF_X2 inst_4814 ( .A(net_4799), .Z(net_4800) );
DFF_X2 inst_3216 ( .D(net_802), .QN(net_260), .CK(net_4619) );
OAI33_X1 inst_273 ( .ZN(net_1654), .A1(net_1653), .A2(net_1283), .B3(net_1173), .A3(net_791), .B2(net_246), .B1(x557) );
CLKBUF_X2 inst_5090 ( .A(net_4337), .Z(net_5076) );
OR2_X4 inst_192 ( .A1(net_3445), .ZN(net_2524), .A2(net_2388) );
NAND2_X2 inst_1965 ( .A2(net_4004), .ZN(net_3324), .A1(net_3106) );
AOI221_X2 inst_3915 ( .ZN(net_3356), .B2(net_3138), .A(net_2642), .B1(net_2591), .C2(net_2589), .C1(net_2583) );
OAI221_X2 inst_366 ( .ZN(net_2729), .A(net_2617), .B1(net_2546), .C1(net_2545), .C2(net_329), .B2(net_250) );
INV_X4 inst_2418 ( .A(net_3108), .ZN(net_319) );
INV_X2 inst_2715 ( .ZN(net_1560), .A(net_1559) );
CLKBUF_X2 inst_4242 ( .A(net_4204), .Z(net_4228) );
AOI22_X2 inst_3540 ( .ZN(net_1635), .A1(net_1634), .B2(net_1228), .A2(net_1089), .B1(net_1071) );
AND2_X4 inst_4126 ( .ZN(net_4052), .A1(net_2690), .A2(net_1444) );
AND2_X4 inst_4178 ( .ZN(net_4135), .A1(net_2185), .A2(net_1768) );
AOI22_X2 inst_3547 ( .B1(net_4054), .A2(net_1791), .A1(net_1578), .ZN(net_1574), .B2(net_243) );
NAND2_X2 inst_1574 ( .A1(net_2965), .ZN(net_2446), .A2(net_146) );
INV_X4 inst_2413 ( .A(net_322), .ZN(net_309) );
DFF_X1 inst_3285 ( .QN(net_3051), .D(net_2899), .CK(net_4860) );
CLKBUF_X2 inst_4746 ( .A(net_4731), .Z(net_4732) );
OR2_X4 inst_228 ( .ZN(net_1613), .A2(net_903), .A1(net_658) );
OAI21_X2 inst_486 ( .B1(net_3278), .ZN(net_2956), .B2(net_2909), .A(net_2463) );
NAND4_X2 inst_1240 ( .ZN(net_3232), .A3(net_3231), .A2(net_2100), .A1(net_2081), .A4(net_1983) );
NOR2_X2 inst_1025 ( .A1(net_3781), .ZN(net_1648), .A2(net_1609) );
OAI21_X2 inst_707 ( .ZN(net_857), .B1(net_709), .B2(net_684), .A(net_414) );
CLKBUF_X2 inst_4655 ( .A(net_4430), .Z(net_4641) );
AOI22_X2 inst_3670 ( .A2(net_571), .B2(net_570), .ZN(net_554), .A1(net_244), .B1(net_139) );
CLKBUF_X2 inst_4460 ( .A(net_4258), .Z(net_4446) );
OR2_X4 inst_244 ( .ZN(net_3945), .A2(net_3109), .A1(net_3107) );
CLKBUF_X2 inst_5262 ( .A(net_5239), .Z(net_5248) );
INV_X2 inst_2804 ( .ZN(net_1094), .A(net_725) );
CLKBUF_X2 inst_5131 ( .A(net_5116), .Z(net_5117) );
NAND2_X2 inst_1521 ( .A1(net_2959), .ZN(net_2501), .A2(net_731) );
INV_X4 inst_2576 ( .ZN(net_3594), .A(net_3591) );
INV_X1 inst_3079 ( .ZN(net_3358), .A(net_2815) );
INV_X2 inst_2631 ( .ZN(net_2694), .A(net_2693) );
CLKBUF_X2 inst_4845 ( .A(net_4830), .Z(net_4831) );
NAND3_X2 inst_1306 ( .ZN(net_1150), .A2(net_1143), .A1(net_1142), .A3(net_970) );
OAI21_X1 inst_772 ( .ZN(net_4012), .B2(net_2965), .B1(net_2893), .A(net_2447) );
INV_X4 inst_2563 ( .A(net_3858), .ZN(net_3515) );
AOI221_X2 inst_3810 ( .B2(net_3133), .ZN(net_2643), .A(net_2642), .B1(net_2641), .C1(net_2640), .C2(net_2222) );
NAND2_X4 inst_1407 ( .ZN(net_3287), .A1(net_3252), .A2(net_2838) );
AOI22_X2 inst_3682 ( .B2(net_4123), .A2(net_555), .ZN(net_501), .B1(net_196), .A1(net_191) );
CLKBUF_X2 inst_4940 ( .A(net_4413), .Z(net_4926) );
CLKBUF_X2 inst_4523 ( .A(net_4482), .Z(net_4509) );
CLKBUF_X2 inst_4583 ( .A(net_4557), .Z(net_4569) );
INV_X2 inst_2636 ( .ZN(net_2516), .A(net_2515) );
CLKBUF_X2 inst_4870 ( .A(net_4855), .Z(net_4856) );
OAI221_X2 inst_445 ( .B1(net_4160), .ZN(net_3697), .B2(net_3407), .C1(net_2328), .A(net_1940), .C2(net_1444) );
CLKBUF_X2 inst_5192 ( .A(net_5177), .Z(net_5178) );
XNOR2_X2 inst_93 ( .ZN(net_813), .A(net_664), .B(net_653) );
AOI22_X2 inst_3606 ( .A1(net_4063), .B1(net_4058), .ZN(net_1411), .A2(net_180), .B2(net_154) );
CLKBUF_X2 inst_4832 ( .A(net_4817), .Z(net_4818) );
OAI21_X2 inst_606 ( .B2(net_3428), .B1(net_3312), .ZN(net_2331), .A(net_2138) );
INV_X2 inst_2942 ( .A(net_3019), .ZN(net_237) );
CLKBUF_X2 inst_5089 ( .A(net_5074), .Z(net_5075) );
AOI222_X1 inst_3761 ( .C1(net_3117), .A1(net_2055), .B2(net_2054), .C2(net_2053), .ZN(net_2001), .B1(net_1743), .A2(net_142) );
CLKBUF_X2 inst_5099 ( .A(net_5084), .Z(net_5085) );
CLKBUF_X2 inst_4595 ( .A(net_4580), .Z(net_4581) );
OAI211_X2 inst_853 ( .A(net_4108), .C1(net_3913), .B(net_3669), .ZN(net_3322), .C2(net_3319) );
SDFF_X2 inst_139 ( .D(net_3343), .SE(net_2514), .SI(net_100), .Q(net_100), .CK(net_4754) );
OAI21_X2 inst_657 ( .B2(net_4088), .ZN(net_1941), .B1(net_1815), .A(net_1803) );
NAND2_X2 inst_1675 ( .ZN(net_2083), .A1(net_2082), .A2(net_163) );
OAI21_X2 inst_584 ( .B1(net_4037), .B2(net_2815), .ZN(net_2744), .A(net_1577) );
CLKBUF_X2 inst_4550 ( .A(net_4535), .Z(net_4536) );
NAND3_X2 inst_1316 ( .A1(net_4096), .A2(net_3713), .ZN(net_995), .A3(net_947) );
NAND2_X1 inst_2098 ( .ZN(net_3605), .A1(net_3541), .A2(net_3270) );
OAI21_X2 inst_470 ( .B1(net_3509), .ZN(net_2980), .B2(net_2972), .A(net_2431) );
AOI22_X2 inst_3551 ( .A1(net_4060), .B1(net_4055), .A2(net_4011), .B2(net_4009), .ZN(net_1499) );
NAND2_X2 inst_1921 ( .A1(net_3156), .ZN(net_1521), .A2(x1023) );
CLKBUF_X2 inst_5149 ( .A(net_5134), .Z(net_5135) );
CLKBUF_X2 inst_4237 ( .A(net_4211), .Z(net_4223) );
CLKBUF_X2 inst_4490 ( .A(net_4475), .Z(net_4476) );
SDFF_X2 inst_148 ( .D(net_3827), .SE(net_2514), .SI(net_97), .Q(net_97), .CK(net_4943) );
NAND2_X2 inst_1752 ( .ZN(net_1312), .A2(net_1311), .A1(net_1114) );
OAI21_X2 inst_554 ( .B2(net_2919), .ZN(net_2872), .B1(net_2871), .A(net_2399) );
CLKBUF_X2 inst_4293 ( .A(net_4278), .Z(net_4279) );
NAND4_X2 inst_1187 ( .A3(net_4049), .A4(net_2144), .ZN(net_1868), .A1(net_1867), .A2(net_1866) );
OR2_X4 inst_191 ( .A2(net_4040), .A1(net_2714), .ZN(net_2528) );
CLKBUF_X2 inst_4333 ( .A(net_4318), .Z(net_4319) );
NOR2_X2 inst_1063 ( .A2(net_4104), .A1(net_4083), .ZN(net_1009) );
INV_X2 inst_2700 ( .ZN(net_1679), .A(net_1678) );
NAND2_X2 inst_1917 ( .A2(net_389), .A1(net_322), .ZN(net_312) );
INV_X2 inst_2638 ( .ZN(net_2387), .A(net_2386) );
DFF_X1 inst_3252 ( .QN(net_3081), .D(net_2953), .CK(net_4732) );
CLKBUF_X2 inst_4565 ( .A(net_4319), .Z(net_4551) );
CLKBUF_X2 inst_4538 ( .A(net_4512), .Z(net_4524) );
CLKBUF_X2 inst_5212 ( .A(net_5197), .Z(net_5198) );
CLKBUF_X2 inst_4955 ( .A(net_4940), .Z(net_4941) );
CLKBUF_X2 inst_4755 ( .A(net_4691), .Z(net_4741) );
DFF_X1 inst_3235 ( .D(net_3279), .QN(net_3043), .CK(net_5047) );
CLKBUF_X2 inst_5276 ( .A(net_5261), .Z(net_5262) );
NOR2_X1 inst_1167 ( .A2(net_514), .ZN(net_425), .A1(net_284) );
AOI221_X2 inst_3879 ( .A(net_4047), .C2(net_1908), .ZN(net_1850), .C1(net_1849), .B2(net_749), .B1(net_98) );
CLKBUF_X2 inst_5269 ( .A(net_5254), .Z(net_5255) );
NAND2_X1 inst_2087 ( .A1(net_2972), .ZN(net_2430), .A2(net_732) );
INV_X4 inst_2184 ( .ZN(net_2775), .A(net_2561) );
NAND3_X2 inst_1303 ( .A3(net_3497), .A1(net_1691), .ZN(net_1317), .A2(net_1316) );
NOR3_X2 inst_892 ( .ZN(net_2345), .A1(net_2325), .A2(net_2282), .A3(net_1173) );
NAND2_X2 inst_1623 ( .A1(net_2917), .ZN(net_2393), .A2(net_205) );
INV_X2 inst_2665 ( .ZN(net_2350), .A(net_2134) );
AND3_X2 inst_4088 ( .A3(net_3627), .ZN(net_944), .A1(net_943), .A2(net_591) );
NOR2_X2 inst_1132 ( .ZN(net_3643), .A2(net_3168), .A1(net_3167) );
CLKBUF_X2 inst_4922 ( .A(net_4907), .Z(net_4908) );
CLKBUF_X2 inst_4464 ( .A(net_4449), .Z(net_4450) );
AND2_X4 inst_4100 ( .A2(net_4034), .ZN(net_1097), .A1(net_1096) );
NOR2_X4 inst_968 ( .ZN(net_3875), .A2(net_3529), .A1(net_3528) );
OAI211_X2 inst_819 ( .A(net_3487), .ZN(net_1946), .B(net_934), .C2(net_433), .C1(net_280) );
CLKBUF_X2 inst_4700 ( .A(net_4685), .Z(net_4686) );
DFF_X1 inst_3320 ( .QN(net_3001), .D(net_2850), .CK(net_5070) );
CLKBUF_X2 inst_4441 ( .A(net_4426), .Z(net_4427) );
NAND2_X4 inst_1468 ( .ZN(net_3898), .A1(net_3897), .A2(net_3289) );
NAND2_X2 inst_1803 ( .A1(net_4082), .ZN(net_1256), .A2(net_778) );
NAND2_X2 inst_1516 ( .A2(net_4040), .ZN(net_2670), .A1(net_2668) );
AOI222_X1 inst_3776 ( .C1(net_3115), .B2(net_2020), .ZN(net_1842), .A1(net_1841), .C2(net_1840), .B1(net_772), .A2(net_206) );
DFF_X2 inst_3153 ( .D(net_2262), .QN(net_45), .CK(net_4413) );
OAI221_X2 inst_386 ( .B1(net_3449), .B2(net_2666), .ZN(net_2616), .C1(net_2615), .C2(net_1727), .A(net_1386) );
INV_X2 inst_2814 ( .ZN(net_646), .A(net_638) );
INV_X4 inst_2617 ( .ZN(net_3889), .A(net_3888) );
NOR2_X4 inst_936 ( .A2(net_3755), .ZN(net_407), .A1(net_337) );
AOI221_X2 inst_3809 ( .ZN(net_2644), .A(net_2642), .B1(net_2641), .C1(net_2640), .C2(net_2220), .B2(net_265) );
AOI21_X2 inst_4004 ( .ZN(net_3844), .B2(net_3842), .A(net_1721), .B1(net_1228) );
AOI21_X2 inst_3942 ( .ZN(net_2239), .B1(net_2238), .A(net_2166), .B2(net_238) );
INV_X16 inst_3068 ( .ZN(net_3817), .A(net_3799) );
CLKBUF_X2 inst_5225 ( .A(net_4471), .Z(net_5211) );
INV_X4 inst_2277 ( .A(net_1081), .ZN(net_973) );
INV_X2 inst_2778 ( .ZN(net_808), .A(net_762) );
CLKBUF_X2 inst_5223 ( .A(net_5208), .Z(net_5209) );
AOI221_X2 inst_3798 ( .ZN(net_2832), .A(net_2783), .C1(net_2781), .B1(net_2724), .C2(net_83), .B2(net_36) );
CLKBUF_X2 inst_5232 ( .A(net_5217), .Z(net_5218) );
AND2_X4 inst_4109 ( .A1(net_3164), .A2(net_3162), .ZN(net_345) );
AND2_X2 inst_4192 ( .ZN(net_2608), .A2(net_2607), .A1(net_2544) );
INV_X2 inst_2962 ( .A(net_2998), .ZN(net_170) );
INV_X2 inst_3004 ( .A(net_3615), .ZN(net_3221) );
AOI222_X1 inst_3780 ( .A2(net_3705), .B1(net_1795), .A1(net_1794), .C1(net_1793), .ZN(net_1792), .C2(net_1791), .B2(net_717) );
INV_X2 inst_2647 ( .A(net_3880), .ZN(net_2335) );
CLKBUF_X2 inst_4672 ( .A(net_4657), .Z(net_4658) );
OAI211_X2 inst_811 ( .ZN(net_1629), .B(net_1628), .C1(net_1627), .A(net_1555), .C2(net_530) );
OR2_X4 inst_208 ( .A2(net_3447), .ZN(net_2714), .A1(net_2281) );
AND2_X2 inst_4202 ( .A2(net_3662), .ZN(net_690), .A1(net_609) );
INV_X4 inst_2456 ( .A(net_3089), .ZN(net_498) );
AOI222_X1 inst_3774 ( .C2(net_2051), .B2(net_2020), .ZN(net_1860), .A1(net_1841), .C1(net_1840), .B1(net_873), .A2(net_83) );
INV_X2 inst_2710 ( .A(net_1799), .ZN(net_1632) );
NOR2_X2 inst_1058 ( .A2(net_4024), .A1(net_1908), .ZN(net_1002) );
INV_X2 inst_2887 ( .A(net_505), .ZN(net_168) );
CLKBUF_X2 inst_5282 ( .A(net_4869), .Z(net_5268) );
AOI221_X2 inst_3909 ( .B1(net_4106), .C1(net_3563), .A(net_3546), .C2(net_3478), .ZN(net_870), .B2(net_281) );
NAND2_X2 inst_1869 ( .ZN(net_610), .A1(net_542), .A2(net_261) );
NOR3_X2 inst_897 ( .A2(net_3783), .ZN(net_1376), .A1(net_1271), .A3(net_657) );
DFF_X1 inst_3360 ( .D(net_2362), .CK(net_4230), .Q(x437) );
AOI21_X2 inst_3945 ( .B1(net_3774), .ZN(net_2225), .A(net_2148), .B2(net_1507) );
CLKBUF_X2 inst_4984 ( .A(net_4969), .Z(net_4970) );
NAND4_X2 inst_1201 ( .ZN(net_1672), .A3(net_1475), .A4(net_1474), .A1(net_1409), .A2(net_1408) );
NAND2_X4 inst_1473 ( .ZN(net_3926), .A1(net_3168), .A2(net_268) );
NAND2_X2 inst_1788 ( .ZN(net_1066), .A2(net_1016), .A1(net_910) );
NAND3_X4 inst_1272 ( .ZN(net_3997), .A2(net_3996), .A3(net_3765), .A1(net_3243) );
AND2_X4 inst_4182 ( .ZN(net_4144), .A2(net_4130), .A1(net_3128) );
OAI21_X2 inst_636 ( .A(net_3750), .B2(net_2076), .ZN(net_2074), .B1(net_1675) );
OAI21_X2 inst_632 ( .ZN(net_2079), .A(net_1961), .B2(net_1960), .B1(net_1189) );
XOR2_X2 inst_0 ( .Z(net_2538), .A(net_2330), .B(net_1781) );
INV_X2 inst_2852 ( .A(net_374), .ZN(net_335) );
NAND2_X2 inst_1927 ( .ZN(net_3190), .A1(net_3186), .A2(net_234) );
OR3_X2 inst_184 ( .ZN(net_606), .A3(net_605), .A1(net_601), .A2(net_523) );
NAND2_X2 inst_1847 ( .ZN(net_680), .A2(net_640), .A1(net_414) );
AOI21_X2 inst_3973 ( .B2(net_1330), .ZN(net_1219), .A(net_1155), .B1(net_1078) );
NAND2_X2 inst_1907 ( .A2(net_1326), .A1(net_686), .ZN(net_311) );
OAI221_X2 inst_433 ( .B2(net_3418), .A(net_629), .B1(net_628), .C1(net_627), .ZN(net_626), .C2(net_40) );
NAND2_X2 inst_1983 ( .A1(net_4095), .ZN(net_3406), .A2(net_297) );
CLKBUF_X2 inst_4939 ( .A(net_4924), .Z(net_4925) );
AOI221_X2 inst_3836 ( .B1(net_3774), .ZN(net_2228), .C1(net_2227), .A(net_2108), .C2(net_1637), .B2(net_1439) );
INV_X4 inst_2192 ( .A(net_2714), .ZN(net_2668) );
NAND2_X2 inst_1948 ( .ZN(net_3266), .A2(net_3265), .A1(net_1978) );
MUX2_X2 inst_2114 ( .Z(net_3380), .S(net_3379), .A(net_1401), .B(net_1400) );
INV_X2 inst_2784 ( .ZN(net_802), .A(net_756) );
CLKBUF_X2 inst_4216 ( .A(net_4201), .Z(net_4202) );
XNOR2_X2 inst_106 ( .B(net_3122), .ZN(net_542), .A(net_309) );
OAI221_X2 inst_422 ( .ZN(net_1185), .A(net_1067), .B2(net_719), .B1(net_716), .C2(net_693), .C1(net_667) );
INV_X4 inst_2583 ( .A(net_3918), .ZN(net_3628) );
INV_X4 inst_2243 ( .ZN(net_1808), .A(net_1520) );
NAND2_X4 inst_1475 ( .A1(net_3977), .ZN(net_3938), .A2(net_3937) );
NAND2_X4 inst_1426 ( .ZN(net_3597), .A2(net_3596), .A1(net_3593) );
CLKBUF_X2 inst_4812 ( .A(net_4487), .Z(net_4798) );
HA_X1 inst_3090 ( .A(net_3492), .S(net_1707), .CO(net_1706), .B(net_1705) );
NAND2_X2 inst_1637 ( .A1(net_4042), .ZN(net_2698), .A2(net_2169) );
AOI21_X2 inst_3997 ( .ZN(net_3560), .B2(net_3559), .B1(net_957), .A(net_848) );
NAND3_X2 inst_1352 ( .A1(net_3719), .ZN(net_3683), .A2(net_3672), .A3(net_3399) );
CLKBUF_X2 inst_5241 ( .A(net_5226), .Z(net_5227) );
CLKBUF_X2 inst_4377 ( .A(net_4213), .Z(net_4363) );
INV_X4 inst_2261 ( .ZN(net_1393), .A(net_1359) );
CLKBUF_X2 inst_4879 ( .A(net_4296), .Z(net_4865) );
CLKBUF_X2 inst_4383 ( .A(net_4368), .Z(net_4369) );
CLKBUF_X2 inst_4301 ( .A(net_4286), .Z(net_4287) );
CLKBUF_X2 inst_4695 ( .A(net_4680), .Z(net_4681) );
AND2_X4 inst_4142 ( .ZN(net_4078), .A2(net_847), .A1(net_663) );
DFF_X1 inst_3390 ( .D(net_1733), .QN(net_81), .CK(net_4428) );
INV_X2 inst_2930 ( .ZN(net_1280), .A(net_113) );
CLKBUF_X2 inst_5106 ( .A(net_5091), .Z(net_5092) );
NAND2_X4 inst_1410 ( .A1(net_3858), .ZN(net_3331), .A2(net_931) );
CLKBUF_X2 inst_4790 ( .A(net_4775), .Z(net_4776) );
CLKBUF_X2 inst_4307 ( .A(net_4292), .Z(net_4293) );
INV_X2 inst_2859 ( .ZN(net_302), .A(net_301) );
CLKBUF_X2 inst_4991 ( .A(net_4976), .Z(net_4977) );
OAI221_X2 inst_397 ( .C2(net_3407), .B1(net_2328), .ZN(net_2294), .C1(net_2194), .A(net_2022), .B2(net_66) );
AOI222_X1 inst_3756 ( .A1(net_3676), .B1(net_2055), .C1(net_2054), .ZN(net_2036), .C2(net_419), .A2(net_256), .B2(net_168) );
OAI21_X2 inst_504 ( .B1(net_3278), .ZN(net_2938), .B2(net_2919), .A(net_2397) );
CLKBUF_X2 inst_4424 ( .A(net_4409), .Z(net_4410) );
DFF_X2 inst_3192 ( .QN(net_3109), .D(net_1630), .CK(net_4834) );
CLKBUF_X2 inst_5006 ( .A(net_4822), .Z(net_4992) );
NAND2_X2 inst_1733 ( .A1(net_1556), .ZN(net_1552), .A2(x672) );
NAND3_X2 inst_1297 ( .A2(net_1821), .ZN(net_1585), .A3(net_1386), .A1(net_1170) );
AOI221_X2 inst_3900 ( .C2(net_3941), .ZN(net_1206), .A(net_1203), .B1(net_1202), .C1(net_1201), .B2(net_599) );
DFF_X2 inst_3194 ( .QN(net_3106), .D(net_1624), .CK(net_5132) );
NOR3_X2 inst_918 ( .ZN(net_4101), .A2(net_3954), .A1(net_637), .A3(net_516) );
INV_X4 inst_2199 ( .A(net_3882), .ZN(net_2314) );
CLKBUF_X2 inst_4751 ( .A(net_4501), .Z(net_4737) );
AOI221_X2 inst_3884 ( .ZN(net_1720), .C1(net_1718), .C2(net_1656), .A(net_1362), .B1(net_1184), .B2(net_204) );
CLKBUF_X2 inst_4246 ( .A(net_4231), .Z(net_4232) );
NOR2_X1 inst_1173 ( .ZN(net_4193), .A2(net_3543), .A1(net_432) );
AOI221_X2 inst_3904 ( .A(net_4090), .B2(net_3680), .B1(net_1028), .ZN(net_1020), .C1(net_746), .C2(net_521) );
INV_X2 inst_2908 ( .A(net_3095), .ZN(net_191) );
CLKBUF_X2 inst_5019 ( .A(net_5004), .Z(net_5005) );
NAND2_X4 inst_1393 ( .A2(net_4013), .A1(net_2134), .ZN(net_2093) );
NAND2_X2 inst_2074 ( .ZN(net_4068), .A1(net_3836), .A2(net_3547) );
AOI211_X1 inst_4035 ( .A(net_3958), .B(net_3621), .ZN(net_3318), .C2(net_963), .C1(net_905) );
NAND2_X2 inst_1862 ( .ZN(net_592), .A1(net_591), .A2(net_590) );
AOI22_X2 inst_3519 ( .B1(net_4045), .B2(net_3151), .A1(net_1955), .ZN(net_1951), .A2(net_295) );
CLKBUF_X2 inst_4823 ( .A(net_4806), .Z(net_4809) );
NAND4_X2 inst_1236 ( .A3(net_4125), .A2(net_3900), .ZN(net_745), .A4(net_431), .A1(net_386) );
OR2_X4 inst_221 ( .A1(net_4081), .ZN(net_1033), .A2(net_245) );
AND3_X4 inst_4075 ( .A3(net_4162), .A2(net_4118), .ZN(net_4085), .A1(net_3900) );
CLKBUF_X2 inst_5112 ( .A(net_5097), .Z(net_5098) );
DFF_X1 inst_3313 ( .QN(net_2999), .D(net_2848), .CK(net_5202) );
AOI22_X2 inst_3562 ( .A1(net_4060), .B1(net_4055), .ZN(net_1488), .A2(net_221), .B2(net_155) );
CLKBUF_X2 inst_4893 ( .A(net_4878), .Z(net_4879) );
CLKBUF_X2 inst_5153 ( .A(net_5138), .Z(net_5139) );
INV_X4 inst_2334 ( .ZN(net_765), .A(net_633) );
INV_X4 inst_2429 ( .A(net_2991), .ZN(net_159) );
INV_X4 inst_2210 ( .ZN(net_2282), .A(net_2206) );
OAI21_X2 inst_754 ( .B1(net_4103), .A(net_3764), .ZN(net_3564), .B2(net_439) );
CLKBUF_X2 inst_4791 ( .A(net_4776), .Z(net_4777) );
INV_X2 inst_2937 ( .A(net_3048), .ZN(net_241) );
CLKBUF_X2 inst_5028 ( .A(net_5013), .Z(net_5014) );
INV_X4 inst_2590 ( .ZN(net_3678), .A(net_3270) );
INV_X2 inst_2913 ( .A(net_3119), .ZN(net_134) );
OAI21_X2 inst_687 ( .B1(net_3228), .A(net_1307), .ZN(net_1305), .B2(net_327) );
NAND2_X2 inst_1774 ( .A1(net_2213), .A2(net_1884), .ZN(net_1394) );
INV_X4 inst_2319 ( .ZN(net_866), .A(net_703) );
CLKBUF_X2 inst_5025 ( .A(net_4513), .Z(net_5011) );
DFF_X1 inst_3295 ( .QN(net_3009), .D(net_2888), .CK(net_5223) );
NOR2_X2 inst_985 ( .ZN(net_2600), .A1(net_2599), .A2(net_2598) );
CLKBUF_X2 inst_5057 ( .A(net_5042), .Z(net_5043) );
INV_X4 inst_2225 ( .ZN(net_2129), .A(net_1835) );
INV_X4 inst_2513 ( .ZN(net_1611), .A(net_85) );
AND3_X4 inst_4061 ( .A3(net_3320), .ZN(net_1968), .A1(net_1828), .A2(net_1645) );
INV_X4 inst_2254 ( .ZN(net_2020), .A(net_1701) );
CLKBUF_X2 inst_4459 ( .A(net_4444), .Z(net_4445) );
INV_X2 inst_2923 ( .A(net_3001), .ZN(net_151) );
INV_X2 inst_2707 ( .ZN(net_2663), .A(net_2594) );
NOR2_X2 inst_1117 ( .A1(net_3654), .ZN(net_3395), .A2(net_283) );
AOI211_X2 inst_4015 ( .C1(net_3554), .ZN(net_2517), .C2(net_2378), .A(net_1747), .B(net_1685) );
AOI21_X2 inst_3958 ( .B2(net_3441), .ZN(net_1703), .B1(net_1527), .A(net_375) );
NAND2_X2 inst_2007 ( .A2(net_3887), .A1(net_3848), .ZN(net_3537) );
INV_X2 inst_2725 ( .ZN(net_1466), .A(net_1395) );
CLKBUF_X2 inst_5141 ( .A(net_4252), .Z(net_5127) );
AOI22_X2 inst_3644 ( .A1(net_4142), .B1(net_4112), .ZN(net_758), .B2(net_396), .A2(x672) );
NAND2_X2 inst_1610 ( .A1(net_2967), .ZN(net_2406), .A2(net_454) );
OAI22_X2 inst_334 ( .ZN(net_515), .A1(net_514), .A2(net_298), .B1(net_284), .B2(net_264) );
CLKBUF_X2 inst_4620 ( .A(net_4605), .Z(net_4606) );
OAI211_X2 inst_805 ( .C2(net_3845), .ZN(net_1913), .C1(net_1912), .A(net_1820), .B(net_1755) );
AOI22_X2 inst_3707 ( .ZN(net_459), .A1(net_458), .B1(net_457), .B2(net_186), .A2(net_162) );
OAI222_X2 inst_354 ( .B1(net_2717), .A1(net_1126), .ZN(net_1093), .A2(net_1092), .C2(net_988), .C1(net_891), .B2(net_854) );
NOR2_X2 inst_1145 ( .ZN(net_3897), .A1(net_3213), .A2(net_3212) );
NOR2_X2 inst_1042 ( .A2(net_4025), .ZN(net_1247), .A1(net_1003) );
CLKBUF_X2 inst_4492 ( .A(net_4477), .Z(net_4478) );
OAI221_X2 inst_373 ( .B1(net_2733), .C1(net_2686), .ZN(net_2683), .A(net_2559), .B2(net_1748), .C2(net_1655) );
INV_X2 inst_3056 ( .ZN(net_3930), .A(net_3929) );
NAND2_X2 inst_1868 ( .ZN(net_662), .A2(net_449), .A1(net_245) );
OAI21_X2 inst_595 ( .B2(net_2815), .ZN(net_2539), .B1(net_2538), .A(net_1745) );
INV_X4 inst_2609 ( .A(net_3823), .ZN(net_3821) );
XOR2_X2 inst_22 ( .Z(net_4073), .A(net_687), .B(net_42) );
CLKBUF_X2 inst_5002 ( .A(net_4987), .Z(net_4988) );
NAND2_X2 inst_1717 ( .A1(net_3492), .ZN(net_2378), .A2(net_1641) );
INV_X4 inst_2556 ( .ZN(net_3489), .A(net_3170) );
HA_X1 inst_3099 ( .S(net_751), .CO(net_676), .A(net_448), .B(net_261) );
NAND2_X2 inst_1704 ( .A1(net_1834), .ZN(net_1833), .A2(net_360) );
CLKBUF_X2 inst_4604 ( .A(net_4519), .Z(net_4590) );
INV_X2 inst_2901 ( .A(net_3146), .ZN(net_265) );
OAI21_X2 inst_767 ( .ZN(net_3962), .A(net_3960), .B2(net_3620), .B1(net_763) );
CLKBUF_X2 inst_4688 ( .A(net_4673), .Z(net_4674) );
OR4_X2 inst_161 ( .A4(net_3955), .ZN(net_1073), .A1(net_1072), .A2(net_969), .A3(net_812) );
DFF_X1 inst_3356 ( .D(net_3707), .CK(net_4411), .Q(x388) );
CLKBUF_X2 inst_4798 ( .A(net_4783), .Z(net_4784) );
AOI221_X2 inst_3849 ( .B1(net_3736), .C2(net_3114), .ZN(net_2116), .C1(net_2115), .A(net_1934), .B2(net_72) );
OAI21_X2 inst_718 ( .B1(net_3670), .B2(net_3214), .A(net_748), .ZN(net_743) );
NOR2_X2 inst_1029 ( .A1(net_2212), .ZN(net_1569), .A2(net_954) );
AOI211_X2 inst_4024 ( .A(net_3438), .ZN(net_1220), .B(net_1089), .C1(net_1007), .C2(net_903) );
INV_X4 inst_2408 ( .ZN(net_313), .A(net_285) );
NAND3_X2 inst_1324 ( .A3(net_3619), .A1(net_1168), .ZN(net_706), .A2(net_531) );
CLKBUF_X2 inst_4310 ( .A(net_4225), .Z(net_4296) );
OAI22_X2 inst_342 ( .B1(net_3871), .A1(net_3556), .ZN(net_3400), .A2(net_3011), .B2(net_3010) );
OAI21_X2 inst_526 ( .B1(net_3302), .ZN(net_2910), .B2(net_2909), .A(net_2464) );
INV_X8 inst_2147 ( .A(net_3580), .ZN(net_3278) );
NAND4_X4 inst_1178 ( .ZN(net_3937), .A4(net_3936), .A3(net_3766), .A2(net_3664), .A1(net_3521) );
OAI21_X4 inst_463 ( .B1(net_3878), .A(net_3858), .B2(net_3611), .ZN(net_3530) );
NAND2_X1 inst_2091 ( .A1(net_3430), .ZN(net_862), .A2(net_184) );
NAND2_X2 inst_1534 ( .A1(net_3207), .ZN(net_2488), .A2(net_217) );
DFF_X2 inst_3104 ( .D(net_2857), .QN(net_50), .CK(net_4689) );
CLKBUF_X2 inst_4667 ( .A(net_4652), .Z(net_4653) );
AOI221_X2 inst_3820 ( .A(net_2642), .B1(net_2641), .C1(net_2581), .ZN(net_2558), .C2(net_2555), .B2(net_256) );
OAI22_X2 inst_319 ( .B1(net_3143), .ZN(net_1641), .A2(net_1071), .B2(net_1036), .A1(net_952) );
NAND2_X4 inst_1450 ( .A2(net_3859), .ZN(net_3807), .A1(net_2335) );
INV_X4 inst_2422 ( .ZN(net_984), .A(net_48) );
DFF_X2 inst_3123 ( .QN(net_3135), .D(net_2652), .CK(net_4581) );
OAI21_X2 inst_649 ( .B1(net_4180), .ZN(net_2563), .B2(net_1975), .A(net_1524) );
INV_X8 inst_2158 ( .A(net_3938), .ZN(net_3637) );
AOI22_X2 inst_3725 ( .ZN(net_3652), .B1(net_3647), .A1(net_3185), .B2(net_467), .A2(net_454) );
NAND2_X2 inst_1711 ( .A2(net_4034), .ZN(net_1746), .A1(net_1603) );
INV_X4 inst_2597 ( .ZN(net_3738), .A(net_3737) );
DFF_X1 inst_3426 ( .Q(net_4013), .D(net_4012), .CK(net_4914) );
OAI21_X2 inst_500 ( .B1(net_3588), .B2(net_2961), .ZN(net_2942), .A(net_2470) );
NAND2_X2 inst_1592 ( .A1(net_2972), .ZN(net_2426), .A2(net_161) );
NAND2_X2 inst_1770 ( .ZN(net_1171), .A2(net_1170), .A1(net_1107) );
CLKBUF_X2 inst_5185 ( .A(net_5170), .Z(net_5171) );
NAND2_X2 inst_1575 ( .A1(net_2965), .ZN(net_2445), .A2(net_568) );
NOR2_X2 inst_995 ( .ZN(net_2271), .A1(net_2211), .A2(net_1090) );
OAI21_X2 inst_550 ( .B2(net_3207), .B1(net_2887), .ZN(net_2881), .A(net_2477) );
NAND2_X2 inst_2052 ( .ZN(net_3885), .A1(net_3787), .A2(net_2279) );
DFF_X1 inst_3413 ( .Q(net_4031), .D(net_1349), .CK(net_4708) );
CLKBUF_X2 inst_4483 ( .A(net_4353), .Z(net_4469) );
INV_X4 inst_2470 ( .A(net_2983), .ZN(net_230) );
NAND4_X2 inst_1258 ( .ZN(net_4005), .A1(net_3656), .A4(net_3167), .A3(net_513), .A2(net_359) );
DFF_X2 inst_3141 ( .QN(net_2982), .D(net_2569), .CK(net_5232) );
AOI221_X1 inst_3921 ( .ZN(net_3795), .B1(net_3792), .B2(net_1719), .C1(net_1718), .C2(net_1717), .A(net_1245) );
NAND2_X2 inst_1957 ( .A2(net_3869), .A1(net_3779), .ZN(net_3292) );
CLKBUF_X2 inst_5151 ( .A(net_5136), .Z(net_5137) );
AOI221_X2 inst_3857 ( .B1(net_3736), .C2(net_3118), .C1(net_2115), .ZN(net_2047), .A(net_1937), .B2(net_69) );
NOR2_X2 inst_1060 ( .A1(net_1908), .ZN(net_1568), .A2(net_749) );
NAND2_X4 inst_1419 ( .A1(net_3713), .A2(net_3656), .ZN(net_3568) );
NOR3_X2 inst_900 ( .ZN(net_1091), .A3(net_1090), .A1(net_981), .A2(net_297) );
INV_X2 inst_2661 ( .A(net_3677), .ZN(net_2108) );
CLKBUF_X2 inst_4949 ( .A(net_4934), .Z(net_4935) );
CLKBUF_X2 inst_4624 ( .A(net_4609), .Z(net_4610) );
INV_X4 inst_2501 ( .A(net_3068), .ZN(net_731) );
AOI22_X2 inst_3548 ( .B1(net_4054), .A1(net_1578), .ZN(net_1573), .B2(net_1189), .A2(net_378) );
INV_X2 inst_2807 ( .ZN(net_696), .A(net_695) );
OAI21_X2 inst_594 ( .A(net_3582), .ZN(net_2544), .B2(net_2543), .B1(net_2513) );
CLKBUF_X2 inst_4435 ( .A(net_4420), .Z(net_4421) );
INV_X2 inst_2983 ( .A(net_315), .ZN(net_228) );
NAND2_X2 inst_1632 ( .ZN(net_2326), .A1(net_2270), .A2(net_356) );
INV_X4 inst_2175 ( .ZN(net_2791), .A(net_2790) );
CLKBUF_X2 inst_4241 ( .A(net_4218), .Z(net_4227) );
NOR2_X4 inst_925 ( .ZN(net_2244), .A2(net_2171), .A1(net_2170) );
INV_X4 inst_2193 ( .A(net_2778), .ZN(net_2346) );
INV_X4 inst_2378 ( .ZN(net_523), .A(net_368) );
NOR2_X2 inst_1120 ( .ZN(net_3412), .A1(net_2718), .A2(net_2717) );
NAND2_X2 inst_1536 ( .A1(net_2907), .ZN(net_2486), .A2(net_188) );
NOR3_X4 inst_881 ( .ZN(net_3798), .A1(net_3797), .A3(net_3218), .A2(net_2027) );
AOI221_X2 inst_3876 ( .B2(net_3112), .B1(net_2020), .C1(net_2019), .ZN(net_1871), .A(net_1870), .C2(x332) );
DFF_X2 inst_3184 ( .QN(net_3159), .D(net_1752), .CK(net_4757) );
AOI221_X2 inst_3848 ( .B1(net_3736), .C2(net_3119), .ZN(net_2117), .C1(net_2115), .A(net_1939), .B2(net_68) );
NAND4_X2 inst_1225 ( .ZN(net_856), .A4(net_654), .A3(net_561), .A1(net_484), .A2(net_481) );
NOR2_X4 inst_947 ( .A2(net_3869), .ZN(net_3555), .A1(net_3262) );
OAI21_X2 inst_731 ( .B1(net_984), .A(net_629), .B2(net_628), .ZN(net_579) );
AOI22_X2 inst_3706 ( .B2(net_4124), .A2(net_509), .ZN(net_460), .A1(net_226), .B1(net_167) );
INV_X4 inst_2459 ( .A(net_3056), .ZN(net_474) );
OAI22_X2 inst_301 ( .ZN(net_1544), .A1(net_1543), .B1(net_1542), .B2(net_1541), .A2(net_315) );
OAI221_X2 inst_363 ( .B1(net_4037), .C1(net_3352), .B2(net_3348), .ZN(net_2769), .A(net_2556), .C2(net_2131) );
INV_X8 inst_2141 ( .A(net_3204), .ZN(net_3185) );
OR2_X2 inst_247 ( .ZN(net_2826), .A1(net_2825), .A2(net_2384) );
CLKBUF_X2 inst_4551 ( .A(net_4536), .Z(net_4537) );
CLKBUF_X2 inst_4313 ( .A(net_4298), .Z(net_4299) );
OAI221_X2 inst_403 ( .C2(net_3959), .ZN(net_2140), .C1(net_2119), .B2(net_2118), .B1(net_1894), .A(net_593) );
CLKBUF_X2 inst_4714 ( .A(net_4699), .Z(net_4700) );
CLKBUF_X2 inst_4706 ( .A(net_4590), .Z(net_4692) );
CLKBUF_X2 inst_4348 ( .A(net_4333), .Z(net_4334) );
INV_X2 inst_2728 ( .ZN(net_1438), .A(net_1437) );
NAND2_X2 inst_1588 ( .A1(net_2972), .ZN(net_2431), .A2(net_735) );
AOI221_X2 inst_3801 ( .C1(net_2781), .B1(net_2775), .ZN(net_2774), .A(net_2664), .B2(net_315), .C2(net_251) );
AND2_X4 inst_4177 ( .ZN(net_4131), .A1(net_3104), .A2(net_121) );
INV_X2 inst_2956 ( .A(net_3097), .ZN(net_226) );
CLKBUF_X2 inst_4713 ( .A(net_4698), .Z(net_4699) );
AOI22_X2 inst_3729 ( .ZN(net_4176), .A1(net_4175), .B1(net_2703), .A2(net_132), .B2(net_73) );
OAI221_X2 inst_412 ( .ZN(net_1718), .A(net_1460), .C1(net_1455), .B2(net_1273), .B1(net_1219), .C2(net_1033) );
INV_X4 inst_2516 ( .A(net_3780), .ZN(net_3187) );
INV_X2 inst_2650 ( .A(net_3470), .ZN(net_2291) );
CLKBUF_X2 inst_4508 ( .A(net_4493), .Z(net_4494) );
INV_X8 inst_2155 ( .ZN(net_3556), .A(net_3555) );
NAND2_X2 inst_1506 ( .A1(net_3530), .A2(net_3510), .ZN(net_2708) );
OAI21_X4 inst_464 ( .B1(net_3904), .B2(net_3638), .ZN(net_3602), .A(net_582) );
OAI22_X2 inst_341 ( .ZN(net_3364), .A1(net_3353), .B2(net_3138), .A2(net_1071), .B1(net_1036) );
AOI222_X1 inst_3785 ( .C1(net_3151), .B1(net_2020), .C2(net_1840), .A2(net_1698), .ZN(net_1661), .B2(net_512), .A1(net_272) );
DFF_X2 inst_3189 ( .D(net_1654), .CK(net_4991), .QN(x557) );
DFF_X2 inst_3163 ( .QN(net_3820), .D(net_2140), .CK(net_5283) );
INV_X4 inst_2504 ( .ZN(net_184), .A(net_89) );
INV_X4 inst_2359 ( .ZN(net_527), .A(net_523) );
AOI22_X2 inst_3702 ( .B1(net_4124), .A2(net_3025), .B2(net_3024), .A1(net_509), .ZN(net_466) );
OAI21_X2 inst_684 ( .B1(net_3228), .ZN(net_1445), .A(net_1307), .B2(net_505) );
CLKBUF_X2 inst_4354 ( .A(net_4339), .Z(net_4340) );
DFF_X1 inst_3374 ( .D(net_2259), .QN(net_47), .CK(net_4478) );
CLKBUF_X2 inst_4400 ( .A(net_4361), .Z(net_4386) );
DFF_X2 inst_3177 ( .D(net_1846), .Q(net_84), .CK(net_4996) );
NAND3_X2 inst_1361 ( .ZN(net_3866), .A3(net_3865), .A2(net_3864), .A1(net_3863) );
CLKBUF_X2 inst_4930 ( .A(net_4915), .Z(net_4916) );
DFF_X1 inst_3401 ( .Q(net_3114), .D(net_1538), .CK(net_4470) );
AOI221_X2 inst_3811 ( .B2(net_3145), .A(net_2642), .ZN(net_2595), .C2(net_2594), .B1(net_2591), .C1(net_2589) );
AOI22_X2 inst_3653 ( .ZN(net_682), .A1(net_458), .B1(net_457), .A2(net_208), .B2(net_150) );
CLKBUF_X2 inst_4968 ( .A(net_4953), .Z(net_4954) );
CLKBUF_X2 inst_4463 ( .A(net_4202), .Z(net_4449) );
INV_X4 inst_2208 ( .ZN(net_2248), .A(net_2247) );
NOR2_X2 inst_1138 ( .ZN(net_3765), .A2(net_3477), .A1(net_358) );
AND2_X4 inst_4162 ( .ZN(net_4115), .A1(net_1107), .A2(net_923) );
NAND4_X2 inst_1241 ( .A2(net_3651), .ZN(net_3248), .A1(net_3247), .A4(net_2176), .A3(net_2175) );
NOR2_X2 inst_1038 ( .ZN(net_1224), .A1(net_1089), .A2(net_775) );
CLKBUF_X2 inst_5171 ( .A(net_4390), .Z(net_5157) );
INV_X4 inst_2174 ( .ZN(net_2795), .A(net_2794) );
NOR2_X4 inst_940 ( .ZN(net_3237), .A2(net_2173), .A1(net_2172) );
NOR2_X2 inst_1004 ( .A1(net_2684), .ZN(net_2060), .A2(net_1905) );
DFF_X2 inst_3201 ( .D(net_1592), .QN(net_120), .CK(net_4988) );
AOI22_X2 inst_3595 ( .A1(net_4063), .B1(net_4058), .B2(net_3402), .A2(net_3401), .ZN(net_1422) );
OR2_X4 inst_189 ( .A2(net_2607), .ZN(net_2579), .A1(net_2578) );
CLKBUF_X2 inst_4876 ( .A(net_4861), .Z(net_4862) );
XOR2_X2 inst_14 ( .A(net_1125), .B(net_1101), .Z(net_1088) );
INV_X4 inst_2450 ( .A(net_3060), .ZN(net_734) );
CLKBUF_X2 inst_4362 ( .A(net_4347), .Z(net_4348) );
XNOR2_X2 inst_62 ( .ZN(net_1903), .A(net_1754), .B(net_1660) );
INV_X4 inst_2325 ( .A(net_3547), .ZN(net_700) );
CLKBUF_X2 inst_4696 ( .A(net_4681), .Z(net_4682) );
CLKBUF_X2 inst_4369 ( .A(net_4354), .Z(net_4355) );
AOI222_X1 inst_3743 ( .A1(net_4189), .C1(net_3504), .B1(net_3472), .ZN(net_2318), .A2(net_1791), .C2(net_920), .B2(net_142) );
OR2_X2 inst_251 ( .A2(net_4131), .ZN(net_1927), .A1(net_1808) );
INV_X2 inst_2860 ( .A(net_3165), .ZN(net_297) );
CLKBUF_X2 inst_5194 ( .A(net_4524), .Z(net_5180) );
NOR2_X2 inst_1074 ( .ZN(net_694), .A1(net_693), .A2(net_639) );
NOR3_X4 inst_879 ( .A2(net_3946), .A3(net_3940), .ZN(net_3725), .A1(net_3108) );
AOI21_X2 inst_4007 ( .ZN(net_4158), .B2(net_3110), .A(net_2273), .B1(net_2241) );
NAND2_X2 inst_1552 ( .A1(net_2961), .ZN(net_2470), .A2(net_461) );
NAND2_X2 inst_1524 ( .A1(net_2959), .ZN(net_2498), .A2(net_833) );
CLKBUF_X2 inst_4789 ( .A(net_4774), .Z(net_4775) );
CLKBUF_X2 inst_4977 ( .A(net_4962), .Z(net_4963) );
CLKBUF_X2 inst_4482 ( .A(net_4467), .Z(net_4468) );
CLKBUF_X2 inst_4291 ( .A(net_4198), .Z(net_4277) );
NAND2_X2 inst_1602 ( .A1(net_2969), .ZN(net_2415), .A2(net_493) );
NOR2_X4 inst_969 ( .ZN(net_3877), .A1(net_3232), .A2(net_2207) );
CLKBUF_X2 inst_4903 ( .A(net_4888), .Z(net_4889) );
OAI21_X2 inst_629 ( .B2(net_4089), .B1(net_2190), .ZN(net_2146), .A(net_2035) );
NOR2_X2 inst_1100 ( .A2(net_3108), .ZN(net_277), .A1(net_218) );
INV_X4 inst_2528 ( .ZN(net_3275), .A(net_647) );
OAI211_X2 inst_791 ( .C1(net_3449), .ZN(net_2705), .C2(net_2704), .A(net_2605), .B(net_2526) );
NAND2_X2 inst_2021 ( .ZN(net_3693), .A1(net_3688), .A2(net_70) );
CLKBUF_X2 inst_4917 ( .A(net_4902), .Z(net_4903) );
CLKBUF_X2 inst_4379 ( .A(net_4364), .Z(net_4365) );
NOR3_X2 inst_898 ( .ZN(net_1223), .A1(net_1222), .A2(net_1158), .A3(net_1081) );
DFF_X1 inst_3383 ( .D(net_1887), .QN(net_82), .CK(net_4433) );
NAND2_X2 inst_1977 ( .A1(net_3804), .ZN(net_3370), .A2(net_3268) );
NAND2_X2 inst_1793 ( .A1(net_3905), .A2(net_1105), .ZN(net_1074) );
NAND4_X2 inst_1191 ( .A2(net_4053), .A3(net_1776), .A1(net_1634), .ZN(net_1633), .A4(net_1382) );
CLKBUF_X2 inst_4227 ( .A(net_4212), .Z(net_4213) );
CLKBUF_X2 inst_5086 ( .A(net_4405), .Z(net_5072) );
OAI21_X2 inst_533 ( .B1(net_3195), .B2(net_2967), .ZN(net_2900), .A(net_2410) );
INV_X4 inst_2478 ( .A(net_3081), .ZN(net_468) );
CLKBUF_X2 inst_5299 ( .A(net_5284), .Z(net_5285) );
CLKBUF_X2 inst_4972 ( .A(net_4400), .Z(net_4958) );
INV_X2 inst_2751 ( .A(net_1330), .ZN(net_1077) );
NAND2_X2 inst_1874 ( .A2(net_3959), .ZN(net_508), .A1(net_276) );
NAND2_X2 inst_1760 ( .A2(net_1394), .ZN(net_1239), .A1(net_37) );
INV_X4 inst_2291 ( .ZN(net_1694), .A(net_868) );
INV_X4 inst_2343 ( .ZN(net_611), .A(net_610) );
INV_X4 inst_2538 ( .ZN(net_3379), .A(net_3378) );
NAND2_X2 inst_2022 ( .ZN(net_3704), .A1(net_2357), .A2(net_1889) );
CLKBUF_X2 inst_4822 ( .A(net_4363), .Z(net_4808) );
INV_X2 inst_2821 ( .A(net_658), .ZN(net_539) );
DFF_X2 inst_3132 ( .D(net_2631), .QN(net_987), .CK(net_4812) );
AOI21_X2 inst_3960 ( .ZN(net_1711), .A(net_1561), .B1(net_433), .B2(net_168) );
NOR2_X2 inst_1095 ( .A2(net_4131), .ZN(net_360), .A1(net_178) );
OR3_X4 inst_176 ( .ZN(net_1274), .A2(net_312), .A1(net_266), .A3(net_263) );
INV_X4 inst_2439 ( .A(net_2988), .ZN(net_197) );
CLKBUF_X2 inst_4999 ( .A(net_4984), .Z(net_4985) );
INV_X2 inst_2826 ( .A(net_3941), .ZN(net_599) );
AOI221_X2 inst_3910 ( .B2(net_3998), .A(net_3325), .ZN(net_783), .C1(net_655), .B1(net_528), .C2(net_377) );
NAND3_X2 inst_1336 ( .A2(net_1401), .ZN(net_1126), .A1(net_406), .A3(net_263) );
NAND3_X2 inst_1332 ( .ZN(net_504), .A1(net_405), .A3(net_374), .A2(net_310) );
CLKBUF_X2 inst_4404 ( .A(net_4389), .Z(net_4390) );
NAND2_X2 inst_1841 ( .A2(net_3590), .ZN(net_843), .A1(net_788) );
CLKBUF_X2 inst_4500 ( .A(net_4485), .Z(net_4486) );
NAND2_X2 inst_1665 ( .ZN(net_2097), .A1(net_2096), .A2(net_195) );
DFF_X1 inst_3345 ( .D(net_2744), .QN(net_115), .CK(net_4448) );
CLKBUF_X2 inst_4763 ( .A(net_4748), .Z(net_4749) );
DFF_X1 inst_3264 ( .QN(net_3072), .D(net_2932), .CK(net_4721) );
CLKBUF_X2 inst_5169 ( .A(net_5154), .Z(net_5155) );
CLKBUF_X2 inst_4945 ( .A(net_4338), .Z(net_4931) );
OAI211_X2 inst_780 ( .C2(net_3348), .ZN(net_2841), .C1(net_2828), .B(net_2614), .A(net_2566) );
INV_X4 inst_2332 ( .A(net_3955), .ZN(net_674) );
AOI21_X2 inst_3967 ( .A(net_2525), .ZN(net_1364), .B1(net_1179), .B2(net_1175) );
INV_X4 inst_2310 ( .ZN(net_966), .A(net_791) );
NOR2_X2 inst_1089 ( .A1(net_3756), .ZN(net_424), .A2(net_373) );
AOI211_X2 inst_4018 ( .A(net_4185), .B(net_4083), .ZN(net_1810), .C1(net_1567), .C2(net_1045) );
NAND2_X2 inst_1767 ( .ZN(net_1627), .A2(net_1386), .A1(net_1232) );
AOI22_X2 inst_3669 ( .B1(net_570), .ZN(net_556), .A1(net_555), .B2(net_217), .A2(net_159) );
INV_X4 inst_2219 ( .ZN(net_2227), .A(net_2190) );
NAND3_X2 inst_1284 ( .A3(net_3127), .ZN(net_2297), .A1(net_2296), .A2(net_248) );
OAI21_X2 inst_546 ( .B2(net_2915), .B1(net_2887), .ZN(net_2885), .A(net_2438) );
INV_X4 inst_2465 ( .A(net_3092), .ZN(net_833) );
CLKBUF_X2 inst_5017 ( .A(net_4198), .Z(net_5003) );
INV_X4 inst_2361 ( .A(net_2514), .ZN(x475) );
NAND3_X2 inst_1290 ( .ZN(net_2257), .A1(net_2205), .A3(net_1951), .A2(net_1924) );
OAI21_X2 inst_704 ( .B2(net_3974), .ZN(net_893), .B1(net_754), .A(net_640) );
CLKBUF_X2 inst_5038 ( .A(net_5023), .Z(net_5024) );
CLKBUF_X2 inst_4542 ( .A(net_4527), .Z(net_4528) );
CLKBUF_X2 inst_5142 ( .A(net_5127), .Z(net_5128) );
INV_X4 inst_2226 ( .A(net_3428), .ZN(net_2049) );
OAI21_X2 inst_694 ( .B2(net_3123), .ZN(net_1330), .B1(net_822), .A(net_814) );
CLKBUF_X2 inst_4899 ( .A(net_4884), .Z(net_4885) );
NAND2_X2 inst_2046 ( .A1(net_3875), .A2(net_3859), .ZN(net_3850) );
CLKBUF_X2 inst_5079 ( .A(net_5064), .Z(net_5065) );
AND2_X4 inst_4129 ( .ZN(net_4056), .A2(net_3339), .A1(net_1247) );
INV_X4 inst_2498 ( .A(net_3164), .ZN(net_223) );
DFF_X2 inst_3154 ( .D(net_2260), .QN(net_46), .CK(net_4629) );
AOI221_X2 inst_3861 ( .B2(net_3120), .ZN(net_2021), .B1(net_2020), .C1(net_2019), .A(net_1899), .C2(x285) );
CLKBUF_X2 inst_4399 ( .A(net_4384), .Z(net_4385) );
CLKBUF_X2 inst_5211 ( .A(net_5196), .Z(net_5197) );
NAND3_X2 inst_1342 ( .A1(net_3782), .ZN(net_3407), .A3(net_3406), .A2(net_1376) );
INV_X2 inst_2971 ( .A(net_3043), .ZN(net_163) );
AND2_X2 inst_4196 ( .A2(net_2222), .ZN(net_1870), .A1(net_1862) );
AOI22_X2 inst_3524 ( .A2(net_3132), .A1(net_1923), .B1(net_1921), .ZN(net_1920), .B2(net_218) );
CLKBUF_X2 inst_4479 ( .A(net_4389), .Z(net_4465) );
CLKBUF_X2 inst_4396 ( .A(net_4293), .Z(net_4382) );
NOR2_X2 inst_1014 ( .A1(net_3486), .ZN(net_1867), .A2(net_1738) );
OAI211_X2 inst_787 ( .ZN(net_2760), .C2(net_2709), .B(net_2649), .A(net_2635), .C1(net_2603) );
INV_X4 inst_2531 ( .A(net_3618), .ZN(net_3290) );
CLKBUF_X2 inst_4549 ( .A(net_4534), .Z(net_4535) );
CLKBUF_X2 inst_4782 ( .A(net_4767), .Z(net_4768) );
AOI21_X2 inst_3933 ( .B2(net_3111), .ZN(net_2796), .B1(net_2792), .A(net_2745) );
NAND3_X2 inst_1347 ( .ZN(net_3476), .A3(net_3475), .A2(net_3474), .A1(net_3473) );
OAI211_X2 inst_825 ( .ZN(net_1464), .C2(net_1463), .A(net_1228), .C1(net_1036), .B(net_593) );
NAND2_X2 inst_1656 ( .A1(net_3200), .ZN(net_2112), .A2(net_1981) );
OAI21_X2 inst_509 ( .B1(net_3274), .B2(net_2965), .ZN(net_2933), .A(net_2443) );
INV_X4 inst_2586 ( .ZN(net_3655), .A(net_3653) );
INV_X2 inst_2687 ( .ZN(net_1788), .A(net_1708) );
NAND2_X2 inst_1680 ( .A1(net_3281), .ZN(net_2028), .A2(net_214) );
NAND2_X2 inst_1881 ( .ZN(net_891), .A1(net_413), .A2(net_335) );
NAND2_X2 inst_1626 ( .ZN(net_2601), .A2(net_2596), .A1(net_2389) );
INV_X4 inst_2622 ( .ZN(net_3953), .A(net_3913) );
SDFF_X2 inst_153 ( .SE(net_2218), .D(net_1610), .SI(net_211), .QN(net_55), .CK(net_4785) );
CLKBUF_X2 inst_4856 ( .A(net_4706), .Z(net_4842) );
NAND2_X2 inst_1892 ( .ZN(net_421), .A1(net_394), .A2(net_393) );
INV_X2 inst_3034 ( .A(net_3660), .ZN(net_3571) );
NAND2_X4 inst_1459 ( .A1(net_4152), .ZN(net_3858), .A2(net_1266) );
OAI21_X2 inst_726 ( .B1(net_3657), .A(net_3215), .ZN(net_602), .B2(net_320) );
OAI22_X2 inst_295 ( .A2(net_4034), .ZN(net_1704), .A1(net_1653), .B1(net_1165), .B2(net_1090) );
AND2_X4 inst_4094 ( .ZN(net_1955), .A2(net_1828), .A1(net_1827) );
OR2_X4 inst_209 ( .ZN(net_2327), .A1(net_2303), .A2(net_2214) );
AOI221_X2 inst_3894 ( .C2(net_4028), .A(net_2525), .C1(net_1394), .B1(net_1393), .ZN(net_1348), .B2(net_1326) );
CLKBUF_X2 inst_4726 ( .A(net_4711), .Z(net_4712) );
NOR2_X2 inst_1087 ( .ZN(net_584), .A1(net_394), .A2(net_393) );
NAND2_X2 inst_1781 ( .ZN(net_1300), .A2(net_1064), .A1(net_1063) );
OAI22_X2 inst_320 ( .B1(net_1614), .ZN(net_1070), .A1(net_1069), .A2(net_729), .B2(net_260) );
OAI21_X2 inst_607 ( .A(net_3886), .B1(net_3883), .B2(net_3516), .ZN(net_2329) );
INV_X2 inst_2769 ( .A(net_3573), .ZN(net_888) );
INV_X4 inst_2432 ( .A(net_2993), .ZN(net_181) );
NAND3_X2 inst_1375 ( .ZN(net_4192), .A2(net_3383), .A1(net_3382), .A3(net_1291) );
CLKBUF_X2 inst_4263 ( .A(net_4248), .Z(net_4249) );
CLKBUF_X2 inst_5061 ( .A(net_5046), .Z(net_5047) );
XOR2_X2 inst_1 ( .Z(net_2304), .A(net_2152), .B(net_1736) );
NAND2_X2 inst_1891 ( .A2(net_3590), .ZN(net_411), .A1(net_398) );
AOI21_X2 inst_3982 ( .B2(net_4144), .B1(net_3627), .ZN(net_946), .A(net_885) );
CLKBUF_X2 inst_4343 ( .A(net_4328), .Z(net_4329) );
CLKBUF_X2 inst_4564 ( .A(net_4549), .Z(net_4550) );
CLKBUF_X2 inst_4558 ( .A(net_4543), .Z(net_4544) );
CLKBUF_X2 inst_5258 ( .A(net_5243), .Z(net_5244) );
DFF_X2 inst_3215 ( .QN(net_3152), .D(net_803), .CK(net_4663) );
OR2_X4 inst_235 ( .ZN(net_3207), .A1(net_3206), .A2(net_2354) );
INV_X16 inst_3063 ( .A(net_3293), .ZN(net_1973) );
INV_X4 inst_2564 ( .ZN(net_3519), .A(net_2094) );
NAND2_X2 inst_1812 ( .A2(net_4120), .ZN(net_914), .A1(net_747) );
NOR2_X2 inst_1082 ( .ZN(net_585), .A2(net_584), .A1(net_422) );
AND2_X4 inst_4167 ( .ZN(net_4121), .A1(net_3160), .A2(net_3159) );
INV_X2 inst_2677 ( .ZN(net_1887), .A(net_1842) );
CLKBUF_X2 inst_4374 ( .A(net_4359), .Z(net_4360) );
NAND2_X2 inst_1995 ( .ZN(net_3480), .A1(net_2563), .A2(net_2003) );
XNOR2_X2 inst_105 ( .ZN(net_616), .A(net_309), .B(net_48) );
CLKBUF_X2 inst_4338 ( .A(net_4248), .Z(net_4324) );
AOI22_X2 inst_3518 ( .B1(net_4045), .B2(net_2051), .A1(net_1955), .ZN(net_1952), .A2(net_280) );
INV_X8 inst_2161 ( .ZN(net_3647), .A(net_3645) );
OAI21_X2 inst_625 ( .B2(net_4061), .ZN(net_2243), .A(net_2142), .B1(net_2127) );
CLKBUF_X2 inst_4721 ( .A(net_4706), .Z(net_4707) );
DFF_X1 inst_3367 ( .D(net_3697), .CK(net_4445), .Q(x256) );
INV_X2 inst_2835 ( .ZN(net_422), .A(net_421) );
OAI21_X2 inst_568 ( .B2(net_2907), .B1(net_2849), .ZN(net_2844), .A(net_2486) );
NAND2_X4 inst_1483 ( .ZN(net_3992), .A1(net_3991), .A2(net_3987) );
OAI21_X2 inst_523 ( .B2(net_2969), .B1(net_2923), .ZN(net_2914), .A(net_2412) );
INV_X2 inst_2731 ( .ZN(net_1396), .A(net_1348) );
INV_X4 inst_2207 ( .ZN(net_2252), .A(net_2224) );
NAND2_X2 inst_1492 ( .A1(net_3499), .ZN(net_2858), .A2(net_2630) );
OR3_X2 inst_181 ( .ZN(net_1721), .A3(net_1617), .A1(net_1587), .A2(net_1586) );
CLKBUF_X2 inst_5215 ( .A(net_4937), .Z(net_5201) );
CLKBUF_X2 inst_4234 ( .A(net_4219), .Z(net_4220) );
CLKBUF_X2 inst_4813 ( .A(net_4678), .Z(net_4799) );
AOI221_X2 inst_3892 ( .B2(net_2051), .C2(net_1394), .B1(net_1393), .ZN(net_1355), .A(net_1173), .C1(net_36) );
OAI21_X2 inst_713 ( .B2(net_874), .ZN(net_816), .A(net_815), .B1(net_616) );
AOI21_X4 inst_3930 ( .B2(net_3889), .B1(net_3838), .ZN(net_3700), .A(net_3567) );
INV_X2 inst_2867 ( .A(net_393), .ZN(net_329) );
INV_X2 inst_2898 ( .ZN(net_182), .A(net_114) );
OAI21_X2 inst_477 ( .ZN(net_2973), .B2(net_2972), .B1(net_2970), .A(net_2430) );
DFF_X1 inst_3398 ( .Q(net_3121), .D(net_1546), .CK(net_4306) );
NAND3_X2 inst_1368 ( .ZN(net_3989), .A3(net_3988), .A1(net_640), .A2(net_432) );
AOI22_X2 inst_3576 ( .A1(net_4060), .B1(net_4055), .ZN(net_1474), .B2(net_834), .A2(net_833) );
OAI221_X2 inst_423 ( .B1(net_3963), .B2(net_3338), .C2(net_3162), .ZN(net_1157), .A(net_1031), .C1(x475) );
OAI211_X2 inst_835 ( .C2(net_2637), .C1(net_1359), .ZN(net_1356), .A(net_1236), .B(net_593) );
NAND2_X1 inst_2088 ( .A2(net_4017), .A1(net_2969), .ZN(net_2419) );
DFF_X1 inst_3305 ( .QN(net_3019), .D(net_2869), .CK(net_5080) );
INV_X1 inst_3082 ( .ZN(net_3549), .A(net_3548) );
AND2_X4 inst_4137 ( .ZN(net_4066), .A1(net_2596), .A2(net_1032) );
DFF_X2 inst_3208 ( .QN(net_3162), .D(net_1157), .CK(net_5088) );
AND2_X4 inst_4134 ( .ZN(net_4063), .A2(net_1192), .A1(net_1136) );
NOR2_X2 inst_1112 ( .ZN(net_3327), .A2(net_3319), .A1(net_605) );
AOI22_X2 inst_3507 ( .B1(net_3676), .B2(net_3141), .A1(net_2012), .ZN(net_2010), .A2(net_379) );
OAI21_X2 inst_710 ( .ZN(net_1013), .A(net_750), .B1(net_725), .B2(net_526) );
AND3_X4 inst_4081 ( .ZN(net_4185), .A2(net_3571), .A1(net_618), .A3(net_594) );
NAND3_X1 inst_1379 ( .ZN(net_3350), .A2(net_3349), .A1(net_2550), .A3(net_1737) );
NOR2_X4 inst_941 ( .A1(net_3550), .ZN(net_3276), .A2(net_1457) );
OR2_X2 inst_271 ( .ZN(net_3771), .A2(net_2053), .A1(net_1808) );
DFF_X1 inst_3350 ( .D(net_2702), .QN(net_70), .CK(net_4267) );
NAND2_X2 inst_1817 ( .ZN(net_831), .A2(net_819), .A1(net_204) );
XNOR2_X2 inst_56 ( .B(net_3240), .ZN(net_2193), .A(net_2121) );
OAI22_X2 inst_308 ( .A2(net_1975), .A1(net_1461), .ZN(net_1333), .B1(net_1332), .B2(net_1200) );
NAND2_X2 inst_1546 ( .A2(net_4023), .A1(net_2961), .ZN(net_2476) );
NAND4_X2 inst_1230 ( .ZN(net_2222), .A4(net_565), .A1(net_546), .A2(net_500), .A3(net_482) );
OAI21_X4 inst_455 ( .B1(net_3673), .A(net_3430), .ZN(net_1457), .B2(net_1272) );
AOI22_X2 inst_3535 ( .A2(net_1908), .ZN(net_1770), .A1(net_1676), .B2(net_749), .B1(net_103) );
NAND2_X2 inst_1694 ( .A1(net_3293), .ZN(net_1976), .A2(net_202) );
INV_X2 inst_2871 ( .ZN(net_284), .A(net_109) );
INV_X4 inst_2540 ( .ZN(net_3397), .A(net_3109) );
AOI22_X2 inst_3497 ( .B1(net_3219), .ZN(net_2176), .A1(net_2134), .A2(net_597), .B2(net_596) );
NOR2_X2 inst_1064 ( .A2(net_3627), .ZN(net_885), .A1(net_511) );
AOI22_X2 inst_3629 ( .ZN(net_1638), .B1(net_931), .A1(net_800), .A2(net_401), .B2(net_267) );
AOI22_X2 inst_3599 ( .A1(net_4063), .B1(net_4058), .ZN(net_1418), .A2(net_237), .B2(net_157) );
INV_X2 inst_3024 ( .ZN(net_3459), .A(net_3458) );
OAI21_X2 inst_583 ( .B1(net_4036), .B2(net_2815), .ZN(net_2777), .A(net_1576) );
NAND2_X2 inst_1904 ( .A2(net_3166), .ZN(net_374), .A1(net_309) );
CLKBUF_X2 inst_5208 ( .A(net_5193), .Z(net_5194) );
AOI22_X2 inst_3581 ( .A1(net_4059), .B1(net_4056), .A2(net_4019), .B2(net_4017), .ZN(net_1469) );
CLKBUF_X2 inst_4414 ( .A(net_4399), .Z(net_4400) );
CLKBUF_X2 inst_4325 ( .A(net_4310), .Z(net_4311) );
CLKBUF_X2 inst_4833 ( .A(net_4818), .Z(net_4819) );
NAND2_X2 inst_2065 ( .ZN(net_3946), .A2(net_3124), .A1(net_3107) );
INV_X4 inst_2251 ( .A(net_4192), .ZN(net_1502) );
INV_X1 inst_3085 ( .ZN(net_3981), .A(net_3980) );
AOI21_X2 inst_3987 ( .A(net_4185), .B2(net_923), .ZN(net_792), .B1(net_692) );
AOI21_X2 inst_3951 ( .B1(net_3736), .ZN(net_1990), .A(net_1856), .B2(net_1439) );
CLKBUF_X2 inst_5124 ( .A(net_5109), .Z(net_5110) );
CLKBUF_X2 inst_4282 ( .A(net_4234), .Z(net_4268) );
CLKBUF_X2 inst_4863 ( .A(net_4848), .Z(net_4849) );
CLKBUF_X2 inst_4910 ( .A(net_4895), .Z(net_4896) );
NAND2_X2 inst_1899 ( .ZN(net_365), .A1(net_291), .A2(net_288) );
INV_X2 inst_2943 ( .A(net_3017), .ZN(net_140) );
NAND2_X2 inst_1593 ( .A1(net_2925), .ZN(net_2425), .A2(net_174) );
INV_X4 inst_2569 ( .ZN(net_3540), .A(net_3129) );
OAI21_X2 inst_724 ( .B2(net_1217), .ZN(net_620), .A(net_619), .B1(net_406) );
CLKBUF_X2 inst_4292 ( .A(net_4277), .Z(net_4278) );
INV_X2 inst_2716 ( .A(net_3802), .ZN(net_1772) );
INV_X4 inst_2449 ( .ZN(net_2623), .A(net_66) );
DFF_X1 inst_3228 ( .QN(net_3069), .D(net_2973), .CK(net_4882) );
NOR2_X4 inst_975 ( .A2(net_3997), .ZN(net_3932), .A1(net_3668) );
INV_X8 inst_2124 ( .A(net_3606), .ZN(net_399) );
INV_X2 inst_2789 ( .ZN(net_1253), .A(net_1131) );
DFF_X2 inst_3191 ( .QN(net_3163), .D(net_1697), .CK(net_5092) );
INV_X4 inst_2289 ( .ZN(net_1100), .A(net_880) );
NAND2_X4 inst_1435 ( .ZN(net_3674), .A1(net_3541), .A2(net_3270) );
NAND2_X4 inst_1431 ( .ZN(net_3660), .A1(net_3603), .A2(net_3243) );
AOI222_X1 inst_3760 ( .A2(net_3466), .C1(net_3119), .A1(net_2055), .B1(net_2054), .C2(net_2053), .ZN(net_2002), .B2(net_1468) );
NAND2_X4 inst_1398 ( .A1(net_3228), .ZN(net_1307), .A2(net_231) );
AOI222_X1 inst_3746 ( .C1(net_3504), .B1(net_3472), .A1(net_3469), .A2(net_3134), .ZN(net_2278), .B2(net_2051), .C2(net_874) );
NAND2_X2 inst_1804 ( .A1(net_4082), .ZN(net_1069), .A2(net_847) );
INV_X2 inst_2750 ( .A(net_2384), .ZN(net_1319) );
INV_X2 inst_2849 ( .ZN(net_375), .A(net_356) );
INV_X4 inst_2440 ( .A(net_3163), .ZN(net_144) );
AND2_X4 inst_4121 ( .ZN(net_4044), .A1(net_1875), .A2(net_1874) );
NAND2_X4 inst_1467 ( .ZN(net_3892), .A2(net_3716), .A1(net_3276) );
INV_X2 inst_2640 ( .ZN(net_2731), .A(net_2581) );
INV_X4 inst_2183 ( .ZN(net_2722), .A(net_2565) );
DFF_X1 inst_3327 ( .Q(net_3115), .D(net_2810), .CK(net_4371) );
CLKBUF_X2 inst_5068 ( .A(net_4589), .Z(net_5054) );
CLKBUF_X2 inst_4448 ( .A(net_4304), .Z(net_4434) );
INV_X2 inst_2659 ( .ZN(net_2113), .A(net_2039) );
INV_X8 inst_2134 ( .A(net_283), .ZN(net_279) );
NAND2_X2 inst_1744 ( .A2(net_1507), .A1(net_1441), .ZN(net_1436) );
CLKBUF_X2 inst_5018 ( .A(net_5003), .Z(net_5004) );
CLKBUF_X2 inst_4805 ( .A(net_4790), .Z(net_4791) );
INV_X2 inst_2834 ( .A(net_3156), .ZN(net_2514) );
CLKBUF_X2 inst_4784 ( .A(net_4769), .Z(net_4770) );
AND2_X4 inst_4117 ( .ZN(net_4035), .A1(net_2735), .A2(net_2694) );
NAND2_X2 inst_1513 ( .A2(net_4066), .ZN(net_2718), .A1(net_2612) );
NOR2_X2 inst_1155 ( .ZN(net_4057), .A2(net_1192), .A1(net_1191) );
OR2_X4 inst_207 ( .A1(net_3816), .ZN(net_2925), .A2(net_2354) );
DFF_X1 inst_3321 ( .QN(net_3000), .D(net_2846), .CK(net_5111) );
AND3_X4 inst_4080 ( .ZN(net_4162), .A1(net_3662), .A2(net_3642), .A3(net_3108) );
NAND2_X2 inst_1545 ( .A2(net_3402), .A1(net_3207), .ZN(net_2477) );
OAI22_X2 inst_333 ( .ZN(net_714), .A1(net_344), .B2(net_263), .B1(net_48), .A2(net_46) );
DFF_X1 inst_3338 ( .D(net_2763), .CK(net_4362), .Q(x0) );
OAI21_X2 inst_712 ( .ZN(net_1064), .B1(net_843), .A(net_842), .B2(net_669) );
NAND4_X2 inst_1215 ( .A1(net_2596), .ZN(net_1275), .A4(net_1126), .A2(net_960), .A3(net_406) );
CLKBUF_X2 inst_5279 ( .A(net_5264), .Z(net_5265) );
SDFF_X2 inst_131 ( .D(net_3483), .SI(net_3025), .Q(net_3025), .SE(net_2919), .CK(net_4892) );
OAI221_X2 inst_406 ( .ZN(net_2553), .A(net_1728), .B1(net_1614), .C1(net_1613), .B2(net_327), .C2(net_192) );
CLKBUF_X2 inst_4579 ( .A(net_4337), .Z(net_4565) );
OAI22_X2 inst_328 ( .ZN(net_880), .B2(net_721), .A1(net_641), .A2(net_329), .B1(net_42) );
DFF_X2 inst_3111 ( .QN(net_2992), .D(net_2800), .CK(net_5244) );
NAND2_X2 inst_2035 ( .ZN(net_3773), .A2(net_1845), .A1(net_1806) );
XNOR2_X2 inst_47 ( .B(net_3175), .ZN(net_2688), .A(net_2372) );
CLKBUF_X2 inst_4217 ( .A(net_4202), .Z(net_4203) );
INV_X2 inst_2764 ( .ZN(net_2131), .A(net_952) );
OAI211_X2 inst_818 ( .A(net_3487), .ZN(net_1799), .B(net_935), .C1(net_433), .C2(net_287) );
CLKBUF_X2 inst_5231 ( .A(net_4986), .Z(net_5217) );
NAND2_X2 inst_1984 ( .A1(net_3782), .ZN(net_3408), .A2(net_1376) );
AND2_X4 inst_4101 ( .A1(net_4081), .ZN(net_1155), .A2(net_686) );
DFF_X2 inst_3178 ( .QN(net_3166), .D(net_1830), .CK(net_4677) );
DFF_X1 inst_3274 ( .QN(net_3101), .D(net_2921), .CK(net_5086) );
AND2_X2 inst_4203 ( .A2(net_3344), .ZN(net_3269), .A1(net_3268) );
CLKBUF_X2 inst_4792 ( .A(net_4664), .Z(net_4778) );
INV_X2 inst_2840 ( .A(net_3395), .ZN(net_400) );
OAI21_X2 inst_525 ( .B2(net_2967), .B1(net_2923), .ZN(net_2911), .A(net_2404) );
INV_X2 inst_2781 ( .ZN(net_805), .A(net_759) );
OAI221_X2 inst_434 ( .C2(net_3468), .A(net_629), .B1(net_628), .C1(net_627), .ZN(net_625), .B2(net_402) );
NOR2_X2 inst_1032 ( .ZN(net_1505), .A1(net_1440), .A2(net_1439) );
NOR3_X2 inst_906 ( .A2(net_3984), .ZN(net_684), .A1(net_658), .A3(net_528) );
CLKBUF_X2 inst_4276 ( .A(net_4261), .Z(net_4262) );
CLKBUF_X2 inst_5222 ( .A(net_5207), .Z(net_5208) );
CLKBUF_X2 inst_5098 ( .A(net_4886), .Z(net_5084) );
NAND4_X2 inst_1248 ( .ZN(net_3611), .A4(net_3610), .A3(net_3609), .A2(net_3608), .A1(net_3607) );
INV_X4 inst_2598 ( .ZN(net_3746), .A(net_2876) );
INV_X4 inst_2402 ( .ZN(net_655), .A(net_359) );
NAND2_X4 inst_1392 ( .A1(net_3187), .ZN(net_2106), .A2(net_165) );
INV_X4 inst_2616 ( .A(net_3896), .ZN(net_3868) );
AND4_X4 inst_4044 ( .ZN(net_4050), .A1(net_1375), .A3(net_1209), .A2(net_1187), .A4(net_1019) );
NAND2_X4 inst_1476 ( .ZN(net_3939), .A1(net_3167), .A2(net_3109) );
INV_X4 inst_2249 ( .A(net_1459), .ZN(net_1378) );
AOI21_X2 inst_3998 ( .B1(net_3620), .ZN(net_3598), .B2(net_1636), .A(net_441) );
CLKBUF_X2 inst_4300 ( .A(net_4243), .Z(net_4286) );
MUX2_X2 inst_2113 ( .B(net_3133), .A(net_2222), .S(net_1071), .Z(net_868) );
CLKBUF_X2 inst_5249 ( .A(net_5234), .Z(net_5235) );
NAND2_X2 inst_1820 ( .A1(net_4098), .ZN(net_860), .A2(net_594) );
INV_X4 inst_2269 ( .ZN(net_1691), .A(net_1021) );
NAND2_X2 inst_1780 ( .A2(net_4109), .A1(net_1202), .ZN(net_1065) );
INV_X4 inst_2390 ( .ZN(net_366), .A(net_365) );
NAND2_X4 inst_1436 ( .A2(net_3819), .ZN(net_3679), .A1(net_3667) );
OR3_X2 inst_183 ( .A3(net_3968), .A2(net_3621), .A1(net_1058), .ZN(net_858) );
OAI211_X2 inst_852 ( .ZN(net_3321), .C1(net_3318), .A(net_3246), .B(net_1299), .C2(net_359) );
AOI221_X2 inst_3871 ( .B2(net_3113), .B1(net_2020), .C1(net_2019), .ZN(net_1933), .A(net_1858), .C2(x142) );
CLKBUF_X2 inst_4306 ( .A(net_4291), .Z(net_4292) );
CLKBUF_X2 inst_4729 ( .A(net_4655), .Z(net_4715) );
CLKBUF_X2 inst_4449 ( .A(net_4434), .Z(net_4435) );
NAND2_X4 inst_1474 ( .A1(net_3944), .ZN(net_3928), .A2(net_392) );
INV_X4 inst_2271 ( .ZN(net_1257), .A(net_1203) );
NAND2_X2 inst_2045 ( .ZN(net_3854), .A2(net_3853), .A1(net_3850) );
NAND2_X2 inst_1920 ( .A2(net_3161), .ZN(net_269), .A1(net_84) );
AOI222_X1 inst_3779 ( .ZN(net_1796), .A1(net_1795), .B1(net_1794), .C1(net_1793), .A2(net_641), .C2(net_379), .B2(net_284) );
NAND2_X2 inst_1848 ( .A2(net_838), .ZN(net_699), .A1(net_535) );
CLKBUF_X2 inst_4451 ( .A(net_4436), .Z(net_4437) );
NAND3_X2 inst_1311 ( .A1(net_2596), .A3(net_1717), .ZN(net_1030), .A2(net_921) );
OAI21_X2 inst_697 ( .A(net_1011), .ZN(net_953), .B1(net_789), .B2(net_614) );
DFF_X1 inst_3415 ( .Q(net_4032), .D(net_1352), .CK(net_4703) );
OAI21_X2 inst_487 ( .B1(net_3394), .B2(net_2972), .ZN(net_2955), .A(net_2428) );
CLKBUF_X2 inst_5159 ( .A(net_5144), .Z(net_5145) );
CLKBUF_X2 inst_4654 ( .A(net_4639), .Z(net_4640) );
NAND2_X2 inst_1640 ( .A1(net_4148), .ZN(net_3212), .A2(net_2105) );
AND2_X4 inst_4143 ( .ZN(net_4079), .A2(net_923), .A1(net_723) );
DFF_X1 inst_3234 ( .QN(net_3062), .D(net_2962), .CK(net_4872) );
CLKBUF_X2 inst_4747 ( .A(net_4438), .Z(net_4733) );
INV_X2 inst_2639 ( .ZN(net_2381), .A(net_2380) );
INV_X8 inst_2133 ( .A(net_3167), .ZN(net_268) );
CLKBUF_X2 inst_4630 ( .A(net_4615), .Z(net_4616) );
INV_X8 inst_2163 ( .ZN(net_3664), .A(net_3663) );
INV_X4 inst_2509 ( .ZN(net_619), .A(net_270) );
INV_X4 inst_2542 ( .ZN(net_3416), .A(net_2718) );
HA_X1 inst_3091 ( .S(net_1571), .CO(net_1570), .A(net_1342), .B(net_238) );
AND2_X2 inst_4197 ( .ZN(net_1601), .A1(net_1600), .A2(net_1514) );
CLKBUF_X2 inst_4668 ( .A(net_4653), .Z(net_4654) );
OAI221_X2 inst_417 ( .B1(net_3982), .ZN(net_1296), .C1(net_1295), .A(net_1098), .B2(net_717), .C2(net_259) );
NAND2_X2 inst_1861 ( .A1(net_3900), .A2(net_3441), .ZN(net_716) );
OAI21_X2 inst_671 ( .ZN(net_1593), .B1(net_1388), .A(net_1279), .B2(net_1103) );
XOR2_X2 inst_21 ( .Z(net_4071), .A(net_815), .B(net_617) );
AOI22_X2 inst_3570 ( .A1(net_4060), .B1(net_4055), .B2(net_3029), .A2(net_3028), .ZN(net_1480) );
CLKBUF_X2 inst_4524 ( .A(net_4361), .Z(net_4510) );
CLKBUF_X2 inst_4871 ( .A(net_4335), .Z(net_4857) );
CLKBUF_X2 inst_4835 ( .A(net_4601), .Z(net_4821) );
NAND2_X2 inst_2004 ( .A1(net_3550), .ZN(net_3527), .A2(net_3490) );
CLKBUF_X2 inst_4586 ( .A(net_4571), .Z(net_4572) );
CLKBUF_X2 inst_4257 ( .A(net_4242), .Z(net_4243) );
INV_X4 inst_2311 ( .A(net_1129), .ZN(net_790) );
AOI221_X2 inst_3885 ( .ZN(net_1658), .C1(net_1657), .C2(net_1656), .A(net_1251), .B1(net_1205), .B2(net_984) );
INV_X2 inst_2857 ( .A(net_4007), .ZN(net_377) );
OR2_X4 inst_220 ( .A1(net_4081), .ZN(net_1081), .A2(net_686) );
NAND2_X2 inst_1585 ( .A1(net_2915), .ZN(net_2435), .A2(net_163) );
NAND3_X2 inst_1317 ( .A3(net_3662), .A1(net_3523), .ZN(net_955), .A2(net_403) );
AOI22_X2 inst_3683 ( .B1(net_4123), .ZN(net_500), .A1(net_458), .B2(net_193), .A2(net_169) );
INV_X2 inst_2941 ( .A(net_3149), .ZN(net_282) );
OR2_X4 inst_245 ( .ZN(net_4133), .A1(net_3959), .A2(net_3952) );
NAND2_X2 inst_1873 ( .A2(net_4003), .ZN(net_658), .A1(net_517) );
AND2_X4 inst_4111 ( .A1(net_3654), .ZN(net_3243), .A2(net_283) );
OAI21_X2 inst_624 ( .B1(net_2235), .ZN(net_2157), .A(net_2045), .B2(net_106) );
SDFF_X2 inst_147 ( .D(net_3884), .SE(net_2625), .SI(net_93), .Q(net_93), .CK(net_4944) );
OAI22_X2 inst_313 ( .ZN(net_1164), .B1(net_641), .A1(net_533), .B2(net_529), .A2(net_523) );
NAND2_X2 inst_1676 ( .A1(net_2134), .ZN(net_2081), .A2(net_568) );
AND2_X4 inst_4170 ( .ZN(net_4124), .A2(net_3163), .A1(net_338) );
NOR2_X2 inst_1041 ( .A1(net_3964), .ZN(net_1328), .A2(net_1173) );
CLKBUF_X2 inst_5263 ( .A(net_5120), .Z(net_5249) );
NAND2_X1 inst_2086 ( .A2(net_4009), .A1(net_2972), .ZN(net_2433) );
DFF_X2 inst_3114 ( .D(net_2817), .QN(net_118), .CK(net_4597) );
AOI22_X2 inst_3577 ( .A1(net_4059), .B1(net_4056), .ZN(net_1473), .A2(net_195), .B2(net_194) );
INV_X2 inst_2637 ( .A(net_3693), .ZN(net_2511) );
AOI22_X2 inst_3624 ( .B2(net_3627), .ZN(net_1109), .A2(net_1011), .B1(net_948), .A1(net_888) );
OR2_X4 inst_236 ( .ZN(net_3208), .A1(net_3206), .A2(net_2352) );
CLKBUF_X2 inst_4539 ( .A(net_4524), .Z(net_4525) );
CLKBUF_X2 inst_4754 ( .A(net_4739), .Z(net_4740) );
OAI21_X2 inst_553 ( .B2(net_2925), .ZN(net_2873), .B1(net_2871), .A(net_2423) );
AOI221_X2 inst_3878 ( .B1(net_2020), .C1(net_2019), .ZN(net_1855), .A(net_1854), .B2(net_272), .C2(x409) );
DFF_X1 inst_3331 ( .D(net_2818), .QN(net_331), .CK(net_4323) );
CLKBUF_X2 inst_4532 ( .A(net_4517), .Z(net_4518) );
OR2_X4 inst_242 ( .ZN(net_3781), .A1(net_2212), .A2(net_1521) );
NOR2_X2 inst_986 ( .A1(net_3813), .ZN(net_2530), .A2(net_2529) );
DFF_X2 inst_3172 ( .D(net_1885), .QN(net_270), .CK(net_4849) );
CLKBUF_X2 inst_4983 ( .A(net_4422), .Z(net_4969) );
CLKBUF_X2 inst_4680 ( .A(net_4665), .Z(net_4666) );
NAND2_X4 inst_1422 ( .A2(net_3600), .ZN(net_3579), .A1(net_3238) );
AOI22_X2 inst_3508 ( .B1(net_3676), .B2(net_3136), .A1(net_2012), .ZN(net_2009), .A2(net_1797) );
CLKBUF_X2 inst_5132 ( .A(net_5117), .Z(net_5118) );
NAND4_X2 inst_1186 ( .ZN(net_1911), .A2(net_1757), .A1(net_1725), .A3(net_1721), .A4(net_1056) );
NAND2_X2 inst_1753 ( .ZN(net_1724), .A2(net_1300), .A1(net_1181) );
NAND2_X2 inst_1727 ( .ZN(net_1566), .A1(net_1565), .A2(net_1454) );
NAND4_X2 inst_1221 ( .ZN(net_952), .A4(net_736), .A3(net_569), .A2(net_489), .A1(net_476) );
NOR2_X1 inst_1166 ( .A1(net_2127), .ZN(net_1190), .A2(net_1189) );
NAND2_X2 inst_1739 ( .A2(net_3751), .ZN(net_1559), .A1(net_1437) );
XNOR2_X2 inst_116 ( .A(net_3875), .B(net_3858), .ZN(net_3224) );
NOR2_X2 inst_1133 ( .ZN(net_3656), .A1(net_3655), .A2(net_3477) );
OAI21_X2 inst_471 ( .B1(net_3509), .ZN(net_2979), .B2(net_2967), .A(net_2409) );
AND3_X2 inst_4087 ( .A2(net_4087), .ZN(net_1012), .A3(net_1011), .A1(net_145) );
CLKBUF_X2 inst_4580 ( .A(net_4565), .Z(net_4566) );
MUX2_X2 inst_2103 ( .S(net_2925), .Z(net_2575), .A(net_2573), .B(net_175) );
CLKBUF_X2 inst_4956 ( .A(net_4941), .Z(net_4942) );
AOI22_X2 inst_3609 ( .A1(net_4063), .B1(net_4058), .ZN(net_1408), .A2(net_597), .B2(net_596) );
CLKBUF_X2 inst_5139 ( .A(net_5124), .Z(net_5125) );
NOR3_X2 inst_896 ( .A2(net_3982), .A1(net_3781), .ZN(net_1702), .A3(net_56) );
CLKBUF_X2 inst_4750 ( .A(net_4735), .Z(net_4736) );
OAI22_X2 inst_339 ( .B1(net_3871), .A1(net_3556), .ZN(net_3217), .A2(net_2995), .B2(net_2994) );
INV_X2 inst_2664 ( .ZN(net_2351), .A(net_2099) );
OAI222_X2 inst_351 ( .C1(net_3784), .B2(net_3152), .A2(net_2189), .ZN(net_1934), .A1(net_1815), .B1(net_1814), .C2(net_119) );
INV_X4 inst_2608 ( .A(net_3817), .ZN(net_3816) );
INV_X4 inst_2557 ( .ZN(net_3497), .A(net_3494) );
INV_X4 inst_2521 ( .A(net_3370), .ZN(net_3252) );
OAI221_X2 inst_385 ( .B2(net_2699), .C2(net_2698), .ZN(net_2627), .B1(net_2626), .A(net_2532), .C1(net_2324) );
DFF_X1 inst_3319 ( .QN(net_3002), .D(net_2843), .CK(net_5071) );
INV_X2 inst_2653 ( .A(net_3827), .ZN(net_2630) );
CLKBUF_X2 inst_4621 ( .A(net_4606), .Z(net_4607) );
INV_X4 inst_2550 ( .ZN(net_3455), .A(net_2986) );
NAND2_X2 inst_1560 ( .A1(net_2912), .ZN(net_2462), .A2(net_227) );
AOI21_X2 inst_3932 ( .A(net_3465), .B2(net_3115), .ZN(net_2864), .B1(net_2822) );
CLKBUF_X2 inst_4281 ( .A(net_4266), .Z(net_4267) );
OAI21_X2 inst_596 ( .ZN(net_2624), .B1(net_2531), .A(net_1600), .B2(net_1443) );
INV_X2 inst_2771 ( .A(net_955), .ZN(net_883) );
CLKBUF_X2 inst_4687 ( .A(net_4287), .Z(net_4673) );
INV_X8 inst_2142 ( .A(net_3780), .ZN(net_3186) );
NAND2_X2 inst_1705 ( .ZN(net_1759), .A1(net_1758), .A2(net_53) );
CLKBUF_X2 inst_5110 ( .A(net_4702), .Z(net_5096) );
CLKBUF_X2 inst_4664 ( .A(net_4489), .Z(net_4650) );
OAI211_X2 inst_847 ( .C1(net_1274), .C2(net_988), .B(net_891), .ZN(net_704), .A(net_615) );
INV_X2 inst_2720 ( .ZN(net_1513), .A(net_1512) );
CLKBUF_X2 inst_5003 ( .A(net_4399), .Z(net_4989) );
CLKBUF_X2 inst_4458 ( .A(net_4443), .Z(net_4444) );
NAND2_X2 inst_1942 ( .ZN(net_3235), .A1(net_3187), .A2(net_221) );
NAND2_X2 inst_1716 ( .A1(net_3492), .A2(net_3364), .ZN(net_1690) );
DFF_X1 inst_3253 ( .QN(net_3088), .D(net_2944), .CK(net_4727) );
INV_X2 inst_2648 ( .A(net_3884), .ZN(net_2626) );
CLKBUF_X2 inst_5184 ( .A(net_5169), .Z(net_5170) );
CLKBUF_X2 inst_4596 ( .A(net_4573), .Z(net_4582) );
NOR2_X2 inst_1146 ( .ZN(net_3913), .A1(net_3489), .A2(net_3488) );
OAI21_X2 inst_637 ( .B2(net_2076), .ZN(net_2073), .A(net_1964), .B1(net_1677) );
AOI22_X2 inst_3708 ( .B1(net_4124), .A1(net_509), .ZN(net_456), .B2(net_236), .A2(net_151) );
OAI21_X2 inst_547 ( .B2(net_2912), .B1(net_2887), .ZN(net_2884), .A(net_2452) );
AOI211_X2 inst_4023 ( .ZN(net_1298), .B(net_1106), .C2(net_1094), .C1(net_840), .A(net_811) );
DFF_X2 inst_3105 ( .D(net_2827), .QN(net_245), .CK(net_4330) );
AOI22_X2 inst_3673 ( .ZN(net_548), .A1(net_458), .B1(net_457), .B2(net_221), .A2(net_155) );
AOI222_X1 inst_3781 ( .C1(net_4065), .B2(net_3789), .ZN(net_1725), .B1(net_1724), .A2(net_1581), .A1(net_1180), .C2(net_1113) );
CLKBUF_X2 inst_5162 ( .A(net_5147), .Z(net_5148) );
CLKBUF_X2 inst_4519 ( .A(net_4367), .Z(net_4505) );
AOI22_X2 inst_3539 ( .B1(net_1840), .A1(net_1698), .ZN(net_1669), .B2(net_179), .A2(net_77) );
INV_X4 inst_2457 ( .A(net_3078), .ZN(net_467) );
AOI22_X2 inst_3552 ( .A1(net_4060), .B1(net_4055), .ZN(net_1498), .A2(net_186), .B2(net_162) );
NAND2_X2 inst_1702 ( .ZN(net_1786), .A2(net_1785), .A1(net_1688) );
OAI33_X1 inst_274 ( .A1(net_1701), .B2(net_1606), .ZN(net_1556), .B1(net_1232), .B3(net_1173), .A3(net_444), .A2(net_143) );
NAND2_X2 inst_1607 ( .A1(net_2967), .ZN(net_2409), .A2(net_475) );
NAND3_X2 inst_1277 ( .ZN(net_2703), .A3(net_2691), .A1(net_2647), .A2(net_2593) );
INV_X2 inst_2817 ( .A(net_714), .ZN(net_604) );
AND3_X4 inst_4076 ( .ZN(net_4090), .A2(net_3959), .A3(net_3948), .A1(net_710) );
NAND2_X1 inst_2092 ( .A2(net_3968), .ZN(net_540), .A1(net_356) );
CLKBUF_X2 inst_4762 ( .A(net_4245), .Z(net_4748) );
OR3_X4 inst_164 ( .A2(net_2596), .ZN(net_2215), .A1(net_2214), .A3(net_2213) );
DFF_X2 inst_3207 ( .Q(net_3158), .D(net_1166), .CK(net_4824) );
DFF_X2 inst_3143 ( .QN(net_3103), .D(net_2542), .CK(net_4633) );
NAND2_X2 inst_1854 ( .A1(net_3243), .ZN(net_652), .A2(net_418) );
INV_X2 inst_2696 ( .ZN(net_1688), .A(net_1687) );
NAND2_X2 inst_1710 ( .A2(net_1772), .ZN(net_1734), .A1(net_1703) );
INV_X4 inst_2407 ( .ZN(net_528), .A(net_357) );
NAND2_X2 inst_1771 ( .ZN(net_1277), .A1(net_1158), .A2(net_973) );
INV_X2 inst_2880 ( .A(net_344), .ZN(net_263) );
CLKBUF_X2 inst_4884 ( .A(net_4869), .Z(net_4870) );
NAND2_X4 inst_1440 ( .ZN(net_3720), .A1(net_3678), .A2(net_3540) );
INV_X2 inst_2660 ( .ZN(net_2109), .A(net_2038) );
DFF_X2 inst_3142 ( .QN(net_2983), .D(net_2572), .CK(net_5228) );
INV_X4 inst_2305 ( .A(net_3924), .ZN(net_848) );
DFF_X1 inst_3355 ( .D(net_3695), .CK(net_4257), .Q(x142) );
OAI21_X2 inst_753 ( .ZN(net_3536), .B1(net_3533), .B2(net_3516), .A(net_3458) );
INV_X8 inst_2150 ( .ZN(net_3302), .A(net_3301) );
INV_X4 inst_2389 ( .A(net_826), .ZN(net_775) );
DFF_X1 inst_3427 ( .Q(net_4015), .D(net_4014), .CK(net_4910) );
NOR2_X4 inst_946 ( .ZN(net_3526), .A2(net_3168), .A1(net_268) );
NAND2_X2 inst_1954 ( .ZN(net_3285), .A1(net_3284), .A2(net_3182) );
INV_X4 inst_2260 ( .ZN(net_2141), .A(net_1172) );
CLKBUF_X2 inst_4946 ( .A(net_4643), .Z(net_4932) );
INV_X8 inst_2148 ( .A(net_3800), .ZN(net_3281) );
AOI21_X2 inst_3941 ( .ZN(net_2242), .B1(net_2238), .A(net_2188), .B2(net_1874) );
INV_X2 inst_2900 ( .A(net_3116), .ZN(net_1532) );
NAND2_X2 inst_1591 ( .A1(net_2972), .ZN(net_2427), .A2(net_834) );
DFF_X1 inst_3247 ( .QN(net_3091), .D(net_2948), .CK(net_4550) );
AOI22_X2 inst_3697 ( .B1(net_4124), .A1(net_509), .ZN(net_477), .A2(net_214), .B2(net_202) );
AOI221_X2 inst_3858 ( .B1(net_3736), .A(net_3362), .C2(net_3117), .C1(net_2115), .ZN(net_2046), .B2(net_239) );
OAI221_X2 inst_379 ( .B1(net_2670), .C1(net_2668), .ZN(net_2662), .B2(net_2661), .A(net_1386), .C2(net_331) );
CLKBUF_X2 inst_4625 ( .A(net_4610), .Z(net_4611) );
NOR2_X4 inst_926 ( .A2(net_3831), .A1(net_3266), .ZN(net_2210) );
AOI21_X4 inst_3922 ( .B2(net_3600), .ZN(net_2887), .B1(net_2878), .A(net_2124) );
NAND2_X2 inst_2053 ( .ZN(net_3895), .A2(net_3892), .A1(net_3347) );
NAND3_X2 inst_1325 ( .A2(net_3913), .ZN(net_1016), .A3(net_838), .A1(net_666) );
INV_X4 inst_2570 ( .ZN(net_3544), .A(net_3543) );
AND2_X4 inst_4153 ( .ZN(net_4102), .A2(net_3662), .A1(net_440) );
CLKBUF_X2 inst_4960 ( .A(net_4363), .Z(net_4946) );
CLKBUF_X2 inst_5105 ( .A(net_5090), .Z(net_5091) );
DFF_X1 inst_3312 ( .Q(net_3140), .D(net_2854), .CK(net_4519) );
AOI22_X2 inst_3646 ( .A1(net_4142), .B1(net_4112), .B2(net_2033), .ZN(net_756), .A2(x916) );
AOI22_X2 inst_3719 ( .A1(net_3815), .ZN(net_3607), .B1(net_3186), .A2(net_732), .B2(net_731) );
NOR3_X2 inst_891 ( .A3(net_3158), .ZN(net_2386), .A2(net_2384), .A1(net_2327) );
AND2_X4 inst_4095 ( .ZN(net_1741), .A1(net_1740), .A2(net_1705) );
XNOR2_X2 inst_74 ( .ZN(net_1462), .B(net_1461), .A(net_1329) );
NAND4_X2 inst_1235 ( .A2(net_3900), .A3(net_3243), .A4(net_721), .ZN(net_685), .A1(net_376) );
INV_X4 inst_2244 ( .A(net_1816), .ZN(net_1793) );
AOI22_X2 inst_3561 ( .B1(net_4062), .A1(net_4056), .ZN(net_1489), .A2(net_214), .B2(net_141) );
OAI22_X2 inst_288 ( .B1(net_1891), .ZN(net_1881), .A1(net_1880), .B2(net_508), .A2(net_276) );
DFF_X1 inst_3284 ( .QN(net_3052), .D(net_2896), .CK(net_4777) );
INV_X2 inst_3046 ( .ZN(net_3708), .A(net_1855) );
AOI22_X2 inst_3626 ( .A1(net_4115), .B1(net_1882), .ZN(net_940), .A2(net_773), .B2(net_210) );
AND4_X4 inst_4036 ( .ZN(net_2145), .A4(net_2144), .A1(net_2120), .A2(net_1867), .A3(net_1866) );
CLKBUF_X2 inst_4644 ( .A(net_4415), .Z(net_4630) );
CLKBUF_X2 inst_5244 ( .A(net_5229), .Z(net_5230) );
CLKBUF_X2 inst_4844 ( .A(net_4829), .Z(net_4830) );
CLKBUF_X2 inst_4512 ( .A(net_4497), .Z(net_4498) );
NAND3_X2 inst_1298 ( .A2(net_1636), .ZN(net_1563), .A1(net_1562), .A3(net_593) );
AOI222_X1 inst_3757 ( .A1(net_3676), .B1(net_2055), .C1(net_2054), .ZN(net_2035), .C2(net_425), .B2(net_379), .A2(net_295) );
NOR3_X2 inst_917 ( .ZN(net_4045), .A3(net_3447), .A1(net_1790), .A2(net_1772) );
AOI22_X2 inst_3712 ( .ZN(net_3205), .A1(net_3198), .A2(net_3023), .B2(net_3022), .B1(net_1982) );
NAND2_X2 inst_1743 ( .ZN(net_1503), .A1(net_1309), .A2(net_271) );
OAI221_X2 inst_372 ( .ZN(net_2685), .B2(net_2684), .B1(net_2670), .C1(net_2668), .A(net_1386), .C2(net_292) );
NAND2_X2 inst_1600 ( .A1(net_2969), .ZN(net_2417), .A2(net_488) );
CLKBUF_X2 inst_5022 ( .A(net_5007), .Z(net_5008) );
OR2_X4 inst_215 ( .A1(net_1445), .ZN(net_1374), .A2(net_300) );
INV_X2 inst_2850 ( .A(net_3526), .ZN(net_373) );
CLKBUF_X2 inst_5163 ( .A(net_5148), .Z(net_5149) );
INV_X4 inst_2624 ( .ZN(net_3968), .A(net_3967) );
OAI211_X2 inst_849 ( .B(net_3243), .ZN(net_719), .C1(net_666), .A(net_517), .C2(net_418) );
NAND2_X2 inst_1775 ( .A1(net_2213), .ZN(net_1359), .A2(net_1107) );
INV_X4 inst_2397 ( .A(net_3391), .ZN(net_1636) );
XOR2_X2 inst_3 ( .B(net_3255), .Z(net_1996), .A(net_1713) );
NOR2_X1 inst_1172 ( .ZN(net_4141), .A1(net_4081), .A2(net_1381) );
NOR2_X2 inst_1090 ( .A1(net_3391), .ZN(net_586), .A2(x974) );
INV_X2 inst_3060 ( .ZN(net_4172), .A(net_1994) );
AOI221_X2 inst_3903 ( .A(net_4078), .ZN(net_1112), .B2(net_990), .B1(net_911), .C1(net_892), .C2(net_361) );
INV_X4 inst_2372 ( .A(net_3900), .ZN(net_526) );
INV_X4 inst_2575 ( .ZN(net_3585), .A(net_3583) );
CLKBUF_X2 inst_5007 ( .A(net_4992), .Z(net_4993) );
OAI21_X2 inst_566 ( .B2(net_2912), .B1(net_2849), .ZN(net_2846), .A(net_2453) );
NAND2_X4 inst_1399 ( .ZN(net_796), .A2(net_672), .A1(net_665) );
NAND4_X2 inst_1239 ( .A1(net_3448), .ZN(net_3230), .A2(net_2597), .A4(net_2596), .A3(net_1295) );
CLKBUF_X2 inst_4357 ( .A(net_4342), .Z(net_4343) );
CLKBUF_X2 inst_4819 ( .A(net_4804), .Z(net_4805) );
DFF_X2 inst_3126 ( .QN(net_3142), .D(net_2687), .CK(net_4573) );
CLKBUF_X2 inst_4327 ( .A(net_4312), .Z(net_4313) );
OAI21_X2 inst_503 ( .B1(net_3394), .B2(net_3208), .ZN(net_2939), .A(net_2491) );
CLKBUF_X2 inst_4774 ( .A(net_4759), .Z(net_4760) );
INV_X4 inst_2333 ( .A(net_1071), .ZN(net_1036) );
NAND2_X2 inst_1936 ( .ZN(net_3203), .A1(net_3198), .A2(net_203) );
DFF_X2 inst_3193 ( .Q(net_3759), .D(net_3758), .QN(net_3168), .CK(net_5272) );
CLKBUF_X2 inst_5088 ( .A(net_5073), .Z(net_5074) );
AND2_X2 inst_4193 ( .A1(net_3448), .ZN(net_2710), .A2(net_1052) );
NAND2_X1 inst_2099 ( .ZN(net_3692), .A1(net_3688), .A2(net_2691) );
AND3_X4 inst_4069 ( .A1(net_4077), .ZN(net_1142), .A2(net_965), .A3(net_850) );
CLKBUF_X2 inst_5056 ( .A(net_5041), .Z(net_5042) );
NOR2_X2 inst_1097 ( .A1(net_3167), .A2(net_3109), .ZN(net_304) );
OAI21_X2 inst_686 ( .B1(net_3228), .B2(net_2037), .ZN(net_1308), .A(net_1259) );
AOI211_X2 inst_4016 ( .C1(net_4065), .ZN(net_1820), .B(net_1724), .C2(net_1663), .A(net_1043) );
CLKBUF_X2 inst_4892 ( .A(net_4877), .Z(net_4878) );
NAND2_X2 inst_1732 ( .A1(net_1556), .ZN(net_1553), .A2(x717) );
INV_X2 inst_2914 ( .A(net_3036), .ZN(net_172) );
INV_X2 inst_2888 ( .A(net_3044), .ZN(net_234) );
DFF_X1 inst_3294 ( .QN(net_3010), .D(net_2881), .CK(net_5121) );
INV_X2 inst_2741 ( .A(net_3966), .ZN(net_1267) );
AOI22_X2 inst_3643 ( .A1(net_4142), .B1(net_4112), .B2(net_1797), .ZN(net_759), .A2(x762) );
NOR2_X4 inst_967 ( .ZN(net_3857), .A2(net_3856), .A1(net_3855) );
INV_X8 inst_2119 ( .A(net_3556), .ZN(net_2134) );
NAND2_X2 inst_1929 ( .ZN(net_3192), .A1(net_3186), .A2(net_734) );
NAND2_X2 inst_1522 ( .A1(net_2959), .ZN(net_2500), .A2(net_737) );
DFF_X1 inst_3391 ( .D(net_1716), .QN(net_78), .CK(net_4246) );
NAND2_X2 inst_1794 ( .A1(net_1013), .ZN(net_1005), .A2(net_521) );
NAND4_X2 inst_1227 ( .ZN(net_800), .A4(net_634), .A3(net_566), .A2(net_483), .A1(net_466) );
INV_X4 inst_2324 ( .A(net_1024), .ZN(net_709) );
INV_X16 inst_3069 ( .A(net_4000), .ZN(net_3900) );
AOI22_X2 inst_3631 ( .ZN(net_879), .A2(net_458), .B2(net_457), .B1(net_190), .A1(net_161) );
NOR2_X2 inst_1101 ( .A2(net_3154), .A1(net_3108), .ZN(net_275) );
INV_X2 inst_3047 ( .ZN(net_3729), .A(net_3728) );
INV_X2 inst_2950 ( .A(net_3039), .ZN(net_205) );
AOI221_X2 inst_3847 ( .B1(net_3736), .ZN(net_2138), .C1(net_2137), .A(net_1941), .B2(net_330), .C2(net_216) );
INV_X2 inst_2897 ( .A(net_3008), .ZN(net_202) );
NOR4_X2 inst_861 ( .A1(net_1718), .ZN(net_1659), .A2(net_1657), .A3(net_1522), .A4(net_1149) );
INV_X4 inst_2529 ( .A(net_3283), .ZN(net_3280) );
NAND2_X2 inst_1787 ( .A1(net_3963), .A2(net_1837), .ZN(net_1031) );
INV_X2 inst_2990 ( .A(net_3152), .ZN(net_378) );
NAND3_X2 inst_1283 ( .ZN(net_2733), .A2(net_2377), .A1(net_2375), .A3(net_2374) );
INV_X4 inst_2451 ( .ZN(net_1874), .A(net_118) );
NAND4_X2 inst_1202 ( .ZN(net_2196), .A3(net_1473), .A4(net_1472), .A1(net_1407), .A2(net_1406) );
CLKBUF_X2 inst_4290 ( .A(net_4275), .Z(net_4276) );
NAND2_X2 inst_1540 ( .A1(net_2907), .ZN(net_2482), .A2(net_234) );
INV_X4 inst_2227 ( .ZN(net_2684), .A(net_2583) );
NAND2_X2 inst_1660 ( .ZN(net_2103), .A1(net_1982), .A2(net_193) );
INV_X2 inst_2742 ( .ZN(net_1227), .A(net_1226) );
AOI22_X2 inst_3536 ( .A2(net_1908), .ZN(net_1768), .A1(net_1767), .B2(net_749), .B1(net_96) );
OAI21_X2 inst_660 ( .ZN(net_2583), .B2(net_1975), .B1(net_1765), .A(net_1452) );
CLKBUF_X2 inst_5243 ( .A(net_4364), .Z(net_5229) );
CLKBUF_X2 inst_4375 ( .A(net_4238), .Z(net_4361) );
INV_X4 inst_2490 ( .A(net_3074), .ZN(net_558) );
OAI21_X2 inst_517 ( .B2(net_2959), .ZN(net_2924), .B1(net_2923), .A(net_2497) );
CLKBUF_X2 inst_5195 ( .A(net_4696), .Z(net_5181) );
NAND2_X2 inst_1576 ( .A1(net_2965), .ZN(net_2444), .A2(net_244) );
INV_X4 inst_2346 ( .ZN(net_722), .A(net_603) );
NAND4_X1 inst_1261 ( .ZN(net_4187), .A4(net_3530), .A2(net_3513), .A3(net_2679), .A1(net_2541) );
AOI22_X4 inst_3462 ( .ZN(net_3264), .A1(net_3263), .B1(net_1445), .A2(net_1374), .B2(net_300) );
CLKBUF_X2 inst_4254 ( .A(x1012), .Z(net_4240) );
CLKBUF_X2 inst_4330 ( .A(net_4315), .Z(net_4316) );
OAI22_X2 inst_310 ( .B1(net_3132), .ZN(net_1242), .A1(net_1099), .A2(net_1071), .B2(net_1036) );
CLKBUF_X2 inst_4368 ( .A(net_4353), .Z(net_4354) );
OAI211_X2 inst_794 ( .ZN(net_2636), .C1(net_2549), .A(net_2548), .C2(net_2547), .B(net_1740) );
INV_X2 inst_2754 ( .A(net_1183), .ZN(net_1004) );
NOR2_X2 inst_1005 ( .A2(net_3505), .ZN(net_1969), .A1(net_1833) );
INV_X2 inst_2759 ( .A(net_1137), .ZN(net_982) );
NOR2_X2 inst_1147 ( .ZN(net_3916), .A2(net_3914), .A1(net_525) );
NAND2_X2 inst_1768 ( .A1(net_4185), .ZN(net_1225), .A2(net_1011) );
NAND2_X2 inst_1580 ( .A1(net_2965), .ZN(net_2440), .A2(net_232) );
NAND2_X2 inst_1842 ( .ZN(net_844), .A2(net_775), .A1(net_435) );
INV_X2 inst_2688 ( .ZN(net_1756), .A(net_1722) );
INV_X2 inst_2917 ( .ZN(net_2307), .A(net_71) );
INV_X4 inst_2423 ( .ZN(net_347), .A(net_225) );
NAND2_X4 inst_1408 ( .A2(net_4135), .ZN(net_3301), .A1(net_3300) );
NOR2_X2 inst_996 ( .A1(net_2732), .ZN(net_2311), .A2(net_1905) );
INV_X4 inst_2351 ( .ZN(net_2525), .A(net_593) );
CLKBUF_X2 inst_5125 ( .A(net_5110), .Z(net_5111) );
NAND2_X2 inst_1853 ( .ZN(net_660), .A2(net_659), .A1(net_589) );
NAND2_X2 inst_1889 ( .A1(net_1636), .ZN(net_511), .A2(x974) );
NAND2_X2 inst_1527 ( .A1(net_3208), .ZN(net_2495), .A2(net_171) );
NAND2_X2 inst_2011 ( .ZN(net_3584), .A2(net_3583), .A1(net_2382) );
NAND2_X2 inst_1761 ( .A1(net_4031), .A2(net_1394), .ZN(net_1238) );
OAI21_X2 inst_740 ( .B1(net_3588), .ZN(net_3267), .B2(net_3208), .A(net_2490) );
OR2_X2 inst_264 ( .A1(net_4132), .A2(net_402), .ZN(net_395) );
AOI22_X2 inst_3703 ( .ZN(net_465), .A1(net_458), .B1(net_457), .B2(net_197), .A2(net_175) );
AND2_X4 inst_4189 ( .ZN(net_4186), .A2(net_591), .A1(net_583) );
XNOR2_X2 inst_84 ( .ZN(net_1222), .B(net_987), .A(net_875) );
NAND3_X2 inst_1333 ( .A3(net_3662), .A2(net_3613), .ZN(net_531), .A1(net_424) );
NAND2_X2 inst_1937 ( .A1(net_3769), .ZN(net_3214), .A2(net_368) );
OR3_X4 inst_173 ( .A1(net_4113), .A3(net_3387), .ZN(net_814), .A2(net_632) );
AOI22_X2 inst_3710 ( .B1(net_4123), .A1(net_571), .ZN(net_443), .B2(net_177), .A2(net_153) );
CLKBUF_X2 inst_4405 ( .A(net_4220), .Z(net_4391) );
OAI21_X2 inst_611 ( .ZN(net_2354), .A(net_2299), .B1(net_2298), .B2(net_2181) );
AOI21_X2 inst_3953 ( .ZN(net_1753), .A(net_1702), .B1(net_1651), .B2(net_231) );
INV_X4 inst_2487 ( .A(net_3013), .ZN(net_155) );
NAND2_X2 inst_1551 ( .A1(net_2961), .ZN(net_2471), .A2(net_467) );
NAND4_X1 inst_1260 ( .ZN(net_506), .A4(net_505), .A1(net_327), .A2(net_289), .A3(net_260) );
NOR2_X2 inst_1088 ( .A1(net_4127), .ZN(net_449), .A2(net_42) );
NAND2_X2 inst_1943 ( .A1(net_4182), .ZN(net_3245), .A2(net_3244) );
OAI21_X2 inst_490 ( .B1(net_3588), .B2(net_2969), .ZN(net_2952), .A(net_2413) );
DFF_X1 inst_3332 ( .Q(net_3151), .D(net_2821), .CK(net_4366) );
CLKBUF_X2 inst_4898 ( .A(net_4883), .Z(net_4884) );
INV_X2 inst_2717 ( .A(net_3515), .ZN(net_2323) );
INV_X4 inst_2218 ( .A(net_3556), .ZN(net_2082) );
AND2_X4 inst_4176 ( .ZN(net_4130), .A2(net_3388), .A1(net_3127) );
SDFF_X2 inst_129 ( .D(net_3483), .SI(net_3028), .Q(net_3028), .SE(net_2907), .CK(net_5061) );
NAND3_X2 inst_1309 ( .A1(net_4069), .ZN(net_1114), .A2(net_409), .A3(net_207) );
INV_X2 inst_2740 ( .ZN(net_1270), .A(net_1218) );
NAND2_X2 inst_1754 ( .ZN(net_1294), .A2(net_1293), .A1(net_1172) );
NAND2_X2 inst_1531 ( .A1(net_3208), .ZN(net_2491), .A2(net_551) );
INV_X2 inst_2931 ( .A(net_3000), .ZN(net_236) );
CLKBUF_X2 inst_4768 ( .A(net_4753), .Z(net_4754) );
CLKBUF_X2 inst_4938 ( .A(net_4322), .Z(net_4924) );
INV_X4 inst_2530 ( .ZN(net_3283), .A(net_3281) );
INV_X2 inst_2727 ( .ZN(net_1451), .A(net_1450) );
INV_X2 inst_2922 ( .A(net_3159), .ZN(net_220) );
AOI221_X2 inst_3803 ( .C1(net_2781), .B1(net_2775), .ZN(net_2772), .A(net_2671), .B2(net_318), .C2(net_77) );
DFF_X2 inst_3183 ( .D(net_1749), .QN(net_106), .CK(net_4528) );
NAND2_X2 inst_1503 ( .ZN(net_2794), .A1(net_2730), .A2(net_2695) );
OAI21_X1 inst_777 ( .A(net_3858), .B2(net_3827), .B1(net_3405), .ZN(net_3329) );
CLKBUF_X2 inst_4312 ( .A(net_4297), .Z(net_4298) );
AOI221_X2 inst_3802 ( .C1(net_2781), .B1(net_2775), .ZN(net_2773), .A(net_2662), .B2(net_331), .C2(net_255) );
CLKBUF_X2 inst_5016 ( .A(net_5001), .Z(net_5002) );
NOR2_X2 inst_1037 ( .ZN(net_1284), .A1(net_1283), .A2(net_586) );
NOR2_X4 inst_933 ( .A2(net_3641), .A1(net_3576), .ZN(net_1272) );
OAI22_X2 inst_300 ( .ZN(net_1546), .B2(net_1545), .A1(net_1543), .B1(net_1542), .A2(net_318) );
AOI22_X2 inst_3596 ( .A1(net_4062), .B1(net_4057), .ZN(net_1421), .A2(net_519), .B2(net_478) );
AOI22_X2 inst_3724 ( .ZN(net_3651), .B1(net_3647), .A1(net_3185), .A2(net_462), .B2(net_461) );
NAND4_X2 inst_1250 ( .ZN(net_3826), .A1(net_3825), .A4(net_3767), .A3(net_3766), .A2(net_3590) );
NAND4_X2 inst_1226 ( .A3(net_2717), .A2(net_1274), .A4(net_1126), .ZN(net_793), .A1(net_686) );
NOR2_X2 inst_1013 ( .A2(net_3321), .ZN(net_1838), .A1(net_1739) );
OAI221_X2 inst_446 ( .B1(net_4161), .ZN(net_3749), .B2(net_3407), .C1(net_2328), .A(net_2021), .C2(net_67) );
CLKBUF_X2 inst_4965 ( .A(net_4950), .Z(net_4951) );
NAND2_X2 inst_1979 ( .ZN(net_3382), .A1(net_3377), .A2(net_3376) );
OAI221_X2 inst_364 ( .ZN(net_2742), .B1(net_2733), .C1(net_2731), .C2(net_2663), .A(net_2644), .B2(net_1818) );
AOI22_X2 inst_3613 ( .A1(net_4063), .B1(net_4058), .ZN(net_1404), .B2(net_235), .A2(net_232) );
INV_X4 inst_2354 ( .ZN(net_1606), .A(net_947) );
CLKBUF_X2 inst_4923 ( .A(net_4908), .Z(net_4909) );
OAI211_X2 inst_824 ( .C1(net_3964), .ZN(net_1816), .A(net_1450), .C2(net_1324), .B(net_671) );
INV_X2 inst_2997 ( .A(net_3003), .ZN(net_219) );
AOI22_X2 inst_3533 ( .ZN(net_1822), .B2(net_1821), .A1(net_1758), .B1(net_1169), .A2(net_54) );
CLKBUF_X2 inst_4712 ( .A(net_4697), .Z(net_4698) );
OAI221_X2 inst_411 ( .B2(net_3789), .ZN(net_1547), .A(net_1390), .B1(net_1343), .C2(net_1089), .C1(net_1040) );
XNOR2_X2 inst_124 ( .ZN(net_4154), .B(net_3459), .A(net_3457) );
AOI22_X2 inst_3515 ( .B1(net_4045), .B2(net_3466), .ZN(net_1956), .A1(net_1955), .A2(net_256) );
AOI222_X1 inst_3750 ( .C1(net_3116), .A2(net_3115), .ZN(net_2056), .A1(net_2055), .B2(net_2054), .C2(net_2053), .B1(net_1910) );
AOI211_X2 inst_4026 ( .B(net_4070), .C2(net_1636), .ZN(net_1226), .A(net_1173), .C1(net_883) );
AND4_X2 inst_4056 ( .ZN(net_1516), .A1(net_1327), .A4(net_1274), .A2(net_1268), .A3(net_1030) );
CLKBUF_X2 inst_4382 ( .A(net_4367), .Z(net_4368) );
CLKBUF_X2 inst_4401 ( .A(net_4386), .Z(net_4387) );
DFF_X1 inst_3430 ( .Q(net_4021), .D(net_4020), .CK(net_4899) );
AOI221_X2 inst_3869 ( .A(net_3362), .B2(net_3117), .B1(net_2020), .C1(net_2019), .ZN(net_1936), .C2(x204) );
AOI22_X2 inst_3488 ( .B1(net_2752), .ZN(net_2605), .A2(net_2520), .A1(net_2275), .B2(net_51) );
NAND3_X4 inst_1270 ( .ZN(net_3954), .A1(net_3927), .A3(net_3451), .A2(net_3450) );
CLKBUF_X2 inst_4563 ( .A(net_4548), .Z(net_4549) );
XNOR2_X2 inst_61 ( .A(net_3256), .ZN(net_2163), .B(net_1644) );
OR2_X4 inst_203 ( .ZN(net_2912), .A2(net_2354), .A1(net_2351) );
NOR2_X2 inst_1139 ( .ZN(net_3786), .A2(net_3266), .A1(net_2209) );
NAND2_X2 inst_1519 ( .A1(net_2959), .ZN(net_2503), .A2(net_150) );
INV_X8 inst_2156 ( .A(net_3939), .ZN(net_3612) );
CLKBUF_X2 inst_4989 ( .A(net_4974), .Z(net_4975) );
CLKBUF_X2 inst_4507 ( .A(net_4492), .Z(net_4493) );
NAND2_X2 inst_1571 ( .A1(net_2912), .ZN(net_2450), .A2(net_215) );
CLKBUF_X2 inst_4324 ( .A(net_4296), .Z(net_4310) );
OAI21_X4 inst_456 ( .A(net_3945), .ZN(net_392), .B1(net_313), .B2(net_275) );
OAI211_X2 inst_832 ( .ZN(net_1360), .C1(net_1359), .A(net_1241), .B(net_593), .C2(net_315) );
INV_X4 inst_2515 ( .A(net_3283), .ZN(net_3178) );
NAND2_X2 inst_1491 ( .A1(net_3368), .A2(net_3296), .ZN(net_2859) );
NAND2_X4 inst_1402 ( .A2(net_3662), .ZN(net_434), .A1(net_407) );
OAI33_X1 inst_275 ( .ZN(net_3796), .A3(net_3792), .B3(net_2717), .A1(net_1297), .A2(net_1288), .B1(net_730), .B2(net_631) );
XNOR2_X2 inst_117 ( .B(net_3859), .ZN(net_3592), .A(net_3511) );
INV_X2 inst_2676 ( .ZN(net_1896), .A(net_1895) );
CLKBUF_X2 inst_5172 ( .A(net_4970), .Z(net_5158) );
DFF_X2 inst_3106 ( .QN(net_3131), .D(net_2830), .CK(net_4490) );
AOI22_X2 inst_3728 ( .ZN(net_3864), .A1(net_3178), .B1(net_2099), .A2(net_226), .B2(net_167) );
SDFF_X2 inst_154 ( .SE(net_2514), .D(net_1886), .SI(net_86), .Q(net_86), .CK(net_4980) );
INV_X4 inst_2416 ( .A(net_3106), .ZN(net_257) );
AND2_X4 inst_4106 ( .A2(net_3163), .ZN(net_458), .A1(net_345) );
AOI221_X2 inst_3812 ( .B2(net_3134), .ZN(net_2592), .B1(net_2591), .C1(net_2590), .C2(net_2589), .A(net_1090) );
OAI21_X4 inst_465 ( .ZN(net_3770), .B1(net_3634), .A(net_1602), .B2(net_923) );
INV_X4 inst_2304 ( .ZN(net_2053), .A(net_1845) );
AOI21_X2 inst_3959 ( .B1(net_1797), .ZN(net_1639), .A(net_1561), .B2(net_433) );
INV_X4 inst_2503 ( .A(net_3155), .ZN(net_207) );
CLKBUF_X2 inst_4877 ( .A(net_4862), .Z(net_4863) );
CLKBUF_X2 inst_4518 ( .A(net_4503), .Z(net_4504) );
CLKBUF_X2 inst_4240 ( .A(net_4225), .Z(net_4226) );
INV_X4 inst_2173 ( .ZN(net_2871), .A(net_2837) );
NAND2_X2 inst_1790 ( .ZN(net_1587), .A2(net_958), .A1(net_937) );
XNOR2_X2 inst_94 ( .ZN(net_715), .A(net_714), .B(net_43) );
DFF_X2 inst_3214 ( .QN(net_3153), .D(net_806), .CK(net_4666) );
NAND2_X2 inst_1905 ( .A2(net_3127), .ZN(net_343), .A1(net_299) );
INV_X4 inst_2264 ( .ZN(net_1518), .A(net_1151) );
NAND3_X1 inst_1378 ( .A2(net_3530), .A1(net_3513), .ZN(net_3295), .A3(net_2679) );
OR2_X4 inst_243 ( .A2(net_4000), .ZN(net_3907), .A1(net_719) );
CLKBUF_X2 inst_4345 ( .A(net_4278), .Z(net_4331) );
OAI221_X2 inst_424 ( .B1(net_3839), .C2(net_3681), .ZN(net_1271), .C1(net_1152), .B2(net_877), .A(net_860) );
OAI21_X2 inst_591 ( .B1(net_3693), .A(net_3229), .ZN(net_2647), .B2(net_71) );
INV_X2 inst_2697 ( .ZN(net_1778), .A(net_1686) );
DFF_X2 inst_3166 ( .D(net_1997), .QN(net_108), .CK(net_4533) );
XOR2_X2 inst_15 ( .A(net_1100), .B(net_1092), .Z(net_1087) );
AOI222_X1 inst_3747 ( .C1(net_3504), .B1(net_3472), .A1(net_3469), .A2(net_3136), .B2(net_3115), .ZN(net_2277), .C2(net_261) );
AOI22_X2 inst_3656 ( .ZN(net_598), .A1(net_597), .B1(net_596), .A2(net_571), .B2(net_570) );
INV_X4 inst_2237 ( .A(net_2144), .ZN(net_1779) );
CLKBUF_X2 inst_4417 ( .A(net_4402), .Z(net_4403) );
AOI22_X2 inst_3496 ( .A1(net_2249), .ZN(net_2211), .B1(net_2153), .A2(net_2141), .B2(net_297) );
INV_X8 inst_2123 ( .ZN(net_570), .A(net_367) );
DFF_X1 inst_3229 ( .QN(net_3066), .D(net_2958), .CK(net_4880) );
CLKBUF_X2 inst_4918 ( .A(net_4367), .Z(net_4904) );
INV_X2 inst_2706 ( .ZN(net_1665), .A(net_1664) );
AND2_X4 inst_4135 ( .ZN(net_4064), .A2(net_2522), .A1(net_2518) );
OAI21_X2 inst_476 ( .B1(net_3509), .B2(net_3208), .ZN(net_2974), .A(net_2494) );
AOI222_X1 inst_3742 ( .A1(net_4189), .C1(net_3504), .B1(net_3472), .ZN(net_2319), .A2(net_2037), .C2(net_393), .B2(net_228) );
INV_X4 inst_2499 ( .ZN(net_1439), .A(net_62) );
INV_X2 inst_2827 ( .A(net_3614), .ZN(net_522) );
XOR2_X2 inst_20 ( .Z(net_4037), .A(net_2379), .B(net_1782) );
INV_X4 inst_2448 ( .A(net_3082), .ZN(net_551) );
NAND3_X2 inst_1369 ( .A3(net_4004), .ZN(net_3987), .A2(net_3986), .A1(net_3395) );
AOI21_X2 inst_3988 ( .B2(net_923), .ZN(net_741), .A(net_740), .B1(net_655) );
OAI222_X2 inst_349 ( .C1(net_3784), .A2(net_2131), .ZN(net_1939), .A1(net_1815), .B1(net_1814), .B2(net_505), .C2(net_115) );
CLKBUF_X2 inst_4994 ( .A(net_4979), .Z(net_4980) );
INV_X4 inst_2541 ( .ZN(net_3399), .A(net_3102) );
OAI21_X2 inst_576 ( .B2(net_2917), .B1(net_2803), .ZN(net_2802), .A(net_2403) );
NAND2_X2 inst_1693 ( .A1(net_3293), .ZN(net_1977), .A2(net_227) );
CLKBUF_X2 inst_4249 ( .A(net_4217), .Z(net_4235) );
CLKBUF_X2 inst_4235 ( .A(net_4220), .Z(net_4221) );
INV_X4 inst_2561 ( .A(net_3858), .ZN(net_3514) );
DFF_X1 inst_3306 ( .QN(net_3018), .D(net_2865), .CK(net_5075) );
NOR2_X2 inst_1020 ( .A2(net_4089), .ZN(net_1854), .A1(net_1815) );
INV_X2 inst_2876 ( .A(net_3270), .ZN(net_262) );
INV_X2 inst_3055 ( .A(net_3943), .ZN(net_3929) );
NOR2_X4 inst_976 ( .A1(net_3997), .ZN(net_3935), .A2(net_3789) );
AOI21_X2 inst_3952 ( .B2(net_4086), .A(net_3963), .B1(net_1844), .ZN(net_1843) );
CLKBUF_X2 inst_4226 ( .A(net_4211), .Z(net_4212) );
NAND3_X2 inst_1279 ( .ZN(net_2748), .A1(net_2680), .A2(net_1518), .A3(net_1213) );
INV_X4 inst_2252 ( .ZN(net_1306), .A(net_1305) );
AOI22_X2 inst_3588 ( .A1(net_4062), .B1(net_4057), .ZN(net_1429), .B2(net_177), .A2(net_159) );
NOR2_X2 inst_1096 ( .A2(net_3164), .A1(net_3162), .ZN(net_338) );
CLKBUF_X2 inst_4229 ( .A(net_4214), .Z(net_4215) );
CLKBUF_X2 inst_4552 ( .A(net_4366), .Z(net_4538) );
INV_X4 inst_2238 ( .ZN(net_1862), .A(net_1815) );
CLKBUF_X2 inst_5207 ( .A(net_5192), .Z(net_5193) );
INV_X2 inst_2763 ( .ZN(net_1068), .A(net_962) );
CLKBUF_X2 inst_5072 ( .A(net_4791), .Z(net_5058) );
CLKBUF_X2 inst_4543 ( .A(net_4199), .Z(net_4529) );
NAND2_X2 inst_1839 ( .A1(net_4106), .ZN(net_1152), .A2(net_326) );
DFF_X2 inst_3151 ( .D(net_2257), .QN(net_192), .CK(net_4464) );
OAI21_X2 inst_761 ( .A(net_3989), .ZN(net_3783), .B2(net_3681), .B1(net_867) );
CLKBUF_X2 inst_4867 ( .A(net_4395), .Z(net_4853) );
DFF_X1 inst_3399 ( .Q(net_3118), .D(net_1534), .CK(net_4303) );
DFF_X1 inst_3414 ( .D(net_1361), .Q(net_30), .CK(net_4295) );
CLKBUF_X2 inst_4436 ( .A(net_4421), .Z(net_4422) );
CLKBUF_X2 inst_4495 ( .A(net_4480), .Z(net_4481) );
INV_X2 inst_2803 ( .A(net_844), .ZN(net_726) );
NAND2_X4 inst_1432 ( .A1(net_3769), .ZN(net_3663), .A2(net_3590) );
OAI21_X2 inst_725 ( .ZN(net_1400), .A(net_363), .B2(net_322), .B1(net_164) );
AND2_X4 inst_4120 ( .ZN(net_4043), .A1(net_2114), .A2(net_1611) );
INV_X1 inst_3084 ( .ZN(net_3689), .A(net_3688) );
CLKBUF_X2 inst_5097 ( .A(net_5082), .Z(net_5083) );
INV_X4 inst_2259 ( .ZN(net_1181), .A(net_1180) );
NAND3_X2 inst_1337 ( .ZN(net_3260), .A1(net_3257), .A2(net_2892), .A3(net_2890) );
INV_X4 inst_2464 ( .A(net_3070), .ZN(net_492) );
INV_X2 inst_2641 ( .ZN(net_2340), .A(net_2320) );
HA_X1 inst_3096 ( .B(net_3103), .S(net_1154), .CO(net_822), .A(net_688) );
INV_X2 inst_3015 ( .ZN(net_3402), .A(net_3010) );
AOI21_X2 inst_4010 ( .ZN(net_4161), .B1(net_2243), .A(net_2123), .B2(net_182) );
NAND2_X2 inst_1638 ( .ZN(net_2186), .A1(net_2185), .A2(net_1771) );
DFF_X1 inst_3328 ( .D(net_2807), .QN(net_292), .CK(net_4487) );
INV_X4 inst_2441 ( .A(net_3154), .ZN(net_218) );
NOR2_X2 inst_1111 ( .ZN(net_3314), .A1(net_3313), .A2(net_1509) );
DFF_X1 inst_3220 ( .QN(net_3060), .D(net_2975), .CK(net_4608) );
INV_X2 inst_2658 ( .ZN(net_2249), .A(net_2153) );
NOR3_X4 inst_878 ( .A3(net_3760), .A2(net_3754), .ZN(net_3603), .A1(net_268) );
CLKBUF_X2 inst_4959 ( .A(net_4363), .Z(net_4945) );
OAI21_X2 inst_480 ( .B1(net_2970), .ZN(net_2966), .B2(net_2965), .A(net_2444) );
NAND2_X2 inst_1926 ( .ZN(net_3189), .A1(net_3186), .A2(net_150) );
CLKBUF_X2 inst_4631 ( .A(net_4306), .Z(net_4617) );
CLKBUF_X2 inst_4351 ( .A(net_4336), .Z(net_4337) );
OAI21_X2 inst_564 ( .B2(net_2917), .B1(net_2849), .ZN(net_2848), .A(net_2396) );
INV_X2 inst_2986 ( .ZN(net_128), .A(net_74) );
CLKBUF_X2 inst_4783 ( .A(net_4768), .Z(net_4769) );
INV_X4 inst_2206 ( .ZN(net_2253), .A(net_2232) );
INV_X2 inst_2792 ( .A(net_965), .ZN(net_787) );
OAI21_X2 inst_739 ( .ZN(net_3241), .B1(net_3240), .B2(net_1975), .A(net_1720) );
AOI221_X2 inst_3862 ( .C2(net_3543), .ZN(net_2018), .B1(net_2017), .C1(net_2016), .A(net_1892), .B2(net_364) );
XNOR2_X2 inst_46 ( .A(net_3692), .ZN(net_2587), .B(net_1449) );
NOR2_X4 inst_934 ( .A2(net_4186), .ZN(net_915), .A1(net_796) );
INV_X4 inst_2537 ( .ZN(net_3349), .A(net_3348) );
NOR2_X2 inst_1000 ( .ZN(net_2031), .A1(net_1973), .A2(net_126) );
NOR2_X2 inst_1126 ( .ZN(net_3472), .A1(net_3471), .A2(net_1835) );
AOI22_X2 inst_3470 ( .B2(net_3120), .A1(net_2724), .B1(net_2722), .ZN(net_2720), .A2(net_31) );
CLKBUF_X2 inst_5304 ( .A(net_4742), .Z(net_5290) );
OAI211_X2 inst_796 ( .ZN(net_2273), .C2(net_2272), .B(net_2237), .C1(net_2190), .A(net_2006) );
INV_X4 inst_2585 ( .ZN(net_3653), .A(net_3169) );
OAI21_X2 inst_633 ( .ZN(net_2078), .B2(net_2076), .A(net_1967), .B1(net_1668) );
INV_X4 inst_2364 ( .ZN(net_691), .A(net_442) );
CLKBUF_X2 inst_4299 ( .A(net_4256), .Z(net_4285) );
OAI21_X2 inst_524 ( .B1(net_3302), .ZN(net_2913), .B2(net_2912), .A(net_2450) );
NAND2_X2 inst_1882 ( .A2(net_2037), .ZN(net_426), .A1(net_401) );
XNOR2_X2 inst_104 ( .B(net_3418), .ZN(net_452), .A(net_366) );
AND3_X4 inst_4060 ( .A1(net_4042), .A2(net_3506), .ZN(net_2534), .A3(net_2125) );
INV_X4 inst_2285 ( .A(net_1332), .ZN(net_1118) );
INV_X4 inst_2331 ( .A(net_2717), .ZN(net_847) );
CLKBUF_X2 inst_4478 ( .A(net_4463), .Z(net_4464) );
DFF_X1 inst_3344 ( .D(net_2779), .CK(net_4350), .Q(x90) );
NAND2_X2 inst_1499 ( .ZN(net_2818), .A1(net_2773), .A2(net_2716) );
INV_X4 inst_2377 ( .ZN(net_2737), .A(net_409) );
INV_X4 inst_2522 ( .ZN(net_3255), .A(net_3254) );
INV_X2 inst_2972 ( .ZN(net_238), .A(net_116) );
CLKBUF_X2 inst_4862 ( .A(net_4847), .Z(net_4848) );
OAI21_X2 inst_727 ( .B2(net_3662), .ZN(net_693), .A(net_424), .B1(net_368) );
CLKBUF_X2 inst_4663 ( .A(net_4648), .Z(net_4649) );
CLKBUF_X2 inst_4804 ( .A(net_4254), .Z(net_4790) );
NOR3_X2 inst_882 ( .ZN(net_2835), .A1(net_2786), .A2(net_2765), .A3(net_2712) );
INV_X2 inst_2874 ( .ZN(net_1173), .A(x1023) );
CLKBUF_X2 inst_4607 ( .A(net_4592), .Z(net_4593) );
INV_X4 inst_2431 ( .ZN(net_225), .A(net_44) );
DFF_X1 inst_3297 ( .QN(net_3007), .D(net_2886), .CK(net_5259) );
CLKBUF_X2 inst_5216 ( .A(net_4810), .Z(net_5202) );
INV_X2 inst_2938 ( .ZN(net_1507), .A(net_63) );
CLKBUF_X2 inst_5257 ( .A(net_5242), .Z(net_5243) );
CLKBUF_X2 inst_4423 ( .A(net_4334), .Z(net_4409) );
CLKBUF_X2 inst_5083 ( .A(net_5068), .Z(net_5069) );
NAND3_X2 inst_1346 ( .A3(net_3634), .A2(net_3620), .ZN(net_3431), .A1(net_1267) );
OAI21_X2 inst_708 ( .B2(net_4186), .A(net_3627), .B1(net_986), .ZN(net_971) );
AOI22_X2 inst_3523 ( .A2(net_3136), .B2(net_3111), .A1(net_1923), .ZN(net_1922), .B1(net_1921) );
CLKBUF_X2 inst_4855 ( .A(net_4840), .Z(net_4841) );
NAND3_X2 inst_1374 ( .ZN(net_4191), .A1(net_1290), .A3(net_593), .A2(net_178) );
NOR2_X4 inst_953 ( .A1(net_4157), .A2(net_3917), .ZN(net_3675) );
CLKBUF_X2 inst_5108 ( .A(net_4596), .Z(net_5094) );
CLKBUF_X2 inst_4342 ( .A(net_4327), .Z(net_4328) );
INV_X4 inst_2510 ( .A(net_3058), .ZN(net_567) );
AOI22_X2 inst_3510 ( .B1(net_3676), .B2(net_3134), .A1(net_2012), .ZN(net_2007), .A2(net_378) );
CLKBUF_X2 inst_4277 ( .A(net_4254), .Z(net_4263) );
NOR2_X2 inst_1071 ( .ZN(net_1176), .A1(net_750), .A2(net_399) );
CLKBUF_X2 inst_5060 ( .A(net_5045), .Z(net_5046) );
CLKBUF_X2 inst_4339 ( .A(net_4324), .Z(net_4325) );
CLKBUF_X2 inst_5291 ( .A(net_4543), .Z(net_5277) );
NAND2_X4 inst_1421 ( .ZN(net_3580), .A1(net_3579), .A2(net_2312) );
DFF_X1 inst_3373 ( .QN(net_3122), .D(net_2256), .CK(net_4481) );
NAND2_X2 inst_1994 ( .ZN(net_3481), .A2(net_3480), .A1(net_3479) );
CLKBUF_X2 inst_4902 ( .A(net_4355), .Z(net_4888) );
CLKBUF_X2 inst_4262 ( .A(net_4247), .Z(net_4248) );
CLKBUF_X2 inst_5298 ( .A(net_4298), .Z(net_5284) );
AOI22_X2 inst_3664 ( .A1(net_571), .B1(net_570), .ZN(net_563), .A2(net_219), .B2(net_160) );
CLKBUF_X2 inst_4720 ( .A(net_4705), .Z(net_4706) );
AOI22_X2 inst_3486 ( .A1(net_4038), .A2(net_3385), .B1(net_2657), .ZN(net_2650), .B2(net_361) );
INV_X8 inst_2162 ( .ZN(net_3654), .A(net_3653) );
CLKBUF_X2 inst_4986 ( .A(net_4545), .Z(net_4972) );
OAI221_X2 inst_392 ( .C2(net_3408), .B1(net_2361), .ZN(net_2360), .C1(net_2219), .A(net_1930), .B2(net_108) );
XNOR2_X2 inst_120 ( .ZN(net_4132), .B(net_290), .A(net_46) );
OAI22_X2 inst_294 ( .A1(net_3781), .B1(net_1884), .ZN(net_1742), .A2(net_1590), .B2(net_266) );
CLKBUF_X2 inst_4398 ( .A(net_4383), .Z(net_4384) );
AND2_X4 inst_4165 ( .ZN(net_4119), .A1(net_401), .A2(net_260) );
NAND2_X2 inst_1514 ( .ZN(net_2550), .A1(net_2549), .A2(net_2548) );
DFF_X1 inst_3384 ( .D(net_1897), .Q(net_83), .CK(net_4474) );
INV_X4 inst_2272 ( .ZN(net_1023), .A(net_972) );
NAND2_X2 inst_1608 ( .A1(net_2967), .ZN(net_2408), .A2(net_519) );
OAI21_X2 inst_567 ( .B2(net_2909), .B1(net_2849), .ZN(net_2845), .A(net_2467) );
DFF_X2 inst_3200 ( .QN(net_3108), .D(net_1629), .CK(net_4828) );
OAI211_X2 inst_810 ( .ZN(net_1630), .B(net_1628), .C1(net_1627), .A(net_1557), .C2(net_1124) );
OR2_X4 inst_230 ( .ZN(net_1826), .A1(net_412), .A2(net_389) );
NAND2_X2 inst_1601 ( .A1(net_2969), .ZN(net_2416), .A2(net_479) );
NAND2_X4 inst_1484 ( .ZN(net_4000), .A1(net_3999), .A2(net_3171) );
INV_X2 inst_3035 ( .ZN(net_3575), .A(net_3574) );
AOI22_X2 inst_3526 ( .A2(net_3138), .A1(net_1923), .B1(net_1921), .ZN(net_1918), .B2(net_1326) );
OAI211_X2 inst_856 ( .ZN(net_3758), .B(net_1628), .C1(net_1627), .A(net_1552), .C2(net_385) );
NAND2_X2 inst_1893 ( .ZN(net_533), .A2(net_385), .A1(net_334) );
endmodule
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_MATLAB_Function.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_MATLAB_Function
// Source Path: velocityControlHdl/Sin_Cos1/Mark_Extract_Bits/MATLAB Function
// Hierarchy Level: 6
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_MATLAB_Function
(
u,
y
);
input [17:0] u; // ufix18
output [8:0] y; // ufix9
wire [8:0] y1; // ufix9_E9
//MATLAB Function 'Sin_Cos/Mark_Extract_Bits/MATLAB Function': '<S38>:1'
// Non-tunable mask parameter
//'<S38>:1:8'
//'<S38>:1:10'
assign y1 = u[17:9];
//'<S38>:1:14'
assign y = y1;
endmodule // velocityControlHdl_MATLAB_Function
|
module fpga_memory
(
// input
// LSU
mem_wr_en, mem_rd_en,
mem_addr, mem_wr_data, mem_tag_req,
// MB
mb_data_in, mb_data_we, mb_ack, mb_done,
clk, rst,
// output
// LSU
mem_tag_resp, mem_rd_data, mem_ack,
// MB
mb_op, mb_data_out, mb_addr
);
input clk;
input rst;
input mem_wr_en;
input mem_rd_en;
input [31:0] mem_addr;
input [31:0] mem_wr_data;
input [6:0] mem_tag_req;
input [31:0] mb_data_in;
input mb_data_we;
input mb_ack;
input mb_done;
output [31:0] mem_rd_data;
output [6:0] mem_tag_resp;
output mem_ack;
output [3:0] mb_op;
output [31:0] mb_data_out;
output [31:0] mb_addr;
reg [31:0] mem_addr_reg;
//reg [31:0] mem_wr_en;
reg [31:0] mb_data_out_reg;
reg[6:0] mem_tag_req_reg;
reg[3:0] mem_state;
reg[3:0] mem_state_next;
reg [31:0] mb_data_in_reg;
reg mem_ack_reg;
reg mb_ack_reg;
reg mb_done_reg;
`define MEM_IDLE 4'b0000
`define MEM_WR_ACK_WAIT 4'b0001
`define MEM_WR_RDY_WAIT 4'b0010
`define MEM_WR_LSU_TO 4'b0011
`define MEM_RD_ACK_WAIT 4'b0100
`define MEM_RD_RDY_WAIT 4'b0101
`define MEM_RD_LSU_TO 4'b0110
assign mem_tag_resp = mem_tag_req_reg;
assign mem_rd_data = mb_data_in_reg;
assign mem_ack = mem_ack_reg;
assign mb_data_out = mb_data_out_reg;
assign mb_addr = mem_addr_reg;
assign mb_op = mem_state;
always@(posedge clk) begin
if(rst) begin
mem_state <= `MEM_IDLE;
mb_data_out_reg <= 32'd0;
mem_addr_reg <= 32'd0;
mem_tag_req_reg <= 7'd0;
mb_data_in_reg <= 32'd0;
mb_ack_reg <= 1'b0;
mb_done_reg <= 1'b0;
end
else begin
mb_ack_reg <= mb_ack;
mb_done_reg <= mb_done;
mem_state <= mem_state_next;
mb_data_out_reg <= mb_data_out_reg;
if(mem_wr_en) begin
mb_data_out_reg <= mem_wr_data;
end
mem_addr_reg <= mem_addr_reg;
mem_tag_req_reg <= mem_tag_req_reg;
if(mem_wr_en | mem_rd_en) begin
mem_addr_reg <= mem_addr;
mem_tag_req_reg <= mem_tag_req;
end
mb_data_in_reg <= mb_data_in_reg;
if(mb_data_we) begin
mb_data_in_reg <= mb_data_in;
end
end
end
always@(*) begin
mem_state_next <= mem_state;
mem_ack_reg <= 1'b0;
case(mem_state)
`MEM_IDLE: begin
if(mem_wr_en) begin
mem_state_next <= `MEM_WR_ACK_WAIT;
end
else if(mem_rd_en) begin
mem_state_next <= `MEM_RD_ACK_WAIT;
end
end
`MEM_WR_ACK_WAIT: begin
if(~mb_ack_reg & mb_ack) begin
mem_state_next <= `MEM_WR_RDY_WAIT;
end
end
`MEM_WR_RDY_WAIT: begin
if(~mb_done_reg & mb_done) begin
mem_state_next <= `MEM_WR_LSU_TO;
end
end
`MEM_WR_LSU_TO: begin
mem_ack_reg <= 1'b1;
mem_state_next <= `MEM_IDLE;
end
`MEM_RD_ACK_WAIT: begin
if(~mb_ack_reg & mb_ack) begin
mem_state_next <= `MEM_RD_RDY_WAIT;
end
end
`MEM_RD_RDY_WAIT: begin
if(~mb_done_reg & mb_done) begin
mem_state_next <= `MEM_RD_LSU_TO;
end
end
`MEM_RD_LSU_TO: begin
mem_ack_reg <= 1'b1;
mem_state_next <= `MEM_IDLE;
end
default: mem_state_next <= mem_state;
endcase
end
endmodule |
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.2 (win64) Build 932637 Wed Jun 11 13:33:10 MDT 2014
// Date : Fri Sep 26 21:45:04 2014
// Host : ECE-411-6 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// C:/Users/coltmw/Documents/GitHub/ecen4024-microphone-array/microphone-array/microphone-array.srcs/sources_1/ip/cascaded_integrator_comb/cascaded_integrator_comb_funcsim.v
// Design : cascaded_integrator_comb
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "cic_compiler_v4_0,Vivado 2014.2" *) (* CHECK_LICENSE_TYPE = "cascaded_integrator_comb,cic_compiler_v4_0,{}" *)
(* core_generation_info = "cascaded_integrator_comb,cic_compiler_v4_0,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=cic_compiler,x_ipVersion=4.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,C_COMPONENT_NAME=cascaded_integrator_comb,C_FILTER_TYPE=1,C_NUM_STAGES=5,C_DIFF_DELAY=1,C_RATE=16,C_INPUT_WIDTH=2,C_OUTPUT_WIDTH=22,C_USE_DSP=1,C_HAS_ROUNDING=0,C_NUM_CHANNELS=1,C_RATE_TYPE=0,C_MIN_RATE=16,C_MAX_RATE=16,C_SAMPLE_FREQ=1,C_CLK_FREQ=1,C_USE_STREAMING_INTERFACE=1,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_C1=22,C_C2=22,C_C3=22,C_C4=22,C_C5=22,C_C6=0,C_I1=22,C_I2=22,C_I3=22,C_I4=22,C_I5=22,C_I6=0,C_S_AXIS_CONFIG_TDATA_WIDTH=1,C_S_AXIS_DATA_TDATA_WIDTH=8,C_M_AXIS_DATA_TDATA_WIDTH=24,C_M_AXIS_DATA_TUSER_WIDTH=1,C_HAS_DOUT_TREADY=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0}" *)
(* NotValidForBitStream *)
module cascaded_integrator_comb
(aclk,
s_axis_data_tdata,
s_axis_data_tvalid,
s_axis_data_tready,
m_axis_data_tdata,
m_axis_data_tvalid);
(* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) input aclk;
input [7:0]s_axis_data_tdata;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID" *) input s_axis_data_tvalid;
(* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY" *) output s_axis_data_tready;
output [23:0]m_axis_data_tdata;
(* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) output m_axis_data_tvalid;
wire aclk;
wire [23:0]m_axis_data_tdata;
wire m_axis_data_tvalid;
wire [7:0]s_axis_data_tdata;
wire s_axis_data_tready;
wire s_axis_data_tvalid;
wire NLW_U0_event_halted_UNCONNECTED;
wire NLW_U0_event_tlast_missing_UNCONNECTED;
wire NLW_U0_event_tlast_unexpected_UNCONNECTED;
wire NLW_U0_m_axis_data_tlast_UNCONNECTED;
wire NLW_U0_s_axis_config_tready_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_data_tuser_UNCONNECTED;
(* C_C1 = "22" *)
(* C_C2 = "22" *)
(* C_C3 = "22" *)
(* C_C4 = "22" *)
(* C_C5 = "22" *)
(* C_C6 = "0" *)
(* C_CLK_FREQ = "1" *)
(* C_COMPONENT_NAME = "cascaded_integrator_comb" *)
(* C_DIFF_DELAY = "1" *)
(* C_FAMILY = "artix7" *)
(* C_FILTER_TYPE = "1" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_DOUT_TREADY = "0" *)
(* C_HAS_ROUNDING = "0" *)
(* C_I1 = "22" *)
(* C_I2 = "22" *)
(* C_I3 = "22" *)
(* C_I4 = "22" *)
(* C_I5 = "22" *)
(* C_I6 = "0" *)
(* C_INPUT_WIDTH = "2" *)
(* C_MAX_RATE = "16" *)
(* C_MIN_RATE = "16" *)
(* C_M_AXIS_DATA_TDATA_WIDTH = "24" *)
(* C_M_AXIS_DATA_TUSER_WIDTH = "1" *)
(* C_NUM_CHANNELS = "1" *)
(* C_NUM_STAGES = "5" *)
(* C_OUTPUT_WIDTH = "22" *)
(* C_RATE = "16" *)
(* C_RATE_TYPE = "0" *)
(* C_SAMPLE_FREQ = "1" *)
(* C_S_AXIS_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_AXIS_DATA_TDATA_WIDTH = "8" *)
(* C_USE_DSP = "1" *)
(* C_USE_STREAMING_INTERFACE = "1" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* DONT_TOUCH *)
(* downgradeipidentifiedwarnings = "yes" *)
cascaded_integrator_comb_cic_compiler_v4_0__parameterized0 U0
(.aclk(aclk),
.aclken(1'b1),
.aresetn(1'b1),
.event_halted(NLW_U0_event_halted_UNCONNECTED),
.event_tlast_missing(NLW_U0_event_tlast_missing_UNCONNECTED),
.event_tlast_unexpected(NLW_U0_event_tlast_unexpected_UNCONNECTED),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(NLW_U0_m_axis_data_tlast_UNCONNECTED),
.m_axis_data_tready(1'b0),
.m_axis_data_tuser(NLW_U0_m_axis_data_tuser_UNCONNECTED[0]),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(1'b0),
.s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED),
.s_axis_config_tvalid(1'b0),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tlast(1'b0),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid));
endmodule
(* ORIG_REF_NAME = "cic_compiler_v4_0" *) (* C_COMPONENT_NAME = "cascaded_integrator_comb" *) (* C_FILTER_TYPE = "1" *)
(* C_NUM_STAGES = "5" *) (* C_DIFF_DELAY = "1" *) (* C_RATE = "16" *)
(* C_INPUT_WIDTH = "2" *) (* C_OUTPUT_WIDTH = "22" *) (* C_USE_DSP = "1" *)
(* C_HAS_ROUNDING = "0" *) (* C_NUM_CHANNELS = "1" *) (* C_RATE_TYPE = "0" *)
(* C_MIN_RATE = "16" *) (* C_MAX_RATE = "16" *) (* C_SAMPLE_FREQ = "1" *)
(* C_CLK_FREQ = "1" *) (* C_USE_STREAMING_INTERFACE = "1" *) (* C_FAMILY = "artix7" *)
(* C_XDEVICEFAMILY = "artix7" *) (* C_C1 = "22" *) (* C_C2 = "22" *)
(* C_C3 = "22" *) (* C_C4 = "22" *) (* C_C5 = "22" *)
(* C_C6 = "0" *) (* C_I1 = "22" *) (* C_I2 = "22" *)
(* C_I3 = "22" *) (* C_I4 = "22" *) (* C_I5 = "22" *)
(* C_I6 = "0" *) (* C_S_AXIS_CONFIG_TDATA_WIDTH = "1" *) (* C_S_AXIS_DATA_TDATA_WIDTH = "8" *)
(* C_M_AXIS_DATA_TDATA_WIDTH = "24" *) (* C_M_AXIS_DATA_TUSER_WIDTH = "1" *) (* C_HAS_DOUT_TREADY = "0" *)
(* C_HAS_ACLKEN = "0" *) (* C_HAS_ARESETN = "0" *) (* downgradeipidentifiedwarnings = "yes" *)
module cascaded_integrator_comb_cic_compiler_v4_0__parameterized0
(aclk,
aclken,
aresetn,
s_axis_config_tdata,
s_axis_config_tvalid,
s_axis_config_tready,
s_axis_data_tdata,
s_axis_data_tvalid,
s_axis_data_tready,
s_axis_data_tlast,
m_axis_data_tdata,
m_axis_data_tuser,
m_axis_data_tvalid,
m_axis_data_tready,
m_axis_data_tlast,
event_tlast_unexpected,
event_tlast_missing,
event_halted);
input aclk;
input aclken;
input aresetn;
input [0:0]s_axis_config_tdata;
input s_axis_config_tvalid;
output s_axis_config_tready;
input [7:0]s_axis_data_tdata;
input s_axis_data_tvalid;
output s_axis_data_tready;
input s_axis_data_tlast;
output [23:0]m_axis_data_tdata;
output [0:0]m_axis_data_tuser;
output m_axis_data_tvalid;
input m_axis_data_tready;
output m_axis_data_tlast;
output event_tlast_unexpected;
output event_tlast_missing;
output event_halted;
wire aclk;
wire aclken;
wire aresetn;
wire event_halted;
wire event_tlast_missing;
wire event_tlast_unexpected;
wire [23:0]m_axis_data_tdata;
wire m_axis_data_tlast;
wire m_axis_data_tready;
wire [0:0]m_axis_data_tuser;
wire m_axis_data_tvalid;
wire [0:0]s_axis_config_tdata;
wire s_axis_config_tready;
wire s_axis_config_tvalid;
wire [7:0]s_axis_data_tdata;
wire s_axis_data_tlast;
wire s_axis_data_tready;
wire s_axis_data_tvalid;
(* C_C1 = "22" *)
(* C_C2 = "22" *)
(* C_C3 = "22" *)
(* C_C4 = "22" *)
(* C_C5 = "22" *)
(* C_C6 = "0" *)
(* C_CLK_FREQ = "1" *)
(* C_COMPONENT_NAME = "cascaded_integrator_comb" *)
(* C_DIFF_DELAY = "1" *)
(* C_FAMILY = "artix7" *)
(* C_FILTER_TYPE = "1" *)
(* C_HAS_ACLKEN = "0" *)
(* C_HAS_ARESETN = "0" *)
(* C_HAS_DOUT_TREADY = "0" *)
(* C_HAS_ROUNDING = "0" *)
(* C_I1 = "22" *)
(* C_I2 = "22" *)
(* C_I3 = "22" *)
(* C_I4 = "22" *)
(* C_I5 = "22" *)
(* C_I6 = "0" *)
(* C_INPUT_WIDTH = "2" *)
(* C_MAX_RATE = "16" *)
(* C_MIN_RATE = "16" *)
(* C_M_AXIS_DATA_TDATA_WIDTH = "24" *)
(* C_M_AXIS_DATA_TUSER_WIDTH = "1" *)
(* C_NUM_CHANNELS = "1" *)
(* C_NUM_STAGES = "5" *)
(* C_OUTPUT_WIDTH = "22" *)
(* C_RATE = "16" *)
(* C_RATE_TYPE = "0" *)
(* C_SAMPLE_FREQ = "1" *)
(* C_S_AXIS_CONFIG_TDATA_WIDTH = "1" *)
(* C_S_AXIS_DATA_TDATA_WIDTH = "8" *)
(* C_USE_DSP = "1" *)
(* C_USE_STREAMING_INTERFACE = "1" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
(* secure_extras = "A" *)
cascaded_integrator_comb_cic_compiler_v4_0_viv__parameterized0 i_synth
(.aclk(aclk),
.aclken(aclken),
.aresetn(aresetn),
.event_halted(event_halted),
.event_tlast_missing(event_tlast_missing),
.event_tlast_unexpected(event_tlast_unexpected),
.m_axis_data_tdata(m_axis_data_tdata),
.m_axis_data_tlast(m_axis_data_tlast),
.m_axis_data_tready(m_axis_data_tready),
.m_axis_data_tuser(m_axis_data_tuser),
.m_axis_data_tvalid(m_axis_data_tvalid),
.s_axis_config_tdata(s_axis_config_tdata),
.s_axis_config_tready(s_axis_config_tready),
.s_axis_config_tvalid(s_axis_config_tvalid),
.s_axis_data_tdata(s_axis_data_tdata),
.s_axis_data_tlast(s_axis_data_tlast),
.s_axis_data_tready(s_axis_data_tready),
.s_axis_data_tvalid(s_axis_data_tvalid));
endmodule
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`pragma protect key_block
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`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
EnsHmMGyJiGWDrh+ITWL3o1lffFiAubTmD62Oh4g9hvhAZ8g7tB8YBzZM6ZPiv0ar4orjc0SdbOC
DDkeaid7hJf2cDiAhvkHHa/uzjFkEiS1uFT0RT4Vt7Ir6NuK8YhExudhnmuzq+nkqeWxIk48bLV6
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`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
YG1Wju7+Sw8pf2ESywntCZKrf+gtSZRqWJyog7Q23z+j0jxbJXXCvtSJXRTs4G2sfX0+DvUgy7E1
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`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
pSSAm/YfwuJTEeqyxCb/pz8bT6T+D8Hman4CpHnq6tQB1mkRHMqZ87Usd4IE33vZFjaL2s8TSzPlXg1SlWYtXMVNrhTvfyfpqt3tynahy1rtPobmMy7T80Se9AnCCqYeYSSAOkJgJsdo24uToVx2Zs7UyCDtngjsYZvj5bA1VbYaHs4Agq2MFpyUW9AhI//E477/pf+ishPv33ntOORVKuXQwRVWcwZS2p3ZrIvNRJOyoo16r/xq7q1W7Mah1UJM8AMQimv9RjLTa5JD1WxvHLFwg6vY4DGZCQmItOoIgBY3zwVbqe46FhK4NxOI8SbwgRdm00gr5lAL2axk1QLMIg==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 3808)
`pragma protect data_block
VW/5iwtAZYmG5ukB4uY/dhWtHZU76cGwDOG/6yMZDKjXeonNEfC1dZRSU2z6nFOVsmViV1H0bdLy
8Xx7aZRkIVtsXC/dvdGjFy4WFuxbJ8ifPmRyeLOsvpT2cTP8HldmAIc9FMjImfGwsANdvOKfaUkT
bZPqYlVrr5ct0kdHqxZF1vFEtjnY5n3dTpQaFH2mu++2KzPNQv/piQNurQM5EnOM8bYoOy/tgv9D
bFaWFVvzRkjxCNTeniA1W0rQvKAxr6hKE+SNPjLuFoUmeA3yh2ZAqQyCbGlB2PR1QRfmkesMavz5
N40QrO15YJ3eWD5LbpoUDrj3UFIanhzamMyrmFk7Y0Ur7lQRbvxoWf57B/lG+POM77xagKc+gccU
QN5XxuWn7MrM2u4OvngfISkRGIrIgdZKbsto/0FpsdgDu72af4J14hkH2e0DdWB9Z7ONAYtDPWUQ
/81d0GIieBzURDmPBJsquIpGrfUl1zf7am8etL/wc40q8iXaIKMvZOz8tqUwSC5s1Pa3z7HAdm4I
WULk12fWn89LyfAZdkEtHO1wYA6AtwYOIkmnx5VAg2AL1x1zk2bqVdPEHxjb7LpfN8HwalhHDxmq
2xJpMlrF98DPl2KZSC3SnyZLDhXQO2fLtH/xKJ+oNZk3jUrHR+qCCvO/kP/F//UzRNfamMK64JTf
nRUnveKppxN0Y1pycht75f+VgF2Wr1CXV6RsHfHCao/SArXtmV4QYcVZZopgqq0W2Ah41tWVLfPL
ykZflkwWCyGHb2bc17Kk0FzSmRV1KxhtA7EWj5HogEVOCkBdqSVFTNyvVZ67IwioGPIMEcraYph7
o9v0zH7Emspf8WnhKh7zX+5vSAJP90ZX9V8hAeOgjGgdFrslpyIV6R8xy+HMN5gHGC0YZu+dZyHJ
wPC/Owh6/mayrAmRNLI6g315kULcjQ4S+03W4GiFHGLO0x65vBf8x5YA/DxzxwXuIF/AwKHTw1CM
fyetgGbQLYDsHEjt2+UQrhCeW0fUxYbVHYqUdcdFchpo+PIE7v4eGJyeQ+jejTs4ZECdUO5DBpsM
iW5FdHl+ZxAsNA2TOHOlTs9QyMsvH7iJcXXQIUKo38wDLfz3wk8C0U+dCO5Xq8gv2N0H6bn2ZEmh
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cX8bvYeFgBNWlutTXsxdPqTdPdQUzVLDASQS8pspTVRWR54i7l2qM1lrIqzTJ/ssyBioYW3JcD1F
5I6C4+PO52C10v8cAF3V1+aQakPju1LXp+zgTfVsCon8pwsfXntT6c9IVitJNiZ/nOnhhmP7pBic
iYtLjCm6Q+XSQPYGx4dD8JnjQA05My93XVTj6xH4rpCcpzpDSMUMT/4BjYXhv4V5nk29jXQZeXWw
0BSq0wdjIx8/WiyMBPBJNeiUO6mcSN+ASx1q5nni3H7jGf4KTMwskW9iiTLz1BYLab/AL8Rua3N+
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k1YYnROYNXTpaBTtHexj8Lhu9QN9WZF3XAsWFn5/iPma2zMhJ7N0ZciF+unil6qByIrpg0gVkkfK
zkjowlEQXxw+fBIDU/zD3Xjdpy30Yen6l5/orlUPW3zrxkZLV+qLWKHpE6yubJY7re4pg1dOfUbp
d/r6yIjhHy4p6PioSSRY+WZZ9OAuVk91Aj/+9W5w/iAVujyY8RPEhs8x3Sm/M7RXg8iOcigCkIgJ
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PU0cOXtCxYT7Ze7Md6ubUF8n96UfcLEZMG4xsPkWbHIBaPrXXrDiaTBwhJ27m30VAK6AEWtNcG3y
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RLP6qsCIHfd25rRvbz9P5Mlk/1yZICRy1MrIkD7DH8Ld8qgNobyTywj7GKFW0gXAUjyeJBDY6KTn
6zPkjjQaQ42ygy/dz4taerQ3rxVMrRdVYmVOrs5XIaBV5dds2pmwWwEBcab+SMPQ85Z7ZLGG44YT
edrHWgiHkNhHxDAN+tRvqIjkardZIohgfC+NkYMA51xLsCpx36Tw8vuXiYLdF3jegvB4vOfeg+re
lWv6vz4Otsu1V3MSVUtN/cCD0BGAsgbbn5XrvQn+Ktc4K/WzOXvhVNROUcqhqlaEoR2N1yCx7TWM
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xoYZKACL/1XK5psY9xiia8/BFZu29ysQFUg9RkKsiuiGJXbk4CpS4QGekiiWHgYWCmCKHUlsaAoK
BdpU8eriFx42CdCYVhi9Vjnoz6GTjG2Wa4mPtA5Gzlu51KbnkCNFXmndgXCbzgdAlmZwz1S9dz0U
wVMFHWEZDAhACEIpv+aWSIH7ATCuzBQcBBhERlCmanj0BfukruAgzyf6HxwQLIrZf1CyImc0+ZVH
DGF7sArAtMBNioZlz7TWmWiJyDplPq9/uM/hXJ3D5vh3Op7Q27icdktSmkNgg3/5dwzpDClYNOBD
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oIjDq/jnVPO6JS2vEK8tWt58HIBK3Gx0z2yDSbNq9FuqeBanW6AI7taDe6dgS8xOGLIig+aQwIkF
PHae+z5KTtIBSyitQZ0kET415BvH7KRRfyXDO5VqG/ADBVHBjuObqsYH+kR5+cdylWBjx4A2A6Ya
AF+QSD8TTLjdjsrUG9Ijfw+BLV6h1jR2tHLS9tKkH9eHAtcYWzfoqRQYCYBdGXyacniV9pMVvbSy
Va5U0NSayZoxnwg/iejWK81EFXSL//fhUNbTy9dwGeB/N6vsXaF04wC4zrW7YxrlOKK2s1uHf4Cw
E0RO3r56/3rgIehMUA9WCEjUhaVnny1m7yJ9tvfV9/7etrgSq8iQV59aiO0HQEVNXWPJ1zXxXjEW
lvZV3l4zDN7NkoQqG8CdWzR/qDoNJMyzaHjxOWjxC7wizN3+dA/FTbBmi9Ygz755yup4E26FJE3i
nzC4h412isLNGmrEfcHfCScAIhI7Jx0yzGpJ2AFI+WXqJw3hoSkdEi1+s4lpMext3iMMmc9jJfOV
Yh5tCeoF0loO24dirVqnkqRR3jBARbHe0kjsbr9abyeHrx4zGkGGhWzm6BkFlKBoK4tQTcoTtVD7
migN66+oTJCNVXCBNFVsYZGncIrzrtRDEhoCHMPAPSPqC4y/z/tcR6SknDYouU+6AmDg339cBqiK
t71x/aGrMn5lmJt6d//5kdzgwf6M+pf0nhBgcqY9Z4Vw2xm9K6wWR9h3Tcb4rzUapqSS8X7xPu3X
aIQ2SPFMy/fa7Qn3XHpFzMAo6wt98vHEq30edJZuxY0pYYld5W4bAagegqWKaDozbHowHjMHdzOu
g47oCT5cWEkNGBcoW+YGY3t1iHnKSBx+oSswBJlFC8eVDUDfiDkQUKrTUcv0ObUXep/WS7HV4hzT
BUnUfd6RsPS412wQX7Qru9+SE8eeKRFwrXyazW8CQ/pUxggITZFtsHH5I/juCkQkDDpFm5J4Ah8x
G/bVslb2DsU0ip5zktJkeAxcv3/a5sw2FUoxZpAR/RDyxu6kGVsqPPBLULkiJcOs5Gj99hovNWPd
YxfJDQRb2miLS3KBPg5xWhIr4PdRUArl4T/UsEax3GR4ycUh4RdFTjxR1HaGS7sHZaAGh+5Ltvq5
o1z+8+GM0XwvIN73/29QCxlp3QFlUw0mFJ5NZz8MNBhucVQkXmHNcjbDL5DotHyPVCQuK4fbbGa4
gGxVC5/hFCxwoE3Wj7X3DbOqXr2uCKrOzUf7qqC/yg4j5hduD5Tc9wYdGPhbNutdWbbGOvi6Dxt0
s5VlLOvpX9sQVG7xSoiQlYKoe2A5PCEo0eGuWvOs9DM5Y/8G3v3gmI/EM3CBpA==
`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
M2SmFx6fkkMNsI4u7NNl7aD/5cZ3fkE5kQPBpZ49rXFuHYOP7PQ220hPUTmAo+k0itXPZ2akNLv/
yyK7yA5Bew==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
AKjZwm+YMXdWOaulf44bv0xv17we+ivbj8KY1vYY/44NKaTFakpptPVB2ZF4m44dYqRop/VyCmS2
jU+WJf4/hAKAe83flEiw/PMfMGBy4+ZQEBtgEtPxGXdTiEoLCJBLJQYdgmvt94Y1KsAU42b+AHcc
JAJKvbAxXgufvVvDHnM=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
gU79D2mNbtSH4/mbg+y4guWjl7TEJiLvV3VH5t+d/h74FNgAvmd4NwtZ2Vp2jrMDajA+3c6vWVnR
Ukm7o8cx0PFlaLfoOS4+hKpXErAFnCQDevw0be46tMK2AssaXOxfTlGS5XPGGkggS71rLlOmIwDa
4HsVUKtsO/vH7auEgkLCSjZfHbCxir8yb1Ucu3CV6JebDf15N20BIHxoCCFPNurttOaSNgfd2w8U
kanJxRPb9+fHV9uMgJUIUGbixpzjnY0/853fOO2pksYuaseJ+UMeq3Sa5eoZikYforx6PWgQs3nQ
TwZC5R5XazKkpcxTnEE3AUrLUr7lg0Ku2g2yHQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
EnsHmMGyJiGWDrh+ITWL3o1lffFiAubTmD62Oh4g9hvhAZ8g7tB8YBzZM6ZPiv0ar4orjc0SdbOC
DDkeaid7hJf2cDiAhvkHHa/uzjFkEiS1uFT0RT4Vt7Ir6NuK8YhExudhnmuzq+nkqeWxIk48bLV6
N6TdSwBoYfDZvm4PsJ4=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
YG1Wju7+Sw8pf2ESywntCZKrf+gtSZRqWJyog7Q23z+j0jxbJXXCvtSJXRTs4G2sfX0+DvUgy7E1
0/Kg9uQgs+ZIRs/61dZ5MXW3cPnmbOP8LWozCwUDSYJ7OTXzA4h+56Kl2ZiSXPE6y3ZbQEppQlPV
MSK4lh2rDxOVvtTDsOPcQYvh7d72bPvzA1xFEHSVv+e+bu/SySE5xDXxdzwlF1xyCytmArikXkSj
3gjJ87IUYi62v4j1ERwXe5KiwhDJbdD3c6bp+AJ74gg4uwZ9BaZpdUlt91Hbjm8wi+4yQnVt9Cc0
gHSpqDOW5OmyNw5GCtMJAJfRikLkD0uF/fwTNw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
pSSAm/YfwuJTEeqyxCb/pz8bT6T+D8Hman4CpHnq6tQB1mkRHMqZ87Usd4IE33vZFjaL2s8TSzPlXg1SlWYtXMVNrhTvfyfpqt3tynahy1rtPobmMy7T80Se9AnCCqYeYSSAOkJgJsdo24uToVx2Zs7UyCDtngjsYZvj5bA1VbYaHs4Agq2MFpyUW9AhI//E477/pf+ishPv33ntOORVKuXQwRVWcwZS2p3ZrIvNRJOyoo16r/xq7q1W7Mah1UJM8AMQimv9RjLTa5JD1WxvHLFwg6vY4DGZCQmItOoIgBY3zwVbqe46FhK4NxOI8SbwgRdm00gr5lAL2axk1QLMIg==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 139264)
`pragma protect data_block
Q9XpvHm3ALJqDl0q66mf9DheYwvKLnc8PDP/Ec8eXHBEG2eXlXIjc0nDq2/EslYaxMJOzBY6swOA
Khe8X7BL4Q8MBNuaWPviB4OF259mJNOwRc+ZJCs1tKvgum0aDptL57vY0Sti89spV5/EbIXdL15X
OgTmfO55ZZVSHeEtXEXFtrbHEJ1s4xpVIVkqVwVwX+aa6PSwnsWXxyQ2ubTOGQSzB6gBKzqvPGeX
RHVhP944dWjxXXpQcDoSMhO6hu4Q6b5K9PXdFm+aOIAiaV93xjjqedOikn6DS5tuUJpSiEHYtwFP
PshEeGtMJDjOhvyTsbRHsPcHkIbsm4B7g9BAJzhsTiaOtUnkC4W1qWZLuxXPW2RxIkA5T7RRbEfV
Cjecg07+hKHaxROpk8zigUSbxfAkiXxtGRPAF8OTT8kAO74CUv9wcYus5W+b9m+9s087s71kBb26
FA5j5iOruVGUT2dovdhjBCDCKelSxIBnxHdPG6lp2mCxXqdSX+DttQx2LP5UBkzaaElup6O47XuF
9S0mXSoKddGHrHc/DKJEsHyhX78TnfvJHmy1tT4dRAmsKLncFm08yNK8RqpR/CgxrqMf9uGdctd2
2GigD3GR26s1GaRJF+yzCGb+LfMtvW46ifuNPzJ47W5CDzkG3RqcgUyOG+Fr7Ipeplvh8Pb1KzuJ
+mhWM3q1flbZn7eo7eIvin6qD7MuCxB7iiKGsYeg6f3pBiWK86dmClqrasn4a1pR+aAr22ZlnB1w
3skdnSyHcaKSEbz1XpDJE1HWlQvl4OQiLB01GXUGzwgEqjFYhmxZaqT5qEu1E8SgQeud4hd3/FyH
Nlum4v0v2RFDys07q7jSimcU6gudZCmkr4Zdktzzf4+0xOP5kuMyVjUu9nCoCqGLDAmAYVsxw09f
NT1pyrgoaNi+knGw4zzF8kKc7MMoHob5NhGGIz70SWu/fSKrqEPR2MD6nAtNiEx2mMIQCWI0CbvM
KR7ZLw609BMBIe1m9cxrO2hLNksyHouG8RxXs0svLUTWJEHP+jXI3XuarmAQcV+CaBbFGB0vuBDk
6GhZ1wMiS+iDtjRkTDN8sNg+/43nURiY37/VRDBh5RTCTIwvJKh3JPV/XryPoyLnjKlzo5DogaW7
sjDg4IsGoyhLwZjXZ1p+fYKhLXyI5SaLw9abdtzHtK9nprrCssDooX84Haj8T79XZs1wXvqhtQGB
2TR9coy1aRMYz4//+vNtjNb6bKz4m5Lg2buxdt7Injf7zrgZqHq1y0IyoXTO3uIPOKPH5hvNfcTG
gbVnyVKsCLv36Eff3JWBqwCtsxMyb89bkBxJbPnaeTF0JxG9lPYJaNpcQIsM+TRW/mTkDnfQLN1o
4svlBLSKJxY4Ta2ZM3t7YeWUbiQXI6OU1bHcaJxffRaL0bwN8qWPBH3BrAanvpe+Qd1qucb9g/VI
G9eO5nnmCxx+KcteSPIDSf5XNg47RXWS++4qf7fMfN4P8BUcq0+A2A3cWJjW2+wrHw/DMAcD/E3W
AX7PO1Zy1gie/CMUwq8cyH1pU8Tdx4xDMvXqfd1wGJOktqHGvPmr2LW5Sc7+joGCdvGCL5lJLi7G
s9JV3GYJTd+0z+fkdZ0unesQ2IzvQHvIR8vxAsUiPc0lTVxyjIPlL/P7h3uD10dX/Ep2jwvoWESz
8twsrAMpmqFaLj1DR8LEiKy9EmOzt0rFPT8v0b+pJepNFdxJrfodruhWPy0tqOaSxqe8sZdNSGRk
9YosxFwOwzLciIXpHkN5ef8x9idLpOfAKoR7fXUyj5rD0MlCPcU8YA29/XtbJPZhg6VP48Twj+S6
lfi59BHosvNlRewa3mU0Ss5YlVeTNBIc/HtQC/PjTm+qvg5ZDD1GYSftoFizjheUJBNKLUBhKovR
8I1aK9crKATVLs59w3n4OAfNSlzzQIpExWz2UPyEfhVcUfXC/AvCZnUjhnygsrjg2yWOnqFS9FHE
ex32l++qUPC5hcxPBdixSfnAC3DZgk3TWgCqB9hpXEt8l1MvfguNd347UT+H+35bybhb5xPJlPZD
3c8SsnaIccdTPvb4intBw9uSUW1Lw8n0ao0MflB0ADeyl1CgEEVKEadsN8qIJAxHqdprbz38rcdN
t1oocOf1nQT+3Ki34Vn3mkneYykPwvO4DXibYfJsABNE0lQoazfSvaHV54rUnvhqpeZ03qdZlA6m
RcCm7sowK+tVO80kwWykatovsA+Hj0mqTmHDNjcsutJRjbt6yI2EMOx7oyL4UM3ZlejWxoQiMTFj
ILyGjC644wIDNLSOUYOeCRRVmc+udCwqseD0KX5GAV6x8gEaBoDDx9sc2ayt4FB2EStcdt45DMG0
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hwPml7nVnPSmiEuDRg==
`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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yyK7yA5Bew==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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JAJKvbAxXgufvVvDHnM=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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TwZC5R5XazKkpcxTnEE3AUrLUr7lg0Ku2g2yHQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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N6TdSwBoYfDZvm4PsJ4=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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gHSpqDOW5OmyNw5GCtMJAJfRikLkD0uF/fwTNw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 13920)
`pragma protect data_block
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gt+T1uG4TCr0rKtX287DY/j3YGv+ng/VmmlMXC4fBHwys6jjCGI9HMEAxfSIdPkW8ZPT6ncFAIoO
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obcHoiHiku34n/37KwL5I1ahraxZMbroKeQjxxqs6JEj67KDlCxe8rIIKfNeXUAVInp4YKM+qOrl
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Z+TA3VFkE3LTv+ui
`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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yyK7yA5Bew==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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jU+WJf4/hAKAe83flEiw/PMfMGBy4+ZQEBtgEtPxGXdTiEoLCJBLJQYdgmvt94Y1KsAU42b+AHcc
JAJKvbAxXgufvVvDHnM=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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kanJxRPb9+fHV9uMgJUIUGbixpzjnY0/853fOO2pksYuaseJ+UMeq3Sa5eoZikYforx6PWgQs3nQ
TwZC5R5XazKkpcxTnEE3AUrLUr7lg0Ku2g2yHQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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DDkeaid7hJf2cDiAhvkHHa/uzjFkEiS1uFT0RT4Vt7Ir6NuK8YhExudhnmuzq+nkqeWxIk48bLV6
N6TdSwBoYfDZvm4PsJ4=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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0/Kg9uQgs+ZIRs/61dZ5MXW3cPnmbOP8LWozCwUDSYJ7OTXzA4h+56Kl2ZiSXPE6y3ZbQEppQlPV
MSK4lh2rDxOVvtTDsOPcQYvh7d72bPvzA1xFEHSVv+e+bu/SySE5xDXxdzwlF1xyCytmArikXkSj
3gjJ87IUYi62v4j1ERwXe5KiwhDJbdD3c6bp+AJ74gg4uwZ9BaZpdUlt91Hbjm8wi+4yQnVt9Cc0
gHSpqDOW5OmyNw5GCtMJAJfRikLkD0uF/fwTNw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
pSSAm/YfwuJTEeqyxCb/pz8bT6T+D8Hman4CpHnq6tQB1mkRHMqZ87Usd4IE33vZFjaL2s8TSzPlXg1SlWYtXMVNrhTvfyfpqt3tynahy1rtPobmMy7T80Se9AnCCqYeYSSAOkJgJsdo24uToVx2Zs7UyCDtngjsYZvj5bA1VbYaHs4Agq2MFpyUW9AhI//E477/pf+ishPv33ntOORVKuXQwRVWcwZS2p3ZrIvNRJOyoo16r/xq7q1W7Mah1UJM8AMQimv9RjLTa5JD1WxvHLFwg6vY4DGZCQmItOoIgBY3zwVbqe46FhK4NxOI8SbwgRdm00gr5lAL2axk1QLMIg==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 21008)
`pragma protect data_block
n2ODDhVuXdf4c+fZONBwB/EWCoD1z3CY9TrJN2AEBSZJc6Vy6HZ1WNte037W6zcBefasAelbObuz
phXAS9jIDrehRMl0WYgCyY2T7ALiFyJZO18YKlBqpSu5dRX9YOd6WvUC0GOKb1cZ1kf1njX7dU/F
Gqxu0/eE278PKc6yr9sk9cV1l+p7KNub4be/ctt8TYk+mhaga0x/yJDLtPSyD20BSyXmETvF51pw
iAfOhTYzhGDsXrpkyjLUWgxUYgxhGcaCMZtKZRUYWtP8yqeb5myEIRYDmXPDthK/RceNnwJHXi6j
QjAEQc2tV5OWi1oeJdrbrcneK4Ht9lthCaXW4q3HGBJnwohReS6pRSZrvZFWOLjOFR3FH4Y8juql
D1s7kMhKGASNtO+aNEgei5YpN+z43EHtCMgWmmDO0PpUZ5AyCgxG/VHYQF1ipM+3/7ytY+3fLrqI
d54wAkXWuS/zZeDUodvUQkKwWicGv5t5jUTnSsZRMrkqzVTURGm0zk9aFIWiScnwWuqu15aeANkp
pBBGMLlHmDMFfkbO/IoKpIbgyAxu9AqDPdu2Pld8BWMNTiC5qBmRPCidlQ9u5RiVSIqkWjvPi5KZ
bdBjz2b/yvSHHmTqRkeHmiH+ICP24rPlBeyHHjrZUVyVIJviKzd/olKHRV9k6s7tNw0toLwAnz8U
6QsxhzkPPZno589TBQ2sZZp3sOf89DWcvj5lJC3tRy5Eq2iGgJHTr748+AI/bEWT2n/amgmw6lsN
NRDJUvxdj4+X8cJnM2NpOc4IhQ1cr4XLchjlzKFqbufpuYPiXNY4/vte2hx6HPYAJ0SlDf9hnnh3
uYEHaW0rVLA3x/Fwe6PTDXzOy+0xlQa69IBbB3lCRA0KllThK+W9k+RrH/OvgVG3Qxa+ajmoWnS9
9CRWutFECbe8AmGg4cZI3lfq0AjGJ0jDMmQZdQO3bGNCHJeQVyvot/11psxUJPMGv1+kcHnpv6Wx
LBFepQ1w8Q0YUajrUNsTvuUy5kUbjQANXPalIBiePeaTcrCP/QJSpGTbh6cFr8NMSArVbK+KnKzV
Axna9Wlr7bZ8FIXgjfTu/uSdtLpwJw2S+yftMXVS/YStsmUnFmelCSaaSGllWgkv2LyQ9IkP1z4V
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`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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yyK7yA5Bew==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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JAJKvbAxXgufvVvDHnM=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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TwZC5R5XazKkpcxTnEE3AUrLUr7lg0Ku2g2yHQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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N6TdSwBoYfDZvm4PsJ4=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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gHSpqDOW5OmyNw5GCtMJAJfRikLkD0uF/fwTNw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 3088)
`pragma protect data_block
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nuwch2a7UkPWDbmjTqrFoETjBsQg4ec4noQddZUmqBxAB+q67HA9+UIkfK4+pMZIchwnYrtc/VIN
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hzRFTu026bIP1GDII8THhubBnJbuilQ91q0GW2X08oNM+Z7DvIOprm3YTK84iRx7qrTNxkNVUvcF
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m0cyPRoEt/fERRg60Pdb2eqRyrtmA5ew7wJ4WvSsqDNv0pjJXTBMd2xjVEtQIw4l5W3E/IcaA3LI
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9gIzph0I5Zs9nREuUQeFuZ81ig+0Btz1sDc1YnDvm+e2LVg7thXbD0qWcrz6L8M9z0zsqRZtBzik
hWnTkky0zD5PZcQvYbO9Ky+E4n4wxizDPa9LrSYl2KllFWJzEuHdppkv+FjcarDs+CfLp1w4FsoT
0qrXijE4sqXmaSaIXneyLTorP+4Ujsc9pmolePBZlfZCE3wt3ODBnMOpgK07vJEe9KesZ1kxumjE
ibHQWJO13u+l6YD5L5YCFG1L+CEd+AEGVZY+nhOv38ECOBgZijtcpnUoBbSae5tOOXMLfngh8Zd+
/jRm4nLuGwobNvEITQFKktWKWuBMNoR1dsShZrCwA6QOaSISE9mkRleAbjHjbFIdX23U54E/YIlQ
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pHBJQRMKYUKglfCa8nbFAi56ABhbh7WZt4zciopZ7Lhi6tcnVWeVQghecNc8k1Ef9BidTPJDnOkv
QjPHssbdS8txc93K0La3coCNpy6yTVRGqn2Z2FFAGZ0fgcC4+vP6oqgSaXivaWj989MzXYkA8Unc
DAihtnlCJz9akcWT1suob16IyRxtZGjXcxlVQCrhVOCDcOHn/UrYfaUiFUZpq0RaEA8q2sb7T8F4
DEh7y3eo/Ymozh+d8Wy3XH0v+5eDtvkGLWwP8CsGxCNmZLSCwIihor0JwUvJoaySVJL0MVcqKM0O
Qsgx0pN1oGQ8h2xVBEC5paSe2PYAGHoWBWAuyMdLHEuDsopbT61Z/RiJLU6qvE8hJq5pc2CiN85t
YbAUOsfM0MuymgRUESnKHzvYe6nRjdkhkaoVTgCH79d+WhUt6H+HtFL8sqQxXqUlO5JylejoBMWZ
eJNyUD0Sc1iJOOGeHjN3sSz46P6+MxVYBEOoz6ewF8TCo5HfhCOdPjJRY9iCs+hcVKaRNXc1W3qX
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fDOhsxGKnPn1cI2das/GycO+pgG7KqXbUgDKxHbX5/hIfDTscPDjyqTx/ZbcNpmZtFs0zL8BNRps
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x/B8tYZ+gzIdYwXO2xARClmzv2vMjGePU1KxQ1P0IBRstblUPPjj1oMinqU/9UOh2ItrO8K3OEMt
bh2y/cvyxTYeAO7ZJF+E2cpJueBl+o/TyzhqNlTogXCcZhEt0o8D3MGJ9wWk1gWT8uI+6uynbrMV
2/nw8LXHw2RychDv87V5uFhVDS/C4htHS2bKtm8Ba8KAk/0SFaFvvke3taZsTVjKAdbbf+vB1Bgu
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5mf9GdS/yZw0XOJJc5WMx9WzjARf7usENKAqoLCfePyT0/CyyUJPAiynFTegsfZCDqy4vpHgJaJo
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nltvW1rT31Fg0A==
`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
M2SmFx6fkkMNsI4u7NNl7aD/5cZ3fkE5kQPBpZ49rXFuHYOP7PQ220hPUTmAo+k0itXPZ2akNLv/
yyK7yA5Bew==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
AKjZwm+YMXdWOaulf44bv0xv17we+ivbj8KY1vYY/44NKaTFakpptPVB2ZF4m44dYqRop/VyCmS2
jU+WJf4/hAKAe83flEiw/PMfMGBy4+ZQEBtgEtPxGXdTiEoLCJBLJQYdgmvt94Y1KsAU42b+AHcc
JAJKvbAxXgufvVvDHnM=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
gU79D2mNbtSH4/mbg+y4guWjl7TEJiLvV3VH5t+d/h74FNgAvmd4NwtZ2Vp2jrMDajA+3c6vWVnR
Ukm7o8cx0PFlaLfoOS4+hKpXErAFnCQDevw0be46tMK2AssaXOxfTlGS5XPGGkggS71rLlOmIwDa
4HsVUKtsO/vH7auEgkLCSjZfHbCxir8yb1Ucu3CV6JebDf15N20BIHxoCCFPNurttOaSNgfd2w8U
kanJxRPb9+fHV9uMgJUIUGbixpzjnY0/853fOO2pksYuaseJ+UMeq3Sa5eoZikYforx6PWgQs3nQ
TwZC5R5XazKkpcxTnEE3AUrLUr7lg0Ku2g2yHQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
EnsHmMGyJiGWDrh+ITWL3o1lffFiAubTmD62Oh4g9hvhAZ8g7tB8YBzZM6ZPiv0ar4orjc0SdbOC
DDkeaid7hJf2cDiAhvkHHa/uzjFkEiS1uFT0RT4Vt7Ir6NuK8YhExudhnmuzq+nkqeWxIk48bLV6
N6TdSwBoYfDZvm4PsJ4=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
YG1Wju7+Sw8pf2ESywntCZKrf+gtSZRqWJyog7Q23z+j0jxbJXXCvtSJXRTs4G2sfX0+DvUgy7E1
0/Kg9uQgs+ZIRs/61dZ5MXW3cPnmbOP8LWozCwUDSYJ7OTXzA4h+56Kl2ZiSXPE6y3ZbQEppQlPV
MSK4lh2rDxOVvtTDsOPcQYvh7d72bPvzA1xFEHSVv+e+bu/SySE5xDXxdzwlF1xyCytmArikXkSj
3gjJ87IUYi62v4j1ERwXe5KiwhDJbdD3c6bp+AJ74gg4uwZ9BaZpdUlt91Hbjm8wi+4yQnVt9Cc0
gHSpqDOW5OmyNw5GCtMJAJfRikLkD0uF/fwTNw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
pSSAm/YfwuJTEeqyxCb/pz8bT6T+D8Hman4CpHnq6tQB1mkRHMqZ87Usd4IE33vZFjaL2s8TSzPlXg1SlWYtXMVNrhTvfyfpqt3tynahy1rtPobmMy7T80Se9AnCCqYeYSSAOkJgJsdo24uToVx2Zs7UyCDtngjsYZvj5bA1VbYaHs4Agq2MFpyUW9AhI//E477/pf+ishPv33ntOORVKuXQwRVWcwZS2p3ZrIvNRJOyoo16r/xq7q1W7Mah1UJM8AMQimv9RjLTa5JD1WxvHLFwg6vY4DGZCQmItOoIgBY3zwVbqe46FhK4NxOI8SbwgRdm00gr5lAL2axk1QLMIg==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 13904)
`pragma protect data_block
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MGfGoCH8ys4+8KssLJHKWe7qyVTwXNM7zYZD8UL11VTHho/5Yrb99TF86/YXTlHaYA/jEaKo2qln
JlqfrRquSN4IGdaO5T+6a7hgRYQDqV03bTGO8utjv6JpxkJC9wB1jPpeAlABpNsoS5kUAj3pwKV4
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FgP7FCYZ/HbamIB2sPOSFWzMUGyKKbbsU8UBbNCtrS5+o5LEf9ZXhHy85dIDuykLlWuZcW7N8MIz
B/OGppycesWZgEf1SpeV+V6sgApVw9tOJ5RFjFJ/d/2Y292MtMwHMVu4tJ0da4NIkUVJs+LQ5BIt
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zspXiOS2GJ1t6ip0sCBJQtvmYqdeyffGPRP2B5PKPLUZ5xEr6gwik+AtVMC4UuZkkSTpmrivqhWY
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KS+3czEO9h0fulf2sZzbrVuKMQLl99JB512kD+PtrXfnzpC25izRXywzu64lVQ3F0E2SvMI=
`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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yyK7yA5Bew==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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jU+WJf4/hAKAe83flEiw/PMfMGBy4+ZQEBtgEtPxGXdTiEoLCJBLJQYdgmvt94Y1KsAU42b+AHcc
JAJKvbAxXgufvVvDHnM=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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4HsVUKtsO/vH7auEgkLCSjZfHbCxir8yb1Ucu3CV6JebDf15N20BIHxoCCFPNurttOaSNgfd2w8U
kanJxRPb9+fHV9uMgJUIUGbixpzjnY0/853fOO2pksYuaseJ+UMeq3Sa5eoZikYforx6PWgQs3nQ
TwZC5R5XazKkpcxTnEE3AUrLUr7lg0Ku2g2yHQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
EnsHmMGyJiGWDrh+ITWL3o1lffFiAubTmD62Oh4g9hvhAZ8g7tB8YBzZM6ZPiv0ar4orjc0SdbOC
DDkeaid7hJf2cDiAhvkHHa/uzjFkEiS1uFT0RT4Vt7Ir6NuK8YhExudhnmuzq+nkqeWxIk48bLV6
N6TdSwBoYfDZvm4PsJ4=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
YG1Wju7+Sw8pf2ESywntCZKrf+gtSZRqWJyog7Q23z+j0jxbJXXCvtSJXRTs4G2sfX0+DvUgy7E1
0/Kg9uQgs+ZIRs/61dZ5MXW3cPnmbOP8LWozCwUDSYJ7OTXzA4h+56Kl2ZiSXPE6y3ZbQEppQlPV
MSK4lh2rDxOVvtTDsOPcQYvh7d72bPvzA1xFEHSVv+e+bu/SySE5xDXxdzwlF1xyCytmArikXkSj
3gjJ87IUYi62v4j1ERwXe5KiwhDJbdD3c6bp+AJ74gg4uwZ9BaZpdUlt91Hbjm8wi+4yQnVt9Cc0
gHSpqDOW5OmyNw5GCtMJAJfRikLkD0uF/fwTNw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
pSSAm/YfwuJTEeqyxCb/pz8bT6T+D8Hman4CpHnq6tQB1mkRHMqZ87Usd4IE33vZFjaL2s8TSzPlXg1SlWYtXMVNrhTvfyfpqt3tynahy1rtPobmMy7T80Se9AnCCqYeYSSAOkJgJsdo24uToVx2Zs7UyCDtngjsYZvj5bA1VbYaHs4Agq2MFpyUW9AhI//E477/pf+ishPv33ntOORVKuXQwRVWcwZS2p3ZrIvNRJOyoo16r/xq7q1W7Mah1UJM8AMQimv9RjLTa5JD1WxvHLFwg6vY4DGZCQmItOoIgBY3zwVbqe46FhK4NxOI8SbwgRdm00gr5lAL2axk1QLMIg==
`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 8944)
`pragma protect data_block
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7iRHOx1X1+fJQ24iYmtEEV6vcbk65OewHxYCbQkmbBXMipAEpsJyJBX+bsjIt9rtpa8EVGg/OaYb
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`pragma protect end_protected
`pragma protect begin_protected
`pragma protect version = 1
`pragma protect encrypt_agent = "XILINX"
`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`pragma protect key_block
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yyK7yA5Bew==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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jU+WJf4/hAKAe83flEiw/PMfMGBy4+ZQEBtgEtPxGXdTiEoLCJBLJQYdgmvt94Y1KsAU42b+AHcc
JAJKvbAxXgufvVvDHnM=
`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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TwZC5R5XazKkpcxTnEE3AUrLUr7lg0Ku2g2yHQ==
`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`pragma protect key_block
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N6TdSwBoYfDZvm4PsJ4=
`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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0/Kg9uQgs+ZIRs/61dZ5MXW3cPnmbOP8LWozCwUDSYJ7OTXzA4h+56Kl2ZiSXPE6y3ZbQEppQlPV
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gHSpqDOW5OmyNw5GCtMJAJfRikLkD0uF/fwTNw==
`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-PREC-RSA", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`pragma protect key_block
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`pragma protect key_keyowner = "Synplicity", key_keyname= "SYNP05_001", key_method = "rsa"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 128)
`pragma protect key_block
GAL6r73nw3gdNXPWBHOsXi6p+X2NfKg/dYjrvN90FfvZOZojU+m7CgmuaUCDlJBq/4BeAgE9gvZlQsMgnh9R/HVmMqnUtg7Qbz2wbeo/TZ8MjA/DTTryWOgu2+kud8cDRemu12+koDI1WM/qI4s3WyYnEXaZrUa/Ns3S9VMPS5cu3i/lyM+l8iS4DjBmOIkSL+gjidmkdxvHq4JprCltw7cCNcFeNPK2dcL82GV2nO45aQn5BH9B+XzSR8xw2KlCEbjH2Fu/JIukHYjunaV9/+CwcVUangBtAER0hoA0LaSXqKmwFCrGIYwe2pCtWZfEXvNJ+PbMPvDYC2FvBXAQPg==
`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 64, bytes = 48128)
`pragma protect data_block
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VD0SBqMNeTexxa2HKuwYjkKeu41E6En9LNSNmo0noS0bkoSUBwV+WEpJMutlTSxwBPqVaNDC82dA
mzEfjxH13S2mXF2t89gJ4d/UolbcmVF6VtmZ1InuRphoEcfk0C3njFUgYf4WvRUZxDBj9TgsHFN+
q/Epay6pQpMO19h6UIjqJZ47vpqRSe6DBD52CP1hV7SekQb7gg8uiuLqlTJiqNNOK2WCMmvrBJRn
nsrwRgmUj9xtEMWKzraJ4wOkyy3WnQ0Nt0soEAgyHXVLxodkDN5YjY7vNVq1fOMy3ODRSUHrVhA2
tQkc2oli78pVAVW9LBeDfNSnENWDzUJ4mwe65csj7psgc1tVP03tXbiXT/As4aEF0BCn2kWQ9qxH
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HSP0Wica/q7glstk8EiFTG6FcIuN1vPwHowpruv3tZmaBR/iULAGqhA1WK0T9pxvVYDpZThJLJiB
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6ug2jPubvnNdx+4jZGXh0iGKvGzWvN/oXUzUmvnvMuYpWzH1mWjEqihVQ7bykoWzm6LVmnYrBT6J
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a3b9IkIiA4kQmg4QYZ4PChVGlji5ZMDkJFXBRwFeTs6a/OjepRxX3PXq1qiapNuTI3OBtezXBiZ5
L4xD5UxJT2A/bQiBitaQIAM+b/EC1cS2RfWfLlHOXV5Fv6JGAJB5mgr2i1iWoN7btr5JaNcYZINj
5P5F9gF0Cro2NDvylRbl5AklQ+3VmcnTWOBYKEQT2j6K9CvZfx56ZsBxZZlTk4+Ey9Pj0xd+AwJ1
ovxaelmkBvZguNZd6SNFYoICTjbUyaUSasFgZIrSwrXepLsBfh87NneQLE/1JZ5um2Q0ah8ran4S
wRlCVFpFeh6oFyqc0qR/pqFpKURyf94rIvjnslCcGcNM1bliqV/t4I7SykCTW8Yla01zTNGrCpQl
un8wPZaTI3Vn8LjX4jqYUraGm0rkbIQOoEei4S46vb4ijCXxv6QA5br30LztMYJkWBQTGy7nPl77
krm2wS3/gXaK2bxXDW58+MbN3Lw+CLQJKvRUAcpgL3kZ1N9RbmmFg480WLBPRoNYCfIysMDPAMAO
/ikGWi0scKAfUSYsDPLK41GRejSXivtEOfz3KcsdsqKd6AXbUpcofkfMQjMVynokkiPDFDSYoAXn
TEtbvrMeKkRbssT2THgr4UYJFj+Rn1yaXX0evK3O/zZYaqkc0JunJnJYFy1NqSSeXJ/I8QHmk5B+
LaU6d9SEh4kO7MZU0E/VlhBFQwI=
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module sim_artemis_ddr3_user (
input ddr3_in_clk,
input rst,
output calibration_done,
output usr_clk,
output usr_rst,
inout [7:0] mcb3_dram_dq,
output [13:0] mcb3_dram_a,
output [2:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_reset_n,
output mcb3_dram_cke,
output mcb3_dram_dm,
inout mcb3_rzq,
inout mcb3_zio,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n,
input p0_cmd_clk,
input p0_cmd_en,
input [2:0] p0_cmd_instr,
input [5:0] p0_cmd_bl,
input [29:0] p0_cmd_byte_addr,
output p0_cmd_empty,
output p0_cmd_full,
input p0_wr_clk,
input p0_wr_en,
input [3:0] p0_wr_mask,
input [31:0] p0_wr_data,
output p0_wr_full,
output p0_wr_empty,
output [6:0] p0_wr_count,
output p0_wr_underrun,
output p0_wr_error,
input p0_rd_clk,
input p0_rd_en,
output [31:0] p0_rd_data,
output p0_rd_full,
output p0_rd_empty,
output [6:0] p0_rd_count,
output p0_rd_overflow,
output p0_rd_error,
input p1_cmd_clk,
input p1_cmd_en,
input [2:0] p1_cmd_instr,
input [5:0] p1_cmd_bl,
input [29:0] p1_cmd_byte_addr,
output p1_cmd_empty,
output p1_cmd_full,
input p1_wr_clk,
input p1_wr_en,
input [3:0] p1_wr_mask,
input [31:0] p1_wr_data,
output p1_wr_full,
output p1_wr_empty,
output [6:0] p1_wr_count,
output p1_wr_underrun,
output p1_wr_error,
input p1_rd_clk,
input p1_rd_en,
output [31:0] p1_rd_data,
output p1_rd_full,
output p1_rd_empty,
output [6:0] p1_rd_count,
output p1_rd_overflow,
output p1_rd_error,
input p2_cmd_clk,
input p2_cmd_en,
input [2:0] p2_cmd_instr,
input [5:0] p2_cmd_bl,
input [29:0] p2_cmd_byte_addr,
output p2_cmd_empty,
output p2_cmd_full,
input p2_wr_clk,
input p2_wr_en,
input [3:0] p2_wr_mask,
input [31:0] p2_wr_data,
output p2_wr_full,
output p2_wr_empty,
output [6:0] p2_wr_count,
output p2_wr_underrun,
output p2_wr_error,
input p2_rd_clk,
input p2_rd_en,
output [31:0] p2_rd_data,
output p2_rd_full,
output p2_rd_empty,
output [6:0] p2_rd_count,
output p2_rd_overflow,
output p2_rd_error,
input p3_cmd_clk,
input p3_cmd_en,
input [2:0] p3_cmd_instr,
input [5:0] p3_cmd_bl,
input [29:0] p3_cmd_byte_addr,
output reg p3_cmd_empty,
output reg p3_cmd_full,
input p3_wr_clk,
input p3_wr_en,
input [3:0] p3_wr_mask,
input [31:0] p3_wr_data,
output reg p3_wr_full,
output reg p3_wr_empty,
output reg [6:0] p3_wr_count,
output reg p3_wr_underrun,
output reg p3_wr_error,
input p3_rd_clk,
input p3_rd_en,
output reg [31:0] p3_rd_data,
output reg p3_rd_full,
output reg p3_rd_empty,
output reg [6:0] p3_rd_count,
output reg p3_rd_overflow,
output reg p3_rd_error
);
//Local Parameters
localparam CMD_WRITE = 3'b000;
localparam CMD_READ = 3'b001;
localparam CMD_WRITE_PC = 3'b010;
localparam CMD_READ_PC = 3'b011;
localparam CMD_REFRESH = 3'b100;
//Registers/Wires
//Submodules
//Asynchronous Logic
assign p0_cmd_empty = 1;
assign p0_cmd_full = 0;
assign p0_wr_empty = 1;
assign p0_wr_full = 0;
assign p0_wr_count = 0;
assign p0_wr_underrun = 0;
assign p0_wr_error = 0;
assign p0_rd_data = 0;
assign p0_rd_full = 0;
assign p0_rd_empty = 1;
assign p0_rd_count = 0;
assign p0_rd_overflow = 0;
assign p0_rd_error = 0;
assign p1_cmd_empty = 1;
assign p1_cmd_full = 0;
assign p1_wr_empty = 1;
assign p1_wr_full = 0;
assign p1_wr_count = 0;
assign p1_wr_underrun = 0;
assign p1_wr_error = 0;
assign p1_rd_data = 0;
assign p1_rd_full = 0;
assign p1_rd_empty = 1;
assign p1_rd_count = 0;
assign p1_rd_overflow = 0;
assign p1_rd_error = 0;
assign p2_cmd_empty = 1;
assign p2_cmd_full = 0;
assign p2_wr_empty = 1;
assign p2_wr_full = 0;
assign p2_wr_count = 0;
assign p2_wr_underrun = 0;
assign p2_wr_error = 0;
assign p2_rd_data = 0;
assign p2_rd_full = 0;
assign p2_rd_empty = 1;
assign p2_rd_count = 0;
assign p2_rd_overflow = 0;
assign p2_rd_error = 0;
//Synchronous Logic
reg [5:0] write_data_count;
reg [5:0] read_data_count;
reg [5:0] read_data_size;
reg [1:0] cmd_count;
parameter RAND_MAX_COUNT = 4;
parameter RAND_MAX_LENGTH = 2;
integer write_full_count;
integer full_max_length;
integer full_count;
integer read_empty_count;
integer empty_max_length;
integer empty_count;
initial begin
write_full_count <= $urandom_range((RAND_MAX_COUNT ** 2), 0);
write_full_max_len<= $urandom_range((RAND_MAX_LENGTH ** 2), 0);
read_empty_count <= $urandom_range((RAND_MAX_COUNT ** 2), 0);
empty_max_length <= $urandom_range((RAND_MAX_LENGTH ** 2), 0);
end
always @ (posedge p3_cmd_clk) begin
if (rst) begin
p3_cmd_empty <= 1;
p3_cmd_full <= 0;
cmd_count <= 0;
write_data_count <= 0;
read_data_count <= 0;
p3_wr_full <= 0;
p3_wr_empty <= 1;
p3_wr_count <= 0;
p3_wr_underrun <= 0;
p3_wr_error <= 0;
full_count <= full_max_length;
p3_rd_full <= 0;
p3_rd_empty <= 1;
p3_rd_data <= 0;
p3_rd_count <= 0;
p3_rd_overflow <= 0;
p3_rd_error <= 0;
empty_count <= empty_max_length;
end
else begin
//Command Stuff
p3_cmd_empty <= 1;
p3_cmd_full <= 0;
if (p3_cmd_en && (p3_cmd_instr == CMD_WRITE) || (p3_cmd_instr == CMD_WRITE_PC)) begin
if (write_data_count != p3_cmd_bl) begin
p3_wr_underrun <= 1;
end
write_data_count <= 0;
write_full_count <= $urandom_range((RAND_MAX_COUNT ** 2), 0);
write_full_max_len<= $urandom_range((RAND_MAX_LENGTH ** 2), 0);
end
else if (p3_cmd_en && (p3_cmd_instr == CMD_READ) || (p3_cmd_instr == CMD_READ_PC)) begin
read_data_size <= p3_cmd_bl;
read_data_count <= 0;
end
//Write Stuff
p3_wr_full <= 1;
p3_wr_empty <= 0;
if (full_count < full_max_length) begin
p3_wr_full <= 1;
p3_wr_empty <= 0;
full_count <= full_count + 1;
end
if (p3_wr_en && !p3_wr_full) begin
if (write_data_count[RAND_MAX_COUNT:0] == write_full_count) begin
full_count <= 0;
end
write_data_count <= write_data_count + 1;
end
//Read Stuff
if (read_data_count >= read_data_size) begin
p3_rd_full <= 0;
p3_rd_empty <= 1;
end
else begin
p3_rd_full <= 1;
p3_rd_empty <= 0;
if (empty_count < read_empty_count) begin
p3_rd_full <= 0;
p3_rd_empty <= 1;
empty_count <= empty_count + 1;
end
if (p3_rd_en && !p3_rd_empty) begin
p3_rd_data <= p3_rd_data + 1;
if (p3_rd_data[RAND_MAX_COUNT:0] == read_empty_count) begin
empty_count <= 0;
end
end
end
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2013 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2013.2
// \ \ Description : Xilinx Unified Simulation Library Component
// / /
// /___/ /\ Filename : FRAME_ECCE3.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 05/30/13 - Initial version.
// 02/26/14 - Pulldown all outputs (CR 775504).
// End Revision
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module FRAME_ECCE3
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output CRCERROR,
output ECCERRORNOTSINGLE,
output ECCERRORSINGLE,
output ENDOFFRAME,
output ENDOFSCAN,
output [25:0] FAR,
input [1:0] FARSEL,
input ICAPBOTCLK,
input ICAPTOPCLK
);
pulldown (CRCERROR);
pulldown (ECCERRORNOTSINGLE);
pulldown (ECCERRORSINGLE);
pulldown (ENDOFFRAME);
pulldown (ENDOFSCAN);
pulldown far_net[25:0] (FAR);
tri0 glblGSR = glbl.GSR;
specify
(ICAPBOTCLK *> FAR) = (0:0:0, 0:0:0);
(ICAPBOTCLK => ECCERRORNOTSINGLE) = (0:0:0, 0:0:0);
(ICAPBOTCLK => ECCERRORSINGLE) = (0:0:0, 0:0:0);
(ICAPBOTCLK => ENDOFFRAME) = (0:0:0, 0:0:0);
(ICAPBOTCLK => ENDOFSCAN) = (0:0:0, 0:0:0);
(ICAPTOPCLK *> FAR) = (0:0:0, 0:0:0);
(ICAPTOPCLK => ECCERRORNOTSINGLE) = (0:0:0, 0:0:0);
(ICAPTOPCLK => ECCERRORSINGLE) = (0:0:0, 0:0:0);
(ICAPTOPCLK => ENDOFFRAME) = (0:0:0, 0:0:0);
(ICAPTOPCLK => ENDOFSCAN) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//-------------------------------------------------------------------------
// COPYRIGHT (C) 2016 Univ. of Nebraska - Lincoln
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//-------------------------------------------------------------------------
// Title : aux_io
// Author : Caleb Fangmeier
// Description : Auxillary data input/output for bi-directional communication
// between CalPC and the Host Computer.
//
// $Id$
//-------------------------------------------------------------------------
`default_nettype none
`timescale 1ns / 1ps
module aux_io(
input wire clk,
input wire reset,
//--------------------------------------------------------------------------
//------------------------CONTROL INTERFACE---------------------------------
//--------------------------------------------------------------------------
input wire write_req,
input wire read_req,
input wire [31:0] data_write,
output reg [31:0] data_read,
input wire [25:0] address,
output wire busy,
//--------------------------------------------------------------------------
//---------------------------FP INTERFACE-----------------------------------
//--------------------------------------------------------------------------
input wire okClk,
input wire [112:0] okHE,
output wire [64:0] okEH
);
//----------------------------------------------------------------------------
// Parameters
//----------------------------------------------------------------------------
localparam IDLE = 3'd0,
RD_1 = 3'd1,
RD_2 = 3'd2,
WR_1 = 3'd3;
localparam WR_BLOCK_SIZE = 10'd512,
RD_BLOCK_SIZE = 10'd4;
//----------------------------------------------------------------------------
// Wires
//----------------------------------------------------------------------------
wire [31:0] input_buffer_data;
wire [31:0] input_buffer_q;
reg [31:0] output_buffer_data;
wire [31:0] output_buffer_q;
reg input_buffer_rdreq;
wire input_buffer_wrreq;
wire input_buffer_empty;
wire output_buffer_rdreq;
reg output_buffer_wrreq;
wire output_buffer_full;
wire [12:0] input_buffer_rdusedw;
wire [12:0] input_buffer_wrusedw;
wire [12:0] output_buffer_rdusedw;
wire [12:0] output_buffer_wrusedw;
wire [65*2-1:0] okEHx;
//----------------------------------------------------------------------------
// Registers
//----------------------------------------------------------------------------
reg [2:0] state;
reg busy_int;
reg [31:0] data_write_buffer;
assign input_buffer_empty = (input_buffer_rdusedw == 0);
assign output_buffer_full = output_buffer_wrusedw[12];
assign busy = busy_int | write_req | read_req;
//----------------------------------------------------------------------------
// State Machine
//----------------------------------------------------------------------------
always @(posedge clk ) begin
if ( reset ) begin
busy_int <= 1;
data_write_buffer <= 32'd0;
state <= IDLE;
end
else begin
input_buffer_rdreq <= 0;
output_buffer_wrreq <= 0;
case ( state )
IDLE: begin
data_read <= 32'd0;
busy_int <= 0;
if ( read_req ) begin
case ( address[1:0] )
2'd0: begin
busy_int <= 1;
state <= RD_1;
end
2'd1: begin
data_read <= {19'd0, input_buffer_rdusedw};
end
2'd2: begin
data_read <= {19'd0, output_buffer_wrusedw};
end
endcase
end
else if ( write_req ) begin
busy_int <= 1;
data_write_buffer <= data_write;
state <= WR_1;
end
end
RD_1: begin
if ( !input_buffer_empty ) begin
input_buffer_rdreq <= 1;
state <= RD_2;
end
end
RD_2: begin
data_read <= input_buffer_q;
busy_int <= 0;
state <= IDLE;
end
WR_1: begin
if ( !output_buffer_full ) begin
output_buffer_wrreq <= 1;
output_buffer_data <= data_write_buffer;
/* output_buffer_data <= {19'd0, output_buffer_wrusedw}; */
busy_int <= 0;
state <= IDLE;
end
end
endcase
end
end
okWireOR # (.N(2)) wireOR (okEH, okEHx);
// 32 bit wide 1024 depth fifo
fifo32_clk_crossing_with_usage output_buffer (
.wrclk ( clk ),
.rdclk ( okClk ),
.aclr ( reset ),
.data ( output_buffer_data),
.q ( output_buffer_q ),
.wrreq ( output_buffer_wrreq ),
.rdreq ( output_buffer_rdreq ),
.rdusedw ( output_buffer_rdusedw ),
.wrusedw ( output_buffer_wrusedw )
);
okBTPipeOut pipeout_inst(
.okHE ( okHE ),
.okEH ( okEHx[64:0] ),
.ep_addr ( 8'hA0 ),
/* .ep_datain ( {19'd0, output_buffer_rdusedw} ), */
.ep_datain ( output_buffer_q ),
.ep_read ( output_buffer_rdreq ),
.ep_blockstrobe ( ),
.ep_ready ( output_buffer_rdusedw >= RD_BLOCK_SIZE )
);
// 32 bit wide 1024 depth fifo
fifo32_clk_crossing_with_usage input_buffer (
.wrclk ( okClk ),
.rdclk ( clk ),
.aclr ( reset ),
.data ( input_buffer_data),
.q ( input_buffer_q ),
.wrreq ( input_buffer_wrreq ),
.rdreq ( input_buffer_rdreq ),
.wrusedw ( input_buffer_wrusedw ),
.rdusedw ( input_buffer_rdusedw )
);
okBTPipeIn pipein_inst(
.okHE ( okHE ),
.okEH ( okEHx[129:65] ),
.ep_addr (8'h80 ),
.ep_dataout ( input_buffer_data),
.ep_write ( input_buffer_wrreq ),
.ep_blockstrobe ( ),
.ep_ready ( input_buffer_wrusedw >= WR_BLOCK_SIZE )
);
endmodule
|
module CoProcessor0RF(clk, din, wEn, regNum, sel, dout, npc_out, expiaddr, ins);
input clk;
input [1:0] wEn;
input [4:0] regNum;
input [2:0] sel;
input [31:0] din;
input [31:0] ins;
input [31:0] npc_out;
output [31:0] dout;
output reg [31:0] expiaddr;
reg [31:0] coprf [0:31];
wire [5:0] op;
wire [5:0] func;
wire [4:0] mf_tc0_eret;
assign op = ins[31:26];
assign mf_tc0_eret = ins[25:21];
assign func = ins[5:0];
// op
parameter R = 6'b000000,
MTC0_MFC0_ERET = 6'b010000;
// Function code.
parameter SYSCALL = 6'b001100;
// MTC0_MFC0_ERET
parameter MTC0 = 5'b00100,
MFC0 = 5'b00000,
ERET = 5'b10000;
initial begin
coprf[12] = 32'h0000_0000;// Status
coprf[13] = 32'h0000_0000;// Cause
coprf[14] = 32'h0000_3000;// EPC
end
assign dout = coprf[regNum];
always @ (posedge clk) begin
if (wEn) begin
if ((op == R) && (func == SYSCALL)) begin// SYSCALL
coprf[14] <= npc_out - 3'b100;
coprf[13][6:2] <= 5'b01000;
coprf[12][1] <= 1'b1;
expiaddr <= 32'h0000_3000;
end else if ((op == MTC0_MFC0_ERET) && (mf_tc0_eret == ERET)) begin// ERET
coprf[12][1] <= 1'b0;
expiaddr <= coprf[14][31:0];
end else begin// MTC0
coprf[regNum] <= din;
end
end
end
endmodule // CoProcessor 0 Register File;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__OR3_1_V
`define SKY130_FD_SC_HVL__OR3_1_V
/**
* or3: 3-input OR.
*
* Verilog wrapper for or3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__or3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__or3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__or3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__or3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__OR3_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SEDFXBP_PP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O311AI_0_V
`define SKY130_FD_SC_LP__O311AI_0_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311ai_0 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o311ai_0 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O311AI_0_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////////////////
// Engineer: Jonathan Whitaker
//
// Create Date: 17:43:13 04/07/2014
// Module Name: cpu_controller
// Description: This verilog module implements a 4-bit CPUs controller unit.
//
////////////////////////////////////////////////////////////////////////////////////////////
module cpu_controller(clk, clr, btn, usr_inst, rom_inst, En, rom_done, LEDRegEn, Rin, Rout,
Ain, Gin, Gout, load_usr, load_rom, usr_Data, rom_Data, ALUOp, inst_done);
// Inputs.
input clk, clr, En, rom_done;
input [7:0] usr_inst; // The incoming instruction from the user.
input [7:0] rom_inst; // The incoming instruction from the ROM.
input [1:0] btn; // Selects user mode (01) or run mode (10).
// Outputs.
output reg LEDRegEn, Ain, Gin, Gout, load_usr, load_rom, inst_done;
output reg [3:0] Rin, Rout;
output reg [1:0] ALUOp;
output [3:0] usr_Data, rom_Data;
// Declare the 15 state parameters.
//*********************************
parameter idle = 4'b0000,
usr_mode = 4'b0001,
usr_load = 4'b0010,
usr_str = 4'b0011,
usr_mv = 4'b0100,
usr_aluop = 4'b0101,
usr_aluwr = 4'b0110,
run_mode = 4'b0111,
run_fetch = 4'b1000,
run_exec = 4'b1001,
run_load = 4'b1010,
run_str = 4'b1011,
run_mv = 4'b1100,
run_aluop = 4'b1101,
run_aluwr = 4'b1110;
//*********************************
reg [3:0] PS, NS;
// Assign the user instruction parameters.
wire [1:0] usr_opcode, usr_Rx, usr_Ry, usr_funct;
wire [3:0] usr_Data;
assign usr_opcode = usr_inst[7:6];
assign usr_Rx = usr_inst[5:4];
assign usr_Ry = usr_inst[3:2];
assign usr_Data = usr_inst[3:0];
assign usr_funct = usr_inst[1:0];
// Assign the rom instruction parameters.
wire [1:0] rom_opcode, rom_Rx, rom_Ry, rom_funct;
wire [3:0] rom_Data;
assign rom_opcode = rom_inst[7:6];
assign rom_Rx = rom_inst[5:4];
assign rom_Ry = rom_inst[3:2];
assign rom_Data = rom_inst[3:0];
assign rom_funct = rom_inst[1:0];
// NS
always@(*)
if(En)
case(PS)
idle: NS = btn[0] ? usr_mode: (btn[1] ? run_mode: idle);
// User mode.
usr_mode:
if(btn[0])
NS = usr_mode;
else
case(usr_opcode)
0: NS = usr_load;
1: NS = usr_str;
2: NS = usr_mv;
3: NS = usr_aluop;
default:
NS = usr_mode;
endcase
usr_load: NS = idle;
usr_str: NS = idle;
usr_mv: NS = idle;
usr_aluop: NS = usr_aluwr;
usr_aluwr: NS = idle;
// Run mode.
run_mode:
if(btn[1])
NS = run_mode;
else
NS = run_fetch;
run_fetch: NS = rom_done ? idle: run_exec;
run_exec:
case(rom_opcode)
0: NS = run_load;
1: NS = run_str;
2: NS = run_mv;
3: NS = run_aluop;
default:
NS = run_exec;
endcase
run_load: NS = rom_done ? idle: run_fetch;
run_str: NS = rom_done ? idle: run_fetch;
run_mv: NS = rom_done ? idle: run_fetch;
run_aluop: NS = run_aluwr;
run_aluwr: NS = rom_done ? idle: run_fetch;
default: NS = idle;
endcase
else
NS = idle;
// PS
always@(posedge clk)
if(clr) PS <= idle;
else PS <= NS;
// Control line outputs
always@(*)
begin
LEDRegEn = 1'b0;
Ain = 1'b0;
load_usr = 1'b0; load_rom = 1'b0;
inst_done = 1'b0;
Gin = 1'b0; Gout = 1'b0;
Rin = 4'b0000; Rout = 4'b0000;
ALUOp = 2'b00;
case(PS)
// user mode outputs.
//*********************************
usr_mode:
begin
// A <- [Rx]
case(usr_Rx)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
Ain = 1'b1;
end
usr_load:
begin
load_usr = 1'b1;
case(usr_Rx)
0: Rin[0] = 1'b1;
1: Rin[1] = 1'b1;
2: Rin[2] = 1'b1;
3: Rin[3] = 1'b1;
default:;
endcase
end
usr_str:
begin
LEDRegEn = 1'b1;
case(usr_Rx)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
end
usr_mv:
begin
case(usr_Ry)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
case(usr_Rx)
0: Rin[0] = 1'b1;
1: Rin[1] = 1'b1;
2: Rin[2] = 1'b1;
3: Rin[3] = 1'b1;
default:;
endcase
end
usr_aluop:
begin
// Bus <- [Ry]
case(usr_Ry)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
ALUOp = usr_funct;
Gin = 1'b1;
end
usr_aluwr:
begin
Gout = 1'b1;
case(usr_Rx)
0: Rin[0] = 1'b1;
1: Rin[1] = 1'b1;
2: Rin[2] = 1'b1;
3: Rin[3] = 1'b1;
default:;
endcase
end
//*********************************
// run mode outputs.
//*********************************
run_exec:
begin
// A <- [Rx]
case(rom_Rx)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
Ain = 1'b1;
end
run_load:
begin
load_rom = 1'b1;
case(rom_Rx)
0: Rin[0] = 1'b1;
1: Rin[1] = 1'b1;
2: Rin[2] = 1'b1;
3: Rin[3] = 1'b1;
default:;
endcase
// Indicate the instruction has finished.
inst_done = 1'b1;
end
run_str:
begin
LEDRegEn = 1'b1;
case(rom_Rx)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
// Indicate the instruction has finished.
inst_done = 1'b1;
end
run_mv:
begin
case(rom_Ry)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
case(rom_Rx)
0: Rin[0] = 1'b1;
1: Rin[1] = 1'b1;
2: Rin[2] = 1'b1;
3: Rin[3] = 1'b1;
default:;
endcase
// Indicate the instruction has finished.
inst_done = 1'b1;
end
run_aluop:
begin
// Bus <- [Ry]
case(rom_Ry)
0: Rout[0] = 1'b1;
1: Rout[1] = 1'b1;
2: Rout[2] = 1'b1;
3: Rout[3] = 1'b1;
default:;
endcase
ALUOp = rom_funct;
Gin = 1'b1;
end
run_aluwr:
begin
Gout = 1'b1;
case(rom_Rx)
0: Rin[0] = 1'b1;
1: Rin[1] = 1'b1;
2: Rin[2] = 1'b1;
3: Rin[3] = 1'b1;
default:;
endcase
// Indicate the instruction has finished.
inst_done = 1'b1;
end
default:;
endcase
//*********************************
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR3B_1_V
`define SKY130_FD_SC_HDLL__NOR3B_1_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog wrapper for nor3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__nor3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_1 (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__nor3b_1 (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__nor3b base (
.Y(Y),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR3B_1_V
|
`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
module arbiter_bench();
// Clock
reg clk_i; // master clock reg
// Interface against the wbm read module
wire master_busy_o;
wire read_request_o;
wire [31:2] addr_o;
wire [3:0] sel_o;
reg [31:0] dat_i;
reg ack_i;
// Interface against masters (clip)
reg m0_read_request_i;
reg [31:2] m0_addr_i;
reg [3:0] m0_sel_i;
wire [31:0] m0_dat_o;
wire m0_ack_o;
// Interface against masters (fragment processor)
reg m1_read_request_i;
reg [31:2] m1_addr_i;
reg [3:0] m1_sel_i;
wire [31:0] m1_dat_o;
wire m1_ack_o;
// Interface against masters (blender)
reg m2_read_request_i;
reg [31:2] m2_addr_i;
reg [3:0] m2_sel_i;
wire [31:0] m2_dat_o;
wire m2_ack_o;
initial begin
$dumpfile("arbiter.vcd");
$dumpvars(0,arbiter_bench);
// init values
clk_i = 0;
dat_i = 32'h12345678;
ack_i = 0;
m0_read_request_i = 0;
m0_addr_i = 10;
m0_sel_i = 0;
m1_read_request_i = 0;
m1_addr_i = 20;
m1_sel_i = 8;
m2_read_request_i = 0;
m2_addr_i = 30;
m2_sel_i = 8;
#10 m0_read_request_i = 1;
#10 m0_read_request_i = 0;
#10 m1_read_request_i = 1;
#10 m1_read_request_i = 0;
#10 m1_read_request_i = 1;
m0_read_request_i = 1;
#10 m1_read_request_i = 0;
#10 m0_read_request_i = 0;
//timing
#100 $finish;
end
always @(posedge clk_i)
begin
ack_i <= #1 read_request_o;
end
always begin
#1 clk_i = ~clk_i;
end
gfx_wbm_read_arbiter arbiter(
.master_busy_o (master_busy_o),
// Interface against the wbm read module
.read_request_o (read_request_o),
.addr_o (addr_o),
.sel_o (sel_o),
.dat_i (dat_i),
.ack_i (ack_i),
// Interface against masters (clip)
.m0_read_request_i (m0_read_request_i),
.m0_addr_i (m0_addr_i),
.m0_sel_i (m0_sel_i),
.m0_dat_o (m0_dat_o),
.m0_ack_o (m0_ack_o),
// Interface against masters (fragment processor)
.m1_read_request_i (m1_read_request_i),
.m1_addr_i (m1_addr_i),
.m1_sel_i (m1_sel_i),
.m1_dat_o (m1_dat_o),
.m1_ack_o (m1_ack_o),
// Interface against masters (blender)
.m2_read_request_i (m2_read_request_i),
.m2_addr_i (m2_addr_i),
.m2_sel_i (m2_sel_i),
.m2_dat_o (m2_dat_o),
.m2_ack_o (m2_ack_o)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_SYMBOL_V
`define SKY130_FD_SC_LP__LSBUFISO1P_SYMBOL_V
/**
* lsbufiso1p: ????.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__lsbufiso1p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input SLEEP
);
// Voltage supply signals
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21BA_2_V
`define SKY130_FD_SC_MS__O21BA_2_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ba_2 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21BA_2_V
|
`timescale 1ns / 1ps
/**
* C_PWM_CNT_WIDTH: 16bits, [0,65535], if using mV as units, range to 65V
* with 150M clock, 60K denominator means 0.4ms, frequency: 2.5kHZ,
* climbing time can reach 60K * 60K / 150M = 25s.
* if inc/dec has 32bits (16bits fractional part), climbing time can reach
* 25s * 60K = 40hours
*/
module DISCHARGE_ctl #
(
parameter integer C_DEFAULT_VALUE = 0,
parameter integer C_PWM_CNT_WIDTH = 16,
parameter integer C_FRACTIONAL_WIDTH = 16,
parameter integer C_NUMBER_WIDTH = 32
) (
input wire clk,
input wire resetn,
output wire def_val,
output wire exe_done,
input wire [C_PWM_CNT_WIDTH-1:0] denominator, // >= 3
input wire [C_PWM_CNT_WIDTH-1:0] numerator0,
input wire [C_PWM_CNT_WIDTH-1:0] numerator1,
input wire [C_NUMBER_WIDTH-1:0] number0,
input wire [C_NUMBER_WIDTH-1:0] number1,
input wire [C_PWM_CNT_WIDTH+C_FRACTIONAL_WIDTH-1:0] inc0,
output wire o_resetn,
output wire drive
);
localparam integer STATE_IDLE = 0;
localparam integer STATE_PRE = 1;
localparam integer STATE_INC = 2;
localparam integer STATE_KEEP = 3;
reg[1:0] pwm_state;
assign def_val = C_DEFAULT_VALUE;
assign o_resetn = resetn;
reg[C_PWM_CNT_WIDTH+C_FRACTIONAL_WIDTH-1:0] numerator_ext;
reg[C_PWM_CNT_WIDTH-1:0] cnt;
reg eop; // end of period
reg eop_p1;
always @ (posedge clk) begin
if (resetn == 0)
cnt <= 0;
else begin
if (cnt == 0)
cnt <= denominator - 1;
else
cnt <= cnt - 1;
end
end
always @ (posedge clk) begin
if (resetn == 0)
eop_p1 <= 0;
else if (eop_p1)
eop_p1 <= 0;
else if (cnt == 2)
eop_p1 <= 1;
end
always @ (posedge clk) begin
if (resetn == 0)
eop <= 0;
else
eop <= eop_p1;
end
reg out_drive;
assign drive = out_drive;
wire[C_PWM_CNT_WIDTH-1:0] numerator;
assign numerator = numerator_ext[C_PWM_CNT_WIDTH+C_FRACTIONAL_WIDTH-1:C_FRACTIONAL_WIDTH];
always @ (posedge clk) begin
if (resetn == 0)
out_drive <= C_DEFAULT_VALUE;
else if (pwm_state != STATE_IDLE) begin
if (cnt == 0) begin
if (numerator != denominator)
out_drive <= ~C_DEFAULT_VALUE;
end
else if (cnt == numerator)
out_drive <= C_DEFAULT_VALUE;
end
end
reg[C_NUMBER_WIDTH-1:0] peroid_cnt;
always @ (posedge clk) begin
if (resetn == 0)
pwm_state <= STATE_IDLE;
else if (eop_p1 && ~exe_done) begin
case (pwm_state)
STATE_IDLE:
pwm_state <= STATE_PRE;
STATE_PRE: begin
if (peroid_cnt <= 1) begin
pwm_state <= STATE_INC;
end
end
STATE_INC: begin
if (numerator <= numerator1) begin
pwm_state <= STATE_KEEP;
end
end
STATE_KEEP: begin
if (peroid_cnt <= 1) begin
pwm_state <= STATE_IDLE;
end
end
endcase
end
end
always @ (posedge clk) begin
if (resetn == 0)
numerator_ext <= 0;
else if (eop_p1 && ~exe_done) begin
case (pwm_state)
STATE_IDLE: begin
numerator_ext <= {numerator0, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= number0;
end
STATE_PRE: begin
numerator_ext <= {numerator0, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= peroid_cnt - 1;
end
STATE_INC: begin
if (numerator <= numerator1) begin
numerator_ext <= {numerator1, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= number1;
end
else begin
numerator_ext <= numerator_ext - inc0;
peroid_cnt <= 0;
end
end
STATE_KEEP: begin
numerator_ext <= {numerator1, {(C_FRACTIONAL_WIDTH){1'b0}}};
peroid_cnt <= peroid_cnt - 1;
end
endcase
end
end
reg end_of_transaction;
assign exe_done = end_of_transaction;
always @ (posedge clk) begin
if (resetn == 0)
end_of_transaction <= 0;
else if (eop_p1 && pwm_state == STATE_KEEP && peroid_cnt <= 1)
end_of_transaction <= 1;
end
endmodule
|
`default_nettype none
module gci_std_display_request_controller #(
parameter P_AREA_H = 640,
parameter P_AREA_V = 480,
parameter P_AREAA_HV_N = 19,
parameter P_MEM_ADDR_N = 23
)(
input wire iCLOCK,
input wire inRESET,
//BUS
input wire iRQ_VALID,
output wire oRQ_BUSY,
input wire [P_MEM_ADDR_N-1:0] iRQ_ADDR,
input wire [23:0] iRQ_DATA,
//VRAM
output wire oRQ_VALID,
input wire iRQ_BUSY,
output wire [23:0] oRQ_DATA,
//New
output wire oIF_REQ,
input wire iIF_ACK,
output wire oIF_FINISH,
input wire iIF_BREAK,
input wire iIF_BUSY,
output wire oIF_ENA,
output wire oIF_RW,
output wire [P_MEM_ADDR_N-1:0] oIF_ADDR,
output wire [7:0] oIF_R,
output wire [7:0] oIF_G,
output wire [7:0] oIF_B,
input wire iIF_VALID,
output wire oIF_BUSY,
input wire [31:0] iIF_DATA
);
assign oBUSMOD_WAIT = reqfifo_wr_full;
wire request_break_condition = iIF_BREAK || ;
wire reqfifo_read_condition =
gci_std_sync_fifo #(24, 16, 4) VRAM_REQ_FIFO(
.inRESET(inRESET),
.iREMOVE(1'b0),
.iCLOCK(iCLOCK),
.iWR_EN(iRQ_VALID && !read_fifo_wr_full),
.iWR_DATA(iIF_DATA[23:0]),
.oWR_FULL(read_fifo_wr_full),
.oWR_ALMOST_FULL(),
.iRD_EN(!read_fifo_rd_empty && !iRQ_BUSY),
.oRD_DATA(read_fifo_rd_data),
.oRD_EMPTY(read_fifo_rd_empty)
);
localparam P_L_MAIN_STT_IDLE = 3'h0;
localparam P_L_MAIN_STT_IF_REQ = 3'h1;
localparam P_L_MAIN_STT_IF_WORK = 3'h2;
localparam P_L_MAIN_STT_IF_READ_WAIT = 3'h3;
localparam P_L_MAIN_STT_IF_END = 3'h4;
reg [2:0] b_main_state;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
else begin
case(b_main_state)
P_L_MAIN_STT_IDLE:
begin
if(iRQ_VALID)begin
b_main_state <= P_L_MAIN_STT_IF_REQ;
end
end
P_L_MAIN_STT_IF_REQ:
begin
if(iIF_ACK)begin
b_main_state <= P_L_MAIN_STT_IF_WORK;
end
end
P_L_MAIN_STT_IF_WORK:
begin
if(request_break_condition)begin
b_main_state <= P_L_MAIN_STT_IF_END;
end
else if()begin
b_main_state <= P_L_MAIN_STT_IF_READ_WAIT;
end
end
P_L_MAIN_STT_IF_READ_WAIT:
begin
if(iIF_VALID && !read_fifo_wr_full)begin
b_main_state <= P_L_MAIN_STT_IF_END;
end
end
P_L_MAIN_STT_IF_END:
begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
default:
begin
b_main_state <= P_L_MAIN_STT_IDLE;
end
endcase
end
end //main(vram-interface) state always
wire read_fifo_wr_full;
wire read_fifo_rd_empty;
wire [23:0] read_fifo_rd_data;
gci_std_sync_fifo #(24, 4, 2) VRAM_RESULT_FIFO(
.inRESET(inRESET),
.iREMOVE(1'b0),
.iCLOCK(iCLOCK),
.iWR_EN(iIF_VALID && !read_fifo_wr_full),
.iWR_DATA(iIF_DATA[23:0]),
.oWR_FULL(read_fifo_wr_full),
.oWR_ALMOST_FULL(),
.iRD_EN(!read_fifo_rd_empty && !iRQ_BUSY),
.oRD_DATA(read_fifo_rd_data),
.oRD_EMPTY(read_fifo_rd_empty)
);
assign oRQ_VALID = !read_fifo_rd_empty && !iRQ_BUSY;
assign oRQ_DATA = read_fifo_rd_data;
assign oIF_BUSY = read_fifo_wr_full;
/***************************************************
Assertion
***************************************************/
/*
`ifdef GCI_STD_DISP_SVA_ASSERTION
proterty PRO_FIFO_NEVER_NOT_FULL;
@(posedge iCLOCK) disable iff (!inRESET) (!read_fifo_wr_full);
endproperty
assert property(PRO_FIFO_NEVER_NOT_FULL);
`endif
*/
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Anton Potocnik
//
// Create Date: 07.01.2017 22:50:51
// Design Name:
// Module Name: frequency_counter
// Project Name:
// Target Devices:
// Tool Versions:
// Description: Reciprotial method
//
// Dependencies:
//
// Revision:
// Revision 0.1 - Reciprotial method implemented
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module frequency_counter #
(
parameter ADC_WIDTH = 14,
parameter AXIS_TDATA_WIDTH = 32,
parameter COUNT_WIDTH = 32,
parameter HIGH_THRESHOLD = -100,
parameter LOW_THRESHOLD = -150
)
(
(* X_INTERFACE_PARAMETER = "FREQ_HZ 125000000" *)
input [AXIS_TDATA_WIDTH-1:0] S_AXIS_IN_tdata,
input S_AXIS_IN_tvalid,
input clk,
input rst,
input [COUNT_WIDTH-1:0] Ncycles,
output [AXIS_TDATA_WIDTH-1:0] M_AXIS_OUT_tdata,
output M_AXIS_OUT_tvalid,
output [COUNT_WIDTH-1:0] counter_output
);
wire signed [ADC_WIDTH-1:0] data;
reg state, state_next;
reg [COUNT_WIDTH-1:0] counter=0, counter_next=0;
reg [COUNT_WIDTH-1:0] counter_output=0, counter_output_next=0;
reg [COUNT_WIDTH-1:0] cycle=0, cycle_next=0;
// Wire AXIS IN to AXIS OUT
assign M_AXIS_OUT_tdata[ADC_WIDTH-1:0] = S_AXIS_IN_tdata[ADC_WIDTH-1:0];
assign M_AXIS_OUT_tvalid = S_AXIS_IN_tvalid;
// Extract only the 14-bits of ADC data
assign data = S_AXIS_IN_tdata[ADC_WIDTH-1:0];
// Handling of the state buffer for finding signal transition at the threshold
always @(posedge clk)
begin
if (~rst)
state <= 1'b0;
else
state <= state_next;
end
always @* // logic for state buffer
begin
if (data > HIGH_THRESHOLD)
state_next = 1;
else if (data < LOW_THRESHOLD)
state_next = 0;
else
state_next = state;
end
// Handling of counter, counter_output and cycle buffer
always @(posedge clk)
begin
if (~rst)
begin
counter <= 0;
counter_output <= 0;
cycle <= 0;
end
else
begin
counter <= counter_next;
counter_output <= counter_output_next;
cycle <= cycle_next;
end
end
always @* // logic for counter, counter_output, and cycle buffer
begin
counter_next = counter + 1; // increment on each clock cycle
counter_output_next = counter_output;
cycle_next = cycle;
if (state < state_next) // high to low signal transition
begin
cycle_next = cycle + 1; // increment on each signal transition
if (cycle >= Ncycles-1)
begin
counter_next = 0;
counter_output_next = counter;
cycle_next = 0;
end
end
end
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Channel Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module lab3_master_0_p2b_adapter (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
output reg in_ready,
input in_valid,
input [ 7: 0] in_data,
input in_startofpacket,
input in_endofpacket,
// Interface: out
input out_ready,
output reg out_valid,
output reg [ 7: 0] out_data,
output reg out_startofpacket,
output reg out_endofpacket,
output reg [ 7: 0] out_channel
);
reg in_channel = 0;
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_ready = out_ready;
out_valid = in_valid;
out_data = in_data;
out_startofpacket = in_startofpacket;
out_endofpacket = in_endofpacket;
out_channel = 0;
out_channel = in_channel;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21AI_4_V
`define SKY130_FD_SC_MS__O21AI_4_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog wrapper for o21ai with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ai_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21ai_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21AI_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__INPUTISO1N_TB_V
`define SKY130_FD_SC_LP__INPUTISO1N_TB_V
/**
* inputiso1n: Input isolation, inverted sleep.
*
* X = (A & SLEEP_B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__inputiso1n.v"
module top();
// Inputs are registered
reg A;
reg SLEEP_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
SLEEP_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 SLEEP_B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 SLEEP_B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 SLEEP_B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 SLEEP_B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 SLEEP_B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__inputiso1n dut (.A(A), .SLEEP_B(SLEEP_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__INPUTISO1N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__HA_PP_SYMBOL_V
`define SKY130_FD_SC_LS__HA_PP_SYMBOL_V
/**
* ha: Half adder.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__ha (
//# {{data|Data Signals}}
input A ,
input B ,
output COUT,
output SUM ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__HA_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_6_V
`define SKY130_FD_SC_HD__BUF_6_V
/**
* buf: Buffer.
*
* Verilog wrapper for buf with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__buf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_6 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__buf_6 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__buf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_6_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu Jun 01 11:35:05 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/system_vga_overlay_0_0_stub.v
// Design : system_vga_overlay_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_overlay,Vivado 2016.4" *)
module system_vga_overlay_0_0(clk, rgb_0, rgb_1, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_0[23:0],rgb_1[23:0],rgb[23:0]" */;
input clk;
input [23:0]rgb_0;
input [23:0]rgb_1;
output [23:0]rgb;
endmodule
|
`timescale 1ns / 1ps
// ***************** DAQ_sequencer ******************************************
//
// Modified for 9 channel
//
// Clocked at 40MHz
//
// This module is a state machine to control the sequence in which the various
// structures holding data for the DAQ stream are enabled.
//
// It Waits idle until it detects the falling edge of the store_strb. At this
// point all data for the pulse have been collected and are ready to transmit
// over the UART.
//
// The module can write values directly to the UART for framing and timestamp purposes,
// monitoring until the values are transmited.
//
// A 7-bit counter is implemented which increments every 40ms. The value of
// this counter is transmitted at the start of each pulse to provide a timestamp
//
// It can also enable the DAQ_RAMs and monitor until they have exposed all of
// data. To enable a DAQ_RAM, trans_en is taken high. The appropriate DAQ_RAM
// output must be connected to the UART externally by multiplexing based on trans_state
// Once that DAQ_RAM has finished, trans_done goes high and the state increments
//
// When all data have finally been transmitted, a reset signal is sent to the DAQ_RAMS
// Reset is also sent when the sequencer module is itself reset
module DAQ_sequencer2(
clk40,
rst,
strobe,
poll_uart,
trans_done,
`ifdef LUTRAMreadout
LUTRAMreadout,
`endif
//num_chans_a,
num_chans,
trans_state,
trans_en,
rst_out,
trig_rdy,
rs232_tx_empty,
rs232_tx_buffer,
rs232_tx_ld
);
input clk40;
input rst;
input strobe;
input poll_uart;
`ifdef LUTRAMreadout
input LUTRAMreadout;
parameter TRANS_STATE_WIDTH = 6;
`else
parameter TRANS_STATE_WIDTH = 5;
`endif
input trans_done;
input rs232_tx_empty;
//input [8:0] num_chans_a;
input [8:0] num_chans;
output reg [TRANS_STATE_WIDTH-1:0] trans_state = {TRANS_STATE_WIDTH{1'd0}};
output reg trans_en = 1'b0;
output reg rst_out = 1'b0;
output reg trig_rdy = 1'b0;
//output [7:0] rs232_tx_buffer;
output reg [6:0] rs232_tx_buffer = 7'd0;
output reg rs232_tx_ld = 1'b0;
//reg [8:0] num_chans = 9'b111111111;
// Internal registers
//reg [5:0] trans_state;
//reg trans_en;
//reg rst_out;
//reg rs232_tx_ld = 0;
reg rs232_tx_pending = 1'b0;
//reg [7:0] rs232_tx_buffer;
//reg [6:0] count_40ms;
reg [6:0] count_40ms = 7'd0;
reg strobe_a = 1'b0;
reg strobe_b = 1'b0;
reg rs232_tx_empty_a = 1'b0;
reg rs232_tx_empty_b = 1'b0;
// State parameterisation
parameter [TRANS_STATE_WIDTH-1:0] TRANS_WAIT = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd0};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_STAMP_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd1};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_STAMP = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd2};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P1_XDIF_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd3};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P1_XDIF = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd4};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P1_YDIF_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd5};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P1_YDIF = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd6};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P1_SUM_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd7};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P1_SUM = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd8};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P2_XDIF_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd9};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P2_XDIF = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd10};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P2_YDIF_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd11};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P2_YDIF = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd12};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P2_SUM_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd13};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P2_SUM = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd14};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P3_XDIF_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd15};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P3_XDIF = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd16};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P3_YDIF_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd17};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P3_YDIF = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd18};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P3_SUM_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd19};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_P3_SUM = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd20};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_DAC_K1_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd21};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_DAC_K1 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd22};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_DAC_K2_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd23};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_DAC_K2 = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd24};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_357_RB_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd25};
//parameter [TRANS_STATE_WIDTH-1:0] TRANS_357_RB = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd26};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_40_RB_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd27};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_40_RB = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd28};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_MON_RB_FRAME = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd29};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_MON_RB = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd30};
`ifdef LUTRAMreadout
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K1P2_FRAME = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd31};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K1P2 = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd32};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K1P3_FRAME = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd33};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K1P3 = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd34};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K2P2_FRAME = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd35};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K2P2 = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd36};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K2P3_FRAME = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd37};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_K2P3 = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd38};
parameter [TRANS_STATE_WIDTH-1:0] TRANS_TERM_BYTE = {{(TRANS_STATE_WIDTH-6){1'b0}}, 6'd39};
`else
parameter TRANS_TERM_BYTE = {{(TRANS_STATE_WIDTH-5){1'b0}}, 5'd31};
`endif
always @(posedge clk40) begin
//num_chans <= num_chans_a;
if (rst) begin
strobe_a <= 0;
strobe_b <= 0;
rs232_tx_empty_a <= 0;
rs232_tx_empty_b <= 0;
trans_state <= TRANS_WAIT;
trans_en <= 0;
//Propogate reset
rst_out <= 1;
trig_rdy <= 1'b1;
end else begin
//Synchronise the uart empty signal
rs232_tx_empty_a <= rs232_tx_empty;
rs232_tx_empty_b <= rs232_tx_empty_a;
//Synchronise the strobe
strobe_a <= strobe;
strobe_b <= strobe_a;
//On falling edge of strobe, move to first transmission state
// if (~strobe_a && strobe_b) begin
// trans_state <= TRANS_STAMP_FRAME;
// end else begin
//STATE MACHINE
case (trans_state)
TRANS_WAIT: begin
//trans_state <= (~strobe_a && strobe_b) ? TRANS_STAMP_FRAME : trans_state;
if (~strobe_a && strobe_b) trans_state <= TRANS_STAMP_FRAME;
else if (poll_uart) trans_state <= TRANS_357_RB_FRAME;
else trans_state <= trans_state;
//Reset internal registers
rs232_tx_ld <= 0;
rs232_tx_pending <= 0;
//If neither channel is transmitting, ensure the daq_ram reset is low
rst_out <= 0;
trig_rdy <= trig_rdy;
end
TRANS_STAMP_FRAME: begin
//Transmit timestamp frame byte
trig_rdy <= 1'b0;
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state
trans_state <= TRANS_STAMP;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd31;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//rs232_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_STAMP: begin
trig_rdy <= trig_rdy;
//Transmit current timestamp as data
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state
trans_state <= TRANS_P1_XDIF_FRAME;
end else begin
//uart is empty. Load timestamp byte to transmit
//rs232_tx_buffer <= {1'b1, count_40ms};
rs232_tx_buffer <= count_40ms;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//rs232_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P1_XDIF_FRAME: begin
trig_rdy <= trig_rdy;
//Send P1 xdif frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
if (num_chans[0]) begin
trans_en <= 1;
trans_state <= TRANS_P1_XDIF;
end else begin
trans_en <= 0;
trans_state <= TRANS_P1_YDIF_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd16;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P1_XDIF: begin
trig_rdy <= trig_rdy;
//Transmit until done, then start next
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P1_YDIF_FRAME;
end
end
end
TRANS_P1_YDIF_FRAME: begin
trig_rdy <= trig_rdy;
//Send P1 ydif frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
rs232_tx_pending <= 0;
if (num_chans[1]) begin
trans_en <= 1;
trans_state <= TRANS_P1_YDIF;
end else begin
trans_en <= 0;
trans_state <= TRANS_P1_SUM_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd18;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P1_YDIF: begin
trig_rdy <= trig_rdy;
//Transmit until done, then start next
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P1_SUM_FRAME;
end
end
end
TRANS_P1_SUM_FRAME: begin
trig_rdy <= trig_rdy;
//Send P1 sum frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
if (num_chans[2]) begin
trans_en <= 1;
trans_state <= TRANS_P1_SUM;
end else begin
trans_en <= 0;
trans_state <= TRANS_P2_XDIF_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd20;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P1_SUM: begin
trig_rdy <= trig_rdy;
//Transmit until done, then move to default state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P2_XDIF_FRAME;
end
end
end
TRANS_P2_XDIF_FRAME: begin
trig_rdy <= trig_rdy;
//Send P2 xdif frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
if (num_chans[3]) begin
trans_en <= 1;
trans_state <= TRANS_P2_XDIF;
end else begin
trans_en <= 0;
trans_state <= TRANS_P2_YDIF_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd21;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P2_XDIF: begin
trig_rdy <= trig_rdy;
//Transmit until done, then start next
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P2_YDIF_FRAME;
end
end
end
TRANS_P2_YDIF_FRAME: begin
trig_rdy <= trig_rdy;
//Send P2 ydif frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
rs232_tx_pending <= 0;
if (num_chans[4]) begin
trans_en <= 1;
trans_state <= TRANS_P2_YDIF;
end else begin
trans_en <= 0;
trans_state <= TRANS_P2_SUM_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd22;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P2_YDIF: begin
trig_rdy <= trig_rdy;
//Transmit until done, then start next
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P2_SUM_FRAME;
end
end
end
TRANS_P2_SUM_FRAME: begin
trig_rdy <= trig_rdy;
//Send P2 sum frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
if (num_chans[5]) begin
trans_en <= 1;
trans_state <= TRANS_P2_SUM;
end else begin
trans_en <= 0;
trans_state <= TRANS_P3_XDIF_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd23;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P2_SUM: begin
trig_rdy <= trig_rdy;
//Transmit until done, then move to default state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P3_XDIF_FRAME;
end
end
end
TRANS_P3_XDIF_FRAME: begin
trig_rdy <= trig_rdy;
//Send P3 xdif frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
if (num_chans[6]) begin
trans_en <= 1;
trans_state <= TRANS_P3_XDIF;
end else begin
trans_en <= 0;
trans_state <= TRANS_P3_YDIF_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd24;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P3_XDIF: begin
trig_rdy <= trig_rdy;
//Transmit until done, then start next
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P3_YDIF_FRAME;
end
end
end
TRANS_P3_YDIF_FRAME: begin
trig_rdy <= trig_rdy;
//Send P3 ydif frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
rs232_tx_pending <= 0;
if (num_chans[7]) begin
trans_en <= 1;
trans_state <= TRANS_P3_YDIF;
end else begin
trans_en <= 0;
trans_state <= TRANS_P3_SUM_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd25;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P3_YDIF: begin
trig_rdy <= trig_rdy;
//Transmit until done, then start next
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_P3_SUM_FRAME;
end
end
end
TRANS_P3_SUM_FRAME: begin
trig_rdy <= trig_rdy;
//Send P3 sum frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
if (num_chans[8]) begin
trans_en <= 1;
trans_state <= TRANS_P3_SUM;
end else begin
trans_en <= 0;
trans_state <= TRANS_DAC_K1_FRAME;
end
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd26;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_P3_SUM: begin
trig_rdy <= trig_rdy;
//Transmit until done, and move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_DAC_K1_FRAME;
end
end
end
TRANS_DAC_K1_FRAME: begin
trig_rdy <= trig_rdy;
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
trans_en <= 1;
trans_state <= TRANS_DAC_K1;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd29;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_DAC_K1: begin
trig_rdy <= trig_rdy;
//Transmit until done, and move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_DAC_K2_FRAME;
end
end
end
TRANS_DAC_K2_FRAME: begin
trig_rdy <= trig_rdy;
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
trans_en <= 1;
trans_state <= TRANS_DAC_K2;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd30;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_DAC_K2: begin
trig_rdy <= trig_rdy;
//Transmit until done, and move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_357_RB_FRAME;
end
end
end
TRANS_357_RB_FRAME: begin
trig_rdy <= trig_rdy;
//Send 357MHz readback frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable control reg transmission
trans_en <= 0;
trans_state <= TRANS_40_RB_FRAME;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd27;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
/*TRANS_357_RB: begin
//Transmit until done, then move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_40_RB_FRAME;
end
end
end */
TRANS_40_RB_FRAME: begin
trig_rdy <= trig_rdy;
//Send 40MHz readback frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable control reg transmission
trans_en <= 1;
trans_state <= TRANS_40_RB;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd28;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_40_RB: begin
trig_rdy <= trig_rdy;
//Transmit until done, then send reset and move to default state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_MON_RB_FRAME;
end
end
end
TRANS_MON_RB_FRAME: begin
trig_rdy <= trig_rdy;
//Send monitor readback frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable control reg transmission
trans_en <= 1;
trans_state <= TRANS_MON_RB;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd15;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_MON_RB: begin
trig_rdy <= trig_rdy;
//Transmit until done, then send reset and move to default state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
//rst_out <= 1;
`ifdef LUTRAMreadout
trans_state <= (LUTRAMreadout) ? TRANS_K1P2_FRAME : TRANS_TERM_BYTE;
`else
trans_state <= TRANS_TERM_BYTE;
`endif
end
end
end
`ifdef LUTRAMreadout
TRANS_K1P2_FRAME: begin
trig_rdy <= trig_rdy;
//Send P3 sum frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
trans_en <= 1;
trans_state <= TRANS_K1P2;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd9;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_K1P2: begin
trig_rdy <= trig_rdy;
//Transmit until done, and move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_K1P3_FRAME;
end
end
end
TRANS_K1P3_FRAME: begin
trig_rdy <= trig_rdy;
//Send P3 sum frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
trans_en <= 1;
trans_state <= TRANS_K1P3;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd11;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_K1P3: begin
trig_rdy <= trig_rdy;
//Transmit until done, and move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_K2P2_FRAME;
end
end
end
TRANS_K2P2_FRAME: begin
trig_rdy <= trig_rdy;
//Send P3 sum frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
trans_en <= 1;
trans_state <= TRANS_K2P2;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd12;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_K2P2: begin
trig_rdy <= trig_rdy;
//Transmit until done, and move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_K2P3_FRAME;
end
end
end
TRANS_K2P3_FRAME: begin
trig_rdy <= trig_rdy;
//Send P3 sum frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable DAQ_RAM transmission
trans_en <= 1;
trans_state <= TRANS_K2P3;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd13;
rs232_tx_ld <= 1;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
end
end
end
TRANS_K2P3: begin
trig_rdy <= trig_rdy;
//Transmit until done, and move to next state
if (trans_en) begin
if (trans_done) begin
trans_en <= 0;
trans_state <= TRANS_TERM_BYTE;
end
end
end
`endif
TRANS_TERM_BYTE: begin
//Send monitor readback frame byte directly to uart
if (!rs232_tx_ld && rs232_tx_empty_b) begin
if (rs232_tx_pending) begin
//Transmission complete
rs232_tx_pending <= 0;
//Move to next state and enable control reg transmission
trans_en <= 0;
rst_out <= 1;
trans_state <= TRANS_WAIT;
trig_rdy <= 1'b1;
end else begin
//uart is empty. Load byte to transmit
rs232_tx_buffer <= 7'd14;
rs232_tx_ld <= 1;
trig_rdy <= trig_rdy;
end
end else begin
if (rs232_tx_ld && !rs232_tx_empty_b) begin
//byte loaded to uart.
//uart_tx_empty will stay low until transmission complete
rs232_tx_ld <= 0;
rs232_tx_pending <= 1;
trig_rdy <= trig_rdy;
end
end
end
endcase
//end
end
end
// Implement the 40ms 7-bit counter
reg [20:0] cycle_count = 21'd0;
always @(posedge clk40) begin
if (cycle_count == 21'd1600000) begin
cycle_count <= 0;
count_40ms <= count_40ms + 1;
end else begin
cycle_count <= cycle_count + 1;
end
end
endmodule
//
//// ***************** dac_readback ******************************************
////
//// The dac output is loaded into a register array. Each dac clock is used
//// as a strobe to load the values at 357MHz. The clocks are 5.6ns pulses,
//// so there will be 2 values clocked in per clock (i.e 6 per pulse, though each pair
//// of values should be identical)
////
//// It contains transmission logic identical to the DAQ_RAM, and is triggered
//// last in the DAQ cycle to transmit its register contents as data
//
//module dac_readback(
// reset,
// tx_en,
// tx_clk,
// tx_data_ready,
// tx_data,
// tx_data_loaded,
// tx_complete,
// wr_clk,
// wr_en,
// wr_data
//);
//
//// Parameters
//parameter ARRAY_SIZE = 6;
//
//
//// Ports
//input reset;
//input tx_en;
//input tx_clk;
//input tx_data_loaded;
//output tx_data_ready;
//output [7:0] tx_data;
//output tx_complete;
//input wr_clk;
//input wr_en;
//input [13:0] wr_data;
//
//// Internal registers
//reg [10:0] tx_cnt;
//reg tx_data_ready;
//reg tx_data_loaded1;
//reg tx_data_loaded2;
//reg tx_complete;
//reg [7:0] tx_data;
//reg [9:0] wr_addr;
//
////Declare register array
//
|
`timescale 1ns/1ns
module aes_tb;
reg rst;
reg clk;
reg [7:0] key_in;
reg [7:0] d_in;
wire [7:0] d_out;
wire d_vld;
parameter CP = 20;
//Two test vectors
//Simple example
//CT = 0x69c4e0d86a7b0430d8cdb78070b4c55a
parameter kin = 128'h000102030405060708090a0b0c0d0e0f;
parameter din = 128'h00112233445566778899aabbccddeeff;
//Example in FIPS-197
//CT = 0x3925841d02dc09fbdc118597196a0b32
//parameter kin = 128'h2b7e151628aed2a6abf7158809cf4f3c;
//parameter din = 128'h3243f6a8885a308d313198a2e0370734;
aes_8_bit test (rst, clk, key_in, d_in, d_out, d_vld);
always # (CP/2)
begin
clk = ~ clk;
end
initial begin
rst = 1'b1;
clk = 1'b1;
#CP
rst = 1'b0;
key_in = kin[127:120];
d_in = din[127:120];
#CP
key_in = kin[119:112];
d_in = din[119:112];
#CP
key_in = kin[111:104];
d_in = din[111:104];
#CP
key_in = kin[103:96];
d_in = din[103:96];
#CP
key_in = kin[95:88];
d_in = din[95:88];
#CP
key_in = kin[87:80];
d_in = din[87:80];
#CP
key_in = kin[79:72];
d_in = din[79:72];
#CP
key_in = kin[71:64];
d_in = din[71:64];
#CP
key_in = kin[63:56];
d_in = din[63:56];
#CP
key_in = kin[55:48];
d_in = din[55:48];
#CP
key_in = kin[47:40];
d_in = din[47:40];
#CP
key_in = kin[39:32];
d_in = din[39:32];
#CP
key_in = kin[31:24];
d_in = din[31:24];
#CP
key_in = kin[23:16];
d_in = din[23:16];
#CP
key_in = kin[15:8];
d_in = din[15:8];
#CP
key_in = kin[7:0];
d_in = din[7:0];
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_PP_V
/**
* iso0n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__iso0n (
X ,
A ,
SLEEP_B,
VPWR ,
KAGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP_B;
input VPWR ;
input KAGND ;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_sleepb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, KAGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_sleepb, SLEEP_B, VPWR, KAGND );
and and0 (X , pwrgood_pp0_out_A, pwrgood_pp1_out_sleepb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO0N_BEHAVIORAL_PP_V |
/**
* Instantiates a 9Kib block RAM for the VGA buffer, and
* exposes an interface to write 32-bit blocks to 64
* addresses and read 8-bit blocks from 256 addresses.
* We are only using 2Kib of memory, but the physical
* hardware in the Spartan 6 only has two of these 9Kib
* block RAM banks.
*
* @author Robert Fotino, 2016
*/
module vga_block_ram
(
input wr_clk,
input wr_en,
input [5:0] wr_addr,
input [31:0] wr_data,
input rd_clk,
input [7:0] rd_addr,
output [7:0] rd_data
);
// Data out for the underlying block RAM. Output
// is 32 bits, but we want to have byte-level indexing
wire [31:0] DO;
assign rd_data = DO[{rd_addr[1:0], 3'b0}+:8];
// Instantiate a 9Kib simple dual-port block RAM
BRAM_SDP_MACRO
#(
.BRAM_SIZE("9Kb"),
.DEVICE("SPARTAN6"),
.WRITE_WIDTH(32),
.READ_WIDTH(32),
.DO_REG(0),
.INIT_FILE("NONE"),
.SRVAL(72'b0),
.INIT(72'b0)
)
BRAM_SDP_MACRO_inst
(
.DO(DO),
.DI(wr_data),
.RDADDR({ 2'b0, rd_addr[7:2] }),
.RDCLK(rd_clk),
.RDEN(1'b1),
.REGCE(REGCE),
.RST(1'b0),
.WE(4'b1111),
.WRADDR({ 2'b0, wr_addr }),
.WRCLK(wr_clk),
.WREN(wr_en)
);
endmodule
|
//----------------------------------------------------------------------------
// user_logic.vhd - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: user_logic.vhd
// Version: 1.00.e
// Description: User logic module.
// Date: Thu Mar 22 15:43:09 2012 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
Bus2IP_Data, // Bus to IP data bus
Bus2IP_BE, // Bus to IP byte enables
Bus2IP_RdCE, // Bus to IP read chip enable
Bus2IP_WrCE, // Bus to IP write chip enable
IP2Bus_Data, // IP to Bus data bus
IP2Bus_RdAck, // IP to Bus read transfer acknowledgement
IP2Bus_WrAck, // IP to Bus write transfer acknowledgement
IP2Bus_Error // IP to Bus error response
// -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_SLV_DWIDTH = 32;
parameter C_NUM_REG = 8;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Reset;
input [0 : C_SLV_DWIDTH-1] Bus2IP_Data;
input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE;
input [0 : C_NUM_REG-1] Bus2IP_RdCE;
input [0 : C_NUM_REG-1] Bus2IP_WrCE;
output [0 : C_SLV_DWIDTH-1] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// --USER nets declarations added here, as needed for user logic
// Nets for user logic slave model s/w accessible register example
reg [0 : C_SLV_DWIDTH-1] slv_reg0;
reg [0 : C_SLV_DWIDTH-1] slv_reg1;
reg [0 : C_SLV_DWIDTH-1] slv_reg2;
reg [0 : C_SLV_DWIDTH-1] slv_reg3;
reg [0 : C_SLV_DWIDTH-1] slv_reg4;
reg [0 : C_SLV_DWIDTH-1] slv_reg5;
reg [0 : C_SLV_DWIDTH-1] slv_reg6;
reg [0 : C_SLV_DWIDTH-1] slv_reg7;
wire [0 : 7] slv_reg_write_sel;
wire [0 : 7] slv_reg_read_sel;
reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
// --USER logic implementation added here
reg [0 : C_SLV_DWIDTH-1] t_ROkey;
reg [0 : C_SLV_DWIDTH-1] t_ROdata;
wire t_Q_full;
wire t_Q_empty;
wire t_insert;
wire t_extract;
TSProject32 ts1(.clk(Bus2IP_Clk), .reset(Bus2IP_Reset),
.insert(t_op0), .extract(t_op1),
.LIkey(slv_reg4), .LIdata(slv_reg5),
.ROkey(t_ROkey), .ROdata(t_ROdata),
.Q_FULL(t_Q_full), .Q_EMPTY(t_Q_empty));
assign t_op0 = slv_reg0[0:0];
assign t_op1 = slv_reg1[0:0];
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
//
// Note:
// The example code presented here is to show you one way of reading/writing
// software accessible registers implemented in the user logic slave model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
// to one software accessible register by the top level template. For example,
// if you have four 32 bit software accessible registers in the user logic,
// you are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------
assign
slv_reg_write_sel = Bus2IP_WrCE[0:7],
slv_reg_read_sel = Bus2IP_RdCE[0:7],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7];
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
end
else
case ( slv_reg_write_sel )
8'b10000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
8'b01000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
8'b00100000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
8'b00010000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
8'b00001000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
8'b00000100 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
8'b00000010 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
8'b00000001 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
default : ;
endcase
end // SLAVE_REG_WRITE_PROC
// implement slave model register read mux
always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 )
begin: SLAVE_REG_READ_PROC
case ( slv_reg_read_sel )
8'b10000000 : slv_ip2bus_data <= slv_reg0;
8'b01000000 : slv_ip2bus_data <= slv_reg1;
8'b00100000 : slv_ip2bus_data <= slv_reg2;
8'b00010000 : slv_ip2bus_data <= slv_reg3;
8'b00001000 : slv_ip2bus_data <= slv_reg4;
8'b00000100 : slv_ip2bus_data <= slv_reg5;
8'b00000010 : slv_ip2bus_data <= t_ROkey; //slv_reg6;
8'b00000001 : slv_ip2bus_data <= t_ROdata;//slv_reg7;
default : slv_ip2bus_data <= 0;
endcase
end // SLAVE_REG_READ_PROC
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
assign IP2Bus_Data = slv_ip2bus_data;
assign IP2Bus_WrAck = slv_write_ack;
assign IP2Bus_RdAck = slv_read_ack;
assign IP2Bus_Error = 0;
endmodule
|
//----------------------------------------------------------------------------
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: DE4Gen2x8If128.v
// Version:
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Altera Stratix IV IP Compiler for PCI Express
// module and the Terasic DE4 Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "altera.vh"
`timescale 1ps / 1ps
module DE4Gen2x8If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 8,
// Settings from Quartus IP Library
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 5
)
(
input OSC_50_BANK2,
input OSC_50_BANK3,
input OSC_50_BANK4,
input OSC_50_BANK5,
input OSC_50_BANK6,
input PCIE_RESET_N,
input PCIE_REFCLK,
input [C_NUM_LANES-1:0] PCIE_RX_IN,
output [C_NUM_LANES-1:0] PCIE_TX_OUT,
output [7:0] LED
);
// ----------PLL Signals----------
wire clk50;
wire clk125;
wire clk250;
wire locked;
wire inclk0;
// ----------PCIe Core Signals----------
// ----------PCIe Clocks----------
wire pld_clk;
wire reconfig_clk;
wire core_clk_out;
wire fixedclk_serdes;
wire refclk;
wire rc_pll_locked;
wire cal_blk_clk;
// ----------PCIe Resets----------
wire pll_powerdown;
wire reset_status;
wire crst;
wire npor;
wire srst;
wire gxb_powerdown;
// ----------PCIe Transaction layer configuration ----------
wire [ 3: 0] tl_cfg_add;
wire [ 31: 0] tl_cfg_ctl;
wire tl_cfg_ctl_wr;
wire [ 52: 0] tl_cfg_sts;
wire tl_cfg_sts_wr;
wire [ 19: 0] ko_cpl_spc_vc0;
// ----------PCIe Interrupt Interface----------
wire app_int_ack;
wire app_msi_ack;
wire app_int_sts;
wire app_msi_req;
// ----------PCIe Status Signals----------
wire hotrst_exit;
wire l2_exit;
wire dlup_exit;
wire [3:0] lane_act;
wire [4:0] ltssm;
wire pme_to_sr;
wire suc_spd_neg;
// ----------PCIe RX Interface----------
wire rx_st_mask0;
wire [ 7: 0] rx_st_bardec0;
wire [ 15: 0] rx_st_be0;
wire [0:0] rx_st_sop0;
wire [0:0] rx_st_eop0;
wire [0:0] rx_st_err0;
wire [0:0] rx_st_valid0;
wire [0:0] rx_st_empty0;
wire rx_st_ready0;
wire [C_PCI_DATA_WIDTH-1:0] rx_st_data0;
// ----------PCIe TX Interface----------
wire [0:0] tx_st_sop0;
wire [0:0] tx_st_eop0;
wire [0:0] tx_st_err0;
wire [0:0] tx_st_valid0;
wire [0:0] tx_st_empty0;
wire tx_st_ready0;
wire [C_PCI_DATA_WIDTH-1:0] tx_st_data0;
// ----------ALTGX Signals----------
wire busy;
wire busy_altgxb_reconfig;
wire [33:0] reconfig_fromgxb;
wire [3:0] reconfig_togxb;
// ----------Resets ----------
reg [4:0] rPCIRstCtr=0,_rPCIRstCtr=0;
reg [2:0] rRstSync=0,_rRstSync=0;
wire wSyncRst;
always @(*) begin
_rRstSync = {rRstSync[1:0], ~npor};
_rPCIRstCtr = rPCIRstCtr;
if (rRstSync[2]) begin
_rPCIRstCtr = 0;
end else if (~rPCIRstCtr[4]) begin
_rPCIRstCtr = rPCIRstCtr + 1;
end
end
always @(posedge pld_clk) begin
rRstSync <= _rRstSync;
rPCIRstCtr <= _rPCIRstCtr;
end
assign wSyncRst = ~ rPCIRstCtr[4];
assign srst = wSyncRst;
assign crst = wSyncRst;
// ----------PLL assignments----------
assign inclk0 = OSC_50_BANK2;
assign fixedclk_serdes = clk125;
assign reconfig_clk = clk50;
// ----------PCIe Resets----------
assign npor = PCIE_RESET_N;
assign gxb_powerdown = ~ npor;
assign pll_powerdown = ~ npor;
// ----------PCIe Clocks / PLLs----------
assign refclk = PCIE_REFCLK;
assign pld_clk = core_clk_out;
assign cal_blk_clk = reconfig_clk;
// ----------ALTGX----------
assign busy = busy_altgxb_reconfig;
// -------------------- BEGIN ALTERA IP INSTANTIATION --------------------
ALTPLL50I50O125O250O ALTPLL50I50O125O250O_inst
(
// Outputs
.c0 (clk50),
.c1 (clk125),
.c2 (clk250),
.locked (locked),
// Inputs
.inclk0 (inclk0));
ALTGXPCIeGen2x8
altgx_inst
(
// Outputs
.busy (busy),
.reconfig_togxb (reconfig_togxb[3:0]),
// Inputs
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb[33:0]));
PCIeGen2x8If128
pcie_inst
(
// Outputs
.app_int_ack (app_int_ack),
.app_msi_ack (app_msi_ack),
.core_clk_out (core_clk_out),
.hotrst_exit (hotrst_exit),
.l2_exit (l2_exit),
.dlup_exit (dlup_exit),
.lane_act (lane_act[3:0]),
.ltssm (ltssm[4:0]),
.rc_pll_locked (rc_pll_locked),
.reconfig_fromgxb (reconfig_fromgxb[33:0]),
.reset_status (reset_status),
.rx_st_bardec0 (rx_st_bardec0[7:0]),
.rx_st_be0 (rx_st_be0[7:0]),
.rx_st_data0 (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.rx_st_eop0 (rx_st_eop0),
.rx_st_err0 (rx_st_err0),
.rx_st_sop0 (rx_st_sop0),
.rx_st_empty0 (rx_st_empty0),
.rx_st_valid0 (rx_st_valid0),
.suc_spd_neg (suc_spd_neg),// Gen 2 successful
.tl_cfg_add (tl_cfg_add[3:0]),
.tl_cfg_ctl (tl_cfg_ctl[31:0]),
.tl_cfg_ctl_wr (tl_cfg_ctl_wr),
.tl_cfg_sts (tl_cfg_sts[52:0]),
.tl_cfg_sts_wr (tl_cfg_sts_wr),
.ko_cpl_spc_vc0 (ko_cpl_spc_vc0),
.tx_out0 (PCIE_TX_OUT[0]),
.tx_out1 (PCIE_TX_OUT[1]),
.tx_out2 (PCIE_TX_OUT[2]),
.tx_out3 (PCIE_TX_OUT[3]),
.tx_out4 (PCIE_TX_OUT[4]),
.tx_out5 (PCIE_TX_OUT[5]),
.tx_out6 (PCIE_TX_OUT[6]),
.tx_out7 (PCIE_TX_OUT[7]),
.tx_st_ready0 (tx_st_ready0),
// Inputs
.app_int_sts (app_int_sts),
.app_msi_req (app_msi_req),
.busy_altgxb_reconfig (busy_altgxb_reconfig),
.cal_blk_clk (cal_blk_clk),
.crst (crst),
.fixedclk_serdes (fixedclk_serdes),
.gxb_powerdown (gxb_powerdown),
.pll_powerdown (pll_powerdown),
.npor (npor),
.pld_clk (pld_clk),
.reconfig_clk (reconfig_clk),
.reconfig_togxb (reconfig_togxb[3:0]),
.refclk (refclk),
.rx_in0 (PCIE_RX_IN[0]),
.rx_in1 (PCIE_RX_IN[1]),
.rx_in2 (PCIE_RX_IN[2]),
.rx_in3 (PCIE_RX_IN[3]),
.rx_in4 (PCIE_RX_IN[4]),
.rx_in5 (PCIE_RX_IN[5]),
.rx_in6 (PCIE_RX_IN[6]),
.rx_in7 (PCIE_RX_IN[7]),
.rx_st_ready0 (rx_st_ready0),
.srst (srst),
.tx_st_data0 (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.tx_st_eop0 (tx_st_eop0),
.tx_st_err0 (1'b0),
.tx_st_sop0 (tx_st_sop0),
.tx_st_empty0 (tx_st_empty0),
.tx_st_valid0 (tx_st_valid0));
// -------------------- END ALTERA IP INSTANTIATION --------------------
// -------------------- BEGIN RIFFA INSTANTAION --------------------
// ----------RIFFA channel interface----------
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*32)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*31)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
wire chnl_reset;
wire chnl_clk;
wire rst_out;
assign chnl_clk = pld_clk;
assign chnl_reset = rst_out;
riffa_wrapper_de4
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(
// Outputs
.RX_ST_READY (rx_st_ready0),
.TX_ST_DATA (tx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.TX_ST_VALID (tx_st_valid0[0:0]),
.TX_ST_EOP (tx_st_eop0[0:0]),
.TX_ST_SOP (tx_st_sop0[0:0]),
.TX_ST_EMPTY (tx_st_empty0[0:0]),
.APP_MSI_REQ (app_msi_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.RX_ST_DATA (rx_st_data0[C_PCI_DATA_WIDTH-1:0]),
.RX_ST_EOP (rx_st_eop0[0:0]),
.RX_ST_SOP (rx_st_sop0[0:0]),
.RX_ST_VALID (rx_st_valid0[0:0]),
.RX_ST_EMPTY (rx_st_empty0[0:0]),
.TX_ST_READY (tx_st_ready0),
.TL_CFG_CTL (tl_cfg_ctl[`SIG_CFG_CTL_W-1:0]),
.TL_CFG_ADD (tl_cfg_add[`SIG_CFG_ADD_W-1:0]),
.TL_CFG_STS (tl_cfg_sts[`SIG_CFG_STS_W-1:0]),
.KO_CPL_SPC_HEADER (ko_cpl_spc_vc0[7:0]),
.KO_CPL_SPC_DATA (ko_cpl_spc_vc0[19:8]),
.APP_MSI_ACK (app_msi_ack),
.PLD_CLK (pld_clk),
.RESET_STATUS (reset_status),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0]));
// -------------------- END RIFFA INSTANTAION --------------------
// -------------------- BEGIN USER CODE --------------------
genvar i;
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : test_channels
// Instantiate and assign modules to RIFFA channels. Users should
// replace the chnl_tester instantiation with their own core.
chnl_tester
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH)
)
chnl_tester_i
(
.CLK(chnl_clk),
.RST(chnl_reset), // chnl_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[i]),
.CHNL_RX(chnl_rx[i]),
.CHNL_RX_ACK(chnl_rx_ack[i]),
.CHNL_RX_LAST(chnl_rx_last[i]),
.CHNL_RX_LEN(chnl_rx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_RX_OFF(chnl_rx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[i]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[i]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[i]),
.CHNL_TX(chnl_tx[i]),
.CHNL_TX_ACK(chnl_tx_ack[i]),
.CHNL_TX_LAST(chnl_tx_last[i]),
.CHNL_TX_LEN(chnl_tx_len[`SIG_CHNL_LENGTH_W*i +:`SIG_CHNL_LENGTH_W]),
.CHNL_TX_OFF(chnl_tx_off[`SIG_CHNL_OFFSET_W*i +:`SIG_CHNL_OFFSET_W]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*i +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[i]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[i])
);
end
endgenerate
// -------------------- END USER CODE --------------------
endmodule // DE4Gen2x8If128
|
//-----------------------------------------------------------------------------
//-- Baudrate generator
//-- It generates a square signal, with a frequency for communicating at the given
//-- given baudrate
//-- The output is set to 1 only during one clock cycle. The rest of the time is 0
//-- Once enabled, the pulse is generated just in the middle of the period
//-- This is necessary for the implementation of the receptor
//--------------------------------------------------------------------------------
//-- (c) BQ. December 2015. written by Juan Gonzalez (obijuan)
//-----------------------------------------------------------------------------
//-- GPL license
//-----------------------------------------------------------------------------
`default_nettype none
`include "src/baudgen.vh"
//----------------------------------------------------------------------------------------
//-- baudgen module
//--
//-- INPUTS:
//-- -clk: System clock (12 MHZ in the iceStick board)
//-- -clk_ena: clock enable:
//-- 1. Normal working: The squeare signal is generated
//-- 0: stoped. Output always 0
//-- OUTPUTS:
//-- - clk_out: Output signal. Pulse width: 1 clock cycle. Output not registered
//-- It tells the uart_rx when to sample the next bit
//-- __ __
//-- ____________________| |________________________________________| |_____________________
//-- | -> <- 1 clock cycle |
//-- <------- Period ------------------------->
//--
//---------------------------------------------------------------------------------------
module baudgen_rx #(
parameter BAUDRATE = `B115200 //-- Default baudrate
)(
input wire rstn, //-- Reset (active low)
input wire clk, //-- System clock
input wire clk_ena, //-- Clock enable
output wire clk_out //-- Bitrate Clock output
);
//-- Number of bits needed for storing the baudrate divisor
`include "src/functions.vh"
localparam N = clog2(BAUDRATE);
//-- Value for generating the pulse in the middle of the period
localparam M2 = (BAUDRATE >> 1);
//-- Counter for implementing the divisor (it is a BAUDRATE module counter)
//-- (when BAUDRATE is reached, it start again from 0)
reg [N-1:0] divcounter = 0;
//-- Contador módulo M
always @(posedge clk or negedge rstn)
if (!rstn)
divcounter <= 0;
else if (clk_ena)
//-- Normal working: counting. When the maximum count is reached, it starts from 0
divcounter <= (divcounter == BAUDRATE - 1) ? 0 : divcounter + 1;
else
//-- Counter fixed to its maximum value
//-- When it is resumed it start from 0
divcounter <= BAUDRATE - 1;
//-- The output is 1 when the counter is in the middle of the period, if clk_ena is active
//-- It is 1 only for one system clock cycle
assign clk_out = (divcounter == M2) ? clk_ena : 0;
endmodule
|
// DESCRIPTION: Verilator: System Verilog test of case and if
//
// This code instantiates and runs a simple CPU written in System Verilog.
//
// This file ONLY is placed into the Public Domain, for any use, without
// warranty.
// Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
/*AUTOWIRE*/
// **************************************************************************
// Regs and Wires
// **************************************************************************
reg rst;
integer rst_count;
st3_testbench st3_testbench_i (/*AUTOINST*/
// Inputs
.clk (clk),
.rst (rst));
// **************************************************************************
// Reset Generation
// **************************************************************************
initial begin
rst = 1'b1;
rst_count = 0;
end
always @( posedge clk ) begin
if (rst_count < 2) begin
rst_count++;
end
else begin
rst = 1'b0;
end
end
// **************************************************************************
// Closing message
// **************************************************************************
final begin
$write("*-* All Finished *-*\n");
end
endmodule
module st3_testbench (/*AUTOARG*/
// Inputs
clk, rst
);
input clk;
input rst;
logic clk;
logic rst;
logic [8*16-1:0] wide_input_bus;
logic decrementA; // 0=Up-counting, 1=down-counting
logic dual_countA; // Advance counter by 2 steps at a time
logic cntA_en; // Enable Counter A
logic decrementB; // 0=Up-counting, 1=down-counting
logic dual_countB; // Advance counter by 2 steps at a time
logic cntB_en; // Enable counter B
logic [47:0] selected_out;
integer i;
initial begin
decrementA = 1'b0;
dual_countA = 1'b0;
cntA_en = 1'b1;
decrementB = 1'b0;
dual_countB = 1'b0;
cntB_en = 1'b1;
wide_input_bus = {8'hf5,
8'hef,
8'hd5,
8'hc5,
8'hb5,
8'ha5,
8'h95,
8'h85,
8'ha7,
8'ha6,
8'ha5,
8'ha4,
8'ha3,
8'ha2,
8'ha1,
8'ha0};
i = 0;
end
simple_test_3
simple_test_3_i
(// Outputs
.selected_out (selected_out[47:0]),
// Inputs
.wide_input_bus (wide_input_bus[8*16-1:0]),
.rst (rst),
.clk (clk),
.decrementA (decrementA),
.dual_countA (dual_countA),
.cntA_en (cntA_en),
.decrementB (decrementB),
.dual_countB (dual_countB),
.cntB_en (cntB_en));
// Logic to print outputs and then finish.
always @(posedge clk) begin
if (i < 50) begin
`ifdef TEST_VERBOSE
$display("%x", simple_test_3_i.cntA_reg ,"%x",
simple_test_3_i.cntB_reg ," ", "%x", selected_out);
`endif
i <= i + 1;
end
else begin
$finish();
end
end // always @ (posedge clk)
endmodule
// Module testing:
// - Unique case
// - Priority case
// - Unique if
// - ++, --, =- and =+ operands.
module simple_test_3
(input logic [8*16-1:0] wide_input_bus,
input logic rst,
input logic clk,
// Counter A
input logic decrementA, // 0=Up-counting, 1=down-counting
input logic dual_countA, // Advance counter by 2 steps at a time
input logic cntA_en, // Enable Counter A
// Counter B
input logic decrementB, // 0=Up-counting, 1=down-counting
input logic dual_countB, // Advance counter by 2 steps at a time
input logic cntB_en, // Enable counter B
// Outputs
output logic [47:0] selected_out);
// Declarations
logic [3:0] cntA_reg; // Registered version of cntA
logic [3:0] cntB_reg; // Registered version of cntA
counterA
counterA_inst
(/*AUTOINST*/
// Outputs
.cntA_reg (cntA_reg[3:0]),
// Inputs
.decrementA (decrementA),
.dual_countA (dual_countA),
.cntA_en (cntA_en),
.clk (clk),
.rst (rst));
counterB
counterB_inst
(/*AUTOINST*/
// Outputs
.cntB_reg (cntB_reg[3:0]),
// Inputs
.decrementB (decrementB),
.dual_countB (dual_countB),
.cntB_en (cntB_en),
.clk (clk),
.rst (rst));
simple_test_3a
sta
(.wide_input_bus (wide_input_bus),
.selector (cntA_reg),
.selected_out (selected_out[7:0]));
simple_test_3b
stb
(.wide_input_bus (wide_input_bus),
.selector (cntA_reg),
.selected_out (selected_out[15:8]));
simple_test_3c
stc
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[23:16]));
simple_test_3d
std
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[31:24]));
simple_test_3e
ste
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[39:32]));
simple_test_3f
stf
(.wide_input_bus (wide_input_bus),
.selector (cntB_reg),
.selected_out (selected_out[47:40]));
endmodule // simple_test_3
module counterA
(output logic [3:0] cntA_reg, // Registered version of cntA
input logic decrementA, // 0=Up-counting, 1=down-counting
input logic dual_countA, // Advance counter by 2 steps at a time
input logic cntA_en, // Enable Counter A
input logic clk, // Clock
input logic rst); // Synchronous reset
logic [3:0] cntA; // combinational count variable.
// Counter A
// Sequential part of counter CntA
always_ff @(posedge clk)
begin
cntA_reg <= cntA;
end
// Combinational part of counter
// Had to be split up to test C-style update, as there are no
// non-blocking version like -<=
always_comb
if (rst)
cntA = 0;
else begin
cntA = cntA_reg; // Necessary to avoid latch
if (cntA_en) begin
if (decrementA)
if (dual_countA)
//cntA = cntA - 2;
cntA -= 2;
else
//cntA = cntA - 1;
cntA--;
else
if (dual_countA)
//cntA = cntA + 2;
cntA += 2;
else
//cntA = cntA + 1;
cntA++;
end // if (cntA_en)
end
endmodule // counterA
module counterB
(output logic [3:0] cntB_reg, // Registered version of cntA
input logic decrementB, // 0=Up-counting, 1=down-counting
input logic dual_countB, // Advance counter by 2 steps at a time
input logic cntB_en, // Enable counter B
input logic clk, // Clock
input logic rst); // Synchronous reset
// Counter B - tried to write sequential only, but ended up without
// SystemVerilog.
always_ff @(posedge clk) begin
if (rst)
cntB_reg <= 0;
else
if (cntB_en) begin
if (decrementB)
if (dual_countB)
cntB_reg <= cntB_reg - 2;
else
cntB_reg <= cntB_reg - 1;
// Attempts to write in SystemVerilog:
else
if (dual_countB)
cntB_reg <= cntB_reg + 2;
else
cntB_reg <= cntB_reg + 1;
// Attempts to write in SystemVerilog:
end
end // always_ff @
endmodule
// A multiplexor in terms of look-up
module simple_test_3a
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb
selected_out = {wide_input_bus[selector*8+7],
wide_input_bus[selector*8+6],
wide_input_bus[selector*8+5],
wide_input_bus[selector*8+4],
wide_input_bus[selector*8+3],
wide_input_bus[selector*8+2],
wide_input_bus[selector*8+1],
wide_input_bus[selector*8]};
endmodule // simple_test_3a
// A multiplexer in terms of standard case
module simple_test_3b
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
case (selector)
4'h0: selected_out = wide_input_bus[ 7: 0];
4'h1: selected_out = wide_input_bus[ 15: 8];
4'h2: selected_out = wide_input_bus[ 23: 16];
4'h3: selected_out = wide_input_bus[ 31: 24];
4'h4: selected_out = wide_input_bus[ 39: 32];
4'h5: selected_out = wide_input_bus[ 47: 40];
4'h6: selected_out = wide_input_bus[ 55: 48];
4'h7: selected_out = wide_input_bus[ 63: 56];
4'h8: selected_out = wide_input_bus[ 71: 64];
4'h9: selected_out = wide_input_bus[ 79: 72];
4'ha: selected_out = wide_input_bus[ 87: 80];
4'hb: selected_out = wide_input_bus[ 95: 88];
4'hc: selected_out = wide_input_bus[103: 96];
4'hd: selected_out = wide_input_bus[111:104];
4'he: selected_out = wide_input_bus[119:112];
4'hf: selected_out = wide_input_bus[127:120];
endcase // case (selector)
end
endmodule // simple_test_3b
// A multiplexer in terms of unique case
module simple_test_3c
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
unique case (selector)
4'h0: selected_out = wide_input_bus[ 7: 0];
4'h1: selected_out = wide_input_bus[ 15: 8];
4'h2: selected_out = wide_input_bus[ 23: 16];
4'h3: selected_out = wide_input_bus[ 31: 24];
4'h4: selected_out = wide_input_bus[ 39: 32];
4'h5: selected_out = wide_input_bus[ 47: 40];
4'h6: selected_out = wide_input_bus[ 55: 48];
4'h7: selected_out = wide_input_bus[ 63: 56];
4'h8: selected_out = wide_input_bus[ 71: 64];
4'h9: selected_out = wide_input_bus[ 79: 72];
4'ha: selected_out = wide_input_bus[ 87: 80];
4'hb: selected_out = wide_input_bus[ 95: 88];
4'hc: selected_out = wide_input_bus[103: 96];
4'hd: selected_out = wide_input_bus[111:104];
4'he: selected_out = wide_input_bus[119:112];
4'hf: selected_out = wide_input_bus[127:120];
endcase // case (selector)
end
endmodule // simple_test_3c
// A multiplexer in terms of unique if
module simple_test_3d
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
unique if (selector == 4'h0) selected_out = wide_input_bus[ 7: 0];
else if (selector == 4'h1) selected_out = wide_input_bus[ 15: 8];
else if (selector == 4'h2) selected_out = wide_input_bus[ 23: 16];
else if (selector == 4'h3) selected_out = wide_input_bus[ 31: 24];
else if (selector == 4'h4) selected_out = wide_input_bus[ 39: 32];
else if (selector == 4'h5) selected_out = wide_input_bus[ 47: 40];
else if (selector == 4'h6) selected_out = wide_input_bus[ 55: 48];
else if (selector == 4'h7) selected_out = wide_input_bus[ 63: 56];
else if (selector == 4'h8) selected_out = wide_input_bus[ 71: 64];
else if (selector == 4'h9) selected_out = wide_input_bus[ 79: 72];
else if (selector == 4'ha) selected_out = wide_input_bus[ 87: 80];
else if (selector == 4'hb) selected_out = wide_input_bus[ 95: 88];
else if (selector == 4'hc) selected_out = wide_input_bus[103: 96];
else if (selector == 4'hd) selected_out = wide_input_bus[111:104];
else if (selector == 4'he) selected_out = wide_input_bus[119:112];
else if (selector == 4'hf) selected_out = wide_input_bus[127:120];
end
endmodule // simple_test_3d
// Test of priority case
// Note: This does NOT try to implement the same function as above.
module simple_test_3e
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
priority case (1'b1)
selector[0]: selected_out = wide_input_bus[ 7: 0]; // Bit 0 has highets priority
selector[2]: selected_out = wide_input_bus[ 39: 32]; // Note 2 higher priority than 1
selector[1]: selected_out = wide_input_bus[ 23: 16]; // Note 1 lower priority than 2
selector[3]: selected_out = wide_input_bus[ 71: 64]; // Bit 3 has lowest priority
default: selected_out = wide_input_bus[127:120]; // for selector = 0.
endcase // case (selector)
end
endmodule // simple_test_3e
// Test of "inside"
// Note: This does NOT try to implement the same function as above.
// Note: Support for "inside" is a separate Verilator feature request, so is
// not used inside a this version of the test.
module simple_test_3f
(input logic [8*16-1:0] wide_input_bus,
input logic [3:0] selector,
output logic [7:0] selected_out);
always_comb begin
/* -----\/----- EXCLUDED -----\/-----
if ( selector[3:0] inside { 4'b?00?, 4'b1100}) // Matching 0000, 0001, 1000, 1100, 1001
// if ( selector[3:2] inside { 2'b?0, selector[1:0]})
selected_out = wide_input_bus[ 7: 0];
else
-----/\----- EXCLUDED -----/\----- */
/* verilator lint_off CASEOVERLAP */
priority casez (selector[3:0])
4'b0?10: selected_out = wide_input_bus[ 15: 8]; // Matching 0010 and 0110
4'b0??0: selected_out = wide_input_bus[ 23: 16]; // Overlap: only 0100 remains (0000 in "if" above)
4'b0100: selected_out = wide_input_bus[ 31: 24]; // Overlap: Will never occur
default: selected_out = wide_input_bus[127:120]; // Remaining 0011,0100,0101,0111,1010,1011,1101,1110,1111
endcase // case (selector)
/* verilator lint_on CASEOVERLAP */
end
endmodule // simple_test_3f
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__AND2B_BEHAVIORAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2B_BEHAVIORAL_PP_V |
module merge_step(X9,Y9,b,X17,Y17,clk);
`define WIDTH 22
input clk;
input [`WIDTH-1:0] X9;
input [`WIDTH-1:0] Y9;
input [7:0] b;
output reg [`WIDTH-1:0] X17;
output reg [`WIDTH-1:0] Y17;
wire [`WIDTH-1:0] tmpX10;
wire [`WIDTH-1:0] tmpX11;
wire [`WIDTH-1:0] tmpX12;
wire [`WIDTH-1:0] tmpX13;
wire [`WIDTH-1:0] tmpX14;
wire [`WIDTH-1:0] tmpX15;
wire [`WIDTH-1:0] tmpX16;
wire [`WIDTH-1:0] tmpX17;
wire [`WIDTH-1:0] tmpY10;
wire [`WIDTH-1:0] tmpY11;
wire [`WIDTH-1:0] tmpY12;
wire [`WIDTH-1:0] tmpY13;
wire [`WIDTH-1:0] tmpY14;
wire [`WIDTH-1:0] tmpY15;
wire [`WIDTH-1:0] tmpY16;
wire [`WIDTH-1:0] tmpY17;
//
//merge Y
merge_loc #(.shift_num(9))
M1 (.A_in(Y9),.b(b[7]),.A_out(tmpY10),.clk(clk));
merge_loc #(.shift_num(10))
M2 (.A_in(Y9),.b(b[6]),.A_out(tmpY11),.clk(clk));
merge_loc #(.shift_num(11))
M3 (.A_in(Y9),.b(b[5]),.A_out(tmpY12),.clk(clk));
merge_loc #(.shift_num(12))
M4 (.A_in(Y9),.b(b[4]),.A_out(tmpY13),.clk(clk));
merge_loc #(.shift_num(13))
M5 (.A_in(Y9),.b(b[3]),.A_out(tmpY14),.clk(clk));
merge_loc #(.shift_num(14))
M6 (.A_in(Y9),.b(b[2]),.A_out(tmpY15),.clk(clk));
merge_loc #(.shift_num(15))
M7 (.A_in(Y9),.b(b[1]),.A_out(tmpY16),.clk(clk));
merge_loc #(.shift_num(16))
M8 (.A_in(Y9),.b(b[0]),.A_out(tmpY17),.clk(clk));
//merge X
merge_loc #(.shift_num(9))
M9 (.A_in(X9),.b(b[7]),.A_out(tmpX10),.clk(clk));
merge_loc #(.shift_num(10))
M10 (.A_in(X9),.b(b[6]),.A_out(tmpX11),.clk(clk));
merge_loc #(.shift_num(11))
M11 (.A_in(X9),.b(b[5]),.A_out(tmpX12),.clk(clk));
merge_loc #(.shift_num(12))
M12 (.A_in(X9),.b(b[4]),.A_out(tmpX13),.clk(clk));
merge_loc #(.shift_num(13))
M13 (.A_in(X9),.b(b[3]),.A_out(tmpX14),.clk(clk));
merge_loc #(.shift_num(14))
M14 (.A_in(X9),.b(b[2]),.A_out(tmpX15),.clk(clk));
merge_loc #(.shift_num(15))
M15 (.A_in(X9),.b(b[1]),.A_out(tmpX16),.clk(clk));
merge_loc #(.shift_num(16))
M16 (.A_in(X9),.b(b[0]),.A_out(tmpX17),.clk(clk));
//sum X17,Y17
always @(*)begin
if(X17>=22'b0111111111111111111111)
X17<=22'b0111111111111111111111;
end
always @(X9 or Y9) begin
X17<=X9-tmpY10-tmpY11-tmpY12-tmpY13-tmpY14-tmpY15-tmpY16-tmpY17;
Y17<=Y9+tmpX10+tmpX11+tmpX12+tmpX13+tmpX14+tmpX15+tmpX16+tmpX17;
// $display("X17=%d,Y17=%d",X17,Y17);
end
endmodule
|
//=============================================================
//
// Copyright (c) 2017 Simon Southwell. All rights reserved.
//
// Date: 30th May 2017
//
// This code is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// The code is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this code. If not, see <http://www.gnu.org/licenses/>.
//
// $Id: test.v,v 1.5 2017/08/28 13:05:19 simon Exp $
// $Source: /home/simon/CVS/src/cpu/mico32/HDL/test/verilog/test.v,v $
//
//=============================================================
//=============================================================
// test
//
// Top level test module, instantiating the UUT, drivers
// memory and a monitor
//
//=============================================================
`include "test_defs.vh"
module test;
wire CLOCK_50;
wire jtag_clk;
wire nreset;
wire jtag_done;
// Display interface
wire [27:0] HEX;
wire [7:0] LEDG;
wire [9:0] LEDR;
// UART
wire UART_TXD;
wire UART_RXD;
// SRAM Interface
wire [15:0] SRAM_DQ;
wire [17:0] SRAM_ADDR;
wire SRAM_UB_N;
wire SRAM_LB_N;
wire SRAM_WE_N;
wire SRAM_CE_N;
wire SRAM_OE_N;
// SDRAM Interface
wire [15:0] DRAM_DQ;
wire [11:0] DRAM_ADDR;
wire DRAM_LDQM;
wire DRAM_UDQM;
wire DRAM_WE_N;
wire DRAM_CAS_N;
wire DRAM_RAS_N;
wire DRAM_CS_N;
wire DRAM_BA_0;
wire DRAM_BA_1;
wire DRAM_CLK;
wire DRAM_CKE;
// USB-JTAG
wire TDI;
wire TCS;
wire TDO;
wire TCK;
// I2C
wire I2C_SDAT;
wire I2C_SCLK;
// PS2
wire PS2_CLK;
wire PS2_DAT;
// UART
wire UART_TXRDY;
wire [7:0] UART_TXDATA;
wire UART_TXACK;
wire UART_RXRDY;
wire [7:0] UART_RXDATA;
wire UART_RXERR;
wire [35:0] GPIO_0;
wire [35:0] GPIO_1;
//-------------------------------------------------------------
// Hierarchical code
alt_lm32 UUT (
// Clock Input
.CLOCK_50 (CLOCK_50),
// Push Button
.KEY ({3'b111, nreset}),
.SW (10'h000),
// 7-SEG Display
.HEX0 (HEX[6:0]),
.HEX1 (HEX[13:7]),
.HEX2 (HEX[20:14]),
.HEX3 (HEX[27:21]),
// LED
.LEDG (LEDG),
.LEDR (LEDR),
// UART
.UART_TXD (UART_TXD),
.UART_RXD (UART_RXD),
// SRAM Interface
.SRAM_DQ (SRAM_DQ),
.SRAM_ADDR (SRAM_ADDR),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_WE_N (SRAM_WE_N),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_OE_N (SRAM_OE_N),
// SDRAM interface
.DRAM_DQ (DRAM_DQ),
.DRAM_ADDR (DRAM_ADDR),
.DRAM_LDQM (DRAM_LDQM),
.DRAM_UDQM (DRAM_UDQM),
.DRAM_WE_N (DRAM_WE_N),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_BA_0 (DRAM_BA_0),
.DRAM_BA_1 (DRAM_BA_1),
.DRAM_CLK (DRAM_CLK),
.DRAM_CKE (DRAM_CKE),
// USB JTAG link
.TDI (TDI),
.TCK (TCK),
.TCS (TCS),
.TDO (TDO),
// I2C interface
.I2C_SCLK (I2C_SCLK),
.I2C_SDAT (I2C_SDAT),
// PS2 interface
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// GPIO interface
.GPIO_0 (GPIO_0),
.GPIO_1 (GPIO_1)
);
// Define parameters for PLL1 test component in UUT. PLL1 simulation
// model has a compatible subset of parameters to the Altera component,
// and so could be substituted for Altera's model.
defparam UUT.p1.altpll_component.inclk0_input_frequency = `CLKPERIOD50, // inclk0 is 50MHz
UUT.p1.altpll_component.clk0_multiply_by = `CLKMUL0, // c0 is inclk0 * 4 / 5 = 40MHz
UUT.p1.altpll_component.clk0_divide_by = `CLKDIV0,
UUT.p1.altpll_component.clk1_multiply_by = `CLKMUL1, // c1 is inclk0 * 4 / 5 = 40MHz
UUT.p1.altpll_component.clk1_divide_by = `CLKDIV1,
UUT.p1.altpll_component.clk2_multiply_by = `CLKMUL2, // c2 is inclk0 * 8 / 5 = 80MHz
UUT.p1.altpll_component.clk2_divide_by = `CLKDIV2,
UUT.p1.altpll_component.clk2_phase_shift = `CLKPHASE2_180, // 180 deg phase shift
UUT.u2.u1.clk_freq_khz = `SYS_CLK_FREQ_KHZ,
UUT.u2.u1.i2c_freq_khz = `I2C_CLK_FREQ_KHZ,
UUT.u4.BAUD_RATE = `TEST_BAUDRATE;
sram sram (
.SRAM_DQ (SRAM_DQ),
.SRAM_ADDR (SRAM_ADDR),
.SRAM_UB_N (SRAM_UB_N),
.SRAM_LB_N (SRAM_LB_N),
.SRAM_WE_N (SRAM_WE_N),
.SRAM_CE_N (SRAM_CE_N),
.SRAM_OE_N (SRAM_OE_N)
);
sdram_1Mx16x4 sdram (
.DRAM_DQ (DRAM_DQ),
.DRAM_ADDR (DRAM_ADDR),
.DRAM_LDQM (DRAM_LDQM),
.DRAM_UDQM (DRAM_UDQM),
.DRAM_WE_N (DRAM_WE_N),
.DRAM_CAS_N (DRAM_CAS_N),
.DRAM_RAS_N (DRAM_RAS_N),
.DRAM_CS_N (DRAM_CS_N),
.DRAM_BA_0 (DRAM_BA_0),
.DRAM_BA_1 (DRAM_BA_1),
.DRAM_CLK (DRAM_CLK),
.DRAM_CKE (DRAM_CKE)
);
jtag_drv jtag (
.clk (jtag_clk),
.nreset (nreset),
.TDI (TDI),
.TCK (TCK),
.TCS (TCS),
.TDO (TDO),
.done (jtag_done)
);
uart_drv uart (
.clk (CLOCK_50),
.nreset (nreset),
.rx (UART_TXD),
.tx (UART_RXD),
.txrdy (UART_TXRDY),
.txdata (UART_TXDATA),
.txack (UART_TXACK),
.rxrdy (UART_RXRDY),
.rxdata (UART_RXDATA),
.rxerr (UART_RXERR)
);
i2c_drv i2c (
.I2C_SCLK (I2C_SCLK),
.I2C_SDAT (I2C_SDAT)
);
monitor mon (
.CLOCK_50 (CLOCK_50),
.jtag_clk (jtag_clk),
.nreset (nreset),
.jtag_done (jtag_done),
// PS2 interface
.PS2_CLK (PS2_CLK),
.PS2_DAT (PS2_DAT),
// LEDs
.HEX (HEX),
.LEDG (LEDG),
.LEDR (LEDR),
// UART
.txrdy (UART_TXRDY),
.txdata (UART_TXDATA),
.txack (UART_TXACK),
.rxrdy (UART_RXRDY),
.rxdata (UART_RXDATA),
.rxerr (UART_RXERR)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 14:33:23 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n286, n287, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n675, n677, n678, n679, n680,
n681, n682, n683, n684, n685, n686, n687, n688, n689, n690, n691,
n692, n693, n694, n695, n696, n697, n698, n699, n700, n701, n702,
n703, n704, n705, n706, n707, n708, n709, n710, n711, n712, n713,
n714, n715, DP_OP_36J30_123_1029_n28, DP_OP_36J30_123_1029_n27,
DP_OP_36J30_123_1029_n26, DP_OP_36J30_123_1029_n25,
DP_OP_36J30_123_1029_n24, DP_OP_36J30_123_1029_n23,
DP_OP_36J30_123_1029_n22, DP_OP_36J30_123_1029_n21,
DP_OP_36J30_123_1029_n20, DP_OP_36J30_123_1029_n19,
DP_OP_36J30_123_1029_n18, DP_OP_36J30_123_1029_n12,
DP_OP_36J30_123_1029_n11, DP_OP_36J30_123_1029_n10,
DP_OP_36J30_123_1029_n9, DP_OP_36J30_123_1029_n8,
DP_OP_36J30_123_1029_n7, DP_OP_36J30_123_1029_n6,
DP_OP_36J30_123_1029_n5, DP_OP_36J30_123_1029_n4,
DP_OP_36J30_123_1029_n3, DP_OP_36J30_123_1029_n2,
DP_OP_36J30_123_1029_n1, DP_OP_168J30_122_4811_n4552,
DP_OP_168J30_122_4811_n4544, DP_OP_168J30_122_4811_n4543,
DP_OP_168J30_122_4811_n4542, DP_OP_168J30_122_4811_n4541,
DP_OP_168J30_122_4811_n4540, DP_OP_168J30_122_4811_n4539,
DP_OP_168J30_122_4811_n4538, DP_OP_168J30_122_4811_n4537,
DP_OP_168J30_122_4811_n4536, DP_OP_168J30_122_4811_n4535,
DP_OP_168J30_122_4811_n4534, DP_OP_168J30_122_4811_n4533,
DP_OP_168J30_122_4811_n4532, DP_OP_168J30_122_4811_n4531,
DP_OP_168J30_122_4811_n4530, DP_OP_168J30_122_4811_n4529,
DP_OP_168J30_122_4811_n4528, DP_OP_168J30_122_4811_n4527,
DP_OP_168J30_122_4811_n4526, DP_OP_168J30_122_4811_n4524,
DP_OP_168J30_122_4811_n4523, DP_OP_168J30_122_4811_n4518,
DP_OP_168J30_122_4811_n4517, DP_OP_168J30_122_4811_n4516,
DP_OP_168J30_122_4811_n4515, DP_OP_168J30_122_4811_n4514,
DP_OP_168J30_122_4811_n4513, DP_OP_168J30_122_4811_n4512,
DP_OP_168J30_122_4811_n4511, DP_OP_168J30_122_4811_n4510,
DP_OP_168J30_122_4811_n4509, DP_OP_168J30_122_4811_n4508,
DP_OP_168J30_122_4811_n4507, DP_OP_168J30_122_4811_n4506,
DP_OP_168J30_122_4811_n4505, DP_OP_168J30_122_4811_n4504,
DP_OP_168J30_122_4811_n4503, DP_OP_168J30_122_4811_n4502,
DP_OP_168J30_122_4811_n4501, DP_OP_168J30_122_4811_n4500,
DP_OP_168J30_122_4811_n4499, DP_OP_168J30_122_4811_n4498,
DP_OP_168J30_122_4811_n4497, DP_OP_168J30_122_4811_n4495,
DP_OP_168J30_122_4811_n4494, DP_OP_168J30_122_4811_n4486,
DP_OP_168J30_122_4811_n4485, DP_OP_168J30_122_4811_n4484,
DP_OP_168J30_122_4811_n4483, DP_OP_168J30_122_4811_n4482,
DP_OP_168J30_122_4811_n4481, DP_OP_168J30_122_4811_n4480,
DP_OP_168J30_122_4811_n4479, DP_OP_168J30_122_4811_n4478,
DP_OP_168J30_122_4811_n4477, DP_OP_168J30_122_4811_n4476,
DP_OP_168J30_122_4811_n4475, DP_OP_168J30_122_4811_n4474,
DP_OP_168J30_122_4811_n4473, DP_OP_168J30_122_4811_n4472,
DP_OP_168J30_122_4811_n4471, DP_OP_168J30_122_4811_n4470,
DP_OP_168J30_122_4811_n4469, DP_OP_168J30_122_4811_n4468,
DP_OP_168J30_122_4811_n4466, DP_OP_168J30_122_4811_n4465,
DP_OP_168J30_122_4811_n4460, DP_OP_168J30_122_4811_n4459,
DP_OP_168J30_122_4811_n4458, DP_OP_168J30_122_4811_n4457,
DP_OP_168J30_122_4811_n4456, DP_OP_168J30_122_4811_n4455,
DP_OP_168J30_122_4811_n4454, DP_OP_168J30_122_4811_n4453,
DP_OP_168J30_122_4811_n4452, DP_OP_168J30_122_4811_n4451,
DP_OP_168J30_122_4811_n4450, DP_OP_168J30_122_4811_n4449,
DP_OP_168J30_122_4811_n4448, DP_OP_168J30_122_4811_n4447,
DP_OP_168J30_122_4811_n4446, DP_OP_168J30_122_4811_n4445,
DP_OP_168J30_122_4811_n4444, DP_OP_168J30_122_4811_n4443,
DP_OP_168J30_122_4811_n4442, DP_OP_168J30_122_4811_n4441,
DP_OP_168J30_122_4811_n4440, DP_OP_168J30_122_4811_n4439,
DP_OP_168J30_122_4811_n4437, DP_OP_168J30_122_4811_n4436,
DP_OP_168J30_122_4811_n4428, DP_OP_168J30_122_4811_n4427,
DP_OP_168J30_122_4811_n4426, DP_OP_168J30_122_4811_n4425,
DP_OP_168J30_122_4811_n4424, DP_OP_168J30_122_4811_n4423,
DP_OP_168J30_122_4811_n4422, DP_OP_168J30_122_4811_n4421,
DP_OP_168J30_122_4811_n4420, DP_OP_168J30_122_4811_n4419,
DP_OP_168J30_122_4811_n4418, DP_OP_168J30_122_4811_n4417,
DP_OP_168J30_122_4811_n4416, DP_OP_168J30_122_4811_n4415,
DP_OP_168J30_122_4811_n4414, DP_OP_168J30_122_4811_n4413,
DP_OP_168J30_122_4811_n4412, DP_OP_168J30_122_4811_n4411,
DP_OP_168J30_122_4811_n4410, DP_OP_168J30_122_4811_n4408,
DP_OP_168J30_122_4811_n4407, DP_OP_168J30_122_4811_n4402,
DP_OP_168J30_122_4811_n4401, DP_OP_168J30_122_4811_n4400,
DP_OP_168J30_122_4811_n4399, DP_OP_168J30_122_4811_n4398,
DP_OP_168J30_122_4811_n4397, DP_OP_168J30_122_4811_n4396,
DP_OP_168J30_122_4811_n4395, DP_OP_168J30_122_4811_n4394,
DP_OP_168J30_122_4811_n4393, DP_OP_168J30_122_4811_n4392,
DP_OP_168J30_122_4811_n4391, DP_OP_168J30_122_4811_n4390,
DP_OP_168J30_122_4811_n4389, DP_OP_168J30_122_4811_n4388,
DP_OP_168J30_122_4811_n4387, DP_OP_168J30_122_4811_n4386,
DP_OP_168J30_122_4811_n4385, DP_OP_168J30_122_4811_n4384,
DP_OP_168J30_122_4811_n4383, DP_OP_168J30_122_4811_n4382,
DP_OP_168J30_122_4811_n4381, DP_OP_168J30_122_4811_n4379,
DP_OP_168J30_122_4811_n4378, DP_OP_168J30_122_4811_n4366,
DP_OP_168J30_122_4811_n4365, DP_OP_168J30_122_4811_n4364,
DP_OP_168J30_122_4811_n4363, DP_OP_168J30_122_4811_n4360,
DP_OP_168J30_122_4811_n4359, DP_OP_168J30_122_4811_n4358,
DP_OP_168J30_122_4811_n4357, DP_OP_168J30_122_4811_n4355,
DP_OP_168J30_122_4811_n4354, DP_OP_168J30_122_4811_n4353,
DP_OP_168J30_122_4811_n4352, DP_OP_168J30_122_4811_n4339,
DP_OP_168J30_122_4811_n4338, DP_OP_168J30_122_4811_n4334,
DP_OP_168J30_122_4811_n4333, DP_OP_168J30_122_4811_n4329,
DP_OP_168J30_122_4811_n4328, DP_OP_168J30_122_4811_n4327,
DP_OP_168J30_122_4811_n4198, DP_OP_168J30_122_4811_n4196,
DP_OP_168J30_122_4811_n4195, DP_OP_168J30_122_4811_n4193,
DP_OP_168J30_122_4811_n4192, DP_OP_168J30_122_4811_n4191,
DP_OP_168J30_122_4811_n4190, DP_OP_168J30_122_4811_n4188,
DP_OP_168J30_122_4811_n4187, DP_OP_168J30_122_4811_n4186,
DP_OP_168J30_122_4811_n4185, DP_OP_168J30_122_4811_n4183,
DP_OP_168J30_122_4811_n4182, DP_OP_168J30_122_4811_n4181,
DP_OP_168J30_122_4811_n4178, DP_OP_168J30_122_4811_n4176,
DP_OP_168J30_122_4811_n4175, DP_OP_168J30_122_4811_n4174,
DP_OP_168J30_122_4811_n4171, DP_OP_168J30_122_4811_n4169,
DP_OP_168J30_122_4811_n4168, DP_OP_168J30_122_4811_n4167,
DP_OP_168J30_122_4811_n4165, DP_OP_168J30_122_4811_n4164,
DP_OP_168J30_122_4811_n4163, DP_OP_168J30_122_4811_n4162,
DP_OP_168J30_122_4811_n4161, DP_OP_168J30_122_4811_n4160,
DP_OP_168J30_122_4811_n4159, DP_OP_168J30_122_4811_n4157,
DP_OP_168J30_122_4811_n4156, DP_OP_168J30_122_4811_n4155,
DP_OP_168J30_122_4811_n4154, DP_OP_168J30_122_4811_n4153,
DP_OP_168J30_122_4811_n4152, DP_OP_168J30_122_4811_n4151,
DP_OP_168J30_122_4811_n4149, DP_OP_168J30_122_4811_n4148,
DP_OP_168J30_122_4811_n4147, DP_OP_168J30_122_4811_n4146,
DP_OP_168J30_122_4811_n4145, DP_OP_168J30_122_4811_n4144,
DP_OP_168J30_122_4811_n4143, DP_OP_168J30_122_4811_n4141,
DP_OP_168J30_122_4811_n4140, DP_OP_168J30_122_4811_n4139,
DP_OP_168J30_122_4811_n4138, DP_OP_168J30_122_4811_n4137,
DP_OP_168J30_122_4811_n4136, DP_OP_168J30_122_4811_n4133,
DP_OP_168J30_122_4811_n4131, DP_OP_168J30_122_4811_n4130,
DP_OP_168J30_122_4811_n4129, DP_OP_168J30_122_4811_n4128,
DP_OP_168J30_122_4811_n4127, DP_OP_168J30_122_4811_n4126,
DP_OP_168J30_122_4811_n4123, DP_OP_168J30_122_4811_n4121,
DP_OP_168J30_122_4811_n4120, DP_OP_168J30_122_4811_n4119,
DP_OP_168J30_122_4811_n4118, DP_OP_168J30_122_4811_n4117,
DP_OP_168J30_122_4811_n4116, DP_OP_168J30_122_4811_n4114,
DP_OP_168J30_122_4811_n4113, DP_OP_168J30_122_4811_n4112,
DP_OP_168J30_122_4811_n4111, DP_OP_168J30_122_4811_n4110,
DP_OP_168J30_122_4811_n4109, DP_OP_168J30_122_4811_n4108,
DP_OP_168J30_122_4811_n4107, DP_OP_168J30_122_4811_n4106,
DP_OP_168J30_122_4811_n4105, DP_OP_168J30_122_4811_n4103,
DP_OP_168J30_122_4811_n4102, DP_OP_168J30_122_4811_n4101,
DP_OP_168J30_122_4811_n4100, DP_OP_168J30_122_4811_n4099,
DP_OP_168J30_122_4811_n4098, DP_OP_168J30_122_4811_n4097,
DP_OP_168J30_122_4811_n4096, DP_OP_168J30_122_4811_n4095,
DP_OP_168J30_122_4811_n4094, DP_OP_168J30_122_4811_n4092,
DP_OP_168J30_122_4811_n4091, DP_OP_168J30_122_4811_n4090,
DP_OP_168J30_122_4811_n4089, DP_OP_168J30_122_4811_n4088,
DP_OP_168J30_122_4811_n4087, DP_OP_168J30_122_4811_n4086,
DP_OP_168J30_122_4811_n4085, DP_OP_168J30_122_4811_n4084,
DP_OP_168J30_122_4811_n4083, DP_OP_168J30_122_4811_n4081,
DP_OP_168J30_122_4811_n4080, DP_OP_168J30_122_4811_n4079,
DP_OP_168J30_122_4811_n4078, DP_OP_168J30_122_4811_n4077,
DP_OP_168J30_122_4811_n4076, DP_OP_168J30_122_4811_n4075,
DP_OP_168J30_122_4811_n4074, DP_OP_168J30_122_4811_n4073,
DP_OP_168J30_122_4811_n4072, DP_OP_168J30_122_4811_n4070,
DP_OP_168J30_122_4811_n4069, DP_OP_168J30_122_4811_n4068,
DP_OP_168J30_122_4811_n4067, DP_OP_168J30_122_4811_n4066,
DP_OP_168J30_122_4811_n4065, DP_OP_168J30_122_4811_n4064,
DP_OP_168J30_122_4811_n4063, DP_OP_168J30_122_4811_n4062,
DP_OP_168J30_122_4811_n4061, DP_OP_168J30_122_4811_n4059,
DP_OP_168J30_122_4811_n4058, DP_OP_168J30_122_4811_n4057,
DP_OP_168J30_122_4811_n4056, DP_OP_168J30_122_4811_n4055,
DP_OP_168J30_122_4811_n4054, DP_OP_168J30_122_4811_n4053,
DP_OP_168J30_122_4811_n4052, DP_OP_168J30_122_4811_n4051,
DP_OP_168J30_122_4811_n4050, DP_OP_168J30_122_4811_n4048,
DP_OP_168J30_122_4811_n4047, DP_OP_168J30_122_4811_n4046,
DP_OP_168J30_122_4811_n4045, DP_OP_168J30_122_4811_n4044,
DP_OP_168J30_122_4811_n4043, DP_OP_168J30_122_4811_n4042,
DP_OP_168J30_122_4811_n4041, DP_OP_168J30_122_4811_n4040,
DP_OP_168J30_122_4811_n4039, DP_OP_168J30_122_4811_n4038,
DP_OP_168J30_122_4811_n4037, DP_OP_168J30_122_4811_n4036,
DP_OP_168J30_122_4811_n4035, DP_OP_168J30_122_4811_n4034,
DP_OP_168J30_122_4811_n4033, DP_OP_168J30_122_4811_n4032,
DP_OP_168J30_122_4811_n4031, DP_OP_168J30_122_4811_n4030,
DP_OP_168J30_122_4811_n4029, DP_OP_168J30_122_4811_n4028,
DP_OP_168J30_122_4811_n4027, DP_OP_168J30_122_4811_n4026,
DP_OP_168J30_122_4811_n4025, DP_OP_168J30_122_4811_n4024,
DP_OP_168J30_122_4811_n4023, DP_OP_168J30_122_4811_n4022,
DP_OP_168J30_122_4811_n4021, DP_OP_168J30_122_4811_n4020,
DP_OP_168J30_122_4811_n4019, DP_OP_168J30_122_4811_n4018,
DP_OP_168J30_122_4811_n4017, DP_OP_168J30_122_4811_n4016,
DP_OP_168J30_122_4811_n4015, DP_OP_168J30_122_4811_n4014,
DP_OP_168J30_122_4811_n4013, DP_OP_168J30_122_4811_n4012,
DP_OP_168J30_122_4811_n4011, DP_OP_168J30_122_4811_n4010,
DP_OP_168J30_122_4811_n4009, DP_OP_168J30_122_4811_n4008,
DP_OP_168J30_122_4811_n4007, DP_OP_168J30_122_4811_n4006,
DP_OP_168J30_122_4811_n4005, DP_OP_168J30_122_4811_n4004,
DP_OP_168J30_122_4811_n4003, DP_OP_168J30_122_4811_n4002,
DP_OP_168J30_122_4811_n4001, DP_OP_168J30_122_4811_n4000,
DP_OP_168J30_122_4811_n3999, DP_OP_168J30_122_4811_n3998,
DP_OP_168J30_122_4811_n3997, DP_OP_168J30_122_4811_n3996,
DP_OP_168J30_122_4811_n3995, DP_OP_168J30_122_4811_n3994,
DP_OP_168J30_122_4811_n3993, DP_OP_168J30_122_4811_n3992,
DP_OP_168J30_122_4811_n3991, DP_OP_168J30_122_4811_n3990,
DP_OP_168J30_122_4811_n3989, DP_OP_168J30_122_4811_n3988,
DP_OP_168J30_122_4811_n3987, DP_OP_168J30_122_4811_n3986,
DP_OP_168J30_122_4811_n3985, DP_OP_168J30_122_4811_n3984,
DP_OP_168J30_122_4811_n3983, DP_OP_168J30_122_4811_n3982,
DP_OP_168J30_122_4811_n3981, DP_OP_168J30_122_4811_n3980,
DP_OP_168J30_122_4811_n3979, DP_OP_168J30_122_4811_n3978,
DP_OP_168J30_122_4811_n3977, DP_OP_168J30_122_4811_n3976,
DP_OP_168J30_122_4811_n3975, DP_OP_168J30_122_4811_n3973,
DP_OP_168J30_122_4811_n3972, DP_OP_168J30_122_4811_n3971,
DP_OP_168J30_122_4811_n3970, DP_OP_168J30_122_4811_n3969,
DP_OP_168J30_122_4811_n3968, DP_OP_168J30_122_4811_n3967,
DP_OP_168J30_122_4811_n3966, DP_OP_168J30_122_4811_n3965,
DP_OP_168J30_122_4811_n3964, DP_OP_168J30_122_4811_n3963,
DP_OP_168J30_122_4811_n3962, DP_OP_168J30_122_4811_n3961,
DP_OP_168J30_122_4811_n3960, DP_OP_168J30_122_4811_n3959,
DP_OP_168J30_122_4811_n3958, DP_OP_168J30_122_4811_n3957,
DP_OP_168J30_122_4811_n3956, DP_OP_168J30_122_4811_n3954,
DP_OP_168J30_122_4811_n3953, DP_OP_168J30_122_4811_n3952,
DP_OP_168J30_122_4811_n3951, DP_OP_168J30_122_4811_n3950,
DP_OP_168J30_122_4811_n3949, DP_OP_168J30_122_4811_n3948,
DP_OP_168J30_122_4811_n3947, DP_OP_168J30_122_4811_n3945,
DP_OP_168J30_122_4811_n3944, DP_OP_168J30_122_4811_n3943,
DP_OP_168J30_122_4811_n3942, DP_OP_168J30_122_4811_n3941,
DP_OP_168J30_122_4811_n3940, DP_OP_168J30_122_4811_n3939,
DP_OP_168J30_122_4811_n3938, DP_OP_168J30_122_4811_n3937,
DP_OP_168J30_122_4811_n3936, DP_OP_168J30_122_4811_n3935,
DP_OP_168J30_122_4811_n3934, DP_OP_168J30_122_4811_n3933,
DP_OP_168J30_122_4811_n3932, DP_OP_168J30_122_4811_n3931,
DP_OP_168J30_122_4811_n3930, DP_OP_168J30_122_4811_n3929,
DP_OP_168J30_122_4811_n3928, DP_OP_168J30_122_4811_n3927,
DP_OP_168J30_122_4811_n3926, DP_OP_168J30_122_4811_n3925,
DP_OP_168J30_122_4811_n3924, DP_OP_168J30_122_4811_n3923,
DP_OP_168J30_122_4811_n3922, DP_OP_168J30_122_4811_n3920,
DP_OP_168J30_122_4811_n3919, DP_OP_168J30_122_4811_n3918,
DP_OP_168J30_122_4811_n3917, DP_OP_168J30_122_4811_n3916,
DP_OP_168J30_122_4811_n3915, DP_OP_168J30_122_4811_n3914,
DP_OP_168J30_122_4811_n3913, DP_OP_168J30_122_4811_n3912,
DP_OP_168J30_122_4811_n3911, DP_OP_168J30_122_4811_n3910,
DP_OP_168J30_122_4811_n3909, DP_OP_168J30_122_4811_n3907,
DP_OP_168J30_122_4811_n3905, DP_OP_168J30_122_4811_n3904,
DP_OP_168J30_122_4811_n3903, DP_OP_168J30_122_4811_n3901,
DP_OP_168J30_122_4811_n3900, DP_OP_168J30_122_4811_n3899,
DP_OP_168J30_122_4811_n3898, DP_OP_168J30_122_4811_n3897,
DP_OP_168J30_122_4811_n3896, DP_OP_168J30_122_4811_n3895,
DP_OP_168J30_122_4811_n3894, DP_OP_168J30_122_4811_n3893,
DP_OP_168J30_122_4811_n3892, DP_OP_168J30_122_4811_n3891,
DP_OP_168J30_122_4811_n3890, DP_OP_168J30_122_4811_n3889,
DP_OP_168J30_122_4811_n3888, DP_OP_168J30_122_4811_n3886,
DP_OP_168J30_122_4811_n3885, DP_OP_168J30_122_4811_n3884,
DP_OP_168J30_122_4811_n3883, DP_OP_168J30_122_4811_n3882,
DP_OP_168J30_122_4811_n3881, DP_OP_168J30_122_4811_n3876,
DP_OP_168J30_122_4811_n3615, DP_OP_168J30_122_4811_n2964,
DP_OP_168J30_122_4811_n2963, DP_OP_168J30_122_4811_n2962,
DP_OP_168J30_122_4811_n2961, DP_OP_168J30_122_4811_n2960,
DP_OP_168J30_122_4811_n2959, DP_OP_168J30_122_4811_n2958,
DP_OP_168J30_122_4811_n2957, DP_OP_168J30_122_4811_n2956,
DP_OP_168J30_122_4811_n2955, DP_OP_168J30_122_4811_n2954,
DP_OP_168J30_122_4811_n2953, DP_OP_168J30_122_4811_n2952,
DP_OP_168J30_122_4811_n2951, DP_OP_168J30_122_4811_n2950,
DP_OP_168J30_122_4811_n2949, DP_OP_168J30_122_4811_n2948,
DP_OP_168J30_122_4811_n2947, DP_OP_168J30_122_4811_n2946,
DP_OP_168J30_122_4811_n2945, DP_OP_168J30_122_4811_n2944,
DP_OP_168J30_122_4811_n2942, DP_OP_168J30_122_4811_n2937,
DP_OP_168J30_122_4811_n2936, DP_OP_168J30_122_4811_n2935,
DP_OP_168J30_122_4811_n2934, DP_OP_168J30_122_4811_n2933,
DP_OP_168J30_122_4811_n2932, DP_OP_168J30_122_4811_n2931,
DP_OP_168J30_122_4811_n2930, DP_OP_168J30_122_4811_n2929,
DP_OP_168J30_122_4811_n2928, DP_OP_168J30_122_4811_n2927,
DP_OP_168J30_122_4811_n2926, DP_OP_168J30_122_4811_n2925,
DP_OP_168J30_122_4811_n2924, DP_OP_168J30_122_4811_n2923,
DP_OP_168J30_122_4811_n2922, DP_OP_168J30_122_4811_n2921,
DP_OP_168J30_122_4811_n2920, DP_OP_168J30_122_4811_n2919,
DP_OP_168J30_122_4811_n2918, DP_OP_168J30_122_4811_n2917,
DP_OP_168J30_122_4811_n2916, DP_OP_168J30_122_4811_n2915,
DP_OP_168J30_122_4811_n2914, DP_OP_168J30_122_4811_n2913,
DP_OP_168J30_122_4811_n2912, DP_OP_168J30_122_4811_n2904,
DP_OP_168J30_122_4811_n2903, DP_OP_168J30_122_4811_n2902,
DP_OP_168J30_122_4811_n2901, DP_OP_168J30_122_4811_n2900,
DP_OP_168J30_122_4811_n2899, DP_OP_168J30_122_4811_n2898,
DP_OP_168J30_122_4811_n2897, DP_OP_168J30_122_4811_n2896,
DP_OP_168J30_122_4811_n2895, DP_OP_168J30_122_4811_n2894,
DP_OP_168J30_122_4811_n2893, DP_OP_168J30_122_4811_n2892,
DP_OP_168J30_122_4811_n2891, DP_OP_168J30_122_4811_n2890,
DP_OP_168J30_122_4811_n2889, DP_OP_168J30_122_4811_n2888,
DP_OP_168J30_122_4811_n2887, DP_OP_168J30_122_4811_n2886,
DP_OP_168J30_122_4811_n2885, DP_OP_168J30_122_4811_n2884,
DP_OP_168J30_122_4811_n2883, DP_OP_168J30_122_4811_n2882,
DP_OP_168J30_122_4811_n2877, DP_OP_168J30_122_4811_n2876,
DP_OP_168J30_122_4811_n2875, DP_OP_168J30_122_4811_n2874,
DP_OP_168J30_122_4811_n2873, DP_OP_168J30_122_4811_n2872,
DP_OP_168J30_122_4811_n2871, DP_OP_168J30_122_4811_n2870,
DP_OP_168J30_122_4811_n2869, DP_OP_168J30_122_4811_n2868,
DP_OP_168J30_122_4811_n2867, DP_OP_168J30_122_4811_n2866,
DP_OP_168J30_122_4811_n2865, DP_OP_168J30_122_4811_n2864,
DP_OP_168J30_122_4811_n2863, DP_OP_168J30_122_4811_n2862,
DP_OP_168J30_122_4811_n2861, DP_OP_168J30_122_4811_n2860,
DP_OP_168J30_122_4811_n2859, DP_OP_168J30_122_4811_n2858,
DP_OP_168J30_122_4811_n2857, DP_OP_168J30_122_4811_n2856,
DP_OP_168J30_122_4811_n2855, DP_OP_168J30_122_4811_n2854,
DP_OP_168J30_122_4811_n2853, DP_OP_168J30_122_4811_n2852,
DP_OP_168J30_122_4811_n2844, DP_OP_168J30_122_4811_n2843,
DP_OP_168J30_122_4811_n2842, DP_OP_168J30_122_4811_n2841,
DP_OP_168J30_122_4811_n2840, DP_OP_168J30_122_4811_n2839,
DP_OP_168J30_122_4811_n2838, DP_OP_168J30_122_4811_n2837,
DP_OP_168J30_122_4811_n2836, DP_OP_168J30_122_4811_n2835,
DP_OP_168J30_122_4811_n2834, DP_OP_168J30_122_4811_n2833,
DP_OP_168J30_122_4811_n2832, DP_OP_168J30_122_4811_n2831,
DP_OP_168J30_122_4811_n2830, DP_OP_168J30_122_4811_n2829,
DP_OP_168J30_122_4811_n2828, DP_OP_168J30_122_4811_n2827,
DP_OP_168J30_122_4811_n2826, DP_OP_168J30_122_4811_n2825,
DP_OP_168J30_122_4811_n2824, DP_OP_168J30_122_4811_n2823,
DP_OP_168J30_122_4811_n2822, DP_OP_168J30_122_4811_n2817,
DP_OP_168J30_122_4811_n2816, DP_OP_168J30_122_4811_n2815,
DP_OP_168J30_122_4811_n2814, DP_OP_168J30_122_4811_n2813,
DP_OP_168J30_122_4811_n2812, DP_OP_168J30_122_4811_n2811,
DP_OP_168J30_122_4811_n2810, DP_OP_168J30_122_4811_n2809,
DP_OP_168J30_122_4811_n2808, DP_OP_168J30_122_4811_n2807,
DP_OP_168J30_122_4811_n2806, DP_OP_168J30_122_4811_n2805,
DP_OP_168J30_122_4811_n2804, DP_OP_168J30_122_4811_n2803,
DP_OP_168J30_122_4811_n2802, DP_OP_168J30_122_4811_n2801,
DP_OP_168J30_122_4811_n2800, DP_OP_168J30_122_4811_n2799,
DP_OP_168J30_122_4811_n2798, DP_OP_168J30_122_4811_n2797,
DP_OP_168J30_122_4811_n2796, DP_OP_168J30_122_4811_n2795,
DP_OP_168J30_122_4811_n2794, DP_OP_168J30_122_4811_n2793,
DP_OP_168J30_122_4811_n2792, DP_OP_168J30_122_4811_n2784,
DP_OP_168J30_122_4811_n2783, DP_OP_168J30_122_4811_n2782,
DP_OP_168J30_122_4811_n2781, DP_OP_168J30_122_4811_n2780,
DP_OP_168J30_122_4811_n2779, DP_OP_168J30_122_4811_n2778,
DP_OP_168J30_122_4811_n2777, DP_OP_168J30_122_4811_n2776,
DP_OP_168J30_122_4811_n2775, DP_OP_168J30_122_4811_n2774,
DP_OP_168J30_122_4811_n2773, DP_OP_168J30_122_4811_n2772,
DP_OP_168J30_122_4811_n2771, DP_OP_168J30_122_4811_n2770,
DP_OP_168J30_122_4811_n2769, DP_OP_168J30_122_4811_n2768,
DP_OP_168J30_122_4811_n2767, DP_OP_168J30_122_4811_n2766,
DP_OP_168J30_122_4811_n2765, DP_OP_168J30_122_4811_n2764,
DP_OP_168J30_122_4811_n2763, DP_OP_168J30_122_4811_n2762,
DP_OP_168J30_122_4811_n2757, DP_OP_168J30_122_4811_n2756,
DP_OP_168J30_122_4811_n2755, DP_OP_168J30_122_4811_n2754,
DP_OP_168J30_122_4811_n2753, DP_OP_168J30_122_4811_n2752,
DP_OP_168J30_122_4811_n2749, DP_OP_168J30_122_4811_n2748,
DP_OP_168J30_122_4811_n2747, DP_OP_168J30_122_4811_n2746,
DP_OP_168J30_122_4811_n2743, DP_OP_168J30_122_4811_n2742,
DP_OP_168J30_122_4811_n2741, DP_OP_168J30_122_4811_n2740,
DP_OP_168J30_122_4811_n2738, DP_OP_168J30_122_4811_n2737,
DP_OP_168J30_122_4811_n2736, DP_OP_168J30_122_4811_n2735,
DP_OP_168J30_122_4811_n2734, DP_OP_168J30_122_4811_n2630,
DP_OP_168J30_122_4811_n2629, DP_OP_168J30_122_4811_n2628,
DP_OP_168J30_122_4811_n2627, DP_OP_168J30_122_4811_n2626,
DP_OP_168J30_122_4811_n2625, DP_OP_168J30_122_4811_n2621,
DP_OP_168J30_122_4811_n2620, DP_OP_168J30_122_4811_n2619,
DP_OP_168J30_122_4811_n2615, DP_OP_168J30_122_4811_n2614,
DP_OP_168J30_122_4811_n2613, DP_OP_168J30_122_4811_n2609,
DP_OP_168J30_122_4811_n2608, DP_OP_168J30_122_4811_n2607,
DP_OP_168J30_122_4811_n2588, DP_OP_168J30_122_4811_n2586,
DP_OP_168J30_122_4811_n2585, DP_OP_168J30_122_4811_n2583,
DP_OP_168J30_122_4811_n2582, DP_OP_168J30_122_4811_n2581,
DP_OP_168J30_122_4811_n2580, DP_OP_168J30_122_4811_n2578,
DP_OP_168J30_122_4811_n2577, DP_OP_168J30_122_4811_n2576,
DP_OP_168J30_122_4811_n2575, DP_OP_168J30_122_4811_n2573,
DP_OP_168J30_122_4811_n2572, DP_OP_168J30_122_4811_n2571,
DP_OP_168J30_122_4811_n2568, DP_OP_168J30_122_4811_n2566,
DP_OP_168J30_122_4811_n2565, DP_OP_168J30_122_4811_n2564,
DP_OP_168J30_122_4811_n2561, DP_OP_168J30_122_4811_n2559,
DP_OP_168J30_122_4811_n2558, DP_OP_168J30_122_4811_n2557,
DP_OP_168J30_122_4811_n2555, DP_OP_168J30_122_4811_n2554,
DP_OP_168J30_122_4811_n2553, DP_OP_168J30_122_4811_n2552,
DP_OP_168J30_122_4811_n2551, DP_OP_168J30_122_4811_n2550,
DP_OP_168J30_122_4811_n2549, DP_OP_168J30_122_4811_n2547,
DP_OP_168J30_122_4811_n2546, DP_OP_168J30_122_4811_n2545,
DP_OP_168J30_122_4811_n2544, DP_OP_168J30_122_4811_n2543,
DP_OP_168J30_122_4811_n2542, DP_OP_168J30_122_4811_n2541,
DP_OP_168J30_122_4811_n2539, DP_OP_168J30_122_4811_n2538,
DP_OP_168J30_122_4811_n2537, DP_OP_168J30_122_4811_n2536,
DP_OP_168J30_122_4811_n2535, DP_OP_168J30_122_4811_n2534,
DP_OP_168J30_122_4811_n2533, DP_OP_168J30_122_4811_n2531,
DP_OP_168J30_122_4811_n2530, DP_OP_168J30_122_4811_n2529,
DP_OP_168J30_122_4811_n2528, DP_OP_168J30_122_4811_n2527,
DP_OP_168J30_122_4811_n2526, DP_OP_168J30_122_4811_n2523,
DP_OP_168J30_122_4811_n2521, DP_OP_168J30_122_4811_n2520,
DP_OP_168J30_122_4811_n2519, DP_OP_168J30_122_4811_n2518,
DP_OP_168J30_122_4811_n2517, DP_OP_168J30_122_4811_n2516,
DP_OP_168J30_122_4811_n2513, DP_OP_168J30_122_4811_n2511,
DP_OP_168J30_122_4811_n2510, DP_OP_168J30_122_4811_n2509,
DP_OP_168J30_122_4811_n2508, DP_OP_168J30_122_4811_n2507,
DP_OP_168J30_122_4811_n2506, DP_OP_168J30_122_4811_n2504,
DP_OP_168J30_122_4811_n2503, DP_OP_168J30_122_4811_n2502,
DP_OP_168J30_122_4811_n2501, DP_OP_168J30_122_4811_n2500,
DP_OP_168J30_122_4811_n2499, DP_OP_168J30_122_4811_n2498,
DP_OP_168J30_122_4811_n2497, DP_OP_168J30_122_4811_n2496,
DP_OP_168J30_122_4811_n2495, DP_OP_168J30_122_4811_n2493,
DP_OP_168J30_122_4811_n2492, DP_OP_168J30_122_4811_n2491,
DP_OP_168J30_122_4811_n2490, DP_OP_168J30_122_4811_n2489,
DP_OP_168J30_122_4811_n2488, DP_OP_168J30_122_4811_n2487,
DP_OP_168J30_122_4811_n2486, DP_OP_168J30_122_4811_n2485,
DP_OP_168J30_122_4811_n2484, DP_OP_168J30_122_4811_n2482,
DP_OP_168J30_122_4811_n2481, DP_OP_168J30_122_4811_n2480,
DP_OP_168J30_122_4811_n2479, DP_OP_168J30_122_4811_n2478,
DP_OP_168J30_122_4811_n2477, DP_OP_168J30_122_4811_n2476,
DP_OP_168J30_122_4811_n2475, DP_OP_168J30_122_4811_n2474,
DP_OP_168J30_122_4811_n2473, DP_OP_168J30_122_4811_n2471,
DP_OP_168J30_122_4811_n2470, DP_OP_168J30_122_4811_n2469,
DP_OP_168J30_122_4811_n2468, DP_OP_168J30_122_4811_n2467,
DP_OP_168J30_122_4811_n2466, DP_OP_168J30_122_4811_n2465,
DP_OP_168J30_122_4811_n2464, DP_OP_168J30_122_4811_n2463,
DP_OP_168J30_122_4811_n2460, DP_OP_168J30_122_4811_n2458,
DP_OP_168J30_122_4811_n2457, DP_OP_168J30_122_4811_n2456,
DP_OP_168J30_122_4811_n2455, DP_OP_168J30_122_4811_n2454,
DP_OP_168J30_122_4811_n2453, DP_OP_168J30_122_4811_n2452,
DP_OP_168J30_122_4811_n2451, DP_OP_168J30_122_4811_n2450,
DP_OP_168J30_122_4811_n2447, DP_OP_168J30_122_4811_n2445,
DP_OP_168J30_122_4811_n2444, DP_OP_168J30_122_4811_n2443,
DP_OP_168J30_122_4811_n2442, DP_OP_168J30_122_4811_n2441,
DP_OP_168J30_122_4811_n2440, DP_OP_168J30_122_4811_n2439,
DP_OP_168J30_122_4811_n2438, DP_OP_168J30_122_4811_n2437,
DP_OP_168J30_122_4811_n2435, DP_OP_168J30_122_4811_n2434,
DP_OP_168J30_122_4811_n2433, DP_OP_168J30_122_4811_n2432,
DP_OP_168J30_122_4811_n2431, DP_OP_168J30_122_4811_n2430,
DP_OP_168J30_122_4811_n2429, DP_OP_168J30_122_4811_n2428,
DP_OP_168J30_122_4811_n2427, DP_OP_168J30_122_4811_n2426,
DP_OP_168J30_122_4811_n2425, DP_OP_168J30_122_4811_n2424,
DP_OP_168J30_122_4811_n2423, DP_OP_168J30_122_4811_n2422,
DP_OP_168J30_122_4811_n2421, DP_OP_168J30_122_4811_n2420,
DP_OP_168J30_122_4811_n2419, DP_OP_168J30_122_4811_n2418,
DP_OP_168J30_122_4811_n2417, DP_OP_168J30_122_4811_n2416,
DP_OP_168J30_122_4811_n2415, DP_OP_168J30_122_4811_n2414,
DP_OP_168J30_122_4811_n2413, DP_OP_168J30_122_4811_n2412,
DP_OP_168J30_122_4811_n2411, DP_OP_168J30_122_4811_n2410,
DP_OP_168J30_122_4811_n2409, DP_OP_168J30_122_4811_n2408,
DP_OP_168J30_122_4811_n2407, DP_OP_168J30_122_4811_n2406,
DP_OP_168J30_122_4811_n2405, DP_OP_168J30_122_4811_n2404,
DP_OP_168J30_122_4811_n2403, DP_OP_168J30_122_4811_n2402,
DP_OP_168J30_122_4811_n2401, DP_OP_168J30_122_4811_n2400,
DP_OP_168J30_122_4811_n2399, DP_OP_168J30_122_4811_n2398,
DP_OP_168J30_122_4811_n2397, DP_OP_168J30_122_4811_n2396,
DP_OP_168J30_122_4811_n2395, DP_OP_168J30_122_4811_n2394,
DP_OP_168J30_122_4811_n2393, DP_OP_168J30_122_4811_n2392,
DP_OP_168J30_122_4811_n2391, DP_OP_168J30_122_4811_n2390,
DP_OP_168J30_122_4811_n2389, DP_OP_168J30_122_4811_n2388,
DP_OP_168J30_122_4811_n2387, DP_OP_168J30_122_4811_n2386,
DP_OP_168J30_122_4811_n2385, DP_OP_168J30_122_4811_n2384,
DP_OP_168J30_122_4811_n2383, DP_OP_168J30_122_4811_n2382,
DP_OP_168J30_122_4811_n2381, DP_OP_168J30_122_4811_n2380,
DP_OP_168J30_122_4811_n2379, DP_OP_168J30_122_4811_n2378,
DP_OP_168J30_122_4811_n2377, DP_OP_168J30_122_4811_n2376,
DP_OP_168J30_122_4811_n2375, DP_OP_168J30_122_4811_n2374,
DP_OP_168J30_122_4811_n2373, DP_OP_168J30_122_4811_n2372,
DP_OP_168J30_122_4811_n2371, DP_OP_168J30_122_4811_n2370,
DP_OP_168J30_122_4811_n2369, DP_OP_168J30_122_4811_n2368,
DP_OP_168J30_122_4811_n2367, DP_OP_168J30_122_4811_n2366,
DP_OP_168J30_122_4811_n2365, DP_OP_168J30_122_4811_n2364,
DP_OP_168J30_122_4811_n2363, DP_OP_168J30_122_4811_n2362,
DP_OP_168J30_122_4811_n2361, DP_OP_168J30_122_4811_n2360,
DP_OP_168J30_122_4811_n2359, DP_OP_168J30_122_4811_n2358,
DP_OP_168J30_122_4811_n2357, DP_OP_168J30_122_4811_n2356,
DP_OP_168J30_122_4811_n2355, DP_OP_168J30_122_4811_n2354,
DP_OP_168J30_122_4811_n2353, DP_OP_168J30_122_4811_n2352,
DP_OP_168J30_122_4811_n2350, DP_OP_168J30_122_4811_n2349,
DP_OP_168J30_122_4811_n2348, DP_OP_168J30_122_4811_n2347,
DP_OP_168J30_122_4811_n2346, DP_OP_168J30_122_4811_n2345,
DP_OP_168J30_122_4811_n2344, DP_OP_168J30_122_4811_n2343,
DP_OP_168J30_122_4811_n2342, DP_OP_168J30_122_4811_n2341,
DP_OP_168J30_122_4811_n2340, DP_OP_168J30_122_4811_n2337,
DP_OP_168J30_122_4811_n2336, DP_OP_168J30_122_4811_n2335,
DP_OP_168J30_122_4811_n2334, DP_OP_168J30_122_4811_n2333,
DP_OP_168J30_122_4811_n2332, DP_OP_168J30_122_4811_n2331,
DP_OP_168J30_122_4811_n2330, DP_OP_168J30_122_4811_n2329,
DP_OP_168J30_122_4811_n2328, DP_OP_168J30_122_4811_n2327,
DP_OP_168J30_122_4811_n2326, DP_OP_168J30_122_4811_n2325,
DP_OP_168J30_122_4811_n2324, DP_OP_168J30_122_4811_n2323,
DP_OP_168J30_122_4811_n2322, DP_OP_168J30_122_4811_n2321,
DP_OP_168J30_122_4811_n2320, DP_OP_168J30_122_4811_n2319,
DP_OP_168J30_122_4811_n2318, DP_OP_168J30_122_4811_n2317,
DP_OP_168J30_122_4811_n2316, DP_OP_168J30_122_4811_n2315,
DP_OP_168J30_122_4811_n2313, DP_OP_168J30_122_4811_n2312,
DP_OP_168J30_122_4811_n2311, DP_OP_168J30_122_4811_n2310,
DP_OP_168J30_122_4811_n2309, DP_OP_168J30_122_4811_n2308,
DP_OP_168J30_122_4811_n2307, DP_OP_168J30_122_4811_n2306,
DP_OP_168J30_122_4811_n2305, DP_OP_168J30_122_4811_n2304,
DP_OP_168J30_122_4811_n2302, DP_OP_168J30_122_4811_n2301,
DP_OP_168J30_122_4811_n2300, DP_OP_168J30_122_4811_n2299,
DP_OP_168J30_122_4811_n2298, DP_OP_168J30_122_4811_n2297,
DP_OP_168J30_122_4811_n2296, DP_OP_168J30_122_4811_n2295,
DP_OP_168J30_122_4811_n2294, DP_OP_168J30_122_4811_n2293,
DP_OP_168J30_122_4811_n2292, DP_OP_168J30_122_4811_n2291,
DP_OP_168J30_122_4811_n2290, DP_OP_168J30_122_4811_n2289,
DP_OP_168J30_122_4811_n2288, DP_OP_168J30_122_4811_n2287,
DP_OP_168J30_122_4811_n2286, DP_OP_168J30_122_4811_n2285,
DP_OP_168J30_122_4811_n2283, DP_OP_168J30_122_4811_n2282,
DP_OP_168J30_122_4811_n2281, DP_OP_168J30_122_4811_n2280,
DP_OP_168J30_122_4811_n2279, DP_OP_168J30_122_4811_n2278,
DP_OP_168J30_122_4811_n2277, DP_OP_168J30_122_4811_n2276,
DP_OP_168J30_122_4811_n2273, DP_OP_168J30_122_4811_n2272,
DP_OP_168J30_122_4811_n2271, DP_OP_168J30_122_4811_n2270,
DP_OP_168J30_122_4811_n2269, DP_OP_168J30_122_4811_n2268,
DP_OP_168J30_122_4811_n2267, DP_OP_168J30_122_4811_n2266,
DP_OP_168J30_122_4811_n2265, DP_OP_168J30_122_4811_n2264,
DP_OP_168J30_122_4811_n2263, DP_OP_168J30_122_4811_n2262,
DP_OP_168J30_122_4811_n2261, DP_OP_168J30_122_4811_n2260,
DP_OP_168J30_122_4811_n2259, DP_OP_168J30_122_4811_n2258,
DP_OP_168J30_122_4811_n2257, DP_OP_168J30_122_4811_n2255,
DP_OP_168J30_122_4811_n2254, DP_OP_168J30_122_4811_n2253,
DP_OP_168J30_122_4811_n2252, DP_OP_168J30_122_4811_n2251,
DP_OP_168J30_122_4811_n2250, DP_OP_168J30_122_4811_n2249,
DP_OP_168J30_122_4811_n2247, DP_OP_168J30_122_4811_n2246,
DP_OP_168J30_122_4811_n2245, DP_OP_168J30_122_4811_n2244,
DP_OP_168J30_122_4811_n2243, DP_OP_168J30_122_4811_n2242,
DP_OP_168J30_122_4811_n2241, DP_OP_168J30_122_4811_n2240,
DP_OP_168J30_122_4811_n2239, DP_OP_168J30_122_4811_n2238,
DP_OP_168J30_122_4811_n2237, DP_OP_168J30_122_4811_n2236,
DP_OP_168J30_122_4811_n2234, DP_OP_168J30_122_4811_n2232,
DP_OP_168J30_122_4811_n2231, DP_OP_168J30_122_4811_n2230,
DP_OP_168J30_122_4811_n2227, DP_OP_168J30_122_4811_n2226,
DP_OP_168J30_122_4811_n2225, DP_OP_168J30_122_4811_n2224,
DP_OP_168J30_122_4811_n2223, DP_OP_168J30_122_4811_n2222,
DP_OP_168J30_122_4811_n2221, DP_OP_168J30_122_4811_n2220,
DP_OP_168J30_122_4811_n2219, DP_OP_168J30_122_4811_n2218,
DP_OP_168J30_122_4811_n2217, DP_OP_168J30_122_4811_n2216,
DP_OP_168J30_122_4811_n2215, DP_OP_168J30_122_4811_n2214,
DP_OP_168J30_122_4811_n2211, DP_OP_168J30_122_4811_n2210,
DP_OP_168J30_122_4811_n2209, DP_OP_168J30_122_4811_n2208,
DP_OP_168J30_122_4811_n2207, DP_OP_168J30_122_4811_n2206,
DP_OP_168J30_122_4811_n2003, DP_OP_168J30_122_4811_n1993,
DP_OP_168J30_122_4811_n1992, DP_OP_168J30_122_4811_n1991,
DP_OP_168J30_122_4811_n1987, DP_OP_168J30_122_4811_n1986,
DP_OP_168J30_122_4811_n1985, DP_OP_168J30_122_4811_n1984,
DP_OP_168J30_122_4811_n1983, DP_OP_168J30_122_4811_n1982,
DP_OP_168J30_122_4811_n1981, DP_OP_168J30_122_4811_n1980,
DP_OP_168J30_122_4811_n1979, DP_OP_168J30_122_4811_n1978,
DP_OP_168J30_122_4811_n1977, DP_OP_168J30_122_4811_n1976,
DP_OP_168J30_122_4811_n1975, DP_OP_168J30_122_4811_n1974,
DP_OP_168J30_122_4811_n1973, DP_OP_168J30_122_4811_n1972,
DP_OP_168J30_122_4811_n1971, DP_OP_168J30_122_4811_n1970,
DP_OP_168J30_122_4811_n1969, DP_OP_168J30_122_4811_n1968,
DP_OP_168J30_122_4811_n1967, DP_OP_168J30_122_4811_n1965,
DP_OP_168J30_122_4811_n1964, DP_OP_168J30_122_4811_n1962,
DP_OP_168J30_122_4811_n1960, DP_OP_168J30_122_4811_n1959,
DP_OP_168J30_122_4811_n1958, DP_OP_168J30_122_4811_n1956,
DP_OP_168J30_122_4811_n1955, DP_OP_168J30_122_4811_n1953,
DP_OP_168J30_122_4811_n1952, DP_OP_168J30_122_4811_n1951,
DP_OP_168J30_122_4811_n1950, DP_OP_168J30_122_4811_n1949,
DP_OP_168J30_122_4811_n1948, DP_OP_168J30_122_4811_n1947,
DP_OP_168J30_122_4811_n1946, DP_OP_168J30_122_4811_n1867,
DP_OP_168J30_122_4811_n1866, DP_OP_168J30_122_4811_n1865,
DP_OP_168J30_122_4811_n1864, DP_OP_168J30_122_4811_n1863,
DP_OP_168J30_122_4811_n1862, DP_OP_168J30_122_4811_n1861,
DP_OP_168J30_122_4811_n1860, DP_OP_168J30_122_4811_n1859,
DP_OP_168J30_122_4811_n1232, DP_OP_168J30_122_4811_n1231,
DP_OP_168J30_122_4811_n1230, DP_OP_168J30_122_4811_n1229,
DP_OP_168J30_122_4811_n1228, DP_OP_168J30_122_4811_n1227,
DP_OP_168J30_122_4811_n1226, DP_OP_168J30_122_4811_n1225,
DP_OP_168J30_122_4811_n1224, DP_OP_168J30_122_4811_n1223,
DP_OP_168J30_122_4811_n1222, DP_OP_168J30_122_4811_n1221,
DP_OP_168J30_122_4811_n1220, DP_OP_168J30_122_4811_n1219,
DP_OP_168J30_122_4811_n1218, DP_OP_168J30_122_4811_n1217,
DP_OP_168J30_122_4811_n1216, DP_OP_168J30_122_4811_n1215,
DP_OP_168J30_122_4811_n1214, DP_OP_168J30_122_4811_n1213,
DP_OP_168J30_122_4811_n1212, DP_OP_168J30_122_4811_n1211,
DP_OP_168J30_122_4811_n1209, DP_OP_168J30_122_4811_n1208,
DP_OP_168J30_122_4811_n1198, DP_OP_168J30_122_4811_n1197,
DP_OP_168J30_122_4811_n1196, DP_OP_168J30_122_4811_n1195,
DP_OP_168J30_122_4811_n1194, DP_OP_168J30_122_4811_n1193,
DP_OP_168J30_122_4811_n1192, DP_OP_168J30_122_4811_n1191,
DP_OP_168J30_122_4811_n1190, DP_OP_168J30_122_4811_n1189,
DP_OP_168J30_122_4811_n1188, DP_OP_168J30_122_4811_n1187,
DP_OP_168J30_122_4811_n1186, DP_OP_168J30_122_4811_n1185,
DP_OP_168J30_122_4811_n1184, DP_OP_168J30_122_4811_n1183,
DP_OP_168J30_122_4811_n1182, DP_OP_168J30_122_4811_n1181,
DP_OP_168J30_122_4811_n1180, DP_OP_168J30_122_4811_n1178,
DP_OP_168J30_122_4811_n1177, DP_OP_168J30_122_4811_n1176,
DP_OP_168J30_122_4811_n1175, DP_OP_168J30_122_4811_n1164,
DP_OP_168J30_122_4811_n1163, DP_OP_168J30_122_4811_n1162,
DP_OP_168J30_122_4811_n1161, DP_OP_168J30_122_4811_n1160,
DP_OP_168J30_122_4811_n1159, DP_OP_168J30_122_4811_n1158,
DP_OP_168J30_122_4811_n1157, DP_OP_168J30_122_4811_n1156,
DP_OP_168J30_122_4811_n1155, DP_OP_168J30_122_4811_n1154,
DP_OP_168J30_122_4811_n1153, DP_OP_168J30_122_4811_n1152,
DP_OP_168J30_122_4811_n1151, DP_OP_168J30_122_4811_n1150,
DP_OP_168J30_122_4811_n1148, DP_OP_168J30_122_4811_n1147,
DP_OP_168J30_122_4811_n1146, DP_OP_168J30_122_4811_n1145,
DP_OP_168J30_122_4811_n1144, DP_OP_168J30_122_4811_n1142,
DP_OP_168J30_122_4811_n1130, DP_OP_168J30_122_4811_n1129,
DP_OP_168J30_122_4811_n1128, DP_OP_168J30_122_4811_n1127,
DP_OP_168J30_122_4811_n1126, DP_OP_168J30_122_4811_n1125,
DP_OP_168J30_122_4811_n1124, DP_OP_168J30_122_4811_n1123,
DP_OP_168J30_122_4811_n1122, DP_OP_168J30_122_4811_n1121,
DP_OP_168J30_122_4811_n1120, DP_OP_168J30_122_4811_n1119,
DP_OP_168J30_122_4811_n1118, DP_OP_168J30_122_4811_n1117,
DP_OP_168J30_122_4811_n1116, DP_OP_168J30_122_4811_n1115,
DP_OP_168J30_122_4811_n1114, DP_OP_168J30_122_4811_n1113,
DP_OP_168J30_122_4811_n1112, DP_OP_168J30_122_4811_n1111,
DP_OP_168J30_122_4811_n1108, DP_OP_168J30_122_4811_n1102,
DP_OP_168J30_122_4811_n1101, DP_OP_168J30_122_4811_n1100,
DP_OP_168J30_122_4811_n1099, DP_OP_168J30_122_4811_n1098,
DP_OP_168J30_122_4811_n1097, DP_OP_168J30_122_4811_n1096,
DP_OP_168J30_122_4811_n1095, DP_OP_168J30_122_4811_n1094,
DP_OP_168J30_122_4811_n1093, DP_OP_168J30_122_4811_n1092,
DP_OP_168J30_122_4811_n1091, DP_OP_168J30_122_4811_n1090,
DP_OP_168J30_122_4811_n1089, DP_OP_168J30_122_4811_n1088,
DP_OP_168J30_122_4811_n1086, DP_OP_168J30_122_4811_n1085,
DP_OP_168J30_122_4811_n1084, DP_OP_168J30_122_4811_n1083,
DP_OP_168J30_122_4811_n1082, DP_OP_168J30_122_4811_n1081,
DP_OP_168J30_122_4811_n1080, DP_OP_168J30_122_4811_n1079,
DP_OP_168J30_122_4811_n1078, DP_OP_168J30_122_4811_n1077,
DP_OP_168J30_122_4811_n1074, DP_OP_168J30_122_4811_n1073,
DP_OP_168J30_122_4811_n1072, DP_OP_168J30_122_4811_n1071,
DP_OP_168J30_122_4811_n1070, DP_OP_168J30_122_4811_n1069,
DP_OP_168J30_122_4811_n1068, DP_OP_168J30_122_4811_n1064,
DP_OP_168J30_122_4811_n1063, DP_OP_168J30_122_4811_n1062,
DP_OP_168J30_122_4811_n1061, DP_OP_168J30_122_4811_n1060,
DP_OP_168J30_122_4811_n1059, DP_OP_168J30_122_4811_n1058,
DP_OP_168J30_122_4811_n1057, DP_OP_168J30_122_4811_n1056,
DP_OP_168J30_122_4811_n1055, DP_OP_168J30_122_4811_n1054,
DP_OP_168J30_122_4811_n1053, DP_OP_168J30_122_4811_n1052,
DP_OP_168J30_122_4811_n1051, DP_OP_168J30_122_4811_n1050,
DP_OP_168J30_122_4811_n1049, DP_OP_168J30_122_4811_n1048,
DP_OP_168J30_122_4811_n1047, DP_OP_168J30_122_4811_n1046,
DP_OP_168J30_122_4811_n1045, DP_OP_168J30_122_4811_n1044,
DP_OP_168J30_122_4811_n1043, DP_OP_168J30_122_4811_n1042,
DP_OP_168J30_122_4811_n1041, DP_OP_168J30_122_4811_n1040,
DP_OP_168J30_122_4811_n1036, DP_OP_168J30_122_4811_n1035,
DP_OP_168J30_122_4811_n1034, DP_OP_168J30_122_4811_n1030,
DP_OP_168J30_122_4811_n1029, DP_OP_168J30_122_4811_n1028,
DP_OP_168J30_122_4811_n1027, DP_OP_168J30_122_4811_n1026,
DP_OP_168J30_122_4811_n1024, DP_OP_168J30_122_4811_n1023,
DP_OP_168J30_122_4811_n1022, DP_OP_168J30_122_4811_n1021,
DP_OP_168J30_122_4811_n1020, DP_OP_168J30_122_4811_n1019,
DP_OP_168J30_122_4811_n1018, DP_OP_168J30_122_4811_n1017,
DP_OP_168J30_122_4811_n1016, DP_OP_168J30_122_4811_n1015,
DP_OP_168J30_122_4811_n1014, DP_OP_168J30_122_4811_n1013,
DP_OP_168J30_122_4811_n1012, DP_OP_168J30_122_4811_n1011,
DP_OP_168J30_122_4811_n1010, DP_OP_168J30_122_4811_n1009,
DP_OP_168J30_122_4811_n1008, DP_OP_168J30_122_4811_n1007,
DP_OP_168J30_122_4811_n1006, DP_OP_168J30_122_4811_n1002,
DP_OP_168J30_122_4811_n1001, DP_OP_168J30_122_4811_n1000,
DP_OP_168J30_122_4811_n996, DP_OP_168J30_122_4811_n995,
DP_OP_168J30_122_4811_n994, DP_OP_168J30_122_4811_n993,
DP_OP_168J30_122_4811_n992, DP_OP_168J30_122_4811_n991,
DP_OP_168J30_122_4811_n990, DP_OP_168J30_122_4811_n989,
DP_OP_168J30_122_4811_n988, DP_OP_168J30_122_4811_n987,
DP_OP_168J30_122_4811_n986, DP_OP_168J30_122_4811_n985,
DP_OP_168J30_122_4811_n984, DP_OP_168J30_122_4811_n983,
DP_OP_168J30_122_4811_n982, DP_OP_168J30_122_4811_n981,
DP_OP_168J30_122_4811_n980, DP_OP_168J30_122_4811_n979,
DP_OP_168J30_122_4811_n978, DP_OP_168J30_122_4811_n977,
DP_OP_168J30_122_4811_n976, DP_OP_168J30_122_4811_n975,
DP_OP_168J30_122_4811_n974, DP_OP_168J30_122_4811_n973,
DP_OP_168J30_122_4811_n972, DP_OP_168J30_122_4811_n971,
DP_OP_168J30_122_4811_n969, DP_OP_168J30_122_4811_n968,
DP_OP_168J30_122_4811_n967, DP_OP_168J30_122_4811_n966,
DP_OP_168J30_122_4811_n964, DP_OP_168J30_122_4811_n850,
DP_OP_168J30_122_4811_n849, DP_OP_168J30_122_4811_n848,
DP_OP_168J30_122_4811_n847, DP_OP_168J30_122_4811_n846,
DP_OP_168J30_122_4811_n845, DP_OP_168J30_122_4811_n844,
DP_OP_168J30_122_4811_n843, DP_OP_168J30_122_4811_n842,
DP_OP_168J30_122_4811_n841, DP_OP_168J30_122_4811_n840,
DP_OP_168J30_122_4811_n839, DP_OP_168J30_122_4811_n838,
DP_OP_168J30_122_4811_n837, DP_OP_168J30_122_4811_n836,
DP_OP_168J30_122_4811_n835, DP_OP_168J30_122_4811_n834,
DP_OP_168J30_122_4811_n833, DP_OP_168J30_122_4811_n832,
DP_OP_168J30_122_4811_n828, DP_OP_168J30_122_4811_n827,
DP_OP_168J30_122_4811_n826, DP_OP_168J30_122_4811_n824,
DP_OP_168J30_122_4811_n818, DP_OP_168J30_122_4811_n817,
DP_OP_168J30_122_4811_n816, DP_OP_168J30_122_4811_n815,
DP_OP_168J30_122_4811_n812, DP_OP_168J30_122_4811_n811,
DP_OP_168J30_122_4811_n810, DP_OP_168J30_122_4811_n809,
DP_OP_168J30_122_4811_n808, DP_OP_168J30_122_4811_n807,
DP_OP_168J30_122_4811_n806, DP_OP_168J30_122_4811_n805,
DP_OP_168J30_122_4811_n804, DP_OP_168J30_122_4811_n803,
DP_OP_168J30_122_4811_n802, DP_OP_168J30_122_4811_n801,
DP_OP_168J30_122_4811_n800, DP_OP_168J30_122_4811_n799,
DP_OP_168J30_122_4811_n798, DP_OP_168J30_122_4811_n797,
DP_OP_168J30_122_4811_n796, DP_OP_168J30_122_4811_n795,
DP_OP_168J30_122_4811_n794, DP_OP_168J30_122_4811_n793,
DP_OP_168J30_122_4811_n792, DP_OP_168J30_122_4811_n791,
DP_OP_168J30_122_4811_n790, DP_OP_168J30_122_4811_n789,
DP_OP_168J30_122_4811_n788, DP_OP_168J30_122_4811_n787,
DP_OP_168J30_122_4811_n786, DP_OP_168J30_122_4811_n785,
DP_OP_168J30_122_4811_n784, DP_OP_168J30_122_4811_n783,
DP_OP_168J30_122_4811_n782, DP_OP_168J30_122_4811_n781,
DP_OP_168J30_122_4811_n780, DP_OP_168J30_122_4811_n779,
DP_OP_168J30_122_4811_n778, DP_OP_168J30_122_4811_n777,
DP_OP_168J30_122_4811_n776, DP_OP_168J30_122_4811_n775,
DP_OP_168J30_122_4811_n774, DP_OP_168J30_122_4811_n773,
DP_OP_168J30_122_4811_n772, DP_OP_168J30_122_4811_n771,
DP_OP_168J30_122_4811_n770, DP_OP_168J30_122_4811_n769,
DP_OP_168J30_122_4811_n762, DP_OP_168J30_122_4811_n760,
DP_OP_168J30_122_4811_n759, DP_OP_168J30_122_4811_n757,
DP_OP_168J30_122_4811_n756, DP_OP_168J30_122_4811_n755,
DP_OP_168J30_122_4811_n754, DP_OP_168J30_122_4811_n752,
DP_OP_168J30_122_4811_n751, DP_OP_168J30_122_4811_n750,
DP_OP_168J30_122_4811_n749, DP_OP_168J30_122_4811_n747,
DP_OP_168J30_122_4811_n746, DP_OP_168J30_122_4811_n745,
DP_OP_168J30_122_4811_n744, DP_OP_168J30_122_4811_n742,
DP_OP_168J30_122_4811_n741, DP_OP_168J30_122_4811_n740,
DP_OP_168J30_122_4811_n739, DP_OP_168J30_122_4811_n738,
DP_OP_168J30_122_4811_n737, DP_OP_168J30_122_4811_n735,
DP_OP_168J30_122_4811_n734, DP_OP_168J30_122_4811_n733,
DP_OP_168J30_122_4811_n732, DP_OP_168J30_122_4811_n731,
DP_OP_168J30_122_4811_n730, DP_OP_168J30_122_4811_n729,
DP_OP_168J30_122_4811_n728, DP_OP_168J30_122_4811_n727,
DP_OP_168J30_122_4811_n726, DP_OP_168J30_122_4811_n725,
DP_OP_168J30_122_4811_n724, DP_OP_168J30_122_4811_n723,
DP_OP_168J30_122_4811_n721, DP_OP_168J30_122_4811_n720,
DP_OP_168J30_122_4811_n719, DP_OP_168J30_122_4811_n718,
DP_OP_168J30_122_4811_n717, DP_OP_168J30_122_4811_n716,
DP_OP_168J30_122_4811_n715, DP_OP_168J30_122_4811_n714,
DP_OP_168J30_122_4811_n713, DP_OP_168J30_122_4811_n712,
DP_OP_168J30_122_4811_n711, DP_OP_168J30_122_4811_n710,
DP_OP_168J30_122_4811_n709, DP_OP_168J30_122_4811_n708,
DP_OP_168J30_122_4811_n707, DP_OP_168J30_122_4811_n705,
DP_OP_168J30_122_4811_n704, DP_OP_168J30_122_4811_n703,
DP_OP_168J30_122_4811_n702, DP_OP_168J30_122_4811_n701,
DP_OP_168J30_122_4811_n700, DP_OP_168J30_122_4811_n697,
DP_OP_168J30_122_4811_n695, DP_OP_168J30_122_4811_n694,
DP_OP_168J30_122_4811_n693, DP_OP_168J30_122_4811_n692,
DP_OP_168J30_122_4811_n691, DP_OP_168J30_122_4811_n690,
DP_OP_168J30_122_4811_n687, DP_OP_168J30_122_4811_n686,
DP_OP_168J30_122_4811_n685, DP_OP_168J30_122_4811_n684,
DP_OP_168J30_122_4811_n683, DP_OP_168J30_122_4811_n682,
DP_OP_168J30_122_4811_n681, DP_OP_168J30_122_4811_n680,
DP_OP_168J30_122_4811_n677, DP_OP_168J30_122_4811_n676,
DP_OP_168J30_122_4811_n675, DP_OP_168J30_122_4811_n674,
DP_OP_168J30_122_4811_n673, DP_OP_168J30_122_4811_n672,
DP_OP_168J30_122_4811_n671, DP_OP_168J30_122_4811_n670,
DP_OP_168J30_122_4811_n669, DP_OP_168J30_122_4811_n668,
DP_OP_168J30_122_4811_n667, DP_OP_168J30_122_4811_n666,
DP_OP_168J30_122_4811_n665, DP_OP_168J30_122_4811_n664,
DP_OP_168J30_122_4811_n663, DP_OP_168J30_122_4811_n662,
DP_OP_168J30_122_4811_n661, DP_OP_168J30_122_4811_n660,
DP_OP_168J30_122_4811_n659, DP_OP_168J30_122_4811_n658,
DP_OP_168J30_122_4811_n657, DP_OP_168J30_122_4811_n656,
DP_OP_168J30_122_4811_n655, DP_OP_168J30_122_4811_n654,
DP_OP_168J30_122_4811_n653, DP_OP_168J30_122_4811_n652,
DP_OP_168J30_122_4811_n651, DP_OP_168J30_122_4811_n650,
DP_OP_168J30_122_4811_n649, DP_OP_168J30_122_4811_n648,
DP_OP_168J30_122_4811_n647, DP_OP_168J30_122_4811_n645,
DP_OP_168J30_122_4811_n644, DP_OP_168J30_122_4811_n643,
DP_OP_168J30_122_4811_n642, DP_OP_168J30_122_4811_n641,
DP_OP_168J30_122_4811_n640, DP_OP_168J30_122_4811_n639,
DP_OP_168J30_122_4811_n638, DP_OP_168J30_122_4811_n637,
DP_OP_168J30_122_4811_n634, DP_OP_168J30_122_4811_n633,
DP_OP_168J30_122_4811_n632, DP_OP_168J30_122_4811_n631,
DP_OP_168J30_122_4811_n630, DP_OP_168J30_122_4811_n629,
DP_OP_168J30_122_4811_n628, DP_OP_168J30_122_4811_n627,
DP_OP_168J30_122_4811_n626, DP_OP_168J30_122_4811_n625,
DP_OP_168J30_122_4811_n624, DP_OP_168J30_122_4811_n621,
DP_OP_168J30_122_4811_n620, DP_OP_168J30_122_4811_n619,
DP_OP_168J30_122_4811_n618, DP_OP_168J30_122_4811_n617,
DP_OP_168J30_122_4811_n616, DP_OP_168J30_122_4811_n615,
DP_OP_168J30_122_4811_n614, DP_OP_168J30_122_4811_n613,
DP_OP_168J30_122_4811_n612, DP_OP_168J30_122_4811_n611,
DP_OP_168J30_122_4811_n608, DP_OP_168J30_122_4811_n607,
DP_OP_168J30_122_4811_n606, DP_OP_168J30_122_4811_n605,
DP_OP_168J30_122_4811_n604, DP_OP_168J30_122_4811_n603,
DP_OP_168J30_122_4811_n602, DP_OP_168J30_122_4811_n601,
DP_OP_168J30_122_4811_n600, DP_OP_168J30_122_4811_n599,
DP_OP_168J30_122_4811_n598, DP_OP_168J30_122_4811_n597,
DP_OP_168J30_122_4811_n596, DP_OP_168J30_122_4811_n595,
DP_OP_168J30_122_4811_n594, DP_OP_168J30_122_4811_n593,
DP_OP_168J30_122_4811_n592, DP_OP_168J30_122_4811_n591,
DP_OP_168J30_122_4811_n590, DP_OP_168J30_122_4811_n589,
DP_OP_168J30_122_4811_n588, DP_OP_168J30_122_4811_n587,
DP_OP_168J30_122_4811_n586, DP_OP_168J30_122_4811_n585,
DP_OP_168J30_122_4811_n584, DP_OP_168J30_122_4811_n583,
DP_OP_168J30_122_4811_n582, DP_OP_168J30_122_4811_n581,
DP_OP_168J30_122_4811_n580, DP_OP_168J30_122_4811_n579,
DP_OP_168J30_122_4811_n578, DP_OP_168J30_122_4811_n577,
DP_OP_168J30_122_4811_n576, DP_OP_168J30_122_4811_n575,
DP_OP_168J30_122_4811_n574, DP_OP_168J30_122_4811_n573,
DP_OP_168J30_122_4811_n572, DP_OP_168J30_122_4811_n571,
DP_OP_168J30_122_4811_n570, DP_OP_168J30_122_4811_n569,
DP_OP_168J30_122_4811_n567, DP_OP_168J30_122_4811_n566,
DP_OP_168J30_122_4811_n565, DP_OP_168J30_122_4811_n564,
DP_OP_168J30_122_4811_n563, DP_OP_168J30_122_4811_n562,
DP_OP_168J30_122_4811_n561, DP_OP_168J30_122_4811_n560,
DP_OP_168J30_122_4811_n559, DP_OP_168J30_122_4811_n558,
DP_OP_168J30_122_4811_n557, DP_OP_168J30_122_4811_n556,
DP_OP_168J30_122_4811_n553, DP_OP_168J30_122_4811_n552,
DP_OP_168J30_122_4811_n551, DP_OP_168J30_122_4811_n550,
DP_OP_168J30_122_4811_n549, DP_OP_168J30_122_4811_n548,
DP_OP_168J30_122_4811_n547, DP_OP_168J30_122_4811_n546,
DP_OP_168J30_122_4811_n545, DP_OP_168J30_122_4811_n544,
DP_OP_168J30_122_4811_n543, DP_OP_168J30_122_4811_n542,
DP_OP_168J30_122_4811_n541, DP_OP_168J30_122_4811_n540,
DP_OP_168J30_122_4811_n537, DP_OP_168J30_122_4811_n536,
DP_OP_168J30_122_4811_n535, DP_OP_168J30_122_4811_n534,
DP_OP_168J30_122_4811_n533, DP_OP_168J30_122_4811_n532,
DP_OP_168J30_122_4811_n531, DP_OP_168J30_122_4811_n530,
DP_OP_168J30_122_4811_n529, DP_OP_168J30_122_4811_n528,
DP_OP_168J30_122_4811_n527, DP_OP_168J30_122_4811_n526,
DP_OP_168J30_122_4811_n525, DP_OP_168J30_122_4811_n524,
DP_OP_168J30_122_4811_n522, DP_OP_168J30_122_4811_n521,
DP_OP_168J30_122_4811_n520, DP_OP_168J30_122_4811_n519,
DP_OP_168J30_122_4811_n518, DP_OP_168J30_122_4811_n517,
DP_OP_168J30_122_4811_n516, DP_OP_168J30_122_4811_n515,
DP_OP_168J30_122_4811_n514, DP_OP_168J30_122_4811_n513,
DP_OP_168J30_122_4811_n512, DP_OP_168J30_122_4811_n511,
DP_OP_168J30_122_4811_n510, DP_OP_168J30_122_4811_n509,
DP_OP_168J30_122_4811_n508, DP_OP_168J30_122_4811_n507,
DP_OP_168J30_122_4811_n506, DP_OP_168J30_122_4811_n505,
DP_OP_168J30_122_4811_n504, DP_OP_168J30_122_4811_n503,
DP_OP_168J30_122_4811_n502, DP_OP_168J30_122_4811_n501,
DP_OP_168J30_122_4811_n500, DP_OP_168J30_122_4811_n499,
DP_OP_168J30_122_4811_n498, DP_OP_168J30_122_4811_n497,
DP_OP_168J30_122_4811_n496, DP_OP_168J30_122_4811_n495,
DP_OP_168J30_122_4811_n494, DP_OP_168J30_122_4811_n493,
DP_OP_168J30_122_4811_n492, DP_OP_168J30_122_4811_n491,
DP_OP_168J30_122_4811_n490, DP_OP_168J30_122_4811_n489,
DP_OP_168J30_122_4811_n488, DP_OP_168J30_122_4811_n487,
DP_OP_168J30_122_4811_n486, DP_OP_168J30_122_4811_n485,
DP_OP_168J30_122_4811_n484, DP_OP_168J30_122_4811_n483,
DP_OP_168J30_122_4811_n482, DP_OP_168J30_122_4811_n481,
DP_OP_168J30_122_4811_n480, DP_OP_168J30_122_4811_n479,
DP_OP_168J30_122_4811_n478, DP_OP_168J30_122_4811_n477,
DP_OP_168J30_122_4811_n476, DP_OP_168J30_122_4811_n475,
DP_OP_168J30_122_4811_n474, DP_OP_168J30_122_4811_n473,
DP_OP_168J30_122_4811_n472, DP_OP_168J30_122_4811_n471,
DP_OP_168J30_122_4811_n470, DP_OP_168J30_122_4811_n469,
DP_OP_168J30_122_4811_n468, DP_OP_168J30_122_4811_n467,
DP_OP_168J30_122_4811_n466, DP_OP_168J30_122_4811_n465,
DP_OP_168J30_122_4811_n464, DP_OP_168J30_122_4811_n463,
DP_OP_168J30_122_4811_n462, DP_OP_168J30_122_4811_n461,
DP_OP_168J30_122_4811_n460, DP_OP_168J30_122_4811_n459,
DP_OP_168J30_122_4811_n458, DP_OP_168J30_122_4811_n457,
DP_OP_168J30_122_4811_n456, DP_OP_168J30_122_4811_n455,
DP_OP_168J30_122_4811_n454, DP_OP_168J30_122_4811_n453,
DP_OP_168J30_122_4811_n452, DP_OP_168J30_122_4811_n451,
DP_OP_168J30_122_4811_n450, DP_OP_168J30_122_4811_n449,
DP_OP_168J30_122_4811_n448, DP_OP_168J30_122_4811_n447,
DP_OP_168J30_122_4811_n446, DP_OP_168J30_122_4811_n445,
DP_OP_168J30_122_4811_n444, DP_OP_168J30_122_4811_n443,
DP_OP_168J30_122_4811_n442, DP_OP_168J30_122_4811_n441,
DP_OP_168J30_122_4811_n440, DP_OP_168J30_122_4811_n439,
DP_OP_168J30_122_4811_n438, DP_OP_168J30_122_4811_n437,
DP_OP_168J30_122_4811_n436, DP_OP_168J30_122_4811_n435,
DP_OP_168J30_122_4811_n434, DP_OP_168J30_122_4811_n433,
DP_OP_168J30_122_4811_n432, DP_OP_168J30_122_4811_n431,
DP_OP_168J30_122_4811_n430, DP_OP_168J30_122_4811_n429,
DP_OP_168J30_122_4811_n428, DP_OP_168J30_122_4811_n427,
DP_OP_168J30_122_4811_n426, DP_OP_168J30_122_4811_n425,
DP_OP_168J30_122_4811_n424, DP_OP_168J30_122_4811_n423,
DP_OP_168J30_122_4811_n422, DP_OP_168J30_122_4811_n421,
DP_OP_168J30_122_4811_n420, DP_OP_168J30_122_4811_n419,
DP_OP_168J30_122_4811_n418, DP_OP_168J30_122_4811_n417,
DP_OP_168J30_122_4811_n416, DP_OP_168J30_122_4811_n415,
DP_OP_168J30_122_4811_n414, DP_OP_168J30_122_4811_n413,
DP_OP_168J30_122_4811_n412, DP_OP_168J30_122_4811_n411,
DP_OP_168J30_122_4811_n410, DP_OP_168J30_122_4811_n409,
DP_OP_168J30_122_4811_n408, DP_OP_168J30_122_4811_n407,
DP_OP_168J30_122_4811_n406, DP_OP_168J30_122_4811_n405,
DP_OP_168J30_122_4811_n404, DP_OP_168J30_122_4811_n403,
DP_OP_168J30_122_4811_n402, DP_OP_168J30_122_4811_n400,
DP_OP_168J30_122_4811_n399, DP_OP_168J30_122_4811_n398,
DP_OP_168J30_122_4811_n397, DP_OP_168J30_122_4811_n396,
DP_OP_168J30_122_4811_n395, DP_OP_168J30_122_4811_n394,
DP_OP_168J30_122_4811_n393, DP_OP_168J30_122_4811_n392,
DP_OP_168J30_122_4811_n391, DP_OP_168J30_122_4811_n390,
DP_OP_168J30_122_4811_n389, DP_OP_168J30_122_4811_n388,
DP_OP_168J30_122_4811_n387, DP_OP_168J30_122_4811_n386,
DP_OP_168J30_122_4811_n385, DP_OP_168J30_122_4811_n384,
DP_OP_168J30_122_4811_n383, DP_OP_168J30_122_4811_n382,
DP_OP_168J30_122_4811_n381, DP_OP_168J30_122_4811_n380,
DP_OP_168J30_122_4811_n379, DP_OP_168J30_122_4811_n378,
DP_OP_168J30_122_4811_n377, DP_OP_168J30_122_4811_n376,
DP_OP_168J30_122_4811_n375, DP_OP_168J30_122_4811_n374,
DP_OP_168J30_122_4811_n373, DP_OP_168J30_122_4811_n372,
DP_OP_168J30_122_4811_n371, DP_OP_168J30_122_4811_n370,
DP_OP_168J30_122_4811_n369, DP_OP_168J30_122_4811_n368,
DP_OP_168J30_122_4811_n367, DP_OP_168J30_122_4811_n366,
DP_OP_168J30_122_4811_n365, DP_OP_168J30_122_4811_n364,
DP_OP_168J30_122_4811_n363, DP_OP_168J30_122_4811_n362,
DP_OP_168J30_122_4811_n361, DP_OP_168J30_122_4811_n360,
DP_OP_168J30_122_4811_n359, DP_OP_168J30_122_4811_n358,
DP_OP_168J30_122_4811_n357, DP_OP_168J30_122_4811_n356,
DP_OP_168J30_122_4811_n355, DP_OP_168J30_122_4811_n354,
DP_OP_168J30_122_4811_n353, DP_OP_168J30_122_4811_n352,
DP_OP_168J30_122_4811_n351, DP_OP_168J30_122_4811_n350,
DP_OP_168J30_122_4811_n349, DP_OP_168J30_122_4811_n348,
DP_OP_168J30_122_4811_n347, DP_OP_168J30_122_4811_n346,
DP_OP_168J30_122_4811_n345, DP_OP_168J30_122_4811_n344,
DP_OP_168J30_122_4811_n343, DP_OP_168J30_122_4811_n342,
DP_OP_168J30_122_4811_n341, DP_OP_168J30_122_4811_n340,
DP_OP_168J30_122_4811_n339, DP_OP_168J30_122_4811_n338,
DP_OP_168J30_122_4811_n337, DP_OP_168J30_122_4811_n336,
DP_OP_168J30_122_4811_n335, DP_OP_168J30_122_4811_n334,
DP_OP_168J30_122_4811_n333, DP_OP_168J30_122_4811_n332,
DP_OP_168J30_122_4811_n331, DP_OP_168J30_122_4811_n330,
DP_OP_168J30_122_4811_n329, DP_OP_168J30_122_4811_n328,
DP_OP_168J30_122_4811_n327, DP_OP_168J30_122_4811_n326,
DP_OP_168J30_122_4811_n325, DP_OP_168J30_122_4811_n324,
DP_OP_168J30_122_4811_n322, DP_OP_168J30_122_4811_n321,
DP_OP_168J30_122_4811_n320, DP_OP_168J30_122_4811_n319,
DP_OP_168J30_122_4811_n318, DP_OP_168J30_122_4811_n317,
DP_OP_168J30_122_4811_n316, DP_OP_168J30_122_4811_n315,
DP_OP_168J30_122_4811_n314, DP_OP_168J30_122_4811_n313,
DP_OP_168J30_122_4811_n312, DP_OP_168J30_122_4811_n311,
DP_OP_168J30_122_4811_n310, DP_OP_168J30_122_4811_n309,
DP_OP_168J30_122_4811_n308, DP_OP_168J30_122_4811_n307,
DP_OP_168J30_122_4811_n306, DP_OP_168J30_122_4811_n305,
DP_OP_168J30_122_4811_n304, DP_OP_168J30_122_4811_n303,
DP_OP_168J30_122_4811_n302, DP_OP_168J30_122_4811_n301,
DP_OP_168J30_122_4811_n300, DP_OP_168J30_122_4811_n299,
DP_OP_168J30_122_4811_n298, DP_OP_168J30_122_4811_n297,
DP_OP_168J30_122_4811_n296, DP_OP_168J30_122_4811_n295,
DP_OP_168J30_122_4811_n294, DP_OP_168J30_122_4811_n293,
DP_OP_168J30_122_4811_n292, DP_OP_168J30_122_4811_n291,
DP_OP_168J30_122_4811_n290, DP_OP_168J30_122_4811_n289,
DP_OP_168J30_122_4811_n288, DP_OP_168J30_122_4811_n287,
DP_OP_168J30_122_4811_n286, DP_OP_168J30_122_4811_n285,
DP_OP_168J30_122_4811_n284, DP_OP_168J30_122_4811_n283,
DP_OP_168J30_122_4811_n282, DP_OP_168J30_122_4811_n281,
DP_OP_168J30_122_4811_n280, DP_OP_168J30_122_4811_n279,
DP_OP_168J30_122_4811_n278, DP_OP_168J30_122_4811_n277,
DP_OP_168J30_122_4811_n276, DP_OP_168J30_122_4811_n275,
DP_OP_168J30_122_4811_n274, DP_OP_168J30_122_4811_n273,
DP_OP_168J30_122_4811_n272, DP_OP_168J30_122_4811_n271,
DP_OP_168J30_122_4811_n270, DP_OP_168J30_122_4811_n269,
DP_OP_168J30_122_4811_n268, DP_OP_168J30_122_4811_n267,
DP_OP_168J30_122_4811_n266, DP_OP_168J30_122_4811_n265,
DP_OP_168J30_122_4811_n264, DP_OP_168J30_122_4811_n263,
DP_OP_168J30_122_4811_n262, DP_OP_168J30_122_4811_n261,
DP_OP_168J30_122_4811_n260, DP_OP_168J30_122_4811_n259,
DP_OP_168J30_122_4811_n258, DP_OP_168J30_122_4811_n257,
DP_OP_168J30_122_4811_n256, DP_OP_168J30_122_4811_n255,
DP_OP_168J30_122_4811_n254, DP_OP_168J30_122_4811_n253,
DP_OP_168J30_122_4811_n252, DP_OP_168J30_122_4811_n251,
DP_OP_168J30_122_4811_n250, DP_OP_168J30_122_4811_n249,
DP_OP_168J30_122_4811_n248, DP_OP_168J30_122_4811_n247,
DP_OP_168J30_122_4811_n246, DP_OP_168J30_122_4811_n245,
DP_OP_168J30_122_4811_n244, DP_OP_168J30_122_4811_n243,
DP_OP_168J30_122_4811_n242, DP_OP_168J30_122_4811_n241,
DP_OP_168J30_122_4811_n240, DP_OP_168J30_122_4811_n239,
DP_OP_168J30_122_4811_n238, DP_OP_168J30_122_4811_n237,
DP_OP_168J30_122_4811_n236, DP_OP_168J30_122_4811_n235,
DP_OP_168J30_122_4811_n234, DP_OP_168J30_122_4811_n233,
DP_OP_168J30_122_4811_n232, DP_OP_168J30_122_4811_n231,
DP_OP_168J30_122_4811_n230, DP_OP_168J30_122_4811_n229,
DP_OP_168J30_122_4811_n228, DP_OP_168J30_122_4811_n227,
DP_OP_168J30_122_4811_n226, DP_OP_168J30_122_4811_n225,
DP_OP_168J30_122_4811_n224, DP_OP_168J30_122_4811_n223,
DP_OP_168J30_122_4811_n222, DP_OP_168J30_122_4811_n221,
DP_OP_168J30_122_4811_n220, DP_OP_168J30_122_4811_n219,
DP_OP_168J30_122_4811_n218, DP_OP_168J30_122_4811_n217,
DP_OP_168J30_122_4811_n216, DP_OP_168J30_122_4811_n215,
DP_OP_168J30_122_4811_n86, DP_OP_168J30_122_4811_n66,
DP_OP_168J30_122_4811_n56, intadd_76_n36, intadd_76_n35,
intadd_76_n34, intadd_76_n33, intadd_76_n32, intadd_76_n31,
intadd_76_n30, intadd_76_n29, intadd_76_n28, intadd_76_n26,
intadd_76_n25, intadd_76_n24, intadd_76_n23, intadd_76_n22,
intadd_76_n21, intadd_76_n20, intadd_76_n19, intadd_76_n18,
intadd_76_n17, intadd_76_n16, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1525, n1526, n1527, n1528, n1529,
n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539,
n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549,
n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559,
n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569,
n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579,
n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589,
n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599,
n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649,
n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659,
n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669,
n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679,
n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689,
n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699,
n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709,
n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719,
n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729,
n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739,
n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749,
n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759,
n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769,
n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779,
n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789,
n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799,
n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809,
n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819,
n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829,
n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839,
n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849,
n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859,
n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869,
n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879,
n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889,
n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909,
n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919,
n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929,
n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939,
n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949,
n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959,
n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969,
n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979,
n1980, n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989,
n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999,
n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009,
n2010, n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019,
n2020, n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029,
n2030, n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039,
n2040, n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049,
n2050, n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059,
n2060, n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069,
n2070, n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079,
n2080, n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089,
n2090, n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099,
n2100, n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109,
n2110, n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119,
n2120, n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129,
n2130, n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139,
n2140, n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149,
n2150, n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159,
n2160, n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169,
n2170, n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179,
n2180, n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189,
n2190, n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199,
n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209,
n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219,
n2220, n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229,
n2230, n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239,
n2240, n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249,
n2250, n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259,
n2260, n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269,
n2270, n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279,
n2280, n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289,
n2290, n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299,
n2300, n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309,
n2310, n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319,
n2320, n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329,
n2330, n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339,
n2340, n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349,
n2350, n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359,
n2360, n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369,
n2370, n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379,
n2380, n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419,
n2420, n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429,
n2430, n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439,
n2440, n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449,
n2450, n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459,
n2460, n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469,
n2470, n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479,
n2480, n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489,
n2490, n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499,
n2500, n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509,
n2510, n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519,
n2520, n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529,
n2530, n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539,
n2540, n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549,
n2550, n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559,
n2560, n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569,
n2570, n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579,
n2580, n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589,
n2590, n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599,
n2600, n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609,
n2610, n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619,
n2620, n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629,
n2630, n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639,
n2640, n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649,
n2650, n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659,
n2660, n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669,
n2670, n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679,
n2680, n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689,
n2690, n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699,
n2700, n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709,
n2710, n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719,
n2720, n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729,
n2730, n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739,
n2740, n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749,
n2750, n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759,
n2760, n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769,
n2770, n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779,
n2780, n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789,
n2790, n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799,
n2800, n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809,
n2810, n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819,
n2820, n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829,
n2830, n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839,
n2840, n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849,
n2850, n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859,
n2860, n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869,
n2870, n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879,
n2880, n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889,
n2890, n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899,
n2900, n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909,
n2910, n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919,
n2920, n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929,
n2930, n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939,
n2940, n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949,
n2950, n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959,
n2960, n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969,
n2970, n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979,
n2980, n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989,
n2990, n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999,
n3000, n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009,
n3010, n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019,
n3020, n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029,
n3030, n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039,
n3040, n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049,
n3050, n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059,
n3060, n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069,
n3070, n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079,
n3080, n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089,
n3090, n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099,
n3100, n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109,
n3110, n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119,
n3120, n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129,
n3130, n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139,
n3140, n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149,
n3150, n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159,
n3160, n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169,
n3170, n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179,
n3180, n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189,
n3190, n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199,
n3200, n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209,
n3210, n3211, n3212, n3213, n3214, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550,
n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560,
n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570,
n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580,
n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590,
n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600,
n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660,
n3661, n3662, n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670,
n3671, n3672, n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680,
n3681, n3682, n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690,
n3691, n3692, n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700,
n3701, n3702, n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710,
n3711, n3712, n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720,
n3721, n3722, n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730,
n3731, n3732, n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740,
n3741, n3742, n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750,
n3751, n3752, n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760,
n3761, n3762, n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770,
n3771, n3772, n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780,
n3781, n3782, n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790,
n3791, n3792, n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800,
n3801, n3802, n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810,
n3811, n3812, n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820,
n3821, n3822, n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830,
n3831, n3832, n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840,
n3841, n3842, n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850,
n3851, n3852, n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860,
n3861, n3862, n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870,
n3871, n3872, n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880,
n3881, n3882, n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890,
n3891, n3892, n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900,
n3901, n3902, n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910,
n3911, n3912, n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920,
n3921, n3922, n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930,
n3931, n3932, n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940,
n3941, n3942, n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950,
n3951, n3952, n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960,
n3961, n3962, n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970,
n3971, n3972, n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980,
n3981, n3982, n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990,
n3991, n3992, n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000,
n4001, n4002, n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010,
n4011, n4012, n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020,
n4021, n4022, n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030,
n4031, n4032, n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040,
n4041, n4042, n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050,
n4051, n4052, n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060,
n4061, n4062, n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070,
n4071, n4072, n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080,
n4081, n4082, n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090,
n4091, n4092, n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100,
n4101, n4102, n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110,
n4111, n4112, n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120,
n4121, n4122, n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130,
n4131, n4132, n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140,
n4141, n4142, n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150,
n4151, n4152, n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160,
n4161, n4162, n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170,
n4171, n4172, n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180,
n4181, n4182, n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190,
n4191, n4192, n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200,
n4201, n4202, n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210,
n4211, n4212, n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220,
n4221, n4222, n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230,
n4231, n4232, n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240,
n4241, n4242, n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250,
n4251, n4252, n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260,
n4261, n4262, n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270,
n4271, n4272, n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280,
n4281, n4282, n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290,
n4291, n4292, n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300,
n4301, n4302, n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310,
n4311, n4312, n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320,
n4321, n4322, n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330,
n4331, n4332, n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340,
n4341, n4342, n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350,
n4351, n4352, n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360,
n4361, n4362, n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370,
n4372, n4373, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, n4984, n4985, n4986, n4987, n4988, n4989, n4990, n4991, n4992,
n4993, n4994, n4995, n4996, n4997, n4998, n4999, n5000, n5001, n5002,
n5003, n5004, n5005, n5006, n5007, n5008, n5009, n5010, n5011, n5012,
n5013, n5014, n5015, n5016, n5017, n5018, n5019, n5020, n5021, n5022,
n5023, n5024, n5025, n5026, n5027, n5028, n5029, n5030, n5031, n5032,
n5033, n5034, n5035, n5036, n5037, n5038, n5039, n5040, n5041, n5042,
n5043, n5044, n5045, n5046, n5047, n5048, n5049, n5050, n5051, n5052,
n5053, n5054, n5055, n5056, n5057, n5058, n5059, n5060, n5061, n5062,
n5063, n5064, n5065, n5066, n5067, n5068, n5069, n5070, n5071, n5072,
n5073, n5074, n5075, n5076, n5077, n5078, n5079, n5080, n5081, n5082,
n5083, n5085, n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093,
n5094, n5095, n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103,
n5104, n5105, n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113,
n5114, n5115, n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123,
n5124, n5125, n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133,
n5134, n5135, n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143,
n5144, n5145, n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153,
n5154, n5155, n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163,
n5164, n5165, n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173,
n5174, n5175, n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183,
n5184, n5185, n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193,
n5194, n5195, n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203,
n5204, n5205, n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213,
n5214, n5215, n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223,
n5224, n5225, n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233,
n5234, n5235, n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243,
n5244, n5245, n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253,
n5254, n5255, n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263,
n5264, n5265, n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273,
n5274, n5275, n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283,
n5284, n5285, n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293,
n5294, n5295, n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303,
n5304, n5305, n5306, n5307, n5309, n5310, n5311, n5312, n5313, n5314,
n5315, n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324,
n5325, n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334,
n5335, n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344,
n5345, n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354,
n5355, n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364,
n5365, n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374,
n5375, n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384,
n5385, n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394,
n5395, n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404,
n5405, n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414,
n5415, n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424,
n5425, n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434,
n5435, n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444,
n5445, n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454,
n5455, n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464,
n5465, n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474,
n5475, n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484,
n5485, n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494,
n5495, n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504,
n5505, n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514,
n5515, n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524,
n5525, n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:0] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
wire [50:30] Sgf_operation_ODD1_Q_left;
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n715), .CK(clk), .RN(
n5532), .Q(Op_MY[63]) );
DFFRXLTS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n698), .CK(clk), .RN(
n5534), .QN(n763) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n528), .CK(clk), .RN(n5538),
.QN(n765) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n529), .CK(clk), .RN(n5538),
.QN(n786) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n530), .CK(clk), .RN(n5538),
.QN(n776) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n531), .CK(clk), .RN(n5538),
.QN(n785) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n532), .CK(clk), .RN(n5538),
.QN(n772) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n533), .CK(clk), .RN(n5538),
.QN(n784) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n534), .CK(clk), .RN(n5538),
.QN(n767) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n535), .CK(clk), .RN(n5538),
.QN(n783) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n536), .CK(clk), .RN(n5538),
.QN(n766) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n548), .CK(clk), .RN(n5540),
.QN(n771) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n549), .CK(clk), .RN(n5540),
.QN(n782) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n550), .CK(clk), .RN(n5540),
.QN(n770) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n551), .CK(clk), .RN(n5540),
.QN(n781) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n552), .CK(clk), .RN(n5540),
.QN(n769) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n553), .CK(clk), .RN(n5540),
.QN(n780) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n554), .CK(clk), .RN(n5540),
.QN(n768) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n555), .CK(clk), .RN(n5540),
.QN(n779) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n556), .CK(clk), .RN(n5540),
.QN(n775) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n557), .CK(clk), .RN(n5540),
.QN(n778) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n558), .CK(clk), .RN(n5540),
.QN(n774) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n559), .CK(clk), .RN(n5540),
.QN(n777) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n560), .CK(clk), .RN(n5538),
.QN(n773) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n564), .CK(clk), .RN(n5538),
.QN(n789) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n566), .CK(clk), .RN(n5538),
.QN(n788) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n5538),
.QN(n787) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n579), .CK(clk), .RN(n5541),
.Q(Add_result[0]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n527), .CK(clk), .RN(n5541),
.Q(Add_result[52]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n641), .CK(clk), .RN(
n5538), .QN(n764) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n640), .CK(clk), .RN(
n5543), .QN(n728) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n639), .CK(clk), .RN(
n5543), .QN(n733) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_70_ ( .D(n491), .CK(clk), .RN(
n5546), .Q(P_Sgf[70]), .QN(n5504) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_47_ ( .D(n468), .CK(clk), .RN(
n5545), .Q(P_Sgf[47]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_46_ ( .D(n467), .CK(clk), .RN(
n5544), .Q(P_Sgf[46]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_45_ ( .D(n466), .CK(clk), .RN(
n5546), .Q(P_Sgf[45]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_44_ ( .D(n465), .CK(clk), .RN(
n5549), .Q(P_Sgf[44]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_43_ ( .D(n464), .CK(clk), .RN(
n5544), .Q(P_Sgf[43]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_42_ ( .D(n463), .CK(clk), .RN(
n5546), .Q(P_Sgf[42]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_41_ ( .D(n462), .CK(clk), .RN(
n5549), .Q(P_Sgf[41]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_40_ ( .D(n461), .CK(clk), .RN(
n5547), .Q(P_Sgf[40]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_36_ ( .D(n457), .CK(clk), .RN(
n5546), .Q(P_Sgf[36]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_35_ ( .D(n456), .CK(clk), .RN(
n5546), .Q(P_Sgf[35]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_31_ ( .D(n452), .CK(clk), .RN(
n5547), .Q(P_Sgf[31]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_27_ ( .D(n448), .CK(clk), .RN(
n5547), .Q(P_Sgf[27]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_23_ ( .D(n444), .CK(clk), .RN(
n5547), .Q(P_Sgf[23]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_19_ ( .D(n440), .CK(clk), .RN(
n5548), .Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_15_ ( .D(n436), .CK(clk), .RN(
n5548), .Q(P_Sgf[15]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_11_ ( .D(n432), .CK(clk), .RN(
n5548), .Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_7_ ( .D(n428), .CK(clk), .RN(
n5549), .Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_3_ ( .D(n424), .CK(clk), .RN(
n5549), .Q(P_Sgf[3]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n405), .CK(clk), .RN(n5542), .Q(
Exp_module_Overflow_flag_A) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n351),
.CK(clk), .RN(n5535), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n350),
.CK(clk), .RN(n5532), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n349),
.CK(clk), .RN(n5537), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n348),
.CK(clk), .RN(n5530), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n347),
.CK(clk), .RN(n5528), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n346),
.CK(clk), .RN(n5534), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n345),
.CK(clk), .RN(n5528), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n344),
.CK(clk), .RN(n5530), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n343),
.CK(clk), .RN(n5528), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n342),
.CK(clk), .RN(n5534), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n341),
.CK(clk), .RN(n5531), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n340),
.CK(clk), .RN(n5530), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n339),
.CK(clk), .RN(n5535), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n338),
.CK(clk), .RN(n5532), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n337),
.CK(clk), .RN(n5537), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n336),
.CK(clk), .RN(n5528), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n335),
.CK(clk), .RN(n5530), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n334),
.CK(clk), .RN(n5534), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n333),
.CK(clk), .RN(n5539), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n332),
.CK(clk), .RN(n5540), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n331),
.CK(clk), .RN(n5539), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n330),
.CK(clk), .RN(n5540), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n329),
.CK(clk), .RN(n5539), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n328),
.CK(clk), .RN(n5540), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n327),
.CK(clk), .RN(n5539), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n326),
.CK(clk), .RN(n5540), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n325),
.CK(clk), .RN(n5539), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n324),
.CK(clk), .RN(n5540), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n323),
.CK(clk), .RN(n5539), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n322),
.CK(clk), .RN(n5540), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n321),
.CK(clk), .RN(n5551), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n320),
.CK(clk), .RN(n5551), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n319),
.CK(clk), .RN(n5551), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n318),
.CK(clk), .RN(n5551), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n317),
.CK(clk), .RN(n5551), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n316),
.CK(clk), .RN(n5551), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n315),
.CK(clk), .RN(n5551), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n314),
.CK(clk), .RN(n5551), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n313),
.CK(clk), .RN(n5551), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n312),
.CK(clk), .RN(n5551), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n311),
.CK(clk), .RN(n5551), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n310),
.CK(clk), .RN(n5551), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n309),
.CK(clk), .RN(n5531), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n308),
.CK(clk), .RN(n5535), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n307),
.CK(clk), .RN(n5537), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n306),
.CK(clk), .RN(n5532), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n305),
.CK(clk), .RN(n5530), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n304),
.CK(clk), .RN(n5528), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n303),
.CK(clk), .RN(n5530), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n302),
.CK(clk), .RN(n5534), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n301),
.CK(clk), .RN(n5531), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n300),
.CK(clk), .RN(n5535), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n299),
.CK(clk), .RN(n5532), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n298),
.CK(clk), .RN(n5537), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n297),
.CK(clk), .RN(n5531), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n296),
.CK(clk), .RN(n5535), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n295),
.CK(clk), .RN(n5532), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n294),
.CK(clk), .RN(n5537), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n293),
.CK(clk), .RN(n5528), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n292),
.CK(clk), .RN(n5530), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n291),
.CK(clk), .RN(n5528), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n290),
.CK(clk), .RN(n5534), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n289),
.CK(clk), .RN(n5530), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n287),
.CK(clk), .RN(n5535), .Q(final_result_ieee[63]), .QN(n5525) );
CMPR32X2TS DP_OP_36J30_123_1029_U13 ( .A(S_Oper_A_exp[0]), .B(n5526), .C(
DP_OP_36J30_123_1029_n28), .CO(DP_OP_36J30_123_1029_n12), .S(
Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_36J30_123_1029_U12 ( .A(DP_OP_36J30_123_1029_n27), .B(
S_Oper_A_exp[1]), .C(DP_OP_36J30_123_1029_n12), .CO(
DP_OP_36J30_123_1029_n11), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_36J30_123_1029_U11 ( .A(DP_OP_36J30_123_1029_n26), .B(
S_Oper_A_exp[2]), .C(DP_OP_36J30_123_1029_n11), .CO(
DP_OP_36J30_123_1029_n10), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_36J30_123_1029_U10 ( .A(DP_OP_36J30_123_1029_n25), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J30_123_1029_n10), .CO(
DP_OP_36J30_123_1029_n9), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_36J30_123_1029_U9 ( .A(DP_OP_36J30_123_1029_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J30_123_1029_n9), .CO(
DP_OP_36J30_123_1029_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J30_123_1029_U8 ( .A(DP_OP_36J30_123_1029_n23), .B(
S_Oper_A_exp[5]), .C(DP_OP_36J30_123_1029_n8), .CO(
DP_OP_36J30_123_1029_n7), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_36J30_123_1029_U7 ( .A(DP_OP_36J30_123_1029_n22), .B(
S_Oper_A_exp[6]), .C(DP_OP_36J30_123_1029_n7), .CO(
DP_OP_36J30_123_1029_n6), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_36J30_123_1029_U6 ( .A(DP_OP_36J30_123_1029_n21), .B(
S_Oper_A_exp[7]), .C(DP_OP_36J30_123_1029_n6), .CO(
DP_OP_36J30_123_1029_n5), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_36J30_123_1029_U5 ( .A(DP_OP_36J30_123_1029_n20), .B(
S_Oper_A_exp[8]), .C(DP_OP_36J30_123_1029_n5), .CO(
DP_OP_36J30_123_1029_n4), .S(Exp_module_Data_S[8]) );
CMPR32X2TS DP_OP_36J30_123_1029_U4 ( .A(DP_OP_36J30_123_1029_n19), .B(
S_Oper_A_exp[9]), .C(DP_OP_36J30_123_1029_n4), .CO(
DP_OP_36J30_123_1029_n3), .S(Exp_module_Data_S[9]) );
CMPR32X2TS DP_OP_36J30_123_1029_U3 ( .A(DP_OP_36J30_123_1029_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_36J30_123_1029_n3), .CO(
DP_OP_36J30_123_1029_n2), .S(Exp_module_Data_S[10]) );
CMPR32X2TS DP_OP_36J30_123_1029_U2 ( .A(n5526), .B(S_Oper_A_exp[11]), .C(
DP_OP_36J30_123_1029_n2), .CO(DP_OP_36J30_123_1029_n1), .S(
Exp_module_Data_S[11]) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n581), .CK(clk),
.RN(n5530), .Q(zero_flag), .QN(n5524) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_60_ ( .D(n481), .CK(clk), .RN(
n5545), .Q(P_Sgf[60]), .QN(n5523) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_62_ ( .D(n483), .CK(clk), .RN(
n5545), .Q(P_Sgf[62]), .QN(n5521) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_63_ ( .D(n484), .CK(clk), .RN(
n5545), .Q(P_Sgf[63]), .QN(n5520) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_64_ ( .D(n485), .CK(clk), .RN(
n5545), .Q(P_Sgf[64]), .QN(n5519) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_65_ ( .D(n486), .CK(clk), .RN(
n5545), .Q(P_Sgf[65]), .QN(n5518) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_66_ ( .D(n487), .CK(clk), .RN(
n5546), .Q(P_Sgf[66]), .QN(n5517) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_67_ ( .D(n488), .CK(clk), .RN(
n5546), .Q(P_Sgf[67]), .QN(n5516) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_68_ ( .D(n489), .CK(clk), .RN(
n5546), .Q(P_Sgf[68]), .QN(n5515) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_69_ ( .D(n490), .CK(clk), .RN(
n5546), .Q(P_Sgf[69]), .QN(n5514) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_53_ ( .D(n474), .CK(clk), .RN(
n286), .Q(P_Sgf[53]), .QN(n5513) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_54_ ( .D(n475), .CK(clk), .RN(
n5545), .Q(P_Sgf[54]), .QN(n5512) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_55_ ( .D(n476), .CK(clk), .RN(
n5545), .Q(P_Sgf[55]), .QN(n5511) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_56_ ( .D(n477), .CK(clk), .RN(
n5545), .Q(P_Sgf[56]), .QN(n5510) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_57_ ( .D(n478), .CK(clk), .RN(
n5545), .Q(P_Sgf[57]), .QN(n5509) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_58_ ( .D(n479), .CK(clk), .RN(
n5545), .Q(P_Sgf[58]), .QN(n5508) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n5534),
.Q(underflow_flag), .QN(n5506) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n404), .CK(clk),
.RN(n5542), .Q(Sgf_normalized_result[51]), .QN(n5502) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n402), .CK(clk),
.RN(n5543), .Q(Sgf_normalized_result[49]), .QN(n5501) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n400), .CK(clk),
.RN(n5542), .Q(Sgf_normalized_result[47]), .QN(n5500) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n398), .CK(clk),
.RN(n5543), .Q(Sgf_normalized_result[45]), .QN(n5499) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n396), .CK(clk),
.RN(n5551), .Q(Sgf_normalized_result[43]), .QN(n5498) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n419), .CK(clk), .RN(n5543), .Q(
FSM_selector_B[0]), .QN(n5497) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n394), .CK(clk),
.RN(n5542), .Q(Sgf_normalized_result[41]), .QN(n5496) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n392), .CK(clk),
.RN(n5528), .Q(Sgf_normalized_result[39]), .QN(n5495) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n713), .CK(clk), .RN(n5544), .Q(
FS_Module_state_reg[0]), .QN(n5494) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n390), .CK(clk),
.RN(n5530), .Q(Sgf_normalized_result[37]), .QN(n5493) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n388), .CK(clk),
.RN(n5532), .Q(Sgf_normalized_result[35]), .QN(n5492) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n386), .CK(clk),
.RN(n5537), .Q(Sgf_normalized_result[33]), .QN(n5491) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n384), .CK(clk),
.RN(n5535), .Q(Sgf_normalized_result[31]), .QN(n5490) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n382), .CK(clk),
.RN(n5531), .Q(Sgf_normalized_result[29]), .QN(n5489) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n380), .CK(clk),
.RN(n5530), .Q(Sgf_normalized_result[27]), .QN(n5488) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n378), .CK(clk),
.RN(n5534), .Q(Sgf_normalized_result[25]), .QN(n5487) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n376), .CK(clk),
.RN(n5537), .Q(Sgf_normalized_result[23]), .QN(n5486) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n374), .CK(clk),
.RN(n5531), .Q(Sgf_normalized_result[21]), .QN(n5485) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n372), .CK(clk),
.RN(n5530), .Q(Sgf_normalized_result[19]), .QN(n5484) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n370), .CK(clk),
.RN(n5528), .Q(Sgf_normalized_result[17]), .QN(n5483) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n368), .CK(clk),
.RN(n5534), .Q(Sgf_normalized_result[15]), .QN(n5482) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n366), .CK(clk),
.RN(n5531), .Q(Sgf_normalized_result[13]), .QN(n5481) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n364), .CK(clk),
.RN(n4671), .Q(Sgf_normalized_result[11]), .QN(n5480) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n362), .CK(clk),
.RN(n4671), .Q(Sgf_normalized_result[9]), .QN(n5479) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n360), .CK(clk),
.RN(n5530), .Q(Sgf_normalized_result[7]), .QN(n5478) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n626), .CK(clk), .RN(
n5542), .Q(Op_MY[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n358), .CK(clk),
.RN(n5535), .Q(Sgf_normalized_result[5]), .QN(n5477) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n625), .CK(clk), .RN(
n5542), .Q(Op_MY[43]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n622), .CK(clk), .RN(
n5542), .Q(Op_MY[40]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n623), .CK(clk), .RN(
n5542), .Q(Op_MY[41]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n624), .CK(clk), .RN(
n5542), .Q(Op_MY[42]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n696), .CK(clk), .RN(
n5531), .Q(Op_MX[50]), .QN(n762) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n620), .CK(clk), .RN(
n5542), .Q(Op_MY[38]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n621), .CK(clk), .RN(
n5542), .Q(Op_MY[39]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n693), .CK(clk), .RN(
n5538), .Q(Op_MX[47]), .QN(n881) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n603), .CK(clk), .RN(
n5539), .Q(Op_MY[21]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n604), .CK(clk), .RN(
n5540), .Q(Op_MY[22]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n606), .CK(clk), .RN(
n5529), .Q(Op_MY[24]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n605), .CK(clk), .RN(
n5539), .Q(Op_MY[23]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n607), .CK(clk), .RN(
n5543), .Q(Op_MY[25]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n618), .CK(clk), .RN(
n5543), .Q(Op_MY[36]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n619), .CK(clk), .RN(
n5542), .Q(Op_MY[37]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n617), .CK(clk), .RN(
n5543), .Q(Op_MY[35]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n690), .CK(clk), .RN(
n4671), .Q(Op_MX[44]), .QN(n912) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n616), .CK(clk), .RN(
n5543), .Q(Op_MY[34]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n687), .CK(clk), .RN(
n5528), .Q(Op_MX[41]), .QN(n891) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n597), .CK(clk), .RN(
n5530), .Q(Op_MY[15]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n598), .CK(clk), .RN(
n5528), .Q(Op_MY[16]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n599), .CK(clk), .RN(
n5537), .Q(Op_MY[17]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n614), .CK(clk), .RN(
n5543), .Q(Op_MY[32]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n615), .CK(clk), .RN(
n5543), .Q(Op_MY[33]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n681), .CK(clk), .RN(
n5540), .Q(Op_MX[35]), .QN(n760) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n684), .CK(clk), .RN(
n4671), .Q(Op_MX[38]), .QN(n761) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n596), .CK(clk), .RN(
n5531), .Q(Op_MY[14]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n613), .CK(clk), .RN(
n5543), .Q(Op_MY[31]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n612), .CK(clk), .RN(
n5543), .Q(Op_MY[30]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n678), .CK(clk), .RN(
n5539), .Q(Op_MX[32]), .QN(n759) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n594), .CK(clk), .RN(
n5535), .Q(Op_MY[12]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n593), .CK(clk), .RN(
n5532), .Q(Op_MY[11]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n595), .CK(clk), .RN(
n5534), .Q(Op_MY[13]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n611), .CK(clk), .RN(
n5543), .Q(Op_MY[29]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n669), .CK(clk), .RN(
n5536), .Q(Op_MX[23]), .QN(n853) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n588), .CK(clk), .RN(
n5542), .Q(Op_MY[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n589), .CK(clk), .RN(
n5530), .Q(Op_MY[7]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n592), .CK(clk), .RN(
n5528), .Q(Op_MY[10]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n590), .CK(clk), .RN(
n5530), .Q(Op_MY[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n591), .CK(clk), .RN(
n5537), .Q(Op_MY[9]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n666), .CK(clk), .RN(
n5536), .Q(Op_MX[20]), .QN(n854) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n663), .CK(clk), .RN(
n5536), .Q(Op_MX[17]), .QN(n861) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n585), .CK(clk), .RN(
n5543), .Q(Op_MY[3]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n587), .CK(clk), .RN(
n5535), .Q(Op_MY[5]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n586), .CK(clk), .RN(
n5541), .Q(Op_MY[4]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n654), .CK(clk), .RN(
n5534), .Q(Op_MX[8]), .QN(n857) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n657), .CK(clk), .RN(
n5528), .Q(Op_MX[11]), .QN(n856) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n660), .CK(clk), .RN(
n5536), .Q(Op_MX[14]), .QN(n858) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n583), .CK(clk), .RN(
n5543), .Q(Op_MY[1]) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n418), .CK(clk), .RN(n5541), .Q(
FSM_selector_B[1]), .QN(n5475) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n711), .CK(clk), .RN(n5544), .Q(
FS_Module_state_reg[2]), .QN(n5474) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n608), .CK(clk), .RN(
n5543), .Q(Op_MY[26]) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n714), .CK(clk), .RN(n286), .Q(
FS_Module_state_reg[3]), .QN(n5473) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n582), .CK(clk), .RN(
n5542), .Q(Op_MY[0]), .QN(n859) );
CMPR42X1TS DP_OP_168J30_122_4811_U3314 ( .A(DP_OP_168J30_122_4811_n4195),
.B(DP_OP_168J30_122_4811_n4518), .C(DP_OP_168J30_122_4811_n4198), .D(
DP_OP_168J30_122_4811_n4544), .ICI(DP_OP_168J30_122_4811_n4196), .S(
DP_OP_168J30_122_4811_n4193), .ICO(DP_OP_168J30_122_4811_n4191), .CO(
DP_OP_168J30_122_4811_n4192) );
CMPR42X1TS DP_OP_168J30_122_4811_U3312 ( .A(DP_OP_168J30_122_4811_n4517),
.B(DP_OP_168J30_122_4811_n4190), .C(DP_OP_168J30_122_4811_n4191), .D(
DP_OP_168J30_122_4811_n4543), .ICI(DP_OP_168J30_122_4811_n4192), .S(
DP_OP_168J30_122_4811_n4188), .ICO(DP_OP_168J30_122_4811_n4186), .CO(
DP_OP_168J30_122_4811_n4187) );
CMPR42X1TS DP_OP_168J30_122_4811_U3310 ( .A(DP_OP_168J30_122_4811_n4516),
.B(DP_OP_168J30_122_4811_n4185), .C(DP_OP_168J30_122_4811_n4186), .D(
DP_OP_168J30_122_4811_n4542), .ICI(DP_OP_168J30_122_4811_n4187), .S(
DP_OP_168J30_122_4811_n4183), .ICO(DP_OP_168J30_122_4811_n4181), .CO(
DP_OP_168J30_122_4811_n4182) );
CMPR42X1TS DP_OP_168J30_122_4811_U3301 ( .A(DP_OP_168J30_122_4811_n4513),
.B(DP_OP_168J30_122_4811_n4164), .C(DP_OP_168J30_122_4811_n4167), .D(
DP_OP_168J30_122_4811_n4539), .ICI(DP_OP_168J30_122_4811_n4168), .S(
DP_OP_168J30_122_4811_n4162), .ICO(DP_OP_168J30_122_4811_n4160), .CO(
DP_OP_168J30_122_4811_n4161) );
CMPR42X1TS DP_OP_168J30_122_4811_U3299 ( .A(DP_OP_168J30_122_4811_n4159),
.B(DP_OP_168J30_122_4811_n4460), .C(DP_OP_168J30_122_4811_n4165), .D(
DP_OP_168J30_122_4811_n4486), .ICI(DP_OP_168J30_122_4811_n4163), .S(
DP_OP_168J30_122_4811_n4157), .ICO(DP_OP_168J30_122_4811_n4155), .CO(
DP_OP_168J30_122_4811_n4156) );
CMPR42X1TS DP_OP_168J30_122_4811_U3298 ( .A(DP_OP_168J30_122_4811_n4512),
.B(DP_OP_168J30_122_4811_n4157), .C(DP_OP_168J30_122_4811_n4160), .D(
DP_OP_168J30_122_4811_n4538), .ICI(DP_OP_168J30_122_4811_n4161), .S(
DP_OP_168J30_122_4811_n4154), .ICO(DP_OP_168J30_122_4811_n4152), .CO(
DP_OP_168J30_122_4811_n4153) );
CMPR42X1TS DP_OP_168J30_122_4811_U3296 ( .A(DP_OP_168J30_122_4811_n4459),
.B(DP_OP_168J30_122_4811_n4151), .C(DP_OP_168J30_122_4811_n4155), .D(
DP_OP_168J30_122_4811_n4485), .ICI(DP_OP_168J30_122_4811_n4156), .S(
DP_OP_168J30_122_4811_n4149), .ICO(DP_OP_168J30_122_4811_n4147), .CO(
DP_OP_168J30_122_4811_n4148) );
CMPR42X1TS DP_OP_168J30_122_4811_U3295 ( .A(DP_OP_168J30_122_4811_n4511),
.B(DP_OP_168J30_122_4811_n4149), .C(DP_OP_168J30_122_4811_n4152), .D(
DP_OP_168J30_122_4811_n4537), .ICI(DP_OP_168J30_122_4811_n4153), .S(
DP_OP_168J30_122_4811_n4146), .ICO(DP_OP_168J30_122_4811_n4144), .CO(
DP_OP_168J30_122_4811_n4145) );
CMPR42X1TS DP_OP_168J30_122_4811_U3293 ( .A(DP_OP_168J30_122_4811_n4458),
.B(DP_OP_168J30_122_4811_n4143), .C(DP_OP_168J30_122_4811_n4147), .D(
DP_OP_168J30_122_4811_n4484), .ICI(DP_OP_168J30_122_4811_n4148), .S(
DP_OP_168J30_122_4811_n4141), .ICO(DP_OP_168J30_122_4811_n4139), .CO(
DP_OP_168J30_122_4811_n4140) );
CMPR42X1TS DP_OP_168J30_122_4811_U3292 ( .A(DP_OP_168J30_122_4811_n4510),
.B(DP_OP_168J30_122_4811_n4141), .C(DP_OP_168J30_122_4811_n4144), .D(
DP_OP_168J30_122_4811_n4536), .ICI(DP_OP_168J30_122_4811_n4145), .S(
DP_OP_168J30_122_4811_n4138), .ICO(DP_OP_168J30_122_4811_n4136), .CO(
DP_OP_168J30_122_4811_n4137) );
CMPR42X1TS DP_OP_168J30_122_4811_U3289 ( .A(DP_OP_168J30_122_4811_n4457),
.B(DP_OP_168J30_122_4811_n4133), .C(DP_OP_168J30_122_4811_n4139), .D(
DP_OP_168J30_122_4811_n4483), .ICI(DP_OP_168J30_122_4811_n4140), .S(
DP_OP_168J30_122_4811_n4131), .ICO(DP_OP_168J30_122_4811_n4129), .CO(
DP_OP_168J30_122_4811_n4130) );
CMPR42X1TS DP_OP_168J30_122_4811_U3288 ( .A(DP_OP_168J30_122_4811_n4509),
.B(DP_OP_168J30_122_4811_n4131), .C(DP_OP_168J30_122_4811_n4136), .D(
DP_OP_168J30_122_4811_n4535), .ICI(DP_OP_168J30_122_4811_n4137), .S(
DP_OP_168J30_122_4811_n4128), .ICO(DP_OP_168J30_122_4811_n4126), .CO(
DP_OP_168J30_122_4811_n4127) );
CMPR42X1TS DP_OP_168J30_122_4811_U3285 ( .A(DP_OP_168J30_122_4811_n4456),
.B(DP_OP_168J30_122_4811_n4123), .C(DP_OP_168J30_122_4811_n4129), .D(
DP_OP_168J30_122_4811_n4482), .ICI(DP_OP_168J30_122_4811_n4130), .S(
DP_OP_168J30_122_4811_n4121), .ICO(DP_OP_168J30_122_4811_n4119), .CO(
DP_OP_168J30_122_4811_n4120) );
CMPR42X1TS DP_OP_168J30_122_4811_U3284 ( .A(DP_OP_168J30_122_4811_n4508),
.B(DP_OP_168J30_122_4811_n4121), .C(DP_OP_168J30_122_4811_n4126), .D(
DP_OP_168J30_122_4811_n4534), .ICI(DP_OP_168J30_122_4811_n4127), .S(
DP_OP_168J30_122_4811_n4118), .ICO(DP_OP_168J30_122_4811_n4116), .CO(
DP_OP_168J30_122_4811_n4117) );
CMPR42X1TS DP_OP_168J30_122_4811_U3281 ( .A(DP_OP_168J30_122_4811_n4455),
.B(DP_OP_168J30_122_4811_n4113), .C(DP_OP_168J30_122_4811_n4119), .D(
DP_OP_168J30_122_4811_n4481), .ICI(DP_OP_168J30_122_4811_n4120), .S(
DP_OP_168J30_122_4811_n4111), .ICO(DP_OP_168J30_122_4811_n4109), .CO(
DP_OP_168J30_122_4811_n4110) );
CMPR42X1TS DP_OP_168J30_122_4811_U3280 ( .A(DP_OP_168J30_122_4811_n4111),
.B(DP_OP_168J30_122_4811_n4507), .C(DP_OP_168J30_122_4811_n4116), .D(
DP_OP_168J30_122_4811_n4533), .ICI(DP_OP_168J30_122_4811_n4117), .S(
DP_OP_168J30_122_4811_n4108), .ICO(DP_OP_168J30_122_4811_n4106), .CO(
DP_OP_168J30_122_4811_n4107) );
CMPR42X1TS DP_OP_168J30_122_4811_U3278 ( .A(DP_OP_168J30_122_4811_n4105),
.B(DP_OP_168J30_122_4811_n4402), .C(DP_OP_168J30_122_4811_n4114), .D(
DP_OP_168J30_122_4811_n4428), .ICI(DP_OP_168J30_122_4811_n4112), .S(
DP_OP_168J30_122_4811_n4103), .ICO(DP_OP_168J30_122_4811_n4101), .CO(
DP_OP_168J30_122_4811_n4102) );
CMPR42X1TS DP_OP_168J30_122_4811_U3277 ( .A(DP_OP_168J30_122_4811_n4454),
.B(DP_OP_168J30_122_4811_n4103), .C(DP_OP_168J30_122_4811_n4109), .D(
DP_OP_168J30_122_4811_n4480), .ICI(DP_OP_168J30_122_4811_n4110), .S(
DP_OP_168J30_122_4811_n4100), .ICO(DP_OP_168J30_122_4811_n4098), .CO(
DP_OP_168J30_122_4811_n4099) );
CMPR42X1TS DP_OP_168J30_122_4811_U3276 ( .A(DP_OP_168J30_122_4811_n4100),
.B(DP_OP_168J30_122_4811_n4506), .C(DP_OP_168J30_122_4811_n4106), .D(
DP_OP_168J30_122_4811_n4532), .ICI(DP_OP_168J30_122_4811_n4107), .S(
DP_OP_168J30_122_4811_n4097), .ICO(DP_OP_168J30_122_4811_n4095), .CO(
DP_OP_168J30_122_4811_n4096) );
CMPR42X1TS DP_OP_168J30_122_4811_U3274 ( .A(DP_OP_168J30_122_4811_n4401),
.B(DP_OP_168J30_122_4811_n4094), .C(DP_OP_168J30_122_4811_n4101), .D(
DP_OP_168J30_122_4811_n4427), .ICI(DP_OP_168J30_122_4811_n4102), .S(
DP_OP_168J30_122_4811_n4092), .ICO(DP_OP_168J30_122_4811_n4090), .CO(
DP_OP_168J30_122_4811_n4091) );
CMPR42X1TS DP_OP_168J30_122_4811_U3273 ( .A(DP_OP_168J30_122_4811_n4453),
.B(DP_OP_168J30_122_4811_n4092), .C(DP_OP_168J30_122_4811_n4098), .D(
DP_OP_168J30_122_4811_n4479), .ICI(DP_OP_168J30_122_4811_n4099), .S(
DP_OP_168J30_122_4811_n4089), .ICO(DP_OP_168J30_122_4811_n4087), .CO(
DP_OP_168J30_122_4811_n4088) );
CMPR42X1TS DP_OP_168J30_122_4811_U3272 ( .A(DP_OP_168J30_122_4811_n4089),
.B(DP_OP_168J30_122_4811_n4505), .C(DP_OP_168J30_122_4811_n4095), .D(
DP_OP_168J30_122_4811_n4531), .ICI(DP_OP_168J30_122_4811_n4096), .S(
DP_OP_168J30_122_4811_n4086), .ICO(DP_OP_168J30_122_4811_n4084), .CO(
DP_OP_168J30_122_4811_n4085) );
CMPR42X1TS DP_OP_168J30_122_4811_U3270 ( .A(DP_OP_168J30_122_4811_n4400),
.B(DP_OP_168J30_122_4811_n4083), .C(DP_OP_168J30_122_4811_n4090), .D(
DP_OP_168J30_122_4811_n4426), .ICI(DP_OP_168J30_122_4811_n4091), .S(
DP_OP_168J30_122_4811_n4081), .ICO(DP_OP_168J30_122_4811_n4079), .CO(
DP_OP_168J30_122_4811_n4080) );
CMPR42X1TS DP_OP_168J30_122_4811_U3269 ( .A(DP_OP_168J30_122_4811_n4452),
.B(DP_OP_168J30_122_4811_n4081), .C(DP_OP_168J30_122_4811_n4087), .D(
DP_OP_168J30_122_4811_n4478), .ICI(DP_OP_168J30_122_4811_n4088), .S(
DP_OP_168J30_122_4811_n4078), .ICO(DP_OP_168J30_122_4811_n4076), .CO(
DP_OP_168J30_122_4811_n4077) );
CMPR42X1TS DP_OP_168J30_122_4811_U3268 ( .A(DP_OP_168J30_122_4811_n4078),
.B(DP_OP_168J30_122_4811_n4504), .C(DP_OP_168J30_122_4811_n4084), .D(
DP_OP_168J30_122_4811_n4530), .ICI(DP_OP_168J30_122_4811_n4085), .S(
DP_OP_168J30_122_4811_n4075), .ICO(DP_OP_168J30_122_4811_n4073), .CO(
DP_OP_168J30_122_4811_n4074) );
CMPR42X1TS DP_OP_168J30_122_4811_U3266 ( .A(DP_OP_168J30_122_4811_n4399),
.B(DP_OP_168J30_122_4811_n4072), .C(DP_OP_168J30_122_4811_n4079), .D(
DP_OP_168J30_122_4811_n4425), .ICI(DP_OP_168J30_122_4811_n4080), .S(
DP_OP_168J30_122_4811_n4070), .ICO(DP_OP_168J30_122_4811_n4068), .CO(
DP_OP_168J30_122_4811_n4069) );
CMPR42X1TS DP_OP_168J30_122_4811_U3265 ( .A(DP_OP_168J30_122_4811_n4451),
.B(DP_OP_168J30_122_4811_n4070), .C(DP_OP_168J30_122_4811_n4076), .D(
DP_OP_168J30_122_4811_n4477), .ICI(DP_OP_168J30_122_4811_n4077), .S(
DP_OP_168J30_122_4811_n4067), .ICO(DP_OP_168J30_122_4811_n4065), .CO(
DP_OP_168J30_122_4811_n4066) );
CMPR42X1TS DP_OP_168J30_122_4811_U3264 ( .A(DP_OP_168J30_122_4811_n4067),
.B(DP_OP_168J30_122_4811_n4503), .C(DP_OP_168J30_122_4811_n4073), .D(
DP_OP_168J30_122_4811_n4529), .ICI(DP_OP_168J30_122_4811_n4074), .S(
DP_OP_168J30_122_4811_n4064), .ICO(DP_OP_168J30_122_4811_n4062), .CO(
DP_OP_168J30_122_4811_n4063) );
CMPR42X1TS DP_OP_168J30_122_4811_U3262 ( .A(DP_OP_168J30_122_4811_n4398),
.B(DP_OP_168J30_122_4811_n4061), .C(DP_OP_168J30_122_4811_n4068), .D(
DP_OP_168J30_122_4811_n4424), .ICI(DP_OP_168J30_122_4811_n4069), .S(
DP_OP_168J30_122_4811_n4059), .ICO(DP_OP_168J30_122_4811_n4057), .CO(
DP_OP_168J30_122_4811_n4058) );
CMPR42X1TS DP_OP_168J30_122_4811_U3261 ( .A(DP_OP_168J30_122_4811_n4450),
.B(DP_OP_168J30_122_4811_n4059), .C(DP_OP_168J30_122_4811_n4065), .D(
DP_OP_168J30_122_4811_n4476), .ICI(DP_OP_168J30_122_4811_n4066), .S(
DP_OP_168J30_122_4811_n4056), .ICO(DP_OP_168J30_122_4811_n4054), .CO(
DP_OP_168J30_122_4811_n4055) );
CMPR42X1TS DP_OP_168J30_122_4811_U3260 ( .A(DP_OP_168J30_122_4811_n4056),
.B(DP_OP_168J30_122_4811_n4502), .C(DP_OP_168J30_122_4811_n4062), .D(
DP_OP_168J30_122_4811_n4528), .ICI(DP_OP_168J30_122_4811_n4063), .S(
DP_OP_168J30_122_4811_n4053), .ICO(DP_OP_168J30_122_4811_n4051), .CO(
DP_OP_168J30_122_4811_n4052) );
CMPR42X1TS DP_OP_168J30_122_4811_U3258 ( .A(DP_OP_168J30_122_4811_n4397),
.B(DP_OP_168J30_122_4811_n4050), .C(DP_OP_168J30_122_4811_n4057), .D(
DP_OP_168J30_122_4811_n4423), .ICI(DP_OP_168J30_122_4811_n4058), .S(
DP_OP_168J30_122_4811_n4048), .ICO(DP_OP_168J30_122_4811_n4046), .CO(
DP_OP_168J30_122_4811_n4047) );
CMPR42X1TS DP_OP_168J30_122_4811_U3257 ( .A(DP_OP_168J30_122_4811_n4048),
.B(DP_OP_168J30_122_4811_n4449), .C(DP_OP_168J30_122_4811_n4054), .D(
DP_OP_168J30_122_4811_n4475), .ICI(DP_OP_168J30_122_4811_n4055), .S(
DP_OP_168J30_122_4811_n4045), .ICO(DP_OP_168J30_122_4811_n4043), .CO(
DP_OP_168J30_122_4811_n4044) );
CMPR42X1TS DP_OP_168J30_122_4811_U3256 ( .A(DP_OP_168J30_122_4811_n4045),
.B(DP_OP_168J30_122_4811_n4501), .C(DP_OP_168J30_122_4811_n4051), .D(
DP_OP_168J30_122_4811_n4527), .ICI(DP_OP_168J30_122_4811_n4052), .S(
DP_OP_168J30_122_4811_n4042), .ICO(DP_OP_168J30_122_4811_n4040), .CO(
DP_OP_168J30_122_4811_n4041) );
CMPR42X1TS DP_OP_168J30_122_4811_U3254 ( .A(DP_OP_168J30_122_4811_n4396),
.B(DP_OP_168J30_122_4811_n4039), .C(DP_OP_168J30_122_4811_n4046), .D(
DP_OP_168J30_122_4811_n4422), .ICI(DP_OP_168J30_122_4811_n4047), .S(
DP_OP_168J30_122_4811_n4037), .ICO(DP_OP_168J30_122_4811_n4035), .CO(
DP_OP_168J30_122_4811_n4036) );
CMPR42X1TS DP_OP_168J30_122_4811_U3253 ( .A(DP_OP_168J30_122_4811_n4037),
.B(DP_OP_168J30_122_4811_n4448), .C(DP_OP_168J30_122_4811_n4043), .D(
DP_OP_168J30_122_4811_n4474), .ICI(DP_OP_168J30_122_4811_n4044), .S(
DP_OP_168J30_122_4811_n4034), .ICO(DP_OP_168J30_122_4811_n4032), .CO(
DP_OP_168J30_122_4811_n4033) );
CMPR42X1TS DP_OP_168J30_122_4811_U3250 ( .A(DP_OP_168J30_122_4811_n4028),
.B(DP_OP_168J30_122_4811_n4038), .C(DP_OP_168J30_122_4811_n4395), .D(
DP_OP_168J30_122_4811_n4035), .ICI(DP_OP_168J30_122_4811_n4421), .S(
DP_OP_168J30_122_4811_n4026), .ICO(DP_OP_168J30_122_4811_n4024), .CO(
DP_OP_168J30_122_4811_n4025) );
CMPR42X1TS DP_OP_168J30_122_4811_U3249 ( .A(DP_OP_168J30_122_4811_n4026),
.B(DP_OP_168J30_122_4811_n4036), .C(DP_OP_168J30_122_4811_n4447), .D(
DP_OP_168J30_122_4811_n4032), .ICI(DP_OP_168J30_122_4811_n4473), .S(
DP_OP_168J30_122_4811_n4023), .ICO(DP_OP_168J30_122_4811_n4021), .CO(
DP_OP_168J30_122_4811_n4022) );
CMPR42X1TS DP_OP_168J30_122_4811_U3248 ( .A(DP_OP_168J30_122_4811_n4033),
.B(DP_OP_168J30_122_4811_n4023), .C(DP_OP_168J30_122_4811_n4029), .D(
DP_OP_168J30_122_4811_n4499), .ICI(DP_OP_168J30_122_4811_n4030), .S(
DP_OP_168J30_122_4811_n4020), .ICO(DP_OP_168J30_122_4811_n4018), .CO(
DP_OP_168J30_122_4811_n4019) );
CMPR42X1TS DP_OP_168J30_122_4811_U3246 ( .A(DP_OP_168J30_122_4811_n4027),
.B(DP_OP_168J30_122_4811_n4017), .C(DP_OP_168J30_122_4811_n4024), .D(
DP_OP_168J30_122_4811_n4394), .ICI(DP_OP_168J30_122_4811_n4025), .S(
DP_OP_168J30_122_4811_n4015), .ICO(DP_OP_168J30_122_4811_n4013), .CO(
DP_OP_168J30_122_4811_n4014) );
CMPR42X1TS DP_OP_168J30_122_4811_U3245 ( .A(DP_OP_168J30_122_4811_n4420),
.B(DP_OP_168J30_122_4811_n4015), .C(DP_OP_168J30_122_4811_n4021), .D(
DP_OP_168J30_122_4811_n4446), .ICI(DP_OP_168J30_122_4811_n4022), .S(
DP_OP_168J30_122_4811_n4012), .ICO(DP_OP_168J30_122_4811_n4010), .CO(
DP_OP_168J30_122_4811_n4011) );
CMPR42X1TS DP_OP_168J30_122_4811_U3242 ( .A(DP_OP_168J30_122_4811_n4016),
.B(DP_OP_168J30_122_4811_n4006), .C(DP_OP_168J30_122_4811_n4013), .D(
DP_OP_168J30_122_4811_n4393), .ICI(DP_OP_168J30_122_4811_n4014), .S(
DP_OP_168J30_122_4811_n4004), .ICO(DP_OP_168J30_122_4811_n4002), .CO(
DP_OP_168J30_122_4811_n4003) );
CMPR42X1TS DP_OP_168J30_122_4811_U3241 ( .A(DP_OP_168J30_122_4811_n4419),
.B(DP_OP_168J30_122_4811_n4004), .C(DP_OP_168J30_122_4811_n4010), .D(
DP_OP_168J30_122_4811_n4445), .ICI(DP_OP_168J30_122_4811_n4011), .S(
DP_OP_168J30_122_4811_n4001), .ICO(DP_OP_168J30_122_4811_n3999), .CO(
DP_OP_168J30_122_4811_n4000) );
CMPR42X1TS DP_OP_168J30_122_4811_U3240 ( .A(DP_OP_168J30_122_4811_n4471),
.B(DP_OP_168J30_122_4811_n4001), .C(DP_OP_168J30_122_4811_n4007), .D(
DP_OP_168J30_122_4811_n4497), .ICI(DP_OP_168J30_122_4811_n4523), .S(
DP_OP_168J30_122_4811_n3998), .ICO(DP_OP_168J30_122_4811_n3996), .CO(
DP_OP_168J30_122_4811_n3997) );
CMPR42X1TS DP_OP_168J30_122_4811_U3238 ( .A(DP_OP_168J30_122_4811_n3995),
.B(DP_OP_168J30_122_4811_n4366), .C(DP_OP_168J30_122_4811_n4005), .D(
DP_OP_168J30_122_4811_n4002), .ICI(DP_OP_168J30_122_4811_n4392), .S(
DP_OP_168J30_122_4811_n3993), .ICO(DP_OP_168J30_122_4811_n3991), .CO(
DP_OP_168J30_122_4811_n3992) );
CMPR42X1TS DP_OP_168J30_122_4811_U3237 ( .A(DP_OP_168J30_122_4811_n3993),
.B(DP_OP_168J30_122_4811_n4003), .C(DP_OP_168J30_122_4811_n4418), .D(
DP_OP_168J30_122_4811_n3999), .ICI(DP_OP_168J30_122_4811_n4444), .S(
DP_OP_168J30_122_4811_n3990), .ICO(DP_OP_168J30_122_4811_n3988), .CO(
DP_OP_168J30_122_4811_n3989) );
CMPR42X1TS DP_OP_168J30_122_4811_U3236 ( .A(DP_OP_168J30_122_4811_n3990),
.B(DP_OP_168J30_122_4811_n4000), .C(DP_OP_168J30_122_4811_n4470), .D(
DP_OP_168J30_122_4811_n3996), .ICI(DP_OP_168J30_122_4811_n3997), .S(
DP_OP_168J30_122_4811_n3987), .ICO(DP_OP_168J30_122_4811_n3985), .CO(
DP_OP_168J30_122_4811_n3986) );
CMPR42X1TS DP_OP_168J30_122_4811_U3234 ( .A(DP_OP_168J30_122_4811_n3994),
.B(DP_OP_168J30_122_4811_n3984), .C(DP_OP_168J30_122_4811_n3991), .D(
DP_OP_168J30_122_4811_n4365), .ICI(DP_OP_168J30_122_4811_n4391), .S(
DP_OP_168J30_122_4811_n3983), .ICO(DP_OP_168J30_122_4811_n3981), .CO(
DP_OP_168J30_122_4811_n3982) );
CMPR42X1TS DP_OP_168J30_122_4811_U3233 ( .A(DP_OP_168J30_122_4811_n3992),
.B(DP_OP_168J30_122_4811_n3983), .C(DP_OP_168J30_122_4811_n3988), .D(
DP_OP_168J30_122_4811_n4417), .ICI(DP_OP_168J30_122_4811_n4443), .S(
DP_OP_168J30_122_4811_n3980), .ICO(DP_OP_168J30_122_4811_n3978), .CO(
DP_OP_168J30_122_4811_n3979) );
CMPR42X1TS DP_OP_168J30_122_4811_U3232 ( .A(DP_OP_168J30_122_4811_n3989),
.B(DP_OP_168J30_122_4811_n3980), .C(DP_OP_168J30_122_4811_n3985), .D(
DP_OP_168J30_122_4811_n4469), .ICI(DP_OP_168J30_122_4811_n4495), .S(
DP_OP_168J30_122_4811_n3977), .ICO(DP_OP_168J30_122_4811_n3975), .CO(
DP_OP_168J30_122_4811_n3976) );
CMPR42X1TS DP_OP_168J30_122_4811_U3230 ( .A(DP_OP_168J30_122_4811_n3984),
.B(DP_OP_168J30_122_4811_n4339), .C(DP_OP_168J30_122_4811_n3981), .D(
DP_OP_168J30_122_4811_n4364), .ICI(DP_OP_168J30_122_4811_n3982), .S(
DP_OP_168J30_122_4811_n3972), .ICO(DP_OP_168J30_122_4811_n3970), .CO(
DP_OP_168J30_122_4811_n3971) );
CMPR42X1TS DP_OP_168J30_122_4811_U3229 ( .A(DP_OP_168J30_122_4811_n4390),
.B(DP_OP_168J30_122_4811_n3972), .C(DP_OP_168J30_122_4811_n3978), .D(
DP_OP_168J30_122_4811_n4416), .ICI(DP_OP_168J30_122_4811_n3979), .S(
DP_OP_168J30_122_4811_n3969), .ICO(DP_OP_168J30_122_4811_n3967), .CO(
DP_OP_168J30_122_4811_n3968) );
CMPR42X1TS DP_OP_168J30_122_4811_U3228 ( .A(DP_OP_168J30_122_4811_n4442),
.B(DP_OP_168J30_122_4811_n3969), .C(DP_OP_168J30_122_4811_n3975), .D(
DP_OP_168J30_122_4811_n4468), .ICI(DP_OP_168J30_122_4811_n4494), .S(
DP_OP_168J30_122_4811_n3966), .ICO(DP_OP_168J30_122_4811_n3964), .CO(
DP_OP_168J30_122_4811_n3965) );
CMPR42X1TS DP_OP_168J30_122_4811_U3227 ( .A(n760), .B(
DP_OP_168J30_122_4811_n3973), .C(DP_OP_168J30_122_4811_n4338), .D(
DP_OP_168J30_122_4811_n3970), .ICI(DP_OP_168J30_122_4811_n4363), .S(
DP_OP_168J30_122_4811_n3963), .ICO(DP_OP_168J30_122_4811_n3945), .CO(
DP_OP_168J30_122_4811_n3962) );
CMPR42X1TS DP_OP_168J30_122_4811_U3226 ( .A(DP_OP_168J30_122_4811_n3963),
.B(DP_OP_168J30_122_4811_n3971), .C(DP_OP_168J30_122_4811_n4389), .D(
DP_OP_168J30_122_4811_n3967), .ICI(DP_OP_168J30_122_4811_n4415), .S(
DP_OP_168J30_122_4811_n3961), .ICO(DP_OP_168J30_122_4811_n3959), .CO(
DP_OP_168J30_122_4811_n3960) );
CMPR42X1TS DP_OP_168J30_122_4811_U3225 ( .A(DP_OP_168J30_122_4811_n3961),
.B(DP_OP_168J30_122_4811_n3968), .C(DP_OP_168J30_122_4811_n4441), .D(
DP_OP_168J30_122_4811_n3964), .ICI(DP_OP_168J30_122_4811_n3965), .S(
DP_OP_168J30_122_4811_n3958), .ICO(DP_OP_168J30_122_4811_n3956), .CO(
DP_OP_168J30_122_4811_n3957) );
CMPR42X1TS DP_OP_168J30_122_4811_U3222 ( .A(DP_OP_168J30_122_4811_n3962),
.B(DP_OP_168J30_122_4811_n3954), .C(DP_OP_168J30_122_4811_n3959), .D(
DP_OP_168J30_122_4811_n4388), .ICI(DP_OP_168J30_122_4811_n4414), .S(
DP_OP_168J30_122_4811_n3952), .ICO(DP_OP_168J30_122_4811_n3950), .CO(
DP_OP_168J30_122_4811_n3951) );
CMPR42X1TS DP_OP_168J30_122_4811_U3218 ( .A(DP_OP_168J30_122_4811_n3953),
.B(DP_OP_168J30_122_4811_n3944), .C(DP_OP_168J30_122_4811_n3950), .D(
DP_OP_168J30_122_4811_n4387), .ICI(DP_OP_168J30_122_4811_n3951), .S(
DP_OP_168J30_122_4811_n3942), .ICO(DP_OP_168J30_122_4811_n3940), .CO(
DP_OP_168J30_122_4811_n3941) );
CMPR42X1TS DP_OP_168J30_122_4811_U3215 ( .A(DP_OP_168J30_122_4811_n3936),
.B(DP_OP_168J30_122_4811_n3943), .C(DP_OP_168J30_122_4811_n4360), .D(
DP_OP_168J30_122_4811_n3940), .ICI(DP_OP_168J30_122_4811_n4386), .S(
DP_OP_168J30_122_4811_n3934), .ICO(DP_OP_168J30_122_4811_n3932), .CO(
DP_OP_168J30_122_4811_n3933) );
CMPR42X1TS DP_OP_168J30_122_4811_U3214 ( .A(DP_OP_168J30_122_4811_n3934),
.B(DP_OP_168J30_122_4811_n3941), .C(DP_OP_168J30_122_4811_n4412), .D(
DP_OP_168J30_122_4811_n3937), .ICI(DP_OP_168J30_122_4811_n3938), .S(
DP_OP_168J30_122_4811_n3931), .ICO(DP_OP_168J30_122_4811_n3929), .CO(
DP_OP_168J30_122_4811_n3930) );
CMPR42X1TS DP_OP_168J30_122_4811_U3212 ( .A(DP_OP_168J30_122_4811_n3935),
.B(DP_OP_168J30_122_4811_n3928), .C(DP_OP_168J30_122_4811_n3932), .D(
DP_OP_168J30_122_4811_n4359), .ICI(DP_OP_168J30_122_4811_n4385), .S(
DP_OP_168J30_122_4811_n3927), .ICO(DP_OP_168J30_122_4811_n3925), .CO(
DP_OP_168J30_122_4811_n3926) );
CMPR42X1TS DP_OP_168J30_122_4811_U3211 ( .A(DP_OP_168J30_122_4811_n3933),
.B(DP_OP_168J30_122_4811_n3927), .C(DP_OP_168J30_122_4811_n3929), .D(
DP_OP_168J30_122_4811_n4411), .ICI(DP_OP_168J30_122_4811_n4437), .S(
DP_OP_168J30_122_4811_n3924), .ICO(DP_OP_168J30_122_4811_n3922), .CO(
DP_OP_168J30_122_4811_n3923) );
CMPR42X1TS DP_OP_168J30_122_4811_U3209 ( .A(DP_OP_168J30_122_4811_n3928),
.B(DP_OP_168J30_122_4811_n4334), .C(DP_OP_168J30_122_4811_n3925), .D(
DP_OP_168J30_122_4811_n4358), .ICI(DP_OP_168J30_122_4811_n3926), .S(
DP_OP_168J30_122_4811_n3919), .ICO(DP_OP_168J30_122_4811_n3917), .CO(
DP_OP_168J30_122_4811_n3918) );
CMPR42X1TS DP_OP_168J30_122_4811_U3208 ( .A(DP_OP_168J30_122_4811_n4384),
.B(DP_OP_168J30_122_4811_n3919), .C(DP_OP_168J30_122_4811_n3922), .D(
DP_OP_168J30_122_4811_n4410), .ICI(DP_OP_168J30_122_4811_n4436), .S(
DP_OP_168J30_122_4811_n3916), .ICO(DP_OP_168J30_122_4811_n3914), .CO(
DP_OP_168J30_122_4811_n3915) );
CMPR42X1TS DP_OP_168J30_122_4811_U3207 ( .A(n891), .B(
DP_OP_168J30_122_4811_n3920), .C(DP_OP_168J30_122_4811_n4333), .D(
DP_OP_168J30_122_4811_n3917), .ICI(DP_OP_168J30_122_4811_n4357), .S(
DP_OP_168J30_122_4811_n3913), .ICO(DP_OP_168J30_122_4811_n3901), .CO(
DP_OP_168J30_122_4811_n3912) );
CMPR42X1TS DP_OP_168J30_122_4811_U3206 ( .A(DP_OP_168J30_122_4811_n3913),
.B(DP_OP_168J30_122_4811_n3918), .C(DP_OP_168J30_122_4811_n4383), .D(
DP_OP_168J30_122_4811_n3914), .ICI(DP_OP_168J30_122_4811_n3915), .S(
DP_OP_168J30_122_4811_n3911), .ICO(DP_OP_168J30_122_4811_n3909), .CO(
DP_OP_168J30_122_4811_n3910) );
CMPR42X1TS DP_OP_168J30_122_4811_U3203 ( .A(DP_OP_168J30_122_4811_n3912),
.B(DP_OP_168J30_122_4811_n3907), .C(DP_OP_168J30_122_4811_n3909), .D(
DP_OP_168J30_122_4811_n4382), .ICI(DP_OP_168J30_122_4811_n4408), .S(
DP_OP_168J30_122_4811_n3905), .ICO(DP_OP_168J30_122_4811_n3903), .CO(
DP_OP_168J30_122_4811_n3904) );
CMPR42X1TS DP_OP_168J30_122_4811_U3200 ( .A(DP_OP_168J30_122_4811_n4355),
.B(DP_OP_168J30_122_4811_n3900), .C(DP_OP_168J30_122_4811_n3903), .D(
DP_OP_168J30_122_4811_n4381), .ICI(DP_OP_168J30_122_4811_n4407), .S(
DP_OP_168J30_122_4811_n3898), .ICO(DP_OP_168J30_122_4811_n3896), .CO(
DP_OP_168J30_122_4811_n3897) );
CMPR42X1TS DP_OP_168J30_122_4811_U3198 ( .A(DP_OP_168J30_122_4811_n3895),
.B(DP_OP_168J30_122_4811_n3899), .C(DP_OP_168J30_122_4811_n4354), .D(
DP_OP_168J30_122_4811_n3896), .ICI(DP_OP_168J30_122_4811_n3897), .S(
DP_OP_168J30_122_4811_n3894), .ICO(DP_OP_168J30_122_4811_n3892), .CO(
DP_OP_168J30_122_4811_n3893) );
CMPR42X1TS DP_OP_168J30_122_4811_U3196 ( .A(DP_OP_168J30_122_4811_n4329),
.B(DP_OP_168J30_122_4811_n3891), .C(DP_OP_168J30_122_4811_n3892), .D(
DP_OP_168J30_122_4811_n4353), .ICI(DP_OP_168J30_122_4811_n4379), .S(
DP_OP_168J30_122_4811_n3890), .ICO(DP_OP_168J30_122_4811_n3888), .CO(
DP_OP_168J30_122_4811_n3889) );
CMPR42X1TS DP_OP_168J30_122_4811_U3194 ( .A(DP_OP_168J30_122_4811_n3891),
.B(DP_OP_168J30_122_4811_n4328), .C(DP_OP_168J30_122_4811_n3888), .D(
DP_OP_168J30_122_4811_n4352), .ICI(DP_OP_168J30_122_4811_n4378), .S(
DP_OP_168J30_122_4811_n3885), .ICO(DP_OP_168J30_122_4811_n3883), .CO(
DP_OP_168J30_122_4811_n3884) );
CMPR42X1TS DP_OP_168J30_122_4811_U1892 ( .A(DP_OP_168J30_122_4811_n2495),
.B(DP_OP_168J30_122_4811_n2817), .C(DP_OP_168J30_122_4811_n2504), .D(
DP_OP_168J30_122_4811_n2844), .ICI(DP_OP_168J30_122_4811_n2502), .S(
DP_OP_168J30_122_4811_n2493), .ICO(DP_OP_168J30_122_4811_n2491), .CO(
DP_OP_168J30_122_4811_n2492) );
CMPR42X1TS DP_OP_168J30_122_4811_U1866 ( .A(DP_OP_168J30_122_4811_n2630),
.B(DP_OP_168J30_122_4811_n2757), .C(DP_OP_168J30_122_4811_n2435), .D(
DP_OP_168J30_122_4811_n2784), .ICI(DP_OP_168J30_122_4811_n2433), .S(
DP_OP_168J30_122_4811_n2423), .ICO(DP_OP_168J30_122_4811_n2421), .CO(
DP_OP_168J30_122_4811_n2422) );
CMPR42X1TS DP_OP_168J30_122_4811_U1862 ( .A(DP_OP_168J30_122_4811_n2629),
.B(DP_OP_168J30_122_4811_n2756), .C(DP_OP_168J30_122_4811_n2421), .D(
DP_OP_168J30_122_4811_n2783), .ICI(DP_OP_168J30_122_4811_n2422), .S(
DP_OP_168J30_122_4811_n2411), .ICO(DP_OP_168J30_122_4811_n2409), .CO(
DP_OP_168J30_122_4811_n2410) );
CMPR42X1TS DP_OP_168J30_122_4811_U1860 ( .A(DP_OP_168J30_122_4811_n2408),
.B(DP_OP_168J30_122_4811_n2864), .C(DP_OP_168J30_122_4811_n2415), .D(
DP_OP_168J30_122_4811_n2891), .ICI(DP_OP_168J30_122_4811_n2416), .S(
DP_OP_168J30_122_4811_n2405), .ICO(DP_OP_168J30_122_4811_n2403), .CO(
DP_OP_168J30_122_4811_n2404) );
CMPR42X1TS DP_OP_168J30_122_4811_U1858 ( .A(DP_OP_168J30_122_4811_n2003),
.B(DP_OP_168J30_122_4811_n2628), .C(DP_OP_168J30_122_4811_n2755), .D(
DP_OP_168J30_122_4811_n2409), .ICI(DP_OP_168J30_122_4811_n2782), .S(
DP_OP_168J30_122_4811_n2399), .ICO(DP_OP_168J30_122_4811_n2397), .CO(
DP_OP_168J30_122_4811_n2398) );
CMPR42X1TS DP_OP_168J30_122_4811_U1857 ( .A(DP_OP_168J30_122_4811_n2399),
.B(DP_OP_168J30_122_4811_n2410), .C(DP_OP_168J30_122_4811_n2809), .D(
DP_OP_168J30_122_4811_n2406), .ICI(DP_OP_168J30_122_4811_n2836), .S(
DP_OP_168J30_122_4811_n2396), .ICO(DP_OP_168J30_122_4811_n2394), .CO(
DP_OP_168J30_122_4811_n2395) );
CMPR42X1TS DP_OP_168J30_122_4811_U1854 ( .A(DP_OP_168J30_122_4811_n2003),
.B(DP_OP_168J30_122_4811_n2627), .C(DP_OP_168J30_122_4811_n2397), .D(
DP_OP_168J30_122_4811_n2754), .ICI(DP_OP_168J30_122_4811_n2398), .S(
DP_OP_168J30_122_4811_n2387), .ICO(DP_OP_168J30_122_4811_n2385), .CO(
DP_OP_168J30_122_4811_n2386) );
CMPR42X1TS DP_OP_168J30_122_4811_U1853 ( .A(DP_OP_168J30_122_4811_n2781),
.B(DP_OP_168J30_122_4811_n2387), .C(DP_OP_168J30_122_4811_n2394), .D(
DP_OP_168J30_122_4811_n2808), .ICI(DP_OP_168J30_122_4811_n2395), .S(
DP_OP_168J30_122_4811_n2384), .ICO(DP_OP_168J30_122_4811_n2382), .CO(
DP_OP_168J30_122_4811_n2383) );
CMPR42X1TS DP_OP_168J30_122_4811_U1850 ( .A(DP_OP_168J30_122_4811_n2003),
.B(DP_OP_168J30_122_4811_n2626), .C(DP_OP_168J30_122_4811_n2385), .D(
DP_OP_168J30_122_4811_n2753), .ICI(DP_OP_168J30_122_4811_n2386), .S(
DP_OP_168J30_122_4811_n2375), .ICO(DP_OP_168J30_122_4811_n2373), .CO(
DP_OP_168J30_122_4811_n2374) );
CMPR42X1TS DP_OP_168J30_122_4811_U1846 ( .A(n758), .B(n879), .C(
DP_OP_168J30_122_4811_n2625), .D(DP_OP_168J30_122_4811_n2373), .ICI(
DP_OP_168J30_122_4811_n2752), .S(DP_OP_168J30_122_4811_n2363), .ICO(
DP_OP_168J30_122_4811_n2361), .CO(DP_OP_168J30_122_4811_n2362) );
CMPR42X1TS DP_OP_168J30_122_4811_U1840 ( .A(DP_OP_168J30_122_4811_n2362),
.B(DP_OP_168J30_122_4811_n2350), .C(DP_OP_168J30_122_4811_n2358), .D(
DP_OP_168J30_122_4811_n2778), .ICI(DP_OP_168J30_122_4811_n2805), .S(
DP_OP_168J30_122_4811_n2348), .ICO(DP_OP_168J30_122_4811_n2346), .CO(
DP_OP_168J30_122_4811_n2347) );
CMPR42X1TS DP_OP_168J30_122_4811_U1839 ( .A(DP_OP_168J30_122_4811_n2359),
.B(DP_OP_168J30_122_4811_n2348), .C(DP_OP_168J30_122_4811_n2355), .D(
DP_OP_168J30_122_4811_n2832), .ICI(DP_OP_168J30_122_4811_n2859), .S(
DP_OP_168J30_122_4811_n2345), .ICO(DP_OP_168J30_122_4811_n2343), .CO(
DP_OP_168J30_122_4811_n2344) );
CMPR42X1TS DP_OP_168J30_122_4811_U1838 ( .A(DP_OP_168J30_122_4811_n2356),
.B(DP_OP_168J30_122_4811_n2345), .C(DP_OP_168J30_122_4811_n2352), .D(
DP_OP_168J30_122_4811_n2886), .ICI(DP_OP_168J30_122_4811_n2913), .S(
DP_OP_168J30_122_4811_n2342), .ICO(DP_OP_168J30_122_4811_n2340), .CO(
DP_OP_168J30_122_4811_n2341) );
CMPR42X1TS DP_OP_168J30_122_4811_U1835 ( .A(DP_OP_168J30_122_4811_n2349),
.B(DP_OP_168J30_122_4811_n2337), .C(DP_OP_168J30_122_4811_n2346), .D(
DP_OP_168J30_122_4811_n2777), .ICI(DP_OP_168J30_122_4811_n2347), .S(
DP_OP_168J30_122_4811_n2335), .ICO(DP_OP_168J30_122_4811_n2333), .CO(
DP_OP_168J30_122_4811_n2334) );
CMPR42X1TS DP_OP_168J30_122_4811_U1834 ( .A(DP_OP_168J30_122_4811_n2804),
.B(DP_OP_168J30_122_4811_n2335), .C(DP_OP_168J30_122_4811_n2343), .D(
DP_OP_168J30_122_4811_n2831), .ICI(DP_OP_168J30_122_4811_n2344), .S(
DP_OP_168J30_122_4811_n2332), .ICO(DP_OP_168J30_122_4811_n2330), .CO(
DP_OP_168J30_122_4811_n2331) );
CMPR42X1TS DP_OP_168J30_122_4811_U1833 ( .A(DP_OP_168J30_122_4811_n2858),
.B(DP_OP_168J30_122_4811_n2332), .C(DP_OP_168J30_122_4811_n2340), .D(
DP_OP_168J30_122_4811_n2885), .ICI(DP_OP_168J30_122_4811_n2912), .S(
DP_OP_168J30_122_4811_n2329), .ICO(DP_OP_168J30_122_4811_n2327), .CO(
DP_OP_168J30_122_4811_n2328) );
CMPR42X1TS DP_OP_168J30_122_4811_U1831 ( .A(DP_OP_168J30_122_4811_n2326),
.B(DP_OP_168J30_122_4811_n2749), .C(DP_OP_168J30_122_4811_n2336), .D(
DP_OP_168J30_122_4811_n2333), .ICI(DP_OP_168J30_122_4811_n2776), .S(
DP_OP_168J30_122_4811_n2324), .ICO(DP_OP_168J30_122_4811_n2322), .CO(
DP_OP_168J30_122_4811_n2323) );
CMPR42X1TS DP_OP_168J30_122_4811_U1830 ( .A(DP_OP_168J30_122_4811_n2324),
.B(DP_OP_168J30_122_4811_n2334), .C(DP_OP_168J30_122_4811_n2803), .D(
DP_OP_168J30_122_4811_n2330), .ICI(DP_OP_168J30_122_4811_n2830), .S(
DP_OP_168J30_122_4811_n2321), .ICO(DP_OP_168J30_122_4811_n2319), .CO(
DP_OP_168J30_122_4811_n2320) );
CMPR42X1TS DP_OP_168J30_122_4811_U1829 ( .A(DP_OP_168J30_122_4811_n2321),
.B(DP_OP_168J30_122_4811_n2331), .C(DP_OP_168J30_122_4811_n2857), .D(
DP_OP_168J30_122_4811_n2327), .ICI(DP_OP_168J30_122_4811_n2884), .S(
DP_OP_168J30_122_4811_n2318), .ICO(DP_OP_168J30_122_4811_n2316), .CO(
DP_OP_168J30_122_4811_n2317) );
CMPR42X1TS DP_OP_168J30_122_4811_U1827 ( .A(DP_OP_168J30_122_4811_n2315),
.B(DP_OP_168J30_122_4811_n2325), .C(DP_OP_168J30_122_4811_n2322), .D(
DP_OP_168J30_122_4811_n2748), .ICI(DP_OP_168J30_122_4811_n2775), .S(
DP_OP_168J30_122_4811_n2313), .ICO(DP_OP_168J30_122_4811_n2311), .CO(
DP_OP_168J30_122_4811_n2312) );
CMPR42X1TS DP_OP_168J30_122_4811_U1826 ( .A(DP_OP_168J30_122_4811_n2323),
.B(DP_OP_168J30_122_4811_n2313), .C(DP_OP_168J30_122_4811_n2319), .D(
DP_OP_168J30_122_4811_n2802), .ICI(DP_OP_168J30_122_4811_n2829), .S(
DP_OP_168J30_122_4811_n2310), .ICO(DP_OP_168J30_122_4811_n2308), .CO(
DP_OP_168J30_122_4811_n2309) );
CMPR42X1TS DP_OP_168J30_122_4811_U1825 ( .A(DP_OP_168J30_122_4811_n2320),
.B(DP_OP_168J30_122_4811_n2310), .C(DP_OP_168J30_122_4811_n2316), .D(
DP_OP_168J30_122_4811_n2856), .ICI(DP_OP_168J30_122_4811_n2883), .S(
DP_OP_168J30_122_4811_n2307), .ICO(DP_OP_168J30_122_4811_n2305), .CO(
DP_OP_168J30_122_4811_n2306) );
CMPR42X1TS DP_OP_168J30_122_4811_U1823 ( .A(DP_OP_168J30_122_4811_n2621),
.B(DP_OP_168J30_122_4811_n2304), .C(DP_OP_168J30_122_4811_n2311), .D(
DP_OP_168J30_122_4811_n2747), .ICI(DP_OP_168J30_122_4811_n2312), .S(
DP_OP_168J30_122_4811_n2302), .ICO(DP_OP_168J30_122_4811_n2300), .CO(
DP_OP_168J30_122_4811_n2301) );
CMPR42X1TS DP_OP_168J30_122_4811_U1822 ( .A(DP_OP_168J30_122_4811_n2774),
.B(DP_OP_168J30_122_4811_n2302), .C(DP_OP_168J30_122_4811_n2308), .D(
DP_OP_168J30_122_4811_n2801), .ICI(DP_OP_168J30_122_4811_n2309), .S(
DP_OP_168J30_122_4811_n2299), .ICO(DP_OP_168J30_122_4811_n2297), .CO(
DP_OP_168J30_122_4811_n2298) );
CMPR42X1TS DP_OP_168J30_122_4811_U1820 ( .A(n856), .B(
DP_OP_168J30_122_4811_n2619), .C(DP_OP_168J30_122_4811_n2620), .D(
DP_OP_168J30_122_4811_n2300), .ICI(DP_OP_168J30_122_4811_n2746), .S(
DP_OP_168J30_122_4811_n2293), .ICO(DP_OP_168J30_122_4811_n2291), .CO(
DP_OP_168J30_122_4811_n2292) );
CMPR42X1TS DP_OP_168J30_122_4811_U1819 ( .A(DP_OP_168J30_122_4811_n2293),
.B(DP_OP_168J30_122_4811_n2301), .C(DP_OP_168J30_122_4811_n2773), .D(
DP_OP_168J30_122_4811_n2297), .ICI(DP_OP_168J30_122_4811_n2800), .S(
DP_OP_168J30_122_4811_n2290), .ICO(DP_OP_168J30_122_4811_n2288), .CO(
DP_OP_168J30_122_4811_n2289) );
CMPR42X1TS DP_OP_168J30_122_4811_U1815 ( .A(DP_OP_168J30_122_4811_n2292),
.B(DP_OP_168J30_122_4811_n2283), .C(DP_OP_168J30_122_4811_n2288), .D(
DP_OP_168J30_122_4811_n2772), .ICI(DP_OP_168J30_122_4811_n2799), .S(
DP_OP_168J30_122_4811_n2281), .ICO(DP_OP_168J30_122_4811_n2279), .CO(
DP_OP_168J30_122_4811_n2280) );
CMPR42X1TS DP_OP_168J30_122_4811_U1814 ( .A(DP_OP_168J30_122_4811_n2289),
.B(DP_OP_168J30_122_4811_n2281), .C(DP_OP_168J30_122_4811_n2285), .D(
DP_OP_168J30_122_4811_n2826), .ICI(DP_OP_168J30_122_4811_n2853), .S(
DP_OP_168J30_122_4811_n2278), .ICO(DP_OP_168J30_122_4811_n2276), .CO(
DP_OP_168J30_122_4811_n2277) );
CMPR42X1TS DP_OP_168J30_122_4811_U1811 ( .A(DP_OP_168J30_122_4811_n2282),
.B(DP_OP_168J30_122_4811_n2273), .C(DP_OP_168J30_122_4811_n2279), .D(
DP_OP_168J30_122_4811_n2771), .ICI(DP_OP_168J30_122_4811_n2280), .S(
DP_OP_168J30_122_4811_n2271), .ICO(DP_OP_168J30_122_4811_n2269), .CO(
DP_OP_168J30_122_4811_n2270) );
CMPR42X1TS DP_OP_168J30_122_4811_U1810 ( .A(DP_OP_168J30_122_4811_n2798),
.B(DP_OP_168J30_122_4811_n2271), .C(DP_OP_168J30_122_4811_n2276), .D(
DP_OP_168J30_122_4811_n2825), .ICI(DP_OP_168J30_122_4811_n2852), .S(
DP_OP_168J30_122_4811_n2268), .ICO(DP_OP_168J30_122_4811_n2266), .CO(
DP_OP_168J30_122_4811_n2267) );
CMPR42X1TS DP_OP_168J30_122_4811_U1808 ( .A(DP_OP_168J30_122_4811_n2265),
.B(DP_OP_168J30_122_4811_n2272), .C(DP_OP_168J30_122_4811_n2743), .D(
DP_OP_168J30_122_4811_n2269), .ICI(DP_OP_168J30_122_4811_n2770), .S(
DP_OP_168J30_122_4811_n2263), .ICO(DP_OP_168J30_122_4811_n2261), .CO(
DP_OP_168J30_122_4811_n2262) );
CMPR42X1TS DP_OP_168J30_122_4811_U1807 ( .A(DP_OP_168J30_122_4811_n2263),
.B(DP_OP_168J30_122_4811_n2270), .C(DP_OP_168J30_122_4811_n2797), .D(
DP_OP_168J30_122_4811_n2266), .ICI(DP_OP_168J30_122_4811_n2824), .S(
DP_OP_168J30_122_4811_n2260), .ICO(DP_OP_168J30_122_4811_n2258), .CO(
DP_OP_168J30_122_4811_n2259) );
CMPR42X1TS DP_OP_168J30_122_4811_U1805 ( .A(DP_OP_168J30_122_4811_n2257),
.B(DP_OP_168J30_122_4811_n2264), .C(DP_OP_168J30_122_4811_n2261), .D(
DP_OP_168J30_122_4811_n2742), .ICI(DP_OP_168J30_122_4811_n2769), .S(
DP_OP_168J30_122_4811_n2255), .ICO(DP_OP_168J30_122_4811_n2253), .CO(
DP_OP_168J30_122_4811_n2254) );
CMPR42X1TS DP_OP_168J30_122_4811_U1804 ( .A(DP_OP_168J30_122_4811_n2262),
.B(DP_OP_168J30_122_4811_n2255), .C(DP_OP_168J30_122_4811_n2258), .D(
DP_OP_168J30_122_4811_n2796), .ICI(DP_OP_168J30_122_4811_n2823), .S(
DP_OP_168J30_122_4811_n2252), .ICO(DP_OP_168J30_122_4811_n2250), .CO(
DP_OP_168J30_122_4811_n2251) );
CMPR42X1TS DP_OP_168J30_122_4811_U1802 ( .A(DP_OP_168J30_122_4811_n2615),
.B(DP_OP_168J30_122_4811_n2249), .C(DP_OP_168J30_122_4811_n2253), .D(
DP_OP_168J30_122_4811_n2741), .ICI(DP_OP_168J30_122_4811_n2254), .S(
DP_OP_168J30_122_4811_n2247), .ICO(DP_OP_168J30_122_4811_n2245), .CO(
DP_OP_168J30_122_4811_n2246) );
CMPR42X1TS DP_OP_168J30_122_4811_U1801 ( .A(DP_OP_168J30_122_4811_n2768),
.B(DP_OP_168J30_122_4811_n2247), .C(DP_OP_168J30_122_4811_n2250), .D(
DP_OP_168J30_122_4811_n2795), .ICI(DP_OP_168J30_122_4811_n2822), .S(
DP_OP_168J30_122_4811_n2244), .ICO(DP_OP_168J30_122_4811_n2242), .CO(
DP_OP_168J30_122_4811_n2243) );
CMPR42X1TS DP_OP_168J30_122_4811_U1800 ( .A(n861), .B(
DP_OP_168J30_122_4811_n2614), .C(DP_OP_168J30_122_4811_n2613), .D(
DP_OP_168J30_122_4811_n2245), .ICI(DP_OP_168J30_122_4811_n2740), .S(
DP_OP_168J30_122_4811_n2241), .ICO(DP_OP_168J30_122_4811_n2239), .CO(
DP_OP_168J30_122_4811_n2240) );
CMPR42X1TS DP_OP_168J30_122_4811_U1799 ( .A(DP_OP_168J30_122_4811_n2241),
.B(DP_OP_168J30_122_4811_n2246), .C(DP_OP_168J30_122_4811_n2767), .D(
DP_OP_168J30_122_4811_n2242), .ICI(DP_OP_168J30_122_4811_n2794), .S(
DP_OP_168J30_122_4811_n2238), .ICO(DP_OP_168J30_122_4811_n2236), .CO(
DP_OP_168J30_122_4811_n2237) );
CMPR42X1TS DP_OP_168J30_122_4811_U1796 ( .A(DP_OP_168J30_122_4811_n2240),
.B(DP_OP_168J30_122_4811_n2234), .C(DP_OP_168J30_122_4811_n2236), .D(
DP_OP_168J30_122_4811_n2766), .ICI(DP_OP_168J30_122_4811_n2793), .S(
DP_OP_168J30_122_4811_n2232), .ICO(DP_OP_168J30_122_4811_n2230), .CO(
DP_OP_168J30_122_4811_n2231) );
CMPR42X1TS DP_OP_168J30_122_4811_U1793 ( .A(DP_OP_168J30_122_4811_n2738),
.B(DP_OP_168J30_122_4811_n2227), .C(DP_OP_168J30_122_4811_n2230), .D(
DP_OP_168J30_122_4811_n2765), .ICI(DP_OP_168J30_122_4811_n2792), .S(
DP_OP_168J30_122_4811_n2225), .ICO(DP_OP_168J30_122_4811_n2223), .CO(
DP_OP_168J30_122_4811_n2224) );
CMPR42X1TS DP_OP_168J30_122_4811_U1791 ( .A(DP_OP_168J30_122_4811_n2222),
.B(DP_OP_168J30_122_4811_n2226), .C(DP_OP_168J30_122_4811_n2737), .D(
DP_OP_168J30_122_4811_n2223), .ICI(DP_OP_168J30_122_4811_n2764), .S(
DP_OP_168J30_122_4811_n2220), .ICO(DP_OP_168J30_122_4811_n2218), .CO(
DP_OP_168J30_122_4811_n2219) );
CMPR42X1TS DP_OP_168J30_122_4811_U1789 ( .A(DP_OP_168J30_122_4811_n2217),
.B(DP_OP_168J30_122_4811_n2221), .C(DP_OP_168J30_122_4811_n2218), .D(
DP_OP_168J30_122_4811_n2736), .ICI(DP_OP_168J30_122_4811_n2763), .S(
DP_OP_168J30_122_4811_n2216), .ICO(DP_OP_168J30_122_4811_n2214), .CO(
DP_OP_168J30_122_4811_n2215) );
CMPR42X1TS DP_OP_168J30_122_4811_U1787 ( .A(DP_OP_168J30_122_4811_n2608),
.B(DP_OP_168J30_122_4811_n2217), .C(DP_OP_168J30_122_4811_n2214), .D(
DP_OP_168J30_122_4811_n2735), .ICI(DP_OP_168J30_122_4811_n2762), .S(
DP_OP_168J30_122_4811_n2211), .ICO(DP_OP_168J30_122_4811_n2209), .CO(
DP_OP_168J30_122_4811_n2210) );
CMPR42X1TS DP_OP_168J30_122_4811_U1786 ( .A(n853), .B(
DP_OP_168J30_122_4811_n2609), .C(DP_OP_168J30_122_4811_n2607), .D(
DP_OP_168J30_122_4811_n2209), .ICI(DP_OP_168J30_122_4811_n2734), .S(
DP_OP_168J30_122_4811_n2208), .ICO(DP_OP_168J30_122_4811_n2206), .CO(
DP_OP_168J30_122_4811_n2207) );
CMPR42X1TS DP_OP_168J30_122_4811_U407 ( .A(DP_OP_168J30_122_4811_n817), .B(
DP_OP_168J30_122_4811_n1992), .C(DP_OP_168J30_122_4811_n755), .D(
DP_OP_168J30_122_4811_n1209), .ICI(DP_OP_168J30_122_4811_n754), .S(
DP_OP_168J30_122_4811_n752), .ICO(DP_OP_168J30_122_4811_n750), .CO(
DP_OP_168J30_122_4811_n751) );
CMPR42X1TS DP_OP_168J30_122_4811_U402 ( .A(DP_OP_168J30_122_4811_n745), .B(
DP_OP_168J30_122_4811_n815), .C(DP_OP_168J30_122_4811_n744), .D(
DP_OP_168J30_122_4811_n742), .ICI(DP_OP_168J30_122_4811_n746), .S(
DP_OP_168J30_122_4811_n740), .ICO(DP_OP_168J30_122_4811_n738), .CO(
DP_OP_168J30_122_4811_n739) );
CMPR42X1TS DP_OP_168J30_122_4811_U396 ( .A(DP_OP_168J30_122_4811_n734), .B(
DP_OP_168J30_122_4811_n731), .C(DP_OP_168J30_122_4811_n730), .D(
DP_OP_168J30_122_4811_n1177), .ICI(DP_OP_168J30_122_4811_n728), .S(
DP_OP_168J30_122_4811_n726), .ICO(DP_OP_168J30_122_4811_n724), .CO(
DP_OP_168J30_122_4811_n725) );
CMPR42X1TS DP_OP_168J30_122_4811_U393 ( .A(DP_OP_168J30_122_4811_n812), .B(
DP_OP_168J30_122_4811_n1987), .C(DP_OP_168J30_122_4811_n727), .D(
DP_OP_168J30_122_4811_n1148), .ICI(DP_OP_168J30_122_4811_n725), .S(
DP_OP_168J30_122_4811_n718), .ICO(DP_OP_168J30_122_4811_n716), .CO(
DP_OP_168J30_122_4811_n717) );
CMPR42X1TS DP_OP_168J30_122_4811_U391 ( .A(DP_OP_168J30_122_4811_n1175), .B(
DP_OP_168J30_122_4811_n1231), .C(DP_OP_168J30_122_4811_n719), .D(
DP_OP_168J30_122_4811_n715), .ICI(DP_OP_168J30_122_4811_n716), .S(
DP_OP_168J30_122_4811_n713), .ICO(DP_OP_168J30_122_4811_n711), .CO(
DP_OP_168J30_122_4811_n712) );
CMPR42X1TS DP_OP_168J30_122_4811_U390 ( .A(DP_OP_168J30_122_4811_n811), .B(
DP_OP_168J30_122_4811_n1986), .C(DP_OP_168J30_122_4811_n720), .D(
DP_OP_168J30_122_4811_n1147), .ICI(DP_OP_168J30_122_4811_n713), .S(
DP_OP_168J30_122_4811_n710), .ICO(DP_OP_168J30_122_4811_n708), .CO(
DP_OP_168J30_122_4811_n709) );
CMPR42X1TS DP_OP_168J30_122_4811_U388 ( .A(DP_OP_168J30_122_4811_n714), .B(
DP_OP_168J30_122_4811_n1230), .C(DP_OP_168J30_122_4811_n707), .D(
DP_OP_168J30_122_4811_n711), .ICI(DP_OP_168J30_122_4811_n810), .S(
DP_OP_168J30_122_4811_n705), .ICO(DP_OP_168J30_122_4811_n703), .CO(
DP_OP_168J30_122_4811_n704) );
CMPR42X1TS DP_OP_168J30_122_4811_U387 ( .A(DP_OP_168J30_122_4811_n1985), .B(
DP_OP_168J30_122_4811_n712), .C(DP_OP_168J30_122_4811_n708), .D(
DP_OP_168J30_122_4811_n1146), .ICI(DP_OP_168J30_122_4811_n705), .S(
DP_OP_168J30_122_4811_n702), .ICO(DP_OP_168J30_122_4811_n700), .CO(
DP_OP_168J30_122_4811_n701) );
CMPR42X1TS DP_OP_168J30_122_4811_U383 ( .A(DP_OP_168J30_122_4811_n809), .B(
DP_OP_168J30_122_4811_n1984), .C(DP_OP_168J30_122_4811_n704), .D(
DP_OP_168J30_122_4811_n1117), .ICI(DP_OP_168J30_122_4811_n701), .S(
DP_OP_168J30_122_4811_n692), .ICO(DP_OP_168J30_122_4811_n690), .CO(
DP_OP_168J30_122_4811_n691) );
CMPR42X1TS DP_OP_168J30_122_4811_U380 ( .A(DP_OP_168J30_122_4811_n1144), .B(
DP_OP_168J30_122_4811_n1228), .C(DP_OP_168J30_122_4811_n693), .D(
DP_OP_168J30_122_4811_n687), .ICI(DP_OP_168J30_122_4811_n690), .S(
DP_OP_168J30_122_4811_n685), .ICO(DP_OP_168J30_122_4811_n683), .CO(
DP_OP_168J30_122_4811_n684) );
CMPR42X1TS DP_OP_168J30_122_4811_U379 ( .A(DP_OP_168J30_122_4811_n808), .B(
DP_OP_168J30_122_4811_n1983), .C(DP_OP_168J30_122_4811_n694), .D(
DP_OP_168J30_122_4811_n1116), .ICI(DP_OP_168J30_122_4811_n685), .S(
DP_OP_168J30_122_4811_n682), .ICO(DP_OP_168J30_122_4811_n680), .CO(
DP_OP_168J30_122_4811_n681) );
CMPR42X1TS DP_OP_168J30_122_4811_U376 ( .A(DP_OP_168J30_122_4811_n686), .B(
DP_OP_168J30_122_4811_n677), .C(DP_OP_168J30_122_4811_n1227), .D(
DP_OP_168J30_122_4811_n683), .ICI(DP_OP_168J30_122_4811_n807), .S(
DP_OP_168J30_122_4811_n675), .ICO(DP_OP_168J30_122_4811_n673), .CO(
DP_OP_168J30_122_4811_n674) );
CMPR42X1TS DP_OP_168J30_122_4811_U375 ( .A(DP_OP_168J30_122_4811_n1982), .B(
DP_OP_168J30_122_4811_n684), .C(DP_OP_168J30_122_4811_n680), .D(
DP_OP_168J30_122_4811_n1115), .ICI(DP_OP_168J30_122_4811_n675), .S(
DP_OP_168J30_122_4811_n672), .ICO(DP_OP_168J30_122_4811_n670), .CO(
DP_OP_168J30_122_4811_n671) );
CMPR42X1TS DP_OP_168J30_122_4811_U373 ( .A(DP_OP_168J30_122_4811_n1198), .B(
DP_OP_168J30_122_4811_n1142), .C(DP_OP_168J30_122_4811_n669), .D(
DP_OP_168J30_122_4811_n676), .ICI(DP_OP_168J30_122_4811_n56), .S(
DP_OP_168J30_122_4811_n667), .ICO(DP_OP_168J30_122_4811_n665), .CO(
DP_OP_168J30_122_4811_n666) );
CMPR42X1TS DP_OP_168J30_122_4811_U371 ( .A(DP_OP_168J30_122_4811_n806), .B(
DP_OP_168J30_122_4811_n1981), .C(DP_OP_168J30_122_4811_n674), .D(
DP_OP_168J30_122_4811_n1086), .ICI(DP_OP_168J30_122_4811_n671), .S(
DP_OP_168J30_122_4811_n661), .ICO(DP_OP_168J30_122_4811_n659), .CO(
DP_OP_168J30_122_4811_n660) );
CMPR42X1TS DP_OP_168J30_122_4811_U369 ( .A(DP_OP_168J30_122_4811_n668), .B(
DP_OP_168J30_122_4811_n1197), .C(DP_OP_168J30_122_4811_n658), .D(
DP_OP_168J30_122_4811_n665), .ICI(DP_OP_168J30_122_4811_n666), .S(
DP_OP_168J30_122_4811_n656), .ICO(DP_OP_168J30_122_4811_n654), .CO(
DP_OP_168J30_122_4811_n655) );
CMPR42X1TS DP_OP_168J30_122_4811_U368 ( .A(DP_OP_168J30_122_4811_n1113), .B(
DP_OP_168J30_122_4811_n1225), .C(DP_OP_168J30_122_4811_n662), .D(
DP_OP_168J30_122_4811_n656), .ICI(DP_OP_168J30_122_4811_n659), .S(
DP_OP_168J30_122_4811_n653), .ICO(DP_OP_168J30_122_4811_n651), .CO(
DP_OP_168J30_122_4811_n652) );
CMPR42X1TS DP_OP_168J30_122_4811_U367 ( .A(DP_OP_168J30_122_4811_n805), .B(
DP_OP_168J30_122_4811_n1980), .C(DP_OP_168J30_122_4811_n663), .D(
DP_OP_168J30_122_4811_n1085), .ICI(DP_OP_168J30_122_4811_n653), .S(
DP_OP_168J30_122_4811_n650), .ICO(DP_OP_168J30_122_4811_n648), .CO(
DP_OP_168J30_122_4811_n649) );
CMPR42X1TS DP_OP_168J30_122_4811_U365 ( .A(DP_OP_168J30_122_4811_n657), .B(
DP_OP_168J30_122_4811_n1196), .C(DP_OP_168J30_122_4811_n647), .D(
DP_OP_168J30_122_4811_n654), .ICI(DP_OP_168J30_122_4811_n1112), .S(
DP_OP_168J30_122_4811_n645), .ICO(DP_OP_168J30_122_4811_n643), .CO(
DP_OP_168J30_122_4811_n644) );
CMPR42X1TS DP_OP_168J30_122_4811_U364 ( .A(DP_OP_168J30_122_4811_n655), .B(
DP_OP_168J30_122_4811_n1224), .C(DP_OP_168J30_122_4811_n645), .D(
DP_OP_168J30_122_4811_n651), .ICI(DP_OP_168J30_122_4811_n804), .S(
DP_OP_168J30_122_4811_n642), .ICO(DP_OP_168J30_122_4811_n640), .CO(
DP_OP_168J30_122_4811_n641) );
CMPR42X1TS DP_OP_168J30_122_4811_U360 ( .A(DP_OP_168J30_122_4811_n1195), .B(
DP_OP_168J30_122_4811_n1111), .C(DP_OP_168J30_122_4811_n634), .D(
DP_OP_168J30_122_4811_n644), .ICI(DP_OP_168J30_122_4811_n66), .S(
DP_OP_168J30_122_4811_n632), .ICO(DP_OP_168J30_122_4811_n630), .CO(
DP_OP_168J30_122_4811_n631) );
CMPR42X1TS DP_OP_168J30_122_4811_U359 ( .A(DP_OP_168J30_122_4811_n640), .B(
DP_OP_168J30_122_4811_n1223), .C(DP_OP_168J30_122_4811_n1083), .D(
DP_OP_168J30_122_4811_n632), .ICI(DP_OP_168J30_122_4811_n641), .S(
DP_OP_168J30_122_4811_n629), .ICO(DP_OP_168J30_122_4811_n627), .CO(
DP_OP_168J30_122_4811_n628) );
CMPR42X1TS DP_OP_168J30_122_4811_U355 ( .A(DP_OP_168J30_122_4811_n633), .B(
DP_OP_168J30_122_4811_n1194), .C(DP_OP_168J30_122_4811_n621), .D(
DP_OP_168J30_122_4811_n630), .ICI(DP_OP_168J30_122_4811_n631), .S(
DP_OP_168J30_122_4811_n619), .ICO(DP_OP_168J30_122_4811_n617), .CO(
DP_OP_168J30_122_4811_n618) );
CMPR42X1TS DP_OP_168J30_122_4811_U354 ( .A(DP_OP_168J30_122_4811_n1082), .B(
DP_OP_168J30_122_4811_n1222), .C(DP_OP_168J30_122_4811_n627), .D(
DP_OP_168J30_122_4811_n619), .ICI(DP_OP_168J30_122_4811_n1977), .S(
DP_OP_168J30_122_4811_n616), .ICO(DP_OP_168J30_122_4811_n614), .CO(
DP_OP_168J30_122_4811_n615) );
CMPR42X1TS DP_OP_168J30_122_4811_U350 ( .A(DP_OP_168J30_122_4811_n620), .B(
DP_OP_168J30_122_4811_n608), .C(DP_OP_168J30_122_4811_n1193), .D(
DP_OP_168J30_122_4811_n617), .ICI(DP_OP_168J30_122_4811_n1081), .S(
DP_OP_168J30_122_4811_n606), .ICO(DP_OP_168J30_122_4811_n604), .CO(
DP_OP_168J30_122_4811_n605) );
CMPR42X1TS DP_OP_168J30_122_4811_U349 ( .A(DP_OP_168J30_122_4811_n618), .B(
DP_OP_168J30_122_4811_n606), .C(DP_OP_168J30_122_4811_n1221), .D(
DP_OP_168J30_122_4811_n614), .ICI(DP_OP_168J30_122_4811_n801), .S(
DP_OP_168J30_122_4811_n603), .ICO(DP_OP_168J30_122_4811_n601), .CO(
DP_OP_168J30_122_4811_n602) );
CMPR42X1TS DP_OP_168J30_122_4811_U348 ( .A(DP_OP_168J30_122_4811_n1976), .B(
DP_OP_168J30_122_4811_n615), .C(DP_OP_168J30_122_4811_n611), .D(
DP_OP_168J30_122_4811_n1053), .ICI(DP_OP_168J30_122_4811_n603), .S(
DP_OP_168J30_122_4811_n600), .ICO(DP_OP_168J30_122_4811_n598), .CO(
DP_OP_168J30_122_4811_n599) );
CMPR42X1TS DP_OP_168J30_122_4811_U346 ( .A(DP_OP_168J30_122_4811_n1164), .B(
DP_OP_168J30_122_4811_n1108), .C(DP_OP_168J30_122_4811_n597), .D(
DP_OP_168J30_122_4811_n607), .ICI(DP_OP_168J30_122_4811_n604), .S(
DP_OP_168J30_122_4811_n595), .ICO(DP_OP_168J30_122_4811_n593), .CO(
DP_OP_168J30_122_4811_n594) );
CMPR42X1TS DP_OP_168J30_122_4811_U345 ( .A(DP_OP_168J30_122_4811_n1192), .B(
DP_OP_168J30_122_4811_n1080), .C(DP_OP_168J30_122_4811_n595), .D(
DP_OP_168J30_122_4811_n605), .ICI(n2361), .S(
DP_OP_168J30_122_4811_n592), .ICO(DP_OP_168J30_122_4811_n590), .CO(
DP_OP_168J30_122_4811_n591) );
CMPR42X1TS DP_OP_168J30_122_4811_U344 ( .A(DP_OP_168J30_122_4811_n601), .B(
DP_OP_168J30_122_4811_n1220), .C(DP_OP_168J30_122_4811_n592), .D(
DP_OP_168J30_122_4811_n1052), .ICI(DP_OP_168J30_122_4811_n602), .S(
DP_OP_168J30_122_4811_n589), .ICO(DP_OP_168J30_122_4811_n587), .CO(
DP_OP_168J30_122_4811_n588) );
CMPR42X1TS DP_OP_168J30_122_4811_U341 ( .A(DP_OP_168J30_122_4811_n596), .B(
DP_OP_168J30_122_4811_n1163), .C(DP_OP_168J30_122_4811_n583), .D(
DP_OP_168J30_122_4811_n593), .ICI(DP_OP_168J30_122_4811_n1079), .S(
DP_OP_168J30_122_4811_n581), .ICO(DP_OP_168J30_122_4811_n579), .CO(
DP_OP_168J30_122_4811_n580) );
CMPR42X1TS DP_OP_168J30_122_4811_U340 ( .A(DP_OP_168J30_122_4811_n594), .B(
DP_OP_168J30_122_4811_n1191), .C(DP_OP_168J30_122_4811_n581), .D(
DP_OP_168J30_122_4811_n590), .ICI(DP_OP_168J30_122_4811_n591), .S(
DP_OP_168J30_122_4811_n578), .ICO(DP_OP_168J30_122_4811_n576), .CO(
DP_OP_168J30_122_4811_n577) );
CMPR42X1TS DP_OP_168J30_122_4811_U339 ( .A(DP_OP_168J30_122_4811_n1051), .B(
DP_OP_168J30_122_4811_n1219), .C(DP_OP_168J30_122_4811_n578), .D(
DP_OP_168J30_122_4811_n587), .ICI(DP_OP_168J30_122_4811_n1974), .S(
DP_OP_168J30_122_4811_n575), .ICO(DP_OP_168J30_122_4811_n573), .CO(
DP_OP_168J30_122_4811_n574) );
CMPR42X1TS DP_OP_168J30_122_4811_U338 ( .A(DP_OP_168J30_122_4811_n799), .B(
DP_OP_168J30_122_4811_n584), .C(DP_OP_168J30_122_4811_n588), .D(
DP_OP_168J30_122_4811_n1023), .ICI(DP_OP_168J30_122_4811_n575), .S(
DP_OP_168J30_122_4811_n572), .ICO(DP_OP_168J30_122_4811_n570), .CO(
DP_OP_168J30_122_4811_n571) );
CMPR42X1TS DP_OP_168J30_122_4811_U336 ( .A(DP_OP_168J30_122_4811_n582), .B(
DP_OP_168J30_122_4811_n1162), .C(DP_OP_168J30_122_4811_n569), .D(
DP_OP_168J30_122_4811_n579), .ICI(DP_OP_168J30_122_4811_n1078), .S(
DP_OP_168J30_122_4811_n567), .ICO(DP_OP_168J30_122_4811_n565), .CO(
DP_OP_168J30_122_4811_n566) );
CMPR42X1TS DP_OP_168J30_122_4811_U335 ( .A(DP_OP_168J30_122_4811_n580), .B(
DP_OP_168J30_122_4811_n1190), .C(DP_OP_168J30_122_4811_n567), .D(
DP_OP_168J30_122_4811_n576), .ICI(DP_OP_168J30_122_4811_n1050), .S(
DP_OP_168J30_122_4811_n564), .ICO(DP_OP_168J30_122_4811_n562), .CO(
DP_OP_168J30_122_4811_n563) );
CMPR42X1TS DP_OP_168J30_122_4811_U334 ( .A(DP_OP_168J30_122_4811_n577), .B(
DP_OP_168J30_122_4811_n564), .C(DP_OP_168J30_122_4811_n1218), .D(
DP_OP_168J30_122_4811_n573), .ICI(DP_OP_168J30_122_4811_n798), .S(
DP_OP_168J30_122_4811_n561), .ICO(DP_OP_168J30_122_4811_n559), .CO(
DP_OP_168J30_122_4811_n560) );
CMPR42X1TS DP_OP_168J30_122_4811_U330 ( .A(DP_OP_168J30_122_4811_n1161), .B(
DP_OP_168J30_122_4811_n1077), .C(DP_OP_168J30_122_4811_n553), .D(
DP_OP_168J30_122_4811_n566), .ICI(DP_OP_168J30_122_4811_n562), .S(
DP_OP_168J30_122_4811_n551), .ICO(DP_OP_168J30_122_4811_n549), .CO(
DP_OP_168J30_122_4811_n550) );
CMPR42X1TS DP_OP_168J30_122_4811_U329 ( .A(DP_OP_168J30_122_4811_n1189), .B(
DP_OP_168J30_122_4811_n1049), .C(DP_OP_168J30_122_4811_n551), .D(
DP_OP_168J30_122_4811_n563), .ICI(DP_OP_168J30_122_4811_n86), .S(
DP_OP_168J30_122_4811_n548), .ICO(DP_OP_168J30_122_4811_n546), .CO(
DP_OP_168J30_122_4811_n547) );
CMPR42X1TS DP_OP_168J30_122_4811_U328 ( .A(DP_OP_168J30_122_4811_n559), .B(
DP_OP_168J30_122_4811_n1217), .C(DP_OP_168J30_122_4811_n548), .D(
DP_OP_168J30_122_4811_n1021), .ICI(DP_OP_168J30_122_4811_n560), .S(
DP_OP_168J30_122_4811_n545), .ICO(DP_OP_168J30_122_4811_n543), .CO(
DP_OP_168J30_122_4811_n544) );
CMPR42X1TS DP_OP_168J30_122_4811_U327 ( .A(DP_OP_168J30_122_4811_n797), .B(
DP_OP_168J30_122_4811_n1972), .C(DP_OP_168J30_122_4811_n556), .D(
DP_OP_168J30_122_4811_n993), .ICI(DP_OP_168J30_122_4811_n557), .S(
DP_OP_168J30_122_4811_n542), .ICO(DP_OP_168J30_122_4811_n540), .CO(
DP_OP_168J30_122_4811_n541) );
CMPR42X1TS DP_OP_168J30_122_4811_U324 ( .A(DP_OP_168J30_122_4811_n552), .B(
DP_OP_168J30_122_4811_n1160), .C(DP_OP_168J30_122_4811_n537), .D(
DP_OP_168J30_122_4811_n549), .ICI(DP_OP_168J30_122_4811_n1048), .S(
DP_OP_168J30_122_4811_n535), .ICO(DP_OP_168J30_122_4811_n533), .CO(
DP_OP_168J30_122_4811_n534) );
CMPR42X1TS DP_OP_168J30_122_4811_U323 ( .A(DP_OP_168J30_122_4811_n550), .B(
DP_OP_168J30_122_4811_n1188), .C(DP_OP_168J30_122_4811_n535), .D(
DP_OP_168J30_122_4811_n546), .ICI(DP_OP_168J30_122_4811_n547), .S(
DP_OP_168J30_122_4811_n532), .ICO(DP_OP_168J30_122_4811_n530), .CO(
DP_OP_168J30_122_4811_n531) );
CMPR42X1TS DP_OP_168J30_122_4811_U322 ( .A(DP_OP_168J30_122_4811_n1020), .B(
DP_OP_168J30_122_4811_n532), .C(DP_OP_168J30_122_4811_n543), .D(
DP_OP_168J30_122_4811_n796), .ICI(DP_OP_168J30_122_4811_n1971), .S(
DP_OP_168J30_122_4811_n529), .ICO(DP_OP_168J30_122_4811_n527), .CO(
DP_OP_168J30_122_4811_n528) );
CMPR42X1TS DP_OP_168J30_122_4811_U318 ( .A(DP_OP_168J30_122_4811_n536), .B(
DP_OP_168J30_122_4811_n521), .C(DP_OP_168J30_122_4811_n1159), .D(
DP_OP_168J30_122_4811_n533), .ICI(DP_OP_168J30_122_4811_n1047), .S(
DP_OP_168J30_122_4811_n519), .ICO(DP_OP_168J30_122_4811_n517), .CO(
DP_OP_168J30_122_4811_n518) );
CMPR42X1TS DP_OP_168J30_122_4811_U317 ( .A(DP_OP_168J30_122_4811_n534), .B(
DP_OP_168J30_122_4811_n519), .C(DP_OP_168J30_122_4811_n1187), .D(
DP_OP_168J30_122_4811_n530), .ICI(DP_OP_168J30_122_4811_n1019), .S(
DP_OP_168J30_122_4811_n516), .ICO(DP_OP_168J30_122_4811_n514), .CO(
DP_OP_168J30_122_4811_n515) );
CMPR42X1TS DP_OP_168J30_122_4811_U314 ( .A(DP_OP_168J30_122_4811_n1102), .B(
DP_OP_168J30_122_4811_n522), .C(DP_OP_168J30_122_4811_n1130), .D(
DP_OP_168J30_122_4811_n1074), .ICI(DP_OP_168J30_122_4811_n520), .S(
DP_OP_168J30_122_4811_n507), .ICO(DP_OP_168J30_122_4811_n505), .CO(
DP_OP_168J30_122_4811_n506) );
CMPR42X1TS DP_OP_168J30_122_4811_U313 ( .A(DP_OP_168J30_122_4811_n507), .B(
DP_OP_168J30_122_4811_n517), .C(DP_OP_168J30_122_4811_n1158), .D(
DP_OP_168J30_122_4811_n1046), .ICI(DP_OP_168J30_122_4811_n518), .S(
DP_OP_168J30_122_4811_n504), .ICO(DP_OP_168J30_122_4811_n502), .CO(
DP_OP_168J30_122_4811_n503) );
CMPR42X1TS DP_OP_168J30_122_4811_U312 ( .A(DP_OP_168J30_122_4811_n504), .B(
DP_OP_168J30_122_4811_n514), .C(DP_OP_168J30_122_4811_n1186), .D(
DP_OP_168J30_122_4811_n1018), .ICI(DP_OP_168J30_122_4811_n850), .S(
DP_OP_168J30_122_4811_n501), .ICO(DP_OP_168J30_122_4811_n499), .CO(
DP_OP_168J30_122_4811_n500) );
CMPR42X1TS DP_OP_168J30_122_4811_U311 ( .A(DP_OP_168J30_122_4811_n515), .B(
DP_OP_168J30_122_4811_n501), .C(DP_OP_168J30_122_4811_n511), .D(
DP_OP_168J30_122_4811_n1214), .ICI(DP_OP_168J30_122_4811_n990), .S(
DP_OP_168J30_122_4811_n498), .ICO(DP_OP_168J30_122_4811_n496), .CO(
DP_OP_168J30_122_4811_n497) );
CMPR42X1TS DP_OP_168J30_122_4811_U310 ( .A(DP_OP_168J30_122_4811_n794), .B(
DP_OP_168J30_122_4811_n1969), .C(DP_OP_168J30_122_4811_n512), .D(
DP_OP_168J30_122_4811_n508), .ICI(DP_OP_168J30_122_4811_n498), .S(
DP_OP_168J30_122_4811_n495), .ICO(DP_OP_168J30_122_4811_n493), .CO(
DP_OP_168J30_122_4811_n494) );
CMPR42X1TS DP_OP_168J30_122_4811_U309 ( .A(DP_OP_168J30_122_4811_n1101), .B(
DP_OP_168J30_122_4811_n1073), .C(DP_OP_168J30_122_4811_n505), .D(
DP_OP_168J30_122_4811_n1129), .ICI(DP_OP_168J30_122_4811_n506), .S(
DP_OP_168J30_122_4811_n492), .ICO(DP_OP_168J30_122_4811_n490), .CO(
DP_OP_168J30_122_4811_n491) );
CMPR42X1TS DP_OP_168J30_122_4811_U308 ( .A(DP_OP_168J30_122_4811_n1045), .B(
DP_OP_168J30_122_4811_n492), .C(DP_OP_168J30_122_4811_n502), .D(
DP_OP_168J30_122_4811_n1157), .ICI(DP_OP_168J30_122_4811_n503), .S(
DP_OP_168J30_122_4811_n489), .ICO(DP_OP_168J30_122_4811_n487), .CO(
DP_OP_168J30_122_4811_n488) );
CMPR42X1TS DP_OP_168J30_122_4811_U307 ( .A(DP_OP_168J30_122_4811_n489), .B(
DP_OP_168J30_122_4811_n1017), .C(DP_OP_168J30_122_4811_n499), .D(
DP_OP_168J30_122_4811_n1185), .ICI(DP_OP_168J30_122_4811_n849), .S(
DP_OP_168J30_122_4811_n486), .ICO(DP_OP_168J30_122_4811_n484), .CO(
DP_OP_168J30_122_4811_n485) );
CMPR42X1TS DP_OP_168J30_122_4811_U306 ( .A(DP_OP_168J30_122_4811_n500), .B(
DP_OP_168J30_122_4811_n989), .C(DP_OP_168J30_122_4811_n496), .D(
DP_OP_168J30_122_4811_n486), .ICI(DP_OP_168J30_122_4811_n1213), .S(
DP_OP_168J30_122_4811_n483), .ICO(DP_OP_168J30_122_4811_n481), .CO(
DP_OP_168J30_122_4811_n482) );
CMPR42X1TS DP_OP_168J30_122_4811_U305 ( .A(DP_OP_168J30_122_4811_n793), .B(
DP_OP_168J30_122_4811_n1968), .C(DP_OP_168J30_122_4811_n497), .D(
DP_OP_168J30_122_4811_n493), .ICI(DP_OP_168J30_122_4811_n483), .S(
DP_OP_168J30_122_4811_n480), .ICO(DP_OP_168J30_122_4811_n478), .CO(
DP_OP_168J30_122_4811_n479) );
CMPR42X1TS DP_OP_168J30_122_4811_U304 ( .A(DP_OP_168J30_122_4811_n1100), .B(
DP_OP_168J30_122_4811_n1072), .C(DP_OP_168J30_122_4811_n490), .D(
DP_OP_168J30_122_4811_n1128), .ICI(DP_OP_168J30_122_4811_n491), .S(
DP_OP_168J30_122_4811_n477), .ICO(DP_OP_168J30_122_4811_n475), .CO(
DP_OP_168J30_122_4811_n476) );
CMPR42X1TS DP_OP_168J30_122_4811_U303 ( .A(DP_OP_168J30_122_4811_n1044), .B(
DP_OP_168J30_122_4811_n477), .C(DP_OP_168J30_122_4811_n487), .D(
DP_OP_168J30_122_4811_n1156), .ICI(DP_OP_168J30_122_4811_n488), .S(
DP_OP_168J30_122_4811_n474), .ICO(DP_OP_168J30_122_4811_n472), .CO(
DP_OP_168J30_122_4811_n473) );
CMPR42X1TS DP_OP_168J30_122_4811_U302 ( .A(DP_OP_168J30_122_4811_n1016), .B(
DP_OP_168J30_122_4811_n474), .C(DP_OP_168J30_122_4811_n484), .D(
DP_OP_168J30_122_4811_n848), .ICI(DP_OP_168J30_122_4811_n1184), .S(
DP_OP_168J30_122_4811_n471), .ICO(DP_OP_168J30_122_4811_n469), .CO(
DP_OP_168J30_122_4811_n470) );
CMPR42X1TS DP_OP_168J30_122_4811_U301 ( .A(DP_OP_168J30_122_4811_n485), .B(
DP_OP_168J30_122_4811_n988), .C(DP_OP_168J30_122_4811_n1212), .D(
DP_OP_168J30_122_4811_n471), .ICI(DP_OP_168J30_122_4811_n481), .S(
DP_OP_168J30_122_4811_n468), .ICO(DP_OP_168J30_122_4811_n466), .CO(
DP_OP_168J30_122_4811_n467) );
CMPR42X1TS DP_OP_168J30_122_4811_U300 ( .A(DP_OP_168J30_122_4811_n792), .B(
DP_OP_168J30_122_4811_n1967), .C(DP_OP_168J30_122_4811_n478), .D(
DP_OP_168J30_122_4811_n482), .ICI(DP_OP_168J30_122_4811_n468), .S(
DP_OP_168J30_122_4811_n465), .ICO(DP_OP_168J30_122_4811_n463), .CO(
DP_OP_168J30_122_4811_n464) );
CMPR42X1TS DP_OP_168J30_122_4811_U299 ( .A(DP_OP_168J30_122_4811_n1211), .B(
DP_OP_168J30_122_4811_n1099), .C(DP_OP_168J30_122_4811_n1071), .D(
DP_OP_168J30_122_4811_n475), .ICI(DP_OP_168J30_122_4811_n1127), .S(
DP_OP_168J30_122_4811_n462), .ICO(DP_OP_168J30_122_4811_n460), .CO(
DP_OP_168J30_122_4811_n461) );
CMPR42X1TS DP_OP_168J30_122_4811_U298 ( .A(DP_OP_168J30_122_4811_n1043), .B(
DP_OP_168J30_122_4811_n476), .C(DP_OP_168J30_122_4811_n462), .D(
DP_OP_168J30_122_4811_n472), .ICI(DP_OP_168J30_122_4811_n1155), .S(
DP_OP_168J30_122_4811_n459), .ICO(DP_OP_168J30_122_4811_n457), .CO(
DP_OP_168J30_122_4811_n458) );
CMPR42X1TS DP_OP_168J30_122_4811_U297 ( .A(DP_OP_168J30_122_4811_n1015), .B(
DP_OP_168J30_122_4811_n473), .C(DP_OP_168J30_122_4811_n459), .D(
DP_OP_168J30_122_4811_n847), .ICI(DP_OP_168J30_122_4811_n469), .S(
DP_OP_168J30_122_4811_n456), .ICO(DP_OP_168J30_122_4811_n454), .CO(
DP_OP_168J30_122_4811_n455) );
CMPR42X1TS DP_OP_168J30_122_4811_U296 ( .A(DP_OP_168J30_122_4811_n1183), .B(
DP_OP_168J30_122_4811_n987), .C(DP_OP_168J30_122_4811_n470), .D(
DP_OP_168J30_122_4811_n456), .ICI(DP_OP_168J30_122_4811_n466), .S(
DP_OP_168J30_122_4811_n453), .ICO(DP_OP_168J30_122_4811_n451), .CO(
DP_OP_168J30_122_4811_n452) );
CMPR42X1TS DP_OP_168J30_122_4811_U294 ( .A(DP_OP_168J30_122_4811_n1070), .B(
DP_OP_168J30_122_4811_n1098), .C(DP_OP_168J30_122_4811_n460), .D(
DP_OP_168J30_122_4811_n1042), .ICI(DP_OP_168J30_122_4811_n1126), .S(
DP_OP_168J30_122_4811_n447), .ICO(DP_OP_168J30_122_4811_n445), .CO(
DP_OP_168J30_122_4811_n446) );
CMPR42X1TS DP_OP_168J30_122_4811_U293 ( .A(DP_OP_168J30_122_4811_n461), .B(
DP_OP_168J30_122_4811_n457), .C(DP_OP_168J30_122_4811_n447), .D(
DP_OP_168J30_122_4811_n1014), .ICI(DP_OP_168J30_122_4811_n458), .S(
DP_OP_168J30_122_4811_n444), .ICO(DP_OP_168J30_122_4811_n442), .CO(
DP_OP_168J30_122_4811_n443) );
CMPR42X1TS DP_OP_168J30_122_4811_U292 ( .A(DP_OP_168J30_122_4811_n1154), .B(
DP_OP_168J30_122_4811_n846), .C(DP_OP_168J30_122_4811_n454), .D(
DP_OP_168J30_122_4811_n444), .ICI(DP_OP_168J30_122_4811_n986), .S(
DP_OP_168J30_122_4811_n441), .ICO(DP_OP_168J30_122_4811_n439), .CO(
DP_OP_168J30_122_4811_n440) );
CMPR42X1TS DP_OP_168J30_122_4811_U291 ( .A(DP_OP_168J30_122_4811_n455), .B(
DP_OP_168J30_122_4811_n1182), .C(DP_OP_168J30_122_4811_n451), .D(
DP_OP_168J30_122_4811_n441), .ICI(DP_OP_168J30_122_4811_n452), .S(
DP_OP_168J30_122_4811_n438), .ICO(DP_OP_168J30_122_4811_n436), .CO(
DP_OP_168J30_122_4811_n437) );
CMPR42X1TS DP_OP_168J30_122_4811_U290 ( .A(n4706), .B(
DP_OP_168J30_122_4811_n438), .C(DP_OP_168J30_122_4811_n448), .D(
Sgf_operation_ODD1_Q_left[31]), .ICI(DP_OP_168J30_122_4811_n790), .S(
DP_OP_168J30_122_4811_n435), .ICO(DP_OP_168J30_122_4811_n433), .CO(
DP_OP_168J30_122_4811_n434) );
CMPR42X1TS DP_OP_168J30_122_4811_U289 ( .A(DP_OP_168J30_122_4811_n1069), .B(
DP_OP_168J30_122_4811_n1097), .C(DP_OP_168J30_122_4811_n445), .D(
DP_OP_168J30_122_4811_n1041), .ICI(DP_OP_168J30_122_4811_n1125), .S(
DP_OP_168J30_122_4811_n432), .ICO(DP_OP_168J30_122_4811_n430), .CO(
DP_OP_168J30_122_4811_n431) );
CMPR42X1TS DP_OP_168J30_122_4811_U288 ( .A(DP_OP_168J30_122_4811_n446), .B(
DP_OP_168J30_122_4811_n432), .C(DP_OP_168J30_122_4811_n442), .D(
DP_OP_168J30_122_4811_n1013), .ICI(DP_OP_168J30_122_4811_n845), .S(
DP_OP_168J30_122_4811_n429), .ICO(DP_OP_168J30_122_4811_n427), .CO(
DP_OP_168J30_122_4811_n428) );
CMPR42X1TS DP_OP_168J30_122_4811_U287 ( .A(DP_OP_168J30_122_4811_n1153), .B(
DP_OP_168J30_122_4811_n443), .C(DP_OP_168J30_122_4811_n429), .D(
DP_OP_168J30_122_4811_n439), .ICI(DP_OP_168J30_122_4811_n985), .S(
DP_OP_168J30_122_4811_n426), .ICO(DP_OP_168J30_122_4811_n424), .CO(
DP_OP_168J30_122_4811_n425) );
CMPR42X1TS DP_OP_168J30_122_4811_U284 ( .A(DP_OP_168J30_122_4811_n1180), .B(
DP_OP_168J30_122_4811_n1068), .C(DP_OP_168J30_122_4811_n1096), .D(
DP_OP_168J30_122_4811_n430), .ICI(DP_OP_168J30_122_4811_n1040), .S(
DP_OP_168J30_122_4811_n417), .ICO(DP_OP_168J30_122_4811_n415), .CO(
DP_OP_168J30_122_4811_n416) );
CMPR42X1TS DP_OP_168J30_122_4811_U283 ( .A(DP_OP_168J30_122_4811_n417), .B(
DP_OP_168J30_122_4811_n431), .C(DP_OP_168J30_122_4811_n1124), .D(
DP_OP_168J30_122_4811_n1012), .ICI(DP_OP_168J30_122_4811_n427), .S(
DP_OP_168J30_122_4811_n414), .ICO(DP_OP_168J30_122_4811_n412), .CO(
DP_OP_168J30_122_4811_n413) );
CMPR42X1TS DP_OP_168J30_122_4811_U282 ( .A(DP_OP_168J30_122_4811_n844), .B(
DP_OP_168J30_122_4811_n414), .C(DP_OP_168J30_122_4811_n428), .D(
DP_OP_168J30_122_4811_n1152), .ICI(DP_OP_168J30_122_4811_n984), .S(
DP_OP_168J30_122_4811_n411), .ICO(DP_OP_168J30_122_4811_n409), .CO(
DP_OP_168J30_122_4811_n410) );
CMPR42X1TS DP_OP_168J30_122_4811_U278 ( .A(DP_OP_168J30_122_4811_n1095), .B(
DP_OP_168J30_122_4811_n416), .C(DP_OP_168J30_122_4811_n402), .D(
DP_OP_168J30_122_4811_n1011), .ICI(DP_OP_168J30_122_4811_n412), .S(
DP_OP_168J30_122_4811_n400), .ICO(DP_OP_168J30_122_4811_n398), .CO(
DP_OP_168J30_122_4811_n399) );
CMPR42X1TS DP_OP_168J30_122_4811_U277 ( .A(DP_OP_168J30_122_4811_n1123), .B(
DP_OP_168J30_122_4811_n843), .C(DP_OP_168J30_122_4811_n413), .D(
DP_OP_168J30_122_4811_n400), .ICI(DP_OP_168J30_122_4811_n983), .S(
DP_OP_168J30_122_4811_n397), .ICO(DP_OP_168J30_122_4811_n395), .CO(
DP_OP_168J30_122_4811_n396) );
CMPR42X1TS DP_OP_168J30_122_4811_U276 ( .A(DP_OP_168J30_122_4811_n409), .B(
DP_OP_168J30_122_4811_n1151), .C(DP_OP_168J30_122_4811_n397), .D(
DP_OP_168J30_122_4811_n410), .ICI(DP_OP_168J30_122_4811_n406), .S(
DP_OP_168J30_122_4811_n394), .ICO(DP_OP_168J30_122_4811_n392), .CO(
DP_OP_168J30_122_4811_n393) );
CMPR42X1TS DP_OP_168J30_122_4811_U273 ( .A(DP_OP_168J30_122_4811_n1094), .B(
DP_OP_168J30_122_4811_n398), .C(DP_OP_168J30_122_4811_n388), .D(
DP_OP_168J30_122_4811_n1010), .ICI(DP_OP_168J30_122_4811_n842), .S(
DP_OP_168J30_122_4811_n386), .ICO(DP_OP_168J30_122_4811_n384), .CO(
DP_OP_168J30_122_4811_n385) );
CMPR42X1TS DP_OP_168J30_122_4811_U272 ( .A(DP_OP_168J30_122_4811_n1122), .B(
DP_OP_168J30_122_4811_n399), .C(DP_OP_168J30_122_4811_n386), .D(
DP_OP_168J30_122_4811_n395), .ICI(DP_OP_168J30_122_4811_n982), .S(
DP_OP_168J30_122_4811_n383), .ICO(DP_OP_168J30_122_4811_n381), .CO(
DP_OP_168J30_122_4811_n382) );
CMPR42X1TS DP_OP_168J30_122_4811_U271 ( .A(DP_OP_168J30_122_4811_n1150), .B(
DP_OP_168J30_122_4811_n396), .C(DP_OP_168J30_122_4811_n383), .D(
DP_OP_168J30_122_4811_n392), .ICI(DP_OP_168J30_122_4811_n393), .S(
DP_OP_168J30_122_4811_n380), .ICO(DP_OP_168J30_122_4811_n378), .CO(
DP_OP_168J30_122_4811_n379) );
CMPR42X1TS DP_OP_168J30_122_4811_U268 ( .A(DP_OP_168J30_122_4811_n374), .B(
DP_OP_168J30_122_4811_n387), .C(DP_OP_168J30_122_4811_n1093), .D(
DP_OP_168J30_122_4811_n1009), .ICI(DP_OP_168J30_122_4811_n384), .S(
DP_OP_168J30_122_4811_n372), .ICO(DP_OP_168J30_122_4811_n370), .CO(
DP_OP_168J30_122_4811_n371) );
CMPR42X1TS DP_OP_168J30_122_4811_U267 ( .A(DP_OP_168J30_122_4811_n841), .B(
DP_OP_168J30_122_4811_n372), .C(DP_OP_168J30_122_4811_n385), .D(
DP_OP_168J30_122_4811_n1121), .ICI(DP_OP_168J30_122_4811_n981), .S(
DP_OP_168J30_122_4811_n369), .ICO(DP_OP_168J30_122_4811_n367), .CO(
DP_OP_168J30_122_4811_n368) );
CMPR42X1TS DP_OP_168J30_122_4811_U266 ( .A(DP_OP_168J30_122_4811_n381), .B(
DP_OP_168J30_122_4811_n382), .C(DP_OP_168J30_122_4811_n369), .D(
DP_OP_168J30_122_4811_n378), .ICI(DP_OP_168J30_122_4811_n379), .S(
DP_OP_168J30_122_4811_n366), .ICO(DP_OP_168J30_122_4811_n364), .CO(
DP_OP_168J30_122_4811_n365) );
CMPR42X1TS DP_OP_168J30_122_4811_U264 ( .A(DP_OP_168J30_122_4811_n1036), .B(
DP_OP_168J30_122_4811_n1064), .C(DP_OP_168J30_122_4811_n373), .D(
DP_OP_168J30_122_4811_n1008), .ICI(DP_OP_168J30_122_4811_n370), .S(
DP_OP_168J30_122_4811_n360), .ICO(DP_OP_168J30_122_4811_n358), .CO(
DP_OP_168J30_122_4811_n359) );
CMPR42X1TS DP_OP_168J30_122_4811_U263 ( .A(DP_OP_168J30_122_4811_n1092), .B(
DP_OP_168J30_122_4811_n840), .C(DP_OP_168J30_122_4811_n371), .D(
DP_OP_168J30_122_4811_n360), .ICI(DP_OP_168J30_122_4811_n980), .S(
DP_OP_168J30_122_4811_n357), .ICO(DP_OP_168J30_122_4811_n355), .CO(
DP_OP_168J30_122_4811_n356) );
CMPR42X1TS DP_OP_168J30_122_4811_U262 ( .A(DP_OP_168J30_122_4811_n367), .B(
DP_OP_168J30_122_4811_n1120), .C(DP_OP_168J30_122_4811_n357), .D(
DP_OP_168J30_122_4811_n368), .ICI(DP_OP_168J30_122_4811_n364), .S(
DP_OP_168J30_122_4811_n354), .ICO(DP_OP_168J30_122_4811_n352), .CO(
DP_OP_168J30_122_4811_n353) );
CMPR42X1TS DP_OP_168J30_122_4811_U260 ( .A(DP_OP_168J30_122_4811_n1035), .B(
DP_OP_168J30_122_4811_n1063), .C(DP_OP_168J30_122_4811_n358), .D(
DP_OP_168J30_122_4811_n1007), .ICI(DP_OP_168J30_122_4811_n839), .S(
DP_OP_168J30_122_4811_n348), .ICO(DP_OP_168J30_122_4811_n346), .CO(
DP_OP_168J30_122_4811_n347) );
CMPR42X1TS DP_OP_168J30_122_4811_U259 ( .A(DP_OP_168J30_122_4811_n1091), .B(
DP_OP_168J30_122_4811_n359), .C(DP_OP_168J30_122_4811_n348), .D(
DP_OP_168J30_122_4811_n355), .ICI(DP_OP_168J30_122_4811_n979), .S(
DP_OP_168J30_122_4811_n345), .ICO(DP_OP_168J30_122_4811_n343), .CO(
DP_OP_168J30_122_4811_n344) );
CMPR42X1TS DP_OP_168J30_122_4811_U258 ( .A(DP_OP_168J30_122_4811_n1119), .B(
DP_OP_168J30_122_4811_n356), .C(DP_OP_168J30_122_4811_n345), .D(
DP_OP_168J30_122_4811_n352), .ICI(DP_OP_168J30_122_4811_n353), .S(
DP_OP_168J30_122_4811_n342), .ICO(DP_OP_168J30_122_4811_n340), .CO(
DP_OP_168J30_122_4811_n341) );
CMPR42X1TS DP_OP_168J30_122_4811_U257 ( .A(DP_OP_168J30_122_4811_n342), .B(
DP_OP_168J30_122_4811_n349), .C(DP_OP_168J30_122_4811_n1959), .D(
Sgf_operation_ODD1_Q_left[38]), .ICI(DP_OP_168J30_122_4811_n783), .S(
DP_OP_168J30_122_4811_n339), .ICO(DP_OP_168J30_122_4811_n337), .CO(
DP_OP_168J30_122_4811_n338) );
CMPR42X1TS DP_OP_168J30_122_4811_U256 ( .A(DP_OP_168J30_122_4811_n1118), .B(
DP_OP_168J30_122_4811_n1034), .C(DP_OP_168J30_122_4811_n1062), .D(
DP_OP_168J30_122_4811_n346), .ICI(DP_OP_168J30_122_4811_n1006), .S(
DP_OP_168J30_122_4811_n336), .ICO(DP_OP_168J30_122_4811_n334), .CO(
DP_OP_168J30_122_4811_n335) );
CMPR42X1TS DP_OP_168J30_122_4811_U255 ( .A(DP_OP_168J30_122_4811_n838), .B(
DP_OP_168J30_122_4811_n336), .C(DP_OP_168J30_122_4811_n347), .D(
DP_OP_168J30_122_4811_n1090), .ICI(DP_OP_168J30_122_4811_n978), .S(
DP_OP_168J30_122_4811_n333), .ICO(DP_OP_168J30_122_4811_n331), .CO(
DP_OP_168J30_122_4811_n332) );
CMPR42X1TS DP_OP_168J30_122_4811_U254 ( .A(DP_OP_168J30_122_4811_n343), .B(
DP_OP_168J30_122_4811_n344), .C(DP_OP_168J30_122_4811_n333), .D(
DP_OP_168J30_122_4811_n340), .ICI(DP_OP_168J30_122_4811_n341), .S(
DP_OP_168J30_122_4811_n330), .ICO(DP_OP_168J30_122_4811_n328), .CO(
DP_OP_168J30_122_4811_n329) );
CMPR42X1TS DP_OP_168J30_122_4811_U251 ( .A(DP_OP_168J30_122_4811_n1061), .B(
DP_OP_168J30_122_4811_n324), .C(DP_OP_168J30_122_4811_n837), .D(
DP_OP_168J30_122_4811_n335), .ICI(DP_OP_168J30_122_4811_n977), .S(
DP_OP_168J30_122_4811_n322), .ICO(DP_OP_168J30_122_4811_n320), .CO(
DP_OP_168J30_122_4811_n321) );
CMPR42X1TS DP_OP_168J30_122_4811_U250 ( .A(DP_OP_168J30_122_4811_n331), .B(
DP_OP_168J30_122_4811_n1089), .C(DP_OP_168J30_122_4811_n322), .D(
DP_OP_168J30_122_4811_n332), .ICI(DP_OP_168J30_122_4811_n328), .S(
DP_OP_168J30_122_4811_n319), .ICO(DP_OP_168J30_122_4811_n317), .CO(
DP_OP_168J30_122_4811_n318) );
CMPR42X1TS DP_OP_168J30_122_4811_U247 ( .A(DP_OP_168J30_122_4811_n836), .B(
DP_OP_168J30_122_4811_n1060), .C(DP_OP_168J30_122_4811_n313), .D(
DP_OP_168J30_122_4811_n320), .ICI(DP_OP_168J30_122_4811_n976), .S(
DP_OP_168J30_122_4811_n311), .ICO(DP_OP_168J30_122_4811_n309), .CO(
DP_OP_168J30_122_4811_n310) );
CMPR42X1TS DP_OP_168J30_122_4811_U246 ( .A(DP_OP_168J30_122_4811_n1088), .B(
DP_OP_168J30_122_4811_n321), .C(DP_OP_168J30_122_4811_n311), .D(
DP_OP_168J30_122_4811_n317), .ICI(DP_OP_168J30_122_4811_n318), .S(
DP_OP_168J30_122_4811_n308), .ICO(DP_OP_168J30_122_4811_n306), .CO(
DP_OP_168J30_122_4811_n307) );
CMPR42X1TS DP_OP_168J30_122_4811_U243 ( .A(DP_OP_168J30_122_4811_n302), .B(
DP_OP_168J30_122_4811_n835), .C(DP_OP_168J30_122_4811_n312), .D(
DP_OP_168J30_122_4811_n1059), .ICI(DP_OP_168J30_122_4811_n975), .S(
DP_OP_168J30_122_4811_n300), .ICO(DP_OP_168J30_122_4811_n298), .CO(
DP_OP_168J30_122_4811_n299) );
CMPR42X1TS DP_OP_168J30_122_4811_U242 ( .A(DP_OP_168J30_122_4811_n309), .B(
DP_OP_168J30_122_4811_n310), .C(DP_OP_168J30_122_4811_n300), .D(
DP_OP_168J30_122_4811_n306), .ICI(DP_OP_168J30_122_4811_n307), .S(
DP_OP_168J30_122_4811_n297), .ICO(DP_OP_168J30_122_4811_n295), .CO(
DP_OP_168J30_122_4811_n296) );
CMPR42X1TS DP_OP_168J30_122_4811_U240 ( .A(DP_OP_168J30_122_4811_n1002), .B(
DP_OP_168J30_122_4811_n301), .C(DP_OP_168J30_122_4811_n1030), .D(
DP_OP_168J30_122_4811_n834), .ICI(DP_OP_168J30_122_4811_n974), .S(
DP_OP_168J30_122_4811_n291), .ICO(DP_OP_168J30_122_4811_n289), .CO(
DP_OP_168J30_122_4811_n290) );
CMPR42X1TS DP_OP_168J30_122_4811_U239 ( .A(DP_OP_168J30_122_4811_n298), .B(
DP_OP_168J30_122_4811_n1058), .C(DP_OP_168J30_122_4811_n291), .D(
DP_OP_168J30_122_4811_n299), .ICI(DP_OP_168J30_122_4811_n295), .S(
DP_OP_168J30_122_4811_n288), .ICO(DP_OP_168J30_122_4811_n286), .CO(
DP_OP_168J30_122_4811_n287) );
CMPR42X1TS DP_OP_168J30_122_4811_U237 ( .A(DP_OP_168J30_122_4811_n1001), .B(
DP_OP_168J30_122_4811_n833), .C(DP_OP_168J30_122_4811_n1029), .D(
DP_OP_168J30_122_4811_n289), .ICI(DP_OP_168J30_122_4811_n973), .S(
DP_OP_168J30_122_4811_n282), .ICO(DP_OP_168J30_122_4811_n280), .CO(
DP_OP_168J30_122_4811_n281) );
CMPR42X1TS DP_OP_168J30_122_4811_U236 ( .A(DP_OP_168J30_122_4811_n1057), .B(
DP_OP_168J30_122_4811_n290), .C(DP_OP_168J30_122_4811_n282), .D(
DP_OP_168J30_122_4811_n286), .ICI(DP_OP_168J30_122_4811_n287), .S(
DP_OP_168J30_122_4811_n279), .ICO(DP_OP_168J30_122_4811_n277), .CO(
DP_OP_168J30_122_4811_n278) );
CMPR42X1TS DP_OP_168J30_122_4811_U234 ( .A(DP_OP_168J30_122_4811_n1056), .B(
DP_OP_168J30_122_4811_n1000), .C(DP_OP_168J30_122_4811_n832), .D(
DP_OP_168J30_122_4811_n280), .ICI(DP_OP_168J30_122_4811_n1028), .S(
DP_OP_168J30_122_4811_n273), .ICO(DP_OP_168J30_122_4811_n271), .CO(
DP_OP_168J30_122_4811_n272) );
CMPR42X1TS DP_OP_168J30_122_4811_U233 ( .A(DP_OP_168J30_122_4811_n972), .B(
DP_OP_168J30_122_4811_n281), .C(DP_OP_168J30_122_4811_n273), .D(
DP_OP_168J30_122_4811_n277), .ICI(DP_OP_168J30_122_4811_n278), .S(
DP_OP_168J30_122_4811_n270), .ICO(DP_OP_168J30_122_4811_n268), .CO(
DP_OP_168J30_122_4811_n269) );
CMPR42X1TS DP_OP_168J30_122_4811_U230 ( .A(DP_OP_168J30_122_4811_n971), .B(
DP_OP_168J30_122_4811_n264), .C(DP_OP_168J30_122_4811_n1027), .D(
DP_OP_168J30_122_4811_n272), .ICI(DP_OP_168J30_122_4811_n268), .S(
DP_OP_168J30_122_4811_n262), .ICO(DP_OP_168J30_122_4811_n260), .CO(
DP_OP_168J30_122_4811_n261) );
CMPR42X1TS DP_OP_168J30_122_4811_U227 ( .A(DP_OP_168J30_122_4811_n263), .B(
DP_OP_168J30_122_4811_n1026), .C(DP_OP_168J30_122_4811_n256), .D(
DP_OP_168J30_122_4811_n260), .ICI(DP_OP_168J30_122_4811_n261), .S(
DP_OP_168J30_122_4811_n254), .ICO(DP_OP_168J30_122_4811_n252), .CO(
DP_OP_168J30_122_4811_n253) );
CMPR42X1TS DP_OP_168J30_122_4811_U224 ( .A(DP_OP_168J30_122_4811_n969), .B(
DP_OP_168J30_122_4811_n248), .C(DP_OP_168J30_122_4811_n255), .D(
DP_OP_168J30_122_4811_n252), .ICI(DP_OP_168J30_122_4811_n253), .S(
DP_OP_168J30_122_4811_n246), .ICO(DP_OP_168J30_122_4811_n244), .CO(
DP_OP_168J30_122_4811_n245) );
CMPR42X1TS DP_OP_168J30_122_4811_U222 ( .A(DP_OP_168J30_122_4811_n828), .B(
DP_OP_168J30_122_4811_n968), .C(DP_OP_168J30_122_4811_n247), .D(
DP_OP_168J30_122_4811_n996), .ICI(DP_OP_168J30_122_4811_n244), .S(
DP_OP_168J30_122_4811_n240), .ICO(DP_OP_168J30_122_4811_n238), .CO(
DP_OP_168J30_122_4811_n239) );
CMPR42X1TS DP_OP_168J30_122_4811_U220 ( .A(DP_OP_168J30_122_4811_n827), .B(
DP_OP_168J30_122_4811_n967), .C(DP_OP_168J30_122_4811_n995), .D(
DP_OP_168J30_122_4811_n238), .ICI(DP_OP_168J30_122_4811_n239), .S(
DP_OP_168J30_122_4811_n234), .ICO(DP_OP_168J30_122_4811_n232), .CO(
DP_OP_168J30_122_4811_n233) );
CMPR42X1TS DP_OP_168J30_122_4811_U218 ( .A(DP_OP_168J30_122_4811_n994), .B(
DP_OP_168J30_122_4811_n826), .C(DP_OP_168J30_122_4811_n966), .D(
DP_OP_168J30_122_4811_n232), .ICI(DP_OP_168J30_122_4811_n233), .S(
DP_OP_168J30_122_4811_n228), .ICO(DP_OP_168J30_122_4811_n226), .CO(
DP_OP_168J30_122_4811_n227) );
CMPR42X1TS DP_OP_168J30_122_4811_U214 ( .A(DP_OP_168J30_122_4811_n824), .B(
DP_OP_168J30_122_4811_n964), .C(DP_OP_168J30_122_4811_n221), .D(
DP_OP_168J30_122_4811_n218), .ICI(DP_OP_168J30_122_4811_n219), .S(
DP_OP_168J30_122_4811_n217), .ICO(DP_OP_168J30_122_4811_n215), .CO(
DP_OP_168J30_122_4811_n216) );
AFCSIHCONX2TS intadd_76_U27 ( .A(Op_MY[28]), .B(Op_MY[1]), .CS(intadd_76_n36), .S(DP_OP_168J30_122_4811_n1867), .CO0N(intadd_76_n35), .CO1N(intadd_76_n34)
);
AFCSHCINX2TS intadd_76_U26 ( .CI1N(intadd_76_n34), .B(Op_MY[29]), .A(
Op_MY[2]), .CI0N(intadd_76_n35), .CS(intadd_76_n36), .CO1(
intadd_76_n32), .CO0(intadd_76_n33), .S(DP_OP_168J30_122_4811_n1866)
);
AFCSHCONX2TS intadd_76_U25 ( .B(Op_MY[30]), .A(Op_MY[3]), .CI0(intadd_76_n33), .CI1(intadd_76_n32), .CS(intadd_76_n36), .S(DP_OP_168J30_122_4811_n1865),
.CO0N(intadd_76_n31), .CO1N(intadd_76_n30) );
AFCSHCINX2TS intadd_76_U24 ( .CI1N(intadd_76_n30), .B(Op_MY[4]), .A(
Op_MY[31]), .CI0N(intadd_76_n31), .CS(intadd_76_n36), .CO1(
intadd_76_n28), .CO0(intadd_76_n29), .S(DP_OP_168J30_122_4811_n1864)
);
AFCSIHCONX2TS intadd_76_U21 ( .A(Op_MY[5]), .B(Op_MY[32]), .CS(intadd_76_n26), .S(DP_OP_168J30_122_4811_n1863), .CO0N(intadd_76_n25), .CO1N(intadd_76_n24)
);
AFCSHCINX2TS intadd_76_U20 ( .CI1N(intadd_76_n24), .B(Op_MY[6]), .A(
Op_MY[33]), .CI0N(intadd_76_n25), .CS(intadd_76_n26), .CO1(
intadd_76_n22), .CO0(intadd_76_n23), .S(DP_OP_168J30_122_4811_n1862)
);
AFCSHCINX2TS intadd_76_U18 ( .CI1N(intadd_76_n20), .B(Op_MY[35]), .A(
Op_MY[8]), .CI0N(intadd_76_n21), .CS(intadd_76_n26), .CO1(
intadd_76_n18), .CO0(intadd_76_n19), .S(DP_OP_168J30_122_4811_n1860)
);
AFCSHCONX2TS intadd_76_U17 ( .B(Op_MY[9]), .A(Op_MY[36]), .CI0(intadd_76_n19), .CI1(intadd_76_n18), .CS(intadd_76_n26), .S(DP_OP_168J30_122_4811_n1859),
.CO0N(intadd_76_n17), .CO1N(intadd_76_n16) );
CMPR42X2TS DP_OP_168J30_122_4811_U353 ( .A(DP_OP_168J30_122_4811_n802), .B(
DP_OP_168J30_122_4811_n624), .C(DP_OP_168J30_122_4811_n628), .D(
DP_OP_168J30_122_4811_n1054), .ICI(DP_OP_168J30_122_4811_n616), .S(
DP_OP_168J30_122_4811_n613), .ICO(DP_OP_168J30_122_4811_n611), .CO(
DP_OP_168J30_122_4811_n612) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n631), .CK(clk), .RN(
n5543), .Q(Op_MY[49]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n630), .CK(clk), .RN(
n5542), .Q(Op_MY[48]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n629), .CK(clk), .RN(
n5542), .Q(Op_MY[47]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n627), .CK(clk), .RN(
n5542), .Q(Op_MY[45]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n632), .CK(clk), .RN(
n5542), .Q(Op_MY[50]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n628), .CK(clk), .RN(
n5542), .Q(Op_MY[46]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n646), .CK(clk), .RN(
n5538), .Q(Op_MX[0]), .QN(DP_OP_168J30_122_4811_n3615) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n633), .CK(clk), .RN(
n5538), .Q(Op_MY[51]) );
DFFRX4TS FS_Module_state_reg_reg_1_ ( .D(n712), .CK(clk), .RN(n286), .Q(
n5527), .QN(n5550) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n580), .CK(clk),
.RN(n5529), .Q(Sgf_normalized_result[52]), .QN(n5505) );
DFFSX2TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n843), .CK(clk), .SN(
n5551), .Q(n934), .QN(Op_MX[28]) );
DFFSX2TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n842), .CK(clk), .SN(
n5551), .QN(Op_MX[30]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n602), .CK(clk), .RN(
n5540), .Q(Op_MY[20]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n600), .CK(clk), .RN(
n5540), .Q(Op_MY[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n672), .CK(clk), .RN(
n5539), .Q(Op_MX[26]), .QN(n917) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n697), .CK(clk), .RN(
n5532), .Q(Op_MX[51]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n667), .CK(clk), .RN(
n5536), .Q(Op_MX[21]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n692), .CK(clk), .RN(
n4671), .Q(Op_MX[46]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n686), .CK(clk), .RN(
n5536), .Q(Op_MX[40]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n659), .CK(clk), .RN(
n5531), .Q(Op_MX[13]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n355), .CK(clk),
.RN(n5534), .Q(Sgf_normalized_result[2]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n664), .CK(clk), .RN(
n5536), .Q(Op_MX[18]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n683), .CK(clk), .RN(
n5529), .Q(Op_MX[37]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n649), .CK(clk), .RN(
n5535), .Q(Op_MX[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n679), .CK(clk), .RN(
n5540), .Q(Op_MX[33]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n652), .CK(clk), .RN(
n5532), .Q(Op_MX[6]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n671), .CK(clk), .RN(
n5536), .Q(Op_MX[25]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n677), .CK(clk), .RN(
n5529), .Q(Op_MX[31]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n680), .CK(clk), .RN(
n4671), .Q(Op_MX[34]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n653), .CK(clk), .RN(
n5528), .Q(Op_MX[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n391), .CK(clk),
.RN(n5532), .Q(Sgf_normalized_result[38]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n395), .CK(clk),
.RN(n5542), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n397), .CK(clk),
.RN(n5543), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n399), .CK(clk),
.RN(n5541), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n401), .CK(clk),
.RN(n5535), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n359), .CK(clk),
.RN(n5535), .Q(Sgf_normalized_result[6]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n361), .CK(clk),
.RN(n5528), .Q(Sgf_normalized_result[8]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n363), .CK(clk),
.RN(n5532), .Q(Sgf_normalized_result[10]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n365), .CK(clk),
.RN(n5530), .Q(Sgf_normalized_result[12]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n367), .CK(clk),
.RN(n5537), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n369), .CK(clk),
.RN(n5528), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n371), .CK(clk),
.RN(n5531), .Q(Sgf_normalized_result[18]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n373), .CK(clk),
.RN(n5534), .Q(Sgf_normalized_result[20]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n375), .CK(clk),
.RN(n5532), .Q(Sgf_normalized_result[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n377), .CK(clk),
.RN(n5537), .Q(Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n379), .CK(clk),
.RN(n5528), .Q(Sgf_normalized_result[26]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n381), .CK(clk),
.RN(n5530), .Q(Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n383), .CK(clk),
.RN(n5534), .Q(Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n385), .CK(clk),
.RN(n5531), .Q(Sgf_normalized_result[32]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n387), .CK(clk),
.RN(n5535), .Q(Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n389), .CK(clk),
.RN(n5537), .Q(Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n393), .CK(clk),
.RN(n5543), .Q(Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n403), .CK(clk),
.RN(n5530), .Q(Sgf_normalized_result[50]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n685), .CK(clk), .RN(
n5543), .Q(Op_MX[39]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n682), .CK(clk), .RN(
n5539), .Q(Op_MX[36]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_71_ ( .D(n492), .CK(clk), .RN(
n286), .Q(P_Sgf[71]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_84_ ( .D(n505), .CK(clk), .RN(
n286), .Q(P_Sgf[84]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_105_ ( .D(n420), .CK(clk), .RN(
n5549), .Q(P_Sgf[105]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n706), .CK(clk), .RN(
n5528), .Q(Op_MX[60]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n5541),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n575), .CK(clk), .RN(n5541),
.Q(Add_result[4]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n644), .CK(clk), .RN(
n5541), .Q(Op_MY[62]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n5538),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n569), .CK(clk), .RN(n5551),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n567), .CK(clk), .RN(n5538),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n565), .CK(clk), .RN(n5538),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n563), .CK(clk), .RN(n5538),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n574), .CK(clk), .RN(n5541),
.Q(Add_result[5]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_72_ ( .D(n493), .CK(clk), .RN(
n286), .Q(P_Sgf[72]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_73_ ( .D(n494), .CK(clk), .RN(
n5548), .Q(P_Sgf[73]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_74_ ( .D(n495), .CK(clk), .RN(
n5547), .Q(P_Sgf[74]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_75_ ( .D(n496), .CK(clk), .RN(
n5549), .Q(P_Sgf[75]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_76_ ( .D(n497), .CK(clk), .RN(
n5549), .Q(P_Sgf[76]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_77_ ( .D(n498), .CK(clk), .RN(
n5546), .Q(P_Sgf[77]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_78_ ( .D(n499), .CK(clk), .RN(
n5544), .Q(P_Sgf[78]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_79_ ( .D(n500), .CK(clk), .RN(
n5545), .Q(P_Sgf[79]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_80_ ( .D(n501), .CK(clk), .RN(
n5548), .Q(P_Sgf[80]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_81_ ( .D(n502), .CK(clk), .RN(
n286), .Q(P_Sgf[81]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_82_ ( .D(n503), .CK(clk), .RN(
n286), .Q(P_Sgf[82]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_83_ ( .D(n504), .CK(clk), .RN(
n286), .Q(P_Sgf[83]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_85_ ( .D(n506), .CK(clk), .RN(
n286), .Q(P_Sgf[85]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_86_ ( .D(n507), .CK(clk), .RN(
n286), .Q(P_Sgf[86]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_87_ ( .D(n508), .CK(clk), .RN(
n286), .Q(P_Sgf[87]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_88_ ( .D(n509), .CK(clk), .RN(
n286), .Q(P_Sgf[88]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_89_ ( .D(n510), .CK(clk), .RN(
n286), .Q(P_Sgf[89]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_90_ ( .D(n511), .CK(clk), .RN(
n286), .Q(P_Sgf[90]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_91_ ( .D(n512), .CK(clk), .RN(
n286), .Q(P_Sgf[91]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_92_ ( .D(n513), .CK(clk), .RN(
n286), .Q(P_Sgf[92]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_93_ ( .D(n514), .CK(clk), .RN(
n5544), .Q(P_Sgf[93]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_94_ ( .D(n515), .CK(clk), .RN(
n5544), .Q(P_Sgf[94]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_95_ ( .D(n516), .CK(clk), .RN(
n5544), .Q(P_Sgf[95]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_96_ ( .D(n517), .CK(clk), .RN(
n5544), .Q(P_Sgf[96]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_97_ ( .D(n518), .CK(clk), .RN(
n5544), .Q(P_Sgf[97]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_98_ ( .D(n519), .CK(clk), .RN(
n5544), .Q(P_Sgf[98]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_99_ ( .D(n521), .CK(clk), .RN(
n5544), .Q(P_Sgf[99]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_100_ ( .D(n522), .CK(clk), .RN(
n5544), .Q(P_Sgf[100]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_101_ ( .D(n523), .CK(clk), .RN(
n5544), .Q(P_Sgf[101]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_102_ ( .D(n524), .CK(clk), .RN(
n5544), .Q(P_Sgf[102]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n642), .CK(clk), .RN(
n5543), .Q(Op_MY[60]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_103_ ( .D(n525), .CK(clk), .RN(
n5546), .Q(P_Sgf[103]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n573), .CK(clk), .RN(n5541),
.Q(Add_result[6]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n702), .CK(clk), .RN(
n5532), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n707), .CK(clk), .RN(
n5528), .Q(Op_MX[61]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n407), .CK(clk), .RN(n5529),
.Q(exp_oper_result[10]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n410), .CK(clk), .RN(n5529),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n411), .CK(clk), .RN(n5529),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n412), .CK(clk), .RN(n5529),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n414), .CK(clk), .RN(n5529),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n415), .CK(clk), .RN(n5529),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n416), .CK(clk), .RN(n5535),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n417), .CK(clk), .RN(n5538),
.Q(exp_oper_result[0]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n526), .CK(clk), .RN(
n5541), .Q(FSM_add_overflow_flag) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n634), .CK(clk), .RN(
n5551), .Q(Op_MY[52]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n643), .CK(clk), .RN(
n5541), .Q(Op_MY[61]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n406), .CK(clk), .RN(n5529),
.Q(exp_oper_result[11]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n635), .CK(clk), .RN(
n5538), .Q(Op_MY[53]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n655), .CK(clk), .RN(
n5530), .Q(Op_MX[9]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n658), .CK(clk), .RN(
n5537), .Q(Op_MX[12]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n689), .CK(clk), .RN(
n4671), .Q(Op_MX[43]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n691), .CK(clk), .RN(
n5536), .Q(Op_MX[45]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_39_ ( .D(n460), .CK(clk), .RN(
n5546), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_48_ ( .D(n469), .CK(clk), .RN(
n5549), .Q(P_Sgf[48]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n656), .CK(clk), .RN(
n5531), .Q(Op_MX[10]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_52_ ( .D(n473), .CK(clk), .RN(
n286), .Q(P_Sgf[52]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_104_ ( .D(n520), .CK(clk), .RN(
n5546), .Q(P_Sgf[104]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_0_ ( .D(n421), .CK(clk), .RN(
n5549), .Q(P_Sgf[0]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_4_ ( .D(n425), .CK(clk), .RN(
n5549), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_8_ ( .D(n429), .CK(clk), .RN(
n5545), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_12_ ( .D(n433), .CK(clk), .RN(
n5548), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_16_ ( .D(n437), .CK(clk), .RN(
n5548), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_20_ ( .D(n441), .CK(clk), .RN(
n5548), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_24_ ( .D(n445), .CK(clk), .RN(
n5547), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_28_ ( .D(n449), .CK(clk), .RN(
n5547), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_32_ ( .D(n453), .CK(clk), .RN(
n5547), .Q(P_Sgf[32]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n645), .CK(clk), .RN(
n5538), .Q(Op_MX[63]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n688), .CK(clk), .RN(
n5536), .Q(Op_MX[42]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n662), .CK(clk), .RN(
n5536), .Q(Op_MX[16]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n695), .CK(clk), .RN(
n5536), .Q(Op_MX[49]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n661), .CK(clk), .RN(
n5536), .Q(Op_MX[15]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n694), .CK(clk), .RN(
n4671), .Q(Op_MX[48]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n670), .CK(clk), .RN(
n5536), .Q(Op_MX[24]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n665), .CK(clk), .RN(
n5536), .Q(Op_MX[19]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n650), .CK(clk), .RN(
n5535), .Q(Op_MX[4]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n356), .CK(clk),
.RN(n5537), .Q(Sgf_normalized_result[3]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n668), .CK(clk), .RN(
n5536), .Q(Op_MX[22]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n357), .CK(clk),
.RN(n5532), .Q(Sgf_normalized_result[4]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n708), .CK(clk), .RN(
n5530), .Q(Op_MX[62]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n704), .CK(clk), .RN(
n5539), .Q(Op_MX[58]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n705), .CK(clk), .RN(
n5528), .Q(Op_MX[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n703), .CK(clk), .RN(
n5530), .Q(Op_MX[57]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n5541),
.Q(Add_result[2]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n5541),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n568), .CK(clk), .RN(n5551),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n572), .CK(clk), .RN(n5541),
.Q(Add_result[7]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n638), .CK(clk), .RN(
n5542), .Q(Op_MY[56]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n576), .CK(clk), .RN(n5541),
.Q(Add_result[3]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n637), .CK(clk), .RN(
n5542), .Q(Op_MY[55]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n700), .CK(clk), .RN(
n5528), .Q(Op_MX[54]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n701), .CK(clk), .RN(
n5531), .Q(Op_MX[55]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n636), .CK(clk), .RN(
n5542), .Q(Op_MY[54]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n699), .CK(clk), .RN(
n5528), .Q(Op_MX[53]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n354), .CK(clk),
.RN(n5537), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n353), .CK(clk),
.RN(n5531), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n413), .CK(clk), .RN(n5529),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n409), .CK(clk), .RN(n5529),
.Q(exp_oper_result[8]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n408), .CK(clk), .RN(n5529),
.Q(exp_oper_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n540), .CK(clk), .RN(n5539),
.Q(Add_result[39]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n542), .CK(clk), .RN(n5539),
.Q(Add_result[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n544), .CK(clk), .RN(n5539),
.Q(Add_result[35]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n561), .CK(clk), .RN(n5528),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n538), .CK(clk), .RN(n5539),
.Q(Add_result[41]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n546), .CK(clk), .RN(n5539),
.Q(Add_result[33]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n537), .CK(clk), .RN(n5539),
.Q(Add_result[42]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n539), .CK(clk), .RN(n5539),
.Q(Add_result[40]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n541), .CK(clk), .RN(n5539),
.Q(Add_result[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n543), .CK(clk), .RN(n5539),
.Q(Add_result[36]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n545), .CK(clk), .RN(n5539),
.Q(Add_result[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n547), .CK(clk), .RN(n5539),
.Q(Add_result[32]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_50_ ( .D(n471), .CK(clk), .RN(
n5549), .Q(P_Sgf[50]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_49_ ( .D(n470), .CK(clk), .RN(
n5549), .Q(P_Sgf[49]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_51_ ( .D(n472), .CK(clk), .RN(
n5547), .Q(P_Sgf[51]) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n647), .CK(clk), .RN(
n5538), .Q(Op_MX[1]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n610), .CK(clk), .RN(
n5543), .Q(Op_MY[28]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_38_ ( .D(n459), .CK(clk), .RN(
n5546), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_34_ ( .D(n455), .CK(clk), .RN(
n5547), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_30_ ( .D(n451), .CK(clk), .RN(
n5547), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_26_ ( .D(n447), .CK(clk), .RN(
n5547), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_22_ ( .D(n443), .CK(clk), .RN(
n5548), .Q(P_Sgf[22]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_18_ ( .D(n439), .CK(clk), .RN(
n5548), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_14_ ( .D(n435), .CK(clk), .RN(
n5548), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_10_ ( .D(n431), .CK(clk), .RN(
n5547), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_6_ ( .D(n427), .CK(clk), .RN(
n5549), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_2_ ( .D(n423), .CK(clk), .RN(
n5549), .Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_37_ ( .D(n458), .CK(clk), .RN(
n5546), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_33_ ( .D(n454), .CK(clk), .RN(
n5547), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_29_ ( .D(n450), .CK(clk), .RN(
n5547), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_25_ ( .D(n446), .CK(clk), .RN(
n5547), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_21_ ( .D(n442), .CK(clk), .RN(
n5548), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_17_ ( .D(n438), .CK(clk), .RN(
n5548), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_13_ ( .D(n434), .CK(clk), .RN(
n5548), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_9_ ( .D(n430), .CK(clk), .RN(
n5548), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_5_ ( .D(n426), .CK(clk), .RN(
n5549), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_1_ ( .D(n422), .CK(clk), .RN(
n5549), .Q(P_Sgf[1]) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n709), .CK(clk), .RN(n5529), .Q(FSM_selector_C),
.QN(n5476) );
CMPR42X1TS DP_OP_168J30_122_4811_U405 ( .A(DP_OP_168J30_122_4811_n816), .B(
DP_OP_168J30_122_4811_n750), .C(DP_OP_168J30_122_4811_n1991), .D(
DP_OP_168J30_122_4811_n1208), .ICI(DP_OP_168J30_122_4811_n749), .S(
DP_OP_168J30_122_4811_n747), .ICO(DP_OP_168J30_122_4811_n745), .CO(
DP_OP_168J30_122_4811_n746) );
CMPR42X2TS DP_OP_168J30_122_4811_U232 ( .A(DP_OP_168J30_122_4811_n270), .B(
DP_OP_168J30_122_4811_n274), .C(DP_OP_168J30_122_4811_n1952), .D(
DP_OP_168J30_122_4811_n776), .ICI(DP_OP_168J30_122_4811_n1951), .S(
DP_OP_168J30_122_4811_n267), .ICO(DP_OP_168J30_122_4811_n265), .CO(
DP_OP_168J30_122_4811_n266) );
CMPR42X2TS DP_OP_168J30_122_4811_U229 ( .A(DP_OP_168J30_122_4811_n262), .B(
DP_OP_168J30_122_4811_n269), .C(DP_OP_168J30_122_4811_n265), .D(
Sgf_operation_ODD1_Q_left[46]), .ICI(DP_OP_168J30_122_4811_n775), .S(
DP_OP_168J30_122_4811_n259), .ICO(DP_OP_168J30_122_4811_n257), .CO(
DP_OP_168J30_122_4811_n258) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_61_ ( .D(n482), .CK(clk), .RN(
n5545), .Q(P_Sgf[61]), .QN(n5522) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_59_ ( .D(n480), .CK(clk), .RN(
n5545), .Q(P_Sgf[59]), .QN(n5507) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n673), .CK(clk), .RN(
n4671), .Q(Op_MX[27]), .QN(n888) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n651), .CK(clk), .RN(
n5532), .Q(Op_MX[5]), .QN(n879) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n584), .CK(clk), .RN(
n5542), .Q(Op_MY[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n648), .CK(clk), .RN(
n5530), .Q(Op_MX[2]), .QN(n758) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n609), .CK(clk), .RN(
n5543), .Q(Op_MY[27]), .QN(n748) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n675), .CK(clk), .RN(
n5540), .Q(Op_MX[29]), .QN(n732) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n601), .CK(clk), .RN(
n5530), .Q(Op_MY[19]) );
DFFRX4TS Sel_A_Q_reg_0_ ( .D(n710), .CK(clk), .RN(n5537), .Q(FSM_selector_A),
.QN(n5503) );
NOR2X4TS U746 ( .A(n5369), .B(n5476), .Y(n4753) );
NAND2X1TS U747 ( .A(n5277), .B(Sgf_operation_ODD1_Q_left[30]), .Y(n5199) );
NAND2X6TS U748 ( .A(n5317), .B(n4672), .Y(n5551) );
NOR2X1TS U749 ( .A(n1636), .B(n3631), .Y(n5187) );
CLKINVX2TS U750 ( .A(n5188), .Y(n2048) );
OR2X2TS U751 ( .A(n2046), .B(n3826), .Y(n886) );
NOR2X1TS U752 ( .A(DP_OP_168J30_122_4811_n1949), .B(n4725), .Y(n4728) );
NAND2X2TS U753 ( .A(n1636), .B(n3631), .Y(n5188) );
AOI21X1TS U754 ( .A0(n1642), .A1(n884), .B0(n1635), .Y(n1636) );
CLKINVX1TS U755 ( .A(n1640), .Y(n1635) );
NAND2XLTS U756 ( .A(n884), .B(n1640), .Y(n1641) );
OAI21X2TS U757 ( .A0(n1651), .A1(n1648), .B0(n1649), .Y(n1642) );
NAND2X1TS U758 ( .A(n1629), .B(n1628), .Y(n1649) );
NAND2X1TS U759 ( .A(Sgf_normalized_result[44]), .B(n5444), .Y(n5443) );
NOR2X1TS U760 ( .A(DP_OP_168J30_122_4811_n1953), .B(n4710), .Y(n4713) );
NAND2X1TS U761 ( .A(n1634), .B(n1633), .Y(n1640) );
NOR2X1TS U762 ( .A(n2039), .B(n3608), .Y(n5139) );
NAND2X1TS U763 ( .A(n2040), .B(n3611), .Y(n5148) );
NAND2X1TS U764 ( .A(DP_OP_168J30_122_4811_n217), .B(n1945), .Y(n1656) );
NAND2X1TS U765 ( .A(Sgf_normalized_result[42]), .B(n5441), .Y(n5440) );
NOR2X1TS U766 ( .A(DP_OP_168J30_122_4811_n1955), .B(n5268), .Y(n5276) );
XNOR2X1TS U767 ( .A(n1683), .B(n1682), .Y(n2039) );
XNOR2X1TS U768 ( .A(n1673), .B(n1672), .Y(n2040) );
OAI21X2TS U769 ( .A0(n1274), .A1(n1679), .B0(n1680), .Y(n1672) );
NOR2X1TS U770 ( .A(DP_OP_168J30_122_4811_n220), .B(
DP_OP_168J30_122_4811_n224), .Y(n1662) );
NAND2X1TS U771 ( .A(DP_OP_168J30_122_4811_n225), .B(n1371), .Y(n1671) );
NOR2X1TS U772 ( .A(n942), .B(n5255), .Y(n5262) );
NAND2X1TS U773 ( .A(Sgf_normalized_result[40]), .B(n5436), .Y(n5438) );
CMPR32X2TS U774 ( .A(DP_OP_168J30_122_4811_n237), .B(
DP_OP_168J30_122_4811_n242), .C(n1687), .CO(n1682), .S(n2038) );
NOR2X1TS U775 ( .A(n2033), .B(n3630), .Y(n5101) );
CMPR42X1TS U776 ( .A(DP_OP_168J30_122_4811_n228), .B(
DP_OP_168J30_122_4811_n229), .C(DP_OP_168J30_122_4811_n1946), .D(
DP_OP_168J30_122_4811_n770), .ICI(DP_OP_168J30_122_4811_n230), .S(
DP_OP_168J30_122_4811_n225), .ICO(DP_OP_168J30_122_4811_n223), .CO(
DP_OP_168J30_122_4811_n224) );
NAND2X1TS U777 ( .A(Sgf_normalized_result[38]), .B(n5434), .Y(n5433) );
CMPR32X2TS U778 ( .A(DP_OP_168J30_122_4811_n251), .B(
DP_OP_168J30_122_4811_n258), .C(n1698), .CO(n1692), .S(n2035) );
INVX2TS U779 ( .A(Sgf_operation_ODD1_Q_left[50]), .Y(
DP_OP_168J30_122_4811_n1946) );
NOR2X1TS U780 ( .A(n2029), .B(n3634), .Y(n4952) );
XOR2X1TS U781 ( .A(n2061), .B(n2060), .Y(Sgf_operation_ODD1_Q_left[49]) );
CMPR32X2TS U782 ( .A(DP_OP_168J30_122_4811_n276), .B(
DP_OP_168J30_122_4811_n284), .C(n1711), .CO(n1705), .S(n2032) );
AOI21X1TS U783 ( .A0(n3626), .A1(n864), .B0(n1353), .Y(n2061) );
CMPR32X2TS U784 ( .A(DP_OP_168J30_122_4811_n285), .B(
DP_OP_168J30_122_4811_n293), .C(n1714), .CO(n1711), .S(n2030) );
NOR2X1TS U785 ( .A(n2026), .B(n4306), .Y(n4966) );
CMPR32X2TS U786 ( .A(n4666), .B(n4665), .C(n4664), .CO(
DP_OP_168J30_122_4811_n247), .S(DP_OP_168J30_122_4811_n248) );
XOR2X1TS U787 ( .A(n2066), .B(n2065), .Y(Sgf_operation_ODD1_Q_left[47]) );
OAI21X1TS U788 ( .A0(n2066), .A1(n2062), .B0(n2063), .Y(n3626) );
CMPR32X2TS U789 ( .A(n3732), .B(n3731), .C(DP_OP_168J30_122_4811_n271), .CO(
DP_OP_168J30_122_4811_n263), .S(DP_OP_168J30_122_4811_n264) );
NAND2X1TS U790 ( .A(DP_OP_168J30_122_4811_n3881), .B(n1344), .Y(n2063) );
OAI21X1TS U791 ( .A0(n3623), .A1(n3619), .B0(n3620), .Y(n2069) );
NAND2X1TS U792 ( .A(DP_OP_168J30_122_4811_n3885), .B(
DP_OP_168J30_122_4811_n3889), .Y(n3620) );
NAND2X1TS U793 ( .A(DP_OP_168J30_122_4811_n3882), .B(n1338), .Y(n2067) );
NOR2X1TS U794 ( .A(n4992), .B(n4988), .Y(n4983) );
CMPR32X2TS U795 ( .A(n1355), .B(n1350), .C(n1349), .CO(n1351), .S(n1344) );
CMPR32X2TS U796 ( .A(DP_OP_168J30_122_4811_n339), .B(
DP_OP_168J30_122_4811_n350), .C(n1953), .CO(n1947), .S(n2017) );
NOR2X1TS U797 ( .A(n5008), .B(n5004), .Y(n4999) );
CMPR32X2TS U798 ( .A(n4621), .B(n4620), .C(n4619), .CO(
DP_OP_168J30_122_4811_n301), .S(DP_OP_168J30_122_4811_n302) );
AOI21X1TS U799 ( .A0(n1738), .A1(n870), .B0(n1610), .Y(n1734) );
NAND2X1TS U800 ( .A(DP_OP_168J30_122_4811_n2207), .B(n1609), .Y(n1736) );
NAND2X1TS U801 ( .A(DP_OP_168J30_122_4811_n3911), .B(n1319), .Y(n3651) );
CMPR32X2TS U802 ( .A(DP_OP_168J30_122_4811_n420), .B(
DP_OP_168J30_122_4811_n434), .C(n1978), .CO(n1974), .S(n2008) );
CMPR32X2TS U803 ( .A(DP_OP_168J30_122_4811_n435), .B(
DP_OP_168J30_122_4811_n449), .C(n1984), .CO(n1978), .S(n2007) );
CMPR32X2TS U804 ( .A(n4556), .B(n4555), .C(n4554), .CO(
DP_OP_168J30_122_4811_n373), .S(DP_OP_168J30_122_4811_n374) );
AO21XLTS U805 ( .A0(n1286), .A1(n2115), .B0(n1285), .Y(n3681) );
CMPR42X1TS U806 ( .A(DP_OP_168J30_122_4811_n467), .B(
DP_OP_168J30_122_4811_n453), .C(Sgf_operation_ODD1_Q_left[30]), .D(
DP_OP_168J30_122_4811_n791), .ICI(DP_OP_168J30_122_4811_n463), .S(
DP_OP_168J30_122_4811_n450), .ICO(DP_OP_168J30_122_4811_n448), .CO(
DP_OP_168J30_122_4811_n449) );
NAND2X1TS U807 ( .A(DP_OP_168J30_122_4811_n3986), .B(
DP_OP_168J30_122_4811_n3977), .Y(n2117) );
NAND2X1TS U808 ( .A(DP_OP_168J30_122_4811_n3987), .B(n1284), .Y(n2122) );
AOI222X1TS U809 ( .A0(n2358), .A1(n4630), .B0(n2356), .B1(n4604), .C0(n2353),
.C1(n2410), .Y(n2320) );
CMPR32X2TS U810 ( .A(DP_OP_168J30_122_4811_n558), .B(
DP_OP_168J30_122_4811_n571), .C(n1745), .CO(n1739), .S(n1940) );
NOR2X1TS U811 ( .A(n3717), .B(n1917), .Y(n4928) );
AOI222X1TS U812 ( .A0(n2406), .A1(n4656), .B0(n2434), .B1(n2407), .C0(n2431),
.C1(n4630), .Y(n2404) );
AOI222X1TS U813 ( .A0(n4315), .A1(n4314), .B0(n790), .B1(n4312), .C0(n4608),
.C1(n2734), .Y(n4316) );
NAND2X1TS U814 ( .A(n2547), .B(n4313), .Y(n2176) );
INVX2TS U815 ( .A(n982), .Y(n3527) );
NOR2X1TS U816 ( .A(DP_OP_168J30_122_4811_n4086), .B(n1167), .Y(n1688) );
INVX2TS U817 ( .A(n992), .Y(n3531) );
CMPR32X2TS U818 ( .A(Op_MY[50]), .B(Op_MY[51]), .C(n991), .CO(n985), .S(n992) );
NOR2X1TS U819 ( .A(n4605), .B(n4616), .Y(n2195) );
INVX2TS U820 ( .A(n996), .Y(n3535) );
OA21XLTS U821 ( .A0(n2201), .A1(n2151), .B0(n2202), .Y(n929) );
AO21XLTS U822 ( .A0(n2157), .A1(n883), .B0(n981), .Y(n959) );
CLKINVX1TS U823 ( .A(n2201), .Y(n2203) );
CMPR32X2TS U824 ( .A(Op_MY[49]), .B(Op_MY[50]), .C(n995), .CO(n991), .S(n996) );
INVX2TS U825 ( .A(n1000), .Y(n3767) );
INVX2TS U826 ( .A(n1004), .Y(n3760) );
CMPR32X2TS U827 ( .A(DP_OP_168J30_122_4811_n692), .B(
DP_OP_168J30_122_4811_n695), .C(n1829), .CO(n1822), .S(n1922) );
CMPR32X2TS U828 ( .A(Op_MY[48]), .B(Op_MY[49]), .C(n999), .CO(n995), .S(
n1000) );
NAND2X1TS U829 ( .A(DP_OP_168J30_122_4811_n2402), .B(n1572), .Y(n1890) );
INVX2TS U830 ( .A(n1009), .Y(n3756) );
CMPR32X2TS U831 ( .A(Op_MY[47]), .B(Op_MY[48]), .C(n1003), .CO(n999), .S(
n1004) );
CMPR32X2TS U832 ( .A(DP_OP_168J30_122_4811_n710), .B(
DP_OP_168J30_122_4811_n717), .C(n1844), .CO(n1834), .S(n1918) );
INVX2TS U833 ( .A(n1013), .Y(n3548) );
CMPR32X2TS U834 ( .A(Op_MY[46]), .B(Op_MY[19]), .C(n2138), .CO(n2137), .S(
n3995) );
CMPR32X2TS U835 ( .A(Op_MY[46]), .B(Op_MY[47]), .C(n1008), .CO(n1003), .S(
n1009) );
INVX2TS U836 ( .A(n2237), .Y(n4163) );
CMPR32X2TS U837 ( .A(DP_OP_168J30_122_4811_n726), .B(
DP_OP_168J30_122_4811_n732), .C(n1855), .CO(n1850), .S(n1915) );
CMPR32X2TS U838 ( .A(Op_MY[45]), .B(Op_MY[46]), .C(n1012), .CO(n1008), .S(
n1013) );
CMPR42X1TS U839 ( .A(DP_OP_168J30_122_4811_n2417), .B(
DP_OP_168J30_122_4811_n2424), .C(DP_OP_168J30_122_4811_n2919), .D(
DP_OP_168J30_122_4811_n2946), .ICI(DP_OP_168J30_122_4811_n2425), .S(
DP_OP_168J30_122_4811_n2414), .ICO(DP_OP_168J30_122_4811_n2412), .CO(
DP_OP_168J30_122_4811_n2413) );
CMPR42X1TS U840 ( .A(DP_OP_168J30_122_4811_n2396), .B(
DP_OP_168J30_122_4811_n2407), .C(DP_OP_168J30_122_4811_n2863), .D(
DP_OP_168J30_122_4811_n2403), .ICI(DP_OP_168J30_122_4811_n2890), .S(
DP_OP_168J30_122_4811_n2393), .ICO(DP_OP_168J30_122_4811_n2391), .CO(
DP_OP_168J30_122_4811_n2392) );
CMPR32X2TS U841 ( .A(Op_MY[44]), .B(Op_MY[45]), .C(n1016), .CO(n1012), .S(
n1017) );
CMPR42X1TS U842 ( .A(DP_OP_168J30_122_4811_n2429), .B(
DP_OP_168J30_122_4811_n2920), .C(DP_OP_168J30_122_4811_n2437), .D(
DP_OP_168J30_122_4811_n2947), .ICI(DP_OP_168J30_122_4811_n2438), .S(
DP_OP_168J30_122_4811_n2426), .ICO(DP_OP_168J30_122_4811_n2424), .CO(
DP_OP_168J30_122_4811_n2425) );
INVX2TS U843 ( .A(n1026), .Y(n3752) );
INVX2TS U844 ( .A(n1375), .Y(n3154) );
CMPR32X2TS U845 ( .A(n1867), .B(n1866), .C(DP_OP_168J30_122_4811_n740), .CO(
n1860), .S(n1912) );
CMPR32X2TS U846 ( .A(Op_MY[43]), .B(Op_MY[44]), .C(n1021), .CO(n1016), .S(
n1022) );
CMPR32X4TS U847 ( .A(Op_MY[12]), .B(Op_MY[39]), .C(n2143), .CO(n2142), .S(
n2725) );
CMPR42X1TS U848 ( .A(DP_OP_168J30_122_4811_n2442), .B(
DP_OP_168J30_122_4811_n2921), .C(DP_OP_168J30_122_4811_n2450), .D(
DP_OP_168J30_122_4811_n2948), .ICI(DP_OP_168J30_122_4811_n2451), .S(
DP_OP_168J30_122_4811_n2439), .ICO(DP_OP_168J30_122_4811_n2437), .CO(
DP_OP_168J30_122_4811_n2438) );
INVX2TS U849 ( .A(n1380), .Y(n3136) );
CMPR32X2TS U850 ( .A(Op_MY[42]), .B(Op_MY[43]), .C(n1025), .CO(n1021), .S(
n1026) );
CMPR32X4TS U851 ( .A(Op_MY[11]), .B(Op_MY[38]), .C(n2144), .CO(n2143), .S(
n2728) );
CMPR42X1TS U852 ( .A(DP_OP_168J30_122_4811_n2455), .B(
DP_OP_168J30_122_4811_n2922), .C(DP_OP_168J30_122_4811_n2463), .D(
DP_OP_168J30_122_4811_n2949), .ICI(DP_OP_168J30_122_4811_n2464), .S(
DP_OP_168J30_122_4811_n2452), .ICO(DP_OP_168J30_122_4811_n2450), .CO(
DP_OP_168J30_122_4811_n2451) );
CMPR32X2TS U853 ( .A(DP_OP_168J30_122_4811_n747), .B(
DP_OP_168J30_122_4811_n751), .C(n1871), .CO(n1867), .S(n1910) );
CMPR32X2TS U854 ( .A(Op_MY[41]), .B(Op_MY[42]), .C(n1029), .CO(n1025), .S(
n1030) );
CMPR32X2TS U855 ( .A(Op_MY[25]), .B(Op_MY[26]), .C(n1384), .CO(n1379), .S(
n1385) );
CMPR42X1TS U856 ( .A(DP_OP_168J30_122_4811_n2468), .B(
DP_OP_168J30_122_4811_n2923), .C(DP_OP_168J30_122_4811_n2474), .D(
DP_OP_168J30_122_4811_n2950), .ICI(DP_OP_168J30_122_4811_n2475), .S(
DP_OP_168J30_122_4811_n2465), .ICO(DP_OP_168J30_122_4811_n2463), .CO(
DP_OP_168J30_122_4811_n2464) );
INVX2TS U857 ( .A(n1390), .Y(n3786) );
AOI222X1TS U858 ( .A0(n4262), .A1(n4279), .B0(n4360), .B1(n4303), .C0(n2690),
.C1(n4477), .Y(n4263) );
CMPR32X2TS U859 ( .A(n1882), .B(n1881), .C(DP_OP_168J30_122_4811_n757), .CO(
n1875), .S(n1907) );
CMPR32X2TS U860 ( .A(Op_MY[24]), .B(Op_MY[25]), .C(n1389), .CO(n1384), .S(
n1390) );
CMPR32X2TS U861 ( .A(Op_MY[40]), .B(Op_MY[41]), .C(n1033), .CO(n1029), .S(
n1034) );
CMPR32X2TS U862 ( .A(Op_MY[23]), .B(Op_MY[24]), .C(n1393), .CO(n1389), .S(
n1394) );
CMPR32X2TS U863 ( .A(Op_MY[39]), .B(Op_MY[40]), .C(n1038), .CO(n1033), .S(
n1039) );
CMPR42X1TS U864 ( .A(DP_OP_168J30_122_4811_n2870), .B(
DP_OP_168J30_122_4811_n2482), .C(DP_OP_168J30_122_4811_n2488), .D(
DP_OP_168J30_122_4811_n2897), .ICI(DP_OP_168J30_122_4811_n2489), .S(
DP_OP_168J30_122_4811_n2479), .ICO(DP_OP_168J30_122_4811_n2477), .CO(
DP_OP_168J30_122_4811_n2478) );
INVX2TS U865 ( .A(n1398), .Y(n3780) );
CMPR32X2TS U866 ( .A(n2128), .B(n2127), .C(n2126), .CO(
DP_OP_168J30_122_4811_n760), .S(n1888) );
ADDHXLTS U867 ( .A(n1195), .B(n2053), .CO(DP_OP_168J30_122_4811_n762), .S(
n1887) );
CMPR32X2TS U868 ( .A(Op_MY[22]), .B(Op_MY[23]), .C(n1397), .CO(n1393), .S(
n1398) );
CMPR32X2TS U869 ( .A(Op_MY[38]), .B(Op_MY[39]), .C(n1042), .CO(n1038), .S(
n1043) );
CMPR42X1TS U870 ( .A(DP_OP_168J30_122_4811_n2501), .B(
DP_OP_168J30_122_4811_n2926), .C(DP_OP_168J30_122_4811_n2506), .D(
DP_OP_168J30_122_4811_n2953), .ICI(DP_OP_168J30_122_4811_n2507), .S(
DP_OP_168J30_122_4811_n2498), .ICO(DP_OP_168J30_122_4811_n2496), .CO(
DP_OP_168J30_122_4811_n2497) );
INVX2TS U871 ( .A(n1406), .Y(n4461) );
AOI222X1TS U872 ( .A0(n2702), .A1(n4279), .B0(n4405), .B1(n4303), .C0(n2721),
.C1(n4477), .Y(n4185) );
AOI222X1TS U873 ( .A0(n2702), .A1(n4283), .B0(n4405), .B1(n4279), .C0(n2721),
.C1(n4303), .Y(n4120) );
CMPR32X2TS U874 ( .A(Op_MY[37]), .B(Op_MY[38]), .C(n1046), .CO(n1042), .S(
n1047) );
CMPR32X2TS U875 ( .A(Op_MY[21]), .B(Op_MY[22]), .C(n1401), .CO(n1397), .S(
n1402) );
CMPR42X1TS U876 ( .A(DP_OP_168J30_122_4811_n2511), .B(
DP_OP_168J30_122_4811_n2927), .C(DP_OP_168J30_122_4811_n2516), .D(
DP_OP_168J30_122_4811_n2954), .ICI(DP_OP_168J30_122_4811_n2517), .S(
DP_OP_168J30_122_4811_n2508), .ICO(DP_OP_168J30_122_4811_n2506), .CO(
DP_OP_168J30_122_4811_n2507) );
CMPR42X1TS U877 ( .A(DP_OP_168J30_122_4811_n2816), .B(
DP_OP_168J30_122_4811_n2484), .C(DP_OP_168J30_122_4811_n2491), .D(
DP_OP_168J30_122_4811_n2843), .ICI(DP_OP_168J30_122_4811_n2492), .S(
DP_OP_168J30_122_4811_n2482), .ICO(DP_OP_168J30_122_4811_n2480), .CO(
DP_OP_168J30_122_4811_n2481) );
CMPR42X1TS U878 ( .A(DP_OP_168J30_122_4811_n2872), .B(
DP_OP_168J30_122_4811_n2503), .C(DP_OP_168J30_122_4811_n2509), .D(
DP_OP_168J30_122_4811_n2899), .ICI(DP_OP_168J30_122_4811_n2510), .S(
DP_OP_168J30_122_4811_n2501), .ICO(DP_OP_168J30_122_4811_n2499), .CO(
DP_OP_168J30_122_4811_n2500) );
CMPR32X2TS U879 ( .A(Op_MY[20]), .B(Op_MY[21]), .C(n1405), .CO(n1401), .S(
n1406) );
CMPR32X2TS U880 ( .A(Op_MY[36]), .B(Op_MY[37]), .C(n1050), .CO(n1046), .S(
n1051) );
INVX2TS U881 ( .A(n1410), .Y(n4449) );
MXI2X1TS U882 ( .A(intadd_76_n17), .B(intadd_76_n16), .S0(intadd_76_n26),
.Y(n2145) );
CMPR32X2TS U883 ( .A(Op_MY[19]), .B(Op_MY[20]), .C(n1409), .CO(n1405), .S(
n1410) );
CMPR32X2TS U884 ( .A(Op_MY[35]), .B(Op_MY[36]), .C(n1054), .CO(n1050), .S(
n1055) );
CMPR42X1TS U885 ( .A(DP_OP_168J30_122_4811_n2929), .B(
DP_OP_168J30_122_4811_n2531), .C(DP_OP_168J30_122_4811_n2534), .D(
DP_OP_168J30_122_4811_n2956), .ICI(DP_OP_168J30_122_4811_n2535), .S(
DP_OP_168J30_122_4811_n2528), .ICO(DP_OP_168J30_122_4811_n2526), .CO(
DP_OP_168J30_122_4811_n2527) );
CMPR42X1TS U886 ( .A(DP_OP_168J30_122_4811_n2874), .B(
DP_OP_168J30_122_4811_n2523), .C(DP_OP_168J30_122_4811_n2529), .D(
DP_OP_168J30_122_4811_n2901), .ICI(DP_OP_168J30_122_4811_n2530), .S(
DP_OP_168J30_122_4811_n2521), .ICO(DP_OP_168J30_122_4811_n2519), .CO(
DP_OP_168J30_122_4811_n2520) );
AOI222X1TS U887 ( .A0(n4271), .A1(n4283), .B0(n4270), .B1(n4279), .C0(n4269),
.C1(n4303), .Y(n3904) );
AOI222X1TS U888 ( .A0(n4271), .A1(n4279), .B0(n4270), .B1(n4303), .C0(n4269),
.C1(n4477), .Y(n1216) );
CMPR32X2TS U889 ( .A(Op_MY[34]), .B(Op_MY[35]), .C(n1094), .CO(n1054), .S(
n1095) );
CMPR32X2TS U890 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(n1413), .CO(n1409), .S(
n1414) );
CMPR42X1TS U891 ( .A(DP_OP_168J30_122_4811_n2875), .B(
DP_OP_168J30_122_4811_n2533), .C(DP_OP_168J30_122_4811_n2537), .D(
DP_OP_168J30_122_4811_n2902), .ICI(DP_OP_168J30_122_4811_n2538), .S(
DP_OP_168J30_122_4811_n2531), .ICO(DP_OP_168J30_122_4811_n2529), .CO(
DP_OP_168J30_122_4811_n2530) );
CMPR42X1TS U892 ( .A(DP_OP_168J30_122_4811_n2930), .B(
DP_OP_168J30_122_4811_n2539), .C(DP_OP_168J30_122_4811_n2542), .D(
DP_OP_168J30_122_4811_n2957), .ICI(DP_OP_168J30_122_4811_n2543), .S(
DP_OP_168J30_122_4811_n2536), .ICO(DP_OP_168J30_122_4811_n2534), .CO(
DP_OP_168J30_122_4811_n2535) );
CMPR32X2TS U893 ( .A(Op_MY[33]), .B(Op_MY[34]), .C(n1101), .CO(n1094), .S(
n1102) );
CMPR32X2TS U894 ( .A(Op_MY[17]), .B(Op_MY[18]), .C(n1417), .CO(n1413), .S(
n1418) );
CMPR42X1TS U895 ( .A(DP_OP_168J30_122_4811_n2876), .B(
DP_OP_168J30_122_4811_n2541), .C(DP_OP_168J30_122_4811_n2545), .D(
DP_OP_168J30_122_4811_n2903), .ICI(DP_OP_168J30_122_4811_n2546), .S(
DP_OP_168J30_122_4811_n2539), .ICO(DP_OP_168J30_122_4811_n2537), .CO(
DP_OP_168J30_122_4811_n2538) );
CMPR42X1TS U896 ( .A(DP_OP_168J30_122_4811_n2931), .B(
DP_OP_168J30_122_4811_n2547), .C(DP_OP_168J30_122_4811_n2550), .D(
DP_OP_168J30_122_4811_n2958), .ICI(DP_OP_168J30_122_4811_n2551), .S(
DP_OP_168J30_122_4811_n2544), .ICO(DP_OP_168J30_122_4811_n2542), .CO(
DP_OP_168J30_122_4811_n2543) );
AFCSHCONX2TS U897 ( .B(Op_MY[7]), .A(Op_MY[34]), .CI0(intadd_76_n23), .CI1(
intadd_76_n22), .CS(intadd_76_n26), .S(DP_OP_168J30_122_4811_n1861),
.CO0N(intadd_76_n21), .CO1N(intadd_76_n20) );
CLKMX2X2TS U898 ( .A(intadd_76_n29), .B(intadd_76_n28), .S0(intadd_76_n36),
.Y(intadd_76_n26) );
CMPR32X2TS U899 ( .A(Op_MY[16]), .B(Op_MY[17]), .C(n1422), .CO(n1417), .S(
n1423) );
CMPR32X2TS U900 ( .A(Op_MY[32]), .B(Op_MY[33]), .C(n1108), .CO(n1101), .S(
n1109) );
AOI222X1TS U901 ( .A0(n1128), .A1(n3872), .B0(n1125), .B1(n3516), .C0(n1035),
.C1(Op_MY[27]), .Y(n1123) );
AOI222X1TS U902 ( .A0(n3598), .A1(n3873), .B0(n3596), .B1(n3872), .C0(n3594),
.C1(n3516), .Y(n1085) );
AOI222X1TS U903 ( .A0(n1128), .A1(n3593), .B0(n1125), .B1(n3873), .C0(n1035),
.C1(n3872), .Y(n1118) );
CMPR32X2TS U904 ( .A(Op_MY[15]), .B(Op_MY[16]), .C(n1426), .CO(n1422), .S(
n1427) );
CMPR32X2TS U905 ( .A(Op_MY[31]), .B(Op_MY[32]), .C(n1070), .CO(n1108), .S(
n1071) );
NOR2X1TS U906 ( .A(DP_OP_168J30_122_4811_n2573), .B(n1547), .Y(n3814) );
CMPR42X1TS U907 ( .A(DP_OP_168J30_122_4811_n2933), .B(
DP_OP_168J30_122_4811_n2561), .C(DP_OP_168J30_122_4811_n2564), .D(
DP_OP_168J30_122_4811_n2960), .ICI(DP_OP_168J30_122_4811_n2565), .S(
DP_OP_168J30_122_4811_n2559), .ICO(DP_OP_168J30_122_4811_n2557), .CO(
DP_OP_168J30_122_4811_n2558) );
AOI222X1TS U908 ( .A0(n1128), .A1(n3873), .B0(n1125), .B1(n3872), .C0(n1035),
.C1(n3516), .Y(n1120) );
CMPR32X2TS U909 ( .A(Op_MY[14]), .B(Op_MY[15]), .C(n1431), .CO(n1426), .S(
n1432) );
CMPR32X2TS U910 ( .A(Op_MY[30]), .B(Op_MY[31]), .C(n1079), .CO(n1070), .S(
n1080) );
CMPR42X1TS U911 ( .A(DP_OP_168J30_122_4811_n2934), .B(
DP_OP_168J30_122_4811_n2568), .C(DP_OP_168J30_122_4811_n2571), .D(
DP_OP_168J30_122_4811_n2961), .ICI(DP_OP_168J30_122_4811_n2572), .S(
DP_OP_168J30_122_4811_n2566), .ICO(DP_OP_168J30_122_4811_n2564), .CO(
DP_OP_168J30_122_4811_n2565) );
CMPR32X2TS U912 ( .A(Op_MY[13]), .B(Op_MY[14]), .C(n1435), .CO(n1431), .S(
n1436) );
CMPR32X2TS U913 ( .A(Op_MY[29]), .B(Op_MY[30]), .C(n1083), .CO(n1079), .S(
n1084) );
CMPR42X1TS U914 ( .A(DP_OP_168J30_122_4811_n2935), .B(
DP_OP_168J30_122_4811_n2575), .C(DP_OP_168J30_122_4811_n2576), .D(
DP_OP_168J30_122_4811_n2962), .ICI(DP_OP_168J30_122_4811_n2577), .S(
DP_OP_168J30_122_4811_n2573), .ICO(DP_OP_168J30_122_4811_n2571), .CO(
DP_OP_168J30_122_4811_n2572) );
CMPR32X2TS U915 ( .A(Op_MY[28]), .B(Op_MY[29]), .C(n1058), .CO(n1083), .S(
n1059) );
CMPR32X2TS U916 ( .A(Op_MY[12]), .B(Op_MY[13]), .C(n1439), .CO(n1435), .S(
n1440) );
OAI21X1TS U917 ( .A0(n1207), .A1(n1210), .B0(n1208), .Y(n1187) );
CMPR32X2TS U918 ( .A(Op_MY[11]), .B(Op_MY[12]), .C(n1443), .CO(n1439), .S(
n1444) );
NOR2X1TS U919 ( .A(n1540), .B(n1539), .Y(n4148) );
CMPR42X1TS U920 ( .A(DP_OP_168J30_122_4811_n2585), .B(
DP_OP_168J30_122_4811_n2937), .C(DP_OP_168J30_122_4811_n2588), .D(
DP_OP_168J30_122_4811_n2964), .ICI(DP_OP_168J30_122_4811_n2586), .S(
DP_OP_168J30_122_4811_n2583), .ICO(DP_OP_168J30_122_4811_n2581), .CO(
DP_OP_168J30_122_4811_n2582) );
ADDHXLTS U921 ( .A(Op_MY[28]), .B(Op_MY[27]), .CO(n1058), .S(n1065) );
CMPR32X2TS U922 ( .A(Op_MY[10]), .B(Op_MY[11]), .C(n1447), .CO(n1443), .S(
n1448) );
NOR2X1TS U923 ( .A(n1538), .B(n1537), .Y(n4425) );
CMPR32X2TS U924 ( .A(Op_MY[9]), .B(Op_MY[10]), .C(n1451), .CO(n1447), .S(
n1452) );
CMPR32X2TS U925 ( .A(Op_MY[8]), .B(Op_MY[9]), .C(n1455), .CO(n1451), .S(
n1456) );
ADDHXLTS U926 ( .A(n1478), .B(n1477), .CO(n4054), .S(n1499) );
NOR2X1TS U927 ( .A(n1533), .B(n1532), .Y(n4348) );
CMPR32X2TS U928 ( .A(Op_MY[7]), .B(Op_MY[8]), .C(n1493), .CO(n1455), .S(
n1494) );
CMPR32X2TS U929 ( .A(Op_MY[6]), .B(Op_MY[7]), .C(n1500), .CO(n1493), .S(
n1501) );
CMPR32X2TS U930 ( .A(Op_MY[5]), .B(Op_MY[6]), .C(n1507), .CO(n1500), .S(
n1508) );
CMPR32X2TS U931 ( .A(Op_MY[3]), .B(Op_MY[4]), .C(n1479), .CO(n1470), .S(
n1480) );
CMPR32X2TS U932 ( .A(Op_MY[2]), .B(Op_MY[3]), .C(n1483), .CO(n1479), .S(
n1484) );
ADDHXLTS U933 ( .A(Op_MY[1]), .B(Op_MY[0]), .CO(n1374), .S(n1196) );
NOR2XLTS U934 ( .A(n1260), .B(n1263), .Y(n1266) );
OAI21XLTS U935 ( .A0(n2530), .A1(n2529), .B0(n2528), .Y(n2535) );
OAI21XLTS U936 ( .A0(n1262), .A1(n1268), .B0(n1269), .Y(n963) );
NOR2X1TS U937 ( .A(n4616), .B(n4615), .Y(n2201) );
OAI21XLTS U938 ( .A0(n4626), .A1(n3243), .B0(n4625), .Y(n4627) );
NOR2X1TS U939 ( .A(n4008), .B(n4605), .Y(n2295) );
OAI21XLTS U940 ( .A0(n4267), .A1(n2576), .B0(n2563), .Y(n2564) );
OAI21XLTS U941 ( .A0(n3571), .A1(n3245), .B0(n3247), .Y(n3248) );
OAI21XLTS U942 ( .A0(n3737), .A1(n3243), .B0(n3254), .Y(n3255) );
OAI21XLTS U943 ( .A0(n932), .A1(n4011), .B0(n3745), .Y(n3746) );
OAI21XLTS U944 ( .A0(n933), .A1(n2313), .B0(n2283), .Y(n2284) );
OAI21XLTS U945 ( .A0(n3575), .A1(n3286), .B0(n3291), .Y(n3292) );
OAI21XLTS U946 ( .A0(n3575), .A1(n3341), .B0(n3347), .Y(n3348) );
OAI21XLTS U947 ( .A0(n2313), .A1(n4366), .B0(n2307), .Y(n2308) );
OAI21XLTS U948 ( .A0(n4383), .A1(n4365), .B0(n3613), .Y(n3614) );
OR2X1TS U949 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n882) );
OAI21XLTS U950 ( .A0(n3579), .A1(n4643), .B0(n3182), .Y(n3187) );
OAI21XLTS U951 ( .A0(n3743), .A1(n3284), .B0(n3279), .Y(n3280) );
OAI21XLTS U952 ( .A0(n3548), .A1(n3189), .B0(n3378), .Y(n3379) );
OAI21XLTS U953 ( .A0(n3756), .A1(n1174), .B0(n3544), .Y(n3545) );
OAI21XLTS U954 ( .A0(n3571), .A1(n3521), .B0(n3496), .Y(n3497) );
OAI21XLTS U955 ( .A0(n4611), .A1(n2313), .B0(n2293), .Y(n2294) );
OAI21XLTS U956 ( .A0(n3760), .A1(n1275), .B0(n3477), .Y(n3478) );
OAI21XLTS U957 ( .A0(n4011), .A1(n4267), .B0(n2210), .Y(n2211) );
OAI21XLTS U958 ( .A0(n838), .A1(n2695), .B0(n2709), .Y(n2710) );
OAI21XLTS U959 ( .A0(n3136), .A1(n2852), .B0(n1607), .Y(n1608) );
OAI21XLTS U960 ( .A0(n835), .A1(n2576), .B0(n2548), .Y(n2549) );
OAI21XLTS U961 ( .A0(n4626), .A1(n3600), .B0(n3591), .Y(n3592) );
OAI21XLTS U962 ( .A0(n3773), .A1(n2968), .B0(n2948), .Y(n2949) );
OAI21XLTS U963 ( .A0(n3795), .A1(n3026), .B0(n2998), .Y(n2999) );
OAI21XLTS U964 ( .A0(n3776), .A1(n2968), .B0(n2944), .Y(n2945) );
OAI21XLTS U965 ( .A0(n4011), .A1(n4366), .B0(n2227), .Y(n2228) );
OAI21XLTS U966 ( .A0(n4011), .A1(n4325), .B0(n2214), .Y(n2215) );
OAI21XLTS U967 ( .A0(n3154), .A1(n1523), .B0(n1377), .Y(n1378) );
OAI21XLTS U968 ( .A0(n3527), .A1(n3243), .B0(n1342), .Y(n1343) );
OAI21XLTS U969 ( .A0(n3767), .A1(n3243), .B0(n3230), .Y(n3231) );
OAI21XLTS U970 ( .A0(n3767), .A1(n3284), .B0(n3264), .Y(n3265) );
OAI21XLTS U971 ( .A0(n3575), .A1(n4643), .B0(n3176), .Y(n3180) );
OAI21XLTS U972 ( .A0(n3767), .A1(n3446), .B0(n3427), .Y(n3428) );
OAI21XLTS U973 ( .A0(n4011), .A1(n4611), .B0(n2193), .Y(n2194) );
OAI21XLTS U974 ( .A0(n4011), .A1(n840), .B0(n2199), .Y(n2200) );
OAI21XLTS U975 ( .A0(n1811), .A1(n1802), .B0(n1803), .Y(n1595) );
OAI21XLTS U976 ( .A0(n1359), .A1(n3339), .B0(n1303), .Y(n1304) );
OAI21XLTS U977 ( .A0(n3531), .A1(n3339), .B0(n3315), .Y(n3316) );
OAI21XLTS U978 ( .A0(n1359), .A1(n3446), .B0(n1291), .Y(n1292) );
CMPR42X1TS U979 ( .A(DP_OP_168J30_122_4811_n4515), .B(
DP_OP_168J30_122_4811_n4178), .C(DP_OP_168J30_122_4811_n4181), .D(
DP_OP_168J30_122_4811_n4541), .ICI(DP_OP_168J30_122_4811_n4182), .S(
DP_OP_168J30_122_4811_n4176), .ICO(DP_OP_168J30_122_4811_n4174), .CO(
DP_OP_168J30_122_4811_n4175) );
OR2X1TS U980 ( .A(DP_OP_168J30_122_4811_n2353), .B(
DP_OP_168J30_122_4811_n2342), .Y(n827) );
INVX2TS U981 ( .A(n1740), .Y(n1742) );
INVX2TS U982 ( .A(n1394), .Y(n3776) );
OAI21XLTS U983 ( .A0(n4446), .A1(n4435), .B0(n3790), .Y(n3791) );
OAI21XLTS U984 ( .A0(n3656), .A1(n2091), .B0(n3651), .Y(n2080) );
NOR2X1TS U985 ( .A(n1629), .B(n1628), .Y(n1648) );
NOR2X1TS U986 ( .A(DP_OP_168J30_122_4811_n4097), .B(n1166), .Y(n1693) );
OR2X1TS U987 ( .A(DP_OP_168J30_122_4811_n2207), .B(n1609), .Y(n870) );
CMPR42X1TS U988 ( .A(DP_OP_168J30_122_4811_n2815), .B(
DP_OP_168J30_122_4811_n2473), .C(DP_OP_168J30_122_4811_n2480), .D(
DP_OP_168J30_122_4811_n2842), .ICI(DP_OP_168J30_122_4811_n2481), .S(
DP_OP_168J30_122_4811_n2471), .ICO(DP_OP_168J30_122_4811_n2469), .CO(
DP_OP_168J30_122_4811_n2470) );
NOR2X1TS U989 ( .A(DP_OP_168J30_122_4811_n2378), .B(n1579), .Y(n1876) );
OR2X1TS U990 ( .A(DP_OP_168J30_122_4811_n2317), .B(
DP_OP_168J30_122_4811_n2307), .Y(n825) );
OAI21XLTS U991 ( .A0(n4446), .A1(n1523), .B0(n1441), .Y(n1442) );
OAI21XLTS U992 ( .A0(n1795), .A1(n1748), .B0(n1747), .Y(n1753) );
CMPR42X1TS U993 ( .A(DP_OP_168J30_122_4811_n2868), .B(
DP_OP_168J30_122_4811_n2458), .C(DP_OP_168J30_122_4811_n2466), .D(
DP_OP_168J30_122_4811_n2895), .ICI(DP_OP_168J30_122_4811_n2467), .S(
DP_OP_168J30_122_4811_n2455), .ICO(DP_OP_168J30_122_4811_n2453), .CO(
DP_OP_168J30_122_4811_n2454) );
NAND2X1TS U994 ( .A(n1352), .B(n1351), .Y(n3624) );
OR2X1TS U995 ( .A(DP_OP_168J30_122_4811_n3910), .B(
DP_OP_168J30_122_4811_n3905), .Y(n940) );
OR2X1TS U996 ( .A(n1634), .B(n1633), .Y(n884) );
OA21XLTS U997 ( .A0(n1966), .A1(n1969), .B0(n1967), .Y(n900) );
OAI21XLTS U998 ( .A0(n1859), .A1(n1851), .B0(n1856), .Y(n1854) );
OAI21XLTS U999 ( .A0(n1795), .A1(n1787), .B0(n1792), .Y(n1790) );
OAI21XLTS U1000 ( .A0(n1795), .A1(n1780), .B0(n1779), .Y(n1785) );
NOR2X1TS U1001 ( .A(DP_OP_168J30_122_4811_n2426), .B(n1569), .Y(n3712) );
OAI21X1TS U1002 ( .A0(n2061), .A1(n2057), .B0(n2058), .Y(n2056) );
AOI21X1TS U1003 ( .A0(n2069), .A1(n936), .B0(n1339), .Y(n2066) );
OAI21XLTS U1004 ( .A0(n821), .A1(n3671), .B0(n3670), .Y(n3676) );
AOI21X1TS U1005 ( .A0(n945), .A1(n5014), .B0(n2012), .Y(n5005) );
NOR2X1TS U1006 ( .A(DP_OP_168J30_122_4811_n2452), .B(n1566), .Y(n4566) );
NOR2X1TS U1007 ( .A(DP_OP_168J30_122_4811_n2583), .B(n1544), .Y(n4480) );
OAI21XLTS U1008 ( .A0(n821), .A1(n3644), .B0(n3643), .Y(n3647) );
NOR2X1TS U1009 ( .A(DP_OP_168J30_122_4811_n1965), .B(n4706), .Y(n5204) );
NAND2X1TS U1010 ( .A(n2042), .B(n3632), .Y(n5156) );
OR2X1TS U1011 ( .A(n2035), .B(n3609), .Y(n730) );
OR2X1TS U1012 ( .A(n2008), .B(n4145), .Y(n944) );
OR2X1TS U1013 ( .A(n2005), .B(n4144), .Y(n943) );
OR2X1TS U1014 ( .A(n2017), .B(n4320), .Y(n947) );
OR2X1TS U1015 ( .A(n2011), .B(n4154), .Y(n945) );
NOR2X1TS U1016 ( .A(DP_OP_168J30_122_4811_n2476), .B(n1563), .Y(n4539) );
INVX2TS U1017 ( .A(Sgf_operation_ODD1_Q_left[49]), .Y(
DP_OP_168J30_122_4811_n1947) );
OAI21XLTS U1018 ( .A0(n5065), .A1(n5064), .B0(n5070), .Y(n5068) );
XOR2X1TS U1019 ( .A(n4711), .B(DP_OP_168J30_122_4811_n1952), .Y(n4712) );
XOR2X1TS U1020 ( .A(n5213), .B(n5212), .Y(n5214) );
XOR2X1TS U1021 ( .A(n4950), .B(DP_OP_168J30_122_4811_n1946), .Y(n4951) );
XOR2X1TS U1022 ( .A(n5235), .B(DP_OP_168J30_122_4811_n1960), .Y(n5236) );
XOR2X1TS U1023 ( .A(n5249), .B(DP_OP_168J30_122_4811_n1958), .Y(n5250) );
XOR2X1TS U1024 ( .A(n5243), .B(DP_OP_168J30_122_4811_n1959), .Y(n5244) );
XOR2X1TS U1025 ( .A(n5280), .B(n5279), .Y(n5282) );
XOR2X1TS U1026 ( .A(n5227), .B(n5226), .Y(n5229) );
XOR2X1TS U1027 ( .A(n4716), .B(DP_OP_168J30_122_4811_n1951), .Y(n4717) );
XOR2X1TS U1028 ( .A(n4726), .B(DP_OP_168J30_122_4811_n1948), .Y(n4727) );
XOR2X1TS U1029 ( .A(n5219), .B(DP_OP_168J30_122_4811_n1962), .Y(n5220) );
XOR2X1TS U1030 ( .A(n4723), .B(DP_OP_168J30_122_4811_n1949), .Y(n4724) );
XOR2X1TS U1031 ( .A(n4708), .B(DP_OP_168J30_122_4811_n1953), .Y(n4709) );
XOR2X1TS U1032 ( .A(n5205), .B(DP_OP_168J30_122_4811_n1964), .Y(n5206) );
XOR2X1TS U1033 ( .A(n5263), .B(DP_OP_168J30_122_4811_n1956), .Y(n5264) );
XOR2X1TS U1034 ( .A(n4719), .B(DP_OP_168J30_122_4811_n1950), .Y(n4720) );
XOR2X1TS U1035 ( .A(n4731), .B(DP_OP_168J30_122_4811_n1947), .Y(n4732) );
XOR2X1TS U1036 ( .A(n5257), .B(n942), .Y(n5258) );
XOR2X1TS U1037 ( .A(n4736), .B(n1371), .Y(n4737) );
XOR2X1TS U1038 ( .A(n5270), .B(DP_OP_168J30_122_4811_n1955), .Y(n5271) );
NAND2X2TS U1039 ( .A(n5277), .B(n5276), .Y(n5280) );
NAND2X2TS U1040 ( .A(n5277), .B(n5204), .Y(n5205) );
NAND2X2TS U1041 ( .A(n5277), .B(n4734), .Y(n4736) );
NAND2X2TS U1042 ( .A(n5277), .B(n4707), .Y(n4708) );
NAND2X2TS U1043 ( .A(n5277), .B(n5248), .Y(n5249) );
NAND2X2TS U1044 ( .A(n5277), .B(n4728), .Y(n4726) );
NAND2X2TS U1045 ( .A(n5277), .B(n5233), .Y(n5235) );
NAND2X2TS U1046 ( .A(n5277), .B(n4730), .Y(n4731) );
NAND2X2TS U1047 ( .A(n5277), .B(n5225), .Y(n5227) );
NAND2X2TS U1048 ( .A(n5277), .B(n4713), .Y(n4711) );
NAND2X2TS U1049 ( .A(n5277), .B(n5242), .Y(n5243) );
NAND2X2TS U1050 ( .A(n5277), .B(n4722), .Y(n4723) );
NAND2X2TS U1051 ( .A(n5277), .B(n4949), .Y(n4950) );
NAND2X2TS U1052 ( .A(n5277), .B(n5256), .Y(n5257) );
NAND2X2TS U1053 ( .A(n5277), .B(n4714), .Y(n4716) );
NAND2X2TS U1054 ( .A(n5277), .B(n5218), .Y(n5219) );
NAND2X2TS U1055 ( .A(n5277), .B(n5262), .Y(n5263) );
NAND2X2TS U1056 ( .A(n5277), .B(n5269), .Y(n5270) );
CLKMX2X2TS U1057 ( .A(P_Sgf[74]), .B(n5118), .S0(n5228), .Y(n495) );
AOI21X2TS U1058 ( .A0(n730), .A1(n747), .B0(n2036), .Y(n5125) );
CLKMX2X2TS U1059 ( .A(P_Sgf[73]), .B(n5112), .S0(n5228), .Y(n494) );
CLKMX2X2TS U1060 ( .A(P_Sgf[72]), .B(n5105), .S0(n5228), .Y(n493) );
OAI2BB1X2TS U1061 ( .A0N(n950), .A1N(n5110), .B0(n5109), .Y(n747) );
OAI21X2TS U1062 ( .A0(n5101), .A1(n736), .B0(n5102), .Y(n5110) );
CLKMX2X2TS U1063 ( .A(P_Sgf[71]), .B(n5096), .S0(n5228), .Y(n492) );
CLKMX2X2TS U1064 ( .A(P_Sgf[70]), .B(n4961), .S0(n5019), .Y(n491) );
OA21X2TS U1065 ( .A0(n5091), .A1(n5094), .B0(n5092), .Y(n736) );
CLKMX2X2TS U1066 ( .A(P_Sgf[69]), .B(n4957), .S0(n5019), .Y(n490) );
NAND2X2TS U1067 ( .A(n2046), .B(n3826), .Y(n5180) );
OR2X2TS U1068 ( .A(n2042), .B(n3632), .Y(n855) );
INVX6TS U1069 ( .A(n5065), .Y(n5073) );
INVX2TS U1070 ( .A(n1656), .Y(n1625) );
OR2X2TS U1071 ( .A(DP_OP_168J30_122_4811_n217), .B(n1945), .Y(n885) );
OA21X2TS U1072 ( .A0(n4832), .A1(n4835), .B0(n4833), .Y(n742) );
OR2X2TS U1073 ( .A(DP_OP_168J30_122_4811_n225), .B(n1371), .Y(n849) );
OR2X2TS U1074 ( .A(n2034), .B(n3627), .Y(n950) );
NOR2X1TS U1075 ( .A(DP_OP_168J30_122_4811_n1947), .B(n4733), .Y(n4949) );
NAND2X1TS U1076 ( .A(n2033), .B(n3630), .Y(n5102) );
OR2X2TS U1077 ( .A(n2030), .B(n3635), .Y(n949) );
OR2X2TS U1078 ( .A(n2027), .B(n3636), .Y(n948) );
INVX1TS U1079 ( .A(n4718), .Y(n4714) );
CMPR42X2TS U1080 ( .A(DP_OP_168J30_122_4811_n279), .B(
DP_OP_168J30_122_4811_n283), .C(DP_OP_168J30_122_4811_n1953), .D(
Sgf_operation_ODD1_Q_left[44]), .ICI(DP_OP_168J30_122_4811_n777), .S(
DP_OP_168J30_122_4811_n276), .ICO(DP_OP_168J30_122_4811_n274), .CO(
DP_OP_168J30_122_4811_n275) );
INVX1TS U1081 ( .A(n4710), .Y(n4707) );
INVX1TS U1082 ( .A(n5268), .Y(n5269) );
AO21XLTS U1083 ( .A0(n816), .A1(n5460), .B0(n5459), .Y(n528) );
INVX1TS U1084 ( .A(n5255), .Y(n5256) );
OR2X2TS U1085 ( .A(n1945), .B(n1944), .Y(n910) );
NOR2X1TS U1086 ( .A(DP_OP_168J30_122_4811_n1959), .B(n5241), .Y(n5248) );
NOR2X1TS U1087 ( .A(n5226), .B(n5224), .Y(n5233) );
CMPR42X1TS U1088 ( .A(DP_OP_168J30_122_4811_n394), .B(
DP_OP_168J30_122_4811_n407), .C(DP_OP_168J30_122_4811_n403), .D(
Sgf_operation_ODD1_Q_left[34]), .ICI(DP_OP_168J30_122_4811_n787), .S(
DP_OP_168J30_122_4811_n391), .ICO(DP_OP_168J30_122_4811_n389), .CO(
DP_OP_168J30_122_4811_n390) );
NOR2X1TS U1089 ( .A(n5212), .B(n5210), .Y(n5218) );
AOI21X1TS U1090 ( .A0(n1835), .A1(n1590), .B0(n1589), .Y(n1797) );
AOI21X1TS U1091 ( .A0(n2072), .A1(n937), .B0(n1331), .Y(n3623) );
INVX2TS U1092 ( .A(n1835), .Y(n1859) );
OAI21X1TS U1093 ( .A0(n821), .A1(n1330), .B0(n1329), .Y(n2072) );
INVX1TS U1094 ( .A(n1756), .Y(n1757) );
INVX1TS U1095 ( .A(n1755), .Y(n1758) );
OAI21X1TS U1096 ( .A0(n1799), .A1(n1810), .B0(n1811), .Y(n1800) );
INVX2TS U1097 ( .A(n2115), .Y(n2124) );
INVX1TS U1098 ( .A(n1771), .Y(n1774) );
OAI21X2TS U1099 ( .A0(n1283), .A1(n1282), .B0(n1281), .Y(n2115) );
OAI21X1TS U1100 ( .A0(n2122), .A1(n2116), .B0(n2117), .Y(n1285) );
INVX1TS U1101 ( .A(n2116), .Y(n2118) );
NAND2XLTS U1102 ( .A(n1751), .B(n1750), .Y(n1752) );
NAND2XLTS U1103 ( .A(n1742), .B(n1741), .Y(n1743) );
OAI21X1TS U1104 ( .A0(n835), .A1(n4365), .B0(n2669), .Y(n2670) );
AOI21X1TS U1105 ( .A0(n955), .A1(n1644), .B0(n1181), .Y(n1182) );
OAI21X1TS U1106 ( .A0(n932), .A1(n4365), .B0(n2666), .Y(n2667) );
OAI21X1TS U1107 ( .A0(n933), .A1(n4365), .B0(n2660), .Y(n2662) );
INVX1TS U1108 ( .A(n1749), .Y(n1751) );
NAND2X1TS U1109 ( .A(n870), .B(n1736), .Y(n1737) );
NAND2X1TS U1110 ( .A(Sgf_normalized_result[36]), .B(n5431), .Y(n5430) );
INVX2TS U1111 ( .A(n1645), .Y(n1181) );
INVX1TS U1112 ( .A(n3677), .Y(n3679) );
NAND2X1TS U1113 ( .A(n955), .B(n956), .Y(n1183) );
INVX1TS U1114 ( .A(n3672), .Y(n3674) );
OR2X2TS U1115 ( .A(DP_OP_168J30_122_4811_n2238), .B(
DP_OP_168J30_122_4811_n2243), .Y(n903) );
INVX1TS U1116 ( .A(n3666), .Y(n3667) );
OR2X2TS U1117 ( .A(DP_OP_168J30_122_4811_n2225), .B(
DP_OP_168J30_122_4811_n2231), .Y(n874) );
OAI21X1TS U1118 ( .A0(n2179), .A1(n2175), .B0(n2176), .Y(n2169) );
OR2X2TS U1119 ( .A(DP_OP_168J30_122_4811_n2219), .B(
DP_OP_168J30_122_4811_n2216), .Y(n875) );
INVX2TS U1120 ( .A(n2067), .Y(n1339) );
OAI21X1TS U1121 ( .A0(n838), .A1(n3919), .B0(n2627), .Y(n2628) );
NAND2X1TS U1122 ( .A(Sgf_normalized_result[34]), .B(n5428), .Y(n5427) );
OAI21X1TS U1123 ( .A0(n4611), .A1(n3919), .B0(n2629), .Y(n2630) );
INVX2TS U1124 ( .A(n2192), .Y(n4611) );
NAND2X1TS U1125 ( .A(Sgf_normalized_result[32]), .B(n5425), .Y(n5424) );
OAI21X1TS U1126 ( .A0(n3136), .A1(n2968), .B0(n2936), .Y(n2937) );
OAI21X1TS U1127 ( .A0(n3154), .A1(n2968), .B0(n2932), .Y(n2933) );
OAI21X1TS U1128 ( .A0(n839), .A1(n3919), .B0(n2631), .Y(n2632) );
OAI21X1TS U1129 ( .A0(n3136), .A1(n3026), .B0(n2994), .Y(n2995) );
OAI21X1TS U1130 ( .A0(n840), .A1(n2576), .B0(n2559), .Y(n2560) );
OAI21X1TS U1131 ( .A0(n3795), .A1(n2968), .B0(n2940), .Y(n2941) );
OAI21X1TS U1132 ( .A0(n3786), .A1(n2968), .B0(n2942), .Y(n2943) );
XOR2X1TS U1133 ( .A(n1280), .B(Op_MX[35]), .Y(n1284) );
OAI21X1TS U1134 ( .A0(n3786), .A1(n3026), .B0(n3000), .Y(n3001) );
NAND2X1TS U1135 ( .A(Sgf_normalized_result[30]), .B(n5422), .Y(n5421) );
OAI21X1TS U1136 ( .A0(n982), .A1(n1275), .B0(n3467), .Y(n3468) );
OAI21X1TS U1137 ( .A0(n982), .A1(n1174), .B0(n3524), .Y(n3525) );
OAI21X1TS U1138 ( .A0(n3786), .A1(n2876), .B0(n2887), .Y(n2888) );
OR2X2TS U1139 ( .A(n1632), .B(n1631), .Y(n1633) );
OAI21X1TS U1140 ( .A0(n3776), .A1(n2876), .B0(n2889), .Y(n2890) );
NAND2X1TS U1141 ( .A(n2184), .B(n2183), .Y(n2185) );
INVX2TS U1142 ( .A(n2182), .Y(n2184) );
OAI21X1TS U1143 ( .A0(n4325), .A1(n2576), .B0(n2565), .Y(n2566) );
OAI21X1TS U1144 ( .A0(n3780), .A1(n3026), .B0(n3004), .Y(n3005) );
OAI21X1TS U1145 ( .A0(n4325), .A1(n4546), .B0(n3968), .Y(n3969) );
NOR2X4TS U1146 ( .A(n985), .B(Op_MY[51]), .Y(n982) );
OAI21X1TS U1147 ( .A0(n3780), .A1(n2876), .B0(n2891), .Y(n2892) );
NAND2X1TS U1148 ( .A(Sgf_normalized_result[28]), .B(n5419), .Y(n5418) );
OAI21X1TS U1149 ( .A0(n3780), .A1(n2968), .B0(n2946), .Y(n2947) );
OAI21X1TS U1150 ( .A0(n2313), .A1(n4552), .B0(n2303), .Y(n2304) );
OAI21X1TS U1151 ( .A0(n4011), .A1(n4552), .B0(n2218), .Y(n2219) );
NOR2X1TS U1152 ( .A(n4313), .B(n3728), .Y(n2182) );
INVX2TS U1153 ( .A(n2213), .Y(n4325) );
OAI21X1TS U1154 ( .A0(n3773), .A1(n2876), .B0(n2893), .Y(n2894) );
OAI21X1TS U1155 ( .A0(n4552), .A1(n2576), .B0(n2567), .Y(n2568) );
OAI21X1TS U1156 ( .A0(n4552), .A1(n4546), .B0(n2481), .Y(n2482) );
OAI21X1TS U1157 ( .A0(n4546), .A1(n4322), .B0(n2483), .Y(n2484) );
INVX2TS U1158 ( .A(n2217), .Y(n4552) );
OAI21X1TS U1159 ( .A0(n4461), .A1(n2876), .B0(n2895), .Y(n2896) );
OAI21X1TS U1160 ( .A0(n4610), .A1(n4322), .B0(n3970), .Y(n3971) );
OAI21X1TS U1161 ( .A0(n4011), .A1(n4322), .B0(n2223), .Y(n2224) );
NAND2X1TS U1162 ( .A(Sgf_normalized_result[26]), .B(n5416), .Y(n5415) );
OAI21X1TS U1163 ( .A0(n4449), .A1(n2852), .B0(n2841), .Y(n2842) );
OAI21X1TS U1164 ( .A0(n4449), .A1(n2876), .B0(n2897), .Y(n2898) );
OAI21X1TS U1165 ( .A0(n4610), .A1(n4366), .B0(n3966), .Y(n3967) );
OAI21X1TS U1166 ( .A0(n4475), .A1(n2852), .B0(n2843), .Y(n2844) );
OAI21X1TS U1167 ( .A0(n4475), .A1(n2876), .B0(n2899), .Y(n2900) );
NAND2X1TS U1168 ( .A(Sgf_normalized_result[24]), .B(n5413), .Y(n5412) );
INVX2TS U1169 ( .A(n2226), .Y(n4366) );
OAI21X1TS U1170 ( .A0(n4011), .A1(n3835), .B0(n2232), .Y(n2234) );
OAI21X1TS U1171 ( .A0(n3548), .A1(n3446), .B0(n3433), .Y(n3434) );
NAND2X1TS U1172 ( .A(n2203), .B(n2202), .Y(n2205) );
INVX2TS U1173 ( .A(n2230), .Y(n3835) );
OAI21X1TS U1174 ( .A0(n4467), .A1(n2852), .B0(n2845), .Y(n2846) );
OAI21X1TS U1175 ( .A0(n3552), .A1(n3446), .B0(n3435), .Y(n3436) );
NAND2X1TS U1176 ( .A(Sgf_normalized_result[22]), .B(n5408), .Y(n5410) );
OAI21X1TS U1177 ( .A0(n3557), .A1(n3189), .B0(n3382), .Y(n3383) );
INVX2TS U1178 ( .A(n2242), .Y(n4376) );
OAI21X1TS U1179 ( .A0(n3743), .A1(n3189), .B0(n3387), .Y(n3388) );
NAND2X1TS U1180 ( .A(Sgf_normalized_result[20]), .B(n5404), .Y(n5406) );
OAI21X1TS U1181 ( .A0(n3798), .A1(n2852), .B0(n2778), .Y(n2779) );
OAI21X1TS U1182 ( .A0(n3740), .A1(n3284), .B0(n3283), .Y(n3285) );
OAI21X1TS U1183 ( .A0(n3740), .A1(n3339), .B0(n3338), .Y(n3340) );
INVX2TS U1184 ( .A(n1030), .Y(n3743) );
OAI21X1TS U1185 ( .A0(n3571), .A1(n3341), .B0(n3344), .Y(n3345) );
NAND2X1TS U1186 ( .A(Sgf_normalized_result[18]), .B(n5400), .Y(n5402) );
OAI21X1TS U1187 ( .A0(n3571), .A1(n3286), .B0(n3288), .Y(n3289) );
OAI21X1TS U1188 ( .A0(n3575), .A1(n3245), .B0(n3250), .Y(n3251) );
INVX2TS U1189 ( .A(n1043), .Y(n3575) );
OAI21X1TS U1190 ( .A0(n3579), .A1(n3243), .B0(n3252), .Y(n3253) );
OAI21X1TS U1191 ( .A0(n3579), .A1(n3284), .B0(n3293), .Y(n3294) );
NAND2X1TS U1192 ( .A(Sgf_normalized_result[16]), .B(n5396), .Y(n5398) );
INVX1TS U1193 ( .A(n2311), .Y(DP_OP_168J30_122_4811_n994) );
OAI21X1TS U1194 ( .A0(n3737), .A1(n3284), .B0(n3295), .Y(n3296) );
INVX2TS U1195 ( .A(n1047), .Y(n3579) );
OAI21X1TS U1196 ( .A0(n4648), .A1(n3284), .B0(n3297), .Y(n3298) );
INVX2TS U1197 ( .A(n1051), .Y(n3737) );
INVX2TS U1198 ( .A(n1055), .Y(n4648) );
INVX2TS U1199 ( .A(n1095), .Y(n4635) );
OAI21X1TS U1200 ( .A0(n4644), .A1(n4643), .B0(n4642), .Y(n4653) );
OAI21X1TS U1201 ( .A0(n2608), .A1(n2598), .B0(n2597), .Y(n2603) );
INVX2TS U1202 ( .A(n1071), .Y(n4633) );
OAI21X1TS U1203 ( .A0(n2608), .A1(n2607), .B0(n2606), .Y(n2612) );
OAI21XLTS U1204 ( .A0(n3446), .A1(n3893), .B0(n3213), .Y(n3214) );
INVX2TS U1205 ( .A(n1080), .Y(n4624) );
OAI21XLTS U1206 ( .A0(n3521), .A1(n748), .B0(n1068), .Y(n1069) );
OAI21XLTS U1207 ( .A0(n3521), .A1(n4587), .B0(n1063), .Y(n1064) );
OAI21XLTS U1208 ( .A0(n3521), .A1(n3893), .B0(n1066), .Y(n1067) );
NAND2X2TS U1209 ( .A(n925), .B(n1225), .Y(n1226) );
INVX2TS U1210 ( .A(n1084), .Y(n4596) );
AOI21X1TS U1211 ( .A0(n962), .A1(n1187), .B0(n961), .Y(n1242) );
INVX1TS U1212 ( .A(n2270), .Y(n2272) );
INVX1TS U1213 ( .A(n2371), .Y(n2373) );
OR2X2TS U1214 ( .A(Op_MX[18]), .B(Op_MX[45]), .Y(n852) );
OR2X2TS U1215 ( .A(Op_MX[43]), .B(Op_MX[16]), .Y(n915) );
XOR2X2TS U1216 ( .A(n5199), .B(DP_OP_168J30_122_4811_n1965), .Y(n5200) );
XNOR2X1TS U1217 ( .A(n5277), .B(n4706), .Y(n2052) );
NAND2X2TS U1218 ( .A(n5277), .B(n4721), .Y(n4719) );
NAND2X2TS U1219 ( .A(n5277), .B(n5211), .Y(n5213) );
INVX16TS U1220 ( .A(n2049), .Y(n5277) );
CLKMX2X2TS U1221 ( .A(P_Sgf[83]), .B(n5192), .S0(n5281), .Y(n504) );
CLKMX2X2TS U1222 ( .A(P_Sgf[82]), .B(n5183), .S0(n5281), .Y(n503) );
CLKMX2X2TS U1223 ( .A(P_Sgf[81]), .B(n5176), .S0(n5228), .Y(n502) );
CLKMX2X2TS U1224 ( .A(P_Sgf[80]), .B(n5167), .S0(n5228), .Y(n501) );
CLKMX2X2TS U1225 ( .A(P_Sgf[79]), .B(n5158), .S0(n5228), .Y(n500) );
CLKMX2X2TS U1226 ( .A(P_Sgf[78]), .B(n5151), .S0(n5228), .Y(n499) );
CLKMX2X2TS U1227 ( .A(P_Sgf[77]), .B(n5143), .S0(n5228), .Y(n498) );
CLKMX2X2TS U1228 ( .A(P_Sgf[76]), .B(n5135), .S0(n5228), .Y(n497) );
CLKMX2X2TS U1229 ( .A(P_Sgf[75]), .B(n5127), .S0(n5228), .Y(n496) );
INVX1TS U1230 ( .A(n5187), .Y(n5189) );
NAND2X2TS U1231 ( .A(n2045), .B(n3628), .Y(n5173) );
XNOR2X2TS U1232 ( .A(n1642), .B(n1641), .Y(n2046) );
OR2X2TS U1233 ( .A(n2040), .B(n3611), .Y(n734) );
CLKXOR2X2TS U1234 ( .A(n1666), .B(n1665), .Y(n2042) );
CLKAND2X2TS U1235 ( .A(Sgf_operation_ODD1_Q_left[50]), .B(n4949), .Y(n4734)
);
NOR2X1TS U1236 ( .A(n2032), .B(n3633), .Y(n5091) );
NAND2X1TS U1237 ( .A(n2032), .B(n3633), .Y(n5092) );
CMPR42X2TS U1238 ( .A(DP_OP_168J30_122_4811_n240), .B(
DP_OP_168J30_122_4811_n245), .C(DP_OP_168J30_122_4811_n241), .D(
Sgf_operation_ODD1_Q_left[49]), .ICI(DP_OP_168J30_122_4811_n772), .S(
DP_OP_168J30_122_4811_n237), .ICO(DP_OP_168J30_122_4811_n235), .CO(
DP_OP_168J30_122_4811_n236) );
CMPR42X2TS U1239 ( .A(DP_OP_168J30_122_4811_n246), .B(
DP_OP_168J30_122_4811_n249), .C(DP_OP_168J30_122_4811_n1949), .D(
DP_OP_168J30_122_4811_n773), .ICI(DP_OP_168J30_122_4811_n1948), .S(
DP_OP_168J30_122_4811_n243), .ICO(DP_OP_168J30_122_4811_n241), .CO(
DP_OP_168J30_122_4811_n242) );
NAND2X1TS U1240 ( .A(n2029), .B(n3634), .Y(n4953) );
CMPR42X2TS U1241 ( .A(DP_OP_168J30_122_4811_n254), .B(
DP_OP_168J30_122_4811_n257), .C(DP_OP_168J30_122_4811_n1950), .D(
Sgf_operation_ODD1_Q_left[47]), .ICI(DP_OP_168J30_122_4811_n774), .S(
DP_OP_168J30_122_4811_n251), .ICO(DP_OP_168J30_122_4811_n249), .CO(
DP_OP_168J30_122_4811_n250) );
NAND2X1TS U1242 ( .A(n2027), .B(n3636), .Y(n4962) );
NOR2X1TS U1243 ( .A(DP_OP_168J30_122_4811_n1951), .B(n4718), .Y(n4721) );
OAI21X1TS U1244 ( .A0(n4976), .A1(n4973), .B0(n4977), .Y(n2020) );
ADDFHX2TS U1245 ( .A(DP_OP_168J30_122_4811_n294), .B(
DP_OP_168J30_122_4811_n304), .CI(n1718), .CO(n1714), .S(n2029) );
NAND2X1TS U1246 ( .A(n2026), .B(n4306), .Y(n4967) );
AOI21X1TS U1247 ( .A0(n947), .A1(n4982), .B0(n2018), .Y(n4973) );
ADDFHX2TS U1248 ( .A(DP_OP_168J30_122_4811_n305), .B(
DP_OP_168J30_122_4811_n315), .CI(n1723), .CO(n1718), .S(n2027) );
ADDFHX2TS U1249 ( .A(DP_OP_168J30_122_4811_n316), .B(
DP_OP_168J30_122_4811_n326), .CI(n2022), .CO(n1723), .S(n2026) );
OAI21X2TS U1250 ( .A0(n4861), .A1(n4864), .B0(n4862), .Y(n4868) );
OAI21X2TS U1251 ( .A0(n4992), .A1(n4989), .B0(n4993), .Y(n4982) );
NAND2X1TS U1252 ( .A(n2017), .B(n4320), .Y(n4984) );
AOI21X2TS U1253 ( .A0(n946), .A1(n4998), .B0(n2015), .Y(n4989) );
NAND2X1TS U1254 ( .A(n946), .B(n4999), .Y(n4988) );
NAND2X1TS U1255 ( .A(n2016), .B(n4319), .Y(n4993) );
OAI21X2TS U1256 ( .A0(n5008), .A1(n5005), .B0(n5009), .Y(n4998) );
NOR2X2TS U1257 ( .A(n2016), .B(n4319), .Y(n4992) );
AOI2BB1X1TS U1258 ( .A0N(n5464), .A1N(FSM_add_overflow_flag), .B0(n5463),
.Y(n526) );
ADDFHX2TS U1259 ( .A(DP_OP_168J30_122_4811_n351), .B(
DP_OP_168J30_122_4811_n362), .CI(n1956), .CO(n1953), .S(n2016) );
NAND2X1TS U1260 ( .A(n2014), .B(n4276), .Y(n5000) );
NAND2X1TS U1261 ( .A(n945), .B(n5015), .Y(n5004) );
NOR2X2TS U1262 ( .A(n2013), .B(n4192), .Y(n5008) );
NAND2X1TS U1263 ( .A(n2013), .B(n4192), .Y(n5009) );
ADDFHX2TS U1264 ( .A(DP_OP_168J30_122_4811_n363), .B(
DP_OP_168J30_122_4811_n376), .CI(n1960), .CO(n1956), .S(n2014) );
OAI21X2TS U1265 ( .A0(n5025), .A1(n5022), .B0(n5026), .Y(n5014) );
NOR2X1TS U1266 ( .A(n5025), .B(n5021), .Y(n5015) );
AO22XLTS U1267 ( .A0(n5454), .A1(n5453), .B0(n5449), .B1(n805), .Y(n530) );
AOI21X1TS U1268 ( .A0(n944), .A1(n5032), .B0(n2009), .Y(n5022) );
NAND2X1TS U1269 ( .A(n2011), .B(n4154), .Y(n5016) );
OAI211X1TS U1270 ( .A0(Sgf_normalized_result[50]), .A1(n5456), .B0(n5455),
.C0(n5458), .Y(n5457) );
ADDFHX2TS U1271 ( .A(DP_OP_168J30_122_4811_n377), .B(
DP_OP_168J30_122_4811_n390), .CI(n1965), .CO(n1960), .S(n2013) );
OAI21X2TS U1272 ( .A0(n4928), .A1(n4931), .B0(n4929), .Y(n4935) );
NAND2X1TS U1273 ( .A(n2010), .B(n4125), .Y(n5026) );
ADDFHX2TS U1274 ( .A(DP_OP_168J30_122_4811_n391), .B(
DP_OP_168J30_122_4811_n404), .CI(n1971), .CO(n1965), .S(n2011) );
OAI21X1TS U1275 ( .A0(n5042), .A1(n5039), .B0(n5043), .Y(n5032) );
NAND2X1TS U1276 ( .A(n2008), .B(n4145), .Y(n5034) );
AOI21X1TS U1277 ( .A0(n943), .A1(n5048), .B0(n2006), .Y(n5039) );
NOR2X1TS U1278 ( .A(n3705), .B(n1943), .Y(n5079) );
NOR2X1TS U1279 ( .A(n5042), .B(n5038), .Y(n5033) );
OAI21X1TS U1280 ( .A0(n5058), .A1(n5055), .B0(n5059), .Y(n5048) );
NOR2X1TS U1281 ( .A(n3702), .B(n1937), .Y(n4819) );
NAND2X1TS U1282 ( .A(n2007), .B(n4143), .Y(n5043) );
INVX1TS U1283 ( .A(n3701), .Y(DP_OP_168J30_122_4811_n770) );
NOR2X1TS U1284 ( .A(n5058), .B(n5054), .Y(n5049) );
NOR2X1TS U1285 ( .A(n3709), .B(n1927), .Y(n4861) );
NAND2X1TS U1286 ( .A(n2005), .B(n4144), .Y(n5050) );
AO22XLTS U1287 ( .A0(n5454), .A1(n4703), .B0(n5374), .B1(n811), .Y(n534) );
AOI21X1TS U1288 ( .A0(n924), .A1(n2002), .B0(n2001), .Y(n5055) );
INVX2TS U1289 ( .A(n5210), .Y(n5211) );
ADDFHX2TS U1290 ( .A(DP_OP_168J30_122_4811_n450), .B(
DP_OP_168J30_122_4811_n464), .CI(n1988), .CO(n1984), .S(n2005) );
AOI21X2TS U1291 ( .A0(n863), .A1(n735), .B0(n1911), .Y(n4918) );
NAND2X1TS U1292 ( .A(n2004), .B(n2003), .Y(n5059) );
AOI21X1TS U1293 ( .A0(n1746), .A1(n1604), .B0(n1603), .Y(n1744) );
ADDFHX2TS U1294 ( .A(DP_OP_168J30_122_4811_n465), .B(
DP_OP_168J30_122_4811_n479), .CI(n1994), .CO(n1988), .S(n2004) );
ADDFHX2TS U1295 ( .A(DP_OP_168J30_122_4811_n480), .B(
DP_OP_168J30_122_4811_n494), .CI(n1995), .CO(n1994), .S(n2000) );
OAI21X1TS U1296 ( .A0(n1598), .A1(n1797), .B0(n1597), .Y(n1746) );
OAI21X1TS U1297 ( .A0(n821), .A1(n3661), .B0(n3660), .Y(n3664) );
ADDFHX2TS U1298 ( .A(DP_OP_168J30_122_4811_n495), .B(
DP_OP_168J30_122_4811_n509), .CI(n1996), .CO(n1995), .S(n1998) );
OAI21X1TS U1299 ( .A0(n821), .A1(n2076), .B0(n2075), .Y(n2079) );
OAI21X1TS U1300 ( .A0(n821), .A1(n2106), .B0(n2105), .Y(n2109) );
OAI21X1TS U1301 ( .A0(n821), .A1(n2101), .B0(n2100), .Y(n2104) );
OAI21X1TS U1302 ( .A0(n821), .A1(n2083), .B0(n2082), .Y(n2086) );
AOI21X2TS U1303 ( .A0(n831), .A1(n729), .B0(n1906), .Y(n4904) );
ADDFHX2TS U1304 ( .A(DP_OP_168J30_122_4811_n510), .B(
DP_OP_168J30_122_4811_n525), .CI(n1729), .CO(n1996), .S(n1944) );
OAI21X2TS U1305 ( .A0(n1583), .A1(n1861), .B0(n1582), .Y(n1835) );
ADDFHX2TS U1306 ( .A(DP_OP_168J30_122_4811_n526), .B(
DP_OP_168J30_122_4811_n541), .CI(n1735), .CO(n1729), .S(n1943) );
AO21X2TS U1307 ( .A0(n741), .A1(n4895), .B0(n1904), .Y(n729) );
OAI21X1TS U1308 ( .A0(n1763), .A1(n1765), .B0(n1766), .Y(n1756) );
AOI21X1TS U1309 ( .A0(n1862), .A1(n827), .B0(n1581), .Y(n1582) );
NOR2X1TS U1310 ( .A(n2101), .B(n1326), .Y(n2073) );
OAI21X1TS U1311 ( .A0(n3656), .A1(n3655), .B0(n3654), .Y(n3657) );
OAI21X2TS U1312 ( .A0(n1889), .A1(n1892), .B0(n1890), .Y(n1885) );
OAI21X2TS U1313 ( .A0(n1643), .A1(n1183), .B0(n1182), .Y(n1639) );
NAND2X1TS U1314 ( .A(n828), .B(n827), .Y(n1583) );
OAI21X1TS U1315 ( .A0(n1588), .A1(n1845), .B0(n1587), .Y(n1589) );
OAI21X1TS U1316 ( .A0(n835), .A1(n2313), .B0(n4662), .Y(n4663) );
NAND2X1TS U1317 ( .A(n1891), .B(n1890), .Y(n1893) );
OAI21X1TS U1318 ( .A0(n1322), .A1(n3651), .B0(n1321), .Y(n1323) );
OAI21X1TS U1319 ( .A0(n835), .A1(n4546), .B0(n2469), .Y(n2470) );
OAI21X1TS U1320 ( .A0(n835), .A1(n3919), .B0(n2623), .Y(n2624) );
NOR2X1TS U1321 ( .A(n2121), .B(n2116), .Y(n1286) );
AOI21X2TS U1322 ( .A0(n958), .A1(n1660), .B0(n1173), .Y(n1643) );
AOI21X2TS U1323 ( .A0(n833), .A1(n1898), .B0(n1571), .Y(n1892) );
CLKXOR2X2TS U1324 ( .A(n1670), .B(n872), .Y(n3632) );
NOR2X2TS U1325 ( .A(n1318), .B(n3637), .Y(n2088) );
OAI21X1TS U1326 ( .A0(n835), .A1(n4011), .B0(n2173), .Y(n2174) );
OAI21X1TS U1327 ( .A0(n932), .A1(n2313), .B0(n2289), .Y(n2290) );
OAI21X1TS U1328 ( .A0(n933), .A1(n4610), .B0(n2378), .Y(n2379) );
NOR2X2TS U1329 ( .A(DP_OP_168J30_122_4811_n3986), .B(
DP_OP_168J30_122_4811_n3977), .Y(n2116) );
OAI21X1TS U1330 ( .A0(n933), .A1(n3919), .B0(n2615), .Y(n2616) );
OAI21X1TS U1331 ( .A0(n932), .A1(n2576), .B0(n2543), .Y(n2544) );
OAI21X1TS U1332 ( .A0(n836), .A1(n4610), .B0(n2388), .Y(n2389) );
OAI21X1TS U1333 ( .A0(n933), .A1(n2576), .B0(n2538), .Y(n2539) );
OAI21X1TS U1334 ( .A0(n836), .A1(n4011), .B0(n2180), .Y(n2181) );
OAI21X1TS U1335 ( .A0(n932), .A1(n3919), .B0(n2619), .Y(n2620) );
OAI21X1TS U1336 ( .A0(n932), .A1(n4610), .B0(n2382), .Y(n2383) );
OAI21X1TS U1337 ( .A0(n836), .A1(n3919), .B0(n2625), .Y(n2626) );
OAI21X2TS U1338 ( .A0(n1667), .A1(n872), .B0(n1668), .Y(n1660) );
OAI21X1TS U1339 ( .A0(n933), .A1(n4011), .B0(n2165), .Y(n2166) );
NAND2XLTS U1340 ( .A(n3621), .B(n3620), .Y(n3622) );
NOR2X2TS U1341 ( .A(DP_OP_168J30_122_4811_n3987), .B(n1284), .Y(n2121) );
OAI21X1TS U1342 ( .A0(n836), .A1(n2576), .B0(n2551), .Y(n2552) );
NAND2X1TS U1343 ( .A(n3665), .B(n1313), .Y(n2101) );
OAI21X1TS U1344 ( .A0(n932), .A1(n4546), .B0(n2465), .Y(n2466) );
ADDFHX2TS U1345 ( .A(DP_OP_168J30_122_4811_n600), .B(
DP_OP_168J30_122_4811_n612), .CI(n1770), .CO(n1762), .S(n1935) );
OAI21X1TS U1346 ( .A0(n933), .A1(n4546), .B0(n2461), .Y(n2462) );
NAND2X1TS U1347 ( .A(n824), .B(n825), .Y(n1588) );
OAI21X2TS U1348 ( .A0(n3712), .A1(n3715), .B0(n3713), .Y(n1898) );
INVX1TS U1349 ( .A(n3651), .Y(n3653) );
NOR2X1TS U1350 ( .A(DP_OP_168J30_122_4811_n2329), .B(
DP_OP_168J30_122_4811_n2341), .Y(n1851) );
INVX1TS U1351 ( .A(n3619), .Y(n3621) );
OR2X2TS U1352 ( .A(DP_OP_168J30_122_4811_n4042), .B(n1172), .Y(n958) );
OR2X1TS U1353 ( .A(DP_OP_168J30_122_4811_n2268), .B(
DP_OP_168J30_122_4811_n2277), .Y(n1373) );
NAND2X1TS U1354 ( .A(DP_OP_168J30_122_4811_n2329), .B(
DP_OP_168J30_122_4811_n2341), .Y(n1856) );
NAND2X1TS U1355 ( .A(DP_OP_168J30_122_4811_n2378), .B(n1579), .Y(n1877) );
NAND2XLTS U1356 ( .A(n864), .B(n3624), .Y(n3625) );
INVX2TS U1357 ( .A(n2054), .Y(n1366) );
OAI21X1TS U1358 ( .A0(n4611), .A1(n4546), .B0(n2475), .Y(n2476) );
OR2X2TS U1359 ( .A(DP_OP_168J30_122_4811_n3893), .B(
DP_OP_168J30_122_4811_n3890), .Y(n937) );
OAI21X1TS U1360 ( .A0(n4611), .A1(n4610), .B0(n4609), .Y(n4612) );
OAI21X1TS U1361 ( .A0(n838), .A1(n2576), .B0(n2553), .Y(n2554) );
AOI21X2TS U1362 ( .A0(n921), .A1(n1685), .B0(n1169), .Y(n1677) );
NAND2X1TS U1363 ( .A(DP_OP_168J30_122_4811_n3930), .B(
DP_OP_168J30_122_4811_n3924), .Y(n3638) );
OR2X2TS U1364 ( .A(n1352), .B(n1351), .Y(n864) );
ADDFHX2TS U1365 ( .A(DP_OP_168J30_122_4811_n626), .B(
DP_OP_168J30_122_4811_n629), .CI(n1786), .CO(n1778), .S(n1932) );
OAI21X1TS U1366 ( .A0(n4011), .A1(n838), .B0(n2187), .Y(n2188) );
OR2X2TS U1367 ( .A(DP_OP_168J30_122_4811_n3882), .B(n1338), .Y(n936) );
OAI21X2TS U1368 ( .A0(n4566), .A1(n4569), .B0(n4567), .Y(n4564) );
OAI21X1TS U1369 ( .A0(n4611), .A1(n2576), .B0(n2555), .Y(n2556) );
OAI21X1TS U1370 ( .A0(n838), .A1(n4546), .B0(n2473), .Y(n2474) );
OAI21X1TS U1371 ( .A0(n838), .A1(n2313), .B0(n3729), .Y(n3730) );
AOI21X2TS U1372 ( .A0(n871), .A1(n3699), .B0(n1565), .Y(n4569) );
OAI21X1TS U1373 ( .A0(n2186), .A1(n2182), .B0(n2183), .Y(n2167) );
ADDFHX2TS U1374 ( .A(DP_OP_168J30_122_4811_n639), .B(
DP_OP_168J30_122_4811_n649), .CI(n1791), .CO(n1786), .S(n1930) );
OR2X2TS U1375 ( .A(n1365), .B(n1364), .Y(n935) );
OAI21X1TS U1376 ( .A0(n839), .A1(n4546), .B0(n2477), .Y(n2478) );
AOI21X1TS U1377 ( .A0(n931), .A1(n2190), .B0(n2152), .Y(n2186) );
OAI21X1TS U1378 ( .A0(n839), .A1(n4610), .B0(n3998), .Y(n3999) );
ADDFHX2TS U1379 ( .A(DP_OP_168J30_122_4811_n650), .B(
DP_OP_168J30_122_4811_n660), .CI(n1796), .CO(n1791), .S(n1928) );
OAI21X1TS U1380 ( .A0(n3136), .A1(n2876), .B0(n2882), .Y(n2883) );
OAI21X1TS U1381 ( .A0(n839), .A1(n2576), .B0(n2557), .Y(n2558) );
OAI21X1TS U1382 ( .A0(n3154), .A1(n2852), .B0(n1611), .Y(n1612) );
OAI21X1TS U1383 ( .A0(n2313), .A1(n839), .B0(n2299), .Y(n2300) );
CMPR42X2TS U1384 ( .A(DP_OP_168J30_122_4811_n803), .B(
DP_OP_168J30_122_4811_n1978), .C(DP_OP_168J30_122_4811_n637), .D(
DP_OP_168J30_122_4811_n1055), .ICI(DP_OP_168J30_122_4811_n638), .S(
DP_OP_168J30_122_4811_n626), .ICO(DP_OP_168J30_122_4811_n624), .CO(
DP_OP_168J30_122_4811_n625) );
OAI21X1TS U1385 ( .A0(n3154), .A1(n2876), .B0(n2878), .Y(n2879) );
OAI21X1TS U1386 ( .A0(n4011), .A1(n839), .B0(n4010), .Y(n4012) );
OAI21X1TS U1387 ( .A0(n3527), .A1(n3284), .B0(n3258), .Y(n3259) );
OAI21X1TS U1388 ( .A0(n3527), .A1(n1174), .B0(n3526), .Y(n3528) );
OAI21X1TS U1389 ( .A0(n3527), .A1(n3446), .B0(n3421), .Y(n3422) );
OAI21X1TS U1390 ( .A0(n3795), .A1(n2852), .B0(n2831), .Y(n2832) );
OAI21X1TS U1391 ( .A0(n3527), .A1(n1275), .B0(n3469), .Y(n3470) );
AOI21X2TS U1392 ( .A0(n739), .A1(n845), .B0(n1165), .Y(n1696) );
OAI21X1TS U1393 ( .A0(n3527), .A1(n3339), .B0(n3313), .Y(n3314) );
NAND2X1TS U1394 ( .A(DP_OP_168J30_122_4811_n4086), .B(n1167), .Y(n1689) );
OAI21X1TS U1395 ( .A0(n3527), .A1(n3189), .B0(n3364), .Y(n3365) );
OAI21X1TS U1396 ( .A0(n3795), .A1(n2876), .B0(n2885), .Y(n2886) );
ADDFHX2TS U1397 ( .A(DP_OP_168J30_122_4811_n661), .B(
DP_OP_168J30_122_4811_n664), .CI(n1807), .CO(n1796), .S(n1927) );
OAI21X1TS U1398 ( .A0(n2313), .A1(n840), .B0(n2301), .Y(n2302) );
OAI21X1TS U1399 ( .A0(n840), .A1(n4610), .B0(n3993), .Y(n3994) );
OAI21X1TS U1400 ( .A0(n840), .A1(n4546), .B0(n2479), .Y(n2480) );
NAND2X1TS U1401 ( .A(DP_OP_168J30_122_4811_n4097), .B(n1166), .Y(n1694) );
OAI21X1TS U1402 ( .A0(n3786), .A1(n2852), .B0(n2833), .Y(n2834) );
INVX4TS U1403 ( .A(n1385), .Y(n3795) );
XOR2X1TS U1404 ( .A(n1292), .B(Op_MX[38]), .Y(n1311) );
XOR2X1TS U1405 ( .A(n3777), .B(n4657), .Y(DP_OP_168J30_122_4811_n2946) );
OAI21X1TS U1406 ( .A0(n982), .A1(n3284), .B0(n3256), .Y(n3257) );
OAI21X1TS U1407 ( .A0(n982), .A1(n3243), .B0(n1347), .Y(n1348) );
XOR2X1TS U1408 ( .A(n1304), .B(n3980), .Y(n1319) );
OAI21X1TS U1409 ( .A0(n982), .A1(n3446), .B0(n3419), .Y(n3420) );
OAI21X1TS U1410 ( .A0(n982), .A1(n3339), .B0(n3311), .Y(n3312) );
ADDFHX2TS U1411 ( .A(DP_OP_168J30_122_4811_n672), .B(
DP_OP_168J30_122_4811_n681), .CI(n1815), .CO(n1807), .S(n1925) );
OAI21X1TS U1412 ( .A0(n982), .A1(n3189), .B0(n3361), .Y(n3362) );
OAI21X1TS U1413 ( .A0(n928), .A1(n2576), .B0(n2561), .Y(n2562) );
OAI21X1TS U1414 ( .A0(n4267), .A1(n4546), .B0(n3972), .Y(n3973) );
AOI222X1TS U1415 ( .A0(n4315), .A1(n3943), .B0(n790), .B1(n4373), .C0(n4608),
.C1(n4372), .Y(n2625) );
OAI21X1TS U1416 ( .A0(n928), .A1(n4546), .B0(n4545), .Y(n4547) );
AOI222X1TS U1417 ( .A0(n790), .A1(n4332), .B0(n4608), .B1(n4331), .C0(n4607),
.C1(n4330), .Y(n2709) );
AOI222X1TS U1418 ( .A0(n4315), .A1(n4332), .B0(n790), .B1(n4331), .C0(n4608),
.C1(n4330), .Y(n2707) );
AOI222X1TS U1419 ( .A0(n4315), .A1(n4362), .B0(n790), .B1(n4261), .C0(n4608),
.C1(n4260), .Y(n2671) );
NAND2X1TS U1420 ( .A(n2177), .B(n2176), .Y(n2178) );
AOI222X1TS U1421 ( .A0(n4660), .A1(n2495), .B0(n790), .B1(n4543), .C0(n3728),
.C1(n2487), .Y(n2471) );
AOI222X1TS U1422 ( .A0(n790), .A1(n4362), .B0(n4608), .B1(n4261), .C0(n4607),
.C1(n4260), .Y(n2673) );
AOI222X1TS U1423 ( .A0(n790), .A1(n2406), .B0(n3728), .B1(n4606), .C0(n4607),
.C1(n2398), .Y(n2390) );
OAI21X1TS U1424 ( .A0(n3531), .A1(n3446), .B0(n3423), .Y(n3424) );
ADDFHX2TS U1425 ( .A(DP_OP_168J30_122_4811_n682), .B(
DP_OP_168J30_122_4811_n691), .CI(n1822), .CO(n1815), .S(n1923) );
OAI21X1TS U1426 ( .A0(n3531), .A1(n1275), .B0(n3471), .Y(n3472) );
OAI21X1TS U1427 ( .A0(n2313), .A1(n928), .B0(n4617), .Y(n4618) );
OAI21X1TS U1428 ( .A0(n2313), .A1(n4267), .B0(n3996), .Y(n3997) );
NAND2X1TS U1429 ( .A(DP_OP_168J30_122_4811_n2476), .B(n1563), .Y(n4540) );
AOI222X1TS U1430 ( .A0(n4227), .A1(n4314), .B0(n4315), .B1(n4312), .C0(n790),
.C1(n2734), .Y(n2742) );
OAI21X1TS U1431 ( .A0(n3531), .A1(n3243), .B0(n3226), .Y(n3227) );
OAI21X1TS U1432 ( .A0(n1359), .A1(n3243), .B0(n1336), .Y(n1337) );
AOI222X1TS U1433 ( .A0(n790), .A1(n4314), .B0(n4608), .B1(n4312), .C0(n4607),
.C1(n2734), .Y(n2744) );
OAI21X1TS U1434 ( .A0(n3776), .A1(n2852), .B0(n2835), .Y(n2836) );
OAI21X1TS U1435 ( .A0(n4011), .A1(n928), .B0(n2206), .Y(n2207) );
AOI222X1TS U1436 ( .A0(n4661), .A1(n2406), .B0(n4660), .B1(n4606), .C0(n790),
.C1(n2398), .Y(n2386) );
NAND2X1TS U1437 ( .A(n1708), .B(n1707), .Y(n1710) );
OAI21X1TS U1438 ( .A0(n1359), .A1(n3284), .B0(n1309), .Y(n1310) );
OAI21X1TS U1439 ( .A0(n3531), .A1(n3284), .B0(n3260), .Y(n3261) );
OAI21X1TS U1440 ( .A0(n1359), .A1(n3189), .B0(n1297), .Y(n1298) );
AOI222X1TS U1441 ( .A0(n4660), .A1(n2317), .B0(n790), .B1(n4659), .C0(n2309),
.C1(n4608), .Y(n4005) );
OAI21X1TS U1442 ( .A0(n3531), .A1(n3189), .B0(n3367), .Y(n3368) );
OAI21X1TS U1443 ( .A0(n3535), .A1(n3189), .B0(n3370), .Y(n3371) );
OAI21X1TS U1444 ( .A0(n3535), .A1(n3339), .B0(n3317), .Y(n3318) );
XNOR2X2TS U1445 ( .A(n1713), .B(n862), .Y(n3633) );
OAI21X1TS U1446 ( .A0(n2313), .A1(n4325), .B0(n3991), .Y(n3992) );
OAI21X1TS U1447 ( .A0(n3780), .A1(n2852), .B0(n2837), .Y(n2838) );
OAI21X1TS U1448 ( .A0(n3535), .A1(n3446), .B0(n3425), .Y(n3426) );
NOR2X1TS U1449 ( .A(n2168), .B(n2175), .Y(n2154) );
OAI21X1TS U1450 ( .A0(n3535), .A1(n3284), .B0(n3262), .Y(n3263) );
AOI222X1TS U1451 ( .A0(n4227), .A1(n3943), .B0(n4315), .B1(n4373), .C0(n4313), .C1(n4372), .Y(n2623) );
OAI21X1TS U1452 ( .A0(n3535), .A1(n3243), .B0(n3228), .Y(n3229) );
BUFX4TS U1453 ( .A(n4313), .Y(n790) );
AOI222X1TS U1454 ( .A0(n4313), .A1(n3911), .B0(n4608), .B1(n4381), .C0(n4607), .C1(n4379), .Y(n2553) );
OAI21X1TS U1455 ( .A0(n3767), .A1(n3189), .B0(n3372), .Y(n3373) );
OAI21X1TS U1456 ( .A0(n3767), .A1(n3339), .B0(n3319), .Y(n3320) );
NOR2X2TS U1457 ( .A(n2547), .B(n4313), .Y(n2175) );
OAI21X1TS U1458 ( .A0(n4610), .A1(n4552), .B0(n4551), .Y(n4553) );
ADDHXLTS U1459 ( .A(n3915), .B(n3914), .CO(n4301), .S(n3843) );
OAI21X1TS U1460 ( .A0(n3773), .A1(n2852), .B0(n2839), .Y(n2840) );
OAI21X1TS U1461 ( .A0(n4461), .A1(n2852), .B0(n2766), .Y(n2767) );
OAI21X1TS U1462 ( .A0(n3760), .A1(n3189), .B0(n3374), .Y(n3375) );
OAI21X1TS U1463 ( .A0(n3760), .A1(n3446), .B0(n3429), .Y(n3430) );
NAND2X1TS U1464 ( .A(n1721), .B(n1720), .Y(n1722) );
OAI21X2TS U1465 ( .A0(n1719), .A1(n896), .B0(n1720), .Y(n1716) );
NAND2X1TS U1466 ( .A(n931), .B(n2189), .Y(n2191) );
NOR2X1TS U1467 ( .A(DP_OP_168J30_122_4811_n2508), .B(n1559), .Y(n4529) );
OAI21X1TS U1468 ( .A0(n3760), .A1(n3284), .B0(n3266), .Y(n3267) );
OAI21X1TS U1469 ( .A0(n3760), .A1(n3243), .B0(n3232), .Y(n3233) );
OAI21X1TS U1470 ( .A0(n3760), .A1(n3339), .B0(n3321), .Y(n3322) );
AOI222X1TS U1471 ( .A0(n4607), .A1(n4314), .B0(n4327), .B1(n4312), .C0(n4658), .C1(n2734), .Y(n2746) );
OAI21X1TS U1472 ( .A0(n3756), .A1(n3243), .B0(n3163), .Y(n3164) );
OR2X2TS U1473 ( .A(n2135), .B(Op_MY[25]), .Y(n2129) );
OR2X2TS U1474 ( .A(n3728), .B(n4008), .Y(n931) );
OAI21X1TS U1475 ( .A0(n3756), .A1(n3284), .B0(n3268), .Y(n3269) );
OAI21X1TS U1476 ( .A0(n3756), .A1(n3339), .B0(n3323), .Y(n3324) );
OAI21X1TS U1477 ( .A0(n3756), .A1(n3446), .B0(n3431), .Y(n3432) );
NAND2X1TS U1478 ( .A(n1726), .B(n1725), .Y(n1728) );
OAI21X1TS U1479 ( .A0(n3756), .A1(n3189), .B0(n3376), .Y(n3377) );
OAI21X1TS U1480 ( .A0(n3548), .A1(n3339), .B0(n3325), .Y(n3326) );
OAI21X1TS U1481 ( .A0(n3548), .A1(n3284), .B0(n3270), .Y(n3271) );
XNOR2X2TS U1482 ( .A(n2025), .B(n2024), .Y(n4306) );
AOI222X1TS U1483 ( .A0(n4327), .A1(n4314), .B0(n4658), .B1(n4312), .C0(n4544), .C1(n2734), .Y(n4248) );
OAI21X1TS U1484 ( .A0(n3548), .A1(n3243), .B0(n3234), .Y(n3235) );
ADDHXLTS U1485 ( .A(n4161), .B(n4160), .CO(n4223), .S(n3942) );
NOR2X1TS U1486 ( .A(DP_OP_168J30_122_4811_n2528), .B(n1556), .Y(n3690) );
OAI21X1TS U1487 ( .A0(n3552), .A1(n3284), .B0(n3272), .Y(n3273) );
OAI21X1TS U1488 ( .A0(n3552), .A1(n3189), .B0(n3380), .Y(n3381) );
AOI222X1TS U1489 ( .A0(n2406), .A1(n4658), .B0(n4606), .B1(n4615), .C0(n2398), .C1(n3995), .Y(n2392) );
OAI21XLTS U1490 ( .A0(n2360), .A1(n4163), .B0(n2315), .Y(n2316) );
OAI21X1TS U1491 ( .A0(n3552), .A1(n3243), .B0(n3236), .Y(n3237) );
OAI21X1TS U1492 ( .A0(n3682), .A1(n3685), .B0(n3683), .Y(n3688) );
OAI21X1TS U1493 ( .A0(n3552), .A1(n3339), .B0(n3327), .Y(n3328) );
OAI21XLTS U1494 ( .A0(n4610), .A1(n4163), .B0(n2404), .Y(n2405) );
NOR2X1TS U1495 ( .A(DP_OP_168J30_122_4811_n2544), .B(n1553), .Y(n4521) );
INVX2TS U1496 ( .A(n1418), .Y(n4467) );
AOI21X1TS U1497 ( .A0(n877), .A1(n4506), .B0(n1549), .Y(n3685) );
OAI21X1TS U1498 ( .A0(n3557), .A1(n3243), .B0(n3238), .Y(n3239) );
XNOR2X2TS U1499 ( .A(n1955), .B(n902), .Y(n4320) );
OAI21X1TS U1500 ( .A0(n3557), .A1(n3339), .B0(n3329), .Y(n3330) );
OAI21X1TS U1501 ( .A0(n3557), .A1(n3284), .B0(n3274), .Y(n3275) );
OAI21X1TS U1502 ( .A0(n4519), .A1(n2852), .B0(n2847), .Y(n2849) );
NAND2X1TS U1503 ( .A(DP_OP_168J30_122_4811_n4176), .B(n1152), .Y(n1949) );
OAI21X1TS U1504 ( .A0(n3752), .A1(n3243), .B0(n3242), .Y(n3244) );
OAI21X1TS U1505 ( .A0(n3752), .A1(n3284), .B0(n3276), .Y(n3277) );
ADDHXLTS U1506 ( .A(n3618), .B(n3617), .CO(DP_OP_168J30_122_4811_n657), .S(
DP_OP_168J30_122_4811_n658) );
NOR2X1TS U1507 ( .A(DP_OP_168J30_122_4811_n4176), .B(n1152), .Y(n1948) );
OAI21X1TS U1508 ( .A0(n3801), .A1(n2852), .B0(n2774), .Y(n2775) );
OAI21XLTS U1509 ( .A0(n4610), .A1(n4221), .B0(n2411), .Y(n2412) );
OAI21X1TS U1510 ( .A0(n3752), .A1(n3339), .B0(n3331), .Y(n3332) );
AOI222X1TS U1511 ( .A0(n2406), .A1(n4615), .B0(n4606), .B1(n3995), .C0(n2398), .C1(n4550), .Y(n2394) );
OAI21X1TS U1512 ( .A0(n3752), .A1(n3189), .B0(n3384), .Y(n3385) );
NOR2X1TS U1513 ( .A(DP_OP_168J30_122_4811_n2559), .B(n1550), .Y(n3682) );
OAI21X1TS U1514 ( .A0(n3743), .A1(n3339), .B0(n3334), .Y(n3335) );
AOI222X1TS U1515 ( .A0(n2406), .A1(n3995), .B0(n4606), .B1(n4550), .C0(n2398), .C1(n4549), .Y(n2396) );
OAI21X1TS U1516 ( .A0(n3743), .A1(n3243), .B0(n3177), .Y(n3178) );
OAI21XLTS U1517 ( .A0(n2360), .A1(n4212), .B0(n2328), .Y(n2329) );
AOI222X1TS U1518 ( .A0(n2317), .A1(n3995), .B0(n4659), .B1(n4550), .C0(n2309), .C1(n4549), .Y(n3991) );
NAND2BX2TS U1519 ( .AN(n2172), .B(n2170), .Y(n2235) );
OAI21XLTS U1520 ( .A0(n2360), .A1(n4409), .B0(n2330), .Y(n2331) );
INVX2TS U1521 ( .A(n1432), .Y(n3798) );
OAI21X1TS U1522 ( .A0(n4480), .A1(n4483), .B0(n4481), .Y(n4491) );
AOI222X1TS U1523 ( .A0(n2358), .A1(n2407), .B0(n2356), .B1(n4630), .C0(n2353), .C1(n4604), .Y(n2318) );
OAI21XLTS U1524 ( .A0(n2643), .A1(n4383), .B0(n3930), .Y(n3931) );
ADDHXLTS U1525 ( .A(n4289), .B(n4288), .CO(DP_OP_168J30_122_4811_n729), .S(
DP_OP_168J30_122_4811_n730) );
AOI222X1TS U1526 ( .A0(n2317), .A1(n4656), .B0(n2356), .B1(n2407), .C0(n2353), .C1(n4630), .Y(n2315) );
OAI21X1TS U1527 ( .A0(n3740), .A1(n3243), .B0(n3184), .Y(n3185) );
OAI21X1TS U1528 ( .A0(n3571), .A1(n4643), .B0(n3173), .Y(n3174) );
OAI21XLTS U1529 ( .A0(n3919), .A1(n4233), .B0(n3936), .Y(n3937) );
AOI21X1TS U1530 ( .A0(n866), .A1(n847), .B0(n1144), .Y(n1969) );
AOI21X1TS U1531 ( .A0(n749), .A1(n4188), .B0(n1543), .Y(n4483) );
NOR2X1TS U1532 ( .A(DP_OP_168J30_122_4811_n4193), .B(n1147), .Y(n1961) );
INVX2TS U1533 ( .A(n2259), .Y(n4233) );
OR2X2TS U1534 ( .A(n959), .B(Op_MX[25]), .Y(n1626) );
NAND2BX4TS U1535 ( .AN(n2291), .B(n2292), .Y(n2313) );
AND3X4TS U1536 ( .A(n2292), .B(n2287), .C(n2291), .Y(n2309) );
OAI21XLTS U1537 ( .A0(n4365), .A1(n4212), .B0(n4201), .Y(n4202) );
CMPR42X1TS U1538 ( .A(DP_OP_168J30_122_4811_n818), .B(
DP_OP_168J30_122_4811_n1993), .C(DP_OP_168J30_122_4811_n762), .D(
DP_OP_168J30_122_4811_n760), .ICI(DP_OP_168J30_122_4811_n759), .S(
DP_OP_168J30_122_4811_n757), .ICO(DP_OP_168J30_122_4811_n755), .CO(
DP_OP_168J30_122_4811_n756) );
OAI21XLTS U1539 ( .A0(n2656), .A1(n4409), .B0(n4203), .Y(n4204) );
ADDHXLTS U1540 ( .A(n4124), .B(n4123), .CO(n4127), .S(
DP_OP_168J30_122_4811_n749) );
OAI21XLTS U1541 ( .A0(n4409), .A1(n4408), .B0(n4407), .Y(n4411) );
OAI21XLTS U1542 ( .A0(n2643), .A1(n926), .B0(n2650), .Y(n2651) );
OAI21XLTS U1543 ( .A0(n2656), .A1(n4488), .B0(n4235), .Y(n4236) );
AOI21X1TS U1544 ( .A0(n867), .A1(n4369), .B0(n1536), .Y(n4428) );
OAI21XLTS U1545 ( .A0(n2643), .A1(n4488), .B0(n2647), .Y(n2649) );
AOI222X1TS U1546 ( .A0(n2580), .A1(n4655), .B0(n2574), .B1(n2725), .C0(n2573), .C1(n4604), .Y(n3830) );
OAI21X1TS U1547 ( .A0(n4348), .A1(n4351), .B0(n4349), .Y(n4369) );
AOI21X1TS U1548 ( .A0(n2280), .A1(n914), .B0(n980), .Y(n2162) );
OAI21XLTS U1549 ( .A0(n4365), .A1(n4121), .B0(n2693), .Y(n2694) );
OAI21XLTS U1550 ( .A0(n4408), .A1(n4498), .B0(n4284), .Y(n4285) );
OAI21XLTS U1551 ( .A0(n4408), .A1(n926), .B0(n4280), .Y(n4281) );
OAI21XLTS U1552 ( .A0(n4408), .A1(n4121), .B0(n4120), .Y(n4122) );
OAI21XLTS U1553 ( .A0(n2656), .A1(n4498), .B0(n4176), .Y(n4177) );
AND3X4TS U1554 ( .A(n2385), .B(n2380), .C(n2384), .Y(n2398) );
AOI222X1TS U1555 ( .A0(n2580), .A1(n2725), .B0(n2574), .B1(n2728), .C0(n2573), .C1(n4603), .Y(n3837) );
ADDHXLTS U1556 ( .A(n4410), .B(n4115), .CO(n4118), .S(
DP_OP_168J30_122_4811_n759) );
INVX2TS U1557 ( .A(n2333), .Y(n4488) );
XNOR2X1TS U1558 ( .A(n4343), .B(n4342), .Y(n4814) );
BUFX3TS U1559 ( .A(n2581), .Y(n2574) );
OAI21X1TS U1560 ( .A0(n2274), .A1(n2270), .B0(n2271), .Y(n2280) );
AND3X4TS U1561 ( .A(n2468), .B(n2463), .C(n2467), .Y(n2487) );
AOI21X1TS U1562 ( .A0(n1531), .A1(n1530), .B0(n1529), .Y(n4351) );
OAI21XLTS U1563 ( .A0(n2733), .A1(n1226), .B0(n1228), .Y(n1229) );
XNOR2X2TS U1564 ( .A(n2277), .B(n2276), .Y(n2400) );
AND3X4TS U1565 ( .A(n2546), .B(n2541), .C(n2545), .Y(n2573) );
OAI21XLTS U1566 ( .A0(n2733), .A1(n4495), .B0(n1216), .Y(n1217) );
OAI21XLTS U1567 ( .A0(n4121), .A1(n2733), .B0(n3904), .Y(n3905) );
OAI21XLTS U1568 ( .A0(n2733), .A1(n1230), .B0(n841), .Y(n1231) );
AND3X4TS U1569 ( .A(n2622), .B(n2617), .C(n2621), .Y(n2646) );
AND3X4TS U1570 ( .A(n2659), .B(n2663), .C(n2664), .Y(n2690) );
OAI21X1TS U1571 ( .A0(n2375), .A1(n2371), .B0(n2372), .Y(n2277) );
ADDHXLTS U1572 ( .A(n1078), .B(n1077), .CO(n3954), .S(n1100) );
AND3X4TS U1573 ( .A(n2698), .B(n2703), .C(n2704), .Y(n2721) );
NOR2X1TS U1574 ( .A(n1528), .B(n1527), .Y(n4339) );
ADDHXLTS U1575 ( .A(n3980), .B(n3979), .CO(n3981), .S(
DP_OP_168J30_122_4811_n4159) );
ADDHXLTS U1576 ( .A(n3465), .B(n3963), .CO(n3959), .S(
DP_OP_168J30_122_4811_n4195) );
ADDHXLTS U1577 ( .A(n4035), .B(n4034), .CO(n4041), .S(n4047) );
ADDHXLTS U1578 ( .A(n4649), .B(n3895), .CO(n4576), .S(
DP_OP_168J30_122_4811_n4105) );
XNOR2X2TS U1579 ( .A(n2455), .B(n2454), .Y(n2577) );
OAI21XLTS U1580 ( .A0(n4624), .A1(n3243), .B0(n3885), .Y(n3886) );
OAI21XLTS U1581 ( .A0(n1523), .A1(n4083), .B0(n1197), .Y(n1198) );
ADDHXLTS U1582 ( .A(n4670), .B(n4066), .CO(n4070), .S(
DP_OP_168J30_122_4811_n2549) );
AND3X4TS U1583 ( .A(n1215), .B(n1214), .C(n1206), .Y(n2734) );
OAI21XLTS U1584 ( .A0(n4596), .A1(n4643), .B0(n4595), .Y(n4601) );
OAI21XLTS U1585 ( .A0(n4587), .A1(n4643), .B0(n4586), .Y(n4598) );
OAI21XLTS U1586 ( .A0(n4624), .A1(n4643), .B0(n4623), .Y(n4629) );
AOI21X2TS U1587 ( .A0(n2440), .A1(n2439), .B0(n2438), .Y(n2530) );
AOI21X1TS U1588 ( .A0(n2440), .A1(n974), .B0(n973), .Y(n2366) );
OR2X4TS U1589 ( .A(n5369), .B(FSM_selector_C), .Y(n4744) );
OAI21XLTS U1590 ( .A0(n3893), .A1(n4643), .B0(n3887), .Y(n4589) );
OAI21XLTS U1591 ( .A0(n4435), .A1(n4083), .B0(n834), .Y(n1490) );
INVX2TS U1592 ( .A(n2440), .Y(n2608) );
AOI22X1TS U1593 ( .A0(n3463), .A1(Op_MY[27]), .B0(n3199), .B1(n3516), .Y(
n3213) );
AOI222X1TS U1594 ( .A0(n4646), .A1(Op_MY[33]), .B0(n4645), .B1(Op_MY[32]),
.C0(n3240), .C1(Op_MY[31]), .Y(n4591) );
AOI222X1TS U1595 ( .A0(n4646), .A1(Op_MY[32]), .B0(n4645), .B1(Op_MY[31]),
.C0(n3240), .C1(Op_MY[30]), .Y(n4581) );
AOI222X1TS U1596 ( .A0(n4646), .A1(Op_MY[31]), .B0(n4645), .B1(Op_MY[30]),
.C0(n3240), .C1(Op_MY[29]), .Y(n3885) );
AOI222X1TS U1597 ( .A0(n4646), .A1(Op_MY[30]), .B0(n4645), .B1(Op_MY[29]),
.C0(n3183), .C1(n4594), .Y(n3888) );
AOI22X1TS U1598 ( .A0(n1428), .A1(n4081), .B0(n1521), .B1(n4131), .Y(n1197)
);
NAND2X1TS U1599 ( .A(n3598), .B(Op_MY[27]), .Y(n1092) );
AOI222X1TS U1600 ( .A0(n4646), .A1(Op_MY[39]), .B0(n4645), .B1(Op_MY[38]),
.C0(n3183), .C1(Op_MY[37]), .Y(n3250) );
BUFX3TS U1601 ( .A(n3191), .Y(n3389) );
AOI22X1TS U1602 ( .A0(n2971), .A1(n4081), .B0(n2975), .B1(n4131), .Y(n4082)
);
BUFX3TS U1603 ( .A(n3287), .Y(n3863) );
AOI21X1TS U1604 ( .A0(n2605), .A1(n968), .B0(n967), .Y(n2437) );
BUFX3TS U1605 ( .A(n3246), .Y(n3241) );
AOI22X1TS U1606 ( .A0(n2880), .A1(n4081), .B0(n2884), .B1(n4131), .Y(n2817)
);
BUFX3TS U1607 ( .A(n3287), .Y(n3282) );
OAI21X1TS U1608 ( .A0(n2528), .A1(n2531), .B0(n2532), .Y(n2442) );
OAI21X1TS U1609 ( .A0(n2447), .A1(n2452), .B0(n2448), .Y(n969) );
AND3X4TS U1610 ( .A(n934), .B(n986), .C(n888), .Y(n1035) );
NOR2X6TS U1611 ( .A(n2765), .B(n2764), .Y(n2785) );
NOR2X2TS U1612 ( .A(n1243), .B(n1245), .Y(n1259) );
OAI21X2TS U1613 ( .A0(n1250), .A1(n1245), .B0(n1246), .Y(n1261) );
NOR2X6TS U1614 ( .A(n1307), .B(n1306), .Y(n3290) );
AND3X4TS U1615 ( .A(n1295), .B(n1293), .C(n1294), .Y(n3192) );
AND3X4TS U1616 ( .A(n2765), .B(n1605), .C(n2764), .Y(n2787) );
NOR2X1TS U1617 ( .A(n1295), .B(n1294), .Y(n3190) );
NOR2X6TS U1618 ( .A(n1289), .B(n1288), .Y(n3199) );
CLKAND2X4TS U1619 ( .A(n960), .B(n4672), .Y(n4947) );
NOR2X6TS U1620 ( .A(n1334), .B(n1333), .Y(n3249) );
NAND2X1TS U1621 ( .A(Op_MX[33]), .B(Op_MX[6]), .Y(n1262) );
NOR2X2TS U1622 ( .A(Op_MX[33]), .B(Op_MX[6]), .Y(n1263) );
OR2X2TS U1623 ( .A(Op_MX[49]), .B(Op_MX[22]), .Y(n914) );
NOR2X1TS U1624 ( .A(Op_MX[31]), .B(Op_MX[4]), .Y(n1243) );
ADDHX2TS U1625 ( .A(Op_MY[0]), .B(Op_MY[27]), .CO(intadd_76_n36), .S(n4512)
);
NAND2X1TS U1626 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n2597) );
NOR2X4TS U1627 ( .A(n2045), .B(n3628), .Y(n5172) );
CMPR42X2TS U1628 ( .A(DP_OP_168J30_122_4811_n4034), .B(
DP_OP_168J30_122_4811_n4500), .C(DP_OP_168J30_122_4811_n4040), .D(
DP_OP_168J30_122_4811_n4526), .ICI(DP_OP_168J30_122_4811_n4552), .S(
DP_OP_168J30_122_4811_n4031), .ICO(DP_OP_168J30_122_4811_n4029), .CO(
DP_OP_168J30_122_4811_n4030) );
CMPR42X2TS U1629 ( .A(DP_OP_168J30_122_4811_n297), .B(
DP_OP_168J30_122_4811_n303), .C(DP_OP_168J30_122_4811_n1955), .D(
DP_OP_168J30_122_4811_n779), .ICI(n5279), .S(
DP_OP_168J30_122_4811_n294), .ICO(DP_OP_168J30_122_4811_n292), .CO(
DP_OP_168J30_122_4811_n293) );
XOR2X1TS U1630 ( .A(n1231), .B(n4668), .Y(n1902) );
NAND2X1TS U1631 ( .A(n4271), .B(n4477), .Y(n841) );
CMPR42X2TS U1632 ( .A(DP_OP_168J30_122_4811_n366), .B(
DP_OP_168J30_122_4811_n375), .C(n5226), .D(DP_OP_168J30_122_4811_n785),
.ICI(DP_OP_168J30_122_4811_n1960), .S(DP_OP_168J30_122_4811_n363),
.ICO(DP_OP_168J30_122_4811_n361), .CO(DP_OP_168J30_122_4811_n362) );
AOI21X4TS U1633 ( .A0(n1672), .A1(n849), .B0(n1372), .Y(n1665) );
CMPR42X2TS U1634 ( .A(DP_OP_168J30_122_4811_n234), .B(
DP_OP_168J30_122_4811_n235), .C(DP_OP_168J30_122_4811_n1947), .D(
Sgf_operation_ODD1_Q_left[50]), .ICI(DP_OP_168J30_122_4811_n771), .S(
DP_OP_168J30_122_4811_n231), .ICO(DP_OP_168J30_122_4811_n229), .CO(
DP_OP_168J30_122_4811_n230) );
AO21X4TS U1635 ( .A0(n737), .A1(n1703), .B0(n1163), .Y(n845) );
OAI21X2TS U1636 ( .A0(n1706), .A1(n1709), .B0(n1707), .Y(n1703) );
OR2X2TS U1637 ( .A(DP_OP_168J30_122_4811_n4075), .B(n1168), .Y(n921) );
BUFX6TS U1638 ( .A(n987), .Y(n1128) );
NOR2X1TS U1639 ( .A(n986), .B(n888), .Y(n987) );
OAI21X1TS U1640 ( .A0(n1130), .A1(n3893), .B0(n1126), .Y(n1127) );
OA21X4TS U1641 ( .A0(n5131), .A1(n951), .B0(n5132), .Y(n952) );
OA21X4TS U1642 ( .A0(n5122), .A1(n5125), .B0(n5123), .Y(n951) );
OAI21X1TS U1643 ( .A0(n3776), .A1(n1574), .B0(n3775), .Y(n3777) );
AO21X4TS U1644 ( .A0(n918), .A1(n4935), .B0(n1919), .Y(n740) );
AOI21X4TS U1645 ( .A0(n910), .A1(n5076), .B0(n1946), .Y(n5065) );
AO21X4TS U1646 ( .A0(n832), .A1(n4909), .B0(n1909), .Y(n735) );
AOI21X4TS U1647 ( .A0(n907), .A1(n745), .B0(n1931), .Y(n4844) );
AO21X4TS U1648 ( .A0(n906), .A1(n4868), .B0(n1929), .Y(n745) );
AOI21X2TS U1649 ( .A0(n1657), .A1(n885), .B0(n1625), .Y(n1651) );
XNOR2X2TS U1650 ( .A(n1658), .B(n1657), .Y(n2044) );
OA21X2TS U1651 ( .A0(n1724), .A1(n1727), .B0(n1725), .Y(n896) );
XNOR2X2TS U1652 ( .A(n1959), .B(n1958), .Y(n4319) );
AO21X2TS U1653 ( .A0(n738), .A1(n1958), .B0(n1149), .Y(n902) );
XNOR2X2TS U1654 ( .A(n1973), .B(n847), .Y(n4154) );
XNOR2X2TS U1655 ( .A(n1977), .B(n1976), .Y(n4125) );
OAI21XLTS U1656 ( .A0(n4546), .A1(n4409), .B0(n2504), .Y(n2505) );
OAI21XLTS U1657 ( .A0(n4610), .A1(n4253), .B0(n2413), .Y(n2414) );
OAI21XLTS U1658 ( .A0(n2360), .A1(n4383), .B0(n2324), .Y(n2325) );
OAI21XLTS U1659 ( .A0(n3284), .A1(n4587), .B0(n3860), .Y(n3861) );
XOR2X1TS U1660 ( .A(n3971), .B(DP_OP_168J30_122_4811_n66), .Y(n3978) );
OAI21XLTS U1661 ( .A0(n4221), .A1(n3919), .B0(n4220), .Y(n4222) );
OAI21XLTS U1662 ( .A0(n3339), .A1(n4587), .B0(n3854), .Y(n3855) );
OAI21XLTS U1663 ( .A0(n2402), .A1(n4383), .B0(n2415), .Y(n2416) );
OAI21XLTS U1664 ( .A0(n2360), .A1(n4376), .B0(n2318), .Y(n2319) );
CLKAND2X2TS U1665 ( .A(n4510), .B(n4654), .Y(DP_OP_168J30_122_4811_n845) );
OAI21XLTS U1666 ( .A0(n2360), .A1(n4253), .B0(n2322), .Y(n2323) );
OAI21XLTS U1667 ( .A0(n4436), .A1(n2929), .B0(n2918), .Y(n2919) );
OAI21XLTS U1668 ( .A0(n4436), .A1(n2784), .B0(n2859), .Y(n2860) );
OAI21XLTS U1669 ( .A0(n2579), .A1(n4212), .B0(n4165), .Y(n4166) );
OAI21XLTS U1670 ( .A0(n4546), .A1(n4233), .B0(n2500), .Y(n2501) );
OAI21XLTS U1671 ( .A0(n3571), .A1(n3416), .B0(n3393), .Y(n3394) );
OAI21XLTS U1672 ( .A0(n3737), .A1(n3416), .B0(n3399), .Y(n3400) );
CLKAND2X2TS U1673 ( .A(n4508), .B(n4654), .Y(DP_OP_168J30_122_4811_n847) );
OAI21XLTS U1674 ( .A0(n2360), .A1(n4233), .B0(n2326), .Y(n2327) );
OAI21XLTS U1675 ( .A0(n4633), .A1(n3446), .B0(n3202), .Y(n3203) );
OAI21XLTS U1676 ( .A0(n2579), .A1(n4376), .B0(n3830), .Y(n3831) );
OAI21XLTS U1677 ( .A0(n2579), .A1(n4221), .B0(n3837), .Y(n3838) );
OAI21XLTS U1678 ( .A0(n3243), .A1(n3893), .B0(n3892), .Y(n3894) );
OAI21XLTS U1679 ( .A0(n3284), .A1(n3893), .B0(n3864), .Y(n3865) );
INVX2TS U1680 ( .A(n2437), .Y(n2438) );
INVX2TS U1681 ( .A(n2436), .Y(n2439) );
NOR2X1TS U1682 ( .A(n2540), .B(n2547), .Y(n2168) );
OAI21XLTS U1683 ( .A0(n4180), .A1(n2929), .B0(n2810), .Y(n2811) );
OAI21XLTS U1684 ( .A0(n4546), .A1(n4212), .B0(n2502), .Y(n2503) );
OAI21XLTS U1685 ( .A0(n4635), .A1(n3284), .B0(n3299), .Y(n3300) );
OAI21XLTS U1686 ( .A0(n4644), .A1(n3284), .B0(n3303), .Y(n3304) );
OAI21XLTS U1687 ( .A0(n2402), .A1(n4233), .B0(n2417), .Y(n2418) );
INVX2TS U1688 ( .A(n2189), .Y(n2152) );
OAI21XLTS U1689 ( .A0(n3341), .A1(n748), .B0(n3858), .Y(n3859) );
OAI21XLTS U1690 ( .A0(n2313), .A1(n3835), .B0(n2310), .Y(n2312) );
OAI21XLTS U1691 ( .A0(n2360), .A1(n4221), .B0(n2320), .Y(n2321) );
OAI21XLTS U1692 ( .A0(n4446), .A1(n2784), .B0(n2855), .Y(n2856) );
OAI21XLTS U1693 ( .A0(n4325), .A1(n4408), .B0(n4324), .Y(n4326) );
OAI21XLTS U1694 ( .A0(n3579), .A1(n3416), .B0(n3397), .Y(n3398) );
OAI21XLTS U1695 ( .A0(n4635), .A1(n3416), .B0(n3403), .Y(n3404) );
NAND2X1TS U1696 ( .A(n2197), .B(n2196), .Y(n2198) );
INVX2TS U1697 ( .A(n2195), .Y(n2197) );
BUFX6TS U1698 ( .A(n4615), .Y(n4544) );
OAI21XLTS U1699 ( .A0(n4633), .A1(n3416), .B0(n3409), .Y(n3410) );
INVX2TS U1700 ( .A(n2175), .Y(n2177) );
OAI21XLTS U1701 ( .A0(n4624), .A1(n3446), .B0(n3206), .Y(n3207) );
CLKAND2X2TS U1702 ( .A(n4511), .B(n4654), .Y(DP_OP_168J30_122_4811_n846) );
OAI21XLTS U1703 ( .A0(n4467), .A1(n3026), .B0(n3014), .Y(n3015) );
INVX2TS U1704 ( .A(n2337), .Y(n4498) );
OAI21XLTS U1705 ( .A0(n4467), .A1(n2968), .B0(n2956), .Y(n2957) );
NOR2X1TS U1706 ( .A(DP_OP_168J30_122_4811_n3957), .B(
DP_OP_168J30_122_4811_n3949), .Y(n2107) );
OAI21XLTS U1707 ( .A0(n3780), .A1(n3078), .B0(n3056), .Y(n3057) );
OAI21XLTS U1708 ( .A0(n3776), .A1(n3026), .B0(n3002), .Y(n3003) );
NOR2X1TS U1709 ( .A(n1588), .B(n1846), .Y(n1590) );
OAI21XLTS U1710 ( .A0(n2576), .A1(n926), .B0(n2588), .Y(n2589) );
INVX2TS U1711 ( .A(n1816), .Y(n1826) );
OAI21XLTS U1712 ( .A0(n2235), .A1(n1226), .B0(n4485), .Y(n4486) );
NAND2X1TS U1713 ( .A(DP_OP_168J30_122_4811_n2286), .B(
DP_OP_168J30_122_4811_n2278), .Y(n1825) );
NOR2X2TS U1714 ( .A(DP_OP_168J30_122_4811_n2260), .B(
DP_OP_168J30_122_4811_n2267), .Y(n1810) );
NOR2X2TS U1715 ( .A(n1594), .B(n1823), .Y(n1809) );
OAI21XLTS U1716 ( .A0(n4376), .A1(n3919), .B0(n4375), .Y(n4378) );
OAI21XLTS U1717 ( .A0(n4322), .A1(n3919), .B0(n3918), .Y(n3920) );
OAI21XLTS U1718 ( .A0(n2579), .A1(n4163), .B0(n3912), .Y(n3913) );
AOI222X1TS U1719 ( .A0(n4658), .A1(n2495), .B0(n4544), .B1(n4543), .C0(n4614), .C1(n2487), .Y(n4545) );
ADDHXLTS U1720 ( .A(n2809), .B(n2808), .CO(n3900), .S(n2826) );
OAI21XLTS U1721 ( .A0(n2852), .A1(n4083), .B0(n2799), .Y(n2800) );
NOR2XLTS U1722 ( .A(n4643), .B(n748), .Y(n3989) );
OAI21XLTS U1723 ( .A0(n4596), .A1(n3243), .B0(n3888), .Y(n3889) );
OAI21XLTS U1724 ( .A0(n4635), .A1(n3339), .B0(n3355), .Y(n3356) );
OAI21XLTS U1725 ( .A0(n4644), .A1(n3339), .B0(n3359), .Y(n3360) );
OAI21X1TS U1726 ( .A0(n1264), .A1(n1263), .B0(n1262), .Y(n1265) );
OAI21XLTS U1727 ( .A0(n3798), .A1(n2968), .B0(n2963), .Y(n2964) );
OAI21XLTS U1728 ( .A0(n4358), .A1(n2852), .B0(n2792), .Y(n2793) );
NOR2X1TS U1729 ( .A(n1237), .B(n1235), .Y(n962) );
OAI21X1TS U1730 ( .A0(n1237), .A1(n1234), .B0(n1238), .Y(n961) );
OAI21XLTS U1731 ( .A0(n4133), .A1(n2929), .B0(n2812), .Y(n2813) );
OAI21XLTS U1732 ( .A0(n3835), .A1(n4365), .B0(n3819), .Y(n3820) );
OAI21XLTS U1733 ( .A0(n4624), .A1(n3284), .B0(n3307), .Y(n3308) );
OAI21XLTS U1734 ( .A0(n4624), .A1(n3339), .B0(n3875), .Y(n3876) );
OAI21XLTS U1735 ( .A0(n2402), .A1(n4212), .B0(n2419), .Y(n2420) );
CLKAND2X2TS U1736 ( .A(n4571), .B(n4654), .Y(DP_OP_168J30_122_4811_n842) );
OAI21XLTS U1737 ( .A0(n4449), .A1(n3078), .B0(n3065), .Y(n3066) );
OAI21XLTS U1738 ( .A0(n4449), .A1(n3026), .B0(n3010), .Y(n3011) );
INVX2TS U1739 ( .A(n2267), .Y(n4409) );
OAI21XLTS U1740 ( .A0(n4461), .A1(n2968), .B0(n2950), .Y(n2951) );
OAI21XLTS U1741 ( .A0(n4475), .A1(n2968), .B0(n2954), .Y(n2955) );
OAI21X1TS U1742 ( .A0(n2530), .A1(n2444), .B0(n2443), .Y(n2455) );
INVX2TS U1743 ( .A(n2441), .Y(n2444) );
INVX2TS U1744 ( .A(n2442), .Y(n2443) );
AOI21X1TS U1745 ( .A0(n2154), .A1(n2167), .B0(n2153), .Y(n2286) );
INVX2TS U1746 ( .A(n2176), .Y(n2153) );
OAI21XLTS U1747 ( .A0(n4610), .A1(n4498), .B0(n2425), .Y(n2426) );
NAND2X1TS U1748 ( .A(n2297), .B(n2296), .Y(n2298) );
INVX2TS U1749 ( .A(n2295), .Y(n2297) );
OAI21XLTS U1750 ( .A0(n3575), .A1(n3416), .B0(n3395), .Y(n3396) );
OAI21XLTS U1751 ( .A0(n4648), .A1(n3416), .B0(n3401), .Y(n3402) );
BUFX6TS U1752 ( .A(n3995), .Y(n4614) );
OAI21XLTS U1753 ( .A0(n4644), .A1(n3416), .B0(n3407), .Y(n3408) );
CLKAND2X2TS U1754 ( .A(n4509), .B(n4654), .Y(DP_OP_168J30_122_4811_n848) );
BUFX6TS U1755 ( .A(n3728), .Y(n4608) );
OAI21XLTS U1756 ( .A0(n840), .A1(n2695), .B0(n4328), .Y(n4329) );
OAI21XLTS U1757 ( .A0(n4596), .A1(n3416), .B0(n3415), .Y(n3418) );
OAI21XLTS U1758 ( .A0(n3579), .A1(n3600), .B0(n3578), .Y(n3580) );
OAI21XLTS U1759 ( .A0(n4596), .A1(n3446), .B0(n3208), .Y(n3209) );
OAI21XLTS U1760 ( .A0(n2235), .A1(n4163), .B0(n2239), .Y(n2240) );
CLKAND2X2TS U1761 ( .A(n4572), .B(n4654), .Y(DP_OP_168J30_122_4811_n843) );
OAI21XLTS U1762 ( .A0(n4011), .A1(n4212), .B0(n2264), .Y(n2265) );
CLKAND2X2TS U1763 ( .A(n4562), .B(n4654), .Y(DP_OP_168J30_122_4811_n844) );
OAI21XLTS U1764 ( .A0(n3801), .A1(n3026), .B0(n3018), .Y(n3019) );
OAI21XLTS U1765 ( .A0(n3795), .A1(n3078), .B0(n3050), .Y(n3051) );
OAI21XLTS U1766 ( .A0(n4519), .A1(n2876), .B0(n2903), .Y(n2904) );
OAI21XLTS U1767 ( .A0(n4546), .A1(n4498), .B0(n2508), .Y(n2509) );
NOR2X1TS U1768 ( .A(n1810), .B(n1802), .Y(n1596) );
INVX2TS U1769 ( .A(n1847), .Y(n1837) );
NOR2X1TS U1770 ( .A(n2107), .B(n3672), .Y(n1313) );
OAI21X2TS U1771 ( .A0(n2110), .A1(n3678), .B0(n2111), .Y(n3669) );
CMPR42X1TS U1772 ( .A(DP_OP_168J30_122_4811_n3960), .B(
DP_OP_168J30_122_4811_n3952), .C(DP_OP_168J30_122_4811_n3956), .D(
DP_OP_168J30_122_4811_n4440), .ICI(DP_OP_168J30_122_4811_n4466), .S(
DP_OP_168J30_122_4811_n3949), .ICO(DP_OP_168J30_122_4811_n3947), .CO(
DP_OP_168J30_122_4811_n3948) );
OAI21XLTS U1773 ( .A0(n4011), .A1(n926), .B0(n4502), .Y(n4504) );
OAI21XLTS U1774 ( .A0(n3776), .A1(n3118), .B0(n3094), .Y(n3095) );
OAI21XLTS U1775 ( .A0(n3776), .A1(n3078), .B0(n3054), .Y(n3055) );
XOR2X1TS U1776 ( .A(n1442), .B(DP_OP_168J30_122_4811_n2003), .Y(n1550) );
XOR2X1TS U1777 ( .A(n1425), .B(DP_OP_168J30_122_4811_n2003), .Y(n1556) );
OR2X1TS U1778 ( .A(DP_OP_168J30_122_4811_n2296), .B(
DP_OP_168J30_122_4811_n2306), .Y(n824) );
OAI21XLTS U1779 ( .A0(n2360), .A1(n1226), .B0(n756), .Y(n2357) );
XOR2X1TS U1780 ( .A(n1396), .B(DP_OP_168J30_122_4811_n2003), .Y(n1566) );
INVX2TS U1781 ( .A(n1823), .Y(n1831) );
INVX2TS U1782 ( .A(n2100), .Y(n3659) );
AOI21X1TS U1783 ( .A0(n3659), .A1(n2102), .B0(n2094), .Y(n2095) );
INVX2TS U1784 ( .A(n3640), .Y(n2094) );
NOR2X2TS U1785 ( .A(DP_OP_168J30_122_4811_n3958), .B(n1311), .Y(n2110) );
XOR2X1TS U1786 ( .A(n1503), .B(Op_MX[2]), .Y(n1539) );
XOR2X1TS U1787 ( .A(n1450), .B(DP_OP_168J30_122_4811_n2003), .Y(n1547) );
XOR2X1TS U1788 ( .A(n1434), .B(DP_OP_168J30_122_4811_n2003), .Y(n1553) );
XOR2X1TS U1789 ( .A(n1416), .B(DP_OP_168J30_122_4811_n2003), .Y(n1559) );
AOI21X2TS U1790 ( .A0(n826), .A1(n1585), .B0(n1584), .Y(n1845) );
NAND2X1TS U1791 ( .A(n826), .B(n1857), .Y(n1846) );
NOR2X2TS U1792 ( .A(DP_OP_168J30_122_4811_n2286), .B(
DP_OP_168J30_122_4811_n2278), .Y(n1816) );
NOR2XLTS U1793 ( .A(n1823), .B(n1816), .Y(n1818) );
OAI21XLTS U1794 ( .A0(n2576), .A1(n4495), .B0(n2592), .Y(n2593) );
NAND2X1TS U1795 ( .A(DP_OP_168J30_122_4811_n2260), .B(
DP_OP_168J30_122_4811_n2267), .Y(n1811) );
OAI21X2TS U1796 ( .A0(n1594), .A1(n1830), .B0(n1593), .Y(n1808) );
AOI21X1TS U1797 ( .A0(n1373), .A1(n1592), .B0(n1591), .Y(n1593) );
NOR2X2TS U1798 ( .A(DP_OP_168J30_122_4811_n2259), .B(
DP_OP_168J30_122_4811_n2252), .Y(n1802) );
INVX2TS U1799 ( .A(n1797), .Y(n1833) );
INVX2TS U1800 ( .A(n1808), .Y(n1799) );
NOR2XLTS U1801 ( .A(n1798), .B(n1810), .Y(n1801) );
NAND2X1TS U1802 ( .A(DP_OP_168J30_122_4811_n2259), .B(
DP_OP_168J30_122_4811_n2252), .Y(n1803) );
NOR2X1TS U1803 ( .A(DP_OP_168J30_122_4811_n2244), .B(
DP_OP_168J30_122_4811_n2251), .Y(n1787) );
NAND2X1TS U1804 ( .A(DP_OP_168J30_122_4811_n2244), .B(
DP_OP_168J30_122_4811_n2251), .Y(n1792) );
INVX2TS U1805 ( .A(n1746), .Y(n1795) );
NAND2X1TS U1806 ( .A(n1664), .B(n1663), .Y(n1666) );
INVX2TS U1807 ( .A(n1662), .Y(n1664) );
INVX2TS U1808 ( .A(n1667), .Y(n1669) );
INVX2TS U1809 ( .A(n5180), .Y(n2047) );
INVX2TS U1810 ( .A(n5148), .Y(n2041) );
OAI21X2TS U1811 ( .A0(n5139), .A1(n952), .B0(n5140), .Y(n5149) );
NOR2X1TS U1812 ( .A(n1998), .B(n1997), .Y(n5064) );
INVX2TS U1813 ( .A(n5064), .Y(n5071) );
NAND2X1TS U1814 ( .A(n1998), .B(n1997), .Y(n5070) );
NAND2X1TS U1815 ( .A(n3710), .B(n1930), .Y(n4838) );
OAI21XLTS U1816 ( .A0(n4366), .A1(n3919), .B0(n3832), .Y(n3833) );
AO22XLTS U1817 ( .A0(n2872), .A1(n4081), .B0(n2785), .B1(Op_MY[1]), .Y(n2798) );
OAI21XLTS U1818 ( .A0(n4395), .A1(n2929), .B0(n2924), .Y(n2925) );
OAI21XLTS U1819 ( .A0(n4295), .A1(n2852), .B0(n2867), .Y(n2868) );
OAI21XLTS U1820 ( .A0(n3835), .A1(n3919), .B0(n3834), .Y(n3836) );
OAI21XLTS U1821 ( .A0(n4354), .A1(n2929), .B0(n2926), .Y(n2927) );
OAI21XLTS U1822 ( .A0(n4180), .A1(n2852), .B0(n2869), .Y(n2870) );
CLKAND2X2TS U1823 ( .A(n4639), .B(Op_MY[29]), .Y(n4593) );
CLKAND2X2TS U1824 ( .A(n4639), .B(n4594), .Y(n4583) );
AOI21X1TS U1825 ( .A0(n2277), .A1(n882), .B0(n979), .Y(n2274) );
INVX2TS U1826 ( .A(n2275), .Y(n979) );
OAI21XLTS U1827 ( .A0(n4267), .A1(n3919), .B0(n2637), .Y(n2638) );
OAI21XLTS U1828 ( .A0(n4322), .A1(n2576), .B0(n2569), .Y(n2570) );
OAI21XLTS U1829 ( .A0(n4546), .A1(n4163), .B0(n2493), .Y(n2494) );
OAI21XLTS U1830 ( .A0(n4325), .A1(n3919), .B0(n2639), .Y(n2640) );
OAI21XLTS U1831 ( .A0(n4366), .A1(n2576), .B0(n2571), .Y(n2572) );
OAI21XLTS U1832 ( .A0(n4546), .A1(n4376), .B0(n2496), .Y(n2497) );
OAI21XLTS U1833 ( .A0(n4552), .A1(n3919), .B0(n2641), .Y(n2642) );
OAI21XLTS U1834 ( .A0(n3835), .A1(n2576), .B0(n2575), .Y(n2578) );
AOI222X1TS U1835 ( .A0(n2406), .A1(n4550), .B0(n4606), .B1(n4549), .C0(n2398), .C1(n4548), .Y(n4551) );
AOI222X1TS U1836 ( .A0(n2406), .A1(n4549), .B0(n4606), .B1(n4548), .C0(n2398), .C1(n4361), .Y(n3970) );
AOI222X1TS U1837 ( .A0(n4544), .A1(n2495), .B0(n4614), .B1(n4543), .C0(n2487), .C1(n4550), .Y(n3972) );
AOI222X1TS U1838 ( .A0(n3956), .A1(n4548), .B0(n4606), .B1(n4361), .C0(n2398), .C1(n4656), .Y(n3966) );
AOI222X1TS U1839 ( .A0(n4614), .A1(n2495), .B0(n4550), .B1(n4543), .C0(n2487), .C1(n4549), .Y(n3968) );
OAI21XLTS U1840 ( .A0(n4546), .A1(n3835), .B0(n2488), .Y(n2490) );
AOI222X1TS U1841 ( .A0(n4397), .A1(n4361), .B0(n4543), .B1(n4656), .C0(n3921), .C1(n4655), .Y(n2488) );
OAI21XLTS U1842 ( .A0(n928), .A1(n3919), .B0(n2635), .Y(n2636) );
AOI222X1TS U1843 ( .A0(n4397), .A1(n4363), .B0(n4543), .B1(n4361), .C0(n2487), .C1(n4656), .Y(n2485) );
OAI21XLTS U1844 ( .A0(n2402), .A1(n4376), .B0(n2408), .Y(n2409) );
OAI21XLTS U1845 ( .A0(n840), .A1(n3919), .B0(n2633), .Y(n2634) );
AOI222X1TS U1846 ( .A0(n2495), .A1(n4549), .B0(n4543), .B1(n4363), .C0(n2487), .C1(n4361), .Y(n2483) );
AOI222X1TS U1847 ( .A0(n2495), .A1(n4550), .B0(n4543), .B1(n4549), .C0(n2487), .C1(n4548), .Y(n2481) );
OAI21XLTS U1848 ( .A0(n4610), .A1(n3835), .B0(n2399), .Y(n2401) );
AOI222X1TS U1849 ( .A0(n3956), .A1(n4361), .B0(n4606), .B1(n4656), .C0(n2431), .C1(n2407), .Y(n2399) );
NAND2X1TS U1850 ( .A(Op_MX[39]), .B(Op_MX[12]), .Y(n2528) );
NOR2X2TS U1851 ( .A(Op_MX[39]), .B(Op_MX[12]), .Y(n2529) );
NOR2X1TS U1852 ( .A(n2519), .B(n2523), .Y(n968) );
OAI21X1TS U1853 ( .A0(n2366), .A1(n977), .B0(n976), .Y(n2365) );
NAND2X1TS U1854 ( .A(n915), .B(n913), .Y(n977) );
AOI21X1TS U1855 ( .A0(n2367), .A1(n913), .B0(n975), .Y(n976) );
INVX2TS U1856 ( .A(n2368), .Y(n975) );
OAI21XLTS U1857 ( .A0(n4455), .A1(n3026), .B0(n3025), .Y(n3027) );
NOR2X2TS U1858 ( .A(Op_MX[36]), .B(Op_MX[9]), .Y(n2599) );
NAND2X1TS U1859 ( .A(Op_MX[36]), .B(Op_MX[9]), .Y(n2600) );
OAI21XLTS U1860 ( .A0(n4366), .A1(n4365), .B0(n4364), .Y(n4367) );
OAI21XLTS U1861 ( .A0(n4322), .A1(n4365), .B0(n4321), .Y(n4323) );
OAI21XLTS U1862 ( .A0(n2576), .A1(n4383), .B0(n4382), .Y(n4385) );
ADDHXLTS U1863 ( .A(n3951), .B(n3950), .CO(n3952), .S(
DP_OP_168J30_122_4811_n569) );
OAI21XLTS U1864 ( .A0(n2579), .A1(n4253), .B0(n3946), .Y(n3947) );
XNOR2X1TS U1865 ( .A(n2280), .B(n2279), .Y(n2282) );
XOR2X1TS U1866 ( .A(n2274), .B(n2273), .Y(n2281) );
OAI21XLTS U1867 ( .A0(n2784), .A1(n859), .B0(n2801), .Y(n2802) );
CLKAND2X2TS U1868 ( .A(n4639), .B(Op_MY[37]), .Y(n3181) );
CLKAND2X2TS U1869 ( .A(n4639), .B(Op_MY[36]), .Y(n3735) );
CLKAND2X2TS U1870 ( .A(n4639), .B(Op_MY[34]), .Y(n3733) );
XNOR2X2TS U1871 ( .A(Op_MX[44]), .B(Op_MX[45]), .Y(n1307) );
CLKAND2X2TS U1872 ( .A(n4639), .B(Op_MY[32]), .Y(n4640) );
CLKAND2X2TS U1873 ( .A(n4639), .B(Op_MY[30]), .Y(n4622) );
CLKAND2X2TS U1874 ( .A(n4639), .B(Op_MY[31]), .Y(n4631) );
OAI21XLTS U1875 ( .A0(n3579), .A1(n3339), .B0(n3349), .Y(n3350) );
OAI21XLTS U1876 ( .A0(n3243), .A1(n4587), .B0(n3890), .Y(n3891) );
OAI21XLTS U1877 ( .A0(n4626), .A1(n3339), .B0(n3357), .Y(n3358) );
OAI21XLTS U1878 ( .A0(n3245), .A1(n748), .B0(n3883), .Y(n3884) );
OAI21XLTS U1879 ( .A0(n3286), .A1(n748), .B0(n3852), .Y(n3853) );
OAI21XLTS U1880 ( .A0(n4611), .A1(n4365), .B0(n2675), .Y(n2676) );
OAI21XLTS U1881 ( .A0(n839), .A1(n4365), .B0(n2677), .Y(n2678) );
OAI21XLTS U1882 ( .A0(n840), .A1(n4365), .B0(n2679), .Y(n2680) );
OAI21XLTS U1883 ( .A0(n928), .A1(n4365), .B0(n2681), .Y(n2682) );
OAI21XLTS U1884 ( .A0(n4325), .A1(n4365), .B0(n2685), .Y(n2686) );
OAI21XLTS U1885 ( .A0(n2491), .A1(n4383), .B0(n3839), .Y(n3840) );
OAI21XLTS U1886 ( .A0(n4267), .A1(n4365), .B0(n2683), .Y(n2684) );
OAI21XLTS U1887 ( .A0(n2491), .A1(n4253), .B0(n3923), .Y(n3924) );
OAI21X1TS U1888 ( .A0(n2162), .A1(n2158), .B0(n2159), .Y(n2157) );
AOI222X1TS U1889 ( .A0(n4605), .A1(n2406), .B0(n4658), .B1(n4606), .C0(n2398), .C1(n4615), .Y(n3993) );
AOI222X1TS U1890 ( .A0(n2317), .A1(n4550), .B0(n4659), .B1(n4549), .C0(n2309), .C1(n4363), .Y(n2303) );
AOI222X1TS U1891 ( .A0(n4608), .A1(n2495), .B0(n4607), .B1(n4543), .C0(n4327), .C1(n2487), .Y(n2475) );
OAI21XLTS U1892 ( .A0(n2313), .A1(n4322), .B0(n2305), .Y(n2306) );
AOI222X1TS U1893 ( .A0(n2317), .A1(n4549), .B0(n4659), .B1(n4363), .C0(n2309), .C1(n4361), .Y(n2305) );
AOI222X1TS U1894 ( .A0(n4607), .A1(n2495), .B0(n4327), .B1(n4543), .C0(n4658), .C1(n2487), .Y(n2477) );
AOI222X1TS U1895 ( .A0(n4327), .A1(n2495), .B0(n4658), .B1(n4543), .C0(n4544), .C1(n2487), .Y(n2479) );
AOI222X1TS U1896 ( .A0(n2358), .A1(n4548), .B0(n4659), .B1(n4361), .C0(n2309), .C1(n4656), .Y(n2307) );
AOI222X1TS U1897 ( .A0(n2358), .A1(n4361), .B0(n4659), .B1(n4656), .C0(n2353), .C1(n4655), .Y(n2310) );
XOR2X1TS U1898 ( .A(n4553), .B(DP_OP_168J30_122_4811_n66), .Y(n4554) );
OAI21XLTS U1899 ( .A0(n4141), .A1(n2929), .B0(n2928), .Y(n2931) );
OAI21XLTS U1900 ( .A0(n4133), .A1(n2852), .B0(n2873), .Y(n2875) );
OAI21XLTS U1901 ( .A0(n4079), .A1(n2852), .B0(n2796), .Y(n2797) );
OAI21XLTS U1902 ( .A0(n4141), .A1(n2852), .B0(n2865), .Y(n2866) );
OAI21XLTS U1903 ( .A0(n4354), .A1(n2852), .B0(n2863), .Y(n2864) );
OAI21XLTS U1904 ( .A0(n4395), .A1(n2852), .B0(n2861), .Y(n2862) );
OAI21X2TS U1905 ( .A0(n2599), .A1(n2597), .B0(n2600), .Y(n2605) );
NOR2X2TS U1906 ( .A(n2599), .B(n2598), .Y(n2604) );
OAI21XLTS U1907 ( .A0(n3798), .A1(n2929), .B0(n2908), .Y(n2909) );
OAI21XLTS U1908 ( .A0(n4441), .A1(n2784), .B0(n2857), .Y(n2858) );
OAI21XLTS U1909 ( .A0(n4418), .A1(n2852), .B0(n2788), .Y(n2789) );
OAI21XLTS U1910 ( .A0(n4455), .A1(n2929), .B0(n2911), .Y(n2912) );
NOR2X1TS U1911 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n2445) );
XOR2X1TS U1912 ( .A(n2530), .B(n2518), .Y(n2536) );
NAND2X1TS U1913 ( .A(n2517), .B(n2528), .Y(n2518) );
INVX2TS U1914 ( .A(n2529), .Y(n2517) );
XNOR2X1TS U1915 ( .A(n2535), .B(n2534), .Y(n2537) );
NAND2X1TS U1916 ( .A(n2533), .B(n2532), .Y(n2534) );
AOI222X1TS U1917 ( .A0(n2644), .A1(n4572), .B0(n3917), .B1(n4406), .C0(n2646), .C1(n4404), .Y(n3615) );
AOI222X1TS U1918 ( .A0(n2644), .A1(n4231), .B0(n4373), .B1(n4572), .C0(n4372), .C1(n4406), .Y(n4211) );
OAI21XLTS U1919 ( .A0(n4253), .A1(n4365), .B0(n4209), .Y(n4210) );
AOI222X1TS U1920 ( .A0(n2728), .A1(n4262), .B0(n4603), .B1(n4261), .C0(n4260), .C1(n4380), .Y(n4209) );
NOR2X1TS U1921 ( .A(n2447), .B(n2445), .Y(n970) );
NOR2X1TS U1922 ( .A(n2529), .B(n2531), .Y(n2441) );
AOI21X1TS U1923 ( .A0(n970), .A1(n2442), .B0(n969), .Y(n971) );
NAND2X1TS U1924 ( .A(n2604), .B(n968), .Y(n2436) );
OAI21XLTS U1925 ( .A0(n4163), .A1(n4365), .B0(n4162), .Y(n4164) );
AOI21X1TS U1926 ( .A0(n2365), .A1(n852), .B0(n978), .Y(n2375) );
INVX2TS U1927 ( .A(n2363), .Y(n978) );
XNOR2X1TS U1928 ( .A(n2365), .B(n2364), .Y(n2376) );
NAND2X1TS U1929 ( .A(n852), .B(n2363), .Y(n2364) );
XOR2X1TS U1930 ( .A(n2375), .B(n2374), .Y(n2377) );
NOR2BX1TS U1931 ( .AN(n2765), .B(n1605), .Y(n2786) );
AOI222X1TS U1932 ( .A0(n2317), .A1(n4615), .B0(n4659), .B1(n3995), .C0(n2309), .C1(n4550), .Y(n3996) );
AOI222X1TS U1933 ( .A0(n4607), .A1(n2406), .B0(n4605), .B1(n4606), .C0(n2398), .C1(n4658), .Y(n3998) );
AOI222X1TS U1934 ( .A0(n4608), .A1(n2406), .B0(n4607), .B1(n4606), .C0(n4605), .C1(n2398), .Y(n4609) );
AOI222X1TS U1935 ( .A0(n2317), .A1(n4616), .B0(n4659), .B1(n4615), .C0(n2309), .C1(n4614), .Y(n4617) );
OAI21XLTS U1936 ( .A0(n2929), .A1(n859), .B0(n2819), .Y(n2820) );
OAI21XLTS U1937 ( .A0(n4449), .A1(n3118), .B0(n3102), .Y(n3103) );
OAI21X2TS U1938 ( .A0(n1242), .A1(n966), .B0(n965), .Y(n2440) );
NAND2X1TS U1939 ( .A(n964), .B(n1259), .Y(n966) );
AOI21X1TS U1940 ( .A0(n964), .A1(n1261), .B0(n963), .Y(n965) );
NOR2X1TS U1941 ( .A(n1263), .B(n1268), .Y(n964) );
OAI21XLTS U1942 ( .A0(n4295), .A1(n2929), .B0(n2806), .Y(n2807) );
XNOR2X1TS U1943 ( .A(n2603), .B(n2602), .Y(n2613) );
NAND2X1TS U1944 ( .A(n2601), .B(n2600), .Y(n2602) );
INVX2TS U1945 ( .A(n2599), .Y(n2601) );
XNOR2X1TS U1946 ( .A(n2612), .B(n2611), .Y(n2614) );
OAI21XLTS U1947 ( .A0(n4552), .A1(n4365), .B0(n2687), .Y(n2688) );
OAI21XLTS U1948 ( .A0(n4267), .A1(n2695), .B0(n4266), .Y(n4268) );
NAND2X1TS U1949 ( .A(n4008), .B(n4605), .Y(n2296) );
OAI21XLTS U1950 ( .A0(n4475), .A1(n3118), .B0(n3104), .Y(n3105) );
NOR2BX1TS U1951 ( .AN(n1334), .B(n1332), .Y(n3246) );
CLKAND2X2TS U1952 ( .A(n3762), .B(n3749), .Y(n3750) );
NOR2BX1TS U1953 ( .AN(n1307), .B(n1305), .Y(n3287) );
CLKAND2X2TS U1954 ( .A(n3762), .B(Op_MY[40]), .Y(n3738) );
CLKAND2X2TS U1955 ( .A(n4639), .B(Op_MY[38]), .Y(n3175) );
NOR2X1TS U1956 ( .A(n1301), .B(n1300), .Y(n3346) );
NOR2BX1TS U1957 ( .AN(n1295), .B(n1293), .Y(n3191) );
CLKAND2X2TS U1958 ( .A(n4639), .B(Op_MY[35]), .Y(n3606) );
BUFX4TS U1959 ( .A(n3170), .Y(n4643) );
AOI222X1TS U1960 ( .A0(n4646), .A1(Op_MY[38]), .B0(n4645), .B1(Op_MY[37]),
.C0(n3183), .C1(Op_MY[36]), .Y(n3252) );
AOI222X1TS U1961 ( .A0(n4646), .A1(Op_MY[37]), .B0(n4645), .B1(Op_MY[36]),
.C0(n3183), .C1(Op_MY[35]), .Y(n3254) );
CLKAND2X2TS U1962 ( .A(n4639), .B(Op_MY[33]), .Y(n3845) );
OAI21XLTS U1963 ( .A0(n3752), .A1(n3446), .B0(n3439), .Y(n3440) );
OAI21XLTS U1964 ( .A0(n4626), .A1(n3284), .B0(n3301), .Y(n3302) );
OAI21XLTS U1965 ( .A0(n3743), .A1(n3446), .B0(n3442), .Y(n3443) );
OAI21XLTS U1966 ( .A0(n3740), .A1(n3446), .B0(n3445), .Y(n3447) );
OAI21XLTS U1967 ( .A0(n4633), .A1(n3284), .B0(n3305), .Y(n3306) );
INVX2TS U1968 ( .A(n2278), .Y(n980) );
NOR2X1TS U1969 ( .A(Op_MX[23]), .B(Op_MX[50]), .Y(n2158) );
NAND2X1TS U1970 ( .A(Op_MX[23]), .B(Op_MX[50]), .Y(n2159) );
OAI21XLTS U1971 ( .A0(n3571), .A1(n3198), .B0(n3449), .Y(n3450) );
NAND2X1TS U1972 ( .A(n3728), .B(n4008), .Y(n2189) );
OAI21X1TS U1973 ( .A0(n2295), .A1(n930), .B0(n2296), .Y(n2190) );
AOI222X1TS U1974 ( .A0(n4661), .A1(n2317), .B0(n4660), .B1(n4659), .C0(n2550), .C1(n2309), .Y(n4662) );
OAI21XLTS U1975 ( .A0(n3575), .A1(n3198), .B0(n3451), .Y(n3452) );
OAI21XLTS U1976 ( .A0(n4596), .A1(n3284), .B0(n3309), .Y(n3310) );
OAI21XLTS U1977 ( .A0(n3579), .A1(n3446), .B0(n3453), .Y(n3454) );
AOI222X1TS U1978 ( .A0(n2550), .A1(n2317), .B0(n3728), .B1(n4659), .C0(n2309), .C1(n4008), .Y(n3729) );
OAI21XLTS U1979 ( .A0(n3737), .A1(n3446), .B0(n3455), .Y(n3456) );
AOI222X1TS U1980 ( .A0(n2317), .A1(n3728), .B0(n4659), .B1(n4008), .C0(n2309), .C1(n4327), .Y(n2293) );
OAI21XLTS U1981 ( .A0(n4648), .A1(n3446), .B0(n3457), .Y(n3458) );
OAI21XLTS U1982 ( .A0(n4596), .A1(n3339), .B0(n3850), .Y(n3851) );
AOI222X1TS U1983 ( .A0(n2317), .A1(n4607), .B0(n4659), .B1(n4605), .C0(n2309), .C1(n4616), .Y(n2299) );
AOI222X1TS U1984 ( .A0(n4660), .A1(n2406), .B0(n4313), .B1(n4606), .C0(n3728), .C1(n2398), .Y(n2388) );
OAI21XLTS U1985 ( .A0(n4611), .A1(n2695), .B0(n2711), .Y(n2712) );
OAI21XLTS U1986 ( .A0(n2360), .A1(n4488), .B0(n2334), .Y(n2335) );
NAND2X1TS U1987 ( .A(n4313), .B(n3728), .Y(n2183) );
NOR2X1TS U1988 ( .A(n2170), .B(n2172), .Y(n2243) );
OAI21XLTS U1989 ( .A0(n839), .A1(n2695), .B0(n2713), .Y(n2714) );
INVX2TS U1990 ( .A(n2167), .Y(n2179) );
XNOR2X1TS U1991 ( .A(n2157), .B(n2156), .Y(n2163) );
OAI21XLTS U1992 ( .A0(n4644), .A1(n3446), .B0(n3464), .Y(n3466) );
AOI222X1TS U1993 ( .A0(n4313), .A1(n2495), .B0(n4608), .B1(n4543), .C0(n4607), .C1(n2487), .Y(n2473) );
OAI21XLTS U1994 ( .A0(n3416), .A1(n748), .B0(n744), .Y(n3197) );
AOI222X1TS U1995 ( .A0(n4315), .A1(n3911), .B0(n4313), .B1(n4381), .C0(n4608), .C1(n4379), .Y(n2551) );
CLKAND2X2TS U1996 ( .A(n4604), .B(n4654), .Y(DP_OP_168J30_122_4811_n839) );
OAI21XLTS U1997 ( .A0(n2235), .A1(n4221), .B0(n2248), .Y(n2249) );
AOI222X1TS U1998 ( .A0(n4313), .A1(n3943), .B0(n4608), .B1(n4373), .C0(n4607), .C1(n4372), .Y(n2627) );
OAI21XLTS U1999 ( .A0(n4011), .A1(n4383), .B0(n2256), .Y(n2257) );
OAI21XLTS U2000 ( .A0(n4011), .A1(n4409), .B0(n2268), .Y(n2269) );
OAI21XLTS U2001 ( .A0(n4011), .A1(n4233), .B0(n2260), .Y(n2261) );
ADDHXLTS U2002 ( .A(n4087), .B(n4086), .CO(n4093), .S(n4099) );
OAI21XLTS U2003 ( .A0(n4079), .A1(n2929), .B0(n2815), .Y(n2816) );
OAI21XLTS U2004 ( .A0(n4467), .A1(n3078), .B0(n3069), .Y(n3070) );
OAI21XLTS U2005 ( .A0(n4475), .A1(n3078), .B0(n3067), .Y(n3068) );
XOR2X1TS U2006 ( .A(n1256), .B(n1255), .Y(n2657) );
INVX2TS U2007 ( .A(n1263), .Y(n1254) );
XOR2X1TS U2008 ( .A(n1272), .B(n1271), .Y(n2658) );
INVX2TS U2009 ( .A(n1268), .Y(n1270) );
OAI21XLTS U2010 ( .A0(n4461), .A1(n3078), .B0(n3062), .Y(n3063) );
OAI21XLTS U2011 ( .A0(n4441), .A1(n2929), .B0(n2916), .Y(n2917) );
AOI21X1TS U2012 ( .A0(n2605), .A1(n2610), .B0(n2520), .Y(n2521) );
NAND2X1TS U2013 ( .A(n2604), .B(n2610), .Y(n2522) );
NAND2X1TS U2014 ( .A(Op_MX[11]), .B(Op_MX[38]), .Y(n2524) );
NOR2X2TS U2015 ( .A(Op_MX[11]), .B(Op_MX[38]), .Y(n2523) );
OAI21X1TS U2016 ( .A0(n2150), .A1(n2348), .B0(n2149), .Y(n2336) );
NAND2X1TS U2017 ( .A(n927), .B(n2347), .Y(n2150) );
NOR2XLTS U2018 ( .A(n2148), .B(n2147), .Y(n2149) );
OAI21XLTS U2019 ( .A0(n4461), .A1(n3026), .B0(n3008), .Y(n3009) );
OAI21XLTS U2020 ( .A0(n4475), .A1(n3026), .B0(n3012), .Y(n3013) );
OAI21XLTS U2021 ( .A0(n4446), .A1(n2929), .B0(n2914), .Y(n2915) );
OAI21XLTS U2022 ( .A0(n4455), .A1(n2852), .B0(n2851), .Y(n2853) );
NAND2X1TS U2023 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n2452) );
ADDHXLTS U2024 ( .A(n4240), .B(n4239), .CO(n4250), .S(n4247) );
OAI21XLTS U2025 ( .A0(n4383), .A1(n4408), .B0(n4205), .Y(n4206) );
OR2X1TS U2026 ( .A(DP_OP_168J30_122_4811_n1864), .B(
DP_OP_168J30_122_4811_n1865), .Y(n927) );
AOI222X1TS U2027 ( .A0(n2580), .A1(n4510), .B0(n4381), .B1(n4401), .C0(n2573), .C1(n4508), .Y(n2586) );
ADDHXLTS U2028 ( .A(n4217), .B(n4216), .CO(n4218), .S(
DP_OP_168J30_122_4811_n647) );
OAI21XLTS U2029 ( .A0(n2643), .A1(n4212), .B0(n4211), .Y(n4213) );
NOR2X1TS U2030 ( .A(n972), .B(n2436), .Y(n974) );
OAI21X1TS U2031 ( .A0(n2437), .A1(n972), .B0(n971), .Y(n973) );
NAND2X1TS U2032 ( .A(n2441), .B(n970), .Y(n972) );
XNOR2X1TS U2033 ( .A(n2458), .B(n2457), .Y(n2460) );
NAND2X1TS U2034 ( .A(n915), .B(n2456), .Y(n2457) );
XOR2X1TS U2035 ( .A(n2451), .B(n2450), .Y(n2459) );
NAND2X1TS U2036 ( .A(n2449), .B(n2448), .Y(n2450) );
AOI21X1TS U2037 ( .A0(n2455), .A1(n2453), .B0(n2446), .Y(n2451) );
OAI21XLTS U2038 ( .A0(n4322), .A1(n4408), .B0(n2719), .Y(n2720) );
OAI21XLTS U2039 ( .A0(n2579), .A1(n4409), .B0(n3938), .Y(n3939) );
AOI222X1TS U2040 ( .A0(n2580), .A1(n4572), .B0(n2574), .B1(n4406), .C0(n2573), .C1(n4510), .Y(n3938) );
NAND2X1TS U2041 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n2275) );
AOI222X1TS U2042 ( .A0(n4661), .A1(n2495), .B0(n4660), .B1(n4543), .C0(n4313), .C1(n2487), .Y(n2469) );
XOR2X1TS U2043 ( .A(n3997), .B(n2361), .Y(n4004) );
XOR2X1TS U2044 ( .A(n3999), .B(DP_OP_168J30_122_4811_n66), .Y(n4003) );
AOI222X1TS U2045 ( .A0(n2317), .A1(n4605), .B0(n4659), .B1(n4616), .C0(n2309), .C1(n4544), .Y(n2301) );
XOR2X1TS U2046 ( .A(n4618), .B(n2361), .Y(n4619) );
XOR2X1TS U2047 ( .A(n4612), .B(DP_OP_168J30_122_4811_n66), .Y(n4621) );
INVX2TS U2048 ( .A(n2540), .Y(n2285) );
OAI21XLTS U2049 ( .A0(n3339), .A1(n3893), .B0(n3856), .Y(n3857) );
NOR2X2TS U2050 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n2598) );
OAI21XLTS U2051 ( .A0(n4446), .A1(n3120), .B0(n3122), .Y(n3123) );
OAI21XLTS U2052 ( .A0(n4519), .A1(n3118), .B0(n3108), .Y(n3109) );
XNOR2X1TS U2053 ( .A(n1267), .B(n1252), .Y(n2697) );
XNOR2X1TS U2054 ( .A(n1241), .B(n1240), .Y(n2696) );
OAI21XLTS U2055 ( .A0(n1236), .A1(n1235), .B0(n1234), .Y(n1241) );
NAND2X1TS U2056 ( .A(Op_MX[5]), .B(Op_MX[32]), .Y(n1246) );
NOR2X2TS U2057 ( .A(Op_MX[5]), .B(Op_MX[32]), .Y(n1245) );
OAI21XLTS U2058 ( .A0(n2656), .A1(n926), .B0(n2691), .Y(n2692) );
AOI222X1TS U2059 ( .A0(n4262), .A1(n4401), .B0(n4360), .B1(n4283), .C0(n2690), .C1(n4279), .Y(n2691) );
INVX2TS U2060 ( .A(n2255), .Y(n4383) );
OAI21XLTS U2061 ( .A0(n3795), .A1(n4474), .B0(n3138), .Y(n3139) );
OAI21XLTS U2062 ( .A0(n3798), .A1(n3118), .B0(n3114), .Y(n3115) );
OAI21XLTS U2063 ( .A0(n4422), .A1(n859), .B0(n4026), .Y(n4027) );
OAI21XLTS U2064 ( .A0(n4552), .A1(n2695), .B0(n2717), .Y(n2718) );
OAI21XLTS U2065 ( .A0(n2579), .A1(n4233), .B0(n2582), .Y(n2583) );
INVX2TS U2066 ( .A(n2247), .Y(n4221) );
BUFX6TS U2067 ( .A(n2410), .Y(n4603) );
OAI21XLTS U2068 ( .A0(n4233), .A1(n4408), .B0(n4232), .Y(n4234) );
INVX2TS U2069 ( .A(n3662), .Y(n1320) );
NAND2X1TS U2070 ( .A(n940), .B(n939), .Y(n1322) );
NOR2X1TS U2071 ( .A(n1322), .B(n2091), .Y(n1324) );
CLKAND2X2TS U2072 ( .A(n4639), .B(Op_MY[39]), .Y(n3172) );
OAI21XLTS U2073 ( .A0(n982), .A1(n3604), .B0(n3603), .Y(n3605) );
OAI21XLTS U2074 ( .A0(n3740), .A1(n3416), .B0(n3390), .Y(n3391) );
OAI21XLTS U2075 ( .A0(n3535), .A1(n1174), .B0(n3534), .Y(n3536) );
OAI21XLTS U2076 ( .A0(n3552), .A1(n1275), .B0(n3483), .Y(n3484) );
OAI21XLTS U2077 ( .A0(n3548), .A1(n1174), .B0(n3547), .Y(n3549) );
CLKAND2X2TS U2078 ( .A(n4658), .B(n916), .Y(n4666) );
XOR2X1TS U2079 ( .A(n4663), .B(n2311), .Y(n4664) );
CLKAND2X2TS U2080 ( .A(n4544), .B(n916), .Y(n4014) );
XOR2X1TS U2081 ( .A(n4006), .B(n2311), .Y(n4015) );
OAI21XLTS U2082 ( .A0(n3557), .A1(n3600), .B0(n3556), .Y(n3558) );
CLKAND2X2TS U2083 ( .A(n4661), .B(n4606), .Y(n2381) );
CLKAND2X2TS U2084 ( .A(n4614), .B(n916), .Y(n3732) );
OAI21XLTS U2085 ( .A0(n3752), .A1(n3600), .B0(n3560), .Y(n3561) );
CLKAND2X2TS U2086 ( .A(n4667), .B(n916), .Y(DP_OP_168J30_122_4811_n832) );
CLKAND2X2TS U2087 ( .A(n2222), .B(n916), .Y(DP_OP_168J30_122_4811_n833) );
OAI21XLTS U2088 ( .A0(n3740), .A1(n3600), .B0(n3566), .Y(n3567) );
CLKAND2X2TS U2089 ( .A(n4227), .B(n4331), .Y(n4228) );
OAI21XLTS U2090 ( .A0(n933), .A1(n4317), .B0(n2735), .Y(n2736) );
OAI21XLTS U2091 ( .A0(n932), .A1(n4317), .B0(n2739), .Y(n2740) );
CLKAND2X2TS U2092 ( .A(n4493), .B(n4654), .Y(DP_OP_168J30_122_4811_n849) );
XNOR2X2TS U2093 ( .A(n2163), .B(n2311), .Y(n2172) );
OAI21XLTS U2094 ( .A0(n3575), .A1(n3600), .B0(n3574), .Y(n3576) );
INVX2TS U2095 ( .A(n1034), .Y(n3740) );
CLKAND2X2TS U2096 ( .A(n4227), .B(n4381), .Y(n2542) );
CLKAND2X2TS U2097 ( .A(n4655), .B(n4654), .Y(DP_OP_168J30_122_4811_n837) );
BUFX4TS U2098 ( .A(n2577), .Y(n4613) );
INVX2TS U2099 ( .A(n1039), .Y(n3571) );
OAI21XLTS U2100 ( .A0(n3737), .A1(n3600), .B0(n3582), .Y(n3583) );
CLKAND2X2TS U2101 ( .A(n4630), .B(n4654), .Y(DP_OP_168J30_122_4811_n838) );
OAI21XLTS U2102 ( .A0(n4648), .A1(n3600), .B0(n3585), .Y(n3586) );
OAI21XLTS U2103 ( .A0(n3446), .A1(n4587), .B0(n3211), .Y(n3212) );
CLKAND2X2TS U2104 ( .A(n4227), .B(n4373), .Y(n2618) );
CLKAND2X2TS U2105 ( .A(n4603), .B(n4654), .Y(DP_OP_168J30_122_4811_n840) );
CLKAND2X2TS U2106 ( .A(n4578), .B(n4654), .Y(DP_OP_168J30_122_4811_n841) );
OAI21XLTS U2107 ( .A0(n4596), .A1(n3521), .B0(n3520), .Y(n3523) );
OAI21XLTS U2108 ( .A0(n2235), .A1(n4253), .B0(n2252), .Y(n2253) );
CLKAND2X2TS U2109 ( .A(n4227), .B(n4261), .Y(n2665) );
NAND2X1TS U2110 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1208) );
OAI21XLTS U2111 ( .A0(n3776), .A1(n4474), .B0(n3142), .Y(n3143) );
OAI21XLTS U2112 ( .A0(n3154), .A1(n1574), .B0(n3153), .Y(n3155) );
OAI21XLTS U2113 ( .A0(n3773), .A1(n3118), .B0(n3098), .Y(n3099) );
OAI21XLTS U2114 ( .A0(n4409), .A1(n4317), .B0(n4152), .Y(n4153) );
OAI21XLTS U2115 ( .A0(n3136), .A1(n4474), .B0(n3135), .Y(n3137) );
OAI21XLTS U2116 ( .A0(n4519), .A1(n3026), .B0(n3016), .Y(n3017) );
OAI21XLTS U2117 ( .A0(n3154), .A1(n4474), .B0(n3131), .Y(n3132) );
OAI21XLTS U2118 ( .A0(n3786), .A1(n3118), .B0(n3092), .Y(n3093) );
OAI21XLTS U2119 ( .A0(n3773), .A1(n3078), .B0(n3059), .Y(n3060) );
XNOR2X2TS U2120 ( .A(n2527), .B(n2526), .Y(n2648) );
OAI21X1TS U2121 ( .A0(n2608), .A1(n2522), .B0(n2521), .Y(n2527) );
BUFX4TS U2122 ( .A(n2648), .Y(n4669) );
OAI21XLTS U2123 ( .A0(n3136), .A1(n3118), .B0(n3086), .Y(n3087) );
OAI21XLTS U2124 ( .A0(n3795), .A1(n3118), .B0(n3090), .Y(n3091) );
OAI21XLTS U2125 ( .A0(n4519), .A1(n2968), .B0(n2958), .Y(n2959) );
ADDHXLTS U2126 ( .A(n4238), .B(n4237), .CO(n4243), .S(
DP_OP_168J30_122_4811_n707) );
OAI21XLTS U2127 ( .A0(n4212), .A1(n4408), .B0(n4174), .Y(n4175) );
INVX2TS U2128 ( .A(n2251), .Y(n4253) );
OAI21XLTS U2129 ( .A0(n3136), .A1(n3078), .B0(n3046), .Y(n3047) );
OAI21XLTS U2130 ( .A0(n4467), .A1(n2876), .B0(n2901), .Y(n2902) );
OAI21XLTS U2131 ( .A0(n3154), .A1(n3118), .B0(n3082), .Y(n3083) );
OAI21XLTS U2132 ( .A0(n3773), .A1(n3026), .B0(n3006), .Y(n3007) );
OAI21XLTS U2133 ( .A0(n3801), .A1(n2876), .B0(n2905), .Y(n2906) );
AOI222X1TS U2134 ( .A0(n2644), .A1(n4401), .B0(n4373), .B1(n4283), .C0(n2646), .C1(n4279), .Y(n2650) );
OAI21XLTS U2135 ( .A0(n4376), .A1(n2733), .B0(n2754), .Y(n2755) );
OAI21XLTS U2136 ( .A0(n3154), .A1(n3078), .B0(n3042), .Y(n3043) );
AOI222X1TS U2137 ( .A0(n2644), .A1(n4406), .B0(n4373), .B1(n4510), .C0(n4372), .C1(n4401), .Y(n2647) );
ADDHXLTS U2138 ( .A(n4208), .B(n4207), .CO(DP_OP_168J30_122_4811_n668), .S(
DP_OP_168J30_122_4811_n669) );
OAI21XLTS U2139 ( .A0(n4233), .A1(n4365), .B0(n4199), .Y(n4200) );
AOI222X1TS U2140 ( .A0(n4262), .A1(n4380), .B0(n4261), .B1(n4231), .C0(n4260), .C1(n4572), .Y(n4199) );
BUFX6TS U2141 ( .A(n2407), .Y(n4655) );
AOI21X1TS U2142 ( .A0(n824), .A1(n1837), .B0(n1586), .Y(n1587) );
AOI222X1TS U2143 ( .A0(n3910), .A1(n4271), .B0(n4655), .B1(n4270), .C0(n2725), .C1(n4269), .Y(n2752) );
OAI21XLTS U2144 ( .A0(n2643), .A1(n4498), .B0(n4255), .Y(n4256) );
AOI222X1TS U2145 ( .A0(n2580), .A1(n4401), .B0(n4381), .B1(n4283), .C0(n4379), .C1(n4509), .Y(n2588) );
OAI21XLTS U2146 ( .A0(n4366), .A1(n4317), .B0(n4307), .Y(n4308) );
AOI222X1TS U2147 ( .A0(n4363), .A1(n4314), .B0(n4361), .B1(n4312), .C0(n4656), .C1(n4269), .Y(n4307) );
OAI21XLTS U2148 ( .A0(n3154), .A1(n3026), .B0(n2990), .Y(n2991) );
AOI222X1TS U2149 ( .A0(n2580), .A1(n4406), .B0(n4381), .B1(n4510), .C0(n4379), .C1(n4511), .Y(n2584) );
BUFX4TS U2150 ( .A(n2400), .Y(DP_OP_168J30_122_4811_n66) );
OAI21XLTS U2151 ( .A0(n2576), .A1(n4498), .B0(n2586), .Y(n2587) );
NAND2X1TS U2152 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n2368) );
INVX2TS U2153 ( .A(n2456), .Y(n2367) );
INVX2TS U2154 ( .A(n2366), .Y(n2458) );
NAND2X1TS U2155 ( .A(DP_OP_168J30_122_4811_n1865), .B(
DP_OP_168J30_122_4811_n1866), .Y(n2346) );
OAI21XLTS U2156 ( .A0(n4325), .A1(n4317), .B0(n3906), .Y(n3907) );
INVX2TS U2157 ( .A(n2209), .Y(n4267) );
CLKAND2X2TS U2158 ( .A(n4656), .B(n4654), .Y(DP_OP_168J30_122_4811_n836) );
CLKAND2X2TS U2159 ( .A(n4661), .B(n4543), .Y(n2464) );
CLKAND2X2TS U2160 ( .A(n4361), .B(n4654), .Y(DP_OP_168J30_122_4811_n835) );
CLKAND2X2TS U2161 ( .A(n4363), .B(n4654), .Y(DP_OP_168J30_122_4811_n834) );
OAI21XLTS U2162 ( .A0(n4624), .A1(n3416), .B0(n3411), .Y(n3412) );
CMPR42X1TS U2163 ( .A(DP_OP_168J30_122_4811_n2871), .B(
DP_OP_168J30_122_4811_n2493), .C(DP_OP_168J30_122_4811_n2499), .D(
DP_OP_168J30_122_4811_n2898), .ICI(DP_OP_168J30_122_4811_n2500), .S(
DP_OP_168J30_122_4811_n2490), .ICO(DP_OP_168J30_122_4811_n2488), .CO(
DP_OP_168J30_122_4811_n2489) );
OAI21XLTS U2164 ( .A0(n4446), .A1(n4422), .B0(n3080), .Y(n3081) );
OAI21XLTS U2165 ( .A0(n3773), .A1(n1574), .B0(n3772), .Y(n3774) );
OAI21XLTS U2166 ( .A0(n3780), .A1(n4474), .B0(n3144), .Y(n3145) );
INVX2TS U2167 ( .A(n1402), .Y(n3773) );
OAI21XLTS U2168 ( .A0(n4475), .A1(n1574), .B0(n3812), .Y(n3813) );
OAI21XLTS U2169 ( .A0(n3780), .A1(n1574), .B0(n3779), .Y(n3781) );
OAI21XLTS U2170 ( .A0(n2643), .A1(n1226), .B0(n3822), .Y(n3823) );
OAI21XLTS U2171 ( .A0(n4610), .A1(n4488), .B0(n2423), .Y(n2424) );
OAI21XLTS U2172 ( .A0(n4611), .A1(n4317), .B0(n3908), .Y(n3909) );
AOI222X1TS U2173 ( .A0(n4608), .A1(n4314), .B0(n4607), .B1(n4312), .C0(n4327), .C1(n2734), .Y(n3908) );
AOI222X1TS U2174 ( .A0(n2358), .A1(n4509), .B0(n2356), .B1(n4493), .C0(n2353), .C1(n4477), .Y(n2354) );
NAND2X1TS U2175 ( .A(DP_OP_168J30_122_4811_n1867), .B(n4512), .Y(n1225) );
OAI21XLTS U2176 ( .A0(n4461), .A1(n1574), .B0(n3782), .Y(n3783) );
OAI21XLTS U2177 ( .A0(n4519), .A1(n1574), .B0(n3807), .Y(n3808) );
INVX2TS U2178 ( .A(n1427), .Y(n3801) );
OAI21XLTS U2179 ( .A0(n4011), .A1(n1230), .B0(n4478), .Y(n4479) );
OAI21XLTS U2180 ( .A0(n2360), .A1(n1230), .B0(n2359), .Y(n2362) );
OAI21XLTS U2181 ( .A0(n928), .A1(n4317), .B0(n4290), .Y(n4291) );
AOI222X1TS U2182 ( .A0(n4658), .A1(n4314), .B0(n4544), .B1(n4312), .C0(n4614), .C1(n2734), .Y(n4290) );
NOR2X1TS U2183 ( .A(n1764), .B(n1765), .Y(n1755) );
NAND2X1TS U2184 ( .A(n2088), .B(n1324), .Y(n1326) );
OAI21X1TS U2185 ( .A0(n2100), .A1(n1326), .B0(n1325), .Y(n2074) );
AOI21X1TS U2186 ( .A0(n2087), .A1(n1324), .B0(n1323), .Y(n1325) );
AOI21X1TS U2187 ( .A0(n3652), .A1(n939), .B0(n1320), .Y(n1321) );
INVX2TS U2188 ( .A(n2084), .Y(n3652) );
NAND2X1TS U2189 ( .A(n3648), .B(n940), .Y(n3655) );
INVX2TS U2190 ( .A(n2088), .Y(n3649) );
INVX2TS U2191 ( .A(n2087), .Y(n3656) );
NOR2X2TS U2192 ( .A(DP_OP_168J30_122_4811_n3911), .B(n1319), .Y(n2091) );
NAND2X1TS U2193 ( .A(n2097), .B(n941), .Y(n1318) );
OAI21X2TS U2194 ( .A0(n1318), .A1(n3640), .B0(n1317), .Y(n2087) );
AOI21X1TS U2195 ( .A0(n1316), .A1(n941), .B0(n1315), .Y(n1317) );
INVX2TS U2196 ( .A(n3645), .Y(n1315) );
INVX2TS U2197 ( .A(n3638), .Y(n1316) );
CMPR42X1TS U2198 ( .A(DP_OP_168J30_122_4811_n4413), .B(
DP_OP_168J30_122_4811_n3942), .C(DP_OP_168J30_122_4811_n3947), .D(
DP_OP_168J30_122_4811_n4439), .ICI(DP_OP_168J30_122_4811_n4465), .S(
DP_OP_168J30_122_4811_n3939), .ICO(DP_OP_168J30_122_4811_n3937), .CO(
DP_OP_168J30_122_4811_n3938) );
XOR2X1TS U2199 ( .A(n1179), .B(n3844), .Y(n1180) );
OAI21XLTS U2200 ( .A0(n1359), .A1(n1174), .B0(n1178), .Y(n1179) );
INVX2TS U2201 ( .A(n1659), .Y(n1173) );
OAI21XLTS U2202 ( .A0(n3527), .A1(n3604), .B0(n983), .Y(n984) );
OAI21XLTS U2203 ( .A0(n3548), .A1(n1275), .B0(n3481), .Y(n3482) );
OAI21XLTS U2204 ( .A0(n1359), .A1(n3604), .B0(n989), .Y(n990) );
OAI21XLTS U2205 ( .A0(n3531), .A1(n1130), .B0(n993), .Y(n994) );
OAI21XLTS U2206 ( .A0(n3535), .A1(n1130), .B0(n997), .Y(n998) );
OAI21XLTS U2207 ( .A0(n3557), .A1(n3521), .B0(n3486), .Y(n3487) );
OAI21XLTS U2208 ( .A0(n3760), .A1(n1130), .B0(n1006), .Y(n1007) );
OAI21XLTS U2209 ( .A0(n3743), .A1(n3521), .B0(n3490), .Y(n3491) );
OAI21XLTS U2210 ( .A0(n3756), .A1(n1130), .B0(n1010), .Y(n1011) );
OAI21XLTS U2211 ( .A0(n3548), .A1(n1130), .B0(n1014), .Y(n1015) );
OAI21XLTS U2212 ( .A0(n3552), .A1(n1130), .B0(n1018), .Y(n1020) );
OAI21XLTS U2213 ( .A0(n3575), .A1(n3521), .B0(n3498), .Y(n3499) );
OAI21XLTS U2214 ( .A0(n3557), .A1(n1130), .B0(n1023), .Y(n1024) );
AOI222X1TS U2215 ( .A0(n1128), .A1(n3555), .B0(n1125), .B1(n3559), .C0(n3602), .C1(Op_MY[42]), .Y(n1023) );
OAI21XLTS U2216 ( .A0(n4624), .A1(n1130), .B0(n1118), .Y(n1119) );
OAI21XLTS U2217 ( .A0(n4011), .A1(n4488), .B0(n4487), .Y(n4489) );
OAI21XLTS U2218 ( .A0(n3600), .A1(n748), .B0(n1092), .Y(n1093) );
INVX2TS U2219 ( .A(n1059), .Y(n4587) );
OAI21XLTS U2220 ( .A0(n2235), .A1(n4121), .B0(n3824), .Y(n3825) );
OAI21XLTS U2221 ( .A0(n4635), .A1(n3521), .B0(n3506), .Y(n3507) );
OAI21XLTS U2222 ( .A0(n3579), .A1(n1130), .B0(n1048), .Y(n1049) );
AOI222X1TS U2223 ( .A0(n1128), .A1(n3577), .B0(n1125), .B1(n3581), .C0(n1035), .C1(n3584), .Y(n1048) );
OAI21XLTS U2224 ( .A0(n3737), .A1(n1130), .B0(n1052), .Y(n1053) );
AOI222X1TS U2225 ( .A0(n1128), .A1(n3581), .B0(n1125), .B1(n3584), .C0(n1035), .C1(n3587), .Y(n1052) );
OAI21XLTS U2226 ( .A0(n4624), .A1(n3521), .B0(n3514), .Y(n3515) );
OAI21XLTS U2227 ( .A0(n4648), .A1(n1130), .B0(n1056), .Y(n1057) );
AOI222X1TS U2228 ( .A0(n1128), .A1(n3584), .B0(n1125), .B1(n3587), .C0(n1035), .C1(n3590), .Y(n1056) );
OAI21XLTS U2229 ( .A0(n4633), .A1(n3600), .B0(n1075), .Y(n1076) );
AOI222X1TS U2230 ( .A0(n3598), .A1(n3595), .B0(n3596), .B1(n3593), .C0(n3594), .C1(n3873), .Y(n1075) );
OAI21XLTS U2231 ( .A0(n4626), .A1(n1130), .B0(n1103), .Y(n1104) );
AOI222X1TS U2232 ( .A0(n1128), .A1(n3590), .B0(n1125), .B1(n3597), .C0(n1035), .C1(n3595), .Y(n1103) );
OAI21XLTS U2233 ( .A0(n933), .A1(n4408), .B0(n2699), .Y(n2701) );
OAI21XLTS U2234 ( .A0(n4644), .A1(n1130), .B0(n1110), .Y(n1111) );
AOI222X1TS U2235 ( .A0(n1128), .A1(n3597), .B0(n1125), .B1(n3595), .C0(n1035), .C1(n3593), .Y(n1110) );
OAI21XLTS U2236 ( .A0(n4596), .A1(n3600), .B0(n1085), .Y(n1086) );
CMPR42X1TS U2237 ( .A(DP_OP_168J30_122_4811_n2549), .B(
DP_OP_168J30_122_4811_n2877), .C(DP_OP_168J30_122_4811_n2555), .D(
DP_OP_168J30_122_4811_n2904), .ICI(DP_OP_168J30_122_4811_n2553), .S(
DP_OP_168J30_122_4811_n2547), .ICO(DP_OP_168J30_122_4811_n2545), .CO(
DP_OP_168J30_122_4811_n2546) );
OAI21XLTS U2238 ( .A0(n4133), .A1(n4422), .B0(n4059), .Y(n4060) );
INVX2TS U2239 ( .A(n1414), .Y(n4475) );
CMPR42X1TS U2240 ( .A(DP_OP_168J30_122_4811_n2873), .B(
DP_OP_168J30_122_4811_n2513), .C(DP_OP_168J30_122_4811_n2519), .D(
DP_OP_168J30_122_4811_n2900), .ICI(DP_OP_168J30_122_4811_n2520), .S(
DP_OP_168J30_122_4811_n2511), .ICO(DP_OP_168J30_122_4811_n2509), .CO(
DP_OP_168J30_122_4811_n2510) );
INVX2TS U2241 ( .A(n1440), .Y(n4446) );
CMPR42X1TS U2242 ( .A(DP_OP_168J30_122_4811_n2869), .B(
DP_OP_168J30_122_4811_n2471), .C(DP_OP_168J30_122_4811_n2477), .D(
DP_OP_168J30_122_4811_n2896), .ICI(DP_OP_168J30_122_4811_n2478), .S(
DP_OP_168J30_122_4811_n2468), .ICO(DP_OP_168J30_122_4811_n2466), .CO(
DP_OP_168J30_122_4811_n2467) );
OAI21XLTS U2243 ( .A0(n4449), .A1(n1574), .B0(n3805), .Y(n3806) );
INVX2TS U2244 ( .A(n1423), .Y(n4519) );
NAND2X1TS U2245 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1234) );
OAI21XLTS U2246 ( .A0(n3798), .A1(n4422), .B0(n3073), .Y(n3074) );
OAI21XLTS U2247 ( .A0(n4408), .A1(n1226), .B0(n4304), .Y(n4305) );
ADDHXLTS U2248 ( .A(n4119), .B(n4118), .CO(n4123), .S(
DP_OP_168J30_122_4811_n754) );
OAI21XLTS U2249 ( .A0(n926), .A1(n2733), .B0(n3902), .Y(n3903) );
OAI21XLTS U2250 ( .A0(n3919), .A1(n1230), .B0(n752), .Y(n3827) );
OAI21XLTS U2251 ( .A0(n4488), .A1(n4408), .B0(n4402), .Y(n4403) );
AOI222X1TS U2252 ( .A0(n2702), .A1(n4406), .B0(n4405), .B1(n4404), .C0(n2721), .C1(n4401), .Y(n4402) );
OAI21XLTS U2253 ( .A0(n2576), .A1(n1230), .B0(n3828), .Y(n3829) );
OAI21XLTS U2254 ( .A0(n2576), .A1(n1226), .B0(n2595), .Y(n2596) );
NAND2X1TS U2255 ( .A(n1373), .B(n1826), .Y(n1594) );
AOI222X1TS U2256 ( .A0(n2580), .A1(n4283), .B0(n4381), .B1(n4279), .C0(n4379), .C1(n4493), .Y(n2590) );
BUFX4TS U2257 ( .A(n2577), .Y(n4384) );
OAI21XLTS U2258 ( .A0(n4546), .A1(n1230), .B0(n754), .Y(n4398) );
OAI21XLTS U2259 ( .A0(n4163), .A1(n2733), .B0(n2752), .Y(n2753) );
AOI222X1TS U2260 ( .A0(n4397), .A1(n4508), .B0(n3922), .B1(n4509), .C0(n3921), .C1(n4493), .Y(n2512) );
OAI21XLTS U2261 ( .A0(n2576), .A1(n4488), .B0(n2584), .Y(n2585) );
OAI21XLTS U2262 ( .A0(n4552), .A1(n4317), .B0(n3928), .Y(n3929) );
AOI222X1TS U2263 ( .A0(n4550), .A1(n4314), .B0(n4549), .B1(n4312), .C0(n4363), .C1(n2734), .Y(n3928) );
NAND2X1TS U2264 ( .A(n913), .B(n2368), .Y(n2369) );
AOI21X1TS U2265 ( .A0(n2458), .A1(n915), .B0(n2367), .Y(n2370) );
OAI21XLTS U2266 ( .A0(n4610), .A1(n1230), .B0(n755), .Y(n3958) );
AOI222X1TS U2267 ( .A0(n3956), .A1(n4509), .B0(n2434), .B1(n4493), .C0(n2431), .C1(n4477), .Y(n2432) );
BUFX4TS U2268 ( .A(n2400), .Y(n3957) );
NOR2X1TS U2269 ( .A(n1780), .B(n1781), .Y(n1771) );
AOI21X1TS U2270 ( .A0(n1596), .A1(n1808), .B0(n1595), .Y(n1597) );
OAI21XLTS U2271 ( .A0(n3752), .A1(n1130), .B0(n1027), .Y(n1028) );
AOI222X1TS U2272 ( .A0(n1128), .A1(n3559), .B0(n1125), .B1(Op_MY[42]), .C0(
n3602), .C1(n3565), .Y(n1027) );
CMPR42X1TS U2273 ( .A(DP_OP_168J30_122_4811_n2936), .B(
DP_OP_168J30_122_4811_n2580), .C(DP_OP_168J30_122_4811_n2581), .D(
DP_OP_168J30_122_4811_n2963), .ICI(DP_OP_168J30_122_4811_n2582), .S(
DP_OP_168J30_122_4811_n2578), .ICO(DP_OP_168J30_122_4811_n2576), .CO(
DP_OP_168J30_122_4811_n2577) );
CMPR42X1TS U2274 ( .A(DP_OP_168J30_122_4811_n2932), .B(
DP_OP_168J30_122_4811_n2554), .C(DP_OP_168J30_122_4811_n2557), .D(
DP_OP_168J30_122_4811_n2959), .ICI(DP_OP_168J30_122_4811_n2558), .S(
DP_OP_168J30_122_4811_n2552), .ICO(DP_OP_168J30_122_4811_n2550), .CO(
DP_OP_168J30_122_4811_n2551) );
OAI21XLTS U2275 ( .A0(n4467), .A1(n1376), .B0(n1420), .Y(n1421) );
AOI222X1TS U2276 ( .A0(n1386), .A1(n4470), .B0(n1428), .B1(n4516), .C0(n1419), .C1(n4514), .Y(n1420) );
CMPR42X1TS U2277 ( .A(DP_OP_168J30_122_4811_n2928), .B(
DP_OP_168J30_122_4811_n2521), .C(DP_OP_168J30_122_4811_n2526), .D(
DP_OP_168J30_122_4811_n2955), .ICI(DP_OP_168J30_122_4811_n2527), .S(
DP_OP_168J30_122_4811_n2518), .ICO(DP_OP_168J30_122_4811_n2516), .CO(
DP_OP_168J30_122_4811_n2517) );
OAI21XLTS U2278 ( .A0(n4441), .A1(n3129), .B0(n4440), .Y(n4442) );
OAI21X1TS U2279 ( .A0(n1744), .A1(n1740), .B0(n1741), .Y(n1738) );
NAND2X1TS U2280 ( .A(DP_OP_168J30_122_4811_n2211), .B(
DP_OP_168J30_122_4811_n2215), .Y(n1750) );
NOR2X2TS U2281 ( .A(DP_OP_168J30_122_4811_n2211), .B(
DP_OP_168J30_122_4811_n2215), .Y(n1749) );
NAND2X1TS U2282 ( .A(n1755), .B(n875), .Y(n1748) );
AOI21X1TS U2283 ( .A0(n1756), .A1(n875), .B0(n1602), .Y(n1747) );
CMPR42X1TS U2284 ( .A(DP_OP_168J30_122_4811_n1973), .B(
DP_OP_168J30_122_4811_n574), .C(DP_OP_168J30_122_4811_n570), .D(
DP_OP_168J30_122_4811_n1022), .ICI(DP_OP_168J30_122_4811_n561), .S(
DP_OP_168J30_122_4811_n558), .ICO(DP_OP_168J30_122_4811_n556), .CO(
DP_OP_168J30_122_4811_n557) );
NOR2X1TS U2285 ( .A(n1748), .B(n1749), .Y(n1604) );
OAI21X1TS U2286 ( .A0(n1747), .A1(n1749), .B0(n1750), .Y(n1603) );
NOR2X1TS U2287 ( .A(DP_OP_168J30_122_4811_n2208), .B(
DP_OP_168J30_122_4811_n2210), .Y(n1740) );
NAND2X1TS U2288 ( .A(DP_OP_168J30_122_4811_n2208), .B(
DP_OP_168J30_122_4811_n2210), .Y(n1741) );
AOI222X1TS U2289 ( .A0(n1521), .A1(n4415), .B0(n1520), .B1(n4356), .C0(n1519), .C1(n4309), .Y(n1495) );
NOR2X6TS U2290 ( .A(n1220), .B(DP_OP_168J30_122_4811_n3615), .Y(n1386) );
NAND2X1TS U2291 ( .A(DP_OP_168J30_122_4811_n2219), .B(
DP_OP_168J30_122_4811_n2216), .Y(n1759) );
CMPR42X1TS U2292 ( .A(DP_OP_168J30_122_4811_n703), .B(
DP_OP_168J30_122_4811_n1229), .C(DP_OP_168J30_122_4811_n697), .D(
DP_OP_168J30_122_4811_n1145), .ICI(DP_OP_168J30_122_4811_n700), .S(
DP_OP_168J30_122_4811_n695), .ICO(DP_OP_168J30_122_4811_n693), .CO(
DP_OP_168J30_122_4811_n694) );
OAI21XLTS U2293 ( .A0(n3919), .A1(n4121), .B0(n2652), .Y(n2653) );
NOR2X1TS U2294 ( .A(DP_OP_168J30_122_4811_n3881), .B(n1344), .Y(n2062) );
NAND2X1TS U2295 ( .A(DP_OP_168J30_122_4811_n3893), .B(
DP_OP_168J30_122_4811_n3890), .Y(n2070) );
NAND2X1TS U2296 ( .A(n2073), .B(n938), .Y(n1330) );
AOI21X1TS U2297 ( .A0(n2074), .A1(n938), .B0(n1328), .Y(n1329) );
INVX2TS U2298 ( .A(n2074), .Y(n2075) );
NAND2X1TS U2299 ( .A(DP_OP_168J30_122_4811_n3898), .B(
DP_OP_168J30_122_4811_n3904), .Y(n3662) );
NOR2X1TS U2300 ( .A(n3649), .B(n3655), .Y(n3658) );
AOI21X1TS U2301 ( .A0(n3653), .A1(n940), .B0(n3652), .Y(n3654) );
NAND2X1TS U2302 ( .A(n3650), .B(n3658), .Y(n3661) );
NAND2X1TS U2303 ( .A(DP_OP_168J30_122_4811_n3910), .B(
DP_OP_168J30_122_4811_n3905), .Y(n2084) );
NOR2X1TS U2304 ( .A(n3649), .B(n2091), .Y(n2081) );
NAND2X1TS U2305 ( .A(n3650), .B(n2081), .Y(n2083) );
INVX2TS U2306 ( .A(n2091), .Y(n3648) );
AOI21X1TS U2307 ( .A0(n3659), .A1(n2088), .B0(n2087), .Y(n2089) );
NOR2X2TS U2308 ( .A(DP_OP_168J30_122_4811_n3930), .B(
DP_OP_168J30_122_4811_n3924), .Y(n3639) );
AOI21X2TS U2309 ( .A0(n3669), .A1(n1313), .B0(n1312), .Y(n2100) );
INVX2TS U2310 ( .A(n3637), .Y(n2102) );
AOI21X1TS U2311 ( .A0(n3669), .A1(n3668), .B0(n3667), .Y(n3670) );
NAND2X1TS U2312 ( .A(n3665), .B(n3668), .Y(n3671) );
NAND2X1TS U2313 ( .A(DP_OP_168J30_122_4811_n3939), .B(
DP_OP_168J30_122_4811_n3948), .Y(n3673) );
NOR2X2TS U2314 ( .A(DP_OP_168J30_122_4811_n3939), .B(
DP_OP_168J30_122_4811_n3948), .Y(n3672) );
NOR2X2TS U2315 ( .A(n2110), .B(n3677), .Y(n3665) );
INVX2TS U2316 ( .A(n2107), .Y(n3668) );
INVX2TS U2317 ( .A(n3669), .Y(n2105) );
NAND2X1TS U2318 ( .A(DP_OP_168J30_122_4811_n3957), .B(
DP_OP_168J30_122_4811_n3949), .Y(n3666) );
CMPR42X1TS U2319 ( .A(DP_OP_168J30_122_4811_n4472), .B(
DP_OP_168J30_122_4811_n4012), .C(DP_OP_168J30_122_4811_n4018), .D(
DP_OP_168J30_122_4811_n4498), .ICI(DP_OP_168J30_122_4811_n4524), .S(
DP_OP_168J30_122_4811_n4009), .ICO(DP_OP_168J30_122_4811_n4007), .CO(
DP_OP_168J30_122_4811_n4008) );
NAND2X1TS U2320 ( .A(DP_OP_168J30_122_4811_n4009), .B(
DP_OP_168J30_122_4811_n4019), .Y(n1637) );
OR2X1TS U2321 ( .A(DP_OP_168J30_122_4811_n4009), .B(
DP_OP_168J30_122_4811_n4019), .Y(n954) );
INVX2TS U2322 ( .A(n1653), .Y(n1644) );
NAND2X1TS U2323 ( .A(DP_OP_168J30_122_4811_n4041), .B(
DP_OP_168J30_122_4811_n4031), .Y(n1653) );
OR2X1TS U2324 ( .A(DP_OP_168J30_122_4811_n4041), .B(
DP_OP_168J30_122_4811_n4031), .Y(n956) );
OAI21X1TS U2325 ( .A0(n1662), .A1(n1665), .B0(n1663), .Y(n1657) );
INVX2TS U2326 ( .A(n1671), .Y(n1372) );
NOR2X1TS U2327 ( .A(DP_OP_168J30_122_4811_n4053), .B(n1171), .Y(n1667) );
OA21X1TS U2328 ( .A0(n1674), .A1(n1677), .B0(n1675), .Y(n872) );
NAND2X1TS U2329 ( .A(DP_OP_168J30_122_4811_n4053), .B(n1171), .Y(n1668) );
INVX2TS U2330 ( .A(n1682), .Y(n1274) );
NOR2X1TS U2331 ( .A(DP_OP_168J30_122_4811_n4064), .B(n1170), .Y(n1674) );
INVX2TS U2332 ( .A(n1684), .Y(n1169) );
NOR2X1TS U2333 ( .A(DP_OP_168J30_122_4811_n231), .B(
DP_OP_168J30_122_4811_n236), .Y(n1679) );
NAND2X1TS U2334 ( .A(DP_OP_168J30_122_4811_n4075), .B(n1168), .Y(n1684) );
OAI21X2TS U2335 ( .A0(n1688), .A1(n920), .B0(n1689), .Y(n1685) );
NAND2X1TS U2336 ( .A(DP_OP_168J30_122_4811_n4108), .B(n1164), .Y(n1699) );
AOI21X2TS U2337 ( .A0(n923), .A1(n862), .B0(n1160), .Y(n1709) );
BUFX6TS U2338 ( .A(n4585), .Y(n4641) );
NOR2X1TS U2339 ( .A(n1361), .B(n1360), .Y(n2057) );
NAND2X1TS U2340 ( .A(n1361), .B(n1360), .Y(n2058) );
INVX2TS U2341 ( .A(n3624), .Y(n1353) );
AOI21X1TS U2342 ( .A0(n868), .A1(n1986), .B0(n1136), .Y(n1982) );
NOR2X1TS U2343 ( .A(n1138), .B(n1137), .Y(n1979) );
NAND2X1TS U2344 ( .A(n1138), .B(n1137), .Y(n1980) );
NOR2X1TS U2345 ( .A(n1133), .B(n1132), .Y(n1989) );
NAND2X1TS U2346 ( .A(n1133), .B(n1132), .Y(n1990) );
CMPR42X1TS U2347 ( .A(DP_OP_168J30_122_4811_n1970), .B(
DP_OP_168J30_122_4811_n524), .C(DP_OP_168J30_122_4811_n991), .D(
DP_OP_168J30_122_4811_n528), .ICI(DP_OP_168J30_122_4811_n513), .S(
DP_OP_168J30_122_4811_n510), .ICO(DP_OP_168J30_122_4811_n508), .CO(
DP_OP_168J30_122_4811_n509) );
OAI21XLTS U2348 ( .A0(n2235), .A1(n4495), .B0(n4494), .Y(n4496) );
NOR2X1TS U2349 ( .A(n1615), .B(n1614), .Y(n1730) );
NAND2X1TS U2350 ( .A(n1615), .B(n1614), .Y(n1731) );
AOI21X1TS U2351 ( .A0(n895), .A1(n2024), .B0(n1154), .Y(n1727) );
NOR2X1TS U2352 ( .A(DP_OP_168J30_122_4811_n4162), .B(n1155), .Y(n1724) );
NAND2X1TS U2353 ( .A(DP_OP_168J30_122_4811_n4162), .B(n1155), .Y(n1725) );
OAI21X2TS U2354 ( .A0(n1948), .A1(n1951), .B0(n1949), .Y(n2024) );
NAND2X1TS U2355 ( .A(DP_OP_168J30_122_4811_n4188), .B(n1148), .Y(n1957) );
OAI21X1TS U2356 ( .A0(n1961), .A1(n900), .B0(n1962), .Y(n1958) );
NOR2X1TS U2357 ( .A(n1146), .B(n1145), .Y(n1966) );
OAI21X1TS U2358 ( .A0(n1979), .A1(n1982), .B0(n1980), .Y(n1976) );
OR2X1TS U2359 ( .A(n1140), .B(n1139), .Y(n873) );
OAI21XLTS U2360 ( .A0(n4435), .A1(n859), .B0(n1491), .Y(n1492) );
OAI21XLTS U2361 ( .A0(n4180), .A1(n4435), .B0(n1481), .Y(n1482) );
OAI21X2TS U2362 ( .A0(n1880), .A1(n1876), .B0(n1877), .Y(n1873) );
OAI21XLTS U2363 ( .A0(n2656), .A1(n1226), .B0(n4183), .Y(n4184) );
OAI21XLTS U2364 ( .A0(n4233), .A1(n2733), .B0(n2760), .Y(n2761) );
CMPR42X1TS U2365 ( .A(DP_OP_168J30_122_4811_n673), .B(
DP_OP_168J30_122_4811_n1226), .C(DP_OP_168J30_122_4811_n1114), .D(
DP_OP_168J30_122_4811_n667), .ICI(DP_OP_168J30_122_4811_n670), .S(
DP_OP_168J30_122_4811_n664), .ICO(DP_OP_168J30_122_4811_n662), .CO(
DP_OP_168J30_122_4811_n663) );
OAI21XLTS U2366 ( .A0(n2576), .A1(n4121), .B0(n2590), .Y(n2591) );
CMPR42X1TS U2367 ( .A(DP_OP_168J30_122_4811_n1979), .B(
DP_OP_168J30_122_4811_n652), .C(DP_OP_168J30_122_4811_n648), .D(
DP_OP_168J30_122_4811_n1084), .ICI(DP_OP_168J30_122_4811_n642), .S(
DP_OP_168J30_122_4811_n639), .ICO(DP_OP_168J30_122_4811_n637), .CO(
DP_OP_168J30_122_4811_n638) );
NAND2X1TS U2368 ( .A(DP_OP_168J30_122_4811_n2238), .B(
DP_OP_168J30_122_4811_n2243), .Y(n1788) );
NOR2X2TS U2369 ( .A(DP_OP_168J30_122_4811_n2237), .B(
DP_OP_168J30_122_4811_n2232), .Y(n1781) );
NAND2X1TS U2370 ( .A(n903), .B(n1793), .Y(n1780) );
AOI21X1TS U2371 ( .A0(n903), .A1(n1600), .B0(n1599), .Y(n1779) );
NAND2X1TS U2372 ( .A(DP_OP_168J30_122_4811_n2237), .B(
DP_OP_168J30_122_4811_n2232), .Y(n1782) );
OAI21X1TS U2373 ( .A0(n1779), .A1(n1781), .B0(n1782), .Y(n1772) );
AOI21X1TS U2374 ( .A0(n1772), .A1(n874), .B0(n1601), .Y(n1763) );
NAND2X1TS U2375 ( .A(n1771), .B(n874), .Y(n1764) );
NOR2X2TS U2376 ( .A(DP_OP_168J30_122_4811_n2220), .B(
DP_OP_168J30_122_4811_n2224), .Y(n1765) );
XNOR2X2TS U2377 ( .A(n1885), .B(n1884), .Y(n4574) );
NAND2X1TS U2378 ( .A(n830), .B(n1883), .Y(n1884) );
OAI21XLTS U2379 ( .A0(n4365), .A1(n1230), .B0(n751), .Y(n1273) );
CLKXOR2X2TS U2380 ( .A(n1865), .B(n1864), .Y(n3718) );
AOI21X1TS U2381 ( .A0(n828), .A1(n1869), .B0(n1862), .Y(n1865) );
XNOR2X2TS U2382 ( .A(n1843), .B(n1842), .Y(n3727) );
OAI21X1TS U2383 ( .A0(n1859), .A1(n1840), .B0(n1839), .Y(n1843) );
NAND2X1TS U2384 ( .A(n1836), .B(n825), .Y(n1840) );
OAI21XLTS U2385 ( .A0(n4408), .A1(n1230), .B0(n750), .Y(n1253) );
CLKXOR2X2TS U2386 ( .A(n1880), .B(n1879), .Y(n3711) );
NAND2X1TS U2387 ( .A(n1878), .B(n1877), .Y(n1879) );
CLKXOR2X2TS U2388 ( .A(n1859), .B(n1858), .Y(n3726) );
NAND2X1TS U2389 ( .A(n1857), .B(n1856), .Y(n1858) );
XNOR2X2TS U2390 ( .A(n1833), .B(n1832), .Y(n3724) );
XNOR2X2TS U2391 ( .A(n1738), .B(n1737), .Y(n3701) );
XNOR2X2TS U2392 ( .A(n1753), .B(n1752), .Y(n3706) );
XNOR2X2TS U2393 ( .A(n1870), .B(n1869), .Y(n3722) );
NAND2X1TS U2394 ( .A(n828), .B(n1868), .Y(n1870) );
INVX2TS U2395 ( .A(n1889), .Y(n1891) );
NAND2X1TS U2396 ( .A(n1542), .B(n1541), .Y(n4187) );
CLKXOR2X2TS U2397 ( .A(n1734), .B(n1733), .Y(n3705) );
XNOR2X2TS U2398 ( .A(n1761), .B(n1760), .Y(n3702) );
OAI21X1TS U2399 ( .A0(n1795), .A1(n1758), .B0(n1757), .Y(n1761) );
NAND2X1TS U2400 ( .A(n1826), .B(n1825), .Y(n1827) );
AOI21X1TS U2401 ( .A0(n1833), .A1(n1831), .B0(n1824), .Y(n1828) );
INVX2TS U2402 ( .A(n1830), .Y(n1824) );
XNOR2X1TS U2403 ( .A(n3626), .B(n3625), .Y(n4729) );
NAND2X1TS U2404 ( .A(n2064), .B(n2063), .Y(n2065) );
NAND2X1TS U2405 ( .A(n936), .B(n2067), .Y(n2068) );
NOR2X1TS U2406 ( .A(DP_OP_168J30_122_4811_n3885), .B(
DP_OP_168J30_122_4811_n3889), .Y(n3619) );
NAND2X1TS U2407 ( .A(n937), .B(n2070), .Y(n2071) );
NAND2X1TS U2408 ( .A(n938), .B(n2077), .Y(n2078) );
INVX2TS U2409 ( .A(n2073), .Y(n2076) );
XNOR2X1TS U2410 ( .A(n3664), .B(n3663), .Y(n5278) );
NAND2X1TS U2411 ( .A(n939), .B(n3662), .Y(n3663) );
AOI21X1TS U2412 ( .A0(n3659), .A1(n3658), .B0(n3657), .Y(n3660) );
XNOR2X1TS U2413 ( .A(n2086), .B(n2085), .Y(Sgf_operation_ODD1_Q_left[41]) );
NAND2X1TS U2414 ( .A(n940), .B(n2084), .Y(n2085) );
AOI21X1TS U2415 ( .A0(n3659), .A1(n2081), .B0(n2080), .Y(n2082) );
NAND2X1TS U2416 ( .A(n3648), .B(n3651), .Y(n2092) );
NAND2X1TS U2417 ( .A(n3650), .B(n2088), .Y(n2090) );
NAND2X1TS U2418 ( .A(DP_OP_168J30_122_4811_n3916), .B(
DP_OP_168J30_122_4811_n3923), .Y(n3645) );
NOR2X1TS U2419 ( .A(n3637), .B(n3639), .Y(n3642) );
AOI21X1TS U2420 ( .A0(n3659), .A1(n3642), .B0(n3641), .Y(n3643) );
OAI21XLTS U2421 ( .A0(n3640), .A1(n3639), .B0(n3638), .Y(n3641) );
INVX2TS U2422 ( .A(n2101), .Y(n3650) );
NAND2X1TS U2423 ( .A(n2097), .B(n3638), .Y(n2098) );
NAND2X1TS U2424 ( .A(n3650), .B(n2102), .Y(n2096) );
XNOR2X1TS U2425 ( .A(n2104), .B(n2103), .Y(Sgf_operation_ODD1_Q_left[37]) );
NAND2X1TS U2426 ( .A(n2102), .B(n3640), .Y(n2103) );
XNOR2X1TS U2427 ( .A(n3676), .B(n3675), .Y(n5234) );
NAND2X1TS U2428 ( .A(n3674), .B(n3673), .Y(n3675) );
XNOR2X1TS U2429 ( .A(n2109), .B(n2108), .Y(Sgf_operation_ODD1_Q_left[35]) );
NAND2X1TS U2430 ( .A(n3668), .B(n3666), .Y(n2108) );
INVX2TS U2431 ( .A(n3665), .Y(n2106) );
XNOR2X2TS U2432 ( .A(n2114), .B(n2113), .Y(Sgf_operation_ODD1_Q_left[34]) );
NAND2X1TS U2433 ( .A(n2112), .B(n2111), .Y(n2113) );
INVX2TS U2434 ( .A(n2110), .Y(n2112) );
NOR2X2TS U2435 ( .A(DP_OP_168J30_122_4811_n3966), .B(
DP_OP_168J30_122_4811_n3976), .Y(n3677) );
NAND2X1TS U2436 ( .A(n2118), .B(n2117), .Y(n2119) );
OAI21X1TS U2437 ( .A0(n2124), .A1(n2121), .B0(n2122), .Y(n2120) );
NOR2X1TS U2438 ( .A(DP_OP_168J30_122_4811_n3998), .B(
DP_OP_168J30_122_4811_n4008), .Y(n1282) );
NAND2X1TS U2439 ( .A(DP_OP_168J30_122_4811_n3998), .B(
DP_OP_168J30_122_4811_n4008), .Y(n1281) );
AOI21X2TS U2440 ( .A0(n1639), .A1(n954), .B0(n1184), .Y(n1283) );
INVX2TS U2441 ( .A(n1637), .Y(n1184) );
XOR2X1TS U2442 ( .A(n2125), .B(n2124), .Y(Sgf_operation_ODD1_Q_left[31]) );
NAND2X1TS U2443 ( .A(n2123), .B(n2122), .Y(n2125) );
INVX2TS U2444 ( .A(n2121), .Y(n2123) );
XNOR2X2TS U2445 ( .A(n1639), .B(n1638), .Y(n3631) );
NAND2X1TS U2446 ( .A(n954), .B(n1637), .Y(n1638) );
CLKXOR2X2TS U2447 ( .A(n1647), .B(n1646), .Y(n3826) );
NAND2X1TS U2448 ( .A(n955), .B(n1645), .Y(n1646) );
AOI21X1TS U2449 ( .A0(n1655), .A1(n956), .B0(n1644), .Y(n1647) );
CLKXOR2X2TS U2450 ( .A(n1652), .B(n1651), .Y(n2045) );
NAND2X1TS U2451 ( .A(n1650), .B(n1649), .Y(n1652) );
INVX2TS U2452 ( .A(n1648), .Y(n1650) );
XNOR2X2TS U2453 ( .A(n1655), .B(n1654), .Y(n3628) );
NAND2X1TS U2454 ( .A(n956), .B(n1653), .Y(n1654) );
NAND2X1TS U2455 ( .A(n885), .B(n1656), .Y(n1658) );
XNOR2X2TS U2456 ( .A(n1661), .B(n1660), .Y(n3629) );
NAND2X1TS U2457 ( .A(n958), .B(n1659), .Y(n1661) );
NAND2X1TS U2458 ( .A(n849), .B(n1671), .Y(n1673) );
CLKXOR2X2TS U2459 ( .A(n1678), .B(n1677), .Y(n3611) );
NAND2X1TS U2460 ( .A(n1676), .B(n1675), .Y(n1678) );
INVX2TS U2461 ( .A(n1674), .Y(n1676) );
NAND2X1TS U2462 ( .A(n1681), .B(n1680), .Y(n1683) );
INVX2TS U2463 ( .A(n1679), .Y(n1681) );
XNOR2X2TS U2464 ( .A(n1686), .B(n1685), .Y(n3608) );
NAND2X1TS U2465 ( .A(n921), .B(n1684), .Y(n1686) );
INVX2TS U2466 ( .A(n1688), .Y(n1690) );
CLKXOR2X2TS U2467 ( .A(n1697), .B(n1696), .Y(n3610) );
NAND2X1TS U2468 ( .A(n1695), .B(n1694), .Y(n1697) );
INVX2TS U2469 ( .A(n1693), .Y(n1695) );
XNOR2X2TS U2470 ( .A(n1700), .B(n845), .Y(n3609) );
NAND2X1TS U2471 ( .A(n739), .B(n1699), .Y(n1700) );
XNOR2X2TS U2472 ( .A(n1704), .B(n1703), .Y(n3627) );
NAND2X1TS U2473 ( .A(n737), .B(n1702), .Y(n1704) );
NAND2X1TS U2474 ( .A(n943), .B(n5049), .Y(n5038) );
NOR2X2TS U2475 ( .A(n2007), .B(n4143), .Y(n5042) );
NAND2X1TS U2476 ( .A(n924), .B(n5071), .Y(n5054) );
NOR2X2TS U2477 ( .A(n2004), .B(n2003), .Y(n5058) );
OAI21X1TS U2478 ( .A0(n1734), .A1(n1730), .B0(n1731), .Y(n1624) );
NAND2X1TS U2479 ( .A(n947), .B(n4983), .Y(n4972) );
INVX2TS U2480 ( .A(n4984), .Y(n2018) );
CLKXOR2X2TS U2481 ( .A(n1952), .B(n1951), .Y(n4298) );
NAND2X1TS U2482 ( .A(n1950), .B(n1949), .Y(n1952) );
NOR2X2TS U2483 ( .A(n2019), .B(n4298), .Y(n4976) );
NAND2X1TS U2484 ( .A(n944), .B(n5033), .Y(n5021) );
NOR2X2TS U2485 ( .A(n2010), .B(n4125), .Y(n5025) );
XNOR2X2TS U2486 ( .A(n1874), .B(n1873), .Y(n3723) );
NAND2X1TS U2487 ( .A(n829), .B(n1872), .Y(n1874) );
XNOR2X2TS U2488 ( .A(n1854), .B(n1853), .Y(n3725) );
XNOR2X2TS U2489 ( .A(n1849), .B(n1848), .Y(n3717) );
OAI21X1TS U2490 ( .A0(n1859), .A1(n1846), .B0(n1845), .Y(n1849) );
CLKXOR2X2TS U2491 ( .A(n1821), .B(n1820), .Y(n3720) );
AOI21X1TS U2492 ( .A0(n1833), .A1(n1818), .B0(n1817), .Y(n1821) );
OAI21XLTS U2493 ( .A0(n1830), .A1(n1816), .B0(n1825), .Y(n1817) );
CLKXOR2X2TS U2494 ( .A(n1814), .B(n1813), .Y(n3721) );
AOI21X1TS U2495 ( .A0(n1833), .A1(n1809), .B0(n1808), .Y(n1814) );
CLKXOR2X2TS U2496 ( .A(n1806), .B(n1805), .Y(n3709) );
NAND2X1TS U2497 ( .A(n1804), .B(n1803), .Y(n1805) );
AOI21X1TS U2498 ( .A0(n1833), .A1(n1801), .B0(n1800), .Y(n1806) );
CLKXOR2X2TS U2499 ( .A(n1795), .B(n1794), .Y(n3719) );
NAND2X1TS U2500 ( .A(n1793), .B(n1792), .Y(n1794) );
XNOR2X2TS U2501 ( .A(n1790), .B(n1789), .Y(n3710) );
XNOR2X2TS U2502 ( .A(n1785), .B(n1784), .Y(n3703) );
NAND2X1TS U2503 ( .A(n1783), .B(n1782), .Y(n1784) );
XNOR2X2TS U2504 ( .A(n1777), .B(n1776), .Y(n3707) );
OAI21X1TS U2505 ( .A0(n1795), .A1(n1774), .B0(n1773), .Y(n1777) );
XNOR2X2TS U2506 ( .A(n1769), .B(n1768), .Y(n3708) );
NAND2X1TS U2507 ( .A(n1767), .B(n1766), .Y(n1768) );
OAI21X1TS U2508 ( .A0(n1795), .A1(n1764), .B0(n1763), .Y(n1769) );
XNOR2X2TS U2509 ( .A(n1717), .B(n1716), .Y(n3635) );
XNOR2X1TS U2510 ( .A(n4370), .B(n4369), .Y(n4816) );
NAND2X1TS U2511 ( .A(n867), .B(n4368), .Y(n4370) );
XOR2X1TS U2512 ( .A(n4484), .B(n4483), .Y(n4873) );
XOR2X1TS U2513 ( .A(n3686), .B(n3685), .Y(n4877) );
NAND2X1TS U2514 ( .A(n3684), .B(n3683), .Y(n3686) );
XOR2X1TS U2515 ( .A(n3694), .B(n3693), .Y(n4881) );
NAND2X1TS U2516 ( .A(n3692), .B(n3691), .Y(n3694) );
XOR2X1TS U2517 ( .A(n4538), .B(n4537), .Y(n4885) );
XNOR2X1TS U2518 ( .A(n4565), .B(n4564), .Y(n4889) );
NAND2X1TS U2519 ( .A(n4574), .B(n1905), .Y(n4898) );
INVX2TS U2520 ( .A(n4894), .Y(n1904) );
INVX2TS U2521 ( .A(n4912), .Y(n1911) );
NOR2X1TS U2522 ( .A(n3718), .B(n1912), .Y(n4915) );
NAND2X1TS U2523 ( .A(n3718), .B(n1912), .Y(n4916) );
NAND2X1TS U2524 ( .A(n3727), .B(n1918), .Y(n4934) );
XNOR2X1TS U2525 ( .A(n1530), .B(n4337), .Y(n4813) );
XOR2X1TS U2526 ( .A(n4429), .B(n4428), .Y(n4817) );
XNOR2X1TS U2527 ( .A(n4492), .B(n4491), .Y(n4874) );
NAND2X1TS U2528 ( .A(n878), .B(n4490), .Y(n4492) );
XNOR2X1TS U2529 ( .A(n3689), .B(n3688), .Y(n4878) );
NAND2X1TS U2530 ( .A(n876), .B(n3687), .Y(n3689) );
XNOR2X1TS U2531 ( .A(n4561), .B(n4560), .Y(n4882) );
NAND2X1TS U2532 ( .A(n898), .B(n4559), .Y(n4561) );
XOR2X1TS U2533 ( .A(n4542), .B(n860), .Y(n4886) );
NAND2X1TS U2534 ( .A(n4541), .B(n4540), .Y(n4542) );
XOR2X1TS U2535 ( .A(n3716), .B(n3715), .Y(n4890) );
INVX2TS U2536 ( .A(n4898), .Y(n1906) );
NOR2X1TS U2537 ( .A(n3711), .B(n1907), .Y(n4901) );
NAND2X1TS U2538 ( .A(n3711), .B(n1907), .Y(n4902) );
NAND2X1TS U2539 ( .A(n3726), .B(n1913), .Y(n4921) );
OAI21X2TS U2540 ( .A0(n4915), .A1(n4918), .B0(n4916), .Y(n4922) );
NAND2X1TS U2541 ( .A(n3724), .B(n1920), .Y(n4938) );
NOR2X1TS U2542 ( .A(n3701), .B(n1942), .Y(n4832) );
NAND2X1TS U2543 ( .A(n3701), .B(n1942), .Y(n4833) );
NAND2X1TS U2544 ( .A(n3706), .B(n1938), .Y(n4825) );
NAND2X1TS U2545 ( .A(n3704), .B(n1940), .Y(n4829) );
NAND2X1TS U2546 ( .A(n3722), .B(n1910), .Y(n4912) );
NAND2X1TS U2547 ( .A(n4573), .B(n1903), .Y(n4894) );
INVX2TS U2548 ( .A(n4893), .Y(n4895) );
XOR2X1TS U2549 ( .A(n4570), .B(n4569), .Y(n4888) );
XNOR2X1TS U2550 ( .A(n3697), .B(n3696), .Y(n4884) );
XNOR2X1TS U2551 ( .A(n4528), .B(n4527), .Y(n4880) );
NAND2X1TS U2552 ( .A(n877), .B(n4505), .Y(n4507) );
XNOR2X1TS U2553 ( .A(n4189), .B(n4188), .Y(n4872) );
NAND2X1TS U2554 ( .A(n749), .B(n4187), .Y(n4189) );
XOR2X1TS U2555 ( .A(n4352), .B(n4351), .Y(n4815) );
NAND2X1TS U2556 ( .A(n4350), .B(n4349), .Y(n4352) );
NAND2X1TS U2557 ( .A(n3705), .B(n1943), .Y(n5080) );
NAND2X1TS U2558 ( .A(n3702), .B(n1937), .Y(n4820) );
NOR2X1TS U2559 ( .A(n4575), .B(n1922), .Y(n4941) );
NAND2X1TS U2560 ( .A(n4575), .B(n1922), .Y(n4942) );
NAND2X1TS U2561 ( .A(n4729), .B(n4728), .Y(n4733) );
NAND2X1TS U2562 ( .A(Sgf_operation_ODD1_Q_left[46]), .B(n4721), .Y(n4725) );
NAND2X1TS U2563 ( .A(Sgf_operation_ODD1_Q_left[44]), .B(n4713), .Y(n4718) );
NAND2X1TS U2564 ( .A(n5278), .B(n5276), .Y(n4710) );
NAND2X1TS U2565 ( .A(Sgf_operation_ODD1_Q_left[40]), .B(n5262), .Y(n5268) );
NAND2X1TS U2566 ( .A(n3650), .B(n3642), .Y(n3644) );
NAND2X1TS U2567 ( .A(Sgf_operation_ODD1_Q_left[38]), .B(n5248), .Y(n5255) );
NAND2X1TS U2568 ( .A(n5234), .B(n5233), .Y(n5241) );
INVX2TS U2569 ( .A(Sgf_operation_ODD1_Q_left[35]), .Y(n5226) );
NAND2X1TS U2570 ( .A(Sgf_operation_ODD1_Q_left[34]), .B(n5218), .Y(n5224) );
NAND2X1TS U2571 ( .A(Sgf_operation_ODD1_Q_left[32]), .B(n5204), .Y(n5210) );
CLKXOR2X2TS U2572 ( .A(n1283), .B(n1186), .Y(Sgf_operation_ODD1_Q_left[30])
);
NAND2X1TS U2573 ( .A(n1185), .B(n1281), .Y(n1186) );
INVX2TS U2574 ( .A(n1282), .Y(n1185) );
INVX2TS U2575 ( .A(n5156), .Y(n2043) );
NOR2X1TS U2576 ( .A(n2044), .B(n3629), .Y(n5162) );
NAND2X1TS U2577 ( .A(n2044), .B(n3629), .Y(n5163) );
NAND2X1TS U2578 ( .A(n2039), .B(n3608), .Y(n5140) );
NOR2X1TS U2579 ( .A(n2038), .B(n3612), .Y(n5131) );
NAND2X1TS U2580 ( .A(n2038), .B(n3612), .Y(n5132) );
INVX2TS U2581 ( .A(n5116), .Y(n2036) );
NOR2X1TS U2582 ( .A(n2037), .B(n3610), .Y(n5122) );
NAND2X1TS U2583 ( .A(n2037), .B(n3610), .Y(n5123) );
NAND2X1TS U2584 ( .A(n2035), .B(n3609), .Y(n5116) );
NAND2X1TS U2585 ( .A(n2034), .B(n3627), .Y(n5109) );
AO21XLTS U2586 ( .A0(n2056), .A1(n935), .B0(n1366), .Y(n731) );
INVX2TS U2587 ( .A(Sgf_operation_ODD1_Q_left[30]), .Y(n4706) );
BUFX6TS U2588 ( .A(n5030), .Y(n5281) );
NAND2X1TS U2589 ( .A(n2019), .B(n4298), .Y(n4977) );
NAND2X1TS U2590 ( .A(n4341), .B(n4340), .Y(n4342) );
NOR2XLTS U2591 ( .A(n4338), .B(n4337), .Y(n4343) );
XOR2X1TS U2592 ( .A(n4151), .B(n865), .Y(n4818) );
NAND2X1TS U2593 ( .A(n4150), .B(n4149), .Y(n4151) );
XOR2X1TS U2594 ( .A(n3818), .B(n3817), .Y(n4875) );
NAND2X1TS U2595 ( .A(n3816), .B(n3815), .Y(n3818) );
XOR2X1TS U2596 ( .A(n4525), .B(n4524), .Y(n4879) );
NAND2X1TS U2597 ( .A(n4523), .B(n4522), .Y(n4525) );
XOR2X1TS U2598 ( .A(n4533), .B(n4532), .Y(n4883) );
NAND2X1TS U2599 ( .A(n4531), .B(n4530), .Y(n4533) );
XNOR2X1TS U2600 ( .A(n3700), .B(n3699), .Y(n4887) );
XNOR2X2TS U2601 ( .A(n1899), .B(n1898), .Y(n4892) );
NAND2X1TS U2602 ( .A(n4892), .B(n4891), .Y(n4893) );
NAND2X1TS U2603 ( .A(n3723), .B(n1908), .Y(n4908) );
OAI21X2TS U2604 ( .A0(n4901), .A1(n4904), .B0(n4902), .Y(n4909) );
NAND2X1TS U2605 ( .A(n3725), .B(n1915), .Y(n4925) );
NAND2X1TS U2606 ( .A(n3717), .B(n1917), .Y(n4929) );
NAND2X1TS U2607 ( .A(n3720), .B(n1923), .Y(n4854) );
NAND2X1TS U2608 ( .A(n3721), .B(n1925), .Y(n4858) );
NAND2X1TS U2609 ( .A(n3709), .B(n1927), .Y(n4862) );
NAND2X1TS U2610 ( .A(n3719), .B(n1928), .Y(n4867) );
NOR2X1TS U2611 ( .A(n3703), .B(n1932), .Y(n4841) );
NAND2X1TS U2612 ( .A(n3703), .B(n1932), .Y(n4842) );
NAND2X1TS U2613 ( .A(n3707), .B(n1933), .Y(n4847) );
OAI21X2TS U2614 ( .A0(n4841), .A1(n4844), .B0(n4842), .Y(n4848) );
NAND2X1TS U2615 ( .A(n3708), .B(n1935), .Y(n4851) );
NAND2X1TS U2616 ( .A(n2030), .B(n3635), .Y(n4958) );
BUFX6TS U2617 ( .A(n5030), .Y(n5019) );
INVX3TS U2618 ( .A(n5374), .Y(n5455) );
MX2X1TS U2619 ( .A(P_Sgf[51]), .B(n4837), .S0(n4871), .Y(n472) );
XOR2X1TS U2620 ( .A(n4836), .B(n4835), .Y(n4837) );
MX2X1TS U2621 ( .A(P_Sgf[49]), .B(n4828), .S0(n4871), .Y(n470) );
MX2X1TS U2622 ( .A(P_Sgf[50]), .B(n4831), .S0(n4871), .Y(n471) );
XNOR2X1TS U2623 ( .A(n4830), .B(n746), .Y(n4831) );
AO22XLTS U2624 ( .A0(n5454), .A1(n4698), .B0(n5374), .B1(Add_result[33]),
.Y(n546) );
AO22XLTS U2625 ( .A0(n5454), .A1(n5439), .B0(n5449), .B1(Add_result[41]),
.Y(n538) );
AO22XLTS U2626 ( .A0(n5464), .A1(n5379), .B0(n5449), .B1(Add_result[7]), .Y(
n572) );
AO22XLTS U2627 ( .A0(n5464), .A1(n5387), .B0(n5449), .B1(Add_result[11]),
.Y(n568) );
AO22XLTS U2628 ( .A0(n5464), .A1(n5399), .B0(n5449), .B1(Add_result[17]),
.Y(n562) );
AO22XLTS U2629 ( .A0(n4947), .A1(Data_MX[63]), .B0(n4948), .B1(Op_MX[63]),
.Y(n645) );
MX2X1TS U2630 ( .A(P_Sgf[52]), .B(n5083), .S0(n5228), .Y(n473) );
XOR2X1TS U2631 ( .A(n5082), .B(n742), .Y(n5083) );
MX2X1TS U2632 ( .A(P_Sgf[48]), .B(n4824), .S0(n4871), .Y(n469) );
XOR2X1TS U2633 ( .A(n5191), .B(n5190), .Y(n5192) );
NAND2X1TS U2634 ( .A(n5189), .B(n5188), .Y(n5191) );
XNOR2X1TS U2635 ( .A(n5182), .B(n5181), .Y(n5183) );
NAND2X1TS U2636 ( .A(n886), .B(n5180), .Y(n5182) );
XOR2X1TS U2637 ( .A(n5175), .B(n957), .Y(n5176) );
NAND2X1TS U2638 ( .A(n5174), .B(n5173), .Y(n5175) );
INVX2TS U2639 ( .A(n5172), .Y(n5174) );
XOR2X1TS U2640 ( .A(n5166), .B(n5165), .Y(n5167) );
NAND2X1TS U2641 ( .A(n5164), .B(n5163), .Y(n5166) );
INVX2TS U2642 ( .A(n5162), .Y(n5164) );
XNOR2X1TS U2643 ( .A(n5157), .B(n953), .Y(n5158) );
XNOR2X1TS U2644 ( .A(n5150), .B(n5149), .Y(n5151) );
NAND2X1TS U2645 ( .A(n734), .B(n5148), .Y(n5150) );
XOR2X1TS U2646 ( .A(n5142), .B(n952), .Y(n5143) );
NAND2X1TS U2647 ( .A(n5141), .B(n5140), .Y(n5142) );
INVX2TS U2648 ( .A(n5139), .Y(n5141) );
XOR2X1TS U2649 ( .A(n5134), .B(n951), .Y(n5135) );
NAND2X1TS U2650 ( .A(n5133), .B(n5132), .Y(n5134) );
INVX2TS U2651 ( .A(n5131), .Y(n5133) );
XOR2X1TS U2652 ( .A(n5126), .B(n5125), .Y(n5127) );
NAND2X1TS U2653 ( .A(n5124), .B(n5123), .Y(n5126) );
INVX2TS U2654 ( .A(n5122), .Y(n5124) );
XNOR2X1TS U2655 ( .A(n5117), .B(n747), .Y(n5118) );
NAND2X1TS U2656 ( .A(n730), .B(n5116), .Y(n5117) );
XNOR2X1TS U2657 ( .A(n5111), .B(n5110), .Y(n5112) );
NAND2X1TS U2658 ( .A(n950), .B(n5109), .Y(n5111) );
NAND2X1TS U2659 ( .A(n5103), .B(n5102), .Y(n5104) );
AO22XLTS U2660 ( .A0(n5464), .A1(n5375), .B0(n5460), .B1(Add_result[5]), .Y(
n574) );
XOR2X1TS U2661 ( .A(n5095), .B(n5094), .Y(n5096) );
NAND2X1TS U2662 ( .A(n5093), .B(n5092), .Y(n5095) );
MX2X1TS U2663 ( .A(P_Sgf[59]), .B(n5037), .S0(n5228), .Y(n480) );
XOR2X1TS U2664 ( .A(n5036), .B(n5035), .Y(n5037) );
AOI21X1TS U2665 ( .A0(n5073), .A1(n5033), .B0(n5032), .Y(n5036) );
MX2X1TS U2666 ( .A(P_Sgf[58]), .B(n5047), .S0(n5228), .Y(n479) );
XOR2X1TS U2667 ( .A(n5046), .B(n5045), .Y(n5047) );
AOI21X1TS U2668 ( .A0(n5073), .A1(n5041), .B0(n5040), .Y(n5046) );
MX2X1TS U2669 ( .A(P_Sgf[57]), .B(n5053), .S0(n5228), .Y(n478) );
XOR2X1TS U2670 ( .A(n5052), .B(n5051), .Y(n5053) );
AOI21X1TS U2671 ( .A0(n5073), .A1(n5049), .B0(n5048), .Y(n5052) );
MX2X1TS U2672 ( .A(P_Sgf[56]), .B(n5063), .S0(n5228), .Y(n477) );
XOR2X1TS U2673 ( .A(n5062), .B(n5061), .Y(n5063) );
AOI21X1TS U2674 ( .A0(n5073), .A1(n5057), .B0(n5056), .Y(n5062) );
MX2X1TS U2675 ( .A(P_Sgf[55]), .B(n5069), .S0(n5228), .Y(n476) );
XNOR2X1TS U2676 ( .A(n5068), .B(n5067), .Y(n5069) );
MX2X1TS U2677 ( .A(P_Sgf[54]), .B(n5074), .S0(n5228), .Y(n475) );
XNOR2X1TS U2678 ( .A(n5073), .B(n5072), .Y(n5074) );
MX2X1TS U2679 ( .A(P_Sgf[53]), .B(n5078), .S0(n5228), .Y(n474) );
XNOR2X1TS U2680 ( .A(n5077), .B(n5076), .Y(n5078) );
XOR2X1TS U2681 ( .A(n4956), .B(n4955), .Y(n4957) );
NAND2X1TS U2682 ( .A(n4954), .B(n4953), .Y(n4956) );
MX2X1TS U2683 ( .A(P_Sgf[68]), .B(n4965), .S0(n5019), .Y(n489) );
XNOR2X1TS U2684 ( .A(n4964), .B(n4963), .Y(n4965) );
MX2X1TS U2685 ( .A(P_Sgf[67]), .B(n4971), .S0(n5019), .Y(n488) );
XOR2X1TS U2686 ( .A(n4970), .B(n4969), .Y(n4971) );
NAND2X1TS U2687 ( .A(n4968), .B(n4967), .Y(n4969) );
MX2X1TS U2688 ( .A(P_Sgf[66]), .B(n4981), .S0(n5019), .Y(n487) );
XOR2X1TS U2689 ( .A(n4980), .B(n4979), .Y(n4981) );
NAND2X1TS U2690 ( .A(n4978), .B(n4977), .Y(n4979) );
AOI21X1TS U2691 ( .A0(n5073), .A1(n4975), .B0(n4974), .Y(n4980) );
MX2X1TS U2692 ( .A(P_Sgf[65]), .B(n4987), .S0(n5019), .Y(n486) );
XOR2X1TS U2693 ( .A(n4986), .B(n4985), .Y(n4987) );
AOI21X1TS U2694 ( .A0(n5073), .A1(n4983), .B0(n4982), .Y(n4986) );
MX2X1TS U2695 ( .A(P_Sgf[64]), .B(n4997), .S0(n5019), .Y(n485) );
AOI21X1TS U2696 ( .A0(n5073), .A1(n4991), .B0(n4990), .Y(n4996) );
MX2X1TS U2697 ( .A(P_Sgf[63]), .B(n5003), .S0(n5019), .Y(n484) );
XOR2X1TS U2698 ( .A(n5002), .B(n5001), .Y(n5003) );
AOI21X1TS U2699 ( .A0(n5073), .A1(n4999), .B0(n4998), .Y(n5002) );
MX2X1TS U2700 ( .A(P_Sgf[62]), .B(n5013), .S0(n5019), .Y(n483) );
XOR2X1TS U2701 ( .A(n5012), .B(n5011), .Y(n5013) );
AOI21X1TS U2702 ( .A0(n5073), .A1(n5007), .B0(n5006), .Y(n5012) );
MX2X1TS U2703 ( .A(P_Sgf[61]), .B(n5020), .S0(n5019), .Y(n482) );
XOR2X1TS U2704 ( .A(n5018), .B(n5017), .Y(n5020) );
AOI21X1TS U2705 ( .A0(n5073), .A1(n5015), .B0(n5014), .Y(n5018) );
MX2X1TS U2706 ( .A(P_Sgf[60]), .B(n5031), .S0(n5228), .Y(n481) );
XOR2X1TS U2707 ( .A(n5029), .B(n5028), .Y(n5031) );
AOI21X1TS U2708 ( .A0(n5073), .A1(n5024), .B0(n5023), .Y(n5029) );
XNOR2X1TS U2709 ( .A(n4960), .B(n4959), .Y(n4961) );
NAND2X1TS U2710 ( .A(n949), .B(n4958), .Y(n4960) );
AO22XLTS U2711 ( .A0(n5464), .A1(n5383), .B0(n5449), .B1(n817), .Y(n570) );
AO22XLTS U2712 ( .A0(n5464), .A1(n5391), .B0(n5449), .B1(n818), .Y(n566) );
AO22XLTS U2713 ( .A0(n5464), .A1(n5395), .B0(n5449), .B1(n819), .Y(n564) );
AO22XLTS U2714 ( .A0(n5464), .A1(n5403), .B0(n5449), .B1(n801), .Y(n560) );
AO22XLTS U2715 ( .A0(n5464), .A1(n5407), .B0(n5449), .B1(n802), .Y(n558) );
AO22XLTS U2716 ( .A0(n5464), .A1(n5411), .B0(n5449), .B1(n803), .Y(n556) );
AO22XLTS U2717 ( .A0(n5454), .A1(n4702), .B0(n5374), .B1(n810), .Y(n536) );
AO22XLTS U2718 ( .A0(n5454), .A1(n4704), .B0(n5374), .B1(n804), .Y(n532) );
OR2X1TS U2719 ( .A(DP_OP_168J30_122_4811_n4118), .B(n1162), .Y(n737) );
OR2X1TS U2720 ( .A(DP_OP_168J30_122_4811_n4188), .B(n1148), .Y(n738) );
OR2X1TS U2721 ( .A(DP_OP_168J30_122_4811_n4108), .B(n1164), .Y(n739) );
OR2X1TS U2722 ( .A(n4573), .B(n1903), .Y(n741) );
NAND2X1TS U2723 ( .A(n3199), .B(Op_MY[27]), .Y(n743) );
NAND2X1TS U2724 ( .A(n3414), .B(Op_MY[27]), .Y(n744) );
AO21X1TS U2725 ( .A0(n908), .A1(n4826), .B0(n1939), .Y(n746) );
BUFX4TS U2726 ( .A(n2550), .Y(n4313) );
XNOR2X2TS U2727 ( .A(n2135), .B(Op_MY[25]), .Y(n2550) );
OR2X1TS U2728 ( .A(n1542), .B(n1541), .Y(n749) );
NAND2X1TS U2729 ( .A(n2702), .B(n4477), .Y(n750) );
BUFX6TS U2730 ( .A(Op_MX[29]), .Y(n4652) );
NAND2X1TS U2731 ( .A(n4262), .B(n4477), .Y(n751) );
NAND2X1TS U2732 ( .A(n2644), .B(n4477), .Y(n752) );
AOI22X1TS U2733 ( .A0(n4397), .A1(n4493), .B0(n3922), .B1(n4477), .Y(n753)
);
NAND2X1TS U2734 ( .A(n4397), .B(n4477), .Y(n754) );
BUFX6TS U2735 ( .A(Op_MX[50]), .Y(n4649) );
NAND2X1TS U2736 ( .A(n3956), .B(n4477), .Y(n755) );
AND3X1TS U2737 ( .A(n1289), .B(n1287), .C(n1288), .Y(n3201) );
AOI22X1TS U2738 ( .A0(n2358), .A1(n4493), .B0(n2356), .B1(n4477), .Y(n756)
);
AOI22X1TS U2739 ( .A0(n3956), .A1(n4493), .B0(n2434), .B1(n4477), .Y(n757)
);
XNOR2X1TS U2740 ( .A(n2079), .B(n2078), .Y(Sgf_operation_ODD1_Q_left[43]) );
BUFX4TS U2741 ( .A(Op_MX[32]), .Y(n3844) );
XOR2X1TS U2742 ( .A(n3623), .B(n3622), .Y(n4715) );
XNOR2X2TS U2743 ( .A(n2056), .B(n2055), .Y(Sgf_operation_ODD1_Q_left[50]) );
XNOR2X2TS U2744 ( .A(n2072), .B(n2071), .Y(Sgf_operation_ODD1_Q_left[44]) );
XNOR2X2TS U2745 ( .A(n2099), .B(n2098), .Y(Sgf_operation_ODD1_Q_left[38]) );
XNOR2X2TS U2746 ( .A(n2093), .B(n2092), .Y(Sgf_operation_ODD1_Q_left[40]) );
XNOR2X2TS U2747 ( .A(n2069), .B(n2068), .Y(Sgf_operation_ODD1_Q_left[46]) );
XNOR2X2TS U2748 ( .A(n2120), .B(n2119), .Y(Sgf_operation_ODD1_Q_left[32]) );
ADDHX1TS U2749 ( .A(n3984), .B(n3983), .CO(n3877), .S(
DP_OP_168J30_122_4811_n4143) );
ADDHX1TS U2750 ( .A(n3982), .B(n3981), .CO(n3983), .S(
DP_OP_168J30_122_4811_n4151) );
ADDHX1TS U2751 ( .A(n3962), .B(n3961), .CO(n3223), .S(
DP_OP_168J30_122_4811_n4185) );
ADDHX1TS U2752 ( .A(n3960), .B(n3959), .CO(n3961), .S(
DP_OP_168J30_122_4811_n4190) );
ADDHX1TS U2753 ( .A(n4580), .B(n4579), .CO(n3988), .S(
DP_OP_168J30_122_4811_n4083) );
ADDHX1TS U2754 ( .A(n4577), .B(n4576), .CO(n4579), .S(
DP_OP_168J30_122_4811_n4094) );
NAND2X1TS U2755 ( .A(n2610), .B(n2609), .Y(n2611) );
INVX2TS U2756 ( .A(n2609), .Y(n2520) );
OAI21X1TS U2757 ( .A0(n2609), .A1(n2523), .B0(n2524), .Y(n967) );
OR2X4TS U2758 ( .A(FSM_selector_B[1]), .B(n5497), .Y(n4803) );
XNOR2X2TS U2759 ( .A(Op_MX[1]), .B(Op_MX[0]), .Y(n1219) );
AOI222X1TS U2760 ( .A0(n4614), .A1(n4314), .B0(n4550), .B1(n4312), .C0(n4549), .C1(n2734), .Y(n3906) );
AOI222X1TS U2761 ( .A0(n4544), .A1(n4314), .B0(n4614), .B1(n4312), .C0(n4550), .C1(n2734), .Y(n2748) );
BUFX4TS U2762 ( .A(n2737), .Y(n4312) );
NAND2X1TS U2763 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n1269) );
NAND2X1TS U2764 ( .A(DP_OP_168J30_122_4811_n4042), .B(n1172), .Y(n1659) );
CMPR42X1TS U2765 ( .A(DP_OP_168J30_122_4811_n741), .B(
DP_OP_168J30_122_4811_n738), .C(DP_OP_168J30_122_4811_n737), .D(
DP_OP_168J30_122_4811_n1178), .ICI(DP_OP_168J30_122_4811_n735), .S(
DP_OP_168J30_122_4811_n733), .ICO(DP_OP_168J30_122_4811_n731), .CO(
DP_OP_168J30_122_4811_n732) );
CMPR42X1TS U2766 ( .A(DP_OP_168J30_122_4811_n729), .B(
DP_OP_168J30_122_4811_n1232), .C(DP_OP_168J30_122_4811_n723), .D(
DP_OP_168J30_122_4811_n1176), .ICI(DP_OP_168J30_122_4811_n724), .S(
DP_OP_168J30_122_4811_n721), .ICO(DP_OP_168J30_122_4811_n719), .CO(
DP_OP_168J30_122_4811_n720) );
AOI222X1TS U2767 ( .A0(n3956), .A1(n4571), .B0(n2434), .B1(n4572), .C0(n2431), .C1(n4562), .Y(n2419) );
AOI222X1TS U2768 ( .A0(n3956), .A1(n4578), .B0(n4606), .B1(n4571), .C0(n2431), .C1(n4572), .Y(n2417) );
AOI222X1TS U2769 ( .A0(n3956), .A1(n4603), .B0(n2434), .B1(n4578), .C0(n2431), .C1(n4571), .Y(n2415) );
AOI222X1TS U2770 ( .A0(n3956), .A1(n2407), .B0(n2434), .B1(n4630), .C0(n2431), .C1(n4604), .Y(n2408) );
AOI222X1TS U2771 ( .A0(n3956), .A1(n4604), .B0(n2434), .B1(n4603), .C0(n2431), .C1(n4578), .Y(n2413) );
BUFX4TS U2772 ( .A(n2398), .Y(n2431) );
AOI222X1TS U2773 ( .A0(n4397), .A1(n4630), .B0(n4543), .B1(n4604), .C0(n3921), .C1(n4603), .Y(n2498) );
AOI222X1TS U2774 ( .A0(n4397), .A1(n4603), .B0(n3922), .B1(n4578), .C0(n3921), .C1(n4571), .Y(n3839) );
AOI222X1TS U2775 ( .A0(n4397), .A1(n4655), .B0(n3922), .B1(n4630), .C0(n3921), .C1(n4604), .Y(n2496) );
AOI222X1TS U2776 ( .A0(n2495), .A1(n4656), .B0(n3922), .B1(n4655), .C0(n3921), .C1(n4630), .Y(n2493) );
AOI222X1TS U2777 ( .A0(n4397), .A1(n4572), .B0(n3922), .B1(n4562), .C0(n3921), .C1(n4510), .Y(n2504) );
BUFX4TS U2778 ( .A(n2487), .Y(n3921) );
AOI222X1TS U2779 ( .A0(n2358), .A1(n4510), .B0(n2356), .B1(n4511), .C0(n2353), .C1(n4508), .Y(n2338) );
AOI222X1TS U2780 ( .A0(n2358), .A1(n4562), .B0(n2356), .B1(n4510), .C0(n2353), .C1(n4511), .Y(n2334) );
AOI222X1TS U2781 ( .A0(n2358), .A1(n4604), .B0(n2356), .B1(n2410), .C0(n2353), .C1(n4578), .Y(n2322) );
AOI222X1TS U2782 ( .A0(n2358), .A1(n4578), .B0(n2356), .B1(n4571), .C0(n2353), .C1(n4572), .Y(n2326) );
BUFX4TS U2783 ( .A(n2309), .Y(n2353) );
AOI222X1TS U2784 ( .A0(n4401), .A1(n4271), .B0(n4283), .B1(n4270), .C0(n4269), .C1(n4279), .Y(n3902) );
AOI222X1TS U2785 ( .A0(n4404), .A1(n4271), .B0(n4401), .B1(n4270), .C0(n4269), .C1(n4283), .Y(n4116) );
AOI222X1TS U2786 ( .A0(n2702), .A1(n4401), .B0(n4405), .B1(n4283), .C0(n2721), .C1(n4279), .Y(n4280) );
AOI222X1TS U2787 ( .A0(n2702), .A1(n4404), .B0(n4405), .B1(n4401), .C0(n2721), .C1(n4283), .Y(n4284) );
BUFX4TS U2788 ( .A(DP_OP_168J30_122_4811_n1865), .Y(n4283) );
AOI222X1TS U2789 ( .A0(n4406), .A1(n4271), .B0(n4404), .B1(n4270), .C0(n4401), .C1(n4269), .Y(n4272) );
AOI222X1TS U2790 ( .A0(n4572), .A1(n4271), .B0(n4406), .B1(n4270), .C0(n4404), .C1(n4269), .Y(n4152) );
AOI222X1TS U2791 ( .A0(n4231), .A1(n4271), .B0(n4572), .B1(n4270), .C0(n4406), .C1(n4269), .Y(n4190) );
AOI222X1TS U2792 ( .A0(n4572), .A1(n2702), .B0(n4406), .B1(n4405), .C0(n2721), .C1(n4404), .Y(n4407) );
AOI222X1TS U2793 ( .A0(n4262), .A1(n4406), .B0(n4360), .B1(n4404), .C0(n2690), .C1(n4401), .Y(n4235) );
BUFX4TS U2794 ( .A(DP_OP_168J30_122_4811_n1862), .Y(n4406) );
NAND2X1TS U2795 ( .A(DP_OP_168J30_122_4811_n2583), .B(n1544), .Y(n4481) );
XOR2X1TS U2796 ( .A(n1458), .B(Op_MX[2]), .Y(n1544) );
ADDHX1TS U2797 ( .A(n3897), .B(n3896), .CO(n2827), .S(
DP_OP_168J30_122_4811_n2473) );
XOR2X1TS U2798 ( .A(n2816), .B(n2930), .Y(n3897) );
NOR4X1TS U2799 ( .A(Op_MY[21]), .B(Op_MY[20]), .C(Op_MY[19]), .D(Op_MY[18]),
.Y(n5327) );
NOR4X1TS U2800 ( .A(Op_MY[31]), .B(Op_MY[30]), .C(Op_MY[29]), .D(Op_MY[28]),
.Y(n5326) );
NOR4X1TS U2801 ( .A(Op_MY[1]), .B(Op_MY[0]), .C(Op_MY[45]), .D(Op_MY[44]),
.Y(n5331) );
NOR4X1TS U2802 ( .A(Op_MY[17]), .B(Op_MY[16]), .C(Op_MY[15]), .D(Op_MY[14]),
.Y(n5335) );
AOI222X1TS U2803 ( .A0(n4380), .A1(n2702), .B0(n4231), .B1(n4405), .C0(n4572), .C1(n2721), .Y(n4232) );
AOI222X1TS U2804 ( .A0(n4380), .A1(n4271), .B0(n4231), .B1(n4270), .C0(
DP_OP_168J30_122_4811_n1861), .C1(n4269), .Y(n2760) );
AOI222X1TS U2805 ( .A0(n4603), .A1(n2702), .B0(n4380), .B1(n4405), .C0(n4231), .C1(n2721), .Y(n4205) );
BUFX4TS U2806 ( .A(DP_OP_168J30_122_4811_n1860), .Y(n4231) );
NOR4X1TS U2807 ( .A(Op_MX[39]), .B(Op_MX[38]), .C(Op_MX[37]), .D(Op_MX[36]),
.Y(n5351) );
NOR4X1TS U2808 ( .A(Op_MY[13]), .B(Op_MY[12]), .C(Op_MY[11]), .D(Op_MY[10]),
.Y(n5336) );
NOR4X1TS U2809 ( .A(Op_MX[35]), .B(Op_MX[34]), .C(Op_MX[33]), .D(Op_MX[32]),
.Y(n5352) );
NOR4X1TS U2810 ( .A(Op_MX[9]), .B(Op_MX[7]), .C(Op_MX[5]), .D(Op_MX[3]), .Y(
n5349) );
BUFX4TS U2811 ( .A(DP_OP_168J30_122_4811_n1866), .Y(n4279) );
AOI222X1TS U2812 ( .A0(n4227), .A1(n4332), .B0(n4315), .B1(n4331), .C0(n4313), .C1(n4330), .Y(n2705) );
AOI222X1TS U2813 ( .A0(n4227), .A1(n4362), .B0(n4315), .B1(n4261), .C0(n790),
.C1(n4260), .Y(n2669) );
BUFX4TS U2814 ( .A(n2540), .Y(n4227) );
CMPR32X4TS U2815 ( .A(Op_MY[47]), .B(Op_MY[20]), .C(n2137), .CO(n2136), .S(
n4615) );
INVX2TS U2816 ( .A(n2519), .Y(n2610) );
BUFX4TS U2817 ( .A(n2689), .Y(n4261) );
BUFX4TS U2818 ( .A(n2645), .Y(n4373) );
BUFX4TS U2819 ( .A(n2724), .Y(n4331) );
BUFX4TS U2820 ( .A(n2581), .Y(n4381) );
BUFX4TS U2821 ( .A(n2646), .Y(n4372) );
BUFX4TS U2822 ( .A(n2721), .Y(n4330) );
BUFX4TS U2823 ( .A(n2690), .Y(n4260) );
BUFX4TS U2824 ( .A(n2573), .Y(n4379) );
AOI222X1TS U2825 ( .A0(n4549), .A1(n4314), .B0(n4363), .B1(n4312), .C0(n4361), .C1(n2734), .Y(n4299) );
AOI222X1TS U2826 ( .A0(n3916), .A1(n4314), .B0(n4656), .B1(n4312), .C0(n4655), .C1(n4269), .Y(n2750) );
INVX2TS U2827 ( .A(n777), .Y(n791) );
INVX2TS U2828 ( .A(n778), .Y(n792) );
INVX2TS U2829 ( .A(n779), .Y(n793) );
INVX2TS U2830 ( .A(n780), .Y(n794) );
INVX2TS U2831 ( .A(n781), .Y(n795) );
INVX2TS U2832 ( .A(n782), .Y(n796) );
INVX2TS U2833 ( .A(n783), .Y(n797) );
INVX2TS U2834 ( .A(n784), .Y(n798) );
INVX2TS U2835 ( .A(n785), .Y(n799) );
INVX2TS U2836 ( .A(n786), .Y(n800) );
INVX2TS U2837 ( .A(n773), .Y(n801) );
INVX2TS U2838 ( .A(n774), .Y(n802) );
INVX2TS U2839 ( .A(n775), .Y(n803) );
INVX2TS U2840 ( .A(n772), .Y(n804) );
INVX2TS U2841 ( .A(n776), .Y(n805) );
INVX2TS U2842 ( .A(n768), .Y(n806) );
INVX2TS U2843 ( .A(n769), .Y(n807) );
INVX2TS U2844 ( .A(n770), .Y(n808) );
INVX2TS U2845 ( .A(n771), .Y(n809) );
NOR3XLTS U2846 ( .A(Op_MX[25]), .B(Op_MX[1]), .C(Op_MX[53]), .Y(n5346) );
INVX2TS U2847 ( .A(n766), .Y(n810) );
INVX2TS U2848 ( .A(n767), .Y(n811) );
INVX2TS U2849 ( .A(n733), .Y(n812) );
INVX2TS U2850 ( .A(n763), .Y(n813) );
NOR4X1TS U2851 ( .A(Op_MX[56]), .B(Op_MX[55]), .C(n813), .D(Op_MX[54]), .Y(
n5342) );
INVX2TS U2852 ( .A(n764), .Y(n814) );
INVX2TS U2853 ( .A(n728), .Y(n815) );
INVX2TS U2854 ( .A(n765), .Y(n816) );
INVX2TS U2855 ( .A(n787), .Y(n817) );
INVX2TS U2856 ( .A(n788), .Y(n818) );
INVX2TS U2857 ( .A(n789), .Y(n819) );
CMPR32X4TS U2858 ( .A(Op_MY[50]), .B(Op_MY[23]), .C(n2131), .CO(n2130), .S(
n4008) );
CMPR32X4TS U2859 ( .A(Op_MY[49]), .B(Op_MY[22]), .C(n2132), .CO(n2131), .S(
n4605) );
NAND2X1TS U2860 ( .A(n4616), .B(n4615), .Y(n2202) );
BUFX6TS U2861 ( .A(n4616), .Y(n4658) );
NAND2X1TS U2862 ( .A(n4605), .B(n4616), .Y(n2196) );
CMPR32X4TS U2863 ( .A(Op_MY[48]), .B(Op_MY[21]), .C(n2136), .CO(n2132), .S(
n4616) );
AOI21X2TS U2864 ( .A0(Sgf_normalized_result[3]), .A1(
Sgf_normalized_result[2]), .B0(Sgf_normalized_result[4]), .Y(n5373) );
BUFX4TS U2865 ( .A(n2233), .Y(n4503) );
BUFX4TS U2866 ( .A(n2233), .Y(DP_OP_168J30_122_4811_n86) );
ADDHX1TS U2867 ( .A(Op_MX[26]), .B(n1626), .CO(n1627), .S(n2233) );
NOR4X1TS U2868 ( .A(Op_MX[26]), .B(Op_MX[24]), .C(Op_MX[22]), .D(Op_MX[20]),
.Y(n5354) );
XNOR2X2TS U2869 ( .A(Op_MX[3]), .B(Op_MX[4]), .Y(n1473) );
NOR4X1TS U2870 ( .A(Op_MX[10]), .B(Op_MX[8]), .C(Op_MX[6]), .D(Op_MX[4]),
.Y(n5356) );
NOR2X1TS U2871 ( .A(Op_MX[46]), .B(Op_MX[19]), .Y(n2371) );
NOR4X1TS U2872 ( .A(Op_MX[23]), .B(Op_MX[21]), .C(Op_MX[19]), .D(Op_MX[27]),
.Y(n5347) );
NOR2X1TS U2873 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2270) );
NOR4X1TS U2874 ( .A(Op_MX[46]), .B(Op_MX[47]), .C(Op_MX[48]), .D(Op_MX[49]),
.Y(n5345) );
NOR2X2TS U2875 ( .A(Op_MX[42]), .B(Op_MX[15]), .Y(n2447) );
NOR4X1TS U2876 ( .A(Op_MX[17]), .B(Op_MX[15]), .C(Op_MX[13]), .D(Op_MX[11]),
.Y(n5348) );
NAND2X1TS U2877 ( .A(Op_MX[49]), .B(Op_MX[22]), .Y(n2278) );
NAND2X1TS U2878 ( .A(Op_MX[43]), .B(Op_MX[16]), .Y(n2456) );
NOR4X1TS U2879 ( .A(Op_MX[18]), .B(Op_MX[16]), .C(Op_MX[14]), .D(Op_MX[12]),
.Y(n5355) );
XNOR2X2TS U2880 ( .A(Op_MX[41]), .B(Op_MX[42]), .Y(n1301) );
XNOR2X2TS U2881 ( .A(Op_MX[42]), .B(Op_MX[43]), .Y(n1299) );
NOR4X1TS U2882 ( .A(Op_MX[43]), .B(Op_MX[42]), .C(Op_MX[41]), .D(Op_MX[40]),
.Y(n5350) );
AOI222X1TS U2883 ( .A0(n1128), .A1(n3529), .B0(n1125), .B1(n3533), .C0(n3602), .C1(n3537), .Y(n993) );
AOI222X1TS U2884 ( .A0(n1128), .A1(n3533), .B0(n1125), .B1(n3537), .C0(n3602), .C1(n3540), .Y(n997) );
AOI222X1TS U2885 ( .A0(n1128), .A1(n3537), .B0(n1125), .B1(n3540), .C0(n3602), .C1(n3543), .Y(n1001) );
AOI222X1TS U2886 ( .A0(n1128), .A1(n3540), .B0(n1005), .B1(n3543), .C0(n3602), .C1(n3546), .Y(n1006) );
AOI222X1TS U2887 ( .A0(n1128), .A1(n3543), .B0(n1125), .B1(n3546), .C0(n3602), .C1(n3550), .Y(n1010) );
AOI222X1TS U2888 ( .A0(n1128), .A1(n3546), .B0(n1125), .B1(n3550), .C0(n3602), .C1(n3555), .Y(n1014) );
AOI222X1TS U2889 ( .A0(n1128), .A1(n3550), .B0(n1125), .B1(n3555), .C0(n3602), .C1(n3559), .Y(n1018) );
AOI222X1TS U2890 ( .A0(n1128), .A1(Op_MY[42]), .B0(n1125), .B1(n3565), .C0(
n3602), .C1(n3568), .Y(n1031) );
AOI222X1TS U2891 ( .A0(n1128), .A1(n3565), .B0(n1125), .B1(n3568), .C0(n1035), .C1(n3573), .Y(n1036) );
AOI222X1TS U2892 ( .A0(n1128), .A1(n3568), .B0(n1125), .B1(n3573), .C0(n1035), .C1(n3577), .Y(n1040) );
AOI222X1TS U2893 ( .A0(n1128), .A1(n3573), .B0(n1125), .B1(n3577), .C0(n1035), .C1(n3581), .Y(n1044) );
AOI222X1TS U2894 ( .A0(n1128), .A1(n3587), .B0(n1125), .B1(n3590), .C0(n1035), .C1(n3597), .Y(n1096) );
XOR2X1TS U2895 ( .A(n2164), .B(n2163), .Y(n2171) );
INVX2TS U2896 ( .A(n2171), .Y(n820) );
AND3X2TS U2897 ( .A(n2170), .B(n820), .C(n2172), .Y(n2231) );
NAND2X1TS U2898 ( .A(DP_OP_168J30_122_4811_n220), .B(
DP_OP_168J30_122_4811_n224), .Y(n1663) );
NAND2X1TS U2899 ( .A(DP_OP_168J30_122_4811_n231), .B(
DP_OP_168J30_122_4811_n236), .Y(n1680) );
XNOR2X2TS U2900 ( .A(Op_MX[9]), .B(Op_MX[10]), .Y(n3084) );
NAND2BX1TS U2901 ( .AN(n888), .B(n986), .Y(n3604) );
NAND2X1TS U2902 ( .A(DP_OP_168J30_122_4811_n2452), .B(n1566), .Y(n4567) );
NAND2X1TS U2903 ( .A(DP_OP_168J30_122_4811_n2508), .B(n1559), .Y(n4530) );
NAND2X1TS U2904 ( .A(DP_OP_168J30_122_4811_n2528), .B(n1556), .Y(n3691) );
NAND2X1TS U2905 ( .A(DP_OP_168J30_122_4811_n2544), .B(n1553), .Y(n4522) );
NAND2X1TS U2906 ( .A(DP_OP_168J30_122_4811_n2559), .B(n1550), .Y(n3683) );
NAND2X1TS U2907 ( .A(DP_OP_168J30_122_4811_n2573), .B(n1547), .Y(n3815) );
NAND2X1TS U2908 ( .A(n1540), .B(n1539), .Y(n4149) );
NOR4X1TS U2909 ( .A(Op_MY[25]), .B(Op_MY[24]), .C(Op_MY[23]), .D(Op_MY[22]),
.Y(n5328) );
NOR4X1TS U2910 ( .A(P_Sgf[39]), .B(P_Sgf[37]), .C(P_Sgf[38]), .D(P_Sgf[36]),
.Y(n4678) );
NOR4X1TS U2911 ( .A(Op_MY[39]), .B(Op_MY[38]), .C(Op_MY[37]), .D(Op_MY[36]),
.Y(n5333) );
NOR4X1TS U2912 ( .A(Op_MY[9]), .B(Op_MY[8]), .C(Op_MY[7]), .D(Op_MY[6]), .Y(
n5337) );
AOI222X4TS U2913 ( .A0(n4646), .A1(Op_MY[36]), .B0(n4645), .B1(Op_MY[35]),
.C0(n3183), .C1(Op_MY[34]), .Y(n4647) );
AOI222X4TS U2914 ( .A0(n4646), .A1(Op_MY[35]), .B0(n4645), .B1(Op_MY[34]),
.C0(n3240), .C1(Op_MY[33]), .Y(n4634) );
AOI222X4TS U2915 ( .A0(n4646), .A1(Op_MY[34]), .B0(n4645), .B1(Op_MY[33]),
.C0(n3240), .C1(Op_MY[32]), .Y(n4625) );
AOI222X4TS U2916 ( .A0(n4646), .A1(Op_MY[29]), .B0(n4645), .B1(n4594), .C0(
n3183), .C1(n4584), .Y(n3890) );
NOR4X1TS U2917 ( .A(Op_MY[46]), .B(Op_MY[47]), .C(Op_MY[48]), .D(Op_MY[49]),
.Y(n5325) );
NOR4X1TS U2918 ( .A(Op_MX[2]), .B(Op_MX[0]), .C(Op_MX[45]), .D(Op_MX[44]),
.Y(n5357) );
NAND2X1TS U2919 ( .A(DP_OP_168J30_122_4811_n4020), .B(n1180), .Y(n1645) );
OR2X2TS U2920 ( .A(DP_OP_168J30_122_4811_n4020), .B(n1180), .Y(n955) );
NAND2X1TS U2921 ( .A(DP_OP_168J30_122_4811_n3894), .B(n1327), .Y(n2077) );
AOI222X4TS U2922 ( .A0(n3862), .A1(n3873), .B0(n3863), .B1(Op_MY[29]), .C0(
n3278), .C1(n4594), .Y(n3309) );
AOI222X1TS U2923 ( .A0(n3874), .A1(n3595), .B0(n3337), .B1(n3593), .C0(n3333), .C1(n3873), .Y(n3868) );
AOI222X1TS U2924 ( .A0(n3874), .A1(n3593), .B0(n3337), .B1(n3873), .C0(n3333), .C1(n3872), .Y(n3875) );
AOI222X1TS U2925 ( .A0(n3414), .A1(n3595), .B0(n3413), .B1(n3593), .C0(n3192), .C1(n3873), .Y(n3409) );
AOI222X1TS U2926 ( .A0(n3874), .A1(n3873), .B0(n3337), .B1(n3872), .C0(n3333), .C1(n4594), .Y(n3850) );
AOI222X1TS U2927 ( .A0(n3414), .A1(n3593), .B0(n3413), .B1(n3873), .C0(n3192), .C1(n3872), .Y(n3411) );
AOI222X4TS U2928 ( .A0(n1128), .A1(n3595), .B0(n1125), .B1(n3593), .C0(n1035), .C1(n3873), .Y(n1112) );
AOI222X1TS U2929 ( .A0(n3414), .A1(n3873), .B0(n3413), .B1(n3872), .C0(n3192), .C1(n4594), .Y(n3415) );
AOI222X1TS U2930 ( .A0(n3199), .A1(n3595), .B0(n3463), .B1(n3593), .C0(n3441), .C1(n3873), .Y(n3202) );
AOI222X1TS U2931 ( .A0(n3519), .A1(n3595), .B0(n3518), .B1(n3593), .C0(n3517), .C1(n3873), .Y(n3512) );
AOI222X4TS U2932 ( .A0(n3199), .A1(n3593), .B0(n3463), .B1(n3873), .C0(n3441), .C1(n3872), .Y(n3206) );
AOI222X4TS U2933 ( .A0(n3519), .A1(n3593), .B0(n3518), .B1(n3873), .C0(n3517), .C1(n3872), .Y(n3514) );
AOI222X4TS U2934 ( .A0(n3598), .A1(n3593), .B0(n3596), .B1(n3873), .C0(n3594), .C1(n3872), .Y(n1081) );
AOI222X1TS U2935 ( .A0(n3199), .A1(n3873), .B0(n3463), .B1(n3872), .C0(n3201), .C1(n3516), .Y(n3208) );
AOI222X4TS U2936 ( .A0(n3519), .A1(n3873), .B0(n3518), .B1(n3872), .C0(n3517), .C1(n3516), .Y(n3520) );
AOI222X1TS U2937 ( .A0(n1521), .A1(n4451), .B0(n1520), .B1(n4443), .C0(n1519), .C1(n4439), .Y(n1445) );
AOI222X1TS U2938 ( .A0(n1521), .A1(n4443), .B0(n1520), .B1(n4439), .C0(n1519), .C1(n4432), .Y(n1449) );
AOI222X4TS U2939 ( .A0(n1521), .A1(n4439), .B0(n1520), .B1(n4432), .C0(n1519), .C1(n4415), .Y(n1453) );
AOI222X4TS U2940 ( .A0(n1521), .A1(n4432), .B0(n1520), .B1(n4415), .C0(n1519), .C1(n4356), .Y(n1457) );
AOI222X4TS U2941 ( .A0(n1521), .A1(n4356), .B0(n1520), .B1(n4309), .C0(n1519), .C1(n4196), .Y(n1502) );
AOI222X4TS U2942 ( .A0(n1521), .A1(n4309), .B0(n1520), .B1(n4196), .C0(n1519), .C1(n4139), .Y(n1509) );
AOI222X4TS U2943 ( .A0(n1521), .A1(n4196), .B0(n1520), .B1(n4139), .C0(n1519), .C1(n4110), .Y(n1513) );
AOI222X4TS U2944 ( .A0(n1521), .A1(n4178), .B0(n1520), .B1(n4131), .C0(n1519), .C1(Op_MY[0]), .Y(n1221) );
AOI222X4TS U2945 ( .A0(n1521), .A1(n4139), .B0(n1520), .B1(n4110), .C0(n1519), .C1(n4178), .Y(n1517) );
AOI222X4TS U2946 ( .A0(n1521), .A1(n4110), .B0(n1520), .B1(n4178), .C0(n1519), .C1(n4131), .Y(n1522) );
AOI222X1TS U2947 ( .A0(n2358), .A1(n4511), .B0(n2356), .B1(n4508), .C0(n2353), .C1(n4509), .Y(n2344) );
AOI222X1TS U2948 ( .A0(n2358), .A1(n4508), .B0(n2356), .B1(n4509), .C0(n2353), .C1(n4493), .Y(n2351) );
AOI222X1TS U2949 ( .A0(n2358), .A1(n4571), .B0(n2356), .B1(n4572), .C0(n2353), .C1(n4562), .Y(n2328) );
AOI222X1TS U2950 ( .A0(n2358), .A1(n4572), .B0(n2356), .B1(n4562), .C0(n2353), .C1(n4510), .Y(n2330) );
AOI222X1TS U2951 ( .A0(n2358), .A1(n2410), .B0(n4659), .B1(n4578), .C0(n2353), .C1(n4571), .Y(n2324) );
BUFX4TS U2952 ( .A(n2314), .Y(n4659) );
AOI222X1TS U2953 ( .A0(n3956), .A1(n4511), .B0(n2434), .B1(n4508), .C0(n2431), .C1(n4509), .Y(n2427) );
AOI222X1TS U2954 ( .A0(n3956), .A1(n4508), .B0(n2434), .B1(n4509), .C0(n2431), .C1(n4493), .Y(n2429) );
AOI222X1TS U2955 ( .A0(n3956), .A1(n4562), .B0(n2434), .B1(n4510), .C0(n2431), .C1(n4511), .Y(n2423) );
AOI222X1TS U2956 ( .A0(n3956), .A1(n4510), .B0(n2434), .B1(n4511), .C0(n2431), .C1(n4508), .Y(n2425) );
AOI222X1TS U2957 ( .A0(n3956), .A1(n4630), .B0(n2434), .B1(n4604), .C0(n2431), .C1(n2410), .Y(n2411) );
AOI222X1TS U2958 ( .A0(n3956), .A1(n4572), .B0(n2434), .B1(n4562), .C0(n2431), .C1(n4510), .Y(n2421) );
BUFX4TS U2959 ( .A(n2403), .Y(n4606) );
AOI222X1TS U2960 ( .A0(n4397), .A1(n4509), .B0(n3922), .B1(n4493), .C0(n3921), .C1(n4477), .Y(n2514) );
AOI222X1TS U2961 ( .A0(n4397), .A1(n4511), .B0(n3922), .B1(n4508), .C0(n3921), .C1(n4509), .Y(n2510) );
AOI222X1TS U2962 ( .A0(n4397), .A1(n4562), .B0(n3922), .B1(n4510), .C0(n3921), .C1(n4511), .Y(n2506) );
AOI222X1TS U2963 ( .A0(n4397), .A1(n4510), .B0(n3922), .B1(n4511), .C0(n3921), .C1(n4508), .Y(n2508) );
AOI222X1TS U2964 ( .A0(n4397), .A1(n4571), .B0(n3922), .B1(n4572), .C0(n3921), .C1(n4562), .Y(n2502) );
AOI222X1TS U2965 ( .A0(n4397), .A1(n4578), .B0(n3922), .B1(n4571), .C0(n3921), .C1(n4572), .Y(n2500) );
AOI222X4TS U2966 ( .A0(n4397), .A1(n4604), .B0(n3922), .B1(n4603), .C0(n3921), .C1(n4578), .Y(n3923) );
BUFX4TS U2967 ( .A(n2492), .Y(n4543) );
BUFX4TS U2968 ( .A(DP_OP_168J30_122_4811_n1864), .Y(n4401) );
AOI222X1TS U2969 ( .A0(n4603), .A1(n4262), .B0(n4380), .B1(n4261), .C0(n4260), .C1(n4231), .Y(n3613) );
AOI222X1TS U2970 ( .A0(n2725), .A1(n4262), .B0(n2728), .B1(n4360), .C0(n4603), .C1(n2690), .Y(n3934) );
AOI222X4TS U2971 ( .A0(n4262), .A1(n4283), .B0(n4360), .B1(n4279), .C0(n2690), .C1(n4303), .Y(n2693) );
AOI222X1TS U2972 ( .A0(n4262), .A1(n4404), .B0(n4360), .B1(n4401), .C0(n2690), .C1(n4283), .Y(n4176) );
AOI222X1TS U2973 ( .A0(n4655), .A1(n4362), .B0(n2725), .B1(n4360), .C0(n2728), .C1(n2690), .Y(n3932) );
BUFX4TS U2974 ( .A(n2668), .Y(n4362) );
AOI222X1TS U2975 ( .A0(n4262), .A1(n4231), .B0(n4360), .B1(
DP_OP_168J30_122_4811_n1861), .C0(n2690), .C1(n4406), .Y(n4201) );
AOI222X1TS U2976 ( .A0(n4262), .A1(DP_OP_168J30_122_4811_n1861), .B0(n4360),
.B1(n4406), .C0(n2690), .C1(n4404), .Y(n4203) );
BUFX6TS U2977 ( .A(DP_OP_168J30_122_4811_n1861), .Y(n4572) );
AOI222X1TS U2978 ( .A0(n4655), .A1(n4332), .B0(n2725), .B1(n4405), .C0(n2728), .C1(n2721), .Y(n2729) );
AOI222X1TS U2979 ( .A0(n2725), .A1(n4332), .B0(n2728), .B1(n4405), .C0(n4603), .C1(n2721), .Y(n2731) );
AOI222X1TS U2980 ( .A0(n2728), .A1(n4332), .B0(n4603), .B1(n4405), .C0(n4380), .C1(n2721), .Y(n4252) );
AOI222X1TS U2981 ( .A0(n4231), .A1(n2702), .B0(DP_OP_168J30_122_4811_n1861),
.B1(n4405), .C0(n2721), .C1(n4406), .Y(n4174) );
NOR2X6TS U2982 ( .A(n2698), .B(n2704), .Y(n2702) );
BUFX4TS U2983 ( .A(n2702), .Y(n4332) );
BUFX4TS U2984 ( .A(n2547), .Y(n4315) );
AOI222X4TS U2985 ( .A0(n2644), .A1(n4283), .B0(n4373), .B1(n4279), .C0(n4372), .C1(n4303), .Y(n2652) );
AOI222X4TS U2986 ( .A0(n2644), .A1(n4279), .B0(n4373), .B1(n4303), .C0(n4372), .C1(n4477), .Y(n2654) );
AOI222X1TS U2987 ( .A0(n2644), .A1(n4510), .B0(n3917), .B1(n4401), .C0(n2646), .C1(n4283), .Y(n4255) );
AOI222X1TS U2988 ( .A0(n2644), .A1(n4380), .B0(n3917), .B1(n4231), .C0(n2646), .C1(DP_OP_168J30_122_4811_n1861), .Y(n3936) );
AOI222X1TS U2989 ( .A0(n4655), .A1(n2644), .B0(n2725), .B1(n3917), .C0(n2646), .C1(n2728), .Y(n4375) );
AOI222X1TS U2990 ( .A0(n3943), .A1(n2725), .B0(n3917), .B1(n2728), .C0(n2646), .C1(n4603), .Y(n4220) );
AOI222X1TS U2991 ( .A0(n3943), .A1(n2728), .B0(n3917), .B1(n4603), .C0(n2646), .C1(n4380), .Y(n4158) );
AOI222X1TS U2992 ( .A0(n2644), .A1(n4603), .B0(n3917), .B1(n4380), .C0(n2646), .C1(n4231), .Y(n3930) );
NOR2X6TS U2993 ( .A(n2622), .B(n2621), .Y(n2644) );
BUFX4TS U2994 ( .A(n2644), .Y(n3943) );
NOR2X6TS U2995 ( .A(n2468), .B(n2467), .Y(n2495) );
BUFX4TS U2996 ( .A(n2495), .Y(n4397) );
NOR4X1TS U2997 ( .A(Op_MY[50]), .B(Op_MY[51]), .C(Op_MY[52]), .D(Op_MY[61]),
.Y(n5324) );
NAND2X1TS U2998 ( .A(FSM_add_overflow_flag), .B(n5527), .Y(n2051) );
AOI222X1TS U2999 ( .A0(n2580), .A1(n4279), .B0(n4381), .B1(n4303), .C0(n4379), .C1(n4477), .Y(n2592) );
AOI222X1TS U3000 ( .A0(n2580), .A1(n4380), .B0(n2574), .B1(n4231), .C0(n2573), .C1(n4572), .Y(n2582) );
AOI222X1TS U3001 ( .A0(n2580), .A1(n4231), .B0(n2574), .B1(n4572), .C0(n2573), .C1(n4562), .Y(n4165) );
AOI222X1TS U3002 ( .A0(n3911), .A1(n2728), .B0(n2574), .B1(n4603), .C0(n2573), .C1(n4578), .Y(n3946) );
AOI222X1TS U3003 ( .A0(n3911), .A1(n4603), .B0(n2574), .B1(n4380), .C0(n2573), .C1(n4571), .Y(n4382) );
NOR2X6TS U3004 ( .A(n2546), .B(n2545), .Y(n2580) );
BUFX4TS U3005 ( .A(n2580), .Y(n3911) );
NAND2X1TS U3006 ( .A(DP_OP_168J30_122_4811_n3958), .B(n1311), .Y(n2111) );
NAND2X2TS U3007 ( .A(DP_OP_168J30_122_4811_n3931), .B(n1314), .Y(n3640) );
NOR2X2TS U3008 ( .A(DP_OP_168J30_122_4811_n3931), .B(n1314), .Y(n3637) );
NOR2X6TS U3009 ( .A(n2385), .B(n2384), .Y(n2406) );
BUFX4TS U3010 ( .A(n2406), .Y(n3956) );
NOR2X6TS U3011 ( .A(n2292), .B(n2291), .Y(n2317) );
BUFX4TS U3012 ( .A(n2317), .Y(n2358) );
NOR2X4TS U3013 ( .A(FS_Module_state_reg[3]), .B(n5320), .Y(n5364) );
AOI222X1TS U3014 ( .A0(n1386), .A1(Op_MY[26]), .B0(n1428), .B1(n3793), .C0(
n1519), .C1(n3792), .Y(n1387) );
AOI222X1TS U3015 ( .A0(n1386), .A1(n3793), .B0(n1428), .B1(n3792), .C0(n1419), .C1(n3784), .Y(n1391) );
AOI222X1TS U3016 ( .A0(n1386), .A1(n3792), .B0(n1428), .B1(n3784), .C0(n1419), .C1(n3778), .Y(n1395) );
AOI222X1TS U3017 ( .A0(n1386), .A1(n3784), .B0(n1520), .B1(n3778), .C0(n1419), .C1(n4459), .Y(n1399) );
AOI222X1TS U3018 ( .A0(n1386), .A1(n3778), .B0(n1520), .B1(n4459), .C0(n1419), .C1(n4458), .Y(n1403) );
AOI222X1TS U3019 ( .A0(n1386), .A1(n4459), .B0(n1520), .B1(n4458), .C0(n1419), .C1(n3061), .Y(n1407) );
AOI222X1TS U3020 ( .A0(n1386), .A1(n4458), .B0(n1520), .B1(n3061), .C0(n1419), .C1(n4470), .Y(n1411) );
AOI222X1TS U3021 ( .A0(n1386), .A1(n3061), .B0(n1428), .B1(n4470), .C0(n1419), .C1(n4516), .Y(n1415) );
AOI222X1TS U3022 ( .A0(n1386), .A1(n4516), .B0(n1428), .B1(n4514), .C0(n1519), .C1(n4463), .Y(n1424) );
AOI222X1TS U3023 ( .A0(n1386), .A1(n4514), .B0(n1428), .B1(n4463), .C0(n1519), .C1(n4453), .Y(n1429) );
AOI222X1TS U3024 ( .A0(n1521), .A1(n4463), .B0(n1520), .B1(n4453), .C0(n1519), .C1(n4452), .Y(n1433) );
AOI222X1TS U3025 ( .A0(n1521), .A1(n4453), .B0(n1520), .B1(n4452), .C0(n1519), .C1(n4451), .Y(n1437) );
AOI222X1TS U3026 ( .A0(n1386), .A1(n4452), .B0(n1520), .B1(n4451), .C0(n1519), .C1(n4443), .Y(n1441) );
BUFX4TS U3027 ( .A(n1386), .Y(n1521) );
CLKMX2X2TS U3028 ( .A(P_Sgf[84]), .B(n2052), .S0(n5281), .Y(n505) );
XNOR2X2TS U3029 ( .A(Op_MX[35]), .B(Op_MX[36]), .Y(n1289) );
XNOR2X2TS U3030 ( .A(Op_MX[38]), .B(Op_MX[39]), .Y(n1295) );
OAI211XLTS U3031 ( .A0(Sgf_normalized_result[48]), .A1(n5450), .B0(n5455),
.C0(n5452), .Y(n5451) );
OAI211XLTS U3032 ( .A0(Sgf_normalized_result[46]), .A1(n5447), .B0(n5455),
.C0(n5446), .Y(n5448) );
OAI211XLTS U3033 ( .A0(Sgf_normalized_result[44]), .A1(n5444), .B0(n5455),
.C0(n5443), .Y(n5445) );
OAI211XLTS U3034 ( .A0(Sgf_normalized_result[42]), .A1(n5441), .B0(n5455),
.C0(n5440), .Y(n5442) );
OAI211XLTS U3035 ( .A0(Sgf_normalized_result[38]), .A1(n5434), .B0(n5455),
.C0(n5433), .Y(n5435) );
NOR2X2TS U3036 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n1268) );
AOI222X1TS U3037 ( .A0(n3874), .A1(n3872), .B0(n3342), .B1(n4594), .C0(n3336), .C1(n4584), .Y(n3854) );
AOI222X1TS U3038 ( .A0(n3874), .A1(n3584), .B0(n3342), .B1(n3587), .C0(n3333), .C1(n3590), .Y(n3353) );
AOI222X1TS U3039 ( .A0(n3874), .A1(n3581), .B0(n3342), .B1(n3584), .C0(n3333), .C1(n3587), .Y(n3351) );
NOR2BX4TS U3040 ( .AN(n1301), .B(n1299), .Y(n3342) );
INVX4TS U3041 ( .A(n3681), .Y(n821) );
OAI21X1TS U3042 ( .A0(n821), .A1(n2090), .B0(n2089), .Y(n2093) );
OAI21X1TS U3043 ( .A0(n821), .A1(n2096), .B0(n2095), .Y(n2099) );
OAI21X1TS U3044 ( .A0(n821), .A1(n3677), .B0(n3678), .Y(n2114) );
NAND2X1TS U3045 ( .A(Op_MX[31]), .B(Op_MX[4]), .Y(n1250) );
NOR4X1TS U3046 ( .A(Op_MX[31]), .B(Op_MX[30]), .C(Op_MX[29]), .D(Op_MX[28]),
.Y(n5353) );
XNOR2X1TS U3047 ( .A(n959), .B(Op_MX[25]), .Y(n2164) );
NOR2X2TS U3048 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1237) );
NAND2X1TS U3049 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1238) );
NOR2X1TS U3050 ( .A(Op_MX[37]), .B(Op_MX[10]), .Y(n2519) );
NOR4BX1TS U3051 ( .AN(n5326), .B(Op_MY[26]), .C(Op_MY[27]), .D(Op_MY[53]),
.Y(n5329) );
NAND2X1TS U3052 ( .A(Op_MX[18]), .B(Op_MX[45]), .Y(n2363) );
NOR2X2TS U3053 ( .A(Op_MX[40]), .B(Op_MX[13]), .Y(n2531) );
NAND2X1TS U3054 ( .A(Op_MX[40]), .B(Op_MX[13]), .Y(n2532) );
NAND2X1TS U3055 ( .A(Op_MX[46]), .B(Op_MX[19]), .Y(n2372) );
NAND2X1TS U3056 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2271) );
NAND2X1TS U3057 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n2155) );
NOR4X1TS U3058 ( .A(Op_MX[50]), .B(Op_MX[51]), .C(Op_MX[62]), .D(Op_MX[61]),
.Y(n5344) );
XNOR2X2TS U3059 ( .A(Op_MX[32]), .B(Op_MX[33]), .Y(n1062) );
OR2X1TS U3060 ( .A(n4892), .B(n4891), .Y(n822) );
CLKAND2X2TS U3061 ( .A(n822), .B(n4893), .Y(n823) );
OR2X2TS U3062 ( .A(DP_OP_168J30_122_4811_n2318), .B(
DP_OP_168J30_122_4811_n2328), .Y(n826) );
OR2X2TS U3063 ( .A(DP_OP_168J30_122_4811_n2354), .B(
DP_OP_168J30_122_4811_n2365), .Y(n828) );
OR2X1TS U3064 ( .A(DP_OP_168J30_122_4811_n2366), .B(
DP_OP_168J30_122_4811_n2377), .Y(n829) );
OR2X1TS U3065 ( .A(DP_OP_168J30_122_4811_n2390), .B(
DP_OP_168J30_122_4811_n2401), .Y(n830) );
OR2X1TS U3066 ( .A(n4574), .B(n1905), .Y(n831) );
OR2X1TS U3067 ( .A(n3723), .B(n1908), .Y(n832) );
OR2X1TS U3068 ( .A(DP_OP_168J30_122_4811_n2414), .B(n1570), .Y(n833) );
AOI22X1TS U3069 ( .A0(n4433), .A1(Op_MY[0]), .B0(n3771), .B1(n4131), .Y(n834) );
CLKXOR2X4TS U3070 ( .A(n2169), .B(n2168), .Y(n835) );
XNOR2X4TS U3071 ( .A(n2179), .B(n2178), .Y(n836) );
AO21X1TS U3072 ( .A0(n889), .A1(n4848), .B0(n1934), .Y(n837) );
XNOR2X4TS U3073 ( .A(n2186), .B(n2185), .Y(n838) );
XNOR2X4TS U3074 ( .A(n2298), .B(n930), .Y(n839) );
XNOR2X4TS U3075 ( .A(n2198), .B(n929), .Y(n840) );
MXI2X1TS U3076 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n4806), .Y(n842) );
MXI2X1TS U3077 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n4806), .Y(n843) );
AO21X4TS U3078 ( .A0(n904), .A1(n4855), .B0(n1924), .Y(n844) );
AO21X2TS U3079 ( .A0(n893), .A1(n4922), .B0(n1914), .Y(n846) );
AO21X1TS U3080 ( .A0(n873), .A1(n1976), .B0(n1141), .Y(n847) );
AOI22X1TS U3081 ( .A0(n3079), .A1(Op_MY[0]), .B0(n4025), .B1(n4131), .Y(n848) );
NAND2X1TS U3082 ( .A(n3124), .B(n4081), .Y(n850) );
AOI22X1TS U3083 ( .A0(n4416), .A1(Op_MY[0]), .B0(n3124), .B1(n4131), .Y(n851) );
BUFX6TS U3084 ( .A(Op_MX[23]), .Y(n2930) );
BUFX6TS U3085 ( .A(Op_MX[20]), .Y(n4296) );
BUFX6TS U3086 ( .A(Op_MX[11]), .Y(n4419) );
BUFX6TS U3087 ( .A(Op_MX[8]), .Y(n4456) );
BUFX6TS U3088 ( .A(Op_MX[14]), .Y(n4423) );
OA21X1TS U3089 ( .A0(n4534), .A1(n4537), .B0(n4535), .Y(n860) );
BUFX6TS U3090 ( .A(Op_MX[17]), .Y(n4670) );
AO21X1TS U3091 ( .A0(n922), .A1(n1716), .B0(n1158), .Y(n862) );
OR2X1TS U3092 ( .A(n3722), .B(n1910), .Y(n863) );
INVX2TS U3093 ( .A(n1202), .Y(n4812) );
NAND2X1TS U3094 ( .A(n880), .B(n4338), .Y(n1202) );
OA21X2TS U3095 ( .A0(n4425), .A1(n4428), .B0(n4426), .Y(n865) );
OR2X1TS U3096 ( .A(n1143), .B(n1142), .Y(n866) );
OR2X1TS U3097 ( .A(n1535), .B(n1534), .Y(n867) );
OR2X1TS U3098 ( .A(n1135), .B(n1134), .Y(n868) );
OR2X1TS U3099 ( .A(DP_OP_168J30_122_4811_n2439), .B(n1567), .Y(n869) );
OR2X1TS U3100 ( .A(DP_OP_168J30_122_4811_n2465), .B(n1564), .Y(n871) );
OR2X1TS U3101 ( .A(DP_OP_168J30_122_4811_n2552), .B(n1551), .Y(n876) );
OR2X1TS U3102 ( .A(DP_OP_168J30_122_4811_n2566), .B(n1548), .Y(n877) );
OR2X1TS U3103 ( .A(DP_OP_168J30_122_4811_n2578), .B(n1545), .Y(n878) );
NAND2BX1TS U3104 ( .AN(n1289), .B(n1288), .Y(n3198) );
BUFX6TS U3105 ( .A(n3198), .Y(n3446) );
BUFX6TS U3106 ( .A(n2643), .Y(n3919) );
BUFX4TS U3107 ( .A(Op_MX[5]), .Y(n4657) );
OR2X1TS U3108 ( .A(n1201), .B(n1200), .Y(n880) );
BUFX6TS U3109 ( .A(Op_MX[47]), .Y(n3867) );
AND3X1TS U3110 ( .A(n1307), .B(n1305), .C(n1306), .Y(n3281) );
BUFX6TS U3111 ( .A(n3281), .Y(n3278) );
NAND2BX2TS U3112 ( .AN(n1307), .B(n1306), .Y(n3286) );
BUFX6TS U3113 ( .A(n3286), .Y(n3284) );
INVX6TS U3114 ( .A(rst), .Y(n286) );
OR2X1TS U3115 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n883) );
BUFX6TS U3116 ( .A(n2700), .Y(n4410) );
BUFX6TS U3117 ( .A(n2695), .Y(n4408) );
OR2X1TS U3118 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n887) );
OR2X1TS U3119 ( .A(n3707), .B(n1933), .Y(n889) );
OR2X1TS U3120 ( .A(n3708), .B(n1935), .Y(n890) );
NAND2X1TS U3121 ( .A(n887), .B(n1210), .Y(n1206) );
OR2X1TS U3122 ( .A(n1193), .B(n1192), .Y(n892) );
OR3X4TS U3123 ( .A(underflow_flag), .B(overflow_flag), .C(n5465), .Y(n5467)
);
INVX2TS U3124 ( .A(n1195), .Y(n1999) );
NAND2X1TS U3125 ( .A(n892), .B(n1194), .Y(n1195) );
OR2X1TS U3126 ( .A(n3726), .B(n1913), .Y(n893) );
OR2X1TS U3127 ( .A(n3725), .B(n1915), .Y(n894) );
OR2X1TS U3128 ( .A(DP_OP_168J30_122_4811_n4169), .B(n1153), .Y(n895) );
OR2X1TS U3129 ( .A(DP_OP_168J30_122_4811_n2536), .B(n1554), .Y(n897) );
OR2X1TS U3130 ( .A(DP_OP_168J30_122_4811_n2518), .B(n1557), .Y(n898) );
OR2X1TS U3131 ( .A(DP_OP_168J30_122_4811_n2498), .B(n1560), .Y(n899) );
OR2X1TS U3132 ( .A(DP_OP_168J30_122_4811_n4183), .B(n1150), .Y(n901) );
BUFX6TS U3133 ( .A(n2661), .Y(n4264) );
BUFX6TS U3134 ( .A(n1376), .Y(n1523) );
OR2X1TS U3135 ( .A(n3720), .B(n1923), .Y(n904) );
OR2X1TS U3136 ( .A(n3721), .B(n1925), .Y(n905) );
OR2X1TS U3137 ( .A(n3719), .B(n1928), .Y(n906) );
OR2X1TS U3138 ( .A(n3710), .B(n1930), .Y(n907) );
OR2X1TS U3139 ( .A(n3706), .B(n1938), .Y(n908) );
OR2X1TS U3140 ( .A(n3704), .B(n1940), .Y(n909) );
AND3X1TS U3141 ( .A(n2805), .B(n2804), .C(n2803), .Y(n2877) );
BUFX6TS U3142 ( .A(n2877), .Y(n2907) );
BUFX4TS U3143 ( .A(n2876), .Y(n2929) );
NAND2BX2TS U3144 ( .AN(n2765), .B(n2764), .Y(n2784) );
BUFX6TS U3145 ( .A(n2784), .Y(n2852) );
AOI22X1TS U3146 ( .A0(n4392), .A1(n4081), .B0(n4067), .B1(n4131), .Y(n911)
);
AND3X1TS U3147 ( .A(n2997), .B(n2992), .C(n2996), .Y(n3023) );
BUFX6TS U3148 ( .A(n3023), .Y(n3020) );
NAND2BX2TS U3149 ( .AN(n2997), .B(n2996), .Y(n3028) );
BUFX6TS U3150 ( .A(n3028), .Y(n3026) );
OR2X2TS U3151 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n913) );
AND3X1TS U3152 ( .A(n1461), .B(n1460), .C(n1459), .Y(n3130) );
BUFX6TS U3153 ( .A(n3130), .Y(n4469) );
BUFX6TS U3154 ( .A(Op_MX[44]), .Y(n3980) );
BUFX6TS U3155 ( .A(n2489), .Y(DP_OP_168J30_122_4811_n56) );
AND3X1TS U3156 ( .A(n3049), .B(n3044), .C(n3048), .Y(n3075) );
BUFX6TS U3157 ( .A(n3075), .Y(n4513) );
BUFX4TS U3158 ( .A(n3078), .Y(n4422) );
NAND2BX2TS U3159 ( .AN(n1334), .B(n1333), .Y(n3245) );
BUFX6TS U3160 ( .A(n3245), .Y(n3243) );
BUFX6TS U3161 ( .A(n3336), .Y(n3333) );
NAND2BX2TS U3162 ( .AN(n1301), .B(n1300), .Y(n3341) );
BUFX6TS U3163 ( .A(n3341), .Y(n3339) );
CLKXOR2X4TS U3164 ( .A(n2233), .B(n1627), .Y(n916) );
BUFX4TS U3165 ( .A(n916), .Y(n4654) );
INVX6TS U3166 ( .A(n917), .Y(n2830) );
BUFX4TS U3167 ( .A(Op_MX[26]), .Y(n2848) );
OR2X1TS U3168 ( .A(n3727), .B(n1918), .Y(n918) );
OR2X1TS U3169 ( .A(n3724), .B(n1920), .Y(n919) );
OA21X4TS U3170 ( .A0(n1693), .A1(n1696), .B0(n1694), .Y(n920) );
OR2X1TS U3171 ( .A(DP_OP_168J30_122_4811_n4146), .B(n1157), .Y(n922) );
OR2X1TS U3172 ( .A(DP_OP_168J30_122_4811_n4138), .B(n1159), .Y(n923) );
AND3X1TS U3173 ( .A(n1474), .B(n1473), .C(n1472), .Y(n1575) );
BUFX4TS U3174 ( .A(n1574), .Y(n4435) );
AND3X1TS U3175 ( .A(n3089), .B(n3084), .C(n3088), .Y(n3116) );
BUFX6TS U3176 ( .A(n3116), .Y(n3112) );
NAND2BX2TS U3177 ( .AN(n3089), .B(n3088), .Y(n3120) );
BUFX6TS U3178 ( .A(n3120), .Y(n3118) );
AND3X1TS U3179 ( .A(n2939), .B(n2934), .C(n2938), .Y(n2965) );
BUFX6TS U3180 ( .A(n2965), .Y(n2962) );
OR2X2TS U3181 ( .A(n2000), .B(n1999), .Y(n924) );
OR2X1TS U3182 ( .A(DP_OP_168J30_122_4811_n1867), .B(n4512), .Y(n925) );
CLKXOR2X4TS U3183 ( .A(n2343), .B(n2342), .Y(n926) );
CLKXOR2X4TS U3184 ( .A(n2205), .B(n2204), .Y(n928) );
OA21X1TS U3185 ( .A0(n2195), .A1(n929), .B0(n2196), .Y(n930) );
XNOR2X4TS U3186 ( .A(n2286), .B(n2285), .Y(n932) );
OR2X2TS U3187 ( .A(n2286), .B(n2285), .Y(n933) );
BUFX6TS U3188 ( .A(n5470), .Y(n5468) );
BUFX4TS U3189 ( .A(n5374), .Y(n5460) );
BUFX4TS U3190 ( .A(n5374), .Y(n5449) );
NAND4X1TS U3191 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]),
.C(n5474), .D(n5550), .Y(n4693) );
BUFX4TS U3192 ( .A(n4693), .Y(n5374) );
OR2X2TS U3193 ( .A(DP_OP_168J30_122_4811_n3894), .B(n1327), .Y(n938) );
OR2X2TS U3194 ( .A(DP_OP_168J30_122_4811_n3898), .B(
DP_OP_168J30_122_4811_n3904), .Y(n939) );
OR2X2TS U3195 ( .A(DP_OP_168J30_122_4811_n3916), .B(
DP_OP_168J30_122_4811_n3923), .Y(n941) );
XOR2X1TS U3196 ( .A(n821), .B(n3680), .Y(n4705) );
CLKXOR2X2TS U3197 ( .A(n3647), .B(n3646), .Y(n942) );
INVX2TS U3198 ( .A(n5278), .Y(n5279) );
OR2X2TS U3199 ( .A(n2014), .B(n4276), .Y(n946) );
AO21X4TS U3200 ( .A0(n734), .A1(n5149), .B0(n2041), .Y(n953) );
OA21X4TS U3201 ( .A0(n5162), .A1(n5165), .B0(n5163), .Y(n957) );
BUFX6TS U3202 ( .A(n2491), .Y(n4546) );
BUFX6TS U3203 ( .A(n2402), .Y(n4610) );
BUFX6TS U3204 ( .A(n2311), .Y(n2361) );
BUFX6TS U3205 ( .A(n2235), .Y(n4011) );
BUFX6TS U3206 ( .A(n4671), .Y(n5530) );
BUFX6TS U3207 ( .A(n4671), .Y(n5528) );
BUFX4TS U3208 ( .A(n4671), .Y(n5531) );
BUFX4TS U3209 ( .A(n5540), .Y(n5541) );
BUFX6TS U3210 ( .A(n5551), .Y(n5543) );
BUFX6TS U3211 ( .A(n5539), .Y(n5542) );
BUFX4TS U3212 ( .A(n5529), .Y(n5536) );
BUFX4TS U3213 ( .A(n5551), .Y(n4671) );
BUFX6TS U3214 ( .A(n5534), .Y(n5540) );
BUFX6TS U3215 ( .A(n5528), .Y(n5539) );
BUFX4TS U3216 ( .A(n4671), .Y(n5535) );
BUFX4TS U3217 ( .A(n4671), .Y(n5532) );
BUFX4TS U3218 ( .A(n4671), .Y(n5534) );
BUFX4TS U3219 ( .A(n4671), .Y(n5537) );
INVX6TS U3220 ( .A(n4947), .Y(n4948) );
INVX6TS U3221 ( .A(n4947), .Y(n4806) );
CLKINVX6TS U3222 ( .A(n4947), .Y(n4807) );
BUFX6TS U3223 ( .A(n4748), .Y(n5240) );
NAND2X1TS U3224 ( .A(Op_MX[42]), .B(Op_MX[15]), .Y(n2448) );
NAND2X1TS U3225 ( .A(Op_MX[37]), .B(Op_MX[10]), .Y(n2609) );
NAND2X1TS U3226 ( .A(n2373), .B(n2372), .Y(n2374) );
INVX2TS U3227 ( .A(n2155), .Y(n981) );
OAI21XLTS U3228 ( .A0(n2491), .A1(n4221), .B0(n2498), .Y(n2499) );
OAI21XLTS U3229 ( .A0(n4546), .A1(n4366), .B0(n2485), .Y(n2486) );
BUFX4TS U3230 ( .A(n3029), .Y(n3024) );
BUFX4TS U3231 ( .A(n3189), .Y(n3416) );
NAND2X1TS U3232 ( .A(n4469), .B(n3152), .Y(n3131) );
NAND2X1TS U3233 ( .A(n3112), .B(n3152), .Y(n3082) );
OAI21XLTS U3234 ( .A0(n4449), .A1(n2968), .B0(n2952), .Y(n2953) );
INVX2TS U3235 ( .A(n2445), .Y(n2453) );
OAI21XLTS U3236 ( .A0(n3919), .A1(n4409), .B0(n3615), .Y(n3616) );
BUFX4TS U3237 ( .A(n2970), .Y(n2968) );
NAND2X1TS U3238 ( .A(n2347), .B(n2346), .Y(n2349) );
OAI21XLTS U3239 ( .A0(n2402), .A1(n4409), .B0(n2421), .Y(n2422) );
OAI21XLTS U3240 ( .A0(n4635), .A1(n3446), .B0(n3459), .Y(n3460) );
OAI21XLTS U3241 ( .A0(n4626), .A1(n3416), .B0(n3405), .Y(n3406) );
OAI21XLTS U3242 ( .A0(n836), .A1(n4408), .B0(n2707), .Y(n2708) );
OAI21XLTS U3243 ( .A0(n2360), .A1(n4498), .B0(n2338), .Y(n2339) );
OAI21XLTS U3244 ( .A0(n4635), .A1(n3600), .B0(n3588), .Y(n3589) );
OAI21XLTS U3245 ( .A0(n2235), .A1(n4376), .B0(n2244), .Y(n2245) );
INVX2TS U3246 ( .A(n1102), .Y(n4626) );
INVX2TS U3247 ( .A(n1109), .Y(n4644) );
OAI21XLTS U3248 ( .A0(n3786), .A1(n4474), .B0(n3140), .Y(n3141) );
INVX2TS U3249 ( .A(n2263), .Y(n4212) );
OAI21XLTS U3250 ( .A0(n3786), .A1(n3078), .B0(n3052), .Y(n3053) );
NAND2X1TS U3251 ( .A(n2453), .B(n2452), .Y(n2454) );
INVX2TS U3252 ( .A(n2221), .Y(n4322) );
CLKAND2X2TS U3253 ( .A(n2830), .B(Op_MY[16]), .Y(DP_OP_168J30_122_4811_n2614) );
OAI21XLTS U3254 ( .A0(n4366), .A1(n4408), .B0(n4333), .Y(n4334) );
XNOR2X1TS U3255 ( .A(n2191), .B(n2190), .Y(n2192) );
BUFX4TS U3256 ( .A(n2243), .Y(n4501) );
OAI21XLTS U3257 ( .A0(n3571), .A1(n3600), .B0(n3570), .Y(n3572) );
OAI21XLTS U3258 ( .A0(n3740), .A1(n3521), .B0(n3493), .Y(n3494) );
OAI21XLTS U3259 ( .A0(n3767), .A1(n1174), .B0(n3538), .Y(n3539) );
OAI21XLTS U3260 ( .A0(n3531), .A1(n1174), .B0(n3530), .Y(n3532) );
BUFX3TS U3261 ( .A(n3192), .Y(n3386) );
INVX2TS U3262 ( .A(n1022), .Y(n3557) );
INVX2TS U3263 ( .A(n1017), .Y(n3552) );
OAI21XLTS U3264 ( .A0(n932), .A1(n4408), .B0(n4229), .Y(n4230) );
OAI21XLTS U3265 ( .A0(n2235), .A1(n4498), .B0(n4497), .Y(n4499) );
OAI21XLTS U3266 ( .A0(n3028), .A1(n859), .B0(n4063), .Y(n4064) );
OAI21XLTS U3267 ( .A0(n4141), .A1(n2970), .B0(n2988), .Y(n2989) );
BUFX4TS U3268 ( .A(n3133), .Y(n4471) );
AOI21X1TS U3269 ( .A0(n1267), .A1(n1251), .B0(n1244), .Y(n1249) );
NAND2X1TS U3270 ( .A(n1257), .B(n2597), .Y(n1258) );
OAI21XLTS U3271 ( .A0(n4212), .A1(n4317), .B0(n4190), .Y(n4191) );
OAI21XLTS U3272 ( .A0(n4221), .A1(n4408), .B0(n2731), .Y(n2732) );
ADDHXLTS U3273 ( .A(n4251), .B(n4250), .CO(n4207), .S(n4259) );
OAI21XLTS U3274 ( .A0(n3835), .A1(n4408), .B0(n2722), .Y(n2723) );
ADDHXLTS U3275 ( .A(n4226), .B(n4225), .CO(DP_OP_168J30_122_4811_n596), .S(
DP_OP_168J30_122_4811_n597) );
BUFX4TS U3276 ( .A(n2733), .Y(n4317) );
OAI21XLTS U3277 ( .A0(n4079), .A1(n3129), .B0(n1462), .Y(n1463) );
BUFX4TS U3278 ( .A(n3129), .Y(n4474) );
OAI21XLTS U3279 ( .A0(n4408), .A1(n4495), .B0(n4185), .Y(n4186) );
OAI21XLTS U3280 ( .A0(n4546), .A1(n1226), .B0(n753), .Y(n2516) );
NAND2X1TS U3281 ( .A(n1596), .B(n1809), .Y(n1598) );
INVX2TS U3282 ( .A(n1985), .Y(n1136) );
INVX2TS U3283 ( .A(n1989), .Y(n1991) );
CMPR42X1TS U3284 ( .A(DP_OP_168J30_122_4811_n531), .B(
DP_OP_168J30_122_4811_n516), .C(DP_OP_168J30_122_4811_n1215), .D(
DP_OP_168J30_122_4811_n527), .ICI(DP_OP_168J30_122_4811_n795), .S(
DP_OP_168J30_122_4811_n513), .ICO(DP_OP_168J30_122_4811_n511), .CO(
DP_OP_168J30_122_4811_n512) );
INVX2TS U3285 ( .A(n1954), .Y(n1151) );
BUFX6TS U3286 ( .A(Op_MY[2]), .Y(n4178) );
OAI21XLTS U3287 ( .A0(n4441), .A1(n4435), .B0(n3848), .Y(n3849) );
BUFX4TS U3288 ( .A(Op_MX[5]), .Y(n4437) );
OAI21XLTS U3289 ( .A0(n3801), .A1(n4435), .B0(n3800), .Y(n3802) );
OAI21XLTS U3290 ( .A0(n4467), .A1(n1574), .B0(n3803), .Y(n3804) );
OAI21XLTS U3291 ( .A0(n4519), .A1(n4474), .B0(n4464), .Y(n4465) );
BUFX6TS U3292 ( .A(n3769), .Y(n4668) );
INVX2TS U3293 ( .A(n1876), .Y(n1878) );
NAND2X2TS U3294 ( .A(DP_OP_168J30_122_4811_n2287), .B(
DP_OP_168J30_122_4811_n2295), .Y(n1830) );
NAND2X1TS U3295 ( .A(DP_OP_168J30_122_4811_n2225), .B(
DP_OP_168J30_122_4811_n2231), .Y(n1775) );
NAND2X1TS U3296 ( .A(DP_OP_168J30_122_4811_n4154), .B(n1156), .Y(n1720) );
NAND2X1TS U3297 ( .A(DP_OP_168J30_122_4811_n4128), .B(n1161), .Y(n1707) );
INVX2TS U3298 ( .A(n1699), .Y(n1165) );
OAI21X1TS U3299 ( .A0(n3666), .A1(n3672), .B0(n3673), .Y(n1312) );
INVX2TS U3300 ( .A(n2077), .Y(n1328) );
NAND2X1TS U3301 ( .A(n1203), .B(n1204), .Y(n1992) );
INVX2TS U3302 ( .A(n5000), .Y(n2015) );
INVX2TS U3303 ( .A(n5034), .Y(n2009) );
INVX2TS U3304 ( .A(n1861), .Y(n1869) );
NAND2X1TS U3305 ( .A(n824), .B(n1841), .Y(n1842) );
NAND2X1TS U3306 ( .A(n1812), .B(n1811), .Y(n1813) );
NAND2X1TS U3307 ( .A(n874), .B(n1775), .Y(n1776) );
NAND2X1TS U3308 ( .A(DP_OP_168J30_122_4811_n3966), .B(
DP_OP_168J30_122_4811_n3976), .Y(n3678) );
INVX2TS U3309 ( .A(n3639), .Y(n2097) );
INVX2TS U3310 ( .A(n2070), .Y(n1331) );
CLKXOR2X2TS U3311 ( .A(n1728), .B(n1727), .Y(n3636) );
CLKXOR2X2TS U3312 ( .A(n1828), .B(n1827), .Y(n4575) );
CLKXOR2X2TS U3313 ( .A(n1691), .B(n920), .Y(n3612) );
NAND2X1TS U3314 ( .A(n3679), .B(n3678), .Y(n3680) );
NAND2X1TS U3315 ( .A(n941), .B(n3645), .Y(n3646) );
NAND2X1TS U3316 ( .A(n935), .B(n2054), .Y(n2055) );
INVX2TS U3317 ( .A(n5038), .Y(n5041) );
INVX2TS U3318 ( .A(n4972), .Y(n4975) );
INVX2TS U3319 ( .A(n5005), .Y(n5006) );
NAND2X1TS U3320 ( .A(n1538), .B(n1537), .Y(n4426) );
INVX2TS U3321 ( .A(n3814), .Y(n3816) );
NAND2X1TS U3322 ( .A(DP_OP_168J30_122_4811_n2536), .B(n1554), .Y(n4526) );
NAND2X1TS U3323 ( .A(DP_OP_168J30_122_4811_n2487), .B(n1562), .Y(n4535) );
NAND2X1TS U3324 ( .A(DP_OP_168J30_122_4811_n2426), .B(n1569), .Y(n3713) );
INVX2TS U3325 ( .A(n5241), .Y(n5242) );
NOR3X2TS U3326 ( .A(n5474), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[3]), .Y(n4743) );
NAND2X1TS U3327 ( .A(n946), .B(n5000), .Y(n5001) );
INVX6TS U3328 ( .A(n5099), .Y(n5305) );
INVX2TS U3329 ( .A(n1223), .Y(n4337) );
NAND2X1TS U3330 ( .A(n4482), .B(n4481), .Y(n4484) );
AOI21X2TS U3331 ( .A0(n897), .A1(n4527), .B0(n1555), .Y(n3693) );
NAND2X1TS U3332 ( .A(n4568), .B(n4567), .Y(n4570) );
NAND2X1TS U3333 ( .A(n863), .B(n4912), .Y(n4913) );
OAI21X2TS U3334 ( .A0(n4941), .A1(n4944), .B0(n4942), .Y(n4855) );
NAND2X1TS U3335 ( .A(n890), .B(n4851), .Y(n4852) );
NAND2X1TS U3336 ( .A(n855), .B(n5156), .Y(n5157) );
INVX2TS U3337 ( .A(n4705), .Y(n5212) );
CLKINVX6TS U3338 ( .A(n4947), .Y(n4810) );
XOR2X1TS U3339 ( .A(n4996), .B(n4995), .Y(n4997) );
BUFX4TS U3340 ( .A(n5465), .Y(n5470) );
BUFX3TS U3341 ( .A(n4748), .Y(n5147) );
BUFX3TS U3342 ( .A(n4748), .Y(n5307) );
XNOR2X1TS U3343 ( .A(n4507), .B(n4506), .Y(n4876) );
XNOR2X1TS U3344 ( .A(n4859), .B(n844), .Y(n4860) );
XOR2X1TS U3345 ( .A(n5104), .B(n736), .Y(n5105) );
OAI21XLTS U3346 ( .A0(n5461), .A1(Sgf_normalized_result[52]), .B0(n5463),
.Y(n5462) );
OAI211XLTS U3347 ( .A0(Sgf_normalized_result[12]), .A1(n5388), .B0(n5455),
.C0(n5390), .Y(n5389) );
OAI211XLTS U3348 ( .A0(Sgf_normalized_result[24]), .A1(n5413), .B0(n5464),
.C0(n5412), .Y(n5414) );
OAI211XLTS U3349 ( .A0(Sgf_normalized_result[40]), .A1(n5436), .B0(n5455),
.C0(n5438), .Y(n5437) );
CLKINVX6TS U3350 ( .A(n4947), .Y(n4808) );
OAI211XLTS U3351 ( .A0(n5315), .A1(n5524), .B0(n4789), .C0(n5251), .Y(n714)
);
OAI211XLTS U3352 ( .A0(n5369), .A1(n5367), .B0(n4787), .C0(n4786), .Y(n404)
);
OAI211XLTS U3353 ( .A0(n4744), .A1(n5512), .B0(n4759), .C0(n4758), .Y(n354)
);
OR2X1TS U3354 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
NOR2XLTS U3355 ( .A(n5494), .B(FS_Module_state_reg[2]), .Y(n960) );
NOR2X2TS U3356 ( .A(FS_Module_state_reg[3]), .B(n5527), .Y(n4672) );
BUFX6TS U3357 ( .A(Op_MX[2]), .Y(DP_OP_168J30_122_4811_n2003) );
NOR2X2TS U3358 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1235) );
NOR2X1TS U3359 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1207) );
NAND2X1TS U3360 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1210) );
CLKXOR2X2TS U3361 ( .A(Op_MX[28]), .B(Op_MX[29]), .Y(n986) );
BUFX3TS U3362 ( .A(n1035), .Y(n3602) );
BUFX3TS U3363 ( .A(Op_MY[51]), .Y(n3529) );
NOR2BX1TS U3364 ( .AN(n888), .B(n934), .Y(n1005) );
BUFX6TS U3365 ( .A(n1005), .Y(n1125) );
AOI21X1TS U3366 ( .A0(n3602), .A1(n3529), .B0(n1125), .Y(n983) );
XOR2X1TS U3367 ( .A(n984), .B(n4652), .Y(n1172) );
CLKXOR2X4TS U3368 ( .A(n985), .B(Op_MY[51]), .Y(n1359) );
BUFX3TS U3369 ( .A(Op_MY[50]), .Y(n3533) );
AO21XLTS U3370 ( .A0(n1125), .A1(n3529), .B0(n1128), .Y(n988) );
AOI21X1TS U3371 ( .A0(n3602), .A1(n3533), .B0(n988), .Y(n989) );
XOR2X1TS U3372 ( .A(n990), .B(n4652), .Y(n1171) );
BUFX6TS U3373 ( .A(n3604), .Y(n1130) );
BUFX3TS U3374 ( .A(Op_MY[49]), .Y(n3537) );
XOR2X1TS U3375 ( .A(n994), .B(n4652), .Y(n1170) );
BUFX3TS U3376 ( .A(Op_MY[48]), .Y(n3540) );
XOR2X1TS U3377 ( .A(n998), .B(n4652), .Y(n1168) );
BUFX3TS U3378 ( .A(Op_MY[47]), .Y(n3543) );
OAI21X1TS U3379 ( .A0(n3767), .A1(n1130), .B0(n1001), .Y(n1002) );
XOR2X1TS U3380 ( .A(n1002), .B(n4652), .Y(n1167) );
BUFX3TS U3381 ( .A(Op_MY[46]), .Y(n3546) );
XOR2X1TS U3382 ( .A(n1007), .B(Op_MX[29]), .Y(n1166) );
BUFX3TS U3383 ( .A(Op_MY[45]), .Y(n3550) );
XOR2X1TS U3384 ( .A(n1011), .B(Op_MX[29]), .Y(n1164) );
BUFX4TS U3385 ( .A(Op_MY[44]), .Y(n3555) );
XOR2X1TS U3386 ( .A(n1015), .B(Op_MX[29]), .Y(n1162) );
BUFX4TS U3387 ( .A(Op_MY[43]), .Y(n3559) );
XOR2X1TS U3388 ( .A(n1020), .B(Op_MX[29]), .Y(n1161) );
NOR2X1TS U3389 ( .A(DP_OP_168J30_122_4811_n4128), .B(n1161), .Y(n1706) );
XOR2X1TS U3390 ( .A(n1024), .B(n4652), .Y(n1159) );
BUFX4TS U3391 ( .A(Op_MY[41]), .Y(n3565) );
XOR2X1TS U3392 ( .A(n1028), .B(n4652), .Y(n1157) );
BUFX4TS U3393 ( .A(Op_MY[40]), .Y(n3568) );
OAI21X1TS U3394 ( .A0(n3743), .A1(n1130), .B0(n1031), .Y(n1032) );
XOR2X1TS U3395 ( .A(n1032), .B(n4652), .Y(n1156) );
NOR2X1TS U3396 ( .A(DP_OP_168J30_122_4811_n4154), .B(n1156), .Y(n1719) );
BUFX4TS U3397 ( .A(Op_MY[39]), .Y(n3573) );
OAI21X1TS U3398 ( .A0(n3740), .A1(n1130), .B0(n1036), .Y(n1037) );
XOR2X1TS U3399 ( .A(n1037), .B(n4652), .Y(n1155) );
BUFX4TS U3400 ( .A(Op_MY[38]), .Y(n3577) );
OAI21X1TS U3401 ( .A0(n3571), .A1(n1130), .B0(n1040), .Y(n1041) );
XOR2X1TS U3402 ( .A(n1041), .B(n4652), .Y(n1153) );
BUFX4TS U3403 ( .A(Op_MY[37]), .Y(n3581) );
OAI21X1TS U3404 ( .A0(n3575), .A1(n1130), .B0(n1044), .Y(n1045) );
XOR2X1TS U3405 ( .A(n1045), .B(n4652), .Y(n1152) );
BUFX4TS U3406 ( .A(Op_MY[36]), .Y(n3584) );
XOR2X1TS U3407 ( .A(n1049), .B(n4652), .Y(n1150) );
BUFX4TS U3408 ( .A(Op_MY[35]), .Y(n3587) );
XOR2X1TS U3409 ( .A(n1053), .B(Op_MX[29]), .Y(n1148) );
BUFX4TS U3410 ( .A(Op_MY[34]), .Y(n3590) );
XOR2X1TS U3411 ( .A(n1057), .B(Op_MX[29]), .Y(n1147) );
CLKXOR2X2TS U3412 ( .A(Op_MX[34]), .B(Op_MX[35]), .Y(n1060) );
NAND2BX4TS U3413 ( .AN(n1062), .B(n1060), .Y(n1275) );
BUFX4TS U3414 ( .A(n1275), .Y(n3521) );
NOR2X1TS U3415 ( .A(n1062), .B(n1060), .Y(n1277) );
BUFX4TS U3416 ( .A(n1277), .Y(n3519) );
BUFX4TS U3417 ( .A(Op_MY[29]), .Y(n3872) );
XNOR2X1TS U3418 ( .A(Op_MX[33]), .B(Op_MX[34]), .Y(n1061) );
NOR2BX1TS U3419 ( .AN(n1062), .B(n1061), .Y(n1276) );
BUFX3TS U3420 ( .A(n1276), .Y(n3518) );
BUFX3TS U3421 ( .A(Op_MY[28]), .Y(n3516) );
AND3X2TS U3422 ( .A(n1062), .B(n1061), .C(n1060), .Y(n3485) );
BUFX4TS U3423 ( .A(n3485), .Y(n3517) );
AOI222X1TS U3424 ( .A0(n3519), .A1(n3872), .B0(n3518), .B1(n3516), .C0(n3517), .C1(Op_MY[27]), .Y(n1063) );
BUFX4TS U3425 ( .A(Op_MX[35]), .Y(n3522) );
XOR2X1TS U3426 ( .A(n1064), .B(n3522), .Y(n3955) );
INVX2TS U3427 ( .A(n1065), .Y(n3893) );
AOI22X1TS U3428 ( .A0(n3518), .A1(Op_MY[27]), .B0(n3519), .B1(n3516), .Y(
n1066) );
XOR2X1TS U3429 ( .A(n1067), .B(n3522), .Y(n1078) );
NAND2X1TS U3430 ( .A(n3519), .B(Op_MY[27]), .Y(n1068) );
XOR2X1TS U3431 ( .A(n1069), .B(n3522), .Y(n1087) );
XNOR2X2TS U3432 ( .A(Op_MX[29]), .B(Op_MX[30]), .Y(n1074) );
CLKXOR2X2TS U3433 ( .A(Op_MX[31]), .B(Op_MX[32]), .Y(n1072) );
NAND2BX4TS U3434 ( .AN(n1074), .B(n1072), .Y(n1174) );
BUFX4TS U3435 ( .A(n1174), .Y(n3600) );
NOR2X1TS U3436 ( .A(n1074), .B(n1072), .Y(n1176) );
BUFX4TS U3437 ( .A(n1176), .Y(n3598) );
BUFX4TS U3438 ( .A(Op_MY[32]), .Y(n3595) );
XNOR2X1TS U3439 ( .A(Op_MX[30]), .B(Op_MX[31]), .Y(n1073) );
NOR2BX1TS U3440 ( .AN(n1074), .B(n1073), .Y(n1175) );
BUFX3TS U3441 ( .A(n1175), .Y(n3596) );
BUFX4TS U3442 ( .A(Op_MY[31]), .Y(n3593) );
AND3X2TS U3443 ( .A(n1074), .B(n1073), .C(n1072), .Y(n3554) );
BUFX4TS U3444 ( .A(n3554), .Y(n3594) );
BUFX4TS U3445 ( .A(Op_MY[30]), .Y(n3873) );
XOR2X1TS U3446 ( .A(n1076), .B(Op_MX[32]), .Y(n4052) );
OAI21XLTS U3447 ( .A0(n4624), .A1(n3600), .B0(n1081), .Y(n1082) );
XOR2X1TS U3448 ( .A(n1082), .B(Op_MX[32]), .Y(n1099) );
XOR2X1TS U3449 ( .A(n1086), .B(n3844), .Y(n1107) );
ADDHXLTS U3450 ( .A(n3522), .B(n1087), .CO(n1077), .S(n1106) );
AOI222X1TS U3451 ( .A0(n3598), .A1(n3872), .B0(n3596), .B1(n3516), .C0(n3594), .C1(Op_MY[27]), .Y(n1088) );
OAI21X1TS U3452 ( .A0(n3600), .A1(n4587), .B0(n1088), .Y(n1089) );
XOR2X1TS U3453 ( .A(n1089), .B(n3844), .Y(n1115) );
AOI22X1TS U3454 ( .A0(n3596), .A1(Op_MY[27]), .B0(n3598), .B1(n3516), .Y(
n1090) );
OAI21X1TS U3455 ( .A0(n3600), .A1(n3893), .B0(n1090), .Y(n1091) );
XOR2X1TS U3456 ( .A(n1091), .B(n3844), .Y(n1117) );
XOR2X1TS U3457 ( .A(n1093), .B(n3844), .Y(n1122) );
BUFX4TS U3458 ( .A(Op_MY[33]), .Y(n3597) );
OAI21X1TS U3459 ( .A0(n4635), .A1(n1130), .B0(n1096), .Y(n1097) );
XOR2X1TS U3460 ( .A(n1097), .B(Op_MX[29]), .Y(n1145) );
CMPR32X2TS U3461 ( .A(n1100), .B(n1099), .C(n1098), .CO(n4051), .S(n1143) );
XOR2X1TS U3462 ( .A(n1104), .B(n4652), .Y(n1142) );
CMPR32X2TS U3463 ( .A(n1107), .B(n1106), .C(n1105), .CO(n1098), .S(n1140) );
XOR2X1TS U3464 ( .A(n1111), .B(n4652), .Y(n1139) );
OAI21X1TS U3465 ( .A0(n4633), .A1(n1130), .B0(n1112), .Y(n1113) );
XOR2X1TS U3466 ( .A(n1113), .B(n4652), .Y(n1138) );
ADDHX1TS U3467 ( .A(n1115), .B(n1114), .CO(n1105), .S(n1137) );
ADDHX1TS U3468 ( .A(n1117), .B(n1116), .CO(n1114), .S(n1135) );
XOR2X1TS U3469 ( .A(n1119), .B(n4652), .Y(n1134) );
OAI21XLTS U3470 ( .A0(n4596), .A1(n1130), .B0(n1120), .Y(n1121) );
XOR2X1TS U3471 ( .A(n1121), .B(n4652), .Y(n1133) );
ADDHX1TS U3472 ( .A(n3844), .B(n1122), .CO(n1116), .S(n1132) );
OAI21XLTS U3473 ( .A0(n4587), .A1(n1130), .B0(n1123), .Y(n1124) );
XOR2X1TS U3474 ( .A(n1124), .B(n4652), .Y(n1203) );
AOI22X1TS U3475 ( .A0(n1125), .A1(Op_MY[27]), .B0(n1128), .B1(n3516), .Y(
n1126) );
XOR2X1TS U3476 ( .A(n1127), .B(Op_MX[29]), .Y(n1193) );
NAND2X1TS U3477 ( .A(n987), .B(Op_MY[27]), .Y(n1129) );
OAI21X1TS U3478 ( .A0(n1130), .A1(n748), .B0(n1129), .Y(n1131) );
XOR2X1TS U3479 ( .A(n1131), .B(Op_MX[29]), .Y(n1232) );
NAND2X1TS U3480 ( .A(n1193), .B(n1192), .Y(n1194) );
INVX2TS U3481 ( .A(n1194), .Y(n1204) );
OAI21X2TS U3482 ( .A0(n1989), .A1(n1992), .B0(n1990), .Y(n1986) );
NAND2X1TS U3483 ( .A(n1135), .B(n1134), .Y(n1985) );
NAND2X1TS U3484 ( .A(n1140), .B(n1139), .Y(n1975) );
INVX2TS U3485 ( .A(n1975), .Y(n1141) );
NAND2X1TS U3486 ( .A(n1143), .B(n1142), .Y(n1972) );
INVX2TS U3487 ( .A(n1972), .Y(n1144) );
NAND2X1TS U3488 ( .A(n1146), .B(n1145), .Y(n1967) );
NAND2X1TS U3489 ( .A(DP_OP_168J30_122_4811_n4193), .B(n1147), .Y(n1962) );
INVX2TS U3490 ( .A(n1957), .Y(n1149) );
NAND2X1TS U3491 ( .A(DP_OP_168J30_122_4811_n4183), .B(n1150), .Y(n1954) );
AOI21X2TS U3492 ( .A0(n901), .A1(n902), .B0(n1151), .Y(n1951) );
NAND2X1TS U3493 ( .A(DP_OP_168J30_122_4811_n4169), .B(n1153), .Y(n2023) );
INVX2TS U3494 ( .A(n2023), .Y(n1154) );
NAND2X1TS U3495 ( .A(DP_OP_168J30_122_4811_n4146), .B(n1157), .Y(n1715) );
INVX2TS U3496 ( .A(n1715), .Y(n1158) );
NAND2X1TS U3497 ( .A(DP_OP_168J30_122_4811_n4138), .B(n1159), .Y(n1712) );
INVX2TS U3498 ( .A(n1712), .Y(n1160) );
NAND2X1TS U3499 ( .A(DP_OP_168J30_122_4811_n4118), .B(n1162), .Y(n1702) );
INVX2TS U3500 ( .A(n1702), .Y(n1163) );
NAND2X1TS U3501 ( .A(DP_OP_168J30_122_4811_n4064), .B(n1170), .Y(n1675) );
BUFX3TS U3502 ( .A(n1175), .Y(n3564) );
BUFX4TS U3503 ( .A(n1176), .Y(n3569) );
AO21XLTS U3504 ( .A0(n3564), .A1(n3529), .B0(n3569), .Y(n1177) );
AOI21X1TS U3505 ( .A0(n3594), .A1(n3533), .B0(n1177), .Y(n1178) );
INVX2TS U3506 ( .A(n1187), .Y(n1236) );
INVX2TS U3507 ( .A(n1235), .Y(n1188) );
NAND2X1TS U3508 ( .A(n1188), .B(n1234), .Y(n1189) );
CLKXOR2X4TS U3509 ( .A(n1236), .B(n1189), .Y(n3769) );
CLKXOR2X2TS U3510 ( .A(Op_MX[1]), .B(Op_MX[2]), .Y(n1220) );
NAND2BX2TS U3511 ( .AN(DP_OP_168J30_122_4811_n3615), .B(n1220), .Y(n1376) );
NAND2X1TS U3512 ( .A(n1521), .B(n4081), .Y(n1190) );
OAI21XLTS U3513 ( .A0(n1523), .A1(n859), .B0(n1190), .Y(n1191) );
XOR2X1TS U3514 ( .A(n1191), .B(Op_MX[2]), .Y(n1199) );
INVX2TS U3515 ( .A(n4811), .Y(n1233) );
INVX2TS U3516 ( .A(n1196), .Y(n4083) );
NOR2BX4TS U3517 ( .AN(DP_OP_168J30_122_4811_n3615), .B(n1219), .Y(n1428) );
BUFX6TS U3518 ( .A(Op_MY[1]), .Y(n4131) );
XOR2X1TS U3519 ( .A(n1198), .B(Op_MX[2]), .Y(n1201) );
ADDHX1TS U3520 ( .A(DP_OP_168J30_122_4811_n2003), .B(n1199), .CO(n1200), .S(
n4811) );
NAND2X1TS U3521 ( .A(n1201), .B(n1200), .Y(n4338) );
INVX2TS U3522 ( .A(n1203), .Y(n1205) );
XNOR2X2TS U3523 ( .A(n1205), .B(n1204), .Y(n2003) );
INVX2TS U3524 ( .A(n2003), .Y(n2127) );
INVX2TS U3525 ( .A(n1207), .Y(n1209) );
NAND2X1TS U3526 ( .A(n1209), .B(n1208), .Y(n1211) );
XOR2X1TS U3527 ( .A(n1211), .B(n1210), .Y(n1213) );
CLKXOR2X2TS U3528 ( .A(n3769), .B(n1213), .Y(n1215) );
NAND2BX4TS U3529 ( .AN(n1206), .B(n1215), .Y(n2733) );
INVX2TS U3530 ( .A(n1225), .Y(n2146) );
INVX2TS U3531 ( .A(n1212), .Y(n4495) );
NOR2X1TS U3532 ( .A(n1215), .B(n1206), .Y(n2741) );
BUFX4TS U3533 ( .A(n2741), .Y(n4271) );
INVX2TS U3534 ( .A(n1213), .Y(n1214) );
NOR2BX1TS U3535 ( .AN(n1206), .B(n1214), .Y(n2737) );
BUFX4TS U3536 ( .A(n2737), .Y(n4270) );
BUFX3TS U3537 ( .A(DP_OP_168J30_122_4811_n1867), .Y(n4303) );
BUFX4TS U3538 ( .A(n2734), .Y(n4269) );
BUFX6TS U3539 ( .A(n4512), .Y(n4477) );
XOR2X1TS U3540 ( .A(n1217), .B(n4668), .Y(n2126) );
INVX2TS U3541 ( .A(n4338), .Y(n1530) );
INVX2TS U3542 ( .A(n1218), .Y(n4079) );
BUFX4TS U3543 ( .A(n1428), .Y(n1520) );
AND3X2TS U3544 ( .A(n1220), .B(n1219), .C(DP_OP_168J30_122_4811_n3615), .Y(
n1419) );
BUFX4TS U3545 ( .A(n1419), .Y(n1519) );
OAI21XLTS U3546 ( .A0(n4079), .A1(n1523), .B0(n1221), .Y(n1222) );
XOR2X1TS U3547 ( .A(n1222), .B(Op_MX[2]), .Y(n1223) );
INVX2TS U3548 ( .A(n4813), .Y(n2053) );
CMPR32X2TS U3549 ( .A(n1224), .B(n1999), .C(n1202), .CO(n2128), .S(n1896) );
AO22XLTS U3550 ( .A0(n4271), .A1(n4303), .B0(n4270), .B1(n4477), .Y(n1227)
);
INVX2TS U3551 ( .A(n1227), .Y(n1228) );
XOR2X1TS U3552 ( .A(n1229), .B(n4668), .Y(n1895) );
INVX2TS U3553 ( .A(n4512), .Y(n1230) );
ADDHX1TS U3554 ( .A(n4652), .B(n1232), .CO(n1192), .S(n1997) );
INVX2TS U3555 ( .A(n1997), .Y(n1901) );
ADDHXLTS U3556 ( .A(n4668), .B(n1233), .CO(n1224), .S(n1900) );
INVX2TS U3557 ( .A(n1237), .Y(n1239) );
NAND2X1TS U3558 ( .A(n1239), .B(n1238), .Y(n1240) );
XNOR2X2TS U3559 ( .A(n2696), .B(n3769), .Y(n2704) );
INVX2TS U3560 ( .A(n1242), .Y(n1267) );
INVX2TS U3561 ( .A(n1243), .Y(n1251) );
INVX2TS U3562 ( .A(n1250), .Y(n1244) );
INVX2TS U3563 ( .A(n1245), .Y(n1247) );
NAND2X1TS U3564 ( .A(n1247), .B(n1246), .Y(n1248) );
CLKXOR2X4TS U3565 ( .A(n1249), .B(n1248), .Y(n2700) );
NAND2X1TS U3566 ( .A(n1251), .B(n1250), .Y(n1252) );
CLKXOR2X2TS U3567 ( .A(n2700), .B(n2697), .Y(n2698) );
NAND2BX2TS U3568 ( .AN(n2704), .B(n2698), .Y(n2695) );
XOR2X1TS U3569 ( .A(n1253), .B(n4410), .Y(n1881) );
AOI21X1TS U3570 ( .A0(n1267), .A1(n1259), .B0(n1261), .Y(n1256) );
NAND2X1TS U3571 ( .A(n1254), .B(n1262), .Y(n1255) );
XNOR2X2TS U3572 ( .A(n2657), .B(n2700), .Y(n2664) );
INVX2TS U3573 ( .A(n2598), .Y(n1257) );
CLKXOR2X4TS U3574 ( .A(n2608), .B(n1258), .Y(n2661) );
INVX2TS U3575 ( .A(n1259), .Y(n1260) );
INVX2TS U3576 ( .A(n1261), .Y(n1264) );
AOI21X1TS U3577 ( .A0(n1267), .A1(n1266), .B0(n1265), .Y(n1272) );
NAND2X1TS U3578 ( .A(n1270), .B(n1269), .Y(n1271) );
CLKXOR2X2TS U3579 ( .A(n2661), .B(n2658), .Y(n2659) );
NAND2BX2TS U3580 ( .AN(n2664), .B(n2659), .Y(n2656) );
NOR2X1TS U3581 ( .A(n2659), .B(n2664), .Y(n2668) );
BUFX3TS U3582 ( .A(n2668), .Y(n4262) );
XOR2X1TS U3583 ( .A(n1273), .B(n4264), .Y(n1866) );
BUFX3TS U3584 ( .A(n1276), .Y(n3492) );
BUFX4TS U3585 ( .A(n1277), .Y(n3495) );
AO21XLTS U3586 ( .A0(n3492), .A1(n3529), .B0(n3495), .Y(n1278) );
AOI21X1TS U3587 ( .A0(n3517), .A1(n3533), .B0(n1278), .Y(n1279) );
OAI21X1TS U3588 ( .A0(n1359), .A1(n1275), .B0(n1279), .Y(n1280) );
CLKXOR2X2TS U3589 ( .A(Op_MX[37]), .B(Op_MX[38]), .Y(n1288) );
XNOR2X1TS U3590 ( .A(Op_MX[36]), .B(Op_MX[37]), .Y(n1287) );
BUFX6TS U3591 ( .A(n3201), .Y(n3441) );
NOR2BX1TS U3592 ( .AN(n1289), .B(n1287), .Y(n3200) );
BUFX3TS U3593 ( .A(n3200), .Y(n3444) );
BUFX4TS U3594 ( .A(n3199), .Y(n3448) );
AO21XLTS U3595 ( .A0(n3444), .A1(n3529), .B0(n3448), .Y(n1290) );
AOI21X1TS U3596 ( .A0(n3441), .A1(n3533), .B0(n1290), .Y(n1291) );
CLKXOR2X2TS U3597 ( .A(Op_MX[40]), .B(Op_MX[41]), .Y(n1294) );
NAND2BX4TS U3598 ( .AN(n1295), .B(n1294), .Y(n3189) );
XNOR2X1TS U3599 ( .A(Op_MX[39]), .B(Op_MX[40]), .Y(n1293) );
BUFX3TS U3600 ( .A(Op_MY[50]), .Y(n3366) );
BUFX3TS U3601 ( .A(Op_MY[51]), .Y(n3363) );
BUFX4TS U3602 ( .A(n3190), .Y(n3392) );
AO21XLTS U3603 ( .A0(n3389), .A1(n3363), .B0(n3392), .Y(n1296) );
AOI21X1TS U3604 ( .A0(n3386), .A1(n3366), .B0(n1296), .Y(n1297) );
XOR2X1TS U3605 ( .A(n1298), .B(Op_MX[41]), .Y(n1314) );
CLKXOR2X2TS U3606 ( .A(Op_MX[43]), .B(Op_MX[44]), .Y(n1300) );
AND3X2TS U3607 ( .A(n1301), .B(n1299), .C(n1300), .Y(n3336) );
BUFX4TS U3608 ( .A(n3342), .Y(n3337) );
BUFX4TS U3609 ( .A(n3346), .Y(n3343) );
AO21XLTS U3610 ( .A0(n3337), .A1(n3363), .B0(n3343), .Y(n1302) );
AOI21X1TS U3611 ( .A0(n3333), .A1(n3366), .B0(n1302), .Y(n1303) );
CLKXOR2X2TS U3612 ( .A(Op_MX[46]), .B(Op_MX[47]), .Y(n1306) );
XNOR2X1TS U3613 ( .A(Op_MX[45]), .B(Op_MX[46]), .Y(n1305) );
AO21XLTS U3614 ( .A0(n3282), .A1(n3363), .B0(n3290), .Y(n1308) );
AOI21X1TS U3615 ( .A0(n3278), .A1(n3366), .B0(n1308), .Y(n1309) );
XOR2X1TS U3616 ( .A(n1310), .B(n3867), .Y(n1327) );
XNOR2X2TS U3617 ( .A(Op_MX[47]), .B(Op_MX[48]), .Y(n1334) );
CLKXOR2X2TS U3618 ( .A(Op_MX[49]), .B(Op_MX[50]), .Y(n1333) );
XNOR2X1TS U3619 ( .A(Op_MX[48]), .B(Op_MX[49]), .Y(n1332) );
AND3X2TS U3620 ( .A(n1334), .B(n1332), .C(n1333), .Y(n3183) );
BUFX4TS U3621 ( .A(n3183), .Y(n3240) );
AO21XLTS U3622 ( .A0(n3241), .A1(n3363), .B0(n3249), .Y(n1335) );
AOI21X1TS U3623 ( .A0(n3240), .A1(n3366), .B0(n1335), .Y(n1336) );
XOR2X1TS U3624 ( .A(n1337), .B(Op_MX[50]), .Y(n1338) );
INVX2TS U3625 ( .A(DP_OP_168J30_122_4811_n3876), .Y(n1355) );
XNOR2X2TS U3626 ( .A(Op_MX[50]), .B(Op_MX[51]), .Y(n3170) );
BUFX4TS U3627 ( .A(n3170), .Y(n3766) );
AND2X2TS U3628 ( .A(n3170), .B(Op_MX[51]), .Y(n4585) );
BUFX3TS U3629 ( .A(Op_MY[48]), .Y(n3761) );
NOR2BX1TS U3630 ( .AN(n3170), .B(Op_MX[51]), .Y(n3171) );
BUFX3TS U3631 ( .A(n3171), .Y(n3762) );
BUFX3TS U3632 ( .A(Op_MY[49]), .Y(n3369) );
CLKAND2X2TS U3633 ( .A(n3762), .B(n3369), .Y(n1340) );
AOI21X1TS U3634 ( .A0(n4641), .A1(n3761), .B0(n1340), .Y(n1341) );
OAI21X1TS U3635 ( .A0(n3535), .A1(n3766), .B0(n1341), .Y(n1350) );
AOI21X1TS U3636 ( .A0(n3240), .A1(n3363), .B0(n3241), .Y(n1342) );
XOR2X1TS U3637 ( .A(n1343), .B(Op_MX[50]), .Y(n1349) );
CLKAND2X2TS U3638 ( .A(n3762), .B(n3366), .Y(n1345) );
AOI21X1TS U3639 ( .A0(n4641), .A1(n3369), .B0(n1345), .Y(n1346) );
OAI21X1TS U3640 ( .A0(n3531), .A1(n3766), .B0(n1346), .Y(n1356) );
INVX2TS U3641 ( .A(n3240), .Y(n1347) );
XOR2X1TS U3642 ( .A(n1348), .B(Op_MX[50]), .Y(n1354) );
CMPR32X2TS U3643 ( .A(n1356), .B(n1355), .C(n1354), .CO(n1361), .S(n1352) );
CLKAND2X2TS U3644 ( .A(n3762), .B(n3363), .Y(n1357) );
AOI21X1TS U3645 ( .A0(n4641), .A1(n3366), .B0(n1357), .Y(n1358) );
OAI21X1TS U3646 ( .A0(n1359), .A1(n3766), .B0(n1358), .Y(n1362) );
CMPR32X2TS U3647 ( .A(DP_OP_168J30_122_4811_n3876), .B(n762), .C(n1362),
.CO(n1365), .S(n1360) );
AOI21X1TS U3648 ( .A0(n4641), .A1(n3363), .B0(n3762), .Y(n1363) );
OAI21X1TS U3649 ( .A0(n3527), .A1(n3766), .B0(n1363), .Y(n1369) );
INVX2TS U3650 ( .A(n1369), .Y(n1364) );
NAND2X1TS U3651 ( .A(n1365), .B(n1364), .Y(n2054) );
INVX2TS U3652 ( .A(n4641), .Y(n1367) );
OA21XLTS U3653 ( .A0(n982), .A1(n3766), .B0(n1367), .Y(n1368) );
XOR2XLTS U3654 ( .A(n1369), .B(n1368), .Y(n1370) );
XOR2X1TS U3655 ( .A(n731), .B(n1370), .Y(n4735) );
INVX2TS U3656 ( .A(n4735), .Y(n1371) );
NOR2X2TS U3657 ( .A(DP_OP_168J30_122_4811_n2287), .B(
DP_OP_168J30_122_4811_n2295), .Y(n1823) );
CMPR32X2TS U3658 ( .A(Op_MY[1]), .B(Op_MY[2]), .C(n1374), .CO(n1483), .S(
n1218) );
BUFX6TS U3659 ( .A(Op_MY[26]), .Y(n3152) );
NAND2X1TS U3660 ( .A(n1519), .B(n3152), .Y(n1377) );
XOR2X1TS U3661 ( .A(n1378), .B(DP_OP_168J30_122_4811_n2003), .Y(n1572) );
NOR2X2TS U3662 ( .A(DP_OP_168J30_122_4811_n2402), .B(n1572), .Y(n1889) );
ADDHX1TS U3663 ( .A(Op_MY[26]), .B(n1379), .CO(n1375), .S(n1380) );
BUFX4TS U3664 ( .A(Op_MY[25]), .Y(n3793) );
CLKAND2X2TS U3665 ( .A(n1520), .B(Op_MY[26]), .Y(n1381) );
AOI21X1TS U3666 ( .A0(n1519), .A1(n3793), .B0(n1381), .Y(n1382) );
OAI21X1TS U3667 ( .A0(n3136), .A1(n1523), .B0(n1382), .Y(n1383) );
XOR2X1TS U3668 ( .A(n1383), .B(DP_OP_168J30_122_4811_n2003), .Y(n1570) );
BUFX4TS U3669 ( .A(Op_MY[24]), .Y(n3792) );
OAI21X1TS U3670 ( .A0(n3795), .A1(n1523), .B0(n1387), .Y(n1388) );
XOR2X1TS U3671 ( .A(n1388), .B(DP_OP_168J30_122_4811_n2003), .Y(n1569) );
BUFX4TS U3672 ( .A(Op_MY[23]), .Y(n3784) );
OAI21X1TS U3673 ( .A0(n3786), .A1(n1523), .B0(n1391), .Y(n1392) );
XOR2X1TS U3674 ( .A(n1392), .B(DP_OP_168J30_122_4811_n2003), .Y(n1567) );
BUFX4TS U3675 ( .A(Op_MY[22]), .Y(n3778) );
OAI21X1TS U3676 ( .A0(n3776), .A1(n1376), .B0(n1395), .Y(n1396) );
BUFX4TS U3677 ( .A(Op_MY[21]), .Y(n4459) );
OAI21X1TS U3678 ( .A0(n3780), .A1(n1376), .B0(n1399), .Y(n1400) );
XOR2X1TS U3679 ( .A(n1400), .B(DP_OP_168J30_122_4811_n2003), .Y(n1564) );
BUFX4TS U3680 ( .A(Op_MY[20]), .Y(n4458) );
OAI21X1TS U3681 ( .A0(n3773), .A1(n1376), .B0(n1403), .Y(n1404) );
XOR2X1TS U3682 ( .A(n1404), .B(DP_OP_168J30_122_4811_n2003), .Y(n1563) );
OAI21X1TS U3683 ( .A0(n4461), .A1(n1376), .B0(n1407), .Y(n1408) );
XOR2X1TS U3684 ( .A(n1408), .B(DP_OP_168J30_122_4811_n2003), .Y(n1562) );
NOR2X1TS U3685 ( .A(DP_OP_168J30_122_4811_n2487), .B(n1562), .Y(n4534) );
BUFX4TS U3686 ( .A(Op_MY[18]), .Y(n4470) );
OAI21X1TS U3687 ( .A0(n4449), .A1(n1376), .B0(n1411), .Y(n1412) );
XOR2X1TS U3688 ( .A(n1412), .B(DP_OP_168J30_122_4811_n2003), .Y(n1560) );
BUFX4TS U3689 ( .A(Op_MY[17]), .Y(n4516) );
OAI21X1TS U3690 ( .A0(n4475), .A1(n1376), .B0(n1415), .Y(n1416) );
BUFX4TS U3691 ( .A(Op_MY[16]), .Y(n4514) );
XOR2X1TS U3692 ( .A(n1421), .B(DP_OP_168J30_122_4811_n2003), .Y(n1557) );
BUFX4TS U3693 ( .A(Op_MY[15]), .Y(n4463) );
OAI21X1TS U3694 ( .A0(n4519), .A1(n1523), .B0(n1424), .Y(n1425) );
BUFX4TS U3695 ( .A(Op_MY[14]), .Y(n4453) );
OAI21X1TS U3696 ( .A0(n3801), .A1(n1523), .B0(n1429), .Y(n1430) );
XOR2X1TS U3697 ( .A(n1430), .B(DP_OP_168J30_122_4811_n2003), .Y(n1554) );
BUFX4TS U3698 ( .A(Op_MY[13]), .Y(n4452) );
OAI21X1TS U3699 ( .A0(n3798), .A1(n1523), .B0(n1433), .Y(n1434) );
INVX2TS U3700 ( .A(n1436), .Y(n4455) );
BUFX4TS U3701 ( .A(Op_MY[12]), .Y(n4451) );
OAI21X1TS U3702 ( .A0(n4455), .A1(n1523), .B0(n1437), .Y(n1438) );
XOR2X1TS U3703 ( .A(n1438), .B(DP_OP_168J30_122_4811_n2003), .Y(n1551) );
BUFX4TS U3704 ( .A(Op_MY[11]), .Y(n4443) );
INVX2TS U3705 ( .A(n1444), .Y(n4441) );
BUFX4TS U3706 ( .A(Op_MY[10]), .Y(n4439) );
OAI21X1TS U3707 ( .A0(n4441), .A1(n1523), .B0(n1445), .Y(n1446) );
XOR2X1TS U3708 ( .A(n1446), .B(DP_OP_168J30_122_4811_n2003), .Y(n1548) );
INVX2TS U3709 ( .A(n1448), .Y(n4436) );
BUFX4TS U3710 ( .A(Op_MY[9]), .Y(n4432) );
OAI21X1TS U3711 ( .A0(n4436), .A1(n1523), .B0(n1449), .Y(n1450) );
INVX2TS U3712 ( .A(n1452), .Y(n4418) );
BUFX4TS U3713 ( .A(Op_MY[8]), .Y(n4415) );
OAI21X1TS U3714 ( .A0(n4418), .A1(n1523), .B0(n1453), .Y(n1454) );
XOR2X1TS U3715 ( .A(n1454), .B(DP_OP_168J30_122_4811_n2003), .Y(n1545) );
INVX2TS U3716 ( .A(n1456), .Y(n4358) );
BUFX4TS U3717 ( .A(Op_MY[7]), .Y(n4356) );
OAI21X1TS U3718 ( .A0(n4358), .A1(n1523), .B0(n1457), .Y(n1458) );
XNOR2X2TS U3719 ( .A(Op_MX[5]), .B(Op_MX[6]), .Y(n1461) );
CLKXOR2X2TS U3720 ( .A(Op_MX[7]), .B(Op_MX[8]), .Y(n1459) );
NAND2BX4TS U3721 ( .AN(n1461), .B(n1459), .Y(n3129) );
NOR2X2TS U3722 ( .A(n1461), .B(n1459), .Y(n1467) );
BUFX6TS U3723 ( .A(n1467), .Y(n4472) );
XNOR2X1TS U3724 ( .A(Op_MX[7]), .B(Op_MX[6]), .Y(n1460) );
NOR2BX1TS U3725 ( .AN(n1461), .B(n1460), .Y(n3133) );
BUFX3TS U3726 ( .A(n3133), .Y(n4444) );
AOI222X1TS U3727 ( .A0(n4472), .A1(n4178), .B0(n4444), .B1(n4131), .C0(n3130), .C1(Op_MY[0]), .Y(n1462) );
XOR2XLTS U3728 ( .A(n1463), .B(n4456), .Y(n4055) );
AO22XLTS U3729 ( .A0(n4444), .A1(Op_MY[0]), .B0(n1467), .B1(n4131), .Y(n1464) );
INVX2TS U3730 ( .A(n1464), .Y(n1465) );
OAI21XLTS U3731 ( .A0(n3129), .A1(n4083), .B0(n1465), .Y(n1466) );
XOR2X1TS U3732 ( .A(n1466), .B(n4456), .Y(n1478) );
NAND2X1TS U3733 ( .A(n1467), .B(n4081), .Y(n1468) );
OAI21XLTS U3734 ( .A0(n3129), .A1(n859), .B0(n1468), .Y(n1469) );
XOR2X1TS U3735 ( .A(n1469), .B(n4456), .Y(n1487) );
CMPR32X2TS U3736 ( .A(Op_MY[4]), .B(Op_MY[5]), .C(n1470), .CO(n1507), .S(
n1471) );
INVX2TS U3737 ( .A(n1471), .Y(n4295) );
XNOR2X2TS U3738 ( .A(Op_MX[3]), .B(Op_MX[2]), .Y(n1474) );
CLKXOR2X2TS U3739 ( .A(Op_MX[5]), .B(Op_MX[4]), .Y(n1472) );
NAND2BX4TS U3740 ( .AN(n1474), .B(n1472), .Y(n1574) );
NOR2X2TS U3741 ( .A(n1474), .B(n1472), .Y(n3771) );
BUFX4TS U3742 ( .A(Op_MY[5]), .Y(n4196) );
NOR2BX4TS U3743 ( .AN(n1474), .B(n1473), .Y(n3810) );
BUFX4TS U3744 ( .A(n3810), .Y(n4433) );
BUFX4TS U3745 ( .A(Op_MY[4]), .Y(n4139) );
BUFX4TS U3746 ( .A(Op_MY[3]), .Y(n4110) );
AOI222X1TS U3747 ( .A0(n3811), .A1(n4196), .B0(n4433), .B1(n4139), .C0(n3809), .C1(n4110), .Y(n1475) );
OAI21XLTS U3748 ( .A0(n4295), .A1(n4435), .B0(n1475), .Y(n1476) );
XOR2X1TS U3749 ( .A(n1476), .B(n4437), .Y(n4057) );
INVX2TS U3750 ( .A(n1480), .Y(n4180) );
AOI222X1TS U3751 ( .A0(n3811), .A1(n4139), .B0(n4433), .B1(n4110), .C0(n3809), .C1(n4178), .Y(n1481) );
XOR2X1TS U3752 ( .A(n1482), .B(n4437), .Y(n1498) );
INVX2TS U3753 ( .A(n1484), .Y(n4133) );
AOI222X1TS U3754 ( .A0(n3811), .A1(n4110), .B0(n4433), .B1(n4178), .C0(n1575), .C1(n4131), .Y(n1485) );
OAI21XLTS U3755 ( .A0(n4133), .A1(n4435), .B0(n1485), .Y(n1486) );
XOR2X1TS U3756 ( .A(n1486), .B(n4437), .Y(n1506) );
ADDHXLTS U3757 ( .A(n4456), .B(n1487), .CO(n1477), .S(n1505) );
AOI222X1TS U3758 ( .A0(n3811), .A1(n4178), .B0(n4433), .B1(n4131), .C0(n1575), .C1(Op_MY[0]), .Y(n1488) );
OAI21XLTS U3759 ( .A0(n4079), .A1(n4435), .B0(n1488), .Y(n1489) );
XOR2X1TS U3760 ( .A(n1489), .B(n4437), .Y(n1512) );
XOR2X1TS U3761 ( .A(n1490), .B(n4437), .Y(n1516) );
NAND2X1TS U3762 ( .A(n3771), .B(n4081), .Y(n1491) );
XOR2X1TS U3763 ( .A(n1492), .B(n4437), .Y(n1526) );
INVX2TS U3764 ( .A(n1494), .Y(n4395) );
BUFX4TS U3765 ( .A(Op_MY[6]), .Y(n4309) );
OAI21XLTS U3766 ( .A0(n4395), .A1(n1523), .B0(n1495), .Y(n1496) );
XOR2X1TS U3767 ( .A(n1496), .B(Op_MX[2]), .Y(n1541) );
CMPR32X2TS U3768 ( .A(n1499), .B(n1498), .C(n1497), .CO(n4056), .S(n1540) );
INVX2TS U3769 ( .A(n1501), .Y(n4354) );
OAI21XLTS U3770 ( .A0(n4354), .A1(n1523), .B0(n1502), .Y(n1503) );
CMPR32X2TS U3771 ( .A(n1506), .B(n1505), .C(n1504), .CO(n1497), .S(n1538) );
INVX2TS U3772 ( .A(n1508), .Y(n4141) );
OAI21XLTS U3773 ( .A0(n4141), .A1(n1523), .B0(n1509), .Y(n1510) );
XOR2X1TS U3774 ( .A(n1510), .B(Op_MX[2]), .Y(n1537) );
ADDHX1TS U3775 ( .A(n1512), .B(n1511), .CO(n1504), .S(n1535) );
OAI21XLTS U3776 ( .A0(n4295), .A1(n1523), .B0(n1513), .Y(n1514) );
XOR2X1TS U3777 ( .A(n1514), .B(Op_MX[2]), .Y(n1534) );
ADDHX1TS U3778 ( .A(n1516), .B(n1515), .CO(n1511), .S(n1533) );
OAI21XLTS U3779 ( .A0(n4180), .A1(n1523), .B0(n1517), .Y(n1518) );
XOR2X1TS U3780 ( .A(n1518), .B(Op_MX[2]), .Y(n1532) );
OAI21XLTS U3781 ( .A0(n4133), .A1(n1523), .B0(n1522), .Y(n1525) );
XOR2X1TS U3782 ( .A(n1525), .B(Op_MX[2]), .Y(n1528) );
ADDHX1TS U3783 ( .A(n4657), .B(n1526), .CO(n1515), .S(n1527) );
NOR2X1TS U3784 ( .A(n4339), .B(n4337), .Y(n1531) );
NAND2X1TS U3785 ( .A(n1528), .B(n1527), .Y(n4340) );
INVX2TS U3786 ( .A(n4340), .Y(n1529) );
NAND2X1TS U3787 ( .A(n1533), .B(n1532), .Y(n4349) );
NAND2X1TS U3788 ( .A(n1535), .B(n1534), .Y(n4368) );
INVX2TS U3789 ( .A(n4368), .Y(n1536) );
OAI21X2TS U3790 ( .A0(n4148), .A1(n865), .B0(n4149), .Y(n4188) );
INVX2TS U3791 ( .A(n4187), .Y(n1543) );
NAND2X1TS U3792 ( .A(DP_OP_168J30_122_4811_n2578), .B(n1545), .Y(n4490) );
INVX2TS U3793 ( .A(n4490), .Y(n1546) );
AOI21X2TS U3794 ( .A0(n878), .A1(n4491), .B0(n1546), .Y(n3817) );
OAI21X2TS U3795 ( .A0(n3814), .A1(n3817), .B0(n3815), .Y(n4506) );
NAND2X1TS U3796 ( .A(DP_OP_168J30_122_4811_n2566), .B(n1548), .Y(n4505) );
INVX2TS U3797 ( .A(n4505), .Y(n1549) );
NAND2X1TS U3798 ( .A(DP_OP_168J30_122_4811_n2552), .B(n1551), .Y(n3687) );
INVX2TS U3799 ( .A(n3687), .Y(n1552) );
AOI21X2TS U3800 ( .A0(n876), .A1(n3688), .B0(n1552), .Y(n4524) );
OAI21X2TS U3801 ( .A0(n4521), .A1(n4524), .B0(n4522), .Y(n4527) );
INVX2TS U3802 ( .A(n4526), .Y(n1555) );
OAI21X2TS U3803 ( .A0(n3690), .A1(n3693), .B0(n3691), .Y(n4560) );
NAND2X1TS U3804 ( .A(DP_OP_168J30_122_4811_n2518), .B(n1557), .Y(n4559) );
INVX2TS U3805 ( .A(n4559), .Y(n1558) );
AOI21X2TS U3806 ( .A0(n898), .A1(n4560), .B0(n1558), .Y(n4532) );
OAI21X2TS U3807 ( .A0(n4529), .A1(n4532), .B0(n4530), .Y(n3696) );
NAND2X1TS U3808 ( .A(DP_OP_168J30_122_4811_n2498), .B(n1560), .Y(n3695) );
INVX2TS U3809 ( .A(n3695), .Y(n1561) );
AOI21X2TS U3810 ( .A0(n899), .A1(n3696), .B0(n1561), .Y(n4537) );
OAI21X2TS U3811 ( .A0(n4539), .A1(n860), .B0(n4540), .Y(n3699) );
NAND2X1TS U3812 ( .A(DP_OP_168J30_122_4811_n2465), .B(n1564), .Y(n3698) );
INVX2TS U3813 ( .A(n3698), .Y(n1565) );
NAND2X1TS U3814 ( .A(DP_OP_168J30_122_4811_n2439), .B(n1567), .Y(n4563) );
INVX2TS U3815 ( .A(n4563), .Y(n1568) );
AOI21X2TS U3816 ( .A0(n869), .A1(n4564), .B0(n1568), .Y(n3715) );
NAND2X1TS U3817 ( .A(DP_OP_168J30_122_4811_n2414), .B(n1570), .Y(n1897) );
INVX2TS U3818 ( .A(n1897), .Y(n1571) );
NAND2X1TS U3819 ( .A(DP_OP_168J30_122_4811_n2390), .B(
DP_OP_168J30_122_4811_n2401), .Y(n1883) );
INVX2TS U3820 ( .A(n1883), .Y(n1573) );
AOI21X4TS U3821 ( .A0(n1885), .A1(n830), .B0(n1573), .Y(n1880) );
BUFX6TS U3822 ( .A(n1575), .Y(n3809) );
CLKAND2X2TS U3823 ( .A(n4433), .B(n3152), .Y(n1576) );
AOI21X1TS U3824 ( .A0(n3809), .A1(n3793), .B0(n1576), .Y(n1577) );
OAI21X1TS U3825 ( .A0(n3136), .A1(n1574), .B0(n1577), .Y(n1578) );
XOR2X1TS U3826 ( .A(n1578), .B(n4657), .Y(n1579) );
NAND2X1TS U3827 ( .A(DP_OP_168J30_122_4811_n2366), .B(
DP_OP_168J30_122_4811_n2377), .Y(n1872) );
INVX2TS U3828 ( .A(n1872), .Y(n1580) );
AOI21X4TS U3829 ( .A0(n1873), .A1(n829), .B0(n1580), .Y(n1861) );
NAND2X1TS U3830 ( .A(DP_OP_168J30_122_4811_n2354), .B(
DP_OP_168J30_122_4811_n2365), .Y(n1868) );
INVX2TS U3831 ( .A(n1868), .Y(n1862) );
NAND2X1TS U3832 ( .A(DP_OP_168J30_122_4811_n2353), .B(
DP_OP_168J30_122_4811_n2342), .Y(n1863) );
INVX2TS U3833 ( .A(n1863), .Y(n1581) );
INVX2TS U3834 ( .A(n1851), .Y(n1857) );
INVX2TS U3835 ( .A(n1856), .Y(n1585) );
NAND2X1TS U3836 ( .A(DP_OP_168J30_122_4811_n2318), .B(
DP_OP_168J30_122_4811_n2328), .Y(n1852) );
INVX2TS U3837 ( .A(n1852), .Y(n1584) );
NAND2X1TS U3838 ( .A(DP_OP_168J30_122_4811_n2317), .B(
DP_OP_168J30_122_4811_n2307), .Y(n1847) );
NAND2X1TS U3839 ( .A(DP_OP_168J30_122_4811_n2296), .B(
DP_OP_168J30_122_4811_n2306), .Y(n1841) );
INVX2TS U3840 ( .A(n1841), .Y(n1586) );
INVX2TS U3841 ( .A(n1825), .Y(n1592) );
NAND2X1TS U3842 ( .A(DP_OP_168J30_122_4811_n2268), .B(
DP_OP_168J30_122_4811_n2277), .Y(n1819) );
INVX2TS U3843 ( .A(n1819), .Y(n1591) );
INVX2TS U3844 ( .A(n1787), .Y(n1793) );
INVX2TS U3845 ( .A(n1792), .Y(n1600) );
INVX2TS U3846 ( .A(n1788), .Y(n1599) );
INVX2TS U3847 ( .A(n1775), .Y(n1601) );
NAND2X1TS U3848 ( .A(DP_OP_168J30_122_4811_n2220), .B(
DP_OP_168J30_122_4811_n2224), .Y(n1766) );
INVX2TS U3849 ( .A(n1759), .Y(n1602) );
CLKAND2X2TS U3850 ( .A(n2830), .B(Op_MY[24]), .Y(n1619) );
INVX2TS U3851 ( .A(n1619), .Y(n1618) );
XNOR2X2TS U3852 ( .A(Op_MX[23]), .B(Op_MX[24]), .Y(n2765) );
CLKXOR2X2TS U3853 ( .A(Op_MX[25]), .B(Op_MX[26]), .Y(n2764) );
XNOR2X1TS U3854 ( .A(Op_MX[24]), .B(Op_MX[25]), .Y(n1605) );
BUFX4TS U3855 ( .A(n2786), .Y(n2850) );
CLKAND2X2TS U3856 ( .A(n2850), .B(n3152), .Y(n1606) );
AOI21X1TS U3857 ( .A0(n2787), .A1(Op_MY[25]), .B0(n1606), .Y(n1607) );
XOR2X1TS U3858 ( .A(n1608), .B(n2848), .Y(n1613) );
INVX2TS U3859 ( .A(n1736), .Y(n1610) );
CLKAND2X2TS U3860 ( .A(n2830), .B(Op_MY[25]), .Y(n1617) );
NAND2X1TS U3861 ( .A(n2787), .B(n3152), .Y(n1611) );
XOR2X1TS U3862 ( .A(n1612), .B(n2848), .Y(n1616) );
CMPR32X2TS U3863 ( .A(DP_OP_168J30_122_4811_n2206), .B(n1618), .C(n1613),
.CO(n1614), .S(n1609) );
CMPR32X2TS U3864 ( .A(n1618), .B(n1617), .C(n1616), .CO(n1622), .S(n1615) );
CLKAND2X2TS U3865 ( .A(n2830), .B(n3152), .Y(n1620) );
XOR3X1TS U3866 ( .A(n917), .B(n1620), .C(n1619), .Y(n1621) );
XOR2X1TS U3867 ( .A(n1622), .B(n1621), .Y(n1623) );
CLKXOR2X2TS U3868 ( .A(n1624), .B(n1623), .Y(n1945) );
BUFX4TS U3869 ( .A(n2540), .Y(n4661) );
CLKAND2X2TS U3870 ( .A(n4661), .B(n916), .Y(n1632) );
INVX2TS U3871 ( .A(DP_OP_168J30_122_4811_n86), .Y(n1631) );
XNOR2X1TS U3872 ( .A(n1632), .B(n1631), .Y(n1630) );
INVX2TS U3873 ( .A(n1945), .Y(n1628) );
CMPR32X2TS U3874 ( .A(DP_OP_168J30_122_4811_n215), .B(n1630), .C(
DP_OP_168J30_122_4811_n216), .CO(n1634), .S(n1629) );
INVX2TS U3875 ( .A(n1643), .Y(n1655) );
NAND2X1TS U3876 ( .A(n1669), .B(n1668), .Y(n1670) );
NAND2X1TS U3877 ( .A(n1690), .B(n1689), .Y(n1691) );
CMPR32X2TS U3878 ( .A(DP_OP_168J30_122_4811_n243), .B(
DP_OP_168J30_122_4811_n250), .C(n1692), .CO(n1687), .S(n2037) );
CMPR32X2TS U3879 ( .A(DP_OP_168J30_122_4811_n259), .B(
DP_OP_168J30_122_4811_n266), .C(n1701), .CO(n1698), .S(n2034) );
CMPR32X2TS U3880 ( .A(DP_OP_168J30_122_4811_n267), .B(
DP_OP_168J30_122_4811_n275), .C(n1705), .CO(n1701), .S(n2033) );
INVX2TS U3881 ( .A(n1706), .Y(n1708) );
CLKXOR2X2TS U3882 ( .A(n1710), .B(n1709), .Y(n3630) );
NAND2X1TS U3883 ( .A(n923), .B(n1712), .Y(n1713) );
NAND2X1TS U3884 ( .A(n922), .B(n1715), .Y(n1717) );
INVX2TS U3885 ( .A(n1719), .Y(n1721) );
CLKXOR2X2TS U3886 ( .A(n1722), .B(n896), .Y(n3634) );
INVX2TS U3887 ( .A(n1724), .Y(n1726) );
INVX2TS U3888 ( .A(n1730), .Y(n1732) );
NAND2X1TS U3889 ( .A(n1732), .B(n1731), .Y(n1733) );
CMPR32X2TS U3890 ( .A(DP_OP_168J30_122_4811_n542), .B(
DP_OP_168J30_122_4811_n545), .C(n1739), .CO(n1735), .S(n1942) );
CLKXOR2X2TS U3891 ( .A(n1744), .B(n1743), .Y(n3704) );
CMPR32X2TS U3892 ( .A(DP_OP_168J30_122_4811_n572), .B(
DP_OP_168J30_122_4811_n585), .C(n1754), .CO(n1745), .S(n1938) );
NAND2X1TS U3893 ( .A(n875), .B(n1759), .Y(n1760) );
CMPR32X2TS U3894 ( .A(DP_OP_168J30_122_4811_n586), .B(
DP_OP_168J30_122_4811_n589), .C(n1762), .CO(n1754), .S(n1937) );
INVX2TS U3895 ( .A(n1765), .Y(n1767) );
INVX2TS U3896 ( .A(n1772), .Y(n1773) );
CMPR32X2TS U3897 ( .A(DP_OP_168J30_122_4811_n613), .B(
DP_OP_168J30_122_4811_n625), .C(n1778), .CO(n1770), .S(n1933) );
INVX2TS U3898 ( .A(n1781), .Y(n1783) );
NAND2X1TS U3899 ( .A(n903), .B(n1788), .Y(n1789) );
INVX2TS U3900 ( .A(n1809), .Y(n1798) );
INVX2TS U3901 ( .A(n1802), .Y(n1804) );
INVX2TS U3902 ( .A(n1810), .Y(n1812) );
NAND2X1TS U3903 ( .A(n1373), .B(n1819), .Y(n1820) );
NAND2X1TS U3904 ( .A(n1831), .B(n1830), .Y(n1832) );
CMPR32X2TS U3905 ( .A(DP_OP_168J30_122_4811_n702), .B(
DP_OP_168J30_122_4811_n709), .C(n1834), .CO(n1829), .S(n1920) );
INVX2TS U3906 ( .A(n1846), .Y(n1836) );
INVX2TS U3907 ( .A(n1845), .Y(n1838) );
AOI21X1TS U3908 ( .A0(n1838), .A1(n825), .B0(n1837), .Y(n1839) );
NAND2X1TS U3909 ( .A(n825), .B(n1847), .Y(n1848) );
CMPR32X2TS U3910 ( .A(n1850), .B(DP_OP_168J30_122_4811_n721), .C(
DP_OP_168J30_122_4811_n718), .CO(n1844), .S(n1917) );
NAND2X1TS U3911 ( .A(n826), .B(n1852), .Y(n1853) );
CMPR32X2TS U3912 ( .A(DP_OP_168J30_122_4811_n733), .B(
DP_OP_168J30_122_4811_n739), .C(n1860), .CO(n1855), .S(n1913) );
NAND2X1TS U3913 ( .A(n827), .B(n1863), .Y(n1864) );
CMPR32X2TS U3914 ( .A(n1875), .B(DP_OP_168J30_122_4811_n756), .C(
DP_OP_168J30_122_4811_n752), .CO(n1871), .S(n1908) );
CMPR32X2TS U3915 ( .A(n1888), .B(n1887), .C(n1886), .CO(n1882), .S(n1905) );
CLKXOR2X2TS U3916 ( .A(n1893), .B(n1892), .Y(n4573) );
CMPR32X2TS U3917 ( .A(n1896), .B(n1895), .C(n1894), .CO(n1886), .S(n1903) );
NAND2X1TS U3918 ( .A(n833), .B(n1897), .Y(n1899) );
CMPR32X2TS U3919 ( .A(n1902), .B(n1901), .C(n1900), .CO(n1894), .S(n4891) );
INVX2TS U3920 ( .A(n4908), .Y(n1909) );
INVX2TS U3921 ( .A(n4921), .Y(n1914) );
INVX2TS U3922 ( .A(n4925), .Y(n1916) );
AOI21X4TS U3923 ( .A0(n894), .A1(n846), .B0(n1916), .Y(n4931) );
INVX2TS U3924 ( .A(n4934), .Y(n1919) );
INVX2TS U3925 ( .A(n4938), .Y(n1921) );
AOI21X4TS U3926 ( .A0(n919), .A1(n740), .B0(n1921), .Y(n4944) );
INVX2TS U3927 ( .A(n4854), .Y(n1924) );
INVX2TS U3928 ( .A(n4858), .Y(n1926) );
AOI21X4TS U3929 ( .A0(n905), .A1(n844), .B0(n1926), .Y(n4864) );
INVX2TS U3930 ( .A(n4867), .Y(n1929) );
INVX2TS U3931 ( .A(n4838), .Y(n1931) );
INVX2TS U3932 ( .A(n4847), .Y(n1934) );
INVX2TS U3933 ( .A(n4851), .Y(n1936) );
AOI21X4TS U3934 ( .A0(n890), .A1(n837), .B0(n1936), .Y(n4822) );
OAI21X4TS U3935 ( .A0(n4819), .A1(n4822), .B0(n4820), .Y(n4826) );
INVX2TS U3936 ( .A(n4825), .Y(n1939) );
INVX2TS U3937 ( .A(n4829), .Y(n1941) );
AOI21X4TS U3938 ( .A0(n909), .A1(n746), .B0(n1941), .Y(n4835) );
OAI21X4TS U3939 ( .A0(n5079), .A1(n742), .B0(n5080), .Y(n5076) );
NAND2X1TS U3940 ( .A(n1945), .B(n1944), .Y(n5075) );
INVX2TS U3941 ( .A(n5075), .Y(n1946) );
CMPR32X2TS U3942 ( .A(DP_OP_168J30_122_4811_n327), .B(
DP_OP_168J30_122_4811_n338), .C(n1947), .CO(n2022), .S(n2019) );
INVX2TS U3943 ( .A(n1948), .Y(n1950) );
NAND2X1TS U3944 ( .A(n901), .B(n1954), .Y(n1955) );
NAND2X1TS U3945 ( .A(n738), .B(n1957), .Y(n1959) );
INVX2TS U3946 ( .A(n1961), .Y(n1963) );
NAND2X1TS U3947 ( .A(n1963), .B(n1962), .Y(n1964) );
CLKXOR2X2TS U3948 ( .A(n1964), .B(n900), .Y(n4276) );
INVX2TS U3949 ( .A(n1966), .Y(n1968) );
NAND2X1TS U3950 ( .A(n1968), .B(n1967), .Y(n1970) );
CLKXOR2X2TS U3951 ( .A(n1970), .B(n1969), .Y(n4192) );
NAND2X1TS U3952 ( .A(n866), .B(n1972), .Y(n1973) );
CMPR32X2TS U3953 ( .A(DP_OP_168J30_122_4811_n405), .B(
DP_OP_168J30_122_4811_n419), .C(n1974), .CO(n1971), .S(n2010) );
NAND2X1TS U3954 ( .A(n873), .B(n1975), .Y(n1977) );
INVX2TS U3955 ( .A(n1979), .Y(n1981) );
NAND2X1TS U3956 ( .A(n1981), .B(n1980), .Y(n1983) );
CLKXOR2X2TS U3957 ( .A(n1983), .B(n1982), .Y(n4145) );
NAND2X1TS U3958 ( .A(n868), .B(n1985), .Y(n1987) );
XNOR2X2TS U3959 ( .A(n1987), .B(n1986), .Y(n4143) );
NAND2X1TS U3960 ( .A(n1991), .B(n1990), .Y(n1993) );
CLKXOR2X2TS U3961 ( .A(n1993), .B(n1992), .Y(n4144) );
NOR2X2TS U3962 ( .A(n4976), .B(n4972), .Y(n2021) );
INVX2TS U3963 ( .A(n5070), .Y(n2002) );
NAND2X1TS U3964 ( .A(n2000), .B(n1999), .Y(n5066) );
INVX2TS U3965 ( .A(n5066), .Y(n2001) );
INVX2TS U3966 ( .A(n5050), .Y(n2006) );
INVX2TS U3967 ( .A(n5016), .Y(n2012) );
AOI21X4TS U3968 ( .A0(n5073), .A1(n2021), .B0(n2020), .Y(n4970) );
NAND2X1TS U3969 ( .A(n895), .B(n2023), .Y(n2025) );
OAI21X4TS U3970 ( .A0(n4970), .A1(n4966), .B0(n4967), .Y(n4963) );
INVX2TS U3971 ( .A(n4962), .Y(n2028) );
AOI21X4TS U3972 ( .A0(n948), .A1(n4963), .B0(n2028), .Y(n4955) );
OAI21X4TS U3973 ( .A0(n4952), .A1(n4955), .B0(n4953), .Y(n4959) );
INVX2TS U3974 ( .A(n4958), .Y(n2031) );
AOI21X4TS U3975 ( .A0(n949), .A1(n4959), .B0(n2031), .Y(n5094) );
AOI21X4TS U3976 ( .A0(n855), .A1(n953), .B0(n2043), .Y(n5165) );
OAI21X4TS U3977 ( .A0(n5172), .A1(n957), .B0(n5173), .Y(n5181) );
AOI21X4TS U3978 ( .A0(n886), .A1(n5181), .B0(n2047), .Y(n5190) );
AOI2BB1X4TS U3979 ( .A0N(n5187), .A1N(n5190), .B0(n2048), .Y(n2049) );
NOR2X2TS U3980 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n5317) );
NAND2X1TS U3981 ( .A(n5317), .B(FS_Module_state_reg[3]), .Y(n4742) );
INVX2TS U3982 ( .A(n4743), .Y(n2050) );
OAI21X4TS U3983 ( .A0(n4742), .A1(n2051), .B0(n2050), .Y(n5030) );
INVX2TS U3984 ( .A(n2057), .Y(n2059) );
NAND2X1TS U3985 ( .A(n2059), .B(n2058), .Y(n2060) );
INVX2TS U3986 ( .A(n2062), .Y(n2064) );
CMPR22X2TS U3987 ( .A(Op_MY[26]), .B(n2129), .CO(n2540), .S(n2547) );
BUFX4TS U3988 ( .A(n2547), .Y(n4660) );
CLKAND2X2TS U3989 ( .A(n4660), .B(n916), .Y(DP_OP_168J30_122_4811_n824) );
CMPR32X4TS U3990 ( .A(Op_MY[24]), .B(Op_MY[51]), .C(n2130), .CO(n2135), .S(
n3728) );
CLKAND2X2TS U3991 ( .A(n4608), .B(n916), .Y(DP_OP_168J30_122_4811_n826) );
BUFX6TS U3992 ( .A(n4008), .Y(n4607) );
CLKAND2X2TS U3993 ( .A(n4607), .B(n916), .Y(DP_OP_168J30_122_4811_n827) );
BUFX6TS U3994 ( .A(n4605), .Y(n4327) );
CLKAND2X2TS U3995 ( .A(n4327), .B(n916), .Y(DP_OP_168J30_122_4811_n828) );
CMPR32X2TS U3996 ( .A(Op_MY[17]), .B(Op_MY[44]), .C(n2133), .CO(n2139), .S(
n2222) );
CMPR32X2TS U3997 ( .A(Op_MY[15]), .B(Op_MY[42]), .C(n2134), .CO(n2140), .S(
n3916) );
BUFX6TS U3998 ( .A(n3916), .Y(n4361) );
CMPR32X2TS U3999 ( .A(Op_MY[45]), .B(Op_MY[18]), .C(n2139), .CO(n2138), .S(
n4667) );
CMPR32X2TS U4000 ( .A(Op_MY[16]), .B(Op_MY[43]), .C(n2140), .CO(n2133), .S(
n4548) );
CMPR32X2TS U4001 ( .A(Op_MY[41]), .B(Op_MY[14]), .C(n2141), .CO(n2134), .S(
n3910) );
CMPR32X2TS U4002 ( .A(Op_MY[13]), .B(Op_MY[40]), .C(n2142), .CO(n2141), .S(
n2407) );
CMPR32X2TS U4003 ( .A(Op_MY[10]), .B(Op_MY[37]), .C(n2145), .CO(n2144), .S(
n2410) );
NOR2X1TS U4004 ( .A(DP_OP_168J30_122_4811_n1865), .B(
DP_OP_168J30_122_4811_n1866), .Y(n2341) );
INVX2TS U4005 ( .A(n2341), .Y(n2347) );
AFHCONX2TS U4006 ( .A(DP_OP_168J30_122_4811_n1867), .B(n2146), .CI(
DP_OP_168J30_122_4811_n1866), .CON(n2348), .S(n1212) );
INVX2TS U4007 ( .A(n2346), .Y(n2148) );
NAND2X1TS U4008 ( .A(DP_OP_168J30_122_4811_n1864), .B(
DP_OP_168J30_122_4811_n1865), .Y(n2340) );
INVX2TS U4009 ( .A(n2340), .Y(n2147) );
INVX2TS U4010 ( .A(n2204), .Y(n2151) );
NAND2X1TS U4011 ( .A(n883), .B(n2155), .Y(n2156) );
INVX2TS U4012 ( .A(n2158), .Y(n2160) );
NAND2X1TS U4013 ( .A(n2160), .B(n2159), .Y(n2161) );
CLKXOR2X4TS U4014 ( .A(n2162), .B(n2161), .Y(n2311) );
CLKXOR2X2TS U4015 ( .A(n2233), .B(n2164), .Y(n2170) );
NAND2X1TS U4016 ( .A(n4500), .B(n4661), .Y(n2165) );
XOR2X1TS U4017 ( .A(n2166), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n964) );
BUFX4TS U4018 ( .A(n2243), .Y(n4009) );
NOR2BX4TS U4019 ( .AN(n2172), .B(n820), .Y(n2238) );
BUFX6TS U4020 ( .A(n2238), .Y(n4007) );
AOI222X1TS U4021 ( .A0(n4009), .A1(n4661), .B0(n4007), .B1(n4660), .C0(n4500), .C1(n790), .Y(n2173) );
XOR2X1TS U4022 ( .A(n2174), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n966) );
AOI222X1TS U4023 ( .A0(n4009), .A1(n4660), .B0(n4007), .B1(n2550), .C0(n4500), .C1(n4608), .Y(n2180) );
XOR2X1TS U4024 ( .A(n2181), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n967) );
AOI222X1TS U4025 ( .A0(n4009), .A1(n790), .B0(n4007), .B1(n4608), .C0(n4500),
.C1(n4008), .Y(n2187) );
XOR2X1TS U4026 ( .A(n2188), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n968) );
AOI222X1TS U4027 ( .A0(n4009), .A1(n4608), .B0(n4007), .B1(n4008), .C0(n4500), .C1(n4327), .Y(n2193) );
XOR2X1TS U4028 ( .A(n2194), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n969) );
AOI222X1TS U4029 ( .A0(n4009), .A1(n4327), .B0(n4007), .B1(n4616), .C0(n2231), .C1(n4544), .Y(n2199) );
XOR2X1TS U4030 ( .A(n2200), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n971) );
AOI222X1TS U4031 ( .A0(n4009), .A1(n4616), .B0(n4007), .B1(n4544), .C0(n4500), .C1(n4614), .Y(n2206) );
XOR2X1TS U4032 ( .A(n2207), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n972) );
AFHCINX2TS U4033 ( .CIN(n2208), .B(n4615), .A(n3995), .S(n2209), .CO(n2204)
);
AOI222X1TS U4034 ( .A0(n4009), .A1(n4544), .B0(n4007), .B1(n4614), .C0(n4500), .C1(n4667), .Y(n2210) );
XOR2X1TS U4035 ( .A(n2211), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n973) );
AFHCONX2TS U4036 ( .A(n4667), .B(n3995), .CI(n2212), .CON(n2208), .S(n2213)
);
AOI222X1TS U4037 ( .A0(n4009), .A1(n4614), .B0(n4007), .B1(n4667), .C0(n4500), .C1(n2222), .Y(n2214) );
XOR2X1TS U4038 ( .A(n2215), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n974) );
AFHCINX2TS U4039 ( .CIN(n2216), .B(n4667), .A(n2222), .S(n2217), .CO(n2212)
);
BUFX6TS U4040 ( .A(n4667), .Y(n4550) );
BUFX6TS U4041 ( .A(n4548), .Y(n4363) );
AOI222X1TS U4042 ( .A0(n4009), .A1(n4550), .B0(n4007), .B1(n2222), .C0(n4500), .C1(n4363), .Y(n2218) );
XOR2X1TS U4043 ( .A(n2219), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n975) );
AFHCONX2TS U4044 ( .A(n4548), .B(n2222), .CI(n2220), .CON(n2216), .S(n2221)
);
BUFX6TS U4045 ( .A(n2222), .Y(n4549) );
AOI222X1TS U4046 ( .A0(n4009), .A1(n4549), .B0(n4007), .B1(n4363), .C0(n4500), .C1(n4361), .Y(n2223) );
XOR2X1TS U4047 ( .A(n2224), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n976) );
AFHCINX2TS U4048 ( .CIN(n2225), .B(n4548), .A(n3916), .S(n2226), .CO(n2220)
);
BUFX6TS U4049 ( .A(n3910), .Y(n4656) );
AOI222X1TS U4050 ( .A0(n4009), .A1(n4363), .B0(n4007), .B1(n4361), .C0(n4500), .C1(n4656), .Y(n2227) );
XOR2X1TS U4051 ( .A(n2228), .B(DP_OP_168J30_122_4811_n86), .Y(
DP_OP_168J30_122_4811_n977) );
AFHCONX2TS U4052 ( .A(n3910), .B(n3916), .CI(n2229), .CON(n2225), .S(n2230)
);
BUFX6TS U4053 ( .A(n2231), .Y(n4500) );
AOI222X1TS U4054 ( .A0(n4009), .A1(n4361), .B0(n4007), .B1(n4656), .C0(n4500), .C1(n4655), .Y(n2232) );
XOR2X1TS U4055 ( .A(n2234), .B(n4503), .Y(DP_OP_168J30_122_4811_n978) );
AFHCINX2TS U4056 ( .CIN(n2236), .B(n3910), .A(n2407), .S(n2237), .CO(n2229)
);
BUFX4TS U4057 ( .A(n2725), .Y(n4630) );
AOI222X1TS U4058 ( .A0(n4009), .A1(n4656), .B0(n2238), .B1(n4655), .C0(n4500), .C1(n4630), .Y(n2239) );
XOR2X1TS U4059 ( .A(n2240), .B(n4503), .Y(DP_OP_168J30_122_4811_n979) );
AFHCONX2TS U4060 ( .A(n2725), .B(n2241), .CI(n2407), .CON(n2236), .S(n2242)
);
BUFX4TS U4061 ( .A(n2728), .Y(n4604) );
AOI222X1TS U4062 ( .A0(n4501), .A1(n4655), .B0(n4007), .B1(n4630), .C0(n4500), .C1(n4604), .Y(n2244) );
XOR2X1TS U4063 ( .A(n2245), .B(n4503), .Y(DP_OP_168J30_122_4811_n980) );
AFHCINX2TS U4064 ( .CIN(n2246), .B(n2725), .A(n2728), .S(n2247), .CO(n2241)
);
AOI222X1TS U4065 ( .A0(n4501), .A1(n4630), .B0(n4007), .B1(n4604), .C0(n4500), .C1(n4603), .Y(n2248) );
XOR2X1TS U4066 ( .A(n2249), .B(n4503), .Y(DP_OP_168J30_122_4811_n981) );
AFHCONX2TS U4067 ( .A(n2410), .B(n2728), .CI(n2250), .CON(n2246), .S(n2251)
);
BUFX4TS U4068 ( .A(DP_OP_168J30_122_4811_n1859), .Y(n4578) );
AOI222X1TS U4069 ( .A0(n4501), .A1(n4604), .B0(n4007), .B1(n4603), .C0(n4500), .C1(n4578), .Y(n2252) );
XOR2X1TS U4070 ( .A(n2253), .B(n4503), .Y(DP_OP_168J30_122_4811_n982) );
AFHCINX2TS U4071 ( .CIN(n2254), .B(n2410), .A(DP_OP_168J30_122_4811_n1859),
.S(n2255), .CO(n2250) );
BUFX4TS U4072 ( .A(DP_OP_168J30_122_4811_n1860), .Y(n4571) );
AOI222X1TS U4073 ( .A0(n4501), .A1(n2410), .B0(n4007), .B1(n4578), .C0(n4500), .C1(n4571), .Y(n2256) );
XOR2X1TS U4074 ( .A(n2257), .B(n4503), .Y(DP_OP_168J30_122_4811_n983) );
AFHCONX2TS U4075 ( .A(DP_OP_168J30_122_4811_n1860), .B(
DP_OP_168J30_122_4811_n1859), .CI(n2258), .CON(n2254), .S(n2259) );
AOI222X1TS U4076 ( .A0(n4501), .A1(n4578), .B0(n4007), .B1(n4571), .C0(n4500), .C1(n4572), .Y(n2260) );
XOR2X1TS U4077 ( .A(n2261), .B(n4503), .Y(DP_OP_168J30_122_4811_n984) );
AFHCINX2TS U4078 ( .CIN(n2262), .B(DP_OP_168J30_122_4811_n1860), .A(
DP_OP_168J30_122_4811_n1861), .S(n2263), .CO(n2258) );
BUFX4TS U4079 ( .A(DP_OP_168J30_122_4811_n1862), .Y(n4562) );
AOI222X1TS U4080 ( .A0(n4501), .A1(n4571), .B0(n4007), .B1(n4572), .C0(n4500), .C1(n4562), .Y(n2264) );
XOR2X1TS U4081 ( .A(n2265), .B(n4503), .Y(DP_OP_168J30_122_4811_n985) );
AFHCONX2TS U4082 ( .A(DP_OP_168J30_122_4811_n1862), .B(
DP_OP_168J30_122_4811_n1861), .CI(n2266), .CON(n2262), .S(n2267) );
BUFX4TS U4083 ( .A(DP_OP_168J30_122_4811_n1863), .Y(n4510) );
AOI222X1TS U4084 ( .A0(n4501), .A1(n4572), .B0(n2238), .B1(n4562), .C0(n4500), .C1(n4510), .Y(n2268) );
XOR2X1TS U4085 ( .A(n2269), .B(n4503), .Y(DP_OP_168J30_122_4811_n986) );
NAND2X1TS U4086 ( .A(n2272), .B(n2271), .Y(n2273) );
NAND2X1TS U4087 ( .A(n882), .B(n2275), .Y(n2276) );
XNOR2X2TS U4088 ( .A(n2281), .B(n2400), .Y(n2291) );
NAND2X1TS U4089 ( .A(n914), .B(n2278), .Y(n2279) );
CLKXOR2X2TS U4090 ( .A(n2311), .B(n2282), .Y(n2292) );
XNOR2X1TS U4091 ( .A(n2282), .B(n2281), .Y(n2287) );
NAND2X1TS U4092 ( .A(n4661), .B(n2309), .Y(n2283) );
XOR2X1TS U4093 ( .A(n2284), .B(n2311), .Y(DP_OP_168J30_122_4811_n995) );
NOR2BX1TS U4094 ( .AN(n2291), .B(n2287), .Y(n2314) );
CLKAND2X2TS U4095 ( .A(n4661), .B(n4659), .Y(n2288) );
AOI21X1TS U4096 ( .A0(n4660), .A1(n2309), .B0(n2288), .Y(n2289) );
XOR2X1TS U4097 ( .A(n2290), .B(n2311), .Y(DP_OP_168J30_122_4811_n996) );
XOR2X1TS U4098 ( .A(n2294), .B(n2311), .Y(DP_OP_168J30_122_4811_n1000) );
XOR2X1TS U4099 ( .A(n2300), .B(n2361), .Y(DP_OP_168J30_122_4811_n1001) );
XOR2X1TS U4100 ( .A(n2302), .B(n2361), .Y(DP_OP_168J30_122_4811_n1002) );
XOR2X1TS U4101 ( .A(n2304), .B(n2361), .Y(DP_OP_168J30_122_4811_n1006) );
XOR2X1TS U4102 ( .A(n2306), .B(n2361), .Y(DP_OP_168J30_122_4811_n1007) );
XOR2X1TS U4103 ( .A(n2308), .B(n2361), .Y(DP_OP_168J30_122_4811_n1008) );
XOR2X1TS U4104 ( .A(n2312), .B(n2361), .Y(DP_OP_168J30_122_4811_n1009) );
BUFX4TS U4105 ( .A(n2313), .Y(n2360) );
BUFX3TS U4106 ( .A(n2314), .Y(n2356) );
XOR2X1TS U4107 ( .A(n2316), .B(n2361), .Y(DP_OP_168J30_122_4811_n1010) );
XOR2X1TS U4108 ( .A(n2319), .B(n2361), .Y(DP_OP_168J30_122_4811_n1011) );
XOR2X1TS U4109 ( .A(n2321), .B(n2361), .Y(DP_OP_168J30_122_4811_n1012) );
XOR2X1TS U4110 ( .A(n2323), .B(n2361), .Y(DP_OP_168J30_122_4811_n1013) );
XOR2X1TS U4111 ( .A(n2325), .B(n2361), .Y(DP_OP_168J30_122_4811_n1014) );
XOR2X1TS U4112 ( .A(n2327), .B(n2361), .Y(DP_OP_168J30_122_4811_n1015) );
XOR2X1TS U4113 ( .A(n2329), .B(n2361), .Y(DP_OP_168J30_122_4811_n1016) );
XOR2X1TS U4114 ( .A(n2331), .B(n2361), .Y(DP_OP_168J30_122_4811_n1017) );
AFHCINX2TS U4115 ( .CIN(n2332), .B(DP_OP_168J30_122_4811_n1862), .A(
DP_OP_168J30_122_4811_n1863), .S(n2333), .CO(n2266) );
BUFX4TS U4116 ( .A(DP_OP_168J30_122_4811_n1864), .Y(n4511) );
XOR2X1TS U4117 ( .A(n2335), .B(n2361), .Y(DP_OP_168J30_122_4811_n1018) );
AFHCONX2TS U4118 ( .A(DP_OP_168J30_122_4811_n1864), .B(
DP_OP_168J30_122_4811_n1863), .CI(n2336), .CON(n2332), .S(n2337) );
BUFX4TS U4119 ( .A(DP_OP_168J30_122_4811_n1865), .Y(n4508) );
XOR2XLTS U4120 ( .A(n2339), .B(n2361), .Y(DP_OP_168J30_122_4811_n1019) );
NAND2X1TS U4121 ( .A(n927), .B(n2340), .Y(n2343) );
OAI21X1TS U4122 ( .A0(n2341), .A1(n2348), .B0(n2346), .Y(n2342) );
BUFX4TS U4123 ( .A(DP_OP_168J30_122_4811_n1866), .Y(n4509) );
OAI21XLTS U4124 ( .A0(n2360), .A1(n926), .B0(n2344), .Y(n2345) );
XOR2X1TS U4125 ( .A(n2345), .B(n2361), .Y(DP_OP_168J30_122_4811_n1020) );
XOR2X1TS U4126 ( .A(n2349), .B(n2348), .Y(n2350) );
INVX2TS U4127 ( .A(n2350), .Y(n4121) );
BUFX4TS U4128 ( .A(DP_OP_168J30_122_4811_n1867), .Y(n4493) );
OAI21XLTS U4129 ( .A0(n2360), .A1(n4121), .B0(n2351), .Y(n2352) );
XOR2X1TS U4130 ( .A(n2352), .B(n2361), .Y(DP_OP_168J30_122_4811_n1021) );
OAI21XLTS U4131 ( .A0(n2360), .A1(n4495), .B0(n2354), .Y(n2355) );
XOR2X1TS U4132 ( .A(n2355), .B(n2361), .Y(DP_OP_168J30_122_4811_n1022) );
XOR2X1TS U4133 ( .A(n2357), .B(n2361), .Y(DP_OP_168J30_122_4811_n1023) );
NAND2X1TS U4134 ( .A(n2358), .B(n4477), .Y(n2359) );
XOR2X1TS U4135 ( .A(n2362), .B(n2361), .Y(DP_OP_168J30_122_4811_n1024) );
CLKXOR2X4TS U4136 ( .A(n2370), .B(n2369), .Y(n2489) );
XNOR2X2TS U4137 ( .A(n2376), .B(n2489), .Y(n2384) );
CLKXOR2X2TS U4138 ( .A(n2400), .B(n2377), .Y(n2385) );
NAND2BX2TS U4139 ( .AN(n2384), .B(n2385), .Y(n2402) );
XNOR2X1TS U4140 ( .A(n2377), .B(n2376), .Y(n2380) );
NAND2X1TS U4141 ( .A(n4661), .B(n2398), .Y(n2378) );
XOR2X1TS U4142 ( .A(n2379), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1026) );
NOR2BX1TS U4143 ( .AN(n2384), .B(n2380), .Y(n2403) );
AOI21X1TS U4144 ( .A0(n4660), .A1(n2398), .B0(n2381), .Y(n2382) );
XOR2X1TS U4145 ( .A(n2383), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1027) );
OAI21X1TS U4146 ( .A0(n835), .A1(n4610), .B0(n2386), .Y(n2387) );
XOR2X1TS U4147 ( .A(n2387), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1028) );
XOR2X1TS U4148 ( .A(n2389), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1029) );
OAI21X1TS U4149 ( .A0(n838), .A1(n4610), .B0(n2390), .Y(n2391) );
XOR2X1TS U4150 ( .A(n2391), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1030) );
OAI21X1TS U4151 ( .A0(n928), .A1(n4610), .B0(n2392), .Y(n2393) );
XOR2X1TS U4152 ( .A(n2393), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1034) );
OAI21X1TS U4153 ( .A0(n4610), .A1(n4267), .B0(n2394), .Y(n2395) );
XOR2X1TS U4154 ( .A(n2395), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1035) );
OAI21X1TS U4155 ( .A0(n4610), .A1(n4325), .B0(n2396), .Y(n2397) );
XOR2X1TS U4156 ( .A(n2397), .B(DP_OP_168J30_122_4811_n66), .Y(
DP_OP_168J30_122_4811_n1036) );
XOR2X1TS U4157 ( .A(n2401), .B(n3957), .Y(DP_OP_168J30_122_4811_n1040) );
BUFX3TS U4158 ( .A(n2403), .Y(n2434) );
XOR2X1TS U4159 ( .A(n2405), .B(n3957), .Y(DP_OP_168J30_122_4811_n1041) );
XOR2X1TS U4160 ( .A(n2409), .B(n3957), .Y(DP_OP_168J30_122_4811_n1042) );
XOR2X1TS U4161 ( .A(n2412), .B(n3957), .Y(DP_OP_168J30_122_4811_n1043) );
XOR2X1TS U4162 ( .A(n2414), .B(n3957), .Y(DP_OP_168J30_122_4811_n1044) );
XOR2X1TS U4163 ( .A(n2416), .B(n3957), .Y(DP_OP_168J30_122_4811_n1045) );
XOR2X1TS U4164 ( .A(n2418), .B(n3957), .Y(DP_OP_168J30_122_4811_n1046) );
XOR2X1TS U4165 ( .A(n2420), .B(n3957), .Y(DP_OP_168J30_122_4811_n1047) );
XOR2XLTS U4166 ( .A(n2422), .B(n3957), .Y(DP_OP_168J30_122_4811_n1048) );
XOR2X1TS U4167 ( .A(n2424), .B(n3957), .Y(DP_OP_168J30_122_4811_n1049) );
XOR2XLTS U4168 ( .A(n2426), .B(n3957), .Y(DP_OP_168J30_122_4811_n1050) );
OAI21XLTS U4169 ( .A0(n4610), .A1(n926), .B0(n2427), .Y(n2428) );
XOR2X1TS U4170 ( .A(n2428), .B(n3957), .Y(DP_OP_168J30_122_4811_n1051) );
OAI21XLTS U4171 ( .A0(n4610), .A1(n4121), .B0(n2429), .Y(n2430) );
XOR2X1TS U4172 ( .A(n2430), .B(n3957), .Y(DP_OP_168J30_122_4811_n1052) );
OAI21XLTS U4173 ( .A0(n4610), .A1(n4495), .B0(n2432), .Y(n2433) );
XOR2X1TS U4174 ( .A(n2433), .B(n3957), .Y(DP_OP_168J30_122_4811_n1053) );
OAI21XLTS U4175 ( .A0(n4610), .A1(n1226), .B0(n757), .Y(n2435) );
XOR2X1TS U4176 ( .A(n2435), .B(n3957), .Y(DP_OP_168J30_122_4811_n1054) );
INVX2TS U4177 ( .A(n2452), .Y(n2446) );
INVX2TS U4178 ( .A(n2447), .Y(n2449) );
XNOR2X2TS U4179 ( .A(n2459), .B(n2577), .Y(n2467) );
CLKXOR2X2TS U4180 ( .A(n2489), .B(n2460), .Y(n2468) );
NAND2BX2TS U4181 ( .AN(n2467), .B(n2468), .Y(n2491) );
XNOR2X1TS U4182 ( .A(n2460), .B(n2459), .Y(n2463) );
NAND2X1TS U4183 ( .A(n4661), .B(n2487), .Y(n2461) );
XOR2X1TS U4184 ( .A(n2462), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1057) );
NOR2BX1TS U4185 ( .AN(n2467), .B(n2463), .Y(n2492) );
AOI21X1TS U4186 ( .A0(n4660), .A1(n2487), .B0(n2464), .Y(n2465) );
XOR2X1TS U4187 ( .A(n2466), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1058) );
XOR2X1TS U4188 ( .A(n2470), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1059) );
OAI21X1TS U4189 ( .A0(n836), .A1(n4546), .B0(n2471), .Y(n2472) );
XOR2X1TS U4190 ( .A(n2472), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1060) );
XOR2X1TS U4191 ( .A(n2474), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1061) );
XOR2X1TS U4192 ( .A(n2476), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1062) );
XOR2X1TS U4193 ( .A(n2478), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1063) );
XOR2X1TS U4194 ( .A(n2480), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1064) );
XOR2X1TS U4195 ( .A(n2482), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1068) );
XOR2X1TS U4196 ( .A(n2484), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1069) );
XOR2X1TS U4197 ( .A(n2486), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1070) );
XOR2X1TS U4198 ( .A(n2490), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1071) );
BUFX3TS U4199 ( .A(n2492), .Y(n3922) );
XOR2X1TS U4200 ( .A(n2494), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1072) );
XOR2X1TS U4201 ( .A(n2497), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1073) );
XOR2X1TS U4202 ( .A(n2499), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1074) );
XOR2X1TS U4203 ( .A(n2501), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1077) );
XOR2XLTS U4204 ( .A(n2503), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1078) );
XOR2XLTS U4205 ( .A(n2505), .B(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1079) );
OAI21XLTS U4206 ( .A0(n2491), .A1(n4488), .B0(n2506), .Y(n2507) );
XOR2X1TS U4207 ( .A(n2507), .B(n2489), .Y(DP_OP_168J30_122_4811_n1080) );
XOR2XLTS U4208 ( .A(n2509), .B(n2489), .Y(DP_OP_168J30_122_4811_n1081) );
OAI21XLTS U4209 ( .A0(n2491), .A1(n926), .B0(n2510), .Y(n2511) );
XOR2X1TS U4210 ( .A(n2511), .B(n2489), .Y(DP_OP_168J30_122_4811_n1082) );
OAI21XLTS U4211 ( .A0(n2491), .A1(n4121), .B0(n2512), .Y(n2513) );
XOR2X1TS U4212 ( .A(n2513), .B(n2489), .Y(DP_OP_168J30_122_4811_n1083) );
OAI21XLTS U4213 ( .A0(n2491), .A1(n4495), .B0(n2514), .Y(n2515) );
XOR2X1TS U4214 ( .A(n2515), .B(n2489), .Y(DP_OP_168J30_122_4811_n1084) );
XOR2X1TS U4215 ( .A(n2516), .B(n2489), .Y(DP_OP_168J30_122_4811_n1085) );
INVX2TS U4216 ( .A(n2523), .Y(n2525) );
NAND2X1TS U4217 ( .A(n2525), .B(n2524), .Y(n2526) );
XNOR2X2TS U4218 ( .A(n2536), .B(n2648), .Y(n2545) );
INVX2TS U4219 ( .A(n2531), .Y(n2533) );
CLKXOR2X2TS U4220 ( .A(n2577), .B(n2537), .Y(n2546) );
NAND2BX2TS U4221 ( .AN(n2545), .B(n2546), .Y(n2579) );
BUFX6TS U4222 ( .A(n2579), .Y(n2576) );
XNOR2X1TS U4223 ( .A(n2537), .B(n2536), .Y(n2541) );
NAND2X1TS U4224 ( .A(n4661), .B(n4379), .Y(n2538) );
XOR2X1TS U4225 ( .A(n2539), .B(n4613), .Y(DP_OP_168J30_122_4811_n1088) );
NOR2BX1TS U4226 ( .AN(n2545), .B(n2541), .Y(n2581) );
AOI21X1TS U4227 ( .A0(n4660), .A1(n4379), .B0(n2542), .Y(n2543) );
XOR2X1TS U4228 ( .A(n2544), .B(n4613), .Y(DP_OP_168J30_122_4811_n1089) );
AOI222X1TS U4229 ( .A0(n4227), .A1(n3911), .B0(n4315), .B1(n4381), .C0(n790),
.C1(n4379), .Y(n2548) );
XOR2X1TS U4230 ( .A(n2549), .B(n4613), .Y(DP_OP_168J30_122_4811_n1090) );
XOR2X1TS U4231 ( .A(n2552), .B(n4613), .Y(DP_OP_168J30_122_4811_n1091) );
XOR2X1TS U4232 ( .A(n2554), .B(n4613), .Y(DP_OP_168J30_122_4811_n1092) );
AOI222X1TS U4233 ( .A0(n4608), .A1(n3911), .B0(n4607), .B1(n4381), .C0(n4327), .C1(n4379), .Y(n2555) );
XOR2X1TS U4234 ( .A(n2556), .B(n4613), .Y(DP_OP_168J30_122_4811_n1093) );
AOI222X1TS U4235 ( .A0(n4607), .A1(n3911), .B0(n4327), .B1(n4381), .C0(n4658), .C1(n4379), .Y(n2557) );
XOR2X1TS U4236 ( .A(n2558), .B(n4613), .Y(DP_OP_168J30_122_4811_n1094) );
AOI222X1TS U4237 ( .A0(n4327), .A1(n3911), .B0(n4658), .B1(n4381), .C0(n4544), .C1(n4379), .Y(n2559) );
XOR2X1TS U4238 ( .A(n2560), .B(n4613), .Y(DP_OP_168J30_122_4811_n1095) );
AOI222X1TS U4239 ( .A0(n4658), .A1(n3911), .B0(n4544), .B1(n4381), .C0(n4614), .C1(n4379), .Y(n2561) );
XOR2X1TS U4240 ( .A(n2562), .B(n4613), .Y(DP_OP_168J30_122_4811_n1096) );
AOI222X1TS U4241 ( .A0(n4544), .A1(n3911), .B0(n4614), .B1(n4381), .C0(n4550), .C1(n4379), .Y(n2563) );
XOR2X1TS U4242 ( .A(n2564), .B(n4613), .Y(DP_OP_168J30_122_4811_n1097) );
AOI222X1TS U4243 ( .A0(n4614), .A1(n3911), .B0(n4550), .B1(n4381), .C0(n4549), .C1(n4379), .Y(n2565) );
XOR2X1TS U4244 ( .A(n2566), .B(n4613), .Y(DP_OP_168J30_122_4811_n1098) );
AOI222X1TS U4245 ( .A0(n4550), .A1(n3911), .B0(n4549), .B1(n2574), .C0(n4363), .C1(n2573), .Y(n2567) );
XOR2X1TS U4246 ( .A(n2568), .B(n4613), .Y(DP_OP_168J30_122_4811_n1099) );
AOI222X1TS U4247 ( .A0(n4549), .A1(n3911), .B0(n4363), .B1(n2574), .C0(n2573), .C1(n4361), .Y(n2569) );
XOR2X1TS U4248 ( .A(n2570), .B(n4613), .Y(DP_OP_168J30_122_4811_n1100) );
AOI222X1TS U4249 ( .A0(n4363), .A1(n3911), .B0(n3916), .B1(n2574), .C0(n2573), .C1(n4656), .Y(n2571) );
XOR2X1TS U4250 ( .A(n2572), .B(n4613), .Y(DP_OP_168J30_122_4811_n1101) );
AOI222X1TS U4251 ( .A0(n3911), .A1(n3916), .B0(n2574), .B1(n3910), .C0(n2573), .C1(n4655), .Y(n2575) );
XOR2X1TS U4252 ( .A(n2578), .B(n4384), .Y(DP_OP_168J30_122_4811_n1102) );
BUFX4TS U4253 ( .A(DP_OP_168J30_122_4811_n1859), .Y(n4380) );
XOR2X1TS U4254 ( .A(n2583), .B(n4384), .Y(DP_OP_168J30_122_4811_n1108) );
CLKBUFX3TS U4255 ( .A(DP_OP_168J30_122_4811_n1863), .Y(n4404) );
XOR2X1TS U4256 ( .A(n2585), .B(n4384), .Y(DP_OP_168J30_122_4811_n1111) );
XOR2XLTS U4257 ( .A(n2587), .B(n4384), .Y(DP_OP_168J30_122_4811_n1112) );
XOR2X1TS U4258 ( .A(n2589), .B(n4384), .Y(DP_OP_168J30_122_4811_n1113) );
XOR2X1TS U4259 ( .A(n2591), .B(n4384), .Y(DP_OP_168J30_122_4811_n1114) );
XOR2X1TS U4260 ( .A(n2593), .B(n4384), .Y(DP_OP_168J30_122_4811_n1115) );
AO22XLTS U4261 ( .A0(n2580), .A1(n4303), .B0(n2574), .B1(n4477), .Y(n2594)
);
INVX2TS U4262 ( .A(n2594), .Y(n2595) );
XOR2X1TS U4263 ( .A(n2596), .B(n4384), .Y(DP_OP_168J30_122_4811_n1116) );
XNOR2X2TS U4264 ( .A(n2613), .B(n2661), .Y(n2621) );
INVX2TS U4265 ( .A(n2604), .Y(n2607) );
INVX2TS U4266 ( .A(n2605), .Y(n2606) );
CLKXOR2X2TS U4267 ( .A(n2648), .B(n2614), .Y(n2622) );
NAND2BX2TS U4268 ( .AN(n2621), .B(n2622), .Y(n2643) );
XNOR2X1TS U4269 ( .A(n2614), .B(n2613), .Y(n2617) );
NAND2X1TS U4270 ( .A(n4227), .B(n4372), .Y(n2615) );
XOR2X1TS U4271 ( .A(n2616), .B(n4669), .Y(DP_OP_168J30_122_4811_n1119) );
NOR2BX1TS U4272 ( .AN(n2621), .B(n2617), .Y(n2645) );
BUFX3TS U4273 ( .A(n2645), .Y(n3917) );
AOI21X1TS U4274 ( .A0(n4315), .A1(n4372), .B0(n2618), .Y(n2619) );
XOR2X1TS U4275 ( .A(n2620), .B(n4669), .Y(DP_OP_168J30_122_4811_n1120) );
XOR2X1TS U4276 ( .A(n2624), .B(n4669), .Y(DP_OP_168J30_122_4811_n1121) );
XOR2X1TS U4277 ( .A(n2626), .B(n4669), .Y(DP_OP_168J30_122_4811_n1122) );
XOR2X1TS U4278 ( .A(n2628), .B(n4669), .Y(DP_OP_168J30_122_4811_n1123) );
AOI222X1TS U4279 ( .A0(n4608), .A1(n3943), .B0(n4607), .B1(n4373), .C0(n4327), .C1(n4372), .Y(n2629) );
XOR2X1TS U4280 ( .A(n2630), .B(n4669), .Y(DP_OP_168J30_122_4811_n1124) );
AOI222X1TS U4281 ( .A0(n4607), .A1(n3943), .B0(n4327), .B1(n4373), .C0(n4658), .C1(n4372), .Y(n2631) );
XOR2X1TS U4282 ( .A(n2632), .B(n4669), .Y(DP_OP_168J30_122_4811_n1125) );
AOI222X1TS U4283 ( .A0(n4327), .A1(n3943), .B0(n4658), .B1(n4373), .C0(n4544), .C1(n4372), .Y(n2633) );
XOR2X1TS U4284 ( .A(n2634), .B(n4669), .Y(DP_OP_168J30_122_4811_n1126) );
AOI222X1TS U4285 ( .A0(n4658), .A1(n3943), .B0(n4544), .B1(n4373), .C0(n4614), .C1(n4372), .Y(n2635) );
XOR2X1TS U4286 ( .A(n2636), .B(n4669), .Y(DP_OP_168J30_122_4811_n1127) );
AOI222X1TS U4287 ( .A0(n4544), .A1(n3943), .B0(n4614), .B1(n4373), .C0(n4550), .C1(n4372), .Y(n2637) );
XOR2X1TS U4288 ( .A(n2638), .B(n4669), .Y(DP_OP_168J30_122_4811_n1128) );
AOI222X1TS U4289 ( .A0(n4614), .A1(n3943), .B0(n4550), .B1(n4373), .C0(n4549), .C1(n4372), .Y(n2639) );
XOR2X1TS U4290 ( .A(n2640), .B(n4669), .Y(DP_OP_168J30_122_4811_n1129) );
AOI222X1TS U4291 ( .A0(n4550), .A1(n3943), .B0(n4549), .B1(n3917), .C0(n4363), .C1(n2646), .Y(n2641) );
XOR2X1TS U4292 ( .A(n2642), .B(n4669), .Y(DP_OP_168J30_122_4811_n1130) );
BUFX4TS U4293 ( .A(n2648), .Y(n4377) );
XOR2X1TS U4294 ( .A(n2649), .B(n4377), .Y(DP_OP_168J30_122_4811_n1142) );
XOR2X1TS U4295 ( .A(n2651), .B(n4377), .Y(DP_OP_168J30_122_4811_n1144) );
XOR2X1TS U4296 ( .A(n2653), .B(n4377), .Y(DP_OP_168J30_122_4811_n1145) );
OAI21XLTS U4297 ( .A0(n2643), .A1(n4495), .B0(n2654), .Y(n2655) );
XOR2X1TS U4298 ( .A(n2655), .B(n4377), .Y(DP_OP_168J30_122_4811_n1146) );
BUFX6TS U4299 ( .A(n2656), .Y(n4365) );
XNOR2X1TS U4300 ( .A(n2658), .B(n2657), .Y(n2663) );
NAND2X1TS U4301 ( .A(n4227), .B(n4260), .Y(n2660) );
XOR2X1TS U4302 ( .A(n2662), .B(n2661), .Y(DP_OP_168J30_122_4811_n1150) );
NOR2BX1TS U4303 ( .AN(n2664), .B(n2663), .Y(n2689) );
BUFX3TS U4304 ( .A(n2689), .Y(n4360) );
AOI21X1TS U4305 ( .A0(n4315), .A1(n4260), .B0(n2665), .Y(n2666) );
XOR2X1TS U4306 ( .A(n2667), .B(n2661), .Y(DP_OP_168J30_122_4811_n1151) );
XOR2X1TS U4307 ( .A(n2670), .B(n2661), .Y(DP_OP_168J30_122_4811_n1152) );
OAI21X1TS U4308 ( .A0(n836), .A1(n4365), .B0(n2671), .Y(n2672) );
XOR2X1TS U4309 ( .A(n2672), .B(n2661), .Y(DP_OP_168J30_122_4811_n1153) );
OAI21X1TS U4310 ( .A0(n838), .A1(n4365), .B0(n2673), .Y(n2674) );
XOR2X1TS U4311 ( .A(n2674), .B(n2661), .Y(DP_OP_168J30_122_4811_n1154) );
AOI222X1TS U4312 ( .A0(n4608), .A1(n4362), .B0(n4607), .B1(n4261), .C0(n4327), .C1(n4260), .Y(n2675) );
XOR2X1TS U4313 ( .A(n2676), .B(n2661), .Y(DP_OP_168J30_122_4811_n1155) );
AOI222X1TS U4314 ( .A0(n4607), .A1(n4362), .B0(n4327), .B1(n4261), .C0(n4658), .C1(n4260), .Y(n2677) );
XOR2X1TS U4315 ( .A(n2678), .B(n4264), .Y(DP_OP_168J30_122_4811_n1156) );
AOI222X1TS U4316 ( .A0(n4327), .A1(n4362), .B0(n4658), .B1(n4261), .C0(n4544), .C1(n4260), .Y(n2679) );
XOR2X1TS U4317 ( .A(n2680), .B(n4264), .Y(DP_OP_168J30_122_4811_n1157) );
AOI222X1TS U4318 ( .A0(n4658), .A1(n4362), .B0(n4544), .B1(n4261), .C0(n4614), .C1(n4260), .Y(n2681) );
XOR2X1TS U4319 ( .A(n2682), .B(n4264), .Y(DP_OP_168J30_122_4811_n1158) );
AOI222X1TS U4320 ( .A0(n4544), .A1(n4362), .B0(n4614), .B1(n4261), .C0(n4550), .C1(n4260), .Y(n2683) );
XOR2X1TS U4321 ( .A(n2684), .B(n4264), .Y(DP_OP_168J30_122_4811_n1159) );
AOI222X1TS U4322 ( .A0(n4614), .A1(n4362), .B0(n4550), .B1(n4261), .C0(n4549), .C1(n4260), .Y(n2685) );
XOR2X1TS U4323 ( .A(n2686), .B(n4264), .Y(DP_OP_168J30_122_4811_n1160) );
AOI222X1TS U4324 ( .A0(n4550), .A1(n4362), .B0(n4549), .B1(n4261), .C0(n4363), .C1(n4260), .Y(n2687) );
XOR2X1TS U4325 ( .A(n2688), .B(n4264), .Y(DP_OP_168J30_122_4811_n1161) );
XOR2X1TS U4326 ( .A(n2692), .B(n4264), .Y(DP_OP_168J30_122_4811_n1175) );
XOR2X1TS U4327 ( .A(n2694), .B(n4264), .Y(DP_OP_168J30_122_4811_n1176) );
XNOR2X1TS U4328 ( .A(n2697), .B(n2696), .Y(n2703) );
NAND2X1TS U4329 ( .A(n4227), .B(n4330), .Y(n2699) );
XOR2X1TS U4330 ( .A(n2701), .B(n2700), .Y(DP_OP_168J30_122_4811_n1181) );
NOR2BX1TS U4331 ( .AN(n2704), .B(n2703), .Y(n2724) );
OAI21X1TS U4332 ( .A0(n835), .A1(n4408), .B0(n2705), .Y(n2706) );
XOR2X1TS U4333 ( .A(n2706), .B(n2700), .Y(DP_OP_168J30_122_4811_n1183) );
XOR2X1TS U4334 ( .A(n2708), .B(n2700), .Y(DP_OP_168J30_122_4811_n1184) );
XOR2X1TS U4335 ( .A(n2710), .B(n2700), .Y(DP_OP_168J30_122_4811_n1185) );
AOI222X1TS U4336 ( .A0(n4608), .A1(n4332), .B0(n4607), .B1(n4331), .C0(n4327), .C1(n4330), .Y(n2711) );
XOR2X1TS U4337 ( .A(n2712), .B(n2700), .Y(DP_OP_168J30_122_4811_n1186) );
AOI222X1TS U4338 ( .A0(n4607), .A1(n4332), .B0(n4327), .B1(n4331), .C0(n4658), .C1(n4330), .Y(n2713) );
XOR2X1TS U4339 ( .A(n2714), .B(n4410), .Y(DP_OP_168J30_122_4811_n1187) );
AOI222X1TS U4340 ( .A0(n4658), .A1(n4332), .B0(n4544), .B1(n4331), .C0(n4614), .C1(n4330), .Y(n2715) );
OAI21X1TS U4341 ( .A0(n928), .A1(n2695), .B0(n2715), .Y(n2716) );
XOR2X1TS U4342 ( .A(n2716), .B(n4410), .Y(DP_OP_168J30_122_4811_n1189) );
AOI222X1TS U4343 ( .A0(n4550), .A1(n4332), .B0(n4549), .B1(n4331), .C0(n4363), .C1(n4330), .Y(n2717) );
XOR2X1TS U4344 ( .A(n2718), .B(n4410), .Y(DP_OP_168J30_122_4811_n1192) );
AOI222X1TS U4345 ( .A0(n4549), .A1(n4332), .B0(n4363), .B1(n4331), .C0(n4361), .C1(n2721), .Y(n2719) );
XOR2X1TS U4346 ( .A(n2720), .B(n4410), .Y(DP_OP_168J30_122_4811_n1193) );
AOI222X1TS U4347 ( .A0(n4361), .A1(n4332), .B0(n4656), .B1(n4331), .C0(n4655), .C1(n4330), .Y(n2722) );
XOR2X1TS U4348 ( .A(n2723), .B(n4410), .Y(DP_OP_168J30_122_4811_n1195) );
BUFX3TS U4349 ( .A(n2724), .Y(n4405) );
AOI222X1TS U4350 ( .A0(n3910), .A1(n4332), .B0(n4655), .B1(n4331), .C0(n2725), .C1(n4330), .Y(n2726) );
OAI21X1TS U4351 ( .A0(n4163), .A1(n4408), .B0(n2726), .Y(n2727) );
XOR2X1TS U4352 ( .A(n2727), .B(n4410), .Y(DP_OP_168J30_122_4811_n1196) );
OAI21X1TS U4353 ( .A0(n4376), .A1(n4408), .B0(n2729), .Y(n2730) );
XOR2X1TS U4354 ( .A(n2730), .B(n4410), .Y(DP_OP_168J30_122_4811_n1197) );
XOR2X1TS U4355 ( .A(n2732), .B(n4410), .Y(DP_OP_168J30_122_4811_n1198) );
NAND2X1TS U4356 ( .A(n4227), .B(n2734), .Y(n2735) );
XOR2X1TS U4357 ( .A(n2736), .B(n4668), .Y(DP_OP_168J30_122_4811_n1212) );
CLKAND2X2TS U4358 ( .A(n4227), .B(n4312), .Y(n2738) );
AOI21X1TS U4359 ( .A0(n4315), .A1(n2734), .B0(n2738), .Y(n2739) );
XOR2X1TS U4360 ( .A(n2740), .B(n4668), .Y(DP_OP_168J30_122_4811_n1213) );
BUFX3TS U4361 ( .A(n2741), .Y(n4314) );
OAI21X1TS U4362 ( .A0(n835), .A1(n4317), .B0(n2742), .Y(n2743) );
XOR2X1TS U4363 ( .A(n2743), .B(n4668), .Y(DP_OP_168J30_122_4811_n1214) );
OAI21X1TS U4364 ( .A0(n838), .A1(n4317), .B0(n2744), .Y(n2745) );
XOR2X1TS U4365 ( .A(n2745), .B(n4668), .Y(DP_OP_168J30_122_4811_n1216) );
OAI21X1TS U4366 ( .A0(n839), .A1(n4317), .B0(n2746), .Y(n2747) );
XOR2X1TS U4367 ( .A(n2747), .B(n4668), .Y(DP_OP_168J30_122_4811_n1218) );
OAI21X1TS U4368 ( .A0(n4267), .A1(n4317), .B0(n2748), .Y(n2749) );
XOR2X1TS U4369 ( .A(n2749), .B(n4668), .Y(DP_OP_168J30_122_4811_n1221) );
OAI21X1TS U4370 ( .A0(n3835), .A1(n4317), .B0(n2750), .Y(n2751) );
XOR2X1TS U4371 ( .A(n2751), .B(n3769), .Y(DP_OP_168J30_122_4811_n1226) );
XOR2X1TS U4372 ( .A(n2753), .B(n3769), .Y(DP_OP_168J30_122_4811_n1227) );
AOI222X1TS U4373 ( .A0(n4655), .A1(n4271), .B0(n2725), .B1(n4270), .C0(n2728), .C1(n4269), .Y(n2754) );
XOR2X1TS U4374 ( .A(n2755), .B(n3769), .Y(DP_OP_168J30_122_4811_n1228) );
AOI222X1TS U4375 ( .A0(n2725), .A1(n4271), .B0(n2728), .B1(n4270), .C0(n4603), .C1(n4269), .Y(n2756) );
OAI21X1TS U4376 ( .A0(n4221), .A1(n2733), .B0(n2756), .Y(n2757) );
XOR2X1TS U4377 ( .A(n2757), .B(n3769), .Y(DP_OP_168J30_122_4811_n1229) );
AOI222X1TS U4378 ( .A0(n2728), .A1(n4271), .B0(n4603), .B1(n4270), .C0(n4380), .C1(n4269), .Y(n2758) );
OAI21X1TS U4379 ( .A0(n4253), .A1(n2733), .B0(n2758), .Y(n2759) );
XOR2X1TS U4380 ( .A(n2759), .B(n3769), .Y(DP_OP_168J30_122_4811_n1230) );
XOR2X1TS U4381 ( .A(n2761), .B(n3769), .Y(DP_OP_168J30_122_4811_n1232) );
BUFX4TS U4382 ( .A(Op_MY[20]), .Y(n3058) );
CLKAND2X2TS U4383 ( .A(n2848), .B(n3058), .Y(n2762) );
BUFX4TS U4384 ( .A(Op_MY[18]), .Y(n3064) );
CLKAND2X2TS U4385 ( .A(n2830), .B(n3064), .Y(n2763) );
CMPR32X2TS U4386 ( .A(n2762), .B(n854), .C(n2763), .CO(
DP_OP_168J30_122_4811_n2221), .S(DP_OP_168J30_122_4811_n2222) );
INVX2TS U4387 ( .A(n2763), .Y(n2771) );
BUFX6TS U4388 ( .A(Op_MY[19]), .Y(n3061) );
CLKAND2X2TS U4389 ( .A(n2830), .B(n3061), .Y(n2769) );
BUFX4TS U4390 ( .A(n2785), .Y(n2854) );
AOI222X1TS U4391 ( .A0(n2854), .A1(Op_MY[21]), .B0(n2850), .B1(n3058), .C0(
n2787), .C1(n3061), .Y(n2766) );
XOR2X1TS U4392 ( .A(n2767), .B(n2848), .Y(n2770) );
CMPR32X2TS U4393 ( .A(n2771), .B(n2769), .C(n2768), .CO(
DP_OP_168J30_122_4811_n2226), .S(DP_OP_168J30_122_4811_n2227) );
CMPR32X2TS U4394 ( .A(DP_OP_168J30_122_4811_n2239), .B(n2771), .C(n2770),
.CO(n2768), .S(DP_OP_168J30_122_4811_n2234) );
CLKAND2X2TS U4395 ( .A(n2830), .B(Op_MY[14]), .Y(n2772) );
CLKAND2X2TS U4396 ( .A(n2830), .B(Op_MY[12]), .Y(n2773) );
CMPR32X2TS U4397 ( .A(n2772), .B(n858), .C(n2773), .CO(
DP_OP_168J30_122_4811_n2264), .S(DP_OP_168J30_122_4811_n2265) );
INVX2TS U4398 ( .A(n2773), .Y(n2781) );
CLKAND2X2TS U4399 ( .A(n2830), .B(Op_MY[13]), .Y(n2777) );
AOI222X1TS U4400 ( .A0(n2854), .A1(Op_MY[16]), .B0(n2850), .B1(Op_MY[15]),
.C0(n2787), .C1(Op_MY[14]), .Y(n2774) );
XOR2X1TS U4401 ( .A(n2775), .B(n2848), .Y(n2776) );
CMPR32X2TS U4402 ( .A(n2781), .B(n2777), .C(n2776), .CO(
DP_OP_168J30_122_4811_n2272), .S(DP_OP_168J30_122_4811_n2273) );
AOI222X1TS U4403 ( .A0(n2854), .A1(Op_MY[15]), .B0(n2850), .B1(Op_MY[14]),
.C0(n2787), .C1(Op_MY[13]), .Y(n2778) );
XOR2X1TS U4404 ( .A(n2779), .B(n2848), .Y(n2780) );
CMPR32X2TS U4405 ( .A(DP_OP_168J30_122_4811_n2291), .B(n2781), .C(n2780),
.CO(DP_OP_168J30_122_4811_n2282), .S(DP_OP_168J30_122_4811_n2283) );
CLKAND2X2TS U4406 ( .A(n2830), .B(Op_MY[6]), .Y(n2783) );
CLKAND2X2TS U4407 ( .A(n2830), .B(Op_MY[8]), .Y(n2782) );
CMPR32X2TS U4408 ( .A(n2783), .B(n857), .C(n2782), .CO(
DP_OP_168J30_122_4811_n2325), .S(DP_OP_168J30_122_4811_n2326) );
INVX2TS U4409 ( .A(n2783), .Y(n2795) );
CLKAND2X2TS U4410 ( .A(n2830), .B(Op_MY[7]), .Y(n2791) );
BUFX3TS U4411 ( .A(n2786), .Y(n2872) );
BUFX3TS U4412 ( .A(n2787), .Y(n2871) );
AOI222X1TS U4413 ( .A0(n2785), .A1(Op_MY[10]), .B0(n2872), .B1(Op_MY[9]),
.C0(n2871), .C1(Op_MY[8]), .Y(n2788) );
BUFX4TS U4414 ( .A(Op_MX[26]), .Y(n2874) );
XOR2X1TS U4415 ( .A(n2789), .B(n2874), .Y(n2790) );
CMPR32X2TS U4416 ( .A(n2795), .B(n2791), .C(n2790), .CO(
DP_OP_168J30_122_4811_n2336), .S(DP_OP_168J30_122_4811_n2337) );
AOI222X1TS U4417 ( .A0(n2785), .A1(Op_MY[9]), .B0(n2872), .B1(Op_MY[8]),
.C0(n2871), .C1(Op_MY[7]), .Y(n2792) );
XOR2X1TS U4418 ( .A(n2793), .B(n2874), .Y(n2794) );
CMPR32X2TS U4419 ( .A(DP_OP_168J30_122_4811_n2361), .B(n2795), .C(n2794),
.CO(DP_OP_168J30_122_4811_n2349), .S(DP_OP_168J30_122_4811_n2350) );
BUFX4TS U4420 ( .A(Op_MY[0]), .Y(n4081) );
AOI222X1TS U4421 ( .A0(n2785), .A1(n4178), .B0(n2872), .B1(n4131), .C0(n2871), .C1(n4081), .Y(n2796) );
XOR2XLTS U4422 ( .A(n2797), .B(n2874), .Y(n3901) );
INVX2TS U4423 ( .A(n2798), .Y(n2799) );
XOR2XLTS U4424 ( .A(n2800), .B(n2874), .Y(n2809) );
NAND2X1TS U4425 ( .A(n2785), .B(n4081), .Y(n2801) );
XOR2X1TS U4426 ( .A(n2802), .B(n2874), .Y(n2814) );
XNOR2X2TS U4427 ( .A(Op_MX[21]), .B(Op_MX[20]), .Y(n2805) );
CLKXOR2X2TS U4428 ( .A(Op_MX[23]), .B(Op_MX[22]), .Y(n2803) );
NAND2BX4TS U4429 ( .AN(n2805), .B(n2803), .Y(n2876) );
NOR2X2TS U4430 ( .A(n2805), .B(n2803), .Y(n2884) );
XNOR2X1TS U4431 ( .A(Op_MX[21]), .B(Op_MX[22]), .Y(n2804) );
NOR2BX2TS U4432 ( .AN(n2805), .B(n2804), .Y(n2880) );
AOI222X1TS U4433 ( .A0(n2913), .A1(Op_MY[5]), .B0(n2910), .B1(Op_MY[4]),
.C0(n2907), .C1(Op_MY[3]), .Y(n2806) );
XOR2X1TS U4434 ( .A(n2807), .B(n2930), .Y(n2822) );
AOI222X1TS U4435 ( .A0(n2913), .A1(Op_MY[4]), .B0(n2910), .B1(Op_MY[3]),
.C0(n2907), .C1(n4178), .Y(n2810) );
XOR2X1TS U4436 ( .A(n2811), .B(n2930), .Y(n2825) );
AOI222X1TS U4437 ( .A0(n2913), .A1(Op_MY[3]), .B0(n2910), .B1(n4178), .C0(
n2907), .C1(n4131), .Y(n2812) );
XOR2X1TS U4438 ( .A(n2813), .B(n2930), .Y(n2829) );
ADDHXLTS U4439 ( .A(n2848), .B(n2814), .CO(n2808), .S(n2828) );
AOI222X1TS U4440 ( .A0(n2913), .A1(n4178), .B0(n2910), .B1(n4131), .C0(n2877), .C1(n4081), .Y(n2815) );
OAI21XLTS U4441 ( .A0(n2929), .A1(n4083), .B0(n2817), .Y(n2818) );
XOR2X1TS U4442 ( .A(n2818), .B(n2930), .Y(n3899) );
NAND2X1TS U4443 ( .A(n2884), .B(n4081), .Y(n2819) );
XOR2X1TS U4444 ( .A(n2820), .B(n2930), .Y(n4109) );
CMPR32X2TS U4445 ( .A(n2823), .B(n2822), .C(n2821), .CO(
DP_OP_168J30_122_4811_n2433), .S(DP_OP_168J30_122_4811_n2434) );
CMPR32X2TS U4446 ( .A(n2826), .B(n2825), .C(n2824), .CO(n2821), .S(
DP_OP_168J30_122_4811_n2447) );
CMPR32X2TS U4447 ( .A(n2829), .B(n2828), .C(n2827), .CO(n2824), .S(
DP_OP_168J30_122_4811_n2460) );
CLKAND2X2TS U4448 ( .A(n2830), .B(Op_MY[23]), .Y(DP_OP_168J30_122_4811_n2607) );
CLKAND2X2TS U4449 ( .A(n2830), .B(Op_MY[22]), .Y(DP_OP_168J30_122_4811_n2608) );
CLKAND2X2TS U4450 ( .A(n2830), .B(Op_MY[17]), .Y(DP_OP_168J30_122_4811_n2613) );
CLKAND2X2TS U4451 ( .A(n2830), .B(Op_MY[11]), .Y(DP_OP_168J30_122_4811_n2619) );
CLKAND2X2TS U4452 ( .A(n2830), .B(Op_MY[5]), .Y(DP_OP_168J30_122_4811_n2625)
);
CLKAND2X2TS U4453 ( .A(n2830), .B(Op_MY[4]), .Y(DP_OP_168J30_122_4811_n2626)
);
CLKAND2X2TS U4454 ( .A(n2830), .B(Op_MY[3]), .Y(DP_OP_168J30_122_4811_n2627)
);
CLKAND2X2TS U4455 ( .A(n2830), .B(Op_MY[2]), .Y(DP_OP_168J30_122_4811_n2628)
);
CLKAND2X2TS U4456 ( .A(n2830), .B(Op_MY[1]), .Y(DP_OP_168J30_122_4811_n2629)
);
CLKAND2X2TS U4457 ( .A(n2830), .B(n4081), .Y(DP_OP_168J30_122_4811_n2630) );
AOI222X1TS U4458 ( .A0(n2854), .A1(n3152), .B0(n2850), .B1(Op_MY[25]), .C0(
n2787), .C1(Op_MY[24]), .Y(n2831) );
XOR2X1TS U4459 ( .A(n2832), .B(n2848), .Y(DP_OP_168J30_122_4811_n2734) );
AOI222X1TS U4460 ( .A0(n2854), .A1(Op_MY[25]), .B0(n2850), .B1(Op_MY[24]),
.C0(n2787), .C1(Op_MY[23]), .Y(n2833) );
XOR2X1TS U4461 ( .A(n2834), .B(n2848), .Y(DP_OP_168J30_122_4811_n2735) );
AOI222X1TS U4462 ( .A0(n2854), .A1(Op_MY[24]), .B0(n2850), .B1(Op_MY[23]),
.C0(n2787), .C1(Op_MY[22]), .Y(n2835) );
XOR2X1TS U4463 ( .A(n2836), .B(n2848), .Y(DP_OP_168J30_122_4811_n2736) );
AOI222X1TS U4464 ( .A0(n2854), .A1(Op_MY[23]), .B0(n2850), .B1(Op_MY[22]),
.C0(n2787), .C1(Op_MY[21]), .Y(n2837) );
XOR2X1TS U4465 ( .A(n2838), .B(n2848), .Y(DP_OP_168J30_122_4811_n2737) );
AOI222X1TS U4466 ( .A0(n2854), .A1(Op_MY[22]), .B0(n2850), .B1(Op_MY[21]),
.C0(n2787), .C1(n3058), .Y(n2839) );
XOR2X1TS U4467 ( .A(n2840), .B(n2848), .Y(DP_OP_168J30_122_4811_n2738) );
AOI222X1TS U4468 ( .A0(n2854), .A1(n3058), .B0(n2850), .B1(n3061), .C0(n2787), .C1(n3064), .Y(n2841) );
XOR2X1TS U4469 ( .A(n2842), .B(n2848), .Y(DP_OP_168J30_122_4811_n2740) );
AOI222X1TS U4470 ( .A0(n2854), .A1(n3061), .B0(n2850), .B1(n3064), .C0(n2787), .C1(Op_MY[17]), .Y(n2843) );
XOR2X1TS U4471 ( .A(n2844), .B(n2848), .Y(DP_OP_168J30_122_4811_n2741) );
AOI222X1TS U4472 ( .A0(n2854), .A1(n3064), .B0(n2850), .B1(Op_MY[17]), .C0(
n2787), .C1(Op_MY[16]), .Y(n2845) );
XOR2X1TS U4473 ( .A(n2846), .B(n2848), .Y(DP_OP_168J30_122_4811_n2742) );
AOI222X1TS U4474 ( .A0(n2854), .A1(Op_MY[17]), .B0(n2850), .B1(Op_MY[16]),
.C0(n2787), .C1(Op_MY[15]), .Y(n2847) );
XOR2X1TS U4475 ( .A(n2849), .B(n2848), .Y(DP_OP_168J30_122_4811_n2743) );
AOI222X1TS U4476 ( .A0(n2854), .A1(Op_MY[14]), .B0(n2850), .B1(Op_MY[13]),
.C0(n2871), .C1(Op_MY[12]), .Y(n2851) );
XOR2X1TS U4477 ( .A(n2853), .B(n2874), .Y(DP_OP_168J30_122_4811_n2746) );
AOI222X1TS U4478 ( .A0(n2854), .A1(Op_MY[13]), .B0(n2872), .B1(Op_MY[12]),
.C0(n2871), .C1(Op_MY[11]), .Y(n2855) );
XOR2X1TS U4479 ( .A(n2856), .B(n2874), .Y(DP_OP_168J30_122_4811_n2747) );
AOI222X1TS U4480 ( .A0(n2785), .A1(Op_MY[12]), .B0(n2872), .B1(Op_MY[11]),
.C0(n2871), .C1(Op_MY[10]), .Y(n2857) );
XOR2X1TS U4481 ( .A(n2858), .B(n2874), .Y(DP_OP_168J30_122_4811_n2748) );
AOI222X1TS U4482 ( .A0(n2785), .A1(Op_MY[11]), .B0(n2872), .B1(Op_MY[10]),
.C0(n2871), .C1(Op_MY[9]), .Y(n2859) );
XOR2X1TS U4483 ( .A(n2860), .B(n2874), .Y(DP_OP_168J30_122_4811_n2749) );
AOI222X1TS U4484 ( .A0(n2785), .A1(Op_MY[8]), .B0(n2872), .B1(Op_MY[7]),
.C0(n2871), .C1(Op_MY[6]), .Y(n2861) );
XOR2XLTS U4485 ( .A(n2862), .B(n2874), .Y(DP_OP_168J30_122_4811_n2752) );
AOI222X1TS U4486 ( .A0(n2785), .A1(Op_MY[7]), .B0(n2872), .B1(Op_MY[6]),
.C0(n2871), .C1(Op_MY[5]), .Y(n2863) );
XOR2X1TS U4487 ( .A(n2864), .B(n2874), .Y(DP_OP_168J30_122_4811_n2753) );
AOI222X1TS U4488 ( .A0(n2785), .A1(Op_MY[6]), .B0(n2872), .B1(Op_MY[5]),
.C0(n2871), .C1(Op_MY[4]), .Y(n2865) );
XOR2X1TS U4489 ( .A(n2866), .B(n2874), .Y(DP_OP_168J30_122_4811_n2754) );
AOI222X1TS U4490 ( .A0(n2785), .A1(n4196), .B0(n2872), .B1(n4139), .C0(n2871), .C1(Op_MY[3]), .Y(n2867) );
XOR2X1TS U4491 ( .A(n2868), .B(n2874), .Y(DP_OP_168J30_122_4811_n2755) );
AOI222X1TS U4492 ( .A0(n2785), .A1(Op_MY[4]), .B0(n2872), .B1(Op_MY[3]),
.C0(n2871), .C1(Op_MY[2]), .Y(n2869) );
XOR2X1TS U4493 ( .A(n2870), .B(n2874), .Y(DP_OP_168J30_122_4811_n2756) );
AOI222X1TS U4494 ( .A0(n2785), .A1(Op_MY[3]), .B0(n2872), .B1(Op_MY[2]),
.C0(n2871), .C1(Op_MY[1]), .Y(n2873) );
XOR2X1TS U4495 ( .A(n2875), .B(n2874), .Y(DP_OP_168J30_122_4811_n2757) );
NAND2X1TS U4496 ( .A(n2907), .B(n3152), .Y(n2878) );
XOR2X1TS U4497 ( .A(n2879), .B(Op_MX[23]), .Y(DP_OP_168J30_122_4811_n2762)
);
BUFX6TS U4498 ( .A(n2880), .Y(n2910) );
CLKAND2X2TS U4499 ( .A(n2910), .B(n3152), .Y(n2881) );
AOI21X1TS U4500 ( .A0(n2907), .A1(Op_MY[25]), .B0(n2881), .Y(n2882) );
XOR2X1TS U4501 ( .A(n2883), .B(Op_MX[23]), .Y(DP_OP_168J30_122_4811_n2763)
);
BUFX6TS U4502 ( .A(n2884), .Y(n2913) );
AOI222X1TS U4503 ( .A0(n2913), .A1(n3152), .B0(n2910), .B1(Op_MY[25]), .C0(
n2907), .C1(Op_MY[24]), .Y(n2885) );
XOR2X1TS U4504 ( .A(n2886), .B(Op_MX[23]), .Y(DP_OP_168J30_122_4811_n2764)
);
AOI222X1TS U4505 ( .A0(n2913), .A1(Op_MY[25]), .B0(n2910), .B1(Op_MY[24]),
.C0(n2907), .C1(Op_MY[23]), .Y(n2887) );
XOR2X1TS U4506 ( .A(n2888), .B(Op_MX[23]), .Y(DP_OP_168J30_122_4811_n2765)
);
AOI222X1TS U4507 ( .A0(n2913), .A1(Op_MY[24]), .B0(n2910), .B1(Op_MY[23]),
.C0(n2907), .C1(Op_MY[22]), .Y(n2889) );
XOR2X1TS U4508 ( .A(n2890), .B(Op_MX[23]), .Y(DP_OP_168J30_122_4811_n2766)
);
AOI222X1TS U4509 ( .A0(n2913), .A1(Op_MY[23]), .B0(n2910), .B1(Op_MY[22]),
.C0(n2907), .C1(Op_MY[21]), .Y(n2891) );
XOR2X1TS U4510 ( .A(n2892), .B(n2930), .Y(DP_OP_168J30_122_4811_n2767) );
AOI222X1TS U4511 ( .A0(n2913), .A1(Op_MY[22]), .B0(n2910), .B1(Op_MY[21]),
.C0(n2907), .C1(n3058), .Y(n2893) );
XOR2X1TS U4512 ( .A(n2894), .B(n2930), .Y(DP_OP_168J30_122_4811_n2768) );
AOI222X1TS U4513 ( .A0(n2913), .A1(Op_MY[21]), .B0(n2910), .B1(n3058), .C0(
n2907), .C1(n3061), .Y(n2895) );
XOR2X1TS U4514 ( .A(n2896), .B(n2930), .Y(DP_OP_168J30_122_4811_n2769) );
AOI222X1TS U4515 ( .A0(n2913), .A1(n3058), .B0(n2910), .B1(n3061), .C0(n2907), .C1(n3064), .Y(n2897) );
XOR2X1TS U4516 ( .A(n2898), .B(n2930), .Y(DP_OP_168J30_122_4811_n2770) );
AOI222X1TS U4517 ( .A0(n2913), .A1(n3061), .B0(n2910), .B1(n3064), .C0(n2907), .C1(Op_MY[17]), .Y(n2899) );
XOR2X1TS U4518 ( .A(n2900), .B(n2930), .Y(DP_OP_168J30_122_4811_n2771) );
AOI222X1TS U4519 ( .A0(n2913), .A1(n3064), .B0(n2910), .B1(Op_MY[17]), .C0(
n2907), .C1(Op_MY[16]), .Y(n2901) );
XOR2X1TS U4520 ( .A(n2902), .B(n2930), .Y(DP_OP_168J30_122_4811_n2772) );
AOI222X1TS U4521 ( .A0(n2913), .A1(Op_MY[17]), .B0(n2910), .B1(Op_MY[16]),
.C0(n2907), .C1(Op_MY[15]), .Y(n2903) );
XOR2X1TS U4522 ( .A(n2904), .B(n2930), .Y(DP_OP_168J30_122_4811_n2773) );
AOI222X1TS U4523 ( .A0(n2913), .A1(Op_MY[16]), .B0(n2910), .B1(Op_MY[15]),
.C0(n2907), .C1(Op_MY[14]), .Y(n2905) );
XOR2X1TS U4524 ( .A(n2906), .B(n2930), .Y(DP_OP_168J30_122_4811_n2774) );
AOI222X1TS U4525 ( .A0(n2913), .A1(Op_MY[15]), .B0(n2910), .B1(Op_MY[14]),
.C0(n2907), .C1(Op_MY[13]), .Y(n2908) );
XOR2X1TS U4526 ( .A(n2909), .B(n2930), .Y(DP_OP_168J30_122_4811_n2775) );
AOI222X1TS U4527 ( .A0(n2913), .A1(Op_MY[14]), .B0(n2910), .B1(Op_MY[13]),
.C0(n2877), .C1(Op_MY[12]), .Y(n2911) );
XOR2XLTS U4528 ( .A(n2912), .B(n2930), .Y(DP_OP_168J30_122_4811_n2776) );
AOI222X1TS U4529 ( .A0(n2913), .A1(Op_MY[13]), .B0(n2910), .B1(Op_MY[12]),
.C0(n2907), .C1(Op_MY[11]), .Y(n2914) );
XOR2X1TS U4530 ( .A(n2915), .B(n2930), .Y(DP_OP_168J30_122_4811_n2777) );
AOI222X1TS U4531 ( .A0(n2913), .A1(Op_MY[12]), .B0(n2910), .B1(Op_MY[11]),
.C0(n2907), .C1(Op_MY[10]), .Y(n2916) );
XOR2X1TS U4532 ( .A(n2917), .B(n2930), .Y(DP_OP_168J30_122_4811_n2778) );
AOI222X1TS U4533 ( .A0(n2913), .A1(Op_MY[11]), .B0(n2880), .B1(Op_MY[10]),
.C0(n2907), .C1(Op_MY[9]), .Y(n2918) );
XOR2X1TS U4534 ( .A(n2919), .B(n2930), .Y(DP_OP_168J30_122_4811_n2779) );
AOI222X1TS U4535 ( .A0(n2913), .A1(Op_MY[10]), .B0(n2910), .B1(Op_MY[9]),
.C0(n2907), .C1(Op_MY[8]), .Y(n2920) );
OAI21XLTS U4536 ( .A0(n4418), .A1(n2929), .B0(n2920), .Y(n2921) );
XOR2X1TS U4537 ( .A(n2921), .B(n2930), .Y(DP_OP_168J30_122_4811_n2780) );
AOI222X1TS U4538 ( .A0(n2913), .A1(Op_MY[9]), .B0(n2880), .B1(Op_MY[8]),
.C0(n2907), .C1(Op_MY[7]), .Y(n2922) );
OAI21XLTS U4539 ( .A0(n4358), .A1(n2929), .B0(n2922), .Y(n2923) );
XOR2X1TS U4540 ( .A(n2923), .B(n2930), .Y(DP_OP_168J30_122_4811_n2781) );
AOI222X1TS U4541 ( .A0(n2913), .A1(n4415), .B0(n2880), .B1(n4356), .C0(n2907), .C1(Op_MY[6]), .Y(n2924) );
XOR2XLTS U4542 ( .A(n2925), .B(n2930), .Y(DP_OP_168J30_122_4811_n2782) );
AOI222X1TS U4543 ( .A0(n2913), .A1(Op_MY[7]), .B0(n2910), .B1(Op_MY[6]),
.C0(n2907), .C1(Op_MY[5]), .Y(n2926) );
XOR2X1TS U4544 ( .A(n2927), .B(n2930), .Y(DP_OP_168J30_122_4811_n2783) );
AOI222X1TS U4545 ( .A0(n2913), .A1(Op_MY[6]), .B0(n2910), .B1(Op_MY[5]),
.C0(n2907), .C1(Op_MY[4]), .Y(n2928) );
XOR2X1TS U4546 ( .A(n2931), .B(n2930), .Y(DP_OP_168J30_122_4811_n2784) );
XNOR2X2TS U4547 ( .A(Op_MX[17]), .B(Op_MX[18]), .Y(n2939) );
CLKXOR2X2TS U4548 ( .A(Op_MX[19]), .B(Op_MX[20]), .Y(n2938) );
NAND2BX4TS U4549 ( .AN(n2939), .B(n2938), .Y(n2970) );
XNOR2X1TS U4550 ( .A(Op_MX[19]), .B(Op_MX[18]), .Y(n2934) );
NAND2X1TS U4551 ( .A(n2962), .B(n3152), .Y(n2932) );
XOR2X1TS U4552 ( .A(n2933), .B(Op_MX[20]), .Y(DP_OP_168J30_122_4811_n2792)
);
NOR2BX2TS U4553 ( .AN(n2939), .B(n2934), .Y(n2971) );
BUFX6TS U4554 ( .A(n2971), .Y(n2966) );
CLKAND2X2TS U4555 ( .A(n2966), .B(n3152), .Y(n2935) );
AOI21X1TS U4556 ( .A0(n2962), .A1(Op_MY[25]), .B0(n2935), .Y(n2936) );
XOR2X1TS U4557 ( .A(n2937), .B(Op_MX[20]), .Y(DP_OP_168J30_122_4811_n2793)
);
NOR2X2TS U4558 ( .A(n2939), .B(n2938), .Y(n2975) );
BUFX6TS U4559 ( .A(n2975), .Y(n2972) );
AOI222X1TS U4560 ( .A0(n2972), .A1(n3152), .B0(n2966), .B1(Op_MY[25]), .C0(
n2962), .C1(Op_MY[24]), .Y(n2940) );
XOR2X1TS U4561 ( .A(n2941), .B(Op_MX[20]), .Y(DP_OP_168J30_122_4811_n2794)
);
AOI222X1TS U4562 ( .A0(n2972), .A1(Op_MY[25]), .B0(n2966), .B1(Op_MY[24]),
.C0(n2962), .C1(Op_MY[23]), .Y(n2942) );
XOR2X1TS U4563 ( .A(n2943), .B(Op_MX[20]), .Y(DP_OP_168J30_122_4811_n2795)
);
AOI222X1TS U4564 ( .A0(n2972), .A1(n3792), .B0(n2966), .B1(Op_MY[23]), .C0(
n2962), .C1(Op_MY[22]), .Y(n2944) );
XOR2X1TS U4565 ( .A(n2945), .B(Op_MX[20]), .Y(DP_OP_168J30_122_4811_n2796)
);
AOI222X1TS U4566 ( .A0(n2972), .A1(Op_MY[23]), .B0(n2966), .B1(Op_MY[22]),
.C0(n2962), .C1(Op_MY[21]), .Y(n2946) );
XOR2X1TS U4567 ( .A(n2947), .B(n4296), .Y(DP_OP_168J30_122_4811_n2797) );
AOI222X1TS U4568 ( .A0(n2972), .A1(n3778), .B0(n2966), .B1(Op_MY[21]), .C0(
n2962), .C1(n3058), .Y(n2948) );
XOR2X1TS U4569 ( .A(n2949), .B(n4296), .Y(DP_OP_168J30_122_4811_n2798) );
AOI222X1TS U4570 ( .A0(n2972), .A1(n4459), .B0(n2966), .B1(n3058), .C0(n2962), .C1(n3061), .Y(n2950) );
XOR2X1TS U4571 ( .A(n2951), .B(n4296), .Y(DP_OP_168J30_122_4811_n2799) );
AOI222X1TS U4572 ( .A0(n2972), .A1(n3058), .B0(n2966), .B1(n3061), .C0(n2962), .C1(n3064), .Y(n2952) );
XOR2X1TS U4573 ( .A(n2953), .B(n4296), .Y(DP_OP_168J30_122_4811_n2800) );
AOI222X1TS U4574 ( .A0(n2972), .A1(n3061), .B0(n2966), .B1(n3064), .C0(n2962), .C1(Op_MY[17]), .Y(n2954) );
XOR2X1TS U4575 ( .A(n2955), .B(n4296), .Y(DP_OP_168J30_122_4811_n2801) );
AOI222X1TS U4576 ( .A0(n2972), .A1(n3064), .B0(n2966), .B1(Op_MY[17]), .C0(
n2962), .C1(Op_MY[16]), .Y(n2956) );
XOR2X1TS U4577 ( .A(n2957), .B(n4296), .Y(DP_OP_168J30_122_4811_n2802) );
AOI222X1TS U4578 ( .A0(n2972), .A1(n4516), .B0(n2966), .B1(n4514), .C0(n2962), .C1(Op_MY[15]), .Y(n2958) );
XOR2X1TS U4579 ( .A(n2959), .B(n4296), .Y(DP_OP_168J30_122_4811_n2803) );
AOI222X1TS U4580 ( .A0(n2972), .A1(Op_MY[16]), .B0(n2966), .B1(Op_MY[15]),
.C0(n2962), .C1(Op_MY[14]), .Y(n2960) );
OAI21XLTS U4581 ( .A0(n3801), .A1(n2968), .B0(n2960), .Y(n2961) );
XOR2X1TS U4582 ( .A(n2961), .B(n4296), .Y(DP_OP_168J30_122_4811_n2804) );
AOI222X1TS U4583 ( .A0(n2972), .A1(n4463), .B0(n2966), .B1(n4453), .C0(n2962), .C1(Op_MY[13]), .Y(n2963) );
XOR2X1TS U4584 ( .A(n2964), .B(n4296), .Y(DP_OP_168J30_122_4811_n2805) );
AOI222X1TS U4585 ( .A0(n2972), .A1(n4453), .B0(n2966), .B1(Op_MY[13]), .C0(
n2965), .C1(Op_MY[12]), .Y(n2967) );
OAI21XLTS U4586 ( .A0(n4455), .A1(n2968), .B0(n2967), .Y(n2969) );
XOR2XLTS U4587 ( .A(n2969), .B(n4296), .Y(DP_OP_168J30_122_4811_n2806) );
AOI222X1TS U4588 ( .A0(n2972), .A1(n4452), .B0(n2966), .B1(Op_MY[12]), .C0(
n2962), .C1(Op_MY[11]), .Y(n2973) );
OAI21XLTS U4589 ( .A0(n4446), .A1(n2970), .B0(n2973), .Y(n2974) );
XOR2X1TS U4590 ( .A(n2974), .B(n4296), .Y(DP_OP_168J30_122_4811_n2807) );
AOI222X1TS U4591 ( .A0(n2972), .A1(Op_MY[12]), .B0(n2966), .B1(Op_MY[11]),
.C0(n2962), .C1(Op_MY[10]), .Y(n2976) );
OAI21XLTS U4592 ( .A0(n4441), .A1(n2970), .B0(n2976), .Y(n2977) );
XOR2X1TS U4593 ( .A(n2977), .B(n4296), .Y(DP_OP_168J30_122_4811_n2808) );
AOI222X1TS U4594 ( .A0(n2972), .A1(n4443), .B0(n2966), .B1(Op_MY[10]), .C0(
n2962), .C1(Op_MY[9]), .Y(n2978) );
OAI21XLTS U4595 ( .A0(n4436), .A1(n2970), .B0(n2978), .Y(n2979) );
XOR2X1TS U4596 ( .A(n2979), .B(n4296), .Y(DP_OP_168J30_122_4811_n2809) );
AOI222X1TS U4597 ( .A0(n2972), .A1(Op_MY[10]), .B0(n2966), .B1(Op_MY[9]),
.C0(n2962), .C1(Op_MY[8]), .Y(n2980) );
OAI21XLTS U4598 ( .A0(n4418), .A1(n2970), .B0(n2980), .Y(n2981) );
XOR2X1TS U4599 ( .A(n2981), .B(n4296), .Y(DP_OP_168J30_122_4811_n2810) );
AOI222X1TS U4600 ( .A0(n2972), .A1(Op_MY[9]), .B0(n2966), .B1(Op_MY[8]),
.C0(n2962), .C1(Op_MY[7]), .Y(n2982) );
OAI21XLTS U4601 ( .A0(n4358), .A1(n2970), .B0(n2982), .Y(n2983) );
XOR2X1TS U4602 ( .A(n2983), .B(n4296), .Y(DP_OP_168J30_122_4811_n2811) );
AOI222X1TS U4603 ( .A0(n2972), .A1(Op_MY[8]), .B0(n2966), .B1(Op_MY[7]),
.C0(n2962), .C1(Op_MY[6]), .Y(n2984) );
OAI21XLTS U4604 ( .A0(n4395), .A1(n2970), .B0(n2984), .Y(n2985) );
XOR2X1TS U4605 ( .A(n2985), .B(n4296), .Y(DP_OP_168J30_122_4811_n2812) );
AOI222X1TS U4606 ( .A0(n2972), .A1(Op_MY[7]), .B0(n2966), .B1(Op_MY[6]),
.C0(n2962), .C1(Op_MY[5]), .Y(n2986) );
OAI21XLTS U4607 ( .A0(n4354), .A1(n2970), .B0(n2986), .Y(n2987) );
XOR2X1TS U4608 ( .A(n2987), .B(n4296), .Y(DP_OP_168J30_122_4811_n2813) );
AOI222X1TS U4609 ( .A0(n2972), .A1(n4309), .B0(n2966), .B1(Op_MY[5]), .C0(
n2962), .C1(Op_MY[4]), .Y(n2988) );
XOR2X1TS U4610 ( .A(n2989), .B(n4296), .Y(DP_OP_168J30_122_4811_n2814) );
XNOR2X2TS U4611 ( .A(Op_MX[15]), .B(Op_MX[14]), .Y(n2997) );
CLKXOR2X2TS U4612 ( .A(Op_MX[17]), .B(Op_MX[16]), .Y(n2996) );
XNOR2X1TS U4613 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n2992) );
NAND2X1TS U4614 ( .A(n3020), .B(n3152), .Y(n2990) );
XOR2X1TS U4615 ( .A(n2991), .B(n4670), .Y(DP_OP_168J30_122_4811_n2822) );
NOR2BX1TS U4616 ( .AN(n2997), .B(n2992), .Y(n3029) );
CLKAND2X2TS U4617 ( .A(n3024), .B(n3152), .Y(n2993) );
AOI21X1TS U4618 ( .A0(n3020), .A1(n3793), .B0(n2993), .Y(n2994) );
XOR2X1TS U4619 ( .A(n2995), .B(n4670), .Y(DP_OP_168J30_122_4811_n2823) );
NOR2X2TS U4620 ( .A(n2997), .B(n2996), .Y(n4067) );
BUFX6TS U4621 ( .A(n4067), .Y(n4393) );
AOI222X1TS U4622 ( .A0(n4393), .A1(n3152), .B0(n3024), .B1(n3793), .C0(n3020), .C1(Op_MY[24]), .Y(n2998) );
XOR2X1TS U4623 ( .A(n2999), .B(n4670), .Y(DP_OP_168J30_122_4811_n2824) );
AOI222X1TS U4624 ( .A0(n4393), .A1(n3793), .B0(n3024), .B1(n3792), .C0(n3020), .C1(n3784), .Y(n3000) );
XOR2X1TS U4625 ( .A(n3001), .B(n4670), .Y(DP_OP_168J30_122_4811_n2825) );
AOI222X1TS U4626 ( .A0(n4393), .A1(n3792), .B0(n3024), .B1(n3784), .C0(n3020), .C1(Op_MY[22]), .Y(n3002) );
XOR2X1TS U4627 ( .A(n3003), .B(n4670), .Y(DP_OP_168J30_122_4811_n2826) );
AOI222X1TS U4628 ( .A0(n4393), .A1(n3784), .B0(n3024), .B1(n3778), .C0(n3020), .C1(n4459), .Y(n3004) );
XOR2X1TS U4629 ( .A(n3005), .B(n4670), .Y(DP_OP_168J30_122_4811_n2827) );
AOI222X1TS U4630 ( .A0(n4393), .A1(n3778), .B0(n3024), .B1(Op_MY[21]), .C0(
n3020), .C1(n3058), .Y(n3006) );
XOR2X1TS U4631 ( .A(n3007), .B(n4670), .Y(DP_OP_168J30_122_4811_n2828) );
AOI222X1TS U4632 ( .A0(n4393), .A1(n4459), .B0(n3024), .B1(n3058), .C0(n3020), .C1(n3061), .Y(n3008) );
XOR2X1TS U4633 ( .A(n3009), .B(n4670), .Y(DP_OP_168J30_122_4811_n2829) );
AOI222X1TS U4634 ( .A0(n4393), .A1(n3058), .B0(n3024), .B1(n3061), .C0(n3020), .C1(n3064), .Y(n3010) );
XOR2X1TS U4635 ( .A(n3011), .B(n4670), .Y(DP_OP_168J30_122_4811_n2830) );
AOI222X1TS U4636 ( .A0(n4393), .A1(n3061), .B0(n3024), .B1(n3064), .C0(n3020), .C1(Op_MY[17]), .Y(n3012) );
XOR2X1TS U4637 ( .A(n3013), .B(n4670), .Y(DP_OP_168J30_122_4811_n2831) );
AOI222X1TS U4638 ( .A0(n4393), .A1(n3064), .B0(n3024), .B1(n4516), .C0(n3020), .C1(Op_MY[16]), .Y(n3014) );
XOR2X1TS U4639 ( .A(n3015), .B(n4670), .Y(DP_OP_168J30_122_4811_n2832) );
AOI222X1TS U4640 ( .A0(n4393), .A1(n4516), .B0(n3024), .B1(n4514), .C0(n3020), .C1(Op_MY[15]), .Y(n3016) );
XOR2X1TS U4641 ( .A(n3017), .B(n4670), .Y(DP_OP_168J30_122_4811_n2833) );
AOI222X1TS U4642 ( .A0(n4393), .A1(n4514), .B0(n3024), .B1(n4463), .C0(n3020), .C1(Op_MY[14]), .Y(n3018) );
XOR2X1TS U4643 ( .A(n3019), .B(n4670), .Y(DP_OP_168J30_122_4811_n2834) );
AOI222X1TS U4644 ( .A0(n4393), .A1(n4463), .B0(n3024), .B1(Op_MY[14]), .C0(
n3020), .C1(Op_MY[13]), .Y(n3021) );
OAI21XLTS U4645 ( .A0(n3798), .A1(n3026), .B0(n3021), .Y(n3022) );
XOR2X1TS U4646 ( .A(n3022), .B(n4670), .Y(DP_OP_168J30_122_4811_n2835) );
AOI222X1TS U4647 ( .A0(n4393), .A1(n4453), .B0(n3024), .B1(n4452), .C0(n3020), .C1(n4451), .Y(n3025) );
XOR2XLTS U4648 ( .A(n3027), .B(Op_MX[17]), .Y(DP_OP_168J30_122_4811_n2836)
);
BUFX4TS U4649 ( .A(n3029), .Y(n4392) );
AOI222X1TS U4650 ( .A0(n4393), .A1(n4452), .B0(n4392), .B1(n4451), .C0(n3020), .C1(Op_MY[11]), .Y(n3030) );
OAI21XLTS U4651 ( .A0(n4446), .A1(n3028), .B0(n3030), .Y(n3031) );
XOR2X1TS U4652 ( .A(n3031), .B(Op_MX[17]), .Y(DP_OP_168J30_122_4811_n2837)
);
AOI222X1TS U4653 ( .A0(n4393), .A1(n4451), .B0(n4392), .B1(n4443), .C0(n3020), .C1(n4439), .Y(n3032) );
OAI21XLTS U4654 ( .A0(n4441), .A1(n3028), .B0(n3032), .Y(n3033) );
XOR2X1TS U4655 ( .A(n3033), .B(Op_MX[17]), .Y(DP_OP_168J30_122_4811_n2838)
);
AOI222X1TS U4656 ( .A0(n4393), .A1(n4443), .B0(n4392), .B1(n4439), .C0(n3020), .C1(n4432), .Y(n3034) );
OAI21XLTS U4657 ( .A0(n4436), .A1(n3028), .B0(n3034), .Y(n3035) );
XOR2X1TS U4658 ( .A(n3035), .B(Op_MX[17]), .Y(DP_OP_168J30_122_4811_n2839)
);
AOI222X1TS U4659 ( .A0(n4393), .A1(n4439), .B0(n4392), .B1(n4432), .C0(n3020), .C1(n4415), .Y(n3036) );
OAI21XLTS U4660 ( .A0(n4418), .A1(n3026), .B0(n3036), .Y(n3037) );
XOR2X1TS U4661 ( .A(n3037), .B(Op_MX[17]), .Y(DP_OP_168J30_122_4811_n2840)
);
AOI222X1TS U4662 ( .A0(n4393), .A1(n4432), .B0(n4392), .B1(n4415), .C0(n3020), .C1(n4356), .Y(n3038) );
OAI21XLTS U4663 ( .A0(n4358), .A1(n3026), .B0(n3038), .Y(n3039) );
XOR2X1TS U4664 ( .A(n3039), .B(Op_MX[17]), .Y(DP_OP_168J30_122_4811_n2841)
);
AOI222X1TS U4665 ( .A0(n4393), .A1(n4309), .B0(n4392), .B1(n4196), .C0(n3020), .C1(n4139), .Y(n3040) );
OAI21XLTS U4666 ( .A0(n4141), .A1(n3026), .B0(n3040), .Y(n3041) );
XOR2X1TS U4667 ( .A(n3041), .B(n4670), .Y(DP_OP_168J30_122_4811_n2844) );
XNOR2X2TS U4668 ( .A(Op_MX[11]), .B(Op_MX[12]), .Y(n3049) );
CLKXOR2X2TS U4669 ( .A(Op_MX[13]), .B(Op_MX[14]), .Y(n3048) );
NAND2BX4TS U4670 ( .AN(n3049), .B(n3048), .Y(n3078) );
XNOR2X1TS U4671 ( .A(Op_MX[13]), .B(Op_MX[12]), .Y(n3044) );
NAND2X1TS U4672 ( .A(n4513), .B(n3152), .Y(n3042) );
XOR2X1TS U4673 ( .A(n3043), .B(Op_MX[14]), .Y(DP_OP_168J30_122_4811_n2852)
);
NOR2BX2TS U4674 ( .AN(n3049), .B(n3044), .Y(n3079) );
BUFX6TS U4675 ( .A(n3079), .Y(n4515) );
CLKAND2X2TS U4676 ( .A(n4515), .B(n3152), .Y(n3045) );
AOI21X1TS U4677 ( .A0(n4513), .A1(n3793), .B0(n3045), .Y(n3046) );
XOR2X1TS U4678 ( .A(n3047), .B(Op_MX[14]), .Y(DP_OP_168J30_122_4811_n2853)
);
NOR2X2TS U4679 ( .A(n3049), .B(n3048), .Y(n4025) );
BUFX6TS U4680 ( .A(n4025), .Y(n4517) );
AOI222X1TS U4681 ( .A0(n4517), .A1(n3152), .B0(n4515), .B1(n3793), .C0(n4513), .C1(n3792), .Y(n3050) );
XOR2X1TS U4682 ( .A(n3051), .B(Op_MX[14]), .Y(DP_OP_168J30_122_4811_n2854)
);
AOI222X1TS U4683 ( .A0(n4517), .A1(n3793), .B0(n4515), .B1(n3792), .C0(n4513), .C1(n3784), .Y(n3052) );
XOR2X1TS U4684 ( .A(n3053), .B(Op_MX[14]), .Y(DP_OP_168J30_122_4811_n2855)
);
AOI222X1TS U4685 ( .A0(n4517), .A1(n3792), .B0(n4515), .B1(n3784), .C0(n4513), .C1(n3778), .Y(n3054) );
XOR2X1TS U4686 ( .A(n3055), .B(Op_MX[14]), .Y(DP_OP_168J30_122_4811_n2856)
);
AOI222X1TS U4687 ( .A0(n4517), .A1(n3784), .B0(n4515), .B1(n3778), .C0(n4513), .C1(n4459), .Y(n3056) );
XOR2X1TS U4688 ( .A(n3057), .B(n4423), .Y(DP_OP_168J30_122_4811_n2857) );
AOI222X1TS U4689 ( .A0(n4517), .A1(n3778), .B0(n4515), .B1(n4459), .C0(n4513), .C1(n3058), .Y(n3059) );
XOR2X1TS U4690 ( .A(n3060), .B(n4423), .Y(DP_OP_168J30_122_4811_n2858) );
AOI222X1TS U4691 ( .A0(n4517), .A1(n4459), .B0(n4515), .B1(n4458), .C0(n4513), .C1(n3061), .Y(n3062) );
XOR2X1TS U4692 ( .A(n3063), .B(n4423), .Y(DP_OP_168J30_122_4811_n2859) );
AOI222X1TS U4693 ( .A0(n4517), .A1(n4458), .B0(n4515), .B1(Op_MY[19]), .C0(
n4513), .C1(n3064), .Y(n3065) );
XOR2X1TS U4694 ( .A(n3066), .B(n4423), .Y(DP_OP_168J30_122_4811_n2860) );
AOI222X1TS U4695 ( .A0(n4517), .A1(Op_MY[19]), .B0(n4515), .B1(n4470), .C0(
n4513), .C1(n4516), .Y(n3067) );
XOR2X1TS U4696 ( .A(n3068), .B(n4423), .Y(DP_OP_168J30_122_4811_n2861) );
AOI222X1TS U4697 ( .A0(n4517), .A1(n4470), .B0(n4515), .B1(n4516), .C0(n4513), .C1(n4514), .Y(n3069) );
XOR2X1TS U4698 ( .A(n3070), .B(n4423), .Y(DP_OP_168J30_122_4811_n2862) );
AOI222X1TS U4699 ( .A0(n4517), .A1(n4514), .B0(n4515), .B1(n4463), .C0(n4513), .C1(n4453), .Y(n3071) );
OAI21X1TS U4700 ( .A0(n3801), .A1(n4422), .B0(n3071), .Y(n3072) );
XOR2X1TS U4701 ( .A(n3072), .B(n4423), .Y(DP_OP_168J30_122_4811_n2864) );
AOI222X1TS U4702 ( .A0(n4517), .A1(n4463), .B0(n4515), .B1(n4453), .C0(n4513), .C1(n4452), .Y(n3073) );
XOR2X1TS U4703 ( .A(n3074), .B(n4423), .Y(DP_OP_168J30_122_4811_n2865) );
AOI222X1TS U4704 ( .A0(n4517), .A1(n4453), .B0(n4515), .B1(n4452), .C0(n3075), .C1(n4451), .Y(n3076) );
OAI21X1TS U4705 ( .A0(n4455), .A1(n4422), .B0(n3076), .Y(n3077) );
XOR2X1TS U4706 ( .A(n3077), .B(n4423), .Y(DP_OP_168J30_122_4811_n2866) );
AOI222X1TS U4707 ( .A0(n4517), .A1(n4452), .B0(n4515), .B1(n4451), .C0(n4513), .C1(n4443), .Y(n3080) );
XOR2X1TS U4708 ( .A(n3081), .B(n4423), .Y(DP_OP_168J30_122_4811_n2867) );
XNOR2X2TS U4709 ( .A(Op_MX[9]), .B(Op_MX[8]), .Y(n3089) );
CLKXOR2X2TS U4710 ( .A(Op_MX[11]), .B(Op_MX[10]), .Y(n3088) );
XOR2X1TS U4711 ( .A(n3083), .B(Op_MX[11]), .Y(DP_OP_168J30_122_4811_n2882)
);
NOR2BX4TS U4712 ( .AN(n3089), .B(n3084), .Y(n3113) );
BUFX4TS U4713 ( .A(n3113), .Y(n4416) );
CLKAND2X2TS U4714 ( .A(n4416), .B(n3152), .Y(n3085) );
AOI21X1TS U4715 ( .A0(n3112), .A1(n3793), .B0(n3085), .Y(n3086) );
XOR2X1TS U4716 ( .A(n3087), .B(Op_MX[11]), .Y(DP_OP_168J30_122_4811_n2883)
);
NOR2X2TS U4717 ( .A(n3089), .B(n3088), .Y(n3124) );
BUFX6TS U4718 ( .A(n3124), .Y(n3121) );
AOI222X1TS U4719 ( .A0(n3121), .A1(n3152), .B0(n4416), .B1(n3793), .C0(n3112), .C1(n3792), .Y(n3090) );
XOR2X1TS U4720 ( .A(n3091), .B(Op_MX[11]), .Y(DP_OP_168J30_122_4811_n2884)
);
AOI222X1TS U4721 ( .A0(n3121), .A1(n3793), .B0(n4416), .B1(n3792), .C0(n3112), .C1(n3784), .Y(n3092) );
XOR2X1TS U4722 ( .A(n3093), .B(Op_MX[11]), .Y(DP_OP_168J30_122_4811_n2885)
);
AOI222X1TS U4723 ( .A0(n3121), .A1(n3792), .B0(n4416), .B1(n3784), .C0(n3112), .C1(n3778), .Y(n3094) );
XOR2X1TS U4724 ( .A(n3095), .B(Op_MX[11]), .Y(DP_OP_168J30_122_4811_n2886)
);
AOI222X1TS U4725 ( .A0(n3121), .A1(n3784), .B0(n3113), .B1(n3778), .C0(n3112), .C1(n4459), .Y(n3096) );
OAI21X1TS U4726 ( .A0(n3780), .A1(n3118), .B0(n3096), .Y(n3097) );
XOR2X1TS U4727 ( .A(n3097), .B(n4419), .Y(DP_OP_168J30_122_4811_n2887) );
AOI222X1TS U4728 ( .A0(n3121), .A1(n3778), .B0(n3113), .B1(n4459), .C0(n3112), .C1(n4458), .Y(n3098) );
XOR2X1TS U4729 ( .A(n3099), .B(n4419), .Y(DP_OP_168J30_122_4811_n2888) );
AOI222X1TS U4730 ( .A0(n3121), .A1(n4459), .B0(n3113), .B1(n4458), .C0(n3112), .C1(Op_MY[19]), .Y(n3100) );
OAI21X1TS U4731 ( .A0(n4461), .A1(n3118), .B0(n3100), .Y(n3101) );
XOR2X1TS U4732 ( .A(n3101), .B(n4419), .Y(DP_OP_168J30_122_4811_n2889) );
AOI222X1TS U4733 ( .A0(n3121), .A1(n4458), .B0(n3113), .B1(n3061), .C0(n3112), .C1(n4470), .Y(n3102) );
XOR2X1TS U4734 ( .A(n3103), .B(n4419), .Y(DP_OP_168J30_122_4811_n2890) );
AOI222X1TS U4735 ( .A0(n3121), .A1(n3061), .B0(n3113), .B1(n4470), .C0(n3112), .C1(n4516), .Y(n3104) );
XOR2X1TS U4736 ( .A(n3105), .B(n4419), .Y(DP_OP_168J30_122_4811_n2891) );
AOI222X1TS U4737 ( .A0(n3121), .A1(n4470), .B0(n3113), .B1(n4516), .C0(n3112), .C1(n4514), .Y(n3106) );
OAI21X1TS U4738 ( .A0(n4467), .A1(n3118), .B0(n3106), .Y(n3107) );
XOR2X1TS U4739 ( .A(n3107), .B(n4419), .Y(DP_OP_168J30_122_4811_n2892) );
AOI222X1TS U4740 ( .A0(n3121), .A1(n4516), .B0(n3113), .B1(n4514), .C0(n3112), .C1(n4463), .Y(n3108) );
XOR2X1TS U4741 ( .A(n3109), .B(n4419), .Y(DP_OP_168J30_122_4811_n2893) );
AOI222X1TS U4742 ( .A0(n3121), .A1(n4514), .B0(n3113), .B1(n4463), .C0(n3112), .C1(n4453), .Y(n3110) );
OAI21X1TS U4743 ( .A0(n3801), .A1(n3118), .B0(n3110), .Y(n3111) );
XOR2X1TS U4744 ( .A(n3111), .B(n4419), .Y(DP_OP_168J30_122_4811_n2894) );
AOI222X1TS U4745 ( .A0(n3121), .A1(n4463), .B0(n3113), .B1(n4453), .C0(n3112), .C1(n4452), .Y(n3114) );
XOR2X1TS U4746 ( .A(n3115), .B(n4419), .Y(DP_OP_168J30_122_4811_n2895) );
AOI222X1TS U4747 ( .A0(n3121), .A1(n4453), .B0(n4416), .B1(n4452), .C0(n3112), .C1(n4451), .Y(n3117) );
OAI21X1TS U4748 ( .A0(n4455), .A1(n3118), .B0(n3117), .Y(n3119) );
XOR2X1TS U4749 ( .A(n3119), .B(n4419), .Y(DP_OP_168J30_122_4811_n2896) );
AOI222X1TS U4750 ( .A0(n3121), .A1(n4452), .B0(n4416), .B1(n4451), .C0(n3112), .C1(n4443), .Y(n3122) );
XOR2X1TS U4751 ( .A(n3123), .B(n4419), .Y(DP_OP_168J30_122_4811_n2897) );
AOI222X1TS U4752 ( .A0(n3121), .A1(n4451), .B0(n4416), .B1(n4443), .C0(n3112), .C1(n4439), .Y(n3125) );
OAI21X1TS U4753 ( .A0(n4441), .A1(n3120), .B0(n3125), .Y(n3126) );
XOR2X1TS U4754 ( .A(n3126), .B(n4419), .Y(DP_OP_168J30_122_4811_n2898) );
AOI222X1TS U4755 ( .A0(n3121), .A1(n4443), .B0(n4416), .B1(n4439), .C0(n3112), .C1(n4432), .Y(n3127) );
OAI21XLTS U4756 ( .A0(n4436), .A1(n3120), .B0(n3127), .Y(n3128) );
XOR2X1TS U4757 ( .A(n3128), .B(n4419), .Y(DP_OP_168J30_122_4811_n2899) );
XOR2X1TS U4758 ( .A(n3132), .B(Op_MX[8]), .Y(DP_OP_168J30_122_4811_n2912) );
CLKAND2X2TS U4759 ( .A(n4471), .B(n3152), .Y(n3134) );
AOI21X1TS U4760 ( .A0(n4469), .A1(n3793), .B0(n3134), .Y(n3135) );
XOR2X1TS U4761 ( .A(n3137), .B(Op_MX[8]), .Y(DP_OP_168J30_122_4811_n2913) );
AOI222X1TS U4762 ( .A0(n4472), .A1(n3152), .B0(n4471), .B1(n3793), .C0(n4469), .C1(n3792), .Y(n3138) );
XOR2X1TS U4763 ( .A(n3139), .B(Op_MX[8]), .Y(DP_OP_168J30_122_4811_n2914) );
AOI222X1TS U4764 ( .A0(n4472), .A1(n3793), .B0(n4471), .B1(n3792), .C0(n4469), .C1(n3784), .Y(n3140) );
XOR2X1TS U4765 ( .A(n3141), .B(Op_MX[8]), .Y(DP_OP_168J30_122_4811_n2915) );
AOI222X1TS U4766 ( .A0(n4472), .A1(n3792), .B0(n4471), .B1(n3784), .C0(n4469), .C1(n3778), .Y(n3142) );
XOR2X1TS U4767 ( .A(n3143), .B(Op_MX[8]), .Y(DP_OP_168J30_122_4811_n2916) );
AOI222X1TS U4768 ( .A0(n4472), .A1(n3784), .B0(n4471), .B1(n3778), .C0(n4469), .C1(n4459), .Y(n3144) );
XOR2X1TS U4769 ( .A(n3145), .B(n4456), .Y(DP_OP_168J30_122_4811_n2917) );
AOI222X1TS U4770 ( .A0(n4472), .A1(n3778), .B0(n4471), .B1(n4459), .C0(n4469), .C1(n4458), .Y(n3146) );
OAI21X1TS U4771 ( .A0(n3773), .A1(n4474), .B0(n3146), .Y(n3147) );
XOR2X1TS U4772 ( .A(n3147), .B(n4456), .Y(DP_OP_168J30_122_4811_n2918) );
AOI222X1TS U4773 ( .A0(n4472), .A1(n4514), .B0(n4471), .B1(n4463), .C0(n4469), .C1(n4453), .Y(n3148) );
OAI21X1TS U4774 ( .A0(n3801), .A1(n4474), .B0(n3148), .Y(n3149) );
XOR2X1TS U4775 ( .A(n3149), .B(n4456), .Y(DP_OP_168J30_122_4811_n2924) );
AOI222X1TS U4776 ( .A0(n4472), .A1(n4463), .B0(n4471), .B1(n4453), .C0(n4469), .C1(n4452), .Y(n3150) );
OAI21X1TS U4777 ( .A0(n3798), .A1(n4474), .B0(n3150), .Y(n3151) );
XOR2X1TS U4778 ( .A(n3151), .B(n4456), .Y(DP_OP_168J30_122_4811_n2925) );
NAND2X1TS U4779 ( .A(n3809), .B(n3152), .Y(n3153) );
XOR2X1TS U4780 ( .A(n3155), .B(n4657), .Y(DP_OP_168J30_122_4811_n2942) );
BUFX3TS U4781 ( .A(Op_MY[45]), .Y(n3754) );
CLKAND2X2TS U4782 ( .A(n3762), .B(n3754), .Y(n3156) );
AOI21X1TS U4783 ( .A0(n4641), .A1(Op_MY[44]), .B0(n3156), .Y(n3157) );
OAI21X1TS U4784 ( .A0(n3548), .A1(n3766), .B0(n3157), .Y(n3158) );
CMPR32X2TS U4785 ( .A(DP_OP_168J30_122_4811_n3901), .B(n912), .C(n3158),
.CO(DP_OP_168J30_122_4811_n3886), .S(DP_OP_168J30_122_4811_n3895) );
CLKAND2X2TS U4786 ( .A(n3762), .B(Op_MY[44]), .Y(n3159) );
AOI21X1TS U4787 ( .A0(n4641), .A1(Op_MY[43]), .B0(n3159), .Y(n3160) );
OAI21X1TS U4788 ( .A0(n3552), .A1(n3766), .B0(n3160), .Y(n3166) );
INVX2TS U4789 ( .A(DP_OP_168J30_122_4811_n3901), .Y(n3169) );
BUFX4TS U4790 ( .A(Op_MY[42]), .Y(n3749) );
CLKAND2X2TS U4791 ( .A(n3762), .B(Op_MY[43]), .Y(n3161) );
AOI21X1TS U4792 ( .A0(n4641), .A1(n3749), .B0(n3161), .Y(n3162) );
OAI21X1TS U4793 ( .A0(n3557), .A1(n3766), .B0(n3162), .Y(n3168) );
BUFX3TS U4794 ( .A(Op_MY[47]), .Y(n3764) );
BUFX3TS U4795 ( .A(Op_MY[46]), .Y(n3758) );
AOI222X1TS U4796 ( .A0(n3249), .A1(n3764), .B0(n3241), .B1(n3758), .C0(n3240), .C1(n3754), .Y(n3163) );
XOR2X1TS U4797 ( .A(n3164), .B(n4649), .Y(n3167) );
CMPR32X2TS U4798 ( .A(n3166), .B(n3169), .C(n3165), .CO(
DP_OP_168J30_122_4811_n3899), .S(DP_OP_168J30_122_4811_n3900) );
CMPR32X2TS U4799 ( .A(n3169), .B(n3168), .C(n3167), .CO(n3165), .S(
DP_OP_168J30_122_4811_n3907) );
BUFX3TS U4800 ( .A(n3171), .Y(n4639) );
AOI21X1TS U4801 ( .A0(n4585), .A1(Op_MY[38]), .B0(n3172), .Y(n3173) );
CMPR32X2TS U4802 ( .A(DP_OP_168J30_122_4811_n3945), .B(n761), .C(n3174),
.CO(DP_OP_168J30_122_4811_n3935), .S(DP_OP_168J30_122_4811_n3936) );
AOI21X1TS U4803 ( .A0(n4585), .A1(Op_MY[37]), .B0(n3175), .Y(n3176) );
INVX2TS U4804 ( .A(DP_OP_168J30_122_4811_n3945), .Y(n3188) );
AOI222X1TS U4805 ( .A0(n3249), .A1(n3749), .B0(n3241), .B1(Op_MY[41]), .C0(
n3240), .C1(Op_MY[40]), .Y(n3177) );
XOR2X1TS U4806 ( .A(n3178), .B(n4649), .Y(n3179) );
CMPR32X2TS U4807 ( .A(n3180), .B(n3188), .C(n3179), .CO(
DP_OP_168J30_122_4811_n3943), .S(DP_OP_168J30_122_4811_n3944) );
AOI21X1TS U4808 ( .A0(n4585), .A1(Op_MY[36]), .B0(n3181), .Y(n3182) );
AOI222X1TS U4809 ( .A0(n3249), .A1(Op_MY[41]), .B0(n3241), .B1(Op_MY[40]),
.C0(n3183), .C1(Op_MY[39]), .Y(n3184) );
XOR2X1TS U4810 ( .A(n3185), .B(n4649), .Y(n3186) );
CMPR32X2TS U4811 ( .A(n3188), .B(n3187), .C(n3186), .CO(
DP_OP_168J30_122_4811_n3953), .S(DP_OP_168J30_122_4811_n3954) );
BUFX4TS U4812 ( .A(n3190), .Y(n3414) );
BUFX4TS U4813 ( .A(n3191), .Y(n3413) );
BUFX3TS U4814 ( .A(Op_MY[28]), .Y(n4594) );
BUFX3TS U4815 ( .A(Op_MY[27]), .Y(n4584) );
AOI222X1TS U4816 ( .A0(n3414), .A1(n3872), .B0(n3413), .B1(n4594), .C0(n3192), .C1(n4584), .Y(n3193) );
OAI21XLTS U4817 ( .A0(n3416), .A1(n4587), .B0(n3193), .Y(n3194) );
BUFX4TS U4818 ( .A(Op_MX[41]), .Y(n3417) );
XOR2XLTS U4819 ( .A(n3194), .B(n3417), .Y(n3965) );
AOI22X1TS U4820 ( .A0(n3413), .A1(n4584), .B0(n3414), .B1(n3516), .Y(n3195)
);
OAI21XLTS U4821 ( .A0(n3416), .A1(n3893), .B0(n3195), .Y(n3196) );
XOR2XLTS U4822 ( .A(n3196), .B(n3417), .Y(n3205) );
XOR2X1TS U4823 ( .A(n3197), .B(n3417), .Y(n3210) );
BUFX3TS U4824 ( .A(n3200), .Y(n3463) );
BUFX4TS U4825 ( .A(Op_MX[38]), .Y(n3465) );
XOR2X1TS U4826 ( .A(n3203), .B(n3465), .Y(n3218) );
ADDHXLTS U4827 ( .A(n3205), .B(n3204), .CO(n3964), .S(n3222) );
XOR2X1TS U4828 ( .A(n3207), .B(n3465), .Y(n3221) );
XOR2X1TS U4829 ( .A(n3209), .B(n3465), .Y(n3225) );
ADDHXLTS U4830 ( .A(n3417), .B(n3210), .CO(n3204), .S(n3224) );
AOI222X1TS U4831 ( .A0(n3199), .A1(n3872), .B0(n3463), .B1(n3516), .C0(n3201), .C1(Op_MY[27]), .Y(n3211) );
XOR2X1TS U4832 ( .A(n3212), .B(n3465), .Y(n3962) );
XOR2X1TS U4833 ( .A(n3214), .B(n3465), .Y(n3960) );
OAI21XLTS U4834 ( .A0(n3198), .A1(n748), .B0(n743), .Y(n3216) );
XOR2X1TS U4835 ( .A(n3216), .B(n3465), .Y(n3963) );
CMPR32X2TS U4836 ( .A(n3219), .B(n3218), .C(n3217), .CO(
DP_OP_168J30_122_4811_n4163), .S(DP_OP_168J30_122_4811_n4164) );
CMPR32X2TS U4837 ( .A(n3222), .B(n3221), .C(n3220), .CO(n3217), .S(
DP_OP_168J30_122_4811_n4171) );
CMPR32X2TS U4838 ( .A(n3225), .B(n3224), .C(n3223), .CO(n3220), .S(
DP_OP_168J30_122_4811_n4178) );
AOI222X1TS U4839 ( .A0(n3249), .A1(n3363), .B0(n3241), .B1(n3366), .C0(n3240), .C1(n3369), .Y(n3226) );
XOR2X1TS U4840 ( .A(n3227), .B(Op_MX[50]), .Y(DP_OP_168J30_122_4811_n4352)
);
AOI222X1TS U4841 ( .A0(n3249), .A1(n3366), .B0(n3241), .B1(n3369), .C0(n3240), .C1(n3761), .Y(n3228) );
XOR2X1TS U4842 ( .A(n3229), .B(n4649), .Y(DP_OP_168J30_122_4811_n4353) );
AOI222X1TS U4843 ( .A0(n3249), .A1(n3369), .B0(n3241), .B1(n3761), .C0(n3240), .C1(n3764), .Y(n3230) );
XOR2X1TS U4844 ( .A(n3231), .B(n4649), .Y(DP_OP_168J30_122_4811_n4354) );
AOI222X1TS U4845 ( .A0(n3249), .A1(n3761), .B0(n3241), .B1(n3764), .C0(n3240), .C1(n3758), .Y(n3232) );
XOR2X1TS U4846 ( .A(n3233), .B(n4649), .Y(DP_OP_168J30_122_4811_n4355) );
AOI222X1TS U4847 ( .A0(n3249), .A1(n3758), .B0(n3241), .B1(n3754), .C0(n3240), .C1(Op_MY[44]), .Y(n3234) );
XOR2X1TS U4848 ( .A(n3235), .B(n4649), .Y(DP_OP_168J30_122_4811_n4357) );
AOI222X1TS U4849 ( .A0(n3249), .A1(n3754), .B0(n3241), .B1(Op_MY[44]), .C0(
n3240), .C1(Op_MY[43]), .Y(n3236) );
XOR2X1TS U4850 ( .A(n3237), .B(n4649), .Y(DP_OP_168J30_122_4811_n4358) );
AOI222X1TS U4851 ( .A0(n3249), .A1(Op_MY[44]), .B0(n3241), .B1(Op_MY[43]),
.C0(n3240), .C1(n3749), .Y(n3238) );
XOR2X1TS U4852 ( .A(n3239), .B(n4649), .Y(DP_OP_168J30_122_4811_n4359) );
AOI222X1TS U4853 ( .A0(n3249), .A1(Op_MY[43]), .B0(n3241), .B1(n3749), .C0(
n3240), .C1(Op_MY[41]), .Y(n3242) );
XOR2X1TS U4854 ( .A(n3244), .B(n4649), .Y(DP_OP_168J30_122_4811_n4360) );
BUFX3TS U4855 ( .A(n3246), .Y(n4645) );
AOI222X1TS U4856 ( .A0(n3249), .A1(Op_MY[40]), .B0(n4645), .B1(Op_MY[39]),
.C0(n3183), .C1(Op_MY[38]), .Y(n3247) );
XOR2X1TS U4857 ( .A(n3248), .B(n4649), .Y(DP_OP_168J30_122_4811_n4363) );
BUFX3TS U4858 ( .A(n3249), .Y(n4646) );
XOR2X1TS U4859 ( .A(n3251), .B(n4649), .Y(DP_OP_168J30_122_4811_n4364) );
XOR2X1TS U4860 ( .A(n3253), .B(n4649), .Y(DP_OP_168J30_122_4811_n4365) );
XOR2X1TS U4861 ( .A(n3255), .B(n4649), .Y(DP_OP_168J30_122_4811_n4366) );
INVX2TS U4862 ( .A(n3278), .Y(n3256) );
XOR2X1TS U4863 ( .A(n3257), .B(n3867), .Y(DP_OP_168J30_122_4811_n4378) );
AOI21X1TS U4864 ( .A0(n3278), .A1(n3363), .B0(n3282), .Y(n3258) );
XOR2X1TS U4865 ( .A(n3259), .B(n3867), .Y(DP_OP_168J30_122_4811_n4379) );
AOI222X1TS U4866 ( .A0(n3290), .A1(n3363), .B0(n3282), .B1(n3366), .C0(n3278), .C1(n3369), .Y(n3260) );
XOR2X1TS U4867 ( .A(n3261), .B(n3867), .Y(DP_OP_168J30_122_4811_n4381) );
AOI222X1TS U4868 ( .A0(n3290), .A1(n3366), .B0(n3282), .B1(n3369), .C0(n3278), .C1(n3761), .Y(n3262) );
XOR2X1TS U4869 ( .A(n3263), .B(n3867), .Y(DP_OP_168J30_122_4811_n4382) );
AOI222X1TS U4870 ( .A0(n3290), .A1(n3369), .B0(n3282), .B1(n3761), .C0(n3278), .C1(n3764), .Y(n3264) );
XOR2X1TS U4871 ( .A(n3265), .B(n3867), .Y(DP_OP_168J30_122_4811_n4383) );
AOI222X1TS U4872 ( .A0(n3290), .A1(n3761), .B0(n3282), .B1(n3764), .C0(n3278), .C1(n3758), .Y(n3266) );
XOR2X1TS U4873 ( .A(n3267), .B(n3867), .Y(DP_OP_168J30_122_4811_n4384) );
AOI222X1TS U4874 ( .A0(n3290), .A1(n3764), .B0(n3282), .B1(n3758), .C0(n3278), .C1(n3754), .Y(n3268) );
XOR2X1TS U4875 ( .A(n3269), .B(n3867), .Y(DP_OP_168J30_122_4811_n4385) );
AOI222X1TS U4876 ( .A0(n3290), .A1(n3758), .B0(n3282), .B1(n3754), .C0(n3278), .C1(Op_MY[44]), .Y(n3270) );
XOR2X1TS U4877 ( .A(n3271), .B(n3867), .Y(DP_OP_168J30_122_4811_n4386) );
AOI222X1TS U4878 ( .A0(n3290), .A1(n3754), .B0(n3282), .B1(Op_MY[44]), .C0(
n3278), .C1(Op_MY[43]), .Y(n3272) );
XOR2X1TS U4879 ( .A(n3273), .B(n3867), .Y(DP_OP_168J30_122_4811_n4387) );
AOI222X1TS U4880 ( .A0(n3290), .A1(Op_MY[44]), .B0(n3282), .B1(Op_MY[43]),
.C0(n3278), .C1(n3749), .Y(n3274) );
XOR2X1TS U4881 ( .A(n3275), .B(n3867), .Y(DP_OP_168J30_122_4811_n4388) );
AOI222X1TS U4882 ( .A0(n3290), .A1(Op_MY[43]), .B0(n3282), .B1(n3749), .C0(
n3278), .C1(Op_MY[41]), .Y(n3276) );
XOR2X1TS U4883 ( .A(n3277), .B(n3867), .Y(DP_OP_168J30_122_4811_n4389) );
AOI222X1TS U4884 ( .A0(n3290), .A1(n3749), .B0(n3282), .B1(Op_MY[41]), .C0(
n3278), .C1(Op_MY[40]), .Y(n3279) );
XOR2X1TS U4885 ( .A(n3280), .B(n3867), .Y(DP_OP_168J30_122_4811_n4390) );
AOI222X1TS U4886 ( .A0(n3290), .A1(n3565), .B0(n3282), .B1(Op_MY[40]), .C0(
n3278), .C1(Op_MY[39]), .Y(n3283) );
XOR2X1TS U4887 ( .A(n3285), .B(Op_MX[47]), .Y(DP_OP_168J30_122_4811_n4391)
);
AOI222X1TS U4888 ( .A0(n3290), .A1(n3568), .B0(n3863), .B1(Op_MY[39]), .C0(
n3278), .C1(Op_MY[38]), .Y(n3288) );
XOR2X1TS U4889 ( .A(n3289), .B(Op_MX[47]), .Y(DP_OP_168J30_122_4811_n4392)
);
BUFX4TS U4890 ( .A(n3290), .Y(n3862) );
AOI222X1TS U4891 ( .A0(n3862), .A1(n3573), .B0(n3863), .B1(Op_MY[38]), .C0(
n3278), .C1(Op_MY[37]), .Y(n3291) );
XOR2X1TS U4892 ( .A(n3292), .B(Op_MX[47]), .Y(DP_OP_168J30_122_4811_n4393)
);
AOI222X1TS U4893 ( .A0(n3862), .A1(Op_MY[38]), .B0(n3863), .B1(Op_MY[37]),
.C0(n3278), .C1(Op_MY[36]), .Y(n3293) );
XOR2X1TS U4894 ( .A(n3294), .B(Op_MX[47]), .Y(DP_OP_168J30_122_4811_n4394)
);
AOI222X1TS U4895 ( .A0(n3862), .A1(Op_MY[37]), .B0(n3863), .B1(Op_MY[36]),
.C0(n3278), .C1(Op_MY[35]), .Y(n3295) );
XOR2X1TS U4896 ( .A(n3296), .B(Op_MX[47]), .Y(DP_OP_168J30_122_4811_n4395)
);
AOI222X1TS U4897 ( .A0(n3862), .A1(Op_MY[36]), .B0(n3863), .B1(Op_MY[35]),
.C0(n3278), .C1(Op_MY[34]), .Y(n3297) );
XOR2X1TS U4898 ( .A(n3298), .B(n3867), .Y(DP_OP_168J30_122_4811_n4396) );
AOI222X1TS U4899 ( .A0(n3862), .A1(Op_MY[35]), .B0(n3863), .B1(Op_MY[34]),
.C0(n3278), .C1(Op_MY[33]), .Y(n3299) );
XOR2X1TS U4900 ( .A(n3300), .B(n3867), .Y(DP_OP_168J30_122_4811_n4397) );
AOI222X1TS U4901 ( .A0(n3862), .A1(Op_MY[34]), .B0(n3863), .B1(Op_MY[33]),
.C0(n3278), .C1(Op_MY[32]), .Y(n3301) );
XOR2X1TS U4902 ( .A(n3302), .B(n3867), .Y(DP_OP_168J30_122_4811_n4398) );
AOI222X1TS U4903 ( .A0(n3862), .A1(Op_MY[33]), .B0(n3863), .B1(Op_MY[32]),
.C0(n3278), .C1(Op_MY[31]), .Y(n3303) );
XOR2X1TS U4904 ( .A(n3304), .B(n3867), .Y(DP_OP_168J30_122_4811_n4399) );
AOI222X1TS U4905 ( .A0(n3862), .A1(Op_MY[32]), .B0(n3863), .B1(Op_MY[31]),
.C0(n3278), .C1(Op_MY[30]), .Y(n3305) );
XOR2X1TS U4906 ( .A(n3306), .B(n3867), .Y(DP_OP_168J30_122_4811_n4400) );
AOI222X1TS U4907 ( .A0(n3862), .A1(Op_MY[31]), .B0(n3863), .B1(Op_MY[30]),
.C0(n3278), .C1(Op_MY[29]), .Y(n3307) );
XOR2X1TS U4908 ( .A(n3308), .B(n3867), .Y(DP_OP_168J30_122_4811_n4401) );
XOR2X1TS U4909 ( .A(n3310), .B(n3867), .Y(DP_OP_168J30_122_4811_n4402) );
INVX2TS U4910 ( .A(n3333), .Y(n3311) );
XOR2X1TS U4911 ( .A(n3312), .B(n3980), .Y(DP_OP_168J30_122_4811_n4407) );
AOI21X1TS U4912 ( .A0(n3333), .A1(n3363), .B0(n3337), .Y(n3313) );
XOR2X1TS U4913 ( .A(n3314), .B(n3980), .Y(DP_OP_168J30_122_4811_n4408) );
AOI222X1TS U4914 ( .A0(n3343), .A1(n3363), .B0(n3337), .B1(n3366), .C0(n3333), .C1(n3369), .Y(n3315) );
XOR2X1TS U4915 ( .A(n3316), .B(n3980), .Y(DP_OP_168J30_122_4811_n4410) );
AOI222X1TS U4916 ( .A0(n3343), .A1(n3366), .B0(n3337), .B1(n3369), .C0(n3333), .C1(n3761), .Y(n3317) );
XOR2X1TS U4917 ( .A(n3318), .B(n3980), .Y(DP_OP_168J30_122_4811_n4411) );
AOI222X1TS U4918 ( .A0(n3343), .A1(n3369), .B0(n3337), .B1(n3761), .C0(n3333), .C1(n3764), .Y(n3319) );
XOR2X1TS U4919 ( .A(n3320), .B(n3980), .Y(DP_OP_168J30_122_4811_n4412) );
AOI222X1TS U4920 ( .A0(n3343), .A1(n3761), .B0(n3337), .B1(n3764), .C0(n3333), .C1(n3758), .Y(n3321) );
XOR2X1TS U4921 ( .A(n3322), .B(n3980), .Y(DP_OP_168J30_122_4811_n4413) );
AOI222X1TS U4922 ( .A0(n3343), .A1(n3764), .B0(n3337), .B1(n3758), .C0(n3333), .C1(n3754), .Y(n3323) );
XOR2X1TS U4923 ( .A(n3324), .B(n3980), .Y(DP_OP_168J30_122_4811_n4414) );
AOI222X1TS U4924 ( .A0(n3343), .A1(n3758), .B0(n3337), .B1(n3754), .C0(n3333), .C1(n3555), .Y(n3325) );
XOR2X1TS U4925 ( .A(n3326), .B(n3980), .Y(DP_OP_168J30_122_4811_n4415) );
AOI222X1TS U4926 ( .A0(n3343), .A1(n3754), .B0(n3337), .B1(n3555), .C0(n3333), .C1(n3559), .Y(n3327) );
XOR2X1TS U4927 ( .A(n3328), .B(n3980), .Y(DP_OP_168J30_122_4811_n4416) );
AOI222X1TS U4928 ( .A0(n3343), .A1(n3555), .B0(n3337), .B1(n3559), .C0(n3333), .C1(n3749), .Y(n3329) );
XOR2X1TS U4929 ( .A(n3330), .B(n3980), .Y(DP_OP_168J30_122_4811_n4417) );
AOI222X1TS U4930 ( .A0(n3343), .A1(n3559), .B0(n3337), .B1(n3749), .C0(n3333), .C1(Op_MY[41]), .Y(n3331) );
XOR2X1TS U4931 ( .A(n3332), .B(n3980), .Y(DP_OP_168J30_122_4811_n4418) );
AOI222X1TS U4932 ( .A0(n3343), .A1(n3749), .B0(n3337), .B1(n3565), .C0(n3333), .C1(Op_MY[40]), .Y(n3334) );
XOR2X1TS U4933 ( .A(n3335), .B(n3980), .Y(DP_OP_168J30_122_4811_n4419) );
AOI222X1TS U4934 ( .A0(n3343), .A1(n3565), .B0(n3337), .B1(n3568), .C0(n3336), .C1(Op_MY[39]), .Y(n3338) );
XOR2X1TS U4935 ( .A(n3340), .B(Op_MX[44]), .Y(DP_OP_168J30_122_4811_n4420)
);
AOI222X1TS U4936 ( .A0(n3343), .A1(n3568), .B0(n3342), .B1(n3573), .C0(n3336), .C1(n3577), .Y(n3344) );
XOR2X1TS U4937 ( .A(n3345), .B(Op_MX[44]), .Y(DP_OP_168J30_122_4811_n4421)
);
BUFX4TS U4938 ( .A(n3346), .Y(n3874) );
AOI222X1TS U4939 ( .A0(n3874), .A1(n3573), .B0(n3342), .B1(n3577), .C0(n3336), .C1(n3581), .Y(n3347) );
XOR2X1TS U4940 ( .A(n3348), .B(Op_MX[44]), .Y(DP_OP_168J30_122_4811_n4422)
);
AOI222X1TS U4941 ( .A0(n3874), .A1(n3577), .B0(n3342), .B1(n3581), .C0(n3336), .C1(n3584), .Y(n3349) );
XOR2X1TS U4942 ( .A(n3350), .B(Op_MX[44]), .Y(DP_OP_168J30_122_4811_n4423)
);
OAI21X1TS U4943 ( .A0(n3737), .A1(n3339), .B0(n3351), .Y(n3352) );
XOR2X1TS U4944 ( .A(n3352), .B(Op_MX[44]), .Y(DP_OP_168J30_122_4811_n4424)
);
OAI21X1TS U4945 ( .A0(n4648), .A1(n3339), .B0(n3353), .Y(n3354) );
XOR2X1TS U4946 ( .A(n3354), .B(n3980), .Y(DP_OP_168J30_122_4811_n4425) );
AOI222X1TS U4947 ( .A0(n3874), .A1(n3587), .B0(n3342), .B1(n3590), .C0(n3333), .C1(n3597), .Y(n3355) );
XOR2X1TS U4948 ( .A(n3356), .B(n3980), .Y(DP_OP_168J30_122_4811_n4426) );
AOI222X1TS U4949 ( .A0(n3874), .A1(n3590), .B0(n3337), .B1(n3597), .C0(n3333), .C1(n3595), .Y(n3357) );
XOR2X1TS U4950 ( .A(n3358), .B(n3980), .Y(DP_OP_168J30_122_4811_n4427) );
AOI222X1TS U4951 ( .A0(n3874), .A1(n3597), .B0(n3337), .B1(n3595), .C0(n3333), .C1(n3593), .Y(n3359) );
XOR2X1TS U4952 ( .A(n3360), .B(n3980), .Y(DP_OP_168J30_122_4811_n4428) );
INVX2TS U4953 ( .A(n3386), .Y(n3361) );
XOR2X1TS U4954 ( .A(n3362), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4436)
);
AOI21X1TS U4955 ( .A0(n3386), .A1(n3363), .B0(n3389), .Y(n3364) );
XOR2X1TS U4956 ( .A(n3365), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4437)
);
AOI222X1TS U4957 ( .A0(n3392), .A1(n3529), .B0(n3389), .B1(n3366), .C0(n3386), .C1(n3369), .Y(n3367) );
XOR2X1TS U4958 ( .A(n3368), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4439)
);
AOI222X1TS U4959 ( .A0(n3392), .A1(n3533), .B0(n3389), .B1(n3369), .C0(n3386), .C1(n3761), .Y(n3370) );
XOR2X1TS U4960 ( .A(n3371), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4440)
);
AOI222X1TS U4961 ( .A0(n3392), .A1(n3537), .B0(n3389), .B1(n3761), .C0(n3386), .C1(n3764), .Y(n3372) );
XOR2X1TS U4962 ( .A(n3373), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4441)
);
AOI222X1TS U4963 ( .A0(n3392), .A1(n3540), .B0(n3389), .B1(n3764), .C0(n3386), .C1(n3758), .Y(n3374) );
XOR2X1TS U4964 ( .A(n3375), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4442)
);
AOI222X1TS U4965 ( .A0(n3392), .A1(n3543), .B0(n3389), .B1(n3758), .C0(n3386), .C1(n3754), .Y(n3376) );
XOR2X1TS U4966 ( .A(n3377), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4443)
);
AOI222X1TS U4967 ( .A0(n3392), .A1(n3546), .B0(n3389), .B1(n3754), .C0(n3386), .C1(n3555), .Y(n3378) );
XOR2X1TS U4968 ( .A(n3379), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4444)
);
AOI222X1TS U4969 ( .A0(n3392), .A1(n3550), .B0(n3389), .B1(n3555), .C0(n3386), .C1(n3559), .Y(n3380) );
XOR2X1TS U4970 ( .A(n3381), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4445)
);
AOI222X1TS U4971 ( .A0(n3392), .A1(n3555), .B0(n3389), .B1(n3559), .C0(n3386), .C1(n3749), .Y(n3382) );
XOR2X1TS U4972 ( .A(n3383), .B(Op_MX[41]), .Y(DP_OP_168J30_122_4811_n4446)
);
AOI222X1TS U4973 ( .A0(n3392), .A1(n3559), .B0(n3389), .B1(n3749), .C0(n3386), .C1(n3565), .Y(n3384) );
XOR2X1TS U4974 ( .A(n3385), .B(n3417), .Y(DP_OP_168J30_122_4811_n4447) );
AOI222X1TS U4975 ( .A0(n3392), .A1(Op_MY[42]), .B0(n3389), .B1(n3565), .C0(
n3386), .C1(n3568), .Y(n3387) );
XOR2X1TS U4976 ( .A(n3388), .B(n3417), .Y(DP_OP_168J30_122_4811_n4448) );
AOI222X1TS U4977 ( .A0(n3392), .A1(n3565), .B0(n3389), .B1(n3568), .C0(n3192), .C1(n3573), .Y(n3390) );
XOR2X1TS U4978 ( .A(n3391), .B(n3417), .Y(DP_OP_168J30_122_4811_n4449) );
AOI222X1TS U4979 ( .A0(n3392), .A1(n3568), .B0(n3413), .B1(n3573), .C0(n3192), .C1(n3577), .Y(n3393) );
XOR2X1TS U4980 ( .A(n3394), .B(n3417), .Y(DP_OP_168J30_122_4811_n4450) );
AOI222X1TS U4981 ( .A0(n3414), .A1(n3573), .B0(n3413), .B1(n3577), .C0(n3192), .C1(n3581), .Y(n3395) );
XOR2X1TS U4982 ( .A(n3396), .B(n3417), .Y(DP_OP_168J30_122_4811_n4451) );
AOI222X1TS U4983 ( .A0(n3414), .A1(n3577), .B0(n3413), .B1(n3581), .C0(n3192), .C1(n3584), .Y(n3397) );
XOR2X1TS U4984 ( .A(n3398), .B(n3417), .Y(DP_OP_168J30_122_4811_n4452) );
AOI222X1TS U4985 ( .A0(n3414), .A1(n3581), .B0(n3413), .B1(n3584), .C0(n3192), .C1(n3587), .Y(n3399) );
XOR2X1TS U4986 ( .A(n3400), .B(n3417), .Y(DP_OP_168J30_122_4811_n4453) );
AOI222X1TS U4987 ( .A0(n3414), .A1(n3584), .B0(n3413), .B1(n3587), .C0(n3192), .C1(n3590), .Y(n3401) );
XOR2X1TS U4988 ( .A(n3402), .B(n3417), .Y(DP_OP_168J30_122_4811_n4454) );
AOI222X1TS U4989 ( .A0(n3414), .A1(n3587), .B0(n3413), .B1(n3590), .C0(n3192), .C1(n3597), .Y(n3403) );
XOR2X1TS U4990 ( .A(n3404), .B(n3417), .Y(DP_OP_168J30_122_4811_n4455) );
AOI222X1TS U4991 ( .A0(n3414), .A1(n3590), .B0(n3413), .B1(n3597), .C0(n3192), .C1(n3595), .Y(n3405) );
XOR2X1TS U4992 ( .A(n3406), .B(n3417), .Y(DP_OP_168J30_122_4811_n4456) );
AOI222X1TS U4993 ( .A0(n3414), .A1(n3597), .B0(n3413), .B1(n3595), .C0(n3192), .C1(n3593), .Y(n3407) );
XOR2X1TS U4994 ( .A(n3408), .B(n3417), .Y(DP_OP_168J30_122_4811_n4457) );
XOR2X1TS U4995 ( .A(n3410), .B(n3417), .Y(DP_OP_168J30_122_4811_n4458) );
XOR2X1TS U4996 ( .A(n3412), .B(n3417), .Y(DP_OP_168J30_122_4811_n4459) );
XOR2X1TS U4997 ( .A(n3418), .B(n3417), .Y(DP_OP_168J30_122_4811_n4460) );
INVX2TS U4998 ( .A(n3441), .Y(n3419) );
XOR2X1TS U4999 ( .A(n3420), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4465)
);
AOI21X1TS U5000 ( .A0(n3441), .A1(n3529), .B0(n3444), .Y(n3421) );
XOR2X1TS U5001 ( .A(n3422), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4466)
);
AOI222X1TS U5002 ( .A0(n3448), .A1(n3529), .B0(n3444), .B1(n3533), .C0(n3441), .C1(n3537), .Y(n3423) );
XOR2X1TS U5003 ( .A(n3424), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4468)
);
AOI222X1TS U5004 ( .A0(n3448), .A1(n3533), .B0(n3444), .B1(n3537), .C0(n3441), .C1(n3540), .Y(n3425) );
XOR2X1TS U5005 ( .A(n3426), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4469)
);
AOI222X1TS U5006 ( .A0(n3448), .A1(n3537), .B0(n3444), .B1(n3540), .C0(n3441), .C1(n3543), .Y(n3427) );
XOR2X1TS U5007 ( .A(n3428), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4470)
);
AOI222X1TS U5008 ( .A0(n3448), .A1(n3540), .B0(n3444), .B1(n3543), .C0(n3441), .C1(n3546), .Y(n3429) );
XOR2X1TS U5009 ( .A(n3430), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4471)
);
AOI222X1TS U5010 ( .A0(n3448), .A1(n3543), .B0(n3444), .B1(n3546), .C0(n3441), .C1(n3550), .Y(n3431) );
XOR2X1TS U5011 ( .A(n3432), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4472)
);
AOI222X1TS U5012 ( .A0(n3448), .A1(n3546), .B0(n3444), .B1(n3550), .C0(n3441), .C1(n3555), .Y(n3433) );
XOR2X1TS U5013 ( .A(n3434), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4473)
);
AOI222X1TS U5014 ( .A0(n3448), .A1(n3550), .B0(n3444), .B1(n3555), .C0(n3441), .C1(n3559), .Y(n3435) );
XOR2X1TS U5015 ( .A(n3436), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4474)
);
AOI222X1TS U5016 ( .A0(n3448), .A1(n3555), .B0(n3444), .B1(n3559), .C0(n3441), .C1(Op_MY[42]), .Y(n3437) );
OAI21X1TS U5017 ( .A0(n3557), .A1(n3446), .B0(n3437), .Y(n3438) );
XOR2X1TS U5018 ( .A(n3438), .B(Op_MX[38]), .Y(DP_OP_168J30_122_4811_n4475)
);
AOI222X1TS U5019 ( .A0(n3448), .A1(n3559), .B0(n3444), .B1(Op_MY[42]), .C0(
n3441), .C1(n3565), .Y(n3439) );
XOR2X1TS U5020 ( .A(n3440), .B(n3465), .Y(DP_OP_168J30_122_4811_n4476) );
AOI222X1TS U5021 ( .A0(n3448), .A1(n3749), .B0(n3444), .B1(n3565), .C0(n3441), .C1(n3568), .Y(n3442) );
XOR2X1TS U5022 ( .A(n3443), .B(n3465), .Y(DP_OP_168J30_122_4811_n4477) );
AOI222X1TS U5023 ( .A0(n3448), .A1(n3565), .B0(n3444), .B1(n3568), .C0(n3441), .C1(n3573), .Y(n3445) );
XOR2X1TS U5024 ( .A(n3447), .B(n3465), .Y(DP_OP_168J30_122_4811_n4478) );
AOI222X1TS U5025 ( .A0(n3448), .A1(n3568), .B0(n3463), .B1(n3573), .C0(n3441), .C1(n3577), .Y(n3449) );
XOR2X1TS U5026 ( .A(n3450), .B(n3465), .Y(DP_OP_168J30_122_4811_n4479) );
AOI222X1TS U5027 ( .A0(n3199), .A1(n3573), .B0(n3463), .B1(n3577), .C0(n3441), .C1(n3581), .Y(n3451) );
XOR2X1TS U5028 ( .A(n3452), .B(n3465), .Y(DP_OP_168J30_122_4811_n4480) );
AOI222X1TS U5029 ( .A0(n3199), .A1(n3577), .B0(n3463), .B1(n3581), .C0(n3441), .C1(n3584), .Y(n3453) );
XOR2X1TS U5030 ( .A(n3454), .B(n3465), .Y(DP_OP_168J30_122_4811_n4481) );
AOI222X1TS U5031 ( .A0(n3199), .A1(n3581), .B0(n3463), .B1(n3584), .C0(n3441), .C1(n3587), .Y(n3455) );
XOR2X1TS U5032 ( .A(n3456), .B(n3465), .Y(DP_OP_168J30_122_4811_n4482) );
AOI222X1TS U5033 ( .A0(n3199), .A1(n3584), .B0(n3463), .B1(n3587), .C0(n3441), .C1(n3590), .Y(n3457) );
XOR2X1TS U5034 ( .A(n3458), .B(n3465), .Y(DP_OP_168J30_122_4811_n4483) );
AOI222X1TS U5035 ( .A0(n3199), .A1(n3587), .B0(n3463), .B1(n3590), .C0(n3441), .C1(n3597), .Y(n3459) );
XOR2X1TS U5036 ( .A(n3460), .B(n3465), .Y(DP_OP_168J30_122_4811_n4484) );
AOI222X1TS U5037 ( .A0(n3199), .A1(n3590), .B0(n3463), .B1(n3597), .C0(n3441), .C1(n3595), .Y(n3461) );
OAI21X1TS U5038 ( .A0(n4626), .A1(n3446), .B0(n3461), .Y(n3462) );
XOR2X1TS U5039 ( .A(n3462), .B(n3465), .Y(DP_OP_168J30_122_4811_n4485) );
AOI222X1TS U5040 ( .A0(n3199), .A1(n3597), .B0(n3463), .B1(n3595), .C0(n3441), .C1(n3593), .Y(n3464) );
XOR2X1TS U5041 ( .A(n3466), .B(n3465), .Y(DP_OP_168J30_122_4811_n4486) );
INVX2TS U5042 ( .A(n3517), .Y(n3467) );
XOR2X1TS U5043 ( .A(n3468), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4494)
);
AOI21X1TS U5044 ( .A0(n3517), .A1(n3529), .B0(n3492), .Y(n3469) );
XOR2X1TS U5045 ( .A(n3470), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4495)
);
AOI222X1TS U5046 ( .A0(n3495), .A1(n3529), .B0(n3492), .B1(n3533), .C0(n3485), .C1(n3537), .Y(n3471) );
XOR2X1TS U5047 ( .A(n3472), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4497)
);
AOI222X1TS U5048 ( .A0(n3495), .A1(n3533), .B0(n3492), .B1(n3537), .C0(n3485), .C1(n3540), .Y(n3473) );
OAI21X1TS U5049 ( .A0(n3535), .A1(n1275), .B0(n3473), .Y(n3474) );
XOR2X1TS U5050 ( .A(n3474), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4498)
);
AOI222X1TS U5051 ( .A0(n3495), .A1(n3537), .B0(n3492), .B1(n3540), .C0(n3485), .C1(n3543), .Y(n3475) );
OAI21X1TS U5052 ( .A0(n3767), .A1(n1275), .B0(n3475), .Y(n3476) );
XOR2X1TS U5053 ( .A(n3476), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4499)
);
AOI222X1TS U5054 ( .A0(n3495), .A1(n3540), .B0(n3492), .B1(n3543), .C0(n3485), .C1(n3546), .Y(n3477) );
XOR2X1TS U5055 ( .A(n3478), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4500)
);
AOI222X1TS U5056 ( .A0(n3495), .A1(n3543), .B0(n3492), .B1(n3546), .C0(n3485), .C1(n3550), .Y(n3479) );
OAI21X1TS U5057 ( .A0(n3756), .A1(n1275), .B0(n3479), .Y(n3480) );
XOR2X1TS U5058 ( .A(n3480), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4501)
);
AOI222X1TS U5059 ( .A0(n3495), .A1(n3546), .B0(n3492), .B1(n3550), .C0(n3485), .C1(n3555), .Y(n3481) );
XOR2X1TS U5060 ( .A(n3482), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4502)
);
AOI222X1TS U5061 ( .A0(n3495), .A1(n3550), .B0(n3492), .B1(n3555), .C0(n3485), .C1(n3559), .Y(n3483) );
XOR2X1TS U5062 ( .A(n3484), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4503)
);
AOI222X1TS U5063 ( .A0(n3495), .A1(n3555), .B0(n3492), .B1(n3559), .C0(n3485), .C1(Op_MY[42]), .Y(n3486) );
XOR2X1TS U5064 ( .A(n3487), .B(Op_MX[35]), .Y(DP_OP_168J30_122_4811_n4504)
);
AOI222X1TS U5065 ( .A0(n3495), .A1(n3559), .B0(n3492), .B1(n3749), .C0(n3517), .C1(n3565), .Y(n3488) );
OAI21X1TS U5066 ( .A0(n3752), .A1(n3521), .B0(n3488), .Y(n3489) );
XOR2X1TS U5067 ( .A(n3489), .B(n3522), .Y(DP_OP_168J30_122_4811_n4505) );
AOI222X1TS U5068 ( .A0(n3495), .A1(n3749), .B0(n3492), .B1(n3565), .C0(n3517), .C1(n3568), .Y(n3490) );
XOR2X1TS U5069 ( .A(n3491), .B(n3522), .Y(DP_OP_168J30_122_4811_n4506) );
AOI222X1TS U5070 ( .A0(n3495), .A1(n3565), .B0(n3492), .B1(n3568), .C0(n3517), .C1(n3573), .Y(n3493) );
XOR2X1TS U5071 ( .A(n3494), .B(n3522), .Y(DP_OP_168J30_122_4811_n4507) );
AOI222X1TS U5072 ( .A0(n3495), .A1(n3568), .B0(n3518), .B1(n3573), .C0(n3517), .C1(n3577), .Y(n3496) );
XOR2X1TS U5073 ( .A(n3497), .B(n3522), .Y(DP_OP_168J30_122_4811_n4508) );
AOI222X1TS U5074 ( .A0(n3519), .A1(n3573), .B0(n3518), .B1(n3577), .C0(n3517), .C1(n3581), .Y(n3498) );
XOR2X1TS U5075 ( .A(n3499), .B(n3522), .Y(DP_OP_168J30_122_4811_n4509) );
AOI222X1TS U5076 ( .A0(n3519), .A1(n3577), .B0(n3518), .B1(n3581), .C0(n3517), .C1(n3584), .Y(n3500) );
OAI21X1TS U5077 ( .A0(n3579), .A1(n3521), .B0(n3500), .Y(n3501) );
XOR2X1TS U5078 ( .A(n3501), .B(n3522), .Y(DP_OP_168J30_122_4811_n4510) );
AOI222X1TS U5079 ( .A0(n3519), .A1(n3581), .B0(n3518), .B1(n3584), .C0(n3517), .C1(n3587), .Y(n3502) );
OAI21X1TS U5080 ( .A0(n3737), .A1(n3521), .B0(n3502), .Y(n3503) );
XOR2X1TS U5081 ( .A(n3503), .B(n3522), .Y(DP_OP_168J30_122_4811_n4511) );
AOI222X1TS U5082 ( .A0(n3519), .A1(n3584), .B0(n3518), .B1(n3587), .C0(n3517), .C1(n3590), .Y(n3504) );
OAI21X1TS U5083 ( .A0(n4648), .A1(n3521), .B0(n3504), .Y(n3505) );
XOR2X1TS U5084 ( .A(n3505), .B(n3522), .Y(DP_OP_168J30_122_4811_n4512) );
AOI222X1TS U5085 ( .A0(n3519), .A1(n3587), .B0(n3518), .B1(n3590), .C0(n3517), .C1(n3597), .Y(n3506) );
XOR2X1TS U5086 ( .A(n3507), .B(n3522), .Y(DP_OP_168J30_122_4811_n4513) );
AOI222X1TS U5087 ( .A0(n3519), .A1(n3590), .B0(n3518), .B1(n3597), .C0(n3517), .C1(n3595), .Y(n3508) );
OAI21X1TS U5088 ( .A0(n4626), .A1(n3521), .B0(n3508), .Y(n3509) );
XOR2X1TS U5089 ( .A(n3509), .B(n3522), .Y(DP_OP_168J30_122_4811_n4514) );
AOI222X1TS U5090 ( .A0(n3519), .A1(n3597), .B0(n3518), .B1(n3595), .C0(n3517), .C1(n3593), .Y(n3510) );
OAI21XLTS U5091 ( .A0(n4644), .A1(n3521), .B0(n3510), .Y(n3511) );
XOR2X1TS U5092 ( .A(n3511), .B(n3522), .Y(DP_OP_168J30_122_4811_n4515) );
OAI21XLTS U5093 ( .A0(n4633), .A1(n3521), .B0(n3512), .Y(n3513) );
XOR2X1TS U5094 ( .A(n3513), .B(n3522), .Y(DP_OP_168J30_122_4811_n4516) );
XOR2X1TS U5095 ( .A(n3515), .B(n3522), .Y(DP_OP_168J30_122_4811_n4517) );
XOR2X1TS U5096 ( .A(n3523), .B(n3522), .Y(DP_OP_168J30_122_4811_n4518) );
INVX2TS U5097 ( .A(n3594), .Y(n3524) );
XOR2X1TS U5098 ( .A(n3525), .B(n3844), .Y(DP_OP_168J30_122_4811_n4523) );
AOI21X1TS U5099 ( .A0(n3594), .A1(n3529), .B0(n3564), .Y(n3526) );
XOR2X1TS U5100 ( .A(n3528), .B(n3844), .Y(DP_OP_168J30_122_4811_n4524) );
AOI222X1TS U5101 ( .A0(n3569), .A1(n3529), .B0(n3564), .B1(n3533), .C0(n3554), .C1(n3537), .Y(n3530) );
XOR2X1TS U5102 ( .A(n3532), .B(n3844), .Y(DP_OP_168J30_122_4811_n4526) );
AOI222X1TS U5103 ( .A0(n3569), .A1(n3533), .B0(n3564), .B1(n3537), .C0(n3554), .C1(n3540), .Y(n3534) );
XOR2X1TS U5104 ( .A(n3536), .B(n3844), .Y(DP_OP_168J30_122_4811_n4527) );
AOI222X1TS U5105 ( .A0(n3569), .A1(n3537), .B0(n3564), .B1(n3540), .C0(n3554), .C1(n3543), .Y(n3538) );
XOR2X1TS U5106 ( .A(n3539), .B(n3844), .Y(DP_OP_168J30_122_4811_n4528) );
AOI222X1TS U5107 ( .A0(n3569), .A1(n3540), .B0(n3564), .B1(n3543), .C0(n3554), .C1(n3546), .Y(n3541) );
OAI21X1TS U5108 ( .A0(n3760), .A1(n1174), .B0(n3541), .Y(n3542) );
XOR2X1TS U5109 ( .A(n3542), .B(n3844), .Y(DP_OP_168J30_122_4811_n4529) );
AOI222X1TS U5110 ( .A0(n3569), .A1(n3543), .B0(n3564), .B1(n3546), .C0(n3554), .C1(n3550), .Y(n3544) );
XOR2X1TS U5111 ( .A(n3545), .B(n3844), .Y(DP_OP_168J30_122_4811_n4530) );
AOI222X1TS U5112 ( .A0(n3569), .A1(n3546), .B0(n3564), .B1(n3550), .C0(n3554), .C1(n3555), .Y(n3547) );
XOR2X1TS U5113 ( .A(n3549), .B(n3844), .Y(DP_OP_168J30_122_4811_n4531) );
AOI222X1TS U5114 ( .A0(n3569), .A1(n3550), .B0(n3564), .B1(n3555), .C0(n3554), .C1(n3559), .Y(n3551) );
OAI21X1TS U5115 ( .A0(n3552), .A1(n1174), .B0(n3551), .Y(n3553) );
XOR2X1TS U5116 ( .A(n3553), .B(n3844), .Y(DP_OP_168J30_122_4811_n4532) );
AOI222X1TS U5117 ( .A0(n3569), .A1(n3555), .B0(n3564), .B1(n3559), .C0(n3554), .C1(Op_MY[42]), .Y(n3556) );
XOR2X1TS U5118 ( .A(n3558), .B(n3844), .Y(DP_OP_168J30_122_4811_n4533) );
AOI222X1TS U5119 ( .A0(n3569), .A1(n3559), .B0(n3564), .B1(n3749), .C0(n3594), .C1(n3565), .Y(n3560) );
XOR2X1TS U5120 ( .A(n3561), .B(n3844), .Y(DP_OP_168J30_122_4811_n4534) );
AOI222X1TS U5121 ( .A0(n3569), .A1(n3749), .B0(n3564), .B1(n3565), .C0(n3594), .C1(n3568), .Y(n3562) );
OAI21X1TS U5122 ( .A0(n3743), .A1(n3600), .B0(n3562), .Y(n3563) );
XOR2X1TS U5123 ( .A(n3563), .B(n3844), .Y(DP_OP_168J30_122_4811_n4535) );
AOI222X1TS U5124 ( .A0(n3569), .A1(n3565), .B0(n3564), .B1(n3568), .C0(n3594), .C1(n3573), .Y(n3566) );
XOR2X1TS U5125 ( .A(n3567), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4536)
);
AOI222X1TS U5126 ( .A0(n3569), .A1(n3568), .B0(n3596), .B1(n3573), .C0(n3594), .C1(n3577), .Y(n3570) );
XOR2X1TS U5127 ( .A(n3572), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4537)
);
AOI222X1TS U5128 ( .A0(n3598), .A1(n3573), .B0(n3596), .B1(n3577), .C0(n3594), .C1(n3581), .Y(n3574) );
XOR2X1TS U5129 ( .A(n3576), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4538)
);
AOI222X1TS U5130 ( .A0(n3598), .A1(n3577), .B0(n3596), .B1(n3581), .C0(n3594), .C1(n3584), .Y(n3578) );
XOR2X1TS U5131 ( .A(n3580), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4539)
);
AOI222X1TS U5132 ( .A0(n3598), .A1(n3581), .B0(n3596), .B1(n3584), .C0(n3594), .C1(n3587), .Y(n3582) );
XOR2X1TS U5133 ( .A(n3583), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4540)
);
AOI222X1TS U5134 ( .A0(n3598), .A1(n3584), .B0(n3596), .B1(n3587), .C0(n3594), .C1(n3590), .Y(n3585) );
XOR2X1TS U5135 ( .A(n3586), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4541)
);
AOI222X1TS U5136 ( .A0(n3598), .A1(n3587), .B0(n3596), .B1(n3590), .C0(n3594), .C1(n3597), .Y(n3588) );
XOR2X1TS U5137 ( .A(n3589), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4542)
);
AOI222X1TS U5138 ( .A0(n3598), .A1(n3590), .B0(n3596), .B1(n3597), .C0(n3594), .C1(n3595), .Y(n3591) );
XOR2X1TS U5139 ( .A(n3592), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4543)
);
AOI222X1TS U5140 ( .A0(n3598), .A1(n3597), .B0(n3596), .B1(n3595), .C0(n3594), .C1(n3593), .Y(n3599) );
OAI21X1TS U5141 ( .A0(n4644), .A1(n3600), .B0(n3599), .Y(n3601) );
XOR2X1TS U5142 ( .A(n3601), .B(Op_MX[32]), .Y(DP_OP_168J30_122_4811_n4544)
);
INVX2TS U5143 ( .A(n3602), .Y(n3603) );
XOR2X1TS U5144 ( .A(n3605), .B(n4652), .Y(DP_OP_168J30_122_4811_n4552) );
AOI21X1TS U5145 ( .A0(n4585), .A1(Op_MY[34]), .B0(n3606), .Y(n3607) );
OAI21X1TS U5146 ( .A0(n4648), .A1(n4643), .B0(n3607), .Y(
DP_OP_168J30_122_4811_n4339) );
INVX2TS U5147 ( .A(Sgf_operation_ODD1_Q_left[43]), .Y(
DP_OP_168J30_122_4811_n1953) );
INVX2TS U5148 ( .A(Sgf_operation_ODD1_Q_left[34]), .Y(
DP_OP_168J30_122_4811_n1962) );
INVX2TS U5149 ( .A(Sgf_operation_ODD1_Q_left[37]), .Y(
DP_OP_168J30_122_4811_n1959) );
INVX2TS U5150 ( .A(Sgf_operation_ODD1_Q_left[40]), .Y(
DP_OP_168J30_122_4811_n1956) );
INVX2TS U5151 ( .A(n3608), .Y(DP_OP_168J30_122_4811_n1973) );
INVX2TS U5152 ( .A(Sgf_operation_ODD1_Q_left[47]), .Y(
DP_OP_168J30_122_4811_n1949) );
INVX2TS U5153 ( .A(Sgf_operation_ODD1_Q_left[31]), .Y(
DP_OP_168J30_122_4811_n1965) );
INVX2TS U5154 ( .A(Sgf_operation_ODD1_Q_left[46]), .Y(
DP_OP_168J30_122_4811_n1950) );
INVX2TS U5155 ( .A(n3609), .Y(DP_OP_168J30_122_4811_n1976) );
INVX2TS U5156 ( .A(Sgf_operation_ODD1_Q_left[44]), .Y(
DP_OP_168J30_122_4811_n1952) );
INVX2TS U5157 ( .A(n3610), .Y(DP_OP_168J30_122_4811_n1975) );
INVX2TS U5158 ( .A(n3611), .Y(DP_OP_168J30_122_4811_n1972) );
INVX2TS U5159 ( .A(n3612), .Y(DP_OP_168J30_122_4811_n1974) );
INVX2TS U5160 ( .A(Sgf_operation_ODD1_Q_left[41]), .Y(
DP_OP_168J30_122_4811_n1955) );
XOR2X1TS U5161 ( .A(n3614), .B(n4264), .Y(n3618) );
XOR2X1TS U5162 ( .A(n3616), .B(n4377), .Y(n3617) );
INVX2TS U5163 ( .A(Sgf_operation_ODD1_Q_left[38]), .Y(
DP_OP_168J30_122_4811_n1958) );
INVX2TS U5164 ( .A(n4715), .Y(DP_OP_168J30_122_4811_n1951) );
INVX2TS U5165 ( .A(n4729), .Y(DP_OP_168J30_122_4811_n1948) );
INVX2TS U5166 ( .A(n3627), .Y(DP_OP_168J30_122_4811_n1977) );
INVX2TS U5167 ( .A(n3628), .Y(DP_OP_168J30_122_4811_n1969) );
INVX2TS U5168 ( .A(Sgf_operation_ODD1_Q_left[32]), .Y(
DP_OP_168J30_122_4811_n1964) );
INVX2TS U5169 ( .A(n3629), .Y(DP_OP_168J30_122_4811_n1970) );
INVX2TS U5170 ( .A(n3630), .Y(DP_OP_168J30_122_4811_n1978) );
INVX2TS U5171 ( .A(n3631), .Y(DP_OP_168J30_122_4811_n1967) );
INVX2TS U5172 ( .A(n3632), .Y(DP_OP_168J30_122_4811_n1971) );
INVX2TS U5173 ( .A(n3633), .Y(DP_OP_168J30_122_4811_n1979) );
INVX2TS U5174 ( .A(n3634), .Y(DP_OP_168J30_122_4811_n1981) );
INVX2TS U5175 ( .A(n3635), .Y(DP_OP_168J30_122_4811_n1980) );
INVX2TS U5176 ( .A(n3636), .Y(DP_OP_168J30_122_4811_n1982) );
INVX2TS U5177 ( .A(n5234), .Y(DP_OP_168J30_122_4811_n1960) );
INVX2TS U5178 ( .A(n3682), .Y(n3684) );
INVX2TS U5179 ( .A(n4877), .Y(DP_OP_168J30_122_4811_n808) );
INVX2TS U5180 ( .A(n4878), .Y(DP_OP_168J30_122_4811_n807) );
INVX2TS U5181 ( .A(n3690), .Y(n3692) );
INVX2TS U5182 ( .A(n4881), .Y(DP_OP_168J30_122_4811_n804) );
NAND2X1TS U5183 ( .A(n899), .B(n3695), .Y(n3697) );
INVX2TS U5184 ( .A(n4884), .Y(DP_OP_168J30_122_4811_n801) );
NAND2X1TS U5185 ( .A(n871), .B(n3698), .Y(n3700) );
INVX2TS U5186 ( .A(n4887), .Y(DP_OP_168J30_122_4811_n798) );
INVX2TS U5187 ( .A(n3702), .Y(DP_OP_168J30_122_4811_n773) );
INVX2TS U5188 ( .A(n3703), .Y(DP_OP_168J30_122_4811_n776) );
INVX2TS U5189 ( .A(n3704), .Y(DP_OP_168J30_122_4811_n771) );
INVX2TS U5190 ( .A(n3705), .Y(DP_OP_168J30_122_4811_n769) );
INVX2TS U5191 ( .A(n3706), .Y(DP_OP_168J30_122_4811_n772) );
INVX2TS U5192 ( .A(n3707), .Y(DP_OP_168J30_122_4811_n775) );
INVX2TS U5193 ( .A(n3708), .Y(DP_OP_168J30_122_4811_n774) );
INVX2TS U5194 ( .A(n3709), .Y(DP_OP_168J30_122_4811_n779) );
INVX2TS U5195 ( .A(n3710), .Y(DP_OP_168J30_122_4811_n777) );
INVX2TS U5196 ( .A(n3711), .Y(DP_OP_168J30_122_4811_n791) );
INVX2TS U5197 ( .A(n3712), .Y(n3714) );
NAND2X1TS U5198 ( .A(n3714), .B(n3713), .Y(n3716) );
INVX2TS U5199 ( .A(n4890), .Y(DP_OP_168J30_122_4811_n795) );
INVX2TS U5200 ( .A(n3717), .Y(DP_OP_168J30_122_4811_n785) );
INVX2TS U5201 ( .A(n3718), .Y(DP_OP_168J30_122_4811_n788) );
INVX2TS U5202 ( .A(n3719), .Y(DP_OP_168J30_122_4811_n778) );
INVX2TS U5203 ( .A(n3720), .Y(DP_OP_168J30_122_4811_n781) );
INVX2TS U5204 ( .A(n3721), .Y(DP_OP_168J30_122_4811_n780) );
INVX2TS U5205 ( .A(n3722), .Y(DP_OP_168J30_122_4811_n789) );
INVX2TS U5206 ( .A(n3723), .Y(DP_OP_168J30_122_4811_n790) );
INVX2TS U5207 ( .A(n3724), .Y(DP_OP_168J30_122_4811_n783) );
INVX2TS U5208 ( .A(n3725), .Y(DP_OP_168J30_122_4811_n786) );
INVX2TS U5209 ( .A(n3726), .Y(DP_OP_168J30_122_4811_n787) );
INVX2TS U5210 ( .A(n3727), .Y(DP_OP_168J30_122_4811_n784) );
XOR2X1TS U5211 ( .A(n3730), .B(n2311), .Y(n3731) );
AOI21X1TS U5212 ( .A0(n4641), .A1(Op_MY[33]), .B0(n3733), .Y(n3734) );
OAI21X1TS U5213 ( .A0(n4635), .A1(n4643), .B0(n3734), .Y(
DP_OP_168J30_122_4811_n3973) );
INVX2TS U5214 ( .A(DP_OP_168J30_122_4811_n3973), .Y(
DP_OP_168J30_122_4811_n3984) );
AOI21X1TS U5215 ( .A0(n4585), .A1(Op_MY[35]), .B0(n3735), .Y(n3736) );
OAI21X1TS U5216 ( .A0(n3737), .A1(n4643), .B0(n3736), .Y(
DP_OP_168J30_122_4811_n4338) );
CLKAND2X2TS U5217 ( .A(n2830), .B(Op_MY[9]), .Y(DP_OP_168J30_122_4811_n2621)
);
INVX2TS U5218 ( .A(DP_OP_168J30_122_4811_n2621), .Y(
DP_OP_168J30_122_4811_n2315) );
AOI21X1TS U5219 ( .A0(n4585), .A1(Op_MY[39]), .B0(n3738), .Y(n3739) );
OAI21X1TS U5220 ( .A0(n3740), .A1(n3766), .B0(n3739), .Y(
DP_OP_168J30_122_4811_n3920) );
INVX2TS U5221 ( .A(DP_OP_168J30_122_4811_n3920), .Y(
DP_OP_168J30_122_4811_n3928) );
CLKAND2X2TS U5222 ( .A(n2830), .B(Op_MY[10]), .Y(DP_OP_168J30_122_4811_n2620) );
INVX2TS U5223 ( .A(DP_OP_168J30_122_4811_n2620), .Y(
DP_OP_168J30_122_4811_n2304) );
CLKAND2X2TS U5224 ( .A(n3762), .B(Op_MY[41]), .Y(n3741) );
AOI21X1TS U5225 ( .A0(n4641), .A1(Op_MY[40]), .B0(n3741), .Y(n3742) );
OAI21X1TS U5226 ( .A0(n3743), .A1(n3766), .B0(n3742), .Y(
DP_OP_168J30_122_4811_n4334) );
CLKAND2X2TS U5227 ( .A(n790), .B(n916), .Y(n3748) );
CLKAND2X2TS U5228 ( .A(n4007), .B(n4661), .Y(n3744) );
AOI21X1TS U5229 ( .A0(n2231), .A1(n4660), .B0(n3744), .Y(n3745) );
XOR2X1TS U5230 ( .A(n3746), .B(DP_OP_168J30_122_4811_n86), .Y(n3747) );
ADDHX1TS U5231 ( .A(n3748), .B(n3747), .CO(DP_OP_168J30_122_4811_n221), .S(
DP_OP_168J30_122_4811_n222) );
AOI21X1TS U5232 ( .A0(n4641), .A1(Op_MY[41]), .B0(n3750), .Y(n3751) );
OAI21X1TS U5233 ( .A0(n3752), .A1(n3766), .B0(n3751), .Y(
DP_OP_168J30_122_4811_n4333) );
INVX2TS U5234 ( .A(DP_OP_168J30_122_4811_n3886), .Y(
DP_OP_168J30_122_4811_n3891) );
CLKAND2X2TS U5235 ( .A(n3762), .B(n3758), .Y(n3753) );
AOI21X1TS U5236 ( .A0(n4641), .A1(n3754), .B0(n3753), .Y(n3755) );
OAI21X1TS U5237 ( .A0(n3756), .A1(n3766), .B0(n3755), .Y(
DP_OP_168J30_122_4811_n4329) );
CLKAND2X2TS U5238 ( .A(n3762), .B(n3764), .Y(n3757) );
AOI21X1TS U5239 ( .A0(n4641), .A1(n3758), .B0(n3757), .Y(n3759) );
OAI21X1TS U5240 ( .A0(n3760), .A1(n3766), .B0(n3759), .Y(
DP_OP_168J30_122_4811_n4328) );
CLKAND2X2TS U5241 ( .A(n3762), .B(n3761), .Y(n3763) );
AOI21X1TS U5242 ( .A0(n4641), .A1(n3764), .B0(n3763), .Y(n3765) );
OAI21X1TS U5243 ( .A0(n3767), .A1(n3766), .B0(n3765), .Y(
DP_OP_168J30_122_4811_n4327) );
CLKAND2X2TS U5244 ( .A(n2830), .B(Op_MY[15]), .Y(DP_OP_168J30_122_4811_n2615) );
INVX2TS U5245 ( .A(DP_OP_168J30_122_4811_n2615), .Y(
DP_OP_168J30_122_4811_n2257) );
INVX2TS U5246 ( .A(DP_OP_168J30_122_4811_n56), .Y(
DP_OP_168J30_122_4811_n1056) );
INVX2TS U5247 ( .A(DP_OP_168J30_122_4811_n2614), .Y(
DP_OP_168J30_122_4811_n2249) );
CLKAND2X2TS U5248 ( .A(n2848), .B(Op_MY[21]), .Y(DP_OP_168J30_122_4811_n2609) );
INVX2TS U5249 ( .A(DP_OP_168J30_122_4811_n2609), .Y(
DP_OP_168J30_122_4811_n2217) );
AOI222X1TS U5250 ( .A0(n4603), .A1(n4271), .B0(n4380), .B1(n4270), .C0(n4231), .C1(n4269), .Y(n3768) );
OAI21X1TS U5251 ( .A0(n4383), .A1(n2733), .B0(n3768), .Y(n3770) );
XOR2X1TS U5252 ( .A(n3770), .B(n3769), .Y(DP_OP_168J30_122_4811_n1231) );
BUFX6TS U5253 ( .A(n3771), .Y(n3811) );
AOI222X1TS U5254 ( .A0(n3811), .A1(n3778), .B0(n3810), .B1(n4459), .C0(n3809), .C1(n4458), .Y(n3772) );
XOR2X1TS U5255 ( .A(n3774), .B(n4657), .Y(DP_OP_168J30_122_4811_n2948) );
AOI222X1TS U5256 ( .A0(n3811), .A1(n3792), .B0(n4433), .B1(n3784), .C0(n3809), .C1(n3778), .Y(n3775) );
AOI222X1TS U5257 ( .A0(n3811), .A1(n3784), .B0(n3810), .B1(n3778), .C0(n3809), .C1(n4459), .Y(n3779) );
XOR2X1TS U5258 ( .A(n3781), .B(n4657), .Y(DP_OP_168J30_122_4811_n2947) );
AOI222X1TS U5259 ( .A0(n3811), .A1(n4459), .B0(n3810), .B1(n4458), .C0(n3809), .C1(n3061), .Y(n3782) );
XOR2X1TS U5260 ( .A(n3783), .B(n4657), .Y(DP_OP_168J30_122_4811_n2949) );
AOI222X1TS U5261 ( .A0(n3811), .A1(n3793), .B0(n4433), .B1(n3792), .C0(n3809), .C1(n3784), .Y(n3785) );
OAI21X1TS U5262 ( .A0(n3786), .A1(n1574), .B0(n3785), .Y(n3787) );
XOR2X1TS U5263 ( .A(n3787), .B(n4657), .Y(DP_OP_168J30_122_4811_n2945) );
AOI222X1TS U5264 ( .A0(n3811), .A1(n4453), .B0(n4433), .B1(n4452), .C0(n3809), .C1(n4451), .Y(n3788) );
OAI21X1TS U5265 ( .A0(n4455), .A1(n4435), .B0(n3788), .Y(n3789) );
XOR2X1TS U5266 ( .A(n3789), .B(n4437), .Y(DP_OP_168J30_122_4811_n2956) );
AOI222X1TS U5267 ( .A0(n3811), .A1(n4452), .B0(n4433), .B1(n4451), .C0(n3809), .C1(n4443), .Y(n3790) );
XOR2X1TS U5268 ( .A(n3791), .B(n4437), .Y(DP_OP_168J30_122_4811_n2957) );
AOI222X1TS U5269 ( .A0(n3811), .A1(Op_MY[26]), .B0(n4433), .B1(n3793), .C0(
n3809), .C1(n3792), .Y(n3794) );
OAI21X1TS U5270 ( .A0(n3795), .A1(n1574), .B0(n3794), .Y(n3796) );
XOR2X1TS U5271 ( .A(n3796), .B(n4657), .Y(DP_OP_168J30_122_4811_n2944) );
AOI222X1TS U5272 ( .A0(n3811), .A1(n4463), .B0(n3810), .B1(n4453), .C0(n3809), .C1(n4452), .Y(n3797) );
OAI21X1TS U5273 ( .A0(n3798), .A1(n1574), .B0(n3797), .Y(n3799) );
XOR2X1TS U5274 ( .A(n3799), .B(n4657), .Y(DP_OP_168J30_122_4811_n2955) );
AOI222X1TS U5275 ( .A0(n3811), .A1(n4514), .B0(n3810), .B1(n4463), .C0(n3809), .C1(n4453), .Y(n3800) );
XOR2X1TS U5276 ( .A(n3802), .B(n4657), .Y(DP_OP_168J30_122_4811_n2954) );
AOI222X1TS U5277 ( .A0(n3811), .A1(n4470), .B0(n3810), .B1(n4516), .C0(n3809), .C1(n4514), .Y(n3803) );
XOR2X1TS U5278 ( .A(n3804), .B(n4657), .Y(DP_OP_168J30_122_4811_n2952) );
AOI222X1TS U5279 ( .A0(n3811), .A1(n4458), .B0(n3810), .B1(n3061), .C0(n3809), .C1(n4470), .Y(n3805) );
XOR2X1TS U5280 ( .A(n3806), .B(n4657), .Y(DP_OP_168J30_122_4811_n2950) );
AOI222X1TS U5281 ( .A0(n3811), .A1(n4516), .B0(n3810), .B1(n4514), .C0(n3809), .C1(n4463), .Y(n3807) );
XOR2X1TS U5282 ( .A(n3808), .B(n4657), .Y(DP_OP_168J30_122_4811_n2953) );
AOI222X1TS U5283 ( .A0(n3811), .A1(n3061), .B0(n3810), .B1(n4470), .C0(n3809), .C1(n4516), .Y(n3812) );
XOR2X1TS U5284 ( .A(n3813), .B(n4657), .Y(DP_OP_168J30_122_4811_n2951) );
INVX2TS U5285 ( .A(n4875), .Y(DP_OP_168J30_122_4811_n810) );
AOI222X1TS U5286 ( .A0(n4361), .A1(n4362), .B0(n4656), .B1(n4360), .C0(n4655), .C1(n2690), .Y(n3819) );
XOR2X1TS U5287 ( .A(n3820), .B(n4264), .Y(DP_OP_168J30_122_4811_n1164) );
AO22XLTS U5288 ( .A0(n2644), .A1(n4303), .B0(n3917), .B1(n4477), .Y(n3821)
);
INVX2TS U5289 ( .A(n3821), .Y(n3822) );
XOR2X1TS U5290 ( .A(n3823), .B(n4377), .Y(DP_OP_168J30_122_4811_n1147) );
AOI222X1TS U5291 ( .A0(n4501), .A1(n4508), .B0(n2238), .B1(n4509), .C0(n4500), .C1(n4493), .Y(n3824) );
XOR2XLTS U5292 ( .A(n3825), .B(n4503), .Y(DP_OP_168J30_122_4811_n990) );
INVX2TS U5293 ( .A(n3826), .Y(DP_OP_168J30_122_4811_n1968) );
XOR2X1TS U5294 ( .A(n3827), .B(n4377), .Y(DP_OP_168J30_122_4811_n1148) );
NAND2X1TS U5295 ( .A(n2580), .B(n4477), .Y(n3828) );
XOR2X1TS U5296 ( .A(n3829), .B(n4384), .Y(DP_OP_168J30_122_4811_n1117) );
XOR2X1TS U5297 ( .A(n3831), .B(n4384), .Y(n3915) );
AOI222X1TS U5298 ( .A0(n4363), .A1(n3943), .B0(n4361), .B1(n3917), .C0(n4656), .C1(n2646), .Y(n3832) );
XOR2X1TS U5299 ( .A(n3833), .B(n4669), .Y(n3914) );
AOI222X1TS U5300 ( .A0(n4361), .A1(n3943), .B0(n4656), .B1(n3917), .C0(n4655), .C1(n2646), .Y(n3834) );
XOR2X1TS U5301 ( .A(n3836), .B(n4377), .Y(n3949) );
XOR2X1TS U5302 ( .A(n3838), .B(n4384), .Y(n3948) );
XOR2X1TS U5303 ( .A(n3840), .B(DP_OP_168J30_122_4811_n56), .Y(n3841) );
CMPR32X2TS U5304 ( .A(n3843), .B(n3842), .C(n3841), .CO(
DP_OP_168J30_122_4811_n536), .S(DP_OP_168J30_122_4811_n537) );
AOI21X1TS U5305 ( .A0(n4641), .A1(Op_MY[32]), .B0(n3845), .Y(n3846) );
OAI21X1TS U5306 ( .A0(n4626), .A1(n4643), .B0(n3846), .Y(n3847) );
CMPR32X2TS U5307 ( .A(n759), .B(n732), .C(n3847), .CO(
DP_OP_168J30_122_4811_n3994), .S(DP_OP_168J30_122_4811_n3995) );
AOI222X1TS U5308 ( .A0(n3811), .A1(n4451), .B0(n4433), .B1(n4443), .C0(n3809), .C1(n4439), .Y(n3848) );
XOR2X1TS U5309 ( .A(n3849), .B(n4437), .Y(DP_OP_168J30_122_4811_n2958) );
XOR2X1TS U5310 ( .A(n3851), .B(n3980), .Y(n3879) );
NAND2X1TS U5311 ( .A(n3862), .B(n4584), .Y(n3852) );
XOR2X1TS U5312 ( .A(n3853), .B(n3867), .Y(n3866) );
XOR2X1TS U5313 ( .A(n3855), .B(n3980), .Y(n3984) );
AOI22X1TS U5314 ( .A0(n3342), .A1(n4584), .B0(n3874), .B1(n4594), .Y(n3856)
);
XOR2X1TS U5315 ( .A(n3857), .B(n3980), .Y(n3982) );
NAND2X1TS U5316 ( .A(n3874), .B(n4584), .Y(n3858) );
XOR2X1TS U5317 ( .A(n3859), .B(n3980), .Y(n3979) );
AOI222X1TS U5318 ( .A0(n3862), .A1(n3872), .B0(n3863), .B1(n4594), .C0(n3281), .C1(n4584), .Y(n3860) );
XOR2X1TS U5319 ( .A(n3861), .B(n3867), .Y(n4558) );
AOI22X1TS U5320 ( .A0(n3863), .A1(n4584), .B0(n3862), .B1(n4594), .Y(n3864)
);
XOR2X1TS U5321 ( .A(n3865), .B(n3867), .Y(n3871) );
ADDHXLTS U5322 ( .A(n3867), .B(n3866), .CO(n3870), .S(n3878) );
OAI21X1TS U5323 ( .A0(n4633), .A1(n3339), .B0(n3868), .Y(n3869) );
XOR2X1TS U5324 ( .A(n3869), .B(n3980), .Y(n3881) );
ADDHXLTS U5325 ( .A(n3871), .B(n3870), .CO(n4557), .S(n3987) );
XOR2X1TS U5326 ( .A(n3876), .B(n3980), .Y(n3986) );
CMPR32X2TS U5327 ( .A(n3879), .B(n3878), .C(n3877), .CO(n3985), .S(
DP_OP_168J30_122_4811_n4133) );
CMPR32X2TS U5328 ( .A(n3882), .B(n3881), .C(n3880), .CO(
DP_OP_168J30_122_4811_n4112), .S(DP_OP_168J30_122_4811_n4113) );
NAND2X1TS U5329 ( .A(n4646), .B(n4584), .Y(n3883) );
XOR2X1TS U5330 ( .A(n3884), .B(n4649), .Y(n3895) );
XOR2X1TS U5331 ( .A(n3886), .B(n4649), .Y(n4590) );
NAND2X1TS U5332 ( .A(n4639), .B(n4584), .Y(n3887) );
XOR2X1TS U5333 ( .A(n3889), .B(n4649), .Y(n3990) );
XOR2X1TS U5334 ( .A(n3891), .B(n4649), .Y(n4580) );
AOI22X1TS U5335 ( .A0(n4645), .A1(n4584), .B0(n4646), .B1(n4594), .Y(n3892)
);
XOR2X1TS U5336 ( .A(n3894), .B(n4649), .Y(n4577) );
ADDHX1TS U5337 ( .A(n3899), .B(n3898), .CO(n3896), .S(
DP_OP_168J30_122_4811_n2484) );
ADDHXLTS U5338 ( .A(n3901), .B(n3900), .CO(DP_OP_168J30_122_4811_n2435), .S(
n2823) );
XOR2X1TS U5339 ( .A(n3903), .B(n4668), .Y(n4119) );
XOR2X1TS U5340 ( .A(n3905), .B(n4668), .Y(n4115) );
XOR2X1TS U5341 ( .A(n3907), .B(n4668), .Y(DP_OP_168J30_122_4811_n1222) );
XOR2X1TS U5342 ( .A(n3909), .B(n4668), .Y(DP_OP_168J30_122_4811_n1217) );
AOI222X1TS U5343 ( .A0(n3911), .A1(n3910), .B0(n2574), .B1(n4655), .C0(n2573), .C1(n4630), .Y(n3912) );
XOR2X1TS U5344 ( .A(n3913), .B(n4384), .Y(n4302) );
AOI222X1TS U5345 ( .A0(n4549), .A1(n3943), .B0(n4363), .B1(n3917), .C0(n3916), .C1(n2646), .Y(n3918) );
XOR2X1TS U5346 ( .A(n3920), .B(n4669), .Y(n3926) );
XOR2X1TS U5347 ( .A(n3924), .B(DP_OP_168J30_122_4811_n56), .Y(n3925) );
CMPR32X2TS U5348 ( .A(n3927), .B(n3926), .C(n3925), .CO(
DP_OP_168J30_122_4811_n520), .S(DP_OP_168J30_122_4811_n521) );
XOR2X1TS U5349 ( .A(n3929), .B(n4668), .Y(DP_OP_168J30_122_4811_n1223) );
XOR2X1TS U5350 ( .A(n3931), .B(n4377), .Y(n4161) );
OAI21X1TS U5351 ( .A0(n4376), .A1(n2656), .B0(n3932), .Y(n3933) );
XOR2X1TS U5352 ( .A(n3933), .B(n4264), .Y(n4160) );
OAI21X1TS U5353 ( .A0(n4221), .A1(n4365), .B0(n3934), .Y(n3935) );
XOR2X1TS U5354 ( .A(n3935), .B(n4264), .Y(n4215) );
XOR2X1TS U5355 ( .A(n3937), .B(n4377), .Y(n4214) );
XOR2X1TS U5356 ( .A(n3939), .B(n4384), .Y(n3940) );
CMPR32X2TS U5357 ( .A(n3942), .B(n3941), .C(n3940), .CO(
DP_OP_168J30_122_4811_n620), .S(DP_OP_168J30_122_4811_n621) );
AOI222X1TS U5358 ( .A0(n4656), .A1(n3943), .B0(n4655), .B1(n3917), .C0(n2646), .C1(n2725), .Y(n3944) );
OAI21X1TS U5359 ( .A0(n4163), .A1(n3919), .B0(n3944), .Y(n3945) );
XOR2X1TS U5360 ( .A(n3945), .B(n4377), .Y(n3951) );
XOR2X1TS U5361 ( .A(n3947), .B(n4384), .Y(n3950) );
ADDHXLTS U5362 ( .A(n3949), .B(n3948), .CO(n3842), .S(n3953) );
CMPR32X2TS U5363 ( .A(n3953), .B(n3952), .C(DP_OP_168J30_122_4811_n565),
.CO(DP_OP_168J30_122_4811_n552), .S(DP_OP_168J30_122_4811_n553) );
ADDHXLTS U5364 ( .A(n3955), .B(n3954), .CO(DP_OP_168J30_122_4811_n4198), .S(
n4053) );
XOR2X1TS U5365 ( .A(n3958), .B(n3957), .Y(DP_OP_168J30_122_4811_n1055) );
ADDHXLTS U5366 ( .A(n3965), .B(n3964), .CO(DP_OP_168J30_122_4811_n4165), .S(
n3219) );
XOR2X1TS U5367 ( .A(n3967), .B(DP_OP_168J30_122_4811_n66), .Y(n3975) );
XOR2X1TS U5368 ( .A(n3969), .B(DP_OP_168J30_122_4811_n56), .Y(n3974) );
XOR2X1TS U5369 ( .A(n3973), .B(DP_OP_168J30_122_4811_n56), .Y(n3977) );
CMPR32X2TS U5370 ( .A(n3975), .B(n3974), .C(DP_OP_168J30_122_4811_n415),
.CO(n3976), .S(DP_OP_168J30_122_4811_n402) );
CMPR32X2TS U5371 ( .A(n3978), .B(n3977), .C(n3976), .CO(
DP_OP_168J30_122_4811_n387), .S(DP_OP_168J30_122_4811_n388) );
CMPR32X2TS U5372 ( .A(n3987), .B(n3986), .C(n3985), .CO(n3880), .S(
DP_OP_168J30_122_4811_n4123) );
CMPR32X2TS U5373 ( .A(n3990), .B(n3989), .C(n3988), .CO(n4588), .S(
DP_OP_168J30_122_4811_n4072) );
XOR2X1TS U5374 ( .A(n3992), .B(n2361), .Y(n4001) );
XOR2X1TS U5375 ( .A(n3994), .B(DP_OP_168J30_122_4811_n66), .Y(n4000) );
CMPR32X2TS U5376 ( .A(n4001), .B(n4000), .C(DP_OP_168J30_122_4811_n334),
.CO(n4002), .S(DP_OP_168J30_122_4811_n324) );
CMPR32X2TS U5377 ( .A(n4004), .B(n4003), .C(n4002), .CO(
DP_OP_168J30_122_4811_n312), .S(DP_OP_168J30_122_4811_n313) );
OAI21X1TS U5378 ( .A0(n836), .A1(n2313), .B0(n4005), .Y(n4006) );
AOI222X1TS U5379 ( .A0(n4009), .A1(n4008), .B0(n4007), .B1(n4327), .C0(n2231), .C1(n4658), .Y(n4010) );
XOR2X1TS U5380 ( .A(n4012), .B(DP_OP_168J30_122_4811_n86), .Y(n4013) );
CMPR32X2TS U5381 ( .A(n4015), .B(n4014), .C(n4013), .CO(
DP_OP_168J30_122_4811_n255), .S(DP_OP_168J30_122_4811_n256) );
OAI21XLTS U5382 ( .A0(n3120), .A1(n859), .B0(n850), .Y(n4016) );
XOR2X1TS U5383 ( .A(n4016), .B(n4419), .Y(n4018) );
OAI21XLTS U5384 ( .A0(n3118), .A1(n4083), .B0(n851), .Y(n4017) );
XOR2X1TS U5385 ( .A(n4017), .B(n4419), .Y(n4022) );
ADDHX1TS U5386 ( .A(n4419), .B(n4018), .CO(n4021), .S(
DP_OP_168J30_122_4811_n2585) );
AOI222X1TS U5387 ( .A0(n3121), .A1(n4178), .B0(n4416), .B1(n4131), .C0(n3116), .C1(Op_MY[0]), .Y(n4019) );
OAI21XLTS U5388 ( .A0(n4079), .A1(n3118), .B0(n4019), .Y(n4020) );
XOR2X1TS U5389 ( .A(n4020), .B(n4419), .Y(n4029) );
ADDHX1TS U5390 ( .A(n4022), .B(n4021), .CO(n4028), .S(
DP_OP_168J30_122_4811_n2580) );
AOI222X1TS U5391 ( .A0(n3121), .A1(n4110), .B0(n4416), .B1(n4178), .C0(n3116), .C1(n4131), .Y(n4023) );
OAI21XLTS U5392 ( .A0(n4133), .A1(n3118), .B0(n4023), .Y(n4024) );
XOR2X1TS U5393 ( .A(n4024), .B(n4419), .Y(n4040) );
NAND2X1TS U5394 ( .A(n4025), .B(Op_MY[0]), .Y(n4026) );
XOR2X1TS U5395 ( .A(n4027), .B(n4423), .Y(n4033) );
ADDHX1TS U5396 ( .A(n4029), .B(n4028), .CO(n4038), .S(
DP_OP_168J30_122_4811_n2575) );
AOI222X1TS U5397 ( .A0(n4517), .A1(n4178), .B0(n4515), .B1(n4131), .C0(n3075), .C1(n4081), .Y(n4030) );
OAI21XLTS U5398 ( .A0(n4079), .A1(n4422), .B0(n4030), .Y(n4031) );
XOR2XLTS U5399 ( .A(n4031), .B(n4423), .Y(n4042) );
OAI21XLTS U5400 ( .A0(n4422), .A1(n4083), .B0(n848), .Y(n4032) );
XOR2XLTS U5401 ( .A(n4032), .B(n4423), .Y(n4035) );
ADDHXLTS U5402 ( .A(n4423), .B(n4033), .CO(n4034), .S(n4039) );
AOI222X1TS U5403 ( .A0(n3121), .A1(n4139), .B0(n4416), .B1(n4110), .C0(n3112), .C1(n4178), .Y(n4036) );
OAI21XLTS U5404 ( .A0(n4180), .A1(n3118), .B0(n4036), .Y(n4037) );
XOR2X1TS U5405 ( .A(n4037), .B(n4419), .Y(n4046) );
CMPR32X2TS U5406 ( .A(n4040), .B(n4039), .C(n4038), .CO(n4045), .S(
DP_OP_168J30_122_4811_n2568) );
ADDHXLTS U5407 ( .A(n4042), .B(n4041), .CO(DP_OP_168J30_122_4811_n2555), .S(
n4050) );
AOI222X1TS U5408 ( .A0(n3121), .A1(n4196), .B0(n4416), .B1(n4139), .C0(n3112), .C1(n4110), .Y(n4043) );
OAI21XLTS U5409 ( .A0(n4295), .A1(n3118), .B0(n4043), .Y(n4044) );
XOR2X1TS U5410 ( .A(n4044), .B(n4419), .Y(n4049) );
CMPR32X2TS U5411 ( .A(n4047), .B(n4046), .C(n4045), .CO(n4048), .S(
DP_OP_168J30_122_4811_n2561) );
CMPR32X2TS U5412 ( .A(n4050), .B(n4049), .C(n4048), .CO(
DP_OP_168J30_122_4811_n2553), .S(DP_OP_168J30_122_4811_n2554) );
CMPR32X2TS U5413 ( .A(n4053), .B(n4052), .C(n4051), .CO(
DP_OP_168J30_122_4811_n4196), .S(n1146) );
ADDHXLTS U5414 ( .A(n4055), .B(n4054), .CO(DP_OP_168J30_122_4811_n2588), .S(
n4058) );
CMPR32X2TS U5415 ( .A(n4058), .B(n4057), .C(n4056), .CO(
DP_OP_168J30_122_4811_n2586), .S(n1542) );
AOI222X1TS U5416 ( .A0(n4517), .A1(n4110), .B0(n3079), .B1(n4178), .C0(n4513), .C1(n4131), .Y(n4059) );
XOR2X1TS U5417 ( .A(n4060), .B(n4423), .Y(DP_OP_168J30_122_4811_n2877) );
AOI222X1TS U5418 ( .A0(n4472), .A1(n4110), .B0(n4444), .B1(n4178), .C0(n4469), .C1(n4131), .Y(n4061) );
OAI21XLTS U5419 ( .A0(n4133), .A1(n4474), .B0(n4061), .Y(n4062) );
XOR2X1TS U5420 ( .A(n4062), .B(n4456), .Y(DP_OP_168J30_122_4811_n2937) );
NAND2X1TS U5421 ( .A(n4067), .B(n4081), .Y(n4063) );
XOR2X1TS U5422 ( .A(n4064), .B(n4670), .Y(n4066) );
OAI21XLTS U5423 ( .A0(n3026), .A1(n4083), .B0(n911), .Y(n4065) );
XOR2X1TS U5424 ( .A(n4065), .B(n4670), .Y(n4071) );
AOI222X1TS U5425 ( .A0(n4067), .A1(n4178), .B0(n4392), .B1(n4131), .C0(n3023), .C1(n4081), .Y(n4068) );
OAI21XLTS U5426 ( .A0(n4079), .A1(n3026), .B0(n4068), .Y(n4069) );
XOR2X1TS U5427 ( .A(n4069), .B(n4670), .Y(n4077) );
ADDHX1TS U5428 ( .A(n4071), .B(n4070), .CO(n4076), .S(
DP_OP_168J30_122_4811_n2541) );
AOI222X1TS U5429 ( .A0(n4393), .A1(n4110), .B0(n4392), .B1(n4178), .C0(n3023), .C1(n4131), .Y(n4072) );
OAI21XLTS U5430 ( .A0(n4133), .A1(n3026), .B0(n4072), .Y(n4073) );
XOR2X1TS U5431 ( .A(n4073), .B(n4670), .Y(n4092) );
NAND2X1TS U5432 ( .A(n2975), .B(n4081), .Y(n4074) );
OAI21XLTS U5433 ( .A0(n2970), .A1(n859), .B0(n4074), .Y(n4075) );
XOR2X1TS U5434 ( .A(n4075), .B(n4296), .Y(n4085) );
ADDHX1TS U5435 ( .A(n4077), .B(n4076), .CO(n4090), .S(
DP_OP_168J30_122_4811_n2533) );
AOI222X1TS U5436 ( .A0(n2972), .A1(n4178), .B0(n2966), .B1(n4131), .C0(n2965), .C1(n4081), .Y(n4078) );
OAI21XLTS U5437 ( .A0(n4079), .A1(n2968), .B0(n4078), .Y(n4080) );
XOR2XLTS U5438 ( .A(n4080), .B(n4296), .Y(n4094) );
OAI21XLTS U5439 ( .A0(n2968), .A1(n4083), .B0(n4082), .Y(n4084) );
XOR2XLTS U5440 ( .A(n4084), .B(n4296), .Y(n4087) );
ADDHXLTS U5441 ( .A(n4296), .B(n4085), .CO(n4086), .S(n4091) );
AOI222X1TS U5442 ( .A0(n4393), .A1(n4139), .B0(n4392), .B1(n4110), .C0(n3020), .C1(n4178), .Y(n4088) );
OAI21XLTS U5443 ( .A0(n4180), .A1(n3026), .B0(n4088), .Y(n4089) );
XOR2X1TS U5444 ( .A(n4089), .B(n4670), .Y(n4098) );
CMPR32X2TS U5445 ( .A(n4092), .B(n4091), .C(n4090), .CO(n4097), .S(
DP_OP_168J30_122_4811_n2523) );
ADDHXLTS U5446 ( .A(n4094), .B(n4093), .CO(DP_OP_168J30_122_4811_n2504), .S(
n4102) );
AOI222X1TS U5447 ( .A0(n4393), .A1(n4196), .B0(n4392), .B1(n4139), .C0(n3020), .C1(n4110), .Y(n4095) );
OAI21XLTS U5448 ( .A0(n4295), .A1(n3026), .B0(n4095), .Y(n4096) );
XOR2X1TS U5449 ( .A(n4096), .B(n4670), .Y(n4101) );
CMPR32X2TS U5450 ( .A(n4099), .B(n4098), .C(n4097), .CO(n4100), .S(
DP_OP_168J30_122_4811_n2513) );
CMPR32X2TS U5451 ( .A(n4102), .B(n4101), .C(n4100), .CO(
DP_OP_168J30_122_4811_n2502), .S(DP_OP_168J30_122_4811_n2503) );
AOI222X1TS U5452 ( .A0(n4517), .A1(n4139), .B0(n3079), .B1(n4110), .C0(n4513), .C1(n4178), .Y(n4103) );
OAI21XLTS U5453 ( .A0(n4180), .A1(n4422), .B0(n4103), .Y(n4104) );
XOR2X1TS U5454 ( .A(n4104), .B(n4423), .Y(DP_OP_168J30_122_4811_n2876) );
AOI222X1TS U5455 ( .A0(n4472), .A1(n4139), .B0(n4444), .B1(n4110), .C0(n4469), .C1(n4178), .Y(n4105) );
OAI21XLTS U5456 ( .A0(n4180), .A1(n4474), .B0(n4105), .Y(n4106) );
XOR2X1TS U5457 ( .A(n4106), .B(n4456), .Y(DP_OP_168J30_122_4811_n2936) );
AOI222X1TS U5458 ( .A0(n4517), .A1(n4196), .B0(n3079), .B1(n4139), .C0(n4513), .C1(Op_MY[3]), .Y(n4107) );
OAI21XLTS U5459 ( .A0(n4295), .A1(n4422), .B0(n4107), .Y(n4108) );
XOR2X1TS U5460 ( .A(n4108), .B(n4423), .Y(DP_OP_168J30_122_4811_n2875) );
ADDHXLTS U5461 ( .A(n2930), .B(n4109), .CO(n3898), .S(
DP_OP_168J30_122_4811_n2495) );
AOI222X1TS U5462 ( .A0(n4472), .A1(n4196), .B0(n4444), .B1(n4139), .C0(n4469), .C1(n4110), .Y(n4111) );
OAI21XLTS U5463 ( .A0(n4295), .A1(n4474), .B0(n4111), .Y(n4112) );
XOR2X1TS U5464 ( .A(n4112), .B(n4456), .Y(DP_OP_168J30_122_4811_n2935) );
AOI222X1TS U5465 ( .A0(n4517), .A1(n4309), .B0(n4515), .B1(n4196), .C0(n4513), .C1(Op_MY[4]), .Y(n4113) );
OAI21XLTS U5466 ( .A0(n4141), .A1(n4422), .B0(n4113), .Y(n4114) );
XOR2X1TS U5467 ( .A(n4114), .B(n4423), .Y(DP_OP_168J30_122_4811_n2874) );
OAI21X1TS U5468 ( .A0(n4498), .A1(n4317), .B0(n4116), .Y(n4117) );
XOR2X1TS U5469 ( .A(n4117), .B(n4668), .Y(n4124) );
XOR2X1TS U5470 ( .A(n4122), .B(n4410), .Y(n4128) );
INVX2TS U5471 ( .A(n4125), .Y(n4126) );
CMPR32X2TS U5472 ( .A(n4128), .B(n4127), .C(n4126), .CO(
DP_OP_168J30_122_4811_n741), .S(DP_OP_168J30_122_4811_n742) );
AOI222X1TS U5473 ( .A0(n4472), .A1(n4309), .B0(n4444), .B1(n4196), .C0(n4469), .C1(n4139), .Y(n4129) );
OAI21XLTS U5474 ( .A0(n4141), .A1(n4474), .B0(n4129), .Y(n4130) );
XOR2X1TS U5475 ( .A(n4130), .B(n4456), .Y(DP_OP_168J30_122_4811_n2934) );
AOI222X1TS U5476 ( .A0(n2972), .A1(n4110), .B0(n2971), .B1(n4178), .C0(n2962), .C1(n4131), .Y(n4132) );
OAI21XLTS U5477 ( .A0(n4133), .A1(n2968), .B0(n4132), .Y(n4134) );
XOR2X1TS U5478 ( .A(n4134), .B(n4296), .Y(DP_OP_168J30_122_4811_n2817) );
AOI222X1TS U5479 ( .A0(n3811), .A1(n4309), .B0(n4433), .B1(n4196), .C0(n3809), .C1(n4139), .Y(n4135) );
OAI21XLTS U5480 ( .A0(n4141), .A1(n4435), .B0(n4135), .Y(n4136) );
XOR2X1TS U5481 ( .A(n4136), .B(n4437), .Y(DP_OP_168J30_122_4811_n2964) );
AOI222X1TS U5482 ( .A0(n4517), .A1(n4356), .B0(n4515), .B1(n4309), .C0(n4513), .C1(Op_MY[5]), .Y(n4137) );
OAI21XLTS U5483 ( .A0(n4354), .A1(n4422), .B0(n4137), .Y(n4138) );
XOR2X1TS U5484 ( .A(n4138), .B(n4423), .Y(DP_OP_168J30_122_4811_n2873) );
AOI222X1TS U5485 ( .A0(n3121), .A1(n4309), .B0(n4416), .B1(n4196), .C0(n3112), .C1(n4139), .Y(n4140) );
OAI21XLTS U5486 ( .A0(n4141), .A1(n3118), .B0(n4140), .Y(n4142) );
XOR2X1TS U5487 ( .A(n4142), .B(n4419), .Y(DP_OP_168J30_122_4811_n2904) );
INVX2TS U5488 ( .A(n4143), .Y(DP_OP_168J30_122_4811_n1992) );
INVX2TS U5489 ( .A(n4144), .Y(DP_OP_168J30_122_4811_n1993) );
INVX2TS U5490 ( .A(n4145), .Y(DP_OP_168J30_122_4811_n1991) );
AOI222X1TS U5491 ( .A0(n4472), .A1(n4356), .B0(n4444), .B1(n4309), .C0(n4469), .C1(n4196), .Y(n4146) );
OAI21XLTS U5492 ( .A0(n4354), .A1(n3129), .B0(n4146), .Y(n4147) );
XOR2X1TS U5493 ( .A(n4147), .B(n4456), .Y(DP_OP_168J30_122_4811_n2933) );
INVX2TS U5494 ( .A(n4148), .Y(n4150) );
INVX2TS U5495 ( .A(n4818), .Y(n4157) );
XOR2X1TS U5496 ( .A(n4153), .B(n4668), .Y(n4156) );
INVX2TS U5497 ( .A(n4154), .Y(n4155) );
CMPR32X2TS U5498 ( .A(n4157), .B(n4156), .C(n4155), .CO(
DP_OP_168J30_122_4811_n734), .S(DP_OP_168J30_122_4811_n735) );
OAI21X1TS U5499 ( .A0(n3919), .A1(n4253), .B0(n4158), .Y(n4159) );
XOR2X1TS U5500 ( .A(n4159), .B(n4377), .Y(n4224) );
AOI222X1TS U5501 ( .A0(n4656), .A1(n4362), .B0(n4655), .B1(n4360), .C0(n2725), .C1(n2690), .Y(n4162) );
XOR2X1TS U5502 ( .A(n4164), .B(n4264), .Y(n4168) );
XOR2X1TS U5503 ( .A(n4166), .B(n4384), .Y(n4167) );
CMPR32X2TS U5504 ( .A(n4169), .B(n4168), .C(n4167), .CO(
DP_OP_168J30_122_4811_n607), .S(DP_OP_168J30_122_4811_n608) );
AOI222X1TS U5505 ( .A0(n4517), .A1(n4415), .B0(n4515), .B1(n4356), .C0(n4513), .C1(Op_MY[6]), .Y(n4170) );
OAI21XLTS U5506 ( .A0(n4395), .A1(n4422), .B0(n4170), .Y(n4171) );
XOR2X1TS U5507 ( .A(n4171), .B(n4423), .Y(DP_OP_168J30_122_4811_n2872) );
AOI222X1TS U5508 ( .A0(n3811), .A1(n4356), .B0(n4433), .B1(n4309), .C0(n3809), .C1(n4196), .Y(n4172) );
OAI21XLTS U5509 ( .A0(n4354), .A1(n4435), .B0(n4172), .Y(n4173) );
XOR2X1TS U5510 ( .A(n4173), .B(n4437), .Y(DP_OP_168J30_122_4811_n2963) );
XOR2X1TS U5511 ( .A(n4175), .B(n4410), .Y(n4238) );
XOR2X1TS U5512 ( .A(n4177), .B(n4264), .Y(n4237) );
AOI222X1TS U5513 ( .A0(n2972), .A1(Op_MY[4]), .B0(n2971), .B1(Op_MY[3]),
.C0(n2962), .C1(n4178), .Y(n4179) );
OAI21XLTS U5514 ( .A0(n4180), .A1(n2968), .B0(n4179), .Y(n4181) );
XOR2X1TS U5515 ( .A(n4181), .B(n4296), .Y(DP_OP_168J30_122_4811_n2816) );
AO22XLTS U5516 ( .A0(n4262), .A1(n4303), .B0(n4360), .B1(n4477), .Y(n4182)
);
INVX2TS U5517 ( .A(n4182), .Y(n4183) );
XOR2X1TS U5518 ( .A(n4184), .B(n4264), .Y(DP_OP_168J30_122_4811_n1178) );
XOR2X1TS U5519 ( .A(n4186), .B(n4410), .Y(DP_OP_168J30_122_4811_n1208) );
INVX2TS U5520 ( .A(n4872), .Y(n4195) );
XOR2X1TS U5521 ( .A(n4191), .B(n4668), .Y(n4194) );
INVX2TS U5522 ( .A(n4192), .Y(n4193) );
CMPR32X2TS U5523 ( .A(n4195), .B(n4194), .C(n4193), .CO(
DP_OP_168J30_122_4811_n727), .S(DP_OP_168J30_122_4811_n728) );
AOI222X1TS U5524 ( .A0(n3121), .A1(n4356), .B0(n4416), .B1(n4309), .C0(n3112), .C1(n4196), .Y(n4197) );
OAI21XLTS U5525 ( .A0(n4354), .A1(n3118), .B0(n4197), .Y(n4198) );
XOR2X1TS U5526 ( .A(n4198), .B(n4419), .Y(DP_OP_168J30_122_4811_n2903) );
XOR2X1TS U5527 ( .A(n4200), .B(n4264), .Y(n4208) );
XOR2X1TS U5528 ( .A(n4202), .B(n4264), .Y(n4251) );
XOR2X1TS U5529 ( .A(n4204), .B(n4264), .Y(n4240) );
XOR2X1TS U5530 ( .A(n4206), .B(n4410), .Y(n4239) );
XOR2X1TS U5531 ( .A(n4210), .B(n4264), .Y(n4217) );
XOR2X1TS U5532 ( .A(n4213), .B(n4377), .Y(n4216) );
ADDHXLTS U5533 ( .A(n4215), .B(n4214), .CO(n3941), .S(n4219) );
CMPR32X2TS U5534 ( .A(n4219), .B(n4218), .C(DP_OP_168J30_122_4811_n643),
.CO(DP_OP_168J30_122_4811_n633), .S(DP_OP_168J30_122_4811_n634) );
XOR2X1TS U5535 ( .A(n4222), .B(n4377), .Y(n4226) );
ADDHXLTS U5536 ( .A(n4224), .B(n4223), .CO(n4225), .S(n4169) );
AOI21X1TS U5537 ( .A0(n4315), .A1(n4330), .B0(n4228), .Y(n4229) );
XOR2X1TS U5538 ( .A(n4230), .B(n2700), .Y(DP_OP_168J30_122_4811_n1182) );
XOR2X1TS U5539 ( .A(n4234), .B(n4410), .Y(n4242) );
XOR2X1TS U5540 ( .A(n4236), .B(n4264), .Y(n4241) );
ADDHXLTS U5541 ( .A(n4242), .B(n4241), .CO(n4246), .S(n4244) );
CMPR32X2TS U5542 ( .A(n4244), .B(n4243), .C(n4613), .CO(n4245), .S(
DP_OP_168J30_122_4811_n697) );
CMPR32X2TS U5543 ( .A(n4247), .B(n4246), .C(n4245), .CO(
DP_OP_168J30_122_4811_n686), .S(DP_OP_168J30_122_4811_n687) );
OAI21X1TS U5544 ( .A0(n840), .A1(n4317), .B0(n4248), .Y(n4249) );
XOR2X1TS U5545 ( .A(n4249), .B(n4668), .Y(DP_OP_168J30_122_4811_n1219) );
OAI21X1TS U5546 ( .A0(n4253), .A1(n4408), .B0(n4252), .Y(n4254) );
XOR2X1TS U5547 ( .A(n4254), .B(n4410), .Y(n4258) );
XOR2X1TS U5548 ( .A(n4256), .B(n4377), .Y(n4257) );
CMPR32X2TS U5549 ( .A(n4259), .B(n4258), .C(n4257), .CO(
DP_OP_168J30_122_4811_n676), .S(DP_OP_168J30_122_4811_n677) );
OAI21XLTS U5550 ( .A0(n2656), .A1(n4495), .B0(n4263), .Y(n4265) );
XOR2X1TS U5551 ( .A(n4265), .B(n4264), .Y(DP_OP_168J30_122_4811_n1177) );
AOI222X1TS U5552 ( .A0(n4544), .A1(n4332), .B0(n4614), .B1(n4331), .C0(n4550), .C1(n4330), .Y(n4266) );
XOR2X1TS U5553 ( .A(n4268), .B(n4410), .Y(DP_OP_168J30_122_4811_n1190) );
OAI21X1TS U5554 ( .A0(n4488), .A1(n4317), .B0(n4272), .Y(n4273) );
XOR2X1TS U5555 ( .A(n4273), .B(n4668), .Y(n4282) );
AOI222X1TS U5556 ( .A0(n4472), .A1(n4415), .B0(n4444), .B1(n4356), .C0(n4469), .C1(n4309), .Y(n4274) );
OAI21XLTS U5557 ( .A0(n4395), .A1(n3129), .B0(n4274), .Y(n4275) );
XOR2X1TS U5558 ( .A(n4275), .B(n4456), .Y(DP_OP_168J30_122_4811_n2932) );
INVX2TS U5559 ( .A(n4276), .Y(DP_OP_168J30_122_4811_n1987) );
AOI222X1TS U5560 ( .A0(n4517), .A1(n4432), .B0(n4515), .B1(n4415), .C0(n4513), .C1(Op_MY[7]), .Y(n4277) );
OAI21XLTS U5561 ( .A0(n4358), .A1(n4422), .B0(n4277), .Y(n4278) );
XOR2X1TS U5562 ( .A(n4278), .B(n4423), .Y(DP_OP_168J30_122_4811_n2871) );
XOR2X1TS U5563 ( .A(n4281), .B(n4410), .Y(n4287) );
ADDHXLTS U5564 ( .A(n4264), .B(n4282), .CO(n4286), .S(
DP_OP_168J30_122_4811_n744) );
XOR2X1TS U5565 ( .A(n4285), .B(n4410), .Y(n4289) );
ADDHXLTS U5566 ( .A(n4287), .B(n4286), .CO(n4288), .S(
DP_OP_168J30_122_4811_n737) );
XOR2X1TS U5567 ( .A(n4291), .B(n4668), .Y(DP_OP_168J30_122_4811_n1220) );
AOI222X1TS U5568 ( .A0(n3811), .A1(n4415), .B0(n4433), .B1(n4356), .C0(n3809), .C1(n4309), .Y(n4292) );
OAI21XLTS U5569 ( .A0(n4395), .A1(n4435), .B0(n4292), .Y(n4293) );
XOR2X1TS U5570 ( .A(n4293), .B(n4437), .Y(DP_OP_168J30_122_4811_n2962) );
AOI222X1TS U5571 ( .A0(n2972), .A1(n4196), .B0(n2971), .B1(Op_MY[4]), .C0(
n2962), .C1(Op_MY[3]), .Y(n4294) );
OAI21XLTS U5572 ( .A0(n4295), .A1(n2970), .B0(n4294), .Y(n4297) );
XOR2X1TS U5573 ( .A(n4297), .B(n4296), .Y(DP_OP_168J30_122_4811_n2815) );
INVX2TS U5574 ( .A(n4298), .Y(DP_OP_168J30_122_4811_n1984) );
OAI21X1TS U5575 ( .A0(n4322), .A1(n4317), .B0(n4299), .Y(n4300) );
XOR2X1TS U5576 ( .A(n4300), .B(n4668), .Y(DP_OP_168J30_122_4811_n1224) );
ADDHXLTS U5577 ( .A(n4302), .B(n4301), .CO(DP_OP_168J30_122_4811_n522), .S(
n3927) );
AOI22X1TS U5578 ( .A0(n2702), .A1(n4303), .B0(n4405), .B1(n4477), .Y(n4304)
);
XOR2X1TS U5579 ( .A(n4305), .B(n4410), .Y(DP_OP_168J30_122_4811_n1209) );
INVX2TS U5580 ( .A(n4306), .Y(DP_OP_168J30_122_4811_n1983) );
XOR2X1TS U5581 ( .A(n4308), .B(n4668), .Y(DP_OP_168J30_122_4811_n1225) );
AOI222X1TS U5582 ( .A0(n3121), .A1(n4415), .B0(n4416), .B1(n4356), .C0(n3112), .C1(n4309), .Y(n4310) );
OAI21XLTS U5583 ( .A0(n4395), .A1(n3118), .B0(n4310), .Y(n4311) );
XOR2X1TS U5584 ( .A(n4311), .B(n4419), .Y(DP_OP_168J30_122_4811_n2902) );
OAI21X1TS U5585 ( .A0(n836), .A1(n4317), .B0(n4316), .Y(n4318) );
XOR2X1TS U5586 ( .A(n4318), .B(n4668), .Y(DP_OP_168J30_122_4811_n1215) );
INVX2TS U5587 ( .A(n4319), .Y(DP_OP_168J30_122_4811_n1986) );
INVX2TS U5588 ( .A(n4320), .Y(DP_OP_168J30_122_4811_n1985) );
AOI222X1TS U5589 ( .A0(n4549), .A1(n4362), .B0(n4363), .B1(n4360), .C0(n4361), .C1(n2690), .Y(n4321) );
XOR2X1TS U5590 ( .A(n4323), .B(n4264), .Y(DP_OP_168J30_122_4811_n1162) );
AOI222X1TS U5591 ( .A0(n4614), .A1(n4332), .B0(n4550), .B1(n4331), .C0(n4549), .C1(n4330), .Y(n4324) );
XOR2X1TS U5592 ( .A(n4326), .B(n4410), .Y(DP_OP_168J30_122_4811_n1191) );
AOI222X1TS U5593 ( .A0(n4327), .A1(n4332), .B0(n4658), .B1(n4331), .C0(n4544), .C1(n4330), .Y(n4328) );
XOR2X1TS U5594 ( .A(n4329), .B(n4410), .Y(DP_OP_168J30_122_4811_n1188) );
AOI222X1TS U5595 ( .A0(n4363), .A1(n4332), .B0(n4361), .B1(n4331), .C0(n4656), .C1(n4330), .Y(n4333) );
XOR2X1TS U5596 ( .A(n4334), .B(n4410), .Y(DP_OP_168J30_122_4811_n1194) );
AOI222X1TS U5597 ( .A0(n4517), .A1(n4439), .B0(n4515), .B1(n4432), .C0(n4513), .C1(Op_MY[8]), .Y(n4335) );
OAI21XLTS U5598 ( .A0(n4418), .A1(n4422), .B0(n4335), .Y(n4336) );
XOR2X1TS U5599 ( .A(n4336), .B(n4423), .Y(DP_OP_168J30_122_4811_n2870) );
INVX2TS U5600 ( .A(n4339), .Y(n4341) );
INVX2TS U5601 ( .A(n4814), .Y(DP_OP_168J30_122_4811_n818) );
AOI222X1TS U5602 ( .A0(n4472), .A1(n4432), .B0(n4444), .B1(n4415), .C0(n4469), .C1(n4356), .Y(n4344) );
OAI21XLTS U5603 ( .A0(n4358), .A1(n3129), .B0(n4344), .Y(n4345) );
XOR2X1TS U5604 ( .A(n4345), .B(n4456), .Y(DP_OP_168J30_122_4811_n2931) );
AOI222X1TS U5605 ( .A0(n3811), .A1(n4432), .B0(n4433), .B1(n4415), .C0(n3809), .C1(n4356), .Y(n4346) );
OAI21X1TS U5606 ( .A0(n4358), .A1(n4435), .B0(n4346), .Y(n4347) );
XOR2X1TS U5607 ( .A(n4347), .B(n4437), .Y(DP_OP_168J30_122_4811_n2961) );
INVX2TS U5608 ( .A(n4348), .Y(n4350) );
INVX2TS U5609 ( .A(n4815), .Y(DP_OP_168J30_122_4811_n817) );
AOI222X1TS U5610 ( .A0(n4393), .A1(n4356), .B0(n4392), .B1(n4309), .C0(n3020), .C1(Op_MY[5]), .Y(n4353) );
OAI21XLTS U5611 ( .A0(n4354), .A1(n3026), .B0(n4353), .Y(n4355) );
XOR2X1TS U5612 ( .A(n4355), .B(n4670), .Y(DP_OP_168J30_122_4811_n2843) );
AOI222X1TS U5613 ( .A0(n3121), .A1(n4432), .B0(n4416), .B1(n4415), .C0(n3112), .C1(n4356), .Y(n4357) );
OAI21XLTS U5614 ( .A0(n4358), .A1(n3118), .B0(n4357), .Y(n4359) );
XOR2X1TS U5615 ( .A(n4359), .B(n4419), .Y(DP_OP_168J30_122_4811_n2901) );
AOI222X1TS U5616 ( .A0(n4363), .A1(n4362), .B0(n4361), .B1(n4261), .C0(n4656), .C1(n2690), .Y(n4364) );
XOR2X1TS U5617 ( .A(n4367), .B(n4264), .Y(DP_OP_168J30_122_4811_n1163) );
INVX2TS U5618 ( .A(n4816), .Y(DP_OP_168J30_122_4811_n816) );
XOR2X1TS U5619 ( .A(n4378), .B(n4377), .Y(n4387) );
XOR2X1TS U5620 ( .A(n4385), .B(n4384), .Y(n4386) );
ADDHXLTS U5621 ( .A(n4387), .B(n4386), .CO(DP_OP_168J30_122_4811_n582), .S(
DP_OP_168J30_122_4811_n583) );
AOI222X1TS U5622 ( .A0(n4517), .A1(n4443), .B0(n4515), .B1(n4439), .C0(n4513), .C1(n4432), .Y(n4388) );
OAI21XLTS U5623 ( .A0(n4436), .A1(n4422), .B0(n4388), .Y(n4389) );
XOR2X1TS U5624 ( .A(n4389), .B(n4423), .Y(DP_OP_168J30_122_4811_n2869) );
AOI222X1TS U5625 ( .A0(n4472), .A1(n4439), .B0(n4444), .B1(n4432), .C0(n4469), .C1(n4415), .Y(n4390) );
OAI21XLTS U5626 ( .A0(n4418), .A1(n3129), .B0(n4390), .Y(n4391) );
XOR2X1TS U5627 ( .A(n4391), .B(n4456), .Y(DP_OP_168J30_122_4811_n2930) );
AOI222X1TS U5628 ( .A0(n4393), .A1(n4415), .B0(n4392), .B1(n4356), .C0(n3020), .C1(n4309), .Y(n4394) );
OAI21XLTS U5629 ( .A0(n4395), .A1(n3026), .B0(n4394), .Y(n4396) );
XOR2X1TS U5630 ( .A(n4396), .B(n4670), .Y(DP_OP_168J30_122_4811_n2842) );
XOR2X1TS U5631 ( .A(n4398), .B(n2489), .Y(DP_OP_168J30_122_4811_n1086) );
AOI222X1TS U5632 ( .A0(n3811), .A1(n4439), .B0(n4433), .B1(n4432), .C0(n3809), .C1(n4415), .Y(n4399) );
OAI21XLTS U5633 ( .A0(n4418), .A1(n4435), .B0(n4399), .Y(n4400) );
XOR2X1TS U5634 ( .A(n4400), .B(n4437), .Y(DP_OP_168J30_122_4811_n2960) );
XOR2X1TS U5635 ( .A(n4403), .B(n4410), .Y(n4412) );
XOR2X1TS U5636 ( .A(n4411), .B(n4410), .Y(n4414) );
ADDHXLTS U5637 ( .A(n4412), .B(n4669), .CO(n4413), .S(
DP_OP_168J30_122_4811_n723) );
ADDHXLTS U5638 ( .A(n4414), .B(n4413), .CO(DP_OP_168J30_122_4811_n714), .S(
DP_OP_168J30_122_4811_n715) );
AOI222X1TS U5639 ( .A0(n3121), .A1(n4439), .B0(n4416), .B1(n4432), .C0(n3112), .C1(n4415), .Y(n4417) );
OAI21XLTS U5640 ( .A0(n4418), .A1(n3118), .B0(n4417), .Y(n4420) );
XOR2X1TS U5641 ( .A(n4420), .B(n4419), .Y(DP_OP_168J30_122_4811_n2900) );
AOI222X1TS U5642 ( .A0(n4517), .A1(n4451), .B0(n4515), .B1(n4443), .C0(n4513), .C1(n4439), .Y(n4421) );
OAI21XLTS U5643 ( .A0(n4441), .A1(n4422), .B0(n4421), .Y(n4424) );
XOR2X1TS U5644 ( .A(n4424), .B(n4423), .Y(DP_OP_168J30_122_4811_n2868) );
INVX2TS U5645 ( .A(n4425), .Y(n4427) );
NAND2X1TS U5646 ( .A(n4427), .B(n4426), .Y(n4429) );
INVX2TS U5647 ( .A(n4817), .Y(DP_OP_168J30_122_4811_n815) );
AOI222X1TS U5648 ( .A0(n4472), .A1(n4443), .B0(n4444), .B1(n4439), .C0(n4469), .C1(n4432), .Y(n4430) );
OAI21XLTS U5649 ( .A0(n4436), .A1(n3129), .B0(n4430), .Y(n4431) );
XOR2X1TS U5650 ( .A(n4431), .B(n4456), .Y(DP_OP_168J30_122_4811_n2929) );
AOI222X1TS U5651 ( .A0(n3811), .A1(n4443), .B0(n4433), .B1(n4439), .C0(n3809), .C1(n4432), .Y(n4434) );
OAI21XLTS U5652 ( .A0(n4436), .A1(n4435), .B0(n4434), .Y(n4438) );
XOR2X1TS U5653 ( .A(n4438), .B(n4437), .Y(DP_OP_168J30_122_4811_n2959) );
AOI222X1TS U5654 ( .A0(n4472), .A1(n4451), .B0(n4444), .B1(n4443), .C0(n4469), .C1(n4439), .Y(n4440) );
XOR2X1TS U5655 ( .A(n4442), .B(n4456), .Y(DP_OP_168J30_122_4811_n2928) );
AOI222X1TS U5656 ( .A0(n4472), .A1(n4452), .B0(n4444), .B1(n4451), .C0(n4469), .C1(n4443), .Y(n4445) );
OAI21X1TS U5657 ( .A0(n4446), .A1(n3129), .B0(n4445), .Y(n4447) );
XOR2X1TS U5658 ( .A(n4447), .B(n4456), .Y(DP_OP_168J30_122_4811_n2927) );
AOI222X1TS U5659 ( .A0(n4472), .A1(n4458), .B0(n4471), .B1(n3061), .C0(n4469), .C1(n4470), .Y(n4448) );
OAI21X1TS U5660 ( .A0(n4449), .A1(n4474), .B0(n4448), .Y(n4450) );
XOR2X1TS U5661 ( .A(n4450), .B(n4456), .Y(DP_OP_168J30_122_4811_n2920) );
AOI222X1TS U5662 ( .A0(n4472), .A1(n4453), .B0(n4471), .B1(n4452), .C0(n3130), .C1(n4451), .Y(n4454) );
OAI21X1TS U5663 ( .A0(n4455), .A1(n4474), .B0(n4454), .Y(n4457) );
XOR2X1TS U5664 ( .A(n4457), .B(n4456), .Y(DP_OP_168J30_122_4811_n2926) );
AOI222X1TS U5665 ( .A0(n4472), .A1(n4459), .B0(n4471), .B1(n4458), .C0(n4469), .C1(n3061), .Y(n4460) );
OAI21X1TS U5666 ( .A0(n4461), .A1(n4474), .B0(n4460), .Y(n4462) );
XOR2X1TS U5667 ( .A(n4462), .B(n4456), .Y(DP_OP_168J30_122_4811_n2919) );
AOI222X1TS U5668 ( .A0(n4472), .A1(n4516), .B0(n4471), .B1(n4514), .C0(n4469), .C1(n4463), .Y(n4464) );
XOR2X1TS U5669 ( .A(n4465), .B(n4456), .Y(DP_OP_168J30_122_4811_n2923) );
AOI222X1TS U5670 ( .A0(n4472), .A1(n4470), .B0(n4471), .B1(n4516), .C0(n4469), .C1(n4514), .Y(n4466) );
OAI21X1TS U5671 ( .A0(n4467), .A1(n4474), .B0(n4466), .Y(n4468) );
XOR2X1TS U5672 ( .A(n4468), .B(n4456), .Y(DP_OP_168J30_122_4811_n2922) );
AOI222X1TS U5673 ( .A0(n4472), .A1(n3061), .B0(n4471), .B1(n4470), .C0(n4469), .C1(n4516), .Y(n4473) );
OAI21X1TS U5674 ( .A0(n4475), .A1(n4474), .B0(n4473), .Y(n4476) );
XOR2X1TS U5675 ( .A(n4476), .B(n4456), .Y(DP_OP_168J30_122_4811_n2921) );
NAND2X1TS U5676 ( .A(n4501), .B(n4477), .Y(n4478) );
XOR2X1TS U5677 ( .A(n4479), .B(n4503), .Y(DP_OP_168J30_122_4811_n993) );
INVX2TS U5678 ( .A(n4480), .Y(n4482) );
INVX2TS U5679 ( .A(n4873), .Y(DP_OP_168J30_122_4811_n812) );
AOI22X1TS U5680 ( .A0(n4501), .A1(n4493), .B0(n4007), .B1(n4512), .Y(n4485)
);
XOR2X1TS U5681 ( .A(n4486), .B(n4503), .Y(DP_OP_168J30_122_4811_n992) );
AOI222X1TS U5682 ( .A0(n4501), .A1(n4562), .B0(n2238), .B1(n4510), .C0(n4500), .C1(n4511), .Y(n4487) );
XOR2X1TS U5683 ( .A(n4489), .B(n4503), .Y(DP_OP_168J30_122_4811_n987) );
INVX2TS U5684 ( .A(n4874), .Y(DP_OP_168J30_122_4811_n811) );
AOI222X1TS U5685 ( .A0(n4501), .A1(n4509), .B0(n4007), .B1(n4493), .C0(n4500), .C1(n4512), .Y(n4494) );
XOR2X1TS U5686 ( .A(n4496), .B(n4503), .Y(DP_OP_168J30_122_4811_n991) );
AOI222X1TS U5687 ( .A0(n4501), .A1(n4510), .B0(n2238), .B1(n4511), .C0(n4500), .C1(n4508), .Y(n4497) );
XOR2X1TS U5688 ( .A(n4499), .B(n4503), .Y(DP_OP_168J30_122_4811_n988) );
AOI222X1TS U5689 ( .A0(n4501), .A1(n4511), .B0(n4007), .B1(n4508), .C0(n4500), .C1(n4509), .Y(n4502) );
XOR2X1TS U5690 ( .A(n4504), .B(n4503), .Y(DP_OP_168J30_122_4811_n989) );
INVX2TS U5691 ( .A(n4876), .Y(DP_OP_168J30_122_4811_n809) );
CLKAND2X2TS U5692 ( .A(n4654), .B(n4512), .Y(DP_OP_168J30_122_4811_n850) );
AOI222X1TS U5693 ( .A0(n4517), .A1(n4516), .B0(n4515), .B1(n4514), .C0(n4513), .C1(n4463), .Y(n4518) );
OAI21X1TS U5694 ( .A0(n4519), .A1(n4422), .B0(n4518), .Y(n4520) );
XOR2X1TS U5695 ( .A(n4520), .B(n4423), .Y(DP_OP_168J30_122_4811_n2863) );
INVX2TS U5696 ( .A(n4521), .Y(n4523) );
INVX2TS U5697 ( .A(n4879), .Y(DP_OP_168J30_122_4811_n806) );
NAND2X1TS U5698 ( .A(n897), .B(n4526), .Y(n4528) );
INVX2TS U5699 ( .A(n4880), .Y(DP_OP_168J30_122_4811_n805) );
INVX2TS U5700 ( .A(n4529), .Y(n4531) );
INVX2TS U5701 ( .A(n4883), .Y(DP_OP_168J30_122_4811_n802) );
INVX2TS U5702 ( .A(n4534), .Y(n4536) );
NAND2X1TS U5703 ( .A(n4536), .B(n4535), .Y(n4538) );
INVX2TS U5704 ( .A(n4885), .Y(DP_OP_168J30_122_4811_n800) );
INVX2TS U5705 ( .A(n4539), .Y(n4541) );
INVX2TS U5706 ( .A(n4886), .Y(DP_OP_168J30_122_4811_n799) );
XOR2X1TS U5707 ( .A(n4547), .B(DP_OP_168J30_122_4811_n56), .Y(n4556) );
INVX2TS U5708 ( .A(n2661), .Y(n4555) );
ADDHXLTS U5709 ( .A(n4558), .B(n4557), .CO(DP_OP_168J30_122_4811_n4114), .S(
n3882) );
INVX2TS U5710 ( .A(n4882), .Y(DP_OP_168J30_122_4811_n803) );
NAND2X1TS U5711 ( .A(n869), .B(n4563), .Y(n4565) );
INVX2TS U5712 ( .A(n4889), .Y(DP_OP_168J30_122_4811_n796) );
INVX2TS U5713 ( .A(n4566), .Y(n4568) );
INVX2TS U5714 ( .A(n4888), .Y(DP_OP_168J30_122_4811_n797) );
INVX2TS U5715 ( .A(n4573), .Y(DP_OP_168J30_122_4811_n793) );
INVX2TS U5716 ( .A(n4574), .Y(DP_OP_168J30_122_4811_n792) );
INVX2TS U5717 ( .A(n4892), .Y(DP_OP_168J30_122_4811_n794) );
INVX2TS U5718 ( .A(n4575), .Y(DP_OP_168J30_122_4811_n782) );
OAI21X1TS U5719 ( .A0(n4633), .A1(n3243), .B0(n4581), .Y(n4582) );
XOR2X1TS U5720 ( .A(n4582), .B(n4649), .Y(n4599) );
AOI21X1TS U5721 ( .A0(n4585), .A1(n4584), .B0(n4583), .Y(n4586) );
CMPR32X2TS U5722 ( .A(n4590), .B(n4589), .C(n4588), .CO(n4597), .S(
DP_OP_168J30_122_4811_n4061) );
OAI21X1TS U5723 ( .A0(n4644), .A1(n3243), .B0(n4591), .Y(n4592) );
XOR2X1TS U5724 ( .A(n4592), .B(n4649), .Y(n4602) );
AOI21X1TS U5725 ( .A0(n4641), .A1(n4594), .B0(n4593), .Y(n4595) );
CMPR32X2TS U5726 ( .A(n4599), .B(n4598), .C(n4597), .CO(n4600), .S(
DP_OP_168J30_122_4811_n4050) );
CMPR32X2TS U5727 ( .A(n4602), .B(n4601), .C(n4600), .CO(
DP_OP_168J30_122_4811_n4038), .S(DP_OP_168J30_122_4811_n4039) );
INVX2TS U5728 ( .A(n4613), .Y(n4620) );
AOI21X1TS U5729 ( .A0(n4641), .A1(Op_MY[29]), .B0(n4622), .Y(n4623) );
XOR2X1TS U5730 ( .A(n4627), .B(n4649), .Y(n4628) );
CMPR32X2TS U5731 ( .A(n4629), .B(n4652), .C(n4628), .CO(
DP_OP_168J30_122_4811_n4027), .S(DP_OP_168J30_122_4811_n4028) );
AOI21X1TS U5732 ( .A0(n4641), .A1(Op_MY[30]), .B0(n4631), .Y(n4632) );
OAI21X1TS U5733 ( .A0(n4633), .A1(n4643), .B0(n4632), .Y(n4638) );
OAI21X1TS U5734 ( .A0(n4635), .A1(n3243), .B0(n4634), .Y(n4636) );
XOR2X1TS U5735 ( .A(n4636), .B(n4649), .Y(n4637) );
CMPR32X2TS U5736 ( .A(n4638), .B(n4652), .C(n4637), .CO(
DP_OP_168J30_122_4811_n4016), .S(DP_OP_168J30_122_4811_n4017) );
AOI21X1TS U5737 ( .A0(n4641), .A1(Op_MY[31]), .B0(n4640), .Y(n4642) );
OAI21X1TS U5738 ( .A0(n4648), .A1(n3243), .B0(n4647), .Y(n4650) );
XOR2X1TS U5739 ( .A(n4650), .B(n4649), .Y(n4651) );
CMPR32X2TS U5740 ( .A(n4653), .B(n4652), .C(n4651), .CO(
DP_OP_168J30_122_4811_n4005), .S(DP_OP_168J30_122_4811_n4006) );
INVX2TS U5741 ( .A(DP_OP_168J30_122_4811_n66), .Y(n4665) );
INVX2TS U5742 ( .A(n2700), .Y(DP_OP_168J30_122_4811_n1180) );
INVX2TS U5743 ( .A(n4668), .Y(DP_OP_168J30_122_4811_n1211) );
INVX2TS U5744 ( .A(n4669), .Y(DP_OP_168J30_122_4811_n1118) );
BUFX4TS U5745 ( .A(n286), .Y(n5548) );
BUFX4TS U5746 ( .A(n286), .Y(n5547) );
BUFX4TS U5747 ( .A(n286), .Y(n5549) );
BUFX4TS U5748 ( .A(n286), .Y(n5545) );
BUFX4TS U5749 ( .A(n286), .Y(n5546) );
BUFX6TS U5750 ( .A(n5551), .Y(n5538) );
BUFX4TS U5751 ( .A(n5551), .Y(n5529) );
BUFX4TS U5752 ( .A(n286), .Y(n5544) );
NAND3X1TS U5753 ( .A(n4672), .B(FS_Module_state_reg[0]), .C(
FS_Module_state_reg[2]), .Y(n5319) );
NAND2BXLTS U5754 ( .AN(n5319), .B(P_Sgf[105]), .Y(n4738) );
NAND3X1TS U5755 ( .A(FS_Module_state_reg[0]), .B(n5527), .C(n5474), .Y(n5320) );
INVX2TS U5756 ( .A(n5364), .Y(n5362) );
NAND2X1TS U5757 ( .A(n5460), .B(n5362), .Y(n4673) );
AO21XLTS U5758 ( .A0(n4738), .A1(FSM_selector_B[0]), .B0(n4673), .Y(n419) );
CLKXOR2X2TS U5759 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n4740) );
NOR4X1TS U5760 ( .A(P_Sgf[0]), .B(P_Sgf[1]), .C(P_Sgf[2]), .D(P_Sgf[3]), .Y(
n4689) );
NOR4X1TS U5761 ( .A(P_Sgf[4]), .B(P_Sgf[5]), .C(P_Sgf[6]), .D(P_Sgf[7]), .Y(
n4688) );
NOR4X1TS U5762 ( .A(P_Sgf[48]), .B(P_Sgf[49]), .C(P_Sgf[50]), .D(P_Sgf[51]),
.Y(n4687) );
OR4X2TS U5763 ( .A(P_Sgf[44]), .B(P_Sgf[45]), .C(P_Sgf[46]), .D(P_Sgf[47]),
.Y(n4685) );
OR4X2TS U5764 ( .A(P_Sgf[40]), .B(P_Sgf[41]), .C(P_Sgf[42]), .D(P_Sgf[43]),
.Y(n4684) );
NOR4X1TS U5765 ( .A(P_Sgf[8]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n4677) );
NOR4X1TS U5766 ( .A(P_Sgf[12]), .B(P_Sgf[13]), .C(P_Sgf[14]), .D(P_Sgf[15]),
.Y(n4676) );
NOR4X1TS U5767 ( .A(P_Sgf[16]), .B(P_Sgf[17]), .C(P_Sgf[18]), .D(P_Sgf[19]),
.Y(n4675) );
NOR4X1TS U5768 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[22]), .D(P_Sgf[23]),
.Y(n4674) );
NAND4XLTS U5769 ( .A(n4677), .B(n4676), .C(n4675), .D(n4674), .Y(n4683) );
NOR4X1TS U5770 ( .A(P_Sgf[24]), .B(P_Sgf[25]), .C(P_Sgf[26]), .D(P_Sgf[27]),
.Y(n4681) );
NOR4X1TS U5771 ( .A(P_Sgf[28]), .B(P_Sgf[29]), .C(P_Sgf[30]), .D(P_Sgf[31]),
.Y(n4680) );
NOR4X1TS U5772 ( .A(P_Sgf[32]), .B(P_Sgf[33]), .C(P_Sgf[34]), .D(P_Sgf[35]),
.Y(n4679) );
NAND4XLTS U5773 ( .A(n4681), .B(n4680), .C(n4679), .D(n4678), .Y(n4682) );
NOR4X1TS U5774 ( .A(n4685), .B(n4684), .C(n4683), .D(n4682), .Y(n4686) );
NAND4XLTS U5775 ( .A(n4689), .B(n4688), .C(n4687), .D(n4686), .Y(n4691) );
MXI2X1TS U5776 ( .A(n4740), .B(round_mode[1]), .S0(round_mode[0]), .Y(n4690)
);
OAI211X1TS U5777 ( .A0(n4740), .A1(round_mode[1]), .B0(n4691), .C0(n4690),
.Y(n4790) );
OAI31X1TS U5778 ( .A0(n5527), .A1(n4742), .A2(n4790), .B0(n5476), .Y(n709)
);
NOR2BX1TS U5779 ( .AN(n4743), .B(n5527), .Y(n4692) );
BUFX4TS U5780 ( .A(n4692), .Y(n5526) );
CLKINVX6TS U5781 ( .A(n5374), .Y(n5454) );
NAND2X1TS U5782 ( .A(n5373), .B(n5477), .Y(n5376) );
NAND2X1TS U5783 ( .A(Sgf_normalized_result[6]), .B(n5376), .Y(n5378) );
NOR2X2TS U5784 ( .A(n5478), .B(n5378), .Y(n5380) );
NAND2X1TS U5785 ( .A(Sgf_normalized_result[8]), .B(n5380), .Y(n5382) );
NOR2X2TS U5786 ( .A(n5479), .B(n5382), .Y(n5384) );
NAND2X1TS U5787 ( .A(Sgf_normalized_result[10]), .B(n5384), .Y(n5386) );
NOR2X2TS U5788 ( .A(n5480), .B(n5386), .Y(n5388) );
NAND2X1TS U5789 ( .A(Sgf_normalized_result[12]), .B(n5388), .Y(n5390) );
NOR2X2TS U5790 ( .A(n5481), .B(n5390), .Y(n5392) );
NAND2X1TS U5791 ( .A(Sgf_normalized_result[14]), .B(n5392), .Y(n5394) );
NOR2X2TS U5792 ( .A(n5482), .B(n5394), .Y(n5396) );
NOR2X2TS U5793 ( .A(n5483), .B(n5398), .Y(n5400) );
NOR2X2TS U5794 ( .A(n5484), .B(n5402), .Y(n5404) );
NOR2X2TS U5795 ( .A(n5485), .B(n5406), .Y(n5408) );
NOR2X2TS U5796 ( .A(n5486), .B(n5410), .Y(n5413) );
NOR2X2TS U5797 ( .A(n5487), .B(n5412), .Y(n5416) );
AOI21X1TS U5798 ( .A0(n5487), .A1(n5412), .B0(n5416), .Y(n4694) );
AO22XLTS U5799 ( .A0(n5454), .A1(n4694), .B0(n5374), .B1(n806), .Y(n554) );
NOR2X2TS U5800 ( .A(n5488), .B(n5415), .Y(n5419) );
AOI21X1TS U5801 ( .A0(n5488), .A1(n5415), .B0(n5419), .Y(n4695) );
AO22XLTS U5802 ( .A0(n5454), .A1(n4695), .B0(n5374), .B1(n807), .Y(n552) );
NOR2X2TS U5803 ( .A(n5489), .B(n5418), .Y(n5422) );
AOI21X1TS U5804 ( .A0(n5489), .A1(n5418), .B0(n5422), .Y(n4696) );
AO22XLTS U5805 ( .A0(n5454), .A1(n4696), .B0(n5374), .B1(n808), .Y(n550) );
NOR2X2TS U5806 ( .A(n5490), .B(n5421), .Y(n5425) );
AOI21X1TS U5807 ( .A0(n5490), .A1(n5421), .B0(n5425), .Y(n4697) );
AO22XLTS U5808 ( .A0(n5454), .A1(n4697), .B0(n5374), .B1(n809), .Y(n548) );
NOR2X2TS U5809 ( .A(n5491), .B(n5424), .Y(n5428) );
AOI21X1TS U5810 ( .A0(n5491), .A1(n5424), .B0(n5428), .Y(n4698) );
NOR2X2TS U5811 ( .A(n5492), .B(n5427), .Y(n5431) );
AOI21X1TS U5812 ( .A0(n5492), .A1(n5427), .B0(n5431), .Y(n4699) );
AO22XLTS U5813 ( .A0(n5454), .A1(n4699), .B0(n5374), .B1(Add_result[35]),
.Y(n544) );
NOR2X2TS U5814 ( .A(n5493), .B(n5430), .Y(n5434) );
AOI21X1TS U5815 ( .A0(n5493), .A1(n5430), .B0(n5434), .Y(n4700) );
AO22XLTS U5816 ( .A0(n5454), .A1(n4700), .B0(n5374), .B1(Add_result[37]),
.Y(n542) );
NOR2X2TS U5817 ( .A(n5495), .B(n5433), .Y(n5436) );
AOI21X1TS U5818 ( .A0(n5495), .A1(n5433), .B0(n5436), .Y(n4701) );
AO22XLTS U5819 ( .A0(n5454), .A1(n4701), .B0(n5374), .B1(Add_result[39]),
.Y(n540) );
NOR2X2TS U5820 ( .A(n5496), .B(n5438), .Y(n5441) );
NOR2X2TS U5821 ( .A(n5498), .B(n5440), .Y(n5444) );
AOI21X1TS U5822 ( .A0(n5498), .A1(n5440), .B0(n5444), .Y(n4702) );
NOR2X2TS U5823 ( .A(n5499), .B(n5443), .Y(n5447) );
AOI21X1TS U5824 ( .A0(n5499), .A1(n5443), .B0(n5447), .Y(n4703) );
NAND2X1TS U5825 ( .A(Sgf_normalized_result[46]), .B(n5447), .Y(n5446) );
NOR2X2TS U5826 ( .A(n5500), .B(n5446), .Y(n5450) );
AOI21X1TS U5827 ( .A0(n5500), .A1(n5446), .B0(n5450), .Y(n4704) );
CLKMX2X2TS U5828 ( .A(P_Sgf[97]), .B(n4709), .S0(n5281), .Y(n518) );
CLKMX2X2TS U5829 ( .A(P_Sgf[98]), .B(n4712), .S0(n5281), .Y(n519) );
CLKMX2X2TS U5830 ( .A(P_Sgf[99]), .B(n4717), .S0(n5281), .Y(n521) );
CLKMX2X2TS U5831 ( .A(P_Sgf[100]), .B(n4720), .S0(n5281), .Y(n522) );
INVX2TS U5832 ( .A(n4725), .Y(n4722) );
CLKMX2X2TS U5833 ( .A(P_Sgf[101]), .B(n4724), .S0(n5281), .Y(n523) );
CLKMX2X2TS U5834 ( .A(P_Sgf[102]), .B(n4727), .S0(n5019), .Y(n524) );
INVX2TS U5835 ( .A(n4733), .Y(n4730) );
CLKMX2X2TS U5836 ( .A(P_Sgf[103]), .B(n4732), .S0(n5019), .Y(n525) );
CLKMX2X2TS U5837 ( .A(P_Sgf[105]), .B(n4737), .S0(n5281), .Y(n420) );
CLKINVX6TS U5838 ( .A(n5374), .Y(n5464) );
OAI31X1TS U5839 ( .A0(n5364), .A1(n5464), .A2(n5475), .B0(n4738), .Y(n418)
);
NOR2XLTS U5840 ( .A(n5320), .B(n5473), .Y(n4739) );
BUFX3TS U5841 ( .A(n4739), .Y(n5472) );
CLKINVX3TS U5842 ( .A(n5472), .Y(n5465) );
NOR2XLTS U5843 ( .A(n4740), .B(underflow_flag), .Y(n4741) );
OAI32X1TS U5844 ( .A0(n5465), .A1(n4741), .A2(overflow_flag), .B0(n5472),
.B1(n5525), .Y(n287) );
INVX2TS U5845 ( .A(n4742), .Y(n4745) );
AOI32X4TS U5846 ( .A0(FSM_add_overflow_flag), .A1(n5527), .A2(n4745), .B0(
n4743), .B1(n5527), .Y(n5369) );
BUFX4TS U5847 ( .A(n4753), .Y(n5152) );
AOI32X1TS U5848 ( .A0(FS_Module_state_reg[2]), .A1(n5527), .A2(n5473), .B0(
n4745), .B1(n5527), .Y(n4746) );
INVX2TS U5849 ( .A(n4746), .Y(n5368) );
INVX4TS U5850 ( .A(n5368), .Y(n5309) );
AOI22X1TS U5851 ( .A0(Add_result[1]), .A1(n4753), .B0(
Sgf_normalized_result[0]), .B1(n5309), .Y(n4750) );
NAND2X1TS U5852 ( .A(n5368), .B(n5369), .Y(n4747) );
NOR2X1TS U5853 ( .A(FSM_selector_C), .B(n4747), .Y(n5313) );
INVX2TS U5854 ( .A(n5313), .Y(n5099) );
NOR2X2TS U5855 ( .A(n5476), .B(n4747), .Y(n4748) );
AOI22X1TS U5856 ( .A0(n5305), .A1(P_Sgf[52]), .B0(n5147), .B1(Add_result[0]),
.Y(n4749) );
OAI211XLTS U5857 ( .A0(n4744), .A1(n5513), .B0(n4750), .C0(n4749), .Y(n353)
);
INVX3TS U5858 ( .A(n5368), .Y(n5366) );
AOI22X1TS U5859 ( .A0(Sgf_normalized_result[3]), .A1(n5366), .B0(n4753),
.B1(Add_result[4]), .Y(n4752) );
INVX6TS U5860 ( .A(n5099), .Y(n5297) );
AOI22X1TS U5861 ( .A0(n5297), .A1(P_Sgf[55]), .B0(n5147), .B1(Add_result[3]),
.Y(n4751) );
OAI211XLTS U5862 ( .A0(n4744), .A1(n5510), .B0(n4752), .C0(n4751), .Y(n356)
);
BUFX6TS U5863 ( .A(n5152), .Y(n5302) );
AOI22X1TS U5864 ( .A0(Sgf_normalized_result[4]), .A1(n5366), .B0(n5302),
.B1(Add_result[5]), .Y(n4755) );
AOI22X1TS U5865 ( .A0(n5297), .A1(P_Sgf[56]), .B0(n5147), .B1(Add_result[4]),
.Y(n4754) );
OAI211XLTS U5866 ( .A0(n4744), .A1(n5509), .B0(n4755), .C0(n4754), .Y(n357)
);
AOI22X1TS U5867 ( .A0(Sgf_normalized_result[6]), .A1(n5366), .B0(n5302),
.B1(Add_result[7]), .Y(n4757) );
AOI22X1TS U5868 ( .A0(n5297), .A1(P_Sgf[58]), .B0(n5147), .B1(Add_result[6]),
.Y(n4756) );
OAI211XLTS U5869 ( .A0(n4744), .A1(n5507), .B0(n4757), .C0(n4756), .Y(n359)
);
AOI22X1TS U5870 ( .A0(Add_result[2]), .A1(n4753), .B0(
Sgf_normalized_result[1]), .B1(n5309), .Y(n4759) );
AOI22X1TS U5871 ( .A0(n5297), .A1(P_Sgf[53]), .B0(n5147), .B1(Add_result[1]),
.Y(n4758) );
AOI22X1TS U5872 ( .A0(Sgf_normalized_result[2]), .A1(n5366), .B0(n4753),
.B1(Add_result[3]), .Y(n4761) );
AOI22X1TS U5873 ( .A0(n5297), .A1(P_Sgf[54]), .B0(n5147), .B1(Add_result[2]),
.Y(n4760) );
OAI211XLTS U5874 ( .A0(n4744), .A1(n5511), .B0(n4761), .C0(n4760), .Y(n355)
);
AOI22X1TS U5875 ( .A0(Sgf_normalized_result[5]), .A1(n5366), .B0(n4753),
.B1(Add_result[6]), .Y(n4763) );
AOI22X1TS U5876 ( .A0(n5297), .A1(P_Sgf[57]), .B0(n5147), .B1(Add_result[5]),
.Y(n4762) );
OAI211XLTS U5877 ( .A0(n4744), .A1(n5508), .B0(n4763), .C0(n4762), .Y(n358)
);
AOI22X1TS U5878 ( .A0(Sgf_normalized_result[7]), .A1(n5366), .B0(
Add_result[8]), .B1(n5152), .Y(n4765) );
AOI22X1TS U5879 ( .A0(n5297), .A1(P_Sgf[59]), .B0(n5147), .B1(Add_result[7]),
.Y(n4764) );
OAI211XLTS U5880 ( .A0(n4744), .A1(n5523), .B0(n4765), .C0(n4764), .Y(n360)
);
AOI22X1TS U5881 ( .A0(Sgf_normalized_result[14]), .A1(n5366), .B0(n819),
.B1(n5152), .Y(n4767) );
AOI22X1TS U5882 ( .A0(Add_result[14]), .A1(n5240), .B0(n5297), .B1(P_Sgf[66]), .Y(n4766) );
OAI211XLTS U5883 ( .A0(n4744), .A1(n5516), .B0(n4767), .C0(n4766), .Y(n367)
);
AOI22X1TS U5884 ( .A0(Sgf_normalized_result[8]), .A1(n5366), .B0(n817), .B1(
n5302), .Y(n4769) );
AOI22X1TS U5885 ( .A0(Add_result[8]), .A1(n5240), .B0(n5297), .B1(P_Sgf[60]),
.Y(n4768) );
OAI211XLTS U5886 ( .A0(n4744), .A1(n5522), .B0(n4769), .C0(n4768), .Y(n361)
);
AOI22X1TS U5887 ( .A0(Sgf_normalized_result[10]), .A1(n5366), .B0(
Add_result[11]), .B1(n5302), .Y(n4771) );
AOI22X1TS U5888 ( .A0(Add_result[10]), .A1(n5240), .B0(n5297), .B1(P_Sgf[62]), .Y(n4770) );
OAI211XLTS U5889 ( .A0(n4744), .A1(n5520), .B0(n4771), .C0(n4770), .Y(n363)
);
INVX3TS U5890 ( .A(n5368), .Y(n5168) );
AOI22X1TS U5891 ( .A0(Sgf_normalized_result[16]), .A1(n5168), .B0(
Add_result[17]), .B1(n5152), .Y(n4773) );
AOI22X1TS U5892 ( .A0(Add_result[16]), .A1(n5240), .B0(n5297), .B1(P_Sgf[68]), .Y(n4772) );
OAI211XLTS U5893 ( .A0(n4744), .A1(n5514), .B0(n4773), .C0(n4772), .Y(n369)
);
INVX4TS U5894 ( .A(n5368), .Y(n5251) );
AOI22X1TS U5895 ( .A0(Sgf_normalized_result[12]), .A1(n5251), .B0(n818),
.B1(n5302), .Y(n4775) );
AOI22X1TS U5896 ( .A0(Add_result[12]), .A1(n5240), .B0(n5297), .B1(P_Sgf[64]), .Y(n4774) );
OAI211XLTS U5897 ( .A0(n4744), .A1(n5518), .B0(n4775), .C0(n4774), .Y(n365)
);
AOI22X1TS U5898 ( .A0(Sgf_normalized_result[15]), .A1(n5168), .B0(
Add_result[16]), .B1(n4753), .Y(n4777) );
AOI22X1TS U5899 ( .A0(n819), .A1(n5240), .B0(n5297), .B1(P_Sgf[67]), .Y(
n4776) );
OAI211XLTS U5900 ( .A0(n4744), .A1(n5515), .B0(n4777), .C0(n4776), .Y(n368)
);
AOI22X1TS U5901 ( .A0(Sgf_normalized_result[17]), .A1(n5168), .B0(
Add_result[18]), .B1(n5152), .Y(n4779) );
AOI22X1TS U5902 ( .A0(Add_result[17]), .A1(n5240), .B0(n5297), .B1(P_Sgf[69]), .Y(n4778) );
OAI211XLTS U5903 ( .A0(n4744), .A1(n5504), .B0(n4779), .C0(n4778), .Y(n370)
);
AOI22X1TS U5904 ( .A0(Sgf_normalized_result[9]), .A1(n5366), .B0(
Add_result[10]), .B1(n4753), .Y(n4781) );
AOI22X1TS U5905 ( .A0(n817), .A1(n5240), .B0(n5297), .B1(P_Sgf[61]), .Y(
n4780) );
OAI211XLTS U5906 ( .A0(n4744), .A1(n5521), .B0(n4781), .C0(n4780), .Y(n362)
);
AOI22X1TS U5907 ( .A0(Sgf_normalized_result[11]), .A1(n5366), .B0(
Add_result[12]), .B1(n4753), .Y(n4783) );
AOI22X1TS U5908 ( .A0(Add_result[11]), .A1(n5240), .B0(n5297), .B1(P_Sgf[63]), .Y(n4782) );
OAI211XLTS U5909 ( .A0(n4744), .A1(n5519), .B0(n4783), .C0(n4782), .Y(n364)
);
AOI22X1TS U5910 ( .A0(Sgf_normalized_result[13]), .A1(n5366), .B0(
Add_result[14]), .B1(n4753), .Y(n4785) );
AOI22X1TS U5911 ( .A0(n818), .A1(n5240), .B0(n5297), .B1(P_Sgf[65]), .Y(
n4784) );
OAI211XLTS U5912 ( .A0(n4744), .A1(n5517), .B0(n4785), .C0(n4784), .Y(n366)
);
AOI22X1TS U5913 ( .A0(FSM_selector_C), .A1(Add_result[52]), .B0(P_Sgf[104]),
.B1(n5476), .Y(n5367) );
AOI22X1TS U5914 ( .A0(Sgf_normalized_result[51]), .A1(n5309), .B0(n816),
.B1(n5147), .Y(n4787) );
NAND2X1TS U5915 ( .A(n5297), .B(P_Sgf[103]), .Y(n4786) );
NOR2X1TS U5916 ( .A(n5474), .B(n5473), .Y(n4792) );
NAND3XLTS U5917 ( .A(n4792), .B(n5494), .C(n5550), .Y(n4788) );
INVX2TS U5918 ( .A(n4788), .Y(ready) );
INVX2TS U5919 ( .A(n5526), .Y(n5315) );
OAI22X2TS U5920 ( .A0(beg_FSM), .A1(n5551), .B0(ack_FSM), .B1(n4788), .Y(
n5318) );
OAI21XLTS U5921 ( .A0(n5474), .A1(n5318), .B0(FS_Module_state_reg[3]), .Y(
n4789) );
AOI32X1TS U5922 ( .A0(FS_Module_state_reg[3]), .A1(n5317), .A2(n4790), .B0(
n5527), .B1(n5317), .Y(n4791) );
OAI31X1TS U5923 ( .A0(n5527), .A1(n4792), .A2(n5494), .B0(n4791), .Y(n712)
);
NOR3BX1TS U5924 ( .AN(Op_MY[62]), .B(FSM_selector_B[0]), .C(
FSM_selector_B[1]), .Y(n4793) );
XOR2X1TS U5925 ( .A(n5526), .B(n4793), .Y(DP_OP_36J30_123_1029_n18) );
OAI2BB1X1TS U5926 ( .A0N(Op_MY[61]), .A1N(n5475), .B0(n4803), .Y(n4794) );
XOR2X1TS U5927 ( .A(n5526), .B(n4794), .Y(DP_OP_36J30_123_1029_n19) );
OAI2BB1X1TS U5928 ( .A0N(Op_MY[60]), .A1N(n5475), .B0(n4803), .Y(n4795) );
XOR2X1TS U5929 ( .A(n5526), .B(n4795), .Y(DP_OP_36J30_123_1029_n20) );
OAI2BB1X1TS U5930 ( .A0N(n814), .A1N(n5475), .B0(n4803), .Y(n4796) );
XOR2X1TS U5931 ( .A(n5526), .B(n4796), .Y(DP_OP_36J30_123_1029_n21) );
OAI2BB1X1TS U5932 ( .A0N(n815), .A1N(n5475), .B0(n4803), .Y(n4797) );
XOR2X1TS U5933 ( .A(n5526), .B(n4797), .Y(DP_OP_36J30_123_1029_n22) );
OAI2BB1X1TS U5934 ( .A0N(n812), .A1N(n5475), .B0(n4803), .Y(n4798) );
XOR2X1TS U5935 ( .A(n5526), .B(n4798), .Y(DP_OP_36J30_123_1029_n23) );
OAI2BB1X1TS U5936 ( .A0N(Op_MY[56]), .A1N(n5475), .B0(n4803), .Y(n4799) );
XOR2X1TS U5937 ( .A(n5526), .B(n4799), .Y(DP_OP_36J30_123_1029_n24) );
OAI2BB1X1TS U5938 ( .A0N(Op_MY[55]), .A1N(n5475), .B0(n4803), .Y(n4800) );
XOR2X1TS U5939 ( .A(n5526), .B(n4800), .Y(DP_OP_36J30_123_1029_n25) );
OAI2BB1X1TS U5940 ( .A0N(Op_MY[54]), .A1N(n5475), .B0(n4803), .Y(n4801) );
XOR2X1TS U5941 ( .A(n5526), .B(n4801), .Y(DP_OP_36J30_123_1029_n26) );
OAI2BB1X1TS U5942 ( .A0N(Op_MY[53]), .A1N(n5475), .B0(n4803), .Y(n4802) );
XOR2X1TS U5943 ( .A(n5526), .B(n4802), .Y(DP_OP_36J30_123_1029_n27) );
NOR2XLTS U5944 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n4804) );
OAI21XLTS U5945 ( .A0(FSM_selector_B[0]), .A1(n4804), .B0(n4803), .Y(n4805)
);
XOR2X1TS U5946 ( .A(n5526), .B(n4805), .Y(DP_OP_36J30_123_1029_n28) );
MX2X1TS U5947 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n4808), .Y(n672) );
MX2X1TS U5948 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n4808), .Y(n671) );
MX2X1TS U5949 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n4808), .Y(n670) );
MX2X1TS U5950 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n4808), .Y(n669) );
MX2X1TS U5951 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n4808), .Y(n668) );
MX2X1TS U5952 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n4808), .Y(n667) );
MX2X1TS U5953 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n4808), .Y(n666) );
MX2X1TS U5954 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n4808), .Y(n665) );
MX2X1TS U5955 ( .A(Data_MX[18]), .B(Op_MX[18]), .S0(n4808), .Y(n664) );
MX2X1TS U5956 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n4808), .Y(n663) );
MX2X1TS U5957 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n4808), .Y(n662) );
MX2X1TS U5958 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n4808), .Y(n661) );
MX2X1TS U5959 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n4808), .Y(n660) );
INVX6TS U5960 ( .A(n4947), .Y(n4809) );
MX2X1TS U5961 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n4809), .Y(n659) );
MX2X1TS U5962 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n4809), .Y(n658) );
MX2X1TS U5963 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n4809), .Y(n657) );
MX2X1TS U5964 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n4809), .Y(n656) );
MX2X1TS U5965 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n4809), .Y(n655) );
MX2X1TS U5966 ( .A(Data_MX[8]), .B(Op_MX[8]), .S0(n4809), .Y(n654) );
MX2X1TS U5967 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n4809), .Y(n653) );
MX2X1TS U5968 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n4809), .Y(n652) );
MX2X1TS U5969 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n4809), .Y(n651) );
MX2X1TS U5970 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n4809), .Y(n650) );
MX2X1TS U5971 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n4809), .Y(n649) );
MX2X1TS U5972 ( .A(Data_MX[2]), .B(Op_MX[2]), .S0(n4809), .Y(n648) );
MX2X1TS U5973 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n4809), .Y(n647) );
MX2X1TS U5974 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n4807), .Y(n646) );
MX2X1TS U5975 ( .A(Data_MX[51]), .B(Op_MX[51]), .S0(n4807), .Y(n697) );
MX2X1TS U5976 ( .A(Data_MX[50]), .B(Op_MX[50]), .S0(n4807), .Y(n696) );
MX2X1TS U5977 ( .A(Data_MX[49]), .B(Op_MX[49]), .S0(n4807), .Y(n695) );
MX2X1TS U5978 ( .A(Data_MX[48]), .B(Op_MX[48]), .S0(n4807), .Y(n694) );
MX2X1TS U5979 ( .A(Data_MX[47]), .B(Op_MX[47]), .S0(n4807), .Y(n693) );
MX2X1TS U5980 ( .A(Data_MX[46]), .B(Op_MX[46]), .S0(n4807), .Y(n692) );
MX2X1TS U5981 ( .A(Data_MX[45]), .B(Op_MX[45]), .S0(n4807), .Y(n691) );
MX2X1TS U5982 ( .A(Data_MX[44]), .B(Op_MX[44]), .S0(n4807), .Y(n690) );
MX2X1TS U5983 ( .A(Data_MX[43]), .B(Op_MX[43]), .S0(n4807), .Y(n689) );
MX2X1TS U5984 ( .A(Data_MX[42]), .B(Op_MX[42]), .S0(n4807), .Y(n688) );
MX2X1TS U5985 ( .A(Data_MX[41]), .B(Op_MX[41]), .S0(n4807), .Y(n687) );
MX2X1TS U5986 ( .A(Data_MX[40]), .B(Op_MX[40]), .S0(n4807), .Y(n686) );
MX2X1TS U5987 ( .A(Data_MX[39]), .B(Op_MX[39]), .S0(n4806), .Y(n685) );
MX2X1TS U5988 ( .A(Data_MX[38]), .B(Op_MX[38]), .S0(n4806), .Y(n684) );
MX2X1TS U5989 ( .A(Data_MX[37]), .B(Op_MX[37]), .S0(n4806), .Y(n683) );
MX2X1TS U5990 ( .A(Data_MX[36]), .B(Op_MX[36]), .S0(n4806), .Y(n682) );
MX2X1TS U5991 ( .A(Data_MX[35]), .B(Op_MX[35]), .S0(n4806), .Y(n681) );
MX2X1TS U5992 ( .A(Data_MX[34]), .B(Op_MX[34]), .S0(n4806), .Y(n680) );
MX2X1TS U5993 ( .A(Data_MX[33]), .B(Op_MX[33]), .S0(n4806), .Y(n679) );
MX2X1TS U5994 ( .A(Data_MX[32]), .B(Op_MX[32]), .S0(n4806), .Y(n678) );
MX2X1TS U5995 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n4806), .Y(n677) );
MX2X1TS U5996 ( .A(Data_MX[29]), .B(Op_MX[29]), .S0(n4806), .Y(n675) );
MX2X1TS U5997 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n4806), .Y(n673) );
MX2X1TS U5998 ( .A(Data_MY[26]), .B(Op_MY[26]), .S0(n4808), .Y(n608) );
MX2X1TS U5999 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n4809), .Y(n607) );
MX2X1TS U6000 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n4810), .Y(n606) );
MX2X1TS U6001 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n4806), .Y(n605) );
MX2X1TS U6002 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n4807), .Y(n604) );
MX2X1TS U6003 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n4808), .Y(n603) );
MX2X1TS U6004 ( .A(Data_MY[20]), .B(Op_MY[20]), .S0(n4809), .Y(n602) );
MX2X1TS U6005 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n4810), .Y(n601) );
MX2X1TS U6006 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n4806), .Y(n600) );
MX2X1TS U6007 ( .A(Data_MY[17]), .B(Op_MY[17]), .S0(n4807), .Y(n599) );
MX2X1TS U6008 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n4808), .Y(n598) );
MX2X1TS U6009 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n4809), .Y(n597) );
MX2X1TS U6010 ( .A(Data_MY[14]), .B(Op_MY[14]), .S0(n4810), .Y(n596) );
MX2X1TS U6011 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n4810), .Y(n595) );
MX2X1TS U6012 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n4810), .Y(n594) );
MX2X1TS U6013 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n4810), .Y(n593) );
MX2X1TS U6014 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n4810), .Y(n592) );
MX2X1TS U6015 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n4810), .Y(n591) );
MX2X1TS U6016 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n4810), .Y(n590) );
MX2X1TS U6017 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n4810), .Y(n589) );
MX2X1TS U6018 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n4810), .Y(n588) );
MX2X1TS U6019 ( .A(Data_MY[5]), .B(Op_MY[5]), .S0(n4810), .Y(n587) );
MX2X1TS U6020 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n4810), .Y(n586) );
MX2X1TS U6021 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n4810), .Y(n585) );
MX2X1TS U6022 ( .A(Data_MY[2]), .B(Op_MY[2]), .S0(n4810), .Y(n584) );
MX2X1TS U6023 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n4810), .Y(n583) );
MX2X1TS U6024 ( .A(Data_MY[0]), .B(Op_MY[0]), .S0(n4809), .Y(n582) );
MX2X1TS U6025 ( .A(Data_MY[51]), .B(Op_MY[51]), .S0(n4809), .Y(n633) );
MX2X1TS U6026 ( .A(Data_MY[50]), .B(Op_MY[50]), .S0(n4809), .Y(n632) );
MX2X1TS U6027 ( .A(Data_MY[49]), .B(Op_MY[49]), .S0(n4809), .Y(n631) );
MX2X1TS U6028 ( .A(Data_MY[48]), .B(Op_MY[48]), .S0(n4806), .Y(n630) );
MX2X1TS U6029 ( .A(Data_MY[47]), .B(Op_MY[47]), .S0(n4806), .Y(n629) );
MX2X1TS U6030 ( .A(Data_MY[46]), .B(Op_MY[46]), .S0(n4948), .Y(n628) );
MX2X1TS U6031 ( .A(Data_MY[45]), .B(Op_MY[45]), .S0(n4806), .Y(n627) );
MX2X1TS U6032 ( .A(Data_MY[44]), .B(Op_MY[44]), .S0(n4809), .Y(n626) );
MX2X1TS U6033 ( .A(Data_MY[43]), .B(Op_MY[43]), .S0(n4809), .Y(n625) );
MX2X1TS U6034 ( .A(Data_MY[42]), .B(Op_MY[42]), .S0(n4809), .Y(n624) );
MX2X1TS U6035 ( .A(Data_MY[41]), .B(Op_MY[41]), .S0(n4809), .Y(n623) );
MX2X1TS U6036 ( .A(Data_MY[40]), .B(Op_MY[40]), .S0(n4809), .Y(n622) );
MX2X1TS U6037 ( .A(Data_MY[39]), .B(Op_MY[39]), .S0(n4806), .Y(n621) );
MX2X1TS U6038 ( .A(Data_MY[38]), .B(Op_MY[38]), .S0(n4948), .Y(n620) );
MX2X1TS U6039 ( .A(Data_MY[37]), .B(Op_MY[37]), .S0(n4806), .Y(n619) );
MX2X1TS U6040 ( .A(Data_MY[36]), .B(Op_MY[36]), .S0(n4948), .Y(n618) );
MX2X1TS U6041 ( .A(Data_MY[35]), .B(Op_MY[35]), .S0(n4806), .Y(n617) );
MX2X1TS U6042 ( .A(Data_MY[34]), .B(Op_MY[34]), .S0(n4948), .Y(n616) );
MX2X1TS U6043 ( .A(Data_MY[33]), .B(Op_MY[33]), .S0(n4948), .Y(n615) );
MX2X1TS U6044 ( .A(Data_MY[32]), .B(Op_MY[32]), .S0(n4948), .Y(n614) );
MX2X1TS U6045 ( .A(Data_MY[31]), .B(Op_MY[31]), .S0(n4806), .Y(n613) );
MX2X1TS U6046 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n4948), .Y(n612) );
MX2X1TS U6047 ( .A(Data_MY[29]), .B(Op_MY[29]), .S0(n4948), .Y(n611) );
MX2X1TS U6048 ( .A(Data_MY[28]), .B(Op_MY[28]), .S0(n4948), .Y(n610) );
MX2X1TS U6049 ( .A(Data_MY[27]), .B(Op_MY[27]), .S0(n4807), .Y(n609) );
BUFX6TS U6050 ( .A(n5030), .Y(n4871) );
MX2X1TS U6051 ( .A(P_Sgf[0]), .B(n4811), .S0(n4871), .Y(n421) );
MX2X1TS U6052 ( .A(P_Sgf[1]), .B(n4812), .S0(n4871), .Y(n422) );
MX2X1TS U6053 ( .A(P_Sgf[2]), .B(n4813), .S0(n4871), .Y(n423) );
MX2X1TS U6054 ( .A(P_Sgf[3]), .B(n4814), .S0(n4871), .Y(n424) );
MX2X1TS U6055 ( .A(P_Sgf[4]), .B(n4815), .S0(n4871), .Y(n425) );
MX2X1TS U6056 ( .A(P_Sgf[5]), .B(n4816), .S0(n4871), .Y(n426) );
MX2X1TS U6057 ( .A(P_Sgf[6]), .B(n4817), .S0(n4871), .Y(n427) );
MX2X1TS U6058 ( .A(P_Sgf[7]), .B(n4818), .S0(n4871), .Y(n428) );
INVX2TS U6059 ( .A(n4819), .Y(n4821) );
NAND2X1TS U6060 ( .A(n4821), .B(n4820), .Y(n4823) );
XOR2X1TS U6061 ( .A(n4823), .B(n4822), .Y(n4824) );
NAND2X1TS U6062 ( .A(n908), .B(n4825), .Y(n4827) );
XNOR2X1TS U6063 ( .A(n4827), .B(n4826), .Y(n4828) );
NAND2X1TS U6064 ( .A(n909), .B(n4829), .Y(n4830) );
INVX2TS U6065 ( .A(n4832), .Y(n4834) );
NAND2X1TS U6066 ( .A(n4834), .B(n4833), .Y(n4836) );
NAND2X1TS U6067 ( .A(n907), .B(n4838), .Y(n4839) );
XNOR2X1TS U6068 ( .A(n4839), .B(n745), .Y(n4840) );
MX2X1TS U6069 ( .A(P_Sgf[44]), .B(n4840), .S0(n4871), .Y(n465) );
INVX2TS U6070 ( .A(n4841), .Y(n4843) );
NAND2X1TS U6071 ( .A(n4843), .B(n4842), .Y(n4845) );
XOR2X1TS U6072 ( .A(n4845), .B(n4844), .Y(n4846) );
MX2X1TS U6073 ( .A(P_Sgf[45]), .B(n4846), .S0(n4871), .Y(n466) );
NAND2X1TS U6074 ( .A(n889), .B(n4847), .Y(n4849) );
XNOR2X1TS U6075 ( .A(n4849), .B(n4848), .Y(n4850) );
MX2X1TS U6076 ( .A(P_Sgf[46]), .B(n4850), .S0(n4871), .Y(n467) );
XNOR2X1TS U6077 ( .A(n4852), .B(n837), .Y(n4853) );
MX2X1TS U6078 ( .A(P_Sgf[47]), .B(n4853), .S0(n4871), .Y(n468) );
NAND2X1TS U6079 ( .A(n904), .B(n4854), .Y(n4856) );
XNOR2X1TS U6080 ( .A(n4856), .B(n4855), .Y(n4857) );
MX2X1TS U6081 ( .A(P_Sgf[40]), .B(n4857), .S0(n4871), .Y(n461) );
NAND2X1TS U6082 ( .A(n905), .B(n4858), .Y(n4859) );
MX2X1TS U6083 ( .A(P_Sgf[41]), .B(n4860), .S0(n4871), .Y(n462) );
INVX2TS U6084 ( .A(n4861), .Y(n4863) );
NAND2X1TS U6085 ( .A(n4863), .B(n4862), .Y(n4865) );
XOR2X1TS U6086 ( .A(n4865), .B(n4864), .Y(n4866) );
MX2X1TS U6087 ( .A(P_Sgf[42]), .B(n4866), .S0(n4871), .Y(n463) );
NAND2X1TS U6088 ( .A(n906), .B(n4867), .Y(n4869) );
XNOR2X1TS U6089 ( .A(n4869), .B(n4868), .Y(n4870) );
MX2X1TS U6090 ( .A(P_Sgf[43]), .B(n4870), .S0(n4871), .Y(n464) );
MX2X1TS U6091 ( .A(P_Sgf[8]), .B(n4872), .S0(n4871), .Y(n429) );
BUFX6TS U6092 ( .A(n5030), .Y(n4906) );
MX2X1TS U6093 ( .A(P_Sgf[9]), .B(n4873), .S0(n4906), .Y(n430) );
MX2X1TS U6094 ( .A(P_Sgf[10]), .B(n4874), .S0(n4906), .Y(n431) );
MX2X1TS U6095 ( .A(P_Sgf[11]), .B(n4875), .S0(n4906), .Y(n432) );
MX2X1TS U6096 ( .A(P_Sgf[12]), .B(n4876), .S0(n4906), .Y(n433) );
MX2X1TS U6097 ( .A(P_Sgf[13]), .B(n4877), .S0(n4906), .Y(n434) );
MX2X1TS U6098 ( .A(P_Sgf[14]), .B(n4878), .S0(n4906), .Y(n435) );
MX2X1TS U6099 ( .A(P_Sgf[15]), .B(n4879), .S0(n4906), .Y(n436) );
MX2X1TS U6100 ( .A(P_Sgf[16]), .B(n4880), .S0(n4906), .Y(n437) );
MX2X1TS U6101 ( .A(P_Sgf[17]), .B(n4881), .S0(n4906), .Y(n438) );
MX2X1TS U6102 ( .A(P_Sgf[18]), .B(n4882), .S0(n4906), .Y(n439) );
MX2X1TS U6103 ( .A(P_Sgf[19]), .B(n4883), .S0(n4906), .Y(n440) );
MX2X1TS U6104 ( .A(P_Sgf[20]), .B(n4884), .S0(n4906), .Y(n441) );
MX2X1TS U6105 ( .A(P_Sgf[21]), .B(n4885), .S0(n4906), .Y(n442) );
MX2X1TS U6106 ( .A(P_Sgf[22]), .B(n4886), .S0(n4906), .Y(n443) );
MX2X1TS U6107 ( .A(P_Sgf[23]), .B(n4887), .S0(n4906), .Y(n444) );
MX2X1TS U6108 ( .A(P_Sgf[24]), .B(n4888), .S0(n4906), .Y(n445) );
MX2X1TS U6109 ( .A(P_Sgf[25]), .B(n4889), .S0(n4906), .Y(n446) );
MX2X1TS U6110 ( .A(P_Sgf[26]), .B(n4890), .S0(n4906), .Y(n447) );
MX2X1TS U6111 ( .A(P_Sgf[27]), .B(n823), .S0(n4906), .Y(n448) );
NAND2X1TS U6112 ( .A(n741), .B(n4894), .Y(n4896) );
XNOR2X1TS U6113 ( .A(n4896), .B(n4895), .Y(n4897) );
MX2X1TS U6114 ( .A(P_Sgf[28]), .B(n4897), .S0(n4906), .Y(n449) );
NAND2X1TS U6115 ( .A(n831), .B(n4898), .Y(n4899) );
XNOR2X1TS U6116 ( .A(n4899), .B(n729), .Y(n4900) );
MX2X1TS U6117 ( .A(P_Sgf[29]), .B(n4900), .S0(n4906), .Y(n450) );
INVX2TS U6118 ( .A(n4901), .Y(n4903) );
NAND2X1TS U6119 ( .A(n4903), .B(n4902), .Y(n4905) );
XOR2XLTS U6120 ( .A(n4905), .B(n4904), .Y(n4907) );
MX2X1TS U6121 ( .A(P_Sgf[30]), .B(n4907), .S0(n4906), .Y(n451) );
NAND2X1TS U6122 ( .A(n832), .B(n4908), .Y(n4910) );
XNOR2X1TS U6123 ( .A(n4910), .B(n4909), .Y(n4911) );
MX2X1TS U6124 ( .A(P_Sgf[31]), .B(n4911), .S0(n5019), .Y(n452) );
XNOR2X1TS U6125 ( .A(n4913), .B(n735), .Y(n4914) );
MX2X1TS U6126 ( .A(P_Sgf[32]), .B(n4914), .S0(n5019), .Y(n453) );
INVX2TS U6127 ( .A(n4915), .Y(n4917) );
NAND2X1TS U6128 ( .A(n4917), .B(n4916), .Y(n4919) );
XOR2XLTS U6129 ( .A(n4919), .B(n4918), .Y(n4920) );
MX2X1TS U6130 ( .A(P_Sgf[33]), .B(n4920), .S0(n5019), .Y(n454) );
NAND2X1TS U6131 ( .A(n893), .B(n4921), .Y(n4923) );
XNOR2X1TS U6132 ( .A(n4923), .B(n4922), .Y(n4924) );
MX2X1TS U6133 ( .A(P_Sgf[34]), .B(n4924), .S0(n5019), .Y(n455) );
NAND2X1TS U6134 ( .A(n894), .B(n4925), .Y(n4926) );
XNOR2X1TS U6135 ( .A(n4926), .B(n846), .Y(n4927) );
MX2X1TS U6136 ( .A(P_Sgf[35]), .B(n4927), .S0(n5019), .Y(n456) );
INVX2TS U6137 ( .A(n4928), .Y(n4930) );
NAND2X1TS U6138 ( .A(n4930), .B(n4929), .Y(n4932) );
XOR2XLTS U6139 ( .A(n4932), .B(n4931), .Y(n4933) );
MX2X1TS U6140 ( .A(P_Sgf[36]), .B(n4933), .S0(n5019), .Y(n457) );
NAND2X1TS U6141 ( .A(n918), .B(n4934), .Y(n4936) );
XNOR2X1TS U6142 ( .A(n4936), .B(n4935), .Y(n4937) );
MX2X1TS U6143 ( .A(P_Sgf[37]), .B(n4937), .S0(n5019), .Y(n458) );
NAND2X1TS U6144 ( .A(n919), .B(n4938), .Y(n4939) );
XNOR2X1TS U6145 ( .A(n4939), .B(n740), .Y(n4940) );
MX2X1TS U6146 ( .A(P_Sgf[38]), .B(n4940), .S0(n5019), .Y(n459) );
INVX2TS U6147 ( .A(n4941), .Y(n4943) );
NAND2X1TS U6148 ( .A(n4943), .B(n4942), .Y(n4945) );
XOR2X1TS U6149 ( .A(n4945), .B(n4944), .Y(n4946) );
MX2X1TS U6150 ( .A(P_Sgf[39]), .B(n4946), .S0(n5019), .Y(n460) );
MX2X1TS U6151 ( .A(Data_MY[52]), .B(Op_MY[52]), .S0(n4948), .Y(n634) );
MX2X1TS U6152 ( .A(Data_MY[61]), .B(Op_MY[61]), .S0(n4948), .Y(n643) );
MX2X1TS U6153 ( .A(Data_MY[60]), .B(Op_MY[60]), .S0(n4948), .Y(n642) );
MX2X1TS U6154 ( .A(Data_MY[59]), .B(n814), .S0(n4948), .Y(n641) );
MX2X1TS U6155 ( .A(Data_MY[58]), .B(n815), .S0(n4948), .Y(n640) );
MX2X1TS U6156 ( .A(Data_MY[57]), .B(n812), .S0(n4948), .Y(n639) );
MX2X1TS U6157 ( .A(Data_MY[56]), .B(Op_MY[56]), .S0(n4948), .Y(n638) );
MX2X1TS U6158 ( .A(Data_MY[55]), .B(Op_MY[55]), .S0(n4948), .Y(n637) );
MX2X1TS U6159 ( .A(Data_MY[62]), .B(Op_MY[62]), .S0(n4948), .Y(n644) );
MX2X1TS U6160 ( .A(Data_MY[54]), .B(Op_MY[54]), .S0(n4948), .Y(n636) );
MX2X1TS U6161 ( .A(Data_MX[62]), .B(Op_MX[62]), .S0(n4948), .Y(n708) );
MX2X1TS U6162 ( .A(Data_MX[61]), .B(Op_MX[61]), .S0(n4948), .Y(n707) );
MX2X1TS U6163 ( .A(Data_MX[60]), .B(Op_MX[60]), .S0(n4948), .Y(n706) );
MX2X1TS U6164 ( .A(Data_MX[59]), .B(Op_MX[59]), .S0(n4806), .Y(n705) );
MX2X1TS U6165 ( .A(Data_MX[58]), .B(Op_MX[58]), .S0(n4948), .Y(n704) );
MX2X1TS U6166 ( .A(Data_MX[57]), .B(Op_MX[57]), .S0(n4808), .Y(n703) );
MX2X1TS U6167 ( .A(Data_MX[56]), .B(Op_MX[56]), .S0(n4810), .Y(n702) );
MX2X1TS U6168 ( .A(Data_MX[55]), .B(Op_MX[55]), .S0(n4807), .Y(n701) );
MX2X1TS U6169 ( .A(Data_MX[52]), .B(n813), .S0(n4808), .Y(n698) );
MX2X1TS U6170 ( .A(Data_MX[54]), .B(Op_MX[54]), .S0(n4810), .Y(n700) );
MX2X1TS U6171 ( .A(Data_MY[53]), .B(Op_MY[53]), .S0(n4807), .Y(n635) );
MX2X1TS U6172 ( .A(Data_MX[53]), .B(Op_MX[53]), .S0(n4808), .Y(n699) );
CLKMX2X2TS U6173 ( .A(P_Sgf[104]), .B(n4951), .S0(n5019), .Y(n520) );
INVX2TS U6174 ( .A(n4952), .Y(n4954) );
NAND2X1TS U6175 ( .A(n948), .B(n4962), .Y(n4964) );
INVX2TS U6176 ( .A(n4966), .Y(n4968) );
INVX2TS U6177 ( .A(n4973), .Y(n4974) );
INVX2TS U6178 ( .A(n4976), .Y(n4978) );
NAND2X1TS U6179 ( .A(n947), .B(n4984), .Y(n4985) );
INVX2TS U6180 ( .A(n4988), .Y(n4991) );
INVX2TS U6181 ( .A(n4989), .Y(n4990) );
INVX2TS U6182 ( .A(n4992), .Y(n4994) );
NAND2X1TS U6183 ( .A(n4994), .B(n4993), .Y(n4995) );
INVX2TS U6184 ( .A(n5004), .Y(n5007) );
INVX2TS U6185 ( .A(n5008), .Y(n5010) );
NAND2X1TS U6186 ( .A(n5010), .B(n5009), .Y(n5011) );
NAND2X1TS U6187 ( .A(n945), .B(n5016), .Y(n5017) );
INVX2TS U6188 ( .A(n5021), .Y(n5024) );
INVX2TS U6189 ( .A(n5022), .Y(n5023) );
INVX2TS U6190 ( .A(n5025), .Y(n5027) );
NAND2X1TS U6191 ( .A(n5027), .B(n5026), .Y(n5028) );
BUFX6TS U6192 ( .A(n5030), .Y(n5228) );
NAND2X1TS U6193 ( .A(n944), .B(n5034), .Y(n5035) );
INVX2TS U6194 ( .A(n5039), .Y(n5040) );
INVX2TS U6195 ( .A(n5042), .Y(n5044) );
NAND2X1TS U6196 ( .A(n5044), .B(n5043), .Y(n5045) );
NAND2X1TS U6197 ( .A(n943), .B(n5050), .Y(n5051) );
INVX2TS U6198 ( .A(n5054), .Y(n5057) );
INVX2TS U6199 ( .A(n5055), .Y(n5056) );
INVX2TS U6200 ( .A(n5058), .Y(n5060) );
NAND2X1TS U6201 ( .A(n5060), .B(n5059), .Y(n5061) );
NAND2X1TS U6202 ( .A(n924), .B(n5066), .Y(n5067) );
NAND2X1TS U6203 ( .A(n5071), .B(n5070), .Y(n5072) );
NAND2X1TS U6204 ( .A(n910), .B(n5075), .Y(n5077) );
INVX2TS U6205 ( .A(n5079), .Y(n5081) );
NAND2X1TS U6206 ( .A(n5081), .B(n5080), .Y(n5082) );
NAND2X1TS U6207 ( .A(n5362), .B(n5503), .Y(n710) );
NOR2BX1TS U6208 ( .AN(exp_oper_result[11]), .B(n5503), .Y(S_Oper_A_exp[11])
);
NOR2X6TS U6209 ( .A(n5281), .B(n5364), .Y(n5085) );
MX2X1TS U6210 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n5085), .Y(n407) );
MX2X1TS U6211 ( .A(Op_MX[62]), .B(exp_oper_result[10]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[10]) );
MX2X1TS U6212 ( .A(Exp_module_Data_S[9]), .B(exp_oper_result[9]), .S0(n5085),
.Y(n408) );
MX2X1TS U6213 ( .A(Op_MX[61]), .B(exp_oper_result[9]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[9]) );
MX2X1TS U6214 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(n5085),
.Y(n409) );
MX2X1TS U6215 ( .A(Op_MX[60]), .B(exp_oper_result[8]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[8]) );
MX2X1TS U6216 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(n5085),
.Y(n410) );
MX2X1TS U6217 ( .A(Op_MX[59]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
MX2X1TS U6218 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(n5085),
.Y(n411) );
MX2X1TS U6219 ( .A(Op_MX[58]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
MX2X1TS U6220 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(n5085),
.Y(n412) );
MX2X1TS U6221 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
MX2X1TS U6222 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(n5085),
.Y(n413) );
MX2X1TS U6223 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
MX2X1TS U6224 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(n5085),
.Y(n414) );
MX2X1TS U6225 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
MX2X1TS U6226 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(n5085),
.Y(n415) );
MX2X1TS U6227 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
MX2X1TS U6228 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(n5085),
.Y(n416) );
MX2X1TS U6229 ( .A(Op_MX[53]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
MX2X1TS U6230 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(n5085),
.Y(n417) );
MX2X1TS U6231 ( .A(n813), .B(exp_oper_result[0]), .S0(FSM_selector_A), .Y(
S_Oper_A_exp[0]) );
MX2X1TS U6232 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n5085), .Y(n406) );
XNOR2X1TS U6233 ( .A(DP_OP_36J30_123_1029_n1), .B(n5315), .Y(n5086) );
MX2X1TS U6234 ( .A(Exp_module_Overflow_flag_A), .B(n5086), .S0(n5228), .Y(
n405) );
NAND4XLTS U6235 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n5087) );
NAND4BXLTS U6236 ( .AN(n5087), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n5088) );
NAND4BXLTS U6237 ( .AN(n5088), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n5089) );
NAND3BXLTS U6238 ( .AN(Exp_module_Data_S[10]), .B(n5364), .C(n5089), .Y(
n5090) );
OAI22X1TS U6239 ( .A0(Exp_module_Data_S[11]), .A1(n5090), .B0(n5364), .B1(
n5506), .Y(n352) );
INVX2TS U6240 ( .A(n5091), .Y(n5093) );
AOI22X1TS U6241 ( .A0(Sgf_normalized_result[18]), .A1(n5168), .B0(n801),
.B1(n5152), .Y(n5098) );
INVX2TS U6242 ( .A(n4744), .Y(n5311) );
BUFX6TS U6243 ( .A(n5311), .Y(n5273) );
NAND2X1TS U6244 ( .A(n5273), .B(P_Sgf[71]), .Y(n5097) );
OAI211XLTS U6245 ( .A0(n5099), .A1(n5504), .B0(n5098), .C0(n5097), .Y(n5100)
);
AO21XLTS U6246 ( .A0(n5240), .A1(Add_result[18]), .B0(n5100), .Y(n371) );
INVX2TS U6247 ( .A(n5101), .Y(n5103) );
AOI22X1TS U6248 ( .A0(Sgf_normalized_result[19]), .A1(n5168), .B0(n791),
.B1(n5152), .Y(n5106) );
OAI2BB1X1TS U6249 ( .A0N(P_Sgf[72]), .A1N(n5273), .B0(n5106), .Y(n5107) );
AOI21X1TS U6250 ( .A0(n5297), .A1(P_Sgf[71]), .B0(n5107), .Y(n5108) );
OAI2BB1X1TS U6251 ( .A0N(n5307), .A1N(n801), .B0(n5108), .Y(n372) );
AOI22X1TS U6252 ( .A0(Sgf_normalized_result[20]), .A1(n5168), .B0(n802),
.B1(n5152), .Y(n5113) );
OAI2BB1X1TS U6253 ( .A0N(P_Sgf[73]), .A1N(n5273), .B0(n5113), .Y(n5114) );
AOI21X1TS U6254 ( .A0(n5305), .A1(P_Sgf[72]), .B0(n5114), .Y(n5115) );
OAI2BB1X1TS U6255 ( .A0N(n5147), .A1N(n791), .B0(n5115), .Y(n373) );
AOI22X1TS U6256 ( .A0(Sgf_normalized_result[21]), .A1(n5168), .B0(n792),
.B1(n5152), .Y(n5119) );
OAI2BB1X1TS U6257 ( .A0N(P_Sgf[74]), .A1N(n5273), .B0(n5119), .Y(n5120) );
AOI21X1TS U6258 ( .A0(n5305), .A1(P_Sgf[73]), .B0(n5120), .Y(n5121) );
OAI2BB1X1TS U6259 ( .A0N(n5147), .A1N(n802), .B0(n5121), .Y(n374) );
AOI22X1TS U6260 ( .A0(Sgf_normalized_result[22]), .A1(n5168), .B0(n803),
.B1(n5152), .Y(n5128) );
OAI2BB1X1TS U6261 ( .A0N(P_Sgf[75]), .A1N(n5273), .B0(n5128), .Y(n5129) );
AOI21X1TS U6262 ( .A0(n5305), .A1(P_Sgf[74]), .B0(n5129), .Y(n5130) );
OAI2BB1X1TS U6263 ( .A0N(n5147), .A1N(n792), .B0(n5130), .Y(n375) );
AOI22X1TS U6264 ( .A0(Sgf_normalized_result[23]), .A1(n5168), .B0(n793),
.B1(n5152), .Y(n5136) );
OAI2BB1X1TS U6265 ( .A0N(P_Sgf[76]), .A1N(n5273), .B0(n5136), .Y(n5137) );
AOI21X1TS U6266 ( .A0(n5305), .A1(P_Sgf[75]), .B0(n5137), .Y(n5138) );
OAI2BB1X1TS U6267 ( .A0N(n5240), .A1N(n803), .B0(n5138), .Y(n376) );
AOI22X1TS U6268 ( .A0(Sgf_normalized_result[24]), .A1(n5168), .B0(n806),
.B1(n5152), .Y(n5144) );
OAI2BB1X1TS U6269 ( .A0N(P_Sgf[77]), .A1N(n5273), .B0(n5144), .Y(n5145) );
AOI21X1TS U6270 ( .A0(n5305), .A1(P_Sgf[76]), .B0(n5145), .Y(n5146) );
OAI2BB1X1TS U6271 ( .A0N(n5147), .A1N(n793), .B0(n5146), .Y(n377) );
AOI22X1TS U6272 ( .A0(Sgf_normalized_result[25]), .A1(n5168), .B0(n794),
.B1(n5152), .Y(n5153) );
OAI2BB1X1TS U6273 ( .A0N(P_Sgf[78]), .A1N(n5273), .B0(n5153), .Y(n5154) );
AOI21X1TS U6274 ( .A0(n5305), .A1(P_Sgf[77]), .B0(n5154), .Y(n5155) );
OAI2BB1X1TS U6275 ( .A0N(n5240), .A1N(n806), .B0(n5155), .Y(n378) );
AOI22X1TS U6276 ( .A0(Sgf_normalized_result[26]), .A1(n5168), .B0(n807),
.B1(n5302), .Y(n5159) );
OAI2BB1X1TS U6277 ( .A0N(P_Sgf[79]), .A1N(n5273), .B0(n5159), .Y(n5160) );
AOI21X1TS U6278 ( .A0(n5305), .A1(P_Sgf[78]), .B0(n5160), .Y(n5161) );
OAI2BB1X1TS U6279 ( .A0N(n5240), .A1N(n794), .B0(n5161), .Y(n379) );
AOI22X1TS U6280 ( .A0(Sgf_normalized_result[27]), .A1(n5168), .B0(n795),
.B1(n5302), .Y(n5169) );
OAI2BB1X1TS U6281 ( .A0N(P_Sgf[80]), .A1N(n5273), .B0(n5169), .Y(n5170) );
AOI21X1TS U6282 ( .A0(n5305), .A1(P_Sgf[79]), .B0(n5170), .Y(n5171) );
OAI2BB1X1TS U6283 ( .A0N(n5240), .A1N(n807), .B0(n5171), .Y(n380) );
AOI22X1TS U6284 ( .A0(Sgf_normalized_result[28]), .A1(n5251), .B0(n808),
.B1(n5302), .Y(n5177) );
OAI2BB1X1TS U6285 ( .A0N(P_Sgf[81]), .A1N(n5273), .B0(n5177), .Y(n5178) );
AOI21X1TS U6286 ( .A0(n5305), .A1(P_Sgf[80]), .B0(n5178), .Y(n5179) );
OAI2BB1X1TS U6287 ( .A0N(n5240), .A1N(n795), .B0(n5179), .Y(n381) );
AOI22X1TS U6288 ( .A0(Sgf_normalized_result[29]), .A1(n5251), .B0(n796),
.B1(n5302), .Y(n5184) );
OAI2BB1X1TS U6289 ( .A0N(P_Sgf[82]), .A1N(n5273), .B0(n5184), .Y(n5185) );
AOI21X1TS U6290 ( .A0(n5305), .A1(P_Sgf[81]), .B0(n5185), .Y(n5186) );
OAI2BB1X1TS U6291 ( .A0N(n5240), .A1N(n808), .B0(n5186), .Y(n382) );
AOI22X1TS U6292 ( .A0(Sgf_normalized_result[30]), .A1(n5251), .B0(n809),
.B1(n5302), .Y(n5193) );
OAI2BB1X1TS U6293 ( .A0N(P_Sgf[83]), .A1N(n5273), .B0(n5193), .Y(n5194) );
AOI21X1TS U6294 ( .A0(n5305), .A1(P_Sgf[82]), .B0(n5194), .Y(n5195) );
OAI2BB1X1TS U6295 ( .A0N(n5307), .A1N(n796), .B0(n5195), .Y(n383) );
AOI22X1TS U6296 ( .A0(Sgf_normalized_result[31]), .A1(n5251), .B0(
Add_result[32]), .B1(n5302), .Y(n5196) );
OAI2BB1X1TS U6297 ( .A0N(P_Sgf[84]), .A1N(n5273), .B0(n5196), .Y(n5197) );
AOI21X1TS U6298 ( .A0(n5305), .A1(P_Sgf[83]), .B0(n5197), .Y(n5198) );
OAI2BB1X1TS U6299 ( .A0N(n5240), .A1N(n809), .B0(n5198), .Y(n384) );
CLKMX2X2TS U6300 ( .A(P_Sgf[85]), .B(n5200), .S0(n5281), .Y(n506) );
AOI22X1TS U6301 ( .A0(Sgf_normalized_result[32]), .A1(n5251), .B0(
Add_result[33]), .B1(n5302), .Y(n5201) );
OAI2BB1X1TS U6302 ( .A0N(P_Sgf[85]), .A1N(n5273), .B0(n5201), .Y(n5202) );
AOI21X1TS U6303 ( .A0(n5305), .A1(P_Sgf[84]), .B0(n5202), .Y(n5203) );
OAI2BB1X1TS U6304 ( .A0N(n5240), .A1N(Add_result[32]), .B0(n5203), .Y(n385)
);
CLKMX2X2TS U6305 ( .A(P_Sgf[86]), .B(n5206), .S0(n5281), .Y(n507) );
AOI22X1TS U6306 ( .A0(Sgf_normalized_result[33]), .A1(n5251), .B0(
Add_result[34]), .B1(n5302), .Y(n5207) );
OAI2BB1X1TS U6307 ( .A0N(P_Sgf[86]), .A1N(n5273), .B0(n5207), .Y(n5208) );
AOI21X1TS U6308 ( .A0(n5305), .A1(P_Sgf[85]), .B0(n5208), .Y(n5209) );
OAI2BB1X1TS U6309 ( .A0N(n5240), .A1N(Add_result[33]), .B0(n5209), .Y(n386)
);
CLKMX2X2TS U6310 ( .A(P_Sgf[87]), .B(n5214), .S0(n5281), .Y(n508) );
AOI22X1TS U6311 ( .A0(Sgf_normalized_result[34]), .A1(n5251), .B0(
Add_result[35]), .B1(n5302), .Y(n5215) );
OAI2BB1X1TS U6312 ( .A0N(P_Sgf[87]), .A1N(n5273), .B0(n5215), .Y(n5216) );
AOI21X1TS U6313 ( .A0(n5305), .A1(P_Sgf[86]), .B0(n5216), .Y(n5217) );
OAI2BB1X1TS U6314 ( .A0N(n5240), .A1N(Add_result[34]), .B0(n5217), .Y(n387)
);
CLKMX2X2TS U6315 ( .A(P_Sgf[88]), .B(n5220), .S0(n5281), .Y(n509) );
AOI22X1TS U6316 ( .A0(Sgf_normalized_result[35]), .A1(n5251), .B0(
Add_result[36]), .B1(n5302), .Y(n5221) );
OAI2BB1X1TS U6317 ( .A0N(P_Sgf[88]), .A1N(n5273), .B0(n5221), .Y(n5222) );
AOI21X1TS U6318 ( .A0(n5305), .A1(P_Sgf[87]), .B0(n5222), .Y(n5223) );
OAI2BB1X1TS U6319 ( .A0N(n5240), .A1N(Add_result[35]), .B0(n5223), .Y(n388)
);
INVX2TS U6320 ( .A(n5224), .Y(n5225) );
CLKMX2X2TS U6321 ( .A(P_Sgf[89]), .B(n5229), .S0(n5228), .Y(n510) );
AOI22X1TS U6322 ( .A0(Sgf_normalized_result[36]), .A1(n5251), .B0(
Add_result[37]), .B1(n5302), .Y(n5230) );
OAI2BB1X1TS U6323 ( .A0N(P_Sgf[89]), .A1N(n5273), .B0(n5230), .Y(n5231) );
AOI21X1TS U6324 ( .A0(n5305), .A1(P_Sgf[88]), .B0(n5231), .Y(n5232) );
OAI2BB1X1TS U6325 ( .A0N(n5240), .A1N(Add_result[36]), .B0(n5232), .Y(n389)
);
CLKMX2X2TS U6326 ( .A(P_Sgf[90]), .B(n5236), .S0(n5281), .Y(n511) );
AOI22X1TS U6327 ( .A0(Sgf_normalized_result[37]), .A1(n5251), .B0(
Add_result[38]), .B1(n5302), .Y(n5237) );
OAI2BB1X1TS U6328 ( .A0N(P_Sgf[90]), .A1N(n5273), .B0(n5237), .Y(n5238) );
AOI21X1TS U6329 ( .A0(n5297), .A1(P_Sgf[89]), .B0(n5238), .Y(n5239) );
OAI2BB1X1TS U6330 ( .A0N(n5240), .A1N(Add_result[37]), .B0(n5239), .Y(n390)
);
CLKMX2X2TS U6331 ( .A(P_Sgf[91]), .B(n5244), .S0(n5281), .Y(n512) );
AOI22X1TS U6332 ( .A0(Sgf_normalized_result[38]), .A1(n5251), .B0(
Add_result[39]), .B1(n5302), .Y(n5245) );
OAI2BB1X1TS U6333 ( .A0N(P_Sgf[91]), .A1N(n5273), .B0(n5245), .Y(n5246) );
AOI21X1TS U6334 ( .A0(n5305), .A1(P_Sgf[90]), .B0(n5246), .Y(n5247) );
OAI2BB1X1TS U6335 ( .A0N(n5307), .A1N(Add_result[38]), .B0(n5247), .Y(n391)
);
CLKMX2X2TS U6336 ( .A(P_Sgf[92]), .B(n5250), .S0(n5281), .Y(n513) );
AOI22X1TS U6337 ( .A0(Sgf_normalized_result[39]), .A1(n5251), .B0(
Add_result[40]), .B1(n5302), .Y(n5252) );
OAI2BB1X1TS U6338 ( .A0N(P_Sgf[92]), .A1N(n5273), .B0(n5252), .Y(n5253) );
AOI21X1TS U6339 ( .A0(n5297), .A1(P_Sgf[91]), .B0(n5253), .Y(n5254) );
OAI2BB1X1TS U6340 ( .A0N(n5307), .A1N(Add_result[39]), .B0(n5254), .Y(n392)
);
CLKMX2X2TS U6341 ( .A(P_Sgf[93]), .B(n5258), .S0(n5281), .Y(n514) );
AOI22X1TS U6342 ( .A0(Sgf_normalized_result[40]), .A1(n5309), .B0(
Add_result[41]), .B1(n5302), .Y(n5259) );
OAI2BB1X1TS U6343 ( .A0N(P_Sgf[93]), .A1N(n5273), .B0(n5259), .Y(n5260) );
AOI21X1TS U6344 ( .A0(n5305), .A1(P_Sgf[92]), .B0(n5260), .Y(n5261) );
OAI2BB1X1TS U6345 ( .A0N(n5307), .A1N(Add_result[40]), .B0(n5261), .Y(n393)
);
CLKMX2X2TS U6346 ( .A(P_Sgf[94]), .B(n5264), .S0(n5281), .Y(n515) );
AOI22X1TS U6347 ( .A0(Sgf_normalized_result[41]), .A1(n5309), .B0(
Add_result[42]), .B1(n5302), .Y(n5265) );
OAI2BB1X1TS U6348 ( .A0N(P_Sgf[94]), .A1N(n5273), .B0(n5265), .Y(n5266) );
AOI21X1TS U6349 ( .A0(n5297), .A1(P_Sgf[93]), .B0(n5266), .Y(n5267) );
OAI2BB1X1TS U6350 ( .A0N(n5307), .A1N(Add_result[41]), .B0(n5267), .Y(n394)
);
CLKMX2X2TS U6351 ( .A(P_Sgf[95]), .B(n5271), .S0(n5281), .Y(n516) );
AOI22X1TS U6352 ( .A0(Sgf_normalized_result[42]), .A1(n5309), .B0(n810),
.B1(n5152), .Y(n5272) );
OAI2BB1X1TS U6353 ( .A0N(P_Sgf[95]), .A1N(n5273), .B0(n5272), .Y(n5274) );
AOI21X1TS U6354 ( .A0(n5305), .A1(P_Sgf[94]), .B0(n5274), .Y(n5275) );
OAI2BB1X1TS U6355 ( .A0N(n5307), .A1N(Add_result[42]), .B0(n5275), .Y(n395)
);
CLKMX2X2TS U6356 ( .A(P_Sgf[96]), .B(n5282), .S0(n5281), .Y(n517) );
AOI22X1TS U6357 ( .A0(Sgf_normalized_result[43]), .A1(n5309), .B0(n797),
.B1(n5302), .Y(n5283) );
OAI2BB1X1TS U6358 ( .A0N(P_Sgf[96]), .A1N(n5311), .B0(n5283), .Y(n5284) );
AOI21X1TS U6359 ( .A0(n5297), .A1(P_Sgf[95]), .B0(n5284), .Y(n5285) );
OAI2BB1X1TS U6360 ( .A0N(n5307), .A1N(n810), .B0(n5285), .Y(n396) );
AOI22X1TS U6361 ( .A0(Sgf_normalized_result[44]), .A1(n5309), .B0(n811),
.B1(n5152), .Y(n5286) );
OAI2BB1X1TS U6362 ( .A0N(P_Sgf[97]), .A1N(n5311), .B0(n5286), .Y(n5287) );
AOI21X1TS U6363 ( .A0(n5305), .A1(P_Sgf[96]), .B0(n5287), .Y(n5288) );
OAI2BB1X1TS U6364 ( .A0N(n5307), .A1N(n797), .B0(n5288), .Y(n397) );
AOI22X1TS U6365 ( .A0(Sgf_normalized_result[45]), .A1(n5309), .B0(n798),
.B1(n5302), .Y(n5289) );
OAI2BB1X1TS U6366 ( .A0N(P_Sgf[98]), .A1N(n5311), .B0(n5289), .Y(n5290) );
AOI21X1TS U6367 ( .A0(n5297), .A1(P_Sgf[97]), .B0(n5290), .Y(n5291) );
OAI2BB1X1TS U6368 ( .A0N(n5307), .A1N(n811), .B0(n5291), .Y(n398) );
AOI22X1TS U6369 ( .A0(Sgf_normalized_result[46]), .A1(n5309), .B0(n804),
.B1(n5152), .Y(n5292) );
OAI2BB1X1TS U6370 ( .A0N(P_Sgf[99]), .A1N(n5311), .B0(n5292), .Y(n5293) );
AOI21X1TS U6371 ( .A0(n5305), .A1(P_Sgf[98]), .B0(n5293), .Y(n5294) );
OAI2BB1X1TS U6372 ( .A0N(n5307), .A1N(n798), .B0(n5294), .Y(n399) );
AOI22X1TS U6373 ( .A0(Sgf_normalized_result[47]), .A1(n5309), .B0(n799),
.B1(n5302), .Y(n5295) );
OAI2BB1X1TS U6374 ( .A0N(P_Sgf[100]), .A1N(n5311), .B0(n5295), .Y(n5296) );
AOI21X1TS U6375 ( .A0(n5297), .A1(P_Sgf[99]), .B0(n5296), .Y(n5298) );
OAI2BB1X1TS U6376 ( .A0N(n5307), .A1N(n804), .B0(n5298), .Y(n400) );
AOI22X1TS U6377 ( .A0(Sgf_normalized_result[48]), .A1(n5309), .B0(n805),
.B1(n5152), .Y(n5299) );
OAI2BB1X1TS U6378 ( .A0N(P_Sgf[101]), .A1N(n5311), .B0(n5299), .Y(n5300) );
AOI21X1TS U6379 ( .A0(n5305), .A1(P_Sgf[100]), .B0(n5300), .Y(n5301) );
OAI2BB1X1TS U6380 ( .A0N(n5307), .A1N(n799), .B0(n5301), .Y(n401) );
AOI22X1TS U6381 ( .A0(Sgf_normalized_result[49]), .A1(n5309), .B0(n800),
.B1(n5302), .Y(n5303) );
OAI2BB1X1TS U6382 ( .A0N(P_Sgf[102]), .A1N(n5311), .B0(n5303), .Y(n5304) );
AOI21X1TS U6383 ( .A0(n5305), .A1(P_Sgf[101]), .B0(n5304), .Y(n5306) );
OAI2BB1X1TS U6384 ( .A0N(n5307), .A1N(n805), .B0(n5306), .Y(n402) );
AOI22X1TS U6385 ( .A0(Sgf_normalized_result[50]), .A1(n5309), .B0(n816),
.B1(n5152), .Y(n5310) );
OAI2BB1X1TS U6386 ( .A0N(P_Sgf[103]), .A1N(n5311), .B0(n5310), .Y(n5312) );
AOI21X1TS U6387 ( .A0(n5313), .A1(P_Sgf[102]), .B0(n5312), .Y(n5314) );
OAI2BB1X1TS U6388 ( .A0N(n5307), .A1N(n800), .B0(n5314), .Y(n403) );
AO22XLTS U6389 ( .A0(n4947), .A1(Data_MY[63]), .B0(n4806), .B1(Op_MY[63]),
.Y(n715) );
OAI22X1TS U6390 ( .A0(n5315), .A1(zero_flag), .B0(P_Sgf[105]), .B1(n5319),
.Y(n5316) );
AOI2BB1XLTS U6391 ( .A0N(n5317), .A1N(n5316), .B0(n5318), .Y(n713) );
AOI21X1TS U6392 ( .A0(FS_Module_state_reg[2]), .A1(n5318), .B0(n5526), .Y(
n5321) );
NAND3XLTS U6393 ( .A(n5321), .B(n5320), .C(n5319), .Y(n711) );
NOR4X1TS U6394 ( .A(Op_MY[60]), .B(n814), .C(n815), .D(n812), .Y(n5323) );
NOR4X1TS U6395 ( .A(Op_MY[56]), .B(Op_MY[55]), .C(Op_MY[62]), .D(Op_MY[54]),
.Y(n5322) );
NAND4XLTS U6396 ( .A(n5325), .B(n5324), .C(n5323), .D(n5322), .Y(n5330) );
NAND4BXLTS U6397 ( .AN(n5330), .B(n5329), .C(n5328), .D(n5327), .Y(n5341) );
NOR4X1TS U6398 ( .A(Op_MY[35]), .B(Op_MY[34]), .C(Op_MY[33]), .D(Op_MY[32]),
.Y(n5334) );
NOR4X1TS U6399 ( .A(Op_MY[43]), .B(Op_MY[42]), .C(Op_MY[41]), .D(Op_MY[40]),
.Y(n5332) );
NAND4XLTS U6400 ( .A(n5334), .B(n5333), .C(n5332), .D(n5331), .Y(n5340) );
NOR4X1TS U6401 ( .A(Op_MY[5]), .B(Op_MY[4]), .C(Op_MY[3]), .D(Op_MY[2]), .Y(
n5338) );
NAND4XLTS U6402 ( .A(n5338), .B(n5337), .C(n5336), .D(n5335), .Y(n5339) );
OR3X1TS U6403 ( .A(n5341), .B(n5340), .C(n5339), .Y(n5365) );
NOR4X1TS U6404 ( .A(Op_MX[60]), .B(Op_MX[59]), .C(Op_MX[58]), .D(Op_MX[57]),
.Y(n5343) );
NAND4XLTS U6405 ( .A(n5345), .B(n5344), .C(n5343), .D(n5342), .Y(n5361) );
NAND4XLTS U6406 ( .A(n5349), .B(n5348), .C(n5347), .D(n5346), .Y(n5360) );
NAND4XLTS U6407 ( .A(n5353), .B(n5352), .C(n5351), .D(n5350), .Y(n5359) );
NAND4XLTS U6408 ( .A(n5357), .B(n5356), .C(n5355), .D(n5354), .Y(n5358) );
OR4X2TS U6409 ( .A(n5361), .B(n5360), .C(n5359), .D(n5358), .Y(n5363) );
AOI32X1TS U6410 ( .A0(n5365), .A1(n5364), .A2(n5363), .B0(n5524), .B1(n5362),
.Y(n581) );
AOI32X1TS U6411 ( .A0(n5369), .A1(n5368), .A2(n5367), .B0(n5505), .B1(n5366),
.Y(n580) );
AO22XLTS U6412 ( .A0(n5464), .A1(Sgf_normalized_result[0]), .B0(n5449), .B1(
Add_result[0]), .Y(n579) );
AO22XLTS U6413 ( .A0(n5464), .A1(Sgf_normalized_result[1]), .B0(n5449), .B1(
Add_result[1]), .Y(n578) );
AOI2BB2XLTS U6414 ( .B0(n5454), .B1(Sgf_normalized_result[2]), .A0N(
Add_result[2]), .A1N(n5454), .Y(n577) );
NAND2X1TS U6415 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n5370) );
OAI211XLTS U6416 ( .A0(Sgf_normalized_result[3]), .A1(
Sgf_normalized_result[2]), .B0(n5455), .C0(n5370), .Y(n5371) );
OAI2BB1X1TS U6417 ( .A0N(Add_result[3]), .A1N(n5449), .B0(n5371), .Y(n576)
);
AOI31XLTS U6418 ( .A0(Sgf_normalized_result[3]), .A1(
Sgf_normalized_result[4]), .A2(Sgf_normalized_result[2]), .B0(n5373),
.Y(n5372) );
AOI2BB2XLTS U6419 ( .B0(n5454), .B1(n5372), .A0N(Add_result[4]), .A1N(n5464),
.Y(n575) );
OAI21XLTS U6420 ( .A0(n5373), .A1(n5477), .B0(n5376), .Y(n5375) );
OAI211XLTS U6421 ( .A0(Sgf_normalized_result[6]), .A1(n5376), .B0(n5455),
.C0(n5378), .Y(n5377) );
OAI2BB1X1TS U6422 ( .A0N(Add_result[6]), .A1N(n4693), .B0(n5377), .Y(n573)
);
AOI21X1TS U6423 ( .A0(n5478), .A1(n5378), .B0(n5380), .Y(n5379) );
OAI211XLTS U6424 ( .A0(Sgf_normalized_result[8]), .A1(n5380), .B0(n5455),
.C0(n5382), .Y(n5381) );
OAI2BB1X1TS U6425 ( .A0N(Add_result[8]), .A1N(n5449), .B0(n5381), .Y(n571)
);
AOI21X1TS U6426 ( .A0(n5479), .A1(n5382), .B0(n5384), .Y(n5383) );
OAI211XLTS U6427 ( .A0(Sgf_normalized_result[10]), .A1(n5384), .B0(n5455),
.C0(n5386), .Y(n5385) );
OAI2BB1X1TS U6428 ( .A0N(Add_result[10]), .A1N(n5460), .B0(n5385), .Y(n569)
);
AOI21X1TS U6429 ( .A0(n5480), .A1(n5386), .B0(n5388), .Y(n5387) );
OAI2BB1X1TS U6430 ( .A0N(Add_result[12]), .A1N(n5449), .B0(n5389), .Y(n567)
);
AOI21X1TS U6431 ( .A0(n5481), .A1(n5390), .B0(n5392), .Y(n5391) );
OAI211XLTS U6432 ( .A0(Sgf_normalized_result[14]), .A1(n5392), .B0(n5455),
.C0(n5394), .Y(n5393) );
OAI2BB1X1TS U6433 ( .A0N(Add_result[14]), .A1N(n5449), .B0(n5393), .Y(n565)
);
AOI21X1TS U6434 ( .A0(n5482), .A1(n5394), .B0(n5396), .Y(n5395) );
OAI211XLTS U6435 ( .A0(Sgf_normalized_result[16]), .A1(n5396), .B0(n5464),
.C0(n5398), .Y(n5397) );
OAI2BB1X1TS U6436 ( .A0N(Add_result[16]), .A1N(n5460), .B0(n5397), .Y(n563)
);
AOI21X1TS U6437 ( .A0(n5483), .A1(n5398), .B0(n5400), .Y(n5399) );
OAI211XLTS U6438 ( .A0(Sgf_normalized_result[18]), .A1(n5400), .B0(n5464),
.C0(n5402), .Y(n5401) );
OAI2BB1X1TS U6439 ( .A0N(Add_result[18]), .A1N(n5460), .B0(n5401), .Y(n561)
);
AOI21X1TS U6440 ( .A0(n5484), .A1(n5402), .B0(n5404), .Y(n5403) );
OAI211XLTS U6441 ( .A0(Sgf_normalized_result[20]), .A1(n5404), .B0(n5464),
.C0(n5406), .Y(n5405) );
OAI2BB1X1TS U6442 ( .A0N(n791), .A1N(n5460), .B0(n5405), .Y(n559) );
AOI21X1TS U6443 ( .A0(n5485), .A1(n5406), .B0(n5408), .Y(n5407) );
OAI211XLTS U6444 ( .A0(Sgf_normalized_result[22]), .A1(n5408), .B0(n5464),
.C0(n5410), .Y(n5409) );
OAI2BB1X1TS U6445 ( .A0N(n792), .A1N(n5460), .B0(n5409), .Y(n557) );
AOI21X1TS U6446 ( .A0(n5486), .A1(n5410), .B0(n5413), .Y(n5411) );
OAI2BB1X1TS U6447 ( .A0N(n793), .A1N(n5460), .B0(n5414), .Y(n555) );
OAI211XLTS U6448 ( .A0(Sgf_normalized_result[26]), .A1(n5416), .B0(n5464),
.C0(n5415), .Y(n5417) );
OAI2BB1X1TS U6449 ( .A0N(n794), .A1N(n5460), .B0(n5417), .Y(n553) );
OAI211XLTS U6450 ( .A0(Sgf_normalized_result[28]), .A1(n5419), .B0(n5454),
.C0(n5418), .Y(n5420) );
OAI2BB1X1TS U6451 ( .A0N(n795), .A1N(n5460), .B0(n5420), .Y(n551) );
OAI211XLTS U6452 ( .A0(Sgf_normalized_result[30]), .A1(n5422), .B0(n5454),
.C0(n5421), .Y(n5423) );
OAI2BB1X1TS U6453 ( .A0N(n796), .A1N(n5460), .B0(n5423), .Y(n549) );
OAI211XLTS U6454 ( .A0(Sgf_normalized_result[32]), .A1(n5425), .B0(n5464),
.C0(n5424), .Y(n5426) );
OAI2BB1X1TS U6455 ( .A0N(Add_result[32]), .A1N(n5460), .B0(n5426), .Y(n547)
);
OAI211XLTS U6456 ( .A0(Sgf_normalized_result[34]), .A1(n5428), .B0(n5454),
.C0(n5427), .Y(n5429) );
OAI2BB1X1TS U6457 ( .A0N(Add_result[34]), .A1N(n5460), .B0(n5429), .Y(n545)
);
OAI211XLTS U6458 ( .A0(Sgf_normalized_result[36]), .A1(n5431), .B0(n5454),
.C0(n5430), .Y(n5432) );
OAI2BB1X1TS U6459 ( .A0N(Add_result[36]), .A1N(n5460), .B0(n5432), .Y(n543)
);
OAI2BB1X1TS U6460 ( .A0N(Add_result[38]), .A1N(n5460), .B0(n5435), .Y(n541)
);
OAI2BB1X1TS U6461 ( .A0N(Add_result[40]), .A1N(n5449), .B0(n5437), .Y(n539)
);
AOI21X1TS U6462 ( .A0(n5496), .A1(n5438), .B0(n5441), .Y(n5439) );
OAI2BB1X1TS U6463 ( .A0N(Add_result[42]), .A1N(n5460), .B0(n5442), .Y(n537)
);
OAI2BB1X1TS U6464 ( .A0N(n797), .A1N(n5460), .B0(n5445), .Y(n535) );
OAI2BB1X1TS U6465 ( .A0N(n798), .A1N(n5449), .B0(n5448), .Y(n533) );
NAND2X1TS U6466 ( .A(Sgf_normalized_result[48]), .B(n5450), .Y(n5452) );
OAI2BB1X1TS U6467 ( .A0N(n799), .A1N(n5460), .B0(n5451), .Y(n531) );
NOR2X2TS U6468 ( .A(n5501), .B(n5452), .Y(n5456) );
AOI21X1TS U6469 ( .A0(n5501), .A1(n5452), .B0(n5456), .Y(n5453) );
NAND2X1TS U6470 ( .A(Sgf_normalized_result[50]), .B(n5456), .Y(n5458) );
OAI2BB1X1TS U6471 ( .A0N(n800), .A1N(n5449), .B0(n5457), .Y(n529) );
NOR2X2TS U6472 ( .A(n5502), .B(n5458), .Y(n5461) );
AOI211X1TS U6473 ( .A0(n5502), .A1(n5458), .B0(n5461), .C0(n5460), .Y(n5459)
);
AOI21X1TS U6474 ( .A0(n5461), .A1(Sgf_normalized_result[52]), .B0(n5374),
.Y(n5463) );
OAI2BB1X1TS U6475 ( .A0N(Add_result[52]), .A1N(n4693), .B0(n5462), .Y(n527)
);
INVX3TS U6476 ( .A(n5467), .Y(n5466) );
AO22XLTS U6477 ( .A0(Sgf_normalized_result[0]), .A1(n5466), .B0(
final_result_ieee[0]), .B1(n5465), .Y(n351) );
AO22XLTS U6478 ( .A0(Sgf_normalized_result[1]), .A1(n5466), .B0(
final_result_ieee[1]), .B1(n5468), .Y(n350) );
AO22XLTS U6479 ( .A0(Sgf_normalized_result[2]), .A1(n5466), .B0(
final_result_ieee[2]), .B1(n5468), .Y(n349) );
AO22XLTS U6480 ( .A0(Sgf_normalized_result[3]), .A1(n5466), .B0(
final_result_ieee[3]), .B1(n5470), .Y(n348) );
AO22XLTS U6481 ( .A0(Sgf_normalized_result[4]), .A1(n5466), .B0(
final_result_ieee[4]), .B1(n5468), .Y(n347) );
AO22XLTS U6482 ( .A0(Sgf_normalized_result[5]), .A1(n5466), .B0(
final_result_ieee[5]), .B1(n5468), .Y(n346) );
AO22XLTS U6483 ( .A0(Sgf_normalized_result[6]), .A1(n5466), .B0(
final_result_ieee[6]), .B1(n5470), .Y(n345) );
AO22XLTS U6484 ( .A0(Sgf_normalized_result[7]), .A1(n5466), .B0(
final_result_ieee[7]), .B1(n5468), .Y(n344) );
AO22XLTS U6485 ( .A0(Sgf_normalized_result[8]), .A1(n5466), .B0(
final_result_ieee[8]), .B1(n5470), .Y(n343) );
AO22XLTS U6486 ( .A0(Sgf_normalized_result[9]), .A1(n5466), .B0(
final_result_ieee[9]), .B1(n5468), .Y(n342) );
AO22XLTS U6487 ( .A0(Sgf_normalized_result[10]), .A1(n5466), .B0(
final_result_ieee[10]), .B1(n5470), .Y(n341) );
AO22XLTS U6488 ( .A0(Sgf_normalized_result[11]), .A1(n5466), .B0(
final_result_ieee[11]), .B1(n5465), .Y(n340) );
AO22XLTS U6489 ( .A0(Sgf_normalized_result[12]), .A1(n5466), .B0(
final_result_ieee[12]), .B1(n5470), .Y(n339) );
CLKINVX6TS U6490 ( .A(n5467), .Y(n5469) );
AO22XLTS U6491 ( .A0(Sgf_normalized_result[13]), .A1(n5469), .B0(
final_result_ieee[13]), .B1(n5468), .Y(n338) );
AO22XLTS U6492 ( .A0(Sgf_normalized_result[14]), .A1(n5469), .B0(
final_result_ieee[14]), .B1(n5468), .Y(n337) );
AO22XLTS U6493 ( .A0(Sgf_normalized_result[15]), .A1(n5469), .B0(
final_result_ieee[15]), .B1(n5468), .Y(n336) );
AO22XLTS U6494 ( .A0(Sgf_normalized_result[16]), .A1(n5469), .B0(
final_result_ieee[16]), .B1(n5468), .Y(n335) );
AO22XLTS U6495 ( .A0(Sgf_normalized_result[17]), .A1(n5469), .B0(
final_result_ieee[17]), .B1(n5468), .Y(n334) );
AO22XLTS U6496 ( .A0(Sgf_normalized_result[18]), .A1(n5469), .B0(
final_result_ieee[18]), .B1(n5468), .Y(n333) );
AO22XLTS U6497 ( .A0(Sgf_normalized_result[19]), .A1(n5469), .B0(
final_result_ieee[19]), .B1(n5468), .Y(n332) );
AO22XLTS U6498 ( .A0(Sgf_normalized_result[20]), .A1(n5469), .B0(
final_result_ieee[20]), .B1(n5468), .Y(n331) );
AO22XLTS U6499 ( .A0(Sgf_normalized_result[21]), .A1(n5469), .B0(
final_result_ieee[21]), .B1(n5468), .Y(n330) );
AO22XLTS U6500 ( .A0(Sgf_normalized_result[22]), .A1(n5469), .B0(
final_result_ieee[22]), .B1(n5468), .Y(n329) );
AO22XLTS U6501 ( .A0(Sgf_normalized_result[23]), .A1(n5469), .B0(
final_result_ieee[23]), .B1(n5468), .Y(n328) );
AO22XLTS U6502 ( .A0(Sgf_normalized_result[24]), .A1(n5469), .B0(
final_result_ieee[24]), .B1(n5468), .Y(n327) );
AO22XLTS U6503 ( .A0(Sgf_normalized_result[25]), .A1(n5469), .B0(
final_result_ieee[25]), .B1(n5468), .Y(n326) );
CLKINVX6TS U6504 ( .A(n5467), .Y(n5471) );
AO22XLTS U6505 ( .A0(Sgf_normalized_result[26]), .A1(n5471), .B0(
final_result_ieee[26]), .B1(n5468), .Y(n325) );
AO22XLTS U6506 ( .A0(Sgf_normalized_result[27]), .A1(n5469), .B0(
final_result_ieee[27]), .B1(n5470), .Y(n324) );
AO22XLTS U6507 ( .A0(Sgf_normalized_result[28]), .A1(n5471), .B0(
final_result_ieee[28]), .B1(n5470), .Y(n323) );
AO22XLTS U6508 ( .A0(Sgf_normalized_result[29]), .A1(n5469), .B0(
final_result_ieee[29]), .B1(n5470), .Y(n322) );
AO22XLTS U6509 ( .A0(Sgf_normalized_result[30]), .A1(n5471), .B0(
final_result_ieee[30]), .B1(n5470), .Y(n321) );
AO22XLTS U6510 ( .A0(Sgf_normalized_result[31]), .A1(n5469), .B0(
final_result_ieee[31]), .B1(n5470), .Y(n320) );
AO22XLTS U6511 ( .A0(Sgf_normalized_result[32]), .A1(n5471), .B0(
final_result_ieee[32]), .B1(n5470), .Y(n319) );
AO22XLTS U6512 ( .A0(Sgf_normalized_result[33]), .A1(n5469), .B0(
final_result_ieee[33]), .B1(n5470), .Y(n318) );
AO22XLTS U6513 ( .A0(Sgf_normalized_result[34]), .A1(n5471), .B0(
final_result_ieee[34]), .B1(n5470), .Y(n317) );
AO22XLTS U6514 ( .A0(Sgf_normalized_result[35]), .A1(n5469), .B0(
final_result_ieee[35]), .B1(n5470), .Y(n316) );
AO22XLTS U6515 ( .A0(Sgf_normalized_result[36]), .A1(n5471), .B0(
final_result_ieee[36]), .B1(n5470), .Y(n315) );
AO22XLTS U6516 ( .A0(Sgf_normalized_result[37]), .A1(n5469), .B0(
final_result_ieee[37]), .B1(n5470), .Y(n314) );
AO22XLTS U6517 ( .A0(Sgf_normalized_result[38]), .A1(n5471), .B0(
final_result_ieee[38]), .B1(n5470), .Y(n313) );
AO22XLTS U6518 ( .A0(Sgf_normalized_result[39]), .A1(n5471), .B0(
final_result_ieee[39]), .B1(n5470), .Y(n312) );
AO22XLTS U6519 ( .A0(Sgf_normalized_result[40]), .A1(n5471), .B0(
final_result_ieee[40]), .B1(n5470), .Y(n311) );
AO22XLTS U6520 ( .A0(Sgf_normalized_result[41]), .A1(n5471), .B0(
final_result_ieee[41]), .B1(n5465), .Y(n310) );
AO22XLTS U6521 ( .A0(Sgf_normalized_result[42]), .A1(n5471), .B0(
final_result_ieee[42]), .B1(n5468), .Y(n309) );
AO22XLTS U6522 ( .A0(Sgf_normalized_result[43]), .A1(n5471), .B0(
final_result_ieee[43]), .B1(n5465), .Y(n308) );
AO22XLTS U6523 ( .A0(Sgf_normalized_result[44]), .A1(n5471), .B0(
final_result_ieee[44]), .B1(n5468), .Y(n307) );
AO22XLTS U6524 ( .A0(Sgf_normalized_result[45]), .A1(n5471), .B0(
final_result_ieee[45]), .B1(n5465), .Y(n306) );
AO22XLTS U6525 ( .A0(Sgf_normalized_result[46]), .A1(n5471), .B0(
final_result_ieee[46]), .B1(n5468), .Y(n305) );
AO22XLTS U6526 ( .A0(Sgf_normalized_result[47]), .A1(n5471), .B0(
final_result_ieee[47]), .B1(n5465), .Y(n304) );
AO22XLTS U6527 ( .A0(Sgf_normalized_result[48]), .A1(n5471), .B0(
final_result_ieee[48]), .B1(n5468), .Y(n303) );
AO22XLTS U6528 ( .A0(Sgf_normalized_result[49]), .A1(n5471), .B0(
final_result_ieee[49]), .B1(n5465), .Y(n302) );
AO22XLTS U6529 ( .A0(Sgf_normalized_result[50]), .A1(n5471), .B0(
final_result_ieee[50]), .B1(n5468), .Y(n301) );
AO22XLTS U6530 ( .A0(Sgf_normalized_result[51]), .A1(n5471), .B0(
final_result_ieee[51]), .B1(n5465), .Y(n300) );
OA22X1TS U6531 ( .A0(n5472), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n5467), .Y(n299) );
OA22X1TS U6532 ( .A0(n5472), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n5467), .Y(n298) );
OA22X1TS U6533 ( .A0(n5472), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n5467), .Y(n297) );
OA22X1TS U6534 ( .A0(n5472), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n5467), .Y(n296) );
OA22X1TS U6535 ( .A0(n5472), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n5467), .Y(n295) );
OA22X1TS U6536 ( .A0(n5472), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n5467), .Y(n294) );
OA22X1TS U6537 ( .A0(n5472), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n5467), .Y(n293) );
OA22X1TS U6538 ( .A0(n5472), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n5467), .Y(n292) );
OA22X1TS U6539 ( .A0(n5472), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n5467), .Y(n291) );
OA22X1TS U6540 ( .A0(n5472), .A1(final_result_ieee[61]), .B0(
exp_oper_result[9]), .B1(n5467), .Y(n290) );
OA22X1TS U6541 ( .A0(n5472), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n5467), .Y(n289) );
CMPR42X2TS U6542 ( .A(DP_OP_168J30_122_4811_n800), .B(
DP_OP_168J30_122_4811_n1975), .C(DP_OP_168J30_122_4811_n598), .D(
DP_OP_168J30_122_4811_n1024), .ICI(DP_OP_168J30_122_4811_n599), .S(
DP_OP_168J30_122_4811_n586), .ICO(DP_OP_168J30_122_4811_n584), .CO(
DP_OP_168J30_122_4811_n585) );
CMPR42X1TS U6543 ( .A(DP_OP_168J30_122_4811_n1181), .B(
DP_OP_168J30_122_4811_n440), .C(DP_OP_168J30_122_4811_n426), .D(
DP_OP_168J30_122_4811_n436), .ICI(DP_OP_168J30_122_4811_n437), .S(
DP_OP_168J30_122_4811_n423), .ICO(DP_OP_168J30_122_4811_n421), .CO(
DP_OP_168J30_122_4811_n422) );
CMPR42X1TS U6544 ( .A(DP_OP_168J30_122_4811_n380), .B(
DP_OP_168J30_122_4811_n1962), .C(DP_OP_168J30_122_4811_n389), .D(
Sgf_operation_ODD1_Q_left[35]), .ICI(DP_OP_168J30_122_4811_n786), .S(
DP_OP_168J30_122_4811_n377), .ICO(DP_OP_168J30_122_4811_n375), .CO(
DP_OP_168J30_122_4811_n376) );
CMPR42X1TS U6545 ( .A(DP_OP_168J30_122_4811_n308), .B(
DP_OP_168J30_122_4811_n314), .C(DP_OP_168J30_122_4811_n1956), .D(
Sgf_operation_ODD1_Q_left[41]), .ICI(DP_OP_168J30_122_4811_n780), .S(
DP_OP_168J30_122_4811_n305), .ICO(DP_OP_168J30_122_4811_n303), .CO(
DP_OP_168J30_122_4811_n304) );
CMPR42X1TS U6546 ( .A(DP_OP_168J30_122_4811_n1216), .B(
DP_OP_168J30_122_4811_n540), .C(DP_OP_168J30_122_4811_n544), .D(
DP_OP_168J30_122_4811_n992), .ICI(DP_OP_168J30_122_4811_n529), .S(
DP_OP_168J30_122_4811_n526), .ICO(DP_OP_168J30_122_4811_n524), .CO(
DP_OP_168J30_122_4811_n525) );
CMPR42X1TS U6547 ( .A(DP_OP_168J30_122_4811_n2888), .B(
DP_OP_168J30_122_4811_n2369), .C(DP_OP_168J30_122_4811_n2376), .D(
DP_OP_168J30_122_4811_n2915), .ICI(DP_OP_168J30_122_4811_n2942), .S(
DP_OP_168J30_122_4811_n2366), .ICO(DP_OP_168J30_122_4811_n2364), .CO(
DP_OP_168J30_122_4811_n2365) );
CMPR42X1TS U6548 ( .A(DP_OP_168J30_122_4811_n2357), .B(
DP_OP_168J30_122_4811_n2368), .C(DP_OP_168J30_122_4811_n2887), .D(
DP_OP_168J30_122_4811_n2364), .ICI(DP_OP_168J30_122_4811_n2914), .S(
DP_OP_168J30_122_4811_n2354), .ICO(DP_OP_168J30_122_4811_n2352), .CO(
DP_OP_168J30_122_4811_n2353) );
CMPR42X1TS U6549 ( .A(DP_OP_168J30_122_4811_n2432), .B(
DP_OP_168J30_122_4811_n2866), .C(DP_OP_168J30_122_4811_n2440), .D(
DP_OP_168J30_122_4811_n2893), .ICI(DP_OP_168J30_122_4811_n2441), .S(
DP_OP_168J30_122_4811_n2429), .ICO(DP_OP_168J30_122_4811_n2427), .CO(
DP_OP_168J30_122_4811_n2428) );
CMPR42X1TS U6550 ( .A(DP_OP_168J30_122_4811_n2420), .B(
DP_OP_168J30_122_4811_n2865), .C(DP_OP_168J30_122_4811_n2427), .D(
DP_OP_168J30_122_4811_n2892), .ICI(DP_OP_168J30_122_4811_n2428), .S(
DP_OP_168J30_122_4811_n2417), .ICO(DP_OP_168J30_122_4811_n2415), .CO(
DP_OP_168J30_122_4811_n2416) );
CMPR42X1TS U6551 ( .A(DP_OP_168J30_122_4811_n330), .B(
DP_OP_168J30_122_4811_n337), .C(DP_OP_168J30_122_4811_n1958), .D(
DP_OP_168J30_122_4811_n782), .ICI(n942), .S(DP_OP_168J30_122_4811_n327), .ICO(DP_OP_168J30_122_4811_n325), .CO(DP_OP_168J30_122_4811_n326) );
CMPR42X1TS U6552 ( .A(DP_OP_168J30_122_4811_n319), .B(
DP_OP_168J30_122_4811_n329), .C(DP_OP_168J30_122_4811_n325), .D(
Sgf_operation_ODD1_Q_left[40]), .ICI(DP_OP_168J30_122_4811_n781), .S(
DP_OP_168J30_122_4811_n316), .ICO(DP_OP_168J30_122_4811_n314), .CO(
DP_OP_168J30_122_4811_n315) );
CMPR42X1TS U6553 ( .A(DP_OP_168J30_122_4811_n1965), .B(
DP_OP_168J30_122_4811_n423), .C(DP_OP_168J30_122_4811_n433), .D(
Sgf_operation_ODD1_Q_left[32]), .ICI(DP_OP_168J30_122_4811_n789), .S(
DP_OP_168J30_122_4811_n420), .ICO(DP_OP_168J30_122_4811_n418), .CO(
DP_OP_168J30_122_4811_n419) );
CMPR42X1TS U6554 ( .A(DP_OP_168J30_122_4811_n424), .B(
DP_OP_168J30_122_4811_n425), .C(DP_OP_168J30_122_4811_n411), .D(
DP_OP_168J30_122_4811_n421), .ICI(DP_OP_168J30_122_4811_n422), .S(
DP_OP_168J30_122_4811_n408), .ICO(DP_OP_168J30_122_4811_n406), .CO(
DP_OP_168J30_122_4811_n407) );
CMPR42X1TS U6555 ( .A(DP_OP_168J30_122_4811_n1964), .B(
DP_OP_168J30_122_4811_n408), .C(DP_OP_168J30_122_4811_n418), .D(
DP_OP_168J30_122_4811_n788), .ICI(n5212), .S(
DP_OP_168J30_122_4811_n405), .ICO(DP_OP_168J30_122_4811_n403), .CO(
DP_OP_168J30_122_4811_n404) );
CMPR42X1TS U6556 ( .A(DP_OP_168J30_122_4811_n288), .B(
DP_OP_168J30_122_4811_n296), .C(DP_OP_168J30_122_4811_n292), .D(
Sgf_operation_ODD1_Q_left[43]), .ICI(DP_OP_168J30_122_4811_n778), .S(
DP_OP_168J30_122_4811_n285), .ICO(DP_OP_168J30_122_4811_n283), .CO(
DP_OP_168J30_122_4811_n284) );
CMPR42X1TS U6557 ( .A(DP_OP_168J30_122_4811_n354), .B(
DP_OP_168J30_122_4811_n365), .C(DP_OP_168J30_122_4811_n361), .D(
Sgf_operation_ODD1_Q_left[37]), .ICI(DP_OP_168J30_122_4811_n784), .S(
DP_OP_168J30_122_4811_n351), .ICO(DP_OP_168J30_122_4811_n349), .CO(
DP_OP_168J30_122_4811_n350) );
CMPR42X1TS U6558 ( .A(DP_OP_168J30_122_4811_n2404), .B(
DP_OP_168J30_122_4811_n2393), .C(DP_OP_168J30_122_4811_n2400), .D(
DP_OP_168J30_122_4811_n2917), .ICI(DP_OP_168J30_122_4811_n2944), .S(
DP_OP_168J30_122_4811_n2390), .ICO(DP_OP_168J30_122_4811_n2388), .CO(
DP_OP_168J30_122_4811_n2389) );
CMPR42X1TS U6559 ( .A(DP_OP_168J30_122_4811_n2889), .B(
DP_OP_168J30_122_4811_n2381), .C(DP_OP_168J30_122_4811_n2388), .D(
DP_OP_168J30_122_4811_n2916), .ICI(DP_OP_168J30_122_4811_n2389), .S(
DP_OP_168J30_122_4811_n2378), .ICO(DP_OP_168J30_122_4811_n2376), .CO(
DP_OP_168J30_122_4811_n2377) );
CMPR42X1TS U6560 ( .A(DP_OP_168J30_122_4811_n2445), .B(
DP_OP_168J30_122_4811_n2867), .C(DP_OP_168J30_122_4811_n2453), .D(
DP_OP_168J30_122_4811_n2894), .ICI(DP_OP_168J30_122_4811_n2454), .S(
DP_OP_168J30_122_4811_n2442), .ICO(DP_OP_168J30_122_4811_n2440), .CO(
DP_OP_168J30_122_4811_n2441) );
CMPR42X1TS U6561 ( .A(DP_OP_168J30_122_4811_n2405), .B(
DP_OP_168J30_122_4811_n2412), .C(DP_OP_168J30_122_4811_n2918), .D(
DP_OP_168J30_122_4811_n2945), .ICI(DP_OP_168J30_122_4811_n2413), .S(
DP_OP_168J30_122_4811_n2402), .ICO(DP_OP_168J30_122_4811_n2400), .CO(
DP_OP_168J30_122_4811_n2401) );
CMPR42X1TS U6562 ( .A(DP_OP_168J30_122_4811_n2834), .B(
DP_OP_168J30_122_4811_n2372), .C(DP_OP_168J30_122_4811_n2379), .D(
DP_OP_168J30_122_4811_n2861), .ICI(DP_OP_168J30_122_4811_n2380), .S(
DP_OP_168J30_122_4811_n2369), .ICO(DP_OP_168J30_122_4811_n2367), .CO(
DP_OP_168J30_122_4811_n2368) );
CMPR42X1TS U6563 ( .A(DP_OP_168J30_122_4811_n2835), .B(
DP_OP_168J30_122_4811_n2384), .C(DP_OP_168J30_122_4811_n2391), .D(
DP_OP_168J30_122_4811_n2862), .ICI(DP_OP_168J30_122_4811_n2392), .S(
DP_OP_168J30_122_4811_n2381), .ICO(DP_OP_168J30_122_4811_n2379), .CO(
DP_OP_168J30_122_4811_n2380) );
CMPR42X1TS U6564 ( .A(DP_OP_168J30_122_4811_n2811), .B(
DP_OP_168J30_122_4811_n2423), .C(DP_OP_168J30_122_4811_n2430), .D(
DP_OP_168J30_122_4811_n2838), .ICI(DP_OP_168J30_122_4811_n2431), .S(
DP_OP_168J30_122_4811_n2420), .ICO(DP_OP_168J30_122_4811_n2418), .CO(
DP_OP_168J30_122_4811_n2419) );
CMPR42X1TS U6565 ( .A(DP_OP_168J30_122_4811_n2810), .B(
DP_OP_168J30_122_4811_n2411), .C(DP_OP_168J30_122_4811_n2418), .D(
DP_OP_168J30_122_4811_n2837), .ICI(DP_OP_168J30_122_4811_n2419), .S(
DP_OP_168J30_122_4811_n2408), .ICO(DP_OP_168J30_122_4811_n2406), .CO(
DP_OP_168J30_122_4811_n2407) );
CMPR42X1TS U6566 ( .A(DP_OP_168J30_122_4811_n226), .B(
DP_OP_168J30_122_4811_n222), .C(DP_OP_168J30_122_4811_n227), .D(
DP_OP_168J30_122_4811_n223), .ICI(DP_OP_168J30_122_4811_n769), .S(
DP_OP_168J30_122_4811_n220), .ICO(DP_OP_168J30_122_4811_n218), .CO(
DP_OP_168J30_122_4811_n219) );
CMPR42X1TS U6567 ( .A(DP_OP_168J30_122_4811_n4514), .B(
DP_OP_168J30_122_4811_n4171), .C(DP_OP_168J30_122_4811_n4174), .D(
DP_OP_168J30_122_4811_n4540), .ICI(DP_OP_168J30_122_4811_n4175), .S(
DP_OP_168J30_122_4811_n4169), .ICO(DP_OP_168J30_122_4811_n4167), .CO(
DP_OP_168J30_122_4811_n4168) );
CMPR42X1TS U6568 ( .A(DP_OP_168J30_122_4811_n2479), .B(
DP_OP_168J30_122_4811_n2924), .C(DP_OP_168J30_122_4811_n2485), .D(
DP_OP_168J30_122_4811_n2951), .ICI(DP_OP_168J30_122_4811_n2486), .S(
DP_OP_168J30_122_4811_n2476), .ICO(DP_OP_168J30_122_4811_n2474), .CO(
DP_OP_168J30_122_4811_n2475) );
CMPR42X1TS U6569 ( .A(DP_OP_168J30_122_4811_n2813), .B(
DP_OP_168J30_122_4811_n2447), .C(DP_OP_168J30_122_4811_n2456), .D(
DP_OP_168J30_122_4811_n2840), .ICI(DP_OP_168J30_122_4811_n2457), .S(
DP_OP_168J30_122_4811_n2445), .ICO(DP_OP_168J30_122_4811_n2443), .CO(
DP_OP_168J30_122_4811_n2444) );
CMPR42X1TS U6570 ( .A(DP_OP_168J30_122_4811_n2812), .B(
DP_OP_168J30_122_4811_n2434), .C(DP_OP_168J30_122_4811_n2443), .D(
DP_OP_168J30_122_4811_n2839), .ICI(DP_OP_168J30_122_4811_n2444), .S(
DP_OP_168J30_122_4811_n2432), .ICO(DP_OP_168J30_122_4811_n2430), .CO(
DP_OP_168J30_122_4811_n2431) );
CMPR42X1TS U6571 ( .A(DP_OP_168J30_122_4811_n2814), .B(
DP_OP_168J30_122_4811_n2460), .C(DP_OP_168J30_122_4811_n2469), .D(
DP_OP_168J30_122_4811_n2841), .ICI(DP_OP_168J30_122_4811_n2470), .S(
DP_OP_168J30_122_4811_n2458), .ICO(DP_OP_168J30_122_4811_n2456), .CO(
DP_OP_168J30_122_4811_n2457) );
CMPR42X1TS U6572 ( .A(DP_OP_168J30_122_4811_n2828), .B(
DP_OP_168J30_122_4811_n2299), .C(DP_OP_168J30_122_4811_n2305), .D(
DP_OP_168J30_122_4811_n2855), .ICI(DP_OP_168J30_122_4811_n2882), .S(
DP_OP_168J30_122_4811_n2296), .ICO(DP_OP_168J30_122_4811_n2294), .CO(
DP_OP_168J30_122_4811_n2295) );
CMPR42X1TS U6573 ( .A(DP_OP_168J30_122_4811_n2290), .B(
DP_OP_168J30_122_4811_n2298), .C(DP_OP_168J30_122_4811_n2827), .D(
DP_OP_168J30_122_4811_n2294), .ICI(DP_OP_168J30_122_4811_n2854), .S(
DP_OP_168J30_122_4811_n2287), .ICO(DP_OP_168J30_122_4811_n2285), .CO(
DP_OP_168J30_122_4811_n2286) );
CMPR42X1TS U6574 ( .A(DP_OP_168J30_122_4811_n2780), .B(
DP_OP_168J30_122_4811_n2375), .C(DP_OP_168J30_122_4811_n2382), .D(
DP_OP_168J30_122_4811_n2807), .ICI(DP_OP_168J30_122_4811_n2383), .S(
DP_OP_168J30_122_4811_n2372), .ICO(DP_OP_168J30_122_4811_n2370), .CO(
DP_OP_168J30_122_4811_n2371) );
CMPR42X1TS U6575 ( .A(DP_OP_168J30_122_4811_n2363), .B(
DP_OP_168J30_122_4811_n2374), .C(DP_OP_168J30_122_4811_n2779), .D(
DP_OP_168J30_122_4811_n2370), .ICI(DP_OP_168J30_122_4811_n2806), .S(
DP_OP_168J30_122_4811_n2360), .ICO(DP_OP_168J30_122_4811_n2358), .CO(
DP_OP_168J30_122_4811_n2359) );
CMPR42X1TS U6576 ( .A(DP_OP_168J30_122_4811_n2360), .B(
DP_OP_168J30_122_4811_n2371), .C(DP_OP_168J30_122_4811_n2833), .D(
DP_OP_168J30_122_4811_n2367), .ICI(DP_OP_168J30_122_4811_n2860), .S(
DP_OP_168J30_122_4811_n2357), .ICO(DP_OP_168J30_122_4811_n2355), .CO(
DP_OP_168J30_122_4811_n2356) );
CMPR42X1TS U6577 ( .A(DP_OP_168J30_122_4811_n2490), .B(
DP_OP_168J30_122_4811_n2925), .C(DP_OP_168J30_122_4811_n2496), .D(
DP_OP_168J30_122_4811_n2952), .ICI(DP_OP_168J30_122_4811_n2497), .S(
DP_OP_168J30_122_4811_n2487), .ICO(DP_OP_168J30_122_4811_n2485), .CO(
DP_OP_168J30_122_4811_n2486) );
CMPR42X1TS U6578 ( .A(n881), .B(DP_OP_168J30_122_4811_n3886), .C(
DP_OP_168J30_122_4811_n4327), .D(DP_OP_168J30_122_4811_n3883), .ICI(
DP_OP_168J30_122_4811_n3884), .S(DP_OP_168J30_122_4811_n3882), .ICO(
DP_OP_168J30_122_4811_n3876), .CO(DP_OP_168J30_122_4811_n3881) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk40.tcl_KOA_1STAGE_syn.sdf");
endmodule
|
`timescale 1ns / 1ps
// @module
// timing clock alarm
// @input
// clk_dst/clk_group: multiple clock source
// timing_clock_switch: switch for enabling to change timing time
// timing_clock_disable: shutdown timing_clock manully
// power: electric power
// enable: enable switch only for real clock
// reset: reset switch
// add_time/sub_time: chaning time switch
// sec/min/hour: time data of real clock
// timing_anodes/timing_cnodes: port for displaying time
// timing_clock_alarm: clock alarm when timing clock arrive
module timing_clock
#(parameter WIDTH = 32, CLK_CH = 25, SEC_RANGE = 60, MIN_RANGE = 60, HOUR_RANGE = 24, LEN = 30, NUM = 5)
(
input clk_dst,
input [(WIDTH-1):0] clk_group,
input timing_clock_switch,
input timing_clock_disable,
input power,
input enable,
input reset,
input [2:0] add_time,
input [2:0] sub_time,
input [(WIDTH-1):0] sec,
input [(WIDTH-1):0] min,
input [(WIDTH-1):0] hour,
output [7:0] timing_anodes,
output [7:0] timing_cnodes,
output [(NUM-1):0] timing_clock_alarm
);
// for timer invoking in this module
wire [(WIDTH-1):0] timing_sec, timing_min, timing_hour;
wire timing_sig_sec, timing_sig_min, timing_sig_hour;
// for ring module invoking in this module
reg [(WIDTH-1):0] timing_count;
reg timing_clock_alarm_sig;
initial begin
timing_count <= 0;
timing_clock_alarm_sig <= 0;
end
/* start of cloning a clock that can't run */
timer #(.WIDTH(WIDTH), .RANGE(SEC_RANGE)) TIMING_SEC_TIMER (
// && !timing_clock_switch : when changing real clock, lock timing clock
.clk_normal(clk_dst && timing_clock_switch),
.clk_change_time(clk_group[CLK_CH] && timing_clock_switch),
.power(power),
.enable(0),
.reset(reset),
.add_time(add_time[0]),
.sub_time(sub_time[0]),
.count(timing_sec),
.sig_end(timing_sig_sec)
);
timer #(.WIDTH(WIDTH), .RANGE(MIN_RANGE)) TIMING_MIN_TIMER (
.clk_normal(timing_sig_sec && timing_clock_switch),
.clk_change_time(clk_group[CLK_CH] && timing_clock_switch),
.power(power),
.enable(0),
.reset(reset),
.add_time(add_time[1]),
.sub_time(sub_time[1]),
.count(timing_min),
.sig_end(timing_sig_min)
);
timer #(.WIDTH(WIDTH), .RANGE(HOUR_RANGE)) TIMING_HOUR_TIMER (
.clk_normal(timing_sig_min && timing_clock_switch),
.clk_change_time(clk_group[CLK_CH] && timing_clock_switch),
.power(power),
.enable(0),
.reset(reset),
.add_time(add_time[2]),
.sub_time(sub_time[2]),
.count(timing_hour),
.sig_end(timing_sig_hour)
);
time_displayer TIMING_SEG_SEVEN (
.clk_src(clk_group[15]),
.sec_data(timing_sec),
.min_data(timing_min),
.hour_data(timing_hour),
// when power off, light off
.anodes(timing_anodes),
.cnodes(timing_cnodes)
);
/* end of cloning a clock that can't run */
// judge whether tming clock arrive or not
always @(posedge clk_group[CLK_CH]) begin
// shutdown timing clock manually
if (timing_clock_disable) begin
timing_clock_alarm_sig = 0;
end
// arrive target time
else if (sec == timing_sec
&& min == timing_min
&& hour == timing_hour
&& enable && !timing_clock_switch) begin
timing_clock_alarm_sig = 1;
end else begin
timing_clock_alarm_sig = 0;
end
end
// timing clock alarm
flow_led #(LEN, NUM) TIMING_RING (
.power(power && !timing_clock_disable),
.sig_ring(timing_clock_alarm_sig),
.sig_step(clk_dst),
.alarm_light(timing_clock_alarm)
);
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
apply ST_Plus2.
apply ST_Plus2.
apply ST_PlusConstConst.
Qed.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst". reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2. rewrite H2. reflexivity.
Case "ST_Plus2".
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst".
reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2.
rewrite H2.
reflexivity.
inversion H1; subst.
inversion Hy1.
Case "ST_Plus2".
inversion H; subst.
inversion H3.
apply IHHy1 in H4.
rewrite H4.
reflexivity.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
exists (P (P (C 0) (C 0)) (C 0)).
split.
Case "left".
apply v_funny.
Case "right".
unfold normal_form.
unfold not.
intros.
apply H.
exists (P (C 0) (C 0)).
apply ST_Plus1.
apply ST_PlusConstConst.
Qed.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
exists (C 0).
split.
Case "left".
apply v_const.
Case "right".
unfold normal_form.
unfold not.
intros.
apply H.
exists (P (C 0) (C 0)).
apply ST_Funny.
Qed.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
exists (P (C 0) (P (C 0) (C 0))).
split.
Case "left".
intros H.
inversion H.
Case "right".
unfold normal_form.
intros H.
inversion H.
inversion H0.
inversion H4.
Qed.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* Not provable *)
Example bool_step_example1 : ~ bool_step_prop1.
Proof.
unfold bool_step_prop1.
intros H.
inversion H.
Qed.
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* Not provable *)
Example bool_step_example2 : ~ bool_step_prop2.
Proof.
unfold bool_step_prop2.
intros H.
inversion H.
Qed.
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* Provable *)
Example bool_step_example3 : bool_step_prop3.
Proof.
apply ST_If.
apply ST_IfTrue.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
induction t; try (left; constructor).
right.
inversion IHt1.
inversion H.
exists t2.
apply ST_IfTrue.
exists t3.
apply ST_IfFalse.
inversion H as [t1'].
exists (tif t1' t2 t3).
apply ST_If.
apply H0.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion); try reflexivity.
apply IHHy1 in H3.
rewrite H3.
reflexivity.
Qed.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
| ST_ShortCircuit : forall t1 t2,
tif t1 t2 t2 ==> t2
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
apply ST_ShortCircuit.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* No, [ST_ShortCircuit] gives other choices. *)
Theorem step_deterministic_false : ~ deterministic step.
Proof.
unfold deterministic.
intros H.
assert (tif ttrue ttrue ttrue = ttrue).
eapply H.
apply ST_If.
apply ST_IfTrue with (t2:=ttrue).
apply ST_ShortCircuit.
inversion H0.
Qed.
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* Yes, only [ttrue] and [tfalse] cannot step *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
induction t; try (left; constructor).
right.
inversion IHt1.
inversion H.
exists t2.
apply ST_IfTrue.
exists t3.
apply ST_IfFalse.
inversion H as [t1'].
exists (tif t1' t2 t3).
apply ST_If.
apply H0.
Qed.
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* Yes, remove [ST_IfTrue] will make [tif ttrue ttrue tfalse] cannot step. *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
eapply multi_step.
apply ST_Plus2.
apply v_const.
apply ST_Plus2.
apply v_const.
apply ST_PlusConstConst.
eapply multi_step.
apply ST_Plus2.
apply v_const.
apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
multi_cases (induction P11) Case.
Case "multi_refl".
intros.
inversion P21.
reflexivity.
exfalso.
apply P12.
exists y.
apply H.
Case "multi_step".
intros.
apply IHP11.
apply P12.
inversion P21; subst.
exfalso.
apply P22.
exists y.
apply H.
assert (x ==> y -> x ==> y0 -> y = y0).
apply step_deterministic.
assert (y = y0).
apply H2.
apply H.
apply H0.
rewrite H3.
apply H1.
apply P22.
Qed.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
intros.
multi_cases (induction H0) Case.
Case "multi_refl".
apply multi_refl.
Case "multi_step".
eapply multi_step.
apply ST_Plus2.
apply H.
apply H0.
apply IHmulti.
Qed.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
intros.
eval_cases (induction H) Case.
Case "E_Const".
apply multi_refl.
Case "E_Plus".
eapply multi_trans.
apply multistep_congr_1.
apply IHeval1.
eapply multi_trans.
apply multistep_congr_2.
apply v_const.
apply IHeval2.
eapply multi_step.
apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(*
Induction on [t].
If [t] = [C n], just [multi_refl].
If [t] = [P t1 t2], by induction hypothesis, [t1 ==>* C n1] and [t2 ==>* C n2],
by multistep congruence get [P t1 t2 ==>* P (C n1) (C n2)] and
[P (C n1) (C n2) ==> C (n1 + n2)].
*)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
step_cases (induction Hs) Case; intros.
Case "ST_PlusConstConst".
inversion H; subst.
apply E_Plus; apply E_Const.
Case "ST_Plus1".
inversion H; subst.
apply E_Plus; try (apply IHHs); assumption.
Case "ST_Plus2".
inversion H0; subst.
apply E_Plus; try (apply IHHs); assumption.
Qed.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
intros.
destruct H.
apply nf_is_value in H0.
inversion H0.
exists n.
split.
Case "left".
reflexivity.
Case "right".
multi_cases (induction H) SCase.
SCase "multi_refl".
rewrite <- H1.
apply E_Const.
SCase "multi_step".
eapply step__eval.
apply H.
apply IHmulti.
apply H0.
apply H1.
Qed.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
split.
Case "->".
generalize dependent n.
tm_cases (induction t) SCase; intros.
SCase "C".
simpl in H.
rewrite H.
apply E_Const.
SCase "P".
simpl in H.
rewrite <- H.
apply E_Plus.
apply IHt1.
reflexivity.
apply IHt2.
reflexivity.
Case "<-".
generalize dependent n.
tm_cases (induction t) SCase; intros.
SCase "C".
inversion H; subst.
reflexivity.
SCase "P".
inversion H; subst.
simpl.
apply IHt1 in H2.
apply IHt2 in H4.
rewrite H2.
rewrite H4.
reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* The combined language is deterministic but not strong progress. *)
Theorem step_deterministic : deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion); try reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2.
rewrite H2.
reflexivity.
inversion H1; subst; inversion Hy1.
Case "ST_Plus2".
inversion H; subst; inversion H3.
apply IHHy1 in H4.
rewrite H4.
reflexivity.
Case "ST_If".
apply IHHy1 in H3.
rewrite H3.
reflexivity.
Qed.
Theorem strong_progress_false :
exists t, ~ value t /\ normal_form step t.
Proof.
exists (tif (C 0) ttrue tfalse).
split.
Case "left".
intros H.
inversion H.
Case "right".
intros H.
inversion H.
inversion H0.
inversion H5.
Qed.
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
intros.
destruct H.
eapply multi_step.
apply CS_Par2.
apply CS_While.
eapply multi_step.
apply CS_Par2.
apply CS_IfStep.
apply BS_Eq1.
apply AS_Id.
eapply multi_step.
apply CS_Par2.
apply CS_IfStep.
apply BS_Eq.
eapply multi_step.
apply CS_Par2.
rewrite H0.
apply CS_IfTrue.
eapply multi_step.
apply CS_Par2.
apply CS_SeqStep.
apply CS_AssStep.
apply AS_Plus1.
apply AS_Id.
eapply multi_step.
apply CS_Par2.
apply CS_SeqStep.
apply CS_AssStep.
apply AS_Plus.
eapply multi_step.
apply CS_Par2.
apply CS_SeqStep.
apply CS_Ass.
eapply multi_step.
apply CS_Par2.
apply CS_SeqFinish.
fold par_loop.
rewrite H.
rewrite <- plus_n_Sm.
rewrite plus_0_r.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
intros.
destruct H.
induction n as [| n'].
Case "n = 0".
exists st.
repeat split.
apply multi_refl.
apply H.
apply H0.
Case "n = S n'".
inversion IHn'; subst.
exists (update x X (S n')).
repeat split.
destruct H1.
eapply multi_trans.
apply H1.
apply par_body_n__Sn.
apply H2.
destruct H1.
destruct H2.
rewrite update_neq.
apply H3.
intros H4.
inversion H4.
Qed.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop := forall a st,
stack_multistep st (s_compile a, []) ([], [aeval st a]).
Lemma stack_step_app : forall p1 p2 st s1 s2 s3,
stack_multistep st (p1, s1) ([], s2) ->
stack_multistep st (p2, s2) ([], s3) ->
stack_multistep st (p1 ++ p2, s1) ([], s3).
Proof.
induction p1 as [| ins p1']; intros; simpl.
Case "p1 = nil".
inversion H; subst.
apply H0.
inversion H1.
Case "p1 = ins :: p1'".
inversion H; subst.
inversion H1; subst; eapply multi_step;
try constructor; eapply IHp1'; try apply H2; try apply H0.
Qed.
Lemma compiler_is_correct_general : forall a st s,
stack_multistep st (s_compile a, s) ([], aeval st a :: s).
Proof.
induction a; intros; simpl;
try (eapply stack_step_app; try apply IHa1);
try (eapply stack_step_app; try apply IHa2);
try (eapply multi_step; constructor).
Qed.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
intros a st.
apply compiler_is_correct_general.
Qed.
(** [] *)
(** $Date: 2014-12-31 15:16:58 -0500 (Wed, 31 Dec 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_PP_BLACKBOX_V
/**
* lpflow_inputisolatch: Latching input isolator with inverted enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_inputisolatch (
Q ,
D ,
SLEEP_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input SLEEP_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISOLATCH_PP_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: jtag_bus.v
// Project: NF2 (NF2 Control Network FPGA)
// Description: NF2/CPCI bus interface.
//
// Provides synchronization logic for CPCI register bus
// including logic to insert/remove from the FIFOs.
//
// Does not implement the register processing logic.
//
// Note: bus_rd_data and bus_rd_data are NOT registers on input
//
///////////////////////////////////////////////////////////////////////////////
module jtag_bus
#(
parameter CPCI_NF2_ADDR_WIDTH = 27,
parameter CPCI_NF2_DATA_WIDTH = 32
)
(
// --- These are sigs to/from pins going to CPCI device
input jtag_rd_wr_L,
input jtag_req,
input [CPCI_NF2_ADDR_WIDTH-1:0] jtag_addr,
input [CPCI_NF2_DATA_WIDTH-1:0] jtag_wr_data,
output wire [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data,
//output wire control_port_read_datavalid,
// --- Internal signals to/from register rd/wr logic
//
output fifo_empty, // functions like a bus_req signal
input fifo_rd_en,
output wire bus_rd_wr_L,
output [CPCI_NF2_ADDR_WIDTH-1:0] bus_addr,
output [CPCI_NF2_DATA_WIDTH-1:0] bus_wr_data,
input wire [CPCI_NF2_DATA_WIDTH-1:0] bus_rd_data,
input bus_rd_vld,
// --- Misc
input reset,
input core_clk
);
// --------------------------------------------------------
// Local registers/wires
// --------------------------------------------------------
// all p2n_* signals are cpci signals registered
reg p2n_rd_wr_L;
reg p2n_req;
reg p2n_req_d1;
reg [CPCI_NF2_ADDR_WIDTH-1:0] p2n_addr;
reg [CPCI_NF2_DATA_WIDTH-1:0] p2n_wr_data;
reg p2n_wr_rdy;
reg p2n_rd_rdy;
reg cpci_wr_rdy_nxt;
reg cpci_rd_rdy_nxt;
reg cpci_wr_rdy;
reg cpci_rd_rdy;
wire p2n_almost_full;
wire p2n_prog_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] n2p_rd_data;
wire n2p_rd_rdy;
// Read/write enables for the N2P fifo
wire n2p_rd_en;
wire n2p_wr_en;
// Full/empty signals for n2p fifo
wire n2p_fifo_empty;
wire n2p_almost_full;
wire [CPCI_NF2_DATA_WIDTH-1:0] cpci_rd_data_nxt;
reg [CPCI_NF2_DATA_WIDTH-1:0] jtag_rd_data_reg;
reg jtag_rd_datavalid_reg;
// -----------------------------------------------------------------
// - Registering of all P2N signals
// -----------------------------------------------------------------
/* We register everything coming in from the pins so that we have a
timing-consistent view of the signals.
Note: the wr_rdy and rd_rdy signals are recorded as we need to be able to
identify whether the other would have recorded the operation as a success
or failure
*/
always @(posedge core_clk) begin
p2n_rd_wr_L <= jtag_rd_wr_L;
p2n_addr <= jtag_addr;
p2n_req <= jtag_req;
p2n_wr_data <= jtag_wr_data;
p2n_wr_rdy <= cpci_wr_rdy;
p2n_rd_rdy <= cpci_rd_rdy;
end
always @(*) begin
if (bus_rd_vld) begin
jtag_rd_data_reg = bus_rd_data;
jtag_rd_datavalid_reg = bus_rd_vld;
end
end
assign jtag_rd_data = jtag_rd_data_reg;
assign control_port_read_datavalid = jtag_rd_datavalid_reg;
/*
-----------------------------------------------------------------
- CPCI -> NF2 requests
-----------------------------------------------------------------
*/
// All requests get funnelled into a 60-bit wide FIFO.
// 60-bits = 32 (data) + 27 (address) + 1 (rd_wr_L)
// Write in new addr/data when req and wr_rdy are high
// In the current design, the CPCI chip PCI clock period is 30ns, the register
// access interface between the CPCI chip and the NetFPGA chip has clock period 16ns,
// the NetFPGA chip internal clock period is 8ns.
// The pkt DMA TX is through the register access interface at this moment (to be
// changed to use the dedicated DMA interface later). So there are a few performance
// requirements:
// 1. When DMA TX is in progress, the register access interface will see register
// write requests back to back on two consecutive clock cycles sometimes.
// 2. The reg_grp and the DMA module must finish acking to DMA TX register write request
// in no more than 3 clock cycles (3 * 8ns = 24ns < 30ns) to prevent the p2n fifo
// from filling up and overflowing. The DMA TX queue full signal to CPCI chip
// is currently indicating whether the cpu queue is full, not whether the pci2net_fifo
// is full.
reg [1:0] p2n_state;
reg [1:0] p2n_state_nxt;
reg p2n_wr_en;
wire p2n_full;
localparam
P2N_IDLE = 2'h 0,
READING = 2'h 1,
P2N_RD_DONE = 2'h 2;
// this state machine runs in the pci-clk domain
always @* begin
// set default values
p2n_wr_en = 1'b0;
p2n_state_nxt = p2n_state;
if (reset)
p2n_state_nxt = P2N_IDLE;
else begin
case (p2n_state)
P2N_IDLE: begin
// Only process the request if the PCI2NET fifo has space for the
// request
if (p2n_req && !p2n_full) begin
p2n_wr_en = 1'b1;
if (p2n_rd_wr_L)
p2n_state_nxt = READING;
end // if
end // P2N_IDLE
READING: begin
// Wait until the result is ready to return
if (p2n_rd_rdy)
p2n_state_nxt = P2N_RD_DONE;
end //READING
P2N_RD_DONE:
// Don't return to idle until the other side deasserts the request
// signal
if ( ! p2n_req )
p2n_state_nxt = P2N_IDLE;
endcase
end
end
always @(posedge core_clk) begin
p2n_state <= p2n_state_nxt;
end
always @*
if (reset) begin
cpci_wr_rdy_nxt = 1'b0;
cpci_rd_rdy_nxt = 1'b0;
end
else begin
cpci_wr_rdy_nxt = !p2n_prog_full;
cpci_rd_rdy_nxt = !fifo_empty;
end
always @(posedge core_clk) begin
cpci_rd_rdy <= cpci_rd_rdy_nxt;
cpci_wr_rdy <= cpci_wr_rdy_nxt;
end
/*
-----------------------------------------------------------------
- NF2 -> CPCI responses
-----------------------------------------------------------------
*/
// Fifo to cross from the PCI clock domain to the core domain
/*
pci2net_16x60 pci2net_fifo (
.din ({p2n_rd_wr_L, p2n_addr, p2n_wr_data}),
.rd_clk (core_clk),
.rd_en (fifo_rd_en),
.rst (reset),
.wr_clk (pci_clk),
.wr_en (p2n_wr_en),
.almost_full (p2n_almost_full),
.prog_full (p2n_prog_full),
.dout ({bus_rd_wr_L, bus_addr, bus_wr_data}),
.empty (fifo_empty),
.full (p2n_full)
);
*/
pci2net_16x60 pci2net_fifo (
.aclr ( reset ),
.clock ( core_clk ),
.data ( {p2n_rd_wr_L, p2n_addr, p2n_wr_data} ),
.rdreq ( fifo_rd_en ),
.wrreq ( p2n_wr_en ),
.almost_empty ( ),
.almost_full ( p2n_prog_full ),
.empty ( fifo_empty ),
.full ( p2n_full ),
.q ( {bus_rd_wr_L, bus_addr, bus_wr_data} ),
.usedw ( )
);
// synthesis translate_on
endmodule // cpci_bus
|
//-----------------------------------------------------------------
// FPGA Audio Project SoC IP
// V0.1
// Ultra-Embedded.com
// Copyright 2011 - 2012
//
// Email: [email protected]
//
// License: LGPL
//
// If you would like a version with a different license for use
// in commercial projects please contact the above email address
// for more details.
//-----------------------------------------------------------------
//
// Copyright (C) 2011 - 2012 Ultra-Embedded.com
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, write to the
// Free Software Foundation, Inc., 59 Temple Place, Suite 330,
// Boston, MA 02111-1307 USA
//-----------------------------------------------------------------
//-----------------------------------------------------------------
// Module
//-----------------------------------------------------------------
module i2s
(
// Clock & Reset
clk_i,
rst_i,
// PCM Data In (2x16-bit BE signed data)
pcm_data_i,
pcm_fifo_empty_i,
pcm_fifo_rd_o,
pcm_fifo_ur_o,
// I2S DAC Interface
bclk_o,
ws_o,
data_o
);
//-----------------------------------------------------------------
// Params
//-----------------------------------------------------------------
parameter CLK_DIVISOR = 6;
//-----------------------------------------------------------------
// I/O
//-----------------------------------------------------------------
input clk_i /*verilator public*/;
input rst_i /*verilator public*/;
input[31:0] pcm_data_i /*verilator public*/;
input pcm_fifo_empty_i /*verilator public*/;
output pcm_fifo_rd_o /*verilator public*/;
output pcm_fifo_ur_o /*verilator public*/;
output bclk_o /*verilator public*/;
output ws_o /*verilator public*/;
output data_o /*verilator public*/;
//-----------------------------------------------------------------
// Registers
//-----------------------------------------------------------------
// Data clock (generated)
reg audio_clock;
// Input clock divider (to generate audio_clock)
integer audio_clock_div;
// Input clock divider (to generate audio_clock)
integer bit_count;
// Word select
reg word_sel;
// Registered audio input data
reg [15:0] input_reg0;
reg [15:0] input_reg1;
// Last sample
reg [31:0] pcm_data_last;
reg prev_audio_clock;
reg pcm_fifo_rd_o;
reg pcm_fifo_ur_o;
reg bclk_o;
reg data_o;
//-----------------------------------------------------------------
// Bit Clock Generator
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
audio_clock_div <= 0;
audio_clock <= 1'b0;
end
else
begin
// Clock divider cycle_count matched?
if (audio_clock_div == (CLK_DIVISOR - 1))
begin
// Toggle clock
audio_clock <= ~audio_clock;
// Reset counter
audio_clock_div <= 0;
end
// Increment clock divider counter
else
audio_clock_div <= audio_clock_div + 1;
end
end
//-----------------------------------------------------------------
// I2S Output Generator
//-----------------------------------------------------------------
always @(posedge clk_i or posedge rst_i)
begin
if (rst_i == 1'b1)
begin
input_reg0 <= 16'h0000;
input_reg1 <= 16'h0000;
bit_count <= 0;
data_o <= 1'b0;
word_sel <= 1'b0;
prev_audio_clock<= 1'b0;
pcm_fifo_rd_o <= 1'b0;
pcm_fifo_ur_o <= 1'b0;
pcm_data_last <= 32'h00000000;
end
else
begin
pcm_fifo_rd_o <= 1'b0;
pcm_fifo_ur_o <= 1'b0;
// Update previous audio_clock value
prev_audio_clock <= audio_clock;
// CLK 1->0 - Falling Edge
if ((prev_audio_clock == 1'b1) && (audio_clock == 1'b0))
begin
bclk_o <= 1'b0;
// Cycle 0
if (bit_count == 0)
begin
// Output last bit (LSB)
if (word_sel == 1'b0)
data_o <= input_reg0[15];
// Output last bit (LSB)
else
data_o <= input_reg1[15];
// Toggle ws_o
word_sel <= ~word_sel;
// Increment cycle counter
bit_count <= bit_count + 1;
// Audio data ready?
if (pcm_fifo_empty_i == 1'b0)
begin
// Convert to big endian 16-bit left & right
pcm_data_last <= pcm_data_i;
input_reg0 <= pcm_data_i[31:16];
input_reg1 <= pcm_data_i[15:0];
pcm_fifo_rd_o <= 1'b1;
end
// Audio data buffer under run condition
else
begin
// Use previous data instead
input_reg0 <= pcm_data_last[31:16];
input_reg1 <= pcm_data_last[15:0];
pcm_fifo_ur_o <= 1'b1;
end
// Cycle 1 - 15
end
else
begin
if (word_sel == 1'b0)
begin
// Output MSB
data_o <= input_reg0[15];
// Shift data right
input_reg0 <= {input_reg0[14:0], 1'b0};
end
else
begin
// Output MSB
data_o <= input_reg1[15];
// Shift data right
input_reg1 <= {input_reg1[14:0], 1'b0};
end
if (bit_count == 15)
bit_count <= 0;
else
bit_count <= bit_count + 1;
end
end
// CLK 0->1 - Rising Edge
else if((prev_audio_clock == 1'b0) && (audio_clock == 1'b1))
bclk_o <= 1'b1;
end
end
//-----------------------------------------------------------------
// Combinatorial
//-----------------------------------------------------------------
assign ws_o = word_sel;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__muxb4to1.v"
module top();
// Inputs are registered
reg D;
reg S;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
S = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 S = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 S = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 S = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 S = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 S = 1'bx;
#600 D = 1'bx;
end
sky130_fd_sc_hdll__muxb4to1 dut (.D(D), .S(S), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A22O_1_V
`define SKY130_FD_SC_HVL__A22O_1_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22o_1 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__a22o_1 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A22O_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__MUX2_PP_SYMBOL_V
/**
* mux2: 2-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__mux2 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
output X ,
//# {{control|Control Signals}}
input S ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRDLXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRDLXTP_BEHAVIORAL_PP_V
/**
* srdlxtp: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dlatch_p_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srdlxtp (
Q ,
D ,
GATE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input D ;
input GATE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_dlatch$P_pp$PKG$sN dlatch0 (buf_Q , D_delayed, GATE_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b1 );
bufif1 bufif10 (Q , buf_Q, VPWR );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRDLXTP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2B_2_V
`define SKY130_FD_SC_HS__OR2B_2_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog wrapper for or2b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__or2b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_2 (
X ,
A ,
B_N ,
VPWR,
VGND
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__or2b_2 (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__or2b base (
.X(X),
.A(A),
.B_N(B_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2B_2_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_out_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// FPU output datapath.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_out_dp (
dest_rdy,
req_thread,
div_exc_out,
d8stg_fdivd,
d8stg_fdivs,
div_sign_out,
div_exp_out,
div_frac_out,
mul_exc_out,
m6stg_fmul_dbl_dst,
m6stg_fmuls,
mul_sign_out,
mul_exp_out,
mul_frac_out,
add_exc_out,
a6stg_fcmpop,
add_cc_out,
add_fcc_out,
a6stg_dbl_dst,
a6stg_sng_dst,
a6stg_long_dst,
a6stg_int_dst,
add_sign_out,
add_exp_out,
add_frac_out,
rclk,
fp_cpx_data_ca,
se,
si,
so
);
input [2:0] dest_rdy; // pipe with result request this cycle
input [1:0] req_thread; // thread ID of result req this cycle
input [4:0] div_exc_out; // divide pipe result- exception flags
input d8stg_fdivd; // divide double- divide stage 8
input d8stg_fdivs; // divide single- divide stage 8
input div_sign_out; // divide sign output
input [10:0] div_exp_out; // divide exponent output
input [51:0] div_frac_out; // divide fraction output
input [4:0] mul_exc_out; // multiply pipe result- exception flags
input m6stg_fmul_dbl_dst; // double precision multiply result
input m6stg_fmuls; // fmuls- multiply 6 stage
input mul_sign_out; // multiply sign output
input [10:0] mul_exp_out; // multiply exponent output
input [51:0] mul_frac_out; // multiply fraction output
input [4:0] add_exc_out; // add pipe result- exception flags
input a6stg_fcmpop; // compare- add 6 stage
input [1:0] add_cc_out; // add pipe result- condition
input [1:0] add_fcc_out; // add pipe input fcc passed through
input a6stg_dbl_dst; // float double result- add 6 stage
input a6stg_sng_dst; // float single result- add 6 stage
input a6stg_long_dst; // 64bit integer result- add 6 stage
input a6stg_int_dst; // 32bit integer result- add 6 stage
input add_sign_out; // add sign output
input [10:0] add_exp_out; // add exponent output
input [63:0] add_frac_out; // add fraction output
input rclk; // global clock
output [144:0] fp_cpx_data_ca; // FPU result to CPX
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [63:0] add_out;
wire [63:0] mul_out;
wire [63:0] div_out;
wire [7:0] fp_cpx_data_ca_84_77_in;
wire [76:0] fp_cpx_data_ca_76_0_in;
wire [7:0] fp_cpx_data_ca_84_77;
wire [76:0] fp_cpx_data_ca_76_0;
wire [144:0] fp_cpx_data_ca;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_out_dp (
.clk(clk),
.rclk(rclk),
.enb_l(1'b0),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Add pipe output.
//
///////////////////////////////////////////////////////////////////////////////
assign add_out[63:0]= ({64{a6stg_dbl_dst}}
& {add_sign_out, add_exp_out[10:0],
add_frac_out[62:11]})
| ({64{a6stg_sng_dst}}
& {add_sign_out, add_exp_out[7:0],
add_frac_out[62:40], 32'b0})
| ({64{a6stg_long_dst}}
& add_frac_out[63:0])
| ({64{a6stg_int_dst}}
& {add_frac_out[63:32], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Multiply output.
//
///////////////////////////////////////////////////////////////////////////////
assign mul_out[63:0]= ({64{m6stg_fmul_dbl_dst}}
& {mul_sign_out, mul_exp_out[10:0],
mul_frac_out[51:0]})
| ({64{m6stg_fmuls}}
& {mul_sign_out, mul_exp_out[7:0],
mul_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Divide output.
//
///////////////////////////////////////////////////////////////////////////////
assign div_out[63:0]= ({64{d8stg_fdivd}}
& {div_sign_out, div_exp_out[10:0],
div_frac_out[51:0]})
| ({64{d8stg_fdivs}}
& {div_sign_out, div_exp_out[7:0],
div_frac_out[51:29], 32'b0});
///////////////////////////////////////////////////////////////////////////////
//
// Choose the output data.
//
// Input to the CPX data (CA) stage.
//
///////////////////////////////////////////////////////////////////////////////
assign fp_cpx_data_ca_84_77_in[7:0]= ({8{(|dest_rdy)}}
& {1'b1, 4'b1000, 1'b0, req_thread[1:0]});
assign fp_cpx_data_ca_76_0_in[76:0]= ({77{dest_rdy[2]}}
& {div_exc_out[4:0], 8'b0, div_out[63:0]})
| ({77{dest_rdy[1]}}
& {mul_exc_out[4:0], 8'b0, mul_out[63:0]})
| ({77{dest_rdy[0]}}
& {add_exc_out[4:0], 2'b0, a6stg_fcmpop,
add_cc_out[1:0], add_fcc_out[1:0], 1'b0,
add_out[63:0]});
dff #(8) i_fp_cpx_data_ca_84_77 (
.din (fp_cpx_data_ca_84_77_in[7:0]),
.clk (clk),
.q (fp_cpx_data_ca_84_77[7:0]),
.se (se),
.si (),
.so ()
);
dff #(77) i_fp_cpx_data_ca_76_0 (
.din (fp_cpx_data_ca_76_0_in[76:0]),
.clk (clk),
.q (fp_cpx_data_ca_76_0[76:0]),
.se (se),
.si (),
.so ()
);
assign fp_cpx_data_ca[144:0]= {fp_cpx_data_ca_84_77[7:3],
3'b0,
fp_cpx_data_ca_84_77[2:0],
57'b0,
fp_cpx_data_ca_76_0[76:0]};
endmodule
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Verilog implementation of Generic Layer Controller
*
* This layer controller is a interface between MBus and layer peripherials.
* It has 4 major IO banks
* 1. IOs with MBus
* 2. IOs with Register Files (RF)
* 3. IOs with Memory controller
* 4. IOs with interrupt configuration
*
* Layer controller configuration:
* Register Files
* 1. LC_RF_DATA_WIDTH; 1 ~ 24 (24 default)
* 2. LC_RF_DEPTH; 1~256
*
* Memory
* 1. LC_MEM_ADDR_WIDTH; 1~32 (32 default)
* 2. LC_MEM_DATA_WIDTH; 1~32 (32 default)
* 3. LC_MEM_DEPTH; 1~2^30
*
* Interrupt
* 1. LC_INT_DEPTH;
*
* In normal application, users need to configure LC_RF_DEPTH, LC_MEM_DEPTH,
* LC_INT_DEPTH for their application. Changing the width causes bits waste
* on the MBus; thus, it's not recommended.
*
* IMPORTANT:
* 1. The memory interface is WORD address. Thus, the width of MEM_ADDR is
* 2-bit less than MEM_RD_DATA or MEM_WR_DATA.
* e.g. 0x00000000 and 0x00000001 address two different WORD in memory.
* If a user has byte address memory controller, remember to pad two 0s at the
* LSB in layer_wrapper.v
*
* 2. Interrupt Commands and Functional ID only work with RF_READ or MEM_READ
* commands, any other command will be rejected.
*
* 3. Unused IO, Don't be panic if synthesis tool reports Warning messages
* a) RX_ADDR[31:4] (default 32-bit width)
* b) TX_ADDR[31:8] (default 32-bit width)
* c) TX_PRIORITY
*
* 4. For more information, please refer to layer controller document
*
* Error Handling:
* The layer controller supports MEM/RF Error handling. If users accenditally
* read or write to a memory/RF location which is not exist. The read
* operation will automatically stops. If users initiate a DMA write which
* beyond the memory location, the layer controller will try to interrupt the
* BMus transaction by holding the RX_REQ low (rx overflow fault) if possible.
* However, user should be aware of the memory/RF depth at any time.
*
*
* Last modified date: 05/06 '13
* Last modified by: Ye-sheng Kuo <[email protected]>
* Update log:
* 5/22 '13
* Change define to parameter
* 5/17 '13
* Change memory interface, MEM_ACK_IN is no longer asynchronously reset MEM_REQ_OUT
* 5/6 '13
* first added
* */
`include "include/mbus_def.v"
module layer_ctrl(
CLK,
RESETn,
// Interface with MBus
TX_ADDR,
TX_DATA,
TX_PEND,
TX_REQ,
TX_ACK,
TX_PRIORITY,
RX_ADDR,
RX_DATA,
RX_PEND,
RX_REQ,
RX_ACK,
RX_BROADCAST,
RX_FAIL,
TX_FAIL,
TX_SUCC,
TX_RESP_ACK,
RELEASE_RST_FROM_MBUS,
// End of interface
// Interface with Registers
REG_RD_DATA,
REG_WR_DATA,
REG_WR_EN,
// End of interface
// Interface with MEM
MEM_REQ_OUT,
MEM_WRITE,
MEM_ACK_IN,
MEM_WR_DATA,
MEM_RD_DATA,
MEM_ADDR,
// End of interface
// Interrupt
INT_VECTOR,
CLR_INT,
INT_FU_ID,
INT_CMD
);
parameter LC_RF_DATA_WIDTH =24;
parameter LC_RF_ADDR_WIDTH =`DATA_WIDTH-LC_RF_DATA_WIDTH;
parameter LC_RF_DEPTH = 128; // 1 ~ 2^8
parameter LC_MEM_ADDR_WIDTH = 32; // should ALWAYS less than DATA_WIDTH
parameter LC_MEM_DATA_WIDTH = 32; // should ALWAYS less than DATA_WIDTH
parameter LC_MEM_DEPTH = 65536; // 1 ~ 2^30
parameter LC_INT_DEPTH = 8;
input CLK;
input RESETn;
// Interface with MBus
output reg [`ADDR_WIDTH-1:0] TX_ADDR;
output reg [`DATA_WIDTH-1:0] TX_DATA;
output reg TX_PEND;
output reg TX_REQ;
input TX_ACK;
output reg TX_PRIORITY;
input [`ADDR_WIDTH-1:0] RX_ADDR;
input [`DATA_WIDTH-1:0] RX_DATA;
input RX_PEND;
input RX_REQ;
output reg RX_ACK;
input RX_BROADCAST;
input RX_FAIL;
input TX_FAIL;
input TX_SUCC;
output reg TX_RESP_ACK;
input RELEASE_RST_FROM_MBUS;
// End of interface
// Interface with Registers
input [(LC_RF_DATA_WIDTH*LC_RF_DEPTH)-1:0] REG_RD_DATA;
output reg [LC_RF_DATA_WIDTH-1:0] REG_WR_DATA;
output reg [LC_RF_DEPTH-1:0] REG_WR_EN;
// End of interface
// Interface with MEM
output MEM_REQ_OUT;
output MEM_WRITE;
input MEM_ACK_IN;
output reg [LC_MEM_DATA_WIDTH-1:0] MEM_WR_DATA;
input [LC_MEM_DATA_WIDTH-1:0] MEM_RD_DATA;
output reg [LC_MEM_ADDR_WIDTH-3:0] MEM_ADDR;
// End of interface
// Interrupt
input [LC_INT_DEPTH-1:0] INT_VECTOR;
output reg [LC_INT_DEPTH-1:0] CLR_INT;
input [`FUNC_WIDTH*LC_INT_DEPTH-1:0] INT_FU_ID;
input [(`DATA_WIDTH<<1)*LC_INT_DEPTH-1:0] INT_CMD;
`include "include/mbus_func.v"
wire RESETn_local = (RESETn & (~RELEASE_RST_FROM_MBUS));
parameter MAX_DMA_LENGTH = 24; // cannot greater than `DATA_WIDTH - `SHORT_ADDR_WIDTH
parameter LC_STATE_IDLE = 4'd0;
parameter LC_STATE_RF_READ = 4'd1;
parameter LC_STATE_RF_WRITE = 4'd2;
parameter LC_STATE_MEM_READ = 4'd3;
parameter LC_STATE_MEM_WRITE = 4'd4;
parameter LC_STATE_BUS_TX = 4'd5;
parameter LC_STATE_WAIT_CPL = 4'd6;
parameter LC_STATE_ERROR = 4'd7;
parameter LC_STATE_INT_ARBI = 4'd8;
parameter LC_STATE_INT_HANDLED = 4'd9;
// Double latching registers
reg TX_ACK_DL1, TX_ACK_DL2;
reg RX_REQ_DL1, RX_REQ_DL2;
// General registers
reg [3:0] lc_state, next_lc_state, lc_return_state, next_lc_return_state;
reg rx_pend_reg, next_rx_pend_reg;
reg [2:0] mem_sub_state, next_mem_sub_state;
reg [MAX_DMA_LENGTH-1:0] dma_counter, next_dma_counter;
// rx buffers
reg [`DATA_WIDTH-1:0] rx_dat_buffer, next_rx_dat_buffer;
// Mbus interface
reg [`ADDR_WIDTH-1:0] next_tx_addr;
reg [`DATA_WIDTH-1:0] next_tx_data;
reg next_tx_pend;
reg next_tx_req;
reg next_priority;
reg next_rx_ack;
reg next_tx_resp_ack;
// RF interface
wire [LC_RF_DATA_WIDTH-1:0] rf_in_array [0:LC_RF_DEPTH-1];
genvar unpk_idx;
generate
for (unpk_idx=0; unpk_idx<(LC_RF_DEPTH); unpk_idx=unpk_idx+1)
begin: UNPACK
assign rf_in_array[unpk_idx] = REG_RD_DATA[((LC_RF_DATA_WIDTH)*(unpk_idx+1)-1):((LC_RF_DATA_WIDTH)*unpk_idx)];
end
endgenerate
reg [LC_RF_DEPTH-1:0] next_rf_load;
wire [LC_RF_DEPTH-1:0] rf_load_temp = (1'b1<<(rx_dat_buffer[`DATA_WIDTH-1:LC_RF_DATA_WIDTH]));
reg [LC_RF_DATA_WIDTH-1:0] next_rf_dout;
wire [LC_RF_ADDR_WIDTH-1:0] rf_dma_length = rx_dat_buffer[LC_RF_DATA_WIDTH-1:LC_RF_DATA_WIDTH-LC_RF_ADDR_WIDTH];
wire [log2(LC_RF_DEPTH-1)-1:0] rf_idx_temp = rx_dat_buffer[(LC_RF_DATA_WIDTH+log2(LC_RF_DEPTH-1)-1):LC_RF_DATA_WIDTH];
wire [`SHORT_ADDR_WIDTH-1:0] rf_relay_addr = rx_dat_buffer[LC_RF_DATA_WIDTH-LC_RF_ADDR_WIDTH-1:LC_RF_DATA_WIDTH-LC_RF_ADDR_WIDTH-`SHORT_ADDR_WIDTH];
reg [log2(LC_RF_DEPTH-1)-1:0] rf_idx, next_rf_idx;
// Mem interface
reg mem_write, next_mem_write, mem_read, next_mem_read;
assign MEM_REQ_OUT = (mem_write | mem_read);
assign MEM_WRITE = mem_write;
reg [LC_MEM_ADDR_WIDTH-3:0] next_mem_aout;
reg [LC_MEM_DATA_WIDTH-1:0] next_mem_dout;
// Interrupt register
reg [LC_INT_DEPTH-1:0] next_clr_int, int_vector_copied, next_int_vector_copied;
reg [log2(LC_INT_DEPTH-1)-1:0] int_idx, next_int_idx;
reg next_layer_interrupted, layer_interrupted;
wire [`FUNC_WIDTH-1:0] interrupt_functional_id [0:LC_INT_DEPTH-1];
wire [(`DATA_WIDTH<<1)-1:0] interrupt_payload [0:LC_INT_DEPTH-1];
generate
for (unpk_idx=0; unpk_idx<(LC_INT_DEPTH); unpk_idx=unpk_idx+1)
begin: UNPACK_INT
assign interrupt_functional_id[unpk_idx] = INT_FU_ID[((`FUNC_WIDTH)*(unpk_idx+1)-1):((`FUNC_WIDTH)*unpk_idx)];
assign interrupt_payload[unpk_idx] = INT_CMD[((`DATA_WIDTH<<1)*(unpk_idx+1)-1):((`DATA_WIDTH<<1)*unpk_idx)];
end
endgenerate
always @ (posedge CLK or negedge RESETn_local)
begin
if (~RESETn_local)
begin
TX_ACK_DL1 <= 0;
TX_ACK_DL2 <= 0;
RX_REQ_DL1 <= 0;
RX_REQ_DL2 <= 0;
end
else
begin
TX_ACK_DL1 <= TX_ACK;
TX_ACK_DL2 <= TX_ACK_DL1;
RX_REQ_DL1 <= RX_REQ;
RX_REQ_DL2 <= RX_REQ_DL1;
end
end
always @ (posedge CLK or negedge RESETn_local)
begin
if (~RESETn_local)
begin
// General registers
lc_state <= LC_STATE_IDLE;
lc_return_state <= LC_STATE_IDLE;
rx_pend_reg <= 0;
mem_sub_state <= 0;
dma_counter <= 0;
// rx buffers
rx_dat_buffer <= 0;
// MBus interface
TX_ADDR <= 0;
TX_DATA <= 0;
TX_REQ <= 0;
TX_PEND <= 0;
TX_PRIORITY<= 0;
RX_ACK <= 0;
TX_RESP_ACK <= 0;
// Register file interface
REG_WR_EN <= 0;
REG_WR_DATA <= 0;
rf_idx <= 0;
// Memory interface
mem_write <= 0;
mem_read <= 0;
MEM_ADDR <= 0;
MEM_WR_DATA <= 0;
// Interrupt interface
CLR_INT <= 0;
int_idx <= 0;
int_vector_copied <= 0;
layer_interrupted <= 0;
end
else
begin
// General registers
lc_state <= next_lc_state;
lc_return_state <= next_lc_return_state;
rx_pend_reg <= next_rx_pend_reg;
mem_sub_state <= next_mem_sub_state;
dma_counter <= next_dma_counter;
// rx buffers
rx_dat_buffer <= next_rx_dat_buffer;
// MBus interface
TX_ADDR <= next_tx_addr;
TX_DATA <= next_tx_data;
TX_REQ <= next_tx_req;
TX_PEND <= next_tx_pend;
TX_PRIORITY <= next_priority;
RX_ACK <= next_rx_ack;
TX_RESP_ACK <= next_tx_resp_ack;
// Register file interface
REG_WR_EN <= next_rf_load;
REG_WR_DATA <= next_rf_dout;
rf_idx <= next_rf_idx;
// Memory interface
mem_write <= next_mem_write;
mem_read <= next_mem_read;
MEM_ADDR <= next_mem_aout;
MEM_WR_DATA <= next_mem_dout;
// Interrupt interface
CLR_INT <= next_clr_int;
int_idx <= next_int_idx;
int_vector_copied <= next_int_vector_copied;
layer_interrupted <= next_layer_interrupted;
end
end
always @ *
begin
// General registers
next_lc_state = lc_state;
next_lc_return_state = lc_return_state;
next_rx_pend_reg= rx_pend_reg;
next_mem_sub_state = mem_sub_state;
next_dma_counter = dma_counter;
// rx buffers
next_rx_dat_buffer = rx_dat_buffer;
// MBus registers
next_tx_addr = TX_ADDR;
next_tx_data = TX_DATA;
next_tx_pend = TX_PEND;
next_tx_req = TX_REQ;
next_priority = TX_PRIORITY;
next_rx_ack = RX_ACK;
next_tx_resp_ack= TX_RESP_ACK;
// RF registers
next_rf_load = 0;
next_rf_dout = REG_WR_DATA;
next_rf_idx = rf_idx;
// MEM registers
next_mem_aout = MEM_ADDR;
next_mem_dout = MEM_WR_DATA;
next_mem_write = mem_write;
next_mem_read = mem_read;
// Interrupt registers
next_clr_int = CLR_INT;
next_int_idx = int_idx;
next_int_vector_copied = int_vector_copied;
next_layer_interrupted = layer_interrupted;
// Asynchronized interface
if ((~(RX_REQ_DL2 | RX_FAIL)) & RX_ACK)
next_rx_ack = 0;
if (CLR_INT & (~INT_VECTOR))
next_clr_int = 0;
if (TX_ACK_DL2 & TX_REQ)
next_tx_req = 0;
if (TX_SUCC | TX_FAIL)
next_tx_resp_ack = 1;
if ((~(TX_SUCC | TX_FAIL)) & TX_RESP_ACK)
next_tx_resp_ack = 0;
if (MEM_ACK_IN & MEM_REQ_OUT)
begin
next_mem_read = 0;
next_mem_write = 0;
end
// End of asynchronized interface
case (lc_state)
LC_STATE_IDLE:
begin
next_mem_sub_state = 0;
next_layer_interrupted = 0;
if ((INT_VECTOR>0) && (CLR_INT==0))
begin
next_int_vector_copied = INT_VECTOR;
next_lc_state = LC_STATE_INT_ARBI;
next_int_idx = 0;
end
else
begin
if (RX_REQ_DL2 | RX_FAIL)
next_rx_ack = 1;
if (RX_REQ_DL2 & (~RX_ACK)) // prevent double trigger
begin
next_rx_dat_buffer = RX_DATA;
next_rx_pend_reg = RX_PEND;
case (RX_ADDR[`FUNC_WIDTH-1:0])
`LC_CMD_RF_READ: begin next_lc_state = LC_STATE_RF_READ; end
`LC_CMD_RF_WRITE: begin next_lc_state = LC_STATE_RF_WRITE; end
`LC_CMD_MEM_READ: begin next_lc_state = LC_STATE_MEM_READ; end
`LC_CMD_MEM_WRITE: begin next_lc_state = LC_STATE_MEM_WRITE; end
default: begin if (RX_PEND) next_lc_state = LC_STATE_ERROR; end // Invalid message
endcase
end
end
end
LC_STATE_RF_READ:
begin
case (mem_sub_state)
0:
begin
if ((~rx_pend_reg)&&((rx_dat_buffer[`DATA_WIDTH-1:LC_RF_DATA_WIDTH]) < LC_RF_DEPTH)) // prevent aliasing
begin
next_dma_counter = {{(MAX_DMA_LENGTH-LC_RF_ADDR_WIDTH){1'b0}}, rf_dma_length};
next_rf_idx = rf_idx_temp;
next_mem_sub_state = 1;
next_tx_addr = {{(`ADDR_WIDTH-`SHORT_ADDR_WIDTH){1'b0}}, rf_relay_addr};
end
else if (rx_pend_reg) // invalid message
begin
next_lc_state = LC_STATE_ERROR;
next_mem_sub_state = 0;
end
else // invalid address
next_lc_state = LC_STATE_IDLE;
end
1:
begin
if (~TX_REQ)
begin
next_tx_data = {{(LC_RF_ADDR_WIDTH){1'b0}}, rf_in_array[rf_idx]};
next_tx_req = 1;
next_lc_state = LC_STATE_BUS_TX;
next_mem_sub_state = 2;
next_lc_return_state = LC_STATE_RF_READ;
if ((dma_counter)&&(rf_idx < (LC_RF_DEPTH-1'b1)))
begin
next_tx_pend = 1;
next_dma_counter = dma_counter - 1'b1;
end
else
next_tx_pend = 0;
end
end
2:
begin
next_rf_idx = rf_idx + 1'b1;
next_mem_sub_state = 1;
end
endcase
end
LC_STATE_RF_WRITE:
begin
case (mem_sub_state)
0:
begin
if ((rx_dat_buffer[`DATA_WIDTH-1:LC_RF_DATA_WIDTH]) < LC_RF_DEPTH)
begin
next_rf_dout = rx_dat_buffer[LC_RF_DATA_WIDTH-1:0];
next_mem_sub_state = 1;
end
else if (rx_pend_reg) // Invalid address
begin
next_lc_state = LC_STATE_ERROR;
next_mem_sub_state = 0;
end
else
next_lc_state = LC_STATE_IDLE;
end
1:
begin
next_rf_load = rf_load_temp;
if (rx_pend_reg)
next_mem_sub_state = 2;
else
next_lc_state = LC_STATE_IDLE;
end
2:
begin
if (RX_REQ_DL2 & (~RX_ACK))
begin
next_rx_ack = 1;
next_mem_sub_state = 0;
next_rx_dat_buffer = RX_DATA;
next_rx_pend_reg = RX_PEND;
end
else if ((RX_FAIL) & (~RX_ACK))
begin
next_rx_ack = 1;
next_lc_state = LC_STATE_IDLE;
end
end
endcase
end
LC_STATE_MEM_READ:
begin
case (mem_sub_state)
0:
begin
if ((rx_pend_reg)&&(rx_dat_buffer[LC_MEM_ADDR_WIDTH-1:2] < LC_MEM_DEPTH))
begin
next_mem_aout = rx_dat_buffer[LC_MEM_ADDR_WIDTH-1:2];
next_dma_counter = 0;
next_mem_sub_state = 1;
end
else if (rx_pend_reg & (~layer_interrupted)) // Invalid address
begin
next_lc_state = LC_STATE_ERROR;
next_mem_sub_state = 0;
end
else // Invalid message
next_lc_state = LC_STATE_IDLE;
end
1:
begin
if (layer_interrupted)
begin
next_rx_pend_reg = 0;
next_mem_sub_state = 2;
next_dma_counter = interrupt_payload[int_idx][MAX_DMA_LENGTH-1:0];
next_tx_addr = {{(`ADDR_WIDTH-`SHORT_ADDR_WIDTH){1'b0}}, interrupt_payload[int_idx][`DATA_WIDTH-1:`DATA_WIDTH-`SHORT_ADDR_WIDTH]};
end
else
begin
if (RX_REQ_DL2 & (~RX_ACK))
begin
next_rx_ack = 1;
next_rx_pend_reg = RX_PEND;
next_mem_sub_state = 2;
next_dma_counter = RX_DATA[MAX_DMA_LENGTH-1:0];
next_tx_addr = {{(`ADDR_WIDTH-`SHORT_ADDR_WIDTH){1'b0}}, RX_DATA[`DATA_WIDTH-1:`DATA_WIDTH-`SHORT_ADDR_WIDTH]};
end
else if (RX_FAIL & (~RX_ACK))
begin
next_rx_ack = 1;
next_lc_state = LC_STATE_IDLE;
end
end
end
2:
begin
if (~MEM_REQ_OUT)
begin
next_mem_read = 1;
next_mem_sub_state = 3;
end
end
3:
begin
// Read complete
if (MEM_ACK_IN & (~TX_REQ))
begin
next_tx_req = 1;
next_tx_data[LC_MEM_DATA_WIDTH-1:0] = MEM_RD_DATA;
next_lc_state = LC_STATE_BUS_TX;
next_lc_return_state = LC_STATE_MEM_READ;
next_mem_sub_state = 4;
if ((dma_counter)&&(MEM_ADDR < (LC_MEM_DEPTH-1'b1)))
begin
next_tx_pend = 1;
next_dma_counter = dma_counter - 1'b1;
end
else
next_tx_pend = 0;
end
end
4: // increment address
begin
next_mem_aout = MEM_ADDR + 1'b1;
next_mem_sub_state = 2;
end
endcase
end
LC_STATE_MEM_WRITE:
begin
case (mem_sub_state)
0:
begin
if ((rx_pend_reg)&&(rx_dat_buffer[LC_MEM_ADDR_WIDTH-1:2] < LC_MEM_DEPTH))
begin
next_mem_aout = rx_dat_buffer[LC_MEM_ADDR_WIDTH-1:2];
next_mem_sub_state = 1;
end
else if (rx_pend_reg) // Invalid Address
begin
next_lc_state = LC_STATE_ERROR;
next_mem_sub_state = 0;
end
else // Invalid message
next_lc_state = LC_STATE_IDLE;
end
1:
begin
if (RX_REQ_DL2 & (~RX_ACK))
begin
next_rx_ack = 1;
next_mem_sub_state = 2;
next_mem_dout = RX_DATA[LC_MEM_DATA_WIDTH-1:0];
next_rx_pend_reg = RX_PEND;
end
else if (RX_FAIL & (~RX_ACK))
begin
next_rx_ack = 1;
next_lc_state = LC_STATE_IDLE;
end
end
2:
begin
if (~MEM_REQ_OUT)
begin
next_mem_write = 1;
next_mem_sub_state = 3;
end
end
3:
begin
// write complete
if (MEM_ACK_IN)
begin
if ((rx_pend_reg)&&(MEM_ADDR<(LC_MEM_DEPTH-1'b1)))
begin
next_mem_aout = MEM_ADDR + 1'b1;
next_mem_sub_state = 1;
end
else if (rx_pend_reg) // Invalid Address
begin
next_lc_state = LC_STATE_ERROR;
next_mem_sub_state = 0;
end
else
next_lc_state = LC_STATE_IDLE;
end
end
endcase
end
LC_STATE_BUS_TX:
begin // cannot modify mem_sub_state here
if (TX_ACK_DL2)
begin
if (TX_PEND)
next_lc_state = lc_return_state;
else
next_lc_state = LC_STATE_WAIT_CPL;
end
else if (TX_FAIL)
next_lc_state = LC_STATE_WAIT_CPL;
end
LC_STATE_WAIT_CPL:
begin
if (TX_SUCC | TX_FAIL)
next_lc_state = LC_STATE_IDLE;
end
LC_STATE_INT_ARBI:
begin
if (int_vector_copied[0])
begin
next_lc_state = LC_STATE_INT_HANDLED;
end
else
begin
next_int_vector_copied = (int_vector_copied>>1);
next_int_idx = int_idx + 1;
end
end
LC_STATE_INT_HANDLED:
begin
next_clr_int = (1'b1 << int_idx); // clear interrupt
next_rx_dat_buffer = interrupt_payload[int_idx][(`DATA_WIDTH<<1)-1:`DATA_WIDTH];
next_layer_interrupted = 1;
case (interrupt_functional_id[int_idx])
`LC_CMD_RF_READ: begin next_lc_state = LC_STATE_RF_READ; next_rx_pend_reg = 0; end
`LC_CMD_MEM_READ: begin next_lc_state = LC_STATE_MEM_READ; next_rx_pend_reg = 1; end
default: begin next_lc_state = LC_STATE_IDLE; end // Invalid interrupt message
endcase
end
// This state handles errors, junk message coming in. disgarding all
// the message before return idle state
LC_STATE_ERROR:
begin
case (mem_sub_state)
0:
begin
if (RX_REQ_DL2 & (~RX_ACK))
begin
next_rx_pend_reg = RX_PEND;
next_mem_sub_state = 1;
end
end
1:
begin
if (rx_pend_reg & RX_FAIL)
begin
next_rx_ack = 1;
next_lc_state = LC_STATE_IDLE;
end
else if (~rx_pend_reg)
begin
next_rx_ack = 1;
next_lc_state = LC_STATE_IDLE;
end
end
endcase
end
endcase
end
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cordic_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cordic_ram (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [31:0] data;
input [7:0] rdaddress;
input [7:0] wraddress;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({32{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
`ifdef SIMULATION
altsyncram_component.init_file = "../../dgn/rtl/altera/cordic_ram.mif",
`else //for syn
altsyncram_component.init_file = "../rtl/altera/cordic_ram.mif",
`endif
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 256,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M10K",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "cordic_ram.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "cordic_ram.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M10K"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 8 0 INPUT NODEFVAL "rdaddress[7..0]"
// Retrieval info: USED_PORT: wraddress 0 0 8 0 INPUT NODEFVAL "wraddress[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 8 0 wraddress 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 8 0 rdaddress 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cordic_ram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:45:48 02/22/2015
// Design Name:
// Module Name: MultiplyMult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MultiplyMult(
input [32:0] aout_Special,
input [32:0] bout_Special,
input [32:0] zout_Special,
input idle_Special,
input clock,
output reg idle_Multiply,
output reg [32:0] zout_Multiply,
output reg [49:0] productout_Multiply
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire a_sign;
wire [7:0] a_exponent;
wire [23:0] a_mantissa;
wire b_sign;
wire [7:0] b_exponent;
wire [23:0] b_mantissa;
assign a_sign = aout_Special[32];
assign a_exponent = aout_Special[31:24] - 127;
assign a_mantissa = {aout_Special[23:0]};
assign b_sign = bout_Special[32];
assign b_exponent = bout_Special[31:24] - 127;
assign b_mantissa = {bout_Special[23:0]};
always @ (posedge clock)
begin
idle_Multiply <= idle_Special;
if (idle_Special == no_idle) begin
zout_Multiply[32] <= a_sign ^ b_sign;
zout_Multiply[31:24] <= a_exponent + b_exponent + 1;
zout_Multiply[23:0] <= 0;
productout_Multiply <= a_mantissa * b_mantissa * 4;
end
else begin
zout_Multiply <= zout_Special;
end
end
endmodule
|
`timescale 1ns / 1ps
/***********************************************************************
This file is part of the OpenADC Project. See www.newae.com for more details,
or the codebase at http://www.assembla.com/spaces/openadc .
This file is the serial interface. It can be replaced with a variety of other
interfaces such as FTDI chip etc.
Copyright (c) 2012, Colin O'Flynn <[email protected]>. All rights reserved.
This project is released under the Modified FreeBSD License. See LICENSE
file which should have came with this code.
*************************************************************************/
module serial_reg_iface(
input reset_i,
input clk_i,
input rx_i,
output tx_o,
output reg cmdfifo_rxf,
output cmdfifo_txe,
input cmdfifo_rd,
input cmdfifo_wr,
output [7:0] cmdfifo_din,
input [7:0] cmdfifo_dout
);
wire clk;
wire tx_out;
wire rx_in;
assign clk = clk_i;
assign rx_in = rx_i;
assign tx_o = tx_out;
reg [7:0] dataout;
wire [7:0] data;
wire data_ready;
assign cmdfifo_din = dataout;
always @(posedge clk) begin
if (data_ready) begin
dataout <= data;
end
end
always @(posedge clk or posedge cmdfifo_rd) begin
if (cmdfifo_rd) begin
cmdfifo_rxf <= 0;
end else begin
if (data_ready) begin
cmdfifo_rxf <= 1;
end
end
end
//Serial
wire txbusy;
async_transmitter AT (.clk(clk),
.TxD_start(cmdfifo_wr),
.TxD_data(cmdfifo_dout),
.TxD(tx_out),
.TxD_busy(txbusy));
assign cmdfifo_txe = ~(txbusy | cmdfifo_wr);
async_receiver AR (.clk(clk),
.RxD(rx_in),
.RxD_idle(),
.RxD_data_ready(data_ready),
.RxD_data_error(),
.RxD_data(data),
.RxD_endofpacket());
endmodule
|
//////////////////////////////////////////////////////////////////////////
// Department of Computer Science
// National Tsing Hua University
// Project : FIFO for CS4125 Digital System Design
// Module : fifo.v
// Author : Chih-Tsun Huang
// E-mail : [email protected]
// Revision : 4
// Date : 2014/04/28
// Abstract :
// The top module of FIFO consists of FIFO controller and the RAM module.
// Note :
// 1. The purpose of this version is to provide a design style. It is
// not a complete module. Please fix any *unexpected feature* by
// yourself if any.
// 2. Feel free to rewrite this file header to your own.
//
module fifo (
input clk,
input rst_n,
input push,
input pop,
input [15:0] datain,
output empty,
output almost_empty,
output full,
output almost_full,
output error,
output reg [15:0] dataout
);
wire [5:0] addr;
wire cen;
wire oen;
wire wen;
wire [15:0] data_to_ram;
wire [7:0] next_dataout_1f, next_dataout_1e, next_dataout_2f, next_dataout_2e;
reg [7:0] next_datain_1f, next_datain_1e, next_datain_2f, next_datain_2e;
reg [5:0] next_addr;
fifo_ctr controller (
.clk(clk),
.rst_n(rst_n),
.push(push),
.pop(pop),
.empty(empty),
.almost_empty(almost_empty),
.full(full),
.almost_full(almost_full),
.error(error),
.cen(cen),
.wen(wen),
.oen(oen),
.addr(addr)
);
// LAB NOTE:
// You should include the memory simulation model by your own
RAM32x8 ram1_front (
.Q(next_dataout_1f),
.CLK(clk),
.CEN(cen),
.WEN(wen),
.A(next_addr[4:0]),
.D(next_datain_1f),
.OEN(oen)
);
RAM32x8 ram1_end (
.Q(next_dataout_1e),
.CLK(clk),
.CEN(cen),
.WEN(wen),
.A(next_addr[4:0]),
.D(next_datain_1e),
.OEN(oen)
);
RAM32x8 ram2_front (
.Q(next_dataout_2f),
.CLK(clk),
.CEN(cen),
.WEN(wen),
.A(next_addr[4:0]),
.D(next_datain_2f),
.OEN(oen)
);
RAM32x8 ram2_end (
.Q(next_dataout_2e),
.CLK(clk),
.CEN(cen),
.WEN(wen),
.A(next_addr[4:0]),
.D(next_dataout_2e),
.OEN(oen)
);
always @(*) begin
if (addr[4] == 1) begin
dataout = {next_dataout_2f, next_dataout_2e};
{next_datain_2f, next_datain_2e} = datain;
{next_datain_1f, next_datain_1e} = {next_datain_1f, next_datain_1e};
end else begin
dataout = {next_dataout_1f, next_dataout_1e};
{next_datain_1f, next_datain_1e} = datain;
{next_datain_2f, next_datain_2e} = {next_datain_2f, next_datain_2e};
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
///////////////////////////////////////////////////////////////////////////////
//
// TX_LL
//
//
// Description: The TX_LL module converts user data from the LocalLink interface
// to Aurora Data, then sends it to the Aurora Channel for transmission.
//
//
//
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_25p4G_TX_LL
(
// S_AXI_TX Interface
s_axi_tx_tdata,
s_axi_tx_tlast,
s_axi_tx_tkeep,
s_axi_tx_tvalid,
s_axi_tx_tready,
// Clock Compensation Interface
DO_CC,
// Global Logic Interface
CHANNEL_UP,
// Aurora Lane Interface
GEN_SEP,
GEN_SEP7,
SEP_NB,
TX_PE_DATA_V,
TX_PE_DATA,
GEN_CC,
// System Interface
USER_CLK,
RESET,
TXDATAVALID_IN
);
`define DLY #1
//***********************************Port Declarations*******************************
// S_AXI_TX Interface
input [0:63] s_axi_tx_tdata;
input s_axi_tx_tvalid;
input s_axi_tx_tlast;
input [0:7] s_axi_tx_tkeep;
output s_axi_tx_tready;
// Clock Compensation Interface
input DO_CC;
// Global Logic Interface
input CHANNEL_UP;
// Aurora Lane Interface
output GEN_SEP;
output GEN_SEP7;
output [0:2] SEP_NB;
output TX_PE_DATA_V;
output [0:63] TX_PE_DATA;
output GEN_CC;
// System Interface
input USER_CLK;
input RESET;
input TXDATAVALID_IN;
//*********************************Wire Declarations**********************************
//*********************************Main Body of Code**********************************
// TX_DST_RDY_N is generated by TX_LL_CONTROL_SM and used by TX_LL_DATAPATH and
// external modules to regulate incoming pdu data signals.
// TX_LL_Datapath module
aurora_64b66b_25p4G_TX_LL_DATAPATH tx_ll_datapath_i
(
// S_AXI_TX Interface
.s_axi_tx_tdata (s_axi_tx_tdata),
.s_axi_tx_tlast (s_axi_tx_tlast),
.s_axi_tx_tvalid (s_axi_tx_tvalid),
.s_axi_tx_tready (s_axi_tx_tready),
// Aurora Lane Interface
.TX_PE_DATA_V(TX_PE_DATA_V),
.TX_PE_DATA(TX_PE_DATA),
// System Interface
.CHANNEL_UP(CHANNEL_UP),
.USER_CLK(USER_CLK)
);
// TX_LL_Control module
aurora_64b66b_25p4G_TX_LL_CONTROL_SM tx_ll_control_sm_i
(
// S_AXI_TX Interface
.s_axi_tx_tlast (s_axi_tx_tlast),
.s_axi_tx_tkeep (s_axi_tx_tkeep),
.s_axi_tx_tvalid (s_axi_tx_tvalid),
.s_axi_tx_tready (s_axi_tx_tready),
// Clock Compensation Interface
.DO_CC(DO_CC),
// Global Logic Interface
.CHANNEL_UP(CHANNEL_UP),
// TX_LL Control Module Interface
// Aurora Lane Interface
.GEN_SEP(GEN_SEP),
.GEN_SEP7(GEN_SEP7),
.SEP_NB(SEP_NB),
.GEN_CC(GEN_CC),
// System Interface
.USER_CLK(USER_CLK),
.TXDATAVALID_IN(TXDATAVALID_IN)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_t_e
//
// Generated
// by: wig
// on: Mon Jun 26 16:49:02 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../open.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_t_e.v,v 1.5 2006/07/04 09:54:11 wig Exp $
// $Date: 2006/07/04 09:54:11 $
// $Log: inst_t_e.v,v $
// Revision 1.5 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_t_e
//
// No user `defines in this module
module inst_t_e
//
// Generated Module inst_t
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
wire [2:0] non_open;
wire non_open_bit;
wire [3:0] wire_open;
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
// Generated Instance Port Map for inst_a
wire [3:0] mix_dmy_open_0; //__I_OPEN_DUMMY
wire mix_dmy_open_1; //__I_OPEN_DUMMY
wire mix_dmy_open_2; //__I_OPEN_DUMMY
wire mix_dmy_open_3; //__I_OPEN_DUMMY
wire [2:0] mix_dmy_open_4; //__I_OPEN_DUMMY
inst_a_e inst_a (
.open_bit(),
.open_bus(),
.open_bus_9(),
.open_in_bit_11(),
.open_in_bus_10(),
.open_part12({ non_open_bit, mix_dmy_open_0, non_open }), // __W_PORT // from 5 to 3 // __W_PORT // __I_BIT_TO_BUSPORT // __I_COMBINE_SPLICES
.open_part13({ mix_dmy_open_3, non_open_bit, mix_dmy_open_2, mix_dmy_open_1, non_open }), // __W_PORT // __I_BIT_TO_BUSPORT (x4) // __I_COMBINE_SPLICES
.openport14(), // check width and type
.wire_open({ mix_dmy_open_4, wire_open }), // __W_PORT (x2) // __I_COMBINE_SPLICES
.wire_open_in(wire_open)
);
// End of Generated Instance Port Map for inst_a
// Generated Instance Port Map for inst_b
inst_b_e inst_b (
.mix_key_open(), // replace name
.non_open(non_open),
.non_open_bit(non_open_bit),
.open_bit_2(),
.open_bit_3(),
.open_bit_4()
);
// End of Generated Instance Port Map for inst_b
endmodule
//
// End of Generated Module rtl of inst_t_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
// Copyright (c) 2012-2013 Ludvig Strigeus
// This program is GPL Licensed. See COPYING for the full license.
`timescale 1ns / 1ps
// Asynchronous PSRAM controller for byte access
// After outputting a byte to read, the result is available 70ns later.
module MemoryController(
input clk,
input read_a, // Set to 1 to read from RAM
input read_b, // Set to 1 to read from RAM
input write, // Set to 1 to write to RAM
input [23:0] addr, // Address to read / write
input [7:0] din, // Data to write
output reg [7:0] dout_a, // Last read data a
output reg [7:0] dout_b, // Last read data b
output reg busy, // 1 while an operation is in progress
output reg MemOE, // Output Enable. Enable when Low.
output reg MemWR, // Write Enable. WRITE when Low.
output MemAdv, // Address valid. Keep LOW for Async.
output MemClk, // Clock for sync oper. Keep LOW for Async.
output reg RamCS, // Chip Enable. Active = LOW
output RamCRE, // CRE = Control Register. LOW = Normal mode.
output reg RamUB, // Upper byte enable
output reg RamLB, // Lower byte enable
output reg [22:0] MemAdr,
inout [15:0] MemDB);
// These are always low for async operations
assign MemAdv = 0;
assign MemClk = 0;
assign RamCRE = 0;
reg [7:0] data_to_write;
assign MemDB = MemOE ? {data_to_write, data_to_write} : 16'bz; // MemOE == 0 means we need to output tristate
reg [1:0] cycles;
reg r_read_a;
always @(posedge clk) begin
// Initiate read or write
if (!busy) begin
if (read_a || read_b || write) begin
MemAdr <= addr[23:1];
RamUB <= !(addr[0] != 0); // addr[0] == 0 asserts RamUB, active low.
RamLB <= !(addr[0] == 0);
RamCS <= 0; // 0 means active
MemWR <= !(write != 0); // Active Low
MemOE <= !(write == 0);
busy <= 1;
data_to_write <= din;
cycles <= 0;
r_read_a <= read_a;
end else begin
MemOE <= 1;
MemWR <= 1;
RamCS <= 1;
RamUB <= 1;
RamLB <= 1;
busy <= 0;
cycles <= 0;
end
end else begin
if (cycles == 2) begin
// Now we have waited 3x45 = 135ns, latch incoming data on read.
if (!MemOE) begin
if (r_read_a) dout_a <= RamUB ? MemDB[7:0] : MemDB[15:8];
else dout_b <= RamUB ? MemDB[7:0] : MemDB[15:8];
end
MemOE <= 1; // Deassert Output Enable.
MemWR <= 1; // Deassert Write
RamCS <= 1; // Deassert Chip Select
RamUB <= 1; // Deassert upper/lower byte
RamLB <= 1;
busy <= 0;
cycles <= 0;
end else begin
cycles <= cycles + 1;
end
end
end
endmodule // MemoryController
// Module reads bytes and writes to proper address in ram.
// Done is asserted when the whole game is loaded.
// This parses iNES headers too.
module GameLoader(input clk, input reset,
input [7:0] indata, input indata_clk,
output reg [21:0] mem_addr, output [7:0] mem_data, output mem_write,
output [31:0] mapper_flags,
output reg done,
output error);
reg [1:0] state = 0;
reg [7:0] prgsize;
reg [3:0] ctr;
reg [7:0] ines[0:15]; // 16 bytes of iNES header
reg [21:0] bytes_left;
assign error = (state == 3);
wire [7:0] prgrom = ines[4];
wire [7:0] chrrom = ines[5];
assign mem_data = indata;
assign mem_write = (bytes_left != 0) && (state == 1 || state == 2) && indata_clk;
wire [2:0] prg_size = prgrom <= 1 ? 0 :
prgrom <= 2 ? 1 :
prgrom <= 4 ? 2 :
prgrom <= 8 ? 3 :
prgrom <= 16 ? 4 :
prgrom <= 32 ? 5 :
prgrom <= 64 ? 6 : 7;
wire [2:0] chr_size = chrrom <= 1 ? 0 :
chrrom <= 2 ? 1 :
chrrom <= 4 ? 2 :
chrrom <= 8 ? 3 :
chrrom <= 16 ? 4 :
chrrom <= 32 ? 5 :
chrrom <= 64 ? 6 : 7;
wire [7:0] mapper = {ines[7][7:4], ines[6][7:4]};
wire has_chr_ram = (chrrom == 0);
assign mapper_flags = {16'b0, has_chr_ram, ines[6][0], chr_size, prg_size, mapper};
always @(posedge clk) begin
if (reset) begin
state <= 0;
done <= 0;
ctr <= 0;
mem_addr <= 0; // Address for PRG
end else begin
case(state)
// Read 16 bytes of ines header
0: if (indata_clk) begin
ctr <= ctr + 1;
ines[ctr] <= indata;
bytes_left <= {prgrom, 14'b0};
if (ctr == 4'b1111)
state <= (ines[0] == 8'h4E) && (ines[1] == 8'h45) && (ines[2] == 8'h53) && (ines[3] == 8'h1A) && !ines[6][2] && !ines[6][3] ? 1 : 3;
end
1, 2: begin // Read the next |bytes_left| bytes into |mem_addr|
if (bytes_left != 0) begin
if (indata_clk) begin
bytes_left <= bytes_left - 1;
mem_addr <= mem_addr + 1;
end
end else if (state == 1) begin
state <= 2;
mem_addr <= 22'b10_0000_0000_0000_0000_0000; // Address for CHR
bytes_left <= {1'b0, chrrom, 13'b0};
end else if (state == 2) begin
done <= 1;
end
end
endcase
end
end
endmodule
module NES_Nexys4(input CLK100MHZ,
input CPU_RESET,
input [4:0] BTN,
input [15:0] SW,
output [15:0] LED,
output [7:0] SSEG_CA,
output [7:0] SSEG_AN,
// UART
input UART_RXD,
output UART_TXD,
// VGA
output vga_v, output vga_h, output [3:0] vga_r, output [3:0] vga_g, output [3:0] vga_b,
// Memory
output MemOE, // Output Enable. Enable when Low.
output MemWR, // Write Enable. WRITE when Low.
output MemAdv, // Address valid. Keep LOW for Async.
input MemWait, // Ignore for Async.
output MemClk, // Clock for sync oper. Keep LOW for Async.
output RamCS, // Chip Enable. Active = LOW
output RamCRE, // CRE = Control Register. LOW = Normal mode.
output RamUB, // Upper byte enable
output RamLB, // Lower byte enable
output [22:0] MemAdr,
inout [15:0] MemDB,
// Sound board
output AUD_MCLK,
output AUD_LRCK,
output AUD_SCK,
output AUD_SDIN
);
wire clock_locked;
wire clk;
clk_wiz_v3_6 clock_21mhz(.CLK_IN1(CLK100MHZ), .CLK_OUT1(clk), .RESET(1'b0), .LOCKED(clock_locked));
// UART
wire [7:0] uart_data;
wire [7:0] uart_addr;
wire uart_write;
wire uart_error;
UartDemux uart_demux(clk, 1'b0, UART_RXD, uart_data, uart_addr, uart_write, uart_error);
assign UART_TXD = 1;
// Loader
wire [7:0] loader_input = uart_data;
wire loader_clk = (uart_addr == 8'h37) && uart_write;
reg [7:0] loader_conf;
reg [7:0] loader_btn, loader_btn_2;
always @(posedge clk) begin
if (uart_addr == 8'h35 && uart_write)
loader_conf <= uart_data;
if (uart_addr == 8'h40 && uart_write)
loader_btn <= uart_data;
if (uart_addr == 8'h41 && uart_write)
loader_btn_2 <= uart_data;
end
// NES Palette -> RGB332 conversion
reg [14:0] pallut[0:63];
initial $readmemh("nes_palette.txt", pallut);
// LED Display
reg [31:0] led_value;
reg [7:0] led_enable;
LedDriver led_driver(clk, led_value, led_enable, SSEG_CA, SSEG_AN);
wire [8:0] cycle;
wire [8:0] scanline;
wire [15:0] sample;
wire [5:0] color;
wire joypad_strobe;
wire [1:0] joypad_clock;
wire [21:0] memory_addr;
wire memory_read_cpu, memory_read_ppu;
wire memory_write;
wire [7:0] memory_din_cpu, memory_din_ppu;
wire [7:0] memory_dout;
reg [7:0] joypad_bits, joypad_bits2;
reg [1:0] last_joypad_clock;
wire [31:0] dbgadr;
wire [1:0] dbgctr;
reg [1:0] nes_ce;
always @(posedge clk) begin
if (joypad_strobe) begin
joypad_bits <= loader_btn;
joypad_bits2 <= loader_btn_2;
end
if (!joypad_clock[0] && last_joypad_clock[0])
joypad_bits <= {1'b0, joypad_bits[7:1]};
if (!joypad_clock[1] && last_joypad_clock[1])
joypad_bits2 <= {1'b0, joypad_bits2[7:1]};
last_joypad_clock <= joypad_clock;
end
wire [21:0] loader_addr;
wire [7:0] loader_write_data;
wire loader_reset = loader_conf[0];
wire loader_write;
wire [31:0] mapper_flags;
wire loader_done, loader_fail;
GameLoader loader(clk, loader_reset, loader_input, loader_clk,
loader_addr, loader_write_data, loader_write,
mapper_flags, loader_done, loader_fail);
wire reset_nes = (BTN[3] || !loader_done);
wire run_mem = (nes_ce == 0) && !reset_nes;
wire run_nes = (nes_ce == 3) && !reset_nes;
// NES is clocked at every 4th cycle.
always @(posedge clk)
nes_ce <= nes_ce + 1;
NES nes(clk, reset_nes, run_nes,
mapper_flags,
sample, color,
joypad_strobe, joypad_clock, {joypad_bits2[0], joypad_bits[0]},
SW[4:0],
memory_addr,
memory_read_cpu, memory_din_cpu,
memory_read_ppu, memory_din_ppu,
memory_write, memory_dout,
cycle, scanline,
dbgadr,
dbgctr);
// This is the memory controller to access the board's PSRAM
wire ram_busy;
MemoryController memory(clk,
memory_read_cpu && run_mem,
memory_read_ppu && run_mem,
memory_write && run_mem || loader_write,
loader_write ? {2'b00, loader_addr} : {2'b00, memory_addr},
loader_write ? loader_write_data : memory_dout,
memory_din_cpu,
memory_din_ppu,
ram_busy,
MemOE, MemWR, MemAdv, MemClk, RamCS, RamCRE, RamUB, RamLB, MemAdr, MemDB);
reg ramfail;
always @(posedge clk) begin
if (loader_reset)
ramfail <= 0;
else
ramfail <= ram_busy && loader_write || ramfail;
end
wire [14:0] doubler_pixel;
wire doubler_sync;
wire [9:0] vga_hcounter, doubler_x;
wire [9:0] vga_vcounter;
VgaDriver vga(clk, vga_h, vga_v, vga_r, vga_g, vga_b, vga_hcounter, vga_vcounter, doubler_x, doubler_pixel, doubler_sync, SW[0]);
wire [14:0] pixel_in = pallut[color];
Hq2x hq2x(clk, pixel_in, SW[5],
scanline[8], // reset_frame
(cycle[8:3] == 42), // reset_line
doubler_x, // 0-511 for line 1, or 512-1023 for line 2.
doubler_sync, // new frame has just started
doubler_pixel); // pixel is outputted
wire [15:0] sound_signal = {sample[15] ^ 1'b1, sample[14:0]};
// wire [15:0] sound_signal_fir;
// wire sample_now_fir;
// FirFilter fir(clk, sound_signal, sound_signal_fir, sample_now_fir);
// Display mapper info on screen
always @(posedge clk) begin
led_enable <= 255;
led_value <= sound_signal;
end
reg [7:0] sound_ctr;
always @(posedge clk)
sound_ctr <= sound_ctr + 1;
wire sound_load = /*SW[6] ? sample_now_fir : */(sound_ctr == 0);
SoundDriver sound_driver(clk,
/*SW[6] ? sound_signal_fir : */sound_signal,
sound_load,
sound_load,
AUD_MCLK, AUD_LRCK, AUD_SCK, AUD_SDIN);
assign LED = {12'b0, uart_error, ramfail, loader_fail, loader_done};
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:38:15 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/system_zed_vga_0_0_stub.v
// Design : system_zed_vga_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "zed_vga,Vivado 2016.4" *)
module system_zed_vga_0_0(rgb565, vga_r, vga_g, vga_b)
/* synthesis syn_black_box black_box_pad_pin="rgb565[15:0],vga_r[3:0],vga_g[3:0],vga_b[3:0]" */;
input [15:0]rgb565;
output [3:0]vga_r;
output [3:0]vga_g;
output [3:0]vga_b;
endmodule
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_receiveActivity (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input in_port;
input reset_n;
wire clk_en;
wire data_in;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
/**
* Module: arbiter
*
* Description:
* A look ahead, round-robing parameterized arbiter.
*
* <> request
* each bit is controlled by an actor and each actor can 'request' ownership
* of the shared resource by bring high its request bit.
*
* <> grant
* when an actor has been given ownership of shared resource its 'grant' bit
* is driven high
*
* <> select
* binary representation of the grant signal (optional use)
*
* <> active
* is brought high by the arbiter when (any) actor has been given ownership
* of shared resource.
*
*
* Created: Sat Jun 1 20:26:44 EDT 2013
*
* Author: Berin Martini // [email protected]
*/
`ifndef _arbiter_ `define _arbiter_
module arbiter
#(parameter
NUM_PORTS = 6,
SEL_WIDTH = ((NUM_PORTS > 1) ? $clog2(NUM_PORTS) : 1))
(input clk,
input rst,
input [NUM_PORTS-1:0] request,
output reg [NUM_PORTS-1:0] grant,
output reg [SEL_WIDTH-1:0] select,
output reg active
);
/**
* Local parameters
*/
localparam WRAP_LENGTH = 2*NUM_PORTS;
// Find First 1 - Start from MSB and count downwards, returns 0 when no
// bit set
function [SEL_WIDTH-1:0] ff1 (
input [NUM_PORTS-1:0] in
);
reg set;
integer i;
begin
set = 1'b0;
ff1 = 'b0;
for (i = 0; i < NUM_PORTS; i = i + 1) begin
if (in[i] & ~set) begin
set = 1'b1;
ff1 = i[0 +: SEL_WIDTH];
end
end
end
endfunction
`ifdef VERBOSE
initial $display("Bus arbiter with %d units", NUM_PORTS);
`endif
/**
* Internal signals
*/
integer yy;
wire next;
wire [NUM_PORTS-1:0] order;
reg [NUM_PORTS-1:0] token;
wire [NUM_PORTS-1:0] token_lookahead [NUM_PORTS-1:0];
wire [WRAP_LENGTH-1:0] token_wrap;
/**
* Implementation
*/
assign token_wrap = {token, token};
assign next = ~|(token & request);
always @(posedge clk)
grant <= token & request;
always @(posedge clk)
select <= ff1(token & request);
always @(posedge clk)
active <= |(token & request);
always @(posedge clk)
if (rst) token <= 'b1;
else if (next) begin
for (yy = 0; yy < NUM_PORTS; yy = yy + 1) begin : TOKEN_
if (order[yy]) begin
token <= token_lookahead[yy];
end
end
end
genvar xx;
generate
for (xx = 0; xx < NUM_PORTS; xx = xx + 1) begin : ORDER_
assign token_lookahead[xx] = token_wrap[xx +: NUM_PORTS];
assign order[xx] = |(token_lookahead[xx] & request);
end
endgenerate
endmodule
`endif // `ifndef _arbiter_
|
`timescale 1 ns / 1 ps
module Eight_Digit_Seven_Segment_Display_v2_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
output wire [6:0] a_to_g,
output wire decimal_point,
output wire [7:0] anode,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
default : begin
slv_reg0 <= slv_reg0;
slv_reg1 <= slv_reg1;
slv_reg2 <= slv_reg2;
slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= slv_reg2;
2'h3 : reg_data_out <= slv_reg3;
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
seven_segment_leds_x_8 ssd(
.bcd_in(slv_reg0[31:0]),
.decimal_points(slv_reg1[7:0]),
.clk(S_AXI_ACLK),
.a_to_g(a_to_g),
.decimal_point(decimal_point),
.anode(anode)
);
// User logic ends
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A22O_FUNCTIONAL_V
`define SKY130_FD_SC_LS__A22O_FUNCTIONAL_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a22o (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A22O_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_SYMBOL_V
`define SKY130_FD_SC_HDLL__OR2_SYMBOL_V
/**
* or2: 2-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or2 (
//# {{data|Data Signals}}
input A,
input B,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_SYMBOL_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
// Date : Wed Mar 02 15:28:43 2016
// Host : Dries007Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// d:/Xilinx/Projects/VGA/VGA.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
// Design : clk_wiz_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v5_2_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_wiz_0
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
(* IBUF_LOW_PWR *) wire clk_in1;
wire clk_out1;
wire locked;
wire reset;
clk_wiz_0_clk_wiz_0_clk_wiz inst
(.clk_in1(clk_in1),
.clk_out1(clk_out1),
.locked(locked),
.reset(reset));
endmodule
(* ORIG_REF_NAME = "clk_wiz_0_clk_wiz" *)
module clk_wiz_0_clk_wiz_0_clk_wiz
(clk_in1,
clk_out1,
reset,
locked);
input clk_in1;
output clk_out1;
input reset;
output locked;
wire clk_in1;
wire clk_in1_clk_wiz_0;
wire clk_out1;
wire clk_out1_clk_wiz_0;
wire clkfbout_buf_clk_wiz_0;
wire clkfbout_clk_wiz_0;
wire locked;
wire reset;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_wiz_0),
.O(clkfbout_buf_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_in1),
.O(clk_in1_clk_wiz_0));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_out1_clk_wiz_0),
.O(clk_out1));
(* BOX_TYPE = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.125000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(9.375000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(1),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.010000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_wiz_0),
.CLKFBOUT(clkfbout_clk_wiz_0),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_in1_clk_wiz_0),
.CLKIN2(1'b0),
.CLKINSEL(1'b1),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_out1_clk_wiz_0),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DCLK(1'b0),
.DEN(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(1'b0),
.LOCKED(locked),
.PSCLK(1'b0),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(1'b0),
.RST(reset));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Interface ////
//// This is the external bus interface, that is WISHBONE ////
//// SoC compliant. ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_wb.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_wb.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.4 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.3 2001/09/24 01:15:28 rudi
//
// Changed reset to be active high async.
//
// Revision 1.2 2001/08/10 08:48:33 rudi
//
// - Changed IO names to be more clear.
// - Uniquifyed define names to be core specific.
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.2 2001/03/31 13:00:52 rudi
//
// - Added Core configuration
// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
// - Modified WISHBONE interface and sync logic
// - Moved SSRAM outside the core (added interface)
// - Many small bug fixes ...
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.1.0.1 2001/02/28 08:11:47 rudi
// Initial Release
//
//
`include "usbf_defines.v"
module usbf_wb( // WISHBONE Interface
wb_clk, phy_clk, rst, wb_addr_i, wb_data_i, wb_data_o,
wb_ack_o, wb_we_i, wb_stb_i, wb_cyc_i,
// Memory Arbiter Interface
ma_adr, ma_dout, ma_din, ma_we, ma_req, ma_ack,
// Register File interface
rf_re, rf_we, rf_din, rf_dout);
input wb_clk, phy_clk;
input rst;
input [`USBF_UFC_HADR:0] wb_addr_i;
input [31:0] wb_data_i;
output [31:0] wb_data_o;
output wb_ack_o;
input wb_we_i;
input wb_stb_i;
input wb_cyc_i;
// Memory Arbiter Interface
output [`USBF_UFC_HADR:0] ma_adr;
output [31:0] ma_dout;
input [31:0] ma_din;
output ma_we;
output ma_req;
input ma_ack;
// Register File interface
output rf_re;
output rf_we;
input [31:0] rf_din;
output [31:0] rf_dout;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
parameter [5:0] // synopsys enum state
IDLE = 6'b00_0001,
MA_WR = 6'b00_0010,
MA_RD = 6'b00_0100,
W0 = 6'b00_1000,
W1 = 6'b01_0000,
W2 = 6'b10_0000;
reg [5:0] state, next_state;
reg wb_req_s1;
reg wb_ack_d, wb_ack_s1, wb_ack_s1a, wb_ack_s2;
reg ma_we;
reg rf_re, rf_we_d;
reg ma_req;
reg wb_ack_o;
reg [31:0] wb_data_o;
///////////////////////////////////////////////////////////////////
//
// Interface Logic
//
assign ma_adr = wb_addr_i;
assign ma_dout = wb_data_i;
assign rf_dout = wb_data_i;
always @(posedge wb_clk)
if( `USBF_RF_SEL ) wb_data_o <= rf_din;
else wb_data_o <= ma_din;
// Sync WISHBONE Request
always @(posedge phy_clk)
wb_req_s1 <= wb_stb_i & wb_cyc_i;
// Sync WISHBONE Ack
always @(posedge wb_clk)
wb_ack_s1 <= wb_ack_d;
always @(posedge wb_clk)
wb_ack_o <= wb_ack_s1 & !wb_ack_s2 & !wb_ack_o;
always @(posedge wb_clk)
wb_ack_s1a <= wb_ack_s1;
always @(posedge wb_clk)
wb_ack_s2 <= wb_ack_s1a;
assign rf_we = rf_we_d;
///////////////////////////////////////////////////////////////////
//
// Interface State Machine
//
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) state <= IDLE;
//to the prefered high reset
if(rst) state <= IDLE;
else state <= next_state;
always @(state or wb_req_s1 or wb_addr_i or ma_ack or wb_we_i)
begin
next_state = state;
ma_req = 1'b0;
ma_we = 1'b0;
wb_ack_d = 1'b0;
rf_re = 1'b0;
rf_we_d = 1'b0;
case(state) // synopsys parallel_case
IDLE:
begin
if(wb_req_s1 && `USBF_MEM_SEL && wb_we_i)
begin
ma_req = 1'b1;
ma_we = 1'b1;
next_state = MA_WR;
end
if(wb_req_s1 && `USBF_MEM_SEL && !wb_we_i)
begin
ma_req = 1'b1;
next_state = MA_RD;
end
if(wb_req_s1 && `USBF_RF_SEL && wb_we_i)
begin
rf_we_d = 1'b1;
next_state = W0;
end
if(wb_req_s1 && `USBF_RF_SEL && !wb_we_i)
begin
rf_re = 1'b1;
next_state = W0;
end
end
MA_WR:
begin
if(!ma_ack)
begin
ma_req = 1'b1;
ma_we = 1'b1;
end
else
begin
wb_ack_d = 1'b1;
next_state = W1;
end
end
MA_RD:
begin
if(!ma_ack)
begin
ma_req = 1'b1;
end
else
begin
wb_ack_d = 1'b1;
next_state = W1;
end
end
W0:
begin
wb_ack_d = 1'b1;
next_state = W1;
end
W1:
begin
next_state = W2;
end
W2:
begin
next_state = IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
`define SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o211a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O211A_PP_SYMBOL_V
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module system_processing_system7_0_0 (
SDIO0_WP,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_5_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(0),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(125.0),
.C_FCLK_CLK1_FREQ(50.0),
.C_FCLK_CLK2_FREQ(50.0),
.C_FCLK_CLK3_FREQ(50.0),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(),
.S_AXI_HP0_AWREADY(),
.S_AXI_HP0_BVALID(),
.S_AXI_HP0_RLAST(),
.S_AXI_HP0_RVALID(),
.S_AXI_HP0_WREADY(),
.S_AXI_HP0_BRESP(),
.S_AXI_HP0_RRESP(),
.S_AXI_HP0_BID(),
.S_AXI_HP0_RID(),
.S_AXI_HP0_RDATA(),
.S_AXI_HP0_ACLK(1'B0),
.S_AXI_HP0_ARVALID(1'B0),
.S_AXI_HP0_AWVALID(1'B0),
.S_AXI_HP0_BREADY(1'B0),
.S_AXI_HP0_RREADY(1'B0),
.S_AXI_HP0_WLAST(1'B0),
.S_AXI_HP0_WVALID(1'B0),
.S_AXI_HP0_ARBURST(2'B0),
.S_AXI_HP0_ARLOCK(2'B0),
.S_AXI_HP0_ARSIZE(3'B0),
.S_AXI_HP0_AWBURST(2'B0),
.S_AXI_HP0_AWLOCK(2'B0),
.S_AXI_HP0_AWSIZE(3'B0),
.S_AXI_HP0_ARPROT(3'B0),
.S_AXI_HP0_AWPROT(3'B0),
.S_AXI_HP0_ARADDR(32'B0),
.S_AXI_HP0_AWADDR(32'B0),
.S_AXI_HP0_ARCACHE(4'B0),
.S_AXI_HP0_ARLEN(4'B0),
.S_AXI_HP0_ARQOS(4'B0),
.S_AXI_HP0_AWCACHE(4'B0),
.S_AXI_HP0_AWLEN(4'B0),
.S_AXI_HP0_AWQOS(4'B0),
.S_AXI_HP0_ARID(6'B0),
.S_AXI_HP0_AWID(6'B0),
.S_AXI_HP0_WID(6'B0),
.S_AXI_HP0_WDATA(64'B0),
.S_AXI_HP0_WSTRB(8'B0),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(),
.FCLK_CLK2(),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__MUX2_1_V
`define SKY130_FD_SC_HS__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
sky130_fd_sc_hs__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__MUX2_1_V
|
// synthesis VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
//
// This file is part of multiexp-a5gx.
//
// multiexp-a5gx is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
module dram_control
#( parameter n_words = 40
, parameter w_width = 27
// vvvvvv THESE SHOULD BE LOCALPARAMS. DO NOT EDIT OR OVERRIDE vvvvvv //
, parameter wbits = $clog2(n_words)
)
( input clk
, input pcie_perstn
, input pcie_ready
, input user_resetn
, output ctrl_reset_n
, input [6:0] command
, output [13:0] g_mem_addr
, output g_mem_wren
, output g_mem_rden
, output [w_width-1:0] g_mem_datai
, input [w_width-1:0] g_mem_datao
, input [25-wbits:0] addr_direct
// memory interface i/o (pin directly from toplevel)
, output [12:0] ddr3_a // memory.mem_a
, output [2:0] ddr3_ba // .mem_ba
, output ddr3_ck_p // .mem_ck
, output ddr3_ck_n // .mem_ck_n
, output ddr3_cke // .mem_cke
, output ddr3_csn // .mem_cs_n
, output [3:0] ddr3_dm // .mem_dm
, output ddr3_rasn // .mem_ras_n
, output ddr3_casn // .mem_cas_n
, output ddr3_wen // .mem_we_n
, output ddr3_rstn // .mem_reset_n
, inout [31:0] ddr3_dq // .mem_dq
, inout [3:0] ddr3_dqs_p // .mem_dqs
, inout [3:0] ddr3_dqs_n // .mem_dqs_n
, output ddr3_odt // .mem_odt
, input ddr3_oct_rzq // oct.rzqin
, input clkin_100_p
, output idle
);
localparam fifodepth = 1 << wbits;
wire mem_ready, mrdata_valid, pll_locked, cal_success, mpfe_reset_n, global_reset_n, init_done, mrden, mwren;
wire [31:0] mrdata, mwdata;
reg [w_width-1:0] gdata_reg, gdata_next;
assign mwdata[31:w_width] = '0;
assign g_mem_datai = gdata_reg;
reg [1:0] state_reg, state_next;
localparam ST_IDLE = 2'b00;
localparam ST_ADDR = 2'b01;
localparam ST_READ = 2'b10;
localparam ST_WRITE = 2'b11;
wire inST_IDLE = state_reg == ST_IDLE;
wire inST_ADDR = state_reg == ST_ADDR; // get addr from g_mem
wire inST_READ = state_reg == ST_READ; // read from g_mem into RAM
wire inST_WRITE = state_reg == ST_WRITE; // write from RAM into g_mem
reg [wbits-1:0] count_reg, count_next;
wire last_count = count_reg == (n_words - 1);
wire count_is_3 = count_reg == {{(wbits-2){1'b0}},2'b11};
localparam SEG_ADDR = 2'b11;
localparam SEG_PRELOAD = 2'b00;
localparam SEG_STORE = 2'b10;
reg [1:0] saddr_reg, saddr_next;
reg [5:0] command_reg, command_next;
assign g_mem_addr = {command_reg[4:0],{(7-wbits){1'b0}},saddr_reg,count_reg};
reg grden_reg, grden_next, gwren_reg, gwren_next;
assign g_mem_wren = gwren_reg;
assign g_mem_rden = grden_reg;
wire empty;
assign mwren = inST_READ;
wire rdreq = (inST_READ & mem_ready) | (inST_ADDR & count_is_3);
reg wrreq_reg, wrreq_next;
reg mrden_reg, mrden_next;
reg begin_reg, begin_next;
reg [25-wbits:0] maddr_reg, maddr_next;
wire [25:0] maddr = {maddr_reg,{(wbits){1'b0}}};
assign idle = inST_IDLE;
// illegal unit address (28) indicates we should read address directly from dispatch
wire do_direct_write = &command[6:2];
always_comb begin
command_next = command_reg;
state_next = state_reg;
count_next = count_reg;
saddr_next = saddr_reg;
grden_next = grden_reg;
gwren_next = '0;
gdata_next = gdata_reg;
mrden_next = mrden_reg;
begin_next = '0;
maddr_next = maddr_reg;
wrreq_next = wrreq_reg;
case (state_reg)
ST_IDLE: begin
if (do_direct_write) begin
command_next = {6'b111100};
maddr_next = addr_direct;
state_next = ST_WRITE;
count_next = '0;
mrden_next = '1;
begin_next = '1;
end else if (command[6]) begin
state_next = ST_ADDR;
command_next = command[5:0];
grden_next = '1;
// address 0 if writing (to preload area), address 1 if reading (from store area)
count_next = {{(wbits-1){1'b0}},~command[5]};
// 11 segment stores addresses
saddr_next = SEG_ADDR;
end else if (command[5]) begin
// going into ST_WRITE with command_reg[5] == 0 enables "clear" action
command_next = {1'b0,command[4:0]};
count_next = '0;
saddr_next = SEG_PRELOAD;
state_next = ST_WRITE;
end
end
/** READING ** gmem -> dram (~command_reg[5])
state saddr_reg saddr_next grden_reg grden_next count_reg count_next wrreq_reg wrreq_next g_mem_datao
IDLE 00 11 0 1 0 1 X 0 X
ADDR 11 10 1 " 1 0 0 " X
ADDR 10 " " " 0 1 " 1 maddr_next
ADDR " " " " 1 2 1 " data[0] -> fifo
ADDR " " " " 2 3 " " data[1] -> fifo (fifo pre-read)
READ " " " " 3 4 " data[2] -> fifo
READ " " " " 4.. 5.. data[3..] -> fifo
READ " 0 " 0 n_words-1 0 data[n_words-2] -> fifo
READ 0 0 0 0 0 " data[n_words-1] -> fifo
transition back to ST_IDLE once gfifo_empty;
*** WRITING ** dram -> gmem (command_reg[5])
state saddr_reg saddr_next grden_reg grden_next count_reg count_next g_mem_datao
IDLE 00 11 0 1 0 0 X
ADDR 11 00 1 0 " " X
ADDR 00 " 0 " " 0 maddr_next
WRITE " " " " 0 " X
wait for mem_ready -> turn off mrden
when mrdata_valid, indicate wren and save data to registers
when wren is active, a write is happening; increment counter. If we're on the last count, done.
*/
ST_ADDR: begin
if (saddr_reg == SEG_ADDR) begin
count_next = '0;
if (~command_reg[5]) begin
// segment 2 if reading from STORE area
saddr_next = SEG_STORE;
end else begin
// segment 1 if writing to PRELOAD area
saddr_next = SEG_PRELOAD;
grden_next = '0;
end
end else if (~wrreq_reg) begin
maddr_next = g_mem_datao[25-wbits:0];
if (~command_reg[5]) begin
wrreq_next = '1;
count_next = count_reg + 1'b1;
end else begin
state_next = ST_WRITE;
count_next = '0;
mrden_next = '1;
begin_next = '1;
end
end else begin
count_next = count_reg + 1'b1;
if (count_is_3) begin
state_next = ST_READ;
begin_next = '1;
end
end
end
// FROM gmem TO dram
ST_READ: begin
if (grden_reg) begin
if (last_count) begin
grden_next = '0;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end else begin
wrreq_next = '0;
if (mem_ready & empty) begin
state_next = ST_IDLE;
end
end
end
// FROM dram TO gmem
ST_WRITE: begin
if (command_reg[5]) begin
if (mrden_reg) begin
if (mem_ready) begin
mrden_next = 1'b0;
end
end else begin
// this is relying on the DRAM controller to deassert
// data_valid after the transfer is finished. This
// seems to be true in practice.
if (mrdata_valid) begin
gdata_next = mrdata[w_width-1:0];
gwren_next = '1;
end
if (gwren_reg) begin
if (last_count) begin
state_next = ST_IDLE;
count_next = '0;
end else begin
count_next = count_reg + 1'b1;
end
end
end
end else begin
// set the PRELOAD register to {'0,1'b1};
if (gwren_reg) begin
if (last_count) begin
state_next = ST_IDLE;
count_next = '0;
end else begin
gdata_next = '0;
gwren_next = '1;
count_next = count_reg + 1'b1;
end
end else begin
gdata_next = {{(w_width-1){1'b0}},1'b1};
gwren_next = '1;
count_next = '0;
end
end
end
endcase
end
always_ff @(posedge clk or negedge ctrl_reset_n) begin
if (~ctrl_reset_n) begin
command_reg <= '0;
state_reg <= '0;
count_reg <= '0;
saddr_reg <= '0;
grden_reg <= '0;
gwren_reg <= '0;
gdata_reg <= '0;
mrden_reg <= '0;
begin_reg <= '0;
maddr_reg <= '0;
wrreq_reg <= '0;
end else begin
command_reg <= command_next;
state_reg <= state_next;
count_reg <= count_next;
saddr_reg <= saddr_next;
grden_reg <= grden_next;
gwren_reg <= gwren_next;
gdata_reg <= gdata_next;
mrden_reg <= mrden_next;
begin_reg <= begin_next;
maddr_reg <= maddr_next;
wrreq_reg <= wrreq_next;
end
end
scfifo #( .add_ram_output_register ("ON")
, .intended_device_family ("Arria V")
, .lpm_numwords (fifodepth)
, .lpm_showahead ("OFF")
, .lpm_type ("scfifo")
, .lpm_width (w_width)
, .lpm_widthu (wbits)
, .overflow_checking ("ON")
, .underflow_checking ("ON")
, .use_eab ("ON")
) gfifo
( .clock (clk)
, .aclr (~ctrl_reset_n)
, .sclr (inST_IDLE)
, .q (mwdata[w_width-1:0])
, .rdreq (rdreq)
, .empty (empty)
, .data (g_mem_datao)
, .wrreq (wrreq_reg)
, .full ()
, .usedw ()
, .almost_full ()
, .almost_empty ()
);
mpfe_rst rstins ( .bus_clk (clk)
, .pll_locked (pll_locked)
, .cal_success (cal_success)
, .init_done (init_done)
, .pcie_perstn (pcie_perstn)
, .pcie_ready (pcie_ready)
, .cpu_resetn (user_resetn)
, .global_reset_n (global_reset_n)
, .mpfe_reset_n (mpfe_reset_n)
, .ctrl_reset_n (ctrl_reset_n)
);
ddr3_x32 ddrins ( .pll_ref_clk (clkin_100_p)
, .global_reset_n (global_reset_n)
, .soft_reset_n (pll_locked)
, .mem_a (ddr3_a)
, .mem_ba (ddr3_ba)
, .mem_ck (ddr3_ck_p)
, .mem_ck_n (ddr3_ck_n)
, .mem_cke (ddr3_cke)
, .mem_cs_n (ddr3_csn)
, .mem_dm (ddr3_dm)
, .mem_ras_n (ddr3_rasn)
, .mem_cas_n (ddr3_casn)
, .mem_we_n (ddr3_wen)
, .mem_reset_n (ddr3_rstn)
, .mem_dq (ddr3_dq)
, .mem_dqs (ddr3_dqs_p)
, .mem_dqs_n (ddr3_dqs_n)
, .mem_odt (ddr3_odt)
, .oct_rzqin (ddr3_oct_rzq)
, .avl_ready_0 (mem_ready)
, .avl_burstbegin_0 (begin_reg)
, .avl_addr_0 (maddr)
, .avl_rdata_valid_0 (mrdata_valid)
, .avl_rdata_0 (mrdata)
, .avl_wdata_0 (mwdata)
, .avl_read_req_0 (mrden_reg)
, .avl_write_req_0 (mwren)
, .avl_size_0 (n_words)
, .avl_be_0 (4'b1111)
, .mp_cmd_clk_0_clk (clk)
, .mp_cmd_reset_n_0_reset_n (mpfe_reset_n)
, .mp_rfifo_clk_0_clk (clk)
, .mp_rfifo_reset_n_0_reset_n (mpfe_reset_n)
, .mp_wfifo_clk_0_clk (clk)
, .mp_wfifo_reset_n_0_reset_n (mpfe_reset_n)
, .afi_clk ()
, .afi_half_clk ()
, .afi_phy_clk ()
, .afi_reset_n ()
, .afi_reset_export_n ()
, .local_init_done (init_done)
, .local_cal_success (cal_success)
, .local_cal_fail ()
, .pll_mem_clk ()
, .pll_write_clk ()
, .pll_locked (pll_locked)
, .pll_write_clk_pre_phy_clk ()
, .pll_addr_cmd_clk ()
, .pll_avl_clk ()
, .pll_config_clk ()
, .pll_mem_phy_clk ()
, .pll_avl_phy_clk ()
);
endmodule
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